26 Aug, 2013
3 commits
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We need to use more of the Macros in asm.h to allow kvm_locore.S to
build in a 64-bit kernel.For 32-bit there is no change in the generated object code.
Signed-off-by: David Daney
Acked-by: Ralf Baechle
Acked-by: Paolo Bonzini
Signed-off-by: Gleb Natapov -
There are:
.set push
.set noreorder
.set noat
.
.
.
.set popSequences all over the place in this file, but in some places the
final ".set pop" is erroneously converted to ".set push", so none of
these really do what they appear to.Clean up the whole mess by moving ".set noreorder", ".set noat" to the
top, and get rid of everything else.Generated object code is unchanged.
Signed-off-by: David Daney
Acked-by: Paolo Bonzini
Signed-off-by: Gleb Natapov -
No code changes, just reflowing some comments and consistently using
tabs and spaces. Object code is verified to be unchanged.Signed-off-by: David Daney
Acked-by: Ralf Baechle
Acked-by: Paolo Bonzini
Reviewed-by: James Hogan
Signed-off-by: Gleb Natapov
18 Jul, 2013
1 commit
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This is called right after the memslots is updated, i.e. when the result
of update_memslots() gets installed in install_new_memslots(). Since
the memslots needs to be updated twice when we delete or move a memslot,
kvm_arch_commit_memory_region() does not correspond to this exactly.In the following patch, x86 will use this new API to check if the mmio
generation has reached its maximum value, in which case mmio sptes need
to be flushed out.Signed-off-by: Takuya Yoshikawa
Acked-by: Alexander Graf
Reviewed-by: Xiao Guangrong
Signed-off-by: Paolo Bonzini
11 Jun, 2013
1 commit
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The API requires that the GET_ONE_REG and SET_ONE_REG ioctls have this
extra information encoded in the register identifiers.Signed-off-by: David Daney
Signed-off-by: Gleb Natapov
03 Jun, 2013
4 commits
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The Linux Way is to return -ENOIOCTLCMD to the vfs when an
unimplemented ioctl is requested. Do this in kvm_mips instead of a
random mixture of -ENOTSUPP and -EINVAL.Signed-off-by: David Daney
Acked-by: Sanjay Lal
Signed-off-by: Paolo Bonzini -
Because not all 256 CP0 registers are ever implemented, we need a
different method of manipulating them. Use the
KVM_SET_ONE_REG/KVM_GET_ONE_REG mechanism.Now unused code and definitions are removed.
Signed-off-by: David Daney
Acked-by: Sanjay Lal
Signed-off-by: Paolo Bonzini -
Also we cannot set special zero register, so force it to zero.
Signed-off-by: David Daney
Acked-by: Sanjay Lal
Signed-off-by: Paolo Bonzini -
Signed-off-by: David Daney
Acked-by: Sanjay Lal
Signed-off-by: Paolo Bonzini
24 May, 2013
1 commit
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Pull kvm bugfixes from Gleb Natapov.
* git://git.kernel.org/pub/scm/virt/kvm/kvm:
KVM/MIPS32: Wrap calls to gfn_to_pfn() with srcu_read_lock/unlock()
KVM/MIPS32: Move include/asm/kvm.h => include/uapi/asm/kvm.h since it is a user visible API.
KVM: take over co-maintainership from Marcelo, fix MAINTAINERS entry
22 May, 2013
1 commit
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- As suggested by Gleb, wrap calls to gfn_to_pfn() with srcu_read_lock/unlock().
Memory slots should be acccessed from a SRCU read section.
- kvm_mips_map_page() now returns an error code to it's callers, instead of
calling panic() if it cannot find a mapping for a particular gfn.Signed-off-by: Sanjay Lal
Signed-off-by: Gleb Natapov
17 May, 2013
1 commit
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This reverts commit d532f3d26716a39dfd4b88d687bd344fbe77e390.
The original commit has several problems:
1) Doesn't work with 64-bit kernels.
2) Calls TLBMISS_HANDLER_SETUP() before the code is generated.
3) Calls TLBMISS_HANDLER_SETUP() twice in per_cpu_trap_init() when
only one call is needed.[ralf@linux-mips.org: Also revert the bits of the ASID patch which were
hidden in the KVM merge.]Signed-off-by: David Daney
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: "Steven J. Hill"
Cc: David Daney
Patchwork: https://patchwork.linux-mips.org/patch/5242/
Signed-off-by: Ralf Baechle
10 May, 2013
1 commit
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Pull MIPS updates from Ralf Baechle:
- More work on DT support for various platforms
- Various fixes that were to late to make it straight into 3.9
- Improved platform support, in particular the Netlogic XLR and
BCM63xx, and the SEAD3 and Malta eval boards.- Support for several Ralink SOC families.
- Complete support for the microMIPS ASE which basically reencodes the
existing MIPS32/MIPS64 ISA to use non-constant size instructions.- Some fallout from LTO work which remove old cruft and will generally
make the MIPS kernel easier to maintain and resistant to compiler
optimization, even in absence of LTO.- KVM support. While MIPS has announced hardware virtualization
extensions this KVM extension uses trap and emulate mode for
virtualization of MIPS32. More KVM work to add support for VZ
hardware virtualizaiton extensions and MIPS64 will probably already
be merged for 3.11.Most of this has been sitting in -next for a long time. All defconfigs
have been build or run time tested except three for which fixes are being
sent by other maintainers.Semantic conflict with kvm updates done as per Ralf
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (118 commits)
MIPS: Add new GIC clockevent driver.
MIPS: Formatting clean-ups for clocksources.
MIPS: Refactor GIC clocksource code.
MIPS: Move 'gic_frequency' to common location.
MIPS: Move 'gic_present' to common location.
MIPS: MIPS16e: Add unaligned access support.
MIPS: MIPS16e: Support handling of delay slots.
MIPS: MIPS16e: Add instruction formats.
MIPS: microMIPS: Optimise 'strnlen' core library function.
MIPS: microMIPS: Optimise 'strlen' core library function.
MIPS: microMIPS: Optimise 'strncpy' core library function.
MIPS: microMIPS: Optimise 'memset' core library function.
MIPS: microMIPS: Add configuration option for microMIPS kernel.
MIPS: microMIPS: Disable LL/SC and fix linker bug.
MIPS: microMIPS: Add vdso support.
MIPS: microMIPS: Add unaligned access support.
MIPS: microMIPS: Support handling of delay slots.
MIPS: microMIPS: Add support for exception handling.
MIPS: microMIPS: Floating point support.
MIPS: microMIPS: Fix macro naming in micro-assembler.
...
09 May, 2013
2 commits
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…into mips-for-linux-next
-
Currently, the following instructions are translated:
- CACHE (indexed)
- CACHE (va based): translated to a SYNCI, overkill on D-CACHE operations,
but still much faster than a trap.
- mfc0/mtc0: the virtual COP0 registers for the guest are implemented as
2-D array.
[COP#][SEL] and this is mapped into the guest kernel address space @ VA 0x0.
mfc0/mtc0 operations are transformed to load/stores.Signed-off-by: Sanjay Lal
Cc: kvm@vger.kernel.org
Cc: linux-mips@linux-mips.org
Signed-off-by: Ralf Baechle
08 May, 2013
9 commits
-
Signed-off-by: Sanjay Lal
Cc: kvm@vger.kernel.org
Cc: linux-mips@linux-mips.org
Signed-off-by: Ralf Baechle -
Signed-off-by: Sanjay Lal
Cc: kvm@vger.kernel.org
Cc: linux-mips@linux-mips.org
Signed-off-by: Ralf Baechle -
Signed-off-by: Sanjay Lal
Cc: kvm@vger.kernel.org
Cc: linux-mips@linux-mips.org
Signed-off-by: Ralf Baechle -
Signed-off-by: Sanjay Lal
Cc: kvm@vger.kernel.org
Cc: linux-mips@linux-mips.org
Signed-off-by: Ralf Baechle -
- Note that this file is statically linked with the rest of the host kernel (KSEG0). This is because kernel modules are
loaded into mapped space on MIPS and we want to make sure that we don't get any host kernel TLB faults while
manipulating TLBs.
- Virtual Guest TLBs are implemented as 64 entry array regardless of the number of host TLB entries.
- Shadow TLBs map Guest virtual addresses to Host physical addresses.- TLB miss handling details:
Guest KSEG0 TLBMISS (0x40000000 – 0x60000000): Transparent to the Guest.
Guest KSEG2/3 (0x60000000 – 0x80000000) & Guest UM TLBMISS (0x00000000 – 0x40000000)
Lookup in Guest/Virtual TLB
If an entry doesn’t match
deliver appropriate TLBMISS LD/ST exception to the guest
If entry does exist in the Guest TLB and is NOT Valid
Deliver TLB invalid exception to the guest
If entry does exist in the Guest TLB and is VALID
Inject the TLB entry into the Shadow TLBSigned-off-by: Sanjay Lal
Cc: kvm@vger.kernel.org
Cc: linux-mips@linux-mips.org
Signed-off-by: Ralf Baechle -
- The Guest kernel is run in UM and privileged instructions cause a trap.
- If the instruction causing the trap is in a branch delay slot, the branch
needs to be emulated to figure out the PC @ which the guest will resume
execution.Signed-off-by: Sanjay Lal
Cc: kvm@vger.kernel.org
Cc: linux-mips@linux-mips.org
Signed-off-by: Ralf Baechle -
- Implements the arch specific APIs for KVM, some are stubs for MIPS
- kvm_mips_handle_exit(): Main 'C' distpatch routine for handling exceptions while in "Guest" mode.
- Also implements in-kernel timer interrupt support for the guest.Signed-off-by: Sanjay Lal
Cc: kvm@vger.kernel.org
Cc: linux-mips@linux-mips.org
Signed-off-by: Ralf Baechle -
- __kvm_mips_vcpu_run: main entry point to enter guest, we save kernel context, load
up guest context from and ERET to guest context.
- mips32_exception: L1 exception handler(s), save k0/k1 and jump to main handlers.
- mips32_GuestException: Generic exception handlers for exceptions/interrupts while in
guest context. Save guest context, restore some kernel context and jump to
main 'C' handler: kvm_mips_handle_exit()Signed-off-by: Sanjay Lal
Cc: kvm@vger.kernel.org
Cc: linux-mips@linux-mips.org
Signed-off-by: Ralf Baechle -
- Add the KVM option to MIPS build files.
- Add default config files for KVM host/guest kernels.
- Change the link address for the Malta KVM Guest kernel to UM (0x40100000).
- Add KVM Kconfig file with KVM/MIPS specific optionsSigned-off-by: Sanjay Lal
Cc: kvm@vger.kernel.org
Cc: linux-mips@linux-mips.org
Signed-off-by: Ralf Baechle