Doug / smarc-fsl-linux-kernel

23 Jan, 2013

1 commit

  • 757be67f5   MIPS: Octeon: Fix warning. ... Browse Code »

    Cong Ding reports correctly that the variable dummy
    is being used without initialization. That said, I can't reproduce this
    warning with GCC 4.7.1. However, since the variable dummy servces no
    real purpose, I'm going for a different fix. This fix
    includes https://patchwork.linux-mips.org/patch/4801/ plus Geert's
    suggestion to use ACCESS_ONCE().

    Signed-off-by: Ralf Baechle

    Ralf Baechle
     

09 Nov, 2012

1 commit

  • 92d11594f   MIPS: Remove irqflags.h dependency from bitops.h ... Browse Code »

    The "else clause" of most functions in bitops.h invoked
    raw_local_irq_{save,restore}() and in doing so had a dependency on
    irqflags.h. This fix moves said code to bitops.c, removing the
    dependency.

    Signed-off-by: Jim Quinlan
    Cc: linux-mips@linux-mips.org
    Cc: David Daney
    Cc: Kevin Cernekee cernekee@gmail.com
    Cc: Jim Quinlan
    Patchwork: https://patchwork.linux-mips.org/patch/4320/
    Signed-off-by: Ralf Baechle

    Jim Quinlan
     

30 Oct, 2010

1 commit

  • b8db85b5b   MIPS: Octeon: Update L2 Cache code for CN63XX ... Browse Code »

    The CN63XX has a different L2 cache architecture. Update the helper
    functions to reflect this.

    Some joining of split lines was also done to improve readability, as
    well as reformatting of comments.

    Signed-off-by: David Daney
    Patchwork: http://patchwork.linux-mips.org/patch/1663/
    Signed-off-by: Ralf Baechle

    David Daney
     

11 Jan, 2009

1 commit

  • 58f07778c   MIPS: Add Cavium OCTEON processor support files to arch/mips/cavium-octeon/executive and asm/octeon. ... Browse Code »

    These files are used to coordinate resource sharing between all of
    the programs running on the OCTEON SOC. The OCTEON processor has many
    CPU cores (current parts have up to 16, but more are possible). It
    also has a variety of on-chip hardware blocks for things like network
    acceleration, encryption and RAID.

    One typical configuration is to run Linux on several of the CPU cores,
    and other dedicated applications on the other cores.

    Resource allocation between the various programs running on the system
    (Linux kernel and other dedicated applications) needs to be
    coordinated. The code we use to do this we call the 'executive'. All
    of this resource allocation and sharing code is gathered together in
    the executive directory.

    Included in the patch set are the following files:

    cvmx-bootmem.c and cvmx-sysinfo.c -- Coordinate memory allocation.
    All memory used by the Linux kernel is obtained here at boot time.

    cvmx-l2c.c -- Coordinates operations on the shared level 2 cache.

    octeon-model.c -- Probes chip capabilities and version.

    The corresponding headers are in asm/octeon.

    Signed-off-by: Tomaso Paoletti
    Signed-off-by: David Daney
    Signed-off-by: Ralf Baechle

    create mode 100644 arch/mips/cavium-octeon/executive/Makefile
    create mode 100644 arch/mips/cavium-octeon/executive/cvmx-bootmem.c
    create mode 100644 arch/mips/cavium-octeon/executive/cvmx-l2c.c
    create mode 100644 arch/mips/cavium-octeon/executive/cvmx-sysinfo.c
    create mode 100644 arch/mips/cavium-octeon/executive/octeon-model.c
    create mode 100644 arch/mips/include/asm/octeon/cvmx-asm.h
    create mode 100644 arch/mips/include/asm/octeon/cvmx-bootinfo.h
    create mode 100644 arch/mips/include/asm/octeon/cvmx-bootmem.h
    create mode 100644 arch/mips/include/asm/octeon/cvmx-l2c.h
    create mode 100644 arch/mips/include/asm/octeon/cvmx-packet.h
    create mode 100644 arch/mips/include/asm/octeon/cvmx-spinlock.h
    create mode 100644 arch/mips/include/asm/octeon/cvmx-sysinfo.h
    create mode 100644 arch/mips/include/asm/octeon/cvmx.h
    create mode 100644 arch/mips/include/asm/octeon/octeon-feature.h
    create mode 100644 arch/mips/include/asm/octeon/octeon-model.h

    David Daney