04 Jul, 2013
1 commit
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Pull clock framework updates from Mike Turquette:
"The common clock framework changes for 3.11 include new clock drivers
across several different platforms and architectures, fixes to
existing drivers, a MAINTAINERS file fix and improvements to the basic
clock types that allow them to be of use to more platforms than before.Only a few fixes to the core framework are included with most all of
the changes landing in the various clock drivers themselves."* tag 'clk-for-linus-3.11' of git://git.linaro.org/people/mturquette/linux: (55 commits)
clk: tegra: fix ifdef for tegra_periph_reset_assert inline
clk: tegra: provide tegra_periph_reset_assert alternative
clk: exynos4: Fix clock aliases for cpufreq related clocks
clk: samsung: Add MUX_FA macro to pass flag and alias
clk: add support for Rockchip gate clocks
clk: vexpress: Make the clock drivers directly available for arm64
clk: vexpress: Use full node name to identify individual clocks
clk: tegra: T114: add DFLL DVCO reset control
clk: tegra: T114: add DFLL source clocks
clk: tegra: T114: add FCPU clock shaper programming, needed by the DFLL
clk: gate: add CLK_GATE_HIWORD_MASK
clk: divider: add CLK_DIVIDER_HIWORD_MASK flag
clk: mux: add CLK_MUX_HIWORD_MASK
clk: Always notify whole subtree when reparenting
MAINTAINERS: make drivers/clk entry match subdirs
clk: honor CLK_GET_RATE_NOCACHE in clk_set_rate
clk: use clk_get_rate() for debugfs
clk: tegra: Use override bits when needed
clk: tegra: override bits for Tegra30 PLLM
clk: tegra: override bits for Tegra114 PLLM
...
03 Jul, 2013
1 commit
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Pull ARM SoC specific changes from Arnd Bergmann:
"These changes are all to SoC-specific code, a total of 33 branches on
17 platforms were pulled into this. Like last time, Renesas sh-mobile
is now the platform with the most changes, followed by OMAP and
EXYNOS.Two new platforms, TI Keystone and Rockchips RK3xxx are added in this
branch, both containing almost no platform specific code at all, since
they are using generic subsystem interfaces for clocks, pinctrl,
interrupts etc. The device drivers are getting merged through the
respective subsystem maintainer trees.One more SoC (u300) is now multiplatform capable and several others
(shmobile, exynos, msm, integrator, kirkwood, clps711x) are moving
towards that goal with this series but need more work.Also noteworthy is the work on PCI here, which is traditionally part
of the SoC specific code. With the changes done by Thomas Petazzoni,
we can now more easily have PCI host controller drivers as loadable
modules and keep them separate from the platform code in
drivers/pci/host. This has already led to the discovery that three
platforms (exynos, spear and imx) are actually using an identical PCIe
host controller and will be able to share a driver once support for
spear and imx is added."* tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (480 commits)
ARM: integrator: let pciv3 use mem/premem from device tree
ARM: integrator: set local side PCI addresses right
ARM: dts: Add pcie controller node for exynos5440-ssdk5440
ARM: dts: Add pcie controller node for Samsung EXYNOS5440 SoC
ARM: EXYNOS: Enable PCIe support for Exynos5440
pci: Add PCIe driver for Samsung Exynos
ARM: OMAP5: voltagedomain data: remove temporary OMAP4 voltage data
ARM: keystone: Move CPU bringup code to dedicated asm file
ARM: multiplatform: always pick one CPU type
ARM: imx: select syscon for IMX6SL
ARM: keystone: select ARM_ERRATA_798181 only for SMP
ARM: imx: Synertronixx scb9328 needs to select SOC_IMX1
ARM: OMAP2+: AM43x: resolve SMP related build error
dmaengine: edma: enable build for AM33XX
ARM: edma: Add EDMA crossbar event mux support
ARM: edma: Add DT and runtime PM support to the private EDMA API
dmaengine: edma: Add TI EDMA device tree binding
arm: add basic support for Rockchip RK3066a boards
arm: add debug uarts for rockchip rk29xx and rk3xxx series
arm: Add basic clocks for Rockchip rk3066a SoCs
...
19 Jun, 2013
3 commits
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Add DFLL DVCO reset line control functions to the CAR IP block driver.
The DVCO present in the DFLL IP block has a separate reset line,
exposed via the CAR IP block. This reset line is asserted upon SoC
reset. Unless something (such as the DFLL driver) deasserts this
line, the DVCO will not oscillate, although reads and writes to the
DFLL IP block will complete.Thanks to Aleksandr Frid for identifying this and
saving hours of debugging time.Signed-off-by: Paul Walmsley
Cc: Aleksandr Frid
Cc: Peter De Schrijver
Signed-off-by: Mike Turquette -
Add the input clocks needed by the DFLL IP blocks. Initialize them to
51MHz (as required by the DFLL GFD) and to use the PLL_P clock source.This patch is a collaboration with Peter De Schrijver
.Thanks to Laxman Dewangan for identifying the
requirement to keep the DFLL clocks enabled to resolve PWR_I2C timeout
issues.Signed-off-by: Paul Walmsley
Cc: Peter De Schrijver
Reviewed-by: Andrew Chew
Cc: Matthew Longnecker
Cc: Laxman Dewangan
Signed-off-by: Mike Turquette -
Add clock functions to initialize, enable, and disable the FCPU clock
shapers, based on the FCPU voltage rail state. These will be used by
the DFLL clocksource driver code.This version of the patch contains a fix for a problem noticed by Andrew
Chew , where some of the FINETRIM_R bitfields were
incorrectly defined.Based on code originally written by Aleksandr Frid .
Signed-off-by: Paul Walmsley
Cc: Andrew Chew
Reviewed-by: Andrew Chew
Cc: Matthew Longnecker
Cc: Aleksandr Frid
Signed-off-by: Mike Turquette
17 Jun, 2013
1 commit
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Registering pciex as peripheral clock instead of fixed clock
as tegra_perih_reset_assert(deassert) api of this clock api
gives warning and ultimately does not succeed to assert(deassert)Signed-off-by: Jay Agarwal
Acked-by: Stephen Warren
Signed-off-by: Mike Turquette
15 Jun, 2013
1 commit
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…swarren/linux-tegra into next/soc
From Stephen Warren:
ARM: tegra: core SoC support enhancementsThis branch contains fixes and enhancement for core Tegra Soc support:
* CPU hotplug support for Tegra114.
* Some preliminary work on Tegra114 CPU sleep modes.
* Minor fix for EMC table DT parsing.* tag 'tegra-for-3.11-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra:
ARM: tegra: don't pass CPU ID to tegra_{set,clear}_cpu_in_lp2
ARM: tegra: cpuidle: using IS_ENABLED for multi SoCs management in init func
ARM: tegra: hook tegra_tear_down_cpu function in the PM suspend init function
ARM: tegra: cpuidle: move the init function behind the suspend init function
ARM: tegra: remove ifdef in the tegra_resume
ARM: tegra: add cpu_disable for hotplug
ARM: tegra114: add CPU hotplug support
clk: tegra114: implement wait_for_reset and disable_clock for tegra_cpu_car_ops
ARM: tegra114: add power up sequence for warm boot CPU
ARM: tegra: make tegra_resume can work for Tegra114
ARM: tegra: skip SCU and PL310 code when CPU is not Cortex-A9
ARM: tegra: add an assembly marco to check Tegra SoC ID
ARM: tegra: emc: correction of ram-code parsing from dtSigned-off-by: Olof Johansson <olof@lixom.net>
12 Jun, 2013
10 commits
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PLLM has override bits in the PMC. Use those when PLLM_OVERRIDE_ENABLE
is set.Signed-off-by: Peter De Schrijver
Tested-by: Stephen Warren
Acked-by: Stephen Warren
Signed-off-by: Mike Turquette -
Define override bits for Tegra30 PLLM.
Signed-off-by: Peter De Schrijver
Tested-by: Stephen Warren
Acked-by: Stephen Warren
Signed-off-by: Mike Turquette -
Define override bits for Tegra114 PLLM.
Signed-off-by: Peter De Schrijver
Tested-by: Stephen Warren
Acked-by: Stephen Warren
Signed-off-by: Mike Turquette
[mturquette@linaro.org: fixed up trivial merge conflict] -
PLLM can have override bits in the PMC. Describe those in the PLL parameters.
Signed-off-by: Peter De Schrijver
Tested-by: Stephen Warren
Acked-by: Stephen Warren
Signed-off-by: Mike Turquette -
Use the correct parents for sclk according to the TRM.
Signed-off-by: Peter De Schrijver
Tested-by: Stephen Warren
Acked-by: Stephen Warren
Signed-off-by: Mike Turquette -
The PLLRE flags weren't set correctly. Fixed in this patch.
Signed-off-by: Peter De Schrijver
Tested-by: Stephen Warren
Acked-by: Stephen Warren
Signed-off-by: Mike Turquette -
Signed-off-by: Peter De Schrijver
Tested-by: Stephen Warren
Acked-by: Stephen Warren
Signed-off-by: Mike Turquette -
The m,n,p fields don't have the same bit offset and width across all PLLs.
This patch allows SoC specific files to indicate the offset and width.Signed-off-by: Peter De Schrijver
Tested-by: Stephen Warren
Acked-by: Stephen Warren
Signed-off-by: Mike Turquette -
The pllp_out2 should be integer only, the fractional bit should always be 0.
Signed-off-by: Peter De Schrijver
Tested-by: Stephen Warren
Acked-by: Stephen Warren
Signed-off-by: Mike Turquette -
The pllc and pllxc code weren't always using the correct pdiv_map to
map between the post divider value and the hw p field. This could result
in illegal values being programmed in the hw.Signed-off-by: Peter De Schrijver
Tested-by: Stephen Warren
Acked-by: Stephen Warren
Signed-off-by: Mike Turquette
05 Jun, 2013
1 commit
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The msenc clock's register was set to the usb3 clock's register.
Signed-off-by: Mikko Perttunen
Acked-by: Peter De Schrijver
Signed-off-by: Mike Turquette
01 Jun, 2013
3 commits
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Use common of_clk_init() function for clocks initialization.
Signed-off-by: Prashant Gaikwad
Reviewed-by: Thierry Reding
Acked-by: Stephen Warren
Signed-off-by: Mike Turquette -
Tegra has a blink timer register that allows to modulate the
clk_32k clock before outputting it. Since clk_32k is presented to the
kernel as a fixed clock, make sure this register does not tamper with
the clock frequency and that clk_32k is outputted as-is, similarly to
what is done on t20 and t30.Signed-off-by: Alexandre Courbot
Acked-by: Stephen Warren
Signed-off-by: Mike Turquette -
Number of parents for clk_out_2 and clk_out_3 was incorrectly set
to clk_out1_parents. Even though it did not break anything since the
size was same better to fix.Signed-off-by: Prashant Gaikwad
Reviewed-by: Thierry Reding
Acked-by: Stephen Warren
Signed-off-by: Mike Turquette
23 May, 2013
1 commit
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The conventional CPU hotplug sequence on the other Tegra chips, we will also
clock gate the CPU in tegra_cpu_kill() after the CPU was power gated. For
Tegra114, the flow controller will clock gate the CPU after the power down
sequence. But we still need to implement a empty function for disable_clock
to avoid kernel warning message.Signed-off-by: Joseph Lo
Acked-by: Mike Turquette
Signed-off-by: Stephen Warren
21 May, 2013
2 commits
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AC97 controller clock is hardwired to pll_a_out0.
Signed-off-by: Lucas Stach
Acked-by: Peter De Schrijver
Reviewed-by: Prashant Gaikwad
Acked-by: Mike Turquette
Tested-by: Stephen Warren
Signed-off-by: Stephen Warren
Signed-off-by: Olof Johansson -
The USB clocks are just clock gates, so no need to set a specific clock.
In fact trying to set a specific clock is just a NOP if the requested
clockrate is the same as those of the parent (clk_m) or will trigger a
WARN_ON() if rates don't match up.As we are not setting a specific rate, nor activating the clocks at
init, there is no point in keeping the the usb entries in the clock init
table.Signed-off-by: Lucas Stach
Acked-by: Peter De Schrijver
Reviewed-by: Prashant Gaikwad
Acked-by: Mike Turquette
Tested-by: Stephen Warren
Signed-off-by: Stephen Warren
Signed-off-by: Olof Johansson
05 May, 2013
1 commit
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Pull ARM SoC driver changes from Olof Johansson:
"This is a rather large set of patches for device drivers that for one
reason or another the subsystem maintainer preferred to get merged
through the arm-soc tree. There are both new drivers as well as
existing drivers that are getting converted from platform-specific
code into standalone drivers using the appropriate subsystem specific
interfaces.In particular, we can now have pinctrl, clk, clksource and irqchip
drivers in one file per driver, without the need to call into platform
specific interface, or to get called from platform specific code, as
long as all information about the hardware is provided through a
device tree.Most of the drivers we touch this time are for clocksource. Since now
most of them are part of drivers/clocksource, I expect that we won't
have to touch these again from arm-soc and can let the clocksource
maintainers take care of these in the future.Another larger part of this series is specific to the exynos platform,
which is seeing some significant effort in upstreaming and
modernization of its device drivers this time around, which
unfortunately is also the cause for the churn and a lot of the merge
conflicts.There is one new subsystem that gets merged as part of this series:
the reset controller interface, which is a very simple interface for
taking devices on the SoC out of reset or back into reset. Patches to
use this interface on i.MX follow later in this merge window, and we
are going to have other platforms (at least tegra and sirf) get
converted in 3.11. This will let us get rid of platform specific
callbacks in a number of platform independent device drivers."* tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (256 commits)
irqchip: s3c24xx: add missing __init annotations
ARM: dts: Disable the RTC by default on exynos5
clk: exynos5250: Fix parent clock for sclk_mmc{0,1,2,3}
ARM: exynos: restore mach/regs-clock.h for exynos5
clocksource: exynos_mct: fix build error on non-DT
pinctrl: vt8500: wmt: Fix checking return value of pinctrl_register()
irqchip: vt8500: Convert arch-vt8500 to new irqchip infrastructure
reset: NULL deref on allocation failure
reset: Add reset controller API
dt: describe base reset signal binding
ARM: EXYNOS: Add arm-pmu DT binding for exynos421x
ARM: EXYNOS: Add arm-pmu DT binding for exynos5250
ARM: EXYNOS: Enable PMUs for exynos4
irqchip: exynos-combiner: Correct combined IRQs for exynos4
irqchip: exynos-combiner: Add set_irq_affinity function for combiner_irq
ARM: EXYNOS: fix compilation error introduced due to common clock migration
clk: exynos5250: Fix divider values for sclk_mmc{0,1,2,3}
clk: exynos4: export clocks required for fimc-is
clk: samsung: Fix compilation error
clk: tegra: fix enum tegra114_clk to match binding
...
03 May, 2013
1 commit
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Pull ARM SoC multiplatform updates from Olof Johansson:
"More multiplatform enablement for ARM platforms. The ones converted
in this branch are:- bcm2835
- cns3xxx
- sirf
- nomadik
- msx
- spear
- tegra
- ux500We're getting close to having most of them converted!
One of the larger platforms remaining is Samsung Exynos, and there are
a bunch of supporting patches in this merge window for it. There was
a patch in this branch to a early version of multiplatform conversion,
but it ended up being reverted due to need of more bake time. The
revert commit is part of the branch since it would have required
rebasing multiple dependent branches and they were stable by then"* tag 'multiplatform-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (70 commits)
mmc: sdhci-s3c: Fix operation on non-single image Samsung platforms
clocksource: nomadik-mtu: fix up clocksource/timer
Revert "ARM: exynos: enable multiplatform support"
ARM: SPEAr13xx: Fix typo "ARCH_HAVE_CPUFREQ"
ARM: exynos: enable multiplatform support
rtc: s3c: make header file local
mtd: onenand/samsung: make regs-onenand.h file local
thermal/exynos: remove unnecessary header inclusions
mmc: sdhci-s3c: remove platform dependencies
ARM: samsung: move mfc device definition to s5p-dev-mfc.c
ARM: exynos: move debug-macro.S to include/debug/
ARM: exynos: prepare for sparse IRQ
ARM: exynos: introduce EXYNOS_ATAGS symbol
ARM: tegra: build assembly files with -march=armv7-a
ARM: Push selects for TWD/SCU into machine entries
ARM: ux500: build hotplug.o for ARMv7-a
ARM: ux500: move to multiplatform
ARM: ux500: make remaining headers local
ARM: ux500: make irqs.h local to platform
ARM: ux500: get rid of
...
02 May, 2013
1 commit
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Pull ARM SoC non-critical fixes from Olof Johansson:
"Here is a collection of fixes (and some intermixed cleanups) that were
considered less important and thus not included in the later parts of
the 3.9-rc cycle.It's a bit all over the map, contents wise. A series of ux500 fixes
and cleanups, a bunch of various fixes for OMAP and tegra, and some
for Freescale i.MX and even Qualcomm MSM.Note that there's also a patch on this branch to globally turn off
-Wmaybe-uninitialized when building with -Os. It's been posted
several times by Arnd and no dissent was raised, but nobody seemed
interested to pick it up. So here it is, as the topmost patch."* tag 'fixes-nc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (70 commits)
Turn off -Wmaybe-uninitialized when building with -Os
ARM: orion5x: include linux/cpu.h
ARM: tegra: call cpu_do_idle from C code
ARM: u300: fix ages old copy/paste bug
ARM: OMAP2+: add dependencies on ARCH_MULTI_V6/V7
ARM: tegra: solve adr range issue with THUMB2_KERNEL enabled
ARM: tegra: fix relocation truncated error when THUMB2_KERNEL enabled
ARM: tegra: fix build error when THUMB2_KERNEL enabled
ARM: msm: Fix uncompess.h tx underrun check
ARM: vexpress: Remove A9 PMU compatible values for non-A9 platforms
ARM: cpuimx27 and mbimx27: prepend CONFIG_ to Kconfig macro
ARM: OMAP2+: fix typo "CONFIG_BRIDGE_DVFS"
ARM: OMAP1: remove "config MACH_OMAP_HTCWIZARD"
ARM: mach-imx: mach-imx6q: Fix sparse warnings
ARM: mach-imx: src: Include "common.h
ARM: mach-imx: gpc: Include "common.h"
ARM: mach-imx: avic: Staticize *avic_base
ARM: mach-imx: tzic: Staticize *tzic_base
ARM: mach-imx: clk: Include "clk.h"
ARM: mach-imx: clk-busy: Staticize clk_busy_mux_ops
...
30 Apr, 2013
1 commit
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Pull clock framework update from Michael Turquette:
"The common clock framework changes for 3.10 include many fixes for
existing platforms, as well as adoption of the framework by new
platforms and devices.Some long-needed fixes to the core framework are here as well as new
features such as improved initialization of clocks from DT as well as
framework reentrancy for nested clock operations."* tag 'clk-for-linus-3.10' of git://git.linaro.org/people/mturquette/linux: (44 commits)
clk: add clk_ignore_unused option to keep boot clocks on
clk: ux500: fix mismatched types
clk: vexpress: Add separate SP810 driver
clk: si5351: make clk-si5351 depend on CONFIG_OF
clk: export __clk_get_flags for modular clock providers
clk: vt8500: Missing breaks in vtwm_pll_round_rate/_set_rate.
clk: sunxi: Unify oscillator clock
clk: composite: allow fixed rates & fixed dividers
clk: composite: rename 'div' references to 'rate'
clk: add si5351 i2c common clock driver
clk: add device tree fixed-factor-clock binding support
clk: Properly handle notifier return values
clk: ux500: abx500: Define clock tree for ab850x
clk: ux500: Add support for sysctrl clocks
clk: mvebu: Fix valid value range checking for cpu_freq_select
clk: Fixup locking issues for clk_set_parent
clk: Fixup errorhandling for clk_set_parent
clk: Restructure code for __clk_reparent
clk: sunxi: drop an unnecesary kmalloc
clk: sunxi: drop CLK_IGNORE_UNUSED
...
09 Apr, 2013
3 commits
-
…ernel/git/swarren/linux-tegra into next/multiplatform
From Stephen Warren <swarren@wwwdotorg.org>:
ARM: tegra: multi-platform conversion
This branch converts Tegra to support multi-platform/single-zImage.
One header is made accessible to drivers. The earlyprintk implementation
is moved to the multi-platform location. Some Kconfig changes are made
to enable multi-platform. Some dead files are deleted.The APIs exposed in the now-global tegra-powergate.h should be replaced
with standard reset and power domain APIs in the future.This branch is based on (part of) the previous soc pull request.
* tag 'tegra-for-3.10-multiplatform' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra:
ARM: tegra: convert to multi-platform
ARM: tegra: move <mach/powergate.h> to <linux/tegra-powergate.h>Signed-off-by: Arnd Bergmann <arnd@arndb.de>
-
This is a dependency for the tegra multiplatform series.
Conflicts:
drivers/clocksource/tegra20_timer.cSigned-off-by: Arnd Bergmann
-
…t/swarren/linux-tegra into next/fixes-non-critical
From Stephen Warren <swarren@wwwdotorg.org>:
ARM: tegra: minor fixes
This branch contains a variety of small build and run-time fixes that
weren't important enough for 3.9.* Enable CPU errata WARs in secondary reset handler as a preparation
for multi-platform support, and a related fix.
* Don't touch DBLGAR in reset/resume handlers, so enable the code to
run on A15 cores.
* Minor build fixes.
* A fix to the Tegra clock driver.
* Some error-handling fixes.This branch is based on the previous fixes-for-mmc pull request.
* tag 'tegra-for-3.10-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra:
ARM: tegra: powergate: Don't error out if new state == old state
ARM: tegra: Export tegra_powergate_sequence_power_up()
memory: tegra30: Fix build error w/o PM
ARM: tegra: fix ignored return value of regulator_enable
ARM: tegra: fix the logical detection of power on sequence of warm boot CPUs
ARM: tegra: Fix unchecked return value
ARM: tegra: don't unlock MMIO access to DBGLAR
clk: tegra: No 7.1 super clk dividers on Tegra20
ARM: tegra: remove save/restore of CPU diag register
ARM: tegra: add CPU errata WARs to Tegra reset handler
ARM: dts: tegra: fix the activate polarity of cd-gpio in mmc hostSigned-off-by: Arnd Bergmann <arnd@arndb.de>
05 Apr, 2013
9 commits
-
A gap exists in the binding's clock ID definitions. Fix the clock driver
to be consistent. This allows pclk to be looked up through device tree
and prevents:ERROR: could not get clock /pmc:pclk(0)
Signed-off-by: Stephen Warren
-
The UART driver enables the console uart clock, so we don't need to do that
anymore in this file.Signed-off-by: Peter De Schrijver
Acked-by: Mike Turquette
Signed-off-by: Stephen Warren -
Signed-off-by: Peter De Schrijver
Acked-by: Mike Turquette
Signed-off-by: Stephen Warren -
Implement clocks for Tegra114.
Signed-off-by: Peter De Schrijver
Acked-by: Mike Turquette
Signed-off-by: Stephen Warren -
Workaround a hardware bug in MSENC during clock enable.
Signed-off-by: Peter De Schrijver
Acked-by: Mike Turquette
Signed-off-by: Stephen Warren -
We will need some tegra peripheral clocks with the CLK_IGNORE_UNUSED flag,
most notably mselect, which is a bridge between AXI and most peripherals.Signed-off-by: Peter De Schrijver
Acked-by: Mike Turquette
Signed-off-by: Stephen Warren -
Tegra114 introduces new PLL types. This requires new clocktypes as well
as some new fields in the pll structure.Signed-off-by: Peter De Schrijver
Acked-by: Mike Turquette
Signed-off-by: Stephen Warren -
PLLC2 and PLLC3 on Tegra114 have separate phaselock and frequencylock bits.
So switch to a lock mask to be able to test both at the same time.Signed-off-by: Peter De Schrijver
Acked-by: Mike Turquette
Signed-off-by: Stephen Warren -
Some PLLs in Tegra114 don't use a power of 2 mapping for the post divider.
Introduce a table based approach and switch PLLU to it.Signed-off-by: Peter De Schrijver
Acked-by: Mike Turquette
Signed-off-by: Stephen Warren
