06 Apr, 2010
1 commit
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Locking statistics are implemented using global atomic
variables. This is usually fine unless some path write them very
often.This is the case for the function and function graph tracers
that disable irqs for each entry saved (except if the function
tracer is in preempt disabled only mode).
And calls to local_irq_save/restore() increment
hardirqs_on_events and hardirqs_off_events stats (or similar
stats for redundant versions).Incrementing these global vars for each function ends up in too
much cache bouncing if lockstats are enabled.To solve this, implement the debug_atomic_*() operations using
per cpu vars.-v2: Use per_cpu() instead of get_cpu_var() to fetch the desired
cpu vars on debug_atomic_read()-v3: Store the stats in a structure. No need for local_t as we
are NMI/irq safe.-v4: Fix tons of build errors. I thought I had tested it but I
probably forgot to select the relevant config.Suggested-by: Steven Rostedt
Signed-off-by: Frederic Weisbecker
Cc: Peter Zijlstra
Cc: Steven Rostedt
LKML-Reference:
Signed-off-by: Ingo Molnar
Cc: Peter Zijlstra
Cc: Steven Rostedt
02 Mar, 2010
39 commits
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i8253_lock needs to be a real spinlock in preempt-rt, i.e. it can
not be converted to a sleeping lock.Convert it to raw_spinlock and fix up all users.
Signed-off-by: Thomas Gleixner
Acked-by: Ralf Baechle
Acked-by: Dmitry Torokhov
Acked-by: Takashi Iwai
Cc: Jens Axboe
LKML-Reference: -
…t/khilman/linux-davinci
* 'davinci-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci: (40 commits)
DaVinci DM365: Adding support for SPI EEPROM
DaVinci DM365: Adding DM365 SPI support
DaVinci DM355: Modifications to DM355 SPI support
DaVinci: SPI: Adding header file for SPI support.
davinci: dm646x: CDCE clocks: davinci_clk converted to clk_lookup
davinci: clkdev cleanup: remove clk_lookup wrapper, use clkdev_add_table()
DaVinci: DM365: Voice codec support for the DM365 SoC
davinci: clock: let clk->set_rate function sleep
Add SDA and SCL pin numbers to i2c platform data
davinci: da8xx/omap-l1xx: Add EDMA platform data for da850/omap-l138
davinci: build list of unused EDMA events dynamically
davinci: Fix edma_alloc_channel api for EDMA_CHANNEL_ANY case
davinci: Keep count of channel controllers on a platform
davinci: Correct return value of edma_alloc_channel api
davinci: add CDCE949 support on DM6467 EVM
davinci: add support for CDCE949 clock synthesizer
davinci: da850/omap-l138 EVM: register for suspend support
davinci: da850/omap-l138: add support for SoC suspend
davinci: add power management support
DaVinci: DM365: Changing default queue for DM365.
... -
* 'upstream-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jgarzik/libata-dev: (38 commits)
sata_via: Delay on vt6420 when starting ATAPI DMA write
ata: Detect Delkin Devices compact flash
pata_efar: Enable parallel scanning
pata_atiixp: enable parallel scan
[libata] pata_atiixp: add locking for parallel scanning
[libata] pata_efar: add locking for parallel scanning
libata: Pass host flags into the pci helper
[libata] pata_marvell: CONFIG_AHCI is really CONFIG_SATA_AHCI
libata: Allow pata_legacy to be built on non-ISA but PCI systems
pata_pdc202xx_old: fix UDMA mode for PDC2026x chipsets
pata_pdc202xx_old: fix UDMA mode for Promise UDMA33 cards
[libata] pata_at91: fix backslash-continued string
pata_via: store UDMA masks in via_isa_bridges table
pata_via: fix address setup timings underlocking
pata_serverworks: fix error message
pata_serverworks: fix PIO setup for the second channel
pata_efar: fix secondary port support
pata_cypress: fix PIO timings underclocking
pata_cs5535: use correct values for PIO1 and PIO2 data timings
pata_cmd64x: remove unused definitions
... -
When writing a disc on certain lite-on dvd-writers (also rebadged
as optiarc/LG/...) connected to a vt6420, the ATAPI CDB ends
up in the datastream and on the disc, causing silent corruption.
Delaying between sending the CDB and starting DMA seems to
prevent this.I do not know if there are burners that do not suffer from
this, but the patch should be safe for those as well.There are many reports of this issue, but AFAICT no solution was
found before. For example:
http://lkml.indiana.edu/hypermail/linux/kernel/0802.3/0561.htmlSigned-off-by: Bart Hartgers
Signed-off-by: Jeff Garzik -
I have a Delkin Devices compact flash card that isn't being recognized using the
SATA/PATA drivers.
The card is recognized and works with the deprecated ATA drivers.The error I am seeing is:
ata1.00: failed to IDENTIFY (device reports invalid type, err_mask=0x0)I tracked it down to ata_id_is_cfa() in include/linux/ata.h.
The Delkin card has id[0] set to 0x844a and id[83] set to 0.
This isn't what the kernel expects and is probably incorrect.The simplest work-around is to add a check for 0x844a to ata_id_is_cfa().
Signed-off-by: Ben Gardner
Signed-off-by: Jeff Garzik -
Again originally proposed by Bartlomiej but this does it by using the
generic helper logic instead.Signed-off-by: Alan Cox
Signed-off-by: Jeff Garzik -
This was originally proposed by Bartlomiej but as a device specific
expansion of the init_one function rather than making the helper more
generic.Enable the parallel scan via the generic flags.
Signed-off-by: Alan Cox
Signed-off-by: Jeff Garzik -
This is similar change as commit 60c3be3 for ata_piix host driver
and while pata_atiixp doesn't enable parallel scan yet the race
could probably also be triggered by requesting re-scanning of both
ports at the same time using SCSI sysfs interface.[Ported to current tree without other patch dependancies by Alan Cox]
Original is
Signed-off-by: Bartlomiej ZolnierkiewiczThis one is
Signed-off-by: Alan Cox
Signed-off-by: Jeff Garzik -
Add clearing of UDMA enable bit also for PIO modes and then add
extra locking for parallel scanning.This is similar change as commit 60c3be3 for ata_piix host driver
and while pata_efar doesn't enable parallel scan yet the race could
probably also be triggered by requesting re-scanning of both ports
at the same time using SCSI sysfs interface.[Ported to current kernel without other patch dependancies by
Alan Cox]Original is
Signed-off-by: Bartlomiej ZolnierkiewiczThis one is
Signed-off-by: Alan Cox
Signed-off-by: Jeff Garzik -
This allows parallel scan and the like to be set without having to stop
using the existing full helper functions. This patch merely adds the argument
and fixes up the callers. It doesn't undo the special cases already in the
tree or add any new parallel callers.Signed-off-by: Alan Cox
Signed-off-by: Jeff Garzik -
The marvell driver comtains a fallback to ahci for the sata ports
which is incorrectly checked as CONFIG_AHCI while the only AHCI config
item is actually called SATA_AHCI (which also sounds sensible
considering it's a fallback for the sata ports).Signed-off-by: Christoph Egger
Signed-off-by: Jeff Garzik -
This is needed for some unsupported hardware setups on strange 64bit
mainboards where crazy stuff has been done like putting flash ata adapters
on the LPC bus, or where the real hardware is hidden/confused.Signed-off-by: Alan Cox
Signed-off-by: Jeff Garzik -
PDC2026x chipsets need the same treatment as PDC20246 one.
This is completely untested but will hopefully fix UDMA issues
that people have been reporting against pata_pdc202xx_old for
the last couple of years.Signed-off-by: Bartlomiej Zolnierkiewicz
Signed-off-by: Jeff Garzik -
On Monday 04 January 2010 02:30:24 pm Russell King wrote:
> Found the problem - getting rid of the read of the alt status register
> after the command has been written fixes the UDMA CRC errors on write:
>
> @@ -676,7 +676,8 @@ void ata_sff_exec_command(struct ata_port *ap, const struct
> ata_taskfile *tf)
> DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
>
> iowrite8(tf->command, ap->ioaddr.command_addr);
> - ata_sff_pause(ap);
> + ndelay(400);
> +// ata_sff_pause(ap);
> }
> EXPORT_SYMBOL_GPL(ata_sff_exec_command);
>
>
> This rather makes sense. The PDC20247 handles the UDMA part of the
> protocol. It has no way to tell the PDC20246 to wait while it suspends
> UDMA, so that a normal register access can take place - the 246 ploughs
> on with the register access without any regard to the state of the 247.
>
> If the drive immediately starts the UDMA protocol after a write to the
> command register (as it probably will for the DMA WRITE command), then
> we'll be accessing the taskfile in the middle of the UDMA setup, which
> can't be good. It's certainly a violation of the ATA specs.Fix it by adding custom ->sff_exec_command method for UDMA33 chipsets.
Debugged-by: Russell King
Signed-off-by: Bartlomiej Zolnierkiewicz
Signed-off-by: Jeff Garzik -
Noticed and rough patch by Joe Perches.
Signed-off-by: Jeff Garzik
-
* store UDMA masks in via_isa_bridges[] and while at it make "flags"
field to be u8 instead of u16* convert the driver to use UDMA masks from via_isa_bridges[]
* remove no longer needed VIA_UDMA* defines
Make some minor documentation and CodingStyle fixes while at it.
Signed-off-by: Bartlomiej Zolnierkiewicz
Signed-off-by: Jeff Garzik -
Correct via_do_set_mode() documentation while at it.
Signed-off-by: Bartlomiej Zolnierkiewicz
Signed-off-by: Jeff Garzik -
Signed-off-by: Bartlomiej Zolnierkiewicz
Signed-off-by: Jeff Garzik -
Signed-off-by: Bartlomiej Zolnierkiewicz
Signed-off-by: Jeff Garzik -
Signed-off-by: Bartlomiej Zolnierkiewicz
Signed-off-by: Jeff Garzik -
Timing registers should be programmed with the desired number of clocks
minus one clock.Signed-off-by: Bartlomiej Zolnierkiewicz
Signed-off-by: Jeff Garzik -
There shouldn't be any problems with it as IDE cs5535 host driver
has been using those values for years and they match values given
in the (publicly available) datasheet.Signed-off-by: Bartlomiej Zolnierkiewicz
Signed-off-by: Jeff Garzik -
s/ARTIM2/ARTTIM23/ in cmd648_bmdma_stop() while at it
Signed-off-by: Bartlomiej Zolnierkiewicz
Signed-off-by: Jeff Garzik -
Clear the primary channel pending interrupt bit
instead of the reserved one.Signed-off-by: Bartlomiej Zolnierkiewicz
Signed-off-by: Jeff Garzik -
Account for the requirements of the DMA mode currently used
by the pair device.Signed-off-by: Bartlomiej Zolnierkiewicz
Signed-off-by: Jeff Garzik -
Fix incorrect handling of recovery clocks value == 16 resulting
in overclocked recovery timings & potentially underclocked active
timings.Signed-off-by: Bartlomiej Zolnierkiewicz
Signed-off-by: Jeff Garzik -
Signed-off-by: Bartlomiej Zolnierkiewicz
Signed-off-by: Jeff Garzik -
Use standard cycle timing for CFA PIO5 and PIO6 modes.
Based on commit 74638c8 for IDE subsystem.
Signed-off-by: Bartlomiej Zolnierkiewicz
Signed-off-by: Jeff Garzik -
Before only the timings for master were set. Datasheet can be found
here: ftp://ftp.vtbridge.org/Docs/Storage/DS_VT6421A_100_CCPL.PDF
Surprisingly, a slave drive works without this patch. According to the
datasheet, the controller by default derives the DMA mode from the
Set Features command issued to a drive. Not sure about the PIO
timings, though. The real problem is that the timings for the master
effectively are the ones tuned for the slave. If these support
different UDMA-settings, there is trouble, especially when the slave
supports a higher UDMA than the master.Anyhow, using the same mechanism for both master and slave seems like
a good idea.Signed-off-by: Bart Hartgers
Acked-by: Tejun Heo
Signed-off-by: Jeff Garzik -
Make some variables in ahci and a function in pata_pcmcia static, as found
using sparse.Signed-off-by: Robert Hancock
Signed-off-by: Jeff Garzik -
Traditional IDE interface sucks in that it doesn't have a reliable IRQ
pending bit, so if the controller raises IRQ while the driver is
expecting it not to, the IRQ won't be cleared and eventually the IRQ
line will be killed by interrupt subsystem. Some controllers have
non-standard mechanism to indicate IRQ pending so that this condition
can be detected and worked around.This patch adds an optional operation ->sff_irq_check() which will be
called for each port from the ata_sff_interrupt() if an unexpected
interrupt is received. If the operation returns %true,
->sff_check_status() and ->sff_irq_clear() will be cleared for the
port. Note that this doesn't mark the interrupt as handled so it
won't prevent IRQ subsystem from killing the IRQ if this mechanism
fails to clear the spurious IRQ.This patch also implements ->sff_irq_check() for ata_piix. Note that
this adds slight overhead to shared IRQ operation as IRQs which are
destined for other controllers will trigger extra register accesses to
check whether IDE interrupt is pending but this solves rare screaming
IRQ cases and for some curious reason also helps weird BIOS related
glitch on Samsung n130 as reported in bko#14314.http://bugzilla.kernel.org/show_bug.cgi?id=14314
* piix_base_ops dropped as suggested by Sergei.
* Spurious IRQ detection doesn't kick in anymore if polling qc is in
progress. This provides less protection but some controllers have
possible data corruption issues if the wrong register is accessed
while a command is in progress.Signed-off-by: Tejun Heo
Reported-by: Johannes Stezenbach
Reported-by: Hans Werner
Cc: Alan Cox
Cc: Sergei Shtylyov
Signed-off-by: Jeff Garzik -
host->ports[i] is never NULL if i < host->n_ports and non-NULL return
from ata_qc_from_tag() guarantees that the returned qc is active.
Drop unnecessary tests.Superflous () dropped as suggested by Sergei.
Signed-off-by: Tejun Heo
Cc: Sergei Shtylyov
Signed-off-by: Jeff Garzik -
Signed-off-by: Seth Heasley
Signed-off-by: Jeff Garzik -
Signed-off-by: Seth Heasley
Signed-off-by: Jeff Garzik -
Tested on AMD internal reference board.
Signed-off-by: Shane Huang
Acked-by: Tejun Heo
Signed-off-by: Jeff Garzik -
HPT36x chips just don't have DPLL.
Signed-off-by: Sergei Shtylyov
Signed-off-by: Jeff Garzik -
Describe UDMA timing bits 18-20 and 21 separately; add a note to bit
31 about it being meaningful for PIO only. Reformat the whole comment,
while at it...Signed-off-by: Sergei Shtylyov
Signed-off-by: Jeff Garzik -
There's no need to clear the fast interrupt bit in hpt366_set_mode()
since we're doing it in hpt366_init_chipset() already.While at it, rename 'addr1' local variable to 'addr' and
exclude 'ap->port_no' from its calculation as HPT36x are
single-channel-per-function chips.Signed-off-by: Sergei Shtylyov
Signed-off-by: Jeff Garzik -
As these drivers' set_piomode() and set_dmamode() methods are almost
identical, factor out the common hpt{37x|3x2n}_set_mode() function
to be called by both of them, the same as in 'pata_hpt366' driver.This results in ~5% decrease in the 'pata_hpt37x' driver binary
size and in ~4% decrease in the 'pata_hpt3x2n' driver binary size
(as measured on x86-32).Signed-off-by: Sergei Shtylyov
Signed-off-by: Jeff Garzik
