05 Mar, 2013
1 commit
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Remove duplicate smp_twd clocks as these clocks are accessed using
DT now.Signed-off-by: Prashant Gaikwad
Signed-off-by: Stephen Warren
Signed-off-by: Olof Johansson
14 Feb, 2013
2 commits
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Initialise the parent of UARTs to PLLP and disabling clock by
default.Signed-off-by: Laxman Dewangan
Acked-by: Mike Turquette
Signed-off-by: Stephen Warren -
enum tegra*_clk is intended to match the IDs listed in the Tegra clock
bindings. There are a few mismatches, which this patch fixes:1) pll_s and cop were left out of the Tegra20 enum.
2) spdif_in and spdif_out were swapped relative to the Tegra30 binding.
3) i2cslow was misnamed as i2c_slow, and a duplicate i2cslow clock added
to the Tegra30 enum.Signed-off-by: Stephen Warren
Reviewed-by: Thierry Reding
Tested-by: Thierry Reding
13 Feb, 2013
4 commits
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cclk_g_parents, cclk_lp_parents and sclk_parents are only accessed from within
clk-tegra30.c. Declare them static to avoid namespace polution.Signed-off-by: Peter De Schrijver
Acked-by: Mike Turquette
Reviewed-by: Prashant Gaikwad
Signed-off-by: Stephen Warren -
The hclk and pclk clocks are controlled by the same register. Hence a lock is
required to avoid corruption.Signed-off-by: Peter De Schrijver
Acked-by: Mike Turquette
Reviewed-by: Prashant Gaikwad
Signed-off-by: Stephen Warren -
Although tegra_clk_register_super_mux() has a lock parameter, the lock is not
actually used by the code. Fixed with this patch.Signed-off-by: Peter De Schrijver
Acked-by: Mike Turquette
Reviewed-by: Prashant Gaikwad
Signed-off-by: Stephen Warren -
The index of se should be 127. And the previous clock index was 125. So
we need to set up the index for se to get the correct index between se
to sata_cold.Signed-off-by: Joseph Lo
Signed-off-by: Stephen Warren
29 Jan, 2013
7 commits
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Implementing suspend, resume and rail_off_ready API for tegra_cpu_car_ops. These
functions were used for CPU powered-down state maintenance.Signed-off-by: Joseph Lo
Signed-off-by: Stephen Warren -
With device tree support added for Tegra clocks look up is done from
device tree, remove unused TEGRA_CLK_DUPLICATE()s.Signed-off-by: Prashant Gaikwad
Acked-by: Mike Turquette
Signed-off-by: Stephen Warren -
With device tree support added for Tegra clocks look up is done from
device tree, remove unused TEGRA_CLK_DUPLICATE()s.Signed-off-by: Prashant Gaikwad
Acked-by: Mike Turquette
Signed-off-by: Stephen Warren -
Migrate Tegra clock support to drivers/clk/tegra, this involves
moving:
1. definition of tegra_cpu_car_ops to clk.c
2. definition of reset functions to clk-peripheral.c
3. change parent of cpu clock.
4. Remove legacy clock initialization.
5. Initialize clocks using DT.
6. Remove all instance of mach/clk.hSigned-off-by: Prashant Gaikwad
[swarren: use to_clk_periph_gate().]
Signed-off-by: Stephen Warren -
Add Tegra30 clock support based on common clock framework.
Signed-off-by: Prashant Gaikwad
[swarren: ensure all OF lookups return valid cookies i.e. an explicit
error pointer or valid pointer not NULL, adapt to renames in earlier
patches, fixed some checkpatch issues.]
Acked-by: Mike Turquette
Signed-off-by: Stephen Warren -
Add Tegra20 clock support based on common clock framework.
Signed-off-by: Prashant Gaikwad
[swarren: s/1GHz/100MHz/ in call to tegra_clk_plle() to fix PCIe,
implemented KBC clock, ensure all OF lookups return valid cookies i.e.
an explicit error pointer or valid pointer not NULL, adapt to renames
in earlier patches, fixed some checkpatch issues.]
Acked-by: Mike Turquette
Signed-off-by: Stephen Warren -
Add Tegra specific clocks, pll, pll_out, peripheral, frac_divider, super.
Signed-off-by: Prashant Gaikwad
[swarren: alloc sizeof(*foo) not sizeof(struct foo), add comments re:
storing pointers to stack variables, make a timeout loop more idiomatic,
use _clk_pll_disable() not clk_disable_pll() from _program_pll() to
avoid redundant lock operations, unified tegra_clk_periph() and
tegra_clk_periph_nodiv(), unified tegra_clk_pll{,e}, rename all clock
registration functions so they don't have the same name as the clock
structs, return -EINVAL from clk_plle_enable when matching table rate
not found, pass ops to _tegra_clk_register_pll rather than a bool.]
Acked-by: Mike Turquette
Signed-off-by: Stephen Warren