12 Aug, 2013
1 commit
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The 'len' variable was declared an unsigned and then checked for less
than 0, which results in warnings on some compilers. Since len is
assigned an int, make it an int.Signed-off-by: Christoffer Dall
27 Jun, 2013
1 commit
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Admitedly, reading a MMIO register to load PC is very weird.
Writing PC to a MMIO register is probably even worse. But
the architecture doesn't forbid any of these, and injecting
a Prefetch Abort is the wrong thing to do anyway.Remove this check altogether, and let the adventurous guest
wander into LaLaLand if they feel compelled to do so.Reported-by: Catalin Marinas
Acked-by: Catalin Marinas
Signed-off-by: Marc Zyngier
Signed-off-by: Christoffer Dall
07 Mar, 2013
11 commits
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Instead of hardcoding the maximum MMIO access to be 4 bytes,
compare it to sizeof(unsigned long), which will do the
right thing on both 32 and 64bit systems.Same thing for sign extention.
Signed-off-by: Marc Zyngier
Signed-off-by: Christoffer Dall -
Signed-off-by: Marc Zyngier
Signed-off-by: Christoffer Dall -
Signed-off-by: Marc Zyngier
Signed-off-by: Christoffer Dall -
Signed-off-by: Marc Zyngier
Signed-off-by: Christoffer Dall -
Bit 8 is cache maintenance, bit 9 is external abort.
Signed-off-by: Marc Zyngier
Signed-off-by: Christoffer Dall -
Signed-off-by: Marc Zyngier
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Signed-off-by: Marc Zyngier
Signed-off-by: Christoffer Dall -
Signed-off-by: Marc Zyngier
Signed-off-by: Christoffer Dall -
Signed-off-by: Marc Zyngier
Signed-off-by: Christoffer Dall -
Instead of directly accessing the fault registers, use proper accessors
so the core code can be shared.Signed-off-by: Marc Zyngier
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On 32bit ARM, unsigned long is guaranteed to be a 32bit quantity.
On 64bit ARM, it is a 64bit quantity.In order to be able to share code between the two architectures,
convert the registers to be unsigned long, so the core code can
be oblivious of the change.Signed-off-by: Marc Zyngier
12 Feb, 2013
1 commit
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Wire the basic framework code for VGIC support and the initial in-kernel
MMIO support code for the VGIC, used for the distributor emulation.Reviewed-by: Will Deacon
Signed-off-by: Christoffer Dall
Signed-off-by: Marc Zyngier
24 Jan, 2013
1 commit
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When the guest accesses I/O memory this will create data abort
exceptions and they are handled by decoding the HSR information
(physical address, read/write, length, register) and forwarding reads
and writes to QEMU which performs the device emulation.Certain classes of load/store operations do not support the syndrome
information provided in the HSR. We don't support decoding these (patches
are available elsewhere), so we report an error to user space in this case.This requires changing the general flow somewhat since new calls to run
the VCPU must check if there's a pending MMIO load and perform the write
after userspace has made the data available.Reviewed-by: Will Deacon
Reviewed-by: Marcelo Tosatti
Signed-off-by: Rusty Russell
Signed-off-by: Marc Zyngier
Signed-off-by: Christoffer Dall
