Doug / smarc-fsl-linux-kernel

03 May, 2010

1 commit

30 Mar, 2010

1 commit

  • 5a0e3ad6a   include cleanup: Update gfp.h and slab.h includes to prepare for breaking implic… ... Browse Code »

    …it slab.h inclusion from percpu.h

    percpu.h is included by sched.h and module.h and thus ends up being
    included when building most .c files. percpu.h includes slab.h which
    in turn includes gfp.h making everything defined by the two files
    universally available and complicating inclusion dependencies.

    percpu.h -> slab.h dependency is about to be removed. Prepare for
    this change by updating users of gfp and slab facilities include those
    headers directly instead of assuming availability. As this conversion
    needs to touch large number of source files, the following script is
    used as the basis of conversion.

    http://userweb.kernel.org/~tj/misc/slabh-sweep.py

    The script does the followings.

    * Scan files for gfp and slab usages and update includes such that
    only the necessary includes are there. ie. if only gfp is used,
    gfp.h, if slab is used, slab.h.

    * When the script inserts a new include, it looks at the include
    blocks and try to put the new include such that its order conforms
    to its surrounding. It's put in the include block which contains
    core kernel includes, in the same order that the rest are ordered -
    alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
    doesn't seem to be any matching order.

    * If the script can't find a place to put a new include (mostly
    because the file doesn't have fitting include block), it prints out
    an error message indicating which .h file needs to be added to the
    file.

    The conversion was done in the following steps.

    1. The initial automatic conversion of all .c files updated slightly
    over 4000 files, deleting around 700 includes and adding ~480 gfp.h
    and ~3000 slab.h inclusions. The script emitted errors for ~400
    files.

    2. Each error was manually checked. Some didn't need the inclusion,
    some needed manual addition while adding it to implementation .h or
    embedding .c file was more appropriate for others. This step added
    inclusions to around 150 files.

    3. The script was run again and the output was compared to the edits
    from #2 to make sure no file was left behind.

    4. Several build tests were done and a couple of problems were fixed.
    e.g. lib/decompress_*.c used malloc/free() wrappers around slab
    APIs requiring slab.h to be added manually.

    5. The script was run on all .h files but without automatically
    editing them as sprinkling gfp.h and slab.h inclusions around .h
    files could easily lead to inclusion dependency hell. Most gfp.h
    inclusion directives were ignored as stuff from gfp.h was usually
    wildly available and often used in preprocessor macros. Each
    slab.h inclusion directive was examined and added manually as
    necessary.

    6. percpu.h was updated not to include slab.h.

    7. Build test were done on the following configurations and failures
    were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
    distributed build env didn't work with gcov compiles) and a few
    more options had to be turned off depending on archs to make things
    build (like ipr on powerpc/64 which failed due to missing writeq).

    * x86 and x86_64 UP and SMP allmodconfig and a custom test config.
    * powerpc and powerpc64 SMP allmodconfig
    * sparc and sparc64 SMP allmodconfig
    * ia64 SMP allmodconfig
    * s390 SMP allmodconfig
    * alpha SMP allmodconfig
    * um on x86_64 SMP allmodconfig

    8. percpu.h modifications were reverted so that it could be applied as
    a separate patch and serve as bisection point.

    Given the fact that I had only a couple of failures from tests on step
    6, I'm fairly confident about the coverage of this conversion patch.
    If there is a breakage, it's likely to be something in one of the arch
    headers which should be easily discoverable easily on most builds of
    the specific arch.

    Signed-off-by: Tejun Heo <tj@kernel.org>
    Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
    Cc: Ingo Molnar <mingo@redhat.com>
    Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>

    Tejun Heo
     

13 Mar, 2010

1 commit

  • 32cbd7dfc   crypto: aesni-intel - Fix CTR optimization build failure with gas 2.16.1 ... Browse Code »

    Andrew Morton reported that AES-NI CTR optimization failed to compile
    with gas 2.16.1, the error message is as follow:

    arch/x86/crypto/aesni-intel_asm.S: Assembler messages:
    arch/x86/crypto/aesni-intel_asm.S:752: Error: suffix or operands invalid for `movq'
    arch/x86/crypto/aesni-intel_asm.S:753: Error: suffix or operands invalid for `movq'

    To fix this, a gas macro is defined to assemble movq with 64bit
    general purpose registers and XMM registers. The macro will generate
    the raw .byte sequence for needed instructions.

    Reported-by: Andrew Morton
    Signed-off-by: Huang Ying
    Signed-off-by: Herbert Xu

    Huang Ying
     

10 Mar, 2010

1 commit

  • 12387a46b   crypto: aesni-intel - Add AES-NI accelerated CTR mode ... Browse Code »

    To take advantage of the hardware pipeline implementation of AES-NI
    instructions. CTR mode cryption is implemented in ASM to schedule
    multiple AES-NI instructions one after another. This way, some latency
    of AES-NI instruction can be eliminated.

    Performance testing based on dm-crypt should 50% reduction of
    ecryption/decryption time.

    Signed-off-by: Huang Ying
    Signed-off-by: Herbert Xu

    Huang Ying
     

09 Feb, 2010

1 commit

  • 3ad2f3fbb   tree-wide: Assorted spelling fixes ... Browse Code »

    In particular, several occurances of funny versions of 'success',
    'unknown', 'therefore', 'acknowledge', 'argument', 'achieve', 'address',
    'beginning', 'desirable', 'separate' and 'necessary' are fixed.

    Signed-off-by: Daniel Mack
    Cc: Joe Perches
    Cc: Junio C Hamano
    Signed-off-by: Jiri Kosina

    Daniel Mack
     

01 Dec, 2009

1 commit

23 Nov, 2009

3 commits

03 Nov, 2009

2 commits

  • 01dd95827   crypto: ghash-intel - Fix irq_fpu_usable usage ... Browse Code »

    When renaming kernel_fpu_using to irq_fpu_usable, the semantics of the
    function is changed too, from mesuring whether kernel is using FPU,
    that is, the FPU is NOT available, to measuring whether FPU is usable,
    that is, the FPU is available.

    But the usage of irq_fpu_usable in ghash-clmulni-intel_glue.c is not
    changed accordingly. This patch fixes this.

    Signed-off-by: Huang Ying
    Signed-off-by: Herbert Xu

    Huang Ying
     
  • 3b0d65969   crypto: ghash-intel - Add PSHUFB macros ... Browse Code »

    Add PSHUFB macros instead of repeating byte sequences, suggested
    by Ingo.

    Signed-off-by: Herbert Xu
    Acked-by: Ingo Molnar

    Herbert Xu
     

02 Nov, 2009

1 commit

20 Oct, 2009

1 commit

  • 13b79b971   crypto: aesni-intel - Fix irq_fpu_usable usage ... Browse Code »

    When renaming kernel_fpu_using to irq_fpu_usable, the semantics of the
    function is changed too, from mesuring whether kernel is using FPU,
    that is, the FPU is NOT available, to measuring whether FPU is usable,
    that is, the FPU is available.

    But the usage of irq_fpu_usable in aesni-intel_glue.c is not changed
    accordingly. This patch fixes this.

    Signed-off-by: Huang Ying
    Signed-off-by: Herbert Xu

    Huang Ying
     

19 Oct, 2009

1 commit

  • 0e1227d35   crypto: ghash - Add PCLMULQDQ accelerated implementation ... Browse Code »

    PCLMULQDQ is used to accelerate the most time-consuming part of GHASH,
    carry-less multiplication. More information about PCLMULQDQ can be
    found at:

    http://software.intel.com/en-us/articles/carry-less-multiplication-and-its-usage-for-computing-the-gcm-mode/

    Because PCLMULQDQ changes XMM state, its usage must be enclosed with
    kernel_fpu_begin/end, which can be used only in process context, the
    acceleration is implemented as crypto_ahash. That is, request in soft
    IRQ context will be defered to the cryptd kernel thread.

    Signed-off-by: Huang Ying
    Signed-off-by: Herbert Xu

    Huang Ying
     

14 Sep, 2009

1 commit

  • c7208de30   Merge branch 'x86-cpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip ... Browse Code »

    * 'x86-cpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: (22 commits)
    x86: Fix code patching for paravirt-alternatives on 486
    x86, msr: change msr-reg.o to obj-y, and export its symbols
    x86: Use hard_smp_processor_id() to get apic id for AMD K8 cpus
    x86, sched: Workaround broken sched domain creation for AMD Magny-Cours
    x86, mcheck: Use correct cpumask for shared bank4
    x86, cacheinfo: Fixup L3 cache information for AMD multi-node processors
    x86: Fix CPU llc_shared_map information for AMD Magny-Cours
    x86, msr: Fix msr-reg.S compilation with gas 2.16.1, on 32-bit too
    x86: Move kernel_fpu_using to irq_fpu_usable in asm/i387.h
    x86, msr: fix msr-reg.S compilation with gas 2.16.1
    x86, msr: Export the register-setting MSR functions via /dev/*/msr
    x86, msr: Create _on_cpu helpers for {rw,wr}msr_safe_regs()
    x86, msr: Have the _safe MSR functions return -EIO, not -EFAULT
    x86, msr: CFI annotations, cleanups for msr-reg.S
    x86, asm: Make _ASM_EXTABLE() usable from assembly code
    x86, asm: Add 32-bit versions of the combined CFI macros
    x86, AMD: Disable wrongly set X86_FEATURE_LAHF_LM CPUID bit
    x86, msr: Rewrite AMD rd/wrmsr variants
    x86, msr: Add rd/wrmsr interfaces with preset registers
    x86: add specific support for Intel Atom architecture
    ...

    Linus Torvalds
     

02 Sep, 2009

1 commit

  • ae4b688db   x86: Move kernel_fpu_using to irq_fpu_usable in asm/i387.h ... Browse Code »

    This function measures whether the FPU/SSE state can be touched in
    interrupt context. If the interrupted code is in user space or has no
    valid FPU/SSE context (CR0.TS == 1), FPU/SSE state can be used in IRQ
    or soft_irq context too.

    This is used by AES-NI accelerated AES implementation and PCLMULQDQ
    accelerated GHASH implementation.

    v3:
    - Renamed to irq_fpu_usable to reflect the purpose of the function.

    v2:
    - Renamed to irq_is_fpu_using to reflect the real situation.

    Signed-off-by: Huang Ying
    CC: H. Peter Anvin
    Signed-off-by: H. Peter Anvin

    Huang Ying
     

24 Jun, 2009

1 commit

  • c9944881a   crypto: aes-ni - Don't print message with KERN_ERR on old system ... Browse Code »

    When the aes-intel module is loaded on a system that does not have the
    AES instructions, it prints

    Intel AES-NI instructions are not detected.

    at level KERN_ERR. Since aes-intel is aliased to "aes" it will be tried
    whenever anything uses AES and spam the console. This doesn't match
    existing practice for how to handle "no hardware" when initializing a
    module, so downgrade the message to KERN_INFO.

    Signed-off-by: Roland Dreier
    Signed-off-by: Herbert Xu

    Roland Dreier
     

18 Jun, 2009

3 commits

02 Jun, 2009

2 commits

  • 2cf4ac8be   crypto: aes-ni - Add support for more modes ... Browse Code »

    Because kernel_fpu_begin() and kernel_fpu_end() operations are too
    slow, the performance gain of general mode implementation + aes-aesni
    is almost all compensated.

    The AES-NI support for more modes are implemented as follow:

    - Add a new AES algorithm implementation named __aes-aesni without
    kernel_fpu_begin/end()

    - Use fpu((AES)) to provide kenrel_fpu_begin/end() invoking

    - Add (AES) ablkcipher, which uses cryptd(fpu((AES))) to
    defer cryption to cryptd context in soft_irq context.

    Now the ctr, lrw, pcbc and xts support are added.

    Performance testing based on dm-crypt shows that cryption time can be
    reduced to 50% of general mode implementation + aes-aesni implementation.

    Signed-off-by: Huang Ying
    Signed-off-by: Herbert Xu

    Huang Ying
     
  • 150c7e855   crypto: fpu - Add template for blkcipher touching FPU ... Browse Code »

    Blkcipher touching FPU need to be enclosed by kernel_fpu_begin() and
    kernel_fpu_end(). If they are invoked in cipher algorithm
    implementation, they will be invoked for each block, so that
    performance will be hurt, because they are "slow" operations. This
    patch implements "fpu" template, which makes these operations to be
    invoked for each request.

    Signed-off-by: Huang Ying
    Signed-off-by: Herbert Xu

    Huang Ying
     

18 Feb, 2009

3 commits

  • 54b6a1bd5   crypto: aes-ni - Add support to Intel AES-NI instructions for x86_64 platform ... Browse Code »

    Intel AES-NI is a new set of Single Instruction Multiple Data (SIMD)
    instructions that are going to be introduced in the next generation of
    Intel processor, as of 2009. These instructions enable fast and secure
    data encryption and decryption, using the Advanced Encryption Standard
    (AES), defined by FIPS Publication number 197. The architecture
    introduces six instructions that offer full hardware support for
    AES. Four of them support high performance data encryption and
    decryption, and the other two instructions support the AES key
    expansion procedure.

    The white paper can be downloaded from:

    http://softwarecommunity.intel.com/isn/downloads/intelavx/AES-Instructions-Set_WP.pdf

    AES may be used in soft_irq context, but MMX/SSE context can not be
    touched safely in soft_irq context. So in_interrupt() is checked, if
    in IRQ or soft_irq context, the general x86_64 implementation are used
    instead.

    Signed-off-by: Huang Ying
    Signed-off-by: Herbert Xu

    Huang Ying
     
  • 07bf44f86   crypto: aes - Export x86 AES encrypt/decrypt functions ... Browse Code »

    Intel AES-NI AES acceleration instructions touch XMM state, to use
    that in soft_irq context, general x86 AES implementation is used as
    fallback. The first parameter is changed from struct crypto_tfm * to
    struct crypto_aes_ctx * to make it easier to deal with 16 bytes
    alignment requirement of AES-NI implementation.

    Signed-off-by: Huang Ying
    Signed-off-by: Herbert Xu

    Huang Ying
     
  • 109568e11   crypto: aes - Move key_length in struct crypto_aes_ctx to be the last field ... Browse Code »

    The Intel AES-NI AES acceleration instructions need key_enc, key_dec
    in struct crypto_aes_ctx to be 16 byte aligned, it make this easier to
    move key_length to be the last one.

    Signed-off-by: Huang Ying
    Signed-off-by: Herbert Xu

    Huang Ying
     

25 Dec, 2008

2 commits

29 Aug, 2008

1 commit

  • 8cb51ba8e   crypto: crc32c - Use Intel CRC32 instruction ... Browse Code »

    From NHM processor onward, Intel processors can support hardware accelerated
    CRC32c algorithm with the new CRC32 instruction in SSE 4.2 instruction set.
    The patch detects the availability of the feature, and chooses the most proper
    way to calculate CRC32c checksum.
    Byte code instructions are used for compiler compatibility.
    No MMX / XMM registers is involved in the implementation.

    Signed-off-by: Austin Zhang
    Signed-off-by: Kent Liu
    Signed-off-by: Herbert Xu

    Austin Zhang
     

21 Apr, 2008

1 commit

14 Jan, 2008

1 commit

11 Jan, 2008

6 commits

24 Oct, 2007

1 commit

11 Oct, 2007

2 commits