05 May, 2010
3 commits
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This is a trivial 4xx plaform that uses the new simple bsp from
Josh and is handy to use in simulators such as ISS or even Mambo
who don't properly implement most of the actual devices in the
SoC but really only the core.Signed-off-by: Torez Smith
Signed-off-by: Dave Kleikamp
Signed-off-by: Josh Boyer -
The 47x core's MCSR varies from 44x, so it needs it's own machine check
handler.Signed-off-by: Dave Kleikamp
Signed-off-by: Josh Boyer -
This patch adds the base support for the 476 processor. The code was
primarily written by Ben Herrenschmidt and Torez Smith, but I've been
maintaining it for a while.The goal is to have a single binary that will run on 44x and 47x, but
we still have some details to work out. The biggest is that the L1 cache
line size differs on the two platforms, but it's currently a compile-time
option.Signed-off-by: Benjamin Herrenschmidt
Signed-off-by: Torez Smith
Signed-off-by: Dave Kleikamp
Signed-off-by: Josh Boyer
05 Mar, 2010
1 commit
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This implements perf_event support for the Freescale embedded performance
monitor, based on the existing perf_event.c that supports server/classic
chips.Some limitations:
- Performance monitor interrupts are regular EE interrupts, and thus you
can't profile places with interrupts disabled. We may want to implement
soft IRQ-disabling, with perfmon interrupts exempted and treated as NMIs.
- When trying to schedule multiple event groups at once, and using
restricted events, situations could arise where scheduling fails even
though it would be possible. Consider three groups, each with two events.
One group has restricted events, the others don't. The two non-restricted
groups are scheduled, then one is removed, which happens to occupy the two
counters that can't do restricted events. The remaining non-restricted
group will not be moved to the non-restricted-capable counters to make
room if the restricted group tries to be scheduled.Signed-off-by: Scott Wood
Acked-by: Paul Mackerras
Signed-off-by: Kumar Gala
13 Dec, 2009
1 commit
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This patch extends the cputable entry of the 750CL to also match
the 750CL-based "Broadway" cpu found on the Nintendo Wii.As of this patch, the following "Broadway" design revision levels have
been seen in the wild:
- DD1.2 (87102)
- DD2.0 (87200)Signed-off-by: Albert Herranz
Acked-by: Benjamin Herrenschmidt
Signed-off-by: Grant Likely
14 Oct, 2009
1 commit
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Here's a patch that adds the ppc750 CL cpu as supported by oprofile.
Signed-off-by: Dragos Tatulea
Signed-off-by: Benjamin Herrenschmidt
28 Aug, 2009
1 commit
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Move the default cpu entry table for CONFIG_PPC_BOOK3E_64 to the
very end since we will probably want to support both 32-bit and
64-bit kernels for some processors that are higher up in the list.Signed-off-by: Kumar Gala
Signed-off-by: Benjamin Herrenschmidt
20 Aug, 2009
2 commits
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Signed-off-by: Stefan Roese
Signed-off-by: Josh Boyer
Signed-off-by: Benjamin Herrenschmidt -
This contains all the bits that didn't fit in previous patches :-) This
includes the actual exception handlers assembly, the changes to the
kernel entry, other misc bits and wiring it all up in Kconfig.Signed-off-by: Benjamin Herrenschmidt
21 May, 2009
1 commit
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This adds the PowerPC 2.06 tlbie mnemonics and keeps backwards
compatibilty for CPUs before 2.06.Only useful for bare metal systems.
Signed-off-by: Milton Miller
Signed-off-by: Michael Neuling
Signed-off-by: Benjamin Herrenschmidt
15 May, 2009
1 commit
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My previous pach for fixing the oprofile CPU type got somewhat mismerged
(by my fault) when it collided with another related patch. This should
finally (fingers crossed) fix the whole thing.We make sure we keep the -old- oprofile type and CPU type whenever
one of them was specified in the first pass through the function.Signed-off-by: Benjamin Herrenschmidt
01 May, 2009
2 commits
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commit 2657dd4e301d4841ed67a4fac7d145ad8f3e1b28 introduced a
bug where we would now always override the "real" oprofile CPU
type with the "compatible" one provided by a pseudo-PVR in the
device-tree which is incorrect and breaks oprofile on all current
configs since the "compatible" ones aren't yet recognized.This fixes it.
Signed-off-by: Benjamin Herrenschmidt
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Oprofile is changing the naming it is using for the compatibility modes.
Instead of having compat-power, oprofile will go to family naming
convention and use ibm-compat-v. Currently only ibm-compat-v1 will
be defined.
The notion of compatibility events just started with POWER6. So there is
no way that any other tool could exist that is using these
oprofile_cpu_type strings we want to change.Signed-off-by: Mike Wolf
Signed-off-by: Benjamin Herrenschmidt
23 Apr, 2009
1 commit
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This reverts commit e9965577406a2148ade97b5e0ce7c448b4ba4ef6. Our HW
guys were able to fix this so it never sees the light of day.Signed-off-by: Kumar Gala
07 Apr, 2009
1 commit
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During the ISA 2.06 development the opcode for tlbilx changed and some
early implementations used to old opcode. Add support for a MMU_FTR
fixup to deal with this.Signed-off-by: Kumar Gala
24 Mar, 2009
1 commit
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Complete workaround for DTLB errata in e300c2/c3/c4 processors.
Due to the bug, the hardware-implemented LRU algorythm always goes to way
1 of the TLB. This fix implements the proposed software workaround in
form of a LRW table for chosing the TLB-way.Based on patch from David Jander
Signed-off-by: Kumar Gala
Signed-off-by: Benjamin Herrenschmidt
11 Mar, 2009
3 commits
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This patch enables oprofile for all 3 FX variants and GX variant of the
750 processor.Signed-off-by: Octavian Purdila
Signed-off-by: Benjamin Herrenschmidt -
When identify_cpu() is called a second time with a logical PVR, it
only copies a subset of the cpu_spec fields so as to avoid overwriting
the performance monitor fields that were initialized based on the
real PVR.However some of the other, non performance monitor related fields are
also not copied:
* pvr_mask
* pvr_value
* mmu_features
* machine_checkThe fact that pvr_mask is not copied can result in show_cpuinfo()
showing the cpu as "unknown", if we override an unknown PVR with a
logical one - as reported by Shaggy.So change the logic to copy all fields, and then put back the PMC
related ones in the case that we're overwriting a real PVR with a
logical one.Signed-off-by: Michael Ellerman
Acked-by: Dave Kleikamp
Signed-off-by: Benjamin Herrenschmidt -
The for-loop body of identify_cpu() has gotten a little big, so move the
loop body logic into a separate function. No other changes.Signed-off-by: Michael Ellerman
Acked-by: Dave Kleikamp
Signed-off-by: Benjamin Herrenschmidt
09 Mar, 2009
1 commit
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The e500mc core supports the new tlbilx instructions that do core
local invalidates and also provide us the ability to take down
all TLB entries matching a given PID.Signed-off-by: Kumar Gala
15 Feb, 2009
1 commit
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This patch contains initial framework for the AMCC Redwood board.
Signed-off-by: Madhulika Madishetty
Signed-off-by: Tirumala Marri
Signed-off-by: Feng Kan
Signed-off-by: Vidhyananth Venkatasamy
Signed-off-by: Preetesh Parekh
Acked-by: Loc Ho
Acked-by: Feng Kan
Signed-off-by: Josh Boyer
29 Jan, 2009
1 commit
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We currently have a few variants of fsl-booke processors (e500v1, e500v2,
e500mc, and e200). They all have minor differences that we had previously
been handling via ifdefs.To move towards having this support the following changes have been made:
* PID1, PID2 only exist on e500v1 & e500v2 and should not be accessed on
e500mc or e200. We use MMUCFG[NPIDS] to determine which case we are
since we only touch PID1/2 in extremely early init code.* Not all IVORs exist on all the processors so introduce cpu_setup
functions for each variant to setup the proper IVORs that are either
unique or exist but have some variations between the processorsSigned-off-by: Kumar Gala
21 Dec, 2008
2 commits
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We're soon running out of CPU features and I need to add some new
ones for various MMU related bits, so this patch separates the MMU
features from the CPU features. I moved over the 32-bit MMU related
ones, added base features for MMU type families, but didn't move
over any 64-bit only feature yet.Signed-off-by: Benjamin Herrenschmidt
Acked-by: Kumar Gala
Signed-off-by: Paul Mackerras -
This adds supports to the "extended" DCR addressing via the indirect
mfdcrx/mtdcrx instructions supported by some 4xx cores (440H6 and
later).I enabled the feature for now only on AMCC 460 chips.
Signed-off-by: Benjamin Herrenschmidt
Acked-by: Josh Boyer
Acked-by: Kumar Gala
Signed-off-by: Paul Mackerras
06 Dec, 2008
1 commit
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The 440x5 core in the Virtex5 uses the 440A type machine check
(ie, they have MCSRR0/MCSRR1). They thus need to call the
appropriate fixup function to hook the right variant of the
exception.Without this, all machine checks become fatal due to loss
of context when entering the exception handler.Signed-off-by: Grant Likely
Signed-off-by: Josh Boyer
17 Oct, 2008
1 commit
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This adds the AMCC PowerPC 405EZ chip to the cputable
Signed-off-by: Josh Boyer
20 Aug, 2008
1 commit
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The file arch/powerpc/kernel/sysfs.c is currently only compiled for
64-bit kernels. It contain code to register CPU sysdevs in sysfs and
add various properties such as cache topology and raw access by root
to performance monitor counters (PMCs). A lot of that can be re-used
as is on 32-bits.This makes the file be built for both, with appropriate ifdef'ing
for the few bits that are really 64-bit specific, and adds some
support for the raw PMCs for 75x and 74xx processors.Signed-off-by: Benjamin Herrenschmidt
Signed-off-by: Paul Mackerras
26 Jul, 2008
1 commit
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Commit 9115d13453dee22473a1e8cacc90a8d64a9c4bc9 ("powerpc: Enable
AT_BASE_PLATFORM aux vector") broke boot on 32-bit powerpc systems; we
have to use PTRRELOC to initialize powerpc_base_platform this early in
boot.Bug reported by Jon Smirl.
Signed-off-by: Nathan Lynch
Signed-off-by: Benjamin Herrenschmidt
25 Jul, 2008
1 commit
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Stash the first platform string matched by identify_cpu() in
powerpc_base_platform, and supply that to the ELF loader for the value
of AT_BASE_PLATFORM.Signed-off-by: Nathan Lynch
Signed-off-by: Benjamin Herrenschmidt
22 Jul, 2008
1 commit
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While running on a system with new hardware and a kernel where the
cpu_specs[] table does not recognize the new hardware, the identify_cpu()
routine will select the default case as it searches through cpu_specs[]
in an attempt to match the real PVR. Once the default case is selected,
non of the oprofile counters and/or fields have been set up or defined.When identify_cpu() is called once more with the logical PVR, some of
the cpu specific fields are replaced with the exception of the oprofile
related ones. However, in the case where we have actually taken the
default case while searching for the real PVR, we need to tell
oprofile that we are now running in compatibility mode so it can pick up
the correct counters. We do this by setting the oprofile_cpu_type field
to be that taken from the cpu_specs[] for the cpu we are now emulating.This change will detect that we are now altering the real PVR and determine
if we also need to update the oprofile_cpu_type field.Signed-off-by: Torez Smith
Signed-off-by: Benjamin Herrenschmidt
15 Jul, 2008
1 commit
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Background from Maynard Johnson:
As of POWER6, a set of 32 common events is defined that must be
supported on all future POWER processors. The main impetus for this
compat set is the need to support partition migration, especially from
processor P(n) to processor P(n+1), where performance software that's
running in the new partition may not be knowledgeable about processor
P(n+1). If a performance tool determines it does not support the
physical processor, but is told (via the
PPC_FEATURE_PSERIES_PERFMON_COMPAT bit) that the processor supports
the notion of the PMU compat set, then the performance tool can
surface just those events to the user of the tool.PPC_FEATURE_PSERIES_PERFMON_COMPAT indicates that the PMU supports at
least this basic subset of events which is compatible across POWER
processor lines.Signed-off-by: Nathan Lynch
Signed-off-by: Benjamin Herrenschmidt
04 Jul, 2008
1 commit
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Updates the cputable to include the 440 processor found in the
Xilinx Virtex5 FXT FPGA.Signed-off-by: John Linn
Signed-off-by: Grant Likely
01 Jul, 2008
3 commits
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The logic to patch CPU feature sections lives in cputable.c, but these days
it's used for CPU features as well as firmware features. Move it into
it's own file for neatness and as preparation for some additions.While we're moving the code, we pull the loop body logic into a separate
routine, and remove a comment which doesn't apply anymore.Signed-off-by: Michael Ellerman
Acked-by: Kumar Gala
Signed-off-by: Paul Mackerras -
A bunch of code has hard-coded the value for a "nop" instruction, it
would be nice to have a #define for it.Signed-off-by: Michael Ellerman
Acked-by: Kumar Gala
Signed-off-by: Paul Mackerras -
Add an entry for Power7 architected mode and add "(raw)" to Power7 raw
mode to distinguish it more clearly.Signed-off-by: Joel Schopp
Signed-off-by: Paul Mackerras
30 Jun, 2008
2 commits
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Add a cputable entry for the POWER7 processor.
Also tell firmware that we know about POWER7.
Signed-off-by: Michael Neuling
Signed-off-by: Joel Schopp
Signed-off-by: Paul Mackerras
26 Jun, 2008
1 commit
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The e500 core enter DOZE/NAP power-saving modes when the core go to
cpu_idle routine.The power management default running mode is DOZE, If the user
echo 1 > /proc/sys/kernel/powersave-nap
the system will change to NAP running mode.
Signed-off-by: Dave Liu
Signed-off-by: Kumar Gala
19 Jun, 2008
1 commit
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The new e500mc core from Freescale is based on the e500v2 but with the
following changes:* Supports only the Enhanced Debug Architecture (DSRR0/1, etc)
* Floating Point
* No SPE
* Supports lwsync
* Doorbell Exceptions
* Hypervisor
* Cache line size is now 64-bytes (e500v1/v2 have a 32-byte cache line)Signed-off-by: Kumar Gala
11 Jun, 2008
1 commit
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This reverts commit acb0142bf01c0ebe18f09e37814451ee6a873e27.
AMCC has indicated that the PPC 460GT does have FPU support. This
revert enables the FPU for those chips again.Signed-off-by: Josh Boyer