board.h
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/*
* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
* Copyright (c) 2017, Embedian, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#if !defined(__BOARD_H__)
#define __BOARD_H__
#include "pin_mux.h"
#include "rdc.h"
#include "rdc_defs_imx7d.h"
#include "ccm_imx7d.h"
#include "clock_freq.h"
/* The board name */
#define BOARD_NAME "IMX7_SMARC_M4"
#define BOARD_DOMAIN_ID (1)
/* ADC information for this board */
#define BOARD_ADC_RDC_PDAP rdcPdapAdc1
#define BOARD_ADC_CCM_CCGR ccmCcgrGateAdc
#define BOARD_ADC_BASEADDR ADC1
#define BOARD_ADC_IRQ_NUM ADC1_IRQn
#define BOARD_ADC_HANDLER ADC1_Handler
#define BOARD_ADC_INPUT_CHANNEL (3)
/* WDOG information for this board */
#define BOARD_WDOG_RDC_PDAP rdcPdapWdog3
#define BOARD_WDOG_CCM_ROOT ccmRootWdog
#define BOARD_WDOG_CCM_CCGR ccmCcgrGateWdog3
#define BOARD_WDOG_BASEADDR WDOG3
#define BOARD_WDOG_IRQ_NUM WDOG3_IRQn
#define BOARD_WDOG_HANDLER WDOG3_Handler
/* SEMA4 information for this board */
#define BOARD_SEMA4_RDC_PDAP rdcPdapSemaphoreHs
#define BOARD_SEMA4_CCM_CCGR ccmCcgrGateSemaHs
#define BOARD_SEMA4_BASEADDR SEMA4
#define BOARD_SEMA4_IRQ_NUM SEMA4_HS_M4_IRQn
#define BOARD_SEMA4_HANDLER SEMA4_HS_M4_Handler
/* GPT instance A information for this board */
#define BOARD_GPTA_RDC_PDAP rdcPdapGpt3
#define BOARD_GPTA_CCM_ROOT ccmRootGpt3
#define BOARD_GPTA_CCM_CCGR ccmCcgrGateGpt3
#define BOARD_GPTA_BASEADDR GPT3
#define BOARD_GPTA_IRQ_NUM GPT3_IRQn
#define BOARD_GPTA_HANDLER GPT3_Handler
/* GPT instance B information for this board */
#define BOARD_GPTB_RDC_PDAP rdcPdapGpt4
#define BOARD_GPTB_CCM_ROOT ccmRootGpt4
#define BOARD_GPTB_CCM_CCGR ccmCcgrGateGpt4
#define BOARD_GPTB_BASEADDR GPT4
#define BOARD_GPTB_IRQ_NUM GPT4_IRQn
#define BOARD_GPTB_HANDLER GPT4_Handler
/* GPIO information for this board */
#define BOARD_GPIO_KEY_CCM_CCGR ccmCcgrGateGpio2
#define BOARD_GPIO_LED_RDC_PDAP rdcPdapGpio1
#define BOARD_GPIO_LED_CONFIG (&gpioLed)
#define BOARD_GPIO_KEY_RDC_PDAP rdcPdapGpio2
#define BOARD_GPIO_KEY_CONFIG (&gpioKeyFunc1)
#define BOARD_GPIO_KEY_IRQ_NUM GPIO5_INT15_0_IRQn
#define BOARD_GPIO_KEY_HANDLER GPIO5_INT15_0_Handler
/* Switch 1 (GPIO6)
* Golden Finger BALL NAME GPIO ALT
* P114 EPDC_DATA05 GPIO2_07 5
*/
#define BOARD_GPIO_SWITCH1_RDC_PDAP rdcPdapGpio2
#define BOARD_GPIO_SWITCH1_CONFIG (&gpioSwitch1)
/* LED 1 (GPIO2)
* Golden Finger BALL NAME GPIO ALT
* P110 EPDC_DATA02 GPIO2_02 5
*/
#define BOARD_GPIO_LED1_RDC_PDAP rdcPdapGpio2
#define BOARD_GPIO_LED1_CONFIG (&gpioLed1)
/* Switch 2 (GPIO8)
* Golden Finger BALL NAME GPIO ALT
* P116 EPDC_DATA06 GPIO2_06 5
*/
#define BOARD_GPIO_SWITCH2_RDC_PDAP rdcPdapGpio2
#define BOARD_GPIO_SWITCH2_CONFIG (&gpioSwitch2)
/* LED 2 (GPIO4)
* Golden Finger BALL NAME GPIO ALT
* P112 EPDC_DATA04 GPIO2_04 5
*/
#define BOARD_GPIO_LED2_RDC_PDAP rdcPdapGpio2
#define BOARD_GPIO_LED2_CONFIG (&gpioLed2)
/* SMARC SPI0 ECSPI1 information for flash demo */
#define BOARD_ECSPI_RDC_PDAP rdcPdapEcspi1
#define BOARD_ECSPI_CCM_ROOT ccmRootEcspi1
#define BOARD_ECSPI_CCM_CCGR ccmCcgrGateEcspi1
#define BOARD_ECSPI_CHANNEL ecspiSelectChannel0
#define BOARD_ECSPI_IRQ_NUM eCSPI1_IRQn
#define BOARD_ECSPI_BASEADDR ECSPI1
#define BOARD_ECSPI_HANDLER eCSPI1_Handler
/* ECSPI information for master mode */
#define BOARD_ECSPI_MASTER_RDC_PDAP rdcPdapEcspi2
#define BOARD_ECSPI_MASTER_CCM_ROOT ccmRootEcspi2
#define BOARD_ECSPI_MASTER_CCM_CCGR ccmCcgrGateEcspi2
#define BOARD_ECSPI_MASTER_BASEADDR ECSPI2
#define BOARD_ECSPI_MASTER_CHANNEL ecspiSelectChannel0
#define BOARD_ECSPI_MASTER_IRQ_NUM eCSPI2_IRQn
#define BOARD_ECSPI_MASTER_HANDLER eCSPI2_Handler
/* ECSPI information for slave mode */
#define BOARD_ECSPI_SLAVE_RDC_PDAP rdcPdapEcspi2
#define BOARD_ECSPI_SLAVE_CCM_ROOT ccmRootEcspi2
#define BOARD_ECSPI_SLAVE_CCM_CCGR ccmCcgrGateEcspi2
#define BOARD_ECSPI_SLAVE_BASEADDR ECSPI2
#define BOARD_ECSPI_SLAVE_CHANNEL ecspiSelectChannel0
#define BOARD_ECSPI_SLAVE_IRQ_NUM eCSPI2_IRQn
#define BOARD_ECSPI_SLAVE_HANDLER eCSPI2_Handler
/* Debug UART information for this board */
#define BOARD_DEBUG_UART_RDC_PDAP rdcPdapUart2
#define BOARD_DEBUG_UART_CCM_ROOT ccmRootUart2
#define BOARD_DEBUG_UART_CCM_CCGR ccmCcgrGateUart2
#define BOARD_DEBUG_UART_BASEADDR UART2
#define BOARD_DEBUG_UART_IRQ_NUM UART2_IRQn
#define BOARD_DEBUG_UART_HANDLER UART2_Handler
/* MU information for this board*/
#define BOARD_MU_HANDLER MU_M4_Handler
#define BOARD_MU_IRQ_NUM MU_M4_IRQn
#define BOARD_MU_BASE_ADDR MUB
#define BOARD_MU_CCM_CCGR ccmCcgrGateMu
#define BOARD_MU_RDC_PDAP rdcPdapMuB
/* I2C3 (I2C_LCD) information for this board */
#define BOARD_I2C_RDC_PDAP rdcPdapI2c3
#define BOARD_I2C_CCM_ROOT ccmRootI2c3
#define BOARD_I2C_CCM_CCGR ccmCcgrGateI2c3
#define BOARD_I2C_BASEADDR I2C3
#define BOARD_I2C_IRQ_NUM I2C3_IRQn
#define BOARD_I2C_HANDLER I2C3_Handler
#define BOARD_I2C_FXAS21002_ADDR (0x20)
#define BOARD_I2C_FXOS8700_ADDR (0x1E)
/* FlexCAN information for this board */
#define BOARD_FLEXCAN_RDC_PDAP rdcPdapFlexCan2
#define BOARD_FLEXCAN_CCM_ROOT ccmRootCan2
#define BOARD_FLEXCAN_CCM_CCGR ccmCcgrGateCan2
#define BOARD_FLEXCAN_BASEADDR CAN2
#define BOARD_FLEXCAN_IRQ_NUM FLEXCAN2_IRQn
#define BOARD_FLEXCAN_HANDLER FLEXCAN2_Handler
/* GPC information for this board*/
#define BOARD_GPC_BASEADDR GPC
/* SIM_WAKEUP CG information*/
#define BOARD_SIM_WAKEUP_CCGR ccmCcgrGateSimWakeup
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
void hardware_init(void);
void dbg_uart_init(void);
/* Function to initialize clock base on board configuration. */
void BOARD_ClockInit(void);
void BOARD_RdcInit(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus */
#endif /* __BOARD_H__ */