pin_mux.c
16.4 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*!
** @addtogroup pin_mux_module pin_mux module documentation
** @{
*/
/* MODULE pin_mux. */
#include "device_imx.h"
#include "pin_mux.h"
void configure_flexcan_pins(CAN_Type* base)
{
switch((uint32_t)base)
{
case CAN1_BASE:
// CAN1_TX
IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13 = IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13_MUX_MODE(3);
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13 = IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_PE_MASK |
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_PS(3) |
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_DSE(0) |
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_HYS_MASK;
// CAN1_RX
IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12 = IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12_MUX_MODE(3);
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12 = IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_PE_MASK |
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_PS(3) |
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_DSE(0) |
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_HYS_MASK;
break;
case CAN2_BASE:
// CAN2_TX
IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO15 = IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO15_MUX_MODE(3);
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15 = IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15_PE_MASK |
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15_PS(3) |
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15_DSE(0) |
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15_HYS_MASK;
// CAN2_RX
IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14 = IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14_MUX_MODE(3);
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14 = IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14_PE_MASK |
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14_PS(3) |
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14_DSE(0) |
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14_HYS_MASK;
break;
}
}
void configure_i2c_pins(I2C_Type* base)
{
switch((uint32_t)base)
{
case I2C1_BASE:
// I2C1 (I2C_PM) iomux configuration
IOMUXC_SW_MUX_CTL_PAD_I2C1_SCL = IOMUXC_SW_MUX_CTL_PAD_I2C1_SCL_MUX_MODE(0) |
IOMUXC_SW_MUX_CTL_PAD_I2C1_SCL_SION_MASK;
IOMUXC_SW_MUX_CTL_PAD_I2C1_SDA = IOMUXC_SW_MUX_CTL_PAD_I2C1_SDA_MUX_MODE(0) |
IOMUXC_SW_MUX_CTL_PAD_I2C1_SDA_SION_MASK;
IOMUXC_I2C1_SCL_SELECT_INPUT = IOMUXC_I2C1_SCL_SELECT_INPUT_DAISY(1);
IOMUXC_I2C1_SDA_SELECT_INPUT = IOMUXC_I2C1_SDA_SELECT_INPUT_DAISY(1);
IOMUXC_SW_PAD_CTL_PAD_I2C1_SCL = IOMUXC_SW_PAD_CTL_PAD_I2C1_SCL_PE_MASK |
IOMUXC_SW_PAD_CTL_PAD_I2C1_SCL_PS(3) |
IOMUXC_SW_PAD_CTL_PAD_I2C1_SCL_DSE(0) |
IOMUXC_SW_PAD_CTL_PAD_I2C1_SCL_HYS_MASK;
IOMUXC_SW_PAD_CTL_PAD_I2C1_SDA = IOMUXC_SW_PAD_CTL_PAD_I2C1_SDA_PE_MASK |
IOMUXC_SW_PAD_CTL_PAD_I2C1_SDA_PS(3) |
IOMUXC_SW_PAD_CTL_PAD_I2C1_SDA_DSE(0) |
IOMUXC_SW_PAD_CTL_PAD_I2C1_SDA_HYS_MASK;
break;
case I2C2_BASE:
// I2C2 (I2C_GP) iomux configuration
IOMUXC_SW_MUX_CTL_PAD_I2C2_SCL = IOMUXC_SW_MUX_CTL_PAD_I2C2_SCL_MUX_MODE(0) |
IOMUXC_SW_MUX_CTL_PAD_I2C2_SCL_SION_MASK;
IOMUXC_SW_MUX_CTL_PAD_I2C2_SDA = IOMUXC_SW_MUX_CTL_PAD_I2C2_SDA_MUX_MODE(0) |
IOMUXC_SW_MUX_CTL_PAD_I2C2_SDA_SION_MASK;
IOMUXC_I2C2_SCL_SELECT_INPUT = IOMUXC_I2C2_SCL_SELECT_INPUT_DAISY(1);
IOMUXC_I2C2_SDA_SELECT_INPUT = IOMUXC_I2C2_SDA_SELECT_INPUT_DAISY(1);
IOMUXC_SW_PAD_CTL_PAD_I2C2_SCL = IOMUXC_SW_PAD_CTL_PAD_I2C2_SCL_PE_MASK |
IOMUXC_SW_PAD_CTL_PAD_I2C2_SCL_PS(3) |
IOMUXC_SW_PAD_CTL_PAD_I2C2_SCL_DSE(0) |
IOMUXC_SW_PAD_CTL_PAD_I2C2_SCL_HYS_MASK;
IOMUXC_SW_PAD_CTL_PAD_I2C2_SDA = IOMUXC_SW_PAD_CTL_PAD_I2C2_SDA_PE_MASK |
IOMUXC_SW_PAD_CTL_PAD_I2C2_SDA_PS(3) |
IOMUXC_SW_PAD_CTL_PAD_I2C2_SDA_DSE(0) |
IOMUXC_SW_PAD_CTL_PAD_I2C2_SDA_HYS_MASK;
break;
case I2C3_BASE:
// I2C3 (I2C_LCD) iomux configuration
IOMUXC_SW_MUX_CTL_PAD_I2C3_SCL = IOMUXC_SW_MUX_CTL_PAD_I2C3_SCL_MUX_MODE(0) |
IOMUXC_SW_MUX_CTL_PAD_I2C3_SCL_SION_MASK;
IOMUXC_SW_MUX_CTL_PAD_I2C3_SDA = IOMUXC_SW_MUX_CTL_PAD_I2C3_SDA_MUX_MODE(0) |
IOMUXC_SW_MUX_CTL_PAD_I2C3_SDA_SION_MASK;
IOMUXC_I2C3_SCL_SELECT_INPUT = IOMUXC_I2C3_SCL_SELECT_INPUT_DAISY(2);
IOMUXC_I2C3_SDA_SELECT_INPUT = IOMUXC_I2C3_SDA_SELECT_INPUT_DAISY(2);
IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL = IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL_PE_MASK |
IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL_PS(3) |
IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL_DSE(0) |
IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL_HYS_MASK;
IOMUXC_SW_PAD_CTL_PAD_I2C3_SDA = IOMUXC_SW_PAD_CTL_PAD_I2C3_SDA_PE_MASK |
IOMUXC_SW_PAD_CTL_PAD_I2C3_SDA_PS(3) |
IOMUXC_SW_PAD_CTL_PAD_I2C3_SDA_DSE(0) |
IOMUXC_SW_PAD_CTL_PAD_I2C3_SDA_HYS_MASK;
break;
case I2C4_BASE:
// I2C4 (I2C_CAM) iomux configuration
IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL = IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_MUX_MODE(0) |
IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_SION_MASK;
IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA = IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_MUX_MODE(0) |
IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_SION_MASK;
IOMUXC_I2C4_SCL_SELECT_INPUT = IOMUXC_I2C4_SCL_SELECT_INPUT_DAISY(2);
IOMUXC_I2C4_SDA_SELECT_INPUT = IOMUXC_I2C4_SDA_SELECT_INPUT_DAISY(2);
IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL = IOMUXC_SW_PAD_CTL_PAD_I2C4_SCL_PE_MASK |
IOMUXC_SW_PAD_CTL_PAD_I2C4_SCL_PS(3) |
IOMUXC_SW_PAD_CTL_PAD_I2C4_SCL_DSE(0) |
IOMUXC_SW_PAD_CTL_PAD_I2C4_SCL_HYS_MASK;
IOMUXC_SW_PAD_CTL_PAD_I2C4_SDA = IOMUXC_SW_PAD_CTL_PAD_I2C4_SDA_PE_MASK |
IOMUXC_SW_PAD_CTL_PAD_I2C4_SDA_PS(3) |
IOMUXC_SW_PAD_CTL_PAD_I2C4_SDA_DSE(0) |
IOMUXC_SW_PAD_CTL_PAD_I2C4_SDA_HYS_MASK;
break;
default:
break;
}
}
void configure_uart_pins(UART_Type* base)
{
switch((uint32_t)base)
{
case UART2_BASE:
// UART2 iomux configuration
IOMUXC_SW_MUX_CTL_PAD_UART2_RX_DATA = IOMUXC_SW_MUX_CTL_PAD_UART2_RX_DATA_MUX_MODE(0);
IOMUXC_SW_MUX_CTL_PAD_UART2_TX_DATA = IOMUXC_SW_MUX_CTL_PAD_UART2_TX_DATA_MUX_MODE(0);
IOMUXC_SW_PAD_CTL_PAD_UART2_RX_DATA = IOMUXC_SW_PAD_CTL_PAD_UART2_RX_DATA_PE_MASK |
IOMUXC_SW_PAD_CTL_PAD_UART2_RX_DATA_PS(3) |
IOMUXC_SW_PAD_CTL_PAD_UART2_RX_DATA_HYS_MASK |
IOMUXC_SW_PAD_CTL_PAD_UART2_RX_DATA_DSE(0);
IOMUXC_SW_PAD_CTL_PAD_UART2_TX_DATA = IOMUXC_SW_PAD_CTL_PAD_UART2_TX_DATA_PE_MASK |
IOMUXC_SW_PAD_CTL_PAD_UART2_TX_DATA_PS(3) |
IOMUXC_SW_PAD_CTL_PAD_UART2_RX_DATA_HYS_MASK |
IOMUXC_SW_PAD_CTL_PAD_UART2_TX_DATA_DSE(0);
IOMUXC_UART2_RX_DATA_SELECT_INPUT = IOMUXC_UART2_RX_DATA_SELECT_INPUT_DAISY(2);
break;
case UART3_BASE:
// UART3 iomux configuration
IOMUXC_SW_MUX_CTL_PAD_UART3_RX_DATA = IOMUXC_SW_MUX_CTL_PAD_UART3_RX_DATA_MUX_MODE(0);
IOMUXC_SW_MUX_CTL_PAD_UART3_TX_DATA = IOMUXC_SW_MUX_CTL_PAD_UART3_TX_DATA_MUX_MODE(0);
IOMUXC_SW_PAD_CTL_PAD_UART3_RX_DATA = IOMUXC_SW_PAD_CTL_PAD_UART3_RX_DATA_PE_MASK |
IOMUXC_SW_PAD_CTL_PAD_UART3_RX_DATA_PS(3) |
IOMUXC_SW_PAD_CTL_PAD_UART3_RX_DATA_HYS_MASK |
IOMUXC_SW_PAD_CTL_PAD_UART3_RX_DATA_DSE(0);
IOMUXC_SW_PAD_CTL_PAD_UART3_TX_DATA = IOMUXC_SW_PAD_CTL_PAD_UART3_TX_DATA_PE_MASK |
IOMUXC_SW_PAD_CTL_PAD_UART3_TX_DATA_PS(3) |
IOMUXC_SW_PAD_CTL_PAD_UART3_RX_DATA_HYS_MASK |
IOMUXC_SW_PAD_CTL_PAD_UART3_TX_DATA_DSE(0);
IOMUXC_UART3_RX_DATA_SELECT_INPUT = IOMUXC_UART3_RX_DATA_SELECT_INPUT_DAISY(2);
break;
default:
break;
}
}
void configure_ecspi_pins(ECSPI_Type* base)
{
switch((uint32_t)base)
{
case ECSPI1_BASE:
// ECSPI1 iomux configuration
/* daisy chain selection */
IOMUXC_ECSPI1_MISO_SELECT_INPUT = 1;
/* iomux */
IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK = IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_MUX_MODE(0); /* ECSPI SLK */
IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI = IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_MUX_MODE(0); /* ECSPI MOSI */
IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MISO = IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MISO_MUX_MODE(0); /* ECSPI MISO */
IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SS0 = IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SS0_MUX_MODE(0); /* ECSPI SS0 */
/* pad control */
IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK = IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_PE_MASK |
IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_PS(0) | /* pull down */
IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_DSE(0) |
IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_HYS_MASK;
IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI = IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_DSE(0) |
IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_HYS_MASK;
IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO = IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO_HYS_MASK;
IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0 = IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0_PE_MASK |
IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0_PS(3) | /* pull up */
IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0_DSE(0) |
IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0_HYS_MASK;
break;
case ECSPI2_BASE:
// ECSPI1 iomux configuration
/* daisy chain selection */
IOMUXC_ECSPI2_MISO_SELECT_INPUT = 0;
/* iomux */
IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SCLK = IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SCLK_MUX_MODE(0); /* ECSPI SLK */
IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MOSI = IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MOSI_MUX_MODE(0); /* ECSPI MOSI */
IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MISO = IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MISO_MUX_MODE(0); /* ECSPI MISO */
IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SS0 = IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SS0_MUX_MODE(0); /* ECSPI SS0 */
/* pad control */
IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK = IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK_PE_MASK |
IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK_PS(0) | /* pull down */
IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK_DSE(0) |
IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK_HYS_MASK;
IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MOSI = IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MOSI_HYS_MASK;
IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO = IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO_DSE(0) |
IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO_HYS_MASK;
IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0 = IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0_PE_MASK |
IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0_PS(3) | /* pull up */
IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0_DSE(0) |
IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0_HYS_MASK;
break;
default:
break;
}
}
void configure_ecspi_slave_pins(ECSPI_Type* base)
{
switch((uint32_t)base)
{
case ECSPI2_BASE:
/* daisy chain selection */
IOMUXC_ECSPI2_SCLK_SELECT_INPUT = 0;
IOMUXC_ECSPI2_MOSI_SELECT_INPUT = 0;
IOMUXC_ECSPI2_SS0_B_SELECT_INPUT = 0;
/* iomux */
IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SCLK = IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SCLK_MUX_MODE(0); /* ECSPI SLK */
IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MOSI = IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MOSI_MUX_MODE(0); /* ECSPI MOSI */
IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MISO = IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MISO_MUX_MODE(0); /* ECSPI MISO */
IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SS0 = IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SS0_MUX_MODE(0); /* ECSPI SS0 */
/* pad control */
IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK = IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK_HYS_MASK;
IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MOSI = IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MOSI_HYS_MASK;
IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO = IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO_DSE(0) |
IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO_HYS_MASK;
IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0 = IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0_HYS_MASK;
break;
default:
break;
}
}
/*******************************************************************************
* EOF
******************************************************************************/