Eric Lee / linux-smarc-t335x-v3.2

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Commit 0088903287aa1a7e49a64e83b9e5d4f08aedec69

Authored by Goutam Kumar
Committed by Hebbar, Gururaja
1 parent c51243440a
Exists in master

arm:omap:am335x: Correct KeyPad GPIO numbers 

This patch corrects keypwr1 pinmux to gpmc_a6.gpio1_22

Signed-off-by: Goutam Kumar <goutam.kumar@ti.com>
Signed-off-by: Hebbar, Gururaja <gururaja.hebbar@ti.com>

Showing 2 changed files with 3 additions and 3 deletions Inline Diff

arch/arm/mach-omap2/board-am335xevm.c
Diff comments   View file @ 0088903
1 /* 1 /*
2 * Code for AM335X EVM. 2 * Code for AM335X EVM.
3 * 3 *
4 * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/ 4 * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
5 * 5 *
6 * This program is free software; you can redistribute it and/or 6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as 7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2. 8 * published by the Free Software Foundation version 2.
9 * 9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty 11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details. 13 * GNU General Public License for more details.
14 */ 14 */
15 #include <linux/kernel.h> 15 #include <linux/kernel.h>
16 #include <linux/init.h> 16 #include <linux/init.h>
17 #include <linux/i2c.h> 17 #include <linux/i2c.h>
18 #include <linux/i2c/at24.h> 18 #include <linux/i2c/at24.h>
19 #include <linux/phy.h> 19 #include <linux/phy.h>
20 #include <linux/gpio.h> 20 #include <linux/gpio.h>
21 #include <linux/spi/spi.h> 21 #include <linux/spi/spi.h>
22 #include <linux/spi/flash.h> 22 #include <linux/spi/flash.h>
23 #ifdef CONFIG_KEYBOARD_GPIO 23 #ifdef CONFIG_KEYBOARD_GPIO
24 #include <linux/gpio_keys.h> 24 #include <linux/gpio_keys.h>
25 #endif 25 #endif
26 #ifdef CONFIG_KEYBOARD_MATRIX 26 #ifdef CONFIG_KEYBOARD_MATRIX
27 #include <linux/input.h> 27 #include <linux/input.h>
28 #include <linux/input/matrix_keypad.h> 28 #include <linux/input/matrix_keypad.h>
29 #endif 29 #endif
30 #include <linux/mtd/mtd.h> 30 #include <linux/mtd/mtd.h>
31 #include <linux/mtd/nand.h> 31 #include <linux/mtd/nand.h>
32 #include <linux/mtd/partitions.h> 32 #include <linux/mtd/partitions.h>
33 #include <linux/platform_device.h> 33 #include <linux/platform_device.h>
34 #include <linux/clk.h> 34 #include <linux/clk.h>
35 #include <linux/err.h> 35 #include <linux/err.h>
36 #include <linux/wl12xx.h> 36 #include <linux/wl12xx.h>
37 #include <linux/ethtool.h> 37 #include <linux/ethtool.h>
38 #include <linux/mfd/tps65910.h> 38 #include <linux/mfd/tps65910.h>
39 39
40 /* LCD controller is similar to DA850 */ 40 /* LCD controller is similar to DA850 */
41 #include <video/da8xx-fb.h> 41 #include <video/da8xx-fb.h>
42 42
43 #include <mach/hardware.h> 43 #include <mach/hardware.h>
44 #include <mach/board-am335xevm.h> 44 #include <mach/board-am335xevm.h>
45 45
46 #include <asm/mach-types.h> 46 #include <asm/mach-types.h>
47 #include <asm/mach/arch.h> 47 #include <asm/mach/arch.h>
48 #include <asm/mach/map.h> 48 #include <asm/mach/map.h>
49 #include <asm/hardware/asp.h> 49 #include <asm/hardware/asp.h>
50 50
51 #include <plat/irqs.h> 51 #include <plat/irqs.h>
52 #include <plat/board.h> 52 #include <plat/board.h>
53 #include <plat/common.h> 53 #include <plat/common.h>
54 #include <plat/lcdc.h> 54 #include <plat/lcdc.h>
55 #include <plat/usb.h> 55 #include <plat/usb.h>
56 #include <plat/mmc.h> 56 #include <plat/mmc.h>
57 57
58 #include "board-flash.h" 58 #include "board-flash.h"
59 #include "cpuidle33xx.h" 59 #include "cpuidle33xx.h"
60 #include "mux.h" 60 #include "mux.h"
61 #include "devices.h" 61 #include "devices.h"
62 #include "hsmmc.h" 62 #include "hsmmc.h"
63 63
64 /* TLK PHY IDs */ 64 /* TLK PHY IDs */
65 #define TLK110_PHY_ID 0x2000A201 65 #define TLK110_PHY_ID 0x2000A201
66 #define TLK110_PHY_MASK 0xfffffff0 66 #define TLK110_PHY_MASK 0xfffffff0
67 67
68 /* BBB PHY IDs */ 68 /* BBB PHY IDs */
69 #define BBB_PHY_ID 0x7c0f1 69 #define BBB_PHY_ID 0x7c0f1
70 #define BBB_PHY_MASK 0xfffffffe 70 #define BBB_PHY_MASK 0xfffffffe
71 71
72 /* TLK110 PHY register offsets */ 72 /* TLK110 PHY register offsets */
73 #define TLK110_COARSEGAIN_REG 0x00A3 73 #define TLK110_COARSEGAIN_REG 0x00A3
74 #define TLK110_LPFHPF_REG 0x00AC 74 #define TLK110_LPFHPF_REG 0x00AC
75 #define TLK110_SPAREANALOG_REG 0x00B9 75 #define TLK110_SPAREANALOG_REG 0x00B9
76 #define TLK110_VRCR_REG 0x00D0 76 #define TLK110_VRCR_REG 0x00D0
77 #define TLK110_SETFFE_REG 0x0107 77 #define TLK110_SETFFE_REG 0x0107
78 #define TLK110_FTSP_REG 0x0154 78 #define TLK110_FTSP_REG 0x0154
79 #define TLK110_ALFATPIDL_REG 0x002A 79 #define TLK110_ALFATPIDL_REG 0x002A
80 #define TLK110_PSCOEF21_REG 0x0096 80 #define TLK110_PSCOEF21_REG 0x0096
81 #define TLK110_PSCOEF3_REG 0x0097 81 #define TLK110_PSCOEF3_REG 0x0097
82 #define TLK110_ALFAFACTOR1_REG 0x002C 82 #define TLK110_ALFAFACTOR1_REG 0x002C
83 #define TLK110_ALFAFACTOR2_REG 0x0023 83 #define TLK110_ALFAFACTOR2_REG 0x0023
84 #define TLK110_CFGPS_REG 0x0095 84 #define TLK110_CFGPS_REG 0x0095
85 #define TLK110_FTSPTXGAIN_REG 0x0150 85 #define TLK110_FTSPTXGAIN_REG 0x0150
86 #define TLK110_SWSCR3_REG 0x000B 86 #define TLK110_SWSCR3_REG 0x000B
87 #define TLK110_SCFALLBACK_REG 0x0040 87 #define TLK110_SCFALLBACK_REG 0x0040
88 #define TLK110_PHYRCR_REG 0x001F 88 #define TLK110_PHYRCR_REG 0x001F
89 89
90 /* TLK110 register writes values */ 90 /* TLK110 register writes values */
91 #define TLK110_COARSEGAIN_VAL 0x0000 91 #define TLK110_COARSEGAIN_VAL 0x0000
92 #define TLK110_LPFHPF_VAL 0x8000 92 #define TLK110_LPFHPF_VAL 0x8000
93 #define TLK110_SPANALOG_VAL 0x0000 93 #define TLK110_SPANALOG_VAL 0x0000
94 #define TLK110_VRCR_VAL 0x0008 94 #define TLK110_VRCR_VAL 0x0008
95 #define TLK110_SETFFE_VAL 0x0605 95 #define TLK110_SETFFE_VAL 0x0605
96 #define TLK110_FTSP_VAL 0x0255 96 #define TLK110_FTSP_VAL 0x0255
97 #define TLK110_ALFATPIDL_VAL 0x7998 97 #define TLK110_ALFATPIDL_VAL 0x7998
98 #define TLK110_PSCOEF21_VAL 0x3A20 98 #define TLK110_PSCOEF21_VAL 0x3A20
99 #define TLK110_PSCOEF3_VAL 0x003F 99 #define TLK110_PSCOEF3_VAL 0x003F
100 #define TLK110_ALFACTOR1_VAL 0xFF80 100 #define TLK110_ALFACTOR1_VAL 0xFF80
101 #define TLK110_ALFACTOR2_VAL 0x021C 101 #define TLK110_ALFACTOR2_VAL 0x021C
102 #define TLK110_CFGPS_VAL 0x0000 102 #define TLK110_CFGPS_VAL 0x0000
103 #define TLK110_FTSPTXGAIN_VAL 0x6A88 103 #define TLK110_FTSPTXGAIN_VAL 0x6A88
104 #define TLK110_SWSCR3_VAL 0x0000 104 #define TLK110_SWSCR3_VAL 0x0000
105 #define TLK110_SCFALLBACK_VAL 0xC11D 105 #define TLK110_SCFALLBACK_VAL 0xC11D
106 #define TLK110_PHYRCR_VAL 0x4000 106 #define TLK110_PHYRCR_VAL 0x4000
107 107
108 #ifdef CONFIG_TLK110_WORKAROUND 108 #ifdef CONFIG_TLK110_WORKAROUND
109 #define am335x_tlk110_phy_init()\ 109 #define am335x_tlk110_phy_init()\
110 do { \ 110 do { \
111 phy_register_fixup_for_uid(TLK110_PHY_ID,\ 111 phy_register_fixup_for_uid(TLK110_PHY_ID,\
112 TLK110_PHY_MASK,\ 112 TLK110_PHY_MASK,\
113 am335x_tlk110_phy_fixup);\ 113 am335x_tlk110_phy_fixup);\
114 } while (0); 114 } while (0);
115 #else 115 #else
116 #define am335x_tlk110_phy_init() do { } while (0); 116 #define am335x_tlk110_phy_init() do { } while (0);
117 #endif 117 #endif
118 118
119 /* Convert GPIO signal to GPIO pin number */ 119 /* Convert GPIO signal to GPIO pin number */
120 #define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio)) 120 #define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
121 121
122 static const struct display_panel disp_panel = { 122 static const struct display_panel disp_panel = {
123 WVGA, 123 WVGA,
124 32, 124 32,
125 32, 125 32,
126 COLOR_ACTIVE, 126 COLOR_ACTIVE,
127 }; 127 };
128 128
129 static struct lcd_ctrl_config lcd_cfg = { 129 static struct lcd_ctrl_config lcd_cfg = {
130 &disp_panel, 130 &disp_panel,
131 .ac_bias = 255, 131 .ac_bias = 255,
132 .ac_bias_intrpt = 0, 132 .ac_bias_intrpt = 0,
133 .dma_burst_sz = 16, 133 .dma_burst_sz = 16,
134 .bpp = 32, 134 .bpp = 32,
135 .fdd = 0x80, 135 .fdd = 0x80,
136 .tft_alt_mode = 0, 136 .tft_alt_mode = 0,
137 .stn_565_mode = 0, 137 .stn_565_mode = 0,
138 .mono_8bit_mode = 0, 138 .mono_8bit_mode = 0,
139 .invert_line_clock = 1, 139 .invert_line_clock = 1,
140 .invert_frm_clock = 1, 140 .invert_frm_clock = 1,
141 .sync_edge = 0, 141 .sync_edge = 0,
142 .sync_ctrl = 1, 142 .sync_ctrl = 1,
143 .raster_order = 0, 143 .raster_order = 0,
144 }; 144 };
145 145
146 struct da8xx_lcdc_platform_data TFC_S9700RTWV35TR_01B_pdata = { 146 struct da8xx_lcdc_platform_data TFC_S9700RTWV35TR_01B_pdata = {
147 .manu_name = "ThreeFive", 147 .manu_name = "ThreeFive",
148 .controller_data = &lcd_cfg, 148 .controller_data = &lcd_cfg,
149 .type = "TFC_S9700RTWV35TR_01B", 149 .type = "TFC_S9700RTWV35TR_01B",
150 }; 150 };
151 151
152 /* TSc controller */ 152 /* TSc controller */
153 #include <linux/input/ti_tscadc.h> 153 #include <linux/input/ti_tscadc.h>
154 #include <linux/lis3lv02d.h> 154 #include <linux/lis3lv02d.h>
155 155
156 static struct resource tsc_resources[] = { 156 static struct resource tsc_resources[] = {
157 [0] = { 157 [0] = {
158 .start = AM33XX_TSC_BASE, 158 .start = AM33XX_TSC_BASE,
159 .end = AM33XX_TSC_BASE + SZ_8K - 1, 159 .end = AM33XX_TSC_BASE + SZ_8K - 1,
160 .flags = IORESOURCE_MEM, 160 .flags = IORESOURCE_MEM,
161 }, 161 },
162 [1] = { 162 [1] = {
163 .start = AM33XX_IRQ_ADC_GEN, 163 .start = AM33XX_IRQ_ADC_GEN,
164 .end = AM33XX_IRQ_ADC_GEN, 164 .end = AM33XX_IRQ_ADC_GEN,
165 .flags = IORESOURCE_IRQ, 165 .flags = IORESOURCE_IRQ,
166 }, 166 },
167 }; 167 };
168 168
169 static struct tsc_data am335x_touchscreen_data = { 169 static struct tsc_data am335x_touchscreen_data = {
170 .wires = 4, 170 .wires = 4,
171 .x_plate_resistance = 200, 171 .x_plate_resistance = 200,
172 }; 172 };
173 173
174 static struct platform_device tsc_device = { 174 static struct platform_device tsc_device = {
175 .name = "tsc", 175 .name = "tsc",
176 .id = -1, 176 .id = -1,
177 .dev = { 177 .dev = {
178 .platform_data = &am335x_touchscreen_data, 178 .platform_data = &am335x_touchscreen_data,
179 }, 179 },
180 .num_resources = ARRAY_SIZE(tsc_resources), 180 .num_resources = ARRAY_SIZE(tsc_resources),
181 .resource = tsc_resources, 181 .resource = tsc_resources,
182 }; 182 };
183 183
184 static u8 am335x_iis_serializer_direction1[] = { 184 static u8 am335x_iis_serializer_direction1[] = {
185 INACTIVE_MODE, INACTIVE_MODE, TX_MODE, RX_MODE, 185 INACTIVE_MODE, INACTIVE_MODE, TX_MODE, RX_MODE,
186 INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, 186 INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
187 INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, 187 INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
188 INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, 188 INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
189 }; 189 };
190 190
191 static struct snd_platform_data am335x_evm_snd_data1 = { 191 static struct snd_platform_data am335x_evm_snd_data1 = {
192 .tx_dma_offset = 0x46400000, /* McASP1 */ 192 .tx_dma_offset = 0x46400000, /* McASP1 */
193 .rx_dma_offset = 0x46400000, 193 .rx_dma_offset = 0x46400000,
194 .op_mode = DAVINCI_MCASP_IIS_MODE, 194 .op_mode = DAVINCI_MCASP_IIS_MODE,
195 .num_serializer = ARRAY_SIZE(am335x_iis_serializer_direction1), 195 .num_serializer = ARRAY_SIZE(am335x_iis_serializer_direction1),
196 .tdm_slots = 2, 196 .tdm_slots = 2,
197 .serial_dir = am335x_iis_serializer_direction1, 197 .serial_dir = am335x_iis_serializer_direction1,
198 .asp_chan_q = EVENTQ_2, 198 .asp_chan_q = EVENTQ_2,
199 .version = MCASP_VERSION_3, 199 .version = MCASP_VERSION_3,
200 .txnumevt = 1, 200 .txnumevt = 1,
201 .rxnumevt = 1, 201 .rxnumevt = 1,
202 }; 202 };
203 203
204 static struct omap2_hsmmc_info am335x_mmc[] __initdata = { 204 static struct omap2_hsmmc_info am335x_mmc[] __initdata = {
205 { 205 {
206 .mmc = 1, 206 .mmc = 1,
207 .caps = MMC_CAP_4_BIT_DATA, 207 .caps = MMC_CAP_4_BIT_DATA,
208 .gpio_cd = GPIO_TO_PIN(0, 6), 208 .gpio_cd = GPIO_TO_PIN(0, 6),
209 .gpio_wp = GPIO_TO_PIN(3, 18), 209 .gpio_wp = GPIO_TO_PIN(3, 18),
210 .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, /* 3V3 */ 210 .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, /* 3V3 */
211 }, 211 },
212 { 212 {
213 .mmc = 0, /* will be set at runtime */ 213 .mmc = 0, /* will be set at runtime */
214 }, 214 },
215 { 215 {
216 .mmc = 0, /* will be set at runtime */ 216 .mmc = 0, /* will be set at runtime */
217 }, 217 },
218 {} /* Terminator */ 218 {} /* Terminator */
219 }; 219 };
220 220
221 221
222 #ifdef CONFIG_OMAP_MUX 222 #ifdef CONFIG_OMAP_MUX
223 static struct omap_board_mux board_mux[] __initdata = { 223 static struct omap_board_mux board_mux[] __initdata = {
224 AM33XX_MUX(I2C0_SDA, OMAP_MUX_MODE0 | AM33XX_SLEWCTRL_SLOW | 224 AM33XX_MUX(I2C0_SDA, OMAP_MUX_MODE0 | AM33XX_SLEWCTRL_SLOW |
225 AM33XX_INPUT_EN | AM33XX_PIN_OUTPUT), 225 AM33XX_INPUT_EN | AM33XX_PIN_OUTPUT),
226 AM33XX_MUX(I2C0_SCL, OMAP_MUX_MODE0 | AM33XX_SLEWCTRL_SLOW | 226 AM33XX_MUX(I2C0_SCL, OMAP_MUX_MODE0 | AM33XX_SLEWCTRL_SLOW |
227 AM33XX_INPUT_EN | AM33XX_PIN_OUTPUT), 227 AM33XX_INPUT_EN | AM33XX_PIN_OUTPUT),
228 { .reg_offset = OMAP_MUX_TERMINATOR }, 228 { .reg_offset = OMAP_MUX_TERMINATOR },
229 }; 229 };
230 #else 230 #else
231 #define board_mux NULL 231 #define board_mux NULL
232 #endif 232 #endif
233 233
234 /* module pin mux structure */ 234 /* module pin mux structure */
235 struct pinmux_config { 235 struct pinmux_config {
236 const char *string_name; /* signal name format */ 236 const char *string_name; /* signal name format */
237 int val; /* Options for the mux register value */ 237 int val; /* Options for the mux register value */
238 }; 238 };
239 239
240 struct evm_dev_cfg { 240 struct evm_dev_cfg {
241 void (*device_init)(int evm_id, int profile); 241 void (*device_init)(int evm_id, int profile);
242 242
243 /* 243 /*
244 * If the device is required on both baseboard & daughter board (ex i2c), 244 * If the device is required on both baseboard & daughter board (ex i2c),
245 * specify DEV_ON_BASEBOARD 245 * specify DEV_ON_BASEBOARD
246 */ 246 */
247 #define DEV_ON_BASEBOARD 0 247 #define DEV_ON_BASEBOARD 0
248 #define DEV_ON_DGHTR_BRD 1 248 #define DEV_ON_DGHTR_BRD 1
249 u32 device_on; 249 u32 device_on;
250 250
251 u32 profile; /* Profiles (0-7) in which the module is present */ 251 u32 profile; /* Profiles (0-7) in which the module is present */
252 }; 252 };
253 253
254 /* AM335X - CPLD Register Offsets */ 254 /* AM335X - CPLD Register Offsets */
255 #define CPLD_DEVICE_HDR 0x00 /* CPLD Header */ 255 #define CPLD_DEVICE_HDR 0x00 /* CPLD Header */
256 #define CPLD_DEVICE_ID 0x04 /* CPLD identification */ 256 #define CPLD_DEVICE_ID 0x04 /* CPLD identification */
257 #define CPLD_DEVICE_REV 0x0C /* Revision of the CPLD code */ 257 #define CPLD_DEVICE_REV 0x0C /* Revision of the CPLD code */
258 #define CPLD_CFG_REG 0x10 /* Configuration Register */ 258 #define CPLD_CFG_REG 0x10 /* Configuration Register */
259 259
260 static struct i2c_client *cpld_client; 260 static struct i2c_client *cpld_client;
261 261
262 static u32 am335x_evm_id; 262 static u32 am335x_evm_id;
263 263
264 static struct omap_board_config_kernel am335x_evm_config[] __initdata = { 264 static struct omap_board_config_kernel am335x_evm_config[] __initdata = {
265 }; 265 };
266 266
267 /* 267 /*
268 * EVM Config held in On-Board eeprom device. 268 * EVM Config held in On-Board eeprom device.
269 * 269 *
270 * Header Format 270 * Header Format
271 * 271 *
272 * Name Size Contents 272 * Name Size Contents
273 * (Bytes) 273 * (Bytes)
274 *------------------------------------------------------------- 274 *-------------------------------------------------------------
275 * Header 4 0xAA, 0x55, 0x33, 0xEE 275 * Header 4 0xAA, 0x55, 0x33, 0xEE
276 * 276 *
277 * Board Name 8 Name for board in ASCII. 277 * Board Name 8 Name for board in ASCII.
278 * example "A33515BB" = "AM335X 278 * example "A33515BB" = "AM335X
279 Low Cost EVM board" 279 Low Cost EVM board"
280 * 280 *
281 * Version 4 Hardware version code for board in 281 * Version 4 Hardware version code for board in
282 * in ASCII. "1.0A" = rev.01.0A 282 * in ASCII. "1.0A" = rev.01.0A
283 * 283 *
284 * Serial Number 12 Serial number of the board. This is a 12 284 * Serial Number 12 Serial number of the board. This is a 12
285 * character string which is WWYY4P16nnnn, where 285 * character string which is WWYY4P16nnnn, where
286 * WW = 2 digit week of the year of production 286 * WW = 2 digit week of the year of production
287 * YY = 2 digit year of production 287 * YY = 2 digit year of production
288 * nnnn = incrementing board number 288 * nnnn = incrementing board number
289 * 289 *
290 * Configuration option 32 Codes(TBD) to show the configuration 290 * Configuration option 32 Codes(TBD) to show the configuration
291 * setup on this board. 291 * setup on this board.
292 * 292 *
293 * Available 32720 Available space for other non-volatile 293 * Available 32720 Available space for other non-volatile
294 * data. 294 * data.
295 */ 295 */
296 struct am335x_evm_eeprom_config { 296 struct am335x_evm_eeprom_config {
297 u32 header; 297 u32 header;
298 u8 name[8]; 298 u8 name[8];
299 char version[4]; 299 char version[4];
300 u8 serial[12]; 300 u8 serial[12];
301 u8 opt[32]; 301 u8 opt[32];
302 }; 302 };
303 303
304 static struct am335x_evm_eeprom_config config; 304 static struct am335x_evm_eeprom_config config;
305 static bool daughter_brd_detected; 305 static bool daughter_brd_detected;
306 306
307 #define GP_EVM_REV_IS_1_0 0x1 307 #define GP_EVM_REV_IS_1_0 0x1
308 #define GP_EVM_REV_IS_1_1A 0x2 308 #define GP_EVM_REV_IS_1_1A 0x2
309 #define GP_EVM_REV_IS_UNKNOWN 0xFF 309 #define GP_EVM_REV_IS_UNKNOWN 0xFF
310 static unsigned int gp_evm_revision = GP_EVM_REV_IS_UNKNOWN; 310 static unsigned int gp_evm_revision = GP_EVM_REV_IS_UNKNOWN;
311 unsigned int gigabit_enable = 1; 311 unsigned int gigabit_enable = 1;
312 312
313 #define EEPROM_MAC_ADDRESS_OFFSET 60 /* 4+8+4+12+32 */ 313 #define EEPROM_MAC_ADDRESS_OFFSET 60 /* 4+8+4+12+32 */
314 #define EEPROM_NO_OF_MAC_ADDR 3 314 #define EEPROM_NO_OF_MAC_ADDR 3
315 static char am335x_mac_addr[EEPROM_NO_OF_MAC_ADDR][ETH_ALEN]; 315 static char am335x_mac_addr[EEPROM_NO_OF_MAC_ADDR][ETH_ALEN];
316 316
317 #define AM335X_EEPROM_HEADER 0xEE3355AA 317 #define AM335X_EEPROM_HEADER 0xEE3355AA
318 318
319 /* current profile if exists else PROFILE_0 on error */ 319 /* current profile if exists else PROFILE_0 on error */
320 static u32 am335x_get_profile_selection(void) 320 static u32 am335x_get_profile_selection(void)
321 { 321 {
322 int val = 0; 322 int val = 0;
323 323
324 if (!cpld_client) 324 if (!cpld_client)
325 /* error checking is not done in func's calling this routine. 325 /* error checking is not done in func's calling this routine.
326 so return profile 0 on error */ 326 so return profile 0 on error */
327 return 0; 327 return 0;
328 328
329 val = i2c_smbus_read_word_data(cpld_client, CPLD_CFG_REG); 329 val = i2c_smbus_read_word_data(cpld_client, CPLD_CFG_REG);
330 if (val < 0) 330 if (val < 0)
331 return 0; /* default to Profile 0 on Error */ 331 return 0; /* default to Profile 0 on Error */
332 else 332 else
333 return val & 0x7; 333 return val & 0x7;
334 } 334 }
335 335
336 /* Module pin mux for LCDC */ 336 /* Module pin mux for LCDC */
337 static struct pinmux_config lcdc_pin_mux[] = { 337 static struct pinmux_config lcdc_pin_mux[] = {
338 {"lcd_data0.lcd_data0", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT 338 {"lcd_data0.lcd_data0", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
339 | AM33XX_PULL_DISA}, 339 | AM33XX_PULL_DISA},
340 {"lcd_data1.lcd_data1", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT 340 {"lcd_data1.lcd_data1", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
341 | AM33XX_PULL_DISA}, 341 | AM33XX_PULL_DISA},
342 {"lcd_data2.lcd_data2", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT 342 {"lcd_data2.lcd_data2", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
343 | AM33XX_PULL_DISA}, 343 | AM33XX_PULL_DISA},
344 {"lcd_data3.lcd_data3", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT 344 {"lcd_data3.lcd_data3", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
345 | AM33XX_PULL_DISA}, 345 | AM33XX_PULL_DISA},
346 {"lcd_data4.lcd_data4", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT 346 {"lcd_data4.lcd_data4", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
347 | AM33XX_PULL_DISA}, 347 | AM33XX_PULL_DISA},
348 {"lcd_data5.lcd_data5", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT 348 {"lcd_data5.lcd_data5", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
349 | AM33XX_PULL_DISA}, 349 | AM33XX_PULL_DISA},
350 {"lcd_data6.lcd_data6", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT 350 {"lcd_data6.lcd_data6", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
351 | AM33XX_PULL_DISA}, 351 | AM33XX_PULL_DISA},
352 {"lcd_data7.lcd_data7", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT 352 {"lcd_data7.lcd_data7", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
353 | AM33XX_PULL_DISA}, 353 | AM33XX_PULL_DISA},
354 {"lcd_data8.lcd_data8", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT 354 {"lcd_data8.lcd_data8", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
355 | AM33XX_PULL_DISA}, 355 | AM33XX_PULL_DISA},
356 {"lcd_data9.lcd_data9", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT 356 {"lcd_data9.lcd_data9", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
357 | AM33XX_PULL_DISA}, 357 | AM33XX_PULL_DISA},
358 {"lcd_data10.lcd_data10", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT 358 {"lcd_data10.lcd_data10", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
359 | AM33XX_PULL_DISA}, 359 | AM33XX_PULL_DISA},
360 {"lcd_data11.lcd_data11", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT 360 {"lcd_data11.lcd_data11", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
361 | AM33XX_PULL_DISA}, 361 | AM33XX_PULL_DISA},
362 {"lcd_data12.lcd_data12", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT 362 {"lcd_data12.lcd_data12", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
363 | AM33XX_PULL_DISA}, 363 | AM33XX_PULL_DISA},
364 {"lcd_data13.lcd_data13", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT 364 {"lcd_data13.lcd_data13", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
365 | AM33XX_PULL_DISA}, 365 | AM33XX_PULL_DISA},
366 {"lcd_data14.lcd_data14", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT 366 {"lcd_data14.lcd_data14", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
367 | AM33XX_PULL_DISA}, 367 | AM33XX_PULL_DISA},
368 {"lcd_data15.lcd_data15", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT 368 {"lcd_data15.lcd_data15", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
369 | AM33XX_PULL_DISA}, 369 | AM33XX_PULL_DISA},
370 {"gpmc_ad8.lcd_data16", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT}, 370 {"gpmc_ad8.lcd_data16", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
371 {"gpmc_ad9.lcd_data17", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT}, 371 {"gpmc_ad9.lcd_data17", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
372 {"gpmc_ad10.lcd_data18", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT}, 372 {"gpmc_ad10.lcd_data18", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
373 {"gpmc_ad11.lcd_data19", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT}, 373 {"gpmc_ad11.lcd_data19", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
374 {"gpmc_ad12.lcd_data20", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT}, 374 {"gpmc_ad12.lcd_data20", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
375 {"gpmc_ad13.lcd_data21", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT}, 375 {"gpmc_ad13.lcd_data21", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
376 {"gpmc_ad14.lcd_data22", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT}, 376 {"gpmc_ad14.lcd_data22", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
377 {"gpmc_ad15.lcd_data23", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT}, 377 {"gpmc_ad15.lcd_data23", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
378 {"lcd_vsync.lcd_vsync", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, 378 {"lcd_vsync.lcd_vsync", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
379 {"lcd_hsync.lcd_hsync", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, 379 {"lcd_hsync.lcd_hsync", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
380 {"lcd_pclk.lcd_pclk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, 380 {"lcd_pclk.lcd_pclk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
381 {"lcd_ac_bias_en.lcd_ac_bias_en", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, 381 {"lcd_ac_bias_en.lcd_ac_bias_en", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
382 {NULL, 0}, 382 {NULL, 0},
383 }; 383 };
384 384
385 static struct pinmux_config tsc_pin_mux[] = { 385 static struct pinmux_config tsc_pin_mux[] = {
386 {"ain0.ain0", OMAP_MUX_MODE0 | AM33XX_INPUT_EN}, 386 {"ain0.ain0", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
387 {"ain1.ain1", OMAP_MUX_MODE0 | AM33XX_INPUT_EN}, 387 {"ain1.ain1", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
388 {"ain2.ain2", OMAP_MUX_MODE0 | AM33XX_INPUT_EN}, 388 {"ain2.ain2", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
389 {"ain3.ain3", OMAP_MUX_MODE0 | AM33XX_INPUT_EN}, 389 {"ain3.ain3", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
390 {"vrefp.vrefp", OMAP_MUX_MODE0 | AM33XX_INPUT_EN}, 390 {"vrefp.vrefp", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
391 {"vrefn.vrefn", OMAP_MUX_MODE0 | AM33XX_INPUT_EN}, 391 {"vrefn.vrefn", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
392 {NULL, 0}, 392 {NULL, 0},
393 }; 393 };
394 394
395 /* Pin mux for nand flash module */ 395 /* Pin mux for nand flash module */
396 static struct pinmux_config nand_pin_mux[] = { 396 static struct pinmux_config nand_pin_mux[] = {
397 {"gpmc_ad0.gpmc_ad0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 397 {"gpmc_ad0.gpmc_ad0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
398 {"gpmc_ad1.gpmc_ad1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 398 {"gpmc_ad1.gpmc_ad1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
399 {"gpmc_ad2.gpmc_ad2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 399 {"gpmc_ad2.gpmc_ad2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
400 {"gpmc_ad3.gpmc_ad3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 400 {"gpmc_ad3.gpmc_ad3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
401 {"gpmc_ad4.gpmc_ad4", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 401 {"gpmc_ad4.gpmc_ad4", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
402 {"gpmc_ad5.gpmc_ad5", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 402 {"gpmc_ad5.gpmc_ad5", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
403 {"gpmc_ad6.gpmc_ad6", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 403 {"gpmc_ad6.gpmc_ad6", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
404 {"gpmc_ad7.gpmc_ad7", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 404 {"gpmc_ad7.gpmc_ad7", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
405 {"gpmc_wait0.gpmc_wait0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 405 {"gpmc_wait0.gpmc_wait0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
406 {"gpmc_wpn.gpmc_wpn", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP}, 406 {"gpmc_wpn.gpmc_wpn", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
407 {"gpmc_csn0.gpmc_csn0", OMAP_MUX_MODE0 | AM33XX_PULL_DISA}, 407 {"gpmc_csn0.gpmc_csn0", OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
408 {"gpmc_advn_ale.gpmc_advn_ale", OMAP_MUX_MODE0 | AM33XX_PULL_DISA}, 408 {"gpmc_advn_ale.gpmc_advn_ale", OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
409 {"gpmc_oen_ren.gpmc_oen_ren", OMAP_MUX_MODE0 | AM33XX_PULL_DISA}, 409 {"gpmc_oen_ren.gpmc_oen_ren", OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
410 {"gpmc_wen.gpmc_wen", OMAP_MUX_MODE0 | AM33XX_PULL_DISA}, 410 {"gpmc_wen.gpmc_wen", OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
411 {"gpmc_ben0_cle.gpmc_ben0_cle", OMAP_MUX_MODE0 | AM33XX_PULL_DISA}, 411 {"gpmc_ben0_cle.gpmc_ben0_cle", OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
412 {NULL, 0}, 412 {NULL, 0},
413 }; 413 };
414 414
415 /* Module pin mux for SPI fash */ 415 /* Module pin mux for SPI fash */
416 static struct pinmux_config spi0_pin_mux[] = { 416 static struct pinmux_config spi0_pin_mux[] = {
417 {"spi0_sclk.spi0_sclk", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL 417 {"spi0_sclk.spi0_sclk", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL
418 | AM33XX_INPUT_EN}, 418 | AM33XX_INPUT_EN},
419 {"spi0_d0.spi0_d0", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL | AM33XX_PULL_UP 419 {"spi0_d0.spi0_d0", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL | AM33XX_PULL_UP
420 | AM33XX_INPUT_EN}, 420 | AM33XX_INPUT_EN},
421 {"spi0_d1.spi0_d1", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL 421 {"spi0_d1.spi0_d1", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL
422 | AM33XX_INPUT_EN}, 422 | AM33XX_INPUT_EN},
423 {"spi0_cs0.spi0_cs0", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL | AM33XX_PULL_UP 423 {"spi0_cs0.spi0_cs0", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL | AM33XX_PULL_UP
424 | AM33XX_INPUT_EN}, 424 | AM33XX_INPUT_EN},
425 {NULL, 0}, 425 {NULL, 0},
426 }; 426 };
427 427
428 /* Module pin mux for SPI flash */ 428 /* Module pin mux for SPI flash */
429 static struct pinmux_config spi1_pin_mux[] = { 429 static struct pinmux_config spi1_pin_mux[] = {
430 {"mcasp0_aclkx.spi1_sclk", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL 430 {"mcasp0_aclkx.spi1_sclk", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
431 | AM33XX_INPUT_EN}, 431 | AM33XX_INPUT_EN},
432 {"mcasp0_fsx.spi1_d0", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL 432 {"mcasp0_fsx.spi1_d0", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
433 | AM33XX_PULL_UP | AM33XX_INPUT_EN}, 433 | AM33XX_PULL_UP | AM33XX_INPUT_EN},
434 {"mcasp0_axr0.spi1_d1", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL 434 {"mcasp0_axr0.spi1_d1", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
435 | AM33XX_INPUT_EN}, 435 | AM33XX_INPUT_EN},
436 {"mcasp0_ahclkr.spi1_cs0", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL 436 {"mcasp0_ahclkr.spi1_cs0", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
437 | AM33XX_PULL_UP | AM33XX_INPUT_EN}, 437 | AM33XX_PULL_UP | AM33XX_INPUT_EN},
438 {NULL, 0}, 438 {NULL, 0},
439 }; 439 };
440 440
441 /* Module pin mux for rgmii1 */ 441 /* Module pin mux for rgmii1 */
442 static struct pinmux_config rgmii1_pin_mux[] = { 442 static struct pinmux_config rgmii1_pin_mux[] = {
443 {"mii1_txen.rgmii1_tctl", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, 443 {"mii1_txen.rgmii1_tctl", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
444 {"mii1_rxdv.rgmii1_rctl", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, 444 {"mii1_rxdv.rgmii1_rctl", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
445 {"mii1_txd3.rgmii1_td3", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, 445 {"mii1_txd3.rgmii1_td3", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
446 {"mii1_txd2.rgmii1_td2", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, 446 {"mii1_txd2.rgmii1_td2", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
447 {"mii1_txd1.rgmii1_td1", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, 447 {"mii1_txd1.rgmii1_td1", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
448 {"mii1_txd0.rgmii1_td0", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, 448 {"mii1_txd0.rgmii1_td0", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
449 {"mii1_txclk.rgmii1_tclk", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, 449 {"mii1_txclk.rgmii1_tclk", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
450 {"mii1_rxclk.rgmii1_rclk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, 450 {"mii1_rxclk.rgmii1_rclk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
451 {"mii1_rxd3.rgmii1_rd3", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, 451 {"mii1_rxd3.rgmii1_rd3", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
452 {"mii1_rxd2.rgmii1_rd2", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, 452 {"mii1_rxd2.rgmii1_rd2", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
453 {"mii1_rxd1.rgmii1_rd1", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, 453 {"mii1_rxd1.rgmii1_rd1", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
454 {"mii1_rxd0.rgmii1_rd0", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, 454 {"mii1_rxd0.rgmii1_rd0", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
455 {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 455 {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
456 {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP}, 456 {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
457 {NULL, 0}, 457 {NULL, 0},
458 }; 458 };
459 459
460 /* Module pin mux for rgmii2 */ 460 /* Module pin mux for rgmii2 */
461 static struct pinmux_config rgmii2_pin_mux[] = { 461 static struct pinmux_config rgmii2_pin_mux[] = {
462 {"gpmc_a0.rgmii2_tctl", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, 462 {"gpmc_a0.rgmii2_tctl", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
463 {"gpmc_a1.rgmii2_rctl", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, 463 {"gpmc_a1.rgmii2_rctl", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
464 {"gpmc_a2.rgmii2_td3", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, 464 {"gpmc_a2.rgmii2_td3", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
465 {"gpmc_a3.rgmii2_td2", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, 465 {"gpmc_a3.rgmii2_td2", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
466 {"gpmc_a4.rgmii2_td1", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, 466 {"gpmc_a4.rgmii2_td1", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
467 {"gpmc_a5.rgmii2_td0", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, 467 {"gpmc_a5.rgmii2_td0", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
468 {"gpmc_a6.rgmii2_tclk", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, 468 {"gpmc_a6.rgmii2_tclk", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
469 {"gpmc_a7.rgmii2_rclk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, 469 {"gpmc_a7.rgmii2_rclk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
470 {"gpmc_a8.rgmii2_rd3", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, 470 {"gpmc_a8.rgmii2_rd3", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
471 {"gpmc_a9.rgmii2_rd2", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, 471 {"gpmc_a9.rgmii2_rd2", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
472 {"gpmc_a10.rgmii2_rd1", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, 472 {"gpmc_a10.rgmii2_rd1", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
473 {"gpmc_a11.rgmii2_rd0", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, 473 {"gpmc_a11.rgmii2_rd0", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
474 {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 474 {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
475 {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP}, 475 {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
476 {NULL, 0}, 476 {NULL, 0},
477 }; 477 };
478 478
479 /* Module pin mux for mii1 */ 479 /* Module pin mux for mii1 */
480 static struct pinmux_config mii1_pin_mux[] = { 480 static struct pinmux_config mii1_pin_mux[] = {
481 {"mii1_rxerr.mii1_rxerr", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN}, 481 {"mii1_rxerr.mii1_rxerr", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
482 {"mii1_txen.mii1_txen", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, 482 {"mii1_txen.mii1_txen", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
483 {"mii1_rxdv.mii1_rxdv", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN}, 483 {"mii1_rxdv.mii1_rxdv", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
484 {"mii1_txd3.mii1_txd3", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, 484 {"mii1_txd3.mii1_txd3", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
485 {"mii1_txd2.mii1_txd2", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, 485 {"mii1_txd2.mii1_txd2", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
486 {"mii1_txd1.mii1_txd1", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, 486 {"mii1_txd1.mii1_txd1", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
487 {"mii1_txd0.mii1_txd0", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, 487 {"mii1_txd0.mii1_txd0", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
488 {"mii1_txclk.mii1_txclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN}, 488 {"mii1_txclk.mii1_txclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
489 {"mii1_rxclk.mii1_rxclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN}, 489 {"mii1_rxclk.mii1_rxclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
490 {"mii1_rxd3.mii1_rxd3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN}, 490 {"mii1_rxd3.mii1_rxd3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
491 {"mii1_rxd2.mii1_rxd2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN}, 491 {"mii1_rxd2.mii1_rxd2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
492 {"mii1_rxd1.mii1_rxd1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN}, 492 {"mii1_rxd1.mii1_rxd1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
493 {"mii1_rxd0.mii1_rxd0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN}, 493 {"mii1_rxd0.mii1_rxd0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
494 {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 494 {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
495 {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP}, 495 {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
496 {NULL, 0}, 496 {NULL, 0},
497 }; 497 };
498 498
499 /* Module pin mux for rmii1 */ 499 /* Module pin mux for rmii1 */
500 static struct pinmux_config rmii1_pin_mux[] = { 500 static struct pinmux_config rmii1_pin_mux[] = {
501 {"mii1_crs.rmii1_crs_dv", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN}, 501 {"mii1_crs.rmii1_crs_dv", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
502 {"mii1_rxerr.mii1_rxerr", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN}, 502 {"mii1_rxerr.mii1_rxerr", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
503 {"mii1_txen.mii1_txen", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT}, 503 {"mii1_txen.mii1_txen", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
504 {"mii1_txd1.mii1_txd1", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT}, 504 {"mii1_txd1.mii1_txd1", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
505 {"mii1_txd0.mii1_txd0", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT}, 505 {"mii1_txd0.mii1_txd0", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
506 {"mii1_rxd1.mii1_rxd1", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN}, 506 {"mii1_rxd1.mii1_rxd1", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
507 {"mii1_rxd0.mii1_rxd0", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN}, 507 {"mii1_rxd0.mii1_rxd0", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
508 {"rmii1_refclk.rmii1_refclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN}, 508 {"rmii1_refclk.rmii1_refclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
509 {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 509 {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
510 {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP}, 510 {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
511 {NULL, 0}, 511 {NULL, 0},
512 }; 512 };
513 513
514 static struct pinmux_config i2c1_pin_mux[] = { 514 static struct pinmux_config i2c1_pin_mux[] = {
515 {"spi0_d1.i2c1_sda", OMAP_MUX_MODE2 | AM33XX_SLEWCTRL_SLOW | 515 {"spi0_d1.i2c1_sda", OMAP_MUX_MODE2 | AM33XX_SLEWCTRL_SLOW |
516 AM33XX_PULL_ENBL | AM33XX_INPUT_EN}, 516 AM33XX_PULL_ENBL | AM33XX_INPUT_EN},
517 {"spi0_cs0.i2c1_scl", OMAP_MUX_MODE2 | AM33XX_SLEWCTRL_SLOW | 517 {"spi0_cs0.i2c1_scl", OMAP_MUX_MODE2 | AM33XX_SLEWCTRL_SLOW |
518 AM33XX_PULL_ENBL | AM33XX_INPUT_EN}, 518 AM33XX_PULL_ENBL | AM33XX_INPUT_EN},
519 {NULL, 0}, 519 {NULL, 0},
520 }; 520 };
521 521
522 /* Module pin mux for mcasp1 */ 522 /* Module pin mux for mcasp1 */
523 static struct pinmux_config mcasp1_pin_mux[] = { 523 static struct pinmux_config mcasp1_pin_mux[] = {
524 {"mii1_crs.mcasp1_aclkx", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN}, 524 {"mii1_crs.mcasp1_aclkx", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
525 {"mii1_rxerr.mcasp1_fsx", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN}, 525 {"mii1_rxerr.mcasp1_fsx", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
526 {"mii1_col.mcasp1_axr2", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN}, 526 {"mii1_col.mcasp1_axr2", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
527 {"rmii1_refclk.mcasp1_axr3", OMAP_MUX_MODE4 | 527 {"rmii1_refclk.mcasp1_axr3", OMAP_MUX_MODE4 |
528 AM33XX_PIN_INPUT_PULLDOWN}, 528 AM33XX_PIN_INPUT_PULLDOWN},
529 {NULL, 0}, 529 {NULL, 0},
530 }; 530 };
531 531
532 532
533 /* Module pin mux for mmc0 */ 533 /* Module pin mux for mmc0 */
534 static struct pinmux_config mmc0_pin_mux[] = { 534 static struct pinmux_config mmc0_pin_mux[] = {
535 {"mmc0_dat3.mmc0_dat3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 535 {"mmc0_dat3.mmc0_dat3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
536 {"mmc0_dat2.mmc0_dat2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 536 {"mmc0_dat2.mmc0_dat2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
537 {"mmc0_dat1.mmc0_dat1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 537 {"mmc0_dat1.mmc0_dat1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
538 {"mmc0_dat0.mmc0_dat0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 538 {"mmc0_dat0.mmc0_dat0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
539 {"mmc0_clk.mmc0_clk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 539 {"mmc0_clk.mmc0_clk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
540 {"mmc0_cmd.mmc0_cmd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 540 {"mmc0_cmd.mmc0_cmd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
541 {"mcasp0_aclkr.mmc0_sdwp", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP}, 541 {"mcasp0_aclkr.mmc0_sdwp", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
542 {"spi0_cs1.mmc0_sdcd", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP}, 542 {"spi0_cs1.mmc0_sdcd", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
543 {NULL, 0}, 543 {NULL, 0},
544 }; 544 };
545 545
546 static struct pinmux_config mmc0_no_cd_pin_mux[] = { 546 static struct pinmux_config mmc0_no_cd_pin_mux[] = {
547 {"mmc0_dat3.mmc0_dat3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 547 {"mmc0_dat3.mmc0_dat3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
548 {"mmc0_dat2.mmc0_dat2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 548 {"mmc0_dat2.mmc0_dat2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
549 {"mmc0_dat1.mmc0_dat1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 549 {"mmc0_dat1.mmc0_dat1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
550 {"mmc0_dat0.mmc0_dat0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 550 {"mmc0_dat0.mmc0_dat0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
551 {"mmc0_clk.mmc0_clk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 551 {"mmc0_clk.mmc0_clk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
552 {"mmc0_cmd.mmc0_cmd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 552 {"mmc0_cmd.mmc0_cmd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
553 {"mcasp0_aclkr.mmc0_sdwp", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN}, 553 {"mcasp0_aclkr.mmc0_sdwp", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
554 {NULL, 0}, 554 {NULL, 0},
555 }; 555 };
556 556
557 /* Module pin mux for mmc1 */ 557 /* Module pin mux for mmc1 */
558 static struct pinmux_config mmc1_pin_mux[] = { 558 static struct pinmux_config mmc1_pin_mux[] = {
559 {"gpmc_ad7.mmc1_dat7", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP}, 559 {"gpmc_ad7.mmc1_dat7", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
560 {"gpmc_ad6.mmc1_dat6", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP}, 560 {"gpmc_ad6.mmc1_dat6", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
561 {"gpmc_ad5.mmc1_dat5", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP}, 561 {"gpmc_ad5.mmc1_dat5", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
562 {"gpmc_ad4.mmc1_dat4", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP}, 562 {"gpmc_ad4.mmc1_dat4", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
563 {"gpmc_ad3.mmc1_dat3", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP}, 563 {"gpmc_ad3.mmc1_dat3", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
564 {"gpmc_ad2.mmc1_dat2", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP}, 564 {"gpmc_ad2.mmc1_dat2", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
565 {"gpmc_ad1.mmc1_dat1", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP}, 565 {"gpmc_ad1.mmc1_dat1", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
566 {"gpmc_ad0.mmc1_dat0", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP}, 566 {"gpmc_ad0.mmc1_dat0", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
567 {"gpmc_csn1.mmc1_clk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP}, 567 {"gpmc_csn1.mmc1_clk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
568 {"gpmc_csn2.mmc1_cmd", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP}, 568 {"gpmc_csn2.mmc1_cmd", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
569 {"gpmc_csn0.mmc1_sdwp", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP}, 569 {"gpmc_csn0.mmc1_sdwp", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
570 {"gpmc_advn_ale.mmc1_sdcd", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP}, 570 {"gpmc_advn_ale.mmc1_sdcd", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
571 {NULL, 0}, 571 {NULL, 0},
572 }; 572 };
573 573
574 /* Module pin mux for uart3 */ 574 /* Module pin mux for uart3 */
575 static struct pinmux_config uart3_pin_mux[] = { 575 static struct pinmux_config uart3_pin_mux[] = {
576 {"spi0_cs1.uart3_rxd", AM33XX_PIN_INPUT_PULLUP}, 576 {"spi0_cs1.uart3_rxd", AM33XX_PIN_INPUT_PULLUP},
577 {"ecap0_in_pwm0_out.uart3_txd", AM33XX_PULL_ENBL}, 577 {"ecap0_in_pwm0_out.uart3_txd", AM33XX_PULL_ENBL},
578 {NULL, 0}, 578 {NULL, 0},
579 }; 579 };
580 580
581 static struct pinmux_config d_can_gp_pin_mux[] = { 581 static struct pinmux_config d_can_gp_pin_mux[] = {
582 {"uart0_ctsn.d_can1_tx", OMAP_MUX_MODE2 | AM33XX_PULL_ENBL}, 582 {"uart0_ctsn.d_can1_tx", OMAP_MUX_MODE2 | AM33XX_PULL_ENBL},
583 {"uart0_rtsn.d_can1_rx", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP}, 583 {"uart0_rtsn.d_can1_rx", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
584 {NULL, 0}, 584 {NULL, 0},
585 }; 585 };
586 586
587 static struct pinmux_config d_can_ia_pin_mux[] = { 587 static struct pinmux_config d_can_ia_pin_mux[] = {
588 {"uart0_rxd.d_can0_tx", OMAP_MUX_MODE2 | AM33XX_PULL_ENBL}, 588 {"uart0_rxd.d_can0_tx", OMAP_MUX_MODE2 | AM33XX_PULL_ENBL},
589 {"uart0_txd.d_can0_rx", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP}, 589 {"uart0_txd.d_can0_rx", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
590 {NULL, 0}, 590 {NULL, 0},
591 }; 591 };
592 592
593 /* 593 /*
594 * @pin_mux - single module pin-mux structure which defines pin-mux 594 * @pin_mux - single module pin-mux structure which defines pin-mux
595 * details for all its pins. 595 * details for all its pins.
596 */ 596 */
597 static void setup_pin_mux(struct pinmux_config *pin_mux) 597 static void setup_pin_mux(struct pinmux_config *pin_mux)
598 { 598 {
599 int i; 599 int i;
600 600
601 for (i = 0; pin_mux->string_name != NULL; pin_mux++) 601 for (i = 0; pin_mux->string_name != NULL; pin_mux++)
602 omap_mux_init_signal(pin_mux->string_name, pin_mux->val); 602 omap_mux_init_signal(pin_mux->string_name, pin_mux->val);
603 603
604 } 604 }
605 605
606 /* Matrix GPIO Keypad Support for profile-0 only: TODO */ 606 /* Matrix GPIO Keypad Support for profile-0 only: TODO */
607 #ifdef CONFIG_KEYBOARD_MATRIX 607 #ifdef CONFIG_KEYBOARD_MATRIX
608 608
609 /* pinmux for keypad device */ 609 /* pinmux for keypad device */
610 static struct pinmux_config matrix_keypad_pin_mux[] = { 610 static struct pinmux_config matrix_keypad_pin_mux[] = {
611 {"gpmc_a5.gpio1_21", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT}, 611 {"gpmc_a5.gpio1_21", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
612 {"gpmc_a8.gpio1_24", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT}, 612 {"gpmc_a8.gpio1_22", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
613 {"gpmc_a9.gpio1_25", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT}, 613 {"gpmc_a9.gpio1_25", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
614 {"gpmc_a10.gpio1_26", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT}, 614 {"gpmc_a10.gpio1_26", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
615 {"gpmc_a11.gpio1_27", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT}, 615 {"gpmc_a11.gpio1_27", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
616 {NULL, 0}, 616 {NULL, 0},
617 }; 617 };
618 618
619 /* Keys mapping */ 619 /* Keys mapping */
620 static const uint32_t am335x_evm_matrix_keys[] = { 620 static const uint32_t am335x_evm_matrix_keys[] = {
621 KEY(0, 0, KEY_MENU), 621 KEY(0, 0, KEY_MENU),
622 KEY(1, 0, KEY_BACK), 622 KEY(1, 0, KEY_BACK),
623 KEY(2, 0, KEY_LEFT), 623 KEY(2, 0, KEY_LEFT),
624 624
625 KEY(0, 1, KEY_RIGHT), 625 KEY(0, 1, KEY_RIGHT),
626 KEY(1, 1, KEY_ENTER), 626 KEY(1, 1, KEY_ENTER),
627 KEY(2, 1, KEY_DOWN), 627 KEY(2, 1, KEY_DOWN),
628 }; 628 };
629 629
630 const struct matrix_keymap_data am335x_evm_keymap_data = { 630 const struct matrix_keymap_data am335x_evm_keymap_data = {
631 .keymap = am335x_evm_matrix_keys, 631 .keymap = am335x_evm_matrix_keys,
632 .keymap_size = ARRAY_SIZE(am335x_evm_matrix_keys), 632 .keymap_size = ARRAY_SIZE(am335x_evm_matrix_keys),
633 }; 633 };
634 634
635 static const unsigned int am335x_evm_keypad_row_gpios[] = { 635 static const unsigned int am335x_evm_keypad_row_gpios[] = {
636 GPIO_TO_PIN(1, 25), GPIO_TO_PIN(1, 26), GPIO_TO_PIN(1, 27) 636 GPIO_TO_PIN(1, 25), GPIO_TO_PIN(1, 26), GPIO_TO_PIN(1, 27)
637 }; 637 };
638 638
639 static const unsigned int am335x_evm_keypad_col_gpios[] = { 639 static const unsigned int am335x_evm_keypad_col_gpios[] = {
640 GPIO_TO_PIN(1, 21), GPIO_TO_PIN(1, 24) 640 GPIO_TO_PIN(1, 21), GPIO_TO_PIN(1, 22)
641 }; 641 };
642 642
643 static struct matrix_keypad_platform_data am335x_evm_keypad_platform_data = { 643 static struct matrix_keypad_platform_data am335x_evm_keypad_platform_data = {
644 .keymap_data = &am335x_evm_keymap_data, 644 .keymap_data = &am335x_evm_keymap_data,
645 .row_gpios = am335x_evm_keypad_row_gpios, 645 .row_gpios = am335x_evm_keypad_row_gpios,
646 .num_row_gpios = ARRAY_SIZE(am335x_evm_keypad_row_gpios), 646 .num_row_gpios = ARRAY_SIZE(am335x_evm_keypad_row_gpios),
647 .col_gpios = am335x_evm_keypad_col_gpios, 647 .col_gpios = am335x_evm_keypad_col_gpios,
648 .num_col_gpios = ARRAY_SIZE(am335x_evm_keypad_col_gpios), 648 .num_col_gpios = ARRAY_SIZE(am335x_evm_keypad_col_gpios),
649 .active_low = false, 649 .active_low = false,
650 .debounce_ms = 5, 650 .debounce_ms = 5,
651 .col_scan_delay_us = 2, 651 .col_scan_delay_us = 2,
652 }; 652 };
653 653
654 static struct platform_device am335x_evm_keyboard = { 654 static struct platform_device am335x_evm_keyboard = {
655 .name = "matrix-keypad", 655 .name = "matrix-keypad",
656 .id = -1, 656 .id = -1,
657 .dev = { 657 .dev = {
658 .platform_data = &am335x_evm_keypad_platform_data, 658 .platform_data = &am335x_evm_keypad_platform_data,
659 }, 659 },
660 }; 660 };
661 661
662 static void matrix_keypad_init(int evm_id, int profile) 662 static void matrix_keypad_init(int evm_id, int profile)
663 { 663 {
664 int err; 664 int err;
665 665
666 setup_pin_mux(matrix_keypad_pin_mux); 666 setup_pin_mux(matrix_keypad_pin_mux);
667 err = platform_device_register(&am335x_evm_keyboard); 667 err = platform_device_register(&am335x_evm_keyboard);
668 if (err) { 668 if (err) {
669 pr_err("failed to register matrix keypad (2x3) device\n"); 669 pr_err("failed to register matrix keypad (2x3) device\n");
670 } 670 }
671 } 671 }
672 #endif 672 #endif
673 673
674 674
675 #ifdef CONFIG_KEYBOARD_GPIO 675 #ifdef CONFIG_KEYBOARD_GPIO
676 /* pinmux for keypad device */ 676 /* pinmux for keypad device */
677 static struct pinmux_config volume_keys_pin_mux[] = { 677 static struct pinmux_config volume_keys_pin_mux[] = {
678 {"spi0_sclk.gpio0_2", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT}, 678 {"spi0_sclk.gpio0_2", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
679 {"spi0_d0.gpio0_3", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT}, 679 {"spi0_d0.gpio0_3", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
680 {NULL, 0}, 680 {NULL, 0},
681 }; 681 };
682 682
683 /* Configure GPIOs for Volume Keys */ 683 /* Configure GPIOs for Volume Keys */
684 static struct gpio_keys_button am335x_evm_volume_gpio_buttons[] = { 684 static struct gpio_keys_button am335x_evm_volume_gpio_buttons[] = {
685 { 685 {
686 .code = KEY_VOLUMEUP, 686 .code = KEY_VOLUMEUP,
687 .gpio = GPIO_TO_PIN(0, 2), 687 .gpio = GPIO_TO_PIN(0, 2),
688 .active_low = true, 688 .active_low = true,
689 .desc = "volume-up", 689 .desc = "volume-up",
690 .type = EV_KEY, 690 .type = EV_KEY,
691 .wakeup = 1, 691 .wakeup = 1,
692 }, 692 },
693 { 693 {
694 .code = KEY_VOLUMEDOWN, 694 .code = KEY_VOLUMEDOWN,
695 .gpio = GPIO_TO_PIN(0, 3), 695 .gpio = GPIO_TO_PIN(0, 3),
696 .active_low = true, 696 .active_low = true,
697 .desc = "volume-down", 697 .desc = "volume-down",
698 .type = EV_KEY, 698 .type = EV_KEY,
699 .wakeup = 1, 699 .wakeup = 1,
700 }, 700 },
701 }; 701 };
702 702
703 static struct gpio_keys_platform_data am335x_evm_volume_gpio_key_info = { 703 static struct gpio_keys_platform_data am335x_evm_volume_gpio_key_info = {
704 .buttons = am335x_evm_volume_gpio_buttons, 704 .buttons = am335x_evm_volume_gpio_buttons,
705 .nbuttons = ARRAY_SIZE(am335x_evm_volume_gpio_buttons), 705 .nbuttons = ARRAY_SIZE(am335x_evm_volume_gpio_buttons),
706 }; 706 };
707 707
708 static struct platform_device am335x_evm_volume_keys = { 708 static struct platform_device am335x_evm_volume_keys = {
709 .name = "gpio-keys", 709 .name = "gpio-keys",
710 .id = -1, 710 .id = -1,
711 .dev = { 711 .dev = {
712 .platform_data = &am335x_evm_volume_gpio_key_info, 712 .platform_data = &am335x_evm_volume_gpio_key_info,
713 }, 713 },
714 }; 714 };
715 715
716 static void volume_keys_init(int evm_id, int profile) 716 static void volume_keys_init(int evm_id, int profile)
717 { 717 {
718 int err; 718 int err;
719 719
720 setup_pin_mux(volume_keys_pin_mux); 720 setup_pin_mux(volume_keys_pin_mux);
721 err = platform_device_register(&am335x_evm_volume_keys); 721 err = platform_device_register(&am335x_evm_volume_keys);
722 if (err) 722 if (err)
723 pr_err("failed to register matrix keypad (2x3) device\n"); 723 pr_err("failed to register matrix keypad (2x3) device\n");
724 } 724 }
725 #endif 725 #endif
726 726
727 /* 727 /*
728 * @evm_id - evm id which needs to be configured 728 * @evm_id - evm id which needs to be configured
729 * @dev_cfg - single evm structure which includes 729 * @dev_cfg - single evm structure which includes
730 * all module inits, pin-mux defines 730 * all module inits, pin-mux defines
731 * @profile - if present, else PROFILE_NONE 731 * @profile - if present, else PROFILE_NONE
732 * @dghtr_brd_flg - Whether Daughter board is present or not 732 * @dghtr_brd_flg - Whether Daughter board is present or not
733 */ 733 */
734 static void _configure_device(int evm_id, struct evm_dev_cfg *dev_cfg, 734 static void _configure_device(int evm_id, struct evm_dev_cfg *dev_cfg,
735 int profile) 735 int profile)
736 { 736 {
737 int i; 737 int i;
738 738
739 /* 739 /*
740 * Only General Purpose & Industrial Auto Motro Control 740 * Only General Purpose & Industrial Auto Motro Control
741 * EVM has profiles. So check if this evm has profile. 741 * EVM has profiles. So check if this evm has profile.
742 * If not, ignore the profile comparison 742 * If not, ignore the profile comparison
743 */ 743 */
744 744
745 /* 745 /*
746 * If the device is on baseboard, directly configure it. Else (device on 746 * If the device is on baseboard, directly configure it. Else (device on
747 * Daughter board), check if the daughter card is detected. 747 * Daughter board), check if the daughter card is detected.
748 */ 748 */
749 if (profile == PROFILE_NONE) { 749 if (profile == PROFILE_NONE) {
750 for (i = 0; dev_cfg->device_init != NULL; dev_cfg++) { 750 for (i = 0; dev_cfg->device_init != NULL; dev_cfg++) {
751 if (dev_cfg->device_on == DEV_ON_BASEBOARD) 751 if (dev_cfg->device_on == DEV_ON_BASEBOARD)
752 dev_cfg->device_init(evm_id, profile); 752 dev_cfg->device_init(evm_id, profile);
753 else if (daughter_brd_detected == true) 753 else if (daughter_brd_detected == true)
754 dev_cfg->device_init(evm_id, profile); 754 dev_cfg->device_init(evm_id, profile);
755 } 755 }
756 } else { 756 } else {
757 for (i = 0; dev_cfg->device_init != NULL; dev_cfg++) { 757 for (i = 0; dev_cfg->device_init != NULL; dev_cfg++) {
758 if (dev_cfg->profile & profile) { 758 if (dev_cfg->profile & profile) {
759 if (dev_cfg->device_on == DEV_ON_BASEBOARD) 759 if (dev_cfg->device_on == DEV_ON_BASEBOARD)
760 dev_cfg->device_init(evm_id, profile); 760 dev_cfg->device_init(evm_id, profile);
761 else if (daughter_brd_detected == true) 761 else if (daughter_brd_detected == true)
762 dev_cfg->device_init(evm_id, profile); 762 dev_cfg->device_init(evm_id, profile);
763 } 763 }
764 } 764 }
765 } 765 }
766 } 766 }
767 767
768 #define AM335X_LCD_BL_PIN GPIO_TO_PIN(0, 7) 768 #define AM335X_LCD_BL_PIN GPIO_TO_PIN(0, 7)
769 769
770 /* pinmux for usb0 drvvbus */ 770 /* pinmux for usb0 drvvbus */
771 static struct pinmux_config usb0_pin_mux[] = { 771 static struct pinmux_config usb0_pin_mux[] = {
772 {"usb0_drvvbus.usb0_drvvbus", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, 772 {"usb0_drvvbus.usb0_drvvbus", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
773 {NULL, 0}, 773 {NULL, 0},
774 }; 774 };
775 775
776 /* pinmux for usb1 drvvbus */ 776 /* pinmux for usb1 drvvbus */
777 static struct pinmux_config usb1_pin_mux[] = { 777 static struct pinmux_config usb1_pin_mux[] = {
778 {"usb1_drvvbus.usb1_drvvbus", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, 778 {"usb1_drvvbus.usb1_drvvbus", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
779 {NULL, 0}, 779 {NULL, 0},
780 }; 780 };
781 781
782 /* pinmux for profibus */ 782 /* pinmux for profibus */
783 static struct pinmux_config profibus_pin_mux[] = { 783 static struct pinmux_config profibus_pin_mux[] = {
784 {"uart1_rxd.pr1_uart0_rxd_mux1", OMAP_MUX_MODE5 | AM33XX_PIN_INPUT}, 784 {"uart1_rxd.pr1_uart0_rxd_mux1", OMAP_MUX_MODE5 | AM33XX_PIN_INPUT},
785 {"uart1_txd.pr1_uart0_txd_mux1", OMAP_MUX_MODE5 | AM33XX_PIN_OUTPUT}, 785 {"uart1_txd.pr1_uart0_txd_mux1", OMAP_MUX_MODE5 | AM33XX_PIN_OUTPUT},
786 {"mcasp0_fsr.pr1_pru0_pru_r30_5", OMAP_MUX_MODE5 | AM33XX_PIN_OUTPUT}, 786 {"mcasp0_fsr.pr1_pru0_pru_r30_5", OMAP_MUX_MODE5 | AM33XX_PIN_OUTPUT},
787 {NULL, 0}, 787 {NULL, 0},
788 }; 788 };
789 789
790 /* Module pin mux for eCAP0 */ 790 /* Module pin mux for eCAP0 */
791 static struct pinmux_config ecap0_pin_mux[] = { 791 static struct pinmux_config ecap0_pin_mux[] = {
792 {"ecap0_in_pwm0_out.gpio0_7", AM33XX_PIN_OUTPUT}, 792 {"ecap0_in_pwm0_out.gpio0_7", AM33XX_PIN_OUTPUT},
793 {NULL, 0}, 793 {NULL, 0},
794 }; 794 };
795 795
796 #define AM335XEVM_WLAN_IRQ_GPIO GPIO_TO_PIN(3, 17) 796 #define AM335XEVM_WLAN_IRQ_GPIO GPIO_TO_PIN(3, 17)
797 797
798 struct wl12xx_platform_data am335xevm_wlan_data = { 798 struct wl12xx_platform_data am335xevm_wlan_data = {
799 .irq = OMAP_GPIO_IRQ(AM335XEVM_WLAN_IRQ_GPIO), 799 .irq = OMAP_GPIO_IRQ(AM335XEVM_WLAN_IRQ_GPIO),
800 .board_ref_clock = WL12XX_REFCLOCK_38_XTAL, /* 38.4Mhz */ 800 .board_ref_clock = WL12XX_REFCLOCK_38_XTAL, /* 38.4Mhz */
801 }; 801 };
802 802
803 /* Module pin mux for wlan and bluetooth */ 803 /* Module pin mux for wlan and bluetooth */
804 static struct pinmux_config mmc2_wl12xx_pin_mux[] = { 804 static struct pinmux_config mmc2_wl12xx_pin_mux[] = {
805 {"gpmc_a1.mmc2_dat0", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP}, 805 {"gpmc_a1.mmc2_dat0", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
806 {"gpmc_a2.mmc2_dat1", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP}, 806 {"gpmc_a2.mmc2_dat1", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
807 {"gpmc_a3.mmc2_dat2", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP}, 807 {"gpmc_a3.mmc2_dat2", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
808 {"gpmc_ben1.mmc2_dat3", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP}, 808 {"gpmc_ben1.mmc2_dat3", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
809 {"gpmc_csn3.mmc2_cmd", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP}, 809 {"gpmc_csn3.mmc2_cmd", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
810 {"gpmc_clk.mmc2_clk", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP}, 810 {"gpmc_clk.mmc2_clk", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
811 {NULL, 0}, 811 {NULL, 0},
812 }; 812 };
813 813
814 static struct pinmux_config uart1_wl12xx_pin_mux[] = { 814 static struct pinmux_config uart1_wl12xx_pin_mux[] = {
815 {"uart1_ctsn.uart1_ctsn", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, 815 {"uart1_ctsn.uart1_ctsn", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
816 {"uart1_rtsn.uart1_rtsn", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT}, 816 {"uart1_rtsn.uart1_rtsn", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT},
817 {"uart1_rxd.uart1_rxd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 817 {"uart1_rxd.uart1_rxd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
818 {"uart1_txd.uart1_txd", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL}, 818 {"uart1_txd.uart1_txd", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL},
819 {NULL, 0}, 819 {NULL, 0},
820 }; 820 };
821 821
822 static struct pinmux_config wl12xx_pin_mux_evm_rev1_1a[] = { 822 static struct pinmux_config wl12xx_pin_mux_evm_rev1_1a[] = {
823 {"gpmc_a0.gpio1_16", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT}, 823 {"gpmc_a0.gpio1_16", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
824 {"mcasp0_ahclkr.gpio3_17", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT}, 824 {"mcasp0_ahclkr.gpio3_17", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
825 {"mcasp0_ahclkx.gpio3_21", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT}, 825 {"mcasp0_ahclkx.gpio3_21", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
826 {NULL, 0}, 826 {NULL, 0},
827 }; 827 };
828 828
829 static struct pinmux_config wl12xx_pin_mux_evm_rev1_0[] = { 829 static struct pinmux_config wl12xx_pin_mux_evm_rev1_0[] = {
830 {"gpmc_csn1.gpio1_30", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT}, 830 {"gpmc_csn1.gpio1_30", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
831 {"mcasp0_ahclkr.gpio3_17", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT}, 831 {"mcasp0_ahclkr.gpio3_17", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
832 {"gpmc_csn2.gpio1_31", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT}, 832 {"gpmc_csn2.gpio1_31", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
833 {NULL, 0}, 833 {NULL, 0},
834 }; 834 };
835 835
836 static int backlight_enable = false; 836 static int backlight_enable = false;
837 837
838 static void enable_ecap0(int evm_id, int profile) 838 static void enable_ecap0(int evm_id, int profile)
839 { 839 {
840 backlight_enable = true; 840 backlight_enable = true;
841 } 841 }
842 842
843 static int __init ecap0_init(void) 843 static int __init ecap0_init(void)
844 { 844 {
845 int status = 0; 845 int status = 0;
846 846
847 if (backlight_enable) { 847 if (backlight_enable) {
848 setup_pin_mux(ecap0_pin_mux); 848 setup_pin_mux(ecap0_pin_mux);
849 849
850 status = gpio_request(AM335X_LCD_BL_PIN, "lcd bl\n"); 850 status = gpio_request(AM335X_LCD_BL_PIN, "lcd bl\n");
851 if (status < 0) 851 if (status < 0)
852 pr_warn("Failed to request gpio for LCD backlight\n"); 852 pr_warn("Failed to request gpio for LCD backlight\n");
853 853
854 gpio_direction_output(AM335X_LCD_BL_PIN, 1); 854 gpio_direction_output(AM335X_LCD_BL_PIN, 1);
855 } 855 }
856 return status; 856 return status;
857 } 857 }
858 late_initcall(ecap0_init); 858 late_initcall(ecap0_init);
859 859
860 static int __init conf_disp_pll(int rate) 860 static int __init conf_disp_pll(int rate)
861 { 861 {
862 struct clk *disp_pll; 862 struct clk *disp_pll;
863 int ret = -EINVAL; 863 int ret = -EINVAL;
864 864
865 disp_pll = clk_get(NULL, "dpll_disp_ck"); 865 disp_pll = clk_get(NULL, "dpll_disp_ck");
866 if (IS_ERR(disp_pll)) { 866 if (IS_ERR(disp_pll)) {
867 pr_err("Cannot clk_get disp_pll\n"); 867 pr_err("Cannot clk_get disp_pll\n");
868 goto out; 868 goto out;
869 } 869 }
870 870
871 ret = clk_set_rate(disp_pll, rate); 871 ret = clk_set_rate(disp_pll, rate);
872 clk_put(disp_pll); 872 clk_put(disp_pll);
873 out: 873 out:
874 return ret; 874 return ret;
875 } 875 }
876 876
877 static void lcdc_init(int evm_id, int profile) 877 static void lcdc_init(int evm_id, int profile)
878 { 878 {
879 879
880 setup_pin_mux(lcdc_pin_mux); 880 setup_pin_mux(lcdc_pin_mux);
881 881
882 if (conf_disp_pll(300000000)) { 882 if (conf_disp_pll(300000000)) {
883 pr_info("Failed configure display PLL, not attempting to" 883 pr_info("Failed configure display PLL, not attempting to"
884 "register LCDC\n"); 884 "register LCDC\n");
885 return; 885 return;
886 } 886 }
887 887
888 if (am33xx_register_lcdc(&TFC_S9700RTWV35TR_01B_pdata)) 888 if (am33xx_register_lcdc(&TFC_S9700RTWV35TR_01B_pdata))
889 pr_info("Failed to register LCDC device\n"); 889 pr_info("Failed to register LCDC device\n");
890 return; 890 return;
891 } 891 }
892 892
893 static void tsc_init(int evm_id, int profile) 893 static void tsc_init(int evm_id, int profile)
894 { 894 {
895 int err; 895 int err;
896 896
897 if (gp_evm_revision == GP_EVM_REV_IS_1_1A) { 897 if (gp_evm_revision == GP_EVM_REV_IS_1_1A) {
898 am335x_touchscreen_data.analog_input = 1; 898 am335x_touchscreen_data.analog_input = 1;
899 pr_info("TSC connected to beta GP EVM\n"); 899 pr_info("TSC connected to beta GP EVM\n");
900 } else { 900 } else {
901 am335x_touchscreen_data.analog_input = 0; 901 am335x_touchscreen_data.analog_input = 0;
902 pr_info("TSC connected to alpha GP EVM\n"); 902 pr_info("TSC connected to alpha GP EVM\n");
903 } 903 }
904 setup_pin_mux(tsc_pin_mux); 904 setup_pin_mux(tsc_pin_mux);
905 err = platform_device_register(&tsc_device); 905 err = platform_device_register(&tsc_device);
906 if (err) 906 if (err)
907 pr_err("failed to register touchscreen device\n"); 907 pr_err("failed to register touchscreen device\n");
908 } 908 }
909 909
910 static void rgmii1_init(int evm_id, int profile) 910 static void rgmii1_init(int evm_id, int profile)
911 { 911 {
912 setup_pin_mux(rgmii1_pin_mux); 912 setup_pin_mux(rgmii1_pin_mux);
913 return; 913 return;
914 } 914 }
915 915
916 static void rgmii2_init(int evm_id, int profile) 916 static void rgmii2_init(int evm_id, int profile)
917 { 917 {
918 setup_pin_mux(rgmii2_pin_mux); 918 setup_pin_mux(rgmii2_pin_mux);
919 return; 919 return;
920 } 920 }
921 921
922 static void mii1_init(int evm_id, int profile) 922 static void mii1_init(int evm_id, int profile)
923 { 923 {
924 setup_pin_mux(mii1_pin_mux); 924 setup_pin_mux(mii1_pin_mux);
925 return; 925 return;
926 } 926 }
927 927
928 static void rmii1_init(int evm_id, int profile) 928 static void rmii1_init(int evm_id, int profile)
929 { 929 {
930 setup_pin_mux(rmii1_pin_mux); 930 setup_pin_mux(rmii1_pin_mux);
931 return; 931 return;
932 } 932 }
933 933
934 static void usb0_init(int evm_id, int profile) 934 static void usb0_init(int evm_id, int profile)
935 { 935 {
936 setup_pin_mux(usb0_pin_mux); 936 setup_pin_mux(usb0_pin_mux);
937 return; 937 return;
938 } 938 }
939 939
940 static void usb1_init(int evm_id, int profile) 940 static void usb1_init(int evm_id, int profile)
941 { 941 {
942 setup_pin_mux(usb1_pin_mux); 942 setup_pin_mux(usb1_pin_mux);
943 return; 943 return;
944 } 944 }
945 945
946 /* setup uart3 */ 946 /* setup uart3 */
947 static void uart3_init(int evm_id, int profile) 947 static void uart3_init(int evm_id, int profile)
948 { 948 {
949 setup_pin_mux(uart3_pin_mux); 949 setup_pin_mux(uart3_pin_mux);
950 return; 950 return;
951 } 951 }
952 952
953 /* NAND partition information */ 953 /* NAND partition information */
954 static struct mtd_partition am335x_nand_partitions[] = { 954 static struct mtd_partition am335x_nand_partitions[] = {
955 /* All the partition sizes are listed in terms of NAND block size */ 955 /* All the partition sizes are listed in terms of NAND block size */
956 { 956 {
957 .name = "SPL", 957 .name = "SPL",
958 .offset = 0, /* Offset = 0x0 */ 958 .offset = 0, /* Offset = 0x0 */
959 .size = SZ_128K, 959 .size = SZ_128K,
960 }, 960 },
961 { 961 {
962 .name = "SPL.backup1", 962 .name = "SPL.backup1",
963 .offset = MTDPART_OFS_APPEND, /* Offset = 0x20000 */ 963 .offset = MTDPART_OFS_APPEND, /* Offset = 0x20000 */
964 .size = SZ_128K, 964 .size = SZ_128K,
965 }, 965 },
966 { 966 {
967 .name = "SPL.backup2", 967 .name = "SPL.backup2",
968 .offset = MTDPART_OFS_APPEND, /* Offset = 0x40000 */ 968 .offset = MTDPART_OFS_APPEND, /* Offset = 0x40000 */
969 .size = SZ_128K, 969 .size = SZ_128K,
970 }, 970 },
971 { 971 {
972 .name = "SPL.backup3", 972 .name = "SPL.backup3",
973 .offset = MTDPART_OFS_APPEND, /* Offset = 0x60000 */ 973 .offset = MTDPART_OFS_APPEND, /* Offset = 0x60000 */
974 .size = SZ_128K, 974 .size = SZ_128K,
975 }, 975 },
976 { 976 {
977 .name = "U-Boot", 977 .name = "U-Boot",
978 .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */ 978 .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */
979 .size = 15 * SZ_128K, 979 .size = 15 * SZ_128K,
980 }, 980 },
981 { 981 {
982 .name = "U-Boot Env", 982 .name = "U-Boot Env",
983 .offset = MTDPART_OFS_APPEND, /* Offset = 0x260000 */ 983 .offset = MTDPART_OFS_APPEND, /* Offset = 0x260000 */
984 .size = 1 * SZ_128K, 984 .size = 1 * SZ_128K,
985 }, 985 },
986 { 986 {
987 .name = "Kernel", 987 .name = "Kernel",
988 .offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */ 988 .offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */
989 .size = 40 * SZ_128K, 989 .size = 40 * SZ_128K,
990 }, 990 },
991 { 991 {
992 .name = "File System", 992 .name = "File System",
993 .offset = MTDPART_OFS_APPEND, /* Offset = 0x780000 */ 993 .offset = MTDPART_OFS_APPEND, /* Offset = 0x780000 */
994 .size = MTDPART_SIZ_FULL, 994 .size = MTDPART_SIZ_FULL,
995 }, 995 },
996 }; 996 };
997 997
998 /* SPI 0/1 Platform Data */ 998 /* SPI 0/1 Platform Data */
999 /* SPI flash information */ 999 /* SPI flash information */
1000 static struct mtd_partition am335x_spi_partitions[] = { 1000 static struct mtd_partition am335x_spi_partitions[] = {
1001 /* All the partition sizes are listed in terms of erase size */ 1001 /* All the partition sizes are listed in terms of erase size */
1002 { 1002 {
1003 .name = "U-Boot-min", 1003 .name = "U-Boot-min",
1004 .offset = 0, 1004 .offset = 0,
1005 .size = SZ_128K, 1005 .size = SZ_128K,
1006 .mask_flags = MTD_WRITEABLE, /* force read-only */ 1006 .mask_flags = MTD_WRITEABLE, /* force read-only */
1007 }, 1007 },
1008 { 1008 {
1009 .name = "U-Boot", 1009 .name = "U-Boot",
1010 .offset = MTDPART_OFS_APPEND, 1010 .offset = MTDPART_OFS_APPEND,
1011 .size = 2 * SZ_128K, 1011 .size = 2 * SZ_128K,
1012 .mask_flags = MTD_WRITEABLE, /* force read-only */ 1012 .mask_flags = MTD_WRITEABLE, /* force read-only */
1013 }, 1013 },
1014 { 1014 {
1015 .name = "U-Boot Env", 1015 .name = "U-Boot Env",
1016 .offset = MTDPART_OFS_APPEND, 1016 .offset = MTDPART_OFS_APPEND,
1017 .size = 2 * SZ_4K, 1017 .size = 2 * SZ_4K,
1018 }, 1018 },
1019 { 1019 {
1020 .name = "Kernel", 1020 .name = "Kernel",
1021 .offset = MTDPART_OFS_APPEND, 1021 .offset = MTDPART_OFS_APPEND,
1022 .size = 28 * SZ_128K, 1022 .size = 28 * SZ_128K,
1023 }, 1023 },
1024 { 1024 {
1025 .name = "File System", 1025 .name = "File System",
1026 .offset = MTDPART_OFS_APPEND, 1026 .offset = MTDPART_OFS_APPEND,
1027 .size = MTDPART_SIZ_FULL, /* size ~= 1.1 MiB */ 1027 .size = MTDPART_SIZ_FULL, /* size ~= 1.1 MiB */
1028 } 1028 }
1029 }; 1029 };
1030 1030
1031 static const struct flash_platform_data am335x_spi_flash = { 1031 static const struct flash_platform_data am335x_spi_flash = {
1032 .type = "w25q64", 1032 .type = "w25q64",
1033 .name = "spi_flash", 1033 .name = "spi_flash",
1034 .parts = am335x_spi_partitions, 1034 .parts = am335x_spi_partitions,
1035 .nr_parts = ARRAY_SIZE(am335x_spi_partitions), 1035 .nr_parts = ARRAY_SIZE(am335x_spi_partitions),
1036 }; 1036 };
1037 1037
1038 /* 1038 /*
1039 * SPI Flash works at 80Mhz however SPI Controller works at 48MHz. 1039 * SPI Flash works at 80Mhz however SPI Controller works at 48MHz.
1040 * So setup Max speed to be less than that of Controller speed 1040 * So setup Max speed to be less than that of Controller speed
1041 */ 1041 */
1042 static struct spi_board_info am335x_spi0_slave_info[] = { 1042 static struct spi_board_info am335x_spi0_slave_info[] = {
1043 { 1043 {
1044 .modalias = "m25p80", 1044 .modalias = "m25p80",
1045 .platform_data = &am335x_spi_flash, 1045 .platform_data = &am335x_spi_flash,
1046 .irq = -1, 1046 .irq = -1,
1047 .max_speed_hz = 24000000, 1047 .max_speed_hz = 24000000,
1048 .bus_num = 1, 1048 .bus_num = 1,
1049 .chip_select = 0, 1049 .chip_select = 0,
1050 }, 1050 },
1051 }; 1051 };
1052 1052
1053 static struct spi_board_info am335x_spi1_slave_info[] = { 1053 static struct spi_board_info am335x_spi1_slave_info[] = {
1054 { 1054 {
1055 .modalias = "m25p80", 1055 .modalias = "m25p80",
1056 .platform_data = &am335x_spi_flash, 1056 .platform_data = &am335x_spi_flash,
1057 .irq = -1, 1057 .irq = -1,
1058 .max_speed_hz = 12000000, 1058 .max_speed_hz = 12000000,
1059 .bus_num = 2, 1059 .bus_num = 2,
1060 .chip_select = 0, 1060 .chip_select = 0,
1061 }, 1061 },
1062 }; 1062 };
1063 1063
1064 static void evm_nand_init(int evm_id, int profile) 1064 static void evm_nand_init(int evm_id, int profile)
1065 { 1065 {
1066 setup_pin_mux(nand_pin_mux); 1066 setup_pin_mux(nand_pin_mux);
1067 board_nand_init(am335x_nand_partitions, 1067 board_nand_init(am335x_nand_partitions,
1068 ARRAY_SIZE(am335x_nand_partitions), 0, 0); 1068 ARRAY_SIZE(am335x_nand_partitions), 0, 0);
1069 } 1069 }
1070 1070
1071 static struct lis3lv02d_platform_data lis331dlh_pdata = { 1071 static struct lis3lv02d_platform_data lis331dlh_pdata = {
1072 .click_flags = LIS3_CLICK_SINGLE_X | 1072 .click_flags = LIS3_CLICK_SINGLE_X |
1073 LIS3_CLICK_SINGLE_Y | 1073 LIS3_CLICK_SINGLE_Y |
1074 LIS3_CLICK_SINGLE_Z, 1074 LIS3_CLICK_SINGLE_Z,
1075 .wakeup_flags = LIS3_WAKEUP_X_LO | LIS3_WAKEUP_X_HI | 1075 .wakeup_flags = LIS3_WAKEUP_X_LO | LIS3_WAKEUP_X_HI |
1076 LIS3_WAKEUP_Y_LO | LIS3_WAKEUP_Y_HI | 1076 LIS3_WAKEUP_Y_LO | LIS3_WAKEUP_Y_HI |
1077 LIS3_WAKEUP_Z_LO | LIS3_WAKEUP_Z_HI, 1077 LIS3_WAKEUP_Z_LO | LIS3_WAKEUP_Z_HI,
1078 .irq_cfg = LIS3_IRQ1_CLICK | LIS3_IRQ2_CLICK, 1078 .irq_cfg = LIS3_IRQ1_CLICK | LIS3_IRQ2_CLICK,
1079 .wakeup_thresh = 10, 1079 .wakeup_thresh = 10,
1080 .click_thresh_x = 10, 1080 .click_thresh_x = 10,
1081 .click_thresh_y = 10, 1081 .click_thresh_y = 10,
1082 .click_thresh_z = 10, 1082 .click_thresh_z = 10,
1083 .g_range = 2, 1083 .g_range = 2,
1084 .st_min_limits[0] = 120, 1084 .st_min_limits[0] = 120,
1085 .st_min_limits[1] = 120, 1085 .st_min_limits[1] = 120,
1086 .st_min_limits[2] = 140, 1086 .st_min_limits[2] = 140,
1087 .st_max_limits[0] = 550, 1087 .st_max_limits[0] = 550,
1088 .st_max_limits[1] = 550, 1088 .st_max_limits[1] = 550,
1089 .st_max_limits[2] = 750, 1089 .st_max_limits[2] = 750,
1090 }; 1090 };
1091 1091
1092 static struct i2c_board_info am335x_i2c_boardinfo1[] = { 1092 static struct i2c_board_info am335x_i2c_boardinfo1[] = {
1093 { 1093 {
1094 I2C_BOARD_INFO("tlv320aic3x", 0x1b), 1094 I2C_BOARD_INFO("tlv320aic3x", 0x1b),
1095 }, 1095 },
1096 { 1096 {
1097 I2C_BOARD_INFO("lis331dlh", 0x18), 1097 I2C_BOARD_INFO("lis331dlh", 0x18),
1098 .platform_data = &lis331dlh_pdata, 1098 .platform_data = &lis331dlh_pdata,
1099 }, 1099 },
1100 { 1100 {
1101 I2C_BOARD_INFO("tsl2550", 0x39), 1101 I2C_BOARD_INFO("tsl2550", 0x39),
1102 }, 1102 },
1103 { 1103 {
1104 I2C_BOARD_INFO("tmp275", 0x48), 1104 I2C_BOARD_INFO("tmp275", 0x48),
1105 }, 1105 },
1106 }; 1106 };
1107 1107
1108 static void i2c1_init(int evm_id, int profile) 1108 static void i2c1_init(int evm_id, int profile)
1109 { 1109 {
1110 setup_pin_mux(i2c1_pin_mux); 1110 setup_pin_mux(i2c1_pin_mux);
1111 omap_register_i2c_bus(2, 100, am335x_i2c_boardinfo1, 1111 omap_register_i2c_bus(2, 100, am335x_i2c_boardinfo1,
1112 ARRAY_SIZE(am335x_i2c_boardinfo1)); 1112 ARRAY_SIZE(am335x_i2c_boardinfo1));
1113 return; 1113 return;
1114 } 1114 }
1115 1115
1116 /* Setup McASP 1 */ 1116 /* Setup McASP 1 */
1117 static void mcasp1_init(int evm_id, int profile) 1117 static void mcasp1_init(int evm_id, int profile)
1118 { 1118 {
1119 /* Configure McASP */ 1119 /* Configure McASP */
1120 setup_pin_mux(mcasp1_pin_mux); 1120 setup_pin_mux(mcasp1_pin_mux);
1121 am335x_register_mcasp1(&am335x_evm_snd_data1); 1121 am335x_register_mcasp1(&am335x_evm_snd_data1);
1122 return; 1122 return;
1123 } 1123 }
1124 1124
1125 static void mmc1_init(int evm_id, int profile) 1125 static void mmc1_init(int evm_id, int profile)
1126 { 1126 {
1127 setup_pin_mux(mmc1_pin_mux); 1127 setup_pin_mux(mmc1_pin_mux);
1128 1128
1129 am335x_mmc[1].mmc = 2; 1129 am335x_mmc[1].mmc = 2;
1130 am335x_mmc[1].caps = MMC_CAP_4_BIT_DATA; 1130 am335x_mmc[1].caps = MMC_CAP_4_BIT_DATA;
1131 am335x_mmc[1].gpio_cd = GPIO_TO_PIN(3, 15); 1131 am335x_mmc[1].gpio_cd = GPIO_TO_PIN(3, 15);
1132 am335x_mmc[1].gpio_wp = GPIO_TO_PIN(0, 14); 1132 am335x_mmc[1].gpio_wp = GPIO_TO_PIN(0, 14);
1133 am335x_mmc[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */ 1133 am335x_mmc[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */
1134 1134
1135 /* mmc will be initialized when mmc0_init is called */ 1135 /* mmc will be initialized when mmc0_init is called */
1136 return; 1136 return;
1137 } 1137 }
1138 1138
1139 static void mmc2_wl12xx_init(int evm_id, int profile) 1139 static void mmc2_wl12xx_init(int evm_id, int profile)
1140 { 1140 {
1141 setup_pin_mux(mmc2_wl12xx_pin_mux); 1141 setup_pin_mux(mmc2_wl12xx_pin_mux);
1142 1142
1143 am335x_mmc[1].mmc = 3; 1143 am335x_mmc[1].mmc = 3;
1144 am335x_mmc[1].name = "wl1271"; 1144 am335x_mmc[1].name = "wl1271";
1145 am335x_mmc[1].caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD 1145 am335x_mmc[1].caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD
1146 | MMC_PM_KEEP_POWER; 1146 | MMC_PM_KEEP_POWER;
1147 am335x_mmc[1].nonremovable = true; 1147 am335x_mmc[1].nonremovable = true;
1148 am335x_mmc[1].gpio_cd = -EINVAL; 1148 am335x_mmc[1].gpio_cd = -EINVAL;
1149 am335x_mmc[1].gpio_wp = -EINVAL; 1149 am335x_mmc[1].gpio_wp = -EINVAL;
1150 am335x_mmc[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */ 1150 am335x_mmc[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */
1151 1151
1152 /* mmc will be initialized when mmc0_init is called */ 1152 /* mmc will be initialized when mmc0_init is called */
1153 return; 1153 return;
1154 } 1154 }
1155 1155
1156 static void uart1_wl12xx_init(int evm_id, int profile) 1156 static void uart1_wl12xx_init(int evm_id, int profile)
1157 { 1157 {
1158 setup_pin_mux(uart1_wl12xx_pin_mux); 1158 setup_pin_mux(uart1_wl12xx_pin_mux);
1159 } 1159 }
1160 1160
1161 static void wl12xx_bluetooth_enable(void) 1161 static void wl12xx_bluetooth_enable(void)
1162 { 1162 {
1163 int status = gpio_request(am335xevm_wlan_data.bt_enable_gpio, 1163 int status = gpio_request(am335xevm_wlan_data.bt_enable_gpio,
1164 "bt_en\n"); 1164 "bt_en\n");
1165 if (status < 0) 1165 if (status < 0)
1166 pr_err("Failed to request gpio for bt_enable"); 1166 pr_err("Failed to request gpio for bt_enable");
1167 1167
1168 pr_info("Configure Bluetooth Enable pin...\n"); 1168 pr_info("Configure Bluetooth Enable pin...\n");
1169 gpio_direction_output(am335xevm_wlan_data.bt_enable_gpio, 0); 1169 gpio_direction_output(am335xevm_wlan_data.bt_enable_gpio, 0);
1170 } 1170 }
1171 1171
1172 static int wl12xx_set_power(struct device *dev, int slot, int on, int vdd) 1172 static int wl12xx_set_power(struct device *dev, int slot, int on, int vdd)
1173 { 1173 {
1174 if (on) { 1174 if (on) {
1175 gpio_set_value(am335xevm_wlan_data.wlan_enable_gpio, 1); 1175 gpio_set_value(am335xevm_wlan_data.wlan_enable_gpio, 1);
1176 mdelay(70); 1176 mdelay(70);
1177 } 1177 }
1178 else 1178 else
1179 gpio_set_value(am335xevm_wlan_data.wlan_enable_gpio, 0); 1179 gpio_set_value(am335xevm_wlan_data.wlan_enable_gpio, 0);
1180 1180
1181 return 0; 1181 return 0;
1182 } 1182 }
1183 1183
1184 static void wl12xx_init(int evm_id, int profile) 1184 static void wl12xx_init(int evm_id, int profile)
1185 { 1185 {
1186 struct device *dev; 1186 struct device *dev;
1187 struct omap_mmc_platform_data *pdata; 1187 struct omap_mmc_platform_data *pdata;
1188 int ret; 1188 int ret;
1189 1189
1190 /* Register WLAN and BT enable pins based on the evm board revision */ 1190 /* Register WLAN and BT enable pins based on the evm board revision */
1191 if (gp_evm_revision == GP_EVM_REV_IS_1_1A) { 1191 if (gp_evm_revision == GP_EVM_REV_IS_1_1A) {
1192 am335xevm_wlan_data.wlan_enable_gpio = GPIO_TO_PIN(1, 16); 1192 am335xevm_wlan_data.wlan_enable_gpio = GPIO_TO_PIN(1, 16);
1193 am335xevm_wlan_data.bt_enable_gpio = GPIO_TO_PIN(3, 21); 1193 am335xevm_wlan_data.bt_enable_gpio = GPIO_TO_PIN(3, 21);
1194 } 1194 }
1195 else { 1195 else {
1196 am335xevm_wlan_data.wlan_enable_gpio = GPIO_TO_PIN(1, 30); 1196 am335xevm_wlan_data.wlan_enable_gpio = GPIO_TO_PIN(1, 30);
1197 am335xevm_wlan_data.bt_enable_gpio = GPIO_TO_PIN(1, 31); 1197 am335xevm_wlan_data.bt_enable_gpio = GPIO_TO_PIN(1, 31);
1198 } 1198 }
1199 1199
1200 wl12xx_bluetooth_enable(); 1200 wl12xx_bluetooth_enable();
1201 1201
1202 if (wl12xx_set_platform_data(&am335xevm_wlan_data)) 1202 if (wl12xx_set_platform_data(&am335xevm_wlan_data))
1203 pr_err("error setting wl12xx data\n"); 1203 pr_err("error setting wl12xx data\n");
1204 1204
1205 dev = am335x_mmc[1].dev; 1205 dev = am335x_mmc[1].dev;
1206 if (!dev) { 1206 if (!dev) {
1207 pr_err("wl12xx mmc device initialization failed\n"); 1207 pr_err("wl12xx mmc device initialization failed\n");
1208 goto out; 1208 goto out;
1209 } 1209 }
1210 1210
1211 pdata = dev->platform_data; 1211 pdata = dev->platform_data;
1212 if (!pdata) { 1212 if (!pdata) {
1213 pr_err("Platfrom data of wl12xx device not set\n"); 1213 pr_err("Platfrom data of wl12xx device not set\n");
1214 goto out; 1214 goto out;
1215 } 1215 }
1216 1216
1217 ret = gpio_request_one(am335xevm_wlan_data.wlan_enable_gpio, 1217 ret = gpio_request_one(am335xevm_wlan_data.wlan_enable_gpio,
1218 GPIOF_OUT_INIT_LOW, "wlan_en"); 1218 GPIOF_OUT_INIT_LOW, "wlan_en");
1219 if (ret) { 1219 if (ret) {
1220 pr_err("Error requesting wlan enable gpio: %d\n", ret); 1220 pr_err("Error requesting wlan enable gpio: %d\n", ret);
1221 goto out; 1221 goto out;
1222 } 1222 }
1223 1223
1224 if (gp_evm_revision == GP_EVM_REV_IS_1_1A) 1224 if (gp_evm_revision == GP_EVM_REV_IS_1_1A)
1225 setup_pin_mux(wl12xx_pin_mux_evm_rev1_1a); 1225 setup_pin_mux(wl12xx_pin_mux_evm_rev1_1a);
1226 else 1226 else
1227 setup_pin_mux(wl12xx_pin_mux_evm_rev1_0); 1227 setup_pin_mux(wl12xx_pin_mux_evm_rev1_0);
1228 1228
1229 pdata->slots[0].set_power = wl12xx_set_power; 1229 pdata->slots[0].set_power = wl12xx_set_power;
1230 out: 1230 out:
1231 return; 1231 return;
1232 } 1232 }
1233 1233
1234 static void d_can_init(int evm_id, int profile) 1234 static void d_can_init(int evm_id, int profile)
1235 { 1235 {
1236 switch (evm_id) { 1236 switch (evm_id) {
1237 case IND_AUT_MTR_EVM: 1237 case IND_AUT_MTR_EVM:
1238 if ((profile == PROFILE_0) || (profile == PROFILE_1)) { 1238 if ((profile == PROFILE_0) || (profile == PROFILE_1)) {
1239 setup_pin_mux(d_can_ia_pin_mux); 1239 setup_pin_mux(d_can_ia_pin_mux);
1240 /* Instance Zero */ 1240 /* Instance Zero */
1241 am33xx_d_can_init(0); 1241 am33xx_d_can_init(0);
1242 } 1242 }
1243 break; 1243 break;
1244 case GEN_PURP_EVM: 1244 case GEN_PURP_EVM:
1245 if (profile == PROFILE_1) { 1245 if (profile == PROFILE_1) {
1246 setup_pin_mux(d_can_gp_pin_mux); 1246 setup_pin_mux(d_can_gp_pin_mux);
1247 /* Instance One */ 1247 /* Instance One */
1248 am33xx_d_can_init(1); 1248 am33xx_d_can_init(1);
1249 } 1249 }
1250 break; 1250 break;
1251 default: 1251 default:
1252 break; 1252 break;
1253 } 1253 }
1254 } 1254 }
1255 1255
1256 static void mmc0_init(int evm_id, int profile) 1256 static void mmc0_init(int evm_id, int profile)
1257 { 1257 {
1258 setup_pin_mux(mmc0_pin_mux); 1258 setup_pin_mux(mmc0_pin_mux);
1259 1259
1260 omap2_hsmmc_init(am335x_mmc); 1260 omap2_hsmmc_init(am335x_mmc);
1261 return; 1261 return;
1262 } 1262 }
1263 1263
1264 static void mmc0_no_cd_init(int evm_id, int profile) 1264 static void mmc0_no_cd_init(int evm_id, int profile)
1265 { 1265 {
1266 setup_pin_mux(mmc0_no_cd_pin_mux); 1266 setup_pin_mux(mmc0_no_cd_pin_mux);
1267 1267
1268 omap2_hsmmc_init(am335x_mmc); 1268 omap2_hsmmc_init(am335x_mmc);
1269 return; 1269 return;
1270 } 1270 }
1271 1271
1272 1272
1273 /* setup spi0 */ 1273 /* setup spi0 */
1274 static void spi0_init(int evm_id, int profile) 1274 static void spi0_init(int evm_id, int profile)
1275 { 1275 {
1276 setup_pin_mux(spi0_pin_mux); 1276 setup_pin_mux(spi0_pin_mux);
1277 spi_register_board_info(am335x_spi0_slave_info, 1277 spi_register_board_info(am335x_spi0_slave_info,
1278 ARRAY_SIZE(am335x_spi0_slave_info)); 1278 ARRAY_SIZE(am335x_spi0_slave_info));
1279 return; 1279 return;
1280 } 1280 }
1281 1281
1282 /* setup spi1 */ 1282 /* setup spi1 */
1283 static void spi1_init(int evm_id, int profile) 1283 static void spi1_init(int evm_id, int profile)
1284 { 1284 {
1285 setup_pin_mux(spi1_pin_mux); 1285 setup_pin_mux(spi1_pin_mux);
1286 spi_register_board_info(am335x_spi1_slave_info, 1286 spi_register_board_info(am335x_spi1_slave_info,
1287 ARRAY_SIZE(am335x_spi1_slave_info)); 1287 ARRAY_SIZE(am335x_spi1_slave_info));
1288 return; 1288 return;
1289 } 1289 }
1290 1290
1291 1291
1292 static int beaglebone_phy_fixup(struct phy_device *phydev) 1292 static int beaglebone_phy_fixup(struct phy_device *phydev)
1293 { 1293 {
1294 phydev->supported &= ~(SUPPORTED_100baseT_Half | 1294 phydev->supported &= ~(SUPPORTED_100baseT_Half |
1295 SUPPORTED_100baseT_Full); 1295 SUPPORTED_100baseT_Full);
1296 1296
1297 return 0; 1297 return 0;
1298 } 1298 }
1299 1299
1300 #ifdef CONFIG_TLK110_WORKAROUND 1300 #ifdef CONFIG_TLK110_WORKAROUND
1301 static int am335x_tlk110_phy_fixup(struct phy_device *phydev) 1301 static int am335x_tlk110_phy_fixup(struct phy_device *phydev)
1302 { 1302 {
1303 unsigned int val; 1303 unsigned int val;
1304 1304
1305 /* This is done as a workaround to support TLK110 rev1.0 phy */ 1305 /* This is done as a workaround to support TLK110 rev1.0 phy */
1306 val = phy_read(phydev, TLK110_COARSEGAIN_REG); 1306 val = phy_read(phydev, TLK110_COARSEGAIN_REG);
1307 phy_write(phydev, TLK110_COARSEGAIN_REG, (val | TLK110_COARSEGAIN_VAL)); 1307 phy_write(phydev, TLK110_COARSEGAIN_REG, (val | TLK110_COARSEGAIN_VAL));
1308 1308
1309 val = phy_read(phydev, TLK110_LPFHPF_REG); 1309 val = phy_read(phydev, TLK110_LPFHPF_REG);
1310 phy_write(phydev, TLK110_LPFHPF_REG, (val | TLK110_LPFHPF_VAL)); 1310 phy_write(phydev, TLK110_LPFHPF_REG, (val | TLK110_LPFHPF_VAL));
1311 1311
1312 val = phy_read(phydev, TLK110_SPAREANALOG_REG); 1312 val = phy_read(phydev, TLK110_SPAREANALOG_REG);
1313 phy_write(phydev, TLK110_SPAREANALOG_REG, (val | TLK110_SPANALOG_VAL)); 1313 phy_write(phydev, TLK110_SPAREANALOG_REG, (val | TLK110_SPANALOG_VAL));
1314 1314
1315 val = phy_read(phydev, TLK110_VRCR_REG); 1315 val = phy_read(phydev, TLK110_VRCR_REG);
1316 phy_write(phydev, TLK110_VRCR_REG, (val | TLK110_VRCR_VAL)); 1316 phy_write(phydev, TLK110_VRCR_REG, (val | TLK110_VRCR_VAL));
1317 1317
1318 val = phy_read(phydev, TLK110_SETFFE_REG); 1318 val = phy_read(phydev, TLK110_SETFFE_REG);
1319 phy_write(phydev, TLK110_SETFFE_REG, (val | TLK110_SETFFE_VAL)); 1319 phy_write(phydev, TLK110_SETFFE_REG, (val | TLK110_SETFFE_VAL));
1320 1320
1321 val = phy_read(phydev, TLK110_FTSP_REG); 1321 val = phy_read(phydev, TLK110_FTSP_REG);
1322 phy_write(phydev, TLK110_FTSP_REG, (val | TLK110_FTSP_VAL)); 1322 phy_write(phydev, TLK110_FTSP_REG, (val | TLK110_FTSP_VAL));
1323 1323
1324 val = phy_read(phydev, TLK110_ALFATPIDL_REG); 1324 val = phy_read(phydev, TLK110_ALFATPIDL_REG);
1325 phy_write(phydev, TLK110_ALFATPIDL_REG, (val | TLK110_ALFATPIDL_VAL)); 1325 phy_write(phydev, TLK110_ALFATPIDL_REG, (val | TLK110_ALFATPIDL_VAL));
1326 1326
1327 val = phy_read(phydev, TLK110_PSCOEF21_REG); 1327 val = phy_read(phydev, TLK110_PSCOEF21_REG);
1328 phy_write(phydev, TLK110_PSCOEF21_REG, (val | TLK110_PSCOEF21_VAL)); 1328 phy_write(phydev, TLK110_PSCOEF21_REG, (val | TLK110_PSCOEF21_VAL));
1329 1329
1330 val = phy_read(phydev, TLK110_PSCOEF3_REG); 1330 val = phy_read(phydev, TLK110_PSCOEF3_REG);
1331 phy_write(phydev, TLK110_PSCOEF3_REG, (val | TLK110_PSCOEF3_VAL)); 1331 phy_write(phydev, TLK110_PSCOEF3_REG, (val | TLK110_PSCOEF3_VAL));
1332 1332
1333 val = phy_read(phydev, TLK110_ALFAFACTOR1_REG); 1333 val = phy_read(phydev, TLK110_ALFAFACTOR1_REG);
1334 phy_write(phydev, TLK110_ALFAFACTOR1_REG, (val | TLK110_ALFACTOR1_VAL)); 1334 phy_write(phydev, TLK110_ALFAFACTOR1_REG, (val | TLK110_ALFACTOR1_VAL));
1335 1335
1336 val = phy_read(phydev, TLK110_ALFAFACTOR2_REG); 1336 val = phy_read(phydev, TLK110_ALFAFACTOR2_REG);
1337 phy_write(phydev, TLK110_ALFAFACTOR2_REG, (val | TLK110_ALFACTOR2_VAL)); 1337 phy_write(phydev, TLK110_ALFAFACTOR2_REG, (val | TLK110_ALFACTOR2_VAL));
1338 1338
1339 val = phy_read(phydev, TLK110_CFGPS_REG); 1339 val = phy_read(phydev, TLK110_CFGPS_REG);
1340 phy_write(phydev, TLK110_CFGPS_REG, (val | TLK110_CFGPS_VAL)); 1340 phy_write(phydev, TLK110_CFGPS_REG, (val | TLK110_CFGPS_VAL));
1341 1341
1342 val = phy_read(phydev, TLK110_FTSPTXGAIN_REG); 1342 val = phy_read(phydev, TLK110_FTSPTXGAIN_REG);
1343 phy_write(phydev, TLK110_FTSPTXGAIN_REG, (val | TLK110_FTSPTXGAIN_VAL)); 1343 phy_write(phydev, TLK110_FTSPTXGAIN_REG, (val | TLK110_FTSPTXGAIN_VAL));
1344 1344
1345 val = phy_read(phydev, TLK110_SWSCR3_REG); 1345 val = phy_read(phydev, TLK110_SWSCR3_REG);
1346 phy_write(phydev, TLK110_SWSCR3_REG, (val | TLK110_SWSCR3_VAL)); 1346 phy_write(phydev, TLK110_SWSCR3_REG, (val | TLK110_SWSCR3_VAL));
1347 1347
1348 val = phy_read(phydev, TLK110_SCFALLBACK_REG); 1348 val = phy_read(phydev, TLK110_SCFALLBACK_REG);
1349 phy_write(phydev, TLK110_SCFALLBACK_REG, (val | TLK110_SCFALLBACK_VAL)); 1349 phy_write(phydev, TLK110_SCFALLBACK_REG, (val | TLK110_SCFALLBACK_VAL));
1350 1350
1351 val = phy_read(phydev, TLK110_PHYRCR_REG); 1351 val = phy_read(phydev, TLK110_PHYRCR_REG);
1352 phy_write(phydev, TLK110_PHYRCR_REG, (val | TLK110_PHYRCR_VAL)); 1352 phy_write(phydev, TLK110_PHYRCR_REG, (val | TLK110_PHYRCR_VAL));
1353 1353
1354 return 0; 1354 return 0;
1355 } 1355 }
1356 #endif 1356 #endif
1357 1357
1358 static void profibus_init(int evm_id, int profile) 1358 static void profibus_init(int evm_id, int profile)
1359 { 1359 {
1360 setup_pin_mux(profibus_pin_mux); 1360 setup_pin_mux(profibus_pin_mux);
1361 return; 1361 return;
1362 } 1362 }
1363 1363
1364 /* Low-Cost EVM */ 1364 /* Low-Cost EVM */
1365 static struct evm_dev_cfg low_cost_evm_dev_cfg[] = { 1365 static struct evm_dev_cfg low_cost_evm_dev_cfg[] = {
1366 {rgmii1_init, DEV_ON_BASEBOARD, PROFILE_NONE}, 1366 {rgmii1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1367 {usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE}, 1367 {usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1368 {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE}, 1368 {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1369 {evm_nand_init, DEV_ON_BASEBOARD, PROFILE_NONE}, 1369 {evm_nand_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1370 {NULL, 0, 0}, 1370 {NULL, 0, 0},
1371 }; 1371 };
1372 1372
1373 /* General Purpose EVM */ 1373 /* General Purpose EVM */
1374 static struct evm_dev_cfg gen_purp_evm_dev_cfg[] = { 1374 static struct evm_dev_cfg gen_purp_evm_dev_cfg[] = {
1375 {enable_ecap0, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 | 1375 {enable_ecap0, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 |
1376 PROFILE_2 | PROFILE_7) }, 1376 PROFILE_2 | PROFILE_7) },
1377 {lcdc_init, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 | 1377 {lcdc_init, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 |
1378 PROFILE_2 | PROFILE_7) }, 1378 PROFILE_2 | PROFILE_7) },
1379 {tsc_init, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 | 1379 {tsc_init, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 |
1380 PROFILE_2 | PROFILE_7) }, 1380 PROFILE_2 | PROFILE_7) },
1381 {rgmii1_init, DEV_ON_BASEBOARD, PROFILE_ALL}, 1381 {rgmii1_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1382 {rgmii2_init, DEV_ON_DGHTR_BRD, (PROFILE_1 | PROFILE_2 | 1382 {rgmii2_init, DEV_ON_DGHTR_BRD, (PROFILE_1 | PROFILE_2 |
1383 PROFILE_4 | PROFILE_6) }, 1383 PROFILE_4 | PROFILE_6) },
1384 {usb0_init, DEV_ON_BASEBOARD, PROFILE_ALL}, 1384 {usb0_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1385 {usb1_init, DEV_ON_BASEBOARD, PROFILE_ALL}, 1385 {usb1_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1386 {evm_nand_init, DEV_ON_DGHTR_BRD, 1386 {evm_nand_init, DEV_ON_DGHTR_BRD,
1387 (PROFILE_ALL & ~PROFILE_2 & ~PROFILE_3)}, 1387 (PROFILE_ALL & ~PROFILE_2 & ~PROFILE_3)},
1388 {i2c1_init, DEV_ON_DGHTR_BRD, (PROFILE_ALL & ~PROFILE_2)}, 1388 {i2c1_init, DEV_ON_DGHTR_BRD, (PROFILE_ALL & ~PROFILE_2)},
1389 {mcasp1_init, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_3 | PROFILE_7) }, 1389 {mcasp1_init, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_3 | PROFILE_7) },
1390 {mmc1_init, DEV_ON_DGHTR_BRD, PROFILE_2}, 1390 {mmc1_init, DEV_ON_DGHTR_BRD, PROFILE_2},
1391 {mmc2_wl12xx_init, DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 | 1391 {mmc2_wl12xx_init, DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 |
1392 PROFILE_5)}, 1392 PROFILE_5)},
1393 {mmc0_init, DEV_ON_BASEBOARD, (PROFILE_ALL & ~PROFILE_5)}, 1393 {mmc0_init, DEV_ON_BASEBOARD, (PROFILE_ALL & ~PROFILE_5)},
1394 {mmc0_no_cd_init, DEV_ON_BASEBOARD, PROFILE_5}, 1394 {mmc0_no_cd_init, DEV_ON_BASEBOARD, PROFILE_5},
1395 {spi0_init, DEV_ON_DGHTR_BRD, PROFILE_2}, 1395 {spi0_init, DEV_ON_DGHTR_BRD, PROFILE_2},
1396 {uart1_wl12xx_init, DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 | 1396 {uart1_wl12xx_init, DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 |
1397 PROFILE_5)}, 1397 PROFILE_5)},
1398 {wl12xx_init, DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 | PROFILE_5)}, 1398 {wl12xx_init, DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 | PROFILE_5)},
1399 {d_can_init, DEV_ON_DGHTR_BRD, PROFILE_1}, 1399 {d_can_init, DEV_ON_DGHTR_BRD, PROFILE_1},
1400 #ifdef CONFIG_KEYBOARD_MATRIX 1400 #ifdef CONFIG_KEYBOARD_MATRIX
1401 {matrix_keypad_init, DEV_ON_DGHTR_BRD, PROFILE_0}, 1401 {matrix_keypad_init, DEV_ON_DGHTR_BRD, PROFILE_0},
1402 #endif 1402 #endif
1403 #ifdef CONFIG_KEYBOARD_GPIO 1403 #ifdef CONFIG_KEYBOARD_GPIO
1404 {volume_keys_init, DEV_ON_DGHTR_BRD, PROFILE_0}, 1404 {volume_keys_init, DEV_ON_DGHTR_BRD, PROFILE_0},
1405 #endif 1405 #endif
1406 {NULL, 0, 0}, 1406 {NULL, 0, 0},
1407 }; 1407 };
1408 1408
1409 /* Industrial Auto Motor Control EVM */ 1409 /* Industrial Auto Motor Control EVM */
1410 static struct evm_dev_cfg ind_auto_mtrl_evm_dev_cfg[] = { 1410 static struct evm_dev_cfg ind_auto_mtrl_evm_dev_cfg[] = {
1411 {mii1_init, DEV_ON_DGHTR_BRD, PROFILE_ALL}, 1411 {mii1_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
1412 {usb0_init, DEV_ON_BASEBOARD, PROFILE_ALL}, 1412 {usb0_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1413 {usb1_init, DEV_ON_BASEBOARD, PROFILE_ALL}, 1413 {usb1_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1414 {profibus_init, DEV_ON_DGHTR_BRD, PROFILE_ALL}, 1414 {profibus_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
1415 {evm_nand_init, DEV_ON_DGHTR_BRD, PROFILE_ALL}, 1415 {evm_nand_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
1416 {spi1_init, DEV_ON_DGHTR_BRD, PROFILE_ALL}, 1416 {spi1_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
1417 {uart3_init, DEV_ON_DGHTR_BRD, PROFILE_ALL}, 1417 {uart3_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
1418 {i2c1_init, DEV_ON_BASEBOARD, PROFILE_ALL}, 1418 {i2c1_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1419 {mmc0_no_cd_init, DEV_ON_BASEBOARD, PROFILE_ALL}, 1419 {mmc0_no_cd_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1420 {NULL, 0, 0}, 1420 {NULL, 0, 0},
1421 }; 1421 };
1422 1422
1423 /* IP-Phone EVM */ 1423 /* IP-Phone EVM */
1424 static struct evm_dev_cfg ip_phn_evm_dev_cfg[] = { 1424 static struct evm_dev_cfg ip_phn_evm_dev_cfg[] = {
1425 {enable_ecap0, DEV_ON_DGHTR_BRD, PROFILE_NONE}, 1425 {enable_ecap0, DEV_ON_DGHTR_BRD, PROFILE_NONE},
1426 {lcdc_init, DEV_ON_DGHTR_BRD, PROFILE_NONE}, 1426 {lcdc_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
1427 {tsc_init, DEV_ON_DGHTR_BRD, PROFILE_NONE}, 1427 {tsc_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
1428 {rgmii1_init, DEV_ON_BASEBOARD, PROFILE_NONE}, 1428 {rgmii1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1429 {rgmii2_init, DEV_ON_DGHTR_BRD, PROFILE_NONE}, 1429 {rgmii2_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
1430 {usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE}, 1430 {usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1431 {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE}, 1431 {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1432 {evm_nand_init, DEV_ON_DGHTR_BRD, PROFILE_NONE}, 1432 {evm_nand_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
1433 {i2c1_init, DEV_ON_BASEBOARD, PROFILE_NONE}, 1433 {i2c1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1434 {mcasp1_init, DEV_ON_DGHTR_BRD, PROFILE_NONE}, 1434 {mcasp1_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
1435 {mmc0_init, DEV_ON_BASEBOARD, PROFILE_NONE}, 1435 {mmc0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1436 {NULL, 0, 0}, 1436 {NULL, 0, 0},
1437 }; 1437 };
1438 1438
1439 /* Beaglebone < Rev A3 */ 1439 /* Beaglebone < Rev A3 */
1440 static struct evm_dev_cfg beaglebone_old_dev_cfg[] = { 1440 static struct evm_dev_cfg beaglebone_old_dev_cfg[] = {
1441 {rmii1_init, DEV_ON_BASEBOARD, PROFILE_NONE}, 1441 {rmii1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1442 {usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE}, 1442 {usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1443 {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE}, 1443 {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1444 {mmc0_init, DEV_ON_BASEBOARD, PROFILE_NONE}, 1444 {mmc0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1445 {NULL, 0, 0}, 1445 {NULL, 0, 0},
1446 }; 1446 };
1447 1447
1448 /* Beaglebone Rev A3 and after */ 1448 /* Beaglebone Rev A3 and after */
1449 static struct evm_dev_cfg beaglebone_dev_cfg[] = { 1449 static struct evm_dev_cfg beaglebone_dev_cfg[] = {
1450 {mii1_init, DEV_ON_BASEBOARD, PROFILE_NONE}, 1450 {mii1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1451 {usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE}, 1451 {usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1452 {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE}, 1452 {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1453 {mmc0_init, DEV_ON_BASEBOARD, PROFILE_NONE}, 1453 {mmc0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1454 {NULL, 0, 0}, 1454 {NULL, 0, 0},
1455 }; 1455 };
1456 1456
1457 static void setup_low_cost_evm(void) 1457 static void setup_low_cost_evm(void)
1458 { 1458 {
1459 pr_info("The board is a AM335x Low Cost EVM.\n"); 1459 pr_info("The board is a AM335x Low Cost EVM.\n");
1460 1460
1461 _configure_device(LOW_COST_EVM, low_cost_evm_dev_cfg, PROFILE_NONE); 1461 _configure_device(LOW_COST_EVM, low_cost_evm_dev_cfg, PROFILE_NONE);
1462 } 1462 }
1463 1463
1464 static void setup_general_purpose_evm(void) 1464 static void setup_general_purpose_evm(void)
1465 { 1465 {
1466 u32 prof_sel = am335x_get_profile_selection(); 1466 u32 prof_sel = am335x_get_profile_selection();
1467 pr_info("The board is general purpose EVM in profile %d\n", prof_sel); 1467 pr_info("The board is general purpose EVM in profile %d\n", prof_sel);
1468 1468
1469 if (!strncmp("1.1A", config.version, 4)) { 1469 if (!strncmp("1.1A", config.version, 4)) {
1470 gp_evm_revision = GP_EVM_REV_IS_1_1A; 1470 gp_evm_revision = GP_EVM_REV_IS_1_1A;
1471 } else if (!strncmp("1.0", config.version, 3)) { 1471 } else if (!strncmp("1.0", config.version, 3)) {
1472 gp_evm_revision = GP_EVM_REV_IS_1_0; 1472 gp_evm_revision = GP_EVM_REV_IS_1_0;
1473 } else { 1473 } else {
1474 pr_err("Found invalid GP EVM revision, falling back to Rev1.1A"); 1474 pr_err("Found invalid GP EVM revision, falling back to Rev1.1A");
1475 gp_evm_revision = GP_EVM_REV_IS_1_1A; 1475 gp_evm_revision = GP_EVM_REV_IS_1_1A;
1476 } 1476 }
1477 1477
1478 if (gp_evm_revision == GP_EVM_REV_IS_1_0) 1478 if (gp_evm_revision == GP_EVM_REV_IS_1_0)
1479 gigabit_enable = 0; 1479 gigabit_enable = 0;
1480 else if (gp_evm_revision == GP_EVM_REV_IS_1_1A) 1480 else if (gp_evm_revision == GP_EVM_REV_IS_1_1A)
1481 gigabit_enable = 1; 1481 gigabit_enable = 1;
1482 1482
1483 _configure_device(GEN_PURP_EVM, gen_purp_evm_dev_cfg, (1L << prof_sel)); 1483 _configure_device(GEN_PURP_EVM, gen_purp_evm_dev_cfg, (1L << prof_sel));
1484 } 1484 }
1485 1485
1486 static void setup_ind_auto_motor_ctrl_evm(void) 1486 static void setup_ind_auto_motor_ctrl_evm(void)
1487 { 1487 {
1488 u32 prof_sel = am335x_get_profile_selection(); 1488 u32 prof_sel = am335x_get_profile_selection();
1489 1489
1490 pr_info("The board is an industrial automation EVM in profile %d\n", 1490 pr_info("The board is an industrial automation EVM in profile %d\n",
1491 prof_sel); 1491 prof_sel);
1492 1492
1493 /* Only Profile 0 is supported */ 1493 /* Only Profile 0 is supported */
1494 if ((1L << prof_sel) != PROFILE_0) { 1494 if ((1L << prof_sel) != PROFILE_0) {
1495 pr_err("AM335X: Only Profile 0 is supported\n"); 1495 pr_err("AM335X: Only Profile 0 is supported\n");
1496 pr_err("Assuming profile 0 & continuing\n"); 1496 pr_err("Assuming profile 0 & continuing\n");
1497 prof_sel = PROFILE_0; 1497 prof_sel = PROFILE_0;
1498 } 1498 }
1499 1499
1500 _configure_device(IND_AUT_MTR_EVM, ind_auto_mtrl_evm_dev_cfg, 1500 _configure_device(IND_AUT_MTR_EVM, ind_auto_mtrl_evm_dev_cfg,
1501 PROFILE_0); 1501 PROFILE_0);
1502 1502
1503 /* Fillup global evmid */ 1503 /* Fillup global evmid */
1504 am33xx_evmid_fillup(IND_AUT_MTR_EVM); 1504 am33xx_evmid_fillup(IND_AUT_MTR_EVM);
1505 1505
1506 /* Initialize TLK110 PHY registers for phy version 1.0 */ 1506 /* Initialize TLK110 PHY registers for phy version 1.0 */
1507 am335x_tlk110_phy_init(); 1507 am335x_tlk110_phy_init();
1508 1508
1509 1509
1510 } 1510 }
1511 1511
1512 static void setup_ip_phone_evm(void) 1512 static void setup_ip_phone_evm(void)
1513 { 1513 {
1514 pr_info("The board is an IP phone EVM\n"); 1514 pr_info("The board is an IP phone EVM\n");
1515 1515
1516 _configure_device(IP_PHN_EVM, ip_phn_evm_dev_cfg, PROFILE_NONE); 1516 _configure_device(IP_PHN_EVM, ip_phn_evm_dev_cfg, PROFILE_NONE);
1517 } 1517 }
1518 1518
1519 /* BeagleBone < Rev A3 */ 1519 /* BeagleBone < Rev A3 */
1520 static void setup_beaglebone_old(void) 1520 static void setup_beaglebone_old(void)
1521 { 1521 {
1522 pr_info("The board is a AM335x Beaglebone < Rev A3.\n"); 1522 pr_info("The board is a AM335x Beaglebone < Rev A3.\n");
1523 1523
1524 /* Beagle Bone has Micro-SD slot which doesn't have Write Protect pin */ 1524 /* Beagle Bone has Micro-SD slot which doesn't have Write Protect pin */
1525 am335x_mmc[0].gpio_wp = -EINVAL; 1525 am335x_mmc[0].gpio_wp = -EINVAL;
1526 1526
1527 _configure_device(LOW_COST_EVM, beaglebone_old_dev_cfg, PROFILE_NONE); 1527 _configure_device(LOW_COST_EVM, beaglebone_old_dev_cfg, PROFILE_NONE);
1528 1528
1529 phy_register_fixup_for_uid(BBB_PHY_ID, BBB_PHY_MASK, 1529 phy_register_fixup_for_uid(BBB_PHY_ID, BBB_PHY_MASK,
1530 beaglebone_phy_fixup); 1530 beaglebone_phy_fixup);
1531 } 1531 }
1532 1532
1533 /* BeagleBone after Rev A3 */ 1533 /* BeagleBone after Rev A3 */
1534 static void setup_beaglebone(void) 1534 static void setup_beaglebone(void)
1535 { 1535 {
1536 pr_info("The board is a AM335x Beaglebone.\n"); 1536 pr_info("The board is a AM335x Beaglebone.\n");
1537 1537
1538 /* Beagle Bone has Micro-SD slot which doesn't have Write Protect pin */ 1538 /* Beagle Bone has Micro-SD slot which doesn't have Write Protect pin */
1539 am335x_mmc[0].gpio_wp = -EINVAL; 1539 am335x_mmc[0].gpio_wp = -EINVAL;
1540 1540
1541 _configure_device(LOW_COST_EVM, beaglebone_dev_cfg, PROFILE_NONE); 1541 _configure_device(LOW_COST_EVM, beaglebone_dev_cfg, PROFILE_NONE);
1542 } 1542 }
1543 1543
1544 1544
1545 static void am335x_setup_daughter_board(struct memory_accessor *m, void *c) 1545 static void am335x_setup_daughter_board(struct memory_accessor *m, void *c)
1546 { 1546 {
1547 u8 tmp; 1547 u8 tmp;
1548 int ret; 1548 int ret;
1549 1549
1550 /* 1550 /*
1551 * try reading a byte from the EEPROM to see if it is 1551 * try reading a byte from the EEPROM to see if it is
1552 * present. We could read a lot more, but that would 1552 * present. We could read a lot more, but that would
1553 * just slow the boot process and we have all the information 1553 * just slow the boot process and we have all the information
1554 * we need from the EEPROM on the base board anyway. 1554 * we need from the EEPROM on the base board anyway.
1555 */ 1555 */
1556 ret = m->read(m, &tmp, 0, sizeof(u8)); 1556 ret = m->read(m, &tmp, 0, sizeof(u8));
1557 if (ret == sizeof(u8)) { 1557 if (ret == sizeof(u8)) {
1558 pr_info("Detected a daughter card on AM335x EVM.."); 1558 pr_info("Detected a daughter card on AM335x EVM..");
1559 daughter_brd_detected = true; 1559 daughter_brd_detected = true;
1560 } else { 1560 } else {
1561 pr_info("No daughter card found\n"); 1561 pr_info("No daughter card found\n");
1562 daughter_brd_detected = false; 1562 daughter_brd_detected = false;
1563 } 1563 }
1564 } 1564 }
1565 1565
1566 static void am335x_evm_setup(struct memory_accessor *mem_acc, void *context) 1566 static void am335x_evm_setup(struct memory_accessor *mem_acc, void *context)
1567 { 1567 {
1568 int ret; 1568 int ret;
1569 char tmp[10]; 1569 char tmp[10];
1570 1570
1571 /* 1st get the MAC address from EEPROM */ 1571 /* 1st get the MAC address from EEPROM */
1572 ret = mem_acc->read(mem_acc, (char *)&am335x_mac_addr, 1572 ret = mem_acc->read(mem_acc, (char *)&am335x_mac_addr,
1573 EEPROM_MAC_ADDRESS_OFFSET, sizeof(am335x_mac_addr)); 1573 EEPROM_MAC_ADDRESS_OFFSET, sizeof(am335x_mac_addr));
1574 1574
1575 if (ret != sizeof(am335x_mac_addr)) { 1575 if (ret != sizeof(am335x_mac_addr)) {
1576 pr_warning("AM335X: EVM Config read fail: %d\n", ret); 1576 pr_warning("AM335X: EVM Config read fail: %d\n", ret);
1577 return; 1577 return;
1578 } 1578 }
1579 1579
1580 /* Fillup global mac id */ 1580 /* Fillup global mac id */
1581 am33xx_cpsw_macidfillup(&am335x_mac_addr[0][0], 1581 am33xx_cpsw_macidfillup(&am335x_mac_addr[0][0],
1582 &am335x_mac_addr[1][0]); 1582 &am335x_mac_addr[1][0]);
1583 1583
1584 /* get board specific data */ 1584 /* get board specific data */
1585 ret = mem_acc->read(mem_acc, (char *)&config, 0, sizeof(config)); 1585 ret = mem_acc->read(mem_acc, (char *)&config, 0, sizeof(config));
1586 if (ret != sizeof(config)) { 1586 if (ret != sizeof(config)) {
1587 pr_warning("AM335X EVM config read fail, read %d bytes\n", ret); 1587 pr_warning("AM335X EVM config read fail, read %d bytes\n", ret);
1588 return; 1588 return;
1589 } 1589 }
1590 1590
1591 if (config.header != AM335X_EEPROM_HEADER) { 1591 if (config.header != AM335X_EEPROM_HEADER) {
1592 pr_warning("AM335X: wrong header 0x%x, expected 0x%x\n", 1592 pr_warning("AM335X: wrong header 0x%x, expected 0x%x\n",
1593 config.header, AM335X_EEPROM_HEADER); 1593 config.header, AM335X_EEPROM_HEADER);
1594 goto out; 1594 goto out;
1595 } 1595 }
1596 1596
1597 if (strncmp("A335", config.name, 4)) { 1597 if (strncmp("A335", config.name, 4)) {
1598 pr_err("Board %s doesn't look like an AM335x board\n", 1598 pr_err("Board %s doesn't look like an AM335x board\n",
1599 config.name); 1599 config.name);
1600 goto out; 1600 goto out;
1601 } 1601 }
1602 1602
1603 snprintf(tmp, sizeof(config.name) + 1, "%s", config.name); 1603 snprintf(tmp, sizeof(config.name) + 1, "%s", config.name);
1604 pr_info("Board name: %s\n", tmp); 1604 pr_info("Board name: %s\n", tmp);
1605 snprintf(tmp, sizeof(config.version) + 1, "%s", config.version); 1605 snprintf(tmp, sizeof(config.version) + 1, "%s", config.version);
1606 pr_info("Board version: %s\n", tmp); 1606 pr_info("Board version: %s\n", tmp);
1607 1607
1608 if (!strncmp("A335BONE", config.name, 8)) { 1608 if (!strncmp("A335BONE", config.name, 8)) {
1609 daughter_brd_detected = false; 1609 daughter_brd_detected = false;
1610 if(!strncmp("00A1", config.version, 4) || 1610 if(!strncmp("00A1", config.version, 4) ||
1611 !strncmp("00A2", config.version, 4)) 1611 !strncmp("00A2", config.version, 4))
1612 setup_beaglebone_old(); 1612 setup_beaglebone_old();
1613 else 1613 else
1614 setup_beaglebone(); 1614 setup_beaglebone();
1615 } else { 1615 } else {
1616 /* only 6 characters of options string used for now */ 1616 /* only 6 characters of options string used for now */
1617 snprintf(tmp, 7, "%s", config.opt); 1617 snprintf(tmp, 7, "%s", config.opt);
1618 pr_info("SKU: %s\n", tmp); 1618 pr_info("SKU: %s\n", tmp);
1619 1619
1620 if (!strncmp("SKU#00", config.opt, 6)) 1620 if (!strncmp("SKU#00", config.opt, 6))
1621 setup_low_cost_evm(); 1621 setup_low_cost_evm();
1622 else if (!strncmp("SKU#01", config.opt, 6)) 1622 else if (!strncmp("SKU#01", config.opt, 6))
1623 setup_general_purpose_evm(); 1623 setup_general_purpose_evm();
1624 else if (!strncmp("SKU#02", config.opt, 6)) 1624 else if (!strncmp("SKU#02", config.opt, 6))
1625 setup_ind_auto_motor_ctrl_evm(); 1625 setup_ind_auto_motor_ctrl_evm();
1626 else if (!strncmp("SKU#03", config.opt, 6)) 1626 else if (!strncmp("SKU#03", config.opt, 6))
1627 setup_ip_phone_evm(); 1627 setup_ip_phone_evm();
1628 else 1628 else
1629 goto out; 1629 goto out;
1630 } 1630 }
1631 /* Initialize cpsw after board detection is completed as board 1631 /* Initialize cpsw after board detection is completed as board
1632 * information is required for configuring phy address and hence 1632 * information is required for configuring phy address and hence
1633 * should be call only after board detection 1633 * should be call only after board detection
1634 */ 1634 */
1635 am33xx_cpsw_init(gigabit_enable); 1635 am33xx_cpsw_init(gigabit_enable);
1636 1636
1637 return; 1637 return;
1638 out: 1638 out:
1639 /* 1639 /*
1640 * If the EEPROM hasn't been programed or an incorrect header 1640 * If the EEPROM hasn't been programed or an incorrect header
1641 * or board name are read, assume this is an old beaglebone board 1641 * or board name are read, assume this is an old beaglebone board
1642 * (< Rev A3) 1642 * (< Rev A3)
1643 */ 1643 */
1644 pr_err("Could not detect any board, falling back to: " 1644 pr_err("Could not detect any board, falling back to: "
1645 "Beaglebone (< Rev A3) with no daughter card connected\n"); 1645 "Beaglebone (< Rev A3) with no daughter card connected\n");
1646 daughter_brd_detected = false; 1646 daughter_brd_detected = false;
1647 setup_beaglebone_old(); 1647 setup_beaglebone_old();
1648 1648
1649 /* Initialize cpsw after board detection is completed as board 1649 /* Initialize cpsw after board detection is completed as board
1650 * information is required for configuring phy address and hence 1650 * information is required for configuring phy address and hence
1651 * should be call only after board detection 1651 * should be call only after board detection
1652 */ 1652 */
1653 1653
1654 am33xx_cpsw_init(gigabit_enable); 1654 am33xx_cpsw_init(gigabit_enable);
1655 } 1655 }
1656 1656
1657 static struct at24_platform_data am335x_daughter_board_eeprom_info = { 1657 static struct at24_platform_data am335x_daughter_board_eeprom_info = {
1658 .byte_len = (256*1024) / 8, 1658 .byte_len = (256*1024) / 8,
1659 .page_size = 64, 1659 .page_size = 64,
1660 .flags = AT24_FLAG_ADDR16, 1660 .flags = AT24_FLAG_ADDR16,
1661 .setup = am335x_setup_daughter_board, 1661 .setup = am335x_setup_daughter_board,
1662 .context = (void *)NULL, 1662 .context = (void *)NULL,
1663 }; 1663 };
1664 1664
1665 static struct at24_platform_data am335x_baseboard_eeprom_info = { 1665 static struct at24_platform_data am335x_baseboard_eeprom_info = {
1666 .byte_len = (256*1024) / 8, 1666 .byte_len = (256*1024) / 8,
1667 .page_size = 64, 1667 .page_size = 64,
1668 .flags = AT24_FLAG_ADDR16, 1668 .flags = AT24_FLAG_ADDR16,
1669 .setup = am335x_evm_setup, 1669 .setup = am335x_evm_setup,
1670 .context = (void *)NULL, 1670 .context = (void *)NULL,
1671 }; 1671 };
1672 1672
1673 static struct regulator_init_data am335x_dummy; 1673 static struct regulator_init_data am335x_dummy;
1674 1674
1675 static struct regulator_consumer_supply am335x_vdd1_supply[] = { 1675 static struct regulator_consumer_supply am335x_vdd1_supply[] = {
1676 REGULATOR_SUPPLY("mpu", "mpu.0"), 1676 REGULATOR_SUPPLY("mpu", "mpu.0"),
1677 }; 1677 };
1678 1678
1679 static struct regulator_init_data am335x_vdd1 = { 1679 static struct regulator_init_data am335x_vdd1 = {
1680 .constraints = { 1680 .constraints = {
1681 .min_uV = 600000, 1681 .min_uV = 600000,
1682 .max_uV = 1500000, 1682 .max_uV = 1500000,
1683 .valid_modes_mask = REGULATOR_MODE_NORMAL, 1683 .valid_modes_mask = REGULATOR_MODE_NORMAL,
1684 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, 1684 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
1685 .always_on = 1, 1685 .always_on = 1,
1686 }, 1686 },
1687 .num_consumer_supplies = ARRAY_SIZE(am335x_vdd1_supply), 1687 .num_consumer_supplies = ARRAY_SIZE(am335x_vdd1_supply),
1688 .consumer_supplies = am335x_vdd1_supply, 1688 .consumer_supplies = am335x_vdd1_supply,
1689 }; 1689 };
1690 1690
1691 static struct tps65910_board am335x_tps65910_info = { 1691 static struct tps65910_board am335x_tps65910_info = {
1692 .tps65910_pmic_init_data[TPS65910_REG_VRTC] = &am335x_dummy, 1692 .tps65910_pmic_init_data[TPS65910_REG_VRTC] = &am335x_dummy,
1693 .tps65910_pmic_init_data[TPS65910_REG_VIO] = &am335x_dummy, 1693 .tps65910_pmic_init_data[TPS65910_REG_VIO] = &am335x_dummy,
1694 .tps65910_pmic_init_data[TPS65910_REG_VDD1] = &am335x_vdd1, 1694 .tps65910_pmic_init_data[TPS65910_REG_VDD1] = &am335x_vdd1,
1695 .tps65910_pmic_init_data[TPS65910_REG_VDD2] = &am335x_dummy, 1695 .tps65910_pmic_init_data[TPS65910_REG_VDD2] = &am335x_dummy,
1696 .tps65910_pmic_init_data[TPS65910_REG_VDD3] = &am335x_dummy, 1696 .tps65910_pmic_init_data[TPS65910_REG_VDD3] = &am335x_dummy,
1697 .tps65910_pmic_init_data[TPS65910_REG_VDIG1] = &am335x_dummy, 1697 .tps65910_pmic_init_data[TPS65910_REG_VDIG1] = &am335x_dummy,
1698 .tps65910_pmic_init_data[TPS65910_REG_VDIG2] = &am335x_dummy, 1698 .tps65910_pmic_init_data[TPS65910_REG_VDIG2] = &am335x_dummy,
1699 .tps65910_pmic_init_data[TPS65910_REG_VPLL] = &am335x_dummy, 1699 .tps65910_pmic_init_data[TPS65910_REG_VPLL] = &am335x_dummy,
1700 .tps65910_pmic_init_data[TPS65910_REG_VDAC] = &am335x_dummy, 1700 .tps65910_pmic_init_data[TPS65910_REG_VDAC] = &am335x_dummy,
1701 .tps65910_pmic_init_data[TPS65910_REG_VAUX1] = &am335x_dummy, 1701 .tps65910_pmic_init_data[TPS65910_REG_VAUX1] = &am335x_dummy,
1702 .tps65910_pmic_init_data[TPS65910_REG_VAUX2] = &am335x_dummy, 1702 .tps65910_pmic_init_data[TPS65910_REG_VAUX2] = &am335x_dummy,
1703 .tps65910_pmic_init_data[TPS65910_REG_VAUX33] = &am335x_dummy, 1703 .tps65910_pmic_init_data[TPS65910_REG_VAUX33] = &am335x_dummy,
1704 .tps65910_pmic_init_data[TPS65910_REG_VMMC] = &am335x_dummy, 1704 .tps65910_pmic_init_data[TPS65910_REG_VMMC] = &am335x_dummy,
1705 }; 1705 };
1706 1706
1707 /* 1707 /*
1708 * Daughter board Detection. 1708 * Daughter board Detection.
1709 * Every board has a ID memory (EEPROM) on board. We probe these devices at 1709 * Every board has a ID memory (EEPROM) on board. We probe these devices at
1710 * machine init, starting from daughter board and ending with baseboard. 1710 * machine init, starting from daughter board and ending with baseboard.
1711 * Assumptions : 1711 * Assumptions :
1712 * 1. probe for i2c devices are called in the order they are included in 1712 * 1. probe for i2c devices are called in the order they are included in
1713 * the below struct. Daughter boards eeprom are probed 1st. Baseboard 1713 * the below struct. Daughter boards eeprom are probed 1st. Baseboard
1714 * eeprom probe is called last. 1714 * eeprom probe is called last.
1715 */ 1715 */
1716 static struct i2c_board_info __initdata am335x_i2c_boardinfo[] = { 1716 static struct i2c_board_info __initdata am335x_i2c_boardinfo[] = {
1717 { 1717 {
1718 /* Daughter Board EEPROM */ 1718 /* Daughter Board EEPROM */
1719 I2C_BOARD_INFO("24c256", DAUG_BOARD_I2C_ADDR), 1719 I2C_BOARD_INFO("24c256", DAUG_BOARD_I2C_ADDR),
1720 .platform_data = &am335x_daughter_board_eeprom_info, 1720 .platform_data = &am335x_daughter_board_eeprom_info,
1721 }, 1721 },
1722 { 1722 {
1723 /* Baseboard board EEPROM */ 1723 /* Baseboard board EEPROM */
1724 I2C_BOARD_INFO("24c256", BASEBOARD_I2C_ADDR), 1724 I2C_BOARD_INFO("24c256", BASEBOARD_I2C_ADDR),
1725 .platform_data = &am335x_baseboard_eeprom_info, 1725 .platform_data = &am335x_baseboard_eeprom_info,
1726 }, 1726 },
1727 { 1727 {
1728 I2C_BOARD_INFO("cpld_reg", 0x35), 1728 I2C_BOARD_INFO("cpld_reg", 0x35),
1729 }, 1729 },
1730 { 1730 {
1731 I2C_BOARD_INFO("tlc59108", 0x40), 1731 I2C_BOARD_INFO("tlc59108", 0x40),
1732 }, 1732 },
1733 { 1733 {
1734 I2C_BOARD_INFO("tps65910", TPS65910_I2C_ID1), 1734 I2C_BOARD_INFO("tps65910", TPS65910_I2C_ID1),
1735 .platform_data = &am335x_tps65910_info, 1735 .platform_data = &am335x_tps65910_info,
1736 }, 1736 },
1737 1737
1738 }; 1738 };
1739 1739
1740 static struct omap_musb_board_data musb_board_data = { 1740 static struct omap_musb_board_data musb_board_data = {
1741 .interface_type = MUSB_INTERFACE_ULPI, 1741 .interface_type = MUSB_INTERFACE_ULPI,
1742 .mode = MUSB_OTG, 1742 .mode = MUSB_OTG,
1743 .power = 500, 1743 .power = 500,
1744 .instances = 1, 1744 .instances = 1,
1745 }; 1745 };
1746 1746
1747 static int cpld_reg_probe(struct i2c_client *client, 1747 static int cpld_reg_probe(struct i2c_client *client,
1748 const struct i2c_device_id *id) 1748 const struct i2c_device_id *id)
1749 { 1749 {
1750 cpld_client = client; 1750 cpld_client = client;
1751 return 0; 1751 return 0;
1752 } 1752 }
1753 1753
1754 static int __devexit cpld_reg_remove(struct i2c_client *client) 1754 static int __devexit cpld_reg_remove(struct i2c_client *client)
1755 { 1755 {
1756 cpld_client = NULL; 1756 cpld_client = NULL;
1757 return 0; 1757 return 0;
1758 } 1758 }
1759 1759
1760 static const struct i2c_device_id cpld_reg_id[] = { 1760 static const struct i2c_device_id cpld_reg_id[] = {
1761 { "cpld_reg", 0 }, 1761 { "cpld_reg", 0 },
1762 { } 1762 { }
1763 }; 1763 };
1764 1764
1765 static struct i2c_driver cpld_reg_driver = { 1765 static struct i2c_driver cpld_reg_driver = {
1766 .driver = { 1766 .driver = {
1767 .name = "cpld_reg", 1767 .name = "cpld_reg",
1768 }, 1768 },
1769 .probe = cpld_reg_probe, 1769 .probe = cpld_reg_probe,
1770 .remove = cpld_reg_remove, 1770 .remove = cpld_reg_remove,
1771 .id_table = cpld_reg_id, 1771 .id_table = cpld_reg_id,
1772 }; 1772 };
1773 1773
1774 static void evm_init_cpld(void) 1774 static void evm_init_cpld(void)
1775 { 1775 {
1776 i2c_add_driver(&cpld_reg_driver); 1776 i2c_add_driver(&cpld_reg_driver);
1777 } 1777 }
1778 1778
1779 static void __init am335x_evm_i2c_init(void) 1779 static void __init am335x_evm_i2c_init(void)
1780 { 1780 {
1781 /* Initially assume Low Cost EVM Config */ 1781 /* Initially assume Low Cost EVM Config */
1782 am335x_evm_id = LOW_COST_EVM; 1782 am335x_evm_id = LOW_COST_EVM;
1783 1783
1784 evm_init_cpld(); 1784 evm_init_cpld();
1785 1785
1786 omap_register_i2c_bus(1, 100, am335x_i2c_boardinfo, 1786 omap_register_i2c_bus(1, 100, am335x_i2c_boardinfo,
1787 ARRAY_SIZE(am335x_i2c_boardinfo)); 1787 ARRAY_SIZE(am335x_i2c_boardinfo));
1788 } 1788 }
1789 1789
1790 static struct resource am335x_rtc_resources[] = { 1790 static struct resource am335x_rtc_resources[] = {
1791 { 1791 {
1792 .start = AM33XX_RTC_BASE, 1792 .start = AM33XX_RTC_BASE,
1793 .end = AM33XX_RTC_BASE + SZ_4K - 1, 1793 .end = AM33XX_RTC_BASE + SZ_4K - 1,
1794 .flags = IORESOURCE_MEM, 1794 .flags = IORESOURCE_MEM,
1795 }, 1795 },
1796 { /* timer irq */ 1796 { /* timer irq */
1797 .start = AM33XX_IRQ_RTC_TIMER, 1797 .start = AM33XX_IRQ_RTC_TIMER,
1798 .end = AM33XX_IRQ_RTC_TIMER, 1798 .end = AM33XX_IRQ_RTC_TIMER,
1799 .flags = IORESOURCE_IRQ, 1799 .flags = IORESOURCE_IRQ,
1800 }, 1800 },
1801 { /* alarm irq */ 1801 { /* alarm irq */
1802 .start = AM33XX_IRQ_RTC_ALARM, 1802 .start = AM33XX_IRQ_RTC_ALARM,
1803 .end = AM33XX_IRQ_RTC_ALARM, 1803 .end = AM33XX_IRQ_RTC_ALARM,
1804 .flags = IORESOURCE_IRQ, 1804 .flags = IORESOURCE_IRQ,
1805 }, 1805 },
1806 }; 1806 };
1807 1807
1808 static struct platform_device am335x_rtc_device = { 1808 static struct platform_device am335x_rtc_device = {
1809 .name = "omap_rtc", 1809 .name = "omap_rtc",
1810 .id = -1, 1810 .id = -1,
1811 .num_resources = ARRAY_SIZE(am335x_rtc_resources), 1811 .num_resources = ARRAY_SIZE(am335x_rtc_resources),
1812 .resource = am335x_rtc_resources, 1812 .resource = am335x_rtc_resources,
1813 }; 1813 };
1814 1814
1815 static int am335x_rtc_init(void) 1815 static int am335x_rtc_init(void)
1816 { 1816 {
1817 void __iomem *base; 1817 void __iomem *base;
1818 struct clk *clk; 1818 struct clk *clk;
1819 1819
1820 clk = clk_get(NULL, "rtc_fck"); 1820 clk = clk_get(NULL, "rtc_fck");
1821 if (IS_ERR(clk)) { 1821 if (IS_ERR(clk)) {
1822 pr_err("rtc : Failed to get RTC clock\n"); 1822 pr_err("rtc : Failed to get RTC clock\n");
1823 return -1; 1823 return -1;
1824 } 1824 }
1825 1825
1826 if (clk_enable(clk)) { 1826 if (clk_enable(clk)) {
1827 pr_err("rtc: Clock Enable Failed\n"); 1827 pr_err("rtc: Clock Enable Failed\n");
1828 return -1; 1828 return -1;
1829 } 1829 }
1830 1830
1831 base = ioremap(AM33XX_RTC_BASE, SZ_4K); 1831 base = ioremap(AM33XX_RTC_BASE, SZ_4K);
1832 1832
1833 if (WARN_ON(!base)) 1833 if (WARN_ON(!base))
1834 return -ENOMEM; 1834 return -ENOMEM;
1835 1835
1836 /* Unlock the rtc's registers */ 1836 /* Unlock the rtc's registers */
1837 __raw_writel(0x83e70b13, base + 0x6c); 1837 __raw_writel(0x83e70b13, base + 0x6c);
1838 __raw_writel(0x95a4f1e0, base + 0x70); 1838 __raw_writel(0x95a4f1e0, base + 0x70);
1839 1839
1840 /* 1840 /*
1841 * Enable the 32K OSc 1841 * Enable the 32K OSc
1842 * TODO: Need a better way to handle this 1842 * TODO: Need a better way to handle this
1843 * Since we want the clock to be running before mmc init 1843 * Since we want the clock to be running before mmc init
1844 * we need to do it before the rtc probe happens 1844 * we need to do it before the rtc probe happens
1845 */ 1845 */
1846 __raw_writel(0x48, base + 0x54); 1846 __raw_writel(0x48, base + 0x54);
1847 1847
1848 iounmap(base); 1848 iounmap(base);
1849 1849
1850 return platform_device_register(&am335x_rtc_device); 1850 return platform_device_register(&am335x_rtc_device);
1851 } 1851 }
1852 1852
1853 /* Enable clkout2 */ 1853 /* Enable clkout2 */
1854 static struct pinmux_config clkout2_pin_mux[] = { 1854 static struct pinmux_config clkout2_pin_mux[] = {
1855 {"xdma_event_intr1.clkout2", OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT}, 1855 {"xdma_event_intr1.clkout2", OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT},
1856 {NULL, 0}, 1856 {NULL, 0},
1857 }; 1857 };
1858 1858
1859 static void __init clkout2_enable(void) 1859 static void __init clkout2_enable(void)
1860 { 1860 {
1861 struct clk *ck_32; 1861 struct clk *ck_32;
1862 1862
1863 ck_32 = clk_get(NULL, "clkout2_ck"); 1863 ck_32 = clk_get(NULL, "clkout2_ck");
1864 if (IS_ERR(ck_32)) { 1864 if (IS_ERR(ck_32)) {
1865 pr_err("Cannot clk_get ck_32\n"); 1865 pr_err("Cannot clk_get ck_32\n");
1866 return; 1866 return;
1867 } 1867 }
1868 1868
1869 clk_enable(ck_32); 1869 clk_enable(ck_32);
1870 1870
1871 setup_pin_mux(clkout2_pin_mux); 1871 setup_pin_mux(clkout2_pin_mux);
1872 } 1872 }
1873 1873
1874 void __iomem * __init am33xx_get_mem_ctlr(void) 1874 void __iomem * __init am33xx_get_mem_ctlr(void)
1875 { 1875 {
1876 void __iomem *am33xx_emif_base; 1876 void __iomem *am33xx_emif_base;
1877 1877
1878 am33xx_emif_base = ioremap(AM33XX_EMIF0_BASE, SZ_32K); 1878 am33xx_emif_base = ioremap(AM33XX_EMIF0_BASE, SZ_32K);
1879 1879
1880 if (!am33xx_emif_base) 1880 if (!am33xx_emif_base)
1881 pr_warning("%s: Unable to map DDR2 controller", __func__); 1881 pr_warning("%s: Unable to map DDR2 controller", __func__);
1882 1882
1883 return am33xx_emif_base; 1883 return am33xx_emif_base;
1884 } 1884 }
1885 1885
1886 static struct resource am33xx_cpuidle_resources[] = { 1886 static struct resource am33xx_cpuidle_resources[] = {
1887 { 1887 {
1888 .start = AM33XX_EMIF0_BASE, 1888 .start = AM33XX_EMIF0_BASE,
1889 .end = AM33XX_EMIF0_BASE + SZ_32K - 1, 1889 .end = AM33XX_EMIF0_BASE + SZ_32K - 1,
1890 .flags = IORESOURCE_MEM, 1890 .flags = IORESOURCE_MEM,
1891 }, 1891 },
1892 }; 1892 };
1893 1893
1894 /* AM33XX devices support DDR2 power down */ 1894 /* AM33XX devices support DDR2 power down */
1895 static struct am33xx_cpuidle_config am33xx_cpuidle_pdata = { 1895 static struct am33xx_cpuidle_config am33xx_cpuidle_pdata = {
1896 .ddr2_pdown = 1, 1896 .ddr2_pdown = 1,
1897 }; 1897 };
1898 1898
1899 static struct platform_device am33xx_cpuidle_device = { 1899 static struct platform_device am33xx_cpuidle_device = {
1900 .name = "cpuidle-am33xx", 1900 .name = "cpuidle-am33xx",
1901 .num_resources = ARRAY_SIZE(am33xx_cpuidle_resources), 1901 .num_resources = ARRAY_SIZE(am33xx_cpuidle_resources),
1902 .resource = am33xx_cpuidle_resources, 1902 .resource = am33xx_cpuidle_resources,
1903 .dev = { 1903 .dev = {
1904 .platform_data = &am33xx_cpuidle_pdata, 1904 .platform_data = &am33xx_cpuidle_pdata,
1905 }, 1905 },
1906 }; 1906 };
1907 1907
1908 static void __init am33xx_cpuidle_init(void) 1908 static void __init am33xx_cpuidle_init(void)
1909 { 1909 {
1910 int ret; 1910 int ret;
1911 1911
1912 am33xx_cpuidle_pdata.emif_base = am33xx_get_mem_ctlr(); 1912 am33xx_cpuidle_pdata.emif_base = am33xx_get_mem_ctlr();
1913 1913
1914 ret = platform_device_register(&am33xx_cpuidle_device); 1914 ret = platform_device_register(&am33xx_cpuidle_device);
1915 1915
1916 if (ret) 1916 if (ret)
1917 pr_warning("AM33XX cpuidle registration failed\n"); 1917 pr_warning("AM33XX cpuidle registration failed\n");
1918 1918
1919 } 1919 }
1920 1920
1921 static void __init am335x_evm_init(void) 1921 static void __init am335x_evm_init(void)
1922 { 1922 {
1923 am33xx_cpuidle_init(); 1923 am33xx_cpuidle_init();
1924 am33xx_mux_init(board_mux); 1924 am33xx_mux_init(board_mux);
1925 omap_serial_init(); 1925 omap_serial_init();
1926 am335x_rtc_init(); 1926 am335x_rtc_init();
1927 clkout2_enable(); 1927 clkout2_enable();
1928 am335x_evm_i2c_init(); 1928 am335x_evm_i2c_init();
1929 omap_sdrc_init(NULL, NULL); 1929 omap_sdrc_init(NULL, NULL);
1930 usb_musb_init(&musb_board_data); 1930 usb_musb_init(&musb_board_data);
1931 omap_board_config = am335x_evm_config; 1931 omap_board_config = am335x_evm_config;
1932 omap_board_config_size = ARRAY_SIZE(am335x_evm_config); 1932 omap_board_config_size = ARRAY_SIZE(am335x_evm_config);
1933 /* Create an alias for icss clock */ 1933 /* Create an alias for icss clock */
1934 if (clk_add_alias("pruss", NULL, "icss_uart_gclk", NULL)) 1934 if (clk_add_alias("pruss", NULL, "icss_uart_gclk", NULL))
1935 pr_err("failed to create an alias: icss_uart_gclk --> pruss\n"); 1935 pr_err("failed to create an alias: icss_uart_gclk --> pruss\n");
1936 /* Create an alias for gfx/sgx clock */ 1936 /* Create an alias for gfx/sgx clock */
1937 if (clk_add_alias("sgx_ck", NULL, "gfx_fclk", NULL)) 1937 if (clk_add_alias("sgx_ck", NULL, "gfx_fclk", NULL))
1938 pr_err("failed to create an alias: gfx_fclk --> sgx_ck\n"); 1938 pr_err("failed to create an alias: gfx_fclk --> sgx_ck\n");
1939 } 1939 }
1940 1940
1941 static void __init am335x_evm_map_io(void) 1941 static void __init am335x_evm_map_io(void)
1942 { 1942 {
1943 omap2_set_globals_am33xx(); 1943 omap2_set_globals_am33xx();
1944 omapam33xx_map_common_io(); 1944 omapam33xx_map_common_io();
1945 } 1945 }
1946 1946
1947 MACHINE_START(AM335XEVM, "am335xevm") 1947 MACHINE_START(AM335XEVM, "am335xevm")
1948 /* Maintainer: Texas Instruments */ 1948 /* Maintainer: Texas Instruments */
1949 .atag_offset = 0x100, 1949 .atag_offset = 0x100,
1950 .map_io = am335x_evm_map_io, 1950 .map_io = am335x_evm_map_io,
1951 .init_irq = ti816x_init_irq, 1951 .init_irq = ti816x_init_irq,
1952 .init_early = am335x_init_early, 1952 .init_early = am335x_init_early,
1953 .timer = &omap3_am33xx_timer, 1953 .timer = &omap3_am33xx_timer,
1954 .init_machine = am335x_evm_init, 1954 .init_machine = am335x_evm_init,
1955 MACHINE_END 1955 MACHINE_END
1956 1956
1957 MACHINE_START(AM335XIAEVM, "am335xiaevm") 1957 MACHINE_START(AM335XIAEVM, "am335xiaevm")
1958 /* Maintainer: Texas Instruments */ 1958 /* Maintainer: Texas Instruments */
1959 .atag_offset = 0x100, 1959 .atag_offset = 0x100,
1960 .map_io = am335x_evm_map_io, 1960 .map_io = am335x_evm_map_io,
1961 .init_irq = ti816x_init_irq, 1961 .init_irq = ti816x_init_irq,
1962 .init_early = am335x_init_early, 1962 .init_early = am335x_init_early,
1963 .timer = &omap3_am33xx_timer, 1963 .timer = &omap3_am33xx_timer,
1964 .init_machine = am335x_evm_init, 1964 .init_machine = am335x_evm_init,
1965 MACHINE_END 1965 MACHINE_END
1966 1966
arch/arm/mach-omap2/mux33xx.c
Diff comments   View file @ 0088903
1 /* 1 /*
2 * AM33XX mux data 2 * AM33XX mux data
3 * 3 *
4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ 4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
5 * 5 *
6 * Derived from: arch/arm/mach-omap2/mux34xx.c Original copyright follows: 6 * Derived from: arch/arm/mach-omap2/mux34xx.c Original copyright follows:
7 * 7 *
8 * Copyright (C) 2009 Nokia 8 * Copyright (C) 2009 Nokia
9 * Copyright (C) 2009 Texas Instruments 9 * Copyright (C) 2009 Texas Instruments
10 * 10 *
11 * This program is free software; you can redistribute it and/or modify 11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as 12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation. 13 * published by the Free Software Foundation.
14 */ 14 */
15 15
16 #include <linux/module.h> 16 #include <linux/module.h>
17 #include <linux/init.h> 17 #include <linux/init.h>
18 18
19 #include "mux.h" 19 #include "mux.h"
20 20
21 #ifdef CONFIG_OMAP_MUX 21 #ifdef CONFIG_OMAP_MUX
22 22
23 #define _AM33XX_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \ 23 #define _AM33XX_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \
24 { \ 24 { \
25 .reg_offset = (AM33XX_CONTROL_PADCONF_##M0##_OFFSET), \ 25 .reg_offset = (AM33XX_CONTROL_PADCONF_##M0##_OFFSET), \
26 .gpio = (g), \ 26 .gpio = (g), \
27 .muxnames = { m0, m1, m2, m3, m4, m5, m6, m7 }, \ 27 .muxnames = { m0, m1, m2, m3, m4, m5, m6, m7 }, \
28 } 28 }
29 29
30 /* AM33XX pin mux super set */ 30 /* AM33XX pin mux super set */
31 static struct omap_mux __initdata am33xx_muxmodes[] = { 31 static struct omap_mux __initdata am33xx_muxmodes[] = {
32 _AM33XX_MUXENTRY(GPMC_AD0, 0, 32 _AM33XX_MUXENTRY(GPMC_AD0, 0,
33 "gpmc_ad0", "mmc1_dat0", NULL, NULL, 33 "gpmc_ad0", "mmc1_dat0", NULL, NULL,
34 NULL, NULL, NULL, NULL), 34 NULL, NULL, NULL, NULL),
35 _AM33XX_MUXENTRY(GPMC_AD1, 0, 35 _AM33XX_MUXENTRY(GPMC_AD1, 0,
36 "gpmc_ad1", "mmc1_dat1", NULL, NULL, 36 "gpmc_ad1", "mmc1_dat1", NULL, NULL,
37 NULL, NULL, NULL, NULL), 37 NULL, NULL, NULL, NULL),
38 _AM33XX_MUXENTRY(GPMC_AD2, 0, 38 _AM33XX_MUXENTRY(GPMC_AD2, 0,
39 "gpmc_ad2", "mmc1_dat2", NULL, NULL, 39 "gpmc_ad2", "mmc1_dat2", NULL, NULL,
40 NULL, NULL, NULL, NULL), 40 NULL, NULL, NULL, NULL),
41 _AM33XX_MUXENTRY(GPMC_AD3, 0, 41 _AM33XX_MUXENTRY(GPMC_AD3, 0,
42 "gpmc_ad3", "mmc1_dat3", NULL, NULL, 42 "gpmc_ad3", "mmc1_dat3", NULL, NULL,
43 NULL, NULL, NULL, NULL), 43 NULL, NULL, NULL, NULL),
44 _AM33XX_MUXENTRY(GPMC_AD4, 0, 44 _AM33XX_MUXENTRY(GPMC_AD4, 0,
45 "gpmc_ad4", "mmc1_dat4", NULL, NULL, 45 "gpmc_ad4", "mmc1_dat4", NULL, NULL,
46 NULL, NULL, NULL, NULL), 46 NULL, NULL, NULL, NULL),
47 _AM33XX_MUXENTRY(GPMC_AD5, 0, 47 _AM33XX_MUXENTRY(GPMC_AD5, 0,
48 "gpmc_ad5", "mmc1_dat5", NULL, NULL, 48 "gpmc_ad5", "mmc1_dat5", NULL, NULL,
49 NULL, NULL, NULL, NULL), 49 NULL, NULL, NULL, NULL),
50 _AM33XX_MUXENTRY(GPMC_AD6, 0, 50 _AM33XX_MUXENTRY(GPMC_AD6, 0,
51 "gpmc_ad6", "mmc1_dat6", NULL, NULL, 51 "gpmc_ad6", "mmc1_dat6", NULL, NULL,
52 NULL, NULL, NULL, NULL), 52 NULL, NULL, NULL, NULL),
53 _AM33XX_MUXENTRY(GPMC_AD7, 0, 53 _AM33XX_MUXENTRY(GPMC_AD7, 0,
54 "gpmc_ad7", "mmc1_dat7", NULL, NULL, 54 "gpmc_ad7", "mmc1_dat7", NULL, NULL,
55 NULL, NULL, NULL, NULL), 55 NULL, NULL, NULL, NULL),
56 _AM33XX_MUXENTRY(GPMC_AD8, 0, 56 _AM33XX_MUXENTRY(GPMC_AD8, 0,
57 "gpmc_ad8", "lcd_data16", "mmc1_dat0", "mmc2_dat4", 57 "gpmc_ad8", "lcd_data16", "mmc1_dat0", "mmc2_dat4",
58 NULL, NULL, NULL, NULL), 58 NULL, NULL, NULL, NULL),
59 _AM33XX_MUXENTRY(GPMC_AD9, 0, 59 _AM33XX_MUXENTRY(GPMC_AD9, 0,
60 "gpmc_ad9", "lcd_data17", "mmc1_dat1", "mmc2_dat5", 60 "gpmc_ad9", "lcd_data17", "mmc1_dat1", "mmc2_dat5",
61 NULL, NULL, NULL, NULL), 61 NULL, NULL, NULL, NULL),
62 _AM33XX_MUXENTRY(GPMC_AD10, 0, 62 _AM33XX_MUXENTRY(GPMC_AD10, 0,
63 "gpmc_ad10", "lcd_data18", "mmc1_dat2", "mmc2_dat6", 63 "gpmc_ad10", "lcd_data18", "mmc1_dat2", "mmc2_dat6",
64 NULL, NULL, NULL, NULL), 64 NULL, NULL, NULL, NULL),
65 _AM33XX_MUXENTRY(GPMC_AD11, 0, 65 _AM33XX_MUXENTRY(GPMC_AD11, 0,
66 "gpmc_ad11", "lcd_data19", "mmc1_dat3", "mmc2_dat7", 66 "gpmc_ad11", "lcd_data19", "mmc1_dat3", "mmc2_dat7",
67 NULL, NULL, NULL, NULL), 67 NULL, NULL, NULL, NULL),
68 _AM33XX_MUXENTRY(GPMC_AD12, 0, 68 _AM33XX_MUXENTRY(GPMC_AD12, 0,
69 "gpmc_ad12", "lcd_data20", "mmc1_dat4", "mmc2_dat0", 69 "gpmc_ad12", "lcd_data20", "mmc1_dat4", "mmc2_dat0",
70 NULL, NULL, NULL, NULL), 70 NULL, NULL, NULL, NULL),
71 _AM33XX_MUXENTRY(GPMC_AD13, 0, 71 _AM33XX_MUXENTRY(GPMC_AD13, 0,
72 "gpmc_ad13", "lcd_data21", "mmc1_dat5", "mmc2_dat1", 72 "gpmc_ad13", "lcd_data21", "mmc1_dat5", "mmc2_dat1",
73 NULL, NULL, NULL, NULL), 73 NULL, NULL, NULL, NULL),
74 _AM33XX_MUXENTRY(GPMC_AD14, 0, 74 _AM33XX_MUXENTRY(GPMC_AD14, 0,
75 "gpmc_ad14", "lcd_data22", "mmc1_dat6", "mmc2_dat2", 75 "gpmc_ad14", "lcd_data22", "mmc1_dat6", "mmc2_dat2",
76 NULL, NULL, NULL, NULL), 76 NULL, NULL, NULL, NULL),
77 _AM33XX_MUXENTRY(GPMC_AD15, 0, 77 _AM33XX_MUXENTRY(GPMC_AD15, 0,
78 "gpmc_ad15", "lcd_data23", "mmc1_dat7", "mmc2_dat3", 78 "gpmc_ad15", "lcd_data23", "mmc1_dat7", "mmc2_dat3",
79 NULL, NULL, NULL, NULL), 79 NULL, NULL, NULL, NULL),
80 _AM33XX_MUXENTRY(GPMC_A0, 0, 80 _AM33XX_MUXENTRY(GPMC_A0, 0,
81 "gpmc_a0", "mii2_txen", "rgmii2_tctl", "rmii2_txen", 81 "gpmc_a0", "mii2_txen", "rgmii2_tctl", "rmii2_txen",
82 NULL, NULL, NULL, "gpio1_16"), 82 NULL, NULL, NULL, "gpio1_16"),
83 _AM33XX_MUXENTRY(GPMC_A1, 0, 83 _AM33XX_MUXENTRY(GPMC_A1, 0,
84 "gpmc_a1", "mii2_rxdv", "rgmii2_rctl", "mmc2_dat0", 84 "gpmc_a1", "mii2_rxdv", "rgmii2_rctl", "mmc2_dat0",
85 NULL, NULL, NULL, NULL), 85 NULL, NULL, NULL, NULL),
86 _AM33XX_MUXENTRY(GPMC_A2, 0, 86 _AM33XX_MUXENTRY(GPMC_A2, 0,
87 "gpmc_a2", "mii2_txd3", "rgmii2_td3", "mmc2_dat1", 87 "gpmc_a2", "mii2_txd3", "rgmii2_td3", "mmc2_dat1",
88 NULL, NULL, NULL, NULL), 88 NULL, NULL, NULL, NULL),
89 _AM33XX_MUXENTRY(GPMC_A3, 0, 89 _AM33XX_MUXENTRY(GPMC_A3, 0,
90 "gpmc_a3", "mii2_txd2", "rgmii2_td2", "mmc2_dat2", 90 "gpmc_a3", "mii2_txd2", "rgmii2_td2", "mmc2_dat2",
91 NULL, NULL, NULL, NULL), 91 NULL, NULL, NULL, NULL),
92 _AM33XX_MUXENTRY(GPMC_A4, 0, 92 _AM33XX_MUXENTRY(GPMC_A4, 0,
93 "gpmc_a4", "mii2_txd1", "rgmii2_td1", "rmii2_txd1", 93 "gpmc_a4", "mii2_txd1", "rgmii2_td1", "rmii2_txd1",
94 "gpmc_a20", NULL, NULL, NULL), 94 "gpmc_a20", NULL, NULL, NULL),
95 _AM33XX_MUXENTRY(GPMC_A5, 0, 95 _AM33XX_MUXENTRY(GPMC_A5, 0,
96 "gpmc_a5", "mii2_txd0", "rgmii2_td0", "rmii2_txd0", 96 "gpmc_a5", "mii2_txd0", "rgmii2_td0", "rmii2_txd0",
97 "gpmc_a21", NULL, NULL, "gpio1_21"), 97 "gpmc_a21", NULL, NULL, "gpio1_21"),
98 _AM33XX_MUXENTRY(GPMC_A6, 0, 98 _AM33XX_MUXENTRY(GPMC_A6, 0,
99 "gpmc_a6", "mii2_txclk", "rgmii2_tclk", "mmc2_dat4", 99 "gpmc_a6", "mii2_txclk", "rgmii2_tclk", "mmc2_dat4",
100 "gpmc_a22", NULL, NULL, NULL), 100 "gpmc_a22", NULL, NULL, "gpio1_22"),
101 _AM33XX_MUXENTRY(GPMC_A7, 0, 101 _AM33XX_MUXENTRY(GPMC_A7, 0,
102 "gpmc_a7", "mii2_rxclk", "rgmii2_rclk", "mmc2_dat5", 102 "gpmc_a7", "mii2_rxclk", "rgmii2_rclk", "mmc2_dat5",
103 NULL, NULL, NULL, NULL), 103 NULL, NULL, NULL, NULL),
104 _AM33XX_MUXENTRY(GPMC_A8, 0, 104 _AM33XX_MUXENTRY(GPMC_A8, 0,
105 "gpmc_a8", "mii2_rxd3", "rgmii2_rd3", "mmc2_dat6", 105 "gpmc_a8", "mii2_rxd3", "rgmii2_rd3", "mmc2_dat6",
106 NULL, NULL, "mcasp0_aclkx", "gpio1_24"), 106 NULL, NULL, "mcasp0_aclkx", "gpio1_24"),
107 _AM33XX_MUXENTRY(GPMC_A9, 0, 107 _AM33XX_MUXENTRY(GPMC_A9, 0,
108 "gpmc_a9", "mii2_rxd2", "rgmii2_rd2", "mmc2_dat7", 108 "gpmc_a9", "mii2_rxd2", "rgmii2_rd2", "mmc2_dat7",
109 NULL, NULL, "mcasp0_fsx", "gpio1_25"), 109 NULL, NULL, "mcasp0_fsx", "gpio1_25"),
110 _AM33XX_MUXENTRY(GPMC_A10, 0, 110 _AM33XX_MUXENTRY(GPMC_A10, 0,
111 "gpmc_a10", "mii2_rxd1", "rgmii2_rd1", "rmii2_rxd1", 111 "gpmc_a10", "mii2_rxd1", "rgmii2_rd1", "rmii2_rxd1",
112 NULL, NULL, "mcasp0_axr0", "gpio1_26"), 112 NULL, NULL, "mcasp0_axr0", "gpio1_26"),
113 _AM33XX_MUXENTRY(GPMC_A11, 0, 113 _AM33XX_MUXENTRY(GPMC_A11, 0,
114 "gpmc_a11", "mii2_rxd0", "rgmii2_rd0", "rmii2_rxd0", 114 "gpmc_a11", "mii2_rxd0", "rgmii2_rd0", "rmii2_rxd0",
115 NULL, NULL, "mcasp0_axr1", "gpio1_27"), 115 NULL, NULL, "mcasp0_axr1", "gpio1_27"),
116 _AM33XX_MUXENTRY(GPMC_WAIT0, 0, 116 _AM33XX_MUXENTRY(GPMC_WAIT0, 0,
117 "gpmc_wait0", "mii2_crs", NULL, "rmii2_crs_dv", 117 "gpmc_wait0", "mii2_crs", NULL, "rmii2_crs_dv",
118 "mmc1_sdcd", NULL, NULL, NULL), 118 "mmc1_sdcd", NULL, NULL, NULL),
119 _AM33XX_MUXENTRY(GPMC_WPN, 0, 119 _AM33XX_MUXENTRY(GPMC_WPN, 0,
120 "gpmc_wpn", "mii2_rxerr", NULL, "rmii2_rxerr", 120 "gpmc_wpn", "mii2_rxerr", NULL, "rmii2_rxerr",
121 "mmc2_sdcd", NULL, NULL, NULL), 121 "mmc2_sdcd", NULL, NULL, NULL),
122 _AM33XX_MUXENTRY(GPMC_BEN1, 0, 122 _AM33XX_MUXENTRY(GPMC_BEN1, 0,
123 "gpmc_ben1", "mii2_col", NULL, "mmc2_dat3", 123 "gpmc_ben1", "mii2_col", NULL, "mmc2_dat3",
124 NULL, NULL, "mcasp0_aclkr", NULL), 124 NULL, NULL, "mcasp0_aclkr", NULL),
125 _AM33XX_MUXENTRY(GPMC_CSN0, 0, 125 _AM33XX_MUXENTRY(GPMC_CSN0, 0,
126 "gpmc_csn0", NULL, NULL, NULL, 126 "gpmc_csn0", NULL, NULL, NULL,
127 NULL, NULL, NULL, "mmc1_sdwp"), 127 NULL, NULL, NULL, "mmc1_sdwp"),
128 _AM33XX_MUXENTRY(GPMC_CSN1, 0, 128 _AM33XX_MUXENTRY(GPMC_CSN1, 0,
129 "gpmc_csn1", NULL, "mmc1_clk", NULL, 129 "gpmc_csn1", NULL, "mmc1_clk", NULL,
130 NULL, NULL, NULL, "gpio1_30"), 130 NULL, NULL, NULL, "gpio1_30"),
131 _AM33XX_MUXENTRY(GPMC_CSN2, 0, 131 _AM33XX_MUXENTRY(GPMC_CSN2, 0,
132 "gpmc_csn2", NULL, "mmc1_cmd", NULL, 132 "gpmc_csn2", NULL, "mmc1_cmd", NULL,
133 NULL, NULL, NULL, "gpio1_31"), 133 NULL, NULL, NULL, "gpio1_31"),
134 _AM33XX_MUXENTRY(GPMC_CSN3, 0, 134 _AM33XX_MUXENTRY(GPMC_CSN3, 0,
135 "gpmc_csn3", NULL, NULL, "mmc2_cmd", 135 "gpmc_csn3", NULL, NULL, "mmc2_cmd",
136 NULL, NULL, NULL, NULL), 136 NULL, NULL, NULL, NULL),
137 _AM33XX_MUXENTRY(GPMC_CLK, 0, 137 _AM33XX_MUXENTRY(GPMC_CLK, 0,
138 "gpmc_clk", NULL, NULL, "mmc2_clk", 138 "gpmc_clk", NULL, NULL, "mmc2_clk",
139 NULL, NULL, "mcasp0_fsr", NULL), 139 NULL, NULL, "mcasp0_fsr", NULL),
140 _AM33XX_MUXENTRY(GPMC_ADVN_ALE, 0, 140 _AM33XX_MUXENTRY(GPMC_ADVN_ALE, 0,
141 "gpmc_advn_ale", NULL, NULL, NULL, 141 "gpmc_advn_ale", NULL, NULL, NULL,
142 NULL, NULL, NULL, "mmc1_sdcd"), 142 NULL, NULL, NULL, "mmc1_sdcd"),
143 _AM33XX_MUXENTRY(GPMC_OEN_REN, 0, 143 _AM33XX_MUXENTRY(GPMC_OEN_REN, 0,
144 "gpmc_oen_ren", NULL, NULL, NULL, 144 "gpmc_oen_ren", NULL, NULL, NULL,
145 NULL, NULL, NULL, NULL), 145 NULL, NULL, NULL, NULL),
146 _AM33XX_MUXENTRY(GPMC_WEN, 0, 146 _AM33XX_MUXENTRY(GPMC_WEN, 0,
147 "gpmc_wen", NULL, NULL, NULL, 147 "gpmc_wen", NULL, NULL, NULL,
148 NULL, NULL, NULL, NULL), 148 NULL, NULL, NULL, NULL),
149 _AM33XX_MUXENTRY(GPMC_BEN0_CLE, 0, 149 _AM33XX_MUXENTRY(GPMC_BEN0_CLE, 0,
150 "gpmc_ben0_cle", NULL, NULL, NULL, 150 "gpmc_ben0_cle", NULL, NULL, NULL,
151 NULL, NULL, NULL, NULL), 151 NULL, NULL, NULL, NULL),
152 _AM33XX_MUXENTRY(LCD_DATA0, 0, 152 _AM33XX_MUXENTRY(LCD_DATA0, 0,
153 "lcd_data0", "gpmc_a0", NULL, NULL, 153 "lcd_data0", "gpmc_a0", NULL, NULL,
154 NULL, NULL, NULL, NULL), 154 NULL, NULL, NULL, NULL),
155 _AM33XX_MUXENTRY(LCD_DATA1, 0, 155 _AM33XX_MUXENTRY(LCD_DATA1, 0,
156 "lcd_data1", "gpmc_a1", NULL, NULL, 156 "lcd_data1", "gpmc_a1", NULL, NULL,
157 NULL, NULL, NULL, NULL), 157 NULL, NULL, NULL, NULL),
158 _AM33XX_MUXENTRY(LCD_DATA2, 0, 158 _AM33XX_MUXENTRY(LCD_DATA2, 0,
159 "lcd_data2", "gpmc_a2", NULL, NULL, 159 "lcd_data2", "gpmc_a2", NULL, NULL,
160 NULL, NULL, NULL, NULL), 160 NULL, NULL, NULL, NULL),
161 _AM33XX_MUXENTRY(LCD_DATA3, 0, 161 _AM33XX_MUXENTRY(LCD_DATA3, 0,
162 "lcd_data3", "gpmc_a3", NULL, NULL, 162 "lcd_data3", "gpmc_a3", NULL, NULL,
163 NULL, NULL, NULL, NULL), 163 NULL, NULL, NULL, NULL),
164 _AM33XX_MUXENTRY(LCD_DATA4, 0, 164 _AM33XX_MUXENTRY(LCD_DATA4, 0,
165 "lcd_data4", "gpmc_a4", NULL, NULL, 165 "lcd_data4", "gpmc_a4", NULL, NULL,
166 NULL, NULL, NULL, NULL), 166 NULL, NULL, NULL, NULL),
167 _AM33XX_MUXENTRY(LCD_DATA5, 0, 167 _AM33XX_MUXENTRY(LCD_DATA5, 0,
168 "lcd_data5", "gpmc_a5", NULL, NULL, 168 "lcd_data5", "gpmc_a5", NULL, NULL,
169 NULL, NULL, NULL, NULL), 169 NULL, NULL, NULL, NULL),
170 _AM33XX_MUXENTRY(LCD_DATA6, 0, 170 _AM33XX_MUXENTRY(LCD_DATA6, 0,
171 "lcd_data6", "gpmc_a6", NULL, NULL, 171 "lcd_data6", "gpmc_a6", NULL, NULL,
172 NULL, NULL, NULL, NULL), 172 NULL, NULL, NULL, NULL),
173 _AM33XX_MUXENTRY(LCD_DATA7, 0, 173 _AM33XX_MUXENTRY(LCD_DATA7, 0,
174 "lcd_data7", "gpmc_a7", NULL, NULL, 174 "lcd_data7", "gpmc_a7", NULL, NULL,
175 NULL, NULL, NULL, NULL), 175 NULL, NULL, NULL, NULL),
176 _AM33XX_MUXENTRY(LCD_DATA8, 0, 176 _AM33XX_MUXENTRY(LCD_DATA8, 0,
177 "lcd_data8", "gpmc_a12", NULL, "mcasp0_aclkx", 177 "lcd_data8", "gpmc_a12", NULL, "mcasp0_aclkx",
178 NULL, NULL, NULL, NULL), 178 NULL, NULL, NULL, NULL),
179 _AM33XX_MUXENTRY(LCD_DATA9, 0, 179 _AM33XX_MUXENTRY(LCD_DATA9, 0,
180 "lcd_data9", "gpmc_a13", NULL, "mcasp0_fsx", 180 "lcd_data9", "gpmc_a13", NULL, "mcasp0_fsx",
181 NULL, NULL, NULL, NULL), 181 NULL, NULL, NULL, NULL),
182 _AM33XX_MUXENTRY(LCD_DATA10, 0, 182 _AM33XX_MUXENTRY(LCD_DATA10, 0,
183 "lcd_data10", "gpmc_a14", NULL, "mcasp0_axr0", 183 "lcd_data10", "gpmc_a14", NULL, "mcasp0_axr0",
184 NULL, NULL, NULL, NULL), 184 NULL, NULL, NULL, NULL),
185 _AM33XX_MUXENTRY(LCD_DATA11, 0, 185 _AM33XX_MUXENTRY(LCD_DATA11, 0,
186 "lcd_data11", "gpmc_a15", NULL, "mcasp0_ahclkr", 186 "lcd_data11", "gpmc_a15", NULL, "mcasp0_ahclkr",
187 "mcasp0_axr2", NULL, NULL, NULL), 187 "mcasp0_axr2", NULL, NULL, NULL),
188 _AM33XX_MUXENTRY(LCD_DATA12, 0, 188 _AM33XX_MUXENTRY(LCD_DATA12, 0,
189 "lcd_data12", "gpmc_a16", NULL, "mcasp0_aclkr", 189 "lcd_data12", "gpmc_a16", NULL, "mcasp0_aclkr",
190 "mcasp0_axr2", NULL, NULL, NULL), 190 "mcasp0_axr2", NULL, NULL, NULL),
191 _AM33XX_MUXENTRY(LCD_DATA13, 0, 191 _AM33XX_MUXENTRY(LCD_DATA13, 0,
192 "lcd_data13", "gpmc_a17", NULL, "mcasp0_fsr", 192 "lcd_data13", "gpmc_a17", NULL, "mcasp0_fsr",
193 "mcasp0_axr3", NULL, NULL, NULL), 193 "mcasp0_axr3", NULL, NULL, NULL),
194 _AM33XX_MUXENTRY(LCD_DATA14, 0, 194 _AM33XX_MUXENTRY(LCD_DATA14, 0,
195 "lcd_data14", "gpmc_a18", NULL, "mcasp0_axr1", 195 "lcd_data14", "gpmc_a18", NULL, "mcasp0_axr1",
196 NULL, NULL, NULL, NULL), 196 NULL, NULL, NULL, NULL),
197 _AM33XX_MUXENTRY(LCD_DATA15, 0, 197 _AM33XX_MUXENTRY(LCD_DATA15, 0,
198 "lcd_data15", "gpmc_a19", NULL, "mcasp0_ahclkx", 198 "lcd_data15", "gpmc_a19", NULL, "mcasp0_ahclkx",
199 "mcasp0_axr3", NULL, NULL, NULL), 199 "mcasp0_axr3", NULL, NULL, NULL),
200 _AM33XX_MUXENTRY(LCD_VSYNC, 0, 200 _AM33XX_MUXENTRY(LCD_VSYNC, 0,
201 "lcd_vsync", NULL, NULL, NULL, 201 "lcd_vsync", NULL, NULL, NULL,
202 NULL, NULL, NULL, NULL), 202 NULL, NULL, NULL, NULL),
203 _AM33XX_MUXENTRY(LCD_HSYNC, 0, 203 _AM33XX_MUXENTRY(LCD_HSYNC, 0,
204 "lcd_hsync", NULL, NULL, NULL, 204 "lcd_hsync", NULL, NULL, NULL,
205 NULL, NULL, NULL, NULL), 205 NULL, NULL, NULL, NULL),
206 _AM33XX_MUXENTRY(LCD_PCLK, 0, 206 _AM33XX_MUXENTRY(LCD_PCLK, 0,
207 "lcd_pclk", NULL, NULL, NULL, 207 "lcd_pclk", NULL, NULL, NULL,
208 NULL, NULL, NULL, NULL), 208 NULL, NULL, NULL, NULL),
209 _AM33XX_MUXENTRY(LCD_AC_BIAS_EN, 0, 209 _AM33XX_MUXENTRY(LCD_AC_BIAS_EN, 0,
210 "lcd_ac_bias_en", NULL, NULL, NULL, 210 "lcd_ac_bias_en", NULL, NULL, NULL,
211 NULL, NULL, NULL, "gpio2_25"), 211 NULL, NULL, NULL, "gpio2_25"),
212 _AM33XX_MUXENTRY(GPMC_CLK, 0, 212 _AM33XX_MUXENTRY(GPMC_CLK, 0,
213 "gpmc_clk", "lcd_memory_clk_mux", NULL, NULL, 213 "gpmc_clk", "lcd_memory_clk_mux", NULL, NULL,
214 NULL, NULL, NULL, NULL), 214 NULL, NULL, NULL, NULL),
215 _AM33XX_MUXENTRY(MMC0_DAT3, 0, 215 _AM33XX_MUXENTRY(MMC0_DAT3, 0,
216 "mmc0_dat3", NULL, NULL, NULL, 216 "mmc0_dat3", NULL, NULL, NULL,
217 NULL, NULL, NULL, NULL), 217 NULL, NULL, NULL, NULL),
218 _AM33XX_MUXENTRY(MMC0_DAT2, 0, 218 _AM33XX_MUXENTRY(MMC0_DAT2, 0,
219 "mmc0_dat2", NULL, NULL, NULL, 219 "mmc0_dat2", NULL, NULL, NULL,
220 NULL, NULL, NULL, NULL), 220 NULL, NULL, NULL, NULL),
221 _AM33XX_MUXENTRY(MMC0_DAT1, 0, 221 _AM33XX_MUXENTRY(MMC0_DAT1, 0,
222 "mmc0_dat1", NULL, NULL, NULL, 222 "mmc0_dat1", NULL, NULL, NULL,
223 NULL, NULL, NULL, NULL), 223 NULL, NULL, NULL, NULL),
224 _AM33XX_MUXENTRY(MMC0_DAT0, 0, 224 _AM33XX_MUXENTRY(MMC0_DAT0, 0,
225 "mmc0_dat0", NULL, NULL, NULL, 225 "mmc0_dat0", NULL, NULL, NULL,
226 NULL, NULL, NULL, NULL), 226 NULL, NULL, NULL, NULL),
227 _AM33XX_MUXENTRY(MMC0_CLK, 0, 227 _AM33XX_MUXENTRY(MMC0_CLK, 0,
228 "mmc0_clk", NULL, NULL, NULL, 228 "mmc0_clk", NULL, NULL, NULL,
229 NULL, NULL, NULL, NULL), 229 NULL, NULL, NULL, NULL),
230 _AM33XX_MUXENTRY(MMC0_CMD, 0, 230 _AM33XX_MUXENTRY(MMC0_CMD, 0,
231 "mmc0_cmd", NULL, NULL, NULL, 231 "mmc0_cmd", NULL, NULL, NULL,
232 NULL, NULL, NULL, NULL), 232 NULL, NULL, NULL, NULL),
233 _AM33XX_MUXENTRY(MII1_COL, 0, 233 _AM33XX_MUXENTRY(MII1_COL, 0,
234 "mii1_col", "rmii2_refclk", "spi1_sclk", NULL, 234 "mii1_col", "rmii2_refclk", "spi1_sclk", NULL,
235 "mcasp1_axr2", "mmc2_dat3", "mcasp0_axr2", NULL), 235 "mcasp1_axr2", "mmc2_dat3", "mcasp0_axr2", NULL),
236 _AM33XX_MUXENTRY(MII1_CRS, 0, 236 _AM33XX_MUXENTRY(MII1_CRS, 0,
237 "mii1_crs", "rmii1_crs_dv", "spi1_d0", NULL, 237 "mii1_crs", "rmii1_crs_dv", "spi1_d0", NULL,
238 "mcasp1_aclkx", NULL, NULL, NULL), 238 "mcasp1_aclkx", NULL, NULL, NULL),
239 _AM33XX_MUXENTRY(MII1_RXERR, 0, 239 _AM33XX_MUXENTRY(MII1_RXERR, 0,
240 "mii1_rxerr", "rmii1_rxerr", "spi1_d1", NULL, 240 "mii1_rxerr", "rmii1_rxerr", "spi1_d1", NULL,
241 "mcasp1_fsx", NULL, NULL, NULL), 241 "mcasp1_fsx", NULL, NULL, NULL),
242 _AM33XX_MUXENTRY(MII1_TXEN, 0, 242 _AM33XX_MUXENTRY(MII1_TXEN, 0,
243 "mii1_txen", "rmii1_txen", "rgmii1_tctl", NULL, 243 "mii1_txen", "rmii1_txen", "rgmii1_tctl", NULL,
244 "mcasp1_axr0", NULL, "mmc2_cmd", NULL), 244 "mcasp1_axr0", NULL, "mmc2_cmd", NULL),
245 _AM33XX_MUXENTRY(MII1_RXDV, 0, 245 _AM33XX_MUXENTRY(MII1_RXDV, 0,
246 "mii1_rxdv", NULL, "rgmii1_rctl", NULL, 246 "mii1_rxdv", NULL, "rgmii1_rctl", NULL,
247 "mcasp1_aclx", "mmc2_dat0", "mcasp0_aclkr", NULL), 247 "mcasp1_aclx", "mmc2_dat0", "mcasp0_aclkr", NULL),
248 _AM33XX_MUXENTRY(MII1_TXD3, 0, 248 _AM33XX_MUXENTRY(MII1_TXD3, 0,
249 "mii1_txd3", NULL, "rgmii1_td3", NULL, 249 "mii1_txd3", NULL, "rgmii1_td3", NULL,
250 "mcasp1_fsx", "mmc2_dat1", "mcasp0_fsr", NULL), 250 "mcasp1_fsx", "mmc2_dat1", "mcasp0_fsr", NULL),
251 _AM33XX_MUXENTRY(MII1_TXD2, 0, 251 _AM33XX_MUXENTRY(MII1_TXD2, 0,
252 "mii1_txd2", NULL, "rgmii1_td2", NULL, 252 "mii1_txd2", NULL, "rgmii1_td2", NULL,
253 "mcasp1_axr0", "mmc2_dat2", "mcasp0_ahclkx", NULL), 253 "mcasp1_axr0", "mmc2_dat2", "mcasp0_ahclkx", NULL),
254 _AM33XX_MUXENTRY(MII1_TXD1, 0, 254 _AM33XX_MUXENTRY(MII1_TXD1, 0,
255 "mii1_txd1", "rmii1_txd1", "rgmii1_td1", "mcasp1_fsr", 255 "mii1_txd1", "rmii1_txd1", "rgmii1_td1", "mcasp1_fsr",
256 "mcasp1_axr1", NULL, "mmc1_cmd", NULL), 256 "mcasp1_axr1", NULL, "mmc1_cmd", NULL),
257 _AM33XX_MUXENTRY(MII1_TXD0, 0, 257 _AM33XX_MUXENTRY(MII1_TXD0, 0,
258 "mii1_txd0", "rmii1_txd0", "rgmii1_td0", "mcasp1_axr2", 258 "mii1_txd0", "rmii1_txd0", "rgmii1_td0", "mcasp1_axr2",
259 "mcasp1_aclkr", NULL, "mmc1_clk", NULL), 259 "mcasp1_aclkr", NULL, "mmc1_clk", NULL),
260 _AM33XX_MUXENTRY(MII1_TXCLK, 0, 260 _AM33XX_MUXENTRY(MII1_TXCLK, 0,
261 "mii1_txclk", NULL, "rgmii1_tclk", "mmc0_dat7", 261 "mii1_txclk", NULL, "rgmii1_tclk", "mmc0_dat7",
262 "mmc1_dat0", NULL, "mcasp0_aclkx", NULL), 262 "mmc1_dat0", NULL, "mcasp0_aclkx", NULL),
263 _AM33XX_MUXENTRY(MII1_RXCLK, 0, 263 _AM33XX_MUXENTRY(MII1_RXCLK, 0,
264 "mii1_rxclk", NULL, "rgmii1_rclk", "mmc0_dat6", 264 "mii1_rxclk", NULL, "rgmii1_rclk", "mmc0_dat6",
265 "mmc1_dat1", NULL, "mcasp0_fsx", NULL), 265 "mmc1_dat1", NULL, "mcasp0_fsx", NULL),
266 _AM33XX_MUXENTRY(MII1_RXD3, 0, 266 _AM33XX_MUXENTRY(MII1_RXD3, 0,
267 "mii1_rxd3", NULL, "rgmii1_rd3", "mmc0_dat5", 267 "mii1_rxd3", NULL, "rgmii1_rd3", "mmc0_dat5",
268 "mmc1_dat2", NULL, "mcasp0_axr0", NULL), 268 "mmc1_dat2", NULL, "mcasp0_axr0", NULL),
269 _AM33XX_MUXENTRY(MII1_RXD2, 0, 269 _AM33XX_MUXENTRY(MII1_RXD2, 0,
270 "mii1_rxd2", NULL, "rgmii1_rd2", "mmc0_dat4", 270 "mii1_rxd2", NULL, "rgmii1_rd2", "mmc0_dat4",
271 "mmc1_dat3", NULL, "mcasp0_axr1", NULL), 271 "mmc1_dat3", NULL, "mcasp0_axr1", NULL),
272 _AM33XX_MUXENTRY(MII1_RXD1, 0, 272 _AM33XX_MUXENTRY(MII1_RXD1, 0,
273 "mii1_rxd1", "rmii1_rxd1", "rgmii1_rd1", "mcasp1_axr3", 273 "mii1_rxd1", "rmii1_rxd1", "rgmii1_rd1", "mcasp1_axr3",
274 "mcasp1_fsr", NULL, "mmc2_clk", NULL), 274 "mcasp1_fsr", NULL, "mmc2_clk", NULL),
275 _AM33XX_MUXENTRY(MII1_RXD0, 0, 275 _AM33XX_MUXENTRY(MII1_RXD0, 0,
276 "mii1_rxd0", "rmii1_rxd0", "rgmii1_rd0", "mcasp1_ahclkx", 276 "mii1_rxd0", "rmii1_rxd0", "rgmii1_rd0", "mcasp1_ahclkx",
277 "mcasp1_ahclkr", "mcasp1_aclkr", "mcasp0_axr3", NULL), 277 "mcasp1_ahclkr", "mcasp1_aclkr", "mcasp0_axr3", NULL),
278 _AM33XX_MUXENTRY(MII1_REFCLK, 0, 278 _AM33XX_MUXENTRY(MII1_REFCLK, 0,
279 "rmii1_refclk", NULL, "spi1_cs0", NULL, 279 "rmii1_refclk", NULL, "spi1_cs0", NULL,
280 "mcasp1_axr3", "mmc0_pow", "mcasp1_ahclkx", NULL), 280 "mcasp1_axr3", "mmc0_pow", "mcasp1_ahclkx", NULL),
281 _AM33XX_MUXENTRY(MDIO_DATA, 0, 281 _AM33XX_MUXENTRY(MDIO_DATA, 0,
282 "mdio_data", NULL, NULL, NULL, 282 "mdio_data", NULL, NULL, NULL,
283 "mmc0_sdcd", "mmc1_cmd", "mmc2_cmd", NULL), 283 "mmc0_sdcd", "mmc1_cmd", "mmc2_cmd", NULL),
284 _AM33XX_MUXENTRY(MDIO_CLK, 0, 284 _AM33XX_MUXENTRY(MDIO_CLK, 0,
285 "mdio_clk", NULL, NULL, NULL, 285 "mdio_clk", NULL, NULL, NULL,
286 "mmc0_sdwp", "mmc1_clk", "mmc2_clk", NULL), 286 "mmc0_sdwp", "mmc1_clk", "mmc2_clk", NULL),
287 _AM33XX_MUXENTRY(SPI0_SCLK, 0, 287 _AM33XX_MUXENTRY(SPI0_SCLK, 0,
288 "spi0_sclk", NULL, NULL, NULL, 288 "spi0_sclk", NULL, NULL, NULL,
289 NULL, NULL, NULL, "gpio0_2"), 289 NULL, NULL, NULL, "gpio0_2"),
290 _AM33XX_MUXENTRY(SPI0_D0, 0, 290 _AM33XX_MUXENTRY(SPI0_D0, 0,
291 "spi0_d0", NULL, NULL, NULL, 291 "spi0_d0", NULL, NULL, NULL,
292 NULL, NULL, NULL, "gpio0_3"), 292 NULL, NULL, NULL, "gpio0_3"),
293 _AM33XX_MUXENTRY(SPI0_D1, 0, 293 _AM33XX_MUXENTRY(SPI0_D1, 0,
294 "spi0_d1", "mmc1_sdwp", "i2c1_sda", NULL, 294 "spi0_d1", "mmc1_sdwp", "i2c1_sda", NULL,
295 NULL, NULL, NULL, NULL), 295 NULL, NULL, NULL, NULL),
296 _AM33XX_MUXENTRY(SPI0_CS0, 0, 296 _AM33XX_MUXENTRY(SPI0_CS0, 0,
297 "spi0_cs0", "mmc2_sdwp", "i2c1_scl", NULL, 297 "spi0_cs0", "mmc2_sdwp", "i2c1_scl", NULL,
298 NULL, NULL, NULL, NULL), 298 NULL, NULL, NULL, NULL),
299 _AM33XX_MUXENTRY(SPI0_CS1, 0, 299 _AM33XX_MUXENTRY(SPI0_CS1, 0,
300 "spi0_cs1", "uart3_rxd", NULL, "mmc0_pow", 300 "spi0_cs1", "uart3_rxd", NULL, "mmc0_pow",
301 NULL, "mmc0_sdcd", NULL, NULL), 301 NULL, "mmc0_sdcd", NULL, NULL),
302 _AM33XX_MUXENTRY(ECAP0_IN_PWM0_OUT, 0, 302 _AM33XX_MUXENTRY(ECAP0_IN_PWM0_OUT, 0,
303 "ecap0_in_pwm0_out", "uart3_txd", "spi1_cs1", NULL, 303 "ecap0_in_pwm0_out", "uart3_txd", "spi1_cs1", NULL,
304 "spi1_sclk", "mmc0_sdwp", NULL, "gpio0_7"), 304 "spi1_sclk", "mmc0_sdwp", NULL, "gpio0_7"),
305 _AM33XX_MUXENTRY(UART0_CTSN, 0, 305 _AM33XX_MUXENTRY(UART0_CTSN, 0,
306 "uart0_ctsn", NULL, "d_can1_tx", NULL, 306 "uart0_ctsn", NULL, "d_can1_tx", NULL,
307 "spi1_d0", NULL, NULL, NULL), 307 "spi1_d0", NULL, NULL, NULL),
308 _AM33XX_MUXENTRY(UART0_RTSN, 0, 308 _AM33XX_MUXENTRY(UART0_RTSN, 0,
309 "uart0_rtsn", NULL, "d_can1_rx", NULL, 309 "uart0_rtsn", NULL, "d_can1_rx", NULL,
310 "spi1_d1", "spi1_cs0", NULL, NULL), 310 "spi1_d1", "spi1_cs0", NULL, NULL),
311 _AM33XX_MUXENTRY(UART0_RXD, 0, 311 _AM33XX_MUXENTRY(UART0_RXD, 0,
312 "uart0_rxd", "spi1_cs0", "d_can0_tx", NULL, 312 "uart0_rxd", "spi1_cs0", "d_can0_tx", NULL,
313 NULL, NULL, NULL, NULL), 313 NULL, NULL, NULL, NULL),
314 _AM33XX_MUXENTRY(UART0_TXD, 0, 314 _AM33XX_MUXENTRY(UART0_TXD, 0,
315 "uart0_txd", "spi1_cs1", "d_can0_rx", NULL, 315 "uart0_txd", "spi1_cs1", "d_can0_rx", NULL,
316 NULL, NULL, NULL, NULL), 316 NULL, NULL, NULL, NULL),
317 _AM33XX_MUXENTRY(UART1_CTSN, 0, 317 _AM33XX_MUXENTRY(UART1_CTSN, 0,
318 "uart1_ctsn", NULL, NULL, NULL, 318 "uart1_ctsn", NULL, NULL, NULL,
319 "spi1_cs0", NULL, NULL, NULL), 319 "spi1_cs0", NULL, NULL, NULL),
320 _AM33XX_MUXENTRY(UART1_RTSN, 0, 320 _AM33XX_MUXENTRY(UART1_RTSN, 0,
321 "uart1_rtsn", NULL, NULL, NULL, 321 "uart1_rtsn", NULL, NULL, NULL,
322 "spi1_cs1", NULL, NULL, NULL), 322 "spi1_cs1", NULL, NULL, NULL),
323 _AM33XX_MUXENTRY(UART1_RXD, 0, 323 _AM33XX_MUXENTRY(UART1_RXD, 0,
324 "uart1_rxd", "mmc1_sdwp", NULL, NULL, 324 "uart1_rxd", "mmc1_sdwp", NULL, NULL,
325 NULL, "pr1_uart0_rxd_mux1", NULL, NULL), 325 NULL, "pr1_uart0_rxd_mux1", NULL, NULL),
326 _AM33XX_MUXENTRY(UART1_TXD, 0, 326 _AM33XX_MUXENTRY(UART1_TXD, 0,
327 "uart1_txd", "mmc2_sdwp", NULL, NULL, 327 "uart1_txd", "mmc2_sdwp", NULL, NULL,
328 NULL, "pr1_uart0_txd_mux1", NULL, NULL), 328 NULL, "pr1_uart0_txd_mux1", NULL, NULL),
329 _AM33XX_MUXENTRY(I2C0_SDA, 0, 329 _AM33XX_MUXENTRY(I2C0_SDA, 0,
330 "i2c0_sda", NULL, NULL, NULL, 330 "i2c0_sda", NULL, NULL, NULL,
331 NULL, NULL, NULL, NULL), 331 NULL, NULL, NULL, NULL),
332 _AM33XX_MUXENTRY(I2C0_SCL, 0, 332 _AM33XX_MUXENTRY(I2C0_SCL, 0,
333 "i2c0_scl", NULL, NULL, NULL, 333 "i2c0_scl", NULL, NULL, NULL,
334 NULL, NULL, NULL, NULL), 334 NULL, NULL, NULL, NULL),
335 _AM33XX_MUXENTRY(MCASP0_ACLKX, 0, 335 _AM33XX_MUXENTRY(MCASP0_ACLKX, 0,
336 "mcasp0_aclkx", NULL, NULL, "spi1_sclk", 336 "mcasp0_aclkx", NULL, NULL, "spi1_sclk",
337 "mmc0_sdcd", NULL, NULL, NULL), 337 "mmc0_sdcd", NULL, NULL, NULL),
338 _AM33XX_MUXENTRY(MCASP0_FSX, 0, 338 _AM33XX_MUXENTRY(MCASP0_FSX, 0,
339 "mcasp0_fsx", NULL, NULL, "spi1_d0", 339 "mcasp0_fsx", NULL, NULL, "spi1_d0",
340 "mmc1_sdcd", NULL, NULL, NULL), 340 "mmc1_sdcd", NULL, NULL, NULL),
341 _AM33XX_MUXENTRY(MCASP0_AXR0, 0, 341 _AM33XX_MUXENTRY(MCASP0_AXR0, 0,
342 "mcasp0_axr0", NULL, NULL, "spi1_d1", 342 "mcasp0_axr0", NULL, NULL, "spi1_d1",
343 "mmc2_sdcd", NULL, NULL, NULL), 343 "mmc2_sdcd", NULL, NULL, NULL),
344 _AM33XX_MUXENTRY(MCASP0_AHCLKR, 0, 344 _AM33XX_MUXENTRY(MCASP0_AHCLKR, 0,
345 "mcasp0_ahclkr", NULL, "mcasp0_axr2", "spi1_cs0", 345 "mcasp0_ahclkr", NULL, "mcasp0_axr2", "spi1_cs0",
346 NULL, NULL, NULL, "gpio3_17"), 346 NULL, NULL, NULL, "gpio3_17"),
347 _AM33XX_MUXENTRY(MCASP0_ACLKR, 0, 347 _AM33XX_MUXENTRY(MCASP0_ACLKR, 0,
348 "mcasp0_aclkr", NULL, "mcasp0_axr2", "mcasp1_aclkx", 348 "mcasp0_aclkr", NULL, "mcasp0_axr2", "mcasp1_aclkx",
349 "mmc0_sdwp", NULL, NULL, NULL), 349 "mmc0_sdwp", NULL, NULL, NULL),
350 _AM33XX_MUXENTRY(MCASP0_FSR, 0, 350 _AM33XX_MUXENTRY(MCASP0_FSR, 0,
351 "mcasp0_fsr", NULL, "mcasp0_axr3", "mcasp1_fsx", 351 "mcasp0_fsr", NULL, "mcasp0_axr3", "mcasp1_fsx",
352 NULL, "pr1_pru0_pru_r30_5", NULL, NULL), 352 NULL, "pr1_pru0_pru_r30_5", NULL, NULL),
353 _AM33XX_MUXENTRY(MCASP0_AXR1, 0, 353 _AM33XX_MUXENTRY(MCASP0_AXR1, 0,
354 "mcasp0_axr1", NULL, NULL, "mcasp1_axr0", 354 "mcasp0_axr1", NULL, NULL, "mcasp1_axr0",
355 NULL, NULL, NULL, NULL), 355 NULL, NULL, NULL, NULL),
356 _AM33XX_MUXENTRY(MCASP0_AHCLKX, 0, 356 _AM33XX_MUXENTRY(MCASP0_AHCLKX, 0,
357 "mcasp0_ahclkx", "mcasp0_axr3", NULL, "mcasp1_axr1", 357 "mcasp0_ahclkx", "mcasp0_axr3", NULL, "mcasp1_axr1",
358 NULL, NULL, NULL, "gpio3_21"), 358 NULL, NULL, NULL, "gpio3_21"),
359 _AM33XX_MUXENTRY(XDMA_EVENT_INTR0, 0, 359 _AM33XX_MUXENTRY(XDMA_EVENT_INTR0, 0,
360 "xdma_event_intr0", NULL, NULL, NULL, 360 "xdma_event_intr0", NULL, NULL, NULL,
361 "spi1_cs1", NULL, NULL, NULL), 361 "spi1_cs1", NULL, NULL, NULL),
362 _AM33XX_MUXENTRY(XDMA_EVENT_INTR1, 0, 362 _AM33XX_MUXENTRY(XDMA_EVENT_INTR1, 0,
363 "xdma_event_intr1", NULL, NULL, "clkout2", 363 "xdma_event_intr1", NULL, NULL, "clkout2",
364 NULL, NULL, NULL, NULL), 364 NULL, NULL, NULL, NULL),
365 _AM33XX_MUXENTRY(WARMRSTN, 0, 365 _AM33XX_MUXENTRY(WARMRSTN, 0,
366 NULL, NULL, NULL, NULL, 366 NULL, NULL, NULL, NULL,
367 NULL, NULL, NULL, NULL), 367 NULL, NULL, NULL, NULL),
368 _AM33XX_MUXENTRY(PWRONRSTN, 0, 368 _AM33XX_MUXENTRY(PWRONRSTN, 0,
369 NULL, NULL, NULL, NULL, 369 NULL, NULL, NULL, NULL,
370 NULL, NULL, NULL, NULL), 370 NULL, NULL, NULL, NULL),
371 _AM33XX_MUXENTRY(NMIN, 0, 371 _AM33XX_MUXENTRY(NMIN, 0,
372 NULL, NULL, NULL, NULL, 372 NULL, NULL, NULL, NULL,
373 NULL, NULL, NULL, NULL), 373 NULL, NULL, NULL, NULL),
374 _AM33XX_MUXENTRY(XTALIN, 0, 374 _AM33XX_MUXENTRY(XTALIN, 0,
375 NULL, NULL, NULL, NULL, 375 NULL, NULL, NULL, NULL,
376 NULL, NULL, NULL, NULL), 376 NULL, NULL, NULL, NULL),
377 _AM33XX_MUXENTRY(XTALOUT, 0, 377 _AM33XX_MUXENTRY(XTALOUT, 0,
378 NULL, NULL, NULL, NULL, 378 NULL, NULL, NULL, NULL,
379 NULL, NULL, NULL, NULL), 379 NULL, NULL, NULL, NULL),
380 _AM33XX_MUXENTRY(TMS, 0, 380 _AM33XX_MUXENTRY(TMS, 0,
381 NULL, NULL, NULL, NULL, 381 NULL, NULL, NULL, NULL,
382 NULL, NULL, NULL, NULL), 382 NULL, NULL, NULL, NULL),
383 _AM33XX_MUXENTRY(TDI, 0, 383 _AM33XX_MUXENTRY(TDI, 0,
384 NULL, NULL, NULL, NULL, 384 NULL, NULL, NULL, NULL,
385 NULL, NULL, NULL, NULL), 385 NULL, NULL, NULL, NULL),
386 _AM33XX_MUXENTRY(TDO, 0, 386 _AM33XX_MUXENTRY(TDO, 0,
387 NULL, NULL, NULL, NULL, 387 NULL, NULL, NULL, NULL,
388 NULL, NULL, NULL, NULL), 388 NULL, NULL, NULL, NULL),
389 _AM33XX_MUXENTRY(TCK, 0, 389 _AM33XX_MUXENTRY(TCK, 0,
390 NULL, NULL, NULL, NULL, 390 NULL, NULL, NULL, NULL,
391 NULL, NULL, NULL, NULL), 391 NULL, NULL, NULL, NULL),
392 _AM33XX_MUXENTRY(TRSTN, 0, 392 _AM33XX_MUXENTRY(TRSTN, 0,
393 NULL, NULL, NULL, NULL, 393 NULL, NULL, NULL, NULL,
394 NULL, NULL, NULL, NULL), 394 NULL, NULL, NULL, NULL),
395 _AM33XX_MUXENTRY(EMU0, 0, 395 _AM33XX_MUXENTRY(EMU0, 0,
396 NULL, NULL, NULL, NULL, 396 NULL, NULL, NULL, NULL,
397 NULL, NULL, NULL, NULL), 397 NULL, NULL, NULL, NULL),
398 _AM33XX_MUXENTRY(EMU1, 0, 398 _AM33XX_MUXENTRY(EMU1, 0,
399 NULL, NULL, NULL, NULL, 399 NULL, NULL, NULL, NULL,
400 NULL, NULL, NULL, NULL), 400 NULL, NULL, NULL, NULL),
401 _AM33XX_MUXENTRY(RTC_XTALIN, 0, 401 _AM33XX_MUXENTRY(RTC_XTALIN, 0,
402 NULL, NULL, NULL, NULL, 402 NULL, NULL, NULL, NULL,
403 NULL, NULL, NULL, NULL), 403 NULL, NULL, NULL, NULL),
404 _AM33XX_MUXENTRY(RTC_XTALOUT, 0, 404 _AM33XX_MUXENTRY(RTC_XTALOUT, 0,
405 NULL, NULL, NULL, NULL, 405 NULL, NULL, NULL, NULL,
406 NULL, NULL, NULL, NULL), 406 NULL, NULL, NULL, NULL),
407 _AM33XX_MUXENTRY(RTC_PWRONRSTN, 0, 407 _AM33XX_MUXENTRY(RTC_PWRONRSTN, 0,
408 NULL, NULL, NULL, NULL, 408 NULL, NULL, NULL, NULL,
409 NULL, NULL, NULL, NULL), 409 NULL, NULL, NULL, NULL),
410 _AM33XX_MUXENTRY(PMIC_POWER_EN, 0, 410 _AM33XX_MUXENTRY(PMIC_POWER_EN, 0,
411 NULL, NULL, NULL, NULL, 411 NULL, NULL, NULL, NULL,
412 NULL, NULL, NULL, NULL), 412 NULL, NULL, NULL, NULL),
413 _AM33XX_MUXENTRY(EXT_WAKEUP, 0, 413 _AM33XX_MUXENTRY(EXT_WAKEUP, 0,
414 NULL, NULL, NULL, NULL, 414 NULL, NULL, NULL, NULL,
415 NULL, NULL, NULL, NULL), 415 NULL, NULL, NULL, NULL),
416 _AM33XX_MUXENTRY(USB0_DRVVBUS, 0, 416 _AM33XX_MUXENTRY(USB0_DRVVBUS, 0,
417 "usb0_drvvbus", NULL, NULL, NULL, 417 "usb0_drvvbus", NULL, NULL, NULL,
418 NULL, NULL, NULL, NULL), 418 NULL, NULL, NULL, NULL),
419 _AM33XX_MUXENTRY(USB1_DRVVBUS, 0, 419 _AM33XX_MUXENTRY(USB1_DRVVBUS, 0,
420 "usb1_drvvbus", NULL, NULL, NULL, 420 "usb1_drvvbus", NULL, NULL, NULL,
421 NULL, NULL, NULL, NULL), 421 NULL, NULL, NULL, NULL),
422 _AM33XX_MUXENTRY(DDR_RESETN, 0, 422 _AM33XX_MUXENTRY(DDR_RESETN, 0,
423 NULL, NULL, NULL, NULL, 423 NULL, NULL, NULL, NULL,
424 NULL, NULL, NULL, NULL), 424 NULL, NULL, NULL, NULL),
425 _AM33XX_MUXENTRY(DDR_CSN0, 0, 425 _AM33XX_MUXENTRY(DDR_CSN0, 0,
426 NULL, NULL, NULL, NULL, 426 NULL, NULL, NULL, NULL,
427 NULL, NULL, NULL, NULL), 427 NULL, NULL, NULL, NULL),
428 _AM33XX_MUXENTRY(DDR_CKE, 0, 428 _AM33XX_MUXENTRY(DDR_CKE, 0,
429 NULL, NULL, NULL, NULL, 429 NULL, NULL, NULL, NULL,
430 NULL, NULL, NULL, NULL), 430 NULL, NULL, NULL, NULL),
431 _AM33XX_MUXENTRY(DDR_CK, 0, 431 _AM33XX_MUXENTRY(DDR_CK, 0,
432 NULL, NULL, NULL, NULL, 432 NULL, NULL, NULL, NULL,
433 NULL, NULL, NULL, NULL), 433 NULL, NULL, NULL, NULL),
434 _AM33XX_MUXENTRY(DDR_CKN, 0, 434 _AM33XX_MUXENTRY(DDR_CKN, 0,
435 NULL, NULL, NULL, NULL, 435 NULL, NULL, NULL, NULL,
436 NULL, NULL, NULL, NULL), 436 NULL, NULL, NULL, NULL),
437 _AM33XX_MUXENTRY(DDR_CASN, 0, 437 _AM33XX_MUXENTRY(DDR_CASN, 0,
438 NULL, NULL, NULL, NULL, 438 NULL, NULL, NULL, NULL,
439 NULL, NULL, NULL, NULL), 439 NULL, NULL, NULL, NULL),
440 _AM33XX_MUXENTRY(DDR_RASN, 0, 440 _AM33XX_MUXENTRY(DDR_RASN, 0,
441 NULL, NULL, NULL, NULL, 441 NULL, NULL, NULL, NULL,
442 NULL, NULL, NULL, NULL), 442 NULL, NULL, NULL, NULL),
443 _AM33XX_MUXENTRY(DDR_WEN, 0, 443 _AM33XX_MUXENTRY(DDR_WEN, 0,
444 NULL, NULL, NULL, NULL, 444 NULL, NULL, NULL, NULL,
445 NULL, NULL, NULL, NULL), 445 NULL, NULL, NULL, NULL),
446 _AM33XX_MUXENTRY(DDR_BA0, 0, 446 _AM33XX_MUXENTRY(DDR_BA0, 0,
447 NULL, NULL, NULL, NULL, 447 NULL, NULL, NULL, NULL,
448 NULL, NULL, NULL, NULL), 448 NULL, NULL, NULL, NULL),
449 _AM33XX_MUXENTRY(DDR_BA1, 0, 449 _AM33XX_MUXENTRY(DDR_BA1, 0,
450 NULL, NULL, NULL, NULL, 450 NULL, NULL, NULL, NULL,
451 NULL, NULL, NULL, NULL), 451 NULL, NULL, NULL, NULL),
452 _AM33XX_MUXENTRY(DDR_BA2, 0, 452 _AM33XX_MUXENTRY(DDR_BA2, 0,
453 NULL, NULL, NULL, NULL, 453 NULL, NULL, NULL, NULL,
454 NULL, NULL, NULL, NULL), 454 NULL, NULL, NULL, NULL),
455 _AM33XX_MUXENTRY(DDR_A0, 0, 455 _AM33XX_MUXENTRY(DDR_A0, 0,
456 NULL, NULL, NULL, NULL, 456 NULL, NULL, NULL, NULL,
457 NULL, NULL, NULL, NULL), 457 NULL, NULL, NULL, NULL),
458 _AM33XX_MUXENTRY(DDR_A1, 0, 458 _AM33XX_MUXENTRY(DDR_A1, 0,
459 NULL, NULL, NULL, NULL, 459 NULL, NULL, NULL, NULL,
460 NULL, NULL, NULL, NULL), 460 NULL, NULL, NULL, NULL),
461 _AM33XX_MUXENTRY(DDR_A2, 0, 461 _AM33XX_MUXENTRY(DDR_A2, 0,
462 NULL, NULL, NULL, NULL, 462 NULL, NULL, NULL, NULL,
463 NULL, NULL, NULL, NULL), 463 NULL, NULL, NULL, NULL),
464 _AM33XX_MUXENTRY(DDR_A3, 0, 464 _AM33XX_MUXENTRY(DDR_A3, 0,
465 NULL, NULL, NULL, NULL, 465 NULL, NULL, NULL, NULL,
466 NULL, NULL, NULL, NULL), 466 NULL, NULL, NULL, NULL),
467 _AM33XX_MUXENTRY(DDR_A4, 0, 467 _AM33XX_MUXENTRY(DDR_A4, 0,
468 NULL, NULL, NULL, NULL, 468 NULL, NULL, NULL, NULL,
469 NULL, NULL, NULL, NULL), 469 NULL, NULL, NULL, NULL),
470 _AM33XX_MUXENTRY(DDR_A5, 0, 470 _AM33XX_MUXENTRY(DDR_A5, 0,
471 NULL, NULL, NULL, NULL, 471 NULL, NULL, NULL, NULL,
472 NULL, NULL, NULL, NULL), 472 NULL, NULL, NULL, NULL),
473 _AM33XX_MUXENTRY(DDR_A6, 0, 473 _AM33XX_MUXENTRY(DDR_A6, 0,
474 NULL, NULL, NULL, NULL, 474 NULL, NULL, NULL, NULL,
475 NULL, NULL, NULL, NULL), 475 NULL, NULL, NULL, NULL),
476 _AM33XX_MUXENTRY(DDR_A7, 0, 476 _AM33XX_MUXENTRY(DDR_A7, 0,
477 NULL, NULL, NULL, NULL, 477 NULL, NULL, NULL, NULL,
478 NULL, NULL, NULL, NULL), 478 NULL, NULL, NULL, NULL),
479 _AM33XX_MUXENTRY(DDR_A8, 0, 479 _AM33XX_MUXENTRY(DDR_A8, 0,
480 NULL, NULL, NULL, NULL, 480 NULL, NULL, NULL, NULL,
481 NULL, NULL, NULL, NULL), 481 NULL, NULL, NULL, NULL),
482 _AM33XX_MUXENTRY(DDR_A9, 0, 482 _AM33XX_MUXENTRY(DDR_A9, 0,
483 NULL, NULL, NULL, NULL, 483 NULL, NULL, NULL, NULL,
484 NULL, NULL, NULL, NULL), 484 NULL, NULL, NULL, NULL),
485 _AM33XX_MUXENTRY(DDR_A10, 0, 485 _AM33XX_MUXENTRY(DDR_A10, 0,
486 NULL, NULL, NULL, NULL, 486 NULL, NULL, NULL, NULL,
487 NULL, NULL, NULL, NULL), 487 NULL, NULL, NULL, NULL),
488 _AM33XX_MUXENTRY(DDR_A11, 0, 488 _AM33XX_MUXENTRY(DDR_A11, 0,
489 NULL, NULL, NULL, NULL, 489 NULL, NULL, NULL, NULL,
490 NULL, NULL, NULL, NULL), 490 NULL, NULL, NULL, NULL),
491 _AM33XX_MUXENTRY(DDR_A12, 0, 491 _AM33XX_MUXENTRY(DDR_A12, 0,
492 NULL, NULL, NULL, NULL, 492 NULL, NULL, NULL, NULL,
493 NULL, NULL, NULL, NULL), 493 NULL, NULL, NULL, NULL),
494 _AM33XX_MUXENTRY(DDR_A13, 0, 494 _AM33XX_MUXENTRY(DDR_A13, 0,
495 NULL, NULL, NULL, NULL, 495 NULL, NULL, NULL, NULL,
496 NULL, NULL, NULL, NULL), 496 NULL, NULL, NULL, NULL),
497 _AM33XX_MUXENTRY(DDR_A14, 0, 497 _AM33XX_MUXENTRY(DDR_A14, 0,
498 NULL, NULL, NULL, NULL, 498 NULL, NULL, NULL, NULL,
499 NULL, NULL, NULL, NULL), 499 NULL, NULL, NULL, NULL),
500 _AM33XX_MUXENTRY(DDR_A15, 0, 500 _AM33XX_MUXENTRY(DDR_A15, 0,
501 NULL, NULL, NULL, NULL, 501 NULL, NULL, NULL, NULL,
502 NULL, NULL, NULL, NULL), 502 NULL, NULL, NULL, NULL),
503 _AM33XX_MUXENTRY(DDR_ODT, 0, 503 _AM33XX_MUXENTRY(DDR_ODT, 0,
504 NULL, NULL, NULL, NULL, 504 NULL, NULL, NULL, NULL,
505 NULL, NULL, NULL, NULL), 505 NULL, NULL, NULL, NULL),
506 _AM33XX_MUXENTRY(DDR_D0, 0, 506 _AM33XX_MUXENTRY(DDR_D0, 0,
507 NULL, NULL, NULL, NULL, 507 NULL, NULL, NULL, NULL,
508 NULL, NULL, NULL, NULL), 508 NULL, NULL, NULL, NULL),
509 _AM33XX_MUXENTRY(DDR_D1, 0, 509 _AM33XX_MUXENTRY(DDR_D1, 0,
510 NULL, NULL, NULL, NULL, 510 NULL, NULL, NULL, NULL,
511 NULL, NULL, NULL, NULL), 511 NULL, NULL, NULL, NULL),
512 _AM33XX_MUXENTRY(DDR_D2, 0, 512 _AM33XX_MUXENTRY(DDR_D2, 0,
513 NULL, NULL, NULL, NULL, 513 NULL, NULL, NULL, NULL,
514 NULL, NULL, NULL, NULL), 514 NULL, NULL, NULL, NULL),
515 _AM33XX_MUXENTRY(DDR_D3, 0, 515 _AM33XX_MUXENTRY(DDR_D3, 0,
516 NULL, NULL, NULL, NULL, 516 NULL, NULL, NULL, NULL,
517 NULL, NULL, NULL, NULL), 517 NULL, NULL, NULL, NULL),
518 _AM33XX_MUXENTRY(DDR_D4, 0, 518 _AM33XX_MUXENTRY(DDR_D4, 0,
519 NULL, NULL, NULL, NULL, 519 NULL, NULL, NULL, NULL,
520 NULL, NULL, NULL, NULL), 520 NULL, NULL, NULL, NULL),
521 _AM33XX_MUXENTRY(DDR_D5, 0, 521 _AM33XX_MUXENTRY(DDR_D5, 0,
522 NULL, NULL, NULL, NULL, 522 NULL, NULL, NULL, NULL,
523 NULL, NULL, NULL, NULL), 523 NULL, NULL, NULL, NULL),
524 _AM33XX_MUXENTRY(DDR_D6, 0, 524 _AM33XX_MUXENTRY(DDR_D6, 0,
525 NULL, NULL, NULL, NULL, 525 NULL, NULL, NULL, NULL,
526 NULL, NULL, NULL, NULL), 526 NULL, NULL, NULL, NULL),
527 _AM33XX_MUXENTRY(DDR_D7, 0, 527 _AM33XX_MUXENTRY(DDR_D7, 0,
528 NULL, NULL, NULL, NULL, 528 NULL, NULL, NULL, NULL,
529 NULL, NULL, NULL, NULL), 529 NULL, NULL, NULL, NULL),
530 _AM33XX_MUXENTRY(DDR_D8, 0, 530 _AM33XX_MUXENTRY(DDR_D8, 0,
531 NULL, NULL, NULL, NULL, 531 NULL, NULL, NULL, NULL,
532 NULL, NULL, NULL, NULL), 532 NULL, NULL, NULL, NULL),
533 _AM33XX_MUXENTRY(DDR_D9, 0, 533 _AM33XX_MUXENTRY(DDR_D9, 0,
534 NULL, NULL, NULL, NULL, 534 NULL, NULL, NULL, NULL,
535 NULL, NULL, NULL, NULL), 535 NULL, NULL, NULL, NULL),
536 _AM33XX_MUXENTRY(DDR_D10, 0, 536 _AM33XX_MUXENTRY(DDR_D10, 0,
537 NULL, NULL, NULL, NULL, 537 NULL, NULL, NULL, NULL,
538 NULL, NULL, NULL, NULL), 538 NULL, NULL, NULL, NULL),
539 _AM33XX_MUXENTRY(DDR_D11, 0, 539 _AM33XX_MUXENTRY(DDR_D11, 0,
540 NULL, NULL, NULL, NULL, 540 NULL, NULL, NULL, NULL,
541 NULL, NULL, NULL, NULL), 541 NULL, NULL, NULL, NULL),
542 _AM33XX_MUXENTRY(DDR_D12, 0, 542 _AM33XX_MUXENTRY(DDR_D12, 0,
543 NULL, NULL, NULL, NULL, 543 NULL, NULL, NULL, NULL,
544 NULL, NULL, NULL, NULL), 544 NULL, NULL, NULL, NULL),
545 _AM33XX_MUXENTRY(DDR_D13, 0, 545 _AM33XX_MUXENTRY(DDR_D13, 0,
546 NULL, NULL, NULL, NULL, 546 NULL, NULL, NULL, NULL,
547 NULL, NULL, NULL, NULL), 547 NULL, NULL, NULL, NULL),
548 _AM33XX_MUXENTRY(DDR_D14, 0, 548 _AM33XX_MUXENTRY(DDR_D14, 0,
549 NULL, NULL, NULL, NULL, 549 NULL, NULL, NULL, NULL,
550 NULL, NULL, NULL, NULL), 550 NULL, NULL, NULL, NULL),
551 _AM33XX_MUXENTRY(DDR_D15, 0, 551 _AM33XX_MUXENTRY(DDR_D15, 0,
552 NULL, NULL, NULL, NULL, 552 NULL, NULL, NULL, NULL,
553 NULL, NULL, NULL, NULL), 553 NULL, NULL, NULL, NULL),
554 _AM33XX_MUXENTRY(DDR_DQM0, 0, 554 _AM33XX_MUXENTRY(DDR_DQM0, 0,
555 NULL, NULL, NULL, NULL, 555 NULL, NULL, NULL, NULL,
556 NULL, NULL, NULL, NULL), 556 NULL, NULL, NULL, NULL),
557 _AM33XX_MUXENTRY(DDR_DQM1, 0, 557 _AM33XX_MUXENTRY(DDR_DQM1, 0,
558 NULL, NULL, NULL, NULL, 558 NULL, NULL, NULL, NULL,
559 NULL, NULL, NULL, NULL), 559 NULL, NULL, NULL, NULL),
560 _AM33XX_MUXENTRY(DDR_DQS0, 0, 560 _AM33XX_MUXENTRY(DDR_DQS0, 0,
561 NULL, NULL, NULL, NULL, 561 NULL, NULL, NULL, NULL,
562 NULL, NULL, NULL, NULL), 562 NULL, NULL, NULL, NULL),
563 _AM33XX_MUXENTRY(DDR_DQSN0, 0, 563 _AM33XX_MUXENTRY(DDR_DQSN0, 0,
564 NULL, NULL, NULL, NULL, 564 NULL, NULL, NULL, NULL,
565 NULL, NULL, NULL, NULL), 565 NULL, NULL, NULL, NULL),
566 _AM33XX_MUXENTRY(DDR_DQS1, 0, 566 _AM33XX_MUXENTRY(DDR_DQS1, 0,
567 NULL, NULL, NULL, NULL, 567 NULL, NULL, NULL, NULL,
568 NULL, NULL, NULL, NULL), 568 NULL, NULL, NULL, NULL),
569 _AM33XX_MUXENTRY(DDR_DQSN1, 0, 569 _AM33XX_MUXENTRY(DDR_DQSN1, 0,
570 NULL, NULL, NULL, NULL, 570 NULL, NULL, NULL, NULL,
571 NULL, NULL, NULL, NULL), 571 NULL, NULL, NULL, NULL),
572 _AM33XX_MUXENTRY(DDR_VREF, 0, 572 _AM33XX_MUXENTRY(DDR_VREF, 0,
573 NULL, NULL, NULL, NULL, 573 NULL, NULL, NULL, NULL,
574 NULL, NULL, NULL, NULL), 574 NULL, NULL, NULL, NULL),
575 _AM33XX_MUXENTRY(DDR_VTP, 0, 575 _AM33XX_MUXENTRY(DDR_VTP, 0,
576 NULL, NULL, NULL, NULL, 576 NULL, NULL, NULL, NULL,
577 NULL, NULL, NULL, NULL), 577 NULL, NULL, NULL, NULL),
578 _AM33XX_MUXENTRY(AIN0, 0, 578 _AM33XX_MUXENTRY(AIN0, 0,
579 "ain0", NULL, NULL, NULL, 579 "ain0", NULL, NULL, NULL,
580 NULL, NULL, NULL, NULL), 580 NULL, NULL, NULL, NULL),
581 _AM33XX_MUXENTRY(AIN1, 0, 581 _AM33XX_MUXENTRY(AIN1, 0,
582 "ain1", NULL, NULL, NULL, 582 "ain1", NULL, NULL, NULL,
583 NULL, NULL, NULL, NULL), 583 NULL, NULL, NULL, NULL),
584 _AM33XX_MUXENTRY(AIN2, 0, 584 _AM33XX_MUXENTRY(AIN2, 0,
585 "ain2", NULL, NULL, NULL, 585 "ain2", NULL, NULL, NULL,
586 NULL, NULL, NULL, NULL), 586 NULL, NULL, NULL, NULL),
587 _AM33XX_MUXENTRY(AIN3, 0, 587 _AM33XX_MUXENTRY(AIN3, 0,
588 "ain3", NULL, NULL, NULL, 588 "ain3", NULL, NULL, NULL,
589 NULL, NULL, NULL, NULL), 589 NULL, NULL, NULL, NULL),
590 _AM33XX_MUXENTRY(VREFP, 0, 590 _AM33XX_MUXENTRY(VREFP, 0,
591 "vrefp", NULL, NULL, NULL, 591 "vrefp", NULL, NULL, NULL,
592 NULL, NULL, NULL, NULL), 592 NULL, NULL, NULL, NULL),
593 _AM33XX_MUXENTRY(VREFN, 0, 593 _AM33XX_MUXENTRY(VREFN, 0,
594 "vrefn", NULL, NULL, NULL, 594 "vrefn", NULL, NULL, NULL,
595 NULL, NULL, NULL, NULL), 595 NULL, NULL, NULL, NULL),
596 { .reg_offset = OMAP_MUX_TERMINATOR }, 596 { .reg_offset = OMAP_MUX_TERMINATOR },
597 }; 597 };
598 598
599 int __init am33xx_mux_init(struct omap_board_mux *board_subset) 599 int __init am33xx_mux_init(struct omap_board_mux *board_subset)
600 { 600 {
601 return omap_mux_init("core", 0, AM33XX_CONTROL_PADCONF_MUX_PBASE, 601 return omap_mux_init("core", 0, AM33XX_CONTROL_PADCONF_MUX_PBASE,
602 AM33XX_CONTROL_PADCONF_MUX_SIZE, am33xx_muxmodes, 602 AM33XX_CONTROL_PADCONF_MUX_SIZE, am33xx_muxmodes,
603 NULL, board_subset, NULL); 603 NULL, board_subset, NULL);
604 } 604 }
605 #else 605 #else
606 int __init am33xx_mux_init(struct omap_board_mux *board_subset) 606 int __init am33xx_mux_init(struct omap_board_mux *board_subset)
607 { 607 {
608 return 0; 608 return 0;
609 } 609 }
610 #endif 610 #endif
611 611