25 Jan, 2012
1 commit
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Default timing causes issues with OOB data corruption on reading and
causes UBIFS torture test. To resolve the above issue, NAND was tested
with different timings and optimal timings were adapted after repeated
tests and trials.Signed-off-by: Philip, Avinash
22 Dec, 2011
1 commit
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LCDC functional clock may or may not be derived from CPU/MPU DPLL,
For example,
AM335x => Separate independent DPLL for LCDC
Davinci => Same DPLL as MPUSo, on platforms where LCDC functional clock is not derived from CPU/MPU
PLL it is not required to reset LCDC module as its functional clock does
not change with DVFS.This patch adds check to do reset only if functional clock changes
between pre and post notifier callbacks with DVFS.Signed-off-by: Manjunathappa, Prakash
16 Dec, 2011
1 commit
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Support for UART 2 is added. UART 2 is tested for working in Profile 3
by passing kernel boot args from u-boot as setenv bootargs
'console=ttyO2,115200n8......'Signed-off-by: Hebbar, Gururaja
13 Dec, 2011
3 commits
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export api used by cpsw driver so that the cpsw driver can be built as
module.Signed-off-by: Hebbar, Gururaja
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export omap_ctrl_writel() so that it can be used by others which are
built as module.Signed-off-by: Hebbar, Gururaja
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Module build adds CONFIG_xxx_MODULE config option which different than
regular CONFIG_xxxx option.This patch corrects the same for audio by checking both options.
Signed-off-by: Hebbar, Gururaja
12 Dec, 2011
2 commits
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Signed-off-by: Patil, Rachna
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This patch removes errors related to module usage of TSC
Signed-off-by: Patil, Rachna
06 Dec, 2011
3 commits
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Patch adds useful debug message on LCDC syn and underflow error.
Signed-off-by: Manjunathappa, Prakash
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The overcurrent situation can occur in 2 scenarios
a) when usb device connected directly to musb root-port and device draw the
more current, further the VBUS_ERROR is generated and root-hub port change
status need to be notified to hub driver to handle over-current situation.
b) when usb device connected thrugh HUB, the hub status change will be
notified by hub through interrupt transfer and handled approperiately by HUB
driver.This patch fixes (a), where root hub status change was not notified to hub driver.
Signed-off-by: Ravi B
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JFFS2 requires 8 byte in OOB area for clean markers leaving 56 bytes for
ECC. However recently added BCH8 support requires 58 bytes for ECC which
leaves 6 bytes. This causes JFSS2 to fail.This patch removes JFFS2 Support. Instead UBIFS will be used
Signed-off-by: Philip, Avinash
01 Dec, 2011
12 commits
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Signed-off-by: Vaibhav Bedia
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The address spaces, irqs and dma reqs count APIs return the
number of corresponding entries in a hwmod including a additional
null value or a -1 terminator in the structure introduced recently.
More information here:- 212738a4: omap_hwmod: use a terminator record with omap_hwmod_mpu_irqs
arrays- 78183f3f: omap_hwmod: use a null structure record to terminate
omap_hwmod_addr_space arrays- bc614958: omap_hwmod: use a terminator record with omap_hwmod_dma_info
arraysThe issue with irqs and dma info was originally reported by Benoit Cousson.
The devices which have multiple hwmods and use device_build_ss are
broken with this, as their resources are populated with a extra null
value, subsequently the probe fails. So fix the API not to include
the array terminator in the count.Reported-by: Benoit Cousson
Signed-off-by: Santosh Shilimkar
Signed-off-by: sricharan
Signed-off-by: Benoit Cousson
Cc: Paul Walmsley
Signed-off-by: Vaibhav Hiremath -
This patch removes the remaining #ifdef. using #ifdef may cause trouble
while building modules but without checking _MODULE config optionSigned-off-by: Hebbar, Gururaja
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NAND read path for BCH8 is corrected to handle reading of erased pages.
Previously on nand read, ecc was taken from wrong offset in oob_poi buffer
and was giving non-0xff data and hence was giving ecc uncorrectable issue
on erased pages.Signed-off-by: Philip, Avinash
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This patch removes the check for unaligned size, on reading from NAND
flash. Previously size check was inserted in order to avoid error
correction handling of non-aligned length of page size.Signed-off-by: Philip, Avinash
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GPIO numbers were updated while moving from alpha to beta version of
EVM.
This patch corercts the GPIO numbers.
MMC1_WP --> GPIO(1, 29)
MMC1_CD --> GPIO(2, 2)Signed-off-by: Hebbar, Gururaja
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This enables support for oProfile on AM335x.
Enabling Oprofile does not impact kernel performance since
Oprofile is dormant unless a profiling session is initiated.Signed-off-by: Jeff Lance
Signed-off-by: Hebbar, Gururaja -
Remove incorrect #ifdef added from a prev commit.
while we are here, also move upwards before any input
or key related macros are used.Signed-off-by: Goutam Kumar
Signed-off-by: Hebbar, Gururaja -
This patch corrects keypwr1 pinmux to gpmc_a6.gpio1_22
Signed-off-by: Goutam Kumar
Signed-off-by: Hebbar, Gururaja -
Enable the following features in the defconfig
- CPU_IDLE support
- A few essential features like DEBUG_LL,
DYNAMIC_DEBUG and EARLYPRINTKSigned-off-by: Vaibhav Bedia
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Add board specific cpuidle hookup for AM335x EVM
Signed-off-by: Vaibhav Bedia
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Add basic cpuidle support for AM33XX family of SoC.
Right now only two idle states (WFI and WFI+SR) are
supported. The latency/residency numbers chosen will
be fine-tuned based on power measurements on actual
hardware.Signed-off-by: Vaibhav Bedia
30 Nov, 2011
17 commits
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TPS65910 VDD1 SMPS is connected to MPU.
Add dummy entries for other regulators.TODO: Replace dummy regulator entries
with proper ones as required.Signed-off-by: Afzal Mohammed
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MPU voltage domain data added. Also added
OPP table for MPU voltage domain.OPP table for CORE voltage domain has not been
added as there were issues upon reducing CORE
voltage, hence no dependency has been defined
for MPU.Signed-off-by: Afzal Mohammed
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Jitter correction for AM33XX is not present.
Handle revelant clock API's properly.Signed-off-by: Afzal Mohammed
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Signed-off-by: Vaibhav Bedia
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Initialize voltage to be as per OPP
Signed-off-by: Vaibhav Bedia
Signed-off-by: Afzal Mohammed -
Replace clk_set_rate with omap_device_scale
in target function. This provides the ability
to change voltage as well as frequency as per
OPP tablesSigned-off-by: Afzal Mohammed
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TI processors in TI81x and AM33x family work with PMICs like
TPS65910/1 which are not part of the TWL series. These processors
also do not have a voltage controller/processor module.In order to invoke the normal regulator calls from the voltage
layer the following changes are done to struct voltagedomain
- Add a flag use_regulator for the SoC voltagedomain
code to indicate its intention of using a PMIC which
is not controlled by VC/VP
- Add a regulator_init callback which the platform code
can utilise for any custom init sequence before making
use of the regulator. Platform code is also expected
to set the voltdm->scale function in the init callbackSigned-off-by: Ravikumar Kattekola
Signed-off-by: Vaibhav Bedia -
Most clock rates can vary to some extent based on the exact
M/N values used to lock a dpll.
Do a round_rate before updating the rates into the OPP table
so that the 'exact' rates appear and a subsequent clk_set_rate
works without issues.Signed-off-by: Rajendra Nayak
Signed-off-by: Nishanth Menon
[vaibhav.bedia@ti.com: Pull in for AM33xx]
Signed-off-by: Vaibhav Bedia
Signed-off-by: Afzal Mohammed -
Ensure that PM initializations are all ready before we proceed.
This allows drivers such as gfx, cpufreq which are ready earlier
than pm to not not attempt to use the scaling infrastructure before
it is ready.Signed-off-by: Nishanth Menon
[vaibhav.bedia@ti.com: Pull in for AM33xx]
Signed-off-by: Vaibhav Bedia -
Make DVFS to try the next available frequency if the higher match
is not available. This will probably be the max available for the device.If we cannot match any thing at all, fail. This modifies the behavior
of device scale to guarenteeing _atleast_ the frequency requested into
_if possible_, the frequency requested.Signed-off-by: Girish S G
[vaibhav.bedia@ti.com: Pull in for AM33xx]
Signed-off-by: Vaibhav Bedia -
Provide mechanism to know if DVFS is scaling on a specific domain.
This API will allow us to detect transition and take appropriate
measures in idle pathAcked-by: Todd Poynor
Acked-by: Santosh Shilimkar
Signed-off-by: Nishanth Menon
[vaibhav.bedia@ti.com: Pull in for AM33xx]
Signed-off-by: Vaibhav Bedia -
Ability to show the dependency table helps debug some of the quirky
issues associated with dvfs when multiple device requests are present[nm@ti.com: log beautification, few fixes]
Signed-off-by: Nishanth Menon
Signed-off-by: Todd Poynor
[vaibhav.bedia@ti.com: Pull in for AM33xx]
Signed-off-by: Vaibhav Bedia -
Let omap_init_opp_table run through all the OPP's instead of
returning on seeing the first invalid one. Skip the invalid ones
and give a fair chance to the rest to get registered,
if they are found to be valid.
For every invalid entry in the OPP table, instead of a pr_warn,
do a WARN so it gets the attention it needs.Signed-off-by: Rajendra Nayak
[vaibhav.bedia@ti.com: Pull in for AM33xx]
Signed-off-by: Vaibhav Bedia -
Allocating dvfs_info for every device instead of doing it
for every voltage domain causes devices registered using
omap_dvfs_register_device() to disappear.Signed-off-by: Rajendra Nayak
[vaibhav.bedia@ti.com: Pull in for AM33xx]
Signed-off-by: Vaibhav Bedia -
dvfs.h is required by omap cpufreq driver that
lives in drivers folder, so move it to plat/
directory. Also move voltage.h, vc.h & vp.h
similarly to have clean header file inclusionsSigned-off-by: Afzal Mohammed
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Register DVFS entries per opp entry to capture all
scalable domain devices.Signed-off-by: Nishanth Menon
[vaibhav.bedia@ti.com: Pull in for AM33xx]
Signed-off-by: Vaibhav Bedia -
With hwmods, ideally, we should have been able to do:
pdm = omap_hwmod_get_pwrdm(oh);
voltdm = pwrdm_get_voltdm(pdm);
clk = clk_get(oh->main_clk);Unfortunately hwmod database is'nt mature enough yet to handle
silicon variance within the same family, e.g. 4430 Vs 4460.
So we explicitly map the domain and clk names within the OPP
entries. This allows us to scale by having a central location for
the registration.IMPORTANT NOTE: we probably will need to fix core and iva clk
setting.Signed-off-by: Nishanth Menon
Signed-off-by: Vishwanath BS
[vaibhav.bedia@ti.com: Pull in for AM33xx]
Signed-off-by: Vaibhav Bedia
