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Commit 04f561ff8714c89733dcf1d178b64d100d5a084a

Authored by Jarod Wilson
Committed by Mauro Carvalho Chehab
1 parent e5fd0f7db3
Exists in master and in 4 other branches v3.2_AM335xPSP_04.06.00.11, v3.2_NEWT335xPSP_04.06.00.11, v3.2_SBC_SMARTMEN, v3.2_SMARCT335xPSP_04.06.00.11

[media] [staging] lirc_sir: fix unused-but-set warnings 

Signed-off-by: Jarod Wilson <jarod@redhat.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>

Showing 1 changed file with 2 additions and 9 deletions Inline Diff

drivers/staging/lirc/lirc_sir.c
Diff comments   View file @ 04f561f
1 /* 1 /*
2 * LIRC SIR driver, (C) 2000 Milan Pikula <www@fornax.sk> 2 * LIRC SIR driver, (C) 2000 Milan Pikula <www@fornax.sk>
3 * 3 *
4 * lirc_sir - Device driver for use with SIR (serial infra red) 4 * lirc_sir - Device driver for use with SIR (serial infra red)
5 * mode of IrDA on many notebooks. 5 * mode of IrDA on many notebooks.
6 * 6 *
7 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by 8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or 9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version. 10 * (at your option) any later version.
11 * 11 *
12 * This program is distributed in the hope that it will be useful, 12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details. 15 * GNU General Public License for more details.
16 * 16 *
17 * You should have received a copy of the GNU General Public License 17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software 18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 * 20 *
21 * 21 *
22 * 2000/09/16 Frank Przybylski <mail@frankprzybylski.de> : 22 * 2000/09/16 Frank Przybylski <mail@frankprzybylski.de> :
23 * added timeout and relaxed pulse detection, removed gap bug 23 * added timeout and relaxed pulse detection, removed gap bug
24 * 24 *
25 * 2000/12/15 Christoph Bartelmus <lirc@bartelmus.de> : 25 * 2000/12/15 Christoph Bartelmus <lirc@bartelmus.de> :
26 * added support for Tekram Irmate 210 (sending does not work yet, 26 * added support for Tekram Irmate 210 (sending does not work yet,
27 * kind of disappointing that nobody was able to implement that 27 * kind of disappointing that nobody was able to implement that
28 * before), 28 * before),
29 * major clean-up 29 * major clean-up
30 * 30 *
31 * 2001/02/27 Christoph Bartelmus <lirc@bartelmus.de> : 31 * 2001/02/27 Christoph Bartelmus <lirc@bartelmus.de> :
32 * added support for StrongARM SA1100 embedded microprocessor 32 * added support for StrongARM SA1100 embedded microprocessor
33 * parts cut'n'pasted from sa1100_ir.c (C) 2000 Russell King 33 * parts cut'n'pasted from sa1100_ir.c (C) 2000 Russell King
34 */ 34 */
35 35
36 #include <linux/module.h> 36 #include <linux/module.h>
37 #include <linux/sched.h> 37 #include <linux/sched.h>
38 #include <linux/errno.h> 38 #include <linux/errno.h>
39 #include <linux/signal.h> 39 #include <linux/signal.h>
40 #include <linux/fs.h> 40 #include <linux/fs.h>
41 #include <linux/interrupt.h> 41 #include <linux/interrupt.h>
42 #include <linux/ioport.h> 42 #include <linux/ioport.h>
43 #include <linux/kernel.h> 43 #include <linux/kernel.h>
44 #include <linux/serial_reg.h> 44 #include <linux/serial_reg.h>
45 #include <linux/time.h> 45 #include <linux/time.h>
46 #include <linux/string.h> 46 #include <linux/string.h>
47 #include <linux/types.h> 47 #include <linux/types.h>
48 #include <linux/wait.h> 48 #include <linux/wait.h>
49 #include <linux/mm.h> 49 #include <linux/mm.h>
50 #include <linux/delay.h> 50 #include <linux/delay.h>
51 #include <linux/poll.h> 51 #include <linux/poll.h>
52 #include <asm/system.h> 52 #include <asm/system.h>
53 #include <linux/io.h> 53 #include <linux/io.h>
54 #include <asm/irq.h> 54 #include <asm/irq.h>
55 #include <linux/fcntl.h> 55 #include <linux/fcntl.h>
56 #ifdef LIRC_ON_SA1100 56 #ifdef LIRC_ON_SA1100
57 #include <asm/hardware.h> 57 #include <asm/hardware.h>
58 #ifdef CONFIG_SA1100_COLLIE 58 #ifdef CONFIG_SA1100_COLLIE
59 #include <asm/arch/tc35143.h> 59 #include <asm/arch/tc35143.h>
60 #include <asm/ucb1200.h> 60 #include <asm/ucb1200.h>
61 #endif 61 #endif
62 #endif 62 #endif
63 63
64 #include <linux/timer.h> 64 #include <linux/timer.h>
65 65
66 #include <media/lirc.h> 66 #include <media/lirc.h>
67 #include <media/lirc_dev.h> 67 #include <media/lirc_dev.h>
68 68
69 /* SECTION: Definitions */ 69 /* SECTION: Definitions */
70 70
71 /*** Tekram dongle ***/ 71 /*** Tekram dongle ***/
72 #ifdef LIRC_SIR_TEKRAM 72 #ifdef LIRC_SIR_TEKRAM
73 /* stolen from kernel source */ 73 /* stolen from kernel source */
74 /* definitions for Tekram dongle */ 74 /* definitions for Tekram dongle */
75 #define TEKRAM_115200 0x00 75 #define TEKRAM_115200 0x00
76 #define TEKRAM_57600 0x01 76 #define TEKRAM_57600 0x01
77 #define TEKRAM_38400 0x02 77 #define TEKRAM_38400 0x02
78 #define TEKRAM_19200 0x03 78 #define TEKRAM_19200 0x03
79 #define TEKRAM_9600 0x04 79 #define TEKRAM_9600 0x04
80 #define TEKRAM_2400 0x08 80 #define TEKRAM_2400 0x08
81 81
82 #define TEKRAM_PW 0x10 /* Pulse select bit */ 82 #define TEKRAM_PW 0x10 /* Pulse select bit */
83 83
84 /* 10bit * 1s/115200bit in milliseconds = 87ms*/ 84 /* 10bit * 1s/115200bit in milliseconds = 87ms*/
85 #define TIME_CONST (10000000ul/115200ul) 85 #define TIME_CONST (10000000ul/115200ul)
86 86
87 #endif 87 #endif
88 88
89 #ifdef LIRC_SIR_ACTISYS_ACT200L 89 #ifdef LIRC_SIR_ACTISYS_ACT200L
90 static void init_act200(void); 90 static void init_act200(void);
91 #elif defined(LIRC_SIR_ACTISYS_ACT220L) 91 #elif defined(LIRC_SIR_ACTISYS_ACT220L)
92 static void init_act220(void); 92 static void init_act220(void);
93 #endif 93 #endif
94 94
95 /*** SA1100 ***/ 95 /*** SA1100 ***/
96 #ifdef LIRC_ON_SA1100 96 #ifdef LIRC_ON_SA1100
97 struct sa1100_ser2_registers { 97 struct sa1100_ser2_registers {
98 /* HSSP control register */ 98 /* HSSP control register */
99 unsigned char hscr0; 99 unsigned char hscr0;
100 /* UART registers */ 100 /* UART registers */
101 unsigned char utcr0; 101 unsigned char utcr0;
102 unsigned char utcr1; 102 unsigned char utcr1;
103 unsigned char utcr2; 103 unsigned char utcr2;
104 unsigned char utcr3; 104 unsigned char utcr3;
105 unsigned char utcr4; 105 unsigned char utcr4;
106 unsigned char utdr; 106 unsigned char utdr;
107 unsigned char utsr0; 107 unsigned char utsr0;
108 unsigned char utsr1; 108 unsigned char utsr1;
109 } sr; 109 } sr;
110 110
111 static int irq = IRQ_Ser2ICP; 111 static int irq = IRQ_Ser2ICP;
112 112
113 #define LIRC_ON_SA1100_TRANSMITTER_LATENCY 0 113 #define LIRC_ON_SA1100_TRANSMITTER_LATENCY 0
114 114
115 /* pulse/space ratio of 50/50 */ 115 /* pulse/space ratio of 50/50 */
116 static unsigned long pulse_width = (13-LIRC_ON_SA1100_TRANSMITTER_LATENCY); 116 static unsigned long pulse_width = (13-LIRC_ON_SA1100_TRANSMITTER_LATENCY);
117 /* 1000000/freq-pulse_width */ 117 /* 1000000/freq-pulse_width */
118 static unsigned long space_width = (13-LIRC_ON_SA1100_TRANSMITTER_LATENCY); 118 static unsigned long space_width = (13-LIRC_ON_SA1100_TRANSMITTER_LATENCY);
119 static unsigned int freq = 38000; /* modulation frequency */ 119 static unsigned int freq = 38000; /* modulation frequency */
120 static unsigned int duty_cycle = 50; /* duty cycle of 50% */ 120 static unsigned int duty_cycle = 50; /* duty cycle of 50% */
121 121
122 #endif 122 #endif
123 123
124 #define RBUF_LEN 1024 124 #define RBUF_LEN 1024
125 #define WBUF_LEN 1024 125 #define WBUF_LEN 1024
126 126
127 #define LIRC_DRIVER_NAME "lirc_sir" 127 #define LIRC_DRIVER_NAME "lirc_sir"
128 128
129 #define PULSE '[' 129 #define PULSE '['
130 130
131 #ifndef LIRC_SIR_TEKRAM 131 #ifndef LIRC_SIR_TEKRAM
132 /* 9bit * 1s/115200bit in milli seconds = 78.125ms*/ 132 /* 9bit * 1s/115200bit in milli seconds = 78.125ms*/
133 #define TIME_CONST (9000000ul/115200ul) 133 #define TIME_CONST (9000000ul/115200ul)
134 #endif 134 #endif
135 135
136 136
137 /* timeout for sequences in jiffies (=5/100s), must be longer than TIME_CONST */ 137 /* timeout for sequences in jiffies (=5/100s), must be longer than TIME_CONST */
138 #define SIR_TIMEOUT (HZ*5/100) 138 #define SIR_TIMEOUT (HZ*5/100)
139 139
140 #ifndef LIRC_ON_SA1100 140 #ifndef LIRC_ON_SA1100
141 #ifndef LIRC_IRQ 141 #ifndef LIRC_IRQ
142 #define LIRC_IRQ 4 142 #define LIRC_IRQ 4
143 #endif 143 #endif
144 #ifndef LIRC_PORT 144 #ifndef LIRC_PORT
145 /* for external dongles, default to com1 */ 145 /* for external dongles, default to com1 */
146 #if defined(LIRC_SIR_ACTISYS_ACT200L) || \ 146 #if defined(LIRC_SIR_ACTISYS_ACT200L) || \
147 defined(LIRC_SIR_ACTISYS_ACT220L) || \ 147 defined(LIRC_SIR_ACTISYS_ACT220L) || \
148 defined(LIRC_SIR_TEKRAM) 148 defined(LIRC_SIR_TEKRAM)
149 #define LIRC_PORT 0x3f8 149 #define LIRC_PORT 0x3f8
150 #else 150 #else
151 /* onboard sir ports are typically com3 */ 151 /* onboard sir ports are typically com3 */
152 #define LIRC_PORT 0x3e8 152 #define LIRC_PORT 0x3e8
153 #endif 153 #endif
154 #endif 154 #endif
155 155
156 static int io = LIRC_PORT; 156 static int io = LIRC_PORT;
157 static int irq = LIRC_IRQ; 157 static int irq = LIRC_IRQ;
158 static int threshold = 3; 158 static int threshold = 3;
159 #endif 159 #endif
160 160
161 static DEFINE_SPINLOCK(timer_lock); 161 static DEFINE_SPINLOCK(timer_lock);
162 static struct timer_list timerlist; 162 static struct timer_list timerlist;
163 /* time of last signal change detected */ 163 /* time of last signal change detected */
164 static struct timeval last_tv = {0, 0}; 164 static struct timeval last_tv = {0, 0};
165 /* time of last UART data ready interrupt */ 165 /* time of last UART data ready interrupt */
166 static struct timeval last_intr_tv = {0, 0}; 166 static struct timeval last_intr_tv = {0, 0};
167 static int last_value; 167 static int last_value;
168 168
169 static DECLARE_WAIT_QUEUE_HEAD(lirc_read_queue); 169 static DECLARE_WAIT_QUEUE_HEAD(lirc_read_queue);
170 170
171 static DEFINE_SPINLOCK(hardware_lock); 171 static DEFINE_SPINLOCK(hardware_lock);
172 172
173 static int rx_buf[RBUF_LEN]; 173 static int rx_buf[RBUF_LEN];
174 static unsigned int rx_tail, rx_head; 174 static unsigned int rx_tail, rx_head;
175 175
176 static int debug; 176 static int debug;
177 #define dprintk(fmt, args...) \ 177 #define dprintk(fmt, args...) \
178 do { \ 178 do { \
179 if (debug) \ 179 if (debug) \
180 printk(KERN_DEBUG LIRC_DRIVER_NAME ": " \ 180 printk(KERN_DEBUG LIRC_DRIVER_NAME ": " \
181 fmt, ## args); \ 181 fmt, ## args); \
182 } while (0) 182 } while (0)
183 183
184 /* SECTION: Prototypes */ 184 /* SECTION: Prototypes */
185 185
186 /* Communication with user-space */ 186 /* Communication with user-space */
187 static unsigned int lirc_poll(struct file *file, poll_table *wait); 187 static unsigned int lirc_poll(struct file *file, poll_table *wait);
188 static ssize_t lirc_read(struct file *file, char *buf, size_t count, 188 static ssize_t lirc_read(struct file *file, char *buf, size_t count,
189 loff_t *ppos); 189 loff_t *ppos);
190 static ssize_t lirc_write(struct file *file, const char *buf, size_t n, 190 static ssize_t lirc_write(struct file *file, const char *buf, size_t n,
191 loff_t *pos); 191 loff_t *pos);
192 static long lirc_ioctl(struct file *filep, unsigned int cmd, unsigned long arg); 192 static long lirc_ioctl(struct file *filep, unsigned int cmd, unsigned long arg);
193 static void add_read_queue(int flag, unsigned long val); 193 static void add_read_queue(int flag, unsigned long val);
194 static int init_chrdev(void); 194 static int init_chrdev(void);
195 static void drop_chrdev(void); 195 static void drop_chrdev(void);
196 /* Hardware */ 196 /* Hardware */
197 static irqreturn_t sir_interrupt(int irq, void *dev_id); 197 static irqreturn_t sir_interrupt(int irq, void *dev_id);
198 static void send_space(unsigned long len); 198 static void send_space(unsigned long len);
199 static void send_pulse(unsigned long len); 199 static void send_pulse(unsigned long len);
200 static int init_hardware(void); 200 static int init_hardware(void);
201 static void drop_hardware(void); 201 static void drop_hardware(void);
202 /* Initialisation */ 202 /* Initialisation */
203 static int init_port(void); 203 static int init_port(void);
204 static void drop_port(void); 204 static void drop_port(void);
205 205
206 #ifdef LIRC_ON_SA1100 206 #ifdef LIRC_ON_SA1100
207 static void on(void) 207 static void on(void)
208 { 208 {
209 PPSR |= PPC_TXD2; 209 PPSR |= PPC_TXD2;
210 } 210 }
211 211
212 static void off(void) 212 static void off(void)
213 { 213 {
214 PPSR &= ~PPC_TXD2; 214 PPSR &= ~PPC_TXD2;
215 } 215 }
216 #else 216 #else
217 static inline unsigned int sinp(int offset) 217 static inline unsigned int sinp(int offset)
218 { 218 {
219 return inb(io + offset); 219 return inb(io + offset);
220 } 220 }
221 221
222 static inline void soutp(int offset, int value) 222 static inline void soutp(int offset, int value)
223 { 223 {
224 outb(value, io + offset); 224 outb(value, io + offset);
225 } 225 }
226 #endif 226 #endif
227 227
228 #ifndef MAX_UDELAY_MS 228 #ifndef MAX_UDELAY_MS
229 #define MAX_UDELAY_US 5000 229 #define MAX_UDELAY_US 5000
230 #else 230 #else
231 #define MAX_UDELAY_US (MAX_UDELAY_MS*1000) 231 #define MAX_UDELAY_US (MAX_UDELAY_MS*1000)
232 #endif 232 #endif
233 233
234 static void safe_udelay(unsigned long usecs) 234 static void safe_udelay(unsigned long usecs)
235 { 235 {
236 while (usecs > MAX_UDELAY_US) { 236 while (usecs > MAX_UDELAY_US) {
237 udelay(MAX_UDELAY_US); 237 udelay(MAX_UDELAY_US);
238 usecs -= MAX_UDELAY_US; 238 usecs -= MAX_UDELAY_US;
239 } 239 }
240 udelay(usecs); 240 udelay(usecs);
241 } 241 }
242 242
243 /* SECTION: Communication with user-space */ 243 /* SECTION: Communication with user-space */
244 244
245 static unsigned int lirc_poll(struct file *file, poll_table *wait) 245 static unsigned int lirc_poll(struct file *file, poll_table *wait)
246 { 246 {
247 poll_wait(file, &lirc_read_queue, wait); 247 poll_wait(file, &lirc_read_queue, wait);
248 if (rx_head != rx_tail) 248 if (rx_head != rx_tail)
249 return POLLIN | POLLRDNORM; 249 return POLLIN | POLLRDNORM;
250 return 0; 250 return 0;
251 } 251 }
252 252
253 static ssize_t lirc_read(struct file *file, char *buf, size_t count, 253 static ssize_t lirc_read(struct file *file, char *buf, size_t count,
254 loff_t *ppos) 254 loff_t *ppos)
255 { 255 {
256 int n = 0; 256 int n = 0;
257 int retval = 0; 257 int retval = 0;
258 DECLARE_WAITQUEUE(wait, current); 258 DECLARE_WAITQUEUE(wait, current);
259 259
260 if (count % sizeof(int)) 260 if (count % sizeof(int))
261 return -EINVAL; 261 return -EINVAL;
262 262
263 add_wait_queue(&lirc_read_queue, &wait); 263 add_wait_queue(&lirc_read_queue, &wait);
264 set_current_state(TASK_INTERRUPTIBLE); 264 set_current_state(TASK_INTERRUPTIBLE);
265 while (n < count) { 265 while (n < count) {
266 if (rx_head != rx_tail) { 266 if (rx_head != rx_tail) {
267 if (copy_to_user((void *) buf + n, 267 if (copy_to_user((void *) buf + n,
268 (void *) (rx_buf + rx_head), 268 (void *) (rx_buf + rx_head),
269 sizeof(int))) { 269 sizeof(int))) {
270 retval = -EFAULT; 270 retval = -EFAULT;
271 break; 271 break;
272 } 272 }
273 rx_head = (rx_head + 1) & (RBUF_LEN - 1); 273 rx_head = (rx_head + 1) & (RBUF_LEN - 1);
274 n += sizeof(int); 274 n += sizeof(int);
275 } else { 275 } else {
276 if (file->f_flags & O_NONBLOCK) { 276 if (file->f_flags & O_NONBLOCK) {
277 retval = -EAGAIN; 277 retval = -EAGAIN;
278 break; 278 break;
279 } 279 }
280 if (signal_pending(current)) { 280 if (signal_pending(current)) {
281 retval = -ERESTARTSYS; 281 retval = -ERESTARTSYS;
282 break; 282 break;
283 } 283 }
284 schedule(); 284 schedule();
285 set_current_state(TASK_INTERRUPTIBLE); 285 set_current_state(TASK_INTERRUPTIBLE);
286 } 286 }
287 } 287 }
288 remove_wait_queue(&lirc_read_queue, &wait); 288 remove_wait_queue(&lirc_read_queue, &wait);
289 set_current_state(TASK_RUNNING); 289 set_current_state(TASK_RUNNING);
290 return n ? n : retval; 290 return n ? n : retval;
291 } 291 }
292 static ssize_t lirc_write(struct file *file, const char *buf, size_t n, 292 static ssize_t lirc_write(struct file *file, const char *buf, size_t n,
293 loff_t *pos) 293 loff_t *pos)
294 { 294 {
295 unsigned long flags; 295 unsigned long flags;
296 int i, count; 296 int i, count;
297 int *tx_buf; 297 int *tx_buf;
298 298
299 count = n / sizeof(int); 299 count = n / sizeof(int);
300 if (n % sizeof(int) || count % 2 == 0) 300 if (n % sizeof(int) || count % 2 == 0)
301 return -EINVAL; 301 return -EINVAL;
302 tx_buf = memdup_user(buf, n); 302 tx_buf = memdup_user(buf, n);
303 if (IS_ERR(tx_buf)) 303 if (IS_ERR(tx_buf))
304 return PTR_ERR(tx_buf); 304 return PTR_ERR(tx_buf);
305 i = 0; 305 i = 0;
306 #ifdef LIRC_ON_SA1100 306 #ifdef LIRC_ON_SA1100
307 /* disable receiver */ 307 /* disable receiver */
308 Ser2UTCR3 = 0; 308 Ser2UTCR3 = 0;
309 #endif 309 #endif
310 local_irq_save(flags); 310 local_irq_save(flags);
311 while (1) { 311 while (1) {
312 if (i >= count) 312 if (i >= count)
313 break; 313 break;
314 if (tx_buf[i]) 314 if (tx_buf[i])
315 send_pulse(tx_buf[i]); 315 send_pulse(tx_buf[i]);
316 i++; 316 i++;
317 if (i >= count) 317 if (i >= count)
318 break; 318 break;
319 if (tx_buf[i]) 319 if (tx_buf[i])
320 send_space(tx_buf[i]); 320 send_space(tx_buf[i]);
321 i++; 321 i++;
322 } 322 }
323 local_irq_restore(flags); 323 local_irq_restore(flags);
324 #ifdef LIRC_ON_SA1100 324 #ifdef LIRC_ON_SA1100
325 off(); 325 off();
326 udelay(1000); /* wait 1ms for IR diode to recover */ 326 udelay(1000); /* wait 1ms for IR diode to recover */
327 Ser2UTCR3 = 0; 327 Ser2UTCR3 = 0;
328 /* clear status register to prevent unwanted interrupts */ 328 /* clear status register to prevent unwanted interrupts */
329 Ser2UTSR0 &= (UTSR0_RID | UTSR0_RBB | UTSR0_REB); 329 Ser2UTSR0 &= (UTSR0_RID | UTSR0_RBB | UTSR0_REB);
330 /* enable receiver */ 330 /* enable receiver */
331 Ser2UTCR3 = UTCR3_RXE|UTCR3_RIE; 331 Ser2UTCR3 = UTCR3_RXE|UTCR3_RIE;
332 #endif 332 #endif
333 kfree(tx_buf); 333 kfree(tx_buf);
334 return count; 334 return count;
335 } 335 }
336 336
337 static long lirc_ioctl(struct file *filep, unsigned int cmd, unsigned long arg) 337 static long lirc_ioctl(struct file *filep, unsigned int cmd, unsigned long arg)
338 { 338 {
339 int retval = 0; 339 int retval = 0;
340 __u32 value = 0; 340 __u32 value = 0;
341 #ifdef LIRC_ON_SA1100 341 #ifdef LIRC_ON_SA1100
342 342
343 if (cmd == LIRC_GET_FEATURES) 343 if (cmd == LIRC_GET_FEATURES)
344 value = LIRC_CAN_SEND_PULSE | 344 value = LIRC_CAN_SEND_PULSE |
345 LIRC_CAN_SET_SEND_DUTY_CYCLE | 345 LIRC_CAN_SET_SEND_DUTY_CYCLE |
346 LIRC_CAN_SET_SEND_CARRIER | 346 LIRC_CAN_SET_SEND_CARRIER |
347 LIRC_CAN_REC_MODE2; 347 LIRC_CAN_REC_MODE2;
348 else if (cmd == LIRC_GET_SEND_MODE) 348 else if (cmd == LIRC_GET_SEND_MODE)
349 value = LIRC_MODE_PULSE; 349 value = LIRC_MODE_PULSE;
350 else if (cmd == LIRC_GET_REC_MODE) 350 else if (cmd == LIRC_GET_REC_MODE)
351 value = LIRC_MODE_MODE2; 351 value = LIRC_MODE_MODE2;
352 #else 352 #else
353 if (cmd == LIRC_GET_FEATURES) 353 if (cmd == LIRC_GET_FEATURES)
354 value = LIRC_CAN_SEND_PULSE | LIRC_CAN_REC_MODE2; 354 value = LIRC_CAN_SEND_PULSE | LIRC_CAN_REC_MODE2;
355 else if (cmd == LIRC_GET_SEND_MODE) 355 else if (cmd == LIRC_GET_SEND_MODE)
356 value = LIRC_MODE_PULSE; 356 value = LIRC_MODE_PULSE;
357 else if (cmd == LIRC_GET_REC_MODE) 357 else if (cmd == LIRC_GET_REC_MODE)
358 value = LIRC_MODE_MODE2; 358 value = LIRC_MODE_MODE2;
359 #endif 359 #endif
360 360
361 switch (cmd) { 361 switch (cmd) {
362 case LIRC_GET_FEATURES: 362 case LIRC_GET_FEATURES:
363 case LIRC_GET_SEND_MODE: 363 case LIRC_GET_SEND_MODE:
364 case LIRC_GET_REC_MODE: 364 case LIRC_GET_REC_MODE:
365 retval = put_user(value, (__u32 *) arg); 365 retval = put_user(value, (__u32 *) arg);
366 break; 366 break;
367 367
368 case LIRC_SET_SEND_MODE: 368 case LIRC_SET_SEND_MODE:
369 case LIRC_SET_REC_MODE: 369 case LIRC_SET_REC_MODE:
370 retval = get_user(value, (__u32 *) arg); 370 retval = get_user(value, (__u32 *) arg);
371 break; 371 break;
372 #ifdef LIRC_ON_SA1100 372 #ifdef LIRC_ON_SA1100
373 case LIRC_SET_SEND_DUTY_CYCLE: 373 case LIRC_SET_SEND_DUTY_CYCLE:
374 retval = get_user(value, (__u32 *) arg); 374 retval = get_user(value, (__u32 *) arg);
375 if (retval) 375 if (retval)
376 return retval; 376 return retval;
377 if (value <= 0 || value > 100) 377 if (value <= 0 || value > 100)
378 return -EINVAL; 378 return -EINVAL;
379 /* (value/100)*(1000000/freq) */ 379 /* (value/100)*(1000000/freq) */
380 duty_cycle = value; 380 duty_cycle = value;
381 pulse_width = (unsigned long) duty_cycle*10000/freq; 381 pulse_width = (unsigned long) duty_cycle*10000/freq;
382 space_width = (unsigned long) 1000000L/freq-pulse_width; 382 space_width = (unsigned long) 1000000L/freq-pulse_width;
383 if (pulse_width >= LIRC_ON_SA1100_TRANSMITTER_LATENCY) 383 if (pulse_width >= LIRC_ON_SA1100_TRANSMITTER_LATENCY)
384 pulse_width -= LIRC_ON_SA1100_TRANSMITTER_LATENCY; 384 pulse_width -= LIRC_ON_SA1100_TRANSMITTER_LATENCY;
385 if (space_width >= LIRC_ON_SA1100_TRANSMITTER_LATENCY) 385 if (space_width >= LIRC_ON_SA1100_TRANSMITTER_LATENCY)
386 space_width -= LIRC_ON_SA1100_TRANSMITTER_LATENCY; 386 space_width -= LIRC_ON_SA1100_TRANSMITTER_LATENCY;
387 break; 387 break;
388 case LIRC_SET_SEND_CARRIER: 388 case LIRC_SET_SEND_CARRIER:
389 retval = get_user(value, (__u32 *) arg); 389 retval = get_user(value, (__u32 *) arg);
390 if (retval) 390 if (retval)
391 return retval; 391 return retval;
392 if (value > 500000 || value < 20000) 392 if (value > 500000 || value < 20000)
393 return -EINVAL; 393 return -EINVAL;
394 freq = value; 394 freq = value;
395 pulse_width = (unsigned long) duty_cycle*10000/freq; 395 pulse_width = (unsigned long) duty_cycle*10000/freq;
396 space_width = (unsigned long) 1000000L/freq-pulse_width; 396 space_width = (unsigned long) 1000000L/freq-pulse_width;
397 if (pulse_width >= LIRC_ON_SA1100_TRANSMITTER_LATENCY) 397 if (pulse_width >= LIRC_ON_SA1100_TRANSMITTER_LATENCY)
398 pulse_width -= LIRC_ON_SA1100_TRANSMITTER_LATENCY; 398 pulse_width -= LIRC_ON_SA1100_TRANSMITTER_LATENCY;
399 if (space_width >= LIRC_ON_SA1100_TRANSMITTER_LATENCY) 399 if (space_width >= LIRC_ON_SA1100_TRANSMITTER_LATENCY)
400 space_width -= LIRC_ON_SA1100_TRANSMITTER_LATENCY; 400 space_width -= LIRC_ON_SA1100_TRANSMITTER_LATENCY;
401 break; 401 break;
402 #endif 402 #endif
403 default: 403 default:
404 retval = -ENOIOCTLCMD; 404 retval = -ENOIOCTLCMD;
405 405
406 } 406 }
407 407
408 if (retval) 408 if (retval)
409 return retval; 409 return retval;
410 if (cmd == LIRC_SET_REC_MODE) { 410 if (cmd == LIRC_SET_REC_MODE) {
411 if (value != LIRC_MODE_MODE2) 411 if (value != LIRC_MODE_MODE2)
412 retval = -ENOSYS; 412 retval = -ENOSYS;
413 } else if (cmd == LIRC_SET_SEND_MODE) { 413 } else if (cmd == LIRC_SET_SEND_MODE) {
414 if (value != LIRC_MODE_PULSE) 414 if (value != LIRC_MODE_PULSE)
415 retval = -ENOSYS; 415 retval = -ENOSYS;
416 } 416 }
417 417
418 return retval; 418 return retval;
419 } 419 }
420 420
421 static void add_read_queue(int flag, unsigned long val) 421 static void add_read_queue(int flag, unsigned long val)
422 { 422 {
423 unsigned int new_rx_tail; 423 unsigned int new_rx_tail;
424 int newval; 424 int newval;
425 425
426 dprintk("add flag %d with val %lu\n", flag, val); 426 dprintk("add flag %d with val %lu\n", flag, val);
427 427
428 newval = val & PULSE_MASK; 428 newval = val & PULSE_MASK;
429 429
430 /* 430 /*
431 * statistically, pulses are ~TIME_CONST/2 too long. we could 431 * statistically, pulses are ~TIME_CONST/2 too long. we could
432 * maybe make this more exact, but this is good enough 432 * maybe make this more exact, but this is good enough
433 */ 433 */
434 if (flag) { 434 if (flag) {
435 /* pulse */ 435 /* pulse */
436 if (newval > TIME_CONST/2) 436 if (newval > TIME_CONST/2)
437 newval -= TIME_CONST/2; 437 newval -= TIME_CONST/2;
438 else /* should not ever happen */ 438 else /* should not ever happen */
439 newval = 1; 439 newval = 1;
440 newval |= PULSE_BIT; 440 newval |= PULSE_BIT;
441 } else { 441 } else {
442 newval += TIME_CONST/2; 442 newval += TIME_CONST/2;
443 } 443 }
444 new_rx_tail = (rx_tail + 1) & (RBUF_LEN - 1); 444 new_rx_tail = (rx_tail + 1) & (RBUF_LEN - 1);
445 if (new_rx_tail == rx_head) { 445 if (new_rx_tail == rx_head) {
446 dprintk("Buffer overrun.\n"); 446 dprintk("Buffer overrun.\n");
447 return; 447 return;
448 } 448 }
449 rx_buf[rx_tail] = newval; 449 rx_buf[rx_tail] = newval;
450 rx_tail = new_rx_tail; 450 rx_tail = new_rx_tail;
451 wake_up_interruptible(&lirc_read_queue); 451 wake_up_interruptible(&lirc_read_queue);
452 } 452 }
453 453
454 static const struct file_operations lirc_fops = { 454 static const struct file_operations lirc_fops = {
455 .owner = THIS_MODULE, 455 .owner = THIS_MODULE,
456 .read = lirc_read, 456 .read = lirc_read,
457 .write = lirc_write, 457 .write = lirc_write,
458 .poll = lirc_poll, 458 .poll = lirc_poll,
459 .unlocked_ioctl = lirc_ioctl, 459 .unlocked_ioctl = lirc_ioctl,
460 #ifdef CONFIG_COMPAT 460 #ifdef CONFIG_COMPAT
461 .compat_ioctl = lirc_ioctl, 461 .compat_ioctl = lirc_ioctl,
462 #endif 462 #endif
463 .open = lirc_dev_fop_open, 463 .open = lirc_dev_fop_open,
464 .release = lirc_dev_fop_close, 464 .release = lirc_dev_fop_close,
465 .llseek = no_llseek, 465 .llseek = no_llseek,
466 }; 466 };
467 467
468 static int set_use_inc(void *data) 468 static int set_use_inc(void *data)
469 { 469 {
470 return 0; 470 return 0;
471 } 471 }
472 472
473 static void set_use_dec(void *data) 473 static void set_use_dec(void *data)
474 { 474 {
475 } 475 }
476 476
477 static struct lirc_driver driver = { 477 static struct lirc_driver driver = {
478 .name = LIRC_DRIVER_NAME, 478 .name = LIRC_DRIVER_NAME,
479 .minor = -1, 479 .minor = -1,
480 .code_length = 1, 480 .code_length = 1,
481 .sample_rate = 0, 481 .sample_rate = 0,
482 .data = NULL, 482 .data = NULL,
483 .add_to_buf = NULL, 483 .add_to_buf = NULL,
484 .set_use_inc = set_use_inc, 484 .set_use_inc = set_use_inc,
485 .set_use_dec = set_use_dec, 485 .set_use_dec = set_use_dec,
486 .fops = &lirc_fops, 486 .fops = &lirc_fops,
487 .dev = NULL, 487 .dev = NULL,
488 .owner = THIS_MODULE, 488 .owner = THIS_MODULE,
489 }; 489 };
490 490
491 491
492 static int init_chrdev(void) 492 static int init_chrdev(void)
493 { 493 {
494 driver.minor = lirc_register_driver(&driver); 494 driver.minor = lirc_register_driver(&driver);
495 if (driver.minor < 0) { 495 if (driver.minor < 0) {
496 printk(KERN_ERR LIRC_DRIVER_NAME ": init_chrdev() failed.\n"); 496 printk(KERN_ERR LIRC_DRIVER_NAME ": init_chrdev() failed.\n");
497 return -EIO; 497 return -EIO;
498 } 498 }
499 return 0; 499 return 0;
500 } 500 }
501 501
502 static void drop_chrdev(void) 502 static void drop_chrdev(void)
503 { 503 {
504 lirc_unregister_driver(driver.minor); 504 lirc_unregister_driver(driver.minor);
505 } 505 }
506 506
507 /* SECTION: Hardware */ 507 /* SECTION: Hardware */
508 static long delta(struct timeval *tv1, struct timeval *tv2) 508 static long delta(struct timeval *tv1, struct timeval *tv2)
509 { 509 {
510 unsigned long deltv; 510 unsigned long deltv;
511 511
512 deltv = tv2->tv_sec - tv1->tv_sec; 512 deltv = tv2->tv_sec - tv1->tv_sec;
513 if (deltv > 15) 513 if (deltv > 15)
514 deltv = 0xFFFFFF; 514 deltv = 0xFFFFFF;
515 else 515 else
516 deltv = deltv*1000000 + 516 deltv = deltv*1000000 +
517 tv2->tv_usec - 517 tv2->tv_usec -
518 tv1->tv_usec; 518 tv1->tv_usec;
519 return deltv; 519 return deltv;
520 } 520 }
521 521
522 static void sir_timeout(unsigned long data) 522 static void sir_timeout(unsigned long data)
523 { 523 {
524 /* 524 /*
525 * if last received signal was a pulse, but receiving stopped 525 * if last received signal was a pulse, but receiving stopped
526 * within the 9 bit frame, we need to finish this pulse and 526 * within the 9 bit frame, we need to finish this pulse and
527 * simulate a signal change to from pulse to space. Otherwise 527 * simulate a signal change to from pulse to space. Otherwise
528 * upper layers will receive two sequences next time. 528 * upper layers will receive two sequences next time.
529 */ 529 */
530 530
531 unsigned long flags; 531 unsigned long flags;
532 unsigned long pulse_end; 532 unsigned long pulse_end;
533 533
534 /* avoid interference with interrupt */ 534 /* avoid interference with interrupt */
535 spin_lock_irqsave(&timer_lock, flags); 535 spin_lock_irqsave(&timer_lock, flags);
536 if (last_value) { 536 if (last_value) {
537 #ifndef LIRC_ON_SA1100 537 #ifndef LIRC_ON_SA1100
538 /* clear unread bits in UART and restart */ 538 /* clear unread bits in UART and restart */
539 outb(UART_FCR_CLEAR_RCVR, io + UART_FCR); 539 outb(UART_FCR_CLEAR_RCVR, io + UART_FCR);
540 #endif 540 #endif
541 /* determine 'virtual' pulse end: */ 541 /* determine 'virtual' pulse end: */
542 pulse_end = delta(&last_tv, &last_intr_tv); 542 pulse_end = delta(&last_tv, &last_intr_tv);
543 dprintk("timeout add %d for %lu usec\n", last_value, pulse_end); 543 dprintk("timeout add %d for %lu usec\n", last_value, pulse_end);
544 add_read_queue(last_value, pulse_end); 544 add_read_queue(last_value, pulse_end);
545 last_value = 0; 545 last_value = 0;
546 last_tv = last_intr_tv; 546 last_tv = last_intr_tv;
547 } 547 }
548 spin_unlock_irqrestore(&timer_lock, flags); 548 spin_unlock_irqrestore(&timer_lock, flags);
549 } 549 }
550 550
551 static irqreturn_t sir_interrupt(int irq, void *dev_id) 551 static irqreturn_t sir_interrupt(int irq, void *dev_id)
552 { 552 {
553 unsigned char data; 553 unsigned char data;
554 struct timeval curr_tv; 554 struct timeval curr_tv;
555 static unsigned long deltv; 555 static unsigned long deltv;
556 #ifdef LIRC_ON_SA1100 556 #ifdef LIRC_ON_SA1100
557 int status; 557 int status;
558 static int n; 558 static int n;
559 559
560 status = Ser2UTSR0; 560 status = Ser2UTSR0;
561 /* 561 /*
562 * Deal with any receive errors first. The bytes in error may be 562 * Deal with any receive errors first. The bytes in error may be
563 * the only bytes in the receive FIFO, so we do this first. 563 * the only bytes in the receive FIFO, so we do this first.
564 */ 564 */
565 while (status & UTSR0_EIF) { 565 while (status & UTSR0_EIF) {
566 int bstat; 566 int bstat;
567 567
568 if (debug) { 568 if (debug) {
569 dprintk("EIF\n"); 569 dprintk("EIF\n");
570 bstat = Ser2UTSR1; 570 bstat = Ser2UTSR1;
571 571
572 if (bstat & UTSR1_FRE) 572 if (bstat & UTSR1_FRE)
573 dprintk("frame error\n"); 573 dprintk("frame error\n");
574 if (bstat & UTSR1_ROR) 574 if (bstat & UTSR1_ROR)
575 dprintk("receive fifo overrun\n"); 575 dprintk("receive fifo overrun\n");
576 if (bstat & UTSR1_PRE) 576 if (bstat & UTSR1_PRE)
577 dprintk("parity error\n"); 577 dprintk("parity error\n");
578 } 578 }
579 579
580 bstat = Ser2UTDR; 580 bstat = Ser2UTDR;
581 n++; 581 n++;
582 status = Ser2UTSR0; 582 status = Ser2UTSR0;
583 } 583 }
584 584
585 if (status & (UTSR0_RFS | UTSR0_RID)) { 585 if (status & (UTSR0_RFS | UTSR0_RID)) {
586 do_gettimeofday(&curr_tv); 586 do_gettimeofday(&curr_tv);
587 deltv = delta(&last_tv, &curr_tv); 587 deltv = delta(&last_tv, &curr_tv);
588 do { 588 do {
589 data = Ser2UTDR; 589 data = Ser2UTDR;
590 dprintk("%d data: %u\n", n, (unsigned int) data); 590 dprintk("%d data: %u\n", n, (unsigned int) data);
591 n++; 591 n++;
592 } while (status & UTSR0_RID && /* do not empty fifo in order to 592 } while (status & UTSR0_RID && /* do not empty fifo in order to
593 * get UTSR0_RID in any case */ 593 * get UTSR0_RID in any case */
594 Ser2UTSR1 & UTSR1_RNE); /* data ready */ 594 Ser2UTSR1 & UTSR1_RNE); /* data ready */
595 595
596 if (status&UTSR0_RID) { 596 if (status&UTSR0_RID) {
597 add_read_queue(0 , deltv - n * TIME_CONST); /*space*/ 597 add_read_queue(0 , deltv - n * TIME_CONST); /*space*/
598 add_read_queue(1, n * TIME_CONST); /*pulse*/ 598 add_read_queue(1, n * TIME_CONST); /*pulse*/
599 n = 0; 599 n = 0;
600 last_tv = curr_tv; 600 last_tv = curr_tv;
601 } 601 }
602 } 602 }
603 603
604 if (status & UTSR0_TFS) 604 if (status & UTSR0_TFS)
605 printk(KERN_ERR "transmit fifo not full, shouldn't happen\n"); 605 printk(KERN_ERR "transmit fifo not full, shouldn't happen\n");
606 606
607 /* We must clear certain bits. */ 607 /* We must clear certain bits. */
608 status &= (UTSR0_RID | UTSR0_RBB | UTSR0_REB); 608 status &= (UTSR0_RID | UTSR0_RBB | UTSR0_REB);
609 if (status) 609 if (status)
610 Ser2UTSR0 = status; 610 Ser2UTSR0 = status;
611 #else 611 #else
612 unsigned long deltintrtv; 612 unsigned long deltintrtv;
613 unsigned long flags; 613 unsigned long flags;
614 int iir, lsr; 614 int iir, lsr;
615 615
616 while ((iir = inb(io + UART_IIR) & UART_IIR_ID)) { 616 while ((iir = inb(io + UART_IIR) & UART_IIR_ID)) {
617 switch (iir&UART_IIR_ID) { /* FIXME toto treba preriedit */ 617 switch (iir&UART_IIR_ID) { /* FIXME toto treba preriedit */
618 case UART_IIR_MSI: 618 case UART_IIR_MSI:
619 (void) inb(io + UART_MSR); 619 (void) inb(io + UART_MSR);
620 break; 620 break;
621 case UART_IIR_RLSI: 621 case UART_IIR_RLSI:
622 (void) inb(io + UART_LSR); 622 (void) inb(io + UART_LSR);
623 break; 623 break;
624 case UART_IIR_THRI: 624 case UART_IIR_THRI:
625 #if 0 625 #if 0
626 if (lsr & UART_LSR_THRE) /* FIFO is empty */ 626 if (lsr & UART_LSR_THRE) /* FIFO is empty */
627 outb(data, io + UART_TX) 627 outb(data, io + UART_TX)
628 #endif 628 #endif
629 break; 629 break;
630 case UART_IIR_RDI: 630 case UART_IIR_RDI:
631 /* avoid interference with timer */ 631 /* avoid interference with timer */
632 spin_lock_irqsave(&timer_lock, flags); 632 spin_lock_irqsave(&timer_lock, flags);
633 do { 633 do {
634 del_timer(&timerlist); 634 del_timer(&timerlist);
635 data = inb(io + UART_RX); 635 data = inb(io + UART_RX);
636 do_gettimeofday(&curr_tv); 636 do_gettimeofday(&curr_tv);
637 deltv = delta(&last_tv, &curr_tv); 637 deltv = delta(&last_tv, &curr_tv);
638 deltintrtv = delta(&last_intr_tv, &curr_tv); 638 deltintrtv = delta(&last_intr_tv, &curr_tv);
639 dprintk("t %lu, d %d\n", deltintrtv, (int)data); 639 dprintk("t %lu, d %d\n", deltintrtv, (int)data);
640 /* 640 /*
641 * if nothing came in last X cycles, 641 * if nothing came in last X cycles,
642 * it was gap 642 * it was gap
643 */ 643 */
644 if (deltintrtv > TIME_CONST * threshold) { 644 if (deltintrtv > TIME_CONST * threshold) {
645 if (last_value) { 645 if (last_value) {
646 dprintk("GAP\n"); 646 dprintk("GAP\n");
647 /* simulate signal change */ 647 /* simulate signal change */
648 add_read_queue(last_value, 648 add_read_queue(last_value,
649 deltv - 649 deltv -
650 deltintrtv); 650 deltintrtv);
651 last_value = 0; 651 last_value = 0;
652 last_tv.tv_sec = 652 last_tv.tv_sec =
653 last_intr_tv.tv_sec; 653 last_intr_tv.tv_sec;
654 last_tv.tv_usec = 654 last_tv.tv_usec =
655 last_intr_tv.tv_usec; 655 last_intr_tv.tv_usec;
656 deltv = deltintrtv; 656 deltv = deltintrtv;
657 } 657 }
658 } 658 }
659 data = 1; 659 data = 1;
660 if (data ^ last_value) { 660 if (data ^ last_value) {
661 /* 661 /*
662 * deltintrtv > 2*TIME_CONST, remember? 662 * deltintrtv > 2*TIME_CONST, remember?
663 * the other case is timeout 663 * the other case is timeout
664 */ 664 */
665 add_read_queue(last_value, 665 add_read_queue(last_value,
666 deltv-TIME_CONST); 666 deltv-TIME_CONST);
667 last_value = data; 667 last_value = data;
668 last_tv = curr_tv; 668 last_tv = curr_tv;
669 if (last_tv.tv_usec >= TIME_CONST) { 669 if (last_tv.tv_usec >= TIME_CONST) {
670 last_tv.tv_usec -= TIME_CONST; 670 last_tv.tv_usec -= TIME_CONST;
671 } else { 671 } else {
672 last_tv.tv_sec--; 672 last_tv.tv_sec--;
673 last_tv.tv_usec += 1000000 - 673 last_tv.tv_usec += 1000000 -
674 TIME_CONST; 674 TIME_CONST;
675 } 675 }
676 } 676 }
677 last_intr_tv = curr_tv; 677 last_intr_tv = curr_tv;
678 if (data) { 678 if (data) {
679 /* 679 /*
680 * start timer for end of 680 * start timer for end of
681 * sequence detection 681 * sequence detection
682 */ 682 */
683 timerlist.expires = jiffies + 683 timerlist.expires = jiffies +
684 SIR_TIMEOUT; 684 SIR_TIMEOUT;
685 add_timer(&timerlist); 685 add_timer(&timerlist);
686 } 686 }
687 687
688 lsr = inb(io + UART_LSR); 688 lsr = inb(io + UART_LSR);
689 } while (lsr & UART_LSR_DR); /* data ready */ 689 } while (lsr & UART_LSR_DR); /* data ready */
690 spin_unlock_irqrestore(&timer_lock, flags); 690 spin_unlock_irqrestore(&timer_lock, flags);
691 break; 691 break;
692 default: 692 default:
693 break; 693 break;
694 } 694 }
695 } 695 }
696 #endif 696 #endif
697 return IRQ_RETVAL(IRQ_HANDLED); 697 return IRQ_RETVAL(IRQ_HANDLED);
698 } 698 }
699 699
700 #ifdef LIRC_ON_SA1100 700 #ifdef LIRC_ON_SA1100
701 static void send_pulse(unsigned long length) 701 static void send_pulse(unsigned long length)
702 { 702 {
703 unsigned long k, delay; 703 unsigned long k, delay;
704 int flag; 704 int flag;
705 705
706 if (length == 0) 706 if (length == 0)
707 return; 707 return;
708 /* 708 /*
709 * this won't give us the carrier frequency we really want 709 * this won't give us the carrier frequency we really want
710 * due to integer arithmetic, but we can accept this inaccuracy 710 * due to integer arithmetic, but we can accept this inaccuracy
711 */ 711 */
712 712
713 for (k = flag = 0; k < length; k += delay, flag = !flag) { 713 for (k = flag = 0; k < length; k += delay, flag = !flag) {
714 if (flag) { 714 if (flag) {
715 off(); 715 off();
716 delay = space_width; 716 delay = space_width;
717 } else { 717 } else {
718 on(); 718 on();
719 delay = pulse_width; 719 delay = pulse_width;
720 } 720 }
721 safe_udelay(delay); 721 safe_udelay(delay);
722 } 722 }
723 off(); 723 off();
724 } 724 }
725 725
726 static void send_space(unsigned long length) 726 static void send_space(unsigned long length)
727 { 727 {
728 if (length == 0) 728 if (length == 0)
729 return; 729 return;
730 off(); 730 off();
731 safe_udelay(length); 731 safe_udelay(length);
732 } 732 }
733 #else 733 #else
734 static void send_space(unsigned long len) 734 static void send_space(unsigned long len)
735 { 735 {
736 safe_udelay(len); 736 safe_udelay(len);
737 } 737 }
738 738
739 static void send_pulse(unsigned long len) 739 static void send_pulse(unsigned long len)
740 { 740 {
741 long bytes_out = len / TIME_CONST; 741 long bytes_out = len / TIME_CONST;
742 long time_left;
743 742
744 time_left = (long)len - (long)bytes_out * (long)TIME_CONST; 743 if (bytes_out == 0)
745 if (bytes_out == 0) {
746 bytes_out++; 744 bytes_out++;
747 time_left = 0; 745
748 }
749 while (bytes_out--) { 746 while (bytes_out--) {
750 outb(PULSE, io + UART_TX); 747 outb(PULSE, io + UART_TX);
751 /* FIXME treba seriozne cakanie z char/serial.c */ 748 /* FIXME treba seriozne cakanie z char/serial.c */
752 while (!(inb(io + UART_LSR) & UART_LSR_THRE)) 749 while (!(inb(io + UART_LSR) & UART_LSR_THRE))
753 ; 750 ;
754 } 751 }
755 #if 0
756 if (time_left > 0)
757 safe_udelay(time_left);
758 #endif
759 } 752 }
760 #endif 753 #endif
761 754
762 #ifdef CONFIG_SA1100_COLLIE 755 #ifdef CONFIG_SA1100_COLLIE
763 static int sa1100_irda_set_power_collie(int state) 756 static int sa1100_irda_set_power_collie(int state)
764 { 757 {
765 if (state) { 758 if (state) {
766 /* 759 /*
767 * 0 - off 760 * 0 - off
768 * 1 - short range, lowest power 761 * 1 - short range, lowest power
769 * 2 - medium range, medium power 762 * 2 - medium range, medium power
770 * 3 - maximum range, high power 763 * 3 - maximum range, high power
771 */ 764 */
772 ucb1200_set_io_direction(TC35143_GPIO_IR_ON, 765 ucb1200_set_io_direction(TC35143_GPIO_IR_ON,
773 TC35143_IODIR_OUTPUT); 766 TC35143_IODIR_OUTPUT);
774 ucb1200_set_io(TC35143_GPIO_IR_ON, TC35143_IODAT_LOW); 767 ucb1200_set_io(TC35143_GPIO_IR_ON, TC35143_IODAT_LOW);
775 udelay(100); 768 udelay(100);
776 } else { 769 } else {
777 /* OFF */ 770 /* OFF */
778 ucb1200_set_io_direction(TC35143_GPIO_IR_ON, 771 ucb1200_set_io_direction(TC35143_GPIO_IR_ON,
779 TC35143_IODIR_OUTPUT); 772 TC35143_IODIR_OUTPUT);
780 ucb1200_set_io(TC35143_GPIO_IR_ON, TC35143_IODAT_HIGH); 773 ucb1200_set_io(TC35143_GPIO_IR_ON, TC35143_IODAT_HIGH);
781 } 774 }
782 return 0; 775 return 0;
783 } 776 }
784 #endif 777 #endif
785 778
786 static int init_hardware(void) 779 static int init_hardware(void)
787 { 780 {
788 unsigned long flags; 781 unsigned long flags;
789 782
790 spin_lock_irqsave(&hardware_lock, flags); 783 spin_lock_irqsave(&hardware_lock, flags);
791 /* reset UART */ 784 /* reset UART */
792 #ifdef LIRC_ON_SA1100 785 #ifdef LIRC_ON_SA1100
793 #ifdef CONFIG_SA1100_BITSY 786 #ifdef CONFIG_SA1100_BITSY
794 if (machine_is_bitsy()) { 787 if (machine_is_bitsy()) {
795 printk(KERN_INFO "Power on IR module\n"); 788 printk(KERN_INFO "Power on IR module\n");
796 set_bitsy_egpio(EGPIO_BITSY_IR_ON); 789 set_bitsy_egpio(EGPIO_BITSY_IR_ON);
797 } 790 }
798 #endif 791 #endif
799 #ifdef CONFIG_SA1100_COLLIE 792 #ifdef CONFIG_SA1100_COLLIE
800 sa1100_irda_set_power_collie(3); /* power on */ 793 sa1100_irda_set_power_collie(3); /* power on */
801 #endif 794 #endif
802 sr.hscr0 = Ser2HSCR0; 795 sr.hscr0 = Ser2HSCR0;
803 796
804 sr.utcr0 = Ser2UTCR0; 797 sr.utcr0 = Ser2UTCR0;
805 sr.utcr1 = Ser2UTCR1; 798 sr.utcr1 = Ser2UTCR1;
806 sr.utcr2 = Ser2UTCR2; 799 sr.utcr2 = Ser2UTCR2;
807 sr.utcr3 = Ser2UTCR3; 800 sr.utcr3 = Ser2UTCR3;
808 sr.utcr4 = Ser2UTCR4; 801 sr.utcr4 = Ser2UTCR4;
809 802
810 sr.utdr = Ser2UTDR; 803 sr.utdr = Ser2UTDR;
811 sr.utsr0 = Ser2UTSR0; 804 sr.utsr0 = Ser2UTSR0;
812 sr.utsr1 = Ser2UTSR1; 805 sr.utsr1 = Ser2UTSR1;
813 806
814 /* configure GPIO */ 807 /* configure GPIO */
815 /* output */ 808 /* output */
816 PPDR |= PPC_TXD2; 809 PPDR |= PPC_TXD2;
817 PSDR |= PPC_TXD2; 810 PSDR |= PPC_TXD2;
818 /* set output to 0 */ 811 /* set output to 0 */
819 off(); 812 off();
820 813
821 /* Enable HP-SIR modulation, and ensure that the port is disabled. */ 814 /* Enable HP-SIR modulation, and ensure that the port is disabled. */
822 Ser2UTCR3 = 0; 815 Ser2UTCR3 = 0;
823 Ser2HSCR0 = sr.hscr0 & (~HSCR0_HSSP); 816 Ser2HSCR0 = sr.hscr0 & (~HSCR0_HSSP);
824 817
825 /* clear status register to prevent unwanted interrupts */ 818 /* clear status register to prevent unwanted interrupts */
826 Ser2UTSR0 &= (UTSR0_RID | UTSR0_RBB | UTSR0_REB); 819 Ser2UTSR0 &= (UTSR0_RID | UTSR0_RBB | UTSR0_REB);
827 820
828 /* 7N1 */ 821 /* 7N1 */
829 Ser2UTCR0 = UTCR0_1StpBit|UTCR0_7BitData; 822 Ser2UTCR0 = UTCR0_1StpBit|UTCR0_7BitData;
830 /* 115200 */ 823 /* 115200 */
831 Ser2UTCR1 = 0; 824 Ser2UTCR1 = 0;
832 Ser2UTCR2 = 1; 825 Ser2UTCR2 = 1;
833 /* use HPSIR, 1.6 usec pulses */ 826 /* use HPSIR, 1.6 usec pulses */
834 Ser2UTCR4 = UTCR4_HPSIR|UTCR4_Z1_6us; 827 Ser2UTCR4 = UTCR4_HPSIR|UTCR4_Z1_6us;
835 828
836 /* enable receiver, receive fifo interrupt */ 829 /* enable receiver, receive fifo interrupt */
837 Ser2UTCR3 = UTCR3_RXE|UTCR3_RIE; 830 Ser2UTCR3 = UTCR3_RXE|UTCR3_RIE;
838 831
839 /* clear status register to prevent unwanted interrupts */ 832 /* clear status register to prevent unwanted interrupts */
840 Ser2UTSR0 &= (UTSR0_RID | UTSR0_RBB | UTSR0_REB); 833 Ser2UTSR0 &= (UTSR0_RID | UTSR0_RBB | UTSR0_REB);
841 834
842 #elif defined(LIRC_SIR_TEKRAM) 835 #elif defined(LIRC_SIR_TEKRAM)
843 /* disable FIFO */ 836 /* disable FIFO */
844 soutp(UART_FCR, 837 soutp(UART_FCR,
845 UART_FCR_CLEAR_RCVR| 838 UART_FCR_CLEAR_RCVR|
846 UART_FCR_CLEAR_XMIT| 839 UART_FCR_CLEAR_XMIT|
847 UART_FCR_TRIGGER_1); 840 UART_FCR_TRIGGER_1);
848 841
849 /* Set DLAB 0. */ 842 /* Set DLAB 0. */
850 soutp(UART_LCR, sinp(UART_LCR) & (~UART_LCR_DLAB)); 843 soutp(UART_LCR, sinp(UART_LCR) & (~UART_LCR_DLAB));
851 844
852 /* First of all, disable all interrupts */ 845 /* First of all, disable all interrupts */
853 soutp(UART_IER, sinp(UART_IER) & 846 soutp(UART_IER, sinp(UART_IER) &
854 (~(UART_IER_MSI|UART_IER_RLSI|UART_IER_THRI|UART_IER_RDI))); 847 (~(UART_IER_MSI|UART_IER_RLSI|UART_IER_THRI|UART_IER_RDI)));
855 848
856 /* Set DLAB 1. */ 849 /* Set DLAB 1. */
857 soutp(UART_LCR, sinp(UART_LCR) | UART_LCR_DLAB); 850 soutp(UART_LCR, sinp(UART_LCR) | UART_LCR_DLAB);
858 851
859 /* Set divisor to 12 => 9600 Baud */ 852 /* Set divisor to 12 => 9600 Baud */
860 soutp(UART_DLM, 0); 853 soutp(UART_DLM, 0);
861 soutp(UART_DLL, 12); 854 soutp(UART_DLL, 12);
862 855
863 /* Set DLAB 0. */ 856 /* Set DLAB 0. */
864 soutp(UART_LCR, sinp(UART_LCR) & (~UART_LCR_DLAB)); 857 soutp(UART_LCR, sinp(UART_LCR) & (~UART_LCR_DLAB));
865 858
866 /* power supply */ 859 /* power supply */
867 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2); 860 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2);
868 safe_udelay(50*1000); 861 safe_udelay(50*1000);
869 862
870 /* -DTR low -> reset PIC */ 863 /* -DTR low -> reset PIC */
871 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_OUT2); 864 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_OUT2);
872 udelay(1*1000); 865 udelay(1*1000);
873 866
874 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2); 867 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2);
875 udelay(100); 868 udelay(100);
876 869
877 870
878 /* -RTS low -> send control byte */ 871 /* -RTS low -> send control byte */
879 soutp(UART_MCR, UART_MCR_DTR|UART_MCR_OUT2); 872 soutp(UART_MCR, UART_MCR_DTR|UART_MCR_OUT2);
880 udelay(7); 873 udelay(7);
881 soutp(UART_TX, TEKRAM_115200|TEKRAM_PW); 874 soutp(UART_TX, TEKRAM_115200|TEKRAM_PW);
882 875
883 /* one byte takes ~1042 usec to transmit at 9600,8N1 */ 876 /* one byte takes ~1042 usec to transmit at 9600,8N1 */
884 udelay(1500); 877 udelay(1500);
885 878
886 /* back to normal operation */ 879 /* back to normal operation */
887 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2); 880 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2);
888 udelay(50); 881 udelay(50);
889 882
890 udelay(1500); 883 udelay(1500);
891 884
892 /* read previous control byte */ 885 /* read previous control byte */
893 printk(KERN_INFO LIRC_DRIVER_NAME 886 printk(KERN_INFO LIRC_DRIVER_NAME
894 ": 0x%02x\n", sinp(UART_RX)); 887 ": 0x%02x\n", sinp(UART_RX));
895 888
896 /* Set DLAB 1. */ 889 /* Set DLAB 1. */
897 soutp(UART_LCR, sinp(UART_LCR) | UART_LCR_DLAB); 890 soutp(UART_LCR, sinp(UART_LCR) | UART_LCR_DLAB);
898 891
899 /* Set divisor to 1 => 115200 Baud */ 892 /* Set divisor to 1 => 115200 Baud */
900 soutp(UART_DLM, 0); 893 soutp(UART_DLM, 0);
901 soutp(UART_DLL, 1); 894 soutp(UART_DLL, 1);
902 895
903 /* Set DLAB 0, 8 Bit */ 896 /* Set DLAB 0, 8 Bit */
904 soutp(UART_LCR, UART_LCR_WLEN8); 897 soutp(UART_LCR, UART_LCR_WLEN8);
905 /* enable interrupts */ 898 /* enable interrupts */
906 soutp(UART_IER, sinp(UART_IER)|UART_IER_RDI); 899 soutp(UART_IER, sinp(UART_IER)|UART_IER_RDI);
907 #else 900 #else
908 outb(0, io + UART_MCR); 901 outb(0, io + UART_MCR);
909 outb(0, io + UART_IER); 902 outb(0, io + UART_IER);
910 /* init UART */ 903 /* init UART */
911 /* set DLAB, speed = 115200 */ 904 /* set DLAB, speed = 115200 */
912 outb(UART_LCR_DLAB | UART_LCR_WLEN7, io + UART_LCR); 905 outb(UART_LCR_DLAB | UART_LCR_WLEN7, io + UART_LCR);
913 outb(1, io + UART_DLL); outb(0, io + UART_DLM); 906 outb(1, io + UART_DLL); outb(0, io + UART_DLM);
914 /* 7N1+start = 9 bits at 115200 ~ 3 bits at 44000 */ 907 /* 7N1+start = 9 bits at 115200 ~ 3 bits at 44000 */
915 outb(UART_LCR_WLEN7, io + UART_LCR); 908 outb(UART_LCR_WLEN7, io + UART_LCR);
916 /* FIFO operation */ 909 /* FIFO operation */
917 outb(UART_FCR_ENABLE_FIFO, io + UART_FCR); 910 outb(UART_FCR_ENABLE_FIFO, io + UART_FCR);
918 /* interrupts */ 911 /* interrupts */
919 /* outb(UART_IER_RLSI|UART_IER_RDI|UART_IER_THRI, io + UART_IER); */ 912 /* outb(UART_IER_RLSI|UART_IER_RDI|UART_IER_THRI, io + UART_IER); */
920 outb(UART_IER_RDI, io + UART_IER); 913 outb(UART_IER_RDI, io + UART_IER);
921 /* turn on UART */ 914 /* turn on UART */
922 outb(UART_MCR_DTR|UART_MCR_RTS|UART_MCR_OUT2, io + UART_MCR); 915 outb(UART_MCR_DTR|UART_MCR_RTS|UART_MCR_OUT2, io + UART_MCR);
923 #ifdef LIRC_SIR_ACTISYS_ACT200L 916 #ifdef LIRC_SIR_ACTISYS_ACT200L
924 init_act200(); 917 init_act200();
925 #elif defined(LIRC_SIR_ACTISYS_ACT220L) 918 #elif defined(LIRC_SIR_ACTISYS_ACT220L)
926 init_act220(); 919 init_act220();
927 #endif 920 #endif
928 #endif 921 #endif
929 spin_unlock_irqrestore(&hardware_lock, flags); 922 spin_unlock_irqrestore(&hardware_lock, flags);
930 return 0; 923 return 0;
931 } 924 }
932 925
933 static void drop_hardware(void) 926 static void drop_hardware(void)
934 { 927 {
935 unsigned long flags; 928 unsigned long flags;
936 929
937 spin_lock_irqsave(&hardware_lock, flags); 930 spin_lock_irqsave(&hardware_lock, flags);
938 931
939 #ifdef LIRC_ON_SA1100 932 #ifdef LIRC_ON_SA1100
940 Ser2UTCR3 = 0; 933 Ser2UTCR3 = 0;
941 934
942 Ser2UTCR0 = sr.utcr0; 935 Ser2UTCR0 = sr.utcr0;
943 Ser2UTCR1 = sr.utcr1; 936 Ser2UTCR1 = sr.utcr1;
944 Ser2UTCR2 = sr.utcr2; 937 Ser2UTCR2 = sr.utcr2;
945 Ser2UTCR4 = sr.utcr4; 938 Ser2UTCR4 = sr.utcr4;
946 Ser2UTCR3 = sr.utcr3; 939 Ser2UTCR3 = sr.utcr3;
947 940
948 Ser2HSCR0 = sr.hscr0; 941 Ser2HSCR0 = sr.hscr0;
949 #ifdef CONFIG_SA1100_BITSY 942 #ifdef CONFIG_SA1100_BITSY
950 if (machine_is_bitsy()) 943 if (machine_is_bitsy())
951 clr_bitsy_egpio(EGPIO_BITSY_IR_ON); 944 clr_bitsy_egpio(EGPIO_BITSY_IR_ON);
952 #endif 945 #endif
953 #ifdef CONFIG_SA1100_COLLIE 946 #ifdef CONFIG_SA1100_COLLIE
954 sa1100_irda_set_power_collie(0); /* power off */ 947 sa1100_irda_set_power_collie(0); /* power off */
955 #endif 948 #endif
956 #else 949 #else
957 /* turn off interrupts */ 950 /* turn off interrupts */
958 outb(0, io + UART_IER); 951 outb(0, io + UART_IER);
959 #endif 952 #endif
960 spin_unlock_irqrestore(&hardware_lock, flags); 953 spin_unlock_irqrestore(&hardware_lock, flags);
961 } 954 }
962 955
963 /* SECTION: Initialisation */ 956 /* SECTION: Initialisation */
964 957
965 static int init_port(void) 958 static int init_port(void)
966 { 959 {
967 int retval; 960 int retval;
968 961
969 /* get I/O port access and IRQ line */ 962 /* get I/O port access and IRQ line */
970 #ifndef LIRC_ON_SA1100 963 #ifndef LIRC_ON_SA1100
971 if (request_region(io, 8, LIRC_DRIVER_NAME) == NULL) { 964 if (request_region(io, 8, LIRC_DRIVER_NAME) == NULL) {
972 printk(KERN_ERR LIRC_DRIVER_NAME 965 printk(KERN_ERR LIRC_DRIVER_NAME
973 ": i/o port 0x%.4x already in use.\n", io); 966 ": i/o port 0x%.4x already in use.\n", io);
974 return -EBUSY; 967 return -EBUSY;
975 } 968 }
976 #endif 969 #endif
977 retval = request_irq(irq, sir_interrupt, IRQF_DISABLED, 970 retval = request_irq(irq, sir_interrupt, IRQF_DISABLED,
978 LIRC_DRIVER_NAME, NULL); 971 LIRC_DRIVER_NAME, NULL);
979 if (retval < 0) { 972 if (retval < 0) {
980 # ifndef LIRC_ON_SA1100 973 # ifndef LIRC_ON_SA1100
981 release_region(io, 8); 974 release_region(io, 8);
982 # endif 975 # endif
983 printk(KERN_ERR LIRC_DRIVER_NAME 976 printk(KERN_ERR LIRC_DRIVER_NAME
984 ": IRQ %d already in use.\n", 977 ": IRQ %d already in use.\n",
985 irq); 978 irq);
986 return retval; 979 return retval;
987 } 980 }
988 #ifndef LIRC_ON_SA1100 981 #ifndef LIRC_ON_SA1100
989 printk(KERN_INFO LIRC_DRIVER_NAME 982 printk(KERN_INFO LIRC_DRIVER_NAME
990 ": I/O port 0x%.4x, IRQ %d.\n", 983 ": I/O port 0x%.4x, IRQ %d.\n",
991 io, irq); 984 io, irq);
992 #endif 985 #endif
993 986
994 init_timer(&timerlist); 987 init_timer(&timerlist);
995 timerlist.function = sir_timeout; 988 timerlist.function = sir_timeout;
996 timerlist.data = 0xabadcafe; 989 timerlist.data = 0xabadcafe;
997 990
998 return 0; 991 return 0;
999 } 992 }
1000 993
1001 static void drop_port(void) 994 static void drop_port(void)
1002 { 995 {
1003 free_irq(irq, NULL); 996 free_irq(irq, NULL);
1004 del_timer_sync(&timerlist); 997 del_timer_sync(&timerlist);
1005 #ifndef LIRC_ON_SA1100 998 #ifndef LIRC_ON_SA1100
1006 release_region(io, 8); 999 release_region(io, 8);
1007 #endif 1000 #endif
1008 } 1001 }
1009 1002
1010 #ifdef LIRC_SIR_ACTISYS_ACT200L 1003 #ifdef LIRC_SIR_ACTISYS_ACT200L
1011 /* Crystal/Cirrus CS8130 IR transceiver, used in Actisys Act200L dongle */ 1004 /* Crystal/Cirrus CS8130 IR transceiver, used in Actisys Act200L dongle */
1012 /* some code borrowed from Linux IRDA driver */ 1005 /* some code borrowed from Linux IRDA driver */
1013 1006
1014 /* Register 0: Control register #1 */ 1007 /* Register 0: Control register #1 */
1015 #define ACT200L_REG0 0x00 1008 #define ACT200L_REG0 0x00
1016 #define ACT200L_TXEN 0x01 /* Enable transmitter */ 1009 #define ACT200L_TXEN 0x01 /* Enable transmitter */
1017 #define ACT200L_RXEN 0x02 /* Enable receiver */ 1010 #define ACT200L_RXEN 0x02 /* Enable receiver */
1018 #define ACT200L_ECHO 0x08 /* Echo control chars */ 1011 #define ACT200L_ECHO 0x08 /* Echo control chars */
1019 1012
1020 /* Register 1: Control register #2 */ 1013 /* Register 1: Control register #2 */
1021 #define ACT200L_REG1 0x10 1014 #define ACT200L_REG1 0x10
1022 #define ACT200L_LODB 0x01 /* Load new baud rate count value */ 1015 #define ACT200L_LODB 0x01 /* Load new baud rate count value */
1023 #define ACT200L_WIDE 0x04 /* Expand the maximum allowable pulse */ 1016 #define ACT200L_WIDE 0x04 /* Expand the maximum allowable pulse */
1024 1017
1025 /* Register 3: Transmit mode register #2 */ 1018 /* Register 3: Transmit mode register #2 */
1026 #define ACT200L_REG3 0x30 1019 #define ACT200L_REG3 0x30
1027 #define ACT200L_B0 0x01 /* DataBits, 0=6, 1=7, 2=8, 3=9(8P) */ 1020 #define ACT200L_B0 0x01 /* DataBits, 0=6, 1=7, 2=8, 3=9(8P) */
1028 #define ACT200L_B1 0x02 /* DataBits, 0=6, 1=7, 2=8, 3=9(8P) */ 1021 #define ACT200L_B1 0x02 /* DataBits, 0=6, 1=7, 2=8, 3=9(8P) */
1029 #define ACT200L_CHSY 0x04 /* StartBit Synced 0=bittime, 1=startbit */ 1022 #define ACT200L_CHSY 0x04 /* StartBit Synced 0=bittime, 1=startbit */
1030 1023
1031 /* Register 4: Output Power register */ 1024 /* Register 4: Output Power register */
1032 #define ACT200L_REG4 0x40 1025 #define ACT200L_REG4 0x40
1033 #define ACT200L_OP0 0x01 /* Enable LED1C output */ 1026 #define ACT200L_OP0 0x01 /* Enable LED1C output */
1034 #define ACT200L_OP1 0x02 /* Enable LED2C output */ 1027 #define ACT200L_OP1 0x02 /* Enable LED2C output */
1035 #define ACT200L_BLKR 0x04 1028 #define ACT200L_BLKR 0x04
1036 1029
1037 /* Register 5: Receive Mode register */ 1030 /* Register 5: Receive Mode register */
1038 #define ACT200L_REG5 0x50 1031 #define ACT200L_REG5 0x50
1039 #define ACT200L_RWIDL 0x01 /* fixed 1.6us pulse mode */ 1032 #define ACT200L_RWIDL 0x01 /* fixed 1.6us pulse mode */
1040 /*.. other various IRDA bit modes, and TV remote modes..*/ 1033 /*.. other various IRDA bit modes, and TV remote modes..*/
1041 1034
1042 /* Register 6: Receive Sensitivity register #1 */ 1035 /* Register 6: Receive Sensitivity register #1 */
1043 #define ACT200L_REG6 0x60 1036 #define ACT200L_REG6 0x60
1044 #define ACT200L_RS0 0x01 /* receive threshold bit 0 */ 1037 #define ACT200L_RS0 0x01 /* receive threshold bit 0 */
1045 #define ACT200L_RS1 0x02 /* receive threshold bit 1 */ 1038 #define ACT200L_RS1 0x02 /* receive threshold bit 1 */
1046 1039
1047 /* Register 7: Receive Sensitivity register #2 */ 1040 /* Register 7: Receive Sensitivity register #2 */
1048 #define ACT200L_REG7 0x70 1041 #define ACT200L_REG7 0x70
1049 #define ACT200L_ENPOS 0x04 /* Ignore the falling edge */ 1042 #define ACT200L_ENPOS 0x04 /* Ignore the falling edge */
1050 1043
1051 /* Register 8,9: Baud Rate Divider register #1,#2 */ 1044 /* Register 8,9: Baud Rate Divider register #1,#2 */
1052 #define ACT200L_REG8 0x80 1045 #define ACT200L_REG8 0x80
1053 #define ACT200L_REG9 0x90 1046 #define ACT200L_REG9 0x90
1054 1047
1055 #define ACT200L_2400 0x5f 1048 #define ACT200L_2400 0x5f
1056 #define ACT200L_9600 0x17 1049 #define ACT200L_9600 0x17
1057 #define ACT200L_19200 0x0b 1050 #define ACT200L_19200 0x0b
1058 #define ACT200L_38400 0x05 1051 #define ACT200L_38400 0x05
1059 #define ACT200L_57600 0x03 1052 #define ACT200L_57600 0x03
1060 #define ACT200L_115200 0x01 1053 #define ACT200L_115200 0x01
1061 1054
1062 /* Register 13: Control register #3 */ 1055 /* Register 13: Control register #3 */
1063 #define ACT200L_REG13 0xd0 1056 #define ACT200L_REG13 0xd0
1064 #define ACT200L_SHDW 0x01 /* Enable access to shadow registers */ 1057 #define ACT200L_SHDW 0x01 /* Enable access to shadow registers */
1065 1058
1066 /* Register 15: Status register */ 1059 /* Register 15: Status register */
1067 #define ACT200L_REG15 0xf0 1060 #define ACT200L_REG15 0xf0
1068 1061
1069 /* Register 21: Control register #4 */ 1062 /* Register 21: Control register #4 */
1070 #define ACT200L_REG21 0x50 1063 #define ACT200L_REG21 0x50
1071 #define ACT200L_EXCK 0x02 /* Disable clock output driver */ 1064 #define ACT200L_EXCK 0x02 /* Disable clock output driver */
1072 #define ACT200L_OSCL 0x04 /* oscillator in low power, medium accuracy mode */ 1065 #define ACT200L_OSCL 0x04 /* oscillator in low power, medium accuracy mode */
1073 1066
1074 static void init_act200(void) 1067 static void init_act200(void)
1075 { 1068 {
1076 int i; 1069 int i;
1077 __u8 control[] = { 1070 __u8 control[] = {
1078 ACT200L_REG15, 1071 ACT200L_REG15,
1079 ACT200L_REG13 | ACT200L_SHDW, 1072 ACT200L_REG13 | ACT200L_SHDW,
1080 ACT200L_REG21 | ACT200L_EXCK | ACT200L_OSCL, 1073 ACT200L_REG21 | ACT200L_EXCK | ACT200L_OSCL,
1081 ACT200L_REG13, 1074 ACT200L_REG13,
1082 ACT200L_REG7 | ACT200L_ENPOS, 1075 ACT200L_REG7 | ACT200L_ENPOS,
1083 ACT200L_REG6 | ACT200L_RS0 | ACT200L_RS1, 1076 ACT200L_REG6 | ACT200L_RS0 | ACT200L_RS1,
1084 ACT200L_REG5 | ACT200L_RWIDL, 1077 ACT200L_REG5 | ACT200L_RWIDL,
1085 ACT200L_REG4 | ACT200L_OP0 | ACT200L_OP1 | ACT200L_BLKR, 1078 ACT200L_REG4 | ACT200L_OP0 | ACT200L_OP1 | ACT200L_BLKR,
1086 ACT200L_REG3 | ACT200L_B0, 1079 ACT200L_REG3 | ACT200L_B0,
1087 ACT200L_REG0 | ACT200L_TXEN | ACT200L_RXEN, 1080 ACT200L_REG0 | ACT200L_TXEN | ACT200L_RXEN,
1088 ACT200L_REG8 | (ACT200L_115200 & 0x0f), 1081 ACT200L_REG8 | (ACT200L_115200 & 0x0f),
1089 ACT200L_REG9 | ((ACT200L_115200 >> 4) & 0x0f), 1082 ACT200L_REG9 | ((ACT200L_115200 >> 4) & 0x0f),
1090 ACT200L_REG1 | ACT200L_LODB | ACT200L_WIDE 1083 ACT200L_REG1 | ACT200L_LODB | ACT200L_WIDE
1091 }; 1084 };
1092 1085
1093 /* Set DLAB 1. */ 1086 /* Set DLAB 1. */
1094 soutp(UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN8); 1087 soutp(UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN8);
1095 1088
1096 /* Set divisor to 12 => 9600 Baud */ 1089 /* Set divisor to 12 => 9600 Baud */
1097 soutp(UART_DLM, 0); 1090 soutp(UART_DLM, 0);
1098 soutp(UART_DLL, 12); 1091 soutp(UART_DLL, 12);
1099 1092
1100 /* Set DLAB 0. */ 1093 /* Set DLAB 0. */
1101 soutp(UART_LCR, UART_LCR_WLEN8); 1094 soutp(UART_LCR, UART_LCR_WLEN8);
1102 /* Set divisor to 12 => 9600 Baud */ 1095 /* Set divisor to 12 => 9600 Baud */
1103 1096
1104 /* power supply */ 1097 /* power supply */
1105 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2); 1098 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2);
1106 for (i = 0; i < 50; i++) 1099 for (i = 0; i < 50; i++)
1107 safe_udelay(1000); 1100 safe_udelay(1000);
1108 1101
1109 /* Reset the dongle : set RTS low for 25 ms */ 1102 /* Reset the dongle : set RTS low for 25 ms */
1110 soutp(UART_MCR, UART_MCR_DTR|UART_MCR_OUT2); 1103 soutp(UART_MCR, UART_MCR_DTR|UART_MCR_OUT2);
1111 for (i = 0; i < 25; i++) 1104 for (i = 0; i < 25; i++)
1112 udelay(1000); 1105 udelay(1000);
1113 1106
1114 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2); 1107 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2);
1115 udelay(100); 1108 udelay(100);
1116 1109
1117 /* Clear DTR and set RTS to enter command mode */ 1110 /* Clear DTR and set RTS to enter command mode */
1118 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_OUT2); 1111 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_OUT2);
1119 udelay(7); 1112 udelay(7);
1120 1113
1121 /* send out the control register settings for 115K 7N1 SIR operation */ 1114 /* send out the control register settings for 115K 7N1 SIR operation */
1122 for (i = 0; i < sizeof(control); i++) { 1115 for (i = 0; i < sizeof(control); i++) {
1123 soutp(UART_TX, control[i]); 1116 soutp(UART_TX, control[i]);
1124 /* one byte takes ~1042 usec to transmit at 9600,8N1 */ 1117 /* one byte takes ~1042 usec to transmit at 9600,8N1 */
1125 udelay(1500); 1118 udelay(1500);
1126 } 1119 }
1127 1120
1128 /* back to normal operation */ 1121 /* back to normal operation */
1129 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2); 1122 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2);
1130 udelay(50); 1123 udelay(50);
1131 1124
1132 udelay(1500); 1125 udelay(1500);
1133 soutp(UART_LCR, sinp(UART_LCR) | UART_LCR_DLAB); 1126 soutp(UART_LCR, sinp(UART_LCR) | UART_LCR_DLAB);
1134 1127
1135 /* Set DLAB 1. */ 1128 /* Set DLAB 1. */
1136 soutp(UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN7); 1129 soutp(UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN7);
1137 1130
1138 /* Set divisor to 1 => 115200 Baud */ 1131 /* Set divisor to 1 => 115200 Baud */
1139 soutp(UART_DLM, 0); 1132 soutp(UART_DLM, 0);
1140 soutp(UART_DLL, 1); 1133 soutp(UART_DLL, 1);
1141 1134
1142 /* Set DLAB 0. */ 1135 /* Set DLAB 0. */
1143 soutp(UART_LCR, sinp(UART_LCR) & (~UART_LCR_DLAB)); 1136 soutp(UART_LCR, sinp(UART_LCR) & (~UART_LCR_DLAB));
1144 1137
1145 /* Set DLAB 0, 7 Bit */ 1138 /* Set DLAB 0, 7 Bit */
1146 soutp(UART_LCR, UART_LCR_WLEN7); 1139 soutp(UART_LCR, UART_LCR_WLEN7);
1147 1140
1148 /* enable interrupts */ 1141 /* enable interrupts */
1149 soutp(UART_IER, sinp(UART_IER)|UART_IER_RDI); 1142 soutp(UART_IER, sinp(UART_IER)|UART_IER_RDI);
1150 } 1143 }
1151 #endif 1144 #endif
1152 1145
1153 #ifdef LIRC_SIR_ACTISYS_ACT220L 1146 #ifdef LIRC_SIR_ACTISYS_ACT220L
1154 /* 1147 /*
1155 * Derived from linux IrDA driver (net/irda/actisys.c) 1148 * Derived from linux IrDA driver (net/irda/actisys.c)
1156 * Drop me a mail for any kind of comment: maxx@spaceboyz.net 1149 * Drop me a mail for any kind of comment: maxx@spaceboyz.net
1157 */ 1150 */
1158 1151
1159 void init_act220(void) 1152 void init_act220(void)
1160 { 1153 {
1161 int i; 1154 int i;
1162 1155
1163 /* DLAB 1 */ 1156 /* DLAB 1 */
1164 soutp(UART_LCR, UART_LCR_DLAB|UART_LCR_WLEN7); 1157 soutp(UART_LCR, UART_LCR_DLAB|UART_LCR_WLEN7);
1165 1158
1166 /* 9600 baud */ 1159 /* 9600 baud */
1167 soutp(UART_DLM, 0); 1160 soutp(UART_DLM, 0);
1168 soutp(UART_DLL, 12); 1161 soutp(UART_DLL, 12);
1169 1162
1170 /* DLAB 0 */ 1163 /* DLAB 0 */
1171 soutp(UART_LCR, UART_LCR_WLEN7); 1164 soutp(UART_LCR, UART_LCR_WLEN7);
1172 1165
1173 /* reset the dongle, set DTR low for 10us */ 1166 /* reset the dongle, set DTR low for 10us */
1174 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_OUT2); 1167 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_OUT2);
1175 udelay(10); 1168 udelay(10);
1176 1169
1177 /* back to normal (still 9600) */ 1170 /* back to normal (still 9600) */
1178 soutp(UART_MCR, UART_MCR_DTR|UART_MCR_RTS|UART_MCR_OUT2); 1171 soutp(UART_MCR, UART_MCR_DTR|UART_MCR_RTS|UART_MCR_OUT2);
1179 1172
1180 /* 1173 /*
1181 * send RTS pulses until we reach 115200 1174 * send RTS pulses until we reach 115200
1182 * i hope this is really the same for act220l/act220l+ 1175 * i hope this is really the same for act220l/act220l+
1183 */ 1176 */
1184 for (i = 0; i < 3; i++) { 1177 for (i = 0; i < 3; i++) {
1185 udelay(10); 1178 udelay(10);
1186 /* set RTS low for 10 us */ 1179 /* set RTS low for 10 us */
1187 soutp(UART_MCR, UART_MCR_DTR|UART_MCR_OUT2); 1180 soutp(UART_MCR, UART_MCR_DTR|UART_MCR_OUT2);
1188 udelay(10); 1181 udelay(10);
1189 /* set RTS high for 10 us */ 1182 /* set RTS high for 10 us */
1190 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2); 1183 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2);
1191 } 1184 }
1192 1185
1193 /* back to normal operation */ 1186 /* back to normal operation */
1194 udelay(1500); /* better safe than sorry ;) */ 1187 udelay(1500); /* better safe than sorry ;) */
1195 1188
1196 /* Set DLAB 1. */ 1189 /* Set DLAB 1. */
1197 soutp(UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN7); 1190 soutp(UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN7);
1198 1191
1199 /* Set divisor to 1 => 115200 Baud */ 1192 /* Set divisor to 1 => 115200 Baud */
1200 soutp(UART_DLM, 0); 1193 soutp(UART_DLM, 0);
1201 soutp(UART_DLL, 1); 1194 soutp(UART_DLL, 1);
1202 1195
1203 /* Set DLAB 0, 7 Bit */ 1196 /* Set DLAB 0, 7 Bit */
1204 /* The dongle doesn't seem to have any problems with operation at 7N1 */ 1197 /* The dongle doesn't seem to have any problems with operation at 7N1 */
1205 soutp(UART_LCR, UART_LCR_WLEN7); 1198 soutp(UART_LCR, UART_LCR_WLEN7);
1206 1199
1207 /* enable interrupts */ 1200 /* enable interrupts */
1208 soutp(UART_IER, UART_IER_RDI); 1201 soutp(UART_IER, UART_IER_RDI);
1209 } 1202 }
1210 #endif 1203 #endif
1211 1204
1212 static int init_lirc_sir(void) 1205 static int init_lirc_sir(void)
1213 { 1206 {
1214 int retval; 1207 int retval;
1215 1208
1216 init_waitqueue_head(&lirc_read_queue); 1209 init_waitqueue_head(&lirc_read_queue);
1217 retval = init_port(); 1210 retval = init_port();
1218 if (retval < 0) 1211 if (retval < 0)
1219 return retval; 1212 return retval;
1220 init_hardware(); 1213 init_hardware();
1221 printk(KERN_INFO LIRC_DRIVER_NAME 1214 printk(KERN_INFO LIRC_DRIVER_NAME
1222 ": Installed.\n"); 1215 ": Installed.\n");
1223 return 0; 1216 return 0;
1224 } 1217 }
1225 1218
1226 1219
1227 static int __init lirc_sir_init(void) 1220 static int __init lirc_sir_init(void)
1228 { 1221 {
1229 int retval; 1222 int retval;
1230 1223
1231 retval = init_chrdev(); 1224 retval = init_chrdev();
1232 if (retval < 0) 1225 if (retval < 0)
1233 return retval; 1226 return retval;
1234 retval = init_lirc_sir(); 1227 retval = init_lirc_sir();
1235 if (retval) { 1228 if (retval) {
1236 drop_chrdev(); 1229 drop_chrdev();
1237 return retval; 1230 return retval;
1238 } 1231 }
1239 return 0; 1232 return 0;
1240 } 1233 }
1241 1234
1242 static void __exit lirc_sir_exit(void) 1235 static void __exit lirc_sir_exit(void)
1243 { 1236 {
1244 drop_hardware(); 1237 drop_hardware();
1245 drop_chrdev(); 1238 drop_chrdev();
1246 drop_port(); 1239 drop_port();
1247 printk(KERN_INFO LIRC_DRIVER_NAME ": Uninstalled.\n"); 1240 printk(KERN_INFO LIRC_DRIVER_NAME ": Uninstalled.\n");
1248 } 1241 }
1249 1242
1250 module_init(lirc_sir_init); 1243 module_init(lirc_sir_init);
1251 module_exit(lirc_sir_exit); 1244 module_exit(lirc_sir_exit);
1252 1245
1253 #ifdef LIRC_SIR_TEKRAM 1246 #ifdef LIRC_SIR_TEKRAM
1254 MODULE_DESCRIPTION("Infrared receiver driver for Tekram Irmate 210"); 1247 MODULE_DESCRIPTION("Infrared receiver driver for Tekram Irmate 210");
1255 MODULE_AUTHOR("Christoph Bartelmus"); 1248 MODULE_AUTHOR("Christoph Bartelmus");
1256 #elif defined(LIRC_ON_SA1100) 1249 #elif defined(LIRC_ON_SA1100)
1257 MODULE_DESCRIPTION("LIRC driver for StrongARM SA1100 embedded microprocessor"); 1250 MODULE_DESCRIPTION("LIRC driver for StrongARM SA1100 embedded microprocessor");
1258 MODULE_AUTHOR("Christoph Bartelmus"); 1251 MODULE_AUTHOR("Christoph Bartelmus");
1259 #elif defined(LIRC_SIR_ACTISYS_ACT200L) 1252 #elif defined(LIRC_SIR_ACTISYS_ACT200L)
1260 MODULE_DESCRIPTION("LIRC driver for Actisys Act200L"); 1253 MODULE_DESCRIPTION("LIRC driver for Actisys Act200L");
1261 MODULE_AUTHOR("Karl Bongers"); 1254 MODULE_AUTHOR("Karl Bongers");
1262 #elif defined(LIRC_SIR_ACTISYS_ACT220L) 1255 #elif defined(LIRC_SIR_ACTISYS_ACT220L)
1263 MODULE_DESCRIPTION("LIRC driver for Actisys Act220L(+)"); 1256 MODULE_DESCRIPTION("LIRC driver for Actisys Act220L(+)");
1264 MODULE_AUTHOR("Jan Roemisch"); 1257 MODULE_AUTHOR("Jan Roemisch");
1265 #else 1258 #else
1266 MODULE_DESCRIPTION("Infrared receiver driver for SIR type serial ports"); 1259 MODULE_DESCRIPTION("Infrared receiver driver for SIR type serial ports");
1267 MODULE_AUTHOR("Milan Pikula"); 1260 MODULE_AUTHOR("Milan Pikula");
1268 #endif 1261 #endif
1269 MODULE_LICENSE("GPL"); 1262 MODULE_LICENSE("GPL");
1270 1263
1271 #ifdef LIRC_ON_SA1100 1264 #ifdef LIRC_ON_SA1100
1272 module_param(irq, int, S_IRUGO); 1265 module_param(irq, int, S_IRUGO);
1273 MODULE_PARM_DESC(irq, "Interrupt (16)"); 1266 MODULE_PARM_DESC(irq, "Interrupt (16)");
1274 #else 1267 #else
1275 module_param(io, int, S_IRUGO); 1268 module_param(io, int, S_IRUGO);
1276 MODULE_PARM_DESC(io, "I/O address base (0x3f8 or 0x2f8)"); 1269 MODULE_PARM_DESC(io, "I/O address base (0x3f8 or 0x2f8)");
1277 1270
1278 module_param(irq, int, S_IRUGO); 1271 module_param(irq, int, S_IRUGO);
1279 MODULE_PARM_DESC(irq, "Interrupt (4 or 3)"); 1272 MODULE_PARM_DESC(irq, "Interrupt (4 or 3)");
1280 1273
1281 module_param(threshold, int, S_IRUGO); 1274 module_param(threshold, int, S_IRUGO);
1282 MODULE_PARM_DESC(threshold, "space detection threshold (3)"); 1275 MODULE_PARM_DESC(threshold, "space detection threshold (3)");
1283 #endif 1276 #endif
1284 1277
1285 module_param(debug, bool, S_IRUGO | S_IWUSR); 1278 module_param(debug, bool, S_IRUGO | S_IWUSR);
1286 MODULE_PARM_DESC(debug, "Enable debugging messages"); 1279 MODULE_PARM_DESC(debug, "Enable debugging messages");
1287 1280