Eric Lee / linux-smarc-t335x-v3.2

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/*

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/*

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* New driver for Marvell Yukon chipset and SysKonnect Gigabit

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* New driver for Marvell Yukon chipset and SysKonnect Gigabit

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* Ethernet adapters. Based on earlier sk98lin, e100 and

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* Ethernet adapters. Based on earlier sk98lin, e100 and

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* FreeBSD if_sk drivers.

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* FreeBSD if_sk drivers.

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*

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*

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* This driver intentionally does not support all the features

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* This driver intentionally does not support all the features

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* of the original driver such as link fail-over and link management because

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* of the original driver such as link fail-over and link management because

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* those should be done at higher levels.

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* those should be done at higher levels.

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*

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*

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*

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*

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* This program is free software; you can redistribute it and/or modify

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* This program is free software; you can redistribute it and/or modify

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* it under the terms of the GNU General Public License as published by

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* it under the terms of the GNU General Public License as published by

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* the Free Software Foundation; either version 2 of the License, or

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* the Free Software Foundation; either version 2 of the License, or

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* (at your option) any later version.

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* (at your option) any later version.

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*

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*

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* This program is distributed in the hope that it will be useful,

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* This program is distributed in the hope that it will be useful,

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* but WITHOUT ANY WARRANTY; without even the implied warranty of

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* but WITHOUT ANY WARRANTY; without even the implied warranty of

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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

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* GNU General Public License for more details.

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* GNU General Public License for more details.

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*

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*

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* You should have received a copy of the GNU General Public License

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* You should have received a copy of the GNU General Public License

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* along with this program; if not, write to the Free Software

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* along with this program; if not, write to the Free Software

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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.

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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.

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*/

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*/

26

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#include <linux/config.h>

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#include <linux/config.h>

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#include <linux/in.h>

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#include <linux/in.h>

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#include <linux/kernel.h>

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#include <linux/kernel.h>

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#include <linux/module.h>

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#include <linux/module.h>

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#include <linux/moduleparam.h>

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#include <linux/moduleparam.h>

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#include <linux/netdevice.h>

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#include <linux/netdevice.h>

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#include <linux/etherdevice.h>

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#include <linux/etherdevice.h>

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#include <linux/ethtool.h>

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#include <linux/ethtool.h>

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#include <linux/pci.h>

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#include <linux/pci.h>

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#include <linux/if_vlan.h>

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#include <linux/if_vlan.h>

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#include <linux/ip.h>

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#include <linux/ip.h>

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#include <linux/delay.h>

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#include <linux/delay.h>

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#include <linux/crc32.h>

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#include <linux/crc32.h>

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#include <linux/dma-mapping.h>

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#include <linux/dma-mapping.h>

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#include <linux/mii.h>

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#include <linux/mii.h>

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#include <asm/irq.h>

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#include <asm/irq.h>

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#include "skge.h"

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#include "skge.h"

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#define DRV_NAME "skge"

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#define DRV_NAME "skge"

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#define DRV_VERSION "1.3"

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#define DRV_VERSION "1.3"

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#define PFX DRV_NAME " "

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#define PFX DRV_NAME " "

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#define DEFAULT_TX_RING_SIZE 128

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#define DEFAULT_TX_RING_SIZE 128

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#define DEFAULT_RX_RING_SIZE 512

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#define DEFAULT_RX_RING_SIZE 512

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#define MAX_TX_RING_SIZE 1024

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#define MAX_TX_RING_SIZE 1024

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#define MAX_RX_RING_SIZE 4096

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#define MAX_RX_RING_SIZE 4096

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#define RX_COPY_THRESHOLD 128

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#define RX_COPY_THRESHOLD 128

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#define RX_BUF_SIZE 1536

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#define RX_BUF_SIZE 1536

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#define PHY_RETRIES 1000

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#define PHY_RETRIES 1000

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#define ETH_JUMBO_MTU 9000

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#define ETH_JUMBO_MTU 9000

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#define TX_WATCHDOG (5 * HZ)

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#define TX_WATCHDOG (5 * HZ)

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#define NAPI_WEIGHT 64

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#define NAPI_WEIGHT 64

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#define BLINK_MS 250

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#define BLINK_MS 250

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MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");

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MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");

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MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");

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MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");

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MODULE_LICENSE("GPL");

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MODULE_LICENSE("GPL");

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MODULE_VERSION(DRV_VERSION);

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MODULE_VERSION(DRV_VERSION);

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static const u32 default_msg

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static const u32 default_msg

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= NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK

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= NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK

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| NETIF_MSG_IFUP| NETIF_MSG_IFDOWN;

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| NETIF_MSG_IFUP| NETIF_MSG_IFDOWN;

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static int debug = -1; /* defaults above */

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static int debug = -1; /* defaults above */

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module_param(debug, int, 0);

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module_param(debug, int, 0);

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MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");

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MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");

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static const struct pci_device_id skge_id_table[] = {

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static const struct pci_device_id skge_id_table[] = {

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{ PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },

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{ PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },

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{ PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },

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{ PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },

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{ PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },

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{ PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },

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{ PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },

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{ PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },

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{ PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T), },

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{ PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T), },

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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },

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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },

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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */

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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */

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{ PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },

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{ PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },

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{ PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },

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{ PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },

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{ PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015, },

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{ PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015, },

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{ 0 }

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{ 0 }

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};

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};

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MODULE_DEVICE_TABLE(pci, skge_id_table);

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MODULE_DEVICE_TABLE(pci, skge_id_table);

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static int skge_up(struct net_device *dev);

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static int skge_up(struct net_device *dev);

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static int skge_down(struct net_device *dev);

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static int skge_down(struct net_device *dev);

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static void skge_phy_reset(struct skge_port *skge);

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static void skge_phy_reset(struct skge_port *skge);

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static void skge_tx_clean(struct skge_port *skge);

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static void skge_tx_clean(struct skge_port *skge);

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static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);

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static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);

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static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);

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static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);

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static void genesis_get_stats(struct skge_port *skge, u64 *data);

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static void genesis_get_stats(struct skge_port *skge, u64 *data);

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static void yukon_get_stats(struct skge_port *skge, u64 *data);

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static void yukon_get_stats(struct skge_port *skge, u64 *data);

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static void yukon_init(struct skge_hw *hw, int port);

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static void yukon_init(struct skge_hw *hw, int port);

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static void genesis_mac_init(struct skge_hw *hw, int port);

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static void genesis_mac_init(struct skge_hw *hw, int port);

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static void genesis_link_up(struct skge_port *skge);

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static void genesis_link_up(struct skge_port *skge);

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/* Avoid conditionals by using array */

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/* Avoid conditionals by using array */

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static const int txqaddr[] = { Q_XA1, Q_XA2 };

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static const int txqaddr[] = { Q_XA1, Q_XA2 };

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static const int rxqaddr[] = { Q_R1, Q_R2 };

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static const int rxqaddr[] = { Q_R1, Q_R2 };

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static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };

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static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };

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static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };

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static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };

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static int skge_get_regs_len(struct net_device *dev)

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static int skge_get_regs_len(struct net_device *dev)

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{

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{

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return 0x4000;

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return 0x4000;

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}

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}

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/*

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/*

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* Returns copy of whole control register region

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* Returns copy of whole control register region

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* Note: skip RAM address register because accessing it will

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* Note: skip RAM address register because accessing it will

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* cause bus hangs!

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* cause bus hangs!

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*/

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*/

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static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,

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static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,

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void *p)

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void *p)

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{

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{

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const struct skge_port *skge = netdev_priv(dev);

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const struct skge_port *skge = netdev_priv(dev);

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const void __iomem *io = skge->hw->regs;

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const void __iomem *io = skge->hw->regs;

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regs->version = 1;

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regs->version = 1;

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memset(p, 0, regs->len);

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memset(p, 0, regs->len);

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memcpy_fromio(p, io, B3_RAM_ADDR);

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memcpy_fromio(p, io, B3_RAM_ADDR);

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memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,

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memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,

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regs->len - B3_RI_WTO_R1);

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regs->len - B3_RI_WTO_R1);

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}

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}

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/* Wake on Lan only supported on Yukon chips with rev 1 or above */

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/* Wake on Lan only supported on Yukon chips with rev 1 or above */

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static int wol_supported(const struct skge_hw *hw)

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static int wol_supported(const struct skge_hw *hw)

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{

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{

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return !((hw->chip_id == CHIP_ID_GENESIS ||

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return !((hw->chip_id == CHIP_ID_GENESIS ||

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(hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)));

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(hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)));

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}

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}

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static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)

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static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)

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{

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{

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struct skge_port *skge = netdev_priv(dev);

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struct skge_port *skge = netdev_priv(dev);

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143

wol->supported = wol_supported(skge->hw) ? WAKE_MAGIC : 0;

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wol->supported = wol_supported(skge->hw) ? WAKE_MAGIC : 0;

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wol->wolopts = skge->wol ? WAKE_MAGIC : 0;

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wol->wolopts = skge->wol ? WAKE_MAGIC : 0;

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}

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}

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static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)

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static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)

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{

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{

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struct skge_port *skge = netdev_priv(dev);

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struct skge_port *skge = netdev_priv(dev);

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struct skge_hw *hw = skge->hw;

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struct skge_hw *hw = skge->hw;

151

152

if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)

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if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)

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return -EOPNOTSUPP;

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return -EOPNOTSUPP;

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155

if (wol->wolopts == WAKE_MAGIC && !wol_supported(hw))

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if (wol->wolopts == WAKE_MAGIC && !wol_supported(hw))

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return -EOPNOTSUPP;

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return -EOPNOTSUPP;

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158

skge->wol = wol->wolopts == WAKE_MAGIC;

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skge->wol = wol->wolopts == WAKE_MAGIC;

159

160

if (skge->wol) {

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if (skge->wol) {

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memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);

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memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);

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skge_write16(hw, WOL_CTRL_STAT,

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skge_write16(hw, WOL_CTRL_STAT,

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WOL_CTL_ENA_PME_ON_MAGIC_PKT |

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WOL_CTL_ENA_PME_ON_MAGIC_PKT |

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WOL_CTL_ENA_MAGIC_PKT_UNIT);

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WOL_CTL_ENA_MAGIC_PKT_UNIT);

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} else

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} else

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skge_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);

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skge_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);

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return 0;

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return 0;

170

}

170

}

171

172

/* Determine supported/advertised modes based on hardware.

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/* Determine supported/advertised modes based on hardware.

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* Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx

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* Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx

174

*/

174

*/

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static u32 skge_supported_modes(const struct skge_hw *hw)

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static u32 skge_supported_modes(const struct skge_hw *hw)

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{

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{

177

u32 supported;

177

u32 supported;

178

179

if (hw->copper) {

179

if (hw->copper) {

180

supported = SUPPORTED_10baseT_Half

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supported = SUPPORTED_10baseT_Half

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| SUPPORTED_10baseT_Full

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| SUPPORTED_10baseT_Full

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| SUPPORTED_100baseT_Half

182

| SUPPORTED_100baseT_Half

183

| SUPPORTED_100baseT_Full

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| SUPPORTED_100baseT_Full

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| SUPPORTED_1000baseT_Half

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| SUPPORTED_1000baseT_Half

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| SUPPORTED_1000baseT_Full

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| SUPPORTED_1000baseT_Full

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| SUPPORTED_Autoneg| SUPPORTED_TP;

186

| SUPPORTED_Autoneg| SUPPORTED_TP;

187

188

if (hw->chip_id == CHIP_ID_GENESIS)

188

if (hw->chip_id == CHIP_ID_GENESIS)

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supported &= ~(SUPPORTED_10baseT_Half

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supported &= ~(SUPPORTED_10baseT_Half

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| SUPPORTED_10baseT_Full

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| SUPPORTED_10baseT_Full

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| SUPPORTED_100baseT_Half

191

| SUPPORTED_100baseT_Half

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| SUPPORTED_100baseT_Full);

192

| SUPPORTED_100baseT_Full);

193

194

else if (hw->chip_id == CHIP_ID_YUKON)

194

else if (hw->chip_id == CHIP_ID_YUKON)

195

supported &= ~SUPPORTED_1000baseT_Half;

195

supported &= ~SUPPORTED_1000baseT_Half;

196

} else

196

} else

197

supported = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE

197

supported = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE

198

| SUPPORTED_Autoneg;

198

| SUPPORTED_Autoneg;

199

200

return supported;

200

return supported;

201

}

201

}

202

203

static int skge_get_settings(struct net_device *dev,

203

static int skge_get_settings(struct net_device *dev,

204

struct ethtool_cmd *ecmd)

204

struct ethtool_cmd *ecmd)

205

{

205

{

206

struct skge_port *skge = netdev_priv(dev);

206

struct skge_port *skge = netdev_priv(dev);

207

struct skge_hw *hw = skge->hw;

207

struct skge_hw *hw = skge->hw;

208

209

ecmd->transceiver = XCVR_INTERNAL;

209

ecmd->transceiver = XCVR_INTERNAL;

210

ecmd->supported = skge_supported_modes(hw);

210

ecmd->supported = skge_supported_modes(hw);

211

212

if (hw->copper) {

212

if (hw->copper) {

213

ecmd->port = PORT_TP;

213

ecmd->port = PORT_TP;

214

ecmd->phy_address = hw->phy_addr;

214

ecmd->phy_address = hw->phy_addr;

215

} else

215

} else

216

ecmd->port = PORT_FIBRE;

216

ecmd->port = PORT_FIBRE;

217

218

ecmd->advertising = skge->advertising;

218

ecmd->advertising = skge->advertising;

219

ecmd->autoneg = skge->autoneg;

219

ecmd->autoneg = skge->autoneg;

220

ecmd->speed = skge->speed;

220

ecmd->speed = skge->speed;

221

ecmd->duplex = skge->duplex;

221

ecmd->duplex = skge->duplex;

222

return 0;

222

return 0;

223

}

223

}

224

225

static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)

225

static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)

226

{

226

{

227

struct skge_port *skge = netdev_priv(dev);

227

struct skge_port *skge = netdev_priv(dev);

228

const struct skge_hw *hw = skge->hw;

228

const struct skge_hw *hw = skge->hw;

229

u32 supported = skge_supported_modes(hw);

229

u32 supported = skge_supported_modes(hw);

230

231

if (ecmd->autoneg == AUTONEG_ENABLE) {

231

if (ecmd->autoneg == AUTONEG_ENABLE) {

232

ecmd->advertising = supported;

232

ecmd->advertising = supported;

233

skge->duplex = -1;

233

skge->duplex = -1;

234

skge->speed = -1;

234

skge->speed = -1;

235

} else {

235

} else {

236

u32 setting;

236

u32 setting;

237

238

switch (ecmd->speed) {

238

switch (ecmd->speed) {

239

case SPEED_1000:

239

case SPEED_1000:

240

if (ecmd->duplex == DUPLEX_FULL)

240

if (ecmd->duplex == DUPLEX_FULL)

241

setting = SUPPORTED_1000baseT_Full;

241

setting = SUPPORTED_1000baseT_Full;

242

else if (ecmd->duplex == DUPLEX_HALF)

242

else if (ecmd->duplex == DUPLEX_HALF)

243

setting = SUPPORTED_1000baseT_Half;

243

setting = SUPPORTED_1000baseT_Half;

244

else

244

else

245

return -EINVAL;

245

return -EINVAL;

246

break;

246

break;

247

case SPEED_100:

247

case SPEED_100:

248

if (ecmd->duplex == DUPLEX_FULL)

248

if (ecmd->duplex == DUPLEX_FULL)

249

setting = SUPPORTED_100baseT_Full;

249

setting = SUPPORTED_100baseT_Full;

250

else if (ecmd->duplex == DUPLEX_HALF)

250

else if (ecmd->duplex == DUPLEX_HALF)

251

setting = SUPPORTED_100baseT_Half;

251

setting = SUPPORTED_100baseT_Half;

252

else

252

else

253

return -EINVAL;

253

return -EINVAL;

254

break;

254

break;

255

256

case SPEED_10:

256

case SPEED_10:

257

if (ecmd->duplex == DUPLEX_FULL)

257

if (ecmd->duplex == DUPLEX_FULL)

258

setting = SUPPORTED_10baseT_Full;

258

setting = SUPPORTED_10baseT_Full;

259

else if (ecmd->duplex == DUPLEX_HALF)

259

else if (ecmd->duplex == DUPLEX_HALF)

260

setting = SUPPORTED_10baseT_Half;

260

setting = SUPPORTED_10baseT_Half;

261

else

261

else

262

return -EINVAL;

262

return -EINVAL;

263

break;

263

break;

264

default:

264

default:

265

return -EINVAL;

265

return -EINVAL;

266

}

266

}

267

268

if ((setting & supported) == 0)

268

if ((setting & supported) == 0)

269

return -EINVAL;

269

return -EINVAL;

270

271

skge->speed = ecmd->speed;

271

skge->speed = ecmd->speed;

272

skge->duplex = ecmd->duplex;

272

skge->duplex = ecmd->duplex;

273

}

273

}

274

275

skge->autoneg = ecmd->autoneg;

275

skge->autoneg = ecmd->autoneg;

276

skge->advertising = ecmd->advertising;

276

skge->advertising = ecmd->advertising;

277

278

if (netif_running(dev))

278

if (netif_running(dev))

279

skge_phy_reset(skge);

279

skge_phy_reset(skge);

280

281

return (0);

281

return (0);

282

}

282

}

283

284

static void skge_get_drvinfo(struct net_device *dev,

284

static void skge_get_drvinfo(struct net_device *dev,

285

struct ethtool_drvinfo *info)

285

struct ethtool_drvinfo *info)

286

{

286

{

287

struct skge_port *skge = netdev_priv(dev);

287

struct skge_port *skge = netdev_priv(dev);

288

289

strcpy(info->driver, DRV_NAME);

289

strcpy(info->driver, DRV_NAME);

290

strcpy(info->version, DRV_VERSION);

290

strcpy(info->version, DRV_VERSION);

291

strcpy(info->fw_version, "N/A");

291

strcpy(info->fw_version, "N/A");

292

strcpy(info->bus_info, pci_name(skge->hw->pdev));

292

strcpy(info->bus_info, pci_name(skge->hw->pdev));

293

}

293

}

294

295

static const struct skge_stat {

295

static const struct skge_stat {

296

char name[ETH_GSTRING_LEN];

296

char name[ETH_GSTRING_LEN];

297

u16 xmac_offset;

297

u16 xmac_offset;

298

u16 gma_offset;

298

u16 gma_offset;

299

} skge_stats[] = {

299

} skge_stats[] = {

300

{ "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },

300

{ "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },

301

{ "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },

301

{ "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },

302

303

{ "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },

303

{ "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },

304

{ "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },

304

{ "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },

305

{ "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },

305

{ "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },

306

{ "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },

306

{ "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },

307

{ "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },

307

{ "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },

308

{ "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },

308

{ "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },

309

{ "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },

309

{ "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },

310

{ "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },

310

{ "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },

311

312

{ "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },

312

{ "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },

313

{ "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },

313

{ "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },

314

{ "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },

314

{ "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },

315

{ "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },

315

{ "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },

316

{ "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },

316

{ "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },

317

{ "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },

317

{ "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },

318

319

{ "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },

319

{ "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },

320

{ "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },

320

{ "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },

321

{ "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },

321

{ "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },

322

{ "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },

322

{ "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },

323

{ "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },

323

{ "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },

324

};

324

};

325

326

static int skge_get_stats_count(struct net_device *dev)

326

static int skge_get_stats_count(struct net_device *dev)

327

{

327

{

328

return ARRAY_SIZE(skge_stats);

328

return ARRAY_SIZE(skge_stats);

329

}

329

}

330

331

static void skge_get_ethtool_stats(struct net_device *dev,

331

static void skge_get_ethtool_stats(struct net_device *dev,

332

struct ethtool_stats *stats, u64 *data)

332

struct ethtool_stats *stats, u64 *data)

333

{

333

{

334

struct skge_port *skge = netdev_priv(dev);

334

struct skge_port *skge = netdev_priv(dev);

335

336

if (skge->hw->chip_id == CHIP_ID_GENESIS)

336

if (skge->hw->chip_id == CHIP_ID_GENESIS)

337

genesis_get_stats(skge, data);

337

genesis_get_stats(skge, data);

338

else

338

else

339

yukon_get_stats(skge, data);

339

yukon_get_stats(skge, data);

340

}

340

}

341

342

/* Use hardware MIB variables for critical path statistics and

342

/* Use hardware MIB variables for critical path statistics and

343

* transmit feedback not reported at interrupt.

343

* transmit feedback not reported at interrupt.

344

* Other errors are accounted for in interrupt handler.

344

* Other errors are accounted for in interrupt handler.

345

*/

345

*/

346

static struct net_device_stats *skge_get_stats(struct net_device *dev)

346

static struct net_device_stats *skge_get_stats(struct net_device *dev)

347

{

347

{

348

struct skge_port *skge = netdev_priv(dev);

348

struct skge_port *skge = netdev_priv(dev);

349

u64 data[ARRAY_SIZE(skge_stats)];

349

u64 data[ARRAY_SIZE(skge_stats)];

350

351

if (skge->hw->chip_id == CHIP_ID_GENESIS)

351

if (skge->hw->chip_id == CHIP_ID_GENESIS)

352

genesis_get_stats(skge, data);

352

genesis_get_stats(skge, data);

353

else

353

else

354

yukon_get_stats(skge, data);

354

yukon_get_stats(skge, data);

355

356

skge->net_stats.tx_bytes = data[0];

356

skge->net_stats.tx_bytes = data[0];

357

skge->net_stats.rx_bytes = data[1];

357

skge->net_stats.rx_bytes = data[1];

358

skge->net_stats.tx_packets = data[2] + data[4] + data[6];

358

skge->net_stats.tx_packets = data[2] + data[4] + data[6];

359

skge->net_stats.rx_packets = data[3] + data[5] + data[7];

359

skge->net_stats.rx_packets = data[3] + data[5] + data[7];

360

skge->net_stats.multicast = data[5] + data[7];

360

skge->net_stats.multicast = data[5] + data[7];

361

skge->net_stats.collisions = data[10];

361

skge->net_stats.collisions = data[10];

362

skge->net_stats.tx_aborted_errors = data[12];

362

skge->net_stats.tx_aborted_errors = data[12];

363

364

return &skge->net_stats;

364

return &skge->net_stats;

365

}

365

}

366

367

static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)

367

static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)

368

{

368

{

369

int i;

369

int i;

370

371

switch (stringset) {

371

switch (stringset) {

372

case ETH_SS_STATS:

372

case ETH_SS_STATS:

373

for (i = 0; i < ARRAY_SIZE(skge_stats); i++)

373

for (i = 0; i < ARRAY_SIZE(skge_stats); i++)

374

memcpy(data + i * ETH_GSTRING_LEN,

374

memcpy(data + i * ETH_GSTRING_LEN,

375

skge_stats[i].name, ETH_GSTRING_LEN);

375

skge_stats[i].name, ETH_GSTRING_LEN);

376

break;

376

break;

377

}

377

}

378

}

378

}

379

380

static void skge_get_ring_param(struct net_device *dev,

380

static void skge_get_ring_param(struct net_device *dev,

381

struct ethtool_ringparam *p)

381

struct ethtool_ringparam *p)

382

{

382

{

383

struct skge_port *skge = netdev_priv(dev);

383

struct skge_port *skge = netdev_priv(dev);

384

385

p->rx_max_pending = MAX_RX_RING_SIZE;

385

p->rx_max_pending = MAX_RX_RING_SIZE;

386

p->tx_max_pending = MAX_TX_RING_SIZE;

386

p->tx_max_pending = MAX_TX_RING_SIZE;

387

p->rx_mini_max_pending = 0;

387

p->rx_mini_max_pending = 0;

388

p->rx_jumbo_max_pending = 0;

388

p->rx_jumbo_max_pending = 0;

389

390

p->rx_pending = skge->rx_ring.count;

390

p->rx_pending = skge->rx_ring.count;

391

p->tx_pending = skge->tx_ring.count;

391

p->tx_pending = skge->tx_ring.count;

392

p->rx_mini_pending = 0;

392

p->rx_mini_pending = 0;

393

p->rx_jumbo_pending = 0;

393

p->rx_jumbo_pending = 0;

394

}

394

}

395

396

static int skge_set_ring_param(struct net_device *dev,

396

static int skge_set_ring_param(struct net_device *dev,

397

struct ethtool_ringparam *p)

397

struct ethtool_ringparam *p)

398

{

398

{

399

struct skge_port *skge = netdev_priv(dev);

399

struct skge_port *skge = netdev_priv(dev);

400

int err;

400

int err;

401

402

if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||

402

if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||

403

p->tx_pending == 0 || p->tx_pending > MAX_TX_RING_SIZE)

403

p->tx_pending == 0 || p->tx_pending > MAX_TX_RING_SIZE)

404

return -EINVAL;

404

return -EINVAL;

405

406

skge->rx_ring.count = p->rx_pending;

406

skge->rx_ring.count = p->rx_pending;

407

skge->tx_ring.count = p->tx_pending;

407

skge->tx_ring.count = p->tx_pending;

408

409

if (netif_running(dev)) {

409

if (netif_running(dev)) {

410

skge_down(dev);

410

skge_down(dev);

411

err = skge_up(dev);

411

err = skge_up(dev);

412

if (err)

412

if (err)

413

dev_close(dev);

413

dev_close(dev);

414

}

414

}

415

416

return 0;

416

return 0;

417

}

417

}

418

419

static u32 skge_get_msglevel(struct net_device *netdev)

419

static u32 skge_get_msglevel(struct net_device *netdev)

420

{

420

{

421

struct skge_port *skge = netdev_priv(netdev);

421

struct skge_port *skge = netdev_priv(netdev);

422

return skge->msg_enable;

422

return skge->msg_enable;

423

}

423

}

424

425

static void skge_set_msglevel(struct net_device *netdev, u32 value)

425

static void skge_set_msglevel(struct net_device *netdev, u32 value)

426

{

426

{

427

struct skge_port *skge = netdev_priv(netdev);

427

struct skge_port *skge = netdev_priv(netdev);

428

skge->msg_enable = value;

428

skge->msg_enable = value;

429

}

429

}

430

431

static int skge_nway_reset(struct net_device *dev)

431

static int skge_nway_reset(struct net_device *dev)

432

{

432

{

433

struct skge_port *skge = netdev_priv(dev);

433

struct skge_port *skge = netdev_priv(dev);

434

435

if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))

435

if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))

436

return -EINVAL;

436

return -EINVAL;

437

438

skge_phy_reset(skge);

438

skge_phy_reset(skge);

439

return 0;

439

return 0;

440

}

440

}

441

442

static int skge_set_sg(struct net_device *dev, u32 data)

442

static int skge_set_sg(struct net_device *dev, u32 data)

443

{

443

{

444

struct skge_port *skge = netdev_priv(dev);

444

struct skge_port *skge = netdev_priv(dev);

445

struct skge_hw *hw = skge->hw;

445

struct skge_hw *hw = skge->hw;

446

447

if (hw->chip_id == CHIP_ID_GENESIS && data)

447

if (hw->chip_id == CHIP_ID_GENESIS && data)

448

return -EOPNOTSUPP;

448

return -EOPNOTSUPP;

449

return ethtool_op_set_sg(dev, data);

449

return ethtool_op_set_sg(dev, data);

450

}

450

}

451

452

static int skge_set_tx_csum(struct net_device *dev, u32 data)

452

static int skge_set_tx_csum(struct net_device *dev, u32 data)

453

{

453

{

454

struct skge_port *skge = netdev_priv(dev);

454

struct skge_port *skge = netdev_priv(dev);

455

struct skge_hw *hw = skge->hw;

455

struct skge_hw *hw = skge->hw;

456

457

if (hw->chip_id == CHIP_ID_GENESIS && data)

457

if (hw->chip_id == CHIP_ID_GENESIS && data)

458

return -EOPNOTSUPP;

458

return -EOPNOTSUPP;

459

460

return ethtool_op_set_tx_csum(dev, data);

460

return ethtool_op_set_tx_csum(dev, data);

461

}

461

}

462

463

static u32 skge_get_rx_csum(struct net_device *dev)

463

static u32 skge_get_rx_csum(struct net_device *dev)

464

{

464

{

465

struct skge_port *skge = netdev_priv(dev);

465

struct skge_port *skge = netdev_priv(dev);

466

467

return skge->rx_csum;

467

return skge->rx_csum;

468

}

468

}

469

470

/* Only Yukon supports checksum offload. */

470

/* Only Yukon supports checksum offload. */

471

static int skge_set_rx_csum(struct net_device *dev, u32 data)

471

static int skge_set_rx_csum(struct net_device *dev, u32 data)

472

{

472

{

473

struct skge_port *skge = netdev_priv(dev);

473

struct skge_port *skge = netdev_priv(dev);

474

475

if (skge->hw->chip_id == CHIP_ID_GENESIS && data)

475

if (skge->hw->chip_id == CHIP_ID_GENESIS && data)

476

return -EOPNOTSUPP;

476

return -EOPNOTSUPP;

477

478

skge->rx_csum = data;

478

skge->rx_csum = data;

479

return 0;

479

return 0;

480

}

480

}

481

482

static void skge_get_pauseparam(struct net_device *dev,

482

static void skge_get_pauseparam(struct net_device *dev,

483

struct ethtool_pauseparam *ecmd)

483

struct ethtool_pauseparam *ecmd)

484

{

484

{

485

struct skge_port *skge = netdev_priv(dev);

485

struct skge_port *skge = netdev_priv(dev);

486

487

ecmd->tx_pause = (skge->flow_control == FLOW_MODE_LOC_SEND)

487

ecmd->tx_pause = (skge->flow_control == FLOW_MODE_LOC_SEND)

488

|| (skge->flow_control == FLOW_MODE_SYMMETRIC);

488

|| (skge->flow_control == FLOW_MODE_SYMMETRIC);

489

ecmd->rx_pause = (skge->flow_control == FLOW_MODE_REM_SEND)

489

ecmd->rx_pause = (skge->flow_control == FLOW_MODE_REM_SEND)

490

|| (skge->flow_control == FLOW_MODE_SYMMETRIC);

490

|| (skge->flow_control == FLOW_MODE_SYMMETRIC);

491

492

ecmd->autoneg = skge->autoneg;

492

ecmd->autoneg = skge->autoneg;

493

}

493

}

494

495

static int skge_set_pauseparam(struct net_device *dev,

495

static int skge_set_pauseparam(struct net_device *dev,

496

struct ethtool_pauseparam *ecmd)

496

struct ethtool_pauseparam *ecmd)

497

{

497

{

498

struct skge_port *skge = netdev_priv(dev);

498

struct skge_port *skge = netdev_priv(dev);

499

500

skge->autoneg = ecmd->autoneg;

500

skge->autoneg = ecmd->autoneg;

501

if (ecmd->rx_pause && ecmd->tx_pause)

501

if (ecmd->rx_pause && ecmd->tx_pause)

502

skge->flow_control = FLOW_MODE_SYMMETRIC;

502

skge->flow_control = FLOW_MODE_SYMMETRIC;

503

else if (ecmd->rx_pause && !ecmd->tx_pause)

503

else if (ecmd->rx_pause && !ecmd->tx_pause)

504

skge->flow_control = FLOW_MODE_REM_SEND;

504

skge->flow_control = FLOW_MODE_REM_SEND;

505

else if (!ecmd->rx_pause && ecmd->tx_pause)

505

else if (!ecmd->rx_pause && ecmd->tx_pause)

506

skge->flow_control = FLOW_MODE_LOC_SEND;

506

skge->flow_control = FLOW_MODE_LOC_SEND;

507

else

507

else

508

skge->flow_control = FLOW_MODE_NONE;

508

skge->flow_control = FLOW_MODE_NONE;

509

510

if (netif_running(dev))

510

if (netif_running(dev))

511

skge_phy_reset(skge);

511

skge_phy_reset(skge);

512

return 0;

512

return 0;

513

}

513

}

514

515

/* Chip internal frequency for clock calculations */

515

/* Chip internal frequency for clock calculations */

516

static inline u32 hwkhz(const struct skge_hw *hw)

516

static inline u32 hwkhz(const struct skge_hw *hw)

517

{

517

{

518

if (hw->chip_id == CHIP_ID_GENESIS)

518

if (hw->chip_id == CHIP_ID_GENESIS)

519

return 53215; /* or: 53.125 MHz */

519

return 53215; /* or: 53.125 MHz */

520

else

520

else

521

return 78215; /* or: 78.125 MHz */

521

return 78215; /* or: 78.125 MHz */

522

}

522

}

523

524

/* Chip HZ to microseconds */

524

/* Chip HZ to microseconds */

525

static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)

525

static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)

526

{

526

{

527

return (ticks * 1000) / hwkhz(hw);

527

return (ticks * 1000) / hwkhz(hw);

528

}

528

}

529

530

/* Microseconds to chip HZ */

530

/* Microseconds to chip HZ */

531

static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)

531

static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)

532

{

532

{

533

return hwkhz(hw) * usec / 1000;

533

return hwkhz(hw) * usec / 1000;

534

}

534

}

535

536

static int skge_get_coalesce(struct net_device *dev,

536

static int skge_get_coalesce(struct net_device *dev,

537

struct ethtool_coalesce *ecmd)

537

struct ethtool_coalesce *ecmd)

538

{

538

{

539

struct skge_port *skge = netdev_priv(dev);

539

struct skge_port *skge = netdev_priv(dev);

540

struct skge_hw *hw = skge->hw;

540

struct skge_hw *hw = skge->hw;

541

int port = skge->port;

541

int port = skge->port;

542

543

ecmd->rx_coalesce_usecs = 0;

543

ecmd->rx_coalesce_usecs = 0;

544

ecmd->tx_coalesce_usecs = 0;

544

ecmd->tx_coalesce_usecs = 0;

545

546

if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {

546

if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {

547

u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));

547

u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));

548

u32 msk = skge_read32(hw, B2_IRQM_MSK);

548

u32 msk = skge_read32(hw, B2_IRQM_MSK);

549

550

if (msk & rxirqmask[port])

550

if (msk & rxirqmask[port])

551

ecmd->rx_coalesce_usecs = delay;

551

ecmd->rx_coalesce_usecs = delay;

552

if (msk & txirqmask[port])

552

if (msk & txirqmask[port])

553

ecmd->tx_coalesce_usecs = delay;

553

ecmd->tx_coalesce_usecs = delay;

554

}

554

}

555

556

return 0;

556

return 0;

557

}

557

}

558

559

/* Note: interrupt timer is per board, but can turn on/off per port */

559

/* Note: interrupt timer is per board, but can turn on/off per port */

560

static int skge_set_coalesce(struct net_device *dev,

560

static int skge_set_coalesce(struct net_device *dev,

561

struct ethtool_coalesce *ecmd)

561

struct ethtool_coalesce *ecmd)

562

{

562

{

563

struct skge_port *skge = netdev_priv(dev);

563

struct skge_port *skge = netdev_priv(dev);

564

struct skge_hw *hw = skge->hw;

564

struct skge_hw *hw = skge->hw;

565

int port = skge->port;

565

int port = skge->port;

566

u32 msk = skge_read32(hw, B2_IRQM_MSK);

566

u32 msk = skge_read32(hw, B2_IRQM_MSK);

567

u32 delay = 25;

567

u32 delay = 25;

568

569

if (ecmd->rx_coalesce_usecs == 0)

569

if (ecmd->rx_coalesce_usecs == 0)

570

msk &= ~rxirqmask[port];

570

msk &= ~rxirqmask[port];

571

else if (ecmd->rx_coalesce_usecs < 25 ||

571

else if (ecmd->rx_coalesce_usecs < 25 ||

572

ecmd->rx_coalesce_usecs > 33333)

572

ecmd->rx_coalesce_usecs > 33333)

573

return -EINVAL;

573

return -EINVAL;

574

else {

574

else {

575

msk |= rxirqmask[port];

575

msk |= rxirqmask[port];

576

delay = ecmd->rx_coalesce_usecs;

576

delay = ecmd->rx_coalesce_usecs;

577

}

577

}

578

579

if (ecmd->tx_coalesce_usecs == 0)

579

if (ecmd->tx_coalesce_usecs == 0)

580

msk &= ~txirqmask[port];

580

msk &= ~txirqmask[port];

581

else if (ecmd->tx_coalesce_usecs < 25 ||

581

else if (ecmd->tx_coalesce_usecs < 25 ||

582

ecmd->tx_coalesce_usecs > 33333)

582

ecmd->tx_coalesce_usecs > 33333)

583

return -EINVAL;

583

return -EINVAL;

584

else {

584

else {

585

msk |= txirqmask[port];

585

msk |= txirqmask[port];

586

delay = min(delay, ecmd->rx_coalesce_usecs);

586

delay = min(delay, ecmd->rx_coalesce_usecs);

587

}

587

}

588

589

skge_write32(hw, B2_IRQM_MSK, msk);

589

skge_write32(hw, B2_IRQM_MSK, msk);

590

if (msk == 0)

590

if (msk == 0)

591

skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);

591

skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);

592

else {

592

else {

593

skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));

593

skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));

594

skge_write32(hw, B2_IRQM_CTRL, TIM_START);

594

skge_write32(hw, B2_IRQM_CTRL, TIM_START);

595

}

595

}

596

return 0;

596

return 0;

597

}

597

}

598

599

enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };

599

enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };

600

static void skge_led(struct skge_port *skge, enum led_mode mode)

600

static void skge_led(struct skge_port *skge, enum led_mode mode)

601

{

601

{

602

struct skge_hw *hw = skge->hw;

602

struct skge_hw *hw = skge->hw;

603

int port = skge->port;

603

int port = skge->port;

604

605

spin_lock_bh(&hw->phy_lock);

605

spin_lock_bh(&hw->phy_lock);

606

if (hw->chip_id == CHIP_ID_GENESIS) {

606

if (hw->chip_id == CHIP_ID_GENESIS) {

607

switch (mode) {

607

switch (mode) {

608

case LED_MODE_OFF:

608

case LED_MODE_OFF:

609

xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);

609

xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);

610

skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);

610

skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);

611

skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);

611

skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);

612

skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);

612

skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);

613

break;

613

break;

614

615

case LED_MODE_ON:

615

case LED_MODE_ON:

616

skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);

616

skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);

617

skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);

617

skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);

618

619

skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);

619

skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);

620

skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);

620

skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);

621

622

break;

622

break;

623

624

case LED_MODE_TST:

624

case LED_MODE_TST:

625

skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);

625

skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);

626

skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);

626

skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);

627

skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);

627

skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);

628

629

xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);

629

xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);

630

break;

630

break;

631

}

631

}

632

} else {

632

} else {

633

switch (mode) {

633

switch (mode) {

634

case LED_MODE_OFF:

634

case LED_MODE_OFF:

635

gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);

635

gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);

636

gm_phy_write(hw, port, PHY_MARV_LED_OVER,

636

gm_phy_write(hw, port, PHY_MARV_LED_OVER,

637

PHY_M_LED_MO_DUP(MO_LED_OFF) |

637

PHY_M_LED_MO_DUP(MO_LED_OFF) |

638

PHY_M_LED_MO_10(MO_LED_OFF) |

638

PHY_M_LED_MO_10(MO_LED_OFF) |

639

PHY_M_LED_MO_100(MO_LED_OFF) |

639

PHY_M_LED_MO_100(MO_LED_OFF) |

640

PHY_M_LED_MO_1000(MO_LED_OFF) |

640

PHY_M_LED_MO_1000(MO_LED_OFF) |

641

PHY_M_LED_MO_RX(MO_LED_OFF));

641

PHY_M_LED_MO_RX(MO_LED_OFF));

642

break;

642

break;

643

case LED_MODE_ON:

643

case LED_MODE_ON:

644

gm_phy_write(hw, port, PHY_MARV_LED_CTRL,

644

gm_phy_write(hw, port, PHY_MARV_LED_CTRL,

645

PHY_M_LED_PULS_DUR(PULS_170MS) |

645

PHY_M_LED_PULS_DUR(PULS_170MS) |

646

PHY_M_LED_BLINK_RT(BLINK_84MS) |

646

PHY_M_LED_BLINK_RT(BLINK_84MS) |

647

PHY_M_LEDC_TX_CTRL |

647

PHY_M_LEDC_TX_CTRL |

648

PHY_M_LEDC_DP_CTRL);

648

PHY_M_LEDC_DP_CTRL);

649

650

gm_phy_write(hw, port, PHY_MARV_LED_OVER,

650

gm_phy_write(hw, port, PHY_MARV_LED_OVER,

651

PHY_M_LED_MO_RX(MO_LED_OFF) |

651

PHY_M_LED_MO_RX(MO_LED_OFF) |

652

(skge->speed == SPEED_100 ?

652

(skge->speed == SPEED_100 ?

653

PHY_M_LED_MO_100(MO_LED_ON) : 0));

653

PHY_M_LED_MO_100(MO_LED_ON) : 0));

654

break;

654

break;

655

case LED_MODE_TST:

655

case LED_MODE_TST:

656

gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);

656

gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);

657

gm_phy_write(hw, port, PHY_MARV_LED_OVER,

657

gm_phy_write(hw, port, PHY_MARV_LED_OVER,

658

PHY_M_LED_MO_DUP(MO_LED_ON) |

658

PHY_M_LED_MO_DUP(MO_LED_ON) |

659

PHY_M_LED_MO_10(MO_LED_ON) |

659

PHY_M_LED_MO_10(MO_LED_ON) |

660

PHY_M_LED_MO_100(MO_LED_ON) |

660

PHY_M_LED_MO_100(MO_LED_ON) |

661

PHY_M_LED_MO_1000(MO_LED_ON) |

661

PHY_M_LED_MO_1000(MO_LED_ON) |

662

PHY_M_LED_MO_RX(MO_LED_ON));

662

PHY_M_LED_MO_RX(MO_LED_ON));

663

}

663

}

664

}

664

}

665

spin_unlock_bh(&hw->phy_lock);

665

spin_unlock_bh(&hw->phy_lock);

666

}

666

}

667

668

/* blink LED's for finding board */

668

/* blink LED's for finding board */

669

static int skge_phys_id(struct net_device *dev, u32 data)

669

static int skge_phys_id(struct net_device *dev, u32 data)

670

{

670

{

671

struct skge_port *skge = netdev_priv(dev);

671

struct skge_port *skge = netdev_priv(dev);

672

unsigned long ms;

672

unsigned long ms;

673

enum led_mode mode = LED_MODE_TST;

673

enum led_mode mode = LED_MODE_TST;

674

675

if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))

675

if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))

676

ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT / HZ) * 1000;

676

ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT / HZ) * 1000;

677

else

677

else

678

ms = data * 1000;

678

ms = data * 1000;

679

680

while (ms > 0) {

680

while (ms > 0) {

681

skge_led(skge, mode);

681

skge_led(skge, mode);

682

mode ^= LED_MODE_TST;

682

mode ^= LED_MODE_TST;

683

684

if (msleep_interruptible(BLINK_MS))

684

if (msleep_interruptible(BLINK_MS))

685

break;

685

break;

686

ms -= BLINK_MS;

686

ms -= BLINK_MS;

687

}

687

}

688

689

/* back to regular LED state */

689

/* back to regular LED state */

690

skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);

690

skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);

691

692

return 0;

692

return 0;

693

}

693

}

694

695

static struct ethtool_ops skge_ethtool_ops = {

695

static struct ethtool_ops skge_ethtool_ops = {

696

.get_settings = skge_get_settings,

696

.get_settings = skge_get_settings,

697

.set_settings = skge_set_settings,

697

.set_settings = skge_set_settings,

698

.get_drvinfo = skge_get_drvinfo,

698

.get_drvinfo = skge_get_drvinfo,

699

.get_regs_len = skge_get_regs_len,

699

.get_regs_len = skge_get_regs_len,

700

.get_regs = skge_get_regs,

700

.get_regs = skge_get_regs,

701

.get_wol = skge_get_wol,

701

.get_wol = skge_get_wol,

702

.set_wol = skge_set_wol,

702

.set_wol = skge_set_wol,

703

.get_msglevel = skge_get_msglevel,

703

.get_msglevel = skge_get_msglevel,

704

.set_msglevel = skge_set_msglevel,

704

.set_msglevel = skge_set_msglevel,

705

.nway_reset = skge_nway_reset,

705

.nway_reset = skge_nway_reset,

706

.get_link = ethtool_op_get_link,

706

.get_link = ethtool_op_get_link,

707

.get_ringparam = skge_get_ring_param,

707

.get_ringparam = skge_get_ring_param,

708

.set_ringparam = skge_set_ring_param,

708

.set_ringparam = skge_set_ring_param,

709

.get_pauseparam = skge_get_pauseparam,

709

.get_pauseparam = skge_get_pauseparam,

710

.set_pauseparam = skge_set_pauseparam,

710

.set_pauseparam = skge_set_pauseparam,

711

.get_coalesce = skge_get_coalesce,

711

.get_coalesce = skge_get_coalesce,

712

.set_coalesce = skge_set_coalesce,

712

.set_coalesce = skge_set_coalesce,

713

.get_sg = ethtool_op_get_sg,

713

.get_sg = ethtool_op_get_sg,

714

.set_sg = skge_set_sg,

714

.set_sg = skge_set_sg,

715

.get_tx_csum = ethtool_op_get_tx_csum,

715

.get_tx_csum = ethtool_op_get_tx_csum,

716

.set_tx_csum = skge_set_tx_csum,

716

.set_tx_csum = skge_set_tx_csum,

717

.get_rx_csum = skge_get_rx_csum,

717

.get_rx_csum = skge_get_rx_csum,

718

.set_rx_csum = skge_set_rx_csum,

718

.set_rx_csum = skge_set_rx_csum,

719

.get_strings = skge_get_strings,

719

.get_strings = skge_get_strings,

720

.phys_id = skge_phys_id,

720

.phys_id = skge_phys_id,

721

.get_stats_count = skge_get_stats_count,

721

.get_stats_count = skge_get_stats_count,

722

.get_ethtool_stats = skge_get_ethtool_stats,

722

.get_ethtool_stats = skge_get_ethtool_stats,

723

.get_perm_addr = ethtool_op_get_perm_addr,

723

.get_perm_addr = ethtool_op_get_perm_addr,

724

};

724

};

725

726

/*

726

/*

727

* Allocate ring elements and chain them together

727

* Allocate ring elements and chain them together

728

* One-to-one association of board descriptors with ring elements

728

* One-to-one association of board descriptors with ring elements

729

*/

729

*/

730

static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base)

730

static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base)

731

{

731

{

732

struct skge_tx_desc *d;

732

struct skge_tx_desc *d;

733

struct skge_element *e;

733

struct skge_element *e;

734

int i;

734

int i;

735

736

ring->start = kcalloc(sizeof(*e), ring->count, GFP_KERNEL);

736

ring->start = kcalloc(sizeof(*e), ring->count, GFP_KERNEL);

737

if (!ring->start)

737

if (!ring->start)

738

return -ENOMEM;

738

return -ENOMEM;

739

740

for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {

740

for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {

741

e->desc = d;

741

e->desc = d;

742

if (i == ring->count - 1) {

742

if (i == ring->count - 1) {

743

e->next = ring->start;

743

e->next = ring->start;

744

d->next_offset = base;

744

d->next_offset = base;

745

} else {

745

} else {

746

e->next = e + 1;

746

e->next = e + 1;

747

d->next_offset = base + (i+1) * sizeof(*d);

747

d->next_offset = base + (i+1) * sizeof(*d);

748

}

748

}

749

}

749

}

750

ring->to_use = ring->to_clean = ring->start;

750

ring->to_use = ring->to_clean = ring->start;

751

752

return 0;

752

return 0;

753

}

753

}

754

755

/* Allocate and setup a new buffer for receiving */

755

/* Allocate and setup a new buffer for receiving */

756

static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,

756

static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,

757

struct sk_buff *skb, unsigned int bufsize)

757

struct sk_buff *skb, unsigned int bufsize)

758

{

758

{

759

struct skge_rx_desc *rd = e->desc;

759

struct skge_rx_desc *rd = e->desc;

760

u64 map;

760

u64 map;

761

762

map = pci_map_single(skge->hw->pdev, skb->data, bufsize,

762

map = pci_map_single(skge->hw->pdev, skb->data, bufsize,

763

PCI_DMA_FROMDEVICE);

763

PCI_DMA_FROMDEVICE);

764

765

rd->dma_lo = map;

765

rd->dma_lo = map;

766

rd->dma_hi = map >> 32;

766

rd->dma_hi = map >> 32;

767

e->skb = skb;

767

e->skb = skb;

768

rd->csum1_start = ETH_HLEN;

768

rd->csum1_start = ETH_HLEN;

769

rd->csum2_start = ETH_HLEN;

769

rd->csum2_start = ETH_HLEN;

770

rd->csum1 = 0;

770

rd->csum1 = 0;

771

rd->csum2 = 0;

771

rd->csum2 = 0;

772

773

wmb();

773

wmb();

774

775

rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;

775

rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;

776

pci_unmap_addr_set(e, mapaddr, map);

776

pci_unmap_addr_set(e, mapaddr, map);

777

pci_unmap_len_set(e, maplen, bufsize);

777

pci_unmap_len_set(e, maplen, bufsize);

778

}

778

}

779

780

/* Resume receiving using existing skb,

780

/* Resume receiving using existing skb,

781

* Note: DMA address is not changed by chip.

781

* Note: DMA address is not changed by chip.

782

* MTU not changed while receiver active.

782

* MTU not changed while receiver active.

783

*/

783

*/

784

static void skge_rx_reuse(struct skge_element *e, unsigned int size)

784

static void skge_rx_reuse(struct skge_element *e, unsigned int size)

785

{

785

{

786

struct skge_rx_desc *rd = e->desc;

786

struct skge_rx_desc *rd = e->desc;

787

788

rd->csum2 = 0;

788

rd->csum2 = 0;

789

rd->csum2_start = ETH_HLEN;

789

rd->csum2_start = ETH_HLEN;

790

791

wmb();

791

wmb();

792

793

rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;

793

rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;

794

}

794

}

795

796

797

/* Free all buffers in receive ring, assumes receiver stopped */

797

/* Free all buffers in receive ring, assumes receiver stopped */

798

static void skge_rx_clean(struct skge_port *skge)

798

static void skge_rx_clean(struct skge_port *skge)

799

{

799

{

800

struct skge_hw *hw = skge->hw;

800

struct skge_hw *hw = skge->hw;

801

struct skge_ring *ring = &skge->rx_ring;

801

struct skge_ring *ring = &skge->rx_ring;

802

struct skge_element *e;

802

struct skge_element *e;

803

804

e = ring->start;

804

e = ring->start;

805

do {

805

do {

806

struct skge_rx_desc *rd = e->desc;

806

struct skge_rx_desc *rd = e->desc;

807

rd->control = 0;

807

rd->control = 0;

808

if (e->skb) {

808

if (e->skb) {

809

pci_unmap_single(hw->pdev,

809

pci_unmap_single(hw->pdev,

810

pci_unmap_addr(e, mapaddr),

810

pci_unmap_addr(e, mapaddr),

811

pci_unmap_len(e, maplen),

811

pci_unmap_len(e, maplen),

812

PCI_DMA_FROMDEVICE);

812

PCI_DMA_FROMDEVICE);

813

dev_kfree_skb(e->skb);

813

dev_kfree_skb(e->skb);

814

e->skb = NULL;

814

e->skb = NULL;

815

}

815

}

816

} while ((e = e->next) != ring->start);

816

} while ((e = e->next) != ring->start);

817

}

817

}

818

819

820

/* Allocate buffers for receive ring

820

/* Allocate buffers for receive ring

821

* For receive: to_clean is next received frame.

821

* For receive: to_clean is next received frame.

822

*/

822

*/

823

static int skge_rx_fill(struct skge_port *skge)

823

static int skge_rx_fill(struct skge_port *skge)

824

{

824

{

825

struct skge_ring *ring = &skge->rx_ring;

825

struct skge_ring *ring = &skge->rx_ring;

826

struct skge_element *e;

826

struct skge_element *e;

827

828

e = ring->start;

828

e = ring->start;

829

do {

829

do {

830

struct sk_buff *skb;

830

struct sk_buff *skb;

831

832

skb = dev_alloc_skb(skge->rx_buf_size + NET_IP_ALIGN);

832

skb = dev_alloc_skb(skge->rx_buf_size + NET_IP_ALIGN);

833

if (!skb)

833

if (!skb)

834

return -ENOMEM;

834

return -ENOMEM;

835

836

skb_reserve(skb, NET_IP_ALIGN);

836

skb_reserve(skb, NET_IP_ALIGN);

837

skge_rx_setup(skge, e, skb, skge->rx_buf_size);

837

skge_rx_setup(skge, e, skb, skge->rx_buf_size);

838

} while ( (e = e->next) != ring->start);

838

} while ( (e = e->next) != ring->start);

839

840

ring->to_clean = ring->start;

840

ring->to_clean = ring->start;

841

return 0;

841

return 0;

842

}

842

}

843

844

static void skge_link_up(struct skge_port *skge)

844

static void skge_link_up(struct skge_port *skge)

845

{

845

{

846

skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),

846

skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),

847

LED_BLK_OFF|LED_SYNC_OFF|LED_ON);

847

LED_BLK_OFF|LED_SYNC_OFF|LED_ON);

848

849

netif_carrier_on(skge->netdev);

849

netif_carrier_on(skge->netdev);

850

if (skge->tx_avail > MAX_SKB_FRAGS + 1)

850

if (skge->tx_avail > MAX_SKB_FRAGS + 1)

851

netif_wake_queue(skge->netdev);

851

netif_wake_queue(skge->netdev);

852

853

if (netif_msg_link(skge))

853

if (netif_msg_link(skge))

854

printk(KERN_INFO PFX

854

printk(KERN_INFO PFX

855

"%s: Link is up at %d Mbps, %s duplex, flow control %s\n",

855

"%s: Link is up at %d Mbps, %s duplex, flow control %s\n",

856

skge->netdev->name, skge->speed,

856

skge->netdev->name, skge->speed,

857

skge->duplex == DUPLEX_FULL ? "full" : "half",

857

skge->duplex == DUPLEX_FULL ? "full" : "half",

858

(skge->flow_control == FLOW_MODE_NONE) ? "none" :

858

(skge->flow_control == FLOW_MODE_NONE) ? "none" :

859

(skge->flow_control == FLOW_MODE_LOC_SEND) ? "tx only" :

859

(skge->flow_control == FLOW_MODE_LOC_SEND) ? "tx only" :

860

(skge->flow_control == FLOW_MODE_REM_SEND) ? "rx only" :

860

(skge->flow_control == FLOW_MODE_REM_SEND) ? "rx only" :

861

(skge->flow_control == FLOW_MODE_SYMMETRIC) ? "tx and rx" :

861

(skge->flow_control == FLOW_MODE_SYMMETRIC) ? "tx and rx" :

862

"unknown");

862

"unknown");

863

}

863

}

864

865

static void skge_link_down(struct skge_port *skge)

865

static void skge_link_down(struct skge_port *skge)

866

{

866

{

867

skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);

867

skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);

868

netif_carrier_off(skge->netdev);

868

netif_carrier_off(skge->netdev);

869

netif_stop_queue(skge->netdev);

869

netif_stop_queue(skge->netdev);

870

871

if (netif_msg_link(skge))

871

if (netif_msg_link(skge))

872

printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);

872

printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);

873

}

873

}

874

875

static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)

875

static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)

876

{

876

{

877

int i;

877

int i;

878

879

xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);

879

xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);

880

*val = xm_read16(hw, port, XM_PHY_DATA);

880

*val = xm_read16(hw, port, XM_PHY_DATA);

881

882

for (i = 0; i < PHY_RETRIES; i++) {

882

for (i = 0; i < PHY_RETRIES; i++) {

883

if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)

883

if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)

884

goto ready;

884

goto ready;

885

udelay(1);

885

udelay(1);

886

}

886

}

887

888

return -ETIMEDOUT;

888

return -ETIMEDOUT;

889

ready:

889

ready:

890

*val = xm_read16(hw, port, XM_PHY_DATA);

890

*val = xm_read16(hw, port, XM_PHY_DATA);

891

892

return 0;

892

return 0;

893

}

893

}

894

895

static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)

895

static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)

896

{

896

{

897

u16 v = 0;

897

u16 v = 0;

898

if (__xm_phy_read(hw, port, reg, &v))

898

if (__xm_phy_read(hw, port, reg, &v))

899

printk(KERN_WARNING PFX "%s: phy read timed out\n",

899

printk(KERN_WARNING PFX "%s: phy read timed out\n",

900

hw->dev[port]->name);

900

hw->dev[port]->name);

901

return v;

901

return v;

902

}

902

}

903

904

static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)

904

static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)

905

{

905

{

906

int i;

906

int i;

907

908

xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);

908

xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);

909

for (i = 0; i < PHY_RETRIES; i++) {

909

for (i = 0; i < PHY_RETRIES; i++) {

910

if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))

910

if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))

911

goto ready;

911

goto ready;

912

udelay(1);

912

udelay(1);

913

}

913

}

914

return -EIO;

914

return -EIO;

915

916

ready:

916

ready:

917

xm_write16(hw, port, XM_PHY_DATA, val);

917

xm_write16(hw, port, XM_PHY_DATA, val);

918

for (i = 0; i < PHY_RETRIES; i++) {

918

for (i = 0; i < PHY_RETRIES; i++) {

919

if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))

919

if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))

920

return 0;

920

return 0;

921

udelay(1);

921

udelay(1);

922

}

922

}

923

return -ETIMEDOUT;

923

return -ETIMEDOUT;

924

}

924

}

925

926

static void genesis_init(struct skge_hw *hw)

926

static void genesis_init(struct skge_hw *hw)

927

{

927

{

928

/* set blink source counter */

928

/* set blink source counter */

929

skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);

929

skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);

930

skge_write8(hw, B2_BSC_CTRL, BSC_START);

930

skge_write8(hw, B2_BSC_CTRL, BSC_START);

931

932

/* configure mac arbiter */

932

/* configure mac arbiter */

933

skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);

933

skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);

934

935

/* configure mac arbiter timeout values */

935

/* configure mac arbiter timeout values */

936

skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);

936

skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);

937

skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);

937

skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);

938

skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);

938

skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);

939

skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);

939

skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);

940

941

skge_write8(hw, B3_MA_RCINI_RX1, 0);

941

skge_write8(hw, B3_MA_RCINI_RX1, 0);

942

skge_write8(hw, B3_MA_RCINI_RX2, 0);

942

skge_write8(hw, B3_MA_RCINI_RX2, 0);

943

skge_write8(hw, B3_MA_RCINI_TX1, 0);

943

skge_write8(hw, B3_MA_RCINI_TX1, 0);

944

skge_write8(hw, B3_MA_RCINI_TX2, 0);

944

skge_write8(hw, B3_MA_RCINI_TX2, 0);

945

946

/* configure packet arbiter timeout */

946

/* configure packet arbiter timeout */

947

skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);

947

skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);

948

skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);

948

skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);

949

skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);

949

skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);

950

skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);

950

skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);

951

skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);

951

skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);

952

}

952

}

953

954

static void genesis_reset(struct skge_hw *hw, int port)

954

static void genesis_reset(struct skge_hw *hw, int port)

955

{

955

{

956

const u8 zero[8] = { 0 };

956

const u8 zero[8] = { 0 };

957

958

skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);

958

skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);

959

960

/* reset the statistics module */

960

/* reset the statistics module */

961

xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);

961

xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);

962

xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */

962

xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */

963

xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */

963

xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */

964

xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */

964

xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */

965

xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */

965

xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */

966

967

/* disable Broadcom PHY IRQ */

967

/* disable Broadcom PHY IRQ */

968

xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);

968

xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);

969

970

xm_outhash(hw, port, XM_HSM, zero);

970

xm_outhash(hw, port, XM_HSM, zero);

971

}

971

}

972

973

974

/* Convert mode to MII values */

974

/* Convert mode to MII values */

975

static const u16 phy_pause_map[] = {

975

static const u16 phy_pause_map[] = {

976

[FLOW_MODE_NONE] = 0,

976

[FLOW_MODE_NONE] = 0,

977

[FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,

977

[FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,

978

[FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,

978

[FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,

979

[FLOW_MODE_REM_SEND] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,

979

[FLOW_MODE_REM_SEND] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,

980

};

980

};

981

982

983

/* Check status of Broadcom phy link */

983

/* Check status of Broadcom phy link */

984

static void bcom_check_link(struct skge_hw *hw, int port)

984

static void bcom_check_link(struct skge_hw *hw, int port)

985

{

985

{

986

struct net_device *dev = hw->dev[port];

986

struct net_device *dev = hw->dev[port];

987

struct skge_port *skge = netdev_priv(dev);

987

struct skge_port *skge = netdev_priv(dev);

988

u16 status;

988

u16 status;

989

990

/* read twice because of latch */

990

/* read twice because of latch */

991

(void) xm_phy_read(hw, port, PHY_BCOM_STAT);

991

(void) xm_phy_read(hw, port, PHY_BCOM_STAT);

992

status = xm_phy_read(hw, port, PHY_BCOM_STAT);

992

status = xm_phy_read(hw, port, PHY_BCOM_STAT);

993

994

if ((status & PHY_ST_LSYNC) == 0) {

994

if ((status & PHY_ST_LSYNC) == 0) {

995

u16 cmd = xm_read16(hw, port, XM_MMU_CMD);

995

u16 cmd = xm_read16(hw, port, XM_MMU_CMD);

996

cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);

996

cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);

997

xm_write16(hw, port, XM_MMU_CMD, cmd);

997

xm_write16(hw, port, XM_MMU_CMD, cmd);

998

/* dummy read to ensure writing */

998

/* dummy read to ensure writing */

999

(void) xm_read16(hw, port, XM_MMU_CMD);

999

(void) xm_read16(hw, port, XM_MMU_CMD);

1000

1001

if (netif_carrier_ok(dev))

1001

if (netif_carrier_ok(dev))

1002

skge_link_down(skge);

1002

skge_link_down(skge);

1003

} else {

1003

} else {

1004

if (skge->autoneg == AUTONEG_ENABLE &&

1004

if (skge->autoneg == AUTONEG_ENABLE &&

1005

(status & PHY_ST_AN_OVER)) {

1005

(status & PHY_ST_AN_OVER)) {

1006

u16 lpa = xm_phy_read(hw, port, PHY_BCOM_AUNE_LP);

1006

u16 lpa = xm_phy_read(hw, port, PHY_BCOM_AUNE_LP);

1007

u16 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);

1007

u16 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);

1008

1009

if (lpa & PHY_B_AN_RF) {

1009

if (lpa & PHY_B_AN_RF) {

1010

printk(KERN_NOTICE PFX "%s: remote fault\n",

1010

printk(KERN_NOTICE PFX "%s: remote fault\n",

1011

dev->name);

1011

dev->name);

1012

return;

1012

return;

1013

}

1013

}

1014

1015

/* Check Duplex mismatch */

1015

/* Check Duplex mismatch */

1016

switch (aux & PHY_B_AS_AN_RES_MSK) {

1016

switch (aux & PHY_B_AS_AN_RES_MSK) {

1017

case PHY_B_RES_1000FD:

1017

case PHY_B_RES_1000FD:

1018

skge->duplex = DUPLEX_FULL;

1018

skge->duplex = DUPLEX_FULL;

1019

break;

1019

break;

1020

case PHY_B_RES_1000HD:

1020

case PHY_B_RES_1000HD:

1021

skge->duplex = DUPLEX_HALF;

1021

skge->duplex = DUPLEX_HALF;

1022

break;

1022

break;

1023

default:

1023

default:

1024

printk(KERN_NOTICE PFX "%s: duplex mismatch\n",

1024

printk(KERN_NOTICE PFX "%s: duplex mismatch\n",

1025

dev->name);

1025

dev->name);

1026

return;

1026

return;

1027

}

1027

}

1028

1029

1030

/* We are using IEEE 802.3z/D5.0 Table 37-4 */

1030

/* We are using IEEE 802.3z/D5.0 Table 37-4 */

1031

switch (aux & PHY_B_AS_PAUSE_MSK) {

1031

switch (aux & PHY_B_AS_PAUSE_MSK) {

1032

case PHY_B_AS_PAUSE_MSK:

1032

case PHY_B_AS_PAUSE_MSK:

1033

skge->flow_control = FLOW_MODE_SYMMETRIC;

1033

skge->flow_control = FLOW_MODE_SYMMETRIC;

1034

break;

1034

break;

1035

case PHY_B_AS_PRR:

1035

case PHY_B_AS_PRR:

1036

skge->flow_control = FLOW_MODE_REM_SEND;

1036

skge->flow_control = FLOW_MODE_REM_SEND;

1037

break;

1037

break;

1038

case PHY_B_AS_PRT:

1038

case PHY_B_AS_PRT:

1039

skge->flow_control = FLOW_MODE_LOC_SEND;

1039

skge->flow_control = FLOW_MODE_LOC_SEND;

1040

break;

1040

break;

1041

default:

1041

default:

1042

skge->flow_control = FLOW_MODE_NONE;

1042

skge->flow_control = FLOW_MODE_NONE;

1043

}

1043

}

1044

1045

skge->speed = SPEED_1000;

1045

skge->speed = SPEED_1000;

1046

}

1046

}

1047

1048

if (!netif_carrier_ok(dev))

1048

if (!netif_carrier_ok(dev))

1049

genesis_link_up(skge);

1049

genesis_link_up(skge);

1050

}

1050

}

1051

}

1051

}

1052

1053

/* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional

1053

/* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional

1054

* Phy on for 100 or 10Mbit operation

1054

* Phy on for 100 or 10Mbit operation

1055

*/

1055

*/

1056

static void bcom_phy_init(struct skge_port *skge, int jumbo)

1056

static void bcom_phy_init(struct skge_port *skge, int jumbo)

1057

{

1057

{

1058

struct skge_hw *hw = skge->hw;

1058

struct skge_hw *hw = skge->hw;

1059

int port = skge->port;

1059

int port = skge->port;

1060

int i;

1060

int i;

1061

u16 id1, r, ext, ctl;

1061

u16 id1, r, ext, ctl;

1062

1063

/* magic workaround patterns for Broadcom */

1063

/* magic workaround patterns for Broadcom */

1064

static const struct {

1064

static const struct {

1065

u16 reg;

1065

u16 reg;

1066

u16 val;

1066

u16 val;

1067

} A1hack[] = {

1067

} A1hack[] = {

1068

{ 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },

1068

{ 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },

1069

{ 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },

1069

{ 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },

1070

{ 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },

1070

{ 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },

1071

{ 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },

1071

{ 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },

1072

}, C0hack[] = {

1072

}, C0hack[] = {

1073

{ 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },

1073

{ 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },

1074

{ 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },

1074

{ 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },

1075

};

1075

};

1076

1077

/* read Id from external PHY (all have the same address) */

1077

/* read Id from external PHY (all have the same address) */

1078

id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);

1078

id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);

1079

1080

/* Optimize MDIO transfer by suppressing preamble. */

1080

/* Optimize MDIO transfer by suppressing preamble. */

1081

r = xm_read16(hw, port, XM_MMU_CMD);

1081

r = xm_read16(hw, port, XM_MMU_CMD);

1082

r |= XM_MMU_NO_PRE;

1082

r |= XM_MMU_NO_PRE;

1083

xm_write16(hw, port, XM_MMU_CMD,r);

1083

xm_write16(hw, port, XM_MMU_CMD,r);

1084

1085

switch (id1) {

1085

switch (id1) {

1086

case PHY_BCOM_ID1_C0:

1086

case PHY_BCOM_ID1_C0:

1087

/*

1087

/*

1088

* Workaround BCOM Errata for the C0 type.

1088

* Workaround BCOM Errata for the C0 type.

1089

* Write magic patterns to reserved registers.

1089

* Write magic patterns to reserved registers.

1090

*/

1090

*/

1091

for (i = 0; i < ARRAY_SIZE(C0hack); i++)

1091

for (i = 0; i < ARRAY_SIZE(C0hack); i++)

1092

xm_phy_write(hw, port,

1092

xm_phy_write(hw, port,

1093

C0hack[i].reg, C0hack[i].val);

1093

C0hack[i].reg, C0hack[i].val);

1094

1095

break;

1095

break;

1096

case PHY_BCOM_ID1_A1:

1096

case PHY_BCOM_ID1_A1:

1097

/*

1097

/*

1098

* Workaround BCOM Errata for the A1 type.

1098

* Workaround BCOM Errata for the A1 type.

1099

* Write magic patterns to reserved registers.

1099

* Write magic patterns to reserved registers.

1100

*/

1100

*/

1101

for (i = 0; i < ARRAY_SIZE(A1hack); i++)

1101

for (i = 0; i < ARRAY_SIZE(A1hack); i++)

1102

xm_phy_write(hw, port,

1102

xm_phy_write(hw, port,

1103

A1hack[i].reg, A1hack[i].val);

1103

A1hack[i].reg, A1hack[i].val);

1104

break;

1104

break;

1105

}

1105

}

1106

1107

/*

1107

/*

1108

* Workaround BCOM Errata (#10523) for all BCom PHYs.

1108

* Workaround BCOM Errata (#10523) for all BCom PHYs.

1109

* Disable Power Management after reset.

1109

* Disable Power Management after reset.

1110

*/

1110

*/

1111

r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);

1111

r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);

1112

r |= PHY_B_AC_DIS_PM;

1112

r |= PHY_B_AC_DIS_PM;

1113

xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);

1113

xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);

1114

1115

/* Dummy read */

1115

/* Dummy read */

1116

xm_read16(hw, port, XM_ISRC);

1116

xm_read16(hw, port, XM_ISRC);

1117

1118

ext = PHY_B_PEC_EN_LTR; /* enable tx led */

1118

ext = PHY_B_PEC_EN_LTR; /* enable tx led */

1119

ctl = PHY_CT_SP1000; /* always 1000mbit */

1119

ctl = PHY_CT_SP1000; /* always 1000mbit */

1120

1121

if (skge->autoneg == AUTONEG_ENABLE) {

1121

if (skge->autoneg == AUTONEG_ENABLE) {

1122

/*

1122

/*

1123

* Workaround BCOM Errata #1 for the C5 type.

1123

* Workaround BCOM Errata #1 for the C5 type.

1124

* 1000Base-T Link Acquisition Failure in Slave Mode

1124

* 1000Base-T Link Acquisition Failure in Slave Mode

1125

* Set Repeater/DTE bit 10 of the 1000Base-T Control Register

1125

* Set Repeater/DTE bit 10 of the 1000Base-T Control Register

1126

*/

1126

*/

1127

u16 adv = PHY_B_1000C_RD;

1127

u16 adv = PHY_B_1000C_RD;

1128

if (skge->advertising & ADVERTISED_1000baseT_Half)

1128

if (skge->advertising & ADVERTISED_1000baseT_Half)

1129

adv |= PHY_B_1000C_AHD;

1129

adv |= PHY_B_1000C_AHD;

1130

if (skge->advertising & ADVERTISED_1000baseT_Full)

1130

if (skge->advertising & ADVERTISED_1000baseT_Full)

1131

adv |= PHY_B_1000C_AFD;

1131

adv |= PHY_B_1000C_AFD;

1132

xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);

1132

xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);

1133

1134

ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;

1134

ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;

1135

} else {

1135

} else {

1136

if (skge->duplex == DUPLEX_FULL)

1136

if (skge->duplex == DUPLEX_FULL)

1137

ctl |= PHY_CT_DUP_MD;

1137

ctl |= PHY_CT_DUP_MD;

1138

/* Force to slave */

1138

/* Force to slave */

1139

xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);

1139

xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);

1140

}

1140

}

1141

1142

/* Set autonegotiation pause parameters */

1142

/* Set autonegotiation pause parameters */

1143

xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,

1143

xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,

1144

phy_pause_map[skge->flow_control] | PHY_AN_CSMA);

1144

phy_pause_map[skge->flow_control] | PHY_AN_CSMA);

1145

1146

/* Handle Jumbo frames */

1146

/* Handle Jumbo frames */

1147

if (jumbo) {

1147

if (jumbo) {

1148

xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,

1148

xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,

1149

PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);

1149

PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);

1150

1151

ext |= PHY_B_PEC_HIGH_LA;

1151

ext |= PHY_B_PEC_HIGH_LA;

1152

1153

}

1153

}

1154

1155

xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);

1155

xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);

1156

xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);

1156

xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);

1157

1158

/* Use link status change interrupt */

1158

/* Use link status change interrupt */

1159

xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);

1159

xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);

1160

1161

bcom_check_link(hw, port);

1161

bcom_check_link(hw, port);

1162

}

1162

}

1163

1164

static void genesis_mac_init(struct skge_hw *hw, int port)

1164

static void genesis_mac_init(struct skge_hw *hw, int port)

1165

{

1165

{

1166

struct net_device *dev = hw->dev[port];

1166

struct net_device *dev = hw->dev[port];

1167

struct skge_port *skge = netdev_priv(dev);

1167

struct skge_port *skge = netdev_priv(dev);

1168

int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;

1168

int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;

1169

int i;

1169

int i;

1170

u32 r;

1170

u32 r;

1171

const u8 zero[6] = { 0 };

1171

const u8 zero[6] = { 0 };

1172

1173

for (i = 0; i < 10; i++) {

1173

for (i = 0; i < 10; i++) {

1174

skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),

1174

skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),

1175

MFF_SET_MAC_RST);

1175

MFF_SET_MAC_RST);

1176

if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)

1176

if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)

1177

goto reset_ok;

1177

goto reset_ok;

1178

udelay(1);

1178

udelay(1);

1179

}

1179

}

1180

1181

printk(KERN_WARNING PFX "%s: genesis reset failed\n", dev->name);

1181

printk(KERN_WARNING PFX "%s: genesis reset failed\n", dev->name);

1182

1183

reset_ok:

1183

reset_ok:

1184

/* Unreset the XMAC. */

1184

/* Unreset the XMAC. */

1185

skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);

1185

skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);

1186

1187

/*

1187

/*

1188

* Perform additional initialization for external PHYs,

1188

* Perform additional initialization for external PHYs,

1189

* namely for the 1000baseTX cards that use the XMAC's

1189

* namely for the 1000baseTX cards that use the XMAC's

1190

* GMII mode.

1190

* GMII mode.

1191

*/

1191

*/

1192

/* Take external Phy out of reset */

1192

/* Take external Phy out of reset */

1193

r = skge_read32(hw, B2_GP_IO);

1193

r = skge_read32(hw, B2_GP_IO);

1194

if (port == 0)

1194

if (port == 0)

1195

r |= GP_DIR_0|GP_IO_0;

1195

r |= GP_DIR_0|GP_IO_0;

1196

else

1196

else

1197

r |= GP_DIR_2|GP_IO_2;

1197

r |= GP_DIR_2|GP_IO_2;

1198

1199

skge_write32(hw, B2_GP_IO, r);

1199

skge_write32(hw, B2_GP_IO, r);

1200

1201

1202

/* Enable GMII interface */

1202

/* Enable GMII interface */

1203

xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);

1203

xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);

1204

1205

bcom_phy_init(skge, jumbo);

1205

bcom_phy_init(skge, jumbo);

1206

1207

/* Set Station Address */

1207

/* Set Station Address */

1208

xm_outaddr(hw, port, XM_SA, dev->dev_addr);

1208

xm_outaddr(hw, port, XM_SA, dev->dev_addr);

1209

1210

/* We don't use match addresses so clear */

1210

/* We don't use match addresses so clear */

1211

for (i = 1; i < 16; i++)

1211

for (i = 1; i < 16; i++)

1212

xm_outaddr(hw, port, XM_EXM(i), zero);

1212

xm_outaddr(hw, port, XM_EXM(i), zero);

1213

1214

/* Clear MIB counters */

1214

/* Clear MIB counters */

1215

xm_write16(hw, port, XM_STAT_CMD,

1215

xm_write16(hw, port, XM_STAT_CMD,

1216

XM_SC_CLR_RXC | XM_SC_CLR_TXC);

1216

XM_SC_CLR_RXC | XM_SC_CLR_TXC);

1217

/* Clear two times according to Errata #3 */

1217

/* Clear two times according to Errata #3 */

1218

xm_write16(hw, port, XM_STAT_CMD,

1218

xm_write16(hw, port, XM_STAT_CMD,

1219

XM_SC_CLR_RXC | XM_SC_CLR_TXC);

1219

XM_SC_CLR_RXC | XM_SC_CLR_TXC);

1220

1221

/* configure Rx High Water Mark (XM_RX_HI_WM) */

1221

/* configure Rx High Water Mark (XM_RX_HI_WM) */

1222

xm_write16(hw, port, XM_RX_HI_WM, 1450);

1222

xm_write16(hw, port, XM_RX_HI_WM, 1450);

1223

1224

/* We don't need the FCS appended to the packet. */

1224

/* We don't need the FCS appended to the packet. */

1225

r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;

1225

r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;

1226

if (jumbo)

1226

if (jumbo)

1227

r |= XM_RX_BIG_PK_OK;

1227

r |= XM_RX_BIG_PK_OK;

1228

1229

if (skge->duplex == DUPLEX_HALF) {

1229

if (skge->duplex == DUPLEX_HALF) {

1230

/*

1230

/*

1231

* If in manual half duplex mode the other side might be in

1231

* If in manual half duplex mode the other side might be in

1232

* full duplex mode, so ignore if a carrier extension is not seen

1232

* full duplex mode, so ignore if a carrier extension is not seen

1233

* on frames received

1233

* on frames received

1234

*/

1234

*/

1235

r |= XM_RX_DIS_CEXT;

1235

r |= XM_RX_DIS_CEXT;

1236

}

1236

}

1237

xm_write16(hw, port, XM_RX_CMD, r);

1237

xm_write16(hw, port, XM_RX_CMD, r);

1238

1239

1240

/* We want short frames padded to 60 bytes. */

1240

/* We want short frames padded to 60 bytes. */

1241

xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);

1241

xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);

1242

1243

/*

1243

/*

1244

* Bump up the transmit threshold. This helps hold off transmit

1244

* Bump up the transmit threshold. This helps hold off transmit

1245

* underruns when we're blasting traffic from both ports at once.

1245

* underruns when we're blasting traffic from both ports at once.

1246

*/

1246

*/

1247

xm_write16(hw, port, XM_TX_THR, 512);

1247

xm_write16(hw, port, XM_TX_THR, 512);

1248

1249

/*

1249

/*

1250

* Enable the reception of all error frames. This is is

1250

* Enable the reception of all error frames. This is is

1251

* a necessary evil due to the design of the XMAC. The

1251

* a necessary evil due to the design of the XMAC. The

1252

* XMAC's receive FIFO is only 8K in size, however jumbo

1252

* XMAC's receive FIFO is only 8K in size, however jumbo

1253

* frames can be up to 9000 bytes in length. When bad

1253

* frames can be up to 9000 bytes in length. When bad

1254

* frame filtering is enabled, the XMAC's RX FIFO operates

1254

* frame filtering is enabled, the XMAC's RX FIFO operates

1255

* in 'store and forward' mode. For this to work, the

1255

* in 'store and forward' mode. For this to work, the

1256

* entire frame has to fit into the FIFO, but that means

1256

* entire frame has to fit into the FIFO, but that means

1257

* that jumbo frames larger than 8192 bytes will be

1257

* that jumbo frames larger than 8192 bytes will be

1258

* truncated. Disabling all bad frame filtering causes

1258

* truncated. Disabling all bad frame filtering causes

1259

* the RX FIFO to operate in streaming mode, in which

1259

* the RX FIFO to operate in streaming mode, in which

1260

* case the XMAC will start transferring frames out of the

1260

* case the XMAC will start transferring frames out of the

1261

* RX FIFO as soon as the FIFO threshold is reached.

1261

* RX FIFO as soon as the FIFO threshold is reached.

1262

*/

1262

*/

1263

xm_write32(hw, port, XM_MODE, XM_DEF_MODE);

1263

xm_write32(hw, port, XM_MODE, XM_DEF_MODE);

1264

1265

1266

/*

1266

/*

1267

* Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)

1267

* Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)

1268

* - Enable all bits excepting 'Octets Rx OK Low CntOv'

1268

* - Enable all bits excepting 'Octets Rx OK Low CntOv'

1269

* and 'Octets Rx OK Hi Cnt Ov'.

1269

* and 'Octets Rx OK Hi Cnt Ov'.

1270

*/

1270

*/

1271

xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);

1271

xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);

1272

1273

/*

1273

/*

1274

* Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)

1274

* Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)

1275

* - Enable all bits excepting 'Octets Tx OK Low CntOv'

1275

* - Enable all bits excepting 'Octets Tx OK Low CntOv'

1276

* and 'Octets Tx OK Hi Cnt Ov'.

1276

* and 'Octets Tx OK Hi Cnt Ov'.

1277

*/

1277

*/

1278

xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);

1278

xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);

1279

1280

/* Configure MAC arbiter */

1280

/* Configure MAC arbiter */

1281

skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);

1281

skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);

1282

1283

/* configure timeout values */

1283

/* configure timeout values */

1284

skge_write8(hw, B3_MA_TOINI_RX1, 72);

1284

skge_write8(hw, B3_MA_TOINI_RX1, 72);

1285

skge_write8(hw, B3_MA_TOINI_RX2, 72);

1285

skge_write8(hw, B3_MA_TOINI_RX2, 72);

1286

skge_write8(hw, B3_MA_TOINI_TX1, 72);

1286

skge_write8(hw, B3_MA_TOINI_TX1, 72);

1287

skge_write8(hw, B3_MA_TOINI_TX2, 72);

1287

skge_write8(hw, B3_MA_TOINI_TX2, 72);

1288

1289

skge_write8(hw, B3_MA_RCINI_RX1, 0);

1289

skge_write8(hw, B3_MA_RCINI_RX1, 0);

1290

skge_write8(hw, B3_MA_RCINI_RX2, 0);

1290

skge_write8(hw, B3_MA_RCINI_RX2, 0);

1291

skge_write8(hw, B3_MA_RCINI_TX1, 0);

1291

skge_write8(hw, B3_MA_RCINI_TX1, 0);

1292

skge_write8(hw, B3_MA_RCINI_TX2, 0);

1292

skge_write8(hw, B3_MA_RCINI_TX2, 0);

1293

1294

/* Configure Rx MAC FIFO */

1294

/* Configure Rx MAC FIFO */

1295

skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);

1295

skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);

1296

skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);

1296

skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);

1297

skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);

1297

skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);

1298

1299

/* Configure Tx MAC FIFO */

1299

/* Configure Tx MAC FIFO */

1300

skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);

1300

skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);

1301

skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);

1301

skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);

1302

skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);

1302

skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);

1303

1304

if (jumbo) {

1304

if (jumbo) {

1305

/* Enable frame flushing if jumbo frames used */

1305

/* Enable frame flushing if jumbo frames used */

1306

skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);

1306

skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);

1307

} else {

1307

} else {

1308

/* enable timeout timers if normal frames */

1308

/* enable timeout timers if normal frames */

1309

skge_write16(hw, B3_PA_CTRL,

1309

skge_write16(hw, B3_PA_CTRL,

1310

(port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);

1310

(port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);

1311

}

1311

}

1312

}

1312

}

1313

1314

static void genesis_stop(struct skge_port *skge)

1314

static void genesis_stop(struct skge_port *skge)

1315

{

1315

{

1316

struct skge_hw *hw = skge->hw;

1316

struct skge_hw *hw = skge->hw;

1317

int port = skge->port;

1317

int port = skge->port;

1318

u32 reg;

1318

u32 reg;

1319

1320

genesis_reset(hw, port);

1320

genesis_reset(hw, port);

1321

1322

/* Clear Tx packet arbiter timeout IRQ */

1322

/* Clear Tx packet arbiter timeout IRQ */

1323

skge_write16(hw, B3_PA_CTRL,

1323

skge_write16(hw, B3_PA_CTRL,

1324

port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);

1324

port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);

1325

1326

/*

1326

/*

1327

* If the transfer sticks at the MAC the STOP command will not

1327

* If the transfer sticks at the MAC the STOP command will not

1328

* terminate if we don't flush the XMAC's transmit FIFO !

1328

* terminate if we don't flush the XMAC's transmit FIFO !

1329

*/

1329

*/

1330

xm_write32(hw, port, XM_MODE,

1330

xm_write32(hw, port, XM_MODE,

1331

xm_read32(hw, port, XM_MODE)|XM_MD_FTF);

1331

xm_read32(hw, port, XM_MODE)|XM_MD_FTF);

1332

1333

1334

/* Reset the MAC */

1334

/* Reset the MAC */

1335

skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);

1335

skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);

1336

1337

/* For external PHYs there must be special handling */

1337

/* For external PHYs there must be special handling */

1338

reg = skge_read32(hw, B2_GP_IO);

1338

reg = skge_read32(hw, B2_GP_IO);

1339

if (port == 0) {

1339

if (port == 0) {

1340

reg |= GP_DIR_0;

1340

reg |= GP_DIR_0;

1341

reg &= ~GP_IO_0;

1341

reg &= ~GP_IO_0;

1342

} else {

1342

} else {

1343

reg |= GP_DIR_2;

1343

reg |= GP_DIR_2;

1344

reg &= ~GP_IO_2;

1344

reg &= ~GP_IO_2;

1345

}

1345

}

1346

skge_write32(hw, B2_GP_IO, reg);

1346

skge_write32(hw, B2_GP_IO, reg);

1347

skge_read32(hw, B2_GP_IO);

1347

skge_read32(hw, B2_GP_IO);

1348

1349

xm_write16(hw, port, XM_MMU_CMD,

1349

xm_write16(hw, port, XM_MMU_CMD,

1350

xm_read16(hw, port, XM_MMU_CMD)

1350

xm_read16(hw, port, XM_MMU_CMD)

1351

& ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));

1351

& ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));

1352

1353

xm_read16(hw, port, XM_MMU_CMD);

1353

xm_read16(hw, port, XM_MMU_CMD);

1354

}

1354

}

1355

1356

1357

static void genesis_get_stats(struct skge_port *skge, u64 *data)

1357

static void genesis_get_stats(struct skge_port *skge, u64 *data)

1358

{

1358

{

1359

struct skge_hw *hw = skge->hw;

1359

struct skge_hw *hw = skge->hw;

1360

int port = skge->port;

1360

int port = skge->port;

1361

int i;

1361

int i;

1362

unsigned long timeout = jiffies + HZ;

1362

unsigned long timeout = jiffies + HZ;

1363

1364

xm_write16(hw, port,

1364

xm_write16(hw, port,

1365

XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);

1365

XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);

1366

1367

/* wait for update to complete */

1367

/* wait for update to complete */

1368

while (xm_read16(hw, port, XM_STAT_CMD)

1368

while (xm_read16(hw, port, XM_STAT_CMD)

1369

& (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {

1369

& (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {

1370

if (time_after(jiffies, timeout))

1370

if (time_after(jiffies, timeout))

1371

break;

1371

break;

1372

udelay(10);

1372

udelay(10);

1373

}

1373

}

1374

1375

/* special case for 64 bit octet counter */

1375

/* special case for 64 bit octet counter */

1376

data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32

1376

data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32

1377

| xm_read32(hw, port, XM_TXO_OK_LO);

1377

| xm_read32(hw, port, XM_TXO_OK_LO);

1378

data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32

1378

data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32

1379

| xm_read32(hw, port, XM_RXO_OK_LO);

1379

| xm_read32(hw, port, XM_RXO_OK_LO);

1380

1381

for (i = 2; i < ARRAY_SIZE(skge_stats); i++)

1381

for (i = 2; i < ARRAY_SIZE(skge_stats); i++)

1382

data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);

1382

data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);

1383

}

1383

}

1384

1385

static void genesis_mac_intr(struct skge_hw *hw, int port)

1385

static void genesis_mac_intr(struct skge_hw *hw, int port)

1386

{

1386

{

1387

struct skge_port *skge = netdev_priv(hw->dev[port]);

1387

struct skge_port *skge = netdev_priv(hw->dev[port]);

1388

u16 status = xm_read16(hw, port, XM_ISRC);

1388

u16 status = xm_read16(hw, port, XM_ISRC);

1389

1390

if (netif_msg_intr(skge))

1390

if (netif_msg_intr(skge))

1391

printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",

1391

printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",

1392

skge->netdev->name, status);

1392

skge->netdev->name, status);

1393

1394

if (status & XM_IS_TXF_UR) {

1394

if (status & XM_IS_TXF_UR) {

1395

xm_write32(hw, port, XM_MODE, XM_MD_FTF);

1395

xm_write32(hw, port, XM_MODE, XM_MD_FTF);

1396

++skge->net_stats.tx_fifo_errors;

1396

++skge->net_stats.tx_fifo_errors;

1397

}

1397

}

1398

if (status & XM_IS_RXF_OV) {

1398

if (status & XM_IS_RXF_OV) {

1399

xm_write32(hw, port, XM_MODE, XM_MD_FRF);

1399

xm_write32(hw, port, XM_MODE, XM_MD_FRF);

1400

++skge->net_stats.rx_fifo_errors;

1400

++skge->net_stats.rx_fifo_errors;

1401

}

1401

}

1402

}

1402

}

1403

1404

static void genesis_link_up(struct skge_port *skge)

1404

static void genesis_link_up(struct skge_port *skge)

1405

{

1405

{

1406

struct skge_hw *hw = skge->hw;

1406

struct skge_hw *hw = skge->hw;

1407

int port = skge->port;

1407

int port = skge->port;

1408

u16 cmd;

1408

u16 cmd;

1409

u32 mode, msk;

1409

u32 mode, msk;

1410

1411

cmd = xm_read16(hw, port, XM_MMU_CMD);

1411

cmd = xm_read16(hw, port, XM_MMU_CMD);

1412

1413

/*

1413

/*

1414

* enabling pause frame reception is required for 1000BT

1414

* enabling pause frame reception is required for 1000BT

1415

* because the XMAC is not reset if the link is going down

1415

* because the XMAC is not reset if the link is going down

1416

*/

1416

*/

1417

if (skge->flow_control == FLOW_MODE_NONE ||

1417

if (skge->flow_control == FLOW_MODE_NONE ||

1418

skge->flow_control == FLOW_MODE_LOC_SEND)

1418

skge->flow_control == FLOW_MODE_LOC_SEND)

1419

/* Disable Pause Frame Reception */

1419

/* Disable Pause Frame Reception */

1420

cmd |= XM_MMU_IGN_PF;

1420

cmd |= XM_MMU_IGN_PF;

1421

else

1421

else

1422

/* Enable Pause Frame Reception */

1422

/* Enable Pause Frame Reception */

1423

cmd &= ~XM_MMU_IGN_PF;

1423

cmd &= ~XM_MMU_IGN_PF;

1424

1425

xm_write16(hw, port, XM_MMU_CMD, cmd);

1425

xm_write16(hw, port, XM_MMU_CMD, cmd);

1426

1427

mode = xm_read32(hw, port, XM_MODE);

1427

mode = xm_read32(hw, port, XM_MODE);

1428

if (skge->flow_control == FLOW_MODE_SYMMETRIC ||

1428

if (skge->flow_control == FLOW_MODE_SYMMETRIC ||

1429

skge->flow_control == FLOW_MODE_LOC_SEND) {

1429

skge->flow_control == FLOW_MODE_LOC_SEND) {

1430

/*

1430

/*

1431

* Configure Pause Frame Generation

1431

* Configure Pause Frame Generation

1432

* Use internal and external Pause Frame Generation.

1432

* Use internal and external Pause Frame Generation.

1433

* Sending pause frames is edge triggered.

1433

* Sending pause frames is edge triggered.

1434

* Send a Pause frame with the maximum pause time if

1434

* Send a Pause frame with the maximum pause time if

1435

* internal oder external FIFO full condition occurs.

1435

* internal oder external FIFO full condition occurs.

1436

* Send a zero pause time frame to re-start transmission.

1436

* Send a zero pause time frame to re-start transmission.

1437

*/

1437

*/

1438

/* XM_PAUSE_DA = '010000C28001' (default) */

1438

/* XM_PAUSE_DA = '010000C28001' (default) */

1439

/* XM_MAC_PTIME = 0xffff (maximum) */

1439

/* XM_MAC_PTIME = 0xffff (maximum) */

1440

/* remember this value is defined in big endian (!) */

1440

/* remember this value is defined in big endian (!) */

1441

xm_write16(hw, port, XM_MAC_PTIME, 0xffff);

1441

xm_write16(hw, port, XM_MAC_PTIME, 0xffff);

1442

1443

mode |= XM_PAUSE_MODE;

1443

mode |= XM_PAUSE_MODE;

1444

skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);

1444

skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);

1445

} else {

1445

} else {

1446

/*

1446

/*

1447

* disable pause frame generation is required for 1000BT

1447

* disable pause frame generation is required for 1000BT

1448

* because the XMAC is not reset if the link is going down

1448

* because the XMAC is not reset if the link is going down

1449

*/

1449

*/

1450

/* Disable Pause Mode in Mode Register */

1450

/* Disable Pause Mode in Mode Register */

1451

mode &= ~XM_PAUSE_MODE;

1451

mode &= ~XM_PAUSE_MODE;

1452

1453

skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);

1453

skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);

1454

}

1454

}

1455

1456

xm_write32(hw, port, XM_MODE, mode);

1456

xm_write32(hw, port, XM_MODE, mode);

1457

1458

msk = XM_DEF_MSK;

1458

msk = XM_DEF_MSK;

1459

/* disable GP0 interrupt bit for external Phy */

1459

/* disable GP0 interrupt bit for external Phy */

1460

msk |= XM_IS_INP_ASS;

1460

msk |= XM_IS_INP_ASS;

1461

1462

xm_write16(hw, port, XM_IMSK, msk);

1462

xm_write16(hw, port, XM_IMSK, msk);

1463

xm_read16(hw, port, XM_ISRC);

1463

xm_read16(hw, port, XM_ISRC);

1464

1465

/* get MMU Command Reg. */

1465

/* get MMU Command Reg. */

1466

cmd = xm_read16(hw, port, XM_MMU_CMD);

1466

cmd = xm_read16(hw, port, XM_MMU_CMD);

1467

if (skge->duplex == DUPLEX_FULL)

1467

if (skge->duplex == DUPLEX_FULL)

1468

cmd |= XM_MMU_GMII_FD;

1468

cmd |= XM_MMU_GMII_FD;

1469

1470

/*

1470

/*

1471

* Workaround BCOM Errata (#10523) for all BCom Phys

1471

* Workaround BCOM Errata (#10523) for all BCom Phys

1472

* Enable Power Management after link up

1472

* Enable Power Management after link up

1473

*/

1473

*/

1474

xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,

1474

xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,

1475

xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)

1475

xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)

1476

& ~PHY_B_AC_DIS_PM);

1476

& ~PHY_B_AC_DIS_PM);

1477

xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);

1477

xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);

1478

1479

/* enable Rx/Tx */

1479

/* enable Rx/Tx */

1480

xm_write16(hw, port, XM_MMU_CMD,

1480

xm_write16(hw, port, XM_MMU_CMD,

1481

cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);

1481

cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);

1482

skge_link_up(skge);

1482

skge_link_up(skge);

1483

}

1483

}

1484

1485

1486

static inline void bcom_phy_intr(struct skge_port *skge)

1486

static inline void bcom_phy_intr(struct skge_port *skge)

1487

{

1487

{

1488

struct skge_hw *hw = skge->hw;

1488

struct skge_hw *hw = skge->hw;

1489

int port = skge->port;

1489

int port = skge->port;

1490

u16 isrc;

1490

u16 isrc;

1491

1492

isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);

1492

isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);

1493

if (netif_msg_intr(skge))

1493

if (netif_msg_intr(skge))

1494

printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x\n",

1494

printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x\n",

1495

skge->netdev->name, isrc);

1495

skge->netdev->name, isrc);

1496

1497

if (isrc & PHY_B_IS_PSE)

1497

if (isrc & PHY_B_IS_PSE)

1498

printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n",

1498

printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n",

1499

hw->dev[port]->name);

1499

hw->dev[port]->name);

1500

1501

/* Workaround BCom Errata:

1501

/* Workaround BCom Errata:

1502

* enable and disable loopback mode if "NO HCD" occurs.

1502

* enable and disable loopback mode if "NO HCD" occurs.

1503

*/

1503

*/

1504

if (isrc & PHY_B_IS_NO_HDCL) {

1504

if (isrc & PHY_B_IS_NO_HDCL) {

1505

u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);

1505

u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);

1506

xm_phy_write(hw, port, PHY_BCOM_CTRL,

1506

xm_phy_write(hw, port, PHY_BCOM_CTRL,

1507

ctrl | PHY_CT_LOOP);

1507

ctrl | PHY_CT_LOOP);

1508

xm_phy_write(hw, port, PHY_BCOM_CTRL,

1508

xm_phy_write(hw, port, PHY_BCOM_CTRL,

1509

ctrl & ~PHY_CT_LOOP);

1509

ctrl & ~PHY_CT_LOOP);

1510

}

1510

}

1511

1512

if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))

1512

if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))

1513

bcom_check_link(hw, port);

1513

bcom_check_link(hw, port);

1514

1515

}

1515

}

1516

1517

static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)

1517

static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)

1518

{

1518

{

1519

int i;

1519

int i;

1520

1521

gma_write16(hw, port, GM_SMI_DATA, val);

1521

gma_write16(hw, port, GM_SMI_DATA, val);

1522

gma_write16(hw, port, GM_SMI_CTRL,

1522

gma_write16(hw, port, GM_SMI_CTRL,

1523

GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));

1523

GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));

1524

for (i = 0; i < PHY_RETRIES; i++) {

1524

for (i = 0; i < PHY_RETRIES; i++) {

1525

udelay(1);

1525

udelay(1);

1526

1527

if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))

1527

if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))

1528

return 0;

1528

return 0;

1529

}

1529

}

1530

1531

printk(KERN_WARNING PFX "%s: phy write timeout\n",

1531

printk(KERN_WARNING PFX "%s: phy write timeout\n",

1532

hw->dev[port]->name);

1532

hw->dev[port]->name);

1533

return -EIO;

1533

return -EIO;

1534

}

1534

}

1535

1536

static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)

1536

static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)

1537

{

1537

{

1538

int i;

1538

int i;

1539

1540

gma_write16(hw, port, GM_SMI_CTRL,

1540

gma_write16(hw, port, GM_SMI_CTRL,

1541

GM_SMI_CT_PHY_AD(hw->phy_addr)

1541

GM_SMI_CT_PHY_AD(hw->phy_addr)

1542

| GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);

1542

| GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);

1543

1544

for (i = 0; i < PHY_RETRIES; i++) {

1544

for (i = 0; i < PHY_RETRIES; i++) {

1545

udelay(1);

1545

udelay(1);

1546

if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)

1546

if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)

1547

goto ready;

1547

goto ready;

1548

}

1548

}

1549

1550

return -ETIMEDOUT;

1550

return -ETIMEDOUT;

1551

ready:

1551

ready:

1552

*val = gma_read16(hw, port, GM_SMI_DATA);

1552

*val = gma_read16(hw, port, GM_SMI_DATA);

1553

return 0;

1553

return 0;

1554

}

1554

}

1555

1556

static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)

1556

static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)

1557

{

1557

{

1558

u16 v = 0;

1558

u16 v = 0;

1559

if (__gm_phy_read(hw, port, reg, &v))

1559

if (__gm_phy_read(hw, port, reg, &v))

1560

printk(KERN_WARNING PFX "%s: phy read timeout\n",

1560

printk(KERN_WARNING PFX "%s: phy read timeout\n",

1561

hw->dev[port]->name);

1561

hw->dev[port]->name);

1562

return v;

1562

return v;

1563

}

1563

}

1564

1565

/* Marvell Phy Initialization */

1565

/* Marvell Phy Initialization */

1566

static void yukon_init(struct skge_hw *hw, int port)

1566

static void yukon_init(struct skge_hw *hw, int port)

1567

{

1567

{

1568

struct skge_port *skge = netdev_priv(hw->dev[port]);

1568

struct skge_port *skge = netdev_priv(hw->dev[port]);

1569

u16 ctrl, ct1000, adv;

1569

u16 ctrl, ct1000, adv;

1570

1571

if (skge->autoneg == AUTONEG_ENABLE) {

1571

if (skge->autoneg == AUTONEG_ENABLE) {

1572

u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);

1572

u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);

1573

1574

ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |

1574

ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |

1575

PHY_M_EC_MAC_S_MSK);

1575

PHY_M_EC_MAC_S_MSK);

1576

ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);

1576

ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);

1577

1578

ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);

1578

ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);

1579

1580

gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);

1580

gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);

1581

}

1581

}

1582

1583

ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);

1583

ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);

1584

if (skge->autoneg == AUTONEG_DISABLE)

1584

if (skge->autoneg == AUTONEG_DISABLE)

1585

ctrl &= ~PHY_CT_ANE;

1585

ctrl &= ~PHY_CT_ANE;

1586

1587

ctrl |= PHY_CT_RESET;

1587

ctrl |= PHY_CT_RESET;

1588

gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);

1588

gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);

1589

1590

ctrl = 0;

1590

ctrl = 0;

1591

ct1000 = 0;

1591

ct1000 = 0;

1592

adv = PHY_AN_CSMA;

1592

adv = PHY_AN_CSMA;

1593

1594

if (skge->autoneg == AUTONEG_ENABLE) {

1594

if (skge->autoneg == AUTONEG_ENABLE) {

1595

if (hw->copper) {

1595

if (hw->copper) {

1596

if (skge->advertising & ADVERTISED_1000baseT_Full)

1596

if (skge->advertising & ADVERTISED_1000baseT_Full)

1597

ct1000 |= PHY_M_1000C_AFD;

1597

ct1000 |= PHY_M_1000C_AFD;

1598

if (skge->advertising & ADVERTISED_1000baseT_Half)

1598

if (skge->advertising & ADVERTISED_1000baseT_Half)

1599

ct1000 |= PHY_M_1000C_AHD;

1599

ct1000 |= PHY_M_1000C_AHD;

1600

if (skge->advertising & ADVERTISED_100baseT_Full)

1600

if (skge->advertising & ADVERTISED_100baseT_Full)

1601

adv |= PHY_M_AN_100_FD;

1601

adv |= PHY_M_AN_100_FD;

1602

if (skge->advertising & ADVERTISED_100baseT_Half)

1602

if (skge->advertising & ADVERTISED_100baseT_Half)

1603

adv |= PHY_M_AN_100_HD;

1603

adv |= PHY_M_AN_100_HD;

1604

if (skge->advertising & ADVERTISED_10baseT_Full)

1604

if (skge->advertising & ADVERTISED_10baseT_Full)

1605

adv |= PHY_M_AN_10_FD;

1605

adv |= PHY_M_AN_10_FD;

1606

if (skge->advertising & ADVERTISED_10baseT_Half)

1606

if (skge->advertising & ADVERTISED_10baseT_Half)

1607

adv |= PHY_M_AN_10_HD;

1607

adv |= PHY_M_AN_10_HD;

1608

} else /* special defines for FIBER (88E1011S only) */

1608

} else /* special defines for FIBER (88E1011S only) */

1609

adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;

1609

adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;

1610

1611

/* Set Flow-control capabilities */

1611

/* Set Flow-control capabilities */

1612

adv |= phy_pause_map[skge->flow_control];

1612

adv |= phy_pause_map[skge->flow_control];

1613

1614

/* Restart Auto-negotiation */

1614

/* Restart Auto-negotiation */

1615

ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;

1615

ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;

1616

} else {

1616

} else {

1617

/* forced speed/duplex settings */

1617

/* forced speed/duplex settings */

1618

ct1000 = PHY_M_1000C_MSE;

1618

ct1000 = PHY_M_1000C_MSE;

1619

1620

if (skge->duplex == DUPLEX_FULL)

1620

if (skge->duplex == DUPLEX_FULL)

1621

ctrl |= PHY_CT_DUP_MD;

1621

ctrl |= PHY_CT_DUP_MD;

1622

1623

switch (skge->speed) {

1623

switch (skge->speed) {

1624

case SPEED_1000:

1624

case SPEED_1000:

1625

ctrl |= PHY_CT_SP1000;

1625

ctrl |= PHY_CT_SP1000;

1626

break;

1626

break;

1627

case SPEED_100:

1627

case SPEED_100:

1628

ctrl |= PHY_CT_SP100;

1628

ctrl |= PHY_CT_SP100;

1629

break;

1629

break;

1630

}

1630

}

1631

1632

ctrl |= PHY_CT_RESET;

1632

ctrl |= PHY_CT_RESET;

1633

}

1633

}

1634

1635

gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);

1635

gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);

1636

1637

gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);

1637

gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);

1638

gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);

1638

gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);

1639

1640

/* Enable phy interrupt on autonegotiation complete (or link up) */

1640

/* Enable phy interrupt on autonegotiation complete (or link up) */

1641

if (skge->autoneg == AUTONEG_ENABLE)

1641

if (skge->autoneg == AUTONEG_ENABLE)

1642

gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);

1642

gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);

1643

else

1643

else

1644

gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);

1644

gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);

1645

}

1645

}

1646

1647

static void yukon_reset(struct skge_hw *hw, int port)

1647

static void yukon_reset(struct skge_hw *hw, int port)

1648

{

1648

{

1649

gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */

1649

gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */

1650

gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */

1650

gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */

1651

gma_write16(hw, port, GM_MC_ADDR_H2, 0);

1651

gma_write16(hw, port, GM_MC_ADDR_H2, 0);

1652

gma_write16(hw, port, GM_MC_ADDR_H3, 0);

1652

gma_write16(hw, port, GM_MC_ADDR_H3, 0);

1653

gma_write16(hw, port, GM_MC_ADDR_H4, 0);

1653

gma_write16(hw, port, GM_MC_ADDR_H4, 0);

1654

1655

gma_write16(hw, port, GM_RX_CTRL,

1655

gma_write16(hw, port, GM_RX_CTRL,

1656

gma_read16(hw, port, GM_RX_CTRL)

1656

gma_read16(hw, port, GM_RX_CTRL)

1657

| GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);

1657

| GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);

1658

}

1658

}

1659

1660

/* Apparently, early versions of Yukon-Lite had wrong chip_id? */

1660

/* Apparently, early versions of Yukon-Lite had wrong chip_id? */

1661

static int is_yukon_lite_a0(struct skge_hw *hw)

1661

static int is_yukon_lite_a0(struct skge_hw *hw)

1662

{

1662

{

1663

u32 reg;

1663

u32 reg;

1664

int ret;

1664

int ret;

1665

1666

if (hw->chip_id != CHIP_ID_YUKON)

1666

if (hw->chip_id != CHIP_ID_YUKON)

1667

return 0;

1667

return 0;

1668

1669

reg = skge_read32(hw, B2_FAR);

1669

reg = skge_read32(hw, B2_FAR);

1670

skge_write8(hw, B2_FAR + 3, 0xff);

1670

skge_write8(hw, B2_FAR + 3, 0xff);

1671

ret = (skge_read8(hw, B2_FAR + 3) != 0);

1671

ret = (skge_read8(hw, B2_FAR + 3) != 0);

1672

skge_write32(hw, B2_FAR, reg);

1672

skge_write32(hw, B2_FAR, reg);

1673

return ret;

1673

return ret;

1674

}

1674

}

1675

1676

static void yukon_mac_init(struct skge_hw *hw, int port)

1676

static void yukon_mac_init(struct skge_hw *hw, int port)

1677

{

1677

{

1678

struct skge_port *skge = netdev_priv(hw->dev[port]);

1678

struct skge_port *skge = netdev_priv(hw->dev[port]);

1679

int i;

1679

int i;

1680

u32 reg;

1680

u32 reg;

1681

const u8 *addr = hw->dev[port]->dev_addr;

1681

const u8 *addr = hw->dev[port]->dev_addr;

1682

1683

/* WA code for COMA mode -- set PHY reset */

1683

/* WA code for COMA mode -- set PHY reset */

1684

if (hw->chip_id == CHIP_ID_YUKON_LITE &&

1684

if (hw->chip_id == CHIP_ID_YUKON_LITE &&

1685

hw->chip_rev >= CHIP_REV_YU_LITE_A3) {

1685

hw->chip_rev >= CHIP_REV_YU_LITE_A3) {

1686

reg = skge_read32(hw, B2_GP_IO);

1686

reg = skge_read32(hw, B2_GP_IO);

1687

reg |= GP_DIR_9 | GP_IO_9;

1687

reg |= GP_DIR_9 | GP_IO_9;

1688

skge_write32(hw, B2_GP_IO, reg);

1688

skge_write32(hw, B2_GP_IO, reg);

1689

}

1689

}

1690

1691

/* hard reset */

1691

/* hard reset */

1692

skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);

1692

skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);

1693

skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);

1693

skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);

1694

1695

/* WA code for COMA mode -- clear PHY reset */

1695

/* WA code for COMA mode -- clear PHY reset */

1696

if (hw->chip_id == CHIP_ID_YUKON_LITE &&

1696

if (hw->chip_id == CHIP_ID_YUKON_LITE &&

1697

hw->chip_rev >= CHIP_REV_YU_LITE_A3) {

1697

hw->chip_rev >= CHIP_REV_YU_LITE_A3) {

1698

reg = skge_read32(hw, B2_GP_IO);

1698

reg = skge_read32(hw, B2_GP_IO);

1699

reg |= GP_DIR_9;

1699

reg |= GP_DIR_9;

1700

reg &= ~GP_IO_9;

1700

reg &= ~GP_IO_9;

1701

skge_write32(hw, B2_GP_IO, reg);

1701

skge_write32(hw, B2_GP_IO, reg);

1702

}

1702

}

1703

1704

/* Set hardware config mode */

1704

/* Set hardware config mode */

1705

reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |

1705

reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |

1706

GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;

1706

GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;

1707

reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;

1707

reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;

1708

1709

/* Clear GMC reset */

1709

/* Clear GMC reset */

1710

skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);

1710

skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);

1711

skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);

1711

skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);

1712

skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);

1712

skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);

1713

1714

if (skge->autoneg == AUTONEG_DISABLE) {

1714

if (skge->autoneg == AUTONEG_DISABLE) {

1715

reg = GM_GPCR_AU_ALL_DIS;

1715

reg = GM_GPCR_AU_ALL_DIS;

1716

gma_write16(hw, port, GM_GP_CTRL,

1716

gma_write16(hw, port, GM_GP_CTRL,

1717

gma_read16(hw, port, GM_GP_CTRL) | reg);

1717

gma_read16(hw, port, GM_GP_CTRL) | reg);

1718

1719

switch (skge->speed) {

1719

switch (skge->speed) {

1720

case SPEED_1000:

1720

case SPEED_1000:

1721

reg &= ~GM_GPCR_SPEED_100;

1721

reg &= ~GM_GPCR_SPEED_100;

1722

reg |= GM_GPCR_SPEED_1000;

1722

reg |= GM_GPCR_SPEED_1000;

1723

break;

1723

break;

1724

case SPEED_100:

1724

case SPEED_100:

1725

reg &= ~GM_GPCR_SPEED_1000;

1725

reg &= ~GM_GPCR_SPEED_1000;

1726

reg |= GM_GPCR_SPEED_100;

1726

reg |= GM_GPCR_SPEED_100;

1727

break;

1727

break;

1728

case SPEED_10:

1728

case SPEED_10:

1729

reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);

1729

reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);

1730

break;

1730

break;

1731

}

1731

}

1732

1733

if (skge->duplex == DUPLEX_FULL)

1733

if (skge->duplex == DUPLEX_FULL)

1734

reg |= GM_GPCR_DUP_FULL;

1734

reg |= GM_GPCR_DUP_FULL;

1735

} else

1735

} else

1736

reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;

1736

reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;

1737

1738

switch (skge->flow_control) {

1738

switch (skge->flow_control) {

1739

case FLOW_MODE_NONE:

1739

case FLOW_MODE_NONE:

1740

skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);

1740

skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);

1741

reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;

1741

reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;

1742

break;

1742

break;

1743

case FLOW_MODE_LOC_SEND:

1743

case FLOW_MODE_LOC_SEND:

1744

/* disable Rx flow-control */

1744

/* disable Rx flow-control */

1745

reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;

1745

reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;

1746

}

1746

}

1747

1748

gma_write16(hw, port, GM_GP_CTRL, reg);

1748

gma_write16(hw, port, GM_GP_CTRL, reg);

1749

skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));

1749

skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));

1750

1751

yukon_init(hw, port);

1751

yukon_init(hw, port);

1752

1753

/* MIB clear */

1753

/* MIB clear */

1754

reg = gma_read16(hw, port, GM_PHY_ADDR);

1754

reg = gma_read16(hw, port, GM_PHY_ADDR);

1755

gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);

1755

gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);

1756

1757

for (i = 0; i < GM_MIB_CNT_SIZE; i++)

1757

for (i = 0; i < GM_MIB_CNT_SIZE; i++)

1758

gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);

1758

gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);

1759

gma_write16(hw, port, GM_PHY_ADDR, reg);

1759

gma_write16(hw, port, GM_PHY_ADDR, reg);

1760

1761

/* transmit control */

1761

/* transmit control */

1762

gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));

1762

gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));

1763

1764

/* receive control reg: unicast + multicast + no FCS */

1764

/* receive control reg: unicast + multicast + no FCS */

1765

gma_write16(hw, port, GM_RX_CTRL,

1765

gma_write16(hw, port, GM_RX_CTRL,

1766

GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);

1766

GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);

1767

1768

/* transmit flow control */

1768

/* transmit flow control */

1769

gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);

1769

gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);

1770

1771

/* transmit parameter */

1771

/* transmit parameter */

1772

gma_write16(hw, port, GM_TX_PARAM,

1772

gma_write16(hw, port, GM_TX_PARAM,

1773

TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |

1773

TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |

1774

TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |

1774

TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |

1775

TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));

1775

TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));

1776

1777

/* serial mode register */

1777

/* serial mode register */

1778

reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);

1778

reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);

1779

if (hw->dev[port]->mtu > 1500)

1779

if (hw->dev[port]->mtu > 1500)

1780

reg |= GM_SMOD_JUMBO_ENA;

1780

reg |= GM_SMOD_JUMBO_ENA;

1781

1782

gma_write16(hw, port, GM_SERIAL_MODE, reg);

1782

gma_write16(hw, port, GM_SERIAL_MODE, reg);

1783

1784

/* physical address: used for pause frames */

1784

/* physical address: used for pause frames */

1785

gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);

1785

gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);

1786

/* virtual address for data */

1786

/* virtual address for data */

1787

gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);

1787

gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);

1788

1789

/* enable interrupt mask for counter overflows */

1789

/* enable interrupt mask for counter overflows */

1790

gma_write16(hw, port, GM_TX_IRQ_MSK, 0);

1790

gma_write16(hw, port, GM_TX_IRQ_MSK, 0);

1791

gma_write16(hw, port, GM_RX_IRQ_MSK, 0);

1791

gma_write16(hw, port, GM_RX_IRQ_MSK, 0);

1792

gma_write16(hw, port, GM_TR_IRQ_MSK, 0);

1792

gma_write16(hw, port, GM_TR_IRQ_MSK, 0);

1793

1794

/* Initialize Mac Fifo */

1794

/* Initialize Mac Fifo */

1795

1796

/* Configure Rx MAC FIFO */

1796

/* Configure Rx MAC FIFO */

1797

skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);

1797

skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);

1798

reg = GMF_OPER_ON | GMF_RX_F_FL_ON;

1798

reg = GMF_OPER_ON | GMF_RX_F_FL_ON;

1799

1800

/* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */

1800

/* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */

1801

if (is_yukon_lite_a0(hw))

1801

if (is_yukon_lite_a0(hw))

1802

reg &= ~GMF_RX_F_FL_ON;

1802

reg &= ~GMF_RX_F_FL_ON;

1803

1804

skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);

1804

skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);

1805

skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);

1805

skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);

1806

/*

1806

/*

1807

* because Pause Packet Truncation in GMAC is not working

1807

* because Pause Packet Truncation in GMAC is not working

1808

* we have to increase the Flush Threshold to 64 bytes

1808

* we have to increase the Flush Threshold to 64 bytes

1809

* in order to flush pause packets in Rx FIFO on Yukon-1

1809

* in order to flush pause packets in Rx FIFO on Yukon-1

1810

*/

1810

*/

1811

skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);

1811

skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);

1812

1813

/* Configure Tx MAC FIFO */

1813

/* Configure Tx MAC FIFO */

1814

skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);

1814

skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);

1815

skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);

1815

skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);

1816

}

1816

}

1817

1818

/* Go into power down mode */

1818

/* Go into power down mode */

1819

static void yukon_suspend(struct skge_hw *hw, int port)

1819

static void yukon_suspend(struct skge_hw *hw, int port)

1820

{

1820

{

1821

u16 ctrl;

1821

u16 ctrl;

1822

1823

ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);

1823

ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);

1824

ctrl |= PHY_M_PC_POL_R_DIS;

1824

ctrl |= PHY_M_PC_POL_R_DIS;

1825

gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);

1825

gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);

1826

1827

ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);

1827

ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);

1828

ctrl |= PHY_CT_RESET;

1828

ctrl |= PHY_CT_RESET;

1829

gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);

1829

gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);

1830

1831

/* switch IEEE compatible power down mode on */

1831

/* switch IEEE compatible power down mode on */

1832

ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);

1832

ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);

1833

ctrl |= PHY_CT_PDOWN;

1833

ctrl |= PHY_CT_PDOWN;

1834

gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);

1834

gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);

1835

}

1835

}

1836

1837

static void yukon_stop(struct skge_port *skge)

1837

static void yukon_stop(struct skge_port *skge)

1838

{

1838

{

1839

struct skge_hw *hw = skge->hw;

1839

struct skge_hw *hw = skge->hw;

1840

int port = skge->port;

1840

int port = skge->port;

1841

1842

skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);

1842

skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);

1843

yukon_reset(hw, port);

1843

yukon_reset(hw, port);

1844

1845

gma_write16(hw, port, GM_GP_CTRL,

1845

gma_write16(hw, port, GM_GP_CTRL,

1846

gma_read16(hw, port, GM_GP_CTRL)

1846

gma_read16(hw, port, GM_GP_CTRL)

1847

& ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));

1847

& ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));

1848

gma_read16(hw, port, GM_GP_CTRL);

1848

gma_read16(hw, port, GM_GP_CTRL);

1849

1850

yukon_suspend(hw, port);

1850

yukon_suspend(hw, port);

1851

1852

/* set GPHY Control reset */

1852

/* set GPHY Control reset */

1853

skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);

1853

skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);

1854

skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);

1854

skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);

1855

}

1855

}

1856

1857

static void yukon_get_stats(struct skge_port *skge, u64 *data)

1857

static void yukon_get_stats(struct skge_port *skge, u64 *data)

1858

{

1858

{

1859

struct skge_hw *hw = skge->hw;

1859

struct skge_hw *hw = skge->hw;

1860

int port = skge->port;

1860

int port = skge->port;

1861

int i;

1861

int i;

1862

1863

data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32

1863

data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32

1864

| gma_read32(hw, port, GM_TXO_OK_LO);

1864

| gma_read32(hw, port, GM_TXO_OK_LO);

1865

data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32

1865

data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32

1866

| gma_read32(hw, port, GM_RXO_OK_LO);

1866

| gma_read32(hw, port, GM_RXO_OK_LO);

1867

1868

for (i = 2; i < ARRAY_SIZE(skge_stats); i++)

1868

for (i = 2; i < ARRAY_SIZE(skge_stats); i++)

1869

data[i] = gma_read32(hw, port,

1869

data[i] = gma_read32(hw, port,

1870

skge_stats[i].gma_offset);

1870

skge_stats[i].gma_offset);

1871

}

1871

}

1872

1873

static void yukon_mac_intr(struct skge_hw *hw, int port)

1873

static void yukon_mac_intr(struct skge_hw *hw, int port)

1874

{

1874

{

1875

struct net_device *dev = hw->dev[port];

1875

struct net_device *dev = hw->dev[port];

1876

struct skge_port *skge = netdev_priv(dev);

1876

struct skge_port *skge = netdev_priv(dev);

1877

u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));

1877

u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));

1878

1879

if (netif_msg_intr(skge))

1879

if (netif_msg_intr(skge))

1880

printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",

1880

printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",

1881

dev->name, status);

1881

dev->name, status);

1882

1883

if (status & GM_IS_RX_FF_OR) {

1883

if (status & GM_IS_RX_FF_OR) {

1884

++skge->net_stats.rx_fifo_errors;

1884

++skge->net_stats.rx_fifo_errors;

1885

skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);

1885

skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);

1886

}

1886

}

1887

1888

if (status & GM_IS_TX_FF_UR) {

1888

if (status & GM_IS_TX_FF_UR) {

1889

++skge->net_stats.tx_fifo_errors;

1889

++skge->net_stats.tx_fifo_errors;

1890

skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);

1890

skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);

1891

}

1891

}

1892

1893

}

1893

}

1894

1895

static u16 yukon_speed(const struct skge_hw *hw, u16 aux)

1895

static u16 yukon_speed(const struct skge_hw *hw, u16 aux)

1896

{

1896

{

1897

switch (aux & PHY_M_PS_SPEED_MSK) {

1897

switch (aux & PHY_M_PS_SPEED_MSK) {

1898

case PHY_M_PS_SPEED_1000:

1898

case PHY_M_PS_SPEED_1000:

1899

return SPEED_1000;

1899

return SPEED_1000;

1900

case PHY_M_PS_SPEED_100:

1900

case PHY_M_PS_SPEED_100:

1901

return SPEED_100;

1901

return SPEED_100;

1902

default:

1902

default:

1903

return SPEED_10;

1903

return SPEED_10;

1904

}

1904

}

1905

}

1905

}

1906

1907

static void yukon_link_up(struct skge_port *skge)

1907

static void yukon_link_up(struct skge_port *skge)

1908

{

1908

{

1909

struct skge_hw *hw = skge->hw;

1909

struct skge_hw *hw = skge->hw;

1910

int port = skge->port;

1910

int port = skge->port;

1911

u16 reg;

1911

u16 reg;

1912

1913

/* Enable Transmit FIFO Underrun */

1913

/* Enable Transmit FIFO Underrun */

1914

skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);

1914

skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);

1915

1916

reg = gma_read16(hw, port, GM_GP_CTRL);

1916

reg = gma_read16(hw, port, GM_GP_CTRL);

1917

if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)

1917

if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)

1918

reg |= GM_GPCR_DUP_FULL;

1918

reg |= GM_GPCR_DUP_FULL;

1919

1920

/* enable Rx/Tx */

1920

/* enable Rx/Tx */

1921

reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;

1921

reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;

1922

gma_write16(hw, port, GM_GP_CTRL, reg);

1922

gma_write16(hw, port, GM_GP_CTRL, reg);

1923

1924

gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);

1924

gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);

1925

skge_link_up(skge);

1925

skge_link_up(skge);

1926

}

1926

}

1927

1928

static void yukon_link_down(struct skge_port *skge)

1928

static void yukon_link_down(struct skge_port *skge)

1929

{

1929

{

1930

struct skge_hw *hw = skge->hw;

1930

struct skge_hw *hw = skge->hw;

1931

int port = skge->port;

1931

int port = skge->port;

1932

u16 ctrl;

1932

u16 ctrl;

1933

1934

gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);

1934

gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);

1935

1936

ctrl = gma_read16(hw, port, GM_GP_CTRL);

1936

ctrl = gma_read16(hw, port, GM_GP_CTRL);

1937

ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);

1937

ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);

1938

gma_write16(hw, port, GM_GP_CTRL, ctrl);

1938

gma_write16(hw, port, GM_GP_CTRL, ctrl);

1939

1940

if (skge->flow_control == FLOW_MODE_REM_SEND) {

1940

if (skge->flow_control == FLOW_MODE_REM_SEND) {

1941

/* restore Asymmetric Pause bit */

1941

/* restore Asymmetric Pause bit */

1942

gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,

1942

gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,

1943

gm_phy_read(hw, port,

1943

gm_phy_read(hw, port,

1944

PHY_MARV_AUNE_ADV)

1944

PHY_MARV_AUNE_ADV)

1945

| PHY_M_AN_ASP);

1945

| PHY_M_AN_ASP);

1946

1947

}

1947

}

1948

1949

yukon_reset(hw, port);

1949

yukon_reset(hw, port);

1950

skge_link_down(skge);

1950

skge_link_down(skge);

1951

1952

yukon_init(hw, port);

1952

yukon_init(hw, port);

1953

}

1953

}

1954

1955

static void yukon_phy_intr(struct skge_port *skge)

1955

static void yukon_phy_intr(struct skge_port *skge)

1956

{

1956

{

1957

struct skge_hw *hw = skge->hw;

1957

struct skge_hw *hw = skge->hw;

1958

int port = skge->port;

1958

int port = skge->port;

1959

const char *reason = NULL;

1959

const char *reason = NULL;

1960

u16 istatus, phystat;

1960

u16 istatus, phystat;

1961

1962

istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);

1962

istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);

1963

phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);

1963

phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);

1964

1965

if (netif_msg_intr(skge))

1965

if (netif_msg_intr(skge))

1966

printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x 0x%x\n",

1966

printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x 0x%x\n",

1967

skge->netdev->name, istatus, phystat);

1967

skge->netdev->name, istatus, phystat);

1968

1969

if (istatus & PHY_M_IS_AN_COMPL) {

1969

if (istatus & PHY_M_IS_AN_COMPL) {

1970

if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)

1970

if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)

1971

& PHY_M_AN_RF) {

1971

& PHY_M_AN_RF) {

1972

reason = "remote fault";

1972

reason = "remote fault";

1973

goto failed;

1973

goto failed;

1974

}

1974

}

1975

1976

if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {

1976

if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {

1977

reason = "master/slave fault";

1977

reason = "master/slave fault";

1978

goto failed;

1978

goto failed;

1979

}

1979

}

1980

1981

if (!(phystat & PHY_M_PS_SPDUP_RES)) {

1981

if (!(phystat & PHY_M_PS_SPDUP_RES)) {

1982

reason = "speed/duplex";

1982

reason = "speed/duplex";

1983

goto failed;

1983

goto failed;

1984

}

1984

}

1985

1986

skge->duplex = (phystat & PHY_M_PS_FULL_DUP)

1986

skge->duplex = (phystat & PHY_M_PS_FULL_DUP)

1987

? DUPLEX_FULL : DUPLEX_HALF;

1987

? DUPLEX_FULL : DUPLEX_HALF;

1988

skge->speed = yukon_speed(hw, phystat);

1988

skge->speed = yukon_speed(hw, phystat);

1989

1990

/* We are using IEEE 802.3z/D5.0 Table 37-4 */

1990

/* We are using IEEE 802.3z/D5.0 Table 37-4 */

1991

switch (phystat & PHY_M_PS_PAUSE_MSK) {

1991

switch (phystat & PHY_M_PS_PAUSE_MSK) {

1992

case PHY_M_PS_PAUSE_MSK:

1992

case PHY_M_PS_PAUSE_MSK:

1993

skge->flow_control = FLOW_MODE_SYMMETRIC;

1993

skge->flow_control = FLOW_MODE_SYMMETRIC;

1994

break;

1994

break;

1995

case PHY_M_PS_RX_P_EN:

1995

case PHY_M_PS_RX_P_EN:

1996

skge->flow_control = FLOW_MODE_REM_SEND;

1996

skge->flow_control = FLOW_MODE_REM_SEND;

1997

break;

1997

break;

1998

case PHY_M_PS_TX_P_EN:

1998

case PHY_M_PS_TX_P_EN:

1999

skge->flow_control = FLOW_MODE_LOC_SEND;

1999

skge->flow_control = FLOW_MODE_LOC_SEND;

2000

break;

2000

break;

2001

default:

2001

default:

2002

skge->flow_control = FLOW_MODE_NONE;

2002

skge->flow_control = FLOW_MODE_NONE;

2003

}

2003

}

2004

2005

if (skge->flow_control == FLOW_MODE_NONE ||

2005

if (skge->flow_control == FLOW_MODE_NONE ||

2006

(skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))

2006

(skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))

2007

skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);

2007

skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);

2008

else

2008

else

2009

skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);

2009

skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);

2010

yukon_link_up(skge);

2010

yukon_link_up(skge);

2011

return;

2011

return;

2012

}

2012

}

2013

2014

if (istatus & PHY_M_IS_LSP_CHANGE)

2014

if (istatus & PHY_M_IS_LSP_CHANGE)

2015

skge->speed = yukon_speed(hw, phystat);

2015

skge->speed = yukon_speed(hw, phystat);

2016

2017

if (istatus & PHY_M_IS_DUP_CHANGE)

2017

if (istatus & PHY_M_IS_DUP_CHANGE)

2018

skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;

2018

skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;

2019

if (istatus & PHY_M_IS_LST_CHANGE) {

2019

if (istatus & PHY_M_IS_LST_CHANGE) {

2020

if (phystat & PHY_M_PS_LINK_UP)

2020

if (phystat & PHY_M_PS_LINK_UP)

2021

yukon_link_up(skge);

2021

yukon_link_up(skge);

2022

else

2022

else

2023

yukon_link_down(skge);

2023

yukon_link_down(skge);

2024

}

2024

}

2025

return;

2025

return;

2026

failed:

2026

failed:

2027

printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n",

2027

printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n",

2028

skge->netdev->name, reason);

2028

skge->netdev->name, reason);

2029

2030

/* XXX restart autonegotiation? */

2030

/* XXX restart autonegotiation? */

2031

}

2031

}

2032

2033

static void skge_phy_reset(struct skge_port *skge)

2033

static void skge_phy_reset(struct skge_port *skge)

2034

{

2034

{

2035

struct skge_hw *hw = skge->hw;

2035

struct skge_hw *hw = skge->hw;

2036

int port = skge->port;

2036

int port = skge->port;

2037

2038

netif_stop_queue(skge->netdev);

2038

netif_stop_queue(skge->netdev);

2039

netif_carrier_off(skge->netdev);

2039

netif_carrier_off(skge->netdev);

2040

2041

spin_lock_bh(&hw->phy_lock);

2041

spin_lock_bh(&hw->phy_lock);

2042

if (hw->chip_id == CHIP_ID_GENESIS) {

2042

if (hw->chip_id == CHIP_ID_GENESIS) {

2043

genesis_reset(hw, port);

2043

genesis_reset(hw, port);

2044

genesis_mac_init(hw, port);

2044

genesis_mac_init(hw, port);

2045

} else {

2045

} else {

2046

yukon_reset(hw, port);

2046

yukon_reset(hw, port);

2047

yukon_init(hw, port);

2047

yukon_init(hw, port);

2048

}

2048

}

2049

spin_unlock_bh(&hw->phy_lock);

2049

spin_unlock_bh(&hw->phy_lock);

2050

}

2050

}

2051

2052

/* Basic MII support */

2052

/* Basic MII support */

2053

static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)

2053

static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)

2054

{

2054

{

2055

struct mii_ioctl_data *data = if_mii(ifr);

2055

struct mii_ioctl_data *data = if_mii(ifr);

2056

struct skge_port *skge = netdev_priv(dev);

2056

struct skge_port *skge = netdev_priv(dev);

2057

struct skge_hw *hw = skge->hw;

2057

struct skge_hw *hw = skge->hw;

2058

int err = -EOPNOTSUPP;

2058

int err = -EOPNOTSUPP;

2059

2060

if (!netif_running(dev))

2060

if (!netif_running(dev))

2061

return -ENODEV; /* Phy still in reset */

2061

return -ENODEV; /* Phy still in reset */

2062

2063

switch(cmd) {

2063

switch(cmd) {

2064

case SIOCGMIIPHY:

2064

case SIOCGMIIPHY:

2065

data->phy_id = hw->phy_addr;

2065

data->phy_id = hw->phy_addr;

2066

2067

/* fallthru */

2067

/* fallthru */

2068

case SIOCGMIIREG: {

2068

case SIOCGMIIREG: {

2069

u16 val = 0;

2069

u16 val = 0;

2070

spin_lock_bh(&hw->phy_lock);

2070

spin_lock_bh(&hw->phy_lock);

2071

if (hw->chip_id == CHIP_ID_GENESIS)

2071

if (hw->chip_id == CHIP_ID_GENESIS)

2072

err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);

2072

err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);

2073

else

2073

else

2074

err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);

2074

err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);

2075

spin_unlock_bh(&hw->phy_lock);

2075

spin_unlock_bh(&hw->phy_lock);

2076

data->val_out = val;

2076

data->val_out = val;

2077

break;

2077

break;

2078

}

2078

}

2079

2080

case SIOCSMIIREG:

2080

case SIOCSMIIREG:

2081

if (!capable(CAP_NET_ADMIN))

2081

if (!capable(CAP_NET_ADMIN))

2082

return -EPERM;

2082

return -EPERM;

2083

2084

spin_lock_bh(&hw->phy_lock);

2084

spin_lock_bh(&hw->phy_lock);

2085

if (hw->chip_id == CHIP_ID_GENESIS)

2085

if (hw->chip_id == CHIP_ID_GENESIS)

2086

err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,

2086

err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,

2087

data->val_in);

2087

data->val_in);

2088

else

2088

else

2089

err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,

2089

err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,

2090

data->val_in);

2090

data->val_in);

2091

spin_unlock_bh(&hw->phy_lock);

2091

spin_unlock_bh(&hw->phy_lock);

2092

break;

2092

break;

2093

}

2093

}

2094

return err;

2094

return err;

2095

}

2095

}

2096

2097

static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)

2097

static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)

2098

{

2098

{

2099

u32 end;

2099

u32 end;

2100

2101

start /= 8;

2101

start /= 8;

2102

len /= 8;

2102

len /= 8;

2103

end = start + len - 1;

2103

end = start + len - 1;

2104

2105

skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);

2105

skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);

2106

skge_write32(hw, RB_ADDR(q, RB_START), start);

2106

skge_write32(hw, RB_ADDR(q, RB_START), start);

2107

skge_write32(hw, RB_ADDR(q, RB_WP), start);

2107

skge_write32(hw, RB_ADDR(q, RB_WP), start);

2108

skge_write32(hw, RB_ADDR(q, RB_RP), start);

2108

skge_write32(hw, RB_ADDR(q, RB_RP), start);

2109

skge_write32(hw, RB_ADDR(q, RB_END), end);

2109

skge_write32(hw, RB_ADDR(q, RB_END), end);

2110

2111

if (q == Q_R1 || q == Q_R2) {

2111

if (q == Q_R1 || q == Q_R2) {

2112

/* Set thresholds on receive queue's */

2112

/* Set thresholds on receive queue's */

2113

skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),

2113

skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),

2114

start + (2*len)/3);

2114

start + (2*len)/3);

2115

skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),

2115

skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),

2116

start + (len/3));

2116

start + (len/3));

2117

} else {

2117

} else {

2118

/* Enable store & forward on Tx queue's because

2118

/* Enable store & forward on Tx queue's because

2119

* Tx FIFO is only 4K on Genesis and 1K on Yukon

2119

* Tx FIFO is only 4K on Genesis and 1K on Yukon

2120

*/

2120

*/

2121

skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);

2121

skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);

2122

}

2122

}

2123

2124

skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);

2124

skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);

2125

}

2125

}

2126

2127

/* Setup Bus Memory Interface */

2127

/* Setup Bus Memory Interface */

2128

static void skge_qset(struct skge_port *skge, u16 q,

2128

static void skge_qset(struct skge_port *skge, u16 q,

2129

const struct skge_element *e)

2129

const struct skge_element *e)

2130

{

2130

{

2131

struct skge_hw *hw = skge->hw;

2131

struct skge_hw *hw = skge->hw;

2132

u32 watermark = 0x600;

2132

u32 watermark = 0x600;

2133

u64 base = skge->dma + (e->desc - skge->mem);

2133

u64 base = skge->dma + (e->desc - skge->mem);

2134

2135

/* optimization to reduce window on 32bit/33mhz */

2135

/* optimization to reduce window on 32bit/33mhz */

2136

if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)

2136

if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)

2137

watermark /= 2;

2137

watermark /= 2;

2138

2139

skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);

2139

skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);

2140

skge_write32(hw, Q_ADDR(q, Q_F), watermark);

2140

skge_write32(hw, Q_ADDR(q, Q_F), watermark);

2141

skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));

2141

skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));

2142

skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);

2142

skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);

2143

}

2143

}

2144

2145

static int skge_up(struct net_device *dev)

2145

static int skge_up(struct net_device *dev)

2146

{

2146

{

2147

struct skge_port *skge = netdev_priv(dev);

2147

struct skge_port *skge = netdev_priv(dev);

2148

struct skge_hw *hw = skge->hw;

2148

struct skge_hw *hw = skge->hw;

2149

int port = skge->port;

2149

int port = skge->port;

2150

u32 chunk, ram_addr;

2150

u32 chunk, ram_addr;

2151

size_t rx_size, tx_size;

2151

size_t rx_size, tx_size;

2152

int err;

2152

int err;

2153

2154

if (netif_msg_ifup(skge))

2154

if (netif_msg_ifup(skge))

2155

printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);

2155

printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);

2156

2157

if (dev->mtu > RX_BUF_SIZE)

2157

if (dev->mtu > RX_BUF_SIZE)

2158

skge->rx_buf_size = dev->mtu + ETH_HLEN + NET_IP_ALIGN;

2158

skge->rx_buf_size = dev->mtu + ETH_HLEN + NET_IP_ALIGN;

2159

else

2159

else

2160

skge->rx_buf_size = RX_BUF_SIZE;

2160

skge->rx_buf_size = RX_BUF_SIZE;

2161

2162

2163

rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);

2163

rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);

2164

tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);

2164

tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);

2165

skge->mem_size = tx_size + rx_size;

2165

skge->mem_size = tx_size + rx_size;

2166

skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);

2166

skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);

2167

if (!skge->mem)

2167

if (!skge->mem)

2168

return -ENOMEM;

2168

return -ENOMEM;

2169

2170

BUG_ON(skge->dma & 7);

2170

BUG_ON(skge->dma & 7);

2171

2172

if ((u64)skge->dma >> 32 != ((u64) skge->dma + skge->mem_size) >> 32) {

2172

if ((u64)skge->dma >> 32 != ((u64) skge->dma + skge->mem_size) >> 32) {

2173

printk(KERN_ERR PFX "pci_alloc_consistent region crosses 4G boundary\n");

2173

printk(KERN_ERR PFX "pci_alloc_consistent region crosses 4G boundary\n");

2174

err = -EINVAL;

2174

err = -EINVAL;

2175

goto free_pci_mem;

2175

goto free_pci_mem;

2176

}

2176

}

2177

2178

memset(skge->mem, 0, skge->mem_size);

2178

memset(skge->mem, 0, skge->mem_size);

2179

2180

if ((err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma)))

2180

err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma);

2181

if (err)

2181

goto free_pci_mem;

2182

goto free_pci_mem;

2182

2183

err = skge_rx_fill(skge);

2184

err = skge_rx_fill(skge);

2184

if (err)

2185

if (err)

2185

goto free_rx_ring;

2186

goto free_rx_ring;

2186

2187

if ((err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,

2188

err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,

2188

skge->dma + rx_size)))

2189

skge->dma + rx_size);

2190

if (err)

2189

goto free_rx_ring;

2191

goto free_rx_ring;

2190

2192

2191

skge->tx_avail = skge->tx_ring.count - 1;

2193

skge->tx_avail = skge->tx_ring.count - 1;

2192

2194

2193

/* Initialize MAC */

2195

/* Initialize MAC */

2194

spin_lock_bh(&hw->phy_lock);

2196

spin_lock_bh(&hw->phy_lock);

2195

if (hw->chip_id == CHIP_ID_GENESIS)

2197

if (hw->chip_id == CHIP_ID_GENESIS)

2196

genesis_mac_init(hw, port);

2198

genesis_mac_init(hw, port);

2197

else

2199

else

2198

yukon_mac_init(hw, port);

2200

yukon_mac_init(hw, port);

2199

spin_unlock_bh(&hw->phy_lock);

2201

spin_unlock_bh(&hw->phy_lock);

2200

2202

2201

/* Configure RAMbuffers */

2203

/* Configure RAMbuffers */

2202

chunk = hw->ram_size / ((hw->ports + 1)*2);

2204

chunk = hw->ram_size / ((hw->ports + 1)*2);

2203

ram_addr = hw->ram_offset + 2 * chunk * port;

2205

ram_addr = hw->ram_offset + 2 * chunk * port;

2204

2206

2205

skge_ramset(hw, rxqaddr[port], ram_addr, chunk);

2207

skge_ramset(hw, rxqaddr[port], ram_addr, chunk);

2206

skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);

2208

skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);

2207

2209

2208

BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);

2210

BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);

2209

skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);

2211

skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);

2210

skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);

2212

skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);

2211

2213

2212

/* Start receiver BMU */

2214

/* Start receiver BMU */

2213

wmb();

2215

wmb();

2214

skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);

2216

skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);

2215

skge_led(skge, LED_MODE_ON);

2217

skge_led(skge, LED_MODE_ON);

2216

2218

2217

return 0;

2219

return 0;

2218

2220

2219

free_rx_ring:

2221

free_rx_ring:

2220

skge_rx_clean(skge);

2222

skge_rx_clean(skge);

2221

kfree(skge->rx_ring.start);

2223

kfree(skge->rx_ring.start);

2222

free_pci_mem:

2224

free_pci_mem:

2223

pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);

2225

pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);

2224

skge->mem = NULL;

2226

skge->mem = NULL;

2225

2227

2226

return err;

2228

return err;

2227

}

2229

}

2228

2230

2229

static int skge_down(struct net_device *dev)

2231

static int skge_down(struct net_device *dev)

2230

{

2232

{

2231

struct skge_port *skge = netdev_priv(dev);

2233

struct skge_port *skge = netdev_priv(dev);

2232

struct skge_hw *hw = skge->hw;

2234

struct skge_hw *hw = skge->hw;

2233

int port = skge->port;

2235

int port = skge->port;

2234

2236

2235

if (skge->mem == NULL)

2237

if (skge->mem == NULL)

2236

return 0;

2238

return 0;

2237

2239

2238

if (netif_msg_ifdown(skge))

2240

if (netif_msg_ifdown(skge))

2239

printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);

2241

printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);

2240

2242

2241

netif_stop_queue(dev);

2243

netif_stop_queue(dev);

2242

2244

2243

skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);

2245

skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);

2244

if (hw->chip_id == CHIP_ID_GENESIS)

2246

if (hw->chip_id == CHIP_ID_GENESIS)

2245

genesis_stop(skge);

2247

genesis_stop(skge);

2246

else

2248

else

2247

yukon_stop(skge);

2249

yukon_stop(skge);

2248

2250

2249

/* Stop transmitter */

2251

/* Stop transmitter */

2250

skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);

2252

skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);

2251

skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),

2253

skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),

2252

RB_RST_SET|RB_DIS_OP_MD);

2254

RB_RST_SET|RB_DIS_OP_MD);

2253

2255

2254

2256

2255

/* Disable Force Sync bit and Enable Alloc bit */

2257

/* Disable Force Sync bit and Enable Alloc bit */

2256

skge_write8(hw, SK_REG(port, TXA_CTRL),

2258

skge_write8(hw, SK_REG(port, TXA_CTRL),

2257

TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);

2259

TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);

2258

2260

2259

/* Stop Interval Timer and Limit Counter of Tx Arbiter */

2261

/* Stop Interval Timer and Limit Counter of Tx Arbiter */

2260

skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);

2262

skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);

2261

skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);

2263

skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);

2262

2264

2263

/* Reset PCI FIFO */

2265

/* Reset PCI FIFO */

2264

skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);

2266

skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);

2265

skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);

2267

skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);

2266

2268

2267

/* Reset the RAM Buffer async Tx queue */

2269

/* Reset the RAM Buffer async Tx queue */

2268

skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);

2270

skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);

2269

/* stop receiver */

2271

/* stop receiver */

2270

skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);

2272

skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);

2271

skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),

2273

skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),

2272

RB_RST_SET|RB_DIS_OP_MD);

2274

RB_RST_SET|RB_DIS_OP_MD);

2273

skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);

2275

skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);

2274

2276

2275

if (hw->chip_id == CHIP_ID_GENESIS) {

2277

if (hw->chip_id == CHIP_ID_GENESIS) {

2276

skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);

2278

skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);

2277

skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);

2279

skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);

2278

} else {

2280

} else {

2279

skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);

2281

skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);

2280

skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);

2282

skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);

2281

}

2283

}

2282

2284

2283

skge_led(skge, LED_MODE_OFF);

2285

skge_led(skge, LED_MODE_OFF);

2284

2286

2285

skge_tx_clean(skge);

2287

skge_tx_clean(skge);

2286

skge_rx_clean(skge);

2288

skge_rx_clean(skge);

2287

2289

2288

kfree(skge->rx_ring.start);

2290

kfree(skge->rx_ring.start);

2289

kfree(skge->tx_ring.start);

2291

kfree(skge->tx_ring.start);

2290

pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);

2292

pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);

2291

skge->mem = NULL;

2293

skge->mem = NULL;

2292

return 0;

2294

return 0;

2293

}

2295

}

2294

2296

2295

static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)

2297

static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)

2296

{

2298

{

2297

struct skge_port *skge = netdev_priv(dev);

2299

struct skge_port *skge = netdev_priv(dev);

2298

struct skge_hw *hw = skge->hw;

2300

struct skge_hw *hw = skge->hw;

2299

struct skge_ring *ring = &skge->tx_ring;

2301

struct skge_ring *ring = &skge->tx_ring;

2300

struct skge_element *e;

2302

struct skge_element *e;

2301

struct skge_tx_desc *td;

2303

struct skge_tx_desc *td;

2302

int i;

2304

int i;

2303

u32 control, len;

2305

u32 control, len;

2304

u64 map;

2306

u64 map;

2305

2307

2306

skb = skb_padto(skb, ETH_ZLEN);

2308

skb = skb_padto(skb, ETH_ZLEN);

2307

if (!skb)

2309

if (!skb)

2308

return NETDEV_TX_OK;

2310

return NETDEV_TX_OK;

2309

2311

2310

if (!spin_trylock(&skge->tx_lock)) {

2312

if (!spin_trylock(&skge->tx_lock)) {

2311

/* Collision - tell upper layer to requeue */

2313

/* Collision - tell upper layer to requeue */

2312

return NETDEV_TX_LOCKED;

2314

return NETDEV_TX_LOCKED;

2313

}

2315

}

2314

2316

2315

if (unlikely(skge->tx_avail < skb_shinfo(skb)->nr_frags +1)) {

2317

if (unlikely(skge->tx_avail < skb_shinfo(skb)->nr_frags +1)) {

2316

if (!netif_queue_stopped(dev)) {

2318

if (!netif_queue_stopped(dev)) {

2317

netif_stop_queue(dev);

2319

netif_stop_queue(dev);

2318

2320

2319

printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",

2321

printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",

2320

dev->name);

2322

dev->name);

2321

}

2323

}

2322

spin_unlock(&skge->tx_lock);

2324

spin_unlock(&skge->tx_lock);

2323

return NETDEV_TX_BUSY;

2325

return NETDEV_TX_BUSY;

2324

}

2326

}

2325

2327

2326

e = ring->to_use;

2328

e = ring->to_use;

2327

td = e->desc;

2329

td = e->desc;

2328

e->skb = skb;

2330

e->skb = skb;

2329

len = skb_headlen(skb);

2331

len = skb_headlen(skb);

2330

map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);

2332

map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);

2331

pci_unmap_addr_set(e, mapaddr, map);

2333

pci_unmap_addr_set(e, mapaddr, map);

2332

pci_unmap_len_set(e, maplen, len);

2334

pci_unmap_len_set(e, maplen, len);

2333

2335

2334

td->dma_lo = map;

2336

td->dma_lo = map;

2335

td->dma_hi = map >> 32;

2337

td->dma_hi = map >> 32;

2336

2338

2337

if (skb->ip_summed == CHECKSUM_HW) {

2339

if (skb->ip_summed == CHECKSUM_HW) {

2338

int offset = skb->h.raw - skb->data;

2340

int offset = skb->h.raw - skb->data;

2339

2341

2340

/* This seems backwards, but it is what the sk98lin

2342

/* This seems backwards, but it is what the sk98lin

2341

* does. Looks like hardware is wrong?

2343

* does. Looks like hardware is wrong?

2342

*/

2344

*/

2343

if (skb->h.ipiph->protocol == IPPROTO_UDP

2345

if (skb->h.ipiph->protocol == IPPROTO_UDP

2344

&& hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)

2346

&& hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)

2345

control = BMU_TCP_CHECK;

2347

control = BMU_TCP_CHECK;

2346

else

2348

else

2347

control = BMU_UDP_CHECK;

2349

control = BMU_UDP_CHECK;

2348

2350

2349

td->csum_offs = 0;

2351

td->csum_offs = 0;

2350

td->csum_start = offset;

2352

td->csum_start = offset;

2351

td->csum_write = offset + skb->csum;

2353

td->csum_write = offset + skb->csum;

2352

} else

2354

} else

2353

control = BMU_CHECK;

2355

control = BMU_CHECK;

2354

2356

2355

if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */

2357

if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */

2356

control |= BMU_EOF| BMU_IRQ_EOF;

2358

control |= BMU_EOF| BMU_IRQ_EOF;

2357

else {

2359

else {

2358

struct skge_tx_desc *tf = td;

2360

struct skge_tx_desc *tf = td;

2359

2361

2360

control |= BMU_STFWD;

2362

control |= BMU_STFWD;

2361

for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {

2363

for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {

2362

skb_frag_t *frag = &skb_shinfo(skb)->frags[i];

2364

skb_frag_t *frag = &skb_shinfo(skb)->frags[i];

2363

2365

2364

map = pci_map_page(hw->pdev, frag->page, frag->page_offset,

2366

map = pci_map_page(hw->pdev, frag->page, frag->page_offset,

2365

frag->size, PCI_DMA_TODEVICE);

2367

frag->size, PCI_DMA_TODEVICE);

2366

2368

2367

e = e->next;

2369

e = e->next;

2368

e->skb = NULL;

2370

e->skb = NULL;

2369

tf = e->desc;

2371

tf = e->desc;

2370

tf->dma_lo = map;

2372

tf->dma_lo = map;

2371

tf->dma_hi = (u64) map >> 32;

2373

tf->dma_hi = (u64) map >> 32;

2372

pci_unmap_addr_set(e, mapaddr, map);

2374

pci_unmap_addr_set(e, mapaddr, map);

2373

pci_unmap_len_set(e, maplen, frag->size);

2375

pci_unmap_len_set(e, maplen, frag->size);

2374

2376

2375

tf->control = BMU_OWN | BMU_SW | control | frag->size;

2377

tf->control = BMU_OWN | BMU_SW | control | frag->size;

2376

}

2378

}

2377

tf->control |= BMU_EOF | BMU_IRQ_EOF;

2379

tf->control |= BMU_EOF | BMU_IRQ_EOF;

2378

}

2380

}

2379

/* Make sure all the descriptors written */

2381

/* Make sure all the descriptors written */

2380

wmb();

2382

wmb();

2381

td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;

2383

td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;

2382

wmb();

2384

wmb();

2383

2385

2384

skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);

2386

skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);

2385

2387

2386

if (netif_msg_tx_queued(skge))

2388

if (netif_msg_tx_queued(skge))

2387

printk(KERN_DEBUG "%s: tx queued, slot %td, len %d\n",

2389

printk(KERN_DEBUG "%s: tx queued, slot %td, len %d\n",

2388

dev->name, e - ring->start, skb->len);

2390

dev->name, e - ring->start, skb->len);

2389

2391

2390

ring->to_use = e->next;

2392

ring->to_use = e->next;

2391

skge->tx_avail -= skb_shinfo(skb)->nr_frags + 1;

2393

skge->tx_avail -= skb_shinfo(skb)->nr_frags + 1;

2392

if (skge->tx_avail <= MAX_SKB_FRAGS + 1) {

2394

if (skge->tx_avail <= MAX_SKB_FRAGS + 1) {

2393

pr_debug("%s: transmit queue full\n", dev->name);

2395

pr_debug("%s: transmit queue full\n", dev->name);

2394

netif_stop_queue(dev);

2396

netif_stop_queue(dev);

2395

}

2397

}

2396

2398

2397

mmiowb();

2399

mmiowb();

2398

spin_unlock(&skge->tx_lock);

2400

spin_unlock(&skge->tx_lock);

2399

2401

2400

dev->trans_start = jiffies;

2402

dev->trans_start = jiffies;

2401

2403

2402

return NETDEV_TX_OK;

2404

return NETDEV_TX_OK;

2403

}

2405

}

2404

2406

2405

static inline void skge_tx_free(struct skge_hw *hw, struct skge_element *e)

2407

static inline void skge_tx_free(struct skge_hw *hw, struct skge_element *e)

2406

{

2408

{

2407

/* This ring element can be skb or fragment */

2409

/* This ring element can be skb or fragment */

2408

if (e->skb) {

2410

if (e->skb) {

2409

pci_unmap_single(hw->pdev,

2411

pci_unmap_single(hw->pdev,

2410

pci_unmap_addr(e, mapaddr),

2412

pci_unmap_addr(e, mapaddr),

2411

pci_unmap_len(e, maplen),

2413

pci_unmap_len(e, maplen),

2412

PCI_DMA_TODEVICE);

2414

PCI_DMA_TODEVICE);

2413

dev_kfree_skb(e->skb);

2415

dev_kfree_skb(e->skb);

2414

e->skb = NULL;

2416

e->skb = NULL;

2415

} else {

2417

} else {

2416

pci_unmap_page(hw->pdev,

2418

pci_unmap_page(hw->pdev,

2417

pci_unmap_addr(e, mapaddr),

2419

pci_unmap_addr(e, mapaddr),

2418

pci_unmap_len(e, maplen),

2420

pci_unmap_len(e, maplen),

2419

PCI_DMA_TODEVICE);

2421

PCI_DMA_TODEVICE);

2420

}

2422

}

2421

}

2423

}

2422

2424

2423

static void skge_tx_clean(struct skge_port *skge)

2425

static void skge_tx_clean(struct skge_port *skge)

2424

{

2426

{

2425

struct skge_ring *ring = &skge->tx_ring;

2427

struct skge_ring *ring = &skge->tx_ring;

2426

struct skge_element *e;

2428

struct skge_element *e;

2427

2429

2428

spin_lock_bh(&skge->tx_lock);

2430

spin_lock_bh(&skge->tx_lock);

2429

for (e = ring->to_clean; e != ring->to_use; e = e->next) {

2431

for (e = ring->to_clean; e != ring->to_use; e = e->next) {

2430

++skge->tx_avail;

2432

++skge->tx_avail;

2431

skge_tx_free(skge->hw, e);

2433

skge_tx_free(skge->hw, e);

2432

}

2434

}

2433

ring->to_clean = e;

2435

ring->to_clean = e;

2434

spin_unlock_bh(&skge->tx_lock);

2436

spin_unlock_bh(&skge->tx_lock);

2435

}

2437

}

2436

2438

2437

static void skge_tx_timeout(struct net_device *dev)

2439

static void skge_tx_timeout(struct net_device *dev)

2438

{

2440

{

2439

struct skge_port *skge = netdev_priv(dev);

2441

struct skge_port *skge = netdev_priv(dev);

2440

2442

2441

if (netif_msg_timer(skge))

2443

if (netif_msg_timer(skge))

2442

printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name);

2444

printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name);

2443

2445

2444

skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);

2446

skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);

2445

skge_tx_clean(skge);

2447

skge_tx_clean(skge);

2446

}

2448

}

2447

2449

2448

static int skge_change_mtu(struct net_device *dev, int new_mtu)

2450

static int skge_change_mtu(struct net_device *dev, int new_mtu)

2449

{

2451

{

2450

int err;

2452

int err;

2451

2453

2452

if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)

2454

if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)

2453

return -EINVAL;

2455

return -EINVAL;

2454

2456

2455

if (!netif_running(dev)) {

2457

if (!netif_running(dev)) {

2456

dev->mtu = new_mtu;

2458

dev->mtu = new_mtu;

2457

return 0;

2459

return 0;

2458

}

2460

}

2459

2461

2460

skge_down(dev);

2462

skge_down(dev);

2461

2463

2462

dev->mtu = new_mtu;

2464

dev->mtu = new_mtu;

2463

2465

2464

err = skge_up(dev);

2466

err = skge_up(dev);

2465

if (err)

2467

if (err)

2466

dev_close(dev);

2468

dev_close(dev);

2467

2469

2468

return err;

2470

return err;

2469

}

2471

}

2470

2472

2471

static void genesis_set_multicast(struct net_device *dev)

2473

static void genesis_set_multicast(struct net_device *dev)

2472

{

2474

{

2473

struct skge_port *skge = netdev_priv(dev);

2475

struct skge_port *skge = netdev_priv(dev);

2474

struct skge_hw *hw = skge->hw;

2476

struct skge_hw *hw = skge->hw;

2475

int port = skge->port;

2477

int port = skge->port;

2476

int i, count = dev->mc_count;

2478

int i, count = dev->mc_count;

2477

struct dev_mc_list *list = dev->mc_list;

2479

struct dev_mc_list *list = dev->mc_list;

2478

u32 mode;

2480

u32 mode;

2479

u8 filter[8];

2481

u8 filter[8];

2480

2482

2481

mode = xm_read32(hw, port, XM_MODE);

2483

mode = xm_read32(hw, port, XM_MODE);

2482

mode |= XM_MD_ENA_HASH;

2484

mode |= XM_MD_ENA_HASH;

2483

if (dev->flags & IFF_PROMISC)

2485

if (dev->flags & IFF_PROMISC)

2484

mode |= XM_MD_ENA_PROM;

2486

mode |= XM_MD_ENA_PROM;

2485

else

2487

else

2486

mode &= ~XM_MD_ENA_PROM;

2488

mode &= ~XM_MD_ENA_PROM;

2487

2489

2488

if (dev->flags & IFF_ALLMULTI)

2490

if (dev->flags & IFF_ALLMULTI)

2489

memset(filter, 0xff, sizeof(filter));

2491

memset(filter, 0xff, sizeof(filter));

2490

else {

2492

else {

2491

memset(filter, 0, sizeof(filter));

2493

memset(filter, 0, sizeof(filter));

2492

for (i = 0; list && i < count; i++, list = list->next) {

2494

for (i = 0; list && i < count; i++, list = list->next) {

2493

u32 crc, bit;

2495

u32 crc, bit;

2494

crc = ether_crc_le(ETH_ALEN, list->dmi_addr);

2496

crc = ether_crc_le(ETH_ALEN, list->dmi_addr);

2495

bit = ~crc & 0x3f;

2497

bit = ~crc & 0x3f;

2496

filter[bit/8] |= 1 << (bit%8);

2498

filter[bit/8] |= 1 << (bit%8);

2497

}

2499

}

2498

}

2500

}

2499

2501

2500

xm_write32(hw, port, XM_MODE, mode);

2502

xm_write32(hw, port, XM_MODE, mode);

2501

xm_outhash(hw, port, XM_HSM, filter);

2503

xm_outhash(hw, port, XM_HSM, filter);

2502

}

2504

}

2503

2505

2504

static void yukon_set_multicast(struct net_device *dev)

2506

static void yukon_set_multicast(struct net_device *dev)

2505

{

2507

{

2506

struct skge_port *skge = netdev_priv(dev);

2508

struct skge_port *skge = netdev_priv(dev);

2507

struct skge_hw *hw = skge->hw;

2509

struct skge_hw *hw = skge->hw;

2508

int port = skge->port;

2510

int port = skge->port;

2509

struct dev_mc_list *list = dev->mc_list;

2511

struct dev_mc_list *list = dev->mc_list;

2510

u16 reg;

2512

u16 reg;

2511

u8 filter[8];

2513

u8 filter[8];

2512

2514

2513

memset(filter, 0, sizeof(filter));

2515

memset(filter, 0, sizeof(filter));

2514

2516

2515

reg = gma_read16(hw, port, GM_RX_CTRL);

2517

reg = gma_read16(hw, port, GM_RX_CTRL);

2516

reg |= GM_RXCR_UCF_ENA;

2518

reg |= GM_RXCR_UCF_ENA;

2517

2519

2518

if (dev->flags & IFF_PROMISC) /* promiscuous */

2520

if (dev->flags & IFF_PROMISC) /* promiscuous */

2519

reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);

2521

reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);

2520

else if (dev->flags & IFF_ALLMULTI) /* all multicast */

2522

else if (dev->flags & IFF_ALLMULTI) /* all multicast */

2521

memset(filter, 0xff, sizeof(filter));

2523

memset(filter, 0xff, sizeof(filter));

2522

else if (dev->mc_count == 0) /* no multicast */

2524

else if (dev->mc_count == 0) /* no multicast */

2523

reg &= ~GM_RXCR_MCF_ENA;

2525

reg &= ~GM_RXCR_MCF_ENA;

2524

else {

2526

else {

2525

int i;

2527

int i;

2526

reg |= GM_RXCR_MCF_ENA;

2528

reg |= GM_RXCR_MCF_ENA;

2527

2529

2528

for (i = 0; list && i < dev->mc_count; i++, list = list->next) {

2530

for (i = 0; list && i < dev->mc_count; i++, list = list->next) {

2529

u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;

2531

u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;

2530

filter[bit/8] |= 1 << (bit%8);

2532

filter[bit/8] |= 1 << (bit%8);

2531

}

2533

}

2532

}

2534

}

2533

2535

2534

2536

2535

gma_write16(hw, port, GM_MC_ADDR_H1,

2537

gma_write16(hw, port, GM_MC_ADDR_H1,

2536

(u16)filter[0] | ((u16)filter[1] << 8));

2538

(u16)filter[0] | ((u16)filter[1] << 8));

2537

gma_write16(hw, port, GM_MC_ADDR_H2,

2539

gma_write16(hw, port, GM_MC_ADDR_H2,

2538

(u16)filter[2] | ((u16)filter[3] << 8));

2540

(u16)filter[2] | ((u16)filter[3] << 8));

2539

gma_write16(hw, port, GM_MC_ADDR_H3,

2541

gma_write16(hw, port, GM_MC_ADDR_H3,

2540

(u16)filter[4] | ((u16)filter[5] << 8));

2542

(u16)filter[4] | ((u16)filter[5] << 8));

2541

gma_write16(hw, port, GM_MC_ADDR_H4,

2543

gma_write16(hw, port, GM_MC_ADDR_H4,

2542

(u16)filter[6] | ((u16)filter[7] << 8));

2544

(u16)filter[6] | ((u16)filter[7] << 8));

2543

2545

2544

gma_write16(hw, port, GM_RX_CTRL, reg);

2546

gma_write16(hw, port, GM_RX_CTRL, reg);

2545

}

2547

}

2546

2548

2547

static inline u16 phy_length(const struct skge_hw *hw, u32 status)

2549

static inline u16 phy_length(const struct skge_hw *hw, u32 status)

2548

{

2550

{

2549

if (hw->chip_id == CHIP_ID_GENESIS)

2551

if (hw->chip_id == CHIP_ID_GENESIS)

2550

return status >> XMR_FS_LEN_SHIFT;

2552

return status >> XMR_FS_LEN_SHIFT;

2551

else

2553

else

2552

return status >> GMR_FS_LEN_SHIFT;

2554

return status >> GMR_FS_LEN_SHIFT;

2553

}

2555

}

2554

2556

2555

static inline int bad_phy_status(const struct skge_hw *hw, u32 status)

2557

static inline int bad_phy_status(const struct skge_hw *hw, u32 status)

2556

{

2558

{

2557

if (hw->chip_id == CHIP_ID_GENESIS)

2559

if (hw->chip_id == CHIP_ID_GENESIS)

2558

return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;

2560

return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;

2559

else

2561

else

2560

return (status & GMR_FS_ANY_ERR) ||

2562

return (status & GMR_FS_ANY_ERR) ||

2561

(status & GMR_FS_RX_OK) == 0;

2563

(status & GMR_FS_RX_OK) == 0;

2562

}

2564

}

2563

2565

2564

2566

2565

/* Get receive buffer from descriptor.

2567

/* Get receive buffer from descriptor.

2566

* Handles copy of small buffers and reallocation failures

2568

* Handles copy of small buffers and reallocation failures

2567

*/

2569

*/

2568

static inline struct sk_buff *skge_rx_get(struct skge_port *skge,

2570

static inline struct sk_buff *skge_rx_get(struct skge_port *skge,

2569

struct skge_element *e,

2571

struct skge_element *e,

2570

u32 control, u32 status, u16 csum)

2572

u32 control, u32 status, u16 csum)

2571

{

2573

{

2572

struct sk_buff *skb;

2574

struct sk_buff *skb;

2573

u16 len = control & BMU_BBC;

2575

u16 len = control & BMU_BBC;

2574

2576

2575

if (unlikely(netif_msg_rx_status(skge)))

2577

if (unlikely(netif_msg_rx_status(skge)))

2576

printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",

2578

printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",

2577

skge->netdev->name, e - skge->rx_ring.start,

2579

skge->netdev->name, e - skge->rx_ring.start,

2578

status, len);

2580

status, len);

2579

2581

2580

if (len > skge->rx_buf_size)

2582

if (len > skge->rx_buf_size)

2581

goto error;

2583

goto error;

2582

2584

2583

if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))

2585

if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))

2584

goto error;

2586

goto error;

2585

2587

2586

if (bad_phy_status(skge->hw, status))

2588

if (bad_phy_status(skge->hw, status))

2587

goto error;

2589

goto error;

2588

2590

2589

if (phy_length(skge->hw, status) != len)

2591

if (phy_length(skge->hw, status) != len)

2590

goto error;

2592

goto error;

2591

2593

2592

if (len < RX_COPY_THRESHOLD) {

2594

if (len < RX_COPY_THRESHOLD) {

2593

skb = dev_alloc_skb(len + 2);

2595

skb = dev_alloc_skb(len + 2);

2594

if (!skb)

2596

if (!skb)

2595

goto resubmit;

2597

goto resubmit;

2596

2598

2597

skb_reserve(skb, 2);

2599

skb_reserve(skb, 2);

2598

pci_dma_sync_single_for_cpu(skge->hw->pdev,

2600

pci_dma_sync_single_for_cpu(skge->hw->pdev,

2599

pci_unmap_addr(e, mapaddr),

2601

pci_unmap_addr(e, mapaddr),

2600

len, PCI_DMA_FROMDEVICE);

2602

len, PCI_DMA_FROMDEVICE);

2601

memcpy(skb->data, e->skb->data, len);

2603

memcpy(skb->data, e->skb->data, len);

2602

pci_dma_sync_single_for_device(skge->hw->pdev,

2604

pci_dma_sync_single_for_device(skge->hw->pdev,

2603

pci_unmap_addr(e, mapaddr),

2605

pci_unmap_addr(e, mapaddr),

2604

len, PCI_DMA_FROMDEVICE);

2606

len, PCI_DMA_FROMDEVICE);

2605

skge_rx_reuse(e, skge->rx_buf_size);

2607

skge_rx_reuse(e, skge->rx_buf_size);

2606

} else {

2608

} else {

2607

struct sk_buff *nskb;

2609

struct sk_buff *nskb;

2608

nskb = dev_alloc_skb(skge->rx_buf_size + NET_IP_ALIGN);

2610

nskb = dev_alloc_skb(skge->rx_buf_size + NET_IP_ALIGN);

2609

if (!nskb)

2611

if (!nskb)

2610

goto resubmit;

2612

goto resubmit;

2611

2613

2612

pci_unmap_single(skge->hw->pdev,

2614

pci_unmap_single(skge->hw->pdev,

2613

pci_unmap_addr(e, mapaddr),

2615

pci_unmap_addr(e, mapaddr),

2614

pci_unmap_len(e, maplen),

2616

pci_unmap_len(e, maplen),

2615

PCI_DMA_FROMDEVICE);

2617

PCI_DMA_FROMDEVICE);

2616

skb = e->skb;

2618

skb = e->skb;

2617

prefetch(skb->data);

2619

prefetch(skb->data);

2618

skge_rx_setup(skge, e, nskb, skge->rx_buf_size);

2620

skge_rx_setup(skge, e, nskb, skge->rx_buf_size);

2619

}

2621

}

2620

2622

2621

skb_put(skb, len);

2623

skb_put(skb, len);

2622

skb->dev = skge->netdev;

2624

skb->dev = skge->netdev;

2623

if (skge->rx_csum) {

2625

if (skge->rx_csum) {

2624

skb->csum = csum;

2626

skb->csum = csum;

2625

skb->ip_summed = CHECKSUM_HW;

2627

skb->ip_summed = CHECKSUM_HW;

2626

}

2628

}

2627

2629

2628

skb->protocol = eth_type_trans(skb, skge->netdev);

2630

skb->protocol = eth_type_trans(skb, skge->netdev);

2629

2631

2630

return skb;

2632

return skb;

2631

error:

2633

error:

2632

2634

2633

if (netif_msg_rx_err(skge))

2635

if (netif_msg_rx_err(skge))

2634

printk(KERN_DEBUG PFX "%s: rx err, slot %td control 0x%x status 0x%x\n",

2636

printk(KERN_DEBUG PFX "%s: rx err, slot %td control 0x%x status 0x%x\n",

2635

skge->netdev->name, e - skge->rx_ring.start,

2637

skge->netdev->name, e - skge->rx_ring.start,

2636

control, status);

2638

control, status);

2637

2639

2638

if (skge->hw->chip_id == CHIP_ID_GENESIS) {

2640

if (skge->hw->chip_id == CHIP_ID_GENESIS) {

2639

if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))

2641

if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))

2640

skge->net_stats.rx_length_errors++;

2642

skge->net_stats.rx_length_errors++;

2641

if (status & XMR_FS_FRA_ERR)

2643

if (status & XMR_FS_FRA_ERR)

2642

skge->net_stats.rx_frame_errors++;

2644

skge->net_stats.rx_frame_errors++;

2643

if (status & XMR_FS_FCS_ERR)

2645

if (status & XMR_FS_FCS_ERR)

2644

skge->net_stats.rx_crc_errors++;

2646

skge->net_stats.rx_crc_errors++;

2645

} else {

2647

} else {

2646

if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))

2648

if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))

2647

skge->net_stats.rx_length_errors++;

2649

skge->net_stats.rx_length_errors++;

2648

if (status & GMR_FS_FRAGMENT)

2650

if (status & GMR_FS_FRAGMENT)

2649

skge->net_stats.rx_frame_errors++;

2651

skge->net_stats.rx_frame_errors++;

2650

if (status & GMR_FS_CRC_ERR)

2652

if (status & GMR_FS_CRC_ERR)

2651

skge->net_stats.rx_crc_errors++;

2653

skge->net_stats.rx_crc_errors++;

2652

}

2654

}

2653

2655

2654

resubmit:

2656

resubmit:

2655

skge_rx_reuse(e, skge->rx_buf_size);

2657

skge_rx_reuse(e, skge->rx_buf_size);

2656

return NULL;

2658

return NULL;

2657

}

2659

}

2658

2660

2659

static void skge_tx_done(struct skge_port *skge)

2661

static void skge_tx_done(struct skge_port *skge)

2660

{

2662

{

2661

struct skge_ring *ring = &skge->tx_ring;

2663

struct skge_ring *ring = &skge->tx_ring;

2662

struct skge_element *e;

2664

struct skge_element *e;

2663

2665

2664

spin_lock(&skge->tx_lock);

2666

spin_lock(&skge->tx_lock);

2665

for (e = ring->to_clean; prefetch(e->next), e != ring->to_use; e = e->next) {

2667

for (e = ring->to_clean; prefetch(e->next), e != ring->to_use; e = e->next) {

2666

struct skge_tx_desc *td = e->desc;

2668

struct skge_tx_desc *td = e->desc;

2667

u32 control;

2669

u32 control;

2668

2670

2669

rmb();

2671

rmb();

2670

control = td->control;

2672

control = td->control;

2671

if (control & BMU_OWN)

2673

if (control & BMU_OWN)

2672

break;

2674

break;

2673

2675

2674

if (unlikely(netif_msg_tx_done(skge)))

2676

if (unlikely(netif_msg_tx_done(skge)))

2675

printk(KERN_DEBUG PFX "%s: tx done slot %td status 0x%x\n",

2677

printk(KERN_DEBUG PFX "%s: tx done slot %td status 0x%x\n",

2676

skge->netdev->name, e - ring->start, td->status);

2678

skge->netdev->name, e - ring->start, td->status);

2677

2679

2678

skge_tx_free(skge->hw, e);

2680

skge_tx_free(skge->hw, e);

2679

e->skb = NULL;

2681

e->skb = NULL;

2680

++skge->tx_avail;

2682

++skge->tx_avail;

2681

}

2683

}

2682

ring->to_clean = e;

2684

ring->to_clean = e;

2683

skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);

2685

skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);

2684

2686

2685

if (skge->tx_avail > MAX_SKB_FRAGS + 1)

2687

if (skge->tx_avail > MAX_SKB_FRAGS + 1)

2686

netif_wake_queue(skge->netdev);

2688

netif_wake_queue(skge->netdev);

2687

2689

2688

spin_unlock(&skge->tx_lock);

2690

spin_unlock(&skge->tx_lock);

2689

}

2691

}

2690

2692

2691

static int skge_poll(struct net_device *dev, int *budget)

2693

static int skge_poll(struct net_device *dev, int *budget)

2692

{

2694

{

2693

struct skge_port *skge = netdev_priv(dev);

2695

struct skge_port *skge = netdev_priv(dev);

2694

struct skge_hw *hw = skge->hw;

2696

struct skge_hw *hw = skge->hw;

2695

struct skge_ring *ring = &skge->rx_ring;

2697

struct skge_ring *ring = &skge->rx_ring;

2696

struct skge_element *e;

2698

struct skge_element *e;

2697

int to_do = min(dev->quota, *budget);

2699

int to_do = min(dev->quota, *budget);

2698

int work_done = 0;

2700

int work_done = 0;

2699

2701

2700

skge_tx_done(skge);

2702

skge_tx_done(skge);

2701

2703

2702

for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) {

2704

for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) {

2703

struct skge_rx_desc *rd = e->desc;

2705

struct skge_rx_desc *rd = e->desc;

2704

struct sk_buff *skb;

2706

struct sk_buff *skb;

2705

u32 control;

2707

u32 control;

2706

2708

2707

rmb();

2709

rmb();

2708

control = rd->control;

2710

control = rd->control;

2709

if (control & BMU_OWN)

2711

if (control & BMU_OWN)

2710

break;

2712

break;

2711

2713

2712

skb = skge_rx_get(skge, e, control, rd->status,

2714

skb = skge_rx_get(skge, e, control, rd->status,

2713

le16_to_cpu(rd->csum2));

2715

le16_to_cpu(rd->csum2));

2714

if (likely(skb)) {

2716

if (likely(skb)) {

2715

dev->last_rx = jiffies;

2717

dev->last_rx = jiffies;

2716

netif_receive_skb(skb);

2718

netif_receive_skb(skb);

2717

2719

2718

++work_done;

2720

++work_done;

2719

} else

2721

} else

2720

skge_rx_reuse(e, skge->rx_buf_size);

2722

skge_rx_reuse(e, skge->rx_buf_size);

2721

}

2723

}

2722

ring->to_clean = e;

2724

ring->to_clean = e;

2723

2725

2724

/* restart receiver */

2726

/* restart receiver */

2725

wmb();

2727

wmb();

2726

skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);

2728

skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);

2727

2729

2728

*budget -= work_done;

2730

*budget -= work_done;

2729

dev->quota -= work_done;

2731

dev->quota -= work_done;

2730

2732

2731

if (work_done >= to_do)

2733

if (work_done >= to_do)

2732

return 1; /* not done */

2734

return 1; /* not done */

2733

2735

2734

netif_rx_complete(dev);

2736

netif_rx_complete(dev);

2735

mmiowb();

2737

mmiowb();

2736

2738

2737

hw->intr_mask |= skge->port == 0 ? (IS_R1_F|IS_XA1_F) : (IS_R2_F|IS_XA2_F);

2739

hw->intr_mask |= skge->port == 0 ? (IS_R1_F|IS_XA1_F) : (IS_R2_F|IS_XA2_F);

2738

skge_write32(hw, B0_IMSK, hw->intr_mask);

2740

skge_write32(hw, B0_IMSK, hw->intr_mask);

2739

2741

2740

return 0;

2742

return 0;

2741

}

2743

}

2742

2744

2743

/* Parity errors seem to happen when Genesis is connected to a switch

2745

/* Parity errors seem to happen when Genesis is connected to a switch

2744

* with no other ports present. Heartbeat error??

2746

* with no other ports present. Heartbeat error??

2745

*/

2747

*/

2746

static void skge_mac_parity(struct skge_hw *hw, int port)

2748

static void skge_mac_parity(struct skge_hw *hw, int port)

2747

{

2749

{

2748

struct net_device *dev = hw->dev[port];

2750

struct net_device *dev = hw->dev[port];

2749

2751

2750

if (dev) {

2752

if (dev) {

2751

struct skge_port *skge = netdev_priv(dev);

2753

struct skge_port *skge = netdev_priv(dev);

2752

++skge->net_stats.tx_heartbeat_errors;

2754

++skge->net_stats.tx_heartbeat_errors;

2753

}

2755

}

2754

2756

2755

if (hw->chip_id == CHIP_ID_GENESIS)

2757

if (hw->chip_id == CHIP_ID_GENESIS)

2756

skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),

2758

skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),

2757

MFF_CLR_PERR);

2759

MFF_CLR_PERR);

2758

else

2760

else

2759

/* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */

2761

/* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */

2760

skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),

2762

skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),

2761

(hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)

2763

(hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)

2762

? GMF_CLI_TX_FC : GMF_CLI_TX_PE);

2764

? GMF_CLI_TX_FC : GMF_CLI_TX_PE);

2763

}

2765

}

2764

2766

2765

static void skge_pci_clear(struct skge_hw *hw)

2767

static void skge_pci_clear(struct skge_hw *hw)

2766

{

2768

{

2767

u16 status;

2769

u16 status;

2768

2770

2769

pci_read_config_word(hw->pdev, PCI_STATUS, &status);

2771

pci_read_config_word(hw->pdev, PCI_STATUS, &status);

2770

skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);

2772

skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);

2771

pci_write_config_word(hw->pdev, PCI_STATUS,

2773

pci_write_config_word(hw->pdev, PCI_STATUS,

2772

status | PCI_STATUS_ERROR_BITS);

2774

status | PCI_STATUS_ERROR_BITS);

2773

skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);

2775

skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);

2774

}

2776

}

2775

2777

2776

static void skge_mac_intr(struct skge_hw *hw, int port)

2778

static void skge_mac_intr(struct skge_hw *hw, int port)

2777

{

2779

{

2778

if (hw->chip_id == CHIP_ID_GENESIS)

2780

if (hw->chip_id == CHIP_ID_GENESIS)

2779

genesis_mac_intr(hw, port);

2781

genesis_mac_intr(hw, port);

2780

else

2782

else

2781

yukon_mac_intr(hw, port);

2783

yukon_mac_intr(hw, port);

2782

}

2784

}

2783

2785

2784

/* Handle device specific framing and timeout interrupts */

2786

/* Handle device specific framing and timeout interrupts */

2785

static void skge_error_irq(struct skge_hw *hw)

2787

static void skge_error_irq(struct skge_hw *hw)

2786

{

2788

{

2787

u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);

2789

u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);

2788

2790

2789

if (hw->chip_id == CHIP_ID_GENESIS) {

2791

if (hw->chip_id == CHIP_ID_GENESIS) {

2790

/* clear xmac errors */

2792

/* clear xmac errors */

2791

if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))

2793

if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))

2792

skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);

2794

skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);

2793

if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))

2795

if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))

2794

skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);

2796

skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);

2795

} else {

2797

} else {

2796

/* Timestamp (unused) overflow */

2798

/* Timestamp (unused) overflow */

2797

if (hwstatus & IS_IRQ_TIST_OV)

2799

if (hwstatus & IS_IRQ_TIST_OV)

2798

skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);

2800

skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);

2799

}

2801

}

2800

2802

2801

if (hwstatus & IS_RAM_RD_PAR) {

2803

if (hwstatus & IS_RAM_RD_PAR) {

2802

printk(KERN_ERR PFX "Ram read data parity error\n");

2804

printk(KERN_ERR PFX "Ram read data parity error\n");

2803

skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);

2805

skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);

2804

}

2806

}

2805

2807

2806

if (hwstatus & IS_RAM_WR_PAR) {

2808

if (hwstatus & IS_RAM_WR_PAR) {

2807

printk(KERN_ERR PFX "Ram write data parity error\n");

2809

printk(KERN_ERR PFX "Ram write data parity error\n");

2808

skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);

2810

skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);

2809

}

2811

}

2810

2812

2811

if (hwstatus & IS_M1_PAR_ERR)

2813

if (hwstatus & IS_M1_PAR_ERR)

2812

skge_mac_parity(hw, 0);

2814

skge_mac_parity(hw, 0);

2813

2815

2814

if (hwstatus & IS_M2_PAR_ERR)

2816

if (hwstatus & IS_M2_PAR_ERR)

2815

skge_mac_parity(hw, 1);

2817

skge_mac_parity(hw, 1);

2816

2818

2817

if (hwstatus & IS_R1_PAR_ERR)

2819

if (hwstatus & IS_R1_PAR_ERR)

2818

skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);

2820

skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);

2819

2821

2820

if (hwstatus & IS_R2_PAR_ERR)

2822

if (hwstatus & IS_R2_PAR_ERR)

2821

skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);

2823

skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);

2822

2824

2823

if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {

2825

if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {

2824

printk(KERN_ERR PFX "hardware error detected (status 0x%x)\n",

2826

printk(KERN_ERR PFX "hardware error detected (status 0x%x)\n",

2825

hwstatus);

2827

hwstatus);

2826

2828

2827

skge_pci_clear(hw);

2829

skge_pci_clear(hw);

2828

2830

2829

/* if error still set then just ignore it */

2831

/* if error still set then just ignore it */

2830

hwstatus = skge_read32(hw, B0_HWE_ISRC);

2832

hwstatus = skge_read32(hw, B0_HWE_ISRC);

2831

if (hwstatus & IS_IRQ_STAT) {

2833

if (hwstatus & IS_IRQ_STAT) {

2832

pr_debug("IRQ status %x: still set ignoring hardware errors\n",

2834

pr_debug("IRQ status %x: still set ignoring hardware errors\n",

2833

hwstatus);

2835

hwstatus);

2834

hw->intr_mask &= ~IS_HW_ERR;

2836

hw->intr_mask &= ~IS_HW_ERR;

2835

}

2837

}

2836

}

2838

}

2837

}

2839

}

2838

2840

2839

/*

2841

/*

2840

* Interrupt from PHY are handled in tasklet (soft irq)

2842

* Interrupt from PHY are handled in tasklet (soft irq)

2841

* because accessing phy registers requires spin wait which might

2843

* because accessing phy registers requires spin wait which might

2842

* cause excess interrupt latency.

2844

* cause excess interrupt latency.

2843

*/

2845

*/

2844

static void skge_extirq(unsigned long data)

2846

static void skge_extirq(unsigned long data)

2845

{

2847

{

2846

struct skge_hw *hw = (struct skge_hw *) data;

2848

struct skge_hw *hw = (struct skge_hw *) data;

2847

int port;

2849

int port;

2848

2850

2849

spin_lock(&hw->phy_lock);

2851

spin_lock(&hw->phy_lock);

2850

for (port = 0; port < hw->ports; port++) {

2852

for (port = 0; port < hw->ports; port++) {

2851

struct net_device *dev = hw->dev[port];

2853

struct net_device *dev = hw->dev[port];

2852

struct skge_port *skge = netdev_priv(dev);

2854

struct skge_port *skge = netdev_priv(dev);

2853

2855

2854

if (netif_running(dev)) {

2856

if (netif_running(dev)) {

2855

if (hw->chip_id != CHIP_ID_GENESIS)

2857

if (hw->chip_id != CHIP_ID_GENESIS)

2856

yukon_phy_intr(skge);

2858

yukon_phy_intr(skge);

2857

else

2859

else

2858

bcom_phy_intr(skge);

2860

bcom_phy_intr(skge);

2859

}

2861

}

2860

}

2862

}

2861

spin_unlock(&hw->phy_lock);

2863

spin_unlock(&hw->phy_lock);

2862

2864

2863

hw->intr_mask |= IS_EXT_REG;

2865

hw->intr_mask |= IS_EXT_REG;

2864

skge_write32(hw, B0_IMSK, hw->intr_mask);

2866

skge_write32(hw, B0_IMSK, hw->intr_mask);

2865

}

2867

}

2866

2868

2867

static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)

2869

static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)

2868

{

2870

{

2869

struct skge_hw *hw = dev_id;

2871

struct skge_hw *hw = dev_id;

2870

u32 status;

2872

u32 status;

2871

2873

2872

/* Reading this register masks IRQ */

2874

/* Reading this register masks IRQ */

2873

status = skge_read32(hw, B0_SP_ISRC);

2875

status = skge_read32(hw, B0_SP_ISRC);

2874

if (status == 0)

2876

if (status == 0)

2875

return IRQ_NONE;

2877

return IRQ_NONE;

2876

2878

2877

if (status & IS_EXT_REG) {

2879

if (status & IS_EXT_REG) {

2878

hw->intr_mask &= ~IS_EXT_REG;

2880

hw->intr_mask &= ~IS_EXT_REG;

2879

tasklet_schedule(&hw->ext_tasklet);

2881

tasklet_schedule(&hw->ext_tasklet);

2880

}

2882

}

2881

2883

2882

if (status & (IS_R1_F|IS_XA1_F)) {

2884

if (status & (IS_R1_F|IS_XA1_F)) {

2883

skge_write8(hw, Q_ADDR(Q_R1, Q_CSR), CSR_IRQ_CL_F);

2885

skge_write8(hw, Q_ADDR(Q_R1, Q_CSR), CSR_IRQ_CL_F);

2884

hw->intr_mask &= ~(IS_R1_F|IS_XA1_F);

2886

hw->intr_mask &= ~(IS_R1_F|IS_XA1_F);

2885

netif_rx_schedule(hw->dev[0]);

2887

netif_rx_schedule(hw->dev[0]);

2886

}

2888

}

2887

2889

2888

if (status & (IS_R2_F|IS_XA2_F)) {

2890

if (status & (IS_R2_F|IS_XA2_F)) {

2889

skge_write8(hw, Q_ADDR(Q_R2, Q_CSR), CSR_IRQ_CL_F);

2891

skge_write8(hw, Q_ADDR(Q_R2, Q_CSR), CSR_IRQ_CL_F);

2890

hw->intr_mask &= ~(IS_R2_F|IS_XA2_F);

2892

hw->intr_mask &= ~(IS_R2_F|IS_XA2_F);

2891

netif_rx_schedule(hw->dev[1]);

2893

netif_rx_schedule(hw->dev[1]);

2892

}

2894

}

2893

2895

2894

if (likely((status & hw->intr_mask) == 0))

2896

if (likely((status & hw->intr_mask) == 0))

2895

return IRQ_HANDLED;

2897

return IRQ_HANDLED;

2896

2898

2897

if (status & IS_PA_TO_RX1) {

2899

if (status & IS_PA_TO_RX1) {

2898

struct skge_port *skge = netdev_priv(hw->dev[0]);

2900

struct skge_port *skge = netdev_priv(hw->dev[0]);

2899

++skge->net_stats.rx_over_errors;

2901

++skge->net_stats.rx_over_errors;

2900

skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);

2902

skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);

2901

}

2903

}

2902

2904

2903

if (status & IS_PA_TO_RX2) {

2905

if (status & IS_PA_TO_RX2) {

2904

struct skge_port *skge = netdev_priv(hw->dev[1]);

2906

struct skge_port *skge = netdev_priv(hw->dev[1]);

2905

++skge->net_stats.rx_over_errors;

2907

++skge->net_stats.rx_over_errors;

2906

skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);

2908

skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);

2907

}

2909

}

2908

2910

2909

if (status & IS_PA_TO_TX1)

2911

if (status & IS_PA_TO_TX1)

2910

skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);

2912

skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);

2911

2913

2912

if (status & IS_PA_TO_TX2)

2914

if (status & IS_PA_TO_TX2)

2913

skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);

2915

skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);

2914

2916

2915

if (status & IS_MAC1)

2917

if (status & IS_MAC1)

2916

skge_mac_intr(hw, 0);

2918

skge_mac_intr(hw, 0);

2917

2919

2918

if (status & IS_MAC2)

2920

if (status & IS_MAC2)

2919

skge_mac_intr(hw, 1);

2921

skge_mac_intr(hw, 1);

2920

2922

2921

if (status & IS_HW_ERR)

2923

if (status & IS_HW_ERR)

2922

skge_error_irq(hw);

2924

skge_error_irq(hw);

2923

2925

2924

skge_write32(hw, B0_IMSK, hw->intr_mask);

2926

skge_write32(hw, B0_IMSK, hw->intr_mask);

2925

2927

2926

return IRQ_HANDLED;

2928

return IRQ_HANDLED;

2927

}

2929

}

2928

2930

2929

#ifdef CONFIG_NET_POLL_CONTROLLER

2931

#ifdef CONFIG_NET_POLL_CONTROLLER

2930

static void skge_netpoll(struct net_device *dev)

2932

static void skge_netpoll(struct net_device *dev)

2931

{

2933

{

2932

struct skge_port *skge = netdev_priv(dev);

2934

struct skge_port *skge = netdev_priv(dev);

2933

2935

2934

disable_irq(dev->irq);

2936

disable_irq(dev->irq);

2935

skge_intr(dev->irq, skge->hw, NULL);

2937

skge_intr(dev->irq, skge->hw, NULL);

2936

enable_irq(dev->irq);

2938

enable_irq(dev->irq);

2937

}

2939

}

2938

#endif

2940

#endif

2939

2941

2940

static int skge_set_mac_address(struct net_device *dev, void *p)

2942

static int skge_set_mac_address(struct net_device *dev, void *p)

2941

{

2943

{

2942

struct skge_port *skge = netdev_priv(dev);

2944

struct skge_port *skge = netdev_priv(dev);

2943

struct skge_hw *hw = skge->hw;

2945

struct skge_hw *hw = skge->hw;

2944

unsigned port = skge->port;

2946

unsigned port = skge->port;

2945

const struct sockaddr *addr = p;

2947

const struct sockaddr *addr = p;

2946

2948

2947

if (!is_valid_ether_addr(addr->sa_data))

2949

if (!is_valid_ether_addr(addr->sa_data))

2948

return -EADDRNOTAVAIL;

2950

return -EADDRNOTAVAIL;

2949

2951

2950

spin_lock_bh(&hw->phy_lock);

2952

spin_lock_bh(&hw->phy_lock);

2951

memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);

2953

memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);

2952

memcpy_toio(hw->regs + B2_MAC_1 + port*8,

2954

memcpy_toio(hw->regs + B2_MAC_1 + port*8,

2953

dev->dev_addr, ETH_ALEN);

2955

dev->dev_addr, ETH_ALEN);

2954

memcpy_toio(hw->regs + B2_MAC_2 + port*8,

2956

memcpy_toio(hw->regs + B2_MAC_2 + port*8,

2955

dev->dev_addr, ETH_ALEN);

2957

dev->dev_addr, ETH_ALEN);

2956

2958

2957

if (hw->chip_id == CHIP_ID_GENESIS)

2959

if (hw->chip_id == CHIP_ID_GENESIS)

2958

xm_outaddr(hw, port, XM_SA, dev->dev_addr);

2960

xm_outaddr(hw, port, XM_SA, dev->dev_addr);

2959

else {

2961

else {

2960

gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);

2962

gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);

2961

gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);

2963

gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);

2962

}

2964

}

2963

spin_unlock_bh(&hw->phy_lock);

2965

spin_unlock_bh(&hw->phy_lock);

2964

2966

2965

return 0;

2967

return 0;

2966

}

2968

}

2967

2969

2968

static const struct {

2970

static const struct {

2969

u8 id;

2971

u8 id;

2970

const char *name;

2972

const char *name;

2971

} skge_chips[] = {

2973

} skge_chips[] = {

2972

{ CHIP_ID_GENESIS, "Genesis" },

2974

{ CHIP_ID_GENESIS, "Genesis" },

2973

{ CHIP_ID_YUKON, "Yukon" },

2975

{ CHIP_ID_YUKON, "Yukon" },

2974

{ CHIP_ID_YUKON_LITE, "Yukon-Lite"},

2976

{ CHIP_ID_YUKON_LITE, "Yukon-Lite"},

2975

{ CHIP_ID_YUKON_LP, "Yukon-LP"},

2977

{ CHIP_ID_YUKON_LP, "Yukon-LP"},

2976

};

2978

};

2977

2979

2978

static const char *skge_board_name(const struct skge_hw *hw)

2980

static const char *skge_board_name(const struct skge_hw *hw)

2979

{

2981

{

2980

int i;

2982

int i;

2981

static char buf[16];

2983

static char buf[16];

2982

2984

2983

for (i = 0; i < ARRAY_SIZE(skge_chips); i++)

2985

for (i = 0; i < ARRAY_SIZE(skge_chips); i++)

2984

if (skge_chips[i].id == hw->chip_id)

2986

if (skge_chips[i].id == hw->chip_id)

2985

return skge_chips[i].name;

2987

return skge_chips[i].name;

2986

2988

2987

snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);

2989

snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);

2988

return buf;

2990

return buf;

2989

}

2991

}

2990

2992

2991

2993

2992

/*

2994

/*

2993

* Setup the board data structure, but don't bring up

2995

* Setup the board data structure, but don't bring up

2994

* the port(s)

2996

* the port(s)

2995

*/

2997

*/

2996

static int skge_reset(struct skge_hw *hw)

2998

static int skge_reset(struct skge_hw *hw)

2997

{

2999

{

2998

u32 reg;

3000

u32 reg;

2999

u16 ctst;

3001

u16 ctst;

3000

u8 t8, mac_cfg, pmd_type, phy_type;

3002

u8 t8, mac_cfg, pmd_type, phy_type;

3001

int i;

3003

int i;

3002

3004

3003

ctst = skge_read16(hw, B0_CTST);

3005

ctst = skge_read16(hw, B0_CTST);

3004

3006

3005

/* do a SW reset */

3007

/* do a SW reset */

3006

skge_write8(hw, B0_CTST, CS_RST_SET);

3008

skge_write8(hw, B0_CTST, CS_RST_SET);

3007

skge_write8(hw, B0_CTST, CS_RST_CLR);

3009

skge_write8(hw, B0_CTST, CS_RST_CLR);

3008

3010

3009

/* clear PCI errors, if any */

3011

/* clear PCI errors, if any */

3010

skge_pci_clear(hw);

3012

skge_pci_clear(hw);

3011

3013

3012

skge_write8(hw, B0_CTST, CS_MRST_CLR);

3014

skge_write8(hw, B0_CTST, CS_MRST_CLR);

3013

3015

3014

/* restore CLK_RUN bits (for Yukon-Lite) */

3016

/* restore CLK_RUN bits (for Yukon-Lite) */

3015

skge_write16(hw, B0_CTST,

3017

skge_write16(hw, B0_CTST,

3016

ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));

3018

ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));

3017

3019

3018

hw->chip_id = skge_read8(hw, B2_CHIP_ID);

3020

hw->chip_id = skge_read8(hw, B2_CHIP_ID);

3019

phy_type = skge_read8(hw, B2_E_1) & 0xf;

3021

phy_type = skge_read8(hw, B2_E_1) & 0xf;

3020

pmd_type = skge_read8(hw, B2_PMD_TYP);

3022

pmd_type = skge_read8(hw, B2_PMD_TYP);

3021

hw->copper = (pmd_type == 'T' || pmd_type == '1');

3023

hw->copper = (pmd_type == 'T' || pmd_type == '1');

3022

3024

3023

switch (hw->chip_id) {

3025

switch (hw->chip_id) {

3024

case CHIP_ID_GENESIS:

3026

case CHIP_ID_GENESIS:

3025

switch (phy_type) {

3027

switch (phy_type) {

3026

case SK_PHY_BCOM:

3028

case SK_PHY_BCOM:

3027

hw->phy_addr = PHY_ADDR_BCOM;

3029

hw->phy_addr = PHY_ADDR_BCOM;

3028

break;

3030

break;

3029

default:

3031

default:

3030

printk(KERN_ERR PFX "%s: unsupported phy type 0x%x\n",

3032

printk(KERN_ERR PFX "%s: unsupported phy type 0x%x\n",

3031

pci_name(hw->pdev), phy_type);

3033

pci_name(hw->pdev), phy_type);

3032

return -EOPNOTSUPP;

3034

return -EOPNOTSUPP;

3033

}

3035

}

3034

break;

3036

break;

3035

3037

3036

case CHIP_ID_YUKON:

3038

case CHIP_ID_YUKON:

3037

case CHIP_ID_YUKON_LITE:

3039

case CHIP_ID_YUKON_LITE:

3038

case CHIP_ID_YUKON_LP:

3040

case CHIP_ID_YUKON_LP:

3039

if (phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')

3041

if (phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')

3040

hw->copper = 1;

3042

hw->copper = 1;

3041

3043

3042

hw->phy_addr = PHY_ADDR_MARV;

3044

hw->phy_addr = PHY_ADDR_MARV;

3043

break;

3045

break;

3044

3046

3045

default:

3047

default:

3046

printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",

3048

printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",

3047

pci_name(hw->pdev), hw->chip_id);

3049

pci_name(hw->pdev), hw->chip_id);

3048

return -EOPNOTSUPP;

3050

return -EOPNOTSUPP;

3049

}

3051

}

3050

3052

3051

mac_cfg = skge_read8(hw, B2_MAC_CFG);

3053

mac_cfg = skge_read8(hw, B2_MAC_CFG);

3052

hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;

3054

hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;

3053

hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;

3055

hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;

3054

3056

3055

/* read the adapters RAM size */

3057

/* read the adapters RAM size */

3056

t8 = skge_read8(hw, B2_E_0);

3058

t8 = skge_read8(hw, B2_E_0);

3057

if (hw->chip_id == CHIP_ID_GENESIS) {

3059

if (hw->chip_id == CHIP_ID_GENESIS) {

3058

if (t8 == 3) {

3060

if (t8 == 3) {

3059

/* special case: 4 x 64k x 36, offset = 0x80000 */

3061

/* special case: 4 x 64k x 36, offset = 0x80000 */

3060

hw->ram_size = 0x100000;

3062

hw->ram_size = 0x100000;

3061

hw->ram_offset = 0x80000;

3063

hw->ram_offset = 0x80000;

3062

} else

3064

} else

3063

hw->ram_size = t8 * 512;

3065

hw->ram_size = t8 * 512;

3064

}

3066

}

3065

else if (t8 == 0)

3067

else if (t8 == 0)

3066

hw->ram_size = 0x20000;

3068

hw->ram_size = 0x20000;

3067

else

3069

else

3068

hw->ram_size = t8 * 4096;

3070

hw->ram_size = t8 * 4096;

3069

3071

3070

hw->intr_mask = IS_HW_ERR | IS_EXT_REG | IS_PORT_1;

3072

hw->intr_mask = IS_HW_ERR | IS_EXT_REG | IS_PORT_1;

3071

if (hw->ports > 1)

3073

if (hw->ports > 1)

3072

hw->intr_mask |= IS_PORT_2;

3074

hw->intr_mask |= IS_PORT_2;

3073

3075

3074

if (hw->chip_id == CHIP_ID_GENESIS)

3076

if (hw->chip_id == CHIP_ID_GENESIS)

3075

genesis_init(hw);

3077

genesis_init(hw);

3076

else {

3078

else {

3077

/* switch power to VCC (WA for VAUX problem) */

3079

/* switch power to VCC (WA for VAUX problem) */

3078

skge_write8(hw, B0_POWER_CTRL,

3080

skge_write8(hw, B0_POWER_CTRL,

3079

PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);

3081

PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);

3080

3082

3081

/* avoid boards with stuck Hardware error bits */

3083

/* avoid boards with stuck Hardware error bits */

3082

if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&

3084

if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&

3083

(skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {

3085

(skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {

3084

printk(KERN_WARNING PFX "stuck hardware sensor bit\n");

3086

printk(KERN_WARNING PFX "stuck hardware sensor bit\n");

3085

hw->intr_mask &= ~IS_HW_ERR;

3087

hw->intr_mask &= ~IS_HW_ERR;

3086

}

3088

}

3087

3089

3088

/* Clear PHY COMA */

3090

/* Clear PHY COMA */

3089

skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);

3091

skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);

3090

pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg);

3092

pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg);

3091

reg &= ~PCI_PHY_COMA;

3093

reg &= ~PCI_PHY_COMA;

3092

pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);

3094

pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);

3093

skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);

3095

skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);

3094

3096

3095

3097

3096

for (i = 0; i < hw->ports; i++) {

3098

for (i = 0; i < hw->ports; i++) {

3097

skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);

3099

skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);

3098

skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);

3100

skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);

3099

}

3101

}

3100

}

3102

}

3101

3103

3102

/* turn off hardware timer (unused) */

3104

/* turn off hardware timer (unused) */

3103

skge_write8(hw, B2_TI_CTRL, TIM_STOP);

3105

skge_write8(hw, B2_TI_CTRL, TIM_STOP);

3104

skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);

3106

skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);

3105

skge_write8(hw, B0_LED, LED_STAT_ON);

3107

skge_write8(hw, B0_LED, LED_STAT_ON);

3106

3108

3107

/* enable the Tx Arbiters */

3109

/* enable the Tx Arbiters */

3108

for (i = 0; i < hw->ports; i++)

3110

for (i = 0; i < hw->ports; i++)

3109

skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);

3111

skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);

3110

3112

3111

/* Initialize ram interface */

3113

/* Initialize ram interface */

3112

skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);

3114

skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);

3113

3115

3114

skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);

3116

skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);

3115

skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);

3117

skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);

3116

skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);

3118

skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);

3117

skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);

3119

skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);

3118

skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);

3120

skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);

3119

skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);

3121

skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);

3120

skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);

3122

skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);

3121

skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);

3123

skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);

3122

skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);

3124

skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);

3123

skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);

3125

skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);

3124

skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);

3126

skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);

3125

skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);

3127

skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);

3126

3128

3127

skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);

3129

skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);

3128

3130

3129

/* Set interrupt moderation for Transmit only

3131

/* Set interrupt moderation for Transmit only

3130

* Receive interrupts avoided by NAPI

3132

* Receive interrupts avoided by NAPI

3131

*/

3133

*/

3132

skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);

3134

skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);

3133

skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));

3135

skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));

3134

skge_write32(hw, B2_IRQM_CTRL, TIM_START);

3136

skge_write32(hw, B2_IRQM_CTRL, TIM_START);

3135

3137

3136

skge_write32(hw, B0_IMSK, hw->intr_mask);

3138

skge_write32(hw, B0_IMSK, hw->intr_mask);

3137

3139

3138

spin_lock_bh(&hw->phy_lock);

3140

spin_lock_bh(&hw->phy_lock);

3139

for (i = 0; i < hw->ports; i++) {

3141

for (i = 0; i < hw->ports; i++) {

3140

if (hw->chip_id == CHIP_ID_GENESIS)

3142

if (hw->chip_id == CHIP_ID_GENESIS)

3141

genesis_reset(hw, i);

3143

genesis_reset(hw, i);

3142

else

3144

else

3143

yukon_reset(hw, i);

3145

yukon_reset(hw, i);

3144

}

3146

}

3145

spin_unlock_bh(&hw->phy_lock);

3147

spin_unlock_bh(&hw->phy_lock);

3146

3148

3147

return 0;

3149

return 0;

3148

}

3150

}

3149

3151

3150

/* Initialize network device */

3152

/* Initialize network device */

3151

static struct net_device *skge_devinit(struct skge_hw *hw, int port,

3153

static struct net_device *skge_devinit(struct skge_hw *hw, int port,

3152

int highmem)

3154

int highmem)

3153

{

3155

{

3154

struct skge_port *skge;

3156

struct skge_port *skge;

3155

struct net_device *dev = alloc_etherdev(sizeof(*skge));

3157

struct net_device *dev = alloc_etherdev(sizeof(*skge));

3156

3158

3157

if (!dev) {

3159

if (!dev) {

3158

printk(KERN_ERR "skge etherdev alloc failed");

3160

printk(KERN_ERR "skge etherdev alloc failed");

3159

return NULL;

3161

return NULL;

3160

}

3162

}

3161

3163

3162

SET_MODULE_OWNER(dev);

3164

SET_MODULE_OWNER(dev);

3163

SET_NETDEV_DEV(dev, &hw->pdev->dev);

3165

SET_NETDEV_DEV(dev, &hw->pdev->dev);

3164

dev->open = skge_up;

3166

dev->open = skge_up;

3165

dev->stop = skge_down;

3167

dev->stop = skge_down;

3166

dev->do_ioctl = skge_ioctl;

3168

dev->do_ioctl = skge_ioctl;

3167

dev->hard_start_xmit = skge_xmit_frame;

3169

dev->hard_start_xmit = skge_xmit_frame;

3168

dev->get_stats = skge_get_stats;

3170

dev->get_stats = skge_get_stats;

3169

if (hw->chip_id == CHIP_ID_GENESIS)

3171

if (hw->chip_id == CHIP_ID_GENESIS)

3170

dev->set_multicast_list = genesis_set_multicast;

3172

dev->set_multicast_list = genesis_set_multicast;

3171

else

3173

else

3172

dev->set_multicast_list = yukon_set_multicast;

3174

dev->set_multicast_list = yukon_set_multicast;

3173

3175

3174

dev->set_mac_address = skge_set_mac_address;

3176

dev->set_mac_address = skge_set_mac_address;

3175

dev->change_mtu = skge_change_mtu;

3177

dev->change_mtu = skge_change_mtu;

3176

SET_ETHTOOL_OPS(dev, &skge_ethtool_ops);

3178

SET_ETHTOOL_OPS(dev, &skge_ethtool_ops);

3177

dev->tx_timeout = skge_tx_timeout;

3179

dev->tx_timeout = skge_tx_timeout;

3178

dev->watchdog_timeo = TX_WATCHDOG;

3180

dev->watchdog_timeo = TX_WATCHDOG;

3179

dev->poll = skge_poll;

3181

dev->poll = skge_poll;

3180

dev->weight = NAPI_WEIGHT;

3182

dev->weight = NAPI_WEIGHT;

3181

#ifdef CONFIG_NET_POLL_CONTROLLER

3183

#ifdef CONFIG_NET_POLL_CONTROLLER

3182

dev->poll_controller = skge_netpoll;

3184

dev->poll_controller = skge_netpoll;

3183

#endif

3185

#endif

3184

dev->irq = hw->pdev->irq;

3186

dev->irq = hw->pdev->irq;

3185

dev->features = NETIF_F_LLTX;

3187

dev->features = NETIF_F_LLTX;

3186

if (highmem)

3188

if (highmem)

3187

dev->features |= NETIF_F_HIGHDMA;

3189

dev->features |= NETIF_F_HIGHDMA;

3188

3190

3189

skge = netdev_priv(dev);

3191

skge = netdev_priv(dev);

3190

skge->netdev = dev;

3192

skge->netdev = dev;

3191

skge->hw = hw;

3193

skge->hw = hw;

3192

skge->msg_enable = netif_msg_init(debug, default_msg);

3194

skge->msg_enable = netif_msg_init(debug, default_msg);

3193

skge->tx_ring.count = DEFAULT_TX_RING_SIZE;

3195

skge->tx_ring.count = DEFAULT_TX_RING_SIZE;

3194

skge->rx_ring.count = DEFAULT_RX_RING_SIZE;

3196

skge->rx_ring.count = DEFAULT_RX_RING_SIZE;

3195

3197

3196

/* Auto speed and flow control */

3198

/* Auto speed and flow control */

3197

skge->autoneg = AUTONEG_ENABLE;

3199

skge->autoneg = AUTONEG_ENABLE;

3198

skge->flow_control = FLOW_MODE_SYMMETRIC;

3200

skge->flow_control = FLOW_MODE_SYMMETRIC;

3199

skge->duplex = -1;

3201

skge->duplex = -1;

3200

skge->speed = -1;

3202

skge->speed = -1;

3201

skge->advertising = skge_supported_modes(hw);

3203

skge->advertising = skge_supported_modes(hw);

3202

3204

3203

hw->dev[port] = dev;

3205

hw->dev[port] = dev;

3204

3206

3205

skge->port = port;

3207

skge->port = port;

3206

3208

3207

spin_lock_init(&skge->tx_lock);

3209

spin_lock_init(&skge->tx_lock);

3208

3210

3209

if (hw->chip_id != CHIP_ID_GENESIS) {

3211

if (hw->chip_id != CHIP_ID_GENESIS) {

3210

dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;

3212

dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;

3211

skge->rx_csum = 1;

3213

skge->rx_csum = 1;

3212

}

3214

}

3213

3215

3214

/* read the mac address */

3216

/* read the mac address */

3215

memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);

3217

memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);

3216

memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);

3218

memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);

3217

3219

3218

/* device is off until link detection */

3220

/* device is off until link detection */

3219

netif_carrier_off(dev);

3221

netif_carrier_off(dev);

3220

netif_stop_queue(dev);

3222

netif_stop_queue(dev);

3221

3223

3222

return dev;

3224

return dev;

3223

}

3225

}

3224

3226

3225

static void __devinit skge_show_addr(struct net_device *dev)

3227

static void __devinit skge_show_addr(struct net_device *dev)

3226

{

3228

{

3227

const struct skge_port *skge = netdev_priv(dev);

3229

const struct skge_port *skge = netdev_priv(dev);

3228

3230

3229

if (netif_msg_probe(skge))

3231

if (netif_msg_probe(skge))

3230

printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",

3232

printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",

3231

dev->name,

3233

dev->name,

3232

dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],

3234

dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],

3233

dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);

3235

dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);

3234

}

3236

}

3235

3237

3236

static int __devinit skge_probe(struct pci_dev *pdev,

3238

static int __devinit skge_probe(struct pci_dev *pdev,

3237

const struct pci_device_id *ent)

3239

const struct pci_device_id *ent)

3238

{

3240

{

3239

struct net_device *dev, *dev1;

3241

struct net_device *dev, *dev1;

3240

struct skge_hw *hw;

3242

struct skge_hw *hw;

3241

int err, using_dac = 0;

3243

int err, using_dac = 0;

3242

3244

3243

if ((err = pci_enable_device(pdev))) {

3245

err = pci_enable_device(pdev);

3246

if (err) {

3244

printk(KERN_ERR PFX "%s cannot enable PCI device\n",

3247

printk(KERN_ERR PFX "%s cannot enable PCI device\n",

3245

pci_name(pdev));

3248

pci_name(pdev));

3246

goto err_out;

3249

goto err_out;

3247

}

3250

}

3248

3251

3249

if ((err = pci_request_regions(pdev, DRV_NAME))) {

3252

err = pci_request_regions(pdev, DRV_NAME);

3253

if (err) {

3250

printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",

3254

printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",

3251

pci_name(pdev));

3255

pci_name(pdev));

3252

goto err_out_disable_pdev;

3256

goto err_out_disable_pdev;

3253

}

3257

}

3254

3258

3255

pci_set_master(pdev);

3259

pci_set_master(pdev);

3256

3260

3257

if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {

3261

if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {

3258

using_dac = 1;

3262

using_dac = 1;

3259

err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);

3263

err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);

3260

} else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {

3264

} else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {

3261

using_dac = 0;

3265

using_dac = 0;

3262

err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);

3266

err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);

3263

}

3267

}

3264

3268

3265

if (err) {

3269

if (err) {

3266

printk(KERN_ERR PFX "%s no usable DMA configuration\n",

3270

printk(KERN_ERR PFX "%s no usable DMA configuration\n",

3267

pci_name(pdev));

3271

pci_name(pdev));

3268

goto err_out_free_regions;

3272

goto err_out_free_regions;

3269

}

3273

}

3270

3274

3271

#ifdef __BIG_ENDIAN

3275

#ifdef __BIG_ENDIAN

3272

/* byte swap descriptors in hardware */

3276

/* byte swap descriptors in hardware */

3273

{

3277

{

3274

u32 reg;

3278

u32 reg;

3275

3279

3276

pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);

3280

pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);

3277

reg |= PCI_REV_DESC;

3281

reg |= PCI_REV_DESC;

3278

pci_write_config_dword(pdev, PCI_DEV_REG2, reg);

3282

pci_write_config_dword(pdev, PCI_DEV_REG2, reg);

3279

}

3283

}

3280

#endif

3284

#endif

3281

3285

3282

err = -ENOMEM;

3286

err = -ENOMEM;

3283

hw = kzalloc(sizeof(*hw), GFP_KERNEL);

3287

hw = kzalloc(sizeof(*hw), GFP_KERNEL);

3284

if (!hw) {

3288

if (!hw) {

3285

printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",

3289

printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",

3286

pci_name(pdev));

3290

pci_name(pdev));

3287

goto err_out_free_regions;

3291

goto err_out_free_regions;

3288

}

3292

}

3289

3293

3290

hw->pdev = pdev;

3294

hw->pdev = pdev;

3291

spin_lock_init(&hw->phy_lock);

3295

spin_lock_init(&hw->phy_lock);

3292

tasklet_init(&hw->ext_tasklet, skge_extirq, (unsigned long) hw);

3296

tasklet_init(&hw->ext_tasklet, skge_extirq, (unsigned long) hw);

3293

3297

3294

hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);

3298

hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);

3295

if (!hw->regs) {

3299

if (!hw->regs) {

3296

printk(KERN_ERR PFX "%s: cannot map device registers\n",

3300

printk(KERN_ERR PFX "%s: cannot map device registers\n",

3297

pci_name(pdev));

3301

pci_name(pdev));

3298

goto err_out_free_hw;

3302

goto err_out_free_hw;

3299

}

3303

}

3300

3304

3301

if ((err = request_irq(pdev->irq, skge_intr, SA_SHIRQ, DRV_NAME, hw))) {

3305

err = request_irq(pdev->irq, skge_intr, SA_SHIRQ, DRV_NAME, hw);

3306

if (err) {

3302

printk(KERN_ERR PFX "%s: cannot assign irq %d\n",

3307

printk(KERN_ERR PFX "%s: cannot assign irq %d\n",

3303

pci_name(pdev), pdev->irq);

3308

pci_name(pdev), pdev->irq);

3304

goto err_out_iounmap;

3309

goto err_out_iounmap;

3305

}

3310

}

3306

pci_set_drvdata(pdev, hw);

3311

pci_set_drvdata(pdev, hw);

3307

3312

3308

err = skge_reset(hw);

3313

err = skge_reset(hw);

3309

if (err)

3314

if (err)

3310

goto err_out_free_irq;

3315

goto err_out_free_irq;

3311

3316

3312

printk(KERN_INFO PFX DRV_VERSION " addr 0x%lx irq %d chip %s rev %d\n",

3317

printk(KERN_INFO PFX DRV_VERSION " addr 0x%lx irq %d chip %s rev %d\n",

3313

pci_resource_start(pdev, 0), pdev->irq,

3318

pci_resource_start(pdev, 0), pdev->irq,

3314

skge_board_name(hw), hw->chip_rev);

3319

skge_board_name(hw), hw->chip_rev);

3315

3320

3316

if ((dev = skge_devinit(hw, 0, using_dac)) == NULL)

3321

if ((dev = skge_devinit(hw, 0, using_dac)) == NULL)

3317

goto err_out_led_off;

3322

goto err_out_led_off;

3318

3323

3319

if ((err = register_netdev(dev))) {

3324

err = register_netdev(dev);

3325

if (err) {

3320

printk(KERN_ERR PFX "%s: cannot register net device\n",

3326

printk(KERN_ERR PFX "%s: cannot register net device\n",

3321

pci_name(pdev));

3327

pci_name(pdev));

3322

goto err_out_free_netdev;

3328

goto err_out_free_netdev;

3323

}

3329

}

3324

3330

3325

skge_show_addr(dev);

3331

skge_show_addr(dev);

3326

3332

3327

if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {

3333

if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {

3328

if (register_netdev(dev1) == 0)

3334

if (register_netdev(dev1) == 0)

3329

skge_show_addr(dev1);

3335

skge_show_addr(dev1);

3330

else {

3336

else {

3331

/* Failure to register second port need not be fatal */

3337

/* Failure to register second port need not be fatal */

3332

printk(KERN_WARNING PFX "register of second port failed\n");

3338

printk(KERN_WARNING PFX "register of second port failed\n");

3333

hw->dev[1] = NULL;

3339

hw->dev[1] = NULL;

3334

free_netdev(dev1);

3340

free_netdev(dev1);

3335

}

3341

}

3336

}

3342

}

3337

3343

3338

return 0;

3344

return 0;

3339

3345

3340

err_out_free_netdev:

3346

err_out_free_netdev:

3341

free_netdev(dev);

3347

free_netdev(dev);

3342

err_out_led_off:

3348

err_out_led_off:

3343

skge_write16(hw, B0_LED, LED_STAT_OFF);

3349

skge_write16(hw, B0_LED, LED_STAT_OFF);

3344

err_out_free_irq:

3350

err_out_free_irq:

3345

free_irq(pdev->irq, hw);

3351

free_irq(pdev->irq, hw);

3346

err_out_iounmap:

3352

err_out_iounmap:

3347

iounmap(hw->regs);

3353

iounmap(hw->regs);

3348

err_out_free_hw:

3354

err_out_free_hw:

3349

kfree(hw);

3355

kfree(hw);

3350

err_out_free_regions:

3356

err_out_free_regions:

3351

pci_release_regions(pdev);

3357

pci_release_regions(pdev);

3352

err_out_disable_pdev:

3358

err_out_disable_pdev:

3353

pci_disable_device(pdev);

3359

pci_disable_device(pdev);

3354

pci_set_drvdata(pdev, NULL);

3360

pci_set_drvdata(pdev, NULL);

3355

err_out:

3361

err_out:

3356

return err;

3362

return err;

3357

}

3363

}

3358

3364

3359

static void __devexit skge_remove(struct pci_dev *pdev)

3365

static void __devexit skge_remove(struct pci_dev *pdev)

3360

{

3366

{

3361

struct skge_hw *hw = pci_get_drvdata(pdev);

3367

struct skge_hw *hw = pci_get_drvdata(pdev);

3362

struct net_device *dev0, *dev1;

3368

struct net_device *dev0, *dev1;

3363

3369

3364

if (!hw)

3370

if (!hw)

3365

return;

3371

return;

3366

3372

3367

if ((dev1 = hw->dev[1]))

3373

if ((dev1 = hw->dev[1]))

3368

unregister_netdev(dev1);

3374

unregister_netdev(dev1);

3369

dev0 = hw->dev[0];

3375

dev0 = hw->dev[0];

3370

unregister_netdev(dev0);

3376

unregister_netdev(dev0);

3371

3377

3372

skge_write32(hw, B0_IMSK, 0);

3378

skge_write32(hw, B0_IMSK, 0);

3373

skge_write16(hw, B0_LED, LED_STAT_OFF);

3379

skge_write16(hw, B0_LED, LED_STAT_OFF);

3374

skge_pci_clear(hw);

3380

skge_pci_clear(hw);

3375

skge_write8(hw, B0_CTST, CS_RST_SET);

3381

skge_write8(hw, B0_CTST, CS_RST_SET);

3376

3382

3377

tasklet_kill(&hw->ext_tasklet);

3383

tasklet_kill(&hw->ext_tasklet);

3378

3384

3379

free_irq(pdev->irq, hw);

3385

free_irq(pdev->irq, hw);

3380

pci_release_regions(pdev);

3386

pci_release_regions(pdev);

3381

pci_disable_device(pdev);

3387

pci_disable_device(pdev);

3382

if (dev1)

3388

if (dev1)

3383

free_netdev(dev1);

3389

free_netdev(dev1);

3384

free_netdev(dev0);

3390

free_netdev(dev0);

3385

3391

3386

iounmap(hw->regs);

3392

iounmap(hw->regs);

3387

kfree(hw);

3393

kfree(hw);

3388

pci_set_drvdata(pdev, NULL);

3394

pci_set_drvdata(pdev, NULL);

3389

}

3395

}

3390

3396

3391

#ifdef CONFIG_PM

3397

#ifdef CONFIG_PM

3392

static int skge_suspend(struct pci_dev *pdev, pm_message_t state)

3398

static int skge_suspend(struct pci_dev *pdev, pm_message_t state)

3393

{

3399

{

3394

struct skge_hw *hw = pci_get_drvdata(pdev);

3400

struct skge_hw *hw = pci_get_drvdata(pdev);

3395

int i, wol = 0;

3401

int i, wol = 0;

3396

3402

3397

for (i = 0; i < 2; i++) {

3403

for (i = 0; i < 2; i++) {

3398

struct net_device *dev = hw->dev[i];

3404

struct net_device *dev = hw->dev[i];

3399

3405

3400

if (dev) {

3406

if (dev) {

3401

struct skge_port *skge = netdev_priv(dev);

3407

struct skge_port *skge = netdev_priv(dev);

3402

if (netif_running(dev)) {

3408

if (netif_running(dev)) {

3403

netif_carrier_off(dev);

3409

netif_carrier_off(dev);

3404

if (skge->wol)

3410

if (skge->wol)

3405

netif_stop_queue(dev);

3411

netif_stop_queue(dev);

3406

else

3412

else

3407

skge_down(dev);

3413

skge_down(dev);

3408

}

3414

}

3409

netif_device_detach(dev);

3415

netif_device_detach(dev);

3410

wol |= skge->wol;

3416

wol |= skge->wol;

3411

}

3417

}

3412

}

3418

}

3413

3419

3414

pci_save_state(pdev);

3420

pci_save_state(pdev);

3415

pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);

3421

pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);

3416

pci_disable_device(pdev);

3422

pci_disable_device(pdev);

3417

pci_set_power_state(pdev, pci_choose_state(pdev, state));

3423

pci_set_power_state(pdev, pci_choose_state(pdev, state));

3418

3424

3419

return 0;

3425

return 0;

3420

}

3426

}

3421

3427

3422

static int skge_resume(struct pci_dev *pdev)

3428

static int skge_resume(struct pci_dev *pdev)

3423

{

3429

{

3424

struct skge_hw *hw = pci_get_drvdata(pdev);

3430

struct skge_hw *hw = pci_get_drvdata(pdev);

3425

int i;

3431

int i;

3426

3432

3427

pci_set_power_state(pdev, PCI_D0);

3433

pci_set_power_state(pdev, PCI_D0);

3428

pci_restore_state(pdev);

3434

pci_restore_state(pdev);

3429

pci_enable_wake(pdev, PCI_D0, 0);

3435

pci_enable_wake(pdev, PCI_D0, 0);

3430

3436

3431

skge_reset(hw);

3437

skge_reset(hw);

3432

3438

3433

for (i = 0; i < 2; i++) {

3439

for (i = 0; i < 2; i++) {

3434

struct net_device *dev = hw->dev[i];

3440

struct net_device *dev = hw->dev[i];

3435

if (dev) {

3441

if (dev) {

3436

netif_device_attach(dev);

3442

netif_device_attach(dev);

3437

if (netif_running(dev) && skge_up(dev))

3443

if (netif_running(dev) && skge_up(dev))

3438

dev_close(dev);

3444

dev_close(dev);

3439

}

3445

}

3440

}

3446

}

3441

return 0;

3447

return 0;

3442

}

3448

}

3443

#endif

3449

#endif

3444

3450

3445

static struct pci_driver skge_driver = {

3451

static struct pci_driver skge_driver = {

3446

.name = DRV_NAME,

3452

.name = DRV_NAME,

3447

.id_table = skge_id_table,

3453

.id_table = skge_id_table,

3448

.probe = skge_probe,

3454

.probe = skge_probe,

3449

.remove = __devexit_p(skge_remove),

3455

.remove = __devexit_p(skge_remove),

3450

#ifdef CONFIG_PM

3456

#ifdef CONFIG_PM

3451

.suspend = skge_suspend,

3457

.suspend = skge_suspend,

3452

.resume = skge_resume,

3458

.resume = skge_resume,

3453

#endif

3459

#endif

3454

};

3460

};

3455

3461

3456

static int __init skge_init_module(void)

3462

static int __init skge_init_module(void)

3457

{

3463

{

3458

return pci_module_init(&skge_driver);

3464

return pci_module_init(&skge_driver);

3459

}

3465

}

3460

3466

3461

static void __exit skge_cleanup_module(void)

3467

static void __exit skge_cleanup_module(void)

3462

{

3468

{

3463

pci_unregister_driver(&skge_driver);

3469

pci_unregister_driver(&skge_driver);

3464

}

3470

}

3465

3471

3466

module_init(skge_init_module);

3472

module_init(skge_init_module);

3467

module_exit(skge_cleanup_module);

3473

module_exit(skge_cleanup_module);

3468

3474

GITLAB

Eric Lee / linux-smarc-t335x-v3.2

[PATCH] skge: formmating and whitespace cleanup

 /*
  * New driver for Marvell Yukon chipset and SysKonnect Gigabit
  * Ethernet adapters. Based on earlier sk98lin, e100 and
  * FreeBSD if_sk drivers.
  *
  * This driver intentionally does not support all the features
  * of the original driver such as link fail-over and link management because
  * those should be done at higher levels.
  *
  * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
  * (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  */
 #include <linux/config.h>
 #include <linux/in.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/moduleparam.h>
 #include <linux/netdevice.h>
 #include <linux/etherdevice.h>
 #include <linux/ethtool.h>
 #include <linux/pci.h>
 #include <linux/if_vlan.h>
 #include <linux/ip.h>
 #include <linux/delay.h>
 #include <linux/crc32.h>
 #include <linux/dma-mapping.h>
 #include <linux/mii.h>
 #include <asm/irq.h>
 #include "skge.h"
 #define DRV_NAME		"skge"
 #define DRV_VERSION		"1.3"
 #define PFX			DRV_NAME " "
 #define DEFAULT_TX_RING_SIZE	128
 #define DEFAULT_RX_RING_SIZE	512
 #define MAX_TX_RING_SIZE	1024
 #define MAX_RX_RING_SIZE	4096
 #define RX_COPY_THRESHOLD	128
 #define RX_BUF_SIZE		1536
 #define PHY_RETRIES	        1000
 #define ETH_JUMBO_MTU		9000
 #define TX_WATCHDOG		(5 * HZ)
 #define NAPI_WEIGHT		64
 #define BLINK_MS		250
 MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
 MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
 MODULE_LICENSE("GPL");
 MODULE_VERSION(DRV_VERSION);
 static const u32 default_msg
 	= NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK
 	  | NETIF_MSG_IFUP| NETIF_MSG_IFDOWN;
 static int debug = -1;	/* defaults above */
 module_param(debug, int, 0);
 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
 static const struct pci_device_id skge_id_table[] = {
 	{ PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
 	{ PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
 	{ PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
 	{ PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
 	{ PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T), },
 	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
 	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
 	{ PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
 	{ PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
 	{ PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015, },
 	{ 0 }
 };
 MODULE_DEVICE_TABLE(pci, skge_id_table);
 static int skge_up(struct net_device *dev);
 static int skge_down(struct net_device *dev);
 static void skge_phy_reset(struct skge_port *skge);
 static void skge_tx_clean(struct skge_port *skge);
 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
 static void genesis_get_stats(struct skge_port *skge, u64 *data);
 static void yukon_get_stats(struct skge_port *skge, u64 *data);
 static void yukon_init(struct skge_hw *hw, int port);
 static void genesis_mac_init(struct skge_hw *hw, int port);
 static void genesis_link_up(struct skge_port *skge);
 /* Avoid conditionals by using array */
 static const int txqaddr[] = { Q_XA1, Q_XA2 };
 static const int rxqaddr[] = { Q_R1, Q_R2 };
 static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
 static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
 static int skge_get_regs_len(struct net_device *dev)
 {
 	return 0x4000;
 }
 /*
  * Returns copy of whole control register region
  * Note: skip RAM address register because accessing it will
  * 	 cause bus hangs!
  */
 static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
 			  void *p)
 {
 	const struct skge_port *skge = netdev_priv(dev);
 	const void __iomem *io = skge->hw->regs;
 	regs->version = 1;
 	memset(p, 0, regs->len);
 	memcpy_fromio(p, io, B3_RAM_ADDR);
 	memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
 		      regs->len - B3_RI_WTO_R1);
 }
 /* Wake on Lan only supported on Yukon chips with rev 1 or above */
 static int wol_supported(const struct skge_hw *hw)
 {
 	return !((hw->chip_id == CHIP_ID_GENESIS ||
 		  (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)));
 }
 static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 {
 	struct skge_port *skge = netdev_priv(dev);
 	wol->supported = wol_supported(skge->hw) ? WAKE_MAGIC : 0;
 	wol->wolopts = skge->wol ? WAKE_MAGIC : 0;
 }
 static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 {
 	struct skge_port *skge = netdev_priv(dev);
 	struct skge_hw *hw = skge->hw;
 	if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
 		return -EOPNOTSUPP;
 	if (wol->wolopts == WAKE_MAGIC && !wol_supported(hw))
 		return -EOPNOTSUPP;
 	skge->wol = wol->wolopts == WAKE_MAGIC;
 	if (skge->wol) {
 		memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
 		skge_write16(hw, WOL_CTRL_STAT,
 			     WOL_CTL_ENA_PME_ON_MAGIC_PKT |
 			     WOL_CTL_ENA_MAGIC_PKT_UNIT);
 	} else
 		skge_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
 	return 0;
 }
 /* Determine supported/advertised modes based on hardware.
  * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
  */
 static u32 skge_supported_modes(const struct skge_hw *hw)
 {
 	u32 supported;
 	if (hw->copper) {
 		supported = SUPPORTED_10baseT_Half
 			| SUPPORTED_10baseT_Full
 			| SUPPORTED_100baseT_Half
 			| SUPPORTED_100baseT_Full
 			| SUPPORTED_1000baseT_Half
 			| SUPPORTED_1000baseT_Full
 			| SUPPORTED_Autoneg| SUPPORTED_TP;
 		if (hw->chip_id == CHIP_ID_GENESIS)
 			supported &= ~(SUPPORTED_10baseT_Half
 					     | SUPPORTED_10baseT_Full
 					     | SUPPORTED_100baseT_Half
 					     | SUPPORTED_100baseT_Full);
 		else if (hw->chip_id == CHIP_ID_YUKON)
 			supported &= ~SUPPORTED_1000baseT_Half;
 	} else
 		supported = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
 			| SUPPORTED_Autoneg;
 	return supported;
 }
 static int skge_get_settings(struct net_device *dev,
 			     struct ethtool_cmd *ecmd)
 {
 	struct skge_port *skge = netdev_priv(dev);
 	struct skge_hw *hw = skge->hw;
 	ecmd->transceiver = XCVR_INTERNAL;
 	ecmd->supported = skge_supported_modes(hw);
 	if (hw->copper) {
 		ecmd->port = PORT_TP;
 		ecmd->phy_address = hw->phy_addr;
 	} else
 		ecmd->port = PORT_FIBRE;
 	ecmd->advertising = skge->advertising;
 	ecmd->autoneg = skge->autoneg;
 	ecmd->speed = skge->speed;
 	ecmd->duplex = skge->duplex;
 	return 0;
 }
 static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
 {
 	struct skge_port *skge = netdev_priv(dev);
 	const struct skge_hw *hw = skge->hw;
 	u32 supported = skge_supported_modes(hw);
 	if (ecmd->autoneg == AUTONEG_ENABLE) {
 		ecmd->advertising = supported;
 		skge->duplex = -1;
 		skge->speed = -1;
 	} else {
 		u32 setting;
 		switch (ecmd->speed) {
 		case SPEED_1000:
 			if (ecmd->duplex == DUPLEX_FULL)
 				setting = SUPPORTED_1000baseT_Full;
 			else if (ecmd->duplex == DUPLEX_HALF)
 				setting = SUPPORTED_1000baseT_Half;
 			else
 				return -EINVAL;
 			break;
 		case SPEED_100:
 			if (ecmd->duplex == DUPLEX_FULL)
 				setting = SUPPORTED_100baseT_Full;
 			else if (ecmd->duplex == DUPLEX_HALF)
 				setting = SUPPORTED_100baseT_Half;
 			else
 				return -EINVAL;
 			break;
 		case SPEED_10:
 			if (ecmd->duplex == DUPLEX_FULL)
 				setting = SUPPORTED_10baseT_Full;
 			else if (ecmd->duplex == DUPLEX_HALF)
 				setting = SUPPORTED_10baseT_Half;
 			else
 				return -EINVAL;
 			break;
 		default:
 			return -EINVAL;
 		}
 		if ((setting & supported) == 0)
 			return -EINVAL;
 		skge->speed = ecmd->speed;
 		skge->duplex = ecmd->duplex;
 	}
 	skge->autoneg = ecmd->autoneg;
 	skge->advertising = ecmd->advertising;
 	if (netif_running(dev))
 		skge_phy_reset(skge);
 	return (0);
 }
 static void skge_get_drvinfo(struct net_device *dev,
 			     struct ethtool_drvinfo *info)
 {
 	struct skge_port *skge = netdev_priv(dev);
 	strcpy(info->driver, DRV_NAME);
 	strcpy(info->version, DRV_VERSION);
 	strcpy(info->fw_version, "N/A");
 	strcpy(info->bus_info, pci_name(skge->hw->pdev));
 }
 static const struct skge_stat {
 	char 	   name[ETH_GSTRING_LEN];
 	u16	   xmac_offset;
 	u16	   gma_offset;
 } skge_stats[] = {
 	{ "tx_bytes",		XM_TXO_OK_HI,  GM_TXO_OK_HI },
 	{ "rx_bytes",		XM_RXO_OK_HI,  GM_RXO_OK_HI },
 	{ "tx_broadcast",	XM_TXF_BC_OK,  GM_TXF_BC_OK },
 	{ "rx_broadcast",	XM_RXF_BC_OK,  GM_RXF_BC_OK },
 	{ "tx_multicast",	XM_TXF_MC_OK,  GM_TXF_MC_OK },
 	{ "rx_multicast",	XM_RXF_MC_OK,  GM_RXF_MC_OK },
 	{ "tx_unicast",		XM_TXF_UC_OK,  GM_TXF_UC_OK },
 	{ "rx_unicast",		XM_RXF_UC_OK,  GM_RXF_UC_OK },
 	{ "tx_mac_pause",	XM_TXF_MPAUSE, GM_TXF_MPAUSE },
 	{ "rx_mac_pause",	XM_RXF_MPAUSE, GM_RXF_MPAUSE },
 	{ "collisions",		XM_TXF_SNG_COL, GM_TXF_SNG_COL },
 	{ "multi_collisions",	XM_TXF_MUL_COL, GM_TXF_MUL_COL },
 	{ "aborted",		XM_TXF_ABO_COL, GM_TXF_ABO_COL },
 	{ "late_collision",	XM_TXF_LAT_COL, GM_TXF_LAT_COL },
 	{ "fifo_underrun",	XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
 	{ "fifo_overflow",	XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
 	{ "rx_toolong",		XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
 	{ "rx_jabber",		XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
 	{ "rx_runt",		XM_RXE_RUNT, 	GM_RXE_FRAG },
 	{ "rx_too_long",	XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
 	{ "rx_fcs_error",	XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
 };
 static int skge_get_stats_count(struct net_device *dev)
 {
 	return ARRAY_SIZE(skge_stats);
 }
 static void skge_get_ethtool_stats(struct net_device *dev,
 				   struct ethtool_stats *stats, u64 *data)
 {
 	struct skge_port *skge = netdev_priv(dev);
 	if (skge->hw->chip_id == CHIP_ID_GENESIS)
 		genesis_get_stats(skge, data);
 	else
 		yukon_get_stats(skge, data);
 }
 /* Use hardware MIB variables for critical path statistics and
  * transmit feedback not reported at interrupt.
  * Other errors are accounted for in interrupt handler.
  */
 static struct net_device_stats *skge_get_stats(struct net_device *dev)
 {
 	struct skge_port *skge = netdev_priv(dev);
 	u64 data[ARRAY_SIZE(skge_stats)];
 	if (skge->hw->chip_id == CHIP_ID_GENESIS)
 		genesis_get_stats(skge, data);
 	else
 		yukon_get_stats(skge, data);
 	skge->net_stats.tx_bytes = data[0];
 	skge->net_stats.rx_bytes = data[1];
 	skge->net_stats.tx_packets = data[2] + data[4] + data[6];
 	skge->net_stats.rx_packets = data[3] + data[5] + data[7];
 	skge->net_stats.multicast = data[5] + data[7];
 	skge->net_stats.collisions = data[10];
 	skge->net_stats.tx_aborted_errors = data[12];
 	return &skge->net_stats;
 }
 static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
 {
 	int i;
 	switch (stringset) {
 	case ETH_SS_STATS:
 		for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
 			memcpy(data + i * ETH_GSTRING_LEN,
 			       skge_stats[i].name, ETH_GSTRING_LEN);
 		break;
 	}
 }
 static void skge_get_ring_param(struct net_device *dev,
 				struct ethtool_ringparam *p)
 {
 	struct skge_port *skge = netdev_priv(dev);
 	p->rx_max_pending = MAX_RX_RING_SIZE;
 	p->tx_max_pending = MAX_TX_RING_SIZE;
 	p->rx_mini_max_pending = 0;
 	p->rx_jumbo_max_pending = 0;
 	p->rx_pending = skge->rx_ring.count;
 	p->tx_pending = skge->tx_ring.count;
 	p->rx_mini_pending = 0;
 	p->rx_jumbo_pending = 0;
 }
 static int skge_set_ring_param(struct net_device *dev,
 			       struct ethtool_ringparam *p)
 {
 	struct skge_port *skge = netdev_priv(dev);
 	int err;
 	if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
 	    p->tx_pending == 0 || p->tx_pending > MAX_TX_RING_SIZE)
 		return -EINVAL;
 	skge->rx_ring.count = p->rx_pending;
 	skge->tx_ring.count = p->tx_pending;
 	if (netif_running(dev)) {
 		skge_down(dev);
 		err = skge_up(dev);
 		if (err)
 			dev_close(dev);
 	}
 	return 0;
 }
 static u32 skge_get_msglevel(struct net_device *netdev)
 {
 	struct skge_port *skge = netdev_priv(netdev);
 	return skge->msg_enable;
 }
 static void skge_set_msglevel(struct net_device *netdev, u32 value)
 {
 	struct skge_port *skge = netdev_priv(netdev);
 	skge->msg_enable = value;
 }
 static int skge_nway_reset(struct net_device *dev)
 {
 	struct skge_port *skge = netdev_priv(dev);
 	if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
 		return -EINVAL;
 	skge_phy_reset(skge);
 	return 0;
 }
 static int skge_set_sg(struct net_device *dev, u32 data)
 {
 	struct skge_port *skge = netdev_priv(dev);
 	struct skge_hw *hw = skge->hw;
 	if (hw->chip_id == CHIP_ID_GENESIS && data)
 		return -EOPNOTSUPP;
 	return ethtool_op_set_sg(dev, data);
 }
 static int skge_set_tx_csum(struct net_device *dev, u32 data)
 {
 	struct skge_port *skge = netdev_priv(dev);
 	struct skge_hw *hw = skge->hw;
 	if (hw->chip_id == CHIP_ID_GENESIS && data)
 		return -EOPNOTSUPP;
 	return ethtool_op_set_tx_csum(dev, data);
 }
 static u32 skge_get_rx_csum(struct net_device *dev)
 {
 	struct skge_port *skge = netdev_priv(dev);
 	return skge->rx_csum;
 }
 /* Only Yukon supports checksum offload. */
 static int skge_set_rx_csum(struct net_device *dev, u32 data)
 {
 	struct skge_port *skge = netdev_priv(dev);
 	if (skge->hw->chip_id == CHIP_ID_GENESIS && data)
 		return -EOPNOTSUPP;
 	skge->rx_csum = data;
 	return 0;
 }
 static void skge_get_pauseparam(struct net_device *dev,
 				struct ethtool_pauseparam *ecmd)
 {
 	struct skge_port *skge = netdev_priv(dev);
 	ecmd->tx_pause = (skge->flow_control == FLOW_MODE_LOC_SEND)
 		|| (skge->flow_control == FLOW_MODE_SYMMETRIC);
 	ecmd->rx_pause = (skge->flow_control == FLOW_MODE_REM_SEND)
 		|| (skge->flow_control == FLOW_MODE_SYMMETRIC);
 	ecmd->autoneg = skge->autoneg;
 }
 static int skge_set_pauseparam(struct net_device *dev,
 			       struct ethtool_pauseparam *ecmd)
 {
 	struct skge_port *skge = netdev_priv(dev);
 	skge->autoneg = ecmd->autoneg;
 	if (ecmd->rx_pause && ecmd->tx_pause)
 		skge->flow_control = FLOW_MODE_SYMMETRIC;
 	else if (ecmd->rx_pause && !ecmd->tx_pause)
 		skge->flow_control = FLOW_MODE_REM_SEND;
 	else if (!ecmd->rx_pause && ecmd->tx_pause)
 		skge->flow_control = FLOW_MODE_LOC_SEND;
 	else
 		skge->flow_control = FLOW_MODE_NONE;
 	if (netif_running(dev))
 		skge_phy_reset(skge);
 	return 0;
 }
 /* Chip internal frequency for clock calculations */
 static inline u32 hwkhz(const struct skge_hw *hw)
 {
 	if (hw->chip_id == CHIP_ID_GENESIS)
 		return 53215; /* or:  53.125 MHz */
 	else
 		return 78215; /* or:  78.125 MHz */
 }
 /* Chip HZ to microseconds */
 static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
 {
 	return (ticks * 1000) / hwkhz(hw);
 }
 /* Microseconds to chip HZ */
 static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
 {
 	return hwkhz(hw) * usec / 1000;
 }
 static int skge_get_coalesce(struct net_device *dev,
 			     struct ethtool_coalesce *ecmd)
 {
 	struct skge_port *skge = netdev_priv(dev);
 	struct skge_hw *hw = skge->hw;
 	int port = skge->port;
 	ecmd->rx_coalesce_usecs = 0;
 	ecmd->tx_coalesce_usecs = 0;
 	if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
 		u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
 		u32 msk = skge_read32(hw, B2_IRQM_MSK);
 		if (msk & rxirqmask[port])
 			ecmd->rx_coalesce_usecs = delay;
 		if (msk & txirqmask[port])
 			ecmd->tx_coalesce_usecs = delay;
 	}
 	return 0;
 }
 /* Note: interrupt timer is per board, but can turn on/off per port */
 static int skge_set_coalesce(struct net_device *dev,
 			     struct ethtool_coalesce *ecmd)
 {
 	struct skge_port *skge = netdev_priv(dev);
 	struct skge_hw *hw = skge->hw;
 	int port = skge->port;
 	u32 msk = skge_read32(hw, B2_IRQM_MSK);
 	u32 delay = 25;
 	if (ecmd->rx_coalesce_usecs == 0)
 		msk &= ~rxirqmask[port];
 	else if (ecmd->rx_coalesce_usecs < 25 ||
 		 ecmd->rx_coalesce_usecs > 33333)
 		return -EINVAL;
 	else {
 		msk |= rxirqmask[port];
 		delay = ecmd->rx_coalesce_usecs;
 	}
 	if (ecmd->tx_coalesce_usecs == 0)
 		msk &= ~txirqmask[port];
 	else if (ecmd->tx_coalesce_usecs < 25 ||
 		 ecmd->tx_coalesce_usecs > 33333)
 		return -EINVAL;
 	else {
 		msk |= txirqmask[port];
 		delay = min(delay, ecmd->rx_coalesce_usecs);
 	}
 	skge_write32(hw, B2_IRQM_MSK, msk);
 	if (msk == 0)
 		skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
 	else {
 		skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
 		skge_write32(hw, B2_IRQM_CTRL, TIM_START);
 	}
 	return 0;
 }
 enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
 static void skge_led(struct skge_port *skge, enum led_mode mode)
 {
 	struct skge_hw *hw = skge->hw;
 	int port = skge->port;
 	spin_lock_bh(&hw->phy_lock);
 	if (hw->chip_id == CHIP_ID_GENESIS) {
 		switch (mode) {
 		case LED_MODE_OFF:
 			xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
 			skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
 			skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
 			skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
 			break;
 		case LED_MODE_ON:
 			skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
 			skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
 			skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
 			skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
 			break;
 		case LED_MODE_TST:
 			skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
 			skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
 			skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
 			xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
 			break;
 		}
 	} else {
 		switch (mode) {
 		case LED_MODE_OFF:
 			gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
 			gm_phy_write(hw, port, PHY_MARV_LED_OVER,
 				     PHY_M_LED_MO_DUP(MO_LED_OFF)  |
 				     PHY_M_LED_MO_10(MO_LED_OFF)   |
 				     PHY_M_LED_MO_100(MO_LED_OFF)  |
 				     PHY_M_LED_MO_1000(MO_LED_OFF) |
 				     PHY_M_LED_MO_RX(MO_LED_OFF));
 			break;
 		case LED_MODE_ON:
 			gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
 				     PHY_M_LED_PULS_DUR(PULS_170MS) |
 				     PHY_M_LED_BLINK_RT(BLINK_84MS) |
 				     PHY_M_LEDC_TX_CTRL |
 				     PHY_M_LEDC_DP_CTRL);
 			gm_phy_write(hw, port, PHY_MARV_LED_OVER,
 				     PHY_M_LED_MO_RX(MO_LED_OFF) |
 				     (skge->speed == SPEED_100 ?
 				      PHY_M_LED_MO_100(MO_LED_ON) : 0));
 			break;
 		case LED_MODE_TST:
 			gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
 			gm_phy_write(hw, port, PHY_MARV_LED_OVER,
 				     PHY_M_LED_MO_DUP(MO_LED_ON)  |
 				     PHY_M_LED_MO_10(MO_LED_ON)   |
 				     PHY_M_LED_MO_100(MO_LED_ON)  |
 				     PHY_M_LED_MO_1000(MO_LED_ON) |
 				     PHY_M_LED_MO_RX(MO_LED_ON));
 		}
 	}
 	spin_unlock_bh(&hw->phy_lock);
 }
 /* blink LED's for finding board */
 static int skge_phys_id(struct net_device *dev, u32 data)
 {
 	struct skge_port *skge = netdev_priv(dev);
 	unsigned long ms;
 	enum led_mode mode = LED_MODE_TST;
 	if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
 		ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT / HZ) * 1000;
 	else
 		ms = data * 1000;
 	while (ms > 0) {
 		skge_led(skge, mode);
 		mode ^= LED_MODE_TST;
 		if (msleep_interruptible(BLINK_MS))
 			break;
 		ms -= BLINK_MS;
 	}
 	/* back to regular LED state */
 	skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
 	return 0;
 }
 static struct ethtool_ops skge_ethtool_ops = {
 	.get_settings	= skge_get_settings,
 	.set_settings	= skge_set_settings,
 	.get_drvinfo	= skge_get_drvinfo,
 	.get_regs_len	= skge_get_regs_len,
 	.get_regs	= skge_get_regs,
 	.get_wol	= skge_get_wol,
 	.set_wol	= skge_set_wol,
 	.get_msglevel	= skge_get_msglevel,
 	.set_msglevel	= skge_set_msglevel,
 	.nway_reset	= skge_nway_reset,
 	.get_link	= ethtool_op_get_link,
 	.get_ringparam	= skge_get_ring_param,
 	.set_ringparam	= skge_set_ring_param,
 	.get_pauseparam = skge_get_pauseparam,
 	.set_pauseparam = skge_set_pauseparam,
 	.get_coalesce	= skge_get_coalesce,
 	.set_coalesce	= skge_set_coalesce,
 	.get_sg		= ethtool_op_get_sg,
 	.set_sg		= skge_set_sg,
 	.get_tx_csum	= ethtool_op_get_tx_csum,
 	.set_tx_csum	= skge_set_tx_csum,
 	.get_rx_csum	= skge_get_rx_csum,
 	.set_rx_csum	= skge_set_rx_csum,
 	.get_strings	= skge_get_strings,
 	.phys_id	= skge_phys_id,
 	.get_stats_count = skge_get_stats_count,
 	.get_ethtool_stats = skge_get_ethtool_stats,
 	.get_perm_addr	= ethtool_op_get_perm_addr,
 };
 /*
  * Allocate ring elements and chain them together
  * One-to-one association of board descriptors with ring elements
  */
 static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base)
 {
 	struct skge_tx_desc *d;
 	struct skge_element *e;
 	int i;
 	ring->start = kcalloc(sizeof(*e), ring->count, GFP_KERNEL);
 	if (!ring->start)
 		return -ENOMEM;
 	for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
 		e->desc = d;
 		if (i == ring->count - 1) {
 			e->next = ring->start;
 			d->next_offset = base;
 		} else {
 			e->next = e + 1;
 			d->next_offset = base + (i+1) * sizeof(*d);
 		}
 	}
 	ring->to_use = ring->to_clean = ring->start;
 	return 0;
 }
 /* Allocate and setup a new buffer for receiving */
 static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,
 			  struct sk_buff *skb, unsigned int bufsize)
 {
 	struct skge_rx_desc *rd = e->desc;
 	u64 map;
 	map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
 			     PCI_DMA_FROMDEVICE);
 	rd->dma_lo = map;
 	rd->dma_hi = map >> 32;
 	e->skb = skb;
 	rd->csum1_start = ETH_HLEN;
 	rd->csum2_start = ETH_HLEN;
 	rd->csum1 = 0;
 	rd->csum2 = 0;
 	wmb();
 	rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
 	pci_unmap_addr_set(e, mapaddr, map);
 	pci_unmap_len_set(e, maplen, bufsize);
 }
 /* Resume receiving using existing skb,
  * Note: DMA address is not changed by chip.
  * 	 MTU not changed while receiver active.
  */
 static void skge_rx_reuse(struct skge_element *e, unsigned int size)
 {
 	struct skge_rx_desc *rd = e->desc;
 	rd->csum2 = 0;
 	rd->csum2_start = ETH_HLEN;
 	wmb();
 	rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
 }
 /* Free all  buffers in receive ring, assumes receiver stopped */
 static void skge_rx_clean(struct skge_port *skge)
 {
 	struct skge_hw *hw = skge->hw;
 	struct skge_ring *ring = &skge->rx_ring;
 	struct skge_element *e;
 	e = ring->start;
 	do {
 		struct skge_rx_desc *rd = e->desc;
 		rd->control = 0;
 		if (e->skb) {
 			pci_unmap_single(hw->pdev,
 					 pci_unmap_addr(e, mapaddr),
 					 pci_unmap_len(e, maplen),
 					 PCI_DMA_FROMDEVICE);
 			dev_kfree_skb(e->skb);
 			e->skb = NULL;
 		}
 	} while ((e = e->next) != ring->start);
 }
 /* Allocate buffers for receive ring
  * For receive:  to_clean is next received frame.
  */
 static int skge_rx_fill(struct skge_port *skge)
 {
 	struct skge_ring *ring = &skge->rx_ring;
 	struct skge_element *e;
 	e = ring->start;
 	do {
 		struct sk_buff *skb;
 		skb = dev_alloc_skb(skge->rx_buf_size + NET_IP_ALIGN);
 		if (!skb)
 			return -ENOMEM;
 		skb_reserve(skb, NET_IP_ALIGN);
 		skge_rx_setup(skge, e, skb, skge->rx_buf_size);
 	} while ( (e = e->next) != ring->start);
 	ring->to_clean = ring->start;
 	return 0;
 }
 static void skge_link_up(struct skge_port *skge)
 {
 	skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
 		    LED_BLK_OFF|LED_SYNC_OFF|LED_ON);
 	netif_carrier_on(skge->netdev);
 	if (skge->tx_avail > MAX_SKB_FRAGS + 1)
 		netif_wake_queue(skge->netdev);
 	if (netif_msg_link(skge))
 		printk(KERN_INFO PFX
 		       "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
 		       skge->netdev->name, skge->speed,
 		       skge->duplex == DUPLEX_FULL ? "full" : "half",
 		       (skge->flow_control == FLOW_MODE_NONE) ? "none" :
 		       (skge->flow_control == FLOW_MODE_LOC_SEND) ? "tx only" :
 		       (skge->flow_control == FLOW_MODE_REM_SEND) ? "rx only" :
 		       (skge->flow_control == FLOW_MODE_SYMMETRIC) ? "tx and rx" :
 		       "unknown");
 }
 static void skge_link_down(struct skge_port *skge)
 {
 	skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
 	netif_carrier_off(skge->netdev);
 	netif_stop_queue(skge->netdev);
 	if (netif_msg_link(skge))
 		printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);
 }
 static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
 {
 	int i;
 	xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
 	*val = xm_read16(hw, port, XM_PHY_DATA);
 	for (i = 0; i < PHY_RETRIES; i++) {
 		if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
 			goto ready;
 		udelay(1);
 	}
 	return -ETIMEDOUT;
  ready:
 	*val = xm_read16(hw, port, XM_PHY_DATA);
 	return 0;
 }
 static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
 {
 	u16 v = 0;
 	if (__xm_phy_read(hw, port, reg, &v))
 		printk(KERN_WARNING PFX "%s: phy read timed out\n",
 		       hw->dev[port]->name);
 	return v;
 }
 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
 {
 	int i;
 	xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
 	for (i = 0; i < PHY_RETRIES; i++) {
 		if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
 			goto ready;
 		udelay(1);
 	}
 	return -EIO;
  ready:
 	xm_write16(hw, port, XM_PHY_DATA, val);
 	for (i = 0; i < PHY_RETRIES; i++) {
 		if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
 			return 0;
 		udelay(1);
 	}
 	return -ETIMEDOUT;
 }
 static void genesis_init(struct skge_hw *hw)
 {
 	/* set blink source counter */
 	skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
 	skge_write8(hw, B2_BSC_CTRL, BSC_START);
 	/* configure mac arbiter */
 	skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
 	/* configure mac arbiter timeout values */
 	skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
 	skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
 	skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
 	skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
 	skge_write8(hw, B3_MA_RCINI_RX1, 0);
 	skge_write8(hw, B3_MA_RCINI_RX2, 0);
 	skge_write8(hw, B3_MA_RCINI_TX1, 0);
 	skge_write8(hw, B3_MA_RCINI_TX2, 0);
 	/* configure packet arbiter timeout */
 	skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
 	skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
 	skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
 	skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
 	skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
 }
 static void genesis_reset(struct skge_hw *hw, int port)
 {
 	const u8 zero[8]  = { 0 };
 	skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
 	/* reset the statistics module */
 	xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
 	xm_write16(hw, port, XM_IMSK, 0xffff);	/* disable XMAC IRQs */
 	xm_write32(hw, port, XM_MODE, 0);		/* clear Mode Reg */
 	xm_write16(hw, port, XM_TX_CMD, 0);	/* reset TX CMD Reg */
 	xm_write16(hw, port, XM_RX_CMD, 0);	/* reset RX CMD Reg */
 	/* disable Broadcom PHY IRQ */
 	xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
 	xm_outhash(hw, port, XM_HSM, zero);
 }
 /* Convert mode to MII values  */
 static const u16 phy_pause_map[] = {
 	[FLOW_MODE_NONE] =	0,
 	[FLOW_MODE_LOC_SEND] =	PHY_AN_PAUSE_ASYM,
 	[FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
 	[FLOW_MODE_REM_SEND]  = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
 };
 /* Check status of Broadcom phy link */
 static void bcom_check_link(struct skge_hw *hw, int port)
 {
 	struct net_device *dev = hw->dev[port];
 	struct skge_port *skge = netdev_priv(dev);
 	u16 status;
 	/* read twice because of latch */
 	(void) xm_phy_read(hw, port, PHY_BCOM_STAT);
 	status = xm_phy_read(hw, port, PHY_BCOM_STAT);
 	if ((status & PHY_ST_LSYNC) == 0) {
 		u16 cmd = xm_read16(hw, port, XM_MMU_CMD);
 		cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
 		xm_write16(hw, port, XM_MMU_CMD, cmd);
 		/* dummy read to ensure writing */
 		(void) xm_read16(hw, port, XM_MMU_CMD);
 		if (netif_carrier_ok(dev))
 			skge_link_down(skge);
 	} else {
 		if (skge->autoneg == AUTONEG_ENABLE &&
 		    (status & PHY_ST_AN_OVER)) {
 			u16 lpa = xm_phy_read(hw, port, PHY_BCOM_AUNE_LP);
 			u16 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
 			if (lpa & PHY_B_AN_RF) {
 				printk(KERN_NOTICE PFX "%s: remote fault\n",
 				       dev->name);
 				return;
 			}
 			/* Check Duplex mismatch */
 			switch (aux & PHY_B_AS_AN_RES_MSK) {
 			case PHY_B_RES_1000FD:
 				skge->duplex = DUPLEX_FULL;
 				break;
 			case PHY_B_RES_1000HD:
 				skge->duplex = DUPLEX_HALF;
 				break;
 			default:
 				printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
 				       dev->name);
 				return;
 			}
 			/* We are using IEEE 802.3z/D5.0 Table 37-4 */
 			switch (aux & PHY_B_AS_PAUSE_MSK) {
 			case PHY_B_AS_PAUSE_MSK:
 				skge->flow_control = FLOW_MODE_SYMMETRIC;
 				break;
 			case PHY_B_AS_PRR:
 				skge->flow_control = FLOW_MODE_REM_SEND;
 				break;
 			case PHY_B_AS_PRT:
 				skge->flow_control = FLOW_MODE_LOC_SEND;
 				break;
 			default:
 				skge->flow_control = FLOW_MODE_NONE;
 			}
 			skge->speed = SPEED_1000;
 		}
 		if (!netif_carrier_ok(dev))
 			genesis_link_up(skge);
 	}
 }
 /* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
  * Phy on for 100 or 10Mbit operation
  */
 static void bcom_phy_init(struct skge_port *skge, int jumbo)
 {
 	struct skge_hw *hw = skge->hw;
 	int port = skge->port;
 	int i;
 	u16 id1, r, ext, ctl;
 	/* magic workaround patterns for Broadcom */
 	static const struct {
 		u16 reg;
 		u16 val;
 	} A1hack[] = {
 		{ 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
 		{ 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
 		{ 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
 		{ 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
 	}, C0hack[] = {
 		{ 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
 		{ 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
 	};
 	/* read Id from external PHY (all have the same address) */
 	id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
 	/* Optimize MDIO transfer by suppressing preamble. */
 	r = xm_read16(hw, port, XM_MMU_CMD);
 	r |=  XM_MMU_NO_PRE;
 	xm_write16(hw, port, XM_MMU_CMD,r);
 	switch (id1) {
 	case PHY_BCOM_ID1_C0:
 		/*
 		 * Workaround BCOM Errata for the C0 type.
 		 * Write magic patterns to reserved registers.
 		 */
 		for (i = 0; i < ARRAY_SIZE(C0hack); i++)
 			xm_phy_write(hw, port,
 				     C0hack[i].reg, C0hack[i].val);
 		break;
 	case PHY_BCOM_ID1_A1:
 		/*
 		 * Workaround BCOM Errata for the A1 type.
 		 * Write magic patterns to reserved registers.
 		 */
 		for (i = 0; i < ARRAY_SIZE(A1hack); i++)
 			xm_phy_write(hw, port,
 				     A1hack[i].reg, A1hack[i].val);
 		break;
 	}
 	/*
 	 * Workaround BCOM Errata (#10523) for all BCom PHYs.
 	 * Disable Power Management after reset.
 	 */
 	r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
 	r |= PHY_B_AC_DIS_PM;
 	xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
 	/* Dummy read */
 	xm_read16(hw, port, XM_ISRC);
 	ext = PHY_B_PEC_EN_LTR; /* enable tx led */
 	ctl = PHY_CT_SP1000;	/* always 1000mbit */
 	if (skge->autoneg == AUTONEG_ENABLE) {
 		/*
 		 * Workaround BCOM Errata #1 for the C5 type.
 		 * 1000Base-T Link Acquisition Failure in Slave Mode
 		 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
 		 */
 		u16 adv = PHY_B_1000C_RD;
 		if (skge->advertising & ADVERTISED_1000baseT_Half)
 			adv |= PHY_B_1000C_AHD;
 		if (skge->advertising & ADVERTISED_1000baseT_Full)
 			adv |= PHY_B_1000C_AFD;
 		xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
 		ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
 	} else {
 		if (skge->duplex == DUPLEX_FULL)
 			ctl |= PHY_CT_DUP_MD;
 		/* Force to slave */
 		xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
 	}
 	/* Set autonegotiation pause parameters */
 	xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
 		     phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
 	/* Handle Jumbo frames */
 	if (jumbo) {
 		xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
 			     PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
 		ext |= PHY_B_PEC_HIGH_LA;
 	}
 	xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
 	xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
 	/* Use link status change interrupt */
 	xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
 	bcom_check_link(hw, port);
 }
 static void genesis_mac_init(struct skge_hw *hw, int port)
 {
 	struct net_device *dev = hw->dev[port];
 	struct skge_port *skge = netdev_priv(dev);
 	int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
 	int i;
 	u32 r;
 	const u8 zero[6]  = { 0 };
 	for (i = 0; i < 10; i++) {
 		skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
 			     MFF_SET_MAC_RST);
 		if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)
 			goto reset_ok;
 		udelay(1);
 	}
 	printk(KERN_WARNING PFX "%s: genesis reset failed\n", dev->name);
  reset_ok:
 	/* Unreset the XMAC. */
 	skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
 	/*
 	 * Perform additional initialization for external PHYs,
 	 * namely for the 1000baseTX cards that use the XMAC's
 	 * GMII mode.
 	 */
 	/* Take external Phy out of reset */
 	r = skge_read32(hw, B2_GP_IO);
 	if (port == 0)
 		r |= GP_DIR_0|GP_IO_0;
 	else
 		r |= GP_DIR_2|GP_IO_2;
 	skge_write32(hw, B2_GP_IO, r);
 	/* Enable GMII interface */
 	xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
 	bcom_phy_init(skge, jumbo);
 	/* Set Station Address */
 	xm_outaddr(hw, port, XM_SA, dev->dev_addr);
 	/* We don't use match addresses so clear */
 	for (i = 1; i < 16; i++)
 		xm_outaddr(hw, port, XM_EXM(i), zero);
 	/* Clear MIB counters */
 	xm_write16(hw, port, XM_STAT_CMD,
 			XM_SC_CLR_RXC | XM_SC_CLR_TXC);
 	/* Clear two times according to Errata #3 */
 	xm_write16(hw, port, XM_STAT_CMD,
 			XM_SC_CLR_RXC | XM_SC_CLR_TXC);
 	/* configure Rx High Water Mark (XM_RX_HI_WM) */
 	xm_write16(hw, port, XM_RX_HI_WM, 1450);
 	/* We don't need the FCS appended to the packet. */
 	r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
 	if (jumbo)
 		r |= XM_RX_BIG_PK_OK;
 	if (skge->duplex == DUPLEX_HALF) {
 		/*
 		 * If in manual half duplex mode the other side might be in
 		 * full duplex mode, so ignore if a carrier extension is not seen
 		 * on frames received
 		 */
 		r |= XM_RX_DIS_CEXT;
 	}
 	xm_write16(hw, port, XM_RX_CMD, r);
 	/* We want short frames padded to 60 bytes. */
 	xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
 	/*
 	 * Bump up the transmit threshold. This helps hold off transmit
 	 * underruns when we're blasting traffic from both ports at once.
 	 */
 	xm_write16(hw, port, XM_TX_THR, 512);
 	/*
 	 * Enable the reception of all error frames. This is is
 	 * a necessary evil due to the design of the XMAC. The
 	 * XMAC's receive FIFO is only 8K in size, however jumbo
 	 * frames can be up to 9000 bytes in length. When bad
 	 * frame filtering is enabled, the XMAC's RX FIFO operates
 	 * in 'store and forward' mode. For this to work, the
 	 * entire frame has to fit into the FIFO, but that means
 	 * that jumbo frames larger than 8192 bytes will be
 	 * truncated. Disabling all bad frame filtering causes
 	 * the RX FIFO to operate in streaming mode, in which
 	 * case the XMAC will start transferring frames out of the
 	 * RX FIFO as soon as the FIFO threshold is reached.
 	 */
 	xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
 	/*
 	 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
 	 *	- Enable all bits excepting 'Octets Rx OK Low CntOv'
 	 *	  and 'Octets Rx OK Hi Cnt Ov'.
 	 */
 	xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
 	/*
 	 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
 	 *	- Enable all bits excepting 'Octets Tx OK Low CntOv'
 	 *	  and 'Octets Tx OK Hi Cnt Ov'.
 	 */
 	xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
 	/* Configure MAC arbiter */
 	skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
 	/* configure timeout values */
 	skge_write8(hw, B3_MA_TOINI_RX1, 72);
 	skge_write8(hw, B3_MA_TOINI_RX2, 72);
 	skge_write8(hw, B3_MA_TOINI_TX1, 72);
 	skge_write8(hw, B3_MA_TOINI_TX2, 72);
 	skge_write8(hw, B3_MA_RCINI_RX1, 0);
 	skge_write8(hw, B3_MA_RCINI_RX2, 0);
 	skge_write8(hw, B3_MA_RCINI_TX1, 0);
 	skge_write8(hw, B3_MA_RCINI_TX2, 0);
 	/* Configure Rx MAC FIFO */
 	skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
 	skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
 	skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
 	/* Configure Tx MAC FIFO */
 	skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
 	skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
 	skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
 	if (jumbo) {
 		/* Enable frame flushing if jumbo frames used */
 		skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
 	} else {
 		/* enable timeout timers if normal frames */
 		skge_write16(hw, B3_PA_CTRL,
 			     (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
 	}
 }
 static void genesis_stop(struct skge_port *skge)
 {
 	struct skge_hw *hw = skge->hw;
 	int port = skge->port;
 	u32 reg;
 	genesis_reset(hw, port);
 	/* Clear Tx packet arbiter timeout IRQ */
 	skge_write16(hw, B3_PA_CTRL,
 		     port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
 	/*
 	 * If the transfer sticks at the MAC the STOP command will not
 	 * terminate if we don't flush the XMAC's transmit FIFO !
 	 */
 	xm_write32(hw, port, XM_MODE,
 			xm_read32(hw, port, XM_MODE)|XM_MD_FTF);
 	/* Reset the MAC */
 	skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
 	/* For external PHYs there must be special handling */
 	reg = skge_read32(hw, B2_GP_IO);
 	if (port == 0) {
 		reg |= GP_DIR_0;
 		reg &= ~GP_IO_0;
 	} else {
 		reg |= GP_DIR_2;
 		reg &= ~GP_IO_2;
 	}
 	skge_write32(hw, B2_GP_IO, reg);
 	skge_read32(hw, B2_GP_IO);
 	xm_write16(hw, port, XM_MMU_CMD,
 			xm_read16(hw, port, XM_MMU_CMD)
 			& ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
 	xm_read16(hw, port, XM_MMU_CMD);
 }
 static void genesis_get_stats(struct skge_port *skge, u64 *data)
 {
 	struct skge_hw *hw = skge->hw;
 	int port = skge->port;
 	int i;
 	unsigned long timeout = jiffies + HZ;
 	xm_write16(hw, port,
 			XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
 	/* wait for update to complete */
 	while (xm_read16(hw, port, XM_STAT_CMD)
 	       & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
 		if (time_after(jiffies, timeout))
 			break;
 		udelay(10);
 	}
 	/* special case for 64 bit octet counter */
 	data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
 		| xm_read32(hw, port, XM_TXO_OK_LO);
 	data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
 		| xm_read32(hw, port, XM_RXO_OK_LO);
 	for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
 		data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
 }
 static void genesis_mac_intr(struct skge_hw *hw, int port)
 {
 	struct skge_port *skge = netdev_priv(hw->dev[port]);
 	u16 status = xm_read16(hw, port, XM_ISRC);
 	if (netif_msg_intr(skge))
 		printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
 		       skge->netdev->name, status);
 	if (status & XM_IS_TXF_UR) {
 		xm_write32(hw, port, XM_MODE, XM_MD_FTF);
 		++skge->net_stats.tx_fifo_errors;
 	}
 	if (status & XM_IS_RXF_OV) {
 		xm_write32(hw, port, XM_MODE, XM_MD_FRF);
 		++skge->net_stats.rx_fifo_errors;
 	}
 }
 static void genesis_link_up(struct skge_port *skge)
 {
 	struct skge_hw *hw = skge->hw;
 	int port = skge->port;
 	u16 cmd;
 	u32 mode, msk;
 	cmd = xm_read16(hw, port, XM_MMU_CMD);
 	/*
 	 * enabling pause frame reception is required for 1000BT
 	 * because the XMAC is not reset if the link is going down
 	 */
 	if (skge->flow_control == FLOW_MODE_NONE ||
 	    skge->flow_control == FLOW_MODE_LOC_SEND)
 		/* Disable Pause Frame Reception */
 		cmd |= XM_MMU_IGN_PF;
 	else
 		/* Enable Pause Frame Reception */
 		cmd &= ~XM_MMU_IGN_PF;
 	xm_write16(hw, port, XM_MMU_CMD, cmd);
 	mode = xm_read32(hw, port, XM_MODE);
 	if (skge->flow_control == FLOW_MODE_SYMMETRIC ||
 	    skge->flow_control == FLOW_MODE_LOC_SEND) {
 		/*
 		 * Configure Pause Frame Generation
 		 * Use internal and external Pause Frame Generation.
 		 * Sending pause frames is edge triggered.
 		 * Send a Pause frame with the maximum pause time if
 		 * internal oder external FIFO full condition occurs.
 		 * Send a zero pause time frame to re-start transmission.
 		 */
 		/* XM_PAUSE_DA = '010000C28001' (default) */
 		/* XM_MAC_PTIME = 0xffff (maximum) */
 		/* remember this value is defined in big endian (!) */
 		xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
 		mode |= XM_PAUSE_MODE;
 		skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
 	} else {
 		/*
 		 * disable pause frame generation is required for 1000BT
 		 * because the XMAC is not reset if the link is going down
 		 */
 		/* Disable Pause Mode in Mode Register */
 		mode &= ~XM_PAUSE_MODE;
 		skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
 	}
 	xm_write32(hw, port, XM_MODE, mode);
 	msk = XM_DEF_MSK;
 	/* disable GP0 interrupt bit for external Phy */
 	msk |= XM_IS_INP_ASS;
 	xm_write16(hw, port, XM_IMSK, msk);
 	xm_read16(hw, port, XM_ISRC);
 	/* get MMU Command Reg. */
 	cmd = xm_read16(hw, port, XM_MMU_CMD);
 	if (skge->duplex == DUPLEX_FULL)
 		cmd |= XM_MMU_GMII_FD;
 	/*
 	 * Workaround BCOM Errata (#10523) for all BCom Phys
 	 * Enable Power Management after link up
 	 */
 	xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
 		     xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
 		     & ~PHY_B_AC_DIS_PM);
 	xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
 	/* enable Rx/Tx */
 	xm_write16(hw, port, XM_MMU_CMD,
 			cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
 	skge_link_up(skge);
 }
 static inline void bcom_phy_intr(struct skge_port *skge)
 {
 	struct skge_hw *hw = skge->hw;
 	int port = skge->port;
 	u16 isrc;
 	isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
 	if (netif_msg_intr(skge))
 		printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x\n",
 		       skge->netdev->name, isrc);
 	if (isrc & PHY_B_IS_PSE)
 		printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n",
 		       hw->dev[port]->name);
 	/* Workaround BCom Errata:
 	 *	enable and disable loopback mode if "NO HCD" occurs.
 	 */
 	if (isrc & PHY_B_IS_NO_HDCL) {
 		u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
 		xm_phy_write(hw, port, PHY_BCOM_CTRL,
 				  ctrl | PHY_CT_LOOP);
 		xm_phy_write(hw, port, PHY_BCOM_CTRL,
 				  ctrl & ~PHY_CT_LOOP);
 	}
 	if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
 		bcom_check_link(hw, port);
 }
 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
 {
 	int i;
 	gma_write16(hw, port, GM_SMI_DATA, val);
 	gma_write16(hw, port, GM_SMI_CTRL,
 			 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
 	for (i = 0; i < PHY_RETRIES; i++) {
 		udelay(1);
 		if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
 			return 0;
 	}
 	printk(KERN_WARNING PFX "%s: phy write timeout\n",
 	       hw->dev[port]->name);
 	return -EIO;
 }
 static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
 {
 	int i;
 	gma_write16(hw, port, GM_SMI_CTRL,
 			 GM_SMI_CT_PHY_AD(hw->phy_addr)
 			 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
 	for (i = 0; i < PHY_RETRIES; i++) {
 		udelay(1);
 		if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
 			goto ready;
 	}
 	return -ETIMEDOUT;
  ready:
 	*val = gma_read16(hw, port, GM_SMI_DATA);
 	return 0;
 }
 static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
 {
 	u16 v = 0;
 	if (__gm_phy_read(hw, port, reg, &v))
 		printk(KERN_WARNING PFX "%s: phy read timeout\n",
 	       hw->dev[port]->name);
 	return v;
 }
 /* Marvell Phy Initialization */
 static void yukon_init(struct skge_hw *hw, int port)
 {
 	struct skge_port *skge = netdev_priv(hw->dev[port]);
 	u16 ctrl, ct1000, adv;
 	if (skge->autoneg == AUTONEG_ENABLE) {
 		u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
 		ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
 			  PHY_M_EC_MAC_S_MSK);
 		ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
 		ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
 		gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
 	}
 	ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
 	if (skge->autoneg == AUTONEG_DISABLE)
 		ctrl &= ~PHY_CT_ANE;
 	ctrl |= PHY_CT_RESET;
 	gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
 	ctrl = 0;
 	ct1000 = 0;
 	adv = PHY_AN_CSMA;
 	if (skge->autoneg == AUTONEG_ENABLE) {
 		if (hw->copper) {
 			if (skge->advertising & ADVERTISED_1000baseT_Full)
 				ct1000 |= PHY_M_1000C_AFD;
 			if (skge->advertising & ADVERTISED_1000baseT_Half)
 				ct1000 |= PHY_M_1000C_AHD;
 			if (skge->advertising & ADVERTISED_100baseT_Full)
 				adv |= PHY_M_AN_100_FD;
 			if (skge->advertising & ADVERTISED_100baseT_Half)
 				adv |= PHY_M_AN_100_HD;
 			if (skge->advertising & ADVERTISED_10baseT_Full)
 				adv |= PHY_M_AN_10_FD;
 			if (skge->advertising & ADVERTISED_10baseT_Half)
 				adv |= PHY_M_AN_10_HD;
 		} else	/* special defines for FIBER (88E1011S only) */
 			adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
 		/* Set Flow-control capabilities */
 		adv |= phy_pause_map[skge->flow_control];
 		/* Restart Auto-negotiation */
 		ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
 	} else {
 		/* forced speed/duplex settings */
 		ct1000 = PHY_M_1000C_MSE;
 		if (skge->duplex == DUPLEX_FULL)
 			ctrl |= PHY_CT_DUP_MD;
 		switch (skge->speed) {
 		case SPEED_1000:
 			ctrl |= PHY_CT_SP1000;
 			break;
 		case SPEED_100:
 			ctrl |= PHY_CT_SP100;
 			break;
 		}
 		ctrl |= PHY_CT_RESET;
 	}
 	gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
 	gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
 	gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
 	/* Enable phy interrupt on autonegotiation complete (or link up) */
 	if (skge->autoneg == AUTONEG_ENABLE)
 		gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
 	else
 		gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
 }
 static void yukon_reset(struct skge_hw *hw, int port)
 {
 	gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
 	gma_write16(hw, port, GM_MC_ADDR_H1, 0);	/* clear MC hash */
 	gma_write16(hw, port, GM_MC_ADDR_H2, 0);
 	gma_write16(hw, port, GM_MC_ADDR_H3, 0);
 	gma_write16(hw, port, GM_MC_ADDR_H4, 0);
 	gma_write16(hw, port, GM_RX_CTRL,
 			 gma_read16(hw, port, GM_RX_CTRL)
 			 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
 }
 /* Apparently, early versions of Yukon-Lite had wrong chip_id? */
 static int is_yukon_lite_a0(struct skge_hw *hw)
 {
 	u32 reg;
 	int ret;
 	if (hw->chip_id != CHIP_ID_YUKON)
 		return 0;
 	reg = skge_read32(hw, B2_FAR);
 	skge_write8(hw, B2_FAR + 3, 0xff);
 	ret = (skge_read8(hw, B2_FAR + 3) != 0);
 	skge_write32(hw, B2_FAR, reg);
 	return ret;
 }
 static void yukon_mac_init(struct skge_hw *hw, int port)
 {
 	struct skge_port *skge = netdev_priv(hw->dev[port]);
 	int i;
 	u32 reg;
 	const u8 *addr = hw->dev[port]->dev_addr;
 	/* WA code for COMA mode -- set PHY reset */
 	if (hw->chip_id == CHIP_ID_YUKON_LITE &&
 	    hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
 		reg = skge_read32(hw, B2_GP_IO);
 		reg |= GP_DIR_9 | GP_IO_9;
 		skge_write32(hw, B2_GP_IO, reg);
 	}
 	/* hard reset */
 	skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
 	skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
 	/* WA code for COMA mode -- clear PHY reset */
 	if (hw->chip_id == CHIP_ID_YUKON_LITE &&
 	    hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
 		reg = skge_read32(hw, B2_GP_IO);
 		reg |= GP_DIR_9;
 		reg &= ~GP_IO_9;
 		skge_write32(hw, B2_GP_IO, reg);
 	}
 	/* Set hardware config mode */
 	reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
 		GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
 	reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
 	/* Clear GMC reset */
 	skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
 	skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
 	skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
 	if (skge->autoneg == AUTONEG_DISABLE) {
 		reg = GM_GPCR_AU_ALL_DIS;
 		gma_write16(hw, port, GM_GP_CTRL,
 				 gma_read16(hw, port, GM_GP_CTRL) | reg);
 		switch (skge->speed) {
 		case SPEED_1000:
 			reg &= ~GM_GPCR_SPEED_100;
 			reg |= GM_GPCR_SPEED_1000;
 			break;
 		case SPEED_100:
 			reg &= ~GM_GPCR_SPEED_1000;
 			reg |= GM_GPCR_SPEED_100;
 			break;
 		case SPEED_10:
 			reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
 			break;
 		}
 		if (skge->duplex == DUPLEX_FULL)
 			reg |= GM_GPCR_DUP_FULL;
 	} else
 		reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
 	switch (skge->flow_control) {
 	case FLOW_MODE_NONE:
 		skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
 		reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
 		break;
 	case FLOW_MODE_LOC_SEND:
 		/* disable Rx flow-control */
 		reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
 	}
 	gma_write16(hw, port, GM_GP_CTRL, reg);
 	skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
 	yukon_init(hw, port);
 	/* MIB clear */
 	reg = gma_read16(hw, port, GM_PHY_ADDR);
 	gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
 	for (i = 0; i < GM_MIB_CNT_SIZE; i++)
 		gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
 	gma_write16(hw, port, GM_PHY_ADDR, reg);
 	/* transmit control */
 	gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
 	/* receive control reg: unicast + multicast + no FCS  */
 	gma_write16(hw, port, GM_RX_CTRL,
 			 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
 	/* transmit flow control */
 	gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
 	/* transmit parameter */
 	gma_write16(hw, port, GM_TX_PARAM,
 			 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
 			 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
 			 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
 	/* serial mode register */
 	reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
 	if (hw->dev[port]->mtu > 1500)
 		reg |= GM_SMOD_JUMBO_ENA;
 	gma_write16(hw, port, GM_SERIAL_MODE, reg);
 	/* physical address: used for pause frames */
 	gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
 	/* virtual address for data */
 	gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
 	/* enable interrupt mask for counter overflows */
 	gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
 	gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
 	gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
 	/* Initialize Mac Fifo */
 	/* Configure Rx MAC FIFO */
 	skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
 	reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
 	/* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
 	if (is_yukon_lite_a0(hw))
 		reg &= ~GMF_RX_F_FL_ON;
 	skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
 	skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
 	/*
 	 * because Pause Packet Truncation in GMAC is not working
 	 * we have to increase the Flush Threshold to 64 bytes
 	 * in order to flush pause packets in Rx FIFO on Yukon-1
 	 */
 	skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
 	/* Configure Tx MAC FIFO */
 	skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
 	skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
 }
 /* Go into power down mode */
 static void yukon_suspend(struct skge_hw *hw, int port)
 {
 	u16 ctrl;
 	ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
 	ctrl |= PHY_M_PC_POL_R_DIS;
 	gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
 	ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
 	ctrl |= PHY_CT_RESET;
 	gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
 	/* switch IEEE compatible power down mode on */
 	ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
 	ctrl |= PHY_CT_PDOWN;
 	gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
 }
 static void yukon_stop(struct skge_port *skge)
 {
 	struct skge_hw *hw = skge->hw;
 	int port = skge->port;
 	skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
 	yukon_reset(hw, port);
 	gma_write16(hw, port, GM_GP_CTRL,
 			 gma_read16(hw, port, GM_GP_CTRL)
 			 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
 	gma_read16(hw, port, GM_GP_CTRL);
 	yukon_suspend(hw, port);
 	/* set GPHY Control reset */
 	skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
 	skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
 }
 static void yukon_get_stats(struct skge_port *skge, u64 *data)
 {
 	struct skge_hw *hw = skge->hw;
 	int port = skge->port;
 	int i;
 	data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
 		| gma_read32(hw, port, GM_TXO_OK_LO);
 	data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
 		| gma_read32(hw, port, GM_RXO_OK_LO);
 	for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
 		data[i] = gma_read32(hw, port,
 					  skge_stats[i].gma_offset);
 }
 static void yukon_mac_intr(struct skge_hw *hw, int port)
 {
 	struct net_device *dev = hw->dev[port];
 	struct skge_port *skge = netdev_priv(dev);
 	u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
 	if (netif_msg_intr(skge))
 		printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
 		       dev->name, status);
 	if (status & GM_IS_RX_FF_OR) {
 		++skge->net_stats.rx_fifo_errors;
 		skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
 	}
 	if (status & GM_IS_TX_FF_UR) {
 		++skge->net_stats.tx_fifo_errors;
 		skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
 	}
 }
 static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
 {
 	switch (aux & PHY_M_PS_SPEED_MSK) {
 	case PHY_M_PS_SPEED_1000:
 		return SPEED_1000;
 	case PHY_M_PS_SPEED_100:
 		return SPEED_100;
 	default:
 		return SPEED_10;
 	}
 }
 static void yukon_link_up(struct skge_port *skge)
 {
 	struct skge_hw *hw = skge->hw;
 	int port = skge->port;
 	u16 reg;
 	/* Enable Transmit FIFO Underrun */
 	skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
 	reg = gma_read16(hw, port, GM_GP_CTRL);
 	if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
 		reg |= GM_GPCR_DUP_FULL;
 	/* enable Rx/Tx */
 	reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
 	gma_write16(hw, port, GM_GP_CTRL, reg);
 	gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
 	skge_link_up(skge);
 }
 static void yukon_link_down(struct skge_port *skge)
 {
 	struct skge_hw *hw = skge->hw;
 	int port = skge->port;
 	u16 ctrl;
 	gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
 	ctrl = gma_read16(hw, port, GM_GP_CTRL);
 	ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
 	gma_write16(hw, port, GM_GP_CTRL, ctrl);
 	if (skge->flow_control == FLOW_MODE_REM_SEND) {
 		/* restore Asymmetric Pause bit */
 		gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
 				  gm_phy_read(hw, port,
 						   PHY_MARV_AUNE_ADV)
 				  | PHY_M_AN_ASP);
 	}
 	yukon_reset(hw, port);
 	skge_link_down(skge);
 	yukon_init(hw, port);
 }
 static void yukon_phy_intr(struct skge_port *skge)
 {
 	struct skge_hw *hw = skge->hw;
 	int port = skge->port;
 	const char *reason = NULL;
 	u16 istatus, phystat;
 	istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
 	phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
 	if (netif_msg_intr(skge))
 		printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x 0x%x\n",
 		       skge->netdev->name, istatus, phystat);
 	if (istatus & PHY_M_IS_AN_COMPL) {
 		if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
 		    & PHY_M_AN_RF) {
 			reason = "remote fault";
 			goto failed;
 		}
 		if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
 			reason = "master/slave fault";
 			goto failed;
 		}
 		if (!(phystat & PHY_M_PS_SPDUP_RES)) {
 			reason = "speed/duplex";
 			goto failed;
 		}
 		skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
 			? DUPLEX_FULL : DUPLEX_HALF;
 		skge->speed = yukon_speed(hw, phystat);
 		/* We are using IEEE 802.3z/D5.0 Table 37-4 */
 		switch (phystat & PHY_M_PS_PAUSE_MSK) {
 		case PHY_M_PS_PAUSE_MSK:
 			skge->flow_control = FLOW_MODE_SYMMETRIC;
 			break;
 		case PHY_M_PS_RX_P_EN:
 			skge->flow_control = FLOW_MODE_REM_SEND;
 			break;
 		case PHY_M_PS_TX_P_EN:
 			skge->flow_control = FLOW_MODE_LOC_SEND;
 			break;
 		default:
 			skge->flow_control = FLOW_MODE_NONE;
 		}
 		if (skge->flow_control == FLOW_MODE_NONE ||
 		    (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
 			skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
 		else
 			skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
 		yukon_link_up(skge);
 		return;
 	}
 	if (istatus & PHY_M_IS_LSP_CHANGE)
 		skge->speed = yukon_speed(hw, phystat);
 	if (istatus & PHY_M_IS_DUP_CHANGE)
 		skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
 	if (istatus & PHY_M_IS_LST_CHANGE) {
 		if (phystat & PHY_M_PS_LINK_UP)
 			yukon_link_up(skge);
 		else
 			yukon_link_down(skge);
 	}
 	return;
  failed:
 	printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n",
 	       skge->netdev->name, reason);
 	/* XXX restart autonegotiation? */
 }
 static void skge_phy_reset(struct skge_port *skge)
 {
 	struct skge_hw *hw = skge->hw;
 	int port = skge->port;
 	netif_stop_queue(skge->netdev);
 	netif_carrier_off(skge->netdev);
 	spin_lock_bh(&hw->phy_lock);
 	if (hw->chip_id == CHIP_ID_GENESIS) {
 		genesis_reset(hw, port);
 		genesis_mac_init(hw, port);
 	} else {
 		yukon_reset(hw, port);
 		yukon_init(hw, port);
 	}
 	spin_unlock_bh(&hw->phy_lock);
 }
 /* Basic MII support */
 static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
 {
 	struct mii_ioctl_data *data = if_mii(ifr);
 	struct skge_port *skge = netdev_priv(dev);
 	struct skge_hw *hw = skge->hw;
 	int err = -EOPNOTSUPP;
 	if (!netif_running(dev))
 		return -ENODEV;	/* Phy still in reset */
 	switch(cmd) {
 	case SIOCGMIIPHY:
 		data->phy_id = hw->phy_addr;
 		/* fallthru */
 	case SIOCGMIIREG: {
 		u16 val = 0;
 		spin_lock_bh(&hw->phy_lock);
 		if (hw->chip_id == CHIP_ID_GENESIS)
 			err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
 		else
 			err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
 		spin_unlock_bh(&hw->phy_lock);
 		data->val_out = val;
 		break;
 	}
 	case SIOCSMIIREG:
 		if (!capable(CAP_NET_ADMIN))
 			return -EPERM;
 		spin_lock_bh(&hw->phy_lock);
 		if (hw->chip_id == CHIP_ID_GENESIS)
 			err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
 				   data->val_in);
 		else
 			err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
 				   data->val_in);
 		spin_unlock_bh(&hw->phy_lock);
 		break;
 	}
 	return err;
 }
 static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
 {
 	u32 end;
 	start /= 8;
 	len /= 8;
 	end = start + len - 1;
 	skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
 	skge_write32(hw, RB_ADDR(q, RB_START), start);
 	skge_write32(hw, RB_ADDR(q, RB_WP), start);
 	skge_write32(hw, RB_ADDR(q, RB_RP), start);
 	skge_write32(hw, RB_ADDR(q, RB_END), end);
 	if (q == Q_R1 || q == Q_R2) {
 		/* Set thresholds on receive queue's */
 		skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
 			     start + (2*len)/3);
 		skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
 			     start + (len/3));
 	} else {
 		/* Enable store & forward on Tx queue's because
 		 * Tx FIFO is only 4K on Genesis and 1K on Yukon
 		 */
 		skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
 	}
 	skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
 }
 /* Setup Bus Memory Interface */
 static void skge_qset(struct skge_port *skge, u16 q,
 		      const struct skge_element *e)
 {
 	struct skge_hw *hw = skge->hw;
 	u32 watermark = 0x600;
 	u64 base = skge->dma + (e->desc - skge->mem);
 	/* optimization to reduce window on 32bit/33mhz */
 	if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
 		watermark /= 2;
 	skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
 	skge_write32(hw, Q_ADDR(q, Q_F), watermark);
 	skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
 	skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
 }
 static int skge_up(struct net_device *dev)
 {
 	struct skge_port *skge = netdev_priv(dev);
 	struct skge_hw *hw = skge->hw;
 	int port = skge->port;
 	u32 chunk, ram_addr;
 	size_t rx_size, tx_size;
 	int err;
 	if (netif_msg_ifup(skge))
 		printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
 	if (dev->mtu > RX_BUF_SIZE)
 		skge->rx_buf_size = dev->mtu + ETH_HLEN + NET_IP_ALIGN;
 	else
 		skge->rx_buf_size = RX_BUF_SIZE;
 	rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
 	tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
 	skge->mem_size = tx_size + rx_size;
 	skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
 	if (!skge->mem)
 		return -ENOMEM;
 	BUG_ON(skge->dma & 7);
 	if ((u64)skge->dma >> 32 != ((u64) skge->dma + skge->mem_size) >> 32) {
 		printk(KERN_ERR PFX "pci_alloc_consistent region crosses 4G boundary\n");
 		err = -EINVAL;
 		goto free_pci_mem;
 	}
 	memset(skge->mem, 0, skge->mem_size);
-	if ((err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma)))
+	err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma);
+	if (err)
 		goto free_pci_mem;
 	err = skge_rx_fill(skge);
 	if (err)
 		goto free_rx_ring;
-	if ((err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
+	err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
-				   skge->dma + rx_size)))
+			      skge->dma + rx_size);
+	if (err)
 		goto free_rx_ring;
 	skge->tx_avail = skge->tx_ring.count - 1;
 	/* Initialize MAC */
 	spin_lock_bh(&hw->phy_lock);
 	if (hw->chip_id == CHIP_ID_GENESIS)
 		genesis_mac_init(hw, port);
 	else
 		yukon_mac_init(hw, port);
 	spin_unlock_bh(&hw->phy_lock);
 	/* Configure RAMbuffers */
 	chunk = hw->ram_size / ((hw->ports + 1)*2);
 	ram_addr = hw->ram_offset + 2 * chunk * port;
 	skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
 	skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
 	BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
 	skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
 	skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
 	/* Start receiver BMU */
 	wmb();
 	skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
 	skge_led(skge, LED_MODE_ON);
 	return 0;
  free_rx_ring:
 	skge_rx_clean(skge);
 	kfree(skge->rx_ring.start);
  free_pci_mem:
 	pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
 	skge->mem = NULL;
 	return err;
 }
 static int skge_down(struct net_device *dev)
 {
 	struct skge_port *skge = netdev_priv(dev);
 	struct skge_hw *hw = skge->hw;
 	int port = skge->port;
 	if (skge->mem == NULL)
 		return 0;
 	if (netif_msg_ifdown(skge))
 		printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
 	netif_stop_queue(dev);
 	skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
 	if (hw->chip_id == CHIP_ID_GENESIS)
 		genesis_stop(skge);
 	else
 		yukon_stop(skge);
 	/* Stop transmitter */
 	skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
 	skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
 		     RB_RST_SET|RB_DIS_OP_MD);
 	/* Disable Force Sync bit and Enable Alloc bit */
 	skge_write8(hw, SK_REG(port, TXA_CTRL),
 		    TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
 	/* Stop Interval Timer and Limit Counter of Tx Arbiter */
 	skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
 	skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
 	/* Reset PCI FIFO */
 	skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
 	skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
 	/* Reset the RAM Buffer async Tx queue */
 	skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
 	/* stop receiver */
 	skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
 	skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
 		     RB_RST_SET|RB_DIS_OP_MD);
 	skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
 	if (hw->chip_id == CHIP_ID_GENESIS) {
 		skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
 		skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
 	} else {
 		skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
 		skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
 	}
 	skge_led(skge, LED_MODE_OFF);
 	skge_tx_clean(skge);
 	skge_rx_clean(skge);
 	kfree(skge->rx_ring.start);
 	kfree(skge->tx_ring.start);
 	pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
 	skge->mem = NULL;
 	return 0;
 }
 static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
 {
 	struct skge_port *skge = netdev_priv(dev);
 	struct skge_hw *hw = skge->hw;
 	struct skge_ring *ring = &skge->tx_ring;
 	struct skge_element *e;
 	struct skge_tx_desc *td;
 	int i;
 	u32 control, len;
 	u64 map;
 	skb = skb_padto(skb, ETH_ZLEN);
 	if (!skb)
 		return NETDEV_TX_OK;
 	if (!spin_trylock(&skge->tx_lock)) {
- 		/* Collision - tell upper layer to requeue */
+		/* Collision - tell upper layer to requeue */
- 		return NETDEV_TX_LOCKED;
+		return NETDEV_TX_LOCKED;
- 	}
+	}
 	if (unlikely(skge->tx_avail < skb_shinfo(skb)->nr_frags +1)) {
 		if (!netif_queue_stopped(dev)) {
 			netif_stop_queue(dev);
 			printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
 			       dev->name);
 		}
 		spin_unlock(&skge->tx_lock);
 		return NETDEV_TX_BUSY;
 	}
 	e = ring->to_use;
 	td = e->desc;
 	e->skb = skb;
 	len = skb_headlen(skb);
 	map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
 	pci_unmap_addr_set(e, mapaddr, map);
 	pci_unmap_len_set(e, maplen, len);
 	td->dma_lo = map;
 	td->dma_hi = map >> 32;
 	if (skb->ip_summed == CHECKSUM_HW) {
 		int offset = skb->h.raw - skb->data;
 		/* This seems backwards, but it is what the sk98lin
 		 * does.  Looks like hardware is wrong?
 		 */
 		if (skb->h.ipiph->protocol == IPPROTO_UDP
 	            && hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
 			control = BMU_TCP_CHECK;
 		else
 			control = BMU_UDP_CHECK;
 		td->csum_offs = 0;
 		td->csum_start = offset;
 		td->csum_write = offset + skb->csum;
 	} else
 		control = BMU_CHECK;
 	if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
 		control |= BMU_EOF| BMU_IRQ_EOF;
 	else {
 		struct skge_tx_desc *tf = td;
 		control |= BMU_STFWD;
 		for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
 			skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
 			map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
 					   frag->size, PCI_DMA_TODEVICE);
 			e = e->next;
 			e->skb = NULL;
 			tf = e->desc;
 			tf->dma_lo = map;
 			tf->dma_hi = (u64) map >> 32;
 			pci_unmap_addr_set(e, mapaddr, map);
 			pci_unmap_len_set(e, maplen, frag->size);
 			tf->control = BMU_OWN | BMU_SW | control | frag->size;
 		}
 		tf->control |= BMU_EOF | BMU_IRQ_EOF;
 	}
 	/* Make sure all the descriptors written */
 	wmb();
 	td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
 	wmb();
 	skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
 	if (netif_msg_tx_queued(skge))
 		printk(KERN_DEBUG "%s: tx queued, slot %td, len %d\n",
 		       dev->name, e - ring->start, skb->len);
 	ring->to_use = e->next;
 	skge->tx_avail -= skb_shinfo(skb)->nr_frags + 1;
 	if (skge->tx_avail <= MAX_SKB_FRAGS + 1) {
 		pr_debug("%s: transmit queue full\n", dev->name);
 		netif_stop_queue(dev);
 	}
 	mmiowb();
 	spin_unlock(&skge->tx_lock);
 	dev->trans_start = jiffies;
 	return NETDEV_TX_OK;
 }
 static inline void skge_tx_free(struct skge_hw *hw, struct skge_element *e)
 {
 	/* This ring element can be skb or fragment */
 	if (e->skb) {
 		pci_unmap_single(hw->pdev,
 			       pci_unmap_addr(e, mapaddr),
 			       pci_unmap_len(e, maplen),
 			       PCI_DMA_TODEVICE);
 		dev_kfree_skb(e->skb);
 		e->skb = NULL;
 	} else {
 		pci_unmap_page(hw->pdev,
 			       pci_unmap_addr(e, mapaddr),
 			       pci_unmap_len(e, maplen),
 			       PCI_DMA_TODEVICE);
 	}
 }
 static void skge_tx_clean(struct skge_port *skge)
 {
 	struct skge_ring *ring = &skge->tx_ring;
 	struct skge_element *e;
 	spin_lock_bh(&skge->tx_lock);
 	for (e = ring->to_clean; e != ring->to_use; e = e->next) {
 		++skge->tx_avail;
 		skge_tx_free(skge->hw, e);
 	}
 	ring->to_clean = e;
 	spin_unlock_bh(&skge->tx_lock);
 }
 static void skge_tx_timeout(struct net_device *dev)
 {
 	struct skge_port *skge = netdev_priv(dev);
 	if (netif_msg_timer(skge))
 		printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name);
 	skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
 	skge_tx_clean(skge);
 }
 static int skge_change_mtu(struct net_device *dev, int new_mtu)
 {
 	int err;
 	if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
 		return -EINVAL;
 	if (!netif_running(dev)) {
 		dev->mtu = new_mtu;
 		return 0;
 	}
 	skge_down(dev);
 	dev->mtu = new_mtu;
 	err = skge_up(dev);
 	if (err)
 		dev_close(dev);
 	return err;
 }
 static void genesis_set_multicast(struct net_device *dev)
 {
 	struct skge_port *skge = netdev_priv(dev);
 	struct skge_hw *hw = skge->hw;
 	int port = skge->port;
 	int i, count = dev->mc_count;
 	struct dev_mc_list *list = dev->mc_list;
 	u32 mode;
 	u8 filter[8];
 	mode = xm_read32(hw, port, XM_MODE);
 	mode |= XM_MD_ENA_HASH;
 	if (dev->flags & IFF_PROMISC)
 		mode |= XM_MD_ENA_PROM;
 	else
 		mode &= ~XM_MD_ENA_PROM;
 	if (dev->flags & IFF_ALLMULTI)
 		memset(filter, 0xff, sizeof(filter));
 	else {
 		memset(filter, 0, sizeof(filter));
 		for (i = 0; list && i < count; i++, list = list->next) {
 			u32 crc, bit;
 			crc = ether_crc_le(ETH_ALEN, list->dmi_addr);
 			bit = ~crc & 0x3f;
 			filter[bit/8] |= 1 << (bit%8);
 		}
 	}
 	xm_write32(hw, port, XM_MODE, mode);
 	xm_outhash(hw, port, XM_HSM, filter);
 }
 static void yukon_set_multicast(struct net_device *dev)
 {
 	struct skge_port *skge = netdev_priv(dev);
 	struct skge_hw *hw = skge->hw;
 	int port = skge->port;
 	struct dev_mc_list *list = dev->mc_list;
 	u16 reg;
 	u8 filter[8];
 	memset(filter, 0, sizeof(filter));
 	reg = gma_read16(hw, port, GM_RX_CTRL);
 	reg |= GM_RXCR_UCF_ENA;
 	if (dev->flags & IFF_PROMISC) 		/* promiscuous */
 		reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
 	else if (dev->flags & IFF_ALLMULTI)	/* all multicast */
 		memset(filter, 0xff, sizeof(filter));
 	else if (dev->mc_count == 0)		/* no multicast */
 		reg &= ~GM_RXCR_MCF_ENA;
 	else {
 		int i;
 		reg |= GM_RXCR_MCF_ENA;
 		for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
 			u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
 			filter[bit/8] |= 1 << (bit%8);
 		}
 	}
 	gma_write16(hw, port, GM_MC_ADDR_H1,
 			 (u16)filter[0] | ((u16)filter[1] << 8));
 	gma_write16(hw, port, GM_MC_ADDR_H2,
 			 (u16)filter[2] | ((u16)filter[3] << 8));
 	gma_write16(hw, port, GM_MC_ADDR_H3,
 			 (u16)filter[4] | ((u16)filter[5] << 8));
 	gma_write16(hw, port, GM_MC_ADDR_H4,
 			 (u16)filter[6] | ((u16)filter[7] << 8));
 	gma_write16(hw, port, GM_RX_CTRL, reg);
 }
 static inline u16 phy_length(const struct skge_hw *hw, u32 status)
 {
 	if (hw->chip_id == CHIP_ID_GENESIS)
 		return status >> XMR_FS_LEN_SHIFT;
 	else
 		return status >> GMR_FS_LEN_SHIFT;
 }
 static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
 {
 	if (hw->chip_id == CHIP_ID_GENESIS)
 		return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
 	else
 		return (status & GMR_FS_ANY_ERR) ||
 			(status & GMR_FS_RX_OK) == 0;
 }
 /* Get receive buffer from descriptor.
  * Handles copy of small buffers and reallocation failures
  */
 static inline struct sk_buff *skge_rx_get(struct skge_port *skge,
 					  struct skge_element *e,
 					  u32 control, u32 status, u16 csum)
 {
 	struct sk_buff *skb;
 	u16 len = control & BMU_BBC;
 	if (unlikely(netif_msg_rx_status(skge)))
 		printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",
 		       skge->netdev->name, e - skge->rx_ring.start,
 		       status, len);
 	if (len > skge->rx_buf_size)
 		goto error;
 	if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
 		goto error;
 	if (bad_phy_status(skge->hw, status))
 		goto error;
 	if (phy_length(skge->hw, status) != len)
 		goto error;
 	if (len < RX_COPY_THRESHOLD) {
 		skb = dev_alloc_skb(len + 2);
 		if (!skb)
 			goto resubmit;
 		skb_reserve(skb, 2);
 		pci_dma_sync_single_for_cpu(skge->hw->pdev,
 					    pci_unmap_addr(e, mapaddr),
 					    len, PCI_DMA_FROMDEVICE);
 		memcpy(skb->data, e->skb->data, len);
 		pci_dma_sync_single_for_device(skge->hw->pdev,
 					       pci_unmap_addr(e, mapaddr),
 					       len, PCI_DMA_FROMDEVICE);
 		skge_rx_reuse(e, skge->rx_buf_size);
 	} else {
 		struct sk_buff *nskb;
 		nskb = dev_alloc_skb(skge->rx_buf_size + NET_IP_ALIGN);
 		if (!nskb)
 			goto resubmit;
 		pci_unmap_single(skge->hw->pdev,
 				 pci_unmap_addr(e, mapaddr),
 				 pci_unmap_len(e, maplen),
 				 PCI_DMA_FROMDEVICE);
 		skb = e->skb;
   		prefetch(skb->data);
 		skge_rx_setup(skge, e, nskb, skge->rx_buf_size);
 	}
 	skb_put(skb, len);
 	skb->dev = skge->netdev;
 	if (skge->rx_csum) {
 		skb->csum = csum;
 		skb->ip_summed = CHECKSUM_HW;
 	}
 	skb->protocol = eth_type_trans(skb, skge->netdev);
 	return skb;
 error:
 	if (netif_msg_rx_err(skge))
 		printk(KERN_DEBUG PFX "%s: rx err, slot %td control 0x%x status 0x%x\n",
 		       skge->netdev->name, e - skge->rx_ring.start,
 		       control, status);
 	if (skge->hw->chip_id == CHIP_ID_GENESIS) {
 		if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
 			skge->net_stats.rx_length_errors++;
 		if (status & XMR_FS_FRA_ERR)
 			skge->net_stats.rx_frame_errors++;
 		if (status & XMR_FS_FCS_ERR)
 			skge->net_stats.rx_crc_errors++;
 	} else {
 		if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
 			skge->net_stats.rx_length_errors++;
 		if (status & GMR_FS_FRAGMENT)
 			skge->net_stats.rx_frame_errors++;
 		if (status & GMR_FS_CRC_ERR)
 			skge->net_stats.rx_crc_errors++;
 	}
 resubmit:
 	skge_rx_reuse(e, skge->rx_buf_size);
 	return NULL;
 }
 static void skge_tx_done(struct skge_port *skge)
 {
 	struct skge_ring *ring = &skge->tx_ring;
 	struct skge_element *e;
 	spin_lock(&skge->tx_lock);
 	for (e = ring->to_clean; prefetch(e->next), e != ring->to_use; e = e->next) {
 		struct skge_tx_desc *td = e->desc;
 		u32 control;
 		rmb();
 		control = td->control;
 		if (control & BMU_OWN)
 			break;
 		if (unlikely(netif_msg_tx_done(skge)))
 			printk(KERN_DEBUG PFX "%s: tx done slot %td status 0x%x\n",
 			       skge->netdev->name, e - ring->start, td->status);
 		skge_tx_free(skge->hw, e);
 		e->skb = NULL;
 		++skge->tx_avail;
 	}
 	ring->to_clean = e;
 	skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
 	if (skge->tx_avail > MAX_SKB_FRAGS + 1)
 		netif_wake_queue(skge->netdev);
 	spin_unlock(&skge->tx_lock);
 }
 static int skge_poll(struct net_device *dev, int *budget)
 {
 	struct skge_port *skge = netdev_priv(dev);
 	struct skge_hw *hw = skge->hw;
 	struct skge_ring *ring = &skge->rx_ring;
 	struct skge_element *e;
 	int to_do = min(dev->quota, *budget);
 	int work_done = 0;
 	skge_tx_done(skge);
 	for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) {
 		struct skge_rx_desc *rd = e->desc;
 		struct sk_buff *skb;
 		u32 control;
 		rmb();
 		control = rd->control;
 		if (control & BMU_OWN)
 			break;
- 		skb = skge_rx_get(skge, e, control, rd->status,
+		skb = skge_rx_get(skge, e, control, rd->status,
- 				  le16_to_cpu(rd->csum2));
+				  le16_to_cpu(rd->csum2));
 		if (likely(skb)) {
 			dev->last_rx = jiffies;
 			netif_receive_skb(skb);
 			++work_done;
 		} else
 			skge_rx_reuse(e, skge->rx_buf_size);
 	}
 	ring->to_clean = e;
 	/* restart receiver */
 	wmb();
 	skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);
 	*budget -= work_done;
 	dev->quota -= work_done;
 	if (work_done >=  to_do)
 		return 1; /* not done */
 	netif_rx_complete(dev);
 	mmiowb();
   	hw->intr_mask |= skge->port == 0 ? (IS_R1_F|IS_XA1_F) : (IS_R2_F|IS_XA2_F);
   	skge_write32(hw, B0_IMSK, hw->intr_mask);
 	return 0;
 }
 /* Parity errors seem to happen when Genesis is connected to a switch
  * with no other ports present. Heartbeat error??
  */
 static void skge_mac_parity(struct skge_hw *hw, int port)
 {
 	struct net_device *dev = hw->dev[port];
 	if (dev) {
 		struct skge_port *skge = netdev_priv(dev);
 		++skge->net_stats.tx_heartbeat_errors;
 	}
 	if (hw->chip_id == CHIP_ID_GENESIS)
 		skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
 			     MFF_CLR_PERR);
 	else
 		/* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
 		skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
 			    (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
 			    ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
 }
 static void skge_pci_clear(struct skge_hw *hw)
 {
 	u16 status;
 	pci_read_config_word(hw->pdev, PCI_STATUS, &status);
 	skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
 	pci_write_config_word(hw->pdev, PCI_STATUS,
 			      status | PCI_STATUS_ERROR_BITS);
 	skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
 }
 static void skge_mac_intr(struct skge_hw *hw, int port)
 {
 	if (hw->chip_id == CHIP_ID_GENESIS)
 		genesis_mac_intr(hw, port);
 	else
 		yukon_mac_intr(hw, port);
 }
 /* Handle device specific framing and timeout interrupts */
 static void skge_error_irq(struct skge_hw *hw)
 {
 	u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
 	if (hw->chip_id == CHIP_ID_GENESIS) {
 		/* clear xmac errors */
 		if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
 			skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
 		if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
 			skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
 	} else {
 		/* Timestamp (unused) overflow */
 		if (hwstatus & IS_IRQ_TIST_OV)
 			skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
 	}
 	if (hwstatus & IS_RAM_RD_PAR) {
 		printk(KERN_ERR PFX "Ram read data parity error\n");
 		skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
 	}
 	if (hwstatus & IS_RAM_WR_PAR) {
 		printk(KERN_ERR PFX "Ram write data parity error\n");
 		skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
 	}
 	if (hwstatus & IS_M1_PAR_ERR)
 		skge_mac_parity(hw, 0);
 	if (hwstatus & IS_M2_PAR_ERR)
 		skge_mac_parity(hw, 1);
 	if (hwstatus & IS_R1_PAR_ERR)
 		skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
 	if (hwstatus & IS_R2_PAR_ERR)
 		skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
 	if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
 		printk(KERN_ERR PFX "hardware error detected (status 0x%x)\n",
 		       hwstatus);
 		skge_pci_clear(hw);
 		/* if error still set then just ignore it */
 		hwstatus = skge_read32(hw, B0_HWE_ISRC);
 		if (hwstatus & IS_IRQ_STAT) {
 			pr_debug("IRQ status %x: still set ignoring hardware errors\n",
 			       hwstatus);
 			hw->intr_mask &= ~IS_HW_ERR;
 		}
 	}
 }
 /*
  * Interrupt from PHY are handled in tasklet (soft irq)
  * because accessing phy registers requires spin wait which might
  * cause excess interrupt latency.
  */
 static void skge_extirq(unsigned long data)
 {
 	struct skge_hw *hw = (struct skge_hw *) data;
 	int port;
 	spin_lock(&hw->phy_lock);
 	for (port = 0; port < hw->ports; port++) {
 		struct net_device *dev = hw->dev[port];
 		struct skge_port *skge = netdev_priv(dev);
 		if (netif_running(dev)) {
 			if (hw->chip_id != CHIP_ID_GENESIS)
 				yukon_phy_intr(skge);
 			else
 				bcom_phy_intr(skge);
 		}
 	}
 	spin_unlock(&hw->phy_lock);
 	hw->intr_mask |= IS_EXT_REG;
 	skge_write32(hw, B0_IMSK, hw->intr_mask);
 }
 static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)
 {
 	struct skge_hw *hw = dev_id;
 	u32 status;
 	/* Reading this register masks IRQ */
 	status = skge_read32(hw, B0_SP_ISRC);
 	if (status == 0)
 		return IRQ_NONE;
 	if (status & IS_EXT_REG) {
 		hw->intr_mask &= ~IS_EXT_REG;
 		tasklet_schedule(&hw->ext_tasklet);
 	}
 	if (status & (IS_R1_F|IS_XA1_F)) {
 		skge_write8(hw, Q_ADDR(Q_R1, Q_CSR), CSR_IRQ_CL_F);
 		hw->intr_mask &= ~(IS_R1_F|IS_XA1_F);
 		netif_rx_schedule(hw->dev[0]);
 	}
 	if (status & (IS_R2_F|IS_XA2_F)) {
 		skge_write8(hw, Q_ADDR(Q_R2, Q_CSR), CSR_IRQ_CL_F);
 		hw->intr_mask &= ~(IS_R2_F|IS_XA2_F);
 		netif_rx_schedule(hw->dev[1]);
 	}
 	if (likely((status & hw->intr_mask) == 0))
 		return IRQ_HANDLED;
 	if (status & IS_PA_TO_RX1) {
 		struct skge_port *skge = netdev_priv(hw->dev[0]);
 		++skge->net_stats.rx_over_errors;
 		skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
 	}
 	if (status & IS_PA_TO_RX2) {
 		struct skge_port *skge = netdev_priv(hw->dev[1]);
 		++skge->net_stats.rx_over_errors;
 		skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
 	}
 	if (status & IS_PA_TO_TX1)
 		skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
 	if (status & IS_PA_TO_TX2)
 		skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
 	if (status & IS_MAC1)
 		skge_mac_intr(hw, 0);
 	if (status & IS_MAC2)
 		skge_mac_intr(hw, 1);
 	if (status & IS_HW_ERR)
 		skge_error_irq(hw);
 	skge_write32(hw, B0_IMSK, hw->intr_mask);
 	return IRQ_HANDLED;
 }
 #ifdef CONFIG_NET_POLL_CONTROLLER
 static void skge_netpoll(struct net_device *dev)
 {
 	struct skge_port *skge = netdev_priv(dev);
 	disable_irq(dev->irq);
 	skge_intr(dev->irq, skge->hw, NULL);
 	enable_irq(dev->irq);
 }
 #endif
 static int skge_set_mac_address(struct net_device *dev, void *p)
 {
 	struct skge_port *skge = netdev_priv(dev);
 	struct skge_hw *hw = skge->hw;
 	unsigned port = skge->port;
 	const struct sockaddr *addr = p;
 	if (!is_valid_ether_addr(addr->sa_data))
 		return -EADDRNOTAVAIL;
 	spin_lock_bh(&hw->phy_lock);
 	memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
 	memcpy_toio(hw->regs + B2_MAC_1 + port*8,
 		    dev->dev_addr, ETH_ALEN);
 	memcpy_toio(hw->regs + B2_MAC_2 + port*8,
 		    dev->dev_addr, ETH_ALEN);
 	if (hw->chip_id == CHIP_ID_GENESIS)
 		xm_outaddr(hw, port, XM_SA, dev->dev_addr);
 	else {
 		gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
 		gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
 	}
 	spin_unlock_bh(&hw->phy_lock);
 	return 0;
 }
 static const struct {
 	u8 id;
 	const char *name;
 } skge_chips[] = {
 	{ CHIP_ID_GENESIS,	"Genesis" },
 	{ CHIP_ID_YUKON,	 "Yukon" },
 	{ CHIP_ID_YUKON_LITE,	 "Yukon-Lite"},
 	{ CHIP_ID_YUKON_LP,	 "Yukon-LP"},
 };
 static const char *skge_board_name(const struct skge_hw *hw)
 {
 	int i;
 	static char buf[16];
 	for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
 		if (skge_chips[i].id == hw->chip_id)
 			return skge_chips[i].name;
 	snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
 	return buf;
 }
 /*
  * Setup the board data structure, but don't bring up
  * the port(s)
  */
 static int skge_reset(struct skge_hw *hw)
 {
 	u32 reg;
 	u16 ctst;
 	u8 t8, mac_cfg, pmd_type, phy_type;
 	int i;
 	ctst = skge_read16(hw, B0_CTST);
 	/* do a SW reset */
 	skge_write8(hw, B0_CTST, CS_RST_SET);
 	skge_write8(hw, B0_CTST, CS_RST_CLR);
 	/* clear PCI errors, if any */
 	skge_pci_clear(hw);
 	skge_write8(hw, B0_CTST, CS_MRST_CLR);
 	/* restore CLK_RUN bits (for Yukon-Lite) */
 	skge_write16(hw, B0_CTST,
 		     ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
 	hw->chip_id = skge_read8(hw, B2_CHIP_ID);
 	phy_type = skge_read8(hw, B2_E_1) & 0xf;
 	pmd_type = skge_read8(hw, B2_PMD_TYP);
 	hw->copper = (pmd_type == 'T' || pmd_type == '1');
 	switch (hw->chip_id) {
 	case CHIP_ID_GENESIS:
 		switch (phy_type) {
 		case SK_PHY_BCOM:
 			hw->phy_addr = PHY_ADDR_BCOM;
 			break;
 		default:
 			printk(KERN_ERR PFX "%s: unsupported phy type 0x%x\n",
 			       pci_name(hw->pdev), phy_type);
 			return -EOPNOTSUPP;
 		}
 		break;
 	case CHIP_ID_YUKON:
 	case CHIP_ID_YUKON_LITE:
 	case CHIP_ID_YUKON_LP:
 		if (phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
 			hw->copper = 1;
 		hw->phy_addr = PHY_ADDR_MARV;
 		break;
 	default:
 		printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
 		       pci_name(hw->pdev), hw->chip_id);
 		return -EOPNOTSUPP;
 	}
 	mac_cfg = skge_read8(hw, B2_MAC_CFG);
 	hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
 	hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
 	/* read the adapters RAM size */
 	t8 = skge_read8(hw, B2_E_0);
 	if (hw->chip_id == CHIP_ID_GENESIS) {
 		if (t8 == 3) {
 			/* special case: 4 x 64k x 36, offset = 0x80000 */
 			hw->ram_size = 0x100000;
 			hw->ram_offset = 0x80000;
 		} else
 			hw->ram_size = t8 * 512;
 	}
 	else if (t8 == 0)
 		hw->ram_size = 0x20000;
 	else
 		hw->ram_size = t8 * 4096;
 	hw->intr_mask = IS_HW_ERR | IS_EXT_REG | IS_PORT_1;
 	if (hw->ports > 1)
 		hw->intr_mask |= IS_PORT_2;
 	if (hw->chip_id == CHIP_ID_GENESIS)
 		genesis_init(hw);
 	else {
 		/* switch power to VCC (WA for VAUX problem) */
 		skge_write8(hw, B0_POWER_CTRL,
 			    PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
 		/* avoid boards with stuck Hardware error bits */
 		if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
 		    (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
 			printk(KERN_WARNING PFX "stuck hardware sensor bit\n");
 			hw->intr_mask &= ~IS_HW_ERR;
 		}
 		/* Clear PHY COMA */
 		skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
 		pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg);
 		reg &= ~PCI_PHY_COMA;
 		pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
 		skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
 		for (i = 0; i < hw->ports; i++) {
 			skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
 			skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
 		}
 	}
 	/* turn off hardware timer (unused) */
 	skge_write8(hw, B2_TI_CTRL, TIM_STOP);
 	skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
 	skge_write8(hw, B0_LED, LED_STAT_ON);
 	/* enable the Tx Arbiters */
 	for (i = 0; i < hw->ports; i++)
 		skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
 	/* Initialize ram interface */
 	skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
 	skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
 	skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
 	skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
 	skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
 	skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
 	skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
 	skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
 	skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
 	skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
 	skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
 	skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
 	skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
 	skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
 	/* Set interrupt moderation for Transmit only
 	 * Receive interrupts avoided by NAPI
 	 */
 	skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
 	skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
 	skge_write32(hw, B2_IRQM_CTRL, TIM_START);
 	skge_write32(hw, B0_IMSK, hw->intr_mask);
 	spin_lock_bh(&hw->phy_lock);
 	for (i = 0; i < hw->ports; i++) {
 		if (hw->chip_id == CHIP_ID_GENESIS)
 			genesis_reset(hw, i);
 		else
 			yukon_reset(hw, i);
 	}
 	spin_unlock_bh(&hw->phy_lock);
 	return 0;
 }
 /* Initialize network device */
 static struct net_device *skge_devinit(struct skge_hw *hw, int port,
 				       int highmem)
 {
 	struct skge_port *skge;
 	struct net_device *dev = alloc_etherdev(sizeof(*skge));
 	if (!dev) {
 		printk(KERN_ERR "skge etherdev alloc failed");
 		return NULL;
 	}
 	SET_MODULE_OWNER(dev);
 	SET_NETDEV_DEV(dev, &hw->pdev->dev);
 	dev->open = skge_up;
 	dev->stop = skge_down;
 	dev->do_ioctl = skge_ioctl;
 	dev->hard_start_xmit = skge_xmit_frame;
 	dev->get_stats = skge_get_stats;
 	if (hw->chip_id == CHIP_ID_GENESIS)
 		dev->set_multicast_list = genesis_set_multicast;
 	else
 		dev->set_multicast_list = yukon_set_multicast;
 	dev->set_mac_address = skge_set_mac_address;
 	dev->change_mtu = skge_change_mtu;
 	SET_ETHTOOL_OPS(dev, &skge_ethtool_ops);
 	dev->tx_timeout = skge_tx_timeout;
 	dev->watchdog_timeo = TX_WATCHDOG;
 	dev->poll = skge_poll;
 	dev->weight = NAPI_WEIGHT;
 #ifdef CONFIG_NET_POLL_CONTROLLER
 	dev->poll_controller = skge_netpoll;
 #endif
 	dev->irq = hw->pdev->irq;
 	dev->features = NETIF_F_LLTX;
 	if (highmem)
 		dev->features |= NETIF_F_HIGHDMA;
 	skge = netdev_priv(dev);
 	skge->netdev = dev;
 	skge->hw = hw;
 	skge->msg_enable = netif_msg_init(debug, default_msg);
 	skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
 	skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
 	/* Auto speed and flow control */
 	skge->autoneg = AUTONEG_ENABLE;
 	skge->flow_control = FLOW_MODE_SYMMETRIC;
 	skge->duplex = -1;
 	skge->speed = -1;
 	skge->advertising = skge_supported_modes(hw);
 	hw->dev[port] = dev;
 	skge->port = port;
 	spin_lock_init(&skge->tx_lock);
 	if (hw->chip_id != CHIP_ID_GENESIS) {
 		dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
 		skge->rx_csum = 1;
 	}
 	/* read the mac address */
 	memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
 	memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
 	/* device is off until link detection */
 	netif_carrier_off(dev);
 	netif_stop_queue(dev);
 	return dev;
 }
 static void __devinit skge_show_addr(struct net_device *dev)
 {
 	const struct skge_port *skge = netdev_priv(dev);
 	if (netif_msg_probe(skge))
 		printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
 		       dev->name,
 		       dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
 		       dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
 }
 static int __devinit skge_probe(struct pci_dev *pdev,
 				const struct pci_device_id *ent)
 {
 	struct net_device *dev, *dev1;
 	struct skge_hw *hw;
 	int err, using_dac = 0;
-	if ((err = pci_enable_device(pdev))) {
+	err = pci_enable_device(pdev);
+	if (err) {
 		printk(KERN_ERR PFX "%s cannot enable PCI device\n",
 		       pci_name(pdev));
 		goto err_out;
 	}
-	if ((err = pci_request_regions(pdev, DRV_NAME))) {
+	err = pci_request_regions(pdev, DRV_NAME);
+	if (err) {
 		printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
 		       pci_name(pdev));
 		goto err_out_disable_pdev;
 	}
 	pci_set_master(pdev);
 	if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
 		using_dac = 1;
 		err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
 	} else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
 		using_dac = 0;
 		err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
 	}
 	if (err) {
 		printk(KERN_ERR PFX "%s no usable DMA configuration\n",
 		       pci_name(pdev));
 		goto err_out_free_regions;
 	}
 #ifdef __BIG_ENDIAN
 	/* byte swap descriptors in hardware */
 	{
 		u32 reg;
 		pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
 		reg |= PCI_REV_DESC;
 		pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
 	}
 #endif
 	err = -ENOMEM;
 	hw = kzalloc(sizeof(*hw), GFP_KERNEL);
 	if (!hw) {
 		printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
 		       pci_name(pdev));
 		goto err_out_free_regions;
 	}
 	hw->pdev = pdev;
 	spin_lock_init(&hw->phy_lock);
 	tasklet_init(&hw->ext_tasklet, skge_extirq, (unsigned long) hw);
 	hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
 	if (!hw->regs) {
 		printk(KERN_ERR PFX "%s: cannot map device registers\n",
 		       pci_name(pdev));
 		goto err_out_free_hw;
 	}
-	if ((err = request_irq(pdev->irq, skge_intr, SA_SHIRQ, DRV_NAME, hw))) {
+	err = request_irq(pdev->irq, skge_intr, SA_SHIRQ, DRV_NAME, hw);
+	if (err) {
 		printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
 		       pci_name(pdev), pdev->irq);
 		goto err_out_iounmap;
 	}
 	pci_set_drvdata(pdev, hw);
 	err = skge_reset(hw);
 	if (err)
 		goto err_out_free_irq;
 	printk(KERN_INFO PFX DRV_VERSION " addr 0x%lx irq %d chip %s rev %d\n",
 	       pci_resource_start(pdev, 0), pdev->irq,
 	       skge_board_name(hw), hw->chip_rev);
 	if ((dev = skge_devinit(hw, 0, using_dac)) == NULL)
 		goto err_out_led_off;
-	if ((err = register_netdev(dev))) {
+	err = register_netdev(dev);
+	if (err) {
 		printk(KERN_ERR PFX "%s: cannot register net device\n",
 		       pci_name(pdev));
 		goto err_out_free_netdev;
 	}
 	skge_show_addr(dev);
 	if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {
 		if (register_netdev(dev1) == 0)
 			skge_show_addr(dev1);
 		else {
 			/* Failure to register second port need not be fatal */
 			printk(KERN_WARNING PFX "register of second port failed\n");
 			hw->dev[1] = NULL;
 			free_netdev(dev1);
 		}
 	}
 	return 0;
 err_out_free_netdev:
 	free_netdev(dev);
 err_out_led_off:
 	skge_write16(hw, B0_LED, LED_STAT_OFF);
 err_out_free_irq:
 	free_irq(pdev->irq, hw);
 err_out_iounmap:
 	iounmap(hw->regs);
 err_out_free_hw:
 	kfree(hw);
 err_out_free_regions:
 	pci_release_regions(pdev);
 err_out_disable_pdev:
 	pci_disable_device(pdev);
 	pci_set_drvdata(pdev, NULL);
 err_out:
 	return err;
 }
 static void __devexit skge_remove(struct pci_dev *pdev)
 {
 	struct skge_hw *hw  = pci_get_drvdata(pdev);
 	struct net_device *dev0, *dev1;
 	if (!hw)
 		return;
 	if ((dev1 = hw->dev[1]))
 		unregister_netdev(dev1);
 	dev0 = hw->dev[0];
 	unregister_netdev(dev0);
 	skge_write32(hw, B0_IMSK, 0);
 	skge_write16(hw, B0_LED, LED_STAT_OFF);
 	skge_pci_clear(hw);
 	skge_write8(hw, B0_CTST, CS_RST_SET);
 	tasklet_kill(&hw->ext_tasklet);
 	free_irq(pdev->irq, hw);
 	pci_release_regions(pdev);
 	pci_disable_device(pdev);
 	if (dev1)
 		free_netdev(dev1);
 	free_netdev(dev0);
 	iounmap(hw->regs);
 	kfree(hw);
 	pci_set_drvdata(pdev, NULL);
 }
 #ifdef CONFIG_PM
 static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
 {
 	struct skge_hw *hw  = pci_get_drvdata(pdev);
 	int i, wol = 0;
 	for (i = 0; i < 2; i++) {
 		struct net_device *dev = hw->dev[i];
 		if (dev) {
 			struct skge_port *skge = netdev_priv(dev);
 			if (netif_running(dev)) {
 				netif_carrier_off(dev);
 				if (skge->wol)
 					netif_stop_queue(dev);
 				else
 					skge_down(dev);
 			}
 			netif_device_detach(dev);
 			wol |= skge->wol;
 		}
 	}
 	pci_save_state(pdev);
 	pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
 	pci_disable_device(pdev);
 	pci_set_power_state(pdev, pci_choose_state(pdev, state));
 	return 0;
 }
 static int skge_resume(struct pci_dev *pdev)
 {
 	struct skge_hw *hw  = pci_get_drvdata(pdev);
 	int i;
 	pci_set_power_state(pdev, PCI_D0);
 	pci_restore_state(pdev);
 	pci_enable_wake(pdev, PCI_D0, 0);
 	skge_reset(hw);
 	for (i = 0; i < 2; i++) {
 		struct net_device *dev = hw->dev[i];
 		if (dev) {
 			netif_device_attach(dev);
 			if (netif_running(dev) && skge_up(dev))
 				dev_close(dev);
 		}
 	}
 	return 0;
 }
 #endif
 static struct pci_driver skge_driver = {
 	.name =         DRV_NAME,
 	.id_table =     skge_id_table,
 	.probe =        skge_probe,
 	.remove =       __devexit_p(skge_remove),
 #ifdef CONFIG_PM
 	.suspend = 	skge_suspend,
 	.resume = 	skge_resume,
 #endif
 };
 static int __init skge_init_module(void)
 {
 	return pci_module_init(&skge_driver);
 }
 static void __exit skge_cleanup_module(void)
 {
 	pci_unregister_driver(&skge_driver);
 }
 module_init(skge_init_module);
 module_exit(skge_cleanup_module);