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Commit 26799e675e47c5aa3104628e2081a7299ea46557

Authored by Lennert Buytenhek
Committed by Russell King
1 parent baaf7ed179
Exists in master and in 4 other branches v3.2_AM335xPSP_04.06.00.11, v3.2_NEWT335xPSP_04.06.00.11, v3.2_SBC_SMARTMEN, v3.2_SMARCT335xPSP_04.06.00.11

[PATCH] ARM: 2757/1: remove ixdp2400_init_irq from ixdp2800 code 

Patch from Lennert Buytenhek

Compiling one kernel that supports both ixdp2400 and ixdp2800 gives
an error, as a copy of the ixdp2400 irq init routing accidentally
ended up in ixdp2800.c somehow.

Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Deepak Saxena
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

Showing 1 changed file with 0 additions and 6 deletions Inline Diff

arch/arm/mach-ixp2000/ixdp2800.c
Diff comments   View file @ 26799e6
1 /* 1 /*
2 * arch/arm/mach-ixp2000/ixdp2800.c 2 * arch/arm/mach-ixp2000/ixdp2800.c
3 * 3 *
4 * IXDP2800 platform support 4 * IXDP2800 platform support
5 * 5 *
6 * Original Author: Jeffrey Daly <jeffrey.daly@intel.com> 6 * Original Author: Jeffrey Daly <jeffrey.daly@intel.com>
7 * Maintainer: Deepak Saxena <dsaxena@plexity.net> 7 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
8 * 8 *
9 * Copyright (C) 2002 Intel Corp. 9 * Copyright (C) 2002 Intel Corp.
10 * Copyright (C) 2003-2004 MontaVista Software, Inc. 10 * Copyright (C) 2003-2004 MontaVista Software, Inc.
11 * 11 *
12 * This program is free software; you can redistribute it and/or modify it 12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the 13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your 14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version. 15 * option) any later version.
16 */ 16 */
17 #include <linux/config.h> 17 #include <linux/config.h>
18 #include <linux/kernel.h> 18 #include <linux/kernel.h>
19 #include <linux/init.h> 19 #include <linux/init.h>
20 #include <linux/mm.h> 20 #include <linux/mm.h>
21 #include <linux/sched.h> 21 #include <linux/sched.h>
22 #include <linux/interrupt.h> 22 #include <linux/interrupt.h>
23 #include <linux/device.h> 23 #include <linux/device.h>
24 #include <linux/bitops.h> 24 #include <linux/bitops.h>
25 #include <linux/pci.h> 25 #include <linux/pci.h>
26 #include <linux/ioport.h> 26 #include <linux/ioport.h>
27 #include <linux/slab.h> 27 #include <linux/slab.h>
28 #include <linux/delay.h> 28 #include <linux/delay.h>
29 29
30 #include <asm/io.h> 30 #include <asm/io.h>
31 #include <asm/irq.h> 31 #include <asm/irq.h>
32 #include <asm/pgtable.h> 32 #include <asm/pgtable.h>
33 #include <asm/page.h> 33 #include <asm/page.h>
34 #include <asm/system.h> 34 #include <asm/system.h>
35 #include <asm/hardware.h> 35 #include <asm/hardware.h>
36 #include <asm/mach-types.h> 36 #include <asm/mach-types.h>
37 37
38 #include <asm/mach/pci.h> 38 #include <asm/mach/pci.h>
39 #include <asm/mach/map.h> 39 #include <asm/mach/map.h>
40 #include <asm/mach/irq.h> 40 #include <asm/mach/irq.h>
41 #include <asm/mach/time.h> 41 #include <asm/mach/time.h>
42 #include <asm/mach/flash.h> 42 #include <asm/mach/flash.h>
43 #include <asm/mach/arch.h> 43 #include <asm/mach/arch.h>
44 44
45
46 void ixdp2400_init_irq(void)
47 {
48 ixdp2x00_init_irq(IXDP2800_CPLD_INT_STAT, IXDP2800_CPLD_INT_MASK, IXDP2400_NR_IRQS);
49 }
50
51 /************************************************************************* 45 /*************************************************************************
52 * IXDP2800 timer tick 46 * IXDP2800 timer tick
53 *************************************************************************/ 47 *************************************************************************/
54 48
55 static void __init ixdp2800_timer_init(void) 49 static void __init ixdp2800_timer_init(void)
56 { 50 {
57 ixp2000_init_time(50000000); 51 ixp2000_init_time(50000000);
58 } 52 }
59 53
60 static struct sys_timer ixdp2800_timer = { 54 static struct sys_timer ixdp2800_timer = {
61 .init = ixdp2800_timer_init, 55 .init = ixdp2800_timer_init,
62 .offset = ixp2000_gettimeoffset, 56 .offset = ixp2000_gettimeoffset,
63 }; 57 };
64 58
65 /************************************************************************* 59 /*************************************************************************
66 * IXDP2800 PCI 60 * IXDP2800 PCI
67 *************************************************************************/ 61 *************************************************************************/
68 static void __init ixdp2800_slave_disable_pci_master(void) 62 static void __init ixdp2800_slave_disable_pci_master(void)
69 { 63 {
70 *IXP2000_PCI_CMDSTAT &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); 64 *IXP2000_PCI_CMDSTAT &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
71 } 65 }
72 66
73 static void __init ixdp2800_master_wait_for_slave(void) 67 static void __init ixdp2800_master_wait_for_slave(void)
74 { 68 {
75 volatile u32 *addr; 69 volatile u32 *addr;
76 70
77 printk(KERN_INFO "IXDP2800: waiting for slave NPU to configure " 71 printk(KERN_INFO "IXDP2800: waiting for slave NPU to configure "
78 "its BAR sizes\n"); 72 "its BAR sizes\n");
79 73
80 addr = ixp2000_pci_config_addr(0, IXDP2X00_SLAVE_NPU_DEVFN, 74 addr = ixp2000_pci_config_addr(0, IXDP2X00_SLAVE_NPU_DEVFN,
81 PCI_BASE_ADDRESS_1); 75 PCI_BASE_ADDRESS_1);
82 do { 76 do {
83 *addr = 0xffffffff; 77 *addr = 0xffffffff;
84 cpu_relax(); 78 cpu_relax();
85 } while (*addr != 0xfe000008); 79 } while (*addr != 0xfe000008);
86 80
87 addr = ixp2000_pci_config_addr(0, IXDP2X00_SLAVE_NPU_DEVFN, 81 addr = ixp2000_pci_config_addr(0, IXDP2X00_SLAVE_NPU_DEVFN,
88 PCI_BASE_ADDRESS_2); 82 PCI_BASE_ADDRESS_2);
89 do { 83 do {
90 *addr = 0xffffffff; 84 *addr = 0xffffffff;
91 cpu_relax(); 85 cpu_relax();
92 } while (*addr != 0xc0000008); 86 } while (*addr != 0xc0000008);
93 87
94 /* 88 /*
95 * Configure the slave's SDRAM BAR by hand. 89 * Configure the slave's SDRAM BAR by hand.
96 */ 90 */
97 *addr = 0x40000008; 91 *addr = 0x40000008;
98 } 92 }
99 93
100 static void __init ixdp2800_slave_wait_for_master_enable(void) 94 static void __init ixdp2800_slave_wait_for_master_enable(void)
101 { 95 {
102 printk(KERN_INFO "IXDP2800: waiting for master NPU to enable us\n"); 96 printk(KERN_INFO "IXDP2800: waiting for master NPU to enable us\n");
103 97
104 while ((*IXP2000_PCI_CMDSTAT & PCI_COMMAND_MASTER) == 0) 98 while ((*IXP2000_PCI_CMDSTAT & PCI_COMMAND_MASTER) == 0)
105 cpu_relax(); 99 cpu_relax();
106 } 100 }
107 101
108 void __init ixdp2800_pci_preinit(void) 102 void __init ixdp2800_pci_preinit(void)
109 { 103 {
110 printk("ixdp2x00_pci_preinit called\n"); 104 printk("ixdp2x00_pci_preinit called\n");
111 105
112 *IXP2000_PCI_ADDR_EXT = 0x0001e000; 106 *IXP2000_PCI_ADDR_EXT = 0x0001e000;
113 107
114 if (!ixdp2x00_master_npu()) 108 if (!ixdp2x00_master_npu())
115 ixdp2800_slave_disable_pci_master(); 109 ixdp2800_slave_disable_pci_master();
116 110
117 *IXP2000_PCI_SRAM_BASE_ADDR_MASK = (0x2000000 - 1) & ~0x3ffff; 111 *IXP2000_PCI_SRAM_BASE_ADDR_MASK = (0x2000000 - 1) & ~0x3ffff;
118 *IXP2000_PCI_DRAM_BASE_ADDR_MASK = (0x40000000 - 1) & ~0xfffff; 112 *IXP2000_PCI_DRAM_BASE_ADDR_MASK = (0x40000000 - 1) & ~0xfffff;
119 113
120 ixp2000_pci_preinit(); 114 ixp2000_pci_preinit();
121 115
122 if (ixdp2x00_master_npu()) { 116 if (ixdp2x00_master_npu()) {
123 /* 117 /*
124 * Wait until the slave set its SRAM/SDRAM BAR sizes 118 * Wait until the slave set its SRAM/SDRAM BAR sizes
125 * correctly before we proceed to scan and enumerate 119 * correctly before we proceed to scan and enumerate
126 * the bus. 120 * the bus.
127 */ 121 */
128 ixdp2800_master_wait_for_slave(); 122 ixdp2800_master_wait_for_slave();
129 123
130 /* 124 /*
131 * We configure the SDRAM BARs by hand because they 125 * We configure the SDRAM BARs by hand because they
132 * are 1G and fall outside of the regular allocated 126 * are 1G and fall outside of the regular allocated
133 * PCI address space. 127 * PCI address space.
134 */ 128 */
135 *IXP2000_PCI_SDRAM_BAR = 0x00000008; 129 *IXP2000_PCI_SDRAM_BAR = 0x00000008;
136 } else { 130 } else {
137 /* 131 /*
138 * Wait for the master to complete scanning the bus 132 * Wait for the master to complete scanning the bus
139 * and assigning resources before we proceed to scan 133 * and assigning resources before we proceed to scan
140 * the bus ourselves. Set pci=firmware to honor the 134 * the bus ourselves. Set pci=firmware to honor the
141 * master's resource assignment. 135 * master's resource assignment.
142 */ 136 */
143 ixdp2800_slave_wait_for_master_enable(); 137 ixdp2800_slave_wait_for_master_enable();
144 pcibios_setup("firmware"); 138 pcibios_setup("firmware");
145 } 139 }
146 } 140 }
147 141
148 /* 142 /*
149 * We assign the SDRAM BARs for the two IXP2800 CPUs by hand, outside 143 * We assign the SDRAM BARs for the two IXP2800 CPUs by hand, outside
150 * of the regular PCI window, because there's only 512M of outbound PCI 144 * of the regular PCI window, because there's only 512M of outbound PCI
151 * memory window on each IXP, while we need 1G for each of the BARs. 145 * memory window on each IXP, while we need 1G for each of the BARs.
152 */ 146 */
153 static void __devinit ixp2800_pci_fixup(struct pci_dev *dev) 147 static void __devinit ixp2800_pci_fixup(struct pci_dev *dev)
154 { 148 {
155 if (machine_is_ixdp2800()) { 149 if (machine_is_ixdp2800()) {
156 dev->resource[2].start = 0; 150 dev->resource[2].start = 0;
157 dev->resource[2].end = 0; 151 dev->resource[2].end = 0;
158 dev->resource[2].flags = 0; 152 dev->resource[2].flags = 0;
159 } 153 }
160 } 154 }
161 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IXP2800, ixp2800_pci_fixup); 155 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IXP2800, ixp2800_pci_fixup);
162 156
163 static int __init ixdp2800_pci_setup(int nr, struct pci_sys_data *sys) 157 static int __init ixdp2800_pci_setup(int nr, struct pci_sys_data *sys)
164 { 158 {
165 sys->mem_offset = 0x00000000; 159 sys->mem_offset = 0x00000000;
166 160
167 ixp2000_pci_setup(nr, sys); 161 ixp2000_pci_setup(nr, sys);
168 162
169 return 1; 163 return 1;
170 } 164 }
171 165
172 static int __init ixdp2800_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 166 static int __init ixdp2800_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
173 { 167 {
174 if (ixdp2x00_master_npu()) { 168 if (ixdp2x00_master_npu()) {
175 169
176 /* 170 /*
177 * Root bus devices. Slave NPU is only one with interrupt. 171 * Root bus devices. Slave NPU is only one with interrupt.
178 * Everything else, we just return -1 which is invalid. 172 * Everything else, we just return -1 which is invalid.
179 */ 173 */
180 if(!dev->bus->self) { 174 if(!dev->bus->self) {
181 if(dev->devfn == IXDP2X00_SLAVE_NPU_DEVFN ) 175 if(dev->devfn == IXDP2X00_SLAVE_NPU_DEVFN )
182 return IRQ_IXDP2800_INGRESS_NPU; 176 return IRQ_IXDP2800_INGRESS_NPU;
183 177
184 return -1; 178 return -1;
185 } 179 }
186 180
187 /* 181 /*
188 * Bridge behind the PMC slot. 182 * Bridge behind the PMC slot.
189 */ 183 */
190 if(dev->bus->self->devfn == IXDP2X00_PMC_DEVFN && 184 if(dev->bus->self->devfn == IXDP2X00_PMC_DEVFN &&
191 dev->bus->parent->self->devfn == IXDP2X00_P2P_DEVFN && 185 dev->bus->parent->self->devfn == IXDP2X00_P2P_DEVFN &&
192 !dev->bus->parent->self->bus->parent) 186 !dev->bus->parent->self->bus->parent)
193 return IRQ_IXDP2800_PMC; 187 return IRQ_IXDP2800_PMC;
194 188
195 /* 189 /*
196 * Device behind the first bridge 190 * Device behind the first bridge
197 */ 191 */
198 if(dev->bus->self->devfn == IXDP2X00_P2P_DEVFN) { 192 if(dev->bus->self->devfn == IXDP2X00_P2P_DEVFN) {
199 switch(dev->devfn) { 193 switch(dev->devfn) {
200 case IXDP2X00_PMC_DEVFN: 194 case IXDP2X00_PMC_DEVFN:
201 return IRQ_IXDP2800_PMC; 195 return IRQ_IXDP2800_PMC;
202 196
203 case IXDP2800_MASTER_ENET_DEVFN: 197 case IXDP2800_MASTER_ENET_DEVFN:
204 return IRQ_IXDP2800_EGRESS_ENET; 198 return IRQ_IXDP2800_EGRESS_ENET;
205 199
206 case IXDP2800_SWITCH_FABRIC_DEVFN: 200 case IXDP2800_SWITCH_FABRIC_DEVFN:
207 return IRQ_IXDP2800_FABRIC; 201 return IRQ_IXDP2800_FABRIC;
208 } 202 }
209 } 203 }
210 204
211 return -1; 205 return -1;
212 } else return IRQ_IXP2000_PCIB; /* Slave NIC interrupt */ 206 } else return IRQ_IXP2000_PCIB; /* Slave NIC interrupt */
213 } 207 }
214 208
215 static void __init ixdp2800_master_enable_slave(void) 209 static void __init ixdp2800_master_enable_slave(void)
216 { 210 {
217 volatile u32 *addr; 211 volatile u32 *addr;
218 212
219 printk(KERN_INFO "IXDP2800: enabling slave NPU\n"); 213 printk(KERN_INFO "IXDP2800: enabling slave NPU\n");
220 214
221 addr = (volatile u32 *)ixp2000_pci_config_addr(0, 215 addr = (volatile u32 *)ixp2000_pci_config_addr(0,
222 IXDP2X00_SLAVE_NPU_DEVFN, 216 IXDP2X00_SLAVE_NPU_DEVFN,
223 PCI_COMMAND); 217 PCI_COMMAND);
224 218
225 *addr |= PCI_COMMAND_MASTER; 219 *addr |= PCI_COMMAND_MASTER;
226 } 220 }
227 221
228 static void __init ixdp2800_master_wait_for_slave_bus_scan(void) 222 static void __init ixdp2800_master_wait_for_slave_bus_scan(void)
229 { 223 {
230 volatile u32 *addr; 224 volatile u32 *addr;
231 225
232 printk(KERN_INFO "IXDP2800: waiting for slave to finish bus scan\n"); 226 printk(KERN_INFO "IXDP2800: waiting for slave to finish bus scan\n");
233 227
234 addr = (volatile u32 *)ixp2000_pci_config_addr(0, 228 addr = (volatile u32 *)ixp2000_pci_config_addr(0,
235 IXDP2X00_SLAVE_NPU_DEVFN, 229 IXDP2X00_SLAVE_NPU_DEVFN,
236 PCI_COMMAND); 230 PCI_COMMAND);
237 while ((*addr & PCI_COMMAND_MEMORY) == 0) 231 while ((*addr & PCI_COMMAND_MEMORY) == 0)
238 cpu_relax(); 232 cpu_relax();
239 } 233 }
240 234
241 static void __init ixdp2800_slave_signal_bus_scan_completion(void) 235 static void __init ixdp2800_slave_signal_bus_scan_completion(void)
242 { 236 {
243 printk(KERN_INFO "IXDP2800: bus scan done, signaling master\n"); 237 printk(KERN_INFO "IXDP2800: bus scan done, signaling master\n");
244 *IXP2000_PCI_CMDSTAT |= PCI_COMMAND_MEMORY; 238 *IXP2000_PCI_CMDSTAT |= PCI_COMMAND_MEMORY;
245 } 239 }
246 240
247 static void __init ixdp2800_pci_postinit(void) 241 static void __init ixdp2800_pci_postinit(void)
248 { 242 {
249 if (!ixdp2x00_master_npu()) { 243 if (!ixdp2x00_master_npu()) {
250 ixdp2x00_slave_pci_postinit(); 244 ixdp2x00_slave_pci_postinit();
251 ixdp2800_slave_signal_bus_scan_completion(); 245 ixdp2800_slave_signal_bus_scan_completion();
252 } 246 }
253 } 247 }
254 248
255 struct __initdata hw_pci ixdp2800_pci __initdata = { 249 struct __initdata hw_pci ixdp2800_pci __initdata = {
256 .nr_controllers = 1, 250 .nr_controllers = 1,
257 .setup = ixdp2800_pci_setup, 251 .setup = ixdp2800_pci_setup,
258 .preinit = ixdp2800_pci_preinit, 252 .preinit = ixdp2800_pci_preinit,
259 .postinit = ixdp2800_pci_postinit, 253 .postinit = ixdp2800_pci_postinit,
260 .scan = ixp2000_pci_scan_bus, 254 .scan = ixp2000_pci_scan_bus,
261 .map_irq = ixdp2800_pci_map_irq, 255 .map_irq = ixdp2800_pci_map_irq,
262 }; 256 };
263 257
264 int __init ixdp2800_pci_init(void) 258 int __init ixdp2800_pci_init(void)
265 { 259 {
266 if (machine_is_ixdp2800()) { 260 if (machine_is_ixdp2800()) {
267 struct pci_dev *dev; 261 struct pci_dev *dev;
268 262
269 pci_common_init(&ixdp2800_pci); 263 pci_common_init(&ixdp2800_pci);
270 if (ixdp2x00_master_npu()) { 264 if (ixdp2x00_master_npu()) {
271 dev = pci_find_slot(1, IXDP2800_SLAVE_ENET_DEVFN); 265 dev = pci_find_slot(1, IXDP2800_SLAVE_ENET_DEVFN);
272 pci_remove_bus_device(dev); 266 pci_remove_bus_device(dev);
273 267
274 ixdp2800_master_enable_slave(); 268 ixdp2800_master_enable_slave();
275 ixdp2800_master_wait_for_slave_bus_scan(); 269 ixdp2800_master_wait_for_slave_bus_scan();
276 } else { 270 } else {
277 dev = pci_find_slot(1, IXDP2800_MASTER_ENET_DEVFN); 271 dev = pci_find_slot(1, IXDP2800_MASTER_ENET_DEVFN);
278 pci_remove_bus_device(dev); 272 pci_remove_bus_device(dev);
279 } 273 }
280 } 274 }
281 275
282 return 0; 276 return 0;
283 } 277 }
284 278
285 subsys_initcall(ixdp2800_pci_init); 279 subsys_initcall(ixdp2800_pci_init);
286 280
287 void ixdp2800_init_irq(void) 281 void ixdp2800_init_irq(void)
288 { 282 {
289 ixdp2x00_init_irq(IXDP2800_CPLD_INT_STAT, IXDP2800_CPLD_INT_MASK, IXDP2800_NR_IRQS); 283 ixdp2x00_init_irq(IXDP2800_CPLD_INT_STAT, IXDP2800_CPLD_INT_MASK, IXDP2800_NR_IRQS);
290 } 284 }
291 285
292 MACHINE_START(IXDP2800, "Intel IXDP2800 Development Platform") 286 MACHINE_START(IXDP2800, "Intel IXDP2800 Development Platform")
293 MAINTAINER("MontaVista Software, Inc.") 287 MAINTAINER("MontaVista Software, Inc.")
294 BOOT_MEM(0x00000000, IXP2000_UART_PHYS_BASE, IXP2000_UART_VIRT_BASE) 288 BOOT_MEM(0x00000000, IXP2000_UART_PHYS_BASE, IXP2000_UART_VIRT_BASE)
295 BOOT_PARAMS(0x00000100) 289 BOOT_PARAMS(0x00000100)
296 MAPIO(ixdp2x00_map_io) 290 MAPIO(ixdp2x00_map_io)
297 INITIRQ(ixdp2800_init_irq) 291 INITIRQ(ixdp2800_init_irq)
298 .timer = &ixdp2800_timer, 292 .timer = &ixdp2800_timer,
299 INIT_MACHINE(ixdp2x00_init_machine) 293 INIT_MACHINE(ixdp2x00_init_machine)
300 MACHINE_END 294 MACHINE_END
301 295
302 296