Eric Lee / linux-smarc-t335x-v3.2

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/*

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/*

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* New driver for Marvell Yukon 2 chipset.

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* New driver for Marvell Yukon 2 chipset.

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* Based on earlier sk98lin, and skge driver.

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* Based on earlier sk98lin, and skge driver.

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*

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*

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* This driver intentionally does not support all the features

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* This driver intentionally does not support all the features

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* of the original driver such as link fail-over and link management because

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* of the original driver such as link fail-over and link management because

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* those should be done at higher levels.

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* those should be done at higher levels.

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*

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*

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*

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*

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* This program is free software; you can redistribute it and/or modify

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* This program is free software; you can redistribute it and/or modify

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* it under the terms of the GNU General Public License as published by

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* it under the terms of the GNU General Public License as published by

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* the Free Software Foundation; either version 2 of the License, or

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* the Free Software Foundation; either version 2 of the License, or

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* (at your option) any later version.

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* (at your option) any later version.

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*

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*

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* This program is distributed in the hope that it will be useful,

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* This program is distributed in the hope that it will be useful,

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* but WITHOUT ANY WARRANTY; without even the implied warranty of

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* but WITHOUT ANY WARRANTY; without even the implied warranty of

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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

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* GNU General Public License for more details.

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* GNU General Public License for more details.

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*

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*

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* You should have received a copy of the GNU General Public License

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* You should have received a copy of the GNU General Public License

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* along with this program; if not, write to the Free Software

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* along with this program; if not, write to the Free Software

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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.

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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.

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*/

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*/

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#include <linux/config.h>

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#include <linux/config.h>

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#include <linux/crc32.h>

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#include <linux/crc32.h>

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#include <linux/kernel.h>

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#include <linux/kernel.h>

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#include <linux/version.h>

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#include <linux/version.h>

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#include <linux/module.h>

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#include <linux/module.h>

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#include <linux/netdevice.h>

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#include <linux/netdevice.h>

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#include <linux/dma-mapping.h>

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#include <linux/dma-mapping.h>

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#include <linux/etherdevice.h>

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#include <linux/etherdevice.h>

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#include <linux/ethtool.h>

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#include <linux/ethtool.h>

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#include <linux/pci.h>

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#include <linux/pci.h>

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#include <linux/ip.h>

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#include <linux/ip.h>

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#include <linux/tcp.h>

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#include <linux/tcp.h>

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#include <linux/in.h>

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#include <linux/in.h>

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#include <linux/delay.h>

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#include <linux/delay.h>

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#include <linux/workqueue.h>

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#include <linux/workqueue.h>

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#include <linux/if_vlan.h>

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#include <linux/if_vlan.h>

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#include <linux/prefetch.h>

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#include <linux/prefetch.h>

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#include <linux/mii.h>

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#include <linux/mii.h>

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#include <asm/irq.h>

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#include <asm/irq.h>

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#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)

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#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)

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#define SKY2_VLAN_TAG_USED 1

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#define SKY2_VLAN_TAG_USED 1

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#endif

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#endif

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#include "sky2.h"

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#include "sky2.h"

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#define DRV_NAME "sky2"

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#define DRV_NAME "sky2"

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#define DRV_VERSION "0.15"

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#define DRV_VERSION "0.15"

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#define PFX DRV_NAME " "

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#define PFX DRV_NAME " "

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/*

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/*

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* The Yukon II chipset takes 64 bit command blocks (called list elements)

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* The Yukon II chipset takes 64 bit command blocks (called list elements)

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* that are organized into three (receive, transmit, status) different rings

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* that are organized into three (receive, transmit, status) different rings

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* similar to Tigon3. A transmit can require several elements;

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* similar to Tigon3. A transmit can require several elements;

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* a receive requires one (or two if using 64 bit dma).

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* a receive requires one (or two if using 64 bit dma).

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*/

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*/

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#define is_ec_a1(hw) \

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unlikely((hw)->chip_id == CHIP_ID_YUKON_EC && \

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(hw)->chip_rev == CHIP_REV_YU_EC_A1)

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#define RX_LE_SIZE 512

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#define RX_LE_SIZE 512

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#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))

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#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))

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#define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)

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#define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)

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#define RX_DEF_PENDING RX_MAX_PENDING

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#define RX_DEF_PENDING RX_MAX_PENDING

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#define RX_SKB_ALIGN 8

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#define RX_SKB_ALIGN 8

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#define TX_RING_SIZE 512

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#define TX_RING_SIZE 512

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#define TX_DEF_PENDING (TX_RING_SIZE - 1)

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#define TX_DEF_PENDING (TX_RING_SIZE - 1)

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#define TX_MIN_PENDING 64

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#define TX_MIN_PENDING 64

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#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)

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#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)

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#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */

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#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */

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#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))

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#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))

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#define ETH_JUMBO_MTU 9000

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#define ETH_JUMBO_MTU 9000

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#define TX_WATCHDOG (5 * HZ)

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#define TX_WATCHDOG (5 * HZ)

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#define NAPI_WEIGHT 64

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#define NAPI_WEIGHT 64

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#define PHY_RETRIES 1000

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#define PHY_RETRIES 1000

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static const u32 default_msg =

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static const u32 default_msg =

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NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK

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NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK

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| NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR

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| NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR

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| NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;

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| NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;

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static int debug = -1; /* defaults above */

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static int debug = -1; /* defaults above */

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module_param(debug, int, 0);

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module_param(debug, int, 0);

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MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");

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MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");

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static int copybreak __read_mostly = 256;

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static int copybreak __read_mostly = 256;

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module_param(copybreak, int, 0);

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module_param(copybreak, int, 0);

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MODULE_PARM_DESC(copybreak, "Receive copy threshold");

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MODULE_PARM_DESC(copybreak, "Receive copy threshold");

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static const struct pci_device_id sky2_id_table[] = {

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static const struct pci_device_id sky2_id_table[] = {

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{ PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },

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{ PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },

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{ PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },

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{ PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },

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{ PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) },

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{ PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) },

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{ PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) },

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{ PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) },

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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },

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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },

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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },

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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },

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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },

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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },

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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },

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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },

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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },

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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },

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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },

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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },

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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },

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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },

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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },

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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },

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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },

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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },

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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },

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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },

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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },

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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },

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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },

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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },

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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },

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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },

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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },

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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },

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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },

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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },

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{ 0 }

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{ 0 }

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};

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};

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MODULE_DEVICE_TABLE(pci, sky2_id_table);

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MODULE_DEVICE_TABLE(pci, sky2_id_table);

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/* Avoid conditionals by using array */

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/* Avoid conditionals by using array */

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static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };

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static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };

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static const unsigned rxqaddr[] = { Q_R1, Q_R2 };

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static const unsigned rxqaddr[] = { Q_R1, Q_R2 };

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/* This driver supports yukon2 chipset only */

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/* This driver supports yukon2 chipset only */

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static const char *yukon2_name[] = {

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static const char *yukon2_name[] = {

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"XL", /* 0xb3 */

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"XL", /* 0xb3 */

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"EC Ultra", /* 0xb4 */

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"EC Ultra", /* 0xb4 */

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"UNKNOWN", /* 0xb5 */

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"UNKNOWN", /* 0xb5 */

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"EC", /* 0xb6 */

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"EC", /* 0xb6 */

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"FE", /* 0xb7 */

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"FE", /* 0xb7 */

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};

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};

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/* Access to external PHY */

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/* Access to external PHY */

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static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)

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static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)

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{

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{

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int i;

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int i;

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gma_write16(hw, port, GM_SMI_DATA, val);

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gma_write16(hw, port, GM_SMI_DATA, val);

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gma_write16(hw, port, GM_SMI_CTRL,

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gma_write16(hw, port, GM_SMI_CTRL,

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GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));

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GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));

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for (i = 0; i < PHY_RETRIES; i++) {

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for (i = 0; i < PHY_RETRIES; i++) {

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if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))

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if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))

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return 0;

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return 0;

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udelay(1);

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udelay(1);

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}

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}

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printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);

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printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);

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return -ETIMEDOUT;

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return -ETIMEDOUT;

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}

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}

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static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)

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static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)

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{

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{

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int i;

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int i;

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gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)

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gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)

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| GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);

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| GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);

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for (i = 0; i < PHY_RETRIES; i++) {

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for (i = 0; i < PHY_RETRIES; i++) {

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if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {

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if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {

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*val = gma_read16(hw, port, GM_SMI_DATA);

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*val = gma_read16(hw, port, GM_SMI_DATA);

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return 0;

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return 0;

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}

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}

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udelay(1);

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udelay(1);

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}

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}

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return -ETIMEDOUT;

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return -ETIMEDOUT;

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}

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}

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static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)

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static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)

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{

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{

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u16 v;

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u16 v;

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if (__gm_phy_read(hw, port, reg, &v) != 0)

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if (__gm_phy_read(hw, port, reg, &v) != 0)

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printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);

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printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);

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return v;

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return v;

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}

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}

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static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)

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static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)

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{

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{

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u16 power_control;

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u16 power_control;

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u32 reg1;

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u32 reg1;

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int vaux;

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int vaux;

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int ret = 0;

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int ret = 0;

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186

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pr_debug("sky2_set_power_state %d\n", state);

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pr_debug("sky2_set_power_state %d\n", state);

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sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);

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sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);

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189

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power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_PMC);

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power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_PMC);

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vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) &&

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vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) &&

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(power_control & PCI_PM_CAP_PME_D3cold);

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(power_control & PCI_PM_CAP_PME_D3cold);

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193

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power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_CTRL);

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power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_CTRL);

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195

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power_control |= PCI_PM_CTRL_PME_STATUS;

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power_control |= PCI_PM_CTRL_PME_STATUS;

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power_control &= ~(PCI_PM_CTRL_STATE_MASK);

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power_control &= ~(PCI_PM_CTRL_STATE_MASK);

202

198

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switch (state) {

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switch (state) {

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case PCI_D0:

200

case PCI_D0:

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/* switch power to VCC (WA for VAUX problem) */

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/* switch power to VCC (WA for VAUX problem) */

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sky2_write8(hw, B0_POWER_CTRL,

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sky2_write8(hw, B0_POWER_CTRL,

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PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);

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PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);

208

204

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/* disable Core Clock Division, */

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/* disable Core Clock Division, */

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sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);

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sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);

211

207

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if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)

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if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)

213

/* enable bits are inverted */

209

/* enable bits are inverted */

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sky2_write8(hw, B2_Y2_CLK_GATE,

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sky2_write8(hw, B2_Y2_CLK_GATE,

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Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |

211

Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |

216

Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |

212

Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |

217

Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);

213

Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);

218

else

214

else

219

sky2_write8(hw, B2_Y2_CLK_GATE, 0);

215

sky2_write8(hw, B2_Y2_CLK_GATE, 0);

220

216

221

/* Turn off phy power saving */

217

/* Turn off phy power saving */

222

reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);

218

reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);

223

reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);

219

reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);

224

220

225

/* looks like this XL is back asswards .. */

221

/* looks like this XL is back asswards .. */

226

if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) {

222

if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) {

227

reg1 |= PCI_Y2_PHY1_COMA;

223

reg1 |= PCI_Y2_PHY1_COMA;

228

if (hw->ports > 1)

224

if (hw->ports > 1)

229

reg1 |= PCI_Y2_PHY2_COMA;

225

reg1 |= PCI_Y2_PHY2_COMA;

230

}

226

}

231

227

232

if (hw->chip_id == CHIP_ID_YUKON_EC_U) {

228

if (hw->chip_id == CHIP_ID_YUKON_EC_U) {

233

sky2_pci_write32(hw, PCI_DEV_REG3, 0);

229

sky2_pci_write32(hw, PCI_DEV_REG3, 0);

234

reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);

230

reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);

235

reg1 &= P_ASPM_CONTROL_MSK;

231

reg1 &= P_ASPM_CONTROL_MSK;

236

sky2_pci_write32(hw, PCI_DEV_REG4, reg1);

232

sky2_pci_write32(hw, PCI_DEV_REG4, reg1);

237

sky2_pci_write32(hw, PCI_DEV_REG5, 0);

233

sky2_pci_write32(hw, PCI_DEV_REG5, 0);

238

}

234

}

239

235

240

sky2_pci_write32(hw, PCI_DEV_REG1, reg1);

236

sky2_pci_write32(hw, PCI_DEV_REG1, reg1);

241

237

242

break;

238

break;

243

239

244

case PCI_D3hot:

240

case PCI_D3hot:

245

case PCI_D3cold:

241

case PCI_D3cold:

246

/* Turn on phy power saving */

242

/* Turn on phy power saving */

247

reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);

243

reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);

248

if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)

244

if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)

249

reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);

245

reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);

250

else

246

else

251

reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);

247

reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);

252

sky2_pci_write32(hw, PCI_DEV_REG1, reg1);

248

sky2_pci_write32(hw, PCI_DEV_REG1, reg1);

253

249

254

if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)

250

if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)

255

sky2_write8(hw, B2_Y2_CLK_GATE, 0);

251

sky2_write8(hw, B2_Y2_CLK_GATE, 0);

256

else

252

else

257

/* enable bits are inverted */

253

/* enable bits are inverted */

258

sky2_write8(hw, B2_Y2_CLK_GATE,

254

sky2_write8(hw, B2_Y2_CLK_GATE,

259

Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |

255

Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |

260

Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |

256

Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |

261

Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);

257

Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);

262

258

263

/* switch power to VAUX */

259

/* switch power to VAUX */

264

if (vaux && state != PCI_D3cold)

260

if (vaux && state != PCI_D3cold)

265

sky2_write8(hw, B0_POWER_CTRL,

261

sky2_write8(hw, B0_POWER_CTRL,

266

(PC_VAUX_ENA | PC_VCC_ENA |

262

(PC_VAUX_ENA | PC_VCC_ENA |

267

PC_VAUX_ON | PC_VCC_OFF));

263

PC_VAUX_ON | PC_VCC_OFF));

268

break;

264

break;

269

default:

265

default:

270

printk(KERN_ERR PFX "Unknown power state %d\n", state);

266

printk(KERN_ERR PFX "Unknown power state %d\n", state);

271

ret = -1;

267

ret = -1;

272

}

268

}

273

269

274

sky2_pci_write16(hw, hw->pm_cap + PCI_PM_CTRL, power_control);

270

sky2_pci_write16(hw, hw->pm_cap + PCI_PM_CTRL, power_control);

275

sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);

271

sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);

276

return ret;

272

return ret;

277

}

273

}

278

274

279

static void sky2_phy_reset(struct sky2_hw *hw, unsigned port)

275

static void sky2_phy_reset(struct sky2_hw *hw, unsigned port)

280

{

276

{

281

u16 reg;

277

u16 reg;

282

278

283

/* disable all GMAC IRQ's */

279

/* disable all GMAC IRQ's */

284

sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);

280

sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);

285

/* disable PHY IRQs */

281

/* disable PHY IRQs */

286

gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);

282

gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);

287

283

288

gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */

284

gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */

289

gma_write16(hw, port, GM_MC_ADDR_H2, 0);

285

gma_write16(hw, port, GM_MC_ADDR_H2, 0);

290

gma_write16(hw, port, GM_MC_ADDR_H3, 0);

286

gma_write16(hw, port, GM_MC_ADDR_H3, 0);

291

gma_write16(hw, port, GM_MC_ADDR_H4, 0);

287

gma_write16(hw, port, GM_MC_ADDR_H4, 0);

292

288

293

reg = gma_read16(hw, port, GM_RX_CTRL);

289

reg = gma_read16(hw, port, GM_RX_CTRL);

294

reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;

290

reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;

295

gma_write16(hw, port, GM_RX_CTRL, reg);

291

gma_write16(hw, port, GM_RX_CTRL, reg);

296

}

292

}

297

293

298

static void sky2_phy_init(struct sky2_hw *hw, unsigned port)

294

static void sky2_phy_init(struct sky2_hw *hw, unsigned port)

299

{

295

{

300

struct sky2_port *sky2 = netdev_priv(hw->dev[port]);

296

struct sky2_port *sky2 = netdev_priv(hw->dev[port]);

301

u16 ctrl, ct1000, adv, pg, ledctrl, ledover;

297

u16 ctrl, ct1000, adv, pg, ledctrl, ledover;

302

298

303

if (sky2->autoneg == AUTONEG_ENABLE && hw->chip_id != CHIP_ID_YUKON_XL) {

299

if (sky2->autoneg == AUTONEG_ENABLE && hw->chip_id != CHIP_ID_YUKON_XL) {

304

u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);

300

u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);

305

301

306

ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |

302

ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |

307

PHY_M_EC_MAC_S_MSK);

303

PHY_M_EC_MAC_S_MSK);

308

ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);

304

ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);

309

305

310

if (hw->chip_id == CHIP_ID_YUKON_EC)

306

if (hw->chip_id == CHIP_ID_YUKON_EC)

311

ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;

307

ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;

312

else

308

else

313

ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);

309

ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);

314

310

315

gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);

311

gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);

316

}

312

}

317

313

318

ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);

314

ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);

319

if (hw->copper) {

315

if (hw->copper) {

320

if (hw->chip_id == CHIP_ID_YUKON_FE) {

316

if (hw->chip_id == CHIP_ID_YUKON_FE) {

321

/* enable automatic crossover */

317

/* enable automatic crossover */

322

ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;

318

ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;

323

} else {

319

} else {

324

/* disable energy detect */

320

/* disable energy detect */

325

ctrl &= ~PHY_M_PC_EN_DET_MSK;

321

ctrl &= ~PHY_M_PC_EN_DET_MSK;

326

322

327

/* enable automatic crossover */

323

/* enable automatic crossover */

328

ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);

324

ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);

329

325

330

if (sky2->autoneg == AUTONEG_ENABLE &&

326

if (sky2->autoneg == AUTONEG_ENABLE &&

331

hw->chip_id == CHIP_ID_YUKON_XL) {

327

hw->chip_id == CHIP_ID_YUKON_XL) {

332

ctrl &= ~PHY_M_PC_DSC_MSK;

328

ctrl &= ~PHY_M_PC_DSC_MSK;

333

ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;

329

ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;

334

}

330

}

335

}

331

}

336

gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);

332

gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);

337

} else {

333

} else {

338

/* workaround for deviation #4.88 (CRC errors) */

334

/* workaround for deviation #4.88 (CRC errors) */

339

/* disable Automatic Crossover */

335

/* disable Automatic Crossover */

340

336

341

ctrl &= ~PHY_M_PC_MDIX_MSK;

337

ctrl &= ~PHY_M_PC_MDIX_MSK;

342

gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);

338

gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);

343

339

344

if (hw->chip_id == CHIP_ID_YUKON_XL) {

340

if (hw->chip_id == CHIP_ID_YUKON_XL) {

345

/* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */

341

/* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */

346

gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);

342

gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);

347

ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);

343

ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);

348

ctrl &= ~PHY_M_MAC_MD_MSK;

344

ctrl &= ~PHY_M_MAC_MD_MSK;

349

ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);

345

ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);

350

gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);

346

gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);

351

347

352

/* select page 1 to access Fiber registers */

348

/* select page 1 to access Fiber registers */

353

gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);

349

gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);

354

}

350

}

355

}

351

}

356

352

357

ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);

353

ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);

358

if (sky2->autoneg == AUTONEG_DISABLE)

354

if (sky2->autoneg == AUTONEG_DISABLE)

359

ctrl &= ~PHY_CT_ANE;

355

ctrl &= ~PHY_CT_ANE;

360

else

356

else

361

ctrl |= PHY_CT_ANE;

357

ctrl |= PHY_CT_ANE;

362

358

363

ctrl |= PHY_CT_RESET;

359

ctrl |= PHY_CT_RESET;

364

gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);

360

gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);

365

361

366

ctrl = 0;

362

ctrl = 0;

367

ct1000 = 0;

363

ct1000 = 0;

368

adv = PHY_AN_CSMA;

364

adv = PHY_AN_CSMA;

369

365

370

if (sky2->autoneg == AUTONEG_ENABLE) {

366

if (sky2->autoneg == AUTONEG_ENABLE) {

371

if (hw->copper) {

367

if (hw->copper) {

372

if (sky2->advertising & ADVERTISED_1000baseT_Full)

368

if (sky2->advertising & ADVERTISED_1000baseT_Full)

373

ct1000 |= PHY_M_1000C_AFD;

369

ct1000 |= PHY_M_1000C_AFD;

374

if (sky2->advertising & ADVERTISED_1000baseT_Half)

370

if (sky2->advertising & ADVERTISED_1000baseT_Half)

375

ct1000 |= PHY_M_1000C_AHD;

371

ct1000 |= PHY_M_1000C_AHD;

376

if (sky2->advertising & ADVERTISED_100baseT_Full)

372

if (sky2->advertising & ADVERTISED_100baseT_Full)

377

adv |= PHY_M_AN_100_FD;

373

adv |= PHY_M_AN_100_FD;

378

if (sky2->advertising & ADVERTISED_100baseT_Half)

374

if (sky2->advertising & ADVERTISED_100baseT_Half)

379

adv |= PHY_M_AN_100_HD;

375

adv |= PHY_M_AN_100_HD;

380

if (sky2->advertising & ADVERTISED_10baseT_Full)

376

if (sky2->advertising & ADVERTISED_10baseT_Full)

381

adv |= PHY_M_AN_10_FD;

377

adv |= PHY_M_AN_10_FD;

382

if (sky2->advertising & ADVERTISED_10baseT_Half)

378

if (sky2->advertising & ADVERTISED_10baseT_Half)

383

adv |= PHY_M_AN_10_HD;

379

adv |= PHY_M_AN_10_HD;

384

} else /* special defines for FIBER (88E1011S only) */

380

} else /* special defines for FIBER (88E1011S only) */

385

adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;

381

adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;

386

382

387

/* Set Flow-control capabilities */

383

/* Set Flow-control capabilities */

388

if (sky2->tx_pause && sky2->rx_pause)

384

if (sky2->tx_pause && sky2->rx_pause)

389

adv |= PHY_AN_PAUSE_CAP; /* symmetric */

385

adv |= PHY_AN_PAUSE_CAP; /* symmetric */

390

else if (sky2->rx_pause && !sky2->tx_pause)

386

else if (sky2->rx_pause && !sky2->tx_pause)

391

adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;

387

adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;

392

else if (!sky2->rx_pause && sky2->tx_pause)

388

else if (!sky2->rx_pause && sky2->tx_pause)

393

adv |= PHY_AN_PAUSE_ASYM; /* local */

389

adv |= PHY_AN_PAUSE_ASYM; /* local */

394

390

395

/* Restart Auto-negotiation */

391

/* Restart Auto-negotiation */

396

ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;

392

ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;

397

} else {

393

} else {

398

/* forced speed/duplex settings */

394

/* forced speed/duplex settings */

399

ct1000 = PHY_M_1000C_MSE;

395

ct1000 = PHY_M_1000C_MSE;

400

396

401

if (sky2->duplex == DUPLEX_FULL)

397

if (sky2->duplex == DUPLEX_FULL)

402

ctrl |= PHY_CT_DUP_MD;

398

ctrl |= PHY_CT_DUP_MD;

403

399

404

switch (sky2->speed) {

400

switch (sky2->speed) {

405

case SPEED_1000:

401

case SPEED_1000:

406

ctrl |= PHY_CT_SP1000;

402

ctrl |= PHY_CT_SP1000;

407

break;

403

break;

408

case SPEED_100:

404

case SPEED_100:

409

ctrl |= PHY_CT_SP100;

405

ctrl |= PHY_CT_SP100;

410

break;

406

break;

411

}

407

}

412

408

413

ctrl |= PHY_CT_RESET;

409

ctrl |= PHY_CT_RESET;

414

}

410

}

415

411

416

if (hw->chip_id != CHIP_ID_YUKON_FE)

412

if (hw->chip_id != CHIP_ID_YUKON_FE)

417

gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);

413

gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);

418

414

419

gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);

415

gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);

420

gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);

416

gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);

421

417

422

/* Setup Phy LED's */

418

/* Setup Phy LED's */

423

ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);

419

ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);

424

ledover = 0;

420

ledover = 0;

425

421

426

switch (hw->chip_id) {

422

switch (hw->chip_id) {

427

case CHIP_ID_YUKON_FE:

423

case CHIP_ID_YUKON_FE:

428

/* on 88E3082 these bits are at 11..9 (shifted left) */

424

/* on 88E3082 these bits are at 11..9 (shifted left) */

429

ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;

425

ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;

430

426

431

ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);

427

ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);

432

428

433

/* delete ACT LED control bits */

429

/* delete ACT LED control bits */

434

ctrl &= ~PHY_M_FELP_LED1_MSK;

430

ctrl &= ~PHY_M_FELP_LED1_MSK;

435

/* change ACT LED control to blink mode */

431

/* change ACT LED control to blink mode */

436

ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);

432

ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);

437

gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);

433

gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);

438

break;

434

break;

439

435

440

case CHIP_ID_YUKON_XL:

436

case CHIP_ID_YUKON_XL:

441

pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);

437

pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);

442

438

443

/* select page 3 to access LED control register */

439

/* select page 3 to access LED control register */

444

gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);

440

gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);

445

441

446

/* set LED Function Control register */

442

/* set LED Function Control register */

447

gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */

443

gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */

448

PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */

444

PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */

449

PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */

445

PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */

450

PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */

446

PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */

451

447

452

/* set Polarity Control register */

448

/* set Polarity Control register */

453

gm_phy_write(hw, port, PHY_MARV_PHY_STAT,

449

gm_phy_write(hw, port, PHY_MARV_PHY_STAT,

454

(PHY_M_POLC_LS1_P_MIX(4) |

450

(PHY_M_POLC_LS1_P_MIX(4) |

455

PHY_M_POLC_IS0_P_MIX(4) |

451

PHY_M_POLC_IS0_P_MIX(4) |

456

PHY_M_POLC_LOS_CTRL(2) |

452

PHY_M_POLC_LOS_CTRL(2) |

457

PHY_M_POLC_INIT_CTRL(2) |

453

PHY_M_POLC_INIT_CTRL(2) |

458

PHY_M_POLC_STA1_CTRL(2) |

454

PHY_M_POLC_STA1_CTRL(2) |

459

PHY_M_POLC_STA0_CTRL(2)));

455

PHY_M_POLC_STA0_CTRL(2)));

460

456

461

/* restore page register */

457

/* restore page register */

462

gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);

458

gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);

463

break;

459

break;

464

460

465

default:

461

default:

466

/* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */

462

/* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */

467

ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;

463

ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;

468

/* turn off the Rx LED (LED_RX) */

464

/* turn off the Rx LED (LED_RX) */

469

ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);

465

ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);

470

}

466

}

471

467

472

if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {

468

if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {

473

/* apply fixes in PHY AFE */

469

/* apply fixes in PHY AFE */

474

gm_phy_write(hw, port, 22, 255);

470

gm_phy_write(hw, port, 22, 255);

475

/* increase differential signal amplitude in 10BASE-T */

471

/* increase differential signal amplitude in 10BASE-T */

476

gm_phy_write(hw, port, 24, 0xaa99);

472

gm_phy_write(hw, port, 24, 0xaa99);

477

gm_phy_write(hw, port, 23, 0x2011);

473

gm_phy_write(hw, port, 23, 0x2011);

478

474

479

/* fix for IEEE A/B Symmetry failure in 1000BASE-T */

475

/* fix for IEEE A/B Symmetry failure in 1000BASE-T */

480

gm_phy_write(hw, port, 24, 0xa204);

476

gm_phy_write(hw, port, 24, 0xa204);

481

gm_phy_write(hw, port, 23, 0x2002);

477

gm_phy_write(hw, port, 23, 0x2002);

482

478

483

/* set page register to 0 */

479

/* set page register to 0 */

484

gm_phy_write(hw, port, 22, 0);

480

gm_phy_write(hw, port, 22, 0);

485

} else {

481

} else {

486

gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);

482

gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);

487

483

488

if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {

484

if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {

489

/* turn on 100 Mbps LED (LED_LINK100) */

485

/* turn on 100 Mbps LED (LED_LINK100) */

490

ledover |= PHY_M_LED_MO_100(MO_LED_ON);

486

ledover |= PHY_M_LED_MO_100(MO_LED_ON);

491

}

487

}

492

488

493

if (ledover)

489

if (ledover)

494

gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);

490

gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);

495

491

496

}

492

}

497

/* Enable phy interrupt on auto-negotiation complete (or link up) */

493

/* Enable phy interrupt on auto-negotiation complete (or link up) */

498

if (sky2->autoneg == AUTONEG_ENABLE)

494

if (sky2->autoneg == AUTONEG_ENABLE)

499

gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);

495

gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);

500

else

496

else

501

gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);

497

gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);

502

}

498

}

503

499

504

/* Force a renegotiation */

500

/* Force a renegotiation */

505

static void sky2_phy_reinit(struct sky2_port *sky2)

501

static void sky2_phy_reinit(struct sky2_port *sky2)

506

{

502

{

507

down(&sky2->phy_sema);

503

down(&sky2->phy_sema);

508

sky2_phy_init(sky2->hw, sky2->port);

504

sky2_phy_init(sky2->hw, sky2->port);

509

up(&sky2->phy_sema);

505

up(&sky2->phy_sema);

510

}

506

}

511

507

512

static void sky2_mac_init(struct sky2_hw *hw, unsigned port)

508

static void sky2_mac_init(struct sky2_hw *hw, unsigned port)

513

{

509

{

514

struct sky2_port *sky2 = netdev_priv(hw->dev[port]);

510

struct sky2_port *sky2 = netdev_priv(hw->dev[port]);

515

u16 reg;

511

u16 reg;

516

int i;

512

int i;

517

const u8 *addr = hw->dev[port]->dev_addr;

513

const u8 *addr = hw->dev[port]->dev_addr;

518

514

519

sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);

515

sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);

520

sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);

516

sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);

521

517

522

sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);

518

sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);

523

519

524

if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {

520

if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {

525

/* WA DEV_472 -- looks like crossed wires on port 2 */

521

/* WA DEV_472 -- looks like crossed wires on port 2 */

526

/* clear GMAC 1 Control reset */

522

/* clear GMAC 1 Control reset */

527

sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);

523

sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);

528

do {

524

do {

529

sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);

525

sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);

530

sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);

526

sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);

531

} while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||

527

} while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||

532

gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||

528

gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||

533

gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);

529

gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);

534

}

530

}

535

531

536

if (sky2->autoneg == AUTONEG_DISABLE) {

532

if (sky2->autoneg == AUTONEG_DISABLE) {

537

reg = gma_read16(hw, port, GM_GP_CTRL);

533

reg = gma_read16(hw, port, GM_GP_CTRL);

538

reg |= GM_GPCR_AU_ALL_DIS;

534

reg |= GM_GPCR_AU_ALL_DIS;

539

gma_write16(hw, port, GM_GP_CTRL, reg);

535

gma_write16(hw, port, GM_GP_CTRL, reg);

540

gma_read16(hw, port, GM_GP_CTRL);

536

gma_read16(hw, port, GM_GP_CTRL);

541

537

542

switch (sky2->speed) {

538

switch (sky2->speed) {

543

case SPEED_1000:

539

case SPEED_1000:

544

reg &= ~GM_GPCR_SPEED_100;

540

reg &= ~GM_GPCR_SPEED_100;

545

reg |= GM_GPCR_SPEED_1000;

541

reg |= GM_GPCR_SPEED_1000;

546

break;

542

break;

547

case SPEED_100:

543

case SPEED_100:

548

reg &= ~GM_GPCR_SPEED_1000;

544

reg &= ~GM_GPCR_SPEED_1000;

549

reg |= GM_GPCR_SPEED_100;

545

reg |= GM_GPCR_SPEED_100;

550

break;

546

break;

551

case SPEED_10:

547

case SPEED_10:

552

reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);

548

reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);

553

break;

549

break;

554

}

550

}

555

551

556

if (sky2->duplex == DUPLEX_FULL)

552

if (sky2->duplex == DUPLEX_FULL)

557

reg |= GM_GPCR_DUP_FULL;

553

reg |= GM_GPCR_DUP_FULL;

558

} else

554

} else

559

reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;

555

reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;

560

556

561

if (!sky2->tx_pause && !sky2->rx_pause) {

557

if (!sky2->tx_pause && !sky2->rx_pause) {

562

sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);

558

sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);

563

reg |=

559

reg |=

564

GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;

560

GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;

565

} else if (sky2->tx_pause && !sky2->rx_pause) {

561

} else if (sky2->tx_pause && !sky2->rx_pause) {

566

/* disable Rx flow-control */

562

/* disable Rx flow-control */

567

reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;

563

reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;

568

}

564

}

569

565

570

gma_write16(hw, port, GM_GP_CTRL, reg);

566

gma_write16(hw, port, GM_GP_CTRL, reg);

571

567

572

sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));

568

sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));

573

569

574

down(&sky2->phy_sema);

570

down(&sky2->phy_sema);

575

sky2_phy_init(hw, port);

571

sky2_phy_init(hw, port);

576

up(&sky2->phy_sema);

572

up(&sky2->phy_sema);

577

573

578

/* MIB clear */

574

/* MIB clear */

579

reg = gma_read16(hw, port, GM_PHY_ADDR);

575

reg = gma_read16(hw, port, GM_PHY_ADDR);

580

gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);

576

gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);

581

577

582

for (i = 0; i < GM_MIB_CNT_SIZE; i++)

578

for (i = 0; i < GM_MIB_CNT_SIZE; i++)

583

gma_read16(hw, port, GM_MIB_CNT_BASE + 8 * i);

579

gma_read16(hw, port, GM_MIB_CNT_BASE + 8 * i);

584

gma_write16(hw, port, GM_PHY_ADDR, reg);

580

gma_write16(hw, port, GM_PHY_ADDR, reg);

585

581

586

/* transmit control */

582

/* transmit control */

587

gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));

583

gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));

588

584

589

/* receive control reg: unicast + multicast + no FCS */

585

/* receive control reg: unicast + multicast + no FCS */

590

gma_write16(hw, port, GM_RX_CTRL,

586

gma_write16(hw, port, GM_RX_CTRL,

591

GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);

587

GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);

592

588

593

/* transmit flow control */

589

/* transmit flow control */

594

gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);

590

gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);

595

591

596

/* transmit parameter */

592

/* transmit parameter */

597

gma_write16(hw, port, GM_TX_PARAM,

593

gma_write16(hw, port, GM_TX_PARAM,

598

TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |

594

TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |

599

TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |

595

TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |

600

TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |

596

TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |

601

TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));

597

TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));

602

598

603

/* serial mode register */

599

/* serial mode register */

604

reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |

600

reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |

605

GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);

601

GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);

606

602

607

if (hw->dev[port]->mtu > ETH_DATA_LEN)

603

if (hw->dev[port]->mtu > ETH_DATA_LEN)

608

reg |= GM_SMOD_JUMBO_ENA;

604

reg |= GM_SMOD_JUMBO_ENA;

609

605

610

gma_write16(hw, port, GM_SERIAL_MODE, reg);

606

gma_write16(hw, port, GM_SERIAL_MODE, reg);

611

607

612

/* virtual address for data */

608

/* virtual address for data */

613

gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);

609

gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);

614

610

615

/* physical address: used for pause frames */

611

/* physical address: used for pause frames */

616

gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);

612

gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);

617

613

618

/* ignore counter overflows */

614

/* ignore counter overflows */

619

gma_write16(hw, port, GM_TX_IRQ_MSK, 0);

615

gma_write16(hw, port, GM_TX_IRQ_MSK, 0);

620

gma_write16(hw, port, GM_RX_IRQ_MSK, 0);

616

gma_write16(hw, port, GM_RX_IRQ_MSK, 0);

621

gma_write16(hw, port, GM_TR_IRQ_MSK, 0);

617

gma_write16(hw, port, GM_TR_IRQ_MSK, 0);

622

618

623

/* Configure Rx MAC FIFO */

619

/* Configure Rx MAC FIFO */

624

sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);

620

sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);

625

sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),

621

sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),

626

GMF_OPER_ON | GMF_RX_F_FL_ON);

622

GMF_OPER_ON | GMF_RX_F_FL_ON);

627

623

628

/* Flush Rx MAC FIFO on any flow control or error */

624

/* Flush Rx MAC FIFO on any flow control or error */

629

sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);

625

sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);

630

626

631

/* Set threshold to 0xa (64 bytes)

627

/* Set threshold to 0xa (64 bytes)

632

* ASF disabled so no need to do WA dev #4.30

628

* ASF disabled so no need to do WA dev #4.30

633

*/

629

*/

634

sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);

630

sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);

635

631

636

/* Configure Tx MAC FIFO */

632

/* Configure Tx MAC FIFO */

637

sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);

633

sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);

638

sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);

634

sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);

639

635

640

if (hw->chip_id == CHIP_ID_YUKON_EC_U) {

636

if (hw->chip_id == CHIP_ID_YUKON_EC_U) {

641

sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);

637

sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);

642

sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);

638

sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);

643

if (hw->dev[port]->mtu > ETH_DATA_LEN) {

639

if (hw->dev[port]->mtu > ETH_DATA_LEN) {

644

/* set Tx GMAC FIFO Almost Empty Threshold */

640

/* set Tx GMAC FIFO Almost Empty Threshold */

645

sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);

641

sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);

646

/* Disable Store & Forward mode for TX */

642

/* Disable Store & Forward mode for TX */

647

sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);

643

sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);

648

}

644

}

649

}

645

}

650

646

651

}

647

}

652

648

653

/* Assign Ram Buffer allocation.

649

/* Assign Ram Buffer allocation.

654

* start and end are in units of 4k bytes

650

* start and end are in units of 4k bytes

655

* ram registers are in units of 64bit words

651

* ram registers are in units of 64bit words

656

*/

652

*/

657

static void sky2_ramset(struct sky2_hw *hw, u16 q, u8 startk, u8 endk)

653

static void sky2_ramset(struct sky2_hw *hw, u16 q, u8 startk, u8 endk)

658

{

654

{

659

u32 start, end;

655

u32 start, end;

660

656

661

start = startk * 4096/8;

657

start = startk * 4096/8;

662

end = (endk * 4096/8) - 1;

658

end = (endk * 4096/8) - 1;

663

659

664

sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);

660

sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);

665

sky2_write32(hw, RB_ADDR(q, RB_START), start);

661

sky2_write32(hw, RB_ADDR(q, RB_START), start);

666

sky2_write32(hw, RB_ADDR(q, RB_END), end);

662

sky2_write32(hw, RB_ADDR(q, RB_END), end);

667

sky2_write32(hw, RB_ADDR(q, RB_WP), start);

663

sky2_write32(hw, RB_ADDR(q, RB_WP), start);

668

sky2_write32(hw, RB_ADDR(q, RB_RP), start);

664

sky2_write32(hw, RB_ADDR(q, RB_RP), start);

669

665

670

if (q == Q_R1 || q == Q_R2) {

666

if (q == Q_R1 || q == Q_R2) {

671

u32 space = (endk - startk) * 4096/8;

667

u32 space = (endk - startk) * 4096/8;

672

u32 tp = space - space/4;

668

u32 tp = space - space/4;

673

669

674

/* On receive queue's set the thresholds

670

/* On receive queue's set the thresholds

675

* give receiver priority when > 3/4 full

671

* give receiver priority when > 3/4 full

676

* send pause when down to 2K

672

* send pause when down to 2K

677

*/

673

*/

678

sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);

674

sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);

679

sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);

675

sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);

680

676

681

tp = space - 2048/8;

677

tp = space - 2048/8;

682

sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);

678

sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);

683

sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);

679

sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);

684

} else {

680

} else {

685

/* Enable store & forward on Tx queue's because

681

/* Enable store & forward on Tx queue's because

686

* Tx FIFO is only 1K on Yukon

682

* Tx FIFO is only 1K on Yukon

687

*/

683

*/

688

sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);

684

sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);

689

}

685

}

690

686

691

sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);

687

sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);

692

sky2_read8(hw, RB_ADDR(q, RB_CTRL));

688

sky2_read8(hw, RB_ADDR(q, RB_CTRL));

693

}

689

}

694

690

695

/* Setup Bus Memory Interface */

691

/* Setup Bus Memory Interface */

696

static void sky2_qset(struct sky2_hw *hw, u16 q)

692

static void sky2_qset(struct sky2_hw *hw, u16 q)

697

{

693

{

698

sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);

694

sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);

699

sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);

695

sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);

700

sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);

696

sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);

701

sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);

697

sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);

702

}

698

}

703

699

704

/* Setup prefetch unit registers. This is the interface between

700

/* Setup prefetch unit registers. This is the interface between

705

* hardware and driver list elements

701

* hardware and driver list elements

706

*/

702

*/

707

static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,

703

static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,

708

u64 addr, u32 last)

704

u64 addr, u32 last)

709

{

705

{

710

sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);

706

sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);

711

sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);

707

sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);

712

sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);

708

sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);

713

sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);

709

sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);

714

sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);

710

sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);

715

sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);

711

sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);

716

712

717

sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));

713

sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));

718

}

714

}

719

715

720

static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)

716

static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)

721

{

717

{

722

struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;

718

struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;

723

719

724

sky2->tx_prod = (sky2->tx_prod + 1) % TX_RING_SIZE;

720

sky2->tx_prod = (sky2->tx_prod + 1) % TX_RING_SIZE;

725

return le;

721

return le;

726

}

722

}

727

723

728

/*

724

/* Update chip's next pointer */

729

* This is a workaround code taken from SysKonnect sk98lin driver

725

static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)

730

* to deal with chip bug on Yukon EC rev 0 in the wraparound case.

731

*/

732

static void sky2_put_idx(struct sky2_hw *hw, unsigned q,

733

u16 idx, u16 *last, u16 size)

734

{

726

{

735

wmb();

727

wmb();

736

if (is_ec_a1(hw) && idx < *last) {

728

sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);

737

u16 hwget = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));

738

739

if (hwget == 0) {

740

/* Start prefetching again */

741

sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 0xe0);

742

goto setnew;

743

}

744

745

if (hwget == size - 1) {

746

/* set watermark to one list element */

747

sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 8);

748

749

/* set put index to first list element */

750

sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), 0);

751

} else /* have hardware go to end of list */

752

sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX),

753

size - 1);

754

} else {

755

setnew:

756

sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);

757

}

758

*last = idx;

759

mmiowb();

729

mmiowb();

760

}

730

}

761

731

762

732

763

static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)

733

static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)

764

{

734

{

765

struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;

735

struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;

766

sky2->rx_put = (sky2->rx_put + 1) % RX_LE_SIZE;

736

sky2->rx_put = (sky2->rx_put + 1) % RX_LE_SIZE;

767

return le;

737

return le;

768

}

738

}

769

739

770

/* Return high part of DMA address (could be 32 or 64 bit) */

740

/* Return high part of DMA address (could be 32 or 64 bit) */

771

static inline u32 high32(dma_addr_t a)

741

static inline u32 high32(dma_addr_t a)

772

{

742

{

773

return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;

743

return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;

774

}

744

}

775

745

776

/* Build description to hardware about buffer */

746

/* Build description to hardware about buffer */

777

static void sky2_rx_add(struct sky2_port *sky2, dma_addr_t map)

747

static void sky2_rx_add(struct sky2_port *sky2, dma_addr_t map)

778

{

748

{

779

struct sky2_rx_le *le;

749

struct sky2_rx_le *le;

780

u32 hi = high32(map);

750

u32 hi = high32(map);

781

u16 len = sky2->rx_bufsize;

751

u16 len = sky2->rx_bufsize;

782

752

783

if (sky2->rx_addr64 != hi) {

753

if (sky2->rx_addr64 != hi) {

784

le = sky2_next_rx(sky2);

754

le = sky2_next_rx(sky2);

785

le->addr = cpu_to_le32(hi);

755

le->addr = cpu_to_le32(hi);

786

le->ctrl = 0;

756

le->ctrl = 0;

787

le->opcode = OP_ADDR64 | HW_OWNER;

757

le->opcode = OP_ADDR64 | HW_OWNER;

788

sky2->rx_addr64 = high32(map + len);

758

sky2->rx_addr64 = high32(map + len);

789

}

759

}

790

760

791

le = sky2_next_rx(sky2);

761

le = sky2_next_rx(sky2);

792

le->addr = cpu_to_le32((u32) map);

762

le->addr = cpu_to_le32((u32) map);

793

le->length = cpu_to_le16(len);

763

le->length = cpu_to_le16(len);

794

le->ctrl = 0;

764

le->ctrl = 0;

795

le->opcode = OP_PACKET | HW_OWNER;

765

le->opcode = OP_PACKET | HW_OWNER;

796

}

766

}

797

767

798

768

799

/* Tell chip where to start receive checksum.

769

/* Tell chip where to start receive checksum.

800

* Actually has two checksums, but set both same to avoid possible byte

770

* Actually has two checksums, but set both same to avoid possible byte

801

* order problems.

771

* order problems.

802

*/

772

*/

803

static void rx_set_checksum(struct sky2_port *sky2)

773

static void rx_set_checksum(struct sky2_port *sky2)

804

{

774

{

805

struct sky2_rx_le *le;

775

struct sky2_rx_le *le;

806

776

807

le = sky2_next_rx(sky2);

777

le = sky2_next_rx(sky2);

808

le->addr = (ETH_HLEN << 16) | ETH_HLEN;

778

le->addr = (ETH_HLEN << 16) | ETH_HLEN;

809

le->ctrl = 0;

779

le->ctrl = 0;

810

le->opcode = OP_TCPSTART | HW_OWNER;

780

le->opcode = OP_TCPSTART | HW_OWNER;

811

781

812

sky2_write32(sky2->hw,

782

sky2_write32(sky2->hw,

813

Q_ADDR(rxqaddr[sky2->port], Q_CSR),

783

Q_ADDR(rxqaddr[sky2->port], Q_CSR),

814

sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);

784

sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);

815

785

816

}

786

}

817

787

818

/*

788

/*

819

* The RX Stop command will not work for Yukon-2 if the BMU does not

789

* The RX Stop command will not work for Yukon-2 if the BMU does not

820

* reach the end of packet and since we can't make sure that we have

790

* reach the end of packet and since we can't make sure that we have

821

* incoming data, we must reset the BMU while it is not doing a DMA

791

* incoming data, we must reset the BMU while it is not doing a DMA

822

* transfer. Since it is possible that the RX path is still active,

792

* transfer. Since it is possible that the RX path is still active,

823

* the RX RAM buffer will be stopped first, so any possible incoming

793

* the RX RAM buffer will be stopped first, so any possible incoming

824

* data will not trigger a DMA. After the RAM buffer is stopped, the

794

* data will not trigger a DMA. After the RAM buffer is stopped, the

825

* BMU is polled until any DMA in progress is ended and only then it

795

* BMU is polled until any DMA in progress is ended and only then it

826

* will be reset.

796

* will be reset.

827

*/

797

*/

828

static void sky2_rx_stop(struct sky2_port *sky2)

798

static void sky2_rx_stop(struct sky2_port *sky2)

829

{

799

{

830

struct sky2_hw *hw = sky2->hw;

800

struct sky2_hw *hw = sky2->hw;

831

unsigned rxq = rxqaddr[sky2->port];

801

unsigned rxq = rxqaddr[sky2->port];

832

int i;

802

int i;

833

803

834

/* disable the RAM Buffer receive queue */

804

/* disable the RAM Buffer receive queue */

835

sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);

805

sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);

836

806

837

for (i = 0; i < 0xffff; i++)

807

for (i = 0; i < 0xffff; i++)

838

if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))

808

if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))

839

== sky2_read8(hw, RB_ADDR(rxq, Q_RL)))

809

== sky2_read8(hw, RB_ADDR(rxq, Q_RL)))

840

goto stopped;

810

goto stopped;

841

811

842

printk(KERN_WARNING PFX "%s: receiver stop failed\n",

812

printk(KERN_WARNING PFX "%s: receiver stop failed\n",

843

sky2->netdev->name);

813

sky2->netdev->name);

844

stopped:

814

stopped:

845

sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);

815

sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);

846

816

847

/* reset the Rx prefetch unit */

817

/* reset the Rx prefetch unit */

848

sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);

818

sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);

849

}

819

}

850

820

851

/* Clean out receive buffer area, assumes receiver hardware stopped */

821

/* Clean out receive buffer area, assumes receiver hardware stopped */

852

static void sky2_rx_clean(struct sky2_port *sky2)

822

static void sky2_rx_clean(struct sky2_port *sky2)

853

{

823

{

854

unsigned i;

824

unsigned i;

855

825

856

memset(sky2->rx_le, 0, RX_LE_BYTES);

826

memset(sky2->rx_le, 0, RX_LE_BYTES);

857

for (i = 0; i < sky2->rx_pending; i++) {

827

for (i = 0; i < sky2->rx_pending; i++) {

858

struct ring_info *re = sky2->rx_ring + i;

828

struct ring_info *re = sky2->rx_ring + i;

859

829

860

if (re->skb) {

830

if (re->skb) {

861

pci_unmap_single(sky2->hw->pdev,

831

pci_unmap_single(sky2->hw->pdev,

862

re->mapaddr, sky2->rx_bufsize,

832

re->mapaddr, sky2->rx_bufsize,

863

PCI_DMA_FROMDEVICE);

833

PCI_DMA_FROMDEVICE);

864

kfree_skb(re->skb);

834

kfree_skb(re->skb);

865

re->skb = NULL;

835

re->skb = NULL;

866

}

836

}

867

}

837

}

868

}

838

}

869

839

870

/* Basic MII support */

840

/* Basic MII support */

871

static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)

841

static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)

872

{

842

{

873

struct mii_ioctl_data *data = if_mii(ifr);

843

struct mii_ioctl_data *data = if_mii(ifr);

874

struct sky2_port *sky2 = netdev_priv(dev);

844

struct sky2_port *sky2 = netdev_priv(dev);

875

struct sky2_hw *hw = sky2->hw;

845

struct sky2_hw *hw = sky2->hw;

876

int err = -EOPNOTSUPP;

846

int err = -EOPNOTSUPP;

877

847

878

if (!netif_running(dev))

848

if (!netif_running(dev))

879

return -ENODEV; /* Phy still in reset */

849

return -ENODEV; /* Phy still in reset */

880

850

881

switch(cmd) {

851

switch(cmd) {

882

case SIOCGMIIPHY:

852

case SIOCGMIIPHY:

883

data->phy_id = PHY_ADDR_MARV;

853

data->phy_id = PHY_ADDR_MARV;

884

854

885

/* fallthru */

855

/* fallthru */

886

case SIOCGMIIREG: {

856

case SIOCGMIIREG: {

887

u16 val = 0;

857

u16 val = 0;

888

858

889

down(&sky2->phy_sema);

859

down(&sky2->phy_sema);

890

err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);

860

err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);

891

up(&sky2->phy_sema);

861

up(&sky2->phy_sema);

892

862

893

data->val_out = val;

863

data->val_out = val;

894

break;

864

break;

895

}

865

}

896

866

897

case SIOCSMIIREG:

867

case SIOCSMIIREG:

898

if (!capable(CAP_NET_ADMIN))

868

if (!capable(CAP_NET_ADMIN))

899

return -EPERM;

869

return -EPERM;

900

870

901

down(&sky2->phy_sema);

871

down(&sky2->phy_sema);

902

err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,

872

err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,

903

data->val_in);

873

data->val_in);

904

up(&sky2->phy_sema);

874

up(&sky2->phy_sema);

905

break;

875

break;

906

}

876

}

907

return err;

877

return err;

908

}

878

}

909

879

910

#ifdef SKY2_VLAN_TAG_USED

880

#ifdef SKY2_VLAN_TAG_USED

911

static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)

881

static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)

912

{

882

{

913

struct sky2_port *sky2 = netdev_priv(dev);

883

struct sky2_port *sky2 = netdev_priv(dev);

914

struct sky2_hw *hw = sky2->hw;

884

struct sky2_hw *hw = sky2->hw;

915

u16 port = sky2->port;

885

u16 port = sky2->port;

916

886

917

spin_lock_bh(&sky2->tx_lock);

887

spin_lock_bh(&sky2->tx_lock);

918

888

919

sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);

889

sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);

920

sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);

890

sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);

921

sky2->vlgrp = grp;

891

sky2->vlgrp = grp;

922

892

923

spin_unlock_bh(&sky2->tx_lock);

893

spin_unlock_bh(&sky2->tx_lock);

924

}

894

}

925

895

926

static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)

896

static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)

927

{

897

{

928

struct sky2_port *sky2 = netdev_priv(dev);

898

struct sky2_port *sky2 = netdev_priv(dev);

929

struct sky2_hw *hw = sky2->hw;

899

struct sky2_hw *hw = sky2->hw;

930

u16 port = sky2->port;

900

u16 port = sky2->port;

931

901

932

spin_lock_bh(&sky2->tx_lock);

902

spin_lock_bh(&sky2->tx_lock);

933

903

934

sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);

904

sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);

935

sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);

905

sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);

936

if (sky2->vlgrp)

906

if (sky2->vlgrp)

937

sky2->vlgrp->vlan_devices[vid] = NULL;

907

sky2->vlgrp->vlan_devices[vid] = NULL;

938

908

939

spin_unlock_bh(&sky2->tx_lock);

909

spin_unlock_bh(&sky2->tx_lock);

940

}

910

}

941

#endif

911

#endif

942

912

943

/*

913

/*

944

* It appears the hardware has a bug in the FIFO logic that

914

* It appears the hardware has a bug in the FIFO logic that

945

* cause it to hang if the FIFO gets overrun and the receive buffer

915

* cause it to hang if the FIFO gets overrun and the receive buffer

946

* is not aligned. ALso alloc_skb() won't align properly if slab

916

* is not aligned. ALso alloc_skb() won't align properly if slab

947

* debugging is enabled.

917

* debugging is enabled.

948

*/

918

*/

949

static inline struct sk_buff *sky2_alloc_skb(unsigned int size, gfp_t gfp_mask)

919

static inline struct sk_buff *sky2_alloc_skb(unsigned int size, gfp_t gfp_mask)

950

{

920

{

951

struct sk_buff *skb;

921

struct sk_buff *skb;

952

922

953

skb = alloc_skb(size + RX_SKB_ALIGN, gfp_mask);

923

skb = alloc_skb(size + RX_SKB_ALIGN, gfp_mask);

954

if (likely(skb)) {

924

if (likely(skb)) {

955

unsigned long p = (unsigned long) skb->data;

925

unsigned long p = (unsigned long) skb->data;

956

skb_reserve(skb,

926

skb_reserve(skb,

957

((p + RX_SKB_ALIGN - 1) & ~(RX_SKB_ALIGN - 1)) - p);

927

((p + RX_SKB_ALIGN - 1) & ~(RX_SKB_ALIGN - 1)) - p);

958

}

928

}

959

929

960

return skb;

930

return skb;

961

}

931

}

962

932

963

/*

933

/*

964

* Allocate and setup receiver buffer pool.

934

* Allocate and setup receiver buffer pool.

965

* In case of 64 bit dma, there are 2X as many list elements

935

* In case of 64 bit dma, there are 2X as many list elements

966

* available as ring entries

936

* available as ring entries

967

* and need to reserve one list element so we don't wrap around.

937

* and need to reserve one list element so we don't wrap around.

968

*/

938

*/

969

static int sky2_rx_start(struct sky2_port *sky2)

939

static int sky2_rx_start(struct sky2_port *sky2)

970

{

940

{

971

struct sky2_hw *hw = sky2->hw;

941

struct sky2_hw *hw = sky2->hw;

972

unsigned rxq = rxqaddr[sky2->port];

942

unsigned rxq = rxqaddr[sky2->port];

973

int i;

943

int i;

974

944

975

sky2->rx_put = sky2->rx_next = 0;

945

sky2->rx_put = sky2->rx_next = 0;

976

sky2_qset(hw, rxq);

946

sky2_qset(hw, rxq);

977

947

978

if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {

948

if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {

979

/* MAC Rx RAM Read is controlled by hardware */

949

/* MAC Rx RAM Read is controlled by hardware */

980

sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);

950

sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);

981

}

951

}

982

952

983

sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);

953

sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);

984

954

985

rx_set_checksum(sky2);

955

rx_set_checksum(sky2);

986

for (i = 0; i < sky2->rx_pending; i++) {

956

for (i = 0; i < sky2->rx_pending; i++) {

987

struct ring_info *re = sky2->rx_ring + i;

957

struct ring_info *re = sky2->rx_ring + i;

988

958

989

re->skb = sky2_alloc_skb(sky2->rx_bufsize, GFP_KERNEL);

959

re->skb = sky2_alloc_skb(sky2->rx_bufsize, GFP_KERNEL);

990

if (!re->skb)

960

if (!re->skb)

991

goto nomem;

961

goto nomem;

992

962

993

re->mapaddr = pci_map_single(hw->pdev, re->skb->data,

963

re->mapaddr = pci_map_single(hw->pdev, re->skb->data,

994

sky2->rx_bufsize, PCI_DMA_FROMDEVICE);

964

sky2->rx_bufsize, PCI_DMA_FROMDEVICE);

995

sky2_rx_add(sky2, re->mapaddr);

965

sky2_rx_add(sky2, re->mapaddr);

996

}

966

}

997

967

998

/* Truncate oversize frames */

968

/* Truncate oversize frames */

999

sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), sky2->rx_bufsize - 8);

969

sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), sky2->rx_bufsize - 8);

1000

sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);

970

sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);

1001

971

1002

/* Tell chip about available buffers */

972

/* Tell chip about available buffers */

1003

sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);

973

sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);

1004

sky2->rx_last_put = sky2_read16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX));

1005

return 0;

974

return 0;

1006

nomem:

975

nomem:

1007

sky2_rx_clean(sky2);

976

sky2_rx_clean(sky2);

1008

return -ENOMEM;

977

return -ENOMEM;

1009

}

978

}

1010

979

1011

/* Bring up network interface. */

980

/* Bring up network interface. */

1012

static int sky2_up(struct net_device *dev)

981

static int sky2_up(struct net_device *dev)

1013

{

982

{

1014

struct sky2_port *sky2 = netdev_priv(dev);

983

struct sky2_port *sky2 = netdev_priv(dev);

1015

struct sky2_hw *hw = sky2->hw;

984

struct sky2_hw *hw = sky2->hw;

1016

unsigned port = sky2->port;

985

unsigned port = sky2->port;

1017

u32 ramsize, rxspace;

986

u32 ramsize, rxspace;

1018

int err = -ENOMEM;

987

int err = -ENOMEM;

1019

988

1020

if (netif_msg_ifup(sky2))

989

if (netif_msg_ifup(sky2))

1021

printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);

990

printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);

1022

991

1023

/* must be power of 2 */

992

/* must be power of 2 */

1024

sky2->tx_le = pci_alloc_consistent(hw->pdev,

993

sky2->tx_le = pci_alloc_consistent(hw->pdev,

1025

TX_RING_SIZE *

994

TX_RING_SIZE *

1026

sizeof(struct sky2_tx_le),

995

sizeof(struct sky2_tx_le),

1027

&sky2->tx_le_map);

996

&sky2->tx_le_map);

1028

if (!sky2->tx_le)

997

if (!sky2->tx_le)

1029

goto err_out;

998

goto err_out;

1030

999

1031

sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),

1000

sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),

1032

GFP_KERNEL);

1001

GFP_KERNEL);

1033

if (!sky2->tx_ring)

1002

if (!sky2->tx_ring)

1034

goto err_out;

1003

goto err_out;

1035

sky2->tx_prod = sky2->tx_cons = 0;

1004

sky2->tx_prod = sky2->tx_cons = 0;

1036

1005

1037

sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,

1006

sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,

1038

&sky2->rx_le_map);

1007

&sky2->rx_le_map);

1039

if (!sky2->rx_le)

1008

if (!sky2->rx_le)

1040

goto err_out;

1009

goto err_out;

1041

memset(sky2->rx_le, 0, RX_LE_BYTES);

1010

memset(sky2->rx_le, 0, RX_LE_BYTES);

1042

1011

1043

sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct ring_info),

1012

sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct ring_info),

1044

GFP_KERNEL);

1013

GFP_KERNEL);

1045

if (!sky2->rx_ring)

1014

if (!sky2->rx_ring)

1046

goto err_out;

1015

goto err_out;

1047

1016

1048

sky2_mac_init(hw, port);

1017

sky2_mac_init(hw, port);

1049

1018

1050

/* Determine available ram buffer space (in 4K blocks).

1019

/* Determine available ram buffer space (in 4K blocks).

1051

* Note: not sure about the FE setting below yet

1020

* Note: not sure about the FE setting below yet

1052

*/

1021

*/

1053

if (hw->chip_id == CHIP_ID_YUKON_FE)

1022

if (hw->chip_id == CHIP_ID_YUKON_FE)

1054

ramsize = 4;

1023

ramsize = 4;

1055

else

1024

else

1056

ramsize = sky2_read8(hw, B2_E_0);

1025

ramsize = sky2_read8(hw, B2_E_0);

1057

1026

1058

/* Give transmitter one third (rounded up) */

1027

/* Give transmitter one third (rounded up) */

1059

rxspace = ramsize - (ramsize + 2) / 3;

1028

rxspace = ramsize - (ramsize + 2) / 3;

1060

1029

1061

sky2_ramset(hw, rxqaddr[port], 0, rxspace);

1030

sky2_ramset(hw, rxqaddr[port], 0, rxspace);

1062

sky2_ramset(hw, txqaddr[port], rxspace, ramsize);

1031

sky2_ramset(hw, txqaddr[port], rxspace, ramsize);

1063

1032

1064

/* Make sure SyncQ is disabled */

1033

/* Make sure SyncQ is disabled */

1065

sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),

1034

sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),

1066

RB_RST_SET);

1035

RB_RST_SET);

1067

1036

1068

sky2_qset(hw, txqaddr[port]);

1037

sky2_qset(hw, txqaddr[port]);

1069

1038

1070

/* Set almost empty threshold */

1039

/* Set almost empty threshold */

1071

if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == 1)

1040

if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == 1)

1072

sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);

1041

sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);

1073

1042

1074

sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,

1043

sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,

1075

TX_RING_SIZE - 1);

1044

TX_RING_SIZE - 1);

1076

1045

1077

err = sky2_rx_start(sky2);

1046

err = sky2_rx_start(sky2);

1078

if (err)

1047

if (err)

1079

goto err_out;

1048

goto err_out;

1080

1049

1081

/* Enable interrupts from phy/mac for port */

1050

/* Enable interrupts from phy/mac for port */

1082

spin_lock_irq(&hw->hw_lock);

1051

spin_lock_irq(&hw->hw_lock);

1083

hw->intr_mask |= (port == 0) ? Y2_IS_PORT_1 : Y2_IS_PORT_2;

1052

hw->intr_mask |= (port == 0) ? Y2_IS_PORT_1 : Y2_IS_PORT_2;

1084

sky2_write32(hw, B0_IMSK, hw->intr_mask);

1053

sky2_write32(hw, B0_IMSK, hw->intr_mask);

1085

spin_unlock_irq(&hw->hw_lock);

1054

spin_unlock_irq(&hw->hw_lock);

1086

return 0;

1055

return 0;

1087

1056

1088

err_out:

1057

err_out:

1089

if (sky2->rx_le) {

1058

if (sky2->rx_le) {

1090

pci_free_consistent(hw->pdev, RX_LE_BYTES,

1059

pci_free_consistent(hw->pdev, RX_LE_BYTES,

1091

sky2->rx_le, sky2->rx_le_map);

1060

sky2->rx_le, sky2->rx_le_map);

1092

sky2->rx_le = NULL;

1061

sky2->rx_le = NULL;

1093

}

1062

}

1094

if (sky2->tx_le) {

1063

if (sky2->tx_le) {

1095

pci_free_consistent(hw->pdev,

1064

pci_free_consistent(hw->pdev,

1096

TX_RING_SIZE * sizeof(struct sky2_tx_le),

1065

TX_RING_SIZE * sizeof(struct sky2_tx_le),

1097

sky2->tx_le, sky2->tx_le_map);

1066

sky2->tx_le, sky2->tx_le_map);

1098

sky2->tx_le = NULL;

1067

sky2->tx_le = NULL;

1099

}

1068

}

1100

kfree(sky2->tx_ring);

1069

kfree(sky2->tx_ring);

1101

kfree(sky2->rx_ring);

1070

kfree(sky2->rx_ring);

1102

1071

1103

sky2->tx_ring = NULL;

1072

sky2->tx_ring = NULL;

1104

sky2->rx_ring = NULL;

1073

sky2->rx_ring = NULL;

1105

return err;

1074

return err;

1106

}

1075

}

1107

1076

1108

/* Modular subtraction in ring */

1077

/* Modular subtraction in ring */

1109

static inline int tx_dist(unsigned tail, unsigned head)

1078

static inline int tx_dist(unsigned tail, unsigned head)

1110

{

1079

{

1111

return (head - tail) % TX_RING_SIZE;

1080

return (head - tail) % TX_RING_SIZE;

1112

}

1081

}

1113

1082

1114

/* Number of list elements available for next tx */

1083

/* Number of list elements available for next tx */

1115

static inline int tx_avail(const struct sky2_port *sky2)

1084

static inline int tx_avail(const struct sky2_port *sky2)

1116

{

1085

{

1117

return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);

1086

return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);

1118

}

1087

}

1119

1088

1120

/* Estimate of number of transmit list elements required */

1089

/* Estimate of number of transmit list elements required */

1121

static unsigned tx_le_req(const struct sk_buff *skb)

1090

static unsigned tx_le_req(const struct sk_buff *skb)

1122

{

1091

{

1123

unsigned count;

1092

unsigned count;

1124

1093

1125

count = sizeof(dma_addr_t) / sizeof(u32);

1094

count = sizeof(dma_addr_t) / sizeof(u32);

1126

count += skb_shinfo(skb)->nr_frags * count;

1095

count += skb_shinfo(skb)->nr_frags * count;

1127

1096

1128

if (skb_shinfo(skb)->tso_size)

1097

if (skb_shinfo(skb)->tso_size)

1129

++count;

1098

++count;

1130

1099

1131

if (skb->ip_summed == CHECKSUM_HW)

1100

if (skb->ip_summed == CHECKSUM_HW)

1132

++count;

1101

++count;

1133

1102

1134

return count;

1103

return count;

1135

}

1104

}

1136

1105

1137

/*

1106

/*

1138

* Put one packet in ring for transmit.

1107

* Put one packet in ring for transmit.

1139

* A single packet can generate multiple list elements, and

1108

* A single packet can generate multiple list elements, and

1140

* the number of ring elements will probably be less than the number

1109

* the number of ring elements will probably be less than the number

1141

* of list elements used.

1110

* of list elements used.

1142

*

1111

*

1143

* No BH disabling for tx_lock here (like tg3)

1112

* No BH disabling for tx_lock here (like tg3)

1144

*/

1113

*/

1145

static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)

1114

static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)

1146

{

1115

{

1147

struct sky2_port *sky2 = netdev_priv(dev);

1116

struct sky2_port *sky2 = netdev_priv(dev);

1148

struct sky2_hw *hw = sky2->hw;

1117

struct sky2_hw *hw = sky2->hw;

1149

struct sky2_tx_le *le = NULL;

1118

struct sky2_tx_le *le = NULL;

1150

struct tx_ring_info *re;

1119

struct tx_ring_info *re;

1151

unsigned i, len;

1120

unsigned i, len;

1152

int avail;

1121

int avail;

1153

dma_addr_t mapping;

1122

dma_addr_t mapping;

1154

u32 addr64;

1123

u32 addr64;

1155

u16 mss;

1124

u16 mss;

1156

u8 ctrl;

1125

u8 ctrl;

1157

1126

1158

/* No BH disabling for tx_lock here. We are running in BH disabled

1127

/* No BH disabling for tx_lock here. We are running in BH disabled

1159

* context and TX reclaim runs via poll inside of a software

1128

* context and TX reclaim runs via poll inside of a software

1160

* interrupt, and no related locks in IRQ processing.

1129

* interrupt, and no related locks in IRQ processing.

1161

*/

1130

*/

1162

if (!spin_trylock(&sky2->tx_lock))

1131

if (!spin_trylock(&sky2->tx_lock))

1163

return NETDEV_TX_LOCKED;

1132

return NETDEV_TX_LOCKED;

1164

1133

1165

if (unlikely(tx_avail(sky2) < tx_le_req(skb))) {

1134

if (unlikely(tx_avail(sky2) < tx_le_req(skb))) {

1166

/* There is a known but harmless race with lockless tx

1135

/* There is a known but harmless race with lockless tx

1167

* and netif_stop_queue.

1136

* and netif_stop_queue.

1168

*/

1137

*/

1169

if (!netif_queue_stopped(dev)) {

1138

if (!netif_queue_stopped(dev)) {

1170

netif_stop_queue(dev);

1139

netif_stop_queue(dev);

1171

if (net_ratelimit())

1140

if (net_ratelimit())

1172

printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",

1141

printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",

1173

dev->name);

1142

dev->name);

1174

}

1143

}

1175

spin_unlock(&sky2->tx_lock);

1144

spin_unlock(&sky2->tx_lock);

1176

1145

1177

return NETDEV_TX_BUSY;

1146

return NETDEV_TX_BUSY;

1178

}

1147

}

1179

1148

1180

if (unlikely(netif_msg_tx_queued(sky2)))

1149

if (unlikely(netif_msg_tx_queued(sky2)))

1181

printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",

1150

printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",

1182

dev->name, sky2->tx_prod, skb->len);

1151

dev->name, sky2->tx_prod, skb->len);

1183

1152

1184

len = skb_headlen(skb);

1153

len = skb_headlen(skb);

1185

mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);

1154

mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);

1186

addr64 = high32(mapping);

1155

addr64 = high32(mapping);

1187

1156

1188

re = sky2->tx_ring + sky2->tx_prod;

1157

re = sky2->tx_ring + sky2->tx_prod;

1189

1158

1190

/* Send high bits if changed or crosses boundary */

1159

/* Send high bits if changed or crosses boundary */

1191

if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {

1160

if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {

1192

le = get_tx_le(sky2);

1161

le = get_tx_le(sky2);

1193

le->tx.addr = cpu_to_le32(addr64);

1162

le->tx.addr = cpu_to_le32(addr64);

1194

le->ctrl = 0;

1163

le->ctrl = 0;

1195

le->opcode = OP_ADDR64 | HW_OWNER;

1164

le->opcode = OP_ADDR64 | HW_OWNER;

1196

sky2->tx_addr64 = high32(mapping + len);

1165

sky2->tx_addr64 = high32(mapping + len);

1197

}

1166

}

1198

1167

1199

/* Check for TCP Segmentation Offload */

1168

/* Check for TCP Segmentation Offload */

1200

mss = skb_shinfo(skb)->tso_size;

1169

mss = skb_shinfo(skb)->tso_size;

1201

if (mss != 0) {

1170

if (mss != 0) {

1202

/* just drop the packet if non-linear expansion fails */

1171

/* just drop the packet if non-linear expansion fails */

1203

if (skb_header_cloned(skb) &&

1172

if (skb_header_cloned(skb) &&

1204

pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {

1173

pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {

1205

dev_kfree_skb_any(skb);

1174

dev_kfree_skb_any(skb);

1206

goto out_unlock;

1175

goto out_unlock;

1207

}

1176

}

1208

1177

1209

mss += ((skb->h.th->doff - 5) * 4); /* TCP options */

1178

mss += ((skb->h.th->doff - 5) * 4); /* TCP options */

1210

mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);

1179

mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);

1211

mss += ETH_HLEN;

1180

mss += ETH_HLEN;

1212

}

1181

}

1213

1182

1214

if (mss != sky2->tx_last_mss) {

1183

if (mss != sky2->tx_last_mss) {

1215

le = get_tx_le(sky2);

1184

le = get_tx_le(sky2);

1216

le->tx.tso.size = cpu_to_le16(mss);

1185

le->tx.tso.size = cpu_to_le16(mss);

1217

le->tx.tso.rsvd = 0;

1186

le->tx.tso.rsvd = 0;

1218

le->opcode = OP_LRGLEN | HW_OWNER;

1187

le->opcode = OP_LRGLEN | HW_OWNER;

1219

le->ctrl = 0;

1188

le->ctrl = 0;

1220

sky2->tx_last_mss = mss;

1189

sky2->tx_last_mss = mss;

1221

}

1190

}

1222

1191

1223

ctrl = 0;

1192

ctrl = 0;

1224

#ifdef SKY2_VLAN_TAG_USED

1193

#ifdef SKY2_VLAN_TAG_USED

1225

/* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */

1194

/* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */

1226

if (sky2->vlgrp && vlan_tx_tag_present(skb)) {

1195

if (sky2->vlgrp && vlan_tx_tag_present(skb)) {

1227

if (!le) {

1196

if (!le) {

1228

le = get_tx_le(sky2);

1197

le = get_tx_le(sky2);

1229

le->tx.addr = 0;

1198

le->tx.addr = 0;

1230

le->opcode = OP_VLAN|HW_OWNER;

1199

le->opcode = OP_VLAN|HW_OWNER;

1231

le->ctrl = 0;

1200

le->ctrl = 0;

1232

} else

1201

} else

1233

le->opcode |= OP_VLAN;

1202

le->opcode |= OP_VLAN;

1234

le->length = cpu_to_be16(vlan_tx_tag_get(skb));

1203

le->length = cpu_to_be16(vlan_tx_tag_get(skb));

1235

ctrl |= INS_VLAN;

1204

ctrl |= INS_VLAN;

1236

}

1205

}

1237

#endif

1206

#endif

1238

1207

1239

/* Handle TCP checksum offload */

1208

/* Handle TCP checksum offload */

1240

if (skb->ip_summed == CHECKSUM_HW) {

1209

if (skb->ip_summed == CHECKSUM_HW) {

1241

u16 hdr = skb->h.raw - skb->data;

1210

u16 hdr = skb->h.raw - skb->data;

1242

u16 offset = hdr + skb->csum;

1211

u16 offset = hdr + skb->csum;

1243

1212

1244

ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;

1213

ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;

1245

if (skb->nh.iph->protocol == IPPROTO_UDP)

1214

if (skb->nh.iph->protocol == IPPROTO_UDP)

1246

ctrl |= UDPTCP;

1215

ctrl |= UDPTCP;

1247

1216

1248

le = get_tx_le(sky2);

1217

le = get_tx_le(sky2);

1249

le->tx.csum.start = cpu_to_le16(hdr);

1218

le->tx.csum.start = cpu_to_le16(hdr);

1250

le->tx.csum.offset = cpu_to_le16(offset);

1219

le->tx.csum.offset = cpu_to_le16(offset);

1251

le->length = 0; /* initial checksum value */

1220

le->length = 0; /* initial checksum value */

1252

le->ctrl = 1; /* one packet */

1221

le->ctrl = 1; /* one packet */

1253

le->opcode = OP_TCPLISW | HW_OWNER;

1222

le->opcode = OP_TCPLISW | HW_OWNER;

1254

}

1223

}

1255

1224

1256

le = get_tx_le(sky2);

1225

le = get_tx_le(sky2);

1257

le->tx.addr = cpu_to_le32((u32) mapping);

1226

le->tx.addr = cpu_to_le32((u32) mapping);

1258

le->length = cpu_to_le16(len);

1227

le->length = cpu_to_le16(len);

1259

le->ctrl = ctrl;

1228

le->ctrl = ctrl;

1260

le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);

1229

le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);

1261

1230

1262

/* Record the transmit mapping info */

1231

/* Record the transmit mapping info */

1263

re->skb = skb;

1232

re->skb = skb;

1264

pci_unmap_addr_set(re, mapaddr, mapping);

1233

pci_unmap_addr_set(re, mapaddr, mapping);

1265

1234

1266

for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {

1235

for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {

1267

skb_frag_t *frag = &skb_shinfo(skb)->frags[i];

1236

skb_frag_t *frag = &skb_shinfo(skb)->frags[i];

1268

struct tx_ring_info *fre;

1237

struct tx_ring_info *fre;

1269

1238

1270

mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,

1239

mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,

1271

frag->size, PCI_DMA_TODEVICE);

1240

frag->size, PCI_DMA_TODEVICE);

1272

addr64 = high32(mapping);

1241

addr64 = high32(mapping);

1273

if (addr64 != sky2->tx_addr64) {

1242

if (addr64 != sky2->tx_addr64) {

1274

le = get_tx_le(sky2);

1243

le = get_tx_le(sky2);

1275

le->tx.addr = cpu_to_le32(addr64);

1244

le->tx.addr = cpu_to_le32(addr64);

1276

le->ctrl = 0;

1245

le->ctrl = 0;

1277

le->opcode = OP_ADDR64 | HW_OWNER;

1246

le->opcode = OP_ADDR64 | HW_OWNER;

1278

sky2->tx_addr64 = addr64;

1247

sky2->tx_addr64 = addr64;

1279

}

1248

}

1280

1249

1281

le = get_tx_le(sky2);

1250

le = get_tx_le(sky2);

1282

le->tx.addr = cpu_to_le32((u32) mapping);

1251

le->tx.addr = cpu_to_le32((u32) mapping);

1283

le->length = cpu_to_le16(frag->size);

1252

le->length = cpu_to_le16(frag->size);

1284

le->ctrl = ctrl;

1253

le->ctrl = ctrl;

1285

le->opcode = OP_BUFFER | HW_OWNER;

1254

le->opcode = OP_BUFFER | HW_OWNER;

1286

1255

1287

fre = sky2->tx_ring

1256

fre = sky2->tx_ring

1288

+ ((re - sky2->tx_ring) + i + 1) % TX_RING_SIZE;

1257

+ ((re - sky2->tx_ring) + i + 1) % TX_RING_SIZE;

1289

pci_unmap_addr_set(fre, mapaddr, mapping);

1258

pci_unmap_addr_set(fre, mapaddr, mapping);

1290

}

1259

}

1291

1260

1292

re->idx = sky2->tx_prod;

1261

re->idx = sky2->tx_prod;

1293

le->ctrl |= EOP;

1262

le->ctrl |= EOP;

1294

1263

1295

avail = tx_avail(sky2);

1264

avail = tx_avail(sky2);

1296

if (mss != 0 || avail < TX_MIN_PENDING) {

1265

if (mss != 0 || avail < TX_MIN_PENDING) {

1297

le->ctrl |= FRC_STAT;

1266

le->ctrl |= FRC_STAT;

1298

if (avail <= MAX_SKB_TX_LE)

1267

if (avail <= MAX_SKB_TX_LE)

1299

netif_stop_queue(dev);

1268

netif_stop_queue(dev);

1300

}

1269

}

1301

1270

1302

sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod,

1271

sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);

1303

&sky2->tx_last_put, TX_RING_SIZE);

1304

1272

1305

out_unlock:

1273

out_unlock:

1306

spin_unlock(&sky2->tx_lock);

1274

spin_unlock(&sky2->tx_lock);

1307

1275

1308

dev->trans_start = jiffies;

1276

dev->trans_start = jiffies;

1309

return NETDEV_TX_OK;

1277

return NETDEV_TX_OK;

1310

}

1278

}

1311

1279

1312

/*

1280

/*

1313

* Free ring elements from starting at tx_cons until "done"

1281

* Free ring elements from starting at tx_cons until "done"

1314

*

1282

*

1315

* NB: the hardware will tell us about partial completion of multi-part

1283

* NB: the hardware will tell us about partial completion of multi-part

1316

* buffers; these are deferred until completion.

1284

* buffers; these are deferred until completion.

1317

*/

1285

*/

1318

static void sky2_tx_complete(struct sky2_port *sky2, u16 done)

1286

static void sky2_tx_complete(struct sky2_port *sky2, u16 done)

1319

{

1287

{

1320

struct net_device *dev = sky2->netdev;

1288

struct net_device *dev = sky2->netdev;

1321

struct pci_dev *pdev = sky2->hw->pdev;

1289

struct pci_dev *pdev = sky2->hw->pdev;

1322

u16 nxt, put;

1290

u16 nxt, put;

1323

unsigned i;

1291

unsigned i;

1324

1292

1325

BUG_ON(done >= TX_RING_SIZE);

1293

BUG_ON(done >= TX_RING_SIZE);

1326

1294

1327

if (unlikely(netif_msg_tx_done(sky2)))

1295

if (unlikely(netif_msg_tx_done(sky2)))

1328

printk(KERN_DEBUG "%s: tx done, up to %u\n",

1296

printk(KERN_DEBUG "%s: tx done, up to %u\n",

1329

dev->name, done);

1297

dev->name, done);

1330

1298

1331

for (put = sky2->tx_cons; put != done; put = nxt) {

1299

for (put = sky2->tx_cons; put != done; put = nxt) {

1332

struct tx_ring_info *re = sky2->tx_ring + put;

1300

struct tx_ring_info *re = sky2->tx_ring + put;

1333

struct sk_buff *skb = re->skb;

1301

struct sk_buff *skb = re->skb;

1334

1302

1335

nxt = re->idx;

1303

nxt = re->idx;

1336

BUG_ON(nxt >= TX_RING_SIZE);

1304

BUG_ON(nxt >= TX_RING_SIZE);

1337

prefetch(sky2->tx_ring + nxt);

1305

prefetch(sky2->tx_ring + nxt);

1338

1306

1339

/* Check for partial status */

1307

/* Check for partial status */

1340

if (tx_dist(put, done) < tx_dist(put, nxt))

1308

if (tx_dist(put, done) < tx_dist(put, nxt))

1341

break;

1309

break;

1342

1310

1343

skb = re->skb;

1311

skb = re->skb;

1344

pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),

1312

pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),

1345

skb_headlen(skb), PCI_DMA_TODEVICE);

1313

skb_headlen(skb), PCI_DMA_TODEVICE);

1346

1314

1347

for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {

1315

for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {

1348

struct tx_ring_info *fre;

1316

struct tx_ring_info *fre;

1349

fre = sky2->tx_ring + (put + i + 1) % TX_RING_SIZE;

1317

fre = sky2->tx_ring + (put + i + 1) % TX_RING_SIZE;

1350

pci_unmap_page(pdev, pci_unmap_addr(fre, mapaddr),

1318

pci_unmap_page(pdev, pci_unmap_addr(fre, mapaddr),

1351

skb_shinfo(skb)->frags[i].size,

1319

skb_shinfo(skb)->frags[i].size,

1352

PCI_DMA_TODEVICE);

1320

PCI_DMA_TODEVICE);

1353

}

1321

}

1354

1322

1355

dev_kfree_skb_any(skb);

1323

dev_kfree_skb_any(skb);

1356

}

1324

}

1357

1325

1358

sky2->tx_cons = put;

1326

sky2->tx_cons = put;

1359

if (netif_queue_stopped(dev) && tx_avail(sky2) > MAX_SKB_TX_LE)

1327

if (netif_queue_stopped(dev) && tx_avail(sky2) > MAX_SKB_TX_LE)

1360

netif_wake_queue(dev);

1328

netif_wake_queue(dev);

1361

}

1329

}

1362

1330

1363

/* Cleanup all untransmitted buffers, assume transmitter not running */

1331

/* Cleanup all untransmitted buffers, assume transmitter not running */

1364

static void sky2_tx_clean(struct sky2_port *sky2)

1332

static void sky2_tx_clean(struct sky2_port *sky2)

1365

{

1333

{

1366

spin_lock_bh(&sky2->tx_lock);

1334

spin_lock_bh(&sky2->tx_lock);

1367

sky2_tx_complete(sky2, sky2->tx_prod);

1335

sky2_tx_complete(sky2, sky2->tx_prod);

1368

spin_unlock_bh(&sky2->tx_lock);

1336

spin_unlock_bh(&sky2->tx_lock);

1369

}

1337

}

1370

1338

1371

/* Network shutdown */

1339

/* Network shutdown */

1372

static int sky2_down(struct net_device *dev)

1340

static int sky2_down(struct net_device *dev)

1373

{

1341

{

1374

struct sky2_port *sky2 = netdev_priv(dev);

1342

struct sky2_port *sky2 = netdev_priv(dev);

1375

struct sky2_hw *hw = sky2->hw;

1343

struct sky2_hw *hw = sky2->hw;

1376

unsigned port = sky2->port;

1344

unsigned port = sky2->port;

1377

u16 ctrl;

1345

u16 ctrl;

1378

1346

1379

/* Never really got started! */

1347

/* Never really got started! */

1380

if (!sky2->tx_le)

1348

if (!sky2->tx_le)

1381

return 0;

1349

return 0;

1382

1350

1383

if (netif_msg_ifdown(sky2))

1351

if (netif_msg_ifdown(sky2))

1384

printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);

1352

printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);

1385

1353

1386

/* Stop more packets from being queued */

1354

/* Stop more packets from being queued */

1387

netif_stop_queue(dev);

1355

netif_stop_queue(dev);

1388

1356

1389

/* Disable port IRQ */

1357

/* Disable port IRQ */

1390

spin_lock_irq(&hw->hw_lock);

1358

spin_lock_irq(&hw->hw_lock);

1391

hw->intr_mask &= ~((sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);

1359

hw->intr_mask &= ~((sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);

1392

sky2_write32(hw, B0_IMSK, hw->intr_mask);

1360

sky2_write32(hw, B0_IMSK, hw->intr_mask);

1393

spin_unlock_irq(&hw->hw_lock);

1361

spin_unlock_irq(&hw->hw_lock);

1394

1362

1395

flush_scheduled_work();

1363

flush_scheduled_work();

1396

1364

1397

sky2_phy_reset(hw, port);

1365

sky2_phy_reset(hw, port);

1398

1366

1399

/* Stop transmitter */

1367

/* Stop transmitter */

1400

sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);

1368

sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);

1401

sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));

1369

sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));

1402

1370

1403

sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),

1371

sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),

1404

RB_RST_SET | RB_DIS_OP_MD);

1372

RB_RST_SET | RB_DIS_OP_MD);

1405

1373

1406

ctrl = gma_read16(hw, port, GM_GP_CTRL);

1374

ctrl = gma_read16(hw, port, GM_GP_CTRL);

1407

ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);

1375

ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);

1408

gma_write16(hw, port, GM_GP_CTRL, ctrl);

1376

gma_write16(hw, port, GM_GP_CTRL, ctrl);

1409

1377

1410

sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);

1378

sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);

1411

1379

1412

/* Workaround shared GMAC reset */

1380

/* Workaround shared GMAC reset */

1413

if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0

1381

if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0

1414

&& port == 0 && hw->dev[1] && netif_running(hw->dev[1])))

1382

&& port == 0 && hw->dev[1] && netif_running(hw->dev[1])))

1415

sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);

1383

sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);

1416

1384

1417

/* Disable Force Sync bit and Enable Alloc bit */

1385

/* Disable Force Sync bit and Enable Alloc bit */

1418

sky2_write8(hw, SK_REG(port, TXA_CTRL),

1386

sky2_write8(hw, SK_REG(port, TXA_CTRL),

1419

TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);

1387

TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);

1420

1388

1421

/* Stop Interval Timer and Limit Counter of Tx Arbiter */

1389

/* Stop Interval Timer and Limit Counter of Tx Arbiter */

1422

sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);

1390

sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);

1423

sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);

1391

sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);

1424

1392

1425

/* Reset the PCI FIFO of the async Tx queue */

1393

/* Reset the PCI FIFO of the async Tx queue */

1426

sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),

1394

sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),

1427

BMU_RST_SET | BMU_FIFO_RST);

1395

BMU_RST_SET | BMU_FIFO_RST);

1428

1396

1429

/* Reset the Tx prefetch units */

1397

/* Reset the Tx prefetch units */

1430

sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),

1398

sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),

1431

PREF_UNIT_RST_SET);

1399

PREF_UNIT_RST_SET);

1432

1400

1433

sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);

1401

sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);

1434

1402

1435

sky2_rx_stop(sky2);

1403

sky2_rx_stop(sky2);

1436

1404

1437

sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);

1405

sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);

1438

sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);

1406

sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);

1439

1407

1440

/* turn off LED's */

1408

/* turn off LED's */

1441

sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);

1409

sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);

1442

1410

1443

synchronize_irq(hw->pdev->irq);

1411

synchronize_irq(hw->pdev->irq);

1444

1412

1445

sky2_tx_clean(sky2);

1413

sky2_tx_clean(sky2);

1446

sky2_rx_clean(sky2);

1414

sky2_rx_clean(sky2);

1447

1415

1448

pci_free_consistent(hw->pdev, RX_LE_BYTES,

1416

pci_free_consistent(hw->pdev, RX_LE_BYTES,

1449

sky2->rx_le, sky2->rx_le_map);

1417

sky2->rx_le, sky2->rx_le_map);

1450

kfree(sky2->rx_ring);

1418

kfree(sky2->rx_ring);

1451

1419

1452

pci_free_consistent(hw->pdev,

1420

pci_free_consistent(hw->pdev,

1453

TX_RING_SIZE * sizeof(struct sky2_tx_le),

1421

TX_RING_SIZE * sizeof(struct sky2_tx_le),

1454

sky2->tx_le, sky2->tx_le_map);

1422

sky2->tx_le, sky2->tx_le_map);

1455

kfree(sky2->tx_ring);

1423

kfree(sky2->tx_ring);

1456

1424

1457

sky2->tx_le = NULL;

1425

sky2->tx_le = NULL;

1458

sky2->rx_le = NULL;

1426

sky2->rx_le = NULL;

1459

1427

1460

sky2->rx_ring = NULL;

1428

sky2->rx_ring = NULL;

1461

sky2->tx_ring = NULL;

1429

sky2->tx_ring = NULL;

1462

1430

1463

return 0;

1431

return 0;

1464

}

1432

}

1465

1433

1466

static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)

1434

static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)

1467

{

1435

{

1468

if (!hw->copper)

1436

if (!hw->copper)

1469

return SPEED_1000;

1437

return SPEED_1000;

1470

1438

1471

if (hw->chip_id == CHIP_ID_YUKON_FE)

1439

if (hw->chip_id == CHIP_ID_YUKON_FE)

1472

return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;

1440

return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;

1473

1441

1474

switch (aux & PHY_M_PS_SPEED_MSK) {

1442

switch (aux & PHY_M_PS_SPEED_MSK) {

1475

case PHY_M_PS_SPEED_1000:

1443

case PHY_M_PS_SPEED_1000:

1476

return SPEED_1000;

1444

return SPEED_1000;

1477

case PHY_M_PS_SPEED_100:

1445

case PHY_M_PS_SPEED_100:

1478

return SPEED_100;

1446

return SPEED_100;

1479

default:

1447

default:

1480

return SPEED_10;

1448

return SPEED_10;

1481

}

1449

}

1482

}

1450

}

1483

1451

1484

static void sky2_link_up(struct sky2_port *sky2)

1452

static void sky2_link_up(struct sky2_port *sky2)

1485

{

1453

{

1486

struct sky2_hw *hw = sky2->hw;

1454

struct sky2_hw *hw = sky2->hw;

1487

unsigned port = sky2->port;

1455

unsigned port = sky2->port;

1488

u16 reg;

1456

u16 reg;

1489

1457

1490

/* Enable Transmit FIFO Underrun */

1458

/* Enable Transmit FIFO Underrun */

1491

sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);

1459

sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);

1492

1460

1493

reg = gma_read16(hw, port, GM_GP_CTRL);

1461

reg = gma_read16(hw, port, GM_GP_CTRL);

1494

if (sky2->autoneg == AUTONEG_DISABLE) {

1462

if (sky2->autoneg == AUTONEG_DISABLE) {

1495

reg |= GM_GPCR_AU_ALL_DIS;

1463

reg |= GM_GPCR_AU_ALL_DIS;

1496

1464

1497

/* Is write/read necessary? Copied from sky2_mac_init */

1465

/* Is write/read necessary? Copied from sky2_mac_init */

1498

gma_write16(hw, port, GM_GP_CTRL, reg);

1466

gma_write16(hw, port, GM_GP_CTRL, reg);

1499

gma_read16(hw, port, GM_GP_CTRL);

1467

gma_read16(hw, port, GM_GP_CTRL);

1500

1468

1501

switch (sky2->speed) {

1469

switch (sky2->speed) {

1502

case SPEED_1000:

1470

case SPEED_1000:

1503

reg &= ~GM_GPCR_SPEED_100;

1471

reg &= ~GM_GPCR_SPEED_100;

1504

reg |= GM_GPCR_SPEED_1000;

1472

reg |= GM_GPCR_SPEED_1000;

1505

break;

1473

break;

1506

case SPEED_100:

1474

case SPEED_100:

1507

reg &= ~GM_GPCR_SPEED_1000;

1475

reg &= ~GM_GPCR_SPEED_1000;

1508

reg |= GM_GPCR_SPEED_100;

1476

reg |= GM_GPCR_SPEED_100;

1509

break;

1477

break;

1510

case SPEED_10:

1478

case SPEED_10:

1511

reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);

1479

reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);

1512

break;

1480

break;

1513

}

1481

}

1514

} else

1482

} else

1515

reg &= ~GM_GPCR_AU_ALL_DIS;

1483

reg &= ~GM_GPCR_AU_ALL_DIS;

1516

1484

1517

if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE)

1485

if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE)

1518

reg |= GM_GPCR_DUP_FULL;

1486

reg |= GM_GPCR_DUP_FULL;

1519

1487

1520

/* enable Rx/Tx */

1488

/* enable Rx/Tx */

1521

reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;

1489

reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;

1522

gma_write16(hw, port, GM_GP_CTRL, reg);

1490

gma_write16(hw, port, GM_GP_CTRL, reg);

1523

gma_read16(hw, port, GM_GP_CTRL);

1491

gma_read16(hw, port, GM_GP_CTRL);

1524

1492

1525

gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);

1493

gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);

1526

1494

1527

netif_carrier_on(sky2->netdev);

1495

netif_carrier_on(sky2->netdev);

1528

netif_wake_queue(sky2->netdev);

1496

netif_wake_queue(sky2->netdev);

1529

1497

1530

/* Turn on link LED */

1498

/* Turn on link LED */

1531

sky2_write8(hw, SK_REG(port, LNK_LED_REG),

1499

sky2_write8(hw, SK_REG(port, LNK_LED_REG),

1532

LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);

1500

LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);

1533

1501

1534

if (hw->chip_id == CHIP_ID_YUKON_XL) {

1502

if (hw->chip_id == CHIP_ID_YUKON_XL) {

1535

u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);

1503

u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);

1536

1504

1537

gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);

1505

gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);

1538

gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */

1506

gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */

1539

PHY_M_LEDC_INIT_CTRL(sky2->speed ==

1507

PHY_M_LEDC_INIT_CTRL(sky2->speed ==

1540

SPEED_10 ? 7 : 0) |

1508

SPEED_10 ? 7 : 0) |

1541

PHY_M_LEDC_STA1_CTRL(sky2->speed ==

1509

PHY_M_LEDC_STA1_CTRL(sky2->speed ==

1542

SPEED_100 ? 7 : 0) |

1510

SPEED_100 ? 7 : 0) |

1543

PHY_M_LEDC_STA0_CTRL(sky2->speed ==

1511

PHY_M_LEDC_STA0_CTRL(sky2->speed ==

1544

SPEED_1000 ? 7 : 0));

1512

SPEED_1000 ? 7 : 0));

1545

gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);

1513

gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);

1546

}

1514

}

1547

1515

1548

if (netif_msg_link(sky2))

1516

if (netif_msg_link(sky2))

1549

printk(KERN_INFO PFX

1517

printk(KERN_INFO PFX

1550

"%s: Link is up at %d Mbps, %s duplex, flow control %s\n",

1518

"%s: Link is up at %d Mbps, %s duplex, flow control %s\n",

1551

sky2->netdev->name, sky2->speed,

1519

sky2->netdev->name, sky2->speed,

1552

sky2->duplex == DUPLEX_FULL ? "full" : "half",

1520

sky2->duplex == DUPLEX_FULL ? "full" : "half",

1553

(sky2->tx_pause && sky2->rx_pause) ? "both" :

1521

(sky2->tx_pause && sky2->rx_pause) ? "both" :

1554

sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");

1522

sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");

1555

}

1523

}

1556

1524

1557

static void sky2_link_down(struct sky2_port *sky2)

1525

static void sky2_link_down(struct sky2_port *sky2)

1558

{

1526

{

1559

struct sky2_hw *hw = sky2->hw;

1527

struct sky2_hw *hw = sky2->hw;

1560

unsigned port = sky2->port;

1528

unsigned port = sky2->port;

1561

u16 reg;

1529

u16 reg;

1562

1530

1563

gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);

1531

gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);

1564

1532

1565

reg = gma_read16(hw, port, GM_GP_CTRL);

1533

reg = gma_read16(hw, port, GM_GP_CTRL);

1566

reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);

1534

reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);

1567

gma_write16(hw, port, GM_GP_CTRL, reg);

1535

gma_write16(hw, port, GM_GP_CTRL, reg);

1568

gma_read16(hw, port, GM_GP_CTRL); /* PCI post */

1536

gma_read16(hw, port, GM_GP_CTRL); /* PCI post */

1569

1537

1570

if (sky2->rx_pause && !sky2->tx_pause) {

1538

if (sky2->rx_pause && !sky2->tx_pause) {

1571

/* restore Asymmetric Pause bit */

1539

/* restore Asymmetric Pause bit */

1572

gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,

1540

gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,

1573

gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)

1541

gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)

1574

| PHY_M_AN_ASP);

1542

| PHY_M_AN_ASP);

1575

}

1543

}

1576

1544

1577

netif_carrier_off(sky2->netdev);

1545

netif_carrier_off(sky2->netdev);

1578

netif_stop_queue(sky2->netdev);

1546

netif_stop_queue(sky2->netdev);

1579

1547

1580

/* Turn on link LED */

1548

/* Turn on link LED */

1581

sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);

1549

sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);

1582

1550

1583

if (netif_msg_link(sky2))

1551

if (netif_msg_link(sky2))

1584

printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);

1552

printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);

1585

sky2_phy_init(hw, port);

1553

sky2_phy_init(hw, port);

1586

}

1554

}

1587

1555

1588

static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)

1556

static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)

1589

{

1557

{

1590

struct sky2_hw *hw = sky2->hw;

1558

struct sky2_hw *hw = sky2->hw;

1591

unsigned port = sky2->port;

1559

unsigned port = sky2->port;

1592

u16 lpa;

1560

u16 lpa;

1593

1561

1594

lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);

1562

lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);

1595

1563

1596

if (lpa & PHY_M_AN_RF) {

1564

if (lpa & PHY_M_AN_RF) {

1597

printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);

1565

printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);

1598

return -1;

1566

return -1;

1599

}

1567

}

1600

1568

1601

if (hw->chip_id != CHIP_ID_YUKON_FE &&

1569

if (hw->chip_id != CHIP_ID_YUKON_FE &&

1602

gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {

1570

gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {

1603

printk(KERN_ERR PFX "%s: master/slave fault",

1571

printk(KERN_ERR PFX "%s: master/slave fault",

1604

sky2->netdev->name);

1572

sky2->netdev->name);

1605

return -1;

1573

return -1;

1606

}

1574

}

1607

1575

1608

if (!(aux & PHY_M_PS_SPDUP_RES)) {

1576

if (!(aux & PHY_M_PS_SPDUP_RES)) {

1609

printk(KERN_ERR PFX "%s: speed/duplex mismatch",

1577

printk(KERN_ERR PFX "%s: speed/duplex mismatch",

1610

sky2->netdev->name);

1578

sky2->netdev->name);

1611

return -1;

1579

return -1;

1612

}

1580

}

1613

1581

1614

sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;

1582

sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;

1615

1583

1616

sky2->speed = sky2_phy_speed(hw, aux);

1584

sky2->speed = sky2_phy_speed(hw, aux);

1617

1585

1618

/* Pause bits are offset (9..8) */

1586

/* Pause bits are offset (9..8) */

1619

if (hw->chip_id == CHIP_ID_YUKON_XL)

1587

if (hw->chip_id == CHIP_ID_YUKON_XL)

1620

aux >>= 6;

1588

aux >>= 6;

1621

1589

1622

sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;

1590

sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;

1623

sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;

1591

sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;

1624

1592

1625

if ((sky2->tx_pause || sky2->rx_pause)

1593

if ((sky2->tx_pause || sky2->rx_pause)

1626

&& !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF))

1594

&& !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF))

1627

sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);

1595

sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);

1628

else

1596

else

1629

sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);

1597

sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);

1630

1598

1631

return 0;

1599

return 0;

1632

}

1600

}

1633

1601

1634

/*

1602

/*

1635

* Interrupt from PHY are handled outside of interrupt context

1603

* Interrupt from PHY are handled outside of interrupt context

1636

* because accessing phy registers requires spin wait which might

1604

* because accessing phy registers requires spin wait which might

1637

* cause excess interrupt latency.

1605

* cause excess interrupt latency.

1638

*/

1606

*/

1639

static void sky2_phy_task(void *arg)

1607

static void sky2_phy_task(void *arg)

1640

{

1608

{

1641

struct sky2_port *sky2 = arg;

1609

struct sky2_port *sky2 = arg;

1642

struct sky2_hw *hw = sky2->hw;

1610

struct sky2_hw *hw = sky2->hw;

1643

u16 istatus, phystat;

1611

u16 istatus, phystat;

1644

1612

1645

down(&sky2->phy_sema);

1613

down(&sky2->phy_sema);

1646

istatus = gm_phy_read(hw, sky2->port, PHY_MARV_INT_STAT);

1614

istatus = gm_phy_read(hw, sky2->port, PHY_MARV_INT_STAT);

1647

phystat = gm_phy_read(hw, sky2->port, PHY_MARV_PHY_STAT);

1615

phystat = gm_phy_read(hw, sky2->port, PHY_MARV_PHY_STAT);

1648

1616

1649

if (netif_msg_intr(sky2))

1617

if (netif_msg_intr(sky2))

1650

printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",

1618

printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",

1651

sky2->netdev->name, istatus, phystat);

1619

sky2->netdev->name, istatus, phystat);

1652

1620

1653

if (istatus & PHY_M_IS_AN_COMPL) {

1621

if (istatus & PHY_M_IS_AN_COMPL) {

1654

if (sky2_autoneg_done(sky2, phystat) == 0)

1622

if (sky2_autoneg_done(sky2, phystat) == 0)

1655

sky2_link_up(sky2);

1623

sky2_link_up(sky2);

1656

goto out;

1624

goto out;

1657

}

1625

}

1658

1626

1659

if (istatus & PHY_M_IS_LSP_CHANGE)

1627

if (istatus & PHY_M_IS_LSP_CHANGE)

1660

sky2->speed = sky2_phy_speed(hw, phystat);

1628

sky2->speed = sky2_phy_speed(hw, phystat);

1661

1629

1662

if (istatus & PHY_M_IS_DUP_CHANGE)

1630

if (istatus & PHY_M_IS_DUP_CHANGE)

1663

sky2->duplex =

1631

sky2->duplex =

1664

(phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;

1632

(phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;

1665

1633

1666

if (istatus & PHY_M_IS_LST_CHANGE) {

1634

if (istatus & PHY_M_IS_LST_CHANGE) {

1667

if (phystat & PHY_M_PS_LINK_UP)

1635

if (phystat & PHY_M_PS_LINK_UP)

1668

sky2_link_up(sky2);

1636

sky2_link_up(sky2);

1669

else

1637

else

1670

sky2_link_down(sky2);

1638

sky2_link_down(sky2);

1671

}

1639

}

1672

out:

1640

out:

1673

up(&sky2->phy_sema);

1641

up(&sky2->phy_sema);

1674

1642

1675

spin_lock_irq(&hw->hw_lock);

1643

spin_lock_irq(&hw->hw_lock);

1676

hw->intr_mask |= (sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2;

1644

hw->intr_mask |= (sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2;

1677

sky2_write32(hw, B0_IMSK, hw->intr_mask);

1645

sky2_write32(hw, B0_IMSK, hw->intr_mask);

1678

spin_unlock_irq(&hw->hw_lock);

1646

spin_unlock_irq(&hw->hw_lock);

1679

}

1647

}

1680

1648

1681

1649

1682

/* Transmit timeout is only called if we are running, carries is up

1650

/* Transmit timeout is only called if we are running, carries is up

1683

* and tx queue is full (stopped).

1651

* and tx queue is full (stopped).

1684

*/

1652

*/

1685

static void sky2_tx_timeout(struct net_device *dev)

1653

static void sky2_tx_timeout(struct net_device *dev)

1686

{

1654

{

1687

struct sky2_port *sky2 = netdev_priv(dev);

1655

struct sky2_port *sky2 = netdev_priv(dev);

1688

struct sky2_hw *hw = sky2->hw;

1656

struct sky2_hw *hw = sky2->hw;

1689

unsigned txq = txqaddr[sky2->port];

1657

unsigned txq = txqaddr[sky2->port];

1690

u16 ridx;

1658

u16 ridx;

1691

1659

1692

/* Maybe we just missed an status interrupt */

1660

/* Maybe we just missed an status interrupt */

1693

spin_lock(&sky2->tx_lock);

1661

spin_lock(&sky2->tx_lock);

1694

ridx = sky2_read16(hw,

1662

ridx = sky2_read16(hw,

1695

sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX);

1663

sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX);

1696

sky2_tx_complete(sky2, ridx);

1664

sky2_tx_complete(sky2, ridx);

1697

spin_unlock(&sky2->tx_lock);

1665

spin_unlock(&sky2->tx_lock);

1698

1666

1699

if (!netif_queue_stopped(dev)) {

1667

if (!netif_queue_stopped(dev)) {

1700

if (net_ratelimit())

1668

if (net_ratelimit())

1701

pr_info(PFX "transmit interrupt missed? recovered\n");

1669

pr_info(PFX "transmit interrupt missed? recovered\n");

1702

return;

1670

return;

1703

}

1671

}

1704

1672

1705

if (netif_msg_timer(sky2))

1673

if (netif_msg_timer(sky2))

1706

printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);

1674

printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);

1707

1675

1708

sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP);

1676

sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP);

1709

sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);

1677

sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);

1710

1678

1711

sky2_tx_clean(sky2);

1679

sky2_tx_clean(sky2);

1712

1680

1713

sky2_qset(hw, txq);

1681

sky2_qset(hw, txq);

1714

sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1);

1682

sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1);

1715

}

1683

}

1716

1684

1717

1685

1718

#define roundup(x, y) ((((x)+((y)-1))/(y))*(y))

1686

#define roundup(x, y) ((((x)+((y)-1))/(y))*(y))

1719

/* Want receive buffer size to be multiple of 64 bits

1687

/* Want receive buffer size to be multiple of 64 bits

1720

* and incl room for vlan and truncation

1688

* and incl room for vlan and truncation

1721

*/

1689

*/

1722

static inline unsigned sky2_buf_size(int mtu)

1690

static inline unsigned sky2_buf_size(int mtu)

1723

{

1691

{

1724

return roundup(mtu + ETH_HLEN + VLAN_HLEN, 8) + 8;

1692

return roundup(mtu + ETH_HLEN + VLAN_HLEN, 8) + 8;

1725

}

1693

}

1726

1694

1727

static int sky2_change_mtu(struct net_device *dev, int new_mtu)

1695

static int sky2_change_mtu(struct net_device *dev, int new_mtu)

1728

{

1696

{

1729

struct sky2_port *sky2 = netdev_priv(dev);

1697

struct sky2_port *sky2 = netdev_priv(dev);

1730

struct sky2_hw *hw = sky2->hw;

1698

struct sky2_hw *hw = sky2->hw;

1731

int err;

1699

int err;

1732

u16 ctl, mode;

1700

u16 ctl, mode;

1733

1701

1734

if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)

1702

if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)

1735

return -EINVAL;

1703

return -EINVAL;

1736

1704

1737

if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)

1705

if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)

1738

return -EINVAL;

1706

return -EINVAL;

1739

1707

1740

if (!netif_running(dev)) {

1708

if (!netif_running(dev)) {

1741

dev->mtu = new_mtu;

1709

dev->mtu = new_mtu;

1742

return 0;

1710

return 0;

1743

}

1711

}

1744

1712

1745

sky2_write32(hw, B0_IMSK, 0);

1713

sky2_write32(hw, B0_IMSK, 0);

1746

1714

1747

dev->trans_start = jiffies; /* prevent tx timeout */

1715

dev->trans_start = jiffies; /* prevent tx timeout */

1748

netif_stop_queue(dev);

1716

netif_stop_queue(dev);

1749

netif_poll_disable(hw->dev[0]);

1717

netif_poll_disable(hw->dev[0]);

1750

1718

1751

ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);

1719

ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);

1752

gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);

1720

gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);

1753

sky2_rx_stop(sky2);

1721

sky2_rx_stop(sky2);

1754

sky2_rx_clean(sky2);

1722

sky2_rx_clean(sky2);

1755

1723

1756

dev->mtu = new_mtu;

1724

dev->mtu = new_mtu;

1757

sky2->rx_bufsize = sky2_buf_size(new_mtu);

1725

sky2->rx_bufsize = sky2_buf_size(new_mtu);

1758

mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |

1726

mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |

1759

GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);

1727

GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);

1760

1728

1761

if (dev->mtu > ETH_DATA_LEN)

1729

if (dev->mtu > ETH_DATA_LEN)

1762

mode |= GM_SMOD_JUMBO_ENA;

1730

mode |= GM_SMOD_JUMBO_ENA;

1763

1731

1764

gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);

1732

gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);

1765

1733

1766

sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);

1734

sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);

1767

1735

1768

err = sky2_rx_start(sky2);

1736

err = sky2_rx_start(sky2);

1769

sky2_write32(hw, B0_IMSK, hw->intr_mask);

1737

sky2_write32(hw, B0_IMSK, hw->intr_mask);

1770

1738

1771

if (err)

1739

if (err)

1772

dev_close(dev);

1740

dev_close(dev);

1773

else {

1741

else {

1774

gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);

1742

gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);

1775

1743

1776

netif_poll_enable(hw->dev[0]);

1744

netif_poll_enable(hw->dev[0]);

1777

netif_wake_queue(dev);

1745

netif_wake_queue(dev);

1778

}

1746

}

1779

1747

1780

return err;

1748

return err;

1781

}

1749

}

1782

1750

1783

/*

1751

/*

1784

* Receive one packet.

1752

* Receive one packet.

1785

* For small packets or errors, just reuse existing skb.

1753

* For small packets or errors, just reuse existing skb.

1786

* For larger packets, get new buffer.

1754

* For larger packets, get new buffer.

1787

*/

1755

*/

1788

static struct sk_buff *sky2_receive(struct sky2_port *sky2,

1756

static struct sk_buff *sky2_receive(struct sky2_port *sky2,

1789

u16 length, u32 status)

1757

u16 length, u32 status)

1790

{

1758

{

1791

struct ring_info *re = sky2->rx_ring + sky2->rx_next;

1759

struct ring_info *re = sky2->rx_ring + sky2->rx_next;

1792

struct sk_buff *skb = NULL;

1760

struct sk_buff *skb = NULL;

1793

1761

1794

if (unlikely(netif_msg_rx_status(sky2)))

1762

if (unlikely(netif_msg_rx_status(sky2)))

1795

printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",

1763

printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",

1796

sky2->netdev->name, sky2->rx_next, status, length);

1764

sky2->netdev->name, sky2->rx_next, status, length);

1797

1765

1798

sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;

1766

sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;

1799

prefetch(sky2->rx_ring + sky2->rx_next);

1767

prefetch(sky2->rx_ring + sky2->rx_next);

1800

1768

1801

if (status & GMR_FS_ANY_ERR)

1769

if (status & GMR_FS_ANY_ERR)

1802

goto error;

1770

goto error;

1803

1771

1804

if (!(status & GMR_FS_RX_OK))

1772

if (!(status & GMR_FS_RX_OK))

1805

goto resubmit;

1773

goto resubmit;

1806

1774

1807

if (length > sky2->netdev->mtu + ETH_HLEN)

1775

if (length > sky2->netdev->mtu + ETH_HLEN)

1808

goto oversize;

1776

goto oversize;

1809

1777

1810

if (length < copybreak) {

1778

if (length < copybreak) {

1811

skb = alloc_skb(length + 2, GFP_ATOMIC);

1779

skb = alloc_skb(length + 2, GFP_ATOMIC);

1812

if (!skb)

1780

if (!skb)

1813

goto resubmit;

1781

goto resubmit;

1814

1782

1815

skb_reserve(skb, 2);

1783

skb_reserve(skb, 2);

1816

pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr,

1784

pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr,

1817

length, PCI_DMA_FROMDEVICE);

1785

length, PCI_DMA_FROMDEVICE);

1818

memcpy(skb->data, re->skb->data, length);

1786

memcpy(skb->data, re->skb->data, length);

1819

skb->ip_summed = re->skb->ip_summed;

1787

skb->ip_summed = re->skb->ip_summed;

1820

skb->csum = re->skb->csum;

1788

skb->csum = re->skb->csum;

1821

pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr,

1789

pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr,

1822

length, PCI_DMA_FROMDEVICE);

1790

length, PCI_DMA_FROMDEVICE);

1823

} else {

1791

} else {

1824

struct sk_buff *nskb;

1792

struct sk_buff *nskb;

1825

1793

1826

nskb = sky2_alloc_skb(sky2->rx_bufsize, GFP_ATOMIC);

1794

nskb = sky2_alloc_skb(sky2->rx_bufsize, GFP_ATOMIC);

1827

if (!nskb)

1795

if (!nskb)

1828

goto resubmit;

1796

goto resubmit;

1829

1797

1830

skb = re->skb;

1798

skb = re->skb;

1831

re->skb = nskb;

1799

re->skb = nskb;

1832

pci_unmap_single(sky2->hw->pdev, re->mapaddr,

1800

pci_unmap_single(sky2->hw->pdev, re->mapaddr,

1833

sky2->rx_bufsize, PCI_DMA_FROMDEVICE);

1801

sky2->rx_bufsize, PCI_DMA_FROMDEVICE);

1834

prefetch(skb->data);

1802

prefetch(skb->data);

1835

1803

1836

re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,

1804

re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,

1837

sky2->rx_bufsize, PCI_DMA_FROMDEVICE);

1805

sky2->rx_bufsize, PCI_DMA_FROMDEVICE);

1838

}

1806

}

1839

1807

1840

skb_put(skb, length);

1808

skb_put(skb, length);

1841

resubmit:

1809

resubmit:

1842

re->skb->ip_summed = CHECKSUM_NONE;

1810

re->skb->ip_summed = CHECKSUM_NONE;

1843

sky2_rx_add(sky2, re->mapaddr);

1811

sky2_rx_add(sky2, re->mapaddr);

1844

1812

1845

/* Tell receiver about new buffers. */

1813

/* Tell receiver about new buffers. */

1846

sky2_put_idx(sky2->hw, rxqaddr[sky2->port], sky2->rx_put,

1814

sky2_put_idx(sky2->hw, rxqaddr[sky2->port], sky2->rx_put);

1847

&sky2->rx_last_put, RX_LE_SIZE);

1848

1815

1849

return skb;

1816

return skb;

1850

1817

1851

oversize:

1818

oversize:

1852

++sky2->net_stats.rx_over_errors;

1819

++sky2->net_stats.rx_over_errors;

1853

goto resubmit;

1820

goto resubmit;

1854

1821

1855

error:

1822

error:

1856

++sky2->net_stats.rx_errors;

1823

++sky2->net_stats.rx_errors;

1857

1824

1858

if (netif_msg_rx_err(sky2) && net_ratelimit())

1825

if (netif_msg_rx_err(sky2) && net_ratelimit())

1859

printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",

1826

printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",

1860

sky2->netdev->name, status, length);

1827

sky2->netdev->name, status, length);

1861

1828

1862

if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))

1829

if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))

1863

sky2->net_stats.rx_length_errors++;

1830

sky2->net_stats.rx_length_errors++;

1864

if (status & GMR_FS_FRAGMENT)

1831

if (status & GMR_FS_FRAGMENT)

1865

sky2->net_stats.rx_frame_errors++;

1832

sky2->net_stats.rx_frame_errors++;

1866

if (status & GMR_FS_CRC_ERR)

1833

if (status & GMR_FS_CRC_ERR)

1867

sky2->net_stats.rx_crc_errors++;

1834

sky2->net_stats.rx_crc_errors++;

1868

if (status & GMR_FS_RX_FF_OV)

1835

if (status & GMR_FS_RX_FF_OV)

1869

sky2->net_stats.rx_fifo_errors++;

1836

sky2->net_stats.rx_fifo_errors++;

1870

1837

1871

goto resubmit;

1838

goto resubmit;

1872

}

1839

}

1873

1840

1874

/*

1841

/*

1875

* Check for transmit complete

1842

* Check for transmit complete

1876

*/

1843

*/

1877

#define TX_NO_STATUS 0xffff

1844

#define TX_NO_STATUS 0xffff

1878

1845

1879

static void sky2_tx_check(struct sky2_hw *hw, int port, u16 last)

1846

static void sky2_tx_check(struct sky2_hw *hw, int port, u16 last)

1880

{

1847

{

1881

if (last != TX_NO_STATUS) {

1848

if (last != TX_NO_STATUS) {

1882

struct net_device *dev = hw->dev[port];

1849

struct net_device *dev = hw->dev[port];

1883

if (dev && netif_running(dev)) {

1850

if (dev && netif_running(dev)) {

1884

struct sky2_port *sky2 = netdev_priv(dev);

1851

struct sky2_port *sky2 = netdev_priv(dev);

1885

1852

1886

spin_lock(&sky2->tx_lock);

1853

spin_lock(&sky2->tx_lock);

1887

sky2_tx_complete(sky2, last);

1854

sky2_tx_complete(sky2, last);

1888

spin_unlock(&sky2->tx_lock);

1855

spin_unlock(&sky2->tx_lock);

1889

}

1856

}

1890

}

1857

}

1891

}

1858

}

1892

1859

1893

/*

1860

/*

1894

* Both ports share the same status interrupt, therefore there is only

1861

* Both ports share the same status interrupt, therefore there is only

1895

* one poll routine.

1862

* one poll routine.

1896

*/

1863

*/

1897

static int sky2_poll(struct net_device *dev0, int *budget)

1864

static int sky2_poll(struct net_device *dev0, int *budget)

1898

{

1865

{

1899

struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;

1866

struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;

1900

unsigned int to_do = min(dev0->quota, *budget);

1867

unsigned int to_do = min(dev0->quota, *budget);

1901

unsigned int work_done = 0;

1868

unsigned int work_done = 0;

1902

u16 hwidx;

1869

u16 hwidx;

1903

u16 tx_done[2] = { TX_NO_STATUS, TX_NO_STATUS };

1870

u16 tx_done[2] = { TX_NO_STATUS, TX_NO_STATUS };

1904

1871

1905

sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);

1872

sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);

1906

1873

1907

/*

1874

/*

1908

* Kick the STAT_LEV_TIMER_CTRL timer.

1875

* Kick the STAT_LEV_TIMER_CTRL timer.

1909

* This fixes my hangs on Yukon-EC (0xb6) rev 1.

1876

* This fixes my hangs on Yukon-EC (0xb6) rev 1.

1910

* The if clause is there to start the timer only if it has been

1877

* The if clause is there to start the timer only if it has been

1911

* configured correctly and not been disabled via ethtool.

1878

* configured correctly and not been disabled via ethtool.

1912

*/

1879

*/

1913

if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_START) {

1880

if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_START) {

1914

sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);

1881

sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);

1915

sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);

1882

sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);

1916

}

1883

}

1917

1884

1918

hwidx = sky2_read16(hw, STAT_PUT_IDX);

1885

hwidx = sky2_read16(hw, STAT_PUT_IDX);

1919

BUG_ON(hwidx >= STATUS_RING_SIZE);

1886

BUG_ON(hwidx >= STATUS_RING_SIZE);

1920

rmb();

1887

rmb();

1921

1888

1922

while (hwidx != hw->st_idx) {

1889

while (hwidx != hw->st_idx) {

1923

struct sky2_status_le *le = hw->st_le + hw->st_idx;

1890

struct sky2_status_le *le = hw->st_le + hw->st_idx;

1924

struct net_device *dev;

1891

struct net_device *dev;

1925

struct sky2_port *sky2;

1892

struct sky2_port *sky2;

1926

struct sk_buff *skb;

1893

struct sk_buff *skb;

1927

u32 status;

1894

u32 status;

1928

u16 length;

1895

u16 length;

1929

1896

1930

le = hw->st_le + hw->st_idx;

1897

le = hw->st_le + hw->st_idx;

1931

hw->st_idx = (hw->st_idx + 1) % STATUS_RING_SIZE;

1898

hw->st_idx = (hw->st_idx + 1) % STATUS_RING_SIZE;

1932

prefetch(hw->st_le + hw->st_idx);

1899

prefetch(hw->st_le + hw->st_idx);

1933

1900

1934

BUG_ON(le->link >= 2);

1901

BUG_ON(le->link >= 2);

1935

dev = hw->dev[le->link];

1902

dev = hw->dev[le->link];

1936

if (dev == NULL || !netif_running(dev))

1903

if (dev == NULL || !netif_running(dev))

1937

continue;

1904

continue;

1938

1905

1939

sky2 = netdev_priv(dev);

1906

sky2 = netdev_priv(dev);

1940

status = le32_to_cpu(le->status);

1907

status = le32_to_cpu(le->status);

1941

length = le16_to_cpu(le->length);

1908

length = le16_to_cpu(le->length);

1942

1909

1943

switch (le->opcode & ~HW_OWNER) {

1910

switch (le->opcode & ~HW_OWNER) {

1944

case OP_RXSTAT:

1911

case OP_RXSTAT:

1945

skb = sky2_receive(sky2, length, status);

1912

skb = sky2_receive(sky2, length, status);

1946

if (!skb)

1913

if (!skb)

1947

break;

1914

break;

1948

1915

1949

skb->dev = dev;

1916

skb->dev = dev;

1950

skb->protocol = eth_type_trans(skb, dev);

1917

skb->protocol = eth_type_trans(skb, dev);

1951

dev->last_rx = jiffies;

1918

dev->last_rx = jiffies;

1952

1919

1953

#ifdef SKY2_VLAN_TAG_USED

1920

#ifdef SKY2_VLAN_TAG_USED

1954

if (sky2->vlgrp && (status & GMR_FS_VLAN)) {

1921

if (sky2->vlgrp && (status & GMR_FS_VLAN)) {

1955

vlan_hwaccel_receive_skb(skb,

1922

vlan_hwaccel_receive_skb(skb,

1956

sky2->vlgrp,

1923

sky2->vlgrp,

1957

be16_to_cpu(sky2->rx_tag));

1924

be16_to_cpu(sky2->rx_tag));

1958

} else

1925

} else

1959

#endif

1926

#endif

1960

netif_receive_skb(skb);

1927

netif_receive_skb(skb);

1961

1928

1962

if (++work_done >= to_do)

1929

if (++work_done >= to_do)

1963

goto exit_loop;

1930

goto exit_loop;

1964

break;

1931

break;

1965

1932

1966

#ifdef SKY2_VLAN_TAG_USED

1933

#ifdef SKY2_VLAN_TAG_USED

1967

case OP_RXVLAN:

1934

case OP_RXVLAN:

1968

sky2->rx_tag = length;

1935

sky2->rx_tag = length;

1969

break;

1936

break;

1970

1937

1971

case OP_RXCHKSVLAN:

1938

case OP_RXCHKSVLAN:

1972

sky2->rx_tag = length;

1939

sky2->rx_tag = length;

1973

/* fall through */

1940

/* fall through */

1974

#endif

1941

#endif

1975

case OP_RXCHKS:

1942

case OP_RXCHKS:

1976

skb = sky2->rx_ring[sky2->rx_next].skb;

1943

skb = sky2->rx_ring[sky2->rx_next].skb;

1977

skb->ip_summed = CHECKSUM_HW;

1944

skb->ip_summed = CHECKSUM_HW;

1978

skb->csum = le16_to_cpu(status);

1945

skb->csum = le16_to_cpu(status);

1979

break;

1946

break;

1980

1947

1981

case OP_TXINDEXLE:

1948

case OP_TXINDEXLE:

1982

/* TX index reports status for both ports */

1949

/* TX index reports status for both ports */

1983

tx_done[0] = status & 0xffff;

1950

tx_done[0] = status & 0xffff;

1984

tx_done[1] = ((status >> 24) & 0xff)

1951

tx_done[1] = ((status >> 24) & 0xff)

1985

| (u16)(length & 0xf) << 8;

1952

| (u16)(length & 0xf) << 8;

1986

break;

1953

break;

1987

1954

1988

default:

1955

default:

1989

if (net_ratelimit())

1956

if (net_ratelimit())

1990

printk(KERN_WARNING PFX

1957

printk(KERN_WARNING PFX

1991

"unknown status opcode 0x%x\n", le->opcode);

1958

"unknown status opcode 0x%x\n", le->opcode);

1992

break;

1959

break;

1993

}

1960

}

1994

}

1961

}

1995

1962

1996

exit_loop:

1963

exit_loop:

1997

sky2_tx_check(hw, 0, tx_done[0]);

1964

sky2_tx_check(hw, 0, tx_done[0]);

1998

sky2_tx_check(hw, 1, tx_done[1]);

1965

sky2_tx_check(hw, 1, tx_done[1]);

1999

1966

2000

if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_START) {

1967

if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_START) {

2001

sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);

1968

sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);

2002

sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);

1969

sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);

2003

}

1970

}

2004

1971

2005

if (likely(work_done < to_do)) {

1972

if (likely(work_done < to_do)) {

2006

spin_lock_irq(&hw->hw_lock);

1973

spin_lock_irq(&hw->hw_lock);

2007

__netif_rx_complete(dev0);

1974

__netif_rx_complete(dev0);

2008

1975

2009

hw->intr_mask |= Y2_IS_STAT_BMU;

1976

hw->intr_mask |= Y2_IS_STAT_BMU;

2010

sky2_write32(hw, B0_IMSK, hw->intr_mask);

1977

sky2_write32(hw, B0_IMSK, hw->intr_mask);

2011

spin_unlock_irq(&hw->hw_lock);

1978

spin_unlock_irq(&hw->hw_lock);

2012

1979

2013

return 0;

1980

return 0;

2014

} else {

1981

} else {

2015

*budget -= work_done;

1982

*budget -= work_done;

2016

dev0->quota -= work_done;

1983

dev0->quota -= work_done;

2017

return 1;

1984

return 1;

2018

}

1985

}

2019

}

1986

}

2020

1987

2021

static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)

1988

static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)

2022

{

1989

{

2023

struct net_device *dev = hw->dev[port];

1990

struct net_device *dev = hw->dev[port];

2024

1991

2025

if (net_ratelimit())

1992

if (net_ratelimit())

2026

printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",

1993

printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",

2027

dev->name, status);

1994

dev->name, status);

2028

1995

2029

if (status & Y2_IS_PAR_RD1) {

1996

if (status & Y2_IS_PAR_RD1) {

2030

if (net_ratelimit())

1997

if (net_ratelimit())

2031

printk(KERN_ERR PFX "%s: ram data read parity error\n",

1998

printk(KERN_ERR PFX "%s: ram data read parity error\n",

2032

dev->name);

1999

dev->name);

2033

/* Clear IRQ */

2000

/* Clear IRQ */

2034

sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);

2001

sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);

2035

}

2002

}

2036

2003

2037

if (status & Y2_IS_PAR_WR1) {

2004

if (status & Y2_IS_PAR_WR1) {

2038

if (net_ratelimit())

2005

if (net_ratelimit())

2039

printk(KERN_ERR PFX "%s: ram data write parity error\n",

2006

printk(KERN_ERR PFX "%s: ram data write parity error\n",

2040

dev->name);

2007

dev->name);

2041

2008

2042

sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);

2009

sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);

2043

}

2010

}

2044

2011

2045

if (status & Y2_IS_PAR_MAC1) {

2012

if (status & Y2_IS_PAR_MAC1) {

2046

if (net_ratelimit())

2013

if (net_ratelimit())

2047

printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);

2014

printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);

2048

sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);

2015

sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);

2049

}

2016

}

2050

2017

2051

if (status & Y2_IS_PAR_RX1) {

2018

if (status & Y2_IS_PAR_RX1) {

2052

if (net_ratelimit())

2019

if (net_ratelimit())

2053

printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);

2020

printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);

2054

sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);

2021

sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);

2055

}

2022

}

2056

2023

2057

if (status & Y2_IS_TCP_TXA1) {

2024

if (status & Y2_IS_TCP_TXA1) {

2058

if (net_ratelimit())

2025

if (net_ratelimit())

2059

printk(KERN_ERR PFX "%s: TCP segmentation error\n",

2026

printk(KERN_ERR PFX "%s: TCP segmentation error\n",

2060

dev->name);

2027

dev->name);

2061

sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);

2028

sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);

2062

}

2029

}

2063

}

2030

}

2064

2031

2065

static void sky2_hw_intr(struct sky2_hw *hw)

2032

static void sky2_hw_intr(struct sky2_hw *hw)

2066

{

2033

{

2067

u32 status = sky2_read32(hw, B0_HWE_ISRC);

2034

u32 status = sky2_read32(hw, B0_HWE_ISRC);

2068

2035

2069

if (status & Y2_IS_TIST_OV)

2036

if (status & Y2_IS_TIST_OV)

2070

sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);

2037

sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);

2071

2038

2072

if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {

2039

if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {

2073

u16 pci_err;

2040

u16 pci_err;

2074

2041

2075

pci_err = sky2_pci_read16(hw, PCI_STATUS);

2042

pci_err = sky2_pci_read16(hw, PCI_STATUS);

2076

if (net_ratelimit())

2043

if (net_ratelimit())

2077

printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",

2044

printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",

2078

pci_name(hw->pdev), pci_err);

2045

pci_name(hw->pdev), pci_err);

2079

2046

2080

sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);

2047

sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);

2081

sky2_pci_write16(hw, PCI_STATUS,

2048

sky2_pci_write16(hw, PCI_STATUS,

2082

pci_err | PCI_STATUS_ERROR_BITS);

2049

pci_err | PCI_STATUS_ERROR_BITS);

2083

sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);

2050

sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);

2084

}

2051

}

2085

2052

2086

if (status & Y2_IS_PCI_EXP) {

2053

if (status & Y2_IS_PCI_EXP) {

2087

/* PCI-Express uncorrectable Error occurred */

2054

/* PCI-Express uncorrectable Error occurred */

2088

u32 pex_err;

2055

u32 pex_err;

2089

2056

2090

pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);

2057

pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);

2091

2058

2092

if (net_ratelimit())

2059

if (net_ratelimit())

2093

printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",

2060

printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",

2094

pci_name(hw->pdev), pex_err);

2061

pci_name(hw->pdev), pex_err);

2095

2062

2096

/* clear the interrupt */

2063

/* clear the interrupt */

2097

sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);

2064

sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);

2098

sky2_pci_write32(hw, PEX_UNC_ERR_STAT,

2065

sky2_pci_write32(hw, PEX_UNC_ERR_STAT,

2099

0xffffffffUL);

2066

0xffffffffUL);

2100

sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);

2067

sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);

2101

2068

2102

if (pex_err & PEX_FATAL_ERRORS) {

2069

if (pex_err & PEX_FATAL_ERRORS) {

2103

u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);

2070

u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);

2104

hwmsk &= ~Y2_IS_PCI_EXP;

2071

hwmsk &= ~Y2_IS_PCI_EXP;

2105

sky2_write32(hw, B0_HWE_IMSK, hwmsk);

2072

sky2_write32(hw, B0_HWE_IMSK, hwmsk);

2106

}

2073

}

2107

}

2074

}

2108

2075

2109

if (status & Y2_HWE_L1_MASK)

2076

if (status & Y2_HWE_L1_MASK)

2110

sky2_hw_error(hw, 0, status);

2077

sky2_hw_error(hw, 0, status);

2111

status >>= 8;

2078

status >>= 8;

2112

if (status & Y2_HWE_L1_MASK)

2079

if (status & Y2_HWE_L1_MASK)

2113

sky2_hw_error(hw, 1, status);

2080

sky2_hw_error(hw, 1, status);

2114

}

2081

}

2115

2082

2116

static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)

2083

static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)

2117

{

2084

{

2118

struct net_device *dev = hw->dev[port];

2085

struct net_device *dev = hw->dev[port];

2119

struct sky2_port *sky2 = netdev_priv(dev);

2086

struct sky2_port *sky2 = netdev_priv(dev);

2120

u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));

2087

u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));

2121

2088

2122

if (netif_msg_intr(sky2))

2089

if (netif_msg_intr(sky2))

2123

printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",

2090

printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",

2124

dev->name, status);

2091

dev->name, status);

2125

2092

2126

if (status & GM_IS_RX_FF_OR) {

2093

if (status & GM_IS_RX_FF_OR) {

2127

++sky2->net_stats.rx_fifo_errors;

2094

++sky2->net_stats.rx_fifo_errors;

2128

sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);

2095

sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);

2129

}

2096

}

2130

2097

2131

if (status & GM_IS_TX_FF_UR) {

2098

if (status & GM_IS_TX_FF_UR) {

2132

++sky2->net_stats.tx_fifo_errors;

2099

++sky2->net_stats.tx_fifo_errors;

2133

sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);

2100

sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);

2134

}

2101

}

2135

}

2102

}

2136

2103

2137

static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)

2104

static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)

2138

{

2105

{

2139

struct net_device *dev = hw->dev[port];

2106

struct net_device *dev = hw->dev[port];

2140

struct sky2_port *sky2 = netdev_priv(dev);

2107

struct sky2_port *sky2 = netdev_priv(dev);

2141

2108

2142

hw->intr_mask &= ~(port == 0 ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);

2109

hw->intr_mask &= ~(port == 0 ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);

2143

sky2_write32(hw, B0_IMSK, hw->intr_mask);

2110

sky2_write32(hw, B0_IMSK, hw->intr_mask);

2144

2111

2145

schedule_work(&sky2->phy_task);

2112

schedule_work(&sky2->phy_task);

2146

}

2113

}

2147

2114

2148

static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)

2115

static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)

2149

{

2116

{

2150

struct sky2_hw *hw = dev_id;

2117

struct sky2_hw *hw = dev_id;

2151

struct net_device *dev0 = hw->dev[0];

2118

struct net_device *dev0 = hw->dev[0];

2152

u32 status;

2119

u32 status;

2153

2120

2154

status = sky2_read32(hw, B0_Y2_SP_ISRC2);

2121

status = sky2_read32(hw, B0_Y2_SP_ISRC2);

2155

if (status == 0 || status == ~0)

2122

if (status == 0 || status == ~0)

2156

return IRQ_NONE;

2123

return IRQ_NONE;

2157

2124

2158

spin_lock(&hw->hw_lock);

2125

spin_lock(&hw->hw_lock);

2159

if (status & Y2_IS_HW_ERR)

2126

if (status & Y2_IS_HW_ERR)

2160

sky2_hw_intr(hw);

2127

sky2_hw_intr(hw);

2161

2128

2162

/* Do NAPI for Rx and Tx status */

2129

/* Do NAPI for Rx and Tx status */

2163

if (status & Y2_IS_STAT_BMU) {

2130

if (status & Y2_IS_STAT_BMU) {

2164

hw->intr_mask &= ~Y2_IS_STAT_BMU;

2131

hw->intr_mask &= ~Y2_IS_STAT_BMU;

2165

sky2_write32(hw, B0_IMSK, hw->intr_mask);

2132

sky2_write32(hw, B0_IMSK, hw->intr_mask);

2166

2133

2167

if (likely(__netif_rx_schedule_prep(dev0))) {

2134

if (likely(__netif_rx_schedule_prep(dev0))) {

2168

prefetch(&hw->st_le[hw->st_idx]);

2135

prefetch(&hw->st_le[hw->st_idx]);

2169

__netif_rx_schedule(dev0);

2136

__netif_rx_schedule(dev0);

2170

}

2137

}

2171

}

2138

}

2172

2139

2173

if (status & Y2_IS_IRQ_PHY1)

2140

if (status & Y2_IS_IRQ_PHY1)

2174

sky2_phy_intr(hw, 0);

2141

sky2_phy_intr(hw, 0);

2175

2142

2176

if (status & Y2_IS_IRQ_PHY2)

2143

if (status & Y2_IS_IRQ_PHY2)

2177

sky2_phy_intr(hw, 1);

2144

sky2_phy_intr(hw, 1);

2178

2145

2179

if (status & Y2_IS_IRQ_MAC1)

2146

if (status & Y2_IS_IRQ_MAC1)

2180

sky2_mac_intr(hw, 0);

2147

sky2_mac_intr(hw, 0);

2181

2148

2182

if (status & Y2_IS_IRQ_MAC2)

2149

if (status & Y2_IS_IRQ_MAC2)

2183

sky2_mac_intr(hw, 1);

2150

sky2_mac_intr(hw, 1);

2184

2151

2185

sky2_write32(hw, B0_Y2_SP_ICR, 2);

2152

sky2_write32(hw, B0_Y2_SP_ICR, 2);

2186

2153

2187

spin_unlock(&hw->hw_lock);

2154

spin_unlock(&hw->hw_lock);

2188

2155

2189

return IRQ_HANDLED;

2156

return IRQ_HANDLED;

2190

}

2157

}

2191

2158

2192

#ifdef CONFIG_NET_POLL_CONTROLLER

2159

#ifdef CONFIG_NET_POLL_CONTROLLER

2193

static void sky2_netpoll(struct net_device *dev)

2160

static void sky2_netpoll(struct net_device *dev)

2194

{

2161

{

2195

struct sky2_port *sky2 = netdev_priv(dev);

2162

struct sky2_port *sky2 = netdev_priv(dev);

2196

2163

2197

sky2_intr(sky2->hw->pdev->irq, sky2->hw, NULL);

2164

sky2_intr(sky2->hw->pdev->irq, sky2->hw, NULL);

2198

}

2165

}

2199

#endif

2166

#endif

2200

2167

2201

/* Chip internal frequency for clock calculations */

2168

/* Chip internal frequency for clock calculations */

2202

static inline u32 sky2_mhz(const struct sky2_hw *hw)

2169

static inline u32 sky2_mhz(const struct sky2_hw *hw)

2203

{

2170

{

2204

switch (hw->chip_id) {

2171

switch (hw->chip_id) {

2205

case CHIP_ID_YUKON_EC:

2172

case CHIP_ID_YUKON_EC:

2206

case CHIP_ID_YUKON_EC_U:

2173

case CHIP_ID_YUKON_EC_U:

2207

return 125; /* 125 Mhz */

2174

return 125; /* 125 Mhz */

2208

case CHIP_ID_YUKON_FE:

2175

case CHIP_ID_YUKON_FE:

2209

return 100; /* 100 Mhz */

2176

return 100; /* 100 Mhz */

2210

default: /* YUKON_XL */

2177

default: /* YUKON_XL */

2211

return 156; /* 156 Mhz */

2178

return 156; /* 156 Mhz */

2212

}

2179

}

2213

}

2180

}

2214

2181

2215

static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)

2182

static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)

2216

{

2183

{

2217

return sky2_mhz(hw) * us;

2184

return sky2_mhz(hw) * us;

2218

}

2185

}

2219

2186

2220

static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)

2187

static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)

2221

{

2188

{

2222

return clk / sky2_mhz(hw);

2189

return clk / sky2_mhz(hw);

2223

}

2190

}

2224

2191

2225

2192

2226

static int sky2_reset(struct sky2_hw *hw)

2193

static int sky2_reset(struct sky2_hw *hw)

2227

{

2194

{

2228

u16 status;

2195

u16 status;

2229

u8 t8, pmd_type;

2196

u8 t8, pmd_type;

2230

int i;

2197

int i;

2231

2198

2232

sky2_write8(hw, B0_CTST, CS_RST_CLR);

2199

sky2_write8(hw, B0_CTST, CS_RST_CLR);

2233

2200

2234

hw->chip_id = sky2_read8(hw, B2_CHIP_ID);

2201

hw->chip_id = sky2_read8(hw, B2_CHIP_ID);

2235

if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {

2202

if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {

2236

printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",

2203

printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",

2237

pci_name(hw->pdev), hw->chip_id);

2204

pci_name(hw->pdev), hw->chip_id);

2238

return -EOPNOTSUPP;

2205

return -EOPNOTSUPP;

2239

}

2206

}

2240

2207

2208

hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;

2209

2210

/* This rev is really old, and requires untested workarounds */

2211

if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {

2212

printk(KERN_ERR PFX "%s: unsupported revision Yukon-%s (0x%x) rev %d\n",

2213

pci_name(hw->pdev), yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],

2214

hw->chip_id, hw->chip_rev);

2215

return -EOPNOTSUPP;

2216

}

2217

2218

/* This chip is new and not tested yet */

2219

if (hw->chip_id == CHIP_ID_YUKON_EC_U) {

2220

pr_info(PFX "%s: is a version of Yukon 2 chipset that has not been tested yet.\n",

2221

pci_name(hw->pdev));

2222

pr_info("Please report success/failure to maintainer <shemminger@osdl.org>\n");

2223

}

2224

2241

/* disable ASF */

2225

/* disable ASF */

2242

if (hw->chip_id <= CHIP_ID_YUKON_EC) {

2226

if (hw->chip_id <= CHIP_ID_YUKON_EC) {

2243

sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);

2227

sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);

2244

sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);

2228

sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);

2245

}

2229

}

2246

2230

2247

/* do a SW reset */

2231

/* do a SW reset */

2248

sky2_write8(hw, B0_CTST, CS_RST_SET);

2232

sky2_write8(hw, B0_CTST, CS_RST_SET);

2249

sky2_write8(hw, B0_CTST, CS_RST_CLR);

2233

sky2_write8(hw, B0_CTST, CS_RST_CLR);

2250

2234

2251

/* clear PCI errors, if any */

2235

/* clear PCI errors, if any */

2252

status = sky2_pci_read16(hw, PCI_STATUS);

2236

status = sky2_pci_read16(hw, PCI_STATUS);

2253

2237

2254

sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);

2238

sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);

2255

sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);

2239

sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);

2256

2240

2257

2241

2258

sky2_write8(hw, B0_CTST, CS_MRST_CLR);

2242

sky2_write8(hw, B0_CTST, CS_MRST_CLR);

2259

2243

2260

/* clear any PEX errors */

2244

/* clear any PEX errors */

2261

if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))

2245

if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))

2262

sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);

2246

sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);

2263

2247

2264

2248

2265

pmd_type = sky2_read8(hw, B2_PMD_TYP);

2249

pmd_type = sky2_read8(hw, B2_PMD_TYP);

2266

hw->copper = !(pmd_type == 'L' || pmd_type == 'S');

2250

hw->copper = !(pmd_type == 'L' || pmd_type == 'S');

2267

2251

2268

hw->ports = 1;

2252

hw->ports = 1;

2269

t8 = sky2_read8(hw, B2_Y2_HW_RES);

2253

t8 = sky2_read8(hw, B2_Y2_HW_RES);

2270

if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {

2254

if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {

2271

if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))

2255

if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))

2272

++hw->ports;

2256

++hw->ports;

2273

}

2257

}

2274

hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;

2275

2258

2276

sky2_set_power_state(hw, PCI_D0);

2259

sky2_set_power_state(hw, PCI_D0);

2277

2260

2278

for (i = 0; i < hw->ports; i++) {

2261

for (i = 0; i < hw->ports; i++) {

2279

sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);

2262

sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);

2280

sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);

2263

sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);

2281

}

2264

}

2282

2265

2283

sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);

2266

sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);

2284

2267

2285

/* Clear I2C IRQ noise */

2268

/* Clear I2C IRQ noise */

2286

sky2_write32(hw, B2_I2C_IRQ, 1);

2269

sky2_write32(hw, B2_I2C_IRQ, 1);

2287

2270

2288

/* turn off hardware timer (unused) */

2271

/* turn off hardware timer (unused) */

2289

sky2_write8(hw, B2_TI_CTRL, TIM_STOP);

2272

sky2_write8(hw, B2_TI_CTRL, TIM_STOP);

2290

sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);

2273

sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);

2291

2274

2292

sky2_write8(hw, B0_Y2LED, LED_STAT_ON);

2275

sky2_write8(hw, B0_Y2LED, LED_STAT_ON);

2293

2276

2294

/* Turn off descriptor polling */

2277

/* Turn off descriptor polling */

2295

sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);

2278

sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);

2296

2279

2297

/* Turn off receive timestamp */

2280

/* Turn off receive timestamp */

2298

sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);

2281

sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);

2299

sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);

2282

sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);

2300

2283

2301

/* enable the Tx Arbiters */

2284

/* enable the Tx Arbiters */

2302

for (i = 0; i < hw->ports; i++)

2285

for (i = 0; i < hw->ports; i++)

2303

sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);

2286

sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);

2304

2287

2305

/* Initialize ram interface */

2288

/* Initialize ram interface */

2306

for (i = 0; i < hw->ports; i++) {

2289

for (i = 0; i < hw->ports; i++) {

2307

sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);

2290

sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);

2308

2291

2309

sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);

2292

sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);

2310

sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);

2293

sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);

2311

sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);

2294

sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);

2312

sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);

2295

sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);

2313

sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);

2296

sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);

2314

sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);

2297

sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);

2315

sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);

2298

sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);

2316

sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);

2299

sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);

2317

sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);

2300

sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);

2318

sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);

2301

sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);

2319

sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);

2302

sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);

2320

sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);

2303

sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);

2321

}

2304

}

2322

2305

2323

sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);

2306

sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);

2324

2307

2325

for (i = 0; i < hw->ports; i++)

2308

for (i = 0; i < hw->ports; i++)

2326

sky2_phy_reset(hw, i);

2309

sky2_phy_reset(hw, i);

2327

2310

2328

memset(hw->st_le, 0, STATUS_LE_BYTES);

2311

memset(hw->st_le, 0, STATUS_LE_BYTES);

2329

hw->st_idx = 0;

2312

hw->st_idx = 0;

2330

2313

2331

sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);

2314

sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);

2332

sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);

2315

sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);

2333

2316

2334

sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);

2317

sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);

2335

sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);

2318

sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);

2336

2319

2337

/* Set the list last index */

2320

/* Set the list last index */

2338

sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);

2321

sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);

2339

2322

2340

/* These status setup values are copied from SysKonnect's driver */

2323

/* These status setup values are copied from SysKonnect's driver */

2341

if (is_ec_a1(hw)) {

2324

sky2_write16(hw, STAT_TX_IDX_TH, 10);

2342

/* WA for dev. #4.3 */

2325

sky2_write8(hw, STAT_FIFO_WM, 16);

2343

sky2_write16(hw, STAT_TX_IDX_TH, 0xfff); /* Tx Threshold */

2344

2326

2345

/* set Status-FIFO watermark */

2327

/* set Status-FIFO ISR watermark */

2346

sky2_write8(hw, STAT_FIFO_WM, 0x21); /* WA for dev. #4.18 */

2328

if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)

2329

sky2_write8(hw, STAT_FIFO_ISR_WM, 4);

2330

else

2331

sky2_write8(hw, STAT_FIFO_ISR_WM, 16);

2347

2332

2348

/* set Status-FIFO ISR watermark */

2333

sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));

2349

sky2_write8(hw, STAT_FIFO_ISR_WM, 0x07); /* WA for dev. #4.18 */

2334

sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 7));

2350

sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 10000));

2351

} else {

2352

sky2_write16(hw, STAT_TX_IDX_TH, 10);

2353

sky2_write8(hw, STAT_FIFO_WM, 16);

2354

2335

2355

/* set Status-FIFO ISR watermark */

2356

if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)

2357

sky2_write8(hw, STAT_FIFO_ISR_WM, 4);

2358

else

2359

sky2_write8(hw, STAT_FIFO_ISR_WM, 16);

2360

2361

sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));

2362

sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 7));

2363

}

2364

2365

/* enable status unit */

2336

/* enable status unit */

2366

sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);

2337

sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);

2367

2338

2368

sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);

2339

sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);

2369

sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);

2340

sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);

2370

sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);

2341

sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);

2371

2342

2372

return 0;

2343

return 0;

2373

}

2344

}

2374

2345

2375

static u32 sky2_supported_modes(const struct sky2_hw *hw)

2346

static u32 sky2_supported_modes(const struct sky2_hw *hw)

2376

{

2347

{

2377

u32 modes;

2348

u32 modes;

2378

if (hw->copper) {

2349

if (hw->copper) {

2379

modes = SUPPORTED_10baseT_Half

2350

modes = SUPPORTED_10baseT_Half

2380

| SUPPORTED_10baseT_Full

2351

| SUPPORTED_10baseT_Full

2381

| SUPPORTED_100baseT_Half

2352

| SUPPORTED_100baseT_Half

2382

| SUPPORTED_100baseT_Full

2353

| SUPPORTED_100baseT_Full

2383

| SUPPORTED_Autoneg | SUPPORTED_TP;

2354

| SUPPORTED_Autoneg | SUPPORTED_TP;

2384

2355

2385

if (hw->chip_id != CHIP_ID_YUKON_FE)

2356

if (hw->chip_id != CHIP_ID_YUKON_FE)

2386

modes |= SUPPORTED_1000baseT_Half

2357

modes |= SUPPORTED_1000baseT_Half

2387

| SUPPORTED_1000baseT_Full;

2358

| SUPPORTED_1000baseT_Full;

2388

} else

2359

} else

2389

modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE

2360

modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE

2390

| SUPPORTED_Autoneg;

2361

| SUPPORTED_Autoneg;

2391

return modes;

2362

return modes;

2392

}

2363

}

2393

2364

2394

static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)

2365

static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)

2395

{

2366

{

2396

struct sky2_port *sky2 = netdev_priv(dev);

2367

struct sky2_port *sky2 = netdev_priv(dev);

2397

struct sky2_hw *hw = sky2->hw;

2368

struct sky2_hw *hw = sky2->hw;

2398

2369

2399

ecmd->transceiver = XCVR_INTERNAL;

2370

ecmd->transceiver = XCVR_INTERNAL;

2400

ecmd->supported = sky2_supported_modes(hw);

2371

ecmd->supported = sky2_supported_modes(hw);

2401

ecmd->phy_address = PHY_ADDR_MARV;

2372

ecmd->phy_address = PHY_ADDR_MARV;

2402

if (hw->copper) {

2373

if (hw->copper) {

2403

ecmd->supported = SUPPORTED_10baseT_Half

2374

ecmd->supported = SUPPORTED_10baseT_Half

2404

| SUPPORTED_10baseT_Full

2375

| SUPPORTED_10baseT_Full

2405

| SUPPORTED_100baseT_Half

2376

| SUPPORTED_100baseT_Half

2406

| SUPPORTED_100baseT_Full

2377

| SUPPORTED_100baseT_Full

2407

| SUPPORTED_1000baseT_Half

2378

| SUPPORTED_1000baseT_Half

2408

| SUPPORTED_1000baseT_Full

2379

| SUPPORTED_1000baseT_Full

2409

| SUPPORTED_Autoneg | SUPPORTED_TP;

2380

| SUPPORTED_Autoneg | SUPPORTED_TP;

2410

ecmd->port = PORT_TP;

2381

ecmd->port = PORT_TP;

2411

} else

2382

} else

2412

ecmd->port = PORT_FIBRE;

2383

ecmd->port = PORT_FIBRE;

2413

2384

2414

ecmd->advertising = sky2->advertising;

2385

ecmd->advertising = sky2->advertising;

2415

ecmd->autoneg = sky2->autoneg;

2386

ecmd->autoneg = sky2->autoneg;

2416

ecmd->speed = sky2->speed;

2387

ecmd->speed = sky2->speed;

2417

ecmd->duplex = sky2->duplex;

2388

ecmd->duplex = sky2->duplex;

2418

return 0;

2389

return 0;

2419

}

2390

}

2420

2391

2421

static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)

2392

static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)

2422

{

2393

{

2423

struct sky2_port *sky2 = netdev_priv(dev);

2394

struct sky2_port *sky2 = netdev_priv(dev);

2424

const struct sky2_hw *hw = sky2->hw;

2395

const struct sky2_hw *hw = sky2->hw;

2425

u32 supported = sky2_supported_modes(hw);

2396

u32 supported = sky2_supported_modes(hw);

2426

2397

2427

if (ecmd->autoneg == AUTONEG_ENABLE) {

2398

if (ecmd->autoneg == AUTONEG_ENABLE) {

2428

ecmd->advertising = supported;

2399

ecmd->advertising = supported;

2429

sky2->duplex = -1;

2400

sky2->duplex = -1;

2430

sky2->speed = -1;

2401

sky2->speed = -1;

2431

} else {

2402

} else {

2432

u32 setting;

2403

u32 setting;

2433

2404

2434

switch (ecmd->speed) {

2405

switch (ecmd->speed) {

2435

case SPEED_1000:

2406

case SPEED_1000:

2436

if (ecmd->duplex == DUPLEX_FULL)

2407

if (ecmd->duplex == DUPLEX_FULL)

2437

setting = SUPPORTED_1000baseT_Full;

2408

setting = SUPPORTED_1000baseT_Full;

2438

else if (ecmd->duplex == DUPLEX_HALF)

2409

else if (ecmd->duplex == DUPLEX_HALF)

2439

setting = SUPPORTED_1000baseT_Half;

2410

setting = SUPPORTED_1000baseT_Half;

2440

else

2411

else

2441

return -EINVAL;

2412

return -EINVAL;

2442

break;

2413

break;

2443

case SPEED_100:

2414

case SPEED_100:

2444

if (ecmd->duplex == DUPLEX_FULL)

2415

if (ecmd->duplex == DUPLEX_FULL)

2445

setting = SUPPORTED_100baseT_Full;

2416

setting = SUPPORTED_100baseT_Full;

2446

else if (ecmd->duplex == DUPLEX_HALF)

2417

else if (ecmd->duplex == DUPLEX_HALF)

2447

setting = SUPPORTED_100baseT_Half;

2418

setting = SUPPORTED_100baseT_Half;

2448

else

2419

else

2449

return -EINVAL;

2420

return -EINVAL;

2450

break;

2421

break;

2451

2422

2452

case SPEED_10:

2423

case SPEED_10:

2453

if (ecmd->duplex == DUPLEX_FULL)

2424

if (ecmd->duplex == DUPLEX_FULL)

2454

setting = SUPPORTED_10baseT_Full;

2425

setting = SUPPORTED_10baseT_Full;

2455

else if (ecmd->duplex == DUPLEX_HALF)

2426

else if (ecmd->duplex == DUPLEX_HALF)

2456

setting = SUPPORTED_10baseT_Half;

2427

setting = SUPPORTED_10baseT_Half;

2457

else

2428

else

2458

return -EINVAL;

2429

return -EINVAL;

2459

break;

2430

break;

2460

default:

2431

default:

2461

return -EINVAL;

2432

return -EINVAL;

2462

}

2433

}

2463

2434

2464

if ((setting & supported) == 0)

2435

if ((setting & supported) == 0)

2465

return -EINVAL;

2436

return -EINVAL;

2466

2437

2467

sky2->speed = ecmd->speed;

2438

sky2->speed = ecmd->speed;

2468

sky2->duplex = ecmd->duplex;

2439

sky2->duplex = ecmd->duplex;

2469

}

2440

}

2470

2441

2471

sky2->autoneg = ecmd->autoneg;

2442

sky2->autoneg = ecmd->autoneg;

2472

sky2->advertising = ecmd->advertising;

2443

sky2->advertising = ecmd->advertising;

2473

2444

2474

if (netif_running(dev))

2445

if (netif_running(dev))

2475

sky2_phy_reinit(sky2);

2446

sky2_phy_reinit(sky2);

2476

2447

2477

return 0;

2448

return 0;

2478

}

2449

}

2479

2450

2480

static void sky2_get_drvinfo(struct net_device *dev,

2451

static void sky2_get_drvinfo(struct net_device *dev,

2481

struct ethtool_drvinfo *info)

2452

struct ethtool_drvinfo *info)

2482

{

2453

{

2483

struct sky2_port *sky2 = netdev_priv(dev);

2454

struct sky2_port *sky2 = netdev_priv(dev);

2484

2455

2485

strcpy(info->driver, DRV_NAME);

2456

strcpy(info->driver, DRV_NAME);

2486

strcpy(info->version, DRV_VERSION);

2457

strcpy(info->version, DRV_VERSION);

2487

strcpy(info->fw_version, "N/A");

2458

strcpy(info->fw_version, "N/A");

2488

strcpy(info->bus_info, pci_name(sky2->hw->pdev));

2459

strcpy(info->bus_info, pci_name(sky2->hw->pdev));

2489

}

2460

}

2490

2461

2491

static const struct sky2_stat {

2462

static const struct sky2_stat {

2492

char name[ETH_GSTRING_LEN];

2463

char name[ETH_GSTRING_LEN];

2493

u16 offset;

2464

u16 offset;

2494

} sky2_stats[] = {

2465

} sky2_stats[] = {

2495

{ "tx_bytes", GM_TXO_OK_HI },

2466

{ "tx_bytes", GM_TXO_OK_HI },

2496

{ "rx_bytes", GM_RXO_OK_HI },

2467

{ "rx_bytes", GM_RXO_OK_HI },

2497

{ "tx_broadcast", GM_TXF_BC_OK },

2468

{ "tx_broadcast", GM_TXF_BC_OK },

2498

{ "rx_broadcast", GM_RXF_BC_OK },

2469

{ "rx_broadcast", GM_RXF_BC_OK },

2499

{ "tx_multicast", GM_TXF_MC_OK },

2470

{ "tx_multicast", GM_TXF_MC_OK },

2500

{ "rx_multicast", GM_RXF_MC_OK },

2471

{ "rx_multicast", GM_RXF_MC_OK },

2501

{ "tx_unicast", GM_TXF_UC_OK },

2472

{ "tx_unicast", GM_TXF_UC_OK },

2502

{ "rx_unicast", GM_RXF_UC_OK },

2473

{ "rx_unicast", GM_RXF_UC_OK },

2503

{ "tx_mac_pause", GM_TXF_MPAUSE },

2474

{ "tx_mac_pause", GM_TXF_MPAUSE },

2504

{ "rx_mac_pause", GM_RXF_MPAUSE },

2475

{ "rx_mac_pause", GM_RXF_MPAUSE },

2505

{ "collisions", GM_TXF_SNG_COL },

2476

{ "collisions", GM_TXF_SNG_COL },

2506

{ "late_collision",GM_TXF_LAT_COL },

2477

{ "late_collision",GM_TXF_LAT_COL },

2507

{ "aborted", GM_TXF_ABO_COL },

2478

{ "aborted", GM_TXF_ABO_COL },

2508

{ "multi_collisions", GM_TXF_MUL_COL },

2479

{ "multi_collisions", GM_TXF_MUL_COL },

2509

{ "fifo_underrun", GM_TXE_FIFO_UR },

2480

{ "fifo_underrun", GM_TXE_FIFO_UR },

2510

{ "fifo_overflow", GM_RXE_FIFO_OV },

2481

{ "fifo_overflow", GM_RXE_FIFO_OV },

2511

{ "rx_toolong", GM_RXF_LNG_ERR },

2482

{ "rx_toolong", GM_RXF_LNG_ERR },

2512

{ "rx_jabber", GM_RXF_JAB_PKT },

2483

{ "rx_jabber", GM_RXF_JAB_PKT },

2513

{ "rx_runt", GM_RXE_FRAG },

2484

{ "rx_runt", GM_RXE_FRAG },

2514

{ "rx_too_long", GM_RXF_LNG_ERR },

2485

{ "rx_too_long", GM_RXF_LNG_ERR },

2515

{ "rx_fcs_error", GM_RXF_FCS_ERR },

2486

{ "rx_fcs_error", GM_RXF_FCS_ERR },

2516

};

2487

};

2517

2488

2518

static u32 sky2_get_rx_csum(struct net_device *dev)

2489

static u32 sky2_get_rx_csum(struct net_device *dev)

2519

{

2490

{

2520

struct sky2_port *sky2 = netdev_priv(dev);

2491

struct sky2_port *sky2 = netdev_priv(dev);

2521

2492

2522

return sky2->rx_csum;

2493

return sky2->rx_csum;

2523

}

2494

}

2524

2495

2525

static int sky2_set_rx_csum(struct net_device *dev, u32 data)

2496

static int sky2_set_rx_csum(struct net_device *dev, u32 data)

2526

{

2497

{

2527

struct sky2_port *sky2 = netdev_priv(dev);

2498

struct sky2_port *sky2 = netdev_priv(dev);

2528

2499

2529

sky2->rx_csum = data;

2500

sky2->rx_csum = data;

2530

2501

2531

sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),

2502

sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),

2532

data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);

2503

data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);

2533

2504

2534

return 0;

2505

return 0;

2535

}

2506

}

2536

2507

2537

static u32 sky2_get_msglevel(struct net_device *netdev)

2508

static u32 sky2_get_msglevel(struct net_device *netdev)

2538

{

2509

{

2539

struct sky2_port *sky2 = netdev_priv(netdev);

2510

struct sky2_port *sky2 = netdev_priv(netdev);

2540

return sky2->msg_enable;

2511

return sky2->msg_enable;

2541

}

2512

}

2542

2513

2543

static int sky2_nway_reset(struct net_device *dev)

2514

static int sky2_nway_reset(struct net_device *dev)

2544

{

2515

{

2545

struct sky2_port *sky2 = netdev_priv(dev);

2516

struct sky2_port *sky2 = netdev_priv(dev);

2546

2517

2547

if (sky2->autoneg != AUTONEG_ENABLE)

2518

if (sky2->autoneg != AUTONEG_ENABLE)

2548

return -EINVAL;

2519

return -EINVAL;

2549

2520

2550

sky2_phy_reinit(sky2);

2521

sky2_phy_reinit(sky2);

2551

2522

2552

return 0;

2523

return 0;

2553

}

2524

}

2554

2525

2555

static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)

2526

static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)

2556

{

2527

{

2557

struct sky2_hw *hw = sky2->hw;

2528

struct sky2_hw *hw = sky2->hw;

2558

unsigned port = sky2->port;

2529

unsigned port = sky2->port;

2559

int i;

2530

int i;

2560

2531

2561

data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32

2532

data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32

2562

| (u64) gma_read32(hw, port, GM_TXO_OK_LO);

2533

| (u64) gma_read32(hw, port, GM_TXO_OK_LO);

2563

data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32

2534

data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32

2564

| (u64) gma_read32(hw, port, GM_RXO_OK_LO);

2535

| (u64) gma_read32(hw, port, GM_RXO_OK_LO);

2565

2536

2566

for (i = 2; i < count; i++)

2537

for (i = 2; i < count; i++)

2567

data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);

2538

data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);

2568

}

2539

}

2569

2540

2570

static void sky2_set_msglevel(struct net_device *netdev, u32 value)

2541

static void sky2_set_msglevel(struct net_device *netdev, u32 value)

2571

{

2542

{

2572

struct sky2_port *sky2 = netdev_priv(netdev);

2543

struct sky2_port *sky2 = netdev_priv(netdev);

2573

sky2->msg_enable = value;

2544

sky2->msg_enable = value;

2574

}

2545

}

2575

2546

2576

static int sky2_get_stats_count(struct net_device *dev)

2547

static int sky2_get_stats_count(struct net_device *dev)

2577

{

2548

{

2578

return ARRAY_SIZE(sky2_stats);

2549

return ARRAY_SIZE(sky2_stats);

2579

}

2550

}

2580

2551

2581

static void sky2_get_ethtool_stats(struct net_device *dev,

2552

static void sky2_get_ethtool_stats(struct net_device *dev,

2582

struct ethtool_stats *stats, u64 * data)

2553

struct ethtool_stats *stats, u64 * data)

2583

{

2554

{

2584

struct sky2_port *sky2 = netdev_priv(dev);

2555

struct sky2_port *sky2 = netdev_priv(dev);

2585

2556

2586

sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));

2557

sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));

2587

}

2558

}

2588

2559

2589

static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)

2560

static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)

2590

{

2561

{

2591

int i;

2562

int i;

2592

2563

2593

switch (stringset) {

2564

switch (stringset) {

2594

case ETH_SS_STATS:

2565

case ETH_SS_STATS:

2595

for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)

2566

for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)

2596

memcpy(data + i * ETH_GSTRING_LEN,

2567

memcpy(data + i * ETH_GSTRING_LEN,

2597

sky2_stats[i].name, ETH_GSTRING_LEN);

2568

sky2_stats[i].name, ETH_GSTRING_LEN);

2598

break;

2569

break;

2599

}

2570

}

2600

}

2571

}

2601

2572

2602

/* Use hardware MIB variables for critical path statistics and

2573

/* Use hardware MIB variables for critical path statistics and

2603

* transmit feedback not reported at interrupt.

2574

* transmit feedback not reported at interrupt.

2604

* Other errors are accounted for in interrupt handler.

2575

* Other errors are accounted for in interrupt handler.

2605

*/

2576

*/

2606

static struct net_device_stats *sky2_get_stats(struct net_device *dev)

2577

static struct net_device_stats *sky2_get_stats(struct net_device *dev)

2607

{

2578

{

2608

struct sky2_port *sky2 = netdev_priv(dev);

2579

struct sky2_port *sky2 = netdev_priv(dev);

2609

u64 data[13];

2580

u64 data[13];

2610

2581

2611

sky2_phy_stats(sky2, data, ARRAY_SIZE(data));

2582

sky2_phy_stats(sky2, data, ARRAY_SIZE(data));

2612

2583

2613

sky2->net_stats.tx_bytes = data[0];

2584

sky2->net_stats.tx_bytes = data[0];

2614

sky2->net_stats.rx_bytes = data[1];

2585

sky2->net_stats.rx_bytes = data[1];

2615

sky2->net_stats.tx_packets = data[2] + data[4] + data[6];

2586

sky2->net_stats.tx_packets = data[2] + data[4] + data[6];

2616

sky2->net_stats.rx_packets = data[3] + data[5] + data[7];

2587

sky2->net_stats.rx_packets = data[3] + data[5] + data[7];

2617

sky2->net_stats.multicast = data[5] + data[7];

2588

sky2->net_stats.multicast = data[5] + data[7];

2618

sky2->net_stats.collisions = data[10];

2589

sky2->net_stats.collisions = data[10];

2619

sky2->net_stats.tx_aborted_errors = data[12];

2590

sky2->net_stats.tx_aborted_errors = data[12];

2620

2591

2621

return &sky2->net_stats;

2592

return &sky2->net_stats;

2622

}

2593

}

2623

2594

2624

static int sky2_set_mac_address(struct net_device *dev, void *p)

2595

static int sky2_set_mac_address(struct net_device *dev, void *p)

2625

{

2596

{

2626

struct sky2_port *sky2 = netdev_priv(dev);

2597

struct sky2_port *sky2 = netdev_priv(dev);

2627

struct sky2_hw *hw = sky2->hw;

2598

struct sky2_hw *hw = sky2->hw;

2628

unsigned port = sky2->port;

2599

unsigned port = sky2->port;

2629

const struct sockaddr *addr = p;

2600

const struct sockaddr *addr = p;

2630

2601

2631

if (!is_valid_ether_addr(addr->sa_data))

2602

if (!is_valid_ether_addr(addr->sa_data))

2632

return -EADDRNOTAVAIL;

2603

return -EADDRNOTAVAIL;

2633

2604

2634

memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);

2605

memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);

2635

memcpy_toio(hw->regs + B2_MAC_1 + port * 8,

2606

memcpy_toio(hw->regs + B2_MAC_1 + port * 8,

2636

dev->dev_addr, ETH_ALEN);

2607

dev->dev_addr, ETH_ALEN);

2637

memcpy_toio(hw->regs + B2_MAC_2 + port * 8,

2608

memcpy_toio(hw->regs + B2_MAC_2 + port * 8,

2638

dev->dev_addr, ETH_ALEN);

2609

dev->dev_addr, ETH_ALEN);

2639

2610

2640

/* virtual address for data */

2611

/* virtual address for data */

2641

gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);

2612

gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);

2642

2613

2643

/* physical address: used for pause frames */

2614

/* physical address: used for pause frames */

2644

gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);

2615

gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);

2645

2616

2646

return 0;

2617

return 0;

2647

}

2618

}

2648

2619

2649

static void sky2_set_multicast(struct net_device *dev)

2620

static void sky2_set_multicast(struct net_device *dev)

2650

{

2621

{

2651

struct sky2_port *sky2 = netdev_priv(dev);

2622

struct sky2_port *sky2 = netdev_priv(dev);

2652

struct sky2_hw *hw = sky2->hw;

2623

struct sky2_hw *hw = sky2->hw;

2653

unsigned port = sky2->port;

2624

unsigned port = sky2->port;

2654

struct dev_mc_list *list = dev->mc_list;

2625

struct dev_mc_list *list = dev->mc_list;

2655

u16 reg;

2626

u16 reg;

2656

u8 filter[8];

2627

u8 filter[8];

2657

2628

2658

memset(filter, 0, sizeof(filter));

2629

memset(filter, 0, sizeof(filter));

2659

2630

2660

reg = gma_read16(hw, port, GM_RX_CTRL);

2631

reg = gma_read16(hw, port, GM_RX_CTRL);

2661

reg |= GM_RXCR_UCF_ENA;

2632

reg |= GM_RXCR_UCF_ENA;

2662

2633

2663

if (dev->flags & IFF_PROMISC) /* promiscuous */

2634

if (dev->flags & IFF_PROMISC) /* promiscuous */

2664

reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);

2635

reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);

2665

else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */

2636

else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */

2666

memset(filter, 0xff, sizeof(filter));

2637

memset(filter, 0xff, sizeof(filter));

2667

else if (dev->mc_count == 0) /* no multicast */

2638

else if (dev->mc_count == 0) /* no multicast */

2668

reg &= ~GM_RXCR_MCF_ENA;

2639

reg &= ~GM_RXCR_MCF_ENA;

2669

else {

2640

else {

2670

int i;

2641

int i;

2671

reg |= GM_RXCR_MCF_ENA;

2642

reg |= GM_RXCR_MCF_ENA;

2672

2643

2673

for (i = 0; list && i < dev->mc_count; i++, list = list->next) {

2644

for (i = 0; list && i < dev->mc_count; i++, list = list->next) {

2674

u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;

2645

u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;

2675

filter[bit / 8] |= 1 << (bit % 8);

2646

filter[bit / 8] |= 1 << (bit % 8);

2676

}

2647

}

2677

}

2648

}

2678

2649

2679

gma_write16(hw, port, GM_MC_ADDR_H1,

2650

gma_write16(hw, port, GM_MC_ADDR_H1,

2680

(u16) filter[0] | ((u16) filter[1] << 8));

2651

(u16) filter[0] | ((u16) filter[1] << 8));

2681

gma_write16(hw, port, GM_MC_ADDR_H2,

2652

gma_write16(hw, port, GM_MC_ADDR_H2,

2682

(u16) filter[2] | ((u16) filter[3] << 8));

2653

(u16) filter[2] | ((u16) filter[3] << 8));

2683

gma_write16(hw, port, GM_MC_ADDR_H3,

2654

gma_write16(hw, port, GM_MC_ADDR_H3,

2684

(u16) filter[4] | ((u16) filter[5] << 8));

2655

(u16) filter[4] | ((u16) filter[5] << 8));

2685

gma_write16(hw, port, GM_MC_ADDR_H4,

2656

gma_write16(hw, port, GM_MC_ADDR_H4,

2686

(u16) filter[6] | ((u16) filter[7] << 8));

2657

(u16) filter[6] | ((u16) filter[7] << 8));

2687

2658

2688

gma_write16(hw, port, GM_RX_CTRL, reg);

2659

gma_write16(hw, port, GM_RX_CTRL, reg);

2689

}

2660

}

2690

2661

2691

/* Can have one global because blinking is controlled by

2662

/* Can have one global because blinking is controlled by

2692

* ethtool and that is always under RTNL mutex

2663

* ethtool and that is always under RTNL mutex

2693

*/

2664

*/

2694

static void sky2_led(struct sky2_hw *hw, unsigned port, int on)

2665

static void sky2_led(struct sky2_hw *hw, unsigned port, int on)

2695

{

2666

{

2696

u16 pg;

2667

u16 pg;

2697

2668

2698

switch (hw->chip_id) {

2669

switch (hw->chip_id) {

2699

case CHIP_ID_YUKON_XL:

2670

case CHIP_ID_YUKON_XL:

2700

pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);

2671

pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);

2701

gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);

2672

gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);

2702

gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,

2673

gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,

2703

on ? (PHY_M_LEDC_LOS_CTRL(1) |

2674

on ? (PHY_M_LEDC_LOS_CTRL(1) |

2704

PHY_M_LEDC_INIT_CTRL(7) |

2675

PHY_M_LEDC_INIT_CTRL(7) |

2705

PHY_M_LEDC_STA1_CTRL(7) |

2676

PHY_M_LEDC_STA1_CTRL(7) |

2706

PHY_M_LEDC_STA0_CTRL(7))

2677

PHY_M_LEDC_STA0_CTRL(7))

2707

: 0);

2678

: 0);

2708

2679

2709

gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);

2680

gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);

2710

break;

2681

break;

2711

2682

2712

default:

2683

default:

2713

gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);

2684

gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);

2714

gm_phy_write(hw, port, PHY_MARV_LED_OVER,

2685

gm_phy_write(hw, port, PHY_MARV_LED_OVER,

2715

on ? PHY_M_LED_MO_DUP(MO_LED_ON) |

2686

on ? PHY_M_LED_MO_DUP(MO_LED_ON) |

2716

PHY_M_LED_MO_10(MO_LED_ON) |

2687

PHY_M_LED_MO_10(MO_LED_ON) |

2717

PHY_M_LED_MO_100(MO_LED_ON) |

2688

PHY_M_LED_MO_100(MO_LED_ON) |

2718

PHY_M_LED_MO_1000(MO_LED_ON) |

2689

PHY_M_LED_MO_1000(MO_LED_ON) |

2719

PHY_M_LED_MO_RX(MO_LED_ON)

2690

PHY_M_LED_MO_RX(MO_LED_ON)

2720

: PHY_M_LED_MO_DUP(MO_LED_OFF) |

2691

: PHY_M_LED_MO_DUP(MO_LED_OFF) |

2721

PHY_M_LED_MO_10(MO_LED_OFF) |

2692

PHY_M_LED_MO_10(MO_LED_OFF) |

2722

PHY_M_LED_MO_100(MO_LED_OFF) |

2693

PHY_M_LED_MO_100(MO_LED_OFF) |

2723

PHY_M_LED_MO_1000(MO_LED_OFF) |

2694

PHY_M_LED_MO_1000(MO_LED_OFF) |

2724

PHY_M_LED_MO_RX(MO_LED_OFF));

2695

PHY_M_LED_MO_RX(MO_LED_OFF));

2725

2696

2726

}

2697

}

2727

}

2698

}

2728

2699

2729

/* blink LED's for finding board */

2700

/* blink LED's for finding board */

2730

static int sky2_phys_id(struct net_device *dev, u32 data)

2701

static int sky2_phys_id(struct net_device *dev, u32 data)

2731

{

2702

{

2732

struct sky2_port *sky2 = netdev_priv(dev);

2703

struct sky2_port *sky2 = netdev_priv(dev);

2733

struct sky2_hw *hw = sky2->hw;

2704

struct sky2_hw *hw = sky2->hw;

2734

unsigned port = sky2->port;

2705

unsigned port = sky2->port;

2735

u16 ledctrl, ledover = 0;

2706

u16 ledctrl, ledover = 0;

2736

long ms;

2707

long ms;

2737

int interrupted;

2708

int interrupted;

2738

int onoff = 1;

2709

int onoff = 1;

2739

2710

2740

if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))

2711

if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))

2741

ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);

2712

ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);

2742

else

2713

else

2743

ms = data * 1000;

2714

ms = data * 1000;

2744

2715

2745

/* save initial values */

2716

/* save initial values */

2746

down(&sky2->phy_sema);

2717

down(&sky2->phy_sema);

2747

if (hw->chip_id == CHIP_ID_YUKON_XL) {

2718

if (hw->chip_id == CHIP_ID_YUKON_XL) {

2748

u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);

2719

u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);

2749

gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);

2720

gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);

2750

ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);

2721

ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);

2751

gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);

2722

gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);

2752

} else {

2723

} else {

2753

ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);

2724

ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);

2754

ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);

2725

ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);

2755

}

2726

}

2756

2727

2757

interrupted = 0;

2728

interrupted = 0;

2758

while (!interrupted && ms > 0) {

2729

while (!interrupted && ms > 0) {

2759

sky2_led(hw, port, onoff);

2730

sky2_led(hw, port, onoff);

2760

onoff = !onoff;

2731

onoff = !onoff;

2761

2732

2762

up(&sky2->phy_sema);

2733

up(&sky2->phy_sema);

2763

interrupted = msleep_interruptible(250);

2734

interrupted = msleep_interruptible(250);

2764

down(&sky2->phy_sema);

2735

down(&sky2->phy_sema);

2765

2736

2766

ms -= 250;

2737

ms -= 250;

2767

}

2738

}

2768

2739

2769

/* resume regularly scheduled programming */

2740

/* resume regularly scheduled programming */

2770

if (hw->chip_id == CHIP_ID_YUKON_XL) {

2741

if (hw->chip_id == CHIP_ID_YUKON_XL) {

2771

u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);

2742

u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);

2772

gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);

2743

gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);

2773

gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);

2744

gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);

2774

gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);

2745

gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);

2775

} else {

2746

} else {

2776

gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);

2747

gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);

2777

gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);

2748

gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);

2778

}

2749

}

2779

up(&sky2->phy_sema);

2750

up(&sky2->phy_sema);

2780

2751

2781

return 0;

2752

return 0;

2782

}

2753

}

2783

2754

2784

static void sky2_get_pauseparam(struct net_device *dev,

2755

static void sky2_get_pauseparam(struct net_device *dev,

2785

struct ethtool_pauseparam *ecmd)

2756

struct ethtool_pauseparam *ecmd)

2786

{

2757

{

2787

struct sky2_port *sky2 = netdev_priv(dev);

2758

struct sky2_port *sky2 = netdev_priv(dev);

2788

2759

2789

ecmd->tx_pause = sky2->tx_pause;

2760

ecmd->tx_pause = sky2->tx_pause;

2790

ecmd->rx_pause = sky2->rx_pause;

2761

ecmd->rx_pause = sky2->rx_pause;

2791

ecmd->autoneg = sky2->autoneg;

2762

ecmd->autoneg = sky2->autoneg;

2792

}

2763

}

2793

2764

2794

static int sky2_set_pauseparam(struct net_device *dev,

2765

static int sky2_set_pauseparam(struct net_device *dev,

2795

struct ethtool_pauseparam *ecmd)

2766

struct ethtool_pauseparam *ecmd)

2796

{

2767

{

2797

struct sky2_port *sky2 = netdev_priv(dev);

2768

struct sky2_port *sky2 = netdev_priv(dev);

2798

int err = 0;

2769

int err = 0;

2799

2770

2800

sky2->autoneg = ecmd->autoneg;

2771

sky2->autoneg = ecmd->autoneg;

2801

sky2->tx_pause = ecmd->tx_pause != 0;

2772

sky2->tx_pause = ecmd->tx_pause != 0;

2802

sky2->rx_pause = ecmd->rx_pause != 0;

2773

sky2->rx_pause = ecmd->rx_pause != 0;

2803

2774

2804

sky2_phy_reinit(sky2);

2775

sky2_phy_reinit(sky2);

2805

2776

2806

return err;

2777

return err;

2807

}

2778

}

2808

2779

2809

#ifdef CONFIG_PM

2780

#ifdef CONFIG_PM

2810

static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)

2781

static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)

2811

{

2782

{

2812

struct sky2_port *sky2 = netdev_priv(dev);

2783

struct sky2_port *sky2 = netdev_priv(dev);

2813

2784

2814

wol->supported = WAKE_MAGIC;

2785

wol->supported = WAKE_MAGIC;

2815

wol->wolopts = sky2->wol ? WAKE_MAGIC : 0;

2786

wol->wolopts = sky2->wol ? WAKE_MAGIC : 0;

2816

}

2787

}

2817

2788

2818

static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)

2789

static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)

2819

{

2790

{

2820

struct sky2_port *sky2 = netdev_priv(dev);

2791

struct sky2_port *sky2 = netdev_priv(dev);

2821

struct sky2_hw *hw = sky2->hw;

2792

struct sky2_hw *hw = sky2->hw;

2822

2793

2823

if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)

2794

if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)

2824

return -EOPNOTSUPP;

2795

return -EOPNOTSUPP;

2825

2796

2826

sky2->wol = wol->wolopts == WAKE_MAGIC;

2797

sky2->wol = wol->wolopts == WAKE_MAGIC;

2827

2798

2828

if (sky2->wol) {

2799

if (sky2->wol) {

2829

memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);

2800

memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);

2830

2801

2831

sky2_write16(hw, WOL_CTRL_STAT,

2802

sky2_write16(hw, WOL_CTRL_STAT,

2832

WOL_CTL_ENA_PME_ON_MAGIC_PKT |

2803

WOL_CTL_ENA_PME_ON_MAGIC_PKT |

2833

WOL_CTL_ENA_MAGIC_PKT_UNIT);

2804

WOL_CTL_ENA_MAGIC_PKT_UNIT);

2834

} else

2805

} else

2835

sky2_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);

2806

sky2_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);

2836

2807

2837

return 0;

2808

return 0;

2838

}

2809

}

2839

#endif

2810

#endif

2840

2811

2841

static int sky2_get_coalesce(struct net_device *dev,

2812

static int sky2_get_coalesce(struct net_device *dev,

2842

struct ethtool_coalesce *ecmd)

2813

struct ethtool_coalesce *ecmd)

2843

{

2814

{

2844

struct sky2_port *sky2 = netdev_priv(dev);

2815

struct sky2_port *sky2 = netdev_priv(dev);

2845

struct sky2_hw *hw = sky2->hw;

2816

struct sky2_hw *hw = sky2->hw;

2846

2817

2847

if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)

2818

if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)

2848

ecmd->tx_coalesce_usecs = 0;

2819

ecmd->tx_coalesce_usecs = 0;

2849

else {

2820

else {

2850

u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);

2821

u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);

2851

ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);

2822

ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);

2852

}

2823

}

2853

ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);

2824

ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);

2854

2825

2855

if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)

2826

if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)

2856

ecmd->rx_coalesce_usecs = 0;

2827

ecmd->rx_coalesce_usecs = 0;

2857

else {

2828

else {

2858

u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);

2829

u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);

2859

ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);

2830

ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);

2860

}

2831

}

2861

ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);

2832

ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);

2862

2833

2863

if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)

2834

if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)

2864

ecmd->rx_coalesce_usecs_irq = 0;

2835

ecmd->rx_coalesce_usecs_irq = 0;

2865

else {

2836

else {

2866

u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);

2837

u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);

2867

ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);

2838

ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);

2868

}

2839

}

2869

2840

2870

ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);

2841

ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);

2871

2842

2872

return 0;

2843

return 0;

2873

}

2844

}

2874

2845

2875

/* Note: this affect both ports */

2846

/* Note: this affect both ports */

2876

static int sky2_set_coalesce(struct net_device *dev,

2847

static int sky2_set_coalesce(struct net_device *dev,

2877

struct ethtool_coalesce *ecmd)

2848

struct ethtool_coalesce *ecmd)

2878

{

2849

{

2879

struct sky2_port *sky2 = netdev_priv(dev);

2850

struct sky2_port *sky2 = netdev_priv(dev);

2880

struct sky2_hw *hw = sky2->hw;

2851

struct sky2_hw *hw = sky2->hw;

2881

const u32 tmin = sky2_clk2us(hw, 1);

2852

const u32 tmin = sky2_clk2us(hw, 1);

2882

const u32 tmax = 5000;

2853

const u32 tmax = 5000;

2883

2854

2884

if (ecmd->tx_coalesce_usecs != 0 &&

2855

if (ecmd->tx_coalesce_usecs != 0 &&

2885

(ecmd->tx_coalesce_usecs < tmin || ecmd->tx_coalesce_usecs > tmax))

2856

(ecmd->tx_coalesce_usecs < tmin || ecmd->tx_coalesce_usecs > tmax))

2886

return -EINVAL;

2857

return -EINVAL;

2887

2858

2888

if (ecmd->rx_coalesce_usecs != 0 &&

2859

if (ecmd->rx_coalesce_usecs != 0 &&

2889

(ecmd->rx_coalesce_usecs < tmin || ecmd->rx_coalesce_usecs > tmax))

2860

(ecmd->rx_coalesce_usecs < tmin || ecmd->rx_coalesce_usecs > tmax))

2890

return -EINVAL;

2861

return -EINVAL;

2891

2862

2892

if (ecmd->rx_coalesce_usecs_irq != 0 &&

2863

if (ecmd->rx_coalesce_usecs_irq != 0 &&

2893

(ecmd->rx_coalesce_usecs_irq < tmin || ecmd->rx_coalesce_usecs_irq > tmax))

2864

(ecmd->rx_coalesce_usecs_irq < tmin || ecmd->rx_coalesce_usecs_irq > tmax))

2894

return -EINVAL;

2865

return -EINVAL;

2895

2866

2896

if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)

2867

if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)

2897

return -EINVAL;

2868

return -EINVAL;

2898

if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)

2869

if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)

2899

return -EINVAL;

2870

return -EINVAL;

2900

if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)

2871

if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)

2901

return -EINVAL;

2872

return -EINVAL;

2902

2873

2903

if (ecmd->tx_coalesce_usecs == 0)

2874

if (ecmd->tx_coalesce_usecs == 0)

2904

sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);

2875

sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);

2905

else {

2876

else {

2906

sky2_write32(hw, STAT_TX_TIMER_INI,

2877

sky2_write32(hw, STAT_TX_TIMER_INI,

2907

sky2_us2clk(hw, ecmd->tx_coalesce_usecs));

2878

sky2_us2clk(hw, ecmd->tx_coalesce_usecs));

2908

sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);

2879

sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);

2909

}

2880

}

2910

sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);

2881

sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);

2911

2882

2912

if (ecmd->rx_coalesce_usecs == 0)

2883

if (ecmd->rx_coalesce_usecs == 0)

2913

sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);

2884

sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);

2914

else {

2885

else {

2915

sky2_write32(hw, STAT_LEV_TIMER_INI,

2886

sky2_write32(hw, STAT_LEV_TIMER_INI,

2916

sky2_us2clk(hw, ecmd->rx_coalesce_usecs));

2887

sky2_us2clk(hw, ecmd->rx_coalesce_usecs));

2917

sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);

2888

sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);

2918

}

2889

}

2919

sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);

2890

sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);

2920

2891

2921

if (ecmd->rx_coalesce_usecs_irq == 0)

2892

if (ecmd->rx_coalesce_usecs_irq == 0)

2922

sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);

2893

sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);

2923

else {

2894

else {

2924

sky2_write32(hw, STAT_ISR_TIMER_INI,

2895

sky2_write32(hw, STAT_ISR_TIMER_INI,

2925

sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));

2896

sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));

2926

sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);

2897

sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);

2927

}

2898

}

2928

sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);

2899

sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);

2929

return 0;

2900

return 0;

2930

}

2901

}

2931

2902

2932

static void sky2_get_ringparam(struct net_device *dev,

2903

static void sky2_get_ringparam(struct net_device *dev,

2933

struct ethtool_ringparam *ering)

2904

struct ethtool_ringparam *ering)

2934

{

2905

{

2935

struct sky2_port *sky2 = netdev_priv(dev);

2906

struct sky2_port *sky2 = netdev_priv(dev);

2936

2907

2937

ering->rx_max_pending = RX_MAX_PENDING;

2908

ering->rx_max_pending = RX_MAX_PENDING;

2938

ering->rx_mini_max_pending = 0;

2909

ering->rx_mini_max_pending = 0;

2939

ering->rx_jumbo_max_pending = 0;

2910

ering->rx_jumbo_max_pending = 0;

2940

ering->tx_max_pending = TX_RING_SIZE - 1;

2911

ering->tx_max_pending = TX_RING_SIZE - 1;

2941

2912

2942

ering->rx_pending = sky2->rx_pending;

2913

ering->rx_pending = sky2->rx_pending;

2943

ering->rx_mini_pending = 0;

2914

ering->rx_mini_pending = 0;

2944

ering->rx_jumbo_pending = 0;

2915

ering->rx_jumbo_pending = 0;

2945

ering->tx_pending = sky2->tx_pending;

2916

ering->tx_pending = sky2->tx_pending;

2946

}

2917

}

2947

2918

2948

static int sky2_set_ringparam(struct net_device *dev,

2919

static int sky2_set_ringparam(struct net_device *dev,

2949

struct ethtool_ringparam *ering)

2920

struct ethtool_ringparam *ering)

2950

{

2921

{

2951

struct sky2_port *sky2 = netdev_priv(dev);

2922

struct sky2_port *sky2 = netdev_priv(dev);

2952

int err = 0;

2923

int err = 0;

2953

2924

2954

if (ering->rx_pending > RX_MAX_PENDING ||

2925

if (ering->rx_pending > RX_MAX_PENDING ||

2955

ering->rx_pending < 8 ||

2926

ering->rx_pending < 8 ||

2956

ering->tx_pending < MAX_SKB_TX_LE ||

2927

ering->tx_pending < MAX_SKB_TX_LE ||

2957

ering->tx_pending > TX_RING_SIZE - 1)

2928

ering->tx_pending > TX_RING_SIZE - 1)

2958

return -EINVAL;

2929

return -EINVAL;

2959

2930

2960

if (netif_running(dev))

2931

if (netif_running(dev))

2961

sky2_down(dev);

2932

sky2_down(dev);

2962

2933

2963

sky2->rx_pending = ering->rx_pending;

2934

sky2->rx_pending = ering->rx_pending;

2964

sky2->tx_pending = ering->tx_pending;

2935

sky2->tx_pending = ering->tx_pending;

2965

2936

2966

if (netif_running(dev)) {

2937

if (netif_running(dev)) {

2967

err = sky2_up(dev);

2938

err = sky2_up(dev);

2968

if (err)

2939

if (err)

2969

dev_close(dev);

2940

dev_close(dev);

2970

else

2941

else

2971

sky2_set_multicast(dev);

2942

sky2_set_multicast(dev);

2972

}

2943

}

2973

2944

2974

return err;

2945

return err;

2975

}

2946

}

2976

2947

2977

static int sky2_get_regs_len(struct net_device *dev)

2948

static int sky2_get_regs_len(struct net_device *dev)

2978

{

2949

{

2979

return 0x4000;

2950

return 0x4000;

2980

}

2951

}

2981

2952

2982

/*

2953

/*

2983

* Returns copy of control register region

2954

* Returns copy of control register region

2984

* Note: access to the RAM address register set will cause timeouts.

2955

* Note: access to the RAM address register set will cause timeouts.

2985

*/

2956

*/

2986

static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,

2957

static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,

2987

void *p)

2958

void *p)

2988

{

2959

{

2989

const struct sky2_port *sky2 = netdev_priv(dev);

2960

const struct sky2_port *sky2 = netdev_priv(dev);

2990

const void __iomem *io = sky2->hw->regs;

2961

const void __iomem *io = sky2->hw->regs;

2991

2962

2992

BUG_ON(regs->len < B3_RI_WTO_R1);

2963

BUG_ON(regs->len < B3_RI_WTO_R1);

2993

regs->version = 1;

2964

regs->version = 1;

2994

memset(p, 0, regs->len);

2965

memset(p, 0, regs->len);

2995

2966

2996

memcpy_fromio(p, io, B3_RAM_ADDR);

2967

memcpy_fromio(p, io, B3_RAM_ADDR);

2997

2968

2998

memcpy_fromio(p + B3_RI_WTO_R1,

2969

memcpy_fromio(p + B3_RI_WTO_R1,

2999

io + B3_RI_WTO_R1,

2970

io + B3_RI_WTO_R1,

3000

regs->len - B3_RI_WTO_R1);

2971

regs->len - B3_RI_WTO_R1);

3001

}

2972

}

3002

2973

3003

static struct ethtool_ops sky2_ethtool_ops = {

2974

static struct ethtool_ops sky2_ethtool_ops = {

3004

.get_settings = sky2_get_settings,

2975

.get_settings = sky2_get_settings,

3005

.set_settings = sky2_set_settings,

2976

.set_settings = sky2_set_settings,

3006

.get_drvinfo = sky2_get_drvinfo,

2977

.get_drvinfo = sky2_get_drvinfo,

3007

.get_msglevel = sky2_get_msglevel,

2978

.get_msglevel = sky2_get_msglevel,

3008

.set_msglevel = sky2_set_msglevel,

2979

.set_msglevel = sky2_set_msglevel,

3009

.nway_reset = sky2_nway_reset,

2980

.nway_reset = sky2_nway_reset,

3010

.get_regs_len = sky2_get_regs_len,

2981

.get_regs_len = sky2_get_regs_len,

3011

.get_regs = sky2_get_regs,

2982

.get_regs = sky2_get_regs,

3012

.get_link = ethtool_op_get_link,

2983

.get_link = ethtool_op_get_link,

3013

.get_sg = ethtool_op_get_sg,

2984

.get_sg = ethtool_op_get_sg,

3014

.set_sg = ethtool_op_set_sg,

2985

.set_sg = ethtool_op_set_sg,

3015

.get_tx_csum = ethtool_op_get_tx_csum,

2986

.get_tx_csum = ethtool_op_get_tx_csum,

3016

.set_tx_csum = ethtool_op_set_tx_csum,

2987

.set_tx_csum = ethtool_op_set_tx_csum,

3017

.get_tso = ethtool_op_get_tso,

2988

.get_tso = ethtool_op_get_tso,

3018

.set_tso = ethtool_op_set_tso,

2989

.set_tso = ethtool_op_set_tso,

3019

.get_rx_csum = sky2_get_rx_csum,

2990

.get_rx_csum = sky2_get_rx_csum,

3020

.set_rx_csum = sky2_set_rx_csum,

2991

.set_rx_csum = sky2_set_rx_csum,

3021

.get_strings = sky2_get_strings,

2992

.get_strings = sky2_get_strings,

3022

.get_coalesce = sky2_get_coalesce,

2993

.get_coalesce = sky2_get_coalesce,

3023

.set_coalesce = sky2_set_coalesce,

2994

.set_coalesce = sky2_set_coalesce,

3024

.get_ringparam = sky2_get_ringparam,

2995

.get_ringparam = sky2_get_ringparam,

3025

.set_ringparam = sky2_set_ringparam,

2996

.set_ringparam = sky2_set_ringparam,

3026

.get_pauseparam = sky2_get_pauseparam,

2997

.get_pauseparam = sky2_get_pauseparam,

3027

.set_pauseparam = sky2_set_pauseparam,

2998

.set_pauseparam = sky2_set_pauseparam,

3028

#ifdef CONFIG_PM

2999

#ifdef CONFIG_PM

3029

.get_wol = sky2_get_wol,

3000

.get_wol = sky2_get_wol,

3030

.set_wol = sky2_set_wol,

3001

.set_wol = sky2_set_wol,

3031

#endif

3002

#endif

3032

.phys_id = sky2_phys_id,

3003

.phys_id = sky2_phys_id,

3033

.get_stats_count = sky2_get_stats_count,

3004

.get_stats_count = sky2_get_stats_count,

3034

.get_ethtool_stats = sky2_get_ethtool_stats,

3005

.get_ethtool_stats = sky2_get_ethtool_stats,

3035

.get_perm_addr = ethtool_op_get_perm_addr,

3006

.get_perm_addr = ethtool_op_get_perm_addr,

3036

};

3007

};

3037

3008

3038

/* Initialize network device */

3009

/* Initialize network device */

3039

static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,

3010

static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,

3040

unsigned port, int highmem)

3011

unsigned port, int highmem)

3041

{

3012

{

3042

struct sky2_port *sky2;

3013

struct sky2_port *sky2;

3043

struct net_device *dev = alloc_etherdev(sizeof(*sky2));

3014

struct net_device *dev = alloc_etherdev(sizeof(*sky2));

3044

3015

3045

if (!dev) {

3016

if (!dev) {

3046

printk(KERN_ERR "sky2 etherdev alloc failed");

3017

printk(KERN_ERR "sky2 etherdev alloc failed");

3047

return NULL;

3018

return NULL;

3048

}

3019

}

3049

3020

3050

SET_MODULE_OWNER(dev);

3021

SET_MODULE_OWNER(dev);

3051

SET_NETDEV_DEV(dev, &hw->pdev->dev);

3022

SET_NETDEV_DEV(dev, &hw->pdev->dev);

3052

dev->irq = hw->pdev->irq;

3023

dev->irq = hw->pdev->irq;

3053

dev->open = sky2_up;

3024

dev->open = sky2_up;

3054

dev->stop = sky2_down;

3025

dev->stop = sky2_down;

3055

dev->do_ioctl = sky2_ioctl;

3026

dev->do_ioctl = sky2_ioctl;

3056

dev->hard_start_xmit = sky2_xmit_frame;

3027

dev->hard_start_xmit = sky2_xmit_frame;

3057

dev->get_stats = sky2_get_stats;

3028

dev->get_stats = sky2_get_stats;

3058

dev->set_multicast_list = sky2_set_multicast;

3029

dev->set_multicast_list = sky2_set_multicast;

3059

dev->set_mac_address = sky2_set_mac_address;

3030

dev->set_mac_address = sky2_set_mac_address;

3060

dev->change_mtu = sky2_change_mtu;

3031

dev->change_mtu = sky2_change_mtu;

3061

SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);

3032

SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);

3062

dev->tx_timeout = sky2_tx_timeout;

3033

dev->tx_timeout = sky2_tx_timeout;

3063

dev->watchdog_timeo = TX_WATCHDOG;

3034

dev->watchdog_timeo = TX_WATCHDOG;

3064

if (port == 0)

3035

if (port == 0)

3065

dev->poll = sky2_poll;

3036

dev->poll = sky2_poll;

3066

dev->weight = NAPI_WEIGHT;

3037

dev->weight = NAPI_WEIGHT;

3067

#ifdef CONFIG_NET_POLL_CONTROLLER

3038

#ifdef CONFIG_NET_POLL_CONTROLLER

3068

dev->poll_controller = sky2_netpoll;

3039

dev->poll_controller = sky2_netpoll;

3069

#endif

3040

#endif

3070

3041

3071

sky2 = netdev_priv(dev);

3042

sky2 = netdev_priv(dev);

3072

sky2->netdev = dev;

3043

sky2->netdev = dev;

3073

sky2->hw = hw;

3044

sky2->hw = hw;

3074

sky2->msg_enable = netif_msg_init(debug, default_msg);

3045

sky2->msg_enable = netif_msg_init(debug, default_msg);

3075

3046

3076

spin_lock_init(&sky2->tx_lock);

3047

spin_lock_init(&sky2->tx_lock);

3077

/* Auto speed and flow control */

3048

/* Auto speed and flow control */

3078

sky2->autoneg = AUTONEG_ENABLE;

3049

sky2->autoneg = AUTONEG_ENABLE;

3079

sky2->tx_pause = 1;

3050

sky2->tx_pause = 1;

3080

sky2->rx_pause = 1;

3051

sky2->rx_pause = 1;

3081

sky2->duplex = -1;

3052

sky2->duplex = -1;

3082

sky2->speed = -1;

3053

sky2->speed = -1;

3083

sky2->advertising = sky2_supported_modes(hw);

3054

sky2->advertising = sky2_supported_modes(hw);

3084

3055

3085

/* Receive checksum disabled for Yukon XL

3056

/* Receive checksum disabled for Yukon XL

3086

* because of observed problems with incorrect

3057

* because of observed problems with incorrect

3087

* values when multiple packets are received in one interrupt

3058

* values when multiple packets are received in one interrupt

3088

*/

3059

*/

3089

sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);

3060

sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);

3090

3061

3091

INIT_WORK(&sky2->phy_task, sky2_phy_task, sky2);

3062

INIT_WORK(&sky2->phy_task, sky2_phy_task, sky2);

3092

init_MUTEX(&sky2->phy_sema);

3063

init_MUTEX(&sky2->phy_sema);

3093

sky2->tx_pending = TX_DEF_PENDING;

3064

sky2->tx_pending = TX_DEF_PENDING;

3094

sky2->rx_pending = is_ec_a1(hw) ? 8 : RX_DEF_PENDING;

3065

sky2->rx_pending = RX_DEF_PENDING;

3095

sky2->rx_bufsize = sky2_buf_size(ETH_DATA_LEN);

3066

sky2->rx_bufsize = sky2_buf_size(ETH_DATA_LEN);

3096

3067

3097

hw->dev[port] = dev;

3068

hw->dev[port] = dev;

3098

3069

3099

sky2->port = port;

3070

sky2->port = port;

3100

3071

3101

dev->features |= NETIF_F_LLTX;

3072

dev->features |= NETIF_F_LLTX;

3102

if (hw->chip_id != CHIP_ID_YUKON_EC_U)

3073

if (hw->chip_id != CHIP_ID_YUKON_EC_U)

3103

dev->features |= NETIF_F_TSO;

3074

dev->features |= NETIF_F_TSO;

3104

if (highmem)

3075

if (highmem)

3105

dev->features |= NETIF_F_HIGHDMA;

3076

dev->features |= NETIF_F_HIGHDMA;

3106

dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;

3077

dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;

3107

3078

3108

#ifdef SKY2_VLAN_TAG_USED

3079

#ifdef SKY2_VLAN_TAG_USED

3109

dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;

3080

dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;

3110

dev->vlan_rx_register = sky2_vlan_rx_register;

3081

dev->vlan_rx_register = sky2_vlan_rx_register;

3111

dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;

3082

dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;

3112

#endif

3083

#endif

3113

3084

3114

/* read the mac address */

3085

/* read the mac address */

3115

memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);

3086

memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);

3116

memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);

3087

memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);

3117

3088

3118

/* device is off until link detection */

3089

/* device is off until link detection */

3119

netif_carrier_off(dev);

3090

netif_carrier_off(dev);

3120

netif_stop_queue(dev);

3091

netif_stop_queue(dev);

3121

3092

3122

return dev;

3093

return dev;

3123

}

3094

}

3124

3095

3125

static void __devinit sky2_show_addr(struct net_device *dev)

3096

static void __devinit sky2_show_addr(struct net_device *dev)

3126

{

3097

{

3127

const struct sky2_port *sky2 = netdev_priv(dev);

3098

const struct sky2_port *sky2 = netdev_priv(dev);

3128

3099

3129

if (netif_msg_probe(sky2))

3100

if (netif_msg_probe(sky2))

3130

printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",

3101

printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",

3131

dev->name,

3102

dev->name,

3132

dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],

3103

dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],

3133

dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);

3104

dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);

3134

}

3105

}

3135

3106

3136

static int __devinit sky2_probe(struct pci_dev *pdev,

3107

static int __devinit sky2_probe(struct pci_dev *pdev,

3137

const struct pci_device_id *ent)

3108

const struct pci_device_id *ent)

3138

{

3109

{

3139

struct net_device *dev, *dev1 = NULL;

3110

struct net_device *dev, *dev1 = NULL;

3140

struct sky2_hw *hw;

3111

struct sky2_hw *hw;

3141

int err, pm_cap, using_dac = 0;

3112

int err, pm_cap, using_dac = 0;

3142

3113

3143

err = pci_enable_device(pdev);

3114

err = pci_enable_device(pdev);

3144

if (err) {

3115

if (err) {

3145

printk(KERN_ERR PFX "%s cannot enable PCI device\n",

3116

printk(KERN_ERR PFX "%s cannot enable PCI device\n",

3146

pci_name(pdev));

3117

pci_name(pdev));

3147

goto err_out;

3118

goto err_out;

3148

}

3119

}

3149

3120

3150

err = pci_request_regions(pdev, DRV_NAME);

3121

err = pci_request_regions(pdev, DRV_NAME);

3151

if (err) {

3122

if (err) {

3152

printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",

3123

printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",

3153

pci_name(pdev));

3124

pci_name(pdev));

3154

goto err_out;

3125

goto err_out;

3155

}

3126

}

3156

3127

3157

pci_set_master(pdev);

3128

pci_set_master(pdev);

3158

3129

3159

/* Find power-management capability. */

3130

/* Find power-management capability. */

3160

pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);

3131

pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);

3161

if (pm_cap == 0) {

3132

if (pm_cap == 0) {

3162

printk(KERN_ERR PFX "Cannot find PowerManagement capability, "

3133

printk(KERN_ERR PFX "Cannot find PowerManagement capability, "

3163

"aborting.\n");

3134

"aborting.\n");

3164

err = -EIO;

3135

err = -EIO;

3165

goto err_out_free_regions;

3136

goto err_out_free_regions;

3166

}

3137

}

3167

3138

3168

if (sizeof(dma_addr_t) > sizeof(u32) &&

3139

if (sizeof(dma_addr_t) > sizeof(u32) &&

3169

!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {

3140

!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {

3170

using_dac = 1;

3141

using_dac = 1;

3171

err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);

3142

err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);

3172

if (err < 0) {

3143

if (err < 0) {

3173

printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA "

3144

printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA "

3174

"for consistent allocations\n", pci_name(pdev));

3145

"for consistent allocations\n", pci_name(pdev));

3175

goto err_out_free_regions;

3146

goto err_out_free_regions;

3176

}

3147

}

3177

3148

3178

} else {

3149

} else {

3179

err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);

3150

err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);

3180

if (err) {

3151

if (err) {

3181

printk(KERN_ERR PFX "%s no usable DMA configuration\n",

3152

printk(KERN_ERR PFX "%s no usable DMA configuration\n",

3182

pci_name(pdev));

3153

pci_name(pdev));

3183

goto err_out_free_regions;

3154

goto err_out_free_regions;

3184

}

3155

}

3185

}

3156

}

3186

3157

3187

err = -ENOMEM;

3158

err = -ENOMEM;

3188

hw = kzalloc(sizeof(*hw), GFP_KERNEL);

3159

hw = kzalloc(sizeof(*hw), GFP_KERNEL);

3189

if (!hw) {

3160

if (!hw) {

3190

printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",

3161

printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",

3191

pci_name(pdev));

3162

pci_name(pdev));

3192

goto err_out_free_regions;

3163

goto err_out_free_regions;

3193

}

3164

}

3194

3165

3195

hw->pdev = pdev;

3166

hw->pdev = pdev;

3196

3167

3197

hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);

3168

hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);

3198

if (!hw->regs) {

3169

if (!hw->regs) {

3199

printk(KERN_ERR PFX "%s: cannot map device registers\n",

3170

printk(KERN_ERR PFX "%s: cannot map device registers\n",

3200

pci_name(pdev));

3171

pci_name(pdev));

3201

goto err_out_free_hw;

3172

goto err_out_free_hw;

3202

}

3173

}

3203

hw->pm_cap = pm_cap;

3174

hw->pm_cap = pm_cap;

3204

spin_lock_init(&hw->hw_lock);

3175

spin_lock_init(&hw->hw_lock);

3205

3176

3206

#ifdef __BIG_ENDIAN

3177

#ifdef __BIG_ENDIAN

3207

/* byte swap descriptors in hardware */

3178

/* byte swap descriptors in hardware */

3208

{

3179

{

3209

u32 reg;

3180

u32 reg;

3210

3181

3211

reg = sky2_pci_read32(hw, PCI_DEV_REG2);

3182

reg = sky2_pci_read32(hw, PCI_DEV_REG2);

3212

reg |= PCI_REV_DESC;

3183

reg |= PCI_REV_DESC;

3213

sky2_pci_write32(hw, PCI_DEV_REG2, reg);

3184

sky2_pci_write32(hw, PCI_DEV_REG2, reg);

3214

}

3185

}

3215

#endif

3186

#endif

3216

3187

3217

/* ring for status responses */

3188

/* ring for status responses */

3218

hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,

3189

hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,

3219

&hw->st_dma);

3190

&hw->st_dma);

3220

if (!hw->st_le)

3191

if (!hw->st_le)

3221

goto err_out_iounmap;

3192

goto err_out_iounmap;

3222

3193

3223

err = sky2_reset(hw);

3194

err = sky2_reset(hw);

3224

if (err)

3195

if (err)

3225

goto err_out_iounmap;

3196

goto err_out_iounmap;

3226

3197

3227

printk(KERN_INFO PFX "v%s addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n",

3198

printk(KERN_INFO PFX "v%s addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n",

3228

DRV_VERSION, pci_resource_start(pdev, 0), pdev->irq,

3199

DRV_VERSION, pci_resource_start(pdev, 0), pdev->irq,

3229

yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],

3200

yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],

3230

hw->chip_id, hw->chip_rev);

3201

hw->chip_id, hw->chip_rev);

3231

3202

3232

dev = sky2_init_netdev(hw, 0, using_dac);

3203

dev = sky2_init_netdev(hw, 0, using_dac);

3233

if (!dev)

3204

if (!dev)

3234

goto err_out_free_pci;

3205

goto err_out_free_pci;

3235

3206

3236

err = register_netdev(dev);

3207

err = register_netdev(dev);

3237

if (err) {

3208

if (err) {

3238

printk(KERN_ERR PFX "%s: cannot register net device\n",

3209

printk(KERN_ERR PFX "%s: cannot register net device\n",

3239

pci_name(pdev));

3210

pci_name(pdev));

3240

goto err_out_free_netdev;

3211

goto err_out_free_netdev;

3241

}

3212

}

3242

3213

3243

sky2_show_addr(dev);

3214

sky2_show_addr(dev);

3244

3215

3245

if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {

3216

if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {

3246

if (register_netdev(dev1) == 0)

3217

if (register_netdev(dev1) == 0)

3247

sky2_show_addr(dev1);

3218

sky2_show_addr(dev1);

3248

else {

3219

else {

3249

/* Failure to register second port need not be fatal */

3220

/* Failure to register second port need not be fatal */

3250

printk(KERN_WARNING PFX

3221

printk(KERN_WARNING PFX

3251

"register of second port failed\n");

3222

"register of second port failed\n");

3252

hw->dev[1] = NULL;

3223

hw->dev[1] = NULL;

3253

free_netdev(dev1);

3224

free_netdev(dev1);

3254

}

3225

}

3255

}

3226

}

3256

3227

3257

err = request_irq(pdev->irq, sky2_intr, SA_SHIRQ, DRV_NAME, hw);

3228

err = request_irq(pdev->irq, sky2_intr, SA_SHIRQ, DRV_NAME, hw);

3258

if (err) {

3229

if (err) {

3259

printk(KERN_ERR PFX "%s: cannot assign irq %d\n",

3230

printk(KERN_ERR PFX "%s: cannot assign irq %d\n",

3260

pci_name(pdev), pdev->irq);

3231

pci_name(pdev), pdev->irq);

3261

goto err_out_unregister;

3232

goto err_out_unregister;

3262

}

3233

}

3263

3234

3264

hw->intr_mask = Y2_IS_BASE;

3235

hw->intr_mask = Y2_IS_BASE;

3265

sky2_write32(hw, B0_IMSK, hw->intr_mask);

3236

sky2_write32(hw, B0_IMSK, hw->intr_mask);

3266

3237

3267

pci_set_drvdata(pdev, hw);

3238

pci_set_drvdata(pdev, hw);

3268

3239

3269

return 0;

3240

return 0;

3270

3241

3271

err_out_unregister:

3242

err_out_unregister:

3272

if (dev1) {

3243

if (dev1) {

3273

unregister_netdev(dev1);

3244

unregister_netdev(dev1);

3274

free_netdev(dev1);

3245

free_netdev(dev1);

3275

}

3246

}

3276

unregister_netdev(dev);

3247

unregister_netdev(dev);

3277

err_out_free_netdev:

3248

err_out_free_netdev:

3278

free_netdev(dev);

3249

free_netdev(dev);

3279

err_out_free_pci:

3250

err_out_free_pci:

3280

sky2_write8(hw, B0_CTST, CS_RST_SET);

3251

sky2_write8(hw, B0_CTST, CS_RST_SET);

3281

pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);

3252

pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);

3282

err_out_iounmap:

3253

err_out_iounmap:

3283

iounmap(hw->regs);

3254

iounmap(hw->regs);

3284

err_out_free_hw:

3255

err_out_free_hw:

3285

kfree(hw);

3256

kfree(hw);

3286

err_out_free_regions:

3257

err_out_free_regions:

3287

pci_release_regions(pdev);

3258

pci_release_regions(pdev);

3288

pci_disable_device(pdev);

3259

pci_disable_device(pdev);

3289

err_out:

3260

err_out:

3290

return err;

3261

return err;

3291

}

3262

}

3292

3263

3293

static void __devexit sky2_remove(struct pci_dev *pdev)

3264

static void __devexit sky2_remove(struct pci_dev *pdev)

3294

{

3265

{

3295

struct sky2_hw *hw = pci_get_drvdata(pdev);

3266

struct sky2_hw *hw = pci_get_drvdata(pdev);

3296

struct net_device *dev0, *dev1;

3267

struct net_device *dev0, *dev1;

3297

3268

3298

if (!hw)

3269

if (!hw)

3299

return;

3270

return;

3300

3271

3301

dev0 = hw->dev[0];

3272

dev0 = hw->dev[0];

3302

dev1 = hw->dev[1];

3273

dev1 = hw->dev[1];

3303

if (dev1)

3274

if (dev1)

3304

unregister_netdev(dev1);

3275

unregister_netdev(dev1);

3305

unregister_netdev(dev0);

3276

unregister_netdev(dev0);

3306

3277

3307

sky2_write32(hw, B0_IMSK, 0);

3278

sky2_write32(hw, B0_IMSK, 0);

3308

sky2_set_power_state(hw, PCI_D3hot);

3279

sky2_set_power_state(hw, PCI_D3hot);

3309

sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);

3280

sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);

3310

sky2_write8(hw, B0_CTST, CS_RST_SET);

3281

sky2_write8(hw, B0_CTST, CS_RST_SET);

3311

sky2_read8(hw, B0_CTST);

3282

sky2_read8(hw, B0_CTST);

3312

3283

3313

free_irq(pdev->irq, hw);

3284

free_irq(pdev->irq, hw);

3314

pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);

3285

pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);

3315

pci_release_regions(pdev);

3286

pci_release_regions(pdev);

3316

pci_disable_device(pdev);

3287

pci_disable_device(pdev);

3317

3288

3318

if (dev1)

3289

if (dev1)

3319

free_netdev(dev1);

3290

free_netdev(dev1);

3320

free_netdev(dev0);

3291

free_netdev(dev0);

3321

iounmap(hw->regs);

3292

iounmap(hw->regs);

3322

kfree(hw);

3293

kfree(hw);

3323

3294

3324

pci_set_drvdata(pdev, NULL);

3295

pci_set_drvdata(pdev, NULL);

3325

}

3296

}

3326

3297

3327

#ifdef CONFIG_PM

3298

#ifdef CONFIG_PM

3328

static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)

3299

static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)

3329

{

3300

{

3330

struct sky2_hw *hw = pci_get_drvdata(pdev);

3301

struct sky2_hw *hw = pci_get_drvdata(pdev);

3331

int i;

3302

int i;

3332

3303

3333

for (i = 0; i < 2; i++) {

3304

for (i = 0; i < 2; i++) {

3334

struct net_device *dev = hw->dev[i];

3305

struct net_device *dev = hw->dev[i];

3335

3306

3336

if (dev) {

3307

if (dev) {

3337

if (!netif_running(dev))

3308

if (!netif_running(dev))

3338

continue;

3309

continue;

3339

3310

3340

sky2_down(dev);

3311

sky2_down(dev);

3341

netif_device_detach(dev);

3312

netif_device_detach(dev);

3342

}

3313

}

3343

}

3314

}

3344

3315

3345

return sky2_set_power_state(hw, pci_choose_state(pdev, state));

3316

return sky2_set_power_state(hw, pci_choose_state(pdev, state));

3346

}

3317

}

3347

3318

3348

static int sky2_resume(struct pci_dev *pdev)

3319

static int sky2_resume(struct pci_dev *pdev)

3349

{

3320

{

3350

struct sky2_hw *hw = pci_get_drvdata(pdev);

3321

struct sky2_hw *hw = pci_get_drvdata(pdev);

3351

int i, err;

3322

int i, err;

3352

3323

3353

pci_restore_state(pdev);

3324

pci_restore_state(pdev);

3354

pci_enable_wake(pdev, PCI_D0, 0);

3325

pci_enable_wake(pdev, PCI_D0, 0);

3355

err = sky2_set_power_state(hw, PCI_D0);

3326

err = sky2_set_power_state(hw, PCI_D0);

3356

if (err)

3327

if (err)

3357

goto out;

3328

goto out;

3358

3329

3359

err = sky2_reset(hw);

3330

err = sky2_reset(hw);

3360

if (err)

3331

if (err)

3361

goto out;

3332

goto out;

3362

3333

3363

for (i = 0; i < 2; i++) {

3334

for (i = 0; i < 2; i++) {

3364

struct net_device *dev = hw->dev[i];

3335

struct net_device *dev = hw->dev[i];

3365

if (dev && netif_running(dev)) {

3336

if (dev && netif_running(dev)) {

3366

netif_device_attach(dev);

3337

netif_device_attach(dev);

3367

err = sky2_up(dev);

3338

err = sky2_up(dev);

3368

if (err) {

3339

if (err) {

3369

printk(KERN_ERR PFX "%s: could not up: %d\n",

3340

printk(KERN_ERR PFX "%s: could not up: %d\n",

3370

dev->name, err);

3341

dev->name, err);

3371

dev_close(dev);

3342

dev_close(dev);

3372

break;

3343

break;

3373

}

3344

}

3374

}

3345

}

3375

}

3346

}

3376

out:

3347

out:

3377

return err;

3348

return err;

3378

}

3349

}

3379

#endif

3350

#endif

3380

3351

3381

static struct pci_driver sky2_driver = {

3352

static struct pci_driver sky2_driver = {

3382

.name = DRV_NAME,

3353

.name = DRV_NAME,

3383

.id_table = sky2_id_table,

3354

.id_table = sky2_id_table,

3384

.probe = sky2_probe,

3355

.probe = sky2_probe,

3385

.remove = __devexit_p(sky2_remove),

3356

.remove = __devexit_p(sky2_remove),

3386

#ifdef CONFIG_PM

3357

#ifdef CONFIG_PM

3387

.suspend = sky2_suspend,

3358

.suspend = sky2_suspend,

3388

.resume = sky2_resume,

3359

.resume = sky2_resume,

3389

#endif

3360

#endif

GITLAB

Eric Lee / linux-smarc-t335x-v3.2

[PATCH] sky2: remove support for untested Yukon EC/rev 0

 /*
  * New driver for Marvell Yukon 2 chipset.
  * Based on earlier sk98lin, and skge driver.
  *
  * This driver intentionally does not support all the features
  * of the original driver such as link fail-over and link management because
  * those should be done at higher levels.
  *
  * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
  * (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  */
 #include <linux/config.h>
 #include <linux/crc32.h>
 #include <linux/kernel.h>
 #include <linux/version.h>
 #include <linux/module.h>
 #include <linux/netdevice.h>
 #include <linux/dma-mapping.h>
 #include <linux/etherdevice.h>
 #include <linux/ethtool.h>
 #include <linux/pci.h>
 #include <linux/ip.h>
 #include <linux/tcp.h>
 #include <linux/in.h>
 #include <linux/delay.h>
 #include <linux/workqueue.h>
 #include <linux/if_vlan.h>
 #include <linux/prefetch.h>
 #include <linux/mii.h>
 #include <asm/irq.h>
 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
 #define SKY2_VLAN_TAG_USED 1
 #endif
 #include "sky2.h"
 #define DRV_NAME		"sky2"
 #define DRV_VERSION		"0.15"
 #define PFX			DRV_NAME " "
 /*
  * The Yukon II chipset takes 64 bit command blocks (called list elements)
  * that are organized into three (receive, transmit, status) different rings
  * similar to Tigon3. A transmit can require several elements;
  * a receive requires one (or two if using 64 bit dma).
  */
-#define is_ec_a1(hw) \
-	unlikely((hw)->chip_id == CHIP_ID_YUKON_EC && \
-		 (hw)->chip_rev == CHIP_REV_YU_EC_A1)
 #define RX_LE_SIZE	    	512
 #define RX_LE_BYTES		(RX_LE_SIZE*sizeof(struct sky2_rx_le))
 #define RX_MAX_PENDING		(RX_LE_SIZE/2 - 2)
 #define RX_DEF_PENDING		RX_MAX_PENDING
 #define RX_SKB_ALIGN		8
 #define TX_RING_SIZE		512
 #define TX_DEF_PENDING		(TX_RING_SIZE - 1)
 #define TX_MIN_PENDING		64
 #define MAX_SKB_TX_LE		(4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
 #define STATUS_RING_SIZE	2048	/* 2 ports * (TX + 2*RX) */
 #define STATUS_LE_BYTES		(STATUS_RING_SIZE*sizeof(struct sky2_status_le))
 #define ETH_JUMBO_MTU		9000
 #define TX_WATCHDOG		(5 * HZ)
 #define NAPI_WEIGHT		64
 #define PHY_RETRIES		1000
 static const u32 default_msg =
     NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
     | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
     | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
 static int debug = -1;		/* defaults above */
 module_param(debug, int, 0);
 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
 static int copybreak __read_mostly = 256;
 module_param(copybreak, int, 0);
 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
 static const struct pci_device_id sky2_id_table[] = {
 	{ PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
 	{ PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
 	{ PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) },
 	{ PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) },
 	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
 	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
 	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
 	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
 	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
 	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
 	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
 	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
 	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
 	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
 	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },
 	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
 	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
 	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
 	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },
 	{ 0 }
 };
 MODULE_DEVICE_TABLE(pci, sky2_id_table);
 /* Avoid conditionals by using array */
 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
 /* This driver supports yukon2 chipset only */
 static const char *yukon2_name[] = {
 	"XL",		/* 0xb3 */
 	"EC Ultra", 	/* 0xb4 */
 	"UNKNOWN",	/* 0xb5 */
 	"EC",		/* 0xb6 */
 	"FE",		/* 0xb7 */
 };
 /* Access to external PHY */
 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
 {
 	int i;
 	gma_write16(hw, port, GM_SMI_DATA, val);
 	gma_write16(hw, port, GM_SMI_CTRL,
 		    GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
 	for (i = 0; i < PHY_RETRIES; i++) {
 		if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
 			return 0;
 		udelay(1);
 	}
 	printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
 	return -ETIMEDOUT;
 }
 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
 {
 	int i;
 	gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
 		    | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
 	for (i = 0; i < PHY_RETRIES; i++) {
 		if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
 			*val = gma_read16(hw, port, GM_SMI_DATA);
 			return 0;
 		}
 		udelay(1);
 	}
 	return -ETIMEDOUT;
 }
 static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
 {
 	u16 v;
 	if (__gm_phy_read(hw, port, reg, &v) != 0)
 		printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
 	return v;
 }
 static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
 {
 	u16 power_control;
 	u32 reg1;
 	int vaux;
 	int ret = 0;
 	pr_debug("sky2_set_power_state %d\n", state);
 	sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
 	power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_PMC);
 	vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
 		(power_control & PCI_PM_CAP_PME_D3cold);
 	power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_CTRL);
 	power_control |= PCI_PM_CTRL_PME_STATUS;
 	power_control &= ~(PCI_PM_CTRL_STATE_MASK);
 	switch (state) {
 	case PCI_D0:
 		/* switch power to VCC (WA for VAUX problem) */
 		sky2_write8(hw, B0_POWER_CTRL,
 			    PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
 		/* disable Core Clock Division, */
 		sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
 		if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
 			/* enable bits are inverted */
 			sky2_write8(hw, B2_Y2_CLK_GATE,
 				    Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
 				    Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
 				    Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
 		else
 			sky2_write8(hw, B2_Y2_CLK_GATE, 0);
 		/* Turn off phy power saving */
 		reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
 		reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
 		/* looks like this XL is back asswards .. */
 		if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) {
 			reg1 |= PCI_Y2_PHY1_COMA;
 			if (hw->ports > 1)
 				reg1 |= PCI_Y2_PHY2_COMA;
 		}
 		if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
 			sky2_pci_write32(hw, PCI_DEV_REG3, 0);
 			reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
 			reg1 &= P_ASPM_CONTROL_MSK;
 			sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
 			sky2_pci_write32(hw, PCI_DEV_REG5, 0);
 		}
 		sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
 		break;
 	case PCI_D3hot:
 	case PCI_D3cold:
 		/* Turn on phy power saving */
 		reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
 		if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
 			reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
 		else
 			reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
 		sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
 		if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
 			sky2_write8(hw, B2_Y2_CLK_GATE, 0);
 		else
 			/* enable bits are inverted */
 			sky2_write8(hw, B2_Y2_CLK_GATE,
 				    Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
 				    Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
 				    Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
 		/* switch power to VAUX */
 		if (vaux && state != PCI_D3cold)
 			sky2_write8(hw, B0_POWER_CTRL,
 				    (PC_VAUX_ENA | PC_VCC_ENA |
 				     PC_VAUX_ON | PC_VCC_OFF));
 		break;
 	default:
 		printk(KERN_ERR PFX "Unknown power state %d\n", state);
 		ret = -1;
 	}
 	sky2_pci_write16(hw, hw->pm_cap + PCI_PM_CTRL, power_control);
 	sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
 	return ret;
 }
 static void sky2_phy_reset(struct sky2_hw *hw, unsigned port)
 {
 	u16 reg;
 	/* disable all GMAC IRQ's */
 	sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
 	/* disable PHY IRQs */
 	gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
 	gma_write16(hw, port, GM_MC_ADDR_H1, 0);	/* clear MC hash */
 	gma_write16(hw, port, GM_MC_ADDR_H2, 0);
 	gma_write16(hw, port, GM_MC_ADDR_H3, 0);
 	gma_write16(hw, port, GM_MC_ADDR_H4, 0);
 	reg = gma_read16(hw, port, GM_RX_CTRL);
 	reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
 	gma_write16(hw, port, GM_RX_CTRL, reg);
 }
 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
 {
 	struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
 	u16 ctrl, ct1000, adv, pg, ledctrl, ledover;
 	if (sky2->autoneg == AUTONEG_ENABLE && hw->chip_id != CHIP_ID_YUKON_XL) {
 		u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
 		ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
 			   PHY_M_EC_MAC_S_MSK);
 		ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
 		if (hw->chip_id == CHIP_ID_YUKON_EC)
 			ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
 		else
 			ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
 		gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
 	}
 	ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
 	if (hw->copper) {
 		if (hw->chip_id == CHIP_ID_YUKON_FE) {
 			/* enable automatic crossover */
 			ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
 		} else {
 			/* disable energy detect */
 			ctrl &= ~PHY_M_PC_EN_DET_MSK;
 			/* enable automatic crossover */
 			ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
 			if (sky2->autoneg == AUTONEG_ENABLE &&
 			    hw->chip_id == CHIP_ID_YUKON_XL) {
 				ctrl &= ~PHY_M_PC_DSC_MSK;
 				ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
 			}
 		}
 		gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
 	} else {
 		/* workaround for deviation #4.88 (CRC errors) */
 		/* disable Automatic Crossover */
 		ctrl &= ~PHY_M_PC_MDIX_MSK;
 		gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
 		if (hw->chip_id == CHIP_ID_YUKON_XL) {
 			/* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
 			gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
 			ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
 			ctrl &= ~PHY_M_MAC_MD_MSK;
 			ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
 			gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
 			/* select page 1 to access Fiber registers */
 			gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
 		}
 	}
 	ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
 	if (sky2->autoneg == AUTONEG_DISABLE)
 		ctrl &= ~PHY_CT_ANE;
 	else
 		ctrl |= PHY_CT_ANE;
 	ctrl |= PHY_CT_RESET;
 	gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
 	ctrl = 0;
 	ct1000 = 0;
 	adv = PHY_AN_CSMA;
 	if (sky2->autoneg == AUTONEG_ENABLE) {
 		if (hw->copper) {
 			if (sky2->advertising & ADVERTISED_1000baseT_Full)
 				ct1000 |= PHY_M_1000C_AFD;
 			if (sky2->advertising & ADVERTISED_1000baseT_Half)
 				ct1000 |= PHY_M_1000C_AHD;
 			if (sky2->advertising & ADVERTISED_100baseT_Full)
 				adv |= PHY_M_AN_100_FD;
 			if (sky2->advertising & ADVERTISED_100baseT_Half)
 				adv |= PHY_M_AN_100_HD;
 			if (sky2->advertising & ADVERTISED_10baseT_Full)
 				adv |= PHY_M_AN_10_FD;
 			if (sky2->advertising & ADVERTISED_10baseT_Half)
 				adv |= PHY_M_AN_10_HD;
 		} else		/* special defines for FIBER (88E1011S only) */
 			adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
 		/* Set Flow-control capabilities */
 		if (sky2->tx_pause && sky2->rx_pause)
 			adv |= PHY_AN_PAUSE_CAP;	/* symmetric */
 		else if (sky2->rx_pause && !sky2->tx_pause)
 			adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;
 		else if (!sky2->rx_pause && sky2->tx_pause)
 			adv |= PHY_AN_PAUSE_ASYM;	/* local */
 		/* Restart Auto-negotiation */
 		ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
 	} else {
 		/* forced speed/duplex settings */
 		ct1000 = PHY_M_1000C_MSE;
 		if (sky2->duplex == DUPLEX_FULL)
 			ctrl |= PHY_CT_DUP_MD;
 		switch (sky2->speed) {
 		case SPEED_1000:
 			ctrl |= PHY_CT_SP1000;
 			break;
 		case SPEED_100:
 			ctrl |= PHY_CT_SP100;
 			break;
 		}
 		ctrl |= PHY_CT_RESET;
 	}
 	if (hw->chip_id != CHIP_ID_YUKON_FE)
 		gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
 	gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
 	gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
 	/* Setup Phy LED's */
 	ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
 	ledover = 0;
 	switch (hw->chip_id) {
 	case CHIP_ID_YUKON_FE:
 		/* on 88E3082 these bits are at 11..9 (shifted left) */
 		ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
 		ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
 		/* delete ACT LED control bits */
 		ctrl &= ~PHY_M_FELP_LED1_MSK;
 		/* change ACT LED control to blink mode */
 		ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
 		gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
 		break;
 	case CHIP_ID_YUKON_XL:
 		pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
 		/* select page 3 to access LED control register */
 		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
 		/* set LED Function Control register */
 		gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, (PHY_M_LEDC_LOS_CTRL(1) |	/* LINK/ACT */
 							   PHY_M_LEDC_INIT_CTRL(7) |	/* 10 Mbps */
 							   PHY_M_LEDC_STA1_CTRL(7) |	/* 100 Mbps */
 							   PHY_M_LEDC_STA0_CTRL(7)));	/* 1000 Mbps */
 		/* set Polarity Control register */
 		gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
 			     (PHY_M_POLC_LS1_P_MIX(4) |
 			      PHY_M_POLC_IS0_P_MIX(4) |
 			      PHY_M_POLC_LOS_CTRL(2) |
 			      PHY_M_POLC_INIT_CTRL(2) |
 			      PHY_M_POLC_STA1_CTRL(2) |
 			      PHY_M_POLC_STA0_CTRL(2)));
 		/* restore page register */
 		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
 		break;
 	default:
 		/* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
 		ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
 		/* turn off the Rx LED (LED_RX) */
 		ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
 	}
 	if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
 		/* apply fixes in PHY AFE */
 		gm_phy_write(hw, port, 22, 255);
 		/* increase differential signal amplitude in 10BASE-T */
 		gm_phy_write(hw, port, 24, 0xaa99);
 		gm_phy_write(hw, port, 23, 0x2011);
 		/* fix for IEEE A/B Symmetry failure in 1000BASE-T */
 		gm_phy_write(hw, port, 24, 0xa204);
 		gm_phy_write(hw, port, 23, 0x2002);
 		/* set page register to 0 */
 		gm_phy_write(hw, port, 22, 0);
 	} else {
 		gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
 		if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
 			/* turn on 100 Mbps LED (LED_LINK100) */
 			ledover |= PHY_M_LED_MO_100(MO_LED_ON);
 		}
 		if (ledover)
 			gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
 	}
 	/* Enable phy interrupt on auto-negotiation complete (or link up) */
 	if (sky2->autoneg == AUTONEG_ENABLE)
 		gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
 	else
 		gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
 }
 /* Force a renegotiation */
 static void sky2_phy_reinit(struct sky2_port *sky2)
 {
 	down(&sky2->phy_sema);
 	sky2_phy_init(sky2->hw, sky2->port);
 	up(&sky2->phy_sema);
 }
 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
 {
 	struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
 	u16 reg;
 	int i;
 	const u8 *addr = hw->dev[port]->dev_addr;
 	sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
 	sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
 	sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
 	if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
 		/* WA DEV_472 -- looks like crossed wires on port 2 */
 		/* clear GMAC 1 Control reset */
 		sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
 		do {
 			sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
 			sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
 		} while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
 			 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
 			 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
 	}
 	if (sky2->autoneg == AUTONEG_DISABLE) {
 		reg = gma_read16(hw, port, GM_GP_CTRL);
 		reg |= GM_GPCR_AU_ALL_DIS;
 		gma_write16(hw, port, GM_GP_CTRL, reg);
 		gma_read16(hw, port, GM_GP_CTRL);
 		switch (sky2->speed) {
 		case SPEED_1000:
 			reg &= ~GM_GPCR_SPEED_100;
 			reg |= GM_GPCR_SPEED_1000;
 			break;
 		case SPEED_100:
 			reg &= ~GM_GPCR_SPEED_1000;
 			reg |= GM_GPCR_SPEED_100;
 			break;
 		case SPEED_10:
 			reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
 			break;
 		}
 		if (sky2->duplex == DUPLEX_FULL)
 			reg |= GM_GPCR_DUP_FULL;
 	} else
 		reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
 	if (!sky2->tx_pause && !sky2->rx_pause) {
 		sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
 		reg |=
 		    GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
 	} else if (sky2->tx_pause && !sky2->rx_pause) {
 		/* disable Rx flow-control */
 		reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
 	}
 	gma_write16(hw, port, GM_GP_CTRL, reg);
 	sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
 	down(&sky2->phy_sema);
 	sky2_phy_init(hw, port);
 	up(&sky2->phy_sema);
 	/* MIB clear */
 	reg = gma_read16(hw, port, GM_PHY_ADDR);
 	gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
 	for (i = 0; i < GM_MIB_CNT_SIZE; i++)
 		gma_read16(hw, port, GM_MIB_CNT_BASE + 8 * i);
 	gma_write16(hw, port, GM_PHY_ADDR, reg);
 	/* transmit control */
 	gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
 	/* receive control reg: unicast + multicast + no FCS  */
 	gma_write16(hw, port, GM_RX_CTRL,
 		    GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
 	/* transmit flow control */
 	gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
 	/* transmit parameter */
 	gma_write16(hw, port, GM_TX_PARAM,
 		    TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
 		    TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
 		    TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
 		    TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
 	/* serial mode register */
 	reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
 		GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
 	if (hw->dev[port]->mtu > ETH_DATA_LEN)
 		reg |= GM_SMOD_JUMBO_ENA;
 	gma_write16(hw, port, GM_SERIAL_MODE, reg);
 	/* virtual address for data */
 	gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
 	/* physical address: used for pause frames */
 	gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
 	/* ignore counter overflows */
 	gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
 	gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
 	gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
 	/* Configure Rx MAC FIFO */
 	sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
 	sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
 		     GMF_OPER_ON | GMF_RX_F_FL_ON);
 	/* Flush Rx MAC FIFO on any flow control or error */
 	sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
 	/* Set threshold to 0xa (64 bytes)
 	 *  ASF disabled so no need to do WA dev #4.30
 	 */
 	sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
 	/* Configure Tx MAC FIFO */
 	sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
 	sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
 	if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
 		sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
 		sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
 		if (hw->dev[port]->mtu > ETH_DATA_LEN) {
 			/* set Tx GMAC FIFO Almost Empty Threshold */
 			sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
 			/* Disable Store & Forward mode for TX */
 			sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
 		}
 	}
 }
 /* Assign Ram Buffer allocation.
  * start and end are in units of 4k bytes
  * ram registers are in units of 64bit words
  */
 static void sky2_ramset(struct sky2_hw *hw, u16 q, u8 startk, u8 endk)
 {
 	u32 start, end;
 	start = startk * 4096/8;
 	end = (endk * 4096/8) - 1;
 	sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
 	sky2_write32(hw, RB_ADDR(q, RB_START), start);
 	sky2_write32(hw, RB_ADDR(q, RB_END), end);
 	sky2_write32(hw, RB_ADDR(q, RB_WP), start);
 	sky2_write32(hw, RB_ADDR(q, RB_RP), start);
 	if (q == Q_R1 || q == Q_R2) {
 		u32 space = (endk - startk) * 4096/8;
 		u32 tp = space - space/4;
 		/* On receive queue's set the thresholds
 		 * give receiver priority when > 3/4 full
 		 * send pause when down to 2K
 		 */
 		sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
 		sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
 		tp = space - 2048/8;
 		sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
 		sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
 	} else {
 		/* Enable store & forward on Tx queue's because
 		 * Tx FIFO is only 1K on Yukon
 		 */
 		sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
 	}
 	sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
 	sky2_read8(hw, RB_ADDR(q, RB_CTRL));
 }
 /* Setup Bus Memory Interface */
 static void sky2_qset(struct sky2_hw *hw, u16 q)
 {
 	sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
 	sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
 	sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
 	sky2_write32(hw, Q_ADDR(q, Q_WM),  BMU_WM_DEFAULT);
 }
 /* Setup prefetch unit registers. This is the interface between
  * hardware and driver list elements
  */
 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
 				      u64 addr, u32 last)
 {
 	sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
 	sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
 	sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
 	sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
 	sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
 	sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
 	sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
 }
 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
 {
 	struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
 	sky2->tx_prod = (sky2->tx_prod + 1) % TX_RING_SIZE;
 	return le;
 }
-/*
+/* Update chip's next pointer */
- * This is a workaround code taken from SysKonnect sk98lin driver
+static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
- * to deal with chip bug on Yukon EC rev 0 in the wraparound case.
- */
-static void sky2_put_idx(struct sky2_hw *hw, unsigned q,
-				u16 idx, u16 *last, u16 size)
 {
 	wmb();
-	if (is_ec_a1(hw) && idx < *last) {
+	sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
-		u16 hwget = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
-		if (hwget == 0) {
-			/* Start prefetching again */
-			sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 0xe0);
-			goto setnew;
-		}
-		if (hwget == size - 1) {
-			/* set watermark to one list element */
-			sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 8);
-			/* set put index to first list element */
-			sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), 0);
-		} else		/* have hardware go to end of list */
-			sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX),
-				     size - 1);
-	} else {
-setnew:
-		sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
-	}
-	*last = idx;
 	mmiowb();
 }
 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
 {
 	struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
 	sky2->rx_put = (sky2->rx_put + 1) % RX_LE_SIZE;
 	return le;
 }
 /* Return high part of DMA address (could be 32 or 64 bit) */
 static inline u32 high32(dma_addr_t a)
 {
 	return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
 }
 /* Build description to hardware about buffer */
 static void sky2_rx_add(struct sky2_port *sky2, dma_addr_t map)
 {
 	struct sky2_rx_le *le;
 	u32 hi = high32(map);
 	u16 len = sky2->rx_bufsize;
 	if (sky2->rx_addr64 != hi) {
 		le = sky2_next_rx(sky2);
 		le->addr = cpu_to_le32(hi);
 		le->ctrl = 0;
 		le->opcode = OP_ADDR64 | HW_OWNER;
 		sky2->rx_addr64 = high32(map + len);
 	}
 	le = sky2_next_rx(sky2);
 	le->addr = cpu_to_le32((u32) map);
 	le->length = cpu_to_le16(len);
 	le->ctrl = 0;
 	le->opcode = OP_PACKET | HW_OWNER;
 }
 /* Tell chip where to start receive checksum.
  * Actually has two checksums, but set both same to avoid possible byte
  * order problems.
  */
 static void rx_set_checksum(struct sky2_port *sky2)
 {
 	struct sky2_rx_le *le;
 	le = sky2_next_rx(sky2);
 	le->addr = (ETH_HLEN << 16) | ETH_HLEN;
 	le->ctrl = 0;
 	le->opcode = OP_TCPSTART | HW_OWNER;
 	sky2_write32(sky2->hw,
 		     Q_ADDR(rxqaddr[sky2->port], Q_CSR),
 		     sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
 }
 /*
  * The RX Stop command will not work for Yukon-2 if the BMU does not
  * reach the end of packet and since we can't make sure that we have
  * incoming data, we must reset the BMU while it is not doing a DMA
  * transfer. Since it is possible that the RX path is still active,
  * the RX RAM buffer will be stopped first, so any possible incoming
  * data will not trigger a DMA. After the RAM buffer is stopped, the
  * BMU is polled until any DMA in progress is ended and only then it
  * will be reset.
  */
 static void sky2_rx_stop(struct sky2_port *sky2)
 {
 	struct sky2_hw *hw = sky2->hw;
 	unsigned rxq = rxqaddr[sky2->port];
 	int i;
 	/* disable the RAM Buffer receive queue */
 	sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
 	for (i = 0; i < 0xffff; i++)
 		if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
 		    == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
 			goto stopped;
 	printk(KERN_WARNING PFX "%s: receiver stop failed\n",
 	       sky2->netdev->name);
 stopped:
 	sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
 	/* reset the Rx prefetch unit */
 	sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
 }
 /* Clean out receive buffer area, assumes receiver hardware stopped */
 static void sky2_rx_clean(struct sky2_port *sky2)
 {
 	unsigned i;
 	memset(sky2->rx_le, 0, RX_LE_BYTES);
 	for (i = 0; i < sky2->rx_pending; i++) {
 		struct ring_info *re = sky2->rx_ring + i;
 		if (re->skb) {
 			pci_unmap_single(sky2->hw->pdev,
 					 re->mapaddr, sky2->rx_bufsize,
 					 PCI_DMA_FROMDEVICE);
 			kfree_skb(re->skb);
 			re->skb = NULL;
 		}
 	}
 }
 /* Basic MII support */
 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
 {
 	struct mii_ioctl_data *data = if_mii(ifr);
 	struct sky2_port *sky2 = netdev_priv(dev);
 	struct sky2_hw *hw = sky2->hw;
 	int err = -EOPNOTSUPP;
 	if (!netif_running(dev))
 		return -ENODEV;	/* Phy still in reset */
 	switch(cmd) {
 	case SIOCGMIIPHY:
 		data->phy_id = PHY_ADDR_MARV;
 		/* fallthru */
 	case SIOCGMIIREG: {
 		u16 val = 0;
 		down(&sky2->phy_sema);
 		err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
 		up(&sky2->phy_sema);
 		data->val_out = val;
 		break;
 	}
 	case SIOCSMIIREG:
 		if (!capable(CAP_NET_ADMIN))
 			return -EPERM;
 		down(&sky2->phy_sema);
 		err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
 				   data->val_in);
 		up(&sky2->phy_sema);
 		break;
 	}
 	return err;
 }
 #ifdef SKY2_VLAN_TAG_USED
 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
 {
 	struct sky2_port *sky2 = netdev_priv(dev);
 	struct sky2_hw *hw = sky2->hw;
 	u16 port = sky2->port;
 	spin_lock_bh(&sky2->tx_lock);
 	sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
 	sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
 	sky2->vlgrp = grp;
 	spin_unlock_bh(&sky2->tx_lock);
 }
 static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
 {
 	struct sky2_port *sky2 = netdev_priv(dev);
 	struct sky2_hw *hw = sky2->hw;
 	u16 port = sky2->port;
 	spin_lock_bh(&sky2->tx_lock);
 	sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
 	sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
 	if (sky2->vlgrp)
 		sky2->vlgrp->vlan_devices[vid] = NULL;
 	spin_unlock_bh(&sky2->tx_lock);
 }
 #endif
 /*
  * It appears the hardware has a bug in the FIFO logic that
  * cause it to hang if the FIFO gets overrun and the receive buffer
  * is not aligned. ALso alloc_skb() won't align properly if slab
  * debugging is enabled.
  */
 static inline struct sk_buff *sky2_alloc_skb(unsigned int size, gfp_t gfp_mask)
 {
 	struct sk_buff *skb;
 	skb = alloc_skb(size + RX_SKB_ALIGN, gfp_mask);
 	if (likely(skb)) {
 		unsigned long p	= (unsigned long) skb->data;
 		skb_reserve(skb,
 			((p + RX_SKB_ALIGN - 1) & ~(RX_SKB_ALIGN - 1)) - p);
 	}
 	return skb;
 }
 /*
  * Allocate and setup receiver buffer pool.
  * In case of 64 bit dma, there are 2X as many list elements
  * available as ring entries
  * and need to reserve one list element so we don't wrap around.
  */
 static int sky2_rx_start(struct sky2_port *sky2)
 {
 	struct sky2_hw *hw = sky2->hw;
 	unsigned rxq = rxqaddr[sky2->port];
 	int i;
 	sky2->rx_put = sky2->rx_next = 0;
 	sky2_qset(hw, rxq);
 	if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
 		/* MAC Rx RAM Read is controlled by hardware */
 		sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
 	}
 	sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
 	rx_set_checksum(sky2);
 	for (i = 0; i < sky2->rx_pending; i++) {
 		struct ring_info *re = sky2->rx_ring + i;
 		re->skb = sky2_alloc_skb(sky2->rx_bufsize, GFP_KERNEL);
 		if (!re->skb)
 			goto nomem;
 		re->mapaddr = pci_map_single(hw->pdev, re->skb->data,
 					     sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
 		sky2_rx_add(sky2, re->mapaddr);
 	}
  	/* Truncate oversize frames */
  	sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), sky2->rx_bufsize - 8);
  	sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
 	/* Tell chip about available buffers */
 	sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
-	sky2->rx_last_put = sky2_read16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX));
 	return 0;
 nomem:
 	sky2_rx_clean(sky2);
 	return -ENOMEM;
 }
 /* Bring up network interface. */
 static int sky2_up(struct net_device *dev)
 {
 	struct sky2_port *sky2 = netdev_priv(dev);
 	struct sky2_hw *hw = sky2->hw;
 	unsigned port = sky2->port;
 	u32 ramsize, rxspace;
 	int err = -ENOMEM;
 	if (netif_msg_ifup(sky2))
 		printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
 	/* must be power of 2 */
 	sky2->tx_le = pci_alloc_consistent(hw->pdev,
 					   TX_RING_SIZE *
 					   sizeof(struct sky2_tx_le),
 					   &sky2->tx_le_map);
 	if (!sky2->tx_le)
 		goto err_out;
 	sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
 				GFP_KERNEL);
 	if (!sky2->tx_ring)
 		goto err_out;
 	sky2->tx_prod = sky2->tx_cons = 0;
 	sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
 					   &sky2->rx_le_map);
 	if (!sky2->rx_le)
 		goto err_out;
 	memset(sky2->rx_le, 0, RX_LE_BYTES);
 	sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct ring_info),
 				GFP_KERNEL);
 	if (!sky2->rx_ring)
 		goto err_out;
 	sky2_mac_init(hw, port);
 	/* Determine available ram buffer space (in 4K blocks).
 	 * Note: not sure about the FE setting below yet
 	 */
 	if (hw->chip_id == CHIP_ID_YUKON_FE)
 		ramsize = 4;
 	else
 		ramsize = sky2_read8(hw, B2_E_0);
 	/* Give transmitter one third (rounded up) */
 	rxspace = ramsize - (ramsize + 2) / 3;
 	sky2_ramset(hw, rxqaddr[port], 0, rxspace);
 	sky2_ramset(hw, txqaddr[port], rxspace, ramsize);
 	/* Make sure SyncQ is disabled */
 	sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
 		    RB_RST_SET);
 	sky2_qset(hw, txqaddr[port]);
 	/* Set almost empty threshold */
 	if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == 1)
 		sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
 	sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
 			   TX_RING_SIZE - 1);
 	err = sky2_rx_start(sky2);
 	if (err)
 		goto err_out;
 	/* Enable interrupts from phy/mac for port */
 	spin_lock_irq(&hw->hw_lock);
 	hw->intr_mask |= (port == 0) ? Y2_IS_PORT_1 : Y2_IS_PORT_2;
 	sky2_write32(hw, B0_IMSK, hw->intr_mask);
 	spin_unlock_irq(&hw->hw_lock);
 	return 0;
 err_out:
 	if (sky2->rx_le) {
 		pci_free_consistent(hw->pdev, RX_LE_BYTES,
 				    sky2->rx_le, sky2->rx_le_map);
 		sky2->rx_le = NULL;
 	}
 	if (sky2->tx_le) {
 		pci_free_consistent(hw->pdev,
 				    TX_RING_SIZE * sizeof(struct sky2_tx_le),
 				    sky2->tx_le, sky2->tx_le_map);
 		sky2->tx_le = NULL;
 	}
 	kfree(sky2->tx_ring);
 	kfree(sky2->rx_ring);
 	sky2->tx_ring = NULL;
 	sky2->rx_ring = NULL;
 	return err;
 }
 /* Modular subtraction in ring */
 static inline int tx_dist(unsigned tail, unsigned head)
 {
 	return (head - tail) % TX_RING_SIZE;
 }
 /* Number of list elements available for next tx */
 static inline int tx_avail(const struct sky2_port *sky2)
 {
 	return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
 }
 /* Estimate of number of transmit list elements required */
 static unsigned tx_le_req(const struct sk_buff *skb)
 {
 	unsigned count;
 	count = sizeof(dma_addr_t) / sizeof(u32);
 	count += skb_shinfo(skb)->nr_frags * count;
 	if (skb_shinfo(skb)->tso_size)
 		++count;
 	if (skb->ip_summed == CHECKSUM_HW)
 		++count;
 	return count;
 }
 /*
  * Put one packet in ring for transmit.
  * A single packet can generate multiple list elements, and
  * the number of ring elements will probably be less than the number
  * of list elements used.
  *
  * No BH disabling for tx_lock here (like tg3)
  */
 static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
 {
 	struct sky2_port *sky2 = netdev_priv(dev);
 	struct sky2_hw *hw = sky2->hw;
 	struct sky2_tx_le *le = NULL;
 	struct tx_ring_info *re;
 	unsigned i, len;
 	int avail;
 	dma_addr_t mapping;
 	u32 addr64;
 	u16 mss;
 	u8 ctrl;
 	/* No BH disabling for tx_lock here.  We are running in BH disabled
 	 * context and TX reclaim runs via poll inside of a software
 	 * interrupt, and no related locks in IRQ processing.
 	 */
 	if (!spin_trylock(&sky2->tx_lock))
 		return NETDEV_TX_LOCKED;
 	if (unlikely(tx_avail(sky2) < tx_le_req(skb))) {
 		/* There is a known but harmless race with lockless tx
 		 * and netif_stop_queue.
 		 */
 		if (!netif_queue_stopped(dev)) {
 			netif_stop_queue(dev);
 			if (net_ratelimit())
 				printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
 				       dev->name);
 		}
 		spin_unlock(&sky2->tx_lock);
 		return NETDEV_TX_BUSY;
 	}
 	if (unlikely(netif_msg_tx_queued(sky2)))
 		printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
 		       dev->name, sky2->tx_prod, skb->len);
 	len = skb_headlen(skb);
 	mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
 	addr64 = high32(mapping);
 	re = sky2->tx_ring + sky2->tx_prod;
 	/* Send high bits if changed or crosses boundary */
 	if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
 		le = get_tx_le(sky2);
 		le->tx.addr = cpu_to_le32(addr64);
 		le->ctrl = 0;
 		le->opcode = OP_ADDR64 | HW_OWNER;
 		sky2->tx_addr64 = high32(mapping + len);
 	}
 	/* Check for TCP Segmentation Offload */
 	mss = skb_shinfo(skb)->tso_size;
 	if (mss != 0) {
 		/* just drop the packet if non-linear expansion fails */
 		if (skb_header_cloned(skb) &&
 		    pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
 			dev_kfree_skb_any(skb);
 			goto out_unlock;
 		}
 		mss += ((skb->h.th->doff - 5) * 4);	/* TCP options */
 		mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
 		mss += ETH_HLEN;
 	}
 	if (mss != sky2->tx_last_mss) {
 		le = get_tx_le(sky2);
 		le->tx.tso.size = cpu_to_le16(mss);
 		le->tx.tso.rsvd = 0;
 		le->opcode = OP_LRGLEN | HW_OWNER;
 		le->ctrl = 0;
 		sky2->tx_last_mss = mss;
 	}
 	ctrl = 0;
 #ifdef SKY2_VLAN_TAG_USED
 	/* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
 	if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
 		if (!le) {
 			le = get_tx_le(sky2);
 			le->tx.addr = 0;
 			le->opcode = OP_VLAN|HW_OWNER;
 			le->ctrl = 0;
 		} else
 			le->opcode |= OP_VLAN;
 		le->length = cpu_to_be16(vlan_tx_tag_get(skb));
 		ctrl |= INS_VLAN;
 	}
 #endif
 	/* Handle TCP checksum offload */
 	if (skb->ip_summed == CHECKSUM_HW) {
 		u16 hdr = skb->h.raw - skb->data;
 		u16 offset = hdr + skb->csum;
 		ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
 		if (skb->nh.iph->protocol == IPPROTO_UDP)
 			ctrl |= UDPTCP;
 		le = get_tx_le(sky2);
 		le->tx.csum.start = cpu_to_le16(hdr);
 		le->tx.csum.offset = cpu_to_le16(offset);
 		le->length = 0;	/* initial checksum value */
 		le->ctrl = 1;	/* one packet */
 		le->opcode = OP_TCPLISW | HW_OWNER;
 	}
 	le = get_tx_le(sky2);
 	le->tx.addr = cpu_to_le32((u32) mapping);
 	le->length = cpu_to_le16(len);
 	le->ctrl = ctrl;
 	le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
 	/* Record the transmit mapping info */
 	re->skb = skb;
 	pci_unmap_addr_set(re, mapaddr, mapping);
 	for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
 		skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
 		struct tx_ring_info *fre;
 		mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
 				       frag->size, PCI_DMA_TODEVICE);
 		addr64 = high32(mapping);
 		if (addr64 != sky2->tx_addr64) {
 			le = get_tx_le(sky2);
 			le->tx.addr = cpu_to_le32(addr64);
 			le->ctrl = 0;
 			le->opcode = OP_ADDR64 | HW_OWNER;
 			sky2->tx_addr64 = addr64;
 		}
 		le = get_tx_le(sky2);
 		le->tx.addr = cpu_to_le32((u32) mapping);
 		le->length = cpu_to_le16(frag->size);
 		le->ctrl = ctrl;
 		le->opcode = OP_BUFFER | HW_OWNER;
 		fre = sky2->tx_ring
 		    + ((re - sky2->tx_ring) + i + 1) % TX_RING_SIZE;
 		pci_unmap_addr_set(fre, mapaddr, mapping);
 	}
 	re->idx = sky2->tx_prod;
 	le->ctrl |= EOP;
 	avail = tx_avail(sky2);
 	if (mss != 0 || avail < TX_MIN_PENDING) {
  		le->ctrl |= FRC_STAT;
 		if (avail <= MAX_SKB_TX_LE)
 			netif_stop_queue(dev);
 	}
-	sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod,
+	sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
-		     &sky2->tx_last_put, TX_RING_SIZE);
 out_unlock:
 	spin_unlock(&sky2->tx_lock);
 	dev->trans_start = jiffies;
 	return NETDEV_TX_OK;
 }
 /*
  * Free ring elements from starting at tx_cons until "done"
  *
  * NB: the hardware will tell us about partial completion of multi-part
  *     buffers; these are deferred until completion.
  */
 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
 {
 	struct net_device *dev = sky2->netdev;
 	struct pci_dev *pdev = sky2->hw->pdev;
 	u16 nxt, put;
 	unsigned i;
 	BUG_ON(done >= TX_RING_SIZE);
 	if (unlikely(netif_msg_tx_done(sky2)))
 		printk(KERN_DEBUG "%s: tx done, up to %u\n",
 		       dev->name, done);
 	for (put = sky2->tx_cons; put != done; put = nxt) {
 		struct tx_ring_info *re = sky2->tx_ring + put;
 		struct sk_buff *skb = re->skb;
   		nxt = re->idx;
 		BUG_ON(nxt >= TX_RING_SIZE);
 		prefetch(sky2->tx_ring + nxt);
 		/* Check for partial status */
 		if (tx_dist(put, done) < tx_dist(put, nxt))
 			break;
 		skb = re->skb;
 		pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
 				 skb_headlen(skb), PCI_DMA_TODEVICE);
 		for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
 			struct tx_ring_info *fre;
 			fre = sky2->tx_ring + (put + i + 1) % TX_RING_SIZE;
 			pci_unmap_page(pdev, pci_unmap_addr(fre, mapaddr),
   				       skb_shinfo(skb)->frags[i].size,
 				       PCI_DMA_TODEVICE);
 		}
 		dev_kfree_skb_any(skb);
 	}
 	sky2->tx_cons = put;
 	if (netif_queue_stopped(dev) && tx_avail(sky2) > MAX_SKB_TX_LE)
 		netif_wake_queue(dev);
 }
 /* Cleanup all untransmitted buffers, assume transmitter not running */
 static void sky2_tx_clean(struct sky2_port *sky2)
 {
 	spin_lock_bh(&sky2->tx_lock);
 	sky2_tx_complete(sky2, sky2->tx_prod);
 	spin_unlock_bh(&sky2->tx_lock);
 }
 /* Network shutdown */
 static int sky2_down(struct net_device *dev)
 {
 	struct sky2_port *sky2 = netdev_priv(dev);
 	struct sky2_hw *hw = sky2->hw;
 	unsigned port = sky2->port;
 	u16 ctrl;
 	/* Never really got started! */
 	if (!sky2->tx_le)
 		return 0;
 	if (netif_msg_ifdown(sky2))
 		printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
 	/* Stop more packets from being queued */
 	netif_stop_queue(dev);
 	/* Disable port IRQ */
 	spin_lock_irq(&hw->hw_lock);
 	hw->intr_mask &= ~((sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);
 	sky2_write32(hw, B0_IMSK, hw->intr_mask);
 	spin_unlock_irq(&hw->hw_lock);
 	flush_scheduled_work();
 	sky2_phy_reset(hw, port);
 	/* Stop transmitter */
 	sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
 	sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
 	sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
 		     RB_RST_SET | RB_DIS_OP_MD);
 	ctrl = gma_read16(hw, port, GM_GP_CTRL);
 	ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
 	gma_write16(hw, port, GM_GP_CTRL, ctrl);
 	sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
 	/* Workaround shared GMAC reset */
 	if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
 	      && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
 		sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
 	/* Disable Force Sync bit and Enable Alloc bit */
 	sky2_write8(hw, SK_REG(port, TXA_CTRL),
 		    TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
 	/* Stop Interval Timer and Limit Counter of Tx Arbiter */
 	sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
 	sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
 	/* Reset the PCI FIFO of the async Tx queue */
 	sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
 		     BMU_RST_SET | BMU_FIFO_RST);
 	/* Reset the Tx prefetch units */
 	sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
 		     PREF_UNIT_RST_SET);
 	sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
 	sky2_rx_stop(sky2);
 	sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
 	sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
 	/* turn off LED's */
 	sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
 	synchronize_irq(hw->pdev->irq);
 	sky2_tx_clean(sky2);
 	sky2_rx_clean(sky2);
 	pci_free_consistent(hw->pdev, RX_LE_BYTES,
 			    sky2->rx_le, sky2->rx_le_map);
 	kfree(sky2->rx_ring);
 	pci_free_consistent(hw->pdev,
 			    TX_RING_SIZE * sizeof(struct sky2_tx_le),
 			    sky2->tx_le, sky2->tx_le_map);
 	kfree(sky2->tx_ring);
 	sky2->tx_le = NULL;
 	sky2->rx_le = NULL;
 	sky2->rx_ring = NULL;
 	sky2->tx_ring = NULL;
 	return 0;
 }
 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
 {
 	if (!hw->copper)
 		return SPEED_1000;
 	if (hw->chip_id == CHIP_ID_YUKON_FE)
 		return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
 	switch (aux & PHY_M_PS_SPEED_MSK) {
 	case PHY_M_PS_SPEED_1000:
 		return SPEED_1000;
 	case PHY_M_PS_SPEED_100:
 		return SPEED_100;
 	default:
 		return SPEED_10;
 	}
 }
 static void sky2_link_up(struct sky2_port *sky2)
 {
 	struct sky2_hw *hw = sky2->hw;
 	unsigned port = sky2->port;
 	u16 reg;
 	/* Enable Transmit FIFO Underrun */
 	sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
 	reg = gma_read16(hw, port, GM_GP_CTRL);
 	if (sky2->autoneg == AUTONEG_DISABLE) {
 		reg |= GM_GPCR_AU_ALL_DIS;
 		/* Is write/read necessary?  Copied from sky2_mac_init */
 		gma_write16(hw, port, GM_GP_CTRL, reg);
 		gma_read16(hw, port, GM_GP_CTRL);
 		switch (sky2->speed) {
 		case SPEED_1000:
 			reg &= ~GM_GPCR_SPEED_100;
 			reg |= GM_GPCR_SPEED_1000;
 			break;
 		case SPEED_100:
 			reg &= ~GM_GPCR_SPEED_1000;
 			reg |= GM_GPCR_SPEED_100;
 			break;
 		case SPEED_10:
 			reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
 			break;
 		}
 	} else
 		reg &= ~GM_GPCR_AU_ALL_DIS;
 	if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE)
 		reg |= GM_GPCR_DUP_FULL;
 	/* enable Rx/Tx */
 	reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
 	gma_write16(hw, port, GM_GP_CTRL, reg);
 	gma_read16(hw, port, GM_GP_CTRL);
 	gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
 	netif_carrier_on(sky2->netdev);
 	netif_wake_queue(sky2->netdev);
 	/* Turn on link LED */
 	sky2_write8(hw, SK_REG(port, LNK_LED_REG),
 		    LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
 	if (hw->chip_id == CHIP_ID_YUKON_XL) {
 		u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
 		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
 		gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, PHY_M_LEDC_LOS_CTRL(1) |	/* LINK/ACT */
 			     PHY_M_LEDC_INIT_CTRL(sky2->speed ==
 						  SPEED_10 ? 7 : 0) |
 			     PHY_M_LEDC_STA1_CTRL(sky2->speed ==
 						  SPEED_100 ? 7 : 0) |
 			     PHY_M_LEDC_STA0_CTRL(sky2->speed ==
 						  SPEED_1000 ? 7 : 0));
 		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
 	}
 	if (netif_msg_link(sky2))
 		printk(KERN_INFO PFX
 		       "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
 		       sky2->netdev->name, sky2->speed,
 		       sky2->duplex == DUPLEX_FULL ? "full" : "half",
 		       (sky2->tx_pause && sky2->rx_pause) ? "both" :
 		       sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
 }
 static void sky2_link_down(struct sky2_port *sky2)
 {
 	struct sky2_hw *hw = sky2->hw;
 	unsigned port = sky2->port;
 	u16 reg;
 	gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
 	reg = gma_read16(hw, port, GM_GP_CTRL);
 	reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
 	gma_write16(hw, port, GM_GP_CTRL, reg);
 	gma_read16(hw, port, GM_GP_CTRL);	/* PCI post */
 	if (sky2->rx_pause && !sky2->tx_pause) {
 		/* restore Asymmetric Pause bit */
 		gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
 			     gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
 			     | PHY_M_AN_ASP);
 	}
 	netif_carrier_off(sky2->netdev);
 	netif_stop_queue(sky2->netdev);
 	/* Turn on link LED */
 	sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
 	if (netif_msg_link(sky2))
 		printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
 	sky2_phy_init(hw, port);
 }
 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
 {
 	struct sky2_hw *hw = sky2->hw;
 	unsigned port = sky2->port;
 	u16 lpa;
 	lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
 	if (lpa & PHY_M_AN_RF) {
 		printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
 		return -1;
 	}
 	if (hw->chip_id != CHIP_ID_YUKON_FE &&
 	    gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
 		printk(KERN_ERR PFX "%s: master/slave fault",
 		       sky2->netdev->name);
 		return -1;
 	}
 	if (!(aux & PHY_M_PS_SPDUP_RES)) {
 		printk(KERN_ERR PFX "%s: speed/duplex mismatch",
 		       sky2->netdev->name);
 		return -1;
 	}
 	sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
 	sky2->speed = sky2_phy_speed(hw, aux);
 	/* Pause bits are offset (9..8) */
 	if (hw->chip_id == CHIP_ID_YUKON_XL)
 		aux >>= 6;
 	sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
 	sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;
 	if ((sky2->tx_pause || sky2->rx_pause)
 	    && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF))
 		sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
 	else
 		sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
 	return 0;
 }
 /*
  * Interrupt from PHY are handled outside of interrupt context
  * because accessing phy registers requires spin wait which might
  * cause excess interrupt latency.
  */
 static void sky2_phy_task(void *arg)
 {
 	struct sky2_port *sky2 = arg;
 	struct sky2_hw *hw = sky2->hw;
 	u16 istatus, phystat;
 	down(&sky2->phy_sema);
 	istatus = gm_phy_read(hw, sky2->port, PHY_MARV_INT_STAT);
 	phystat = gm_phy_read(hw, sky2->port, PHY_MARV_PHY_STAT);
 	if (netif_msg_intr(sky2))
 		printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
 		       sky2->netdev->name, istatus, phystat);
 	if (istatus & PHY_M_IS_AN_COMPL) {
 		if (sky2_autoneg_done(sky2, phystat) == 0)
 			sky2_link_up(sky2);
 		goto out;
 	}
 	if (istatus & PHY_M_IS_LSP_CHANGE)
 		sky2->speed = sky2_phy_speed(hw, phystat);
 	if (istatus & PHY_M_IS_DUP_CHANGE)
 		sky2->duplex =
 		    (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
 	if (istatus & PHY_M_IS_LST_CHANGE) {
 		if (phystat & PHY_M_PS_LINK_UP)
 			sky2_link_up(sky2);
 		else
 			sky2_link_down(sky2);
 	}
 out:
 	up(&sky2->phy_sema);
 	spin_lock_irq(&hw->hw_lock);
 	hw->intr_mask |= (sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2;
 	sky2_write32(hw, B0_IMSK, hw->intr_mask);
 	spin_unlock_irq(&hw->hw_lock);
 }
 /* Transmit timeout is only called if we are running, carries is up
  * and tx queue is full (stopped).
  */
 static void sky2_tx_timeout(struct net_device *dev)
 {
 	struct sky2_port *sky2 = netdev_priv(dev);
 	struct sky2_hw *hw = sky2->hw;
 	unsigned txq = txqaddr[sky2->port];
 	u16 ridx;
 	/* Maybe we just missed an status interrupt */
 	spin_lock(&sky2->tx_lock);
 	ridx = sky2_read16(hw,
 			   sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX);
 	sky2_tx_complete(sky2, ridx);
 	spin_unlock(&sky2->tx_lock);
 	if (!netif_queue_stopped(dev)) {
 		if (net_ratelimit())
 			pr_info(PFX "transmit interrupt missed? recovered\n");
 		return;
 	}
 	if (netif_msg_timer(sky2))
 		printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
 	sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP);
 	sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
 	sky2_tx_clean(sky2);
 	sky2_qset(hw, txq);
 	sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1);
 }
 #define roundup(x, y)   ((((x)+((y)-1))/(y))*(y))
 /* Want receive buffer size to be multiple of 64 bits
  * and incl room for vlan and truncation
  */
 static inline unsigned sky2_buf_size(int mtu)
 {
 	return roundup(mtu + ETH_HLEN + VLAN_HLEN, 8) + 8;
 }
 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
 {
 	struct sky2_port *sky2 = netdev_priv(dev);
 	struct sky2_hw *hw = sky2->hw;
 	int err;
 	u16 ctl, mode;
 	if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
 		return -EINVAL;
 	if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
 		return -EINVAL;
 	if (!netif_running(dev)) {
 		dev->mtu = new_mtu;
 		return 0;
 	}
 	sky2_write32(hw, B0_IMSK, 0);
 	dev->trans_start = jiffies;	/* prevent tx timeout */
 	netif_stop_queue(dev);
 	netif_poll_disable(hw->dev[0]);
 	ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
 	gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
 	sky2_rx_stop(sky2);
 	sky2_rx_clean(sky2);
 	dev->mtu = new_mtu;
 	sky2->rx_bufsize = sky2_buf_size(new_mtu);
 	mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
 		GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
 	if (dev->mtu > ETH_DATA_LEN)
 		mode |= GM_SMOD_JUMBO_ENA;
 	gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
 	sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
 	err = sky2_rx_start(sky2);
 	sky2_write32(hw, B0_IMSK, hw->intr_mask);
 	if (err)
 		dev_close(dev);
 	else {
 		gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
 		netif_poll_enable(hw->dev[0]);
 		netif_wake_queue(dev);
 	}
 	return err;
 }
 /*
  * Receive one packet.
  * For small packets or errors, just reuse existing skb.
  * For larger packets, get new buffer.
  */
 static struct sk_buff *sky2_receive(struct sky2_port *sky2,
 				    u16 length, u32 status)
 {
 	struct ring_info *re = sky2->rx_ring + sky2->rx_next;
 	struct sk_buff *skb = NULL;
 	if (unlikely(netif_msg_rx_status(sky2)))
 		printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
 		       sky2->netdev->name, sky2->rx_next, status, length);
 	sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
 	prefetch(sky2->rx_ring + sky2->rx_next);
 	if (status & GMR_FS_ANY_ERR)
 		goto error;
 	if (!(status & GMR_FS_RX_OK))
 		goto resubmit;
 	if (length > sky2->netdev->mtu + ETH_HLEN)
 		goto oversize;
 	if (length < copybreak) {
 		skb = alloc_skb(length + 2, GFP_ATOMIC);
 		if (!skb)
 			goto resubmit;
 		skb_reserve(skb, 2);
 		pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr,
 					    length, PCI_DMA_FROMDEVICE);
 		memcpy(skb->data, re->skb->data, length);
 		skb->ip_summed = re->skb->ip_summed;
 		skb->csum = re->skb->csum;
 		pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr,
 					       length, PCI_DMA_FROMDEVICE);
 	} else {
 		struct sk_buff *nskb;
 		nskb = sky2_alloc_skb(sky2->rx_bufsize, GFP_ATOMIC);
 		if (!nskb)
 			goto resubmit;
 		skb = re->skb;
 		re->skb = nskb;
 		pci_unmap_single(sky2->hw->pdev, re->mapaddr,
 				 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
 		prefetch(skb->data);
 		re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,
 					     sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
 	}
 	skb_put(skb, length);
 resubmit:
 	re->skb->ip_summed = CHECKSUM_NONE;
 	sky2_rx_add(sky2, re->mapaddr);
 	/* Tell receiver about new buffers. */
-	sky2_put_idx(sky2->hw, rxqaddr[sky2->port], sky2->rx_put,
+	sky2_put_idx(sky2->hw, rxqaddr[sky2->port], sky2->rx_put);
-		     &sky2->rx_last_put, RX_LE_SIZE);
 	return skb;
 oversize:
 	++sky2->net_stats.rx_over_errors;
 	goto resubmit;
 error:
 	++sky2->net_stats.rx_errors;
 	if (netif_msg_rx_err(sky2) && net_ratelimit())
 		printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
 		       sky2->netdev->name, status, length);
 	if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
 		sky2->net_stats.rx_length_errors++;
 	if (status & GMR_FS_FRAGMENT)
 		sky2->net_stats.rx_frame_errors++;
 	if (status & GMR_FS_CRC_ERR)
 		sky2->net_stats.rx_crc_errors++;
 	if (status & GMR_FS_RX_FF_OV)
 		sky2->net_stats.rx_fifo_errors++;
 	goto resubmit;
 }
 /*
  * Check for transmit complete
  */
 #define TX_NO_STATUS	0xffff
 static void sky2_tx_check(struct sky2_hw *hw, int port, u16 last)
 {
 	if (last != TX_NO_STATUS) {
 		struct net_device *dev = hw->dev[port];
 		if (dev && netif_running(dev)) {
 			struct sky2_port *sky2 = netdev_priv(dev);
 			spin_lock(&sky2->tx_lock);
 			sky2_tx_complete(sky2, last);
 			spin_unlock(&sky2->tx_lock);
 		}
 	}
 }
 /*
  * Both ports share the same status interrupt, therefore there is only
  * one poll routine.
  */
 static int sky2_poll(struct net_device *dev0, int *budget)
 {
 	struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
 	unsigned int to_do = min(dev0->quota, *budget);
 	unsigned int work_done = 0;
 	u16 hwidx;
 	u16 tx_done[2] = { TX_NO_STATUS, TX_NO_STATUS };
 	sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
 	/*
 	 * Kick the STAT_LEV_TIMER_CTRL timer.
 	 * This fixes my hangs on Yukon-EC (0xb6) rev 1.
 	 * The if clause is there to start the timer only if it has been
 	 * configured correctly and not been disabled via ethtool.
 	 */
 	if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_START) {
 		sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
 		sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
 	}
 	hwidx = sky2_read16(hw, STAT_PUT_IDX);
 	BUG_ON(hwidx >= STATUS_RING_SIZE);
 	rmb();
 	while (hwidx != hw->st_idx) {
 		struct sky2_status_le *le  = hw->st_le + hw->st_idx;
 		struct net_device *dev;
 		struct sky2_port *sky2;
 		struct sk_buff *skb;
 		u32 status;
 		u16 length;
 		le = hw->st_le + hw->st_idx;
 		hw->st_idx = (hw->st_idx + 1) % STATUS_RING_SIZE;
 		prefetch(hw->st_le + hw->st_idx);
 		BUG_ON(le->link >= 2);
 		dev = hw->dev[le->link];
 		if (dev == NULL || !netif_running(dev))
 			continue;
 		sky2 = netdev_priv(dev);
 		status = le32_to_cpu(le->status);
 		length = le16_to_cpu(le->length);
 		switch (le->opcode & ~HW_OWNER) {
 		case OP_RXSTAT:
 			skb = sky2_receive(sky2, length, status);
 			if (!skb)
 				break;
 			skb->dev = dev;
 			skb->protocol = eth_type_trans(skb, dev);
 			dev->last_rx = jiffies;
 #ifdef SKY2_VLAN_TAG_USED
 			if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
 				vlan_hwaccel_receive_skb(skb,
 							 sky2->vlgrp,
 							 be16_to_cpu(sky2->rx_tag));
 			} else
 #endif
 				netif_receive_skb(skb);
 			if (++work_done >= to_do)
 				goto exit_loop;
 			break;
 #ifdef SKY2_VLAN_TAG_USED
 		case OP_RXVLAN:
 			sky2->rx_tag = length;
 			break;
 		case OP_RXCHKSVLAN:
 			sky2->rx_tag = length;
 			/* fall through */
 #endif
 		case OP_RXCHKS:
 			skb = sky2->rx_ring[sky2->rx_next].skb;
 			skb->ip_summed = CHECKSUM_HW;
 			skb->csum = le16_to_cpu(status);
 			break;
 		case OP_TXINDEXLE:
 			/* TX index reports status for both ports */
 			tx_done[0] = status & 0xffff;
 			tx_done[1] = ((status >> 24) & 0xff)
 				| (u16)(length & 0xf) << 8;
 			break;
 		default:
 			if (net_ratelimit())
 				printk(KERN_WARNING PFX
 				       "unknown status opcode 0x%x\n", le->opcode);
 			break;
 		}
 	}
 exit_loop:
 	sky2_tx_check(hw, 0, tx_done[0]);
 	sky2_tx_check(hw, 1, tx_done[1]);
 	if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_START) {
 		sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
 		sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
 	}
 	if (likely(work_done < to_do)) {
 		spin_lock_irq(&hw->hw_lock);
 		__netif_rx_complete(dev0);
 		hw->intr_mask |= Y2_IS_STAT_BMU;
 		sky2_write32(hw, B0_IMSK, hw->intr_mask);
 		spin_unlock_irq(&hw->hw_lock);
 		return 0;
 	} else {
 		*budget -= work_done;
 		dev0->quota -= work_done;
 		return 1;
 	}
 }
 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
 {
 	struct net_device *dev = hw->dev[port];
 	if (net_ratelimit())
 		printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
 		       dev->name, status);
 	if (status & Y2_IS_PAR_RD1) {
 		if (net_ratelimit())
 			printk(KERN_ERR PFX "%s: ram data read parity error\n",
 			       dev->name);
 		/* Clear IRQ */
 		sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
 	}
 	if (status & Y2_IS_PAR_WR1) {
 		if (net_ratelimit())
 			printk(KERN_ERR PFX "%s: ram data write parity error\n",
 			       dev->name);
 		sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
 	}
 	if (status & Y2_IS_PAR_MAC1) {
 		if (net_ratelimit())
 			printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
 		sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
 	}
 	if (status & Y2_IS_PAR_RX1) {
 		if (net_ratelimit())
 			printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
 		sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
 	}
 	if (status & Y2_IS_TCP_TXA1) {
 		if (net_ratelimit())
 			printk(KERN_ERR PFX "%s: TCP segmentation error\n",
 			       dev->name);
 		sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
 	}
 }
 static void sky2_hw_intr(struct sky2_hw *hw)
 {
 	u32 status = sky2_read32(hw, B0_HWE_ISRC);
 	if (status & Y2_IS_TIST_OV)
 		sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
 	if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
 		u16 pci_err;
 		pci_err = sky2_pci_read16(hw, PCI_STATUS);
 		if (net_ratelimit())
 			printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
 			       pci_name(hw->pdev), pci_err);
 		sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
 		sky2_pci_write16(hw, PCI_STATUS,
 				      pci_err | PCI_STATUS_ERROR_BITS);
 		sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
 	}
 	if (status & Y2_IS_PCI_EXP) {
 		/* PCI-Express uncorrectable Error occurred */
 		u32 pex_err;
 		pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
 		if (net_ratelimit())
 			printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
 			       pci_name(hw->pdev), pex_err);
 		/* clear the interrupt */
 		sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
 		sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
 				       0xffffffffUL);
 		sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
 		if (pex_err & PEX_FATAL_ERRORS) {
 			u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
 			hwmsk &= ~Y2_IS_PCI_EXP;
 			sky2_write32(hw, B0_HWE_IMSK, hwmsk);
 		}
 	}
 	if (status & Y2_HWE_L1_MASK)
 		sky2_hw_error(hw, 0, status);
 	status >>= 8;
 	if (status & Y2_HWE_L1_MASK)
 		sky2_hw_error(hw, 1, status);
 }
 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
 {
 	struct net_device *dev = hw->dev[port];
 	struct sky2_port *sky2 = netdev_priv(dev);
 	u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
 	if (netif_msg_intr(sky2))
 		printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
 		       dev->name, status);
 	if (status & GM_IS_RX_FF_OR) {
 		++sky2->net_stats.rx_fifo_errors;
 		sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
 	}
 	if (status & GM_IS_TX_FF_UR) {
 		++sky2->net_stats.tx_fifo_errors;
 		sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
 	}
 }
 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
 {
 	struct net_device *dev = hw->dev[port];
 	struct sky2_port *sky2 = netdev_priv(dev);
 	hw->intr_mask &= ~(port == 0 ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);
 	sky2_write32(hw, B0_IMSK, hw->intr_mask);
 	schedule_work(&sky2->phy_task);
 }
 static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
 {
 	struct sky2_hw *hw = dev_id;
 	struct net_device *dev0 = hw->dev[0];
 	u32 status;
 	status = sky2_read32(hw, B0_Y2_SP_ISRC2);
 	if (status == 0 || status == ~0)
 		return IRQ_NONE;
 	spin_lock(&hw->hw_lock);
 	if (status & Y2_IS_HW_ERR)
 		sky2_hw_intr(hw);
 	/* Do NAPI for Rx and Tx status */
 	if (status & Y2_IS_STAT_BMU) {
 		hw->intr_mask &= ~Y2_IS_STAT_BMU;
 		sky2_write32(hw, B0_IMSK, hw->intr_mask);
 		if (likely(__netif_rx_schedule_prep(dev0))) {
 			prefetch(&hw->st_le[hw->st_idx]);
 			__netif_rx_schedule(dev0);
 		}
 	}
 	if (status & Y2_IS_IRQ_PHY1)
 		sky2_phy_intr(hw, 0);
 	if (status & Y2_IS_IRQ_PHY2)
 		sky2_phy_intr(hw, 1);
 	if (status & Y2_IS_IRQ_MAC1)
 		sky2_mac_intr(hw, 0);
 	if (status & Y2_IS_IRQ_MAC2)
 		sky2_mac_intr(hw, 1);
 	sky2_write32(hw, B0_Y2_SP_ICR, 2);
 	spin_unlock(&hw->hw_lock);
 	return IRQ_HANDLED;
 }
 #ifdef CONFIG_NET_POLL_CONTROLLER
 static void sky2_netpoll(struct net_device *dev)
 {
 	struct sky2_port *sky2 = netdev_priv(dev);
 	sky2_intr(sky2->hw->pdev->irq, sky2->hw, NULL);
 }
 #endif
 /* Chip internal frequency for clock calculations */
 static inline u32 sky2_mhz(const struct sky2_hw *hw)
 {
 	switch (hw->chip_id) {
 	case CHIP_ID_YUKON_EC:
 	case CHIP_ID_YUKON_EC_U:
 		return 125;	/* 125 Mhz */
 	case CHIP_ID_YUKON_FE:
 		return 100;	/* 100 Mhz */
 	default:		/* YUKON_XL */
 		return 156;	/* 156 Mhz */
 	}
 }
 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
 {
 	return sky2_mhz(hw) * us;
 }
 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
 {
 	return clk / sky2_mhz(hw);
 }
 static int sky2_reset(struct sky2_hw *hw)
 {
 	u16 status;
 	u8 t8, pmd_type;
 	int i;
 	sky2_write8(hw, B0_CTST, CS_RST_CLR);
 	hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
 	if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
 		printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
 		       pci_name(hw->pdev), hw->chip_id);
 		return -EOPNOTSUPP;
 	}
+	hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
+	/* This rev is really old, and requires untested workarounds */
+	if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
+		printk(KERN_ERR PFX "%s: unsupported revision Yukon-%s (0x%x) rev %d\n",
+		       pci_name(hw->pdev), yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
+		       hw->chip_id, hw->chip_rev);
+		return -EOPNOTSUPP;
+	}
+	/* This chip is new and not tested yet */
+	if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
+		pr_info(PFX "%s: is a version of Yukon 2 chipset that has not been tested yet.\n",
+			pci_name(hw->pdev));
+		pr_info("Please report success/failure to maintainer <shemminger@osdl.org>\n");
+	}
 	/* disable ASF */
 	if (hw->chip_id <= CHIP_ID_YUKON_EC) {
 		sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
 		sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
 	}
 	/* do a SW reset */
 	sky2_write8(hw, B0_CTST, CS_RST_SET);
 	sky2_write8(hw, B0_CTST, CS_RST_CLR);
 	/* clear PCI errors, if any */
 	status = sky2_pci_read16(hw, PCI_STATUS);
 	sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
 	sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
 	sky2_write8(hw, B0_CTST, CS_MRST_CLR);
 	/* clear any PEX errors */
 	if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
 		sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
 	pmd_type = sky2_read8(hw, B2_PMD_TYP);
 	hw->copper = !(pmd_type == 'L' || pmd_type == 'S');
 	hw->ports = 1;
 	t8 = sky2_read8(hw, B2_Y2_HW_RES);
 	if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
 		if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
 			++hw->ports;
 	}
-	hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
 	sky2_set_power_state(hw, PCI_D0);
 	for (i = 0; i < hw->ports; i++) {
 		sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
 		sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
 	}
 	sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
 	/* Clear I2C IRQ noise */
 	sky2_write32(hw, B2_I2C_IRQ, 1);
 	/* turn off hardware timer (unused) */
 	sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
 	sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
 	sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
 	/* Turn off descriptor polling */
 	sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
 	/* Turn off receive timestamp */
 	sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
 	sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
 	/* enable the Tx Arbiters */
 	for (i = 0; i < hw->ports; i++)
 		sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
 	/* Initialize ram interface */
 	for (i = 0; i < hw->ports; i++) {
 		sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
 		sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
 		sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
 		sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
 		sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
 		sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
 		sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
 		sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
 		sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
 		sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
 		sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
 		sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
 		sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
 	}
 	sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
 	for (i = 0; i < hw->ports; i++)
 		sky2_phy_reset(hw, i);
 	memset(hw->st_le, 0, STATUS_LE_BYTES);
 	hw->st_idx = 0;
 	sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
 	sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
 	sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
 	sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
 	/* Set the list last index */
 	sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
 	/* These status setup values are copied from SysKonnect's driver */
-	if (is_ec_a1(hw)) {
+	sky2_write16(hw, STAT_TX_IDX_TH, 10);
-		/* WA for dev. #4.3 */
+	sky2_write8(hw, STAT_FIFO_WM, 16);
-		sky2_write16(hw, STAT_TX_IDX_TH, 0xfff);	/* Tx Threshold */
-		/* set Status-FIFO watermark */
+	/* set Status-FIFO ISR watermark */
-		sky2_write8(hw, STAT_FIFO_WM, 0x21);	/* WA for dev. #4.18 */
+	if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
+		sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
+	else
+		sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
-		/* set Status-FIFO ISR watermark */
+	sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
-		sky2_write8(hw, STAT_FIFO_ISR_WM, 0x07);	/* WA for dev. #4.18 */
+	sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 7));
-		sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 10000));
-	} else {
-		sky2_write16(hw, STAT_TX_IDX_TH, 10);
-		sky2_write8(hw, STAT_FIFO_WM, 16);
-		/* set Status-FIFO ISR watermark */
-		if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
-			sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
-		else
-			sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
-		sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
-		sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 7));
-	}
 	/* enable status unit */
 	sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
 	sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
 	sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
 	sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
 	return 0;
 }
 static u32 sky2_supported_modes(const struct sky2_hw *hw)
 {
 	u32 modes;
 	if (hw->copper) {
 		modes = SUPPORTED_10baseT_Half
 		    | SUPPORTED_10baseT_Full
 		    | SUPPORTED_100baseT_Half
 		    | SUPPORTED_100baseT_Full
 		    | SUPPORTED_Autoneg | SUPPORTED_TP;
 		if (hw->chip_id != CHIP_ID_YUKON_FE)
 			modes |= SUPPORTED_1000baseT_Half
 			    | SUPPORTED_1000baseT_Full;
 	} else
 		modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
 		    | SUPPORTED_Autoneg;
 	return modes;
 }
 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
 {
 	struct sky2_port *sky2 = netdev_priv(dev);
 	struct sky2_hw *hw = sky2->hw;
 	ecmd->transceiver = XCVR_INTERNAL;
 	ecmd->supported = sky2_supported_modes(hw);
 	ecmd->phy_address = PHY_ADDR_MARV;
 	if (hw->copper) {
 		ecmd->supported = SUPPORTED_10baseT_Half
 		    | SUPPORTED_10baseT_Full
 		    | SUPPORTED_100baseT_Half
 		    | SUPPORTED_100baseT_Full
 		    | SUPPORTED_1000baseT_Half
 		    | SUPPORTED_1000baseT_Full
 		    | SUPPORTED_Autoneg | SUPPORTED_TP;
 		ecmd->port = PORT_TP;
 	} else
 		ecmd->port = PORT_FIBRE;
 	ecmd->advertising = sky2->advertising;
 	ecmd->autoneg = sky2->autoneg;
 	ecmd->speed = sky2->speed;
 	ecmd->duplex = sky2->duplex;
 	return 0;
 }
 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
 {
 	struct sky2_port *sky2 = netdev_priv(dev);
 	const struct sky2_hw *hw = sky2->hw;
 	u32 supported = sky2_supported_modes(hw);
 	if (ecmd->autoneg == AUTONEG_ENABLE) {
 		ecmd->advertising = supported;
 		sky2->duplex = -1;
 		sky2->speed = -1;
 	} else {
 		u32 setting;
 		switch (ecmd->speed) {
 		case SPEED_1000:
 			if (ecmd->duplex == DUPLEX_FULL)
 				setting = SUPPORTED_1000baseT_Full;
 			else if (ecmd->duplex == DUPLEX_HALF)
 				setting = SUPPORTED_1000baseT_Half;
 			else
 				return -EINVAL;
 			break;
 		case SPEED_100:
 			if (ecmd->duplex == DUPLEX_FULL)
 				setting = SUPPORTED_100baseT_Full;
 			else if (ecmd->duplex == DUPLEX_HALF)
 				setting = SUPPORTED_100baseT_Half;
 			else
 				return -EINVAL;
 			break;
 		case SPEED_10:
 			if (ecmd->duplex == DUPLEX_FULL)
 				setting = SUPPORTED_10baseT_Full;
 			else if (ecmd->duplex == DUPLEX_HALF)
 				setting = SUPPORTED_10baseT_Half;
 			else
 				return -EINVAL;
 			break;
 		default:
 			return -EINVAL;
 		}
 		if ((setting & supported) == 0)
 			return -EINVAL;
 		sky2->speed = ecmd->speed;
 		sky2->duplex = ecmd->duplex;
 	}
 	sky2->autoneg = ecmd->autoneg;
 	sky2->advertising = ecmd->advertising;
 	if (netif_running(dev))
 		sky2_phy_reinit(sky2);
 	return 0;
 }
 static void sky2_get_drvinfo(struct net_device *dev,
 			     struct ethtool_drvinfo *info)
 {
 	struct sky2_port *sky2 = netdev_priv(dev);
 	strcpy(info->driver, DRV_NAME);
 	strcpy(info->version, DRV_VERSION);
 	strcpy(info->fw_version, "N/A");
 	strcpy(info->bus_info, pci_name(sky2->hw->pdev));
 }
 static const struct sky2_stat {
 	char name[ETH_GSTRING_LEN];
 	u16 offset;
 } sky2_stats[] = {
 	{ "tx_bytes",	   GM_TXO_OK_HI },
 	{ "rx_bytes",	   GM_RXO_OK_HI },
 	{ "tx_broadcast",  GM_TXF_BC_OK },
 	{ "rx_broadcast",  GM_RXF_BC_OK },
 	{ "tx_multicast",  GM_TXF_MC_OK },
 	{ "rx_multicast",  GM_RXF_MC_OK },
 	{ "tx_unicast",    GM_TXF_UC_OK },
 	{ "rx_unicast",    GM_RXF_UC_OK },
 	{ "tx_mac_pause",  GM_TXF_MPAUSE },
 	{ "rx_mac_pause",  GM_RXF_MPAUSE },
 	{ "collisions",    GM_TXF_SNG_COL },
 	{ "late_collision",GM_TXF_LAT_COL },
 	{ "aborted", 	   GM_TXF_ABO_COL },
 	{ "multi_collisions", GM_TXF_MUL_COL },
 	{ "fifo_underrun", GM_TXE_FIFO_UR },
 	{ "fifo_overflow", GM_RXE_FIFO_OV },
 	{ "rx_toolong",    GM_RXF_LNG_ERR },
 	{ "rx_jabber",     GM_RXF_JAB_PKT },
 	{ "rx_runt", 	   GM_RXE_FRAG },
 	{ "rx_too_long",   GM_RXF_LNG_ERR },
 	{ "rx_fcs_error",   GM_RXF_FCS_ERR },
 };
 static u32 sky2_get_rx_csum(struct net_device *dev)
 {
 	struct sky2_port *sky2 = netdev_priv(dev);
 	return sky2->rx_csum;
 }
 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
 {
 	struct sky2_port *sky2 = netdev_priv(dev);
 	sky2->rx_csum = data;
 	sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
 		     data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
 	return 0;
 }
 static u32 sky2_get_msglevel(struct net_device *netdev)
 {
 	struct sky2_port *sky2 = netdev_priv(netdev);
 	return sky2->msg_enable;
 }
 static int sky2_nway_reset(struct net_device *dev)
 {
 	struct sky2_port *sky2 = netdev_priv(dev);
 	if (sky2->autoneg != AUTONEG_ENABLE)
 		return -EINVAL;
 	sky2_phy_reinit(sky2);
 	return 0;
 }
 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
 {
 	struct sky2_hw *hw = sky2->hw;
 	unsigned port = sky2->port;
 	int i;
 	data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
 	    | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
 	data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
 	    | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
 	for (i = 2; i < count; i++)
 		data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
 }
 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
 {
 	struct sky2_port *sky2 = netdev_priv(netdev);
 	sky2->msg_enable = value;
 }
 static int sky2_get_stats_count(struct net_device *dev)
 {
 	return ARRAY_SIZE(sky2_stats);
 }
 static void sky2_get_ethtool_stats(struct net_device *dev,
 				   struct ethtool_stats *stats, u64 * data)
 {
 	struct sky2_port *sky2 = netdev_priv(dev);
 	sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
 }
 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
 {
 	int i;
 	switch (stringset) {
 	case ETH_SS_STATS:
 		for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
 			memcpy(data + i * ETH_GSTRING_LEN,
 			       sky2_stats[i].name, ETH_GSTRING_LEN);
 		break;
 	}
 }
 /* Use hardware MIB variables for critical path statistics and
  * transmit feedback not reported at interrupt.
  * Other errors are accounted for in interrupt handler.
  */
 static struct net_device_stats *sky2_get_stats(struct net_device *dev)
 {
 	struct sky2_port *sky2 = netdev_priv(dev);
 	u64 data[13];
 	sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
 	sky2->net_stats.tx_bytes = data[0];
 	sky2->net_stats.rx_bytes = data[1];
 	sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
 	sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
 	sky2->net_stats.multicast = data[5] + data[7];
 	sky2->net_stats.collisions = data[10];
 	sky2->net_stats.tx_aborted_errors = data[12];
 	return &sky2->net_stats;
 }
 static int sky2_set_mac_address(struct net_device *dev, void *p)
 {
 	struct sky2_port *sky2 = netdev_priv(dev);
 	struct sky2_hw *hw = sky2->hw;
 	unsigned port = sky2->port;
 	const struct sockaddr *addr = p;
 	if (!is_valid_ether_addr(addr->sa_data))
 		return -EADDRNOTAVAIL;
 	memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
 	memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
 		    dev->dev_addr, ETH_ALEN);
 	memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
 		    dev->dev_addr, ETH_ALEN);
 	/* virtual address for data */
 	gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
 	/* physical address: used for pause frames */
 	gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
 	return 0;
 }
 static void sky2_set_multicast(struct net_device *dev)
 {
 	struct sky2_port *sky2 = netdev_priv(dev);
 	struct sky2_hw *hw = sky2->hw;
 	unsigned port = sky2->port;
 	struct dev_mc_list *list = dev->mc_list;
 	u16 reg;
 	u8 filter[8];
 	memset(filter, 0, sizeof(filter));
 	reg = gma_read16(hw, port, GM_RX_CTRL);
 	reg |= GM_RXCR_UCF_ENA;
 	if (dev->flags & IFF_PROMISC)	/* promiscuous */
 		reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
 	else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16)	/* all multicast */
 		memset(filter, 0xff, sizeof(filter));
 	else if (dev->mc_count == 0)	/* no multicast */
 		reg &= ~GM_RXCR_MCF_ENA;
 	else {
 		int i;
 		reg |= GM_RXCR_MCF_ENA;
 		for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
 			u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
 			filter[bit / 8] |= 1 << (bit % 8);
 		}
 	}
 	gma_write16(hw, port, GM_MC_ADDR_H1,
 		    (u16) filter[0] | ((u16) filter[1] << 8));
 	gma_write16(hw, port, GM_MC_ADDR_H2,
 		    (u16) filter[2] | ((u16) filter[3] << 8));
 	gma_write16(hw, port, GM_MC_ADDR_H3,
 		    (u16) filter[4] | ((u16) filter[5] << 8));
 	gma_write16(hw, port, GM_MC_ADDR_H4,
 		    (u16) filter[6] | ((u16) filter[7] << 8));
 	gma_write16(hw, port, GM_RX_CTRL, reg);
 }
 /* Can have one global because blinking is controlled by
  * ethtool and that is always under RTNL mutex
  */
 static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
 {
 	u16 pg;
 	switch (hw->chip_id) {
 	case CHIP_ID_YUKON_XL:
 		pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
 		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
 		gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
 			     on ? (PHY_M_LEDC_LOS_CTRL(1) |
 				   PHY_M_LEDC_INIT_CTRL(7) |
 				   PHY_M_LEDC_STA1_CTRL(7) |
 				   PHY_M_LEDC_STA0_CTRL(7))
 			     : 0);
 		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
 		break;
 	default:
 		gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
 		gm_phy_write(hw, port, PHY_MARV_LED_OVER,
 			     on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
 			     PHY_M_LED_MO_10(MO_LED_ON) |
 			     PHY_M_LED_MO_100(MO_LED_ON) |
 			     PHY_M_LED_MO_1000(MO_LED_ON) |
 			     PHY_M_LED_MO_RX(MO_LED_ON)
 			     : PHY_M_LED_MO_DUP(MO_LED_OFF) |
 			     PHY_M_LED_MO_10(MO_LED_OFF) |
 			     PHY_M_LED_MO_100(MO_LED_OFF) |
 			     PHY_M_LED_MO_1000(MO_LED_OFF) |
 			     PHY_M_LED_MO_RX(MO_LED_OFF));
 	}
 }
 /* blink LED's for finding board */
 static int sky2_phys_id(struct net_device *dev, u32 data)
 {
 	struct sky2_port *sky2 = netdev_priv(dev);
 	struct sky2_hw *hw = sky2->hw;
 	unsigned port = sky2->port;
 	u16 ledctrl, ledover = 0;
 	long ms;
 	int interrupted;
 	int onoff = 1;
 	if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
 		ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
 	else
 		ms = data * 1000;
 	/* save initial values */
 	down(&sky2->phy_sema);
 	if (hw->chip_id == CHIP_ID_YUKON_XL) {
 		u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
 		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
 		ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
 		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
 	} else {
 		ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
 		ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
 	}
 	interrupted = 0;
 	while (!interrupted && ms > 0) {
 		sky2_led(hw, port, onoff);
 		onoff = !onoff;
 		up(&sky2->phy_sema);
 		interrupted = msleep_interruptible(250);
 		down(&sky2->phy_sema);
 		ms -= 250;
 	}
 	/* resume regularly scheduled programming */
 	if (hw->chip_id == CHIP_ID_YUKON_XL) {
 		u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
 		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
 		gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
 		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
 	} else {
 		gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
 		gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
 	}
 	up(&sky2->phy_sema);
 	return 0;
 }
 static void sky2_get_pauseparam(struct net_device *dev,
 				struct ethtool_pauseparam *ecmd)
 {
 	struct sky2_port *sky2 = netdev_priv(dev);
 	ecmd->tx_pause = sky2->tx_pause;
 	ecmd->rx_pause = sky2->rx_pause;
 	ecmd->autoneg = sky2->autoneg;
 }
 static int sky2_set_pauseparam(struct net_device *dev,
 			       struct ethtool_pauseparam *ecmd)
 {
 	struct sky2_port *sky2 = netdev_priv(dev);
 	int err = 0;
 	sky2->autoneg = ecmd->autoneg;
 	sky2->tx_pause = ecmd->tx_pause != 0;
 	sky2->rx_pause = ecmd->rx_pause != 0;
 	sky2_phy_reinit(sky2);
 	return err;
 }
 #ifdef CONFIG_PM
 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 {
 	struct sky2_port *sky2 = netdev_priv(dev);
 	wol->supported = WAKE_MAGIC;
 	wol->wolopts = sky2->wol ? WAKE_MAGIC : 0;
 }
 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 {
 	struct sky2_port *sky2 = netdev_priv(dev);
 	struct sky2_hw *hw = sky2->hw;
 	if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
 		return -EOPNOTSUPP;
 	sky2->wol = wol->wolopts == WAKE_MAGIC;
 	if (sky2->wol) {
 		memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
 		sky2_write16(hw, WOL_CTRL_STAT,
 			     WOL_CTL_ENA_PME_ON_MAGIC_PKT |
 			     WOL_CTL_ENA_MAGIC_PKT_UNIT);
 	} else
 		sky2_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
 	return 0;
 }
 #endif
 static int sky2_get_coalesce(struct net_device *dev,
 			     struct ethtool_coalesce *ecmd)
 {
 	struct sky2_port *sky2 = netdev_priv(dev);
 	struct sky2_hw *hw = sky2->hw;
 	if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
 		ecmd->tx_coalesce_usecs = 0;
 	else {
 		u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
 		ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
 	}
 	ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
 	if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
 		ecmd->rx_coalesce_usecs = 0;
 	else {
 		u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
 		ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
 	}
 	ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
 	if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
 		ecmd->rx_coalesce_usecs_irq = 0;
 	else {
 		u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
 		ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
 	}
 	ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
 	return 0;
 }
 /* Note: this affect both ports */
 static int sky2_set_coalesce(struct net_device *dev,
 			     struct ethtool_coalesce *ecmd)
 {
 	struct sky2_port *sky2 = netdev_priv(dev);
 	struct sky2_hw *hw = sky2->hw;
 	const u32 tmin = sky2_clk2us(hw, 1);
 	const u32 tmax = 5000;
 	if (ecmd->tx_coalesce_usecs != 0 &&
 	    (ecmd->tx_coalesce_usecs < tmin || ecmd->tx_coalesce_usecs > tmax))
 		return -EINVAL;
 	if (ecmd->rx_coalesce_usecs != 0 &&
 	    (ecmd->rx_coalesce_usecs < tmin || ecmd->rx_coalesce_usecs > tmax))
 		return -EINVAL;
 	if (ecmd->rx_coalesce_usecs_irq != 0 &&
 	    (ecmd->rx_coalesce_usecs_irq < tmin || ecmd->rx_coalesce_usecs_irq > tmax))
 		return -EINVAL;
 	if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
 		return -EINVAL;
 	if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
 		return -EINVAL;
 	if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
 		return -EINVAL;
 	if (ecmd->tx_coalesce_usecs == 0)
 		sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
 	else {
 		sky2_write32(hw, STAT_TX_TIMER_INI,
 			     sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
 		sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
 	}
 	sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
 	if (ecmd->rx_coalesce_usecs == 0)
 		sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
 	else {
 		sky2_write32(hw, STAT_LEV_TIMER_INI,
 			     sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
 		sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
 	}
 	sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
 	if (ecmd->rx_coalesce_usecs_irq == 0)
 		sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
 	else {
 		sky2_write32(hw, STAT_ISR_TIMER_INI,
 			     sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
 		sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
 	}
 	sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
 	return 0;
 }
 static void sky2_get_ringparam(struct net_device *dev,
 			       struct ethtool_ringparam *ering)
 {
 	struct sky2_port *sky2 = netdev_priv(dev);
 	ering->rx_max_pending = RX_MAX_PENDING;
 	ering->rx_mini_max_pending = 0;
 	ering->rx_jumbo_max_pending = 0;
 	ering->tx_max_pending = TX_RING_SIZE - 1;
 	ering->rx_pending = sky2->rx_pending;
 	ering->rx_mini_pending = 0;
 	ering->rx_jumbo_pending = 0;
 	ering->tx_pending = sky2->tx_pending;
 }
 static int sky2_set_ringparam(struct net_device *dev,
 			      struct ethtool_ringparam *ering)
 {
 	struct sky2_port *sky2 = netdev_priv(dev);
 	int err = 0;
 	if (ering->rx_pending > RX_MAX_PENDING ||
 	    ering->rx_pending < 8 ||
 	    ering->tx_pending < MAX_SKB_TX_LE ||
 	    ering->tx_pending > TX_RING_SIZE - 1)
 		return -EINVAL;
 	if (netif_running(dev))
 		sky2_down(dev);
 	sky2->rx_pending = ering->rx_pending;
 	sky2->tx_pending = ering->tx_pending;
 	if (netif_running(dev)) {
 		err = sky2_up(dev);
 		if (err)
 			dev_close(dev);
 		else
 			sky2_set_multicast(dev);
 	}
 	return err;
 }
 static int sky2_get_regs_len(struct net_device *dev)
 {
 	return 0x4000;
 }
 /*
  * Returns copy of control register region
  * Note: access to the RAM address register set will cause timeouts.
  */
 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
 			  void *p)
 {
 	const struct sky2_port *sky2 = netdev_priv(dev);
 	const void __iomem *io = sky2->hw->regs;
 	BUG_ON(regs->len < B3_RI_WTO_R1);
 	regs->version = 1;
 	memset(p, 0, regs->len);
 	memcpy_fromio(p, io, B3_RAM_ADDR);
 	memcpy_fromio(p + B3_RI_WTO_R1,
 		      io + B3_RI_WTO_R1,
 		      regs->len - B3_RI_WTO_R1);
 }
 static struct ethtool_ops sky2_ethtool_ops = {
 	.get_settings = sky2_get_settings,
 	.set_settings = sky2_set_settings,
 	.get_drvinfo = sky2_get_drvinfo,
 	.get_msglevel = sky2_get_msglevel,
 	.set_msglevel = sky2_set_msglevel,
 	.nway_reset   = sky2_nway_reset,
 	.get_regs_len = sky2_get_regs_len,
 	.get_regs = sky2_get_regs,
 	.get_link = ethtool_op_get_link,
 	.get_sg = ethtool_op_get_sg,
 	.set_sg = ethtool_op_set_sg,
 	.get_tx_csum = ethtool_op_get_tx_csum,
 	.set_tx_csum = ethtool_op_set_tx_csum,
 	.get_tso = ethtool_op_get_tso,
 	.set_tso = ethtool_op_set_tso,
 	.get_rx_csum = sky2_get_rx_csum,
 	.set_rx_csum = sky2_set_rx_csum,
 	.get_strings = sky2_get_strings,
 	.get_coalesce = sky2_get_coalesce,
 	.set_coalesce = sky2_set_coalesce,
 	.get_ringparam = sky2_get_ringparam,
 	.set_ringparam = sky2_set_ringparam,
 	.get_pauseparam = sky2_get_pauseparam,
 	.set_pauseparam = sky2_set_pauseparam,
 #ifdef CONFIG_PM
 	.get_wol = sky2_get_wol,
 	.set_wol = sky2_set_wol,
 #endif
 	.phys_id = sky2_phys_id,
 	.get_stats_count = sky2_get_stats_count,
 	.get_ethtool_stats = sky2_get_ethtool_stats,
 	.get_perm_addr	= ethtool_op_get_perm_addr,
 };
 /* Initialize network device */
 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
 						     unsigned port, int highmem)
 {
 	struct sky2_port *sky2;
 	struct net_device *dev = alloc_etherdev(sizeof(*sky2));
 	if (!dev) {
 		printk(KERN_ERR "sky2 etherdev alloc failed");
 		return NULL;
 	}
 	SET_MODULE_OWNER(dev);
 	SET_NETDEV_DEV(dev, &hw->pdev->dev);
 	dev->irq = hw->pdev->irq;
 	dev->open = sky2_up;
 	dev->stop = sky2_down;
 	dev->do_ioctl = sky2_ioctl;
 	dev->hard_start_xmit = sky2_xmit_frame;
 	dev->get_stats = sky2_get_stats;
 	dev->set_multicast_list = sky2_set_multicast;
 	dev->set_mac_address = sky2_set_mac_address;
 	dev->change_mtu = sky2_change_mtu;
 	SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
 	dev->tx_timeout = sky2_tx_timeout;
 	dev->watchdog_timeo = TX_WATCHDOG;
 	if (port == 0)
 		dev->poll = sky2_poll;
 	dev->weight = NAPI_WEIGHT;
 #ifdef CONFIG_NET_POLL_CONTROLLER
 	dev->poll_controller = sky2_netpoll;
 #endif
 	sky2 = netdev_priv(dev);
 	sky2->netdev = dev;
 	sky2->hw = hw;
 	sky2->msg_enable = netif_msg_init(debug, default_msg);
 	spin_lock_init(&sky2->tx_lock);
 	/* Auto speed and flow control */
 	sky2->autoneg = AUTONEG_ENABLE;
 	sky2->tx_pause = 1;
 	sky2->rx_pause = 1;
 	sky2->duplex = -1;
 	sky2->speed = -1;
 	sky2->advertising = sky2_supported_modes(hw);
  	/* Receive checksum disabled for Yukon XL
 	 * because of observed problems with incorrect
 	 * values when multiple packets are received in one interrupt
 	 */
 	sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);
 	INIT_WORK(&sky2->phy_task, sky2_phy_task, sky2);
 	init_MUTEX(&sky2->phy_sema);
 	sky2->tx_pending = TX_DEF_PENDING;
-	sky2->rx_pending = is_ec_a1(hw) ? 8 : RX_DEF_PENDING;
+	sky2->rx_pending = RX_DEF_PENDING;
 	sky2->rx_bufsize = sky2_buf_size(ETH_DATA_LEN);
 	hw->dev[port] = dev;
 	sky2->port = port;
 	dev->features |= NETIF_F_LLTX;
 	if (hw->chip_id != CHIP_ID_YUKON_EC_U)
 		dev->features |= NETIF_F_TSO;
 	if (highmem)
 		dev->features |= NETIF_F_HIGHDMA;
 	dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
 #ifdef SKY2_VLAN_TAG_USED
 	dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
 	dev->vlan_rx_register = sky2_vlan_rx_register;
 	dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
 #endif
 	/* read the mac address */
 	memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
 	memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
 	/* device is off until link detection */
 	netif_carrier_off(dev);
 	netif_stop_queue(dev);
 	return dev;
 }
 static void __devinit sky2_show_addr(struct net_device *dev)
 {
 	const struct sky2_port *sky2 = netdev_priv(dev);
 	if (netif_msg_probe(sky2))
 		printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
 		       dev->name,
 		       dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
 		       dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
 }
 static int __devinit sky2_probe(struct pci_dev *pdev,
 				const struct pci_device_id *ent)
 {
 	struct net_device *dev, *dev1 = NULL;
 	struct sky2_hw *hw;
 	int err, pm_cap, using_dac = 0;
 	err = pci_enable_device(pdev);
 	if (err) {
 		printk(KERN_ERR PFX "%s cannot enable PCI device\n",
 		       pci_name(pdev));
 		goto err_out;
 	}
 	err = pci_request_regions(pdev, DRV_NAME);
 	if (err) {
 		printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
 		       pci_name(pdev));
 		goto err_out;
 	}
 	pci_set_master(pdev);
 	/* Find power-management capability. */
 	pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
 	if (pm_cap == 0) {
 		printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
 		       "aborting.\n");
 		err = -EIO;
 		goto err_out_free_regions;
 	}
 	if (sizeof(dma_addr_t) > sizeof(u32) &&
 	    !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
 		using_dac = 1;
 		err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
 		if (err < 0) {
 			printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA "
 			       "for consistent allocations\n", pci_name(pdev));
 			goto err_out_free_regions;
 		}
 	} else {
 		err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
 		if (err) {
 			printk(KERN_ERR PFX "%s no usable DMA configuration\n",
 			       pci_name(pdev));
 			goto err_out_free_regions;
 		}
 	}
 	err = -ENOMEM;
 	hw = kzalloc(sizeof(*hw), GFP_KERNEL);
 	if (!hw) {
 		printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
 		       pci_name(pdev));
 		goto err_out_free_regions;
 	}
 	hw->pdev = pdev;
 	hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
 	if (!hw->regs) {
 		printk(KERN_ERR PFX "%s: cannot map device registers\n",
 		       pci_name(pdev));
 		goto err_out_free_hw;
 	}
 	hw->pm_cap = pm_cap;
 	spin_lock_init(&hw->hw_lock);
 #ifdef __BIG_ENDIAN
 	/* byte swap descriptors in hardware */
 	{
 		u32 reg;
 		reg = sky2_pci_read32(hw, PCI_DEV_REG2);
 		reg |= PCI_REV_DESC;
 		sky2_pci_write32(hw, PCI_DEV_REG2, reg);
 	}
 #endif
 	/* ring for status responses */
 	hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
 					 &hw->st_dma);
 	if (!hw->st_le)
 		goto err_out_iounmap;
 	err = sky2_reset(hw);
 	if (err)
 		goto err_out_iounmap;
 	printk(KERN_INFO PFX "v%s addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n",
 	       DRV_VERSION, pci_resource_start(pdev, 0), pdev->irq,
 	       yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
 	       hw->chip_id, hw->chip_rev);
 	dev = sky2_init_netdev(hw, 0, using_dac);
 	if (!dev)
 		goto err_out_free_pci;
 	err = register_netdev(dev);
 	if (err) {
 		printk(KERN_ERR PFX "%s: cannot register net device\n",
 		       pci_name(pdev));
 		goto err_out_free_netdev;
 	}
 	sky2_show_addr(dev);
 	if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
 		if (register_netdev(dev1) == 0)
 			sky2_show_addr(dev1);
 		else {
 			/* Failure to register second port need not be fatal */
 			printk(KERN_WARNING PFX
 			       "register of second port failed\n");
 			hw->dev[1] = NULL;
 			free_netdev(dev1);
 		}
 	}
 	err = request_irq(pdev->irq, sky2_intr, SA_SHIRQ, DRV_NAME, hw);
 	if (err) {
 		printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
 		       pci_name(pdev), pdev->irq);
 		goto err_out_unregister;
 	}
 	hw->intr_mask = Y2_IS_BASE;
 	sky2_write32(hw, B0_IMSK, hw->intr_mask);
 	pci_set_drvdata(pdev, hw);
 	return 0;
 err_out_unregister:
 	if (dev1) {
 		unregister_netdev(dev1);
 		free_netdev(dev1);
 	}
 	unregister_netdev(dev);
 err_out_free_netdev:
 	free_netdev(dev);
 err_out_free_pci:
 	sky2_write8(hw, B0_CTST, CS_RST_SET);
 	pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
 err_out_iounmap:
 	iounmap(hw->regs);
 err_out_free_hw:
 	kfree(hw);
 err_out_free_regions:
 	pci_release_regions(pdev);
 	pci_disable_device(pdev);
 err_out:
 	return err;
 }
 static void __devexit sky2_remove(struct pci_dev *pdev)
 {
 	struct sky2_hw *hw = pci_get_drvdata(pdev);
 	struct net_device *dev0, *dev1;
 	if (!hw)
 		return;
 	dev0 = hw->dev[0];
 	dev1 = hw->dev[1];
 	if (dev1)
 		unregister_netdev(dev1);
 	unregister_netdev(dev0);
 	sky2_write32(hw, B0_IMSK, 0);
 	sky2_set_power_state(hw, PCI_D3hot);
 	sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
 	sky2_write8(hw, B0_CTST, CS_RST_SET);
 	sky2_read8(hw, B0_CTST);
 	free_irq(pdev->irq, hw);
 	pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
 	pci_release_regions(pdev);
 	pci_disable_device(pdev);
 	if (dev1)
 		free_netdev(dev1);
 	free_netdev(dev0);
 	iounmap(hw->regs);
 	kfree(hw);
 	pci_set_drvdata(pdev, NULL);
 }
 #ifdef CONFIG_PM
 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
 {
 	struct sky2_hw *hw = pci_get_drvdata(pdev);
 	int i;
 	for (i = 0; i < 2; i++) {
 		struct net_device *dev = hw->dev[i];
 		if (dev) {
 			if (!netif_running(dev))
 				continue;
 			sky2_down(dev);
 			netif_device_detach(dev);
 		}
 	}
 	return sky2_set_power_state(hw, pci_choose_state(pdev, state));
 }
 static int sky2_resume(struct pci_dev *pdev)
 {
 	struct sky2_hw *hw = pci_get_drvdata(pdev);
 	int i, err;
 	pci_restore_state(pdev);
 	pci_enable_wake(pdev, PCI_D0, 0);
 	err = sky2_set_power_state(hw, PCI_D0);
 	if (err)
 		goto out;
 	err = sky2_reset(hw);
 	if (err)
 		goto out;
 	for (i = 0; i < 2; i++) {
 		struct net_device *dev = hw->dev[i];
 		if (dev && netif_running(dev)) {
 			netif_device_attach(dev);
 			err = sky2_up(dev);
 			if (err) {
 				printk(KERN_ERR PFX "%s: could not up: %d\n",
 				       dev->name, err);
 				dev_close(dev);
 				break;
 			}
 		}
 	}
 out:
 	return err;
 }
 #endif
 static struct pci_driver sky2_driver = {
 	.name = DRV_NAME,
 	.id_table = sky2_id_table,
 	.probe = sky2_probe,
 	.remove = __devexit_p(sky2_remove),
 #ifdef CONFIG_PM
 	.suspend = sky2_suspend,
 	.resume = sky2_resume,
 #endif

 /*
  * Definitions for the new Marvell Yukon 2 driver.
  */
 #ifndef _SKY2_H
 #define _SKY2_H
 /* PCI config registers */
 enum {
 	PCI_DEV_REG1	= 0x40,
 	PCI_DEV_REG2	= 0x44,
 	PCI_DEV_STATUS  = 0x7c,
 	PCI_DEV_REG3	= 0x80,
 	PCI_DEV_REG4	= 0x84,
 	PCI_DEV_REG5    = 0x88,
 };
 enum {
 	PEX_DEV_CAP	= 0xe4,
 	PEX_DEV_CTRL	= 0xe8,
 	PEX_DEV_STA	= 0xea,
 	PEX_LNK_STAT	= 0xf2,
 	PEX_UNC_ERR_STAT= 0x104,
 };
 /* Yukon-2 */
 enum pci_dev_reg_1 {
 	PCI_Y2_PIG_ENA	 = 1<<31, /* Enable Plug-in-Go (YUKON-2) */
 	PCI_Y2_DLL_DIS	 = 1<<30, /* Disable PCI DLL (YUKON-2) */
 	PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */
 	PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */
 	PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */
 	PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */
 };
 enum pci_dev_reg_2 {
 	PCI_VPD_WR_THR	= 0xffL<<24,	/* Bit 31..24:	VPD Write Threshold */
 	PCI_DEV_SEL	= 0x7fL<<17,	/* Bit 23..17:	EEPROM Device Select */
 	PCI_VPD_ROM_SZ	= 7L<<14,	/* Bit 16..14:	VPD ROM Size	*/
 	PCI_PATCH_DIR	= 0xfL<<8,	/* Bit 11.. 8:	Ext Patches dir 3..0 */
 	PCI_EXT_PATCHS	= 0xfL<<4,	/* Bit	7.. 4:	Extended Patches 3..0 */
 	PCI_EN_DUMMY_RD	= 1<<3,		/* Enable Dummy Read */
 	PCI_REV_DESC	= 1<<2,		/* Reverse Desc. Bytes */
 	PCI_USEDATA64	= 1<<0,		/* Use 64Bit Data bus ext */
 };
 /*	PCI_OUR_REG_4		32 bit	Our Register 4 (Yukon-ECU only) */
 enum pci_dev_reg_4 {
 					/* (Link Training & Status State Machine) */
 	P_TIMER_VALUE_MSK	= 0xffL<<16,	/* Bit 23..16:	Timer Value Mask */
 					/* (Active State Power Management) */
 	P_FORCE_ASPM_REQUEST	= 1<<15, /* Force ASPM Request (A1 only) */
 	P_ASPM_GPHY_LINK_DOWN	= 1<<14, /* GPHY Link Down (A1 only) */
 	P_ASPM_INT_FIFO_EMPTY	= 1<<13, /* Internal FIFO Empty (A1 only) */
 	P_ASPM_CLKRUN_REQUEST	= 1<<12, /* CLKRUN Request (A1 only) */
 	P_ASPM_FORCE_CLKREQ_ENA	= 1<<4,	/* Force CLKREQ Enable (A1b only) */
 	P_ASPM_CLKREQ_PAD_CTL	= 1<<3,	/* CLKREQ PAD Control (A1 only) */
 	P_ASPM_A1_MODE_SELECT	= 1<<2,	/* A1 Mode Select (A1 only) */
 	P_CLK_GATE_PEX_UNIT_ENA	= 1<<1,	/* Enable Gate PEX Unit Clock */
 	P_CLK_GATE_ROOT_COR_ENA	= 1<<0,	/* Enable Gate Root Core Clock */
 	P_ASPM_CONTROL_MSK	= P_FORCE_ASPM_REQUEST | P_ASPM_GPHY_LINK_DOWN
 				  | P_ASPM_CLKRUN_REQUEST | P_ASPM_INT_FIFO_EMPTY,
 };
 #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
 			       PCI_STATUS_SIG_SYSTEM_ERROR | \
 			       PCI_STATUS_REC_MASTER_ABORT | \
 			       PCI_STATUS_REC_TARGET_ABORT | \
 			       PCI_STATUS_PARITY)
 enum pex_dev_ctrl {
 	PEX_DC_MAX_RRS_MSK	= 7<<12, /* Bit 14..12:	Max. Read Request Size */
 	PEX_DC_EN_NO_SNOOP	= 1<<11,/* Enable No Snoop */
 	PEX_DC_EN_AUX_POW	= 1<<10,/* Enable AUX Power */
 	PEX_DC_EN_PHANTOM	= 1<<9,	/* Enable Phantom Functions */
 	PEX_DC_EN_EXT_TAG	= 1<<8,	/* Enable Extended Tag Field */
 	PEX_DC_MAX_PLS_MSK	= 7<<5,	/* Bit  7.. 5:	Max. Payload Size Mask */
 	PEX_DC_EN_REL_ORD	= 1<<4,	/* Enable Relaxed Ordering */
 	PEX_DC_EN_UNS_RQ_RP	= 1<<3,	/* Enable Unsupported Request Reporting */
 	PEX_DC_EN_FAT_ER_RP	= 1<<2,	/* Enable Fatal Error Reporting */
 	PEX_DC_EN_NFA_ER_RP	= 1<<1,	/* Enable Non-Fatal Error Reporting */
 	PEX_DC_EN_COR_ER_RP	= 1<<0,	/* Enable Correctable Error Reporting */
 };
 #define  PEX_DC_MAX_RD_RQ_SIZE(x) (((x)<<12) & PEX_DC_MAX_RRS_MSK)
 /* PEX_UNC_ERR_STAT	 PEX Uncorrectable Errors Status Register (Yukon-2) */
 enum pex_err {
 	PEX_UNSUP_REQ 	= 1<<20, /* Unsupported Request Error */
 	PEX_MALFOR_TLP	= 1<<18, /* Malformed TLP */
 	PEX_UNEXP_COMP	= 1<<16, /* Unexpected Completion */
 	PEX_COMP_TO	= 1<<14, /* Completion Timeout */
 	PEX_FLOW_CTRL_P	= 1<<13, /* Flow Control Protocol Error */
 	PEX_POIS_TLP	= 1<<12, /* Poisoned TLP */
 	PEX_DATA_LINK_P = 1<<4,	/* Data Link Protocol Error */
 	PEX_FATAL_ERRORS= (PEX_MALFOR_TLP | PEX_FLOW_CTRL_P | PEX_DATA_LINK_P),
 };
 enum csr_regs {
 	B0_RAP		= 0x0000,
 	B0_CTST		= 0x0004,
 	B0_Y2LED	= 0x0005,
 	B0_POWER_CTRL	= 0x0007,
 	B0_ISRC		= 0x0008,
 	B0_IMSK		= 0x000c,
 	B0_HWE_ISRC	= 0x0010,
 	B0_HWE_IMSK	= 0x0014,
 	/* Special ISR registers (Yukon-2 only) */
 	B0_Y2_SP_ISRC2	= 0x001c,
 	B0_Y2_SP_ISRC3	= 0x0020,
 	B0_Y2_SP_EISR	= 0x0024,
 	B0_Y2_SP_LISR	= 0x0028,
 	B0_Y2_SP_ICR	= 0x002c,
 	B2_MAC_1	= 0x0100,
 	B2_MAC_2	= 0x0108,
 	B2_MAC_3	= 0x0110,
 	B2_CONN_TYP	= 0x0118,
 	B2_PMD_TYP	= 0x0119,
 	B2_MAC_CFG	= 0x011a,
 	B2_CHIP_ID	= 0x011b,
 	B2_E_0		= 0x011c,
 	B2_Y2_CLK_GATE  = 0x011d,
 	B2_Y2_HW_RES	= 0x011e,
 	B2_E_3		= 0x011f,
 	B2_Y2_CLK_CTRL	= 0x0120,
 	B2_TI_INI	= 0x0130,
 	B2_TI_VAL	= 0x0134,
 	B2_TI_CTRL	= 0x0138,
 	B2_TI_TEST	= 0x0139,
 	B2_TST_CTRL1	= 0x0158,
 	B2_TST_CTRL2	= 0x0159,
 	B2_GP_IO	= 0x015c,
 	B2_I2C_CTRL	= 0x0160,
 	B2_I2C_DATA	= 0x0164,
 	B2_I2C_IRQ	= 0x0168,
 	B2_I2C_SW	= 0x016c,
 	B3_RAM_ADDR	= 0x0180,
 	B3_RAM_DATA_LO	= 0x0184,
 	B3_RAM_DATA_HI	= 0x0188,
 /* RAM Interface Registers */
 /* Yukon-2: use RAM_BUFFER() to access the RAM buffer */
 /*
  * The HW-Spec. calls this registers Timeout Value 0..11. But this names are
  * not usable in SW. Please notice these are NOT real timeouts, these are
  * the number of qWords transferred continuously.
  */
 #define RAM_BUFFER(port, reg)	(reg | (port <<6))
 	B3_RI_WTO_R1	= 0x0190,
 	B3_RI_WTO_XA1	= 0x0191,
 	B3_RI_WTO_XS1	= 0x0192,
 	B3_RI_RTO_R1	= 0x0193,
 	B3_RI_RTO_XA1	= 0x0194,
 	B3_RI_RTO_XS1	= 0x0195,
 	B3_RI_WTO_R2	= 0x0196,
 	B3_RI_WTO_XA2	= 0x0197,
 	B3_RI_WTO_XS2	= 0x0198,
 	B3_RI_RTO_R2	= 0x0199,
 	B3_RI_RTO_XA2	= 0x019a,
 	B3_RI_RTO_XS2	= 0x019b,
 	B3_RI_TO_VAL	= 0x019c,
 	B3_RI_CTRL	= 0x01a0,
 	B3_RI_TEST	= 0x01a2,
 	B3_MA_TOINI_RX1	= 0x01b0,
 	B3_MA_TOINI_RX2	= 0x01b1,
 	B3_MA_TOINI_TX1	= 0x01b2,
 	B3_MA_TOINI_TX2	= 0x01b3,
 	B3_MA_TOVAL_RX1	= 0x01b4,
 	B3_MA_TOVAL_RX2	= 0x01b5,
 	B3_MA_TOVAL_TX1	= 0x01b6,
 	B3_MA_TOVAL_TX2	= 0x01b7,
 	B3_MA_TO_CTRL	= 0x01b8,
 	B3_MA_TO_TEST	= 0x01ba,
 	B3_MA_RCINI_RX1	= 0x01c0,
 	B3_MA_RCINI_RX2	= 0x01c1,
 	B3_MA_RCINI_TX1	= 0x01c2,
 	B3_MA_RCINI_TX2	= 0x01c3,
 	B3_MA_RCVAL_RX1	= 0x01c4,
 	B3_MA_RCVAL_RX2	= 0x01c5,
 	B3_MA_RCVAL_TX1	= 0x01c6,
 	B3_MA_RCVAL_TX2	= 0x01c7,
 	B3_MA_RC_CTRL	= 0x01c8,
 	B3_MA_RC_TEST	= 0x01ca,
 	B3_PA_TOINI_RX1	= 0x01d0,
 	B3_PA_TOINI_RX2	= 0x01d4,
 	B3_PA_TOINI_TX1	= 0x01d8,
 	B3_PA_TOINI_TX2	= 0x01dc,
 	B3_PA_TOVAL_RX1	= 0x01e0,
 	B3_PA_TOVAL_RX2	= 0x01e4,
 	B3_PA_TOVAL_TX1	= 0x01e8,
 	B3_PA_TOVAL_TX2	= 0x01ec,
 	B3_PA_CTRL	= 0x01f0,
 	B3_PA_TEST	= 0x01f2,
 	Y2_CFG_SPC	= 0x1c00,
 };
 /*	B0_CTST			16 bit	Control/Status register */
 enum {
 	Y2_VMAIN_AVAIL	= 1<<17,/* VMAIN available (YUKON-2 only) */
 	Y2_VAUX_AVAIL	= 1<<16,/* VAUX available (YUKON-2 only) */
 	Y2_ASF_ENABLE	= 1<<13,/* ASF Unit Enable (YUKON-2 only) */
 	Y2_ASF_DISABLE	= 1<<12,/* ASF Unit Disable (YUKON-2 only) */
 	Y2_CLK_RUN_ENA	= 1<<11,/* CLK_RUN Enable  (YUKON-2 only) */
 	Y2_CLK_RUN_DIS	= 1<<10,/* CLK_RUN Disable (YUKON-2 only) */
 	Y2_LED_STAT_ON	= 1<<9, /* Status LED On  (YUKON-2 only) */
 	Y2_LED_STAT_OFF	= 1<<8, /* Status LED Off (YUKON-2 only) */
 	CS_ST_SW_IRQ	= 1<<7,	/* Set IRQ SW Request */
 	CS_CL_SW_IRQ	= 1<<6,	/* Clear IRQ SW Request */
 	CS_STOP_DONE	= 1<<5,	/* Stop Master is finished */
 	CS_STOP_MAST	= 1<<4,	/* Command Bit to stop the master */
 	CS_MRST_CLR	= 1<<3,	/* Clear Master reset	*/
 	CS_MRST_SET	= 1<<2,	/* Set Master reset	*/
 	CS_RST_CLR	= 1<<1,	/* Clear Software reset	*/
 	CS_RST_SET	= 1,	/* Set   Software reset	*/
 };
 /*	B0_LED			 8 Bit	LED register */
 enum {
 /* Bit  7.. 2:	reserved */
 	LED_STAT_ON	= 1<<1,	/* Status LED on	*/
 	LED_STAT_OFF	= 1,	/* Status LED off	*/
 };
 /*	B0_POWER_CTRL	 8 Bit	Power Control reg (YUKON only) */
 enum {
 	PC_VAUX_ENA	= 1<<7,	/* Switch VAUX Enable  */
 	PC_VAUX_DIS	= 1<<6,	/* Switch VAUX Disable */
 	PC_VCC_ENA	= 1<<5,	/* Switch VCC Enable  */
 	PC_VCC_DIS	= 1<<4,	/* Switch VCC Disable */
 	PC_VAUX_ON	= 1<<3,	/* Switch VAUX On  */
 	PC_VAUX_OFF	= 1<<2,	/* Switch VAUX Off */
 	PC_VCC_ON	= 1<<1,	/* Switch VCC On  */
 	PC_VCC_OFF	= 1<<0,	/* Switch VCC Off */
 };
 /*	B2_IRQM_MSK 	32 bit	IRQ Moderation Mask */
 /*	B0_Y2_SP_ISRC2	32 bit	Special Interrupt Source Reg 2 */
 /*	B0_Y2_SP_ISRC3	32 bit	Special Interrupt Source Reg 3 */
 /*	B0_Y2_SP_EISR	32 bit	Enter ISR Reg */
 /*	B0_Y2_SP_LISR	32 bit	Leave ISR Reg */
 enum {
 	Y2_IS_HW_ERR	= 1<<31,	/* Interrupt HW Error */
 	Y2_IS_STAT_BMU	= 1<<30,	/* Status BMU Interrupt */
 	Y2_IS_ASF	= 1<<29,	/* ASF subsystem Interrupt */
 	Y2_IS_POLL_CHK	= 1<<27,	/* Check IRQ from polling unit */
 	Y2_IS_TWSI_RDY	= 1<<26,	/* IRQ on end of TWSI Tx */
 	Y2_IS_IRQ_SW	= 1<<25,	/* SW forced IRQ	*/
 	Y2_IS_TIMINT	= 1<<24,	/* IRQ from Timer	*/
 	Y2_IS_IRQ_PHY2	= 1<<12,	/* Interrupt from PHY 2 */
 	Y2_IS_IRQ_MAC2	= 1<<11,	/* Interrupt from MAC 2 */
 	Y2_IS_CHK_RX2	= 1<<10,	/* Descriptor error Rx 2 */
 	Y2_IS_CHK_TXS2	= 1<<9,		/* Descriptor error TXS 2 */
 	Y2_IS_CHK_TXA2	= 1<<8,		/* Descriptor error TXA 2 */
 	Y2_IS_IRQ_PHY1	= 1<<4,		/* Interrupt from PHY 1 */
 	Y2_IS_IRQ_MAC1	= 1<<3,		/* Interrupt from MAC 1 */
 	Y2_IS_CHK_RX1	= 1<<2,		/* Descriptor error Rx 1 */
 	Y2_IS_CHK_TXS1	= 1<<1,		/* Descriptor error TXS 1 */
 	Y2_IS_CHK_TXA1	= 1<<0,		/* Descriptor error TXA 1 */
 	Y2_IS_BASE	= Y2_IS_HW_ERR | Y2_IS_STAT_BMU |
 			  Y2_IS_POLL_CHK | Y2_IS_TWSI_RDY |
 			  Y2_IS_IRQ_SW | Y2_IS_TIMINT,
 	Y2_IS_PORT_1	= Y2_IS_IRQ_PHY1 | Y2_IS_IRQ_MAC1 |
 			  Y2_IS_CHK_RX1 | Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXS1,
 	Y2_IS_PORT_2	= Y2_IS_IRQ_PHY2 | Y2_IS_IRQ_MAC2 |
 			  Y2_IS_CHK_RX2 | Y2_IS_CHK_TXA2 | Y2_IS_CHK_TXS2,
 };
 /*	B2_IRQM_HWE_MSK	32 bit	IRQ Moderation HW Error Mask */
 enum {
 	IS_ERR_MSK	= 0x00003fff,/* 		All Error bits */
 	IS_IRQ_TIST_OV	= 1<<13, /* Time Stamp Timer Overflow (YUKON only) */
 	IS_IRQ_SENSOR	= 1<<12, /* IRQ from Sensor (YUKON only) */
 	IS_IRQ_MST_ERR	= 1<<11, /* IRQ master error detected */
 	IS_IRQ_STAT	= 1<<10, /* IRQ status exception */
 	IS_NO_STAT_M1	= 1<<9,	/* No Rx Status from MAC 1 */
 	IS_NO_STAT_M2	= 1<<8,	/* No Rx Status from MAC 2 */
 	IS_NO_TIST_M1	= 1<<7,	/* No Time Stamp from MAC 1 */
 	IS_NO_TIST_M2	= 1<<6,	/* No Time Stamp from MAC 2 */
 	IS_RAM_RD_PAR	= 1<<5,	/* RAM Read  Parity Error */
 	IS_RAM_WR_PAR	= 1<<4,	/* RAM Write Parity Error */
 	IS_M1_PAR_ERR	= 1<<3,	/* MAC 1 Parity Error */
 	IS_M2_PAR_ERR	= 1<<2,	/* MAC 2 Parity Error */
 	IS_R1_PAR_ERR	= 1<<1,	/* Queue R1 Parity Error */
 	IS_R2_PAR_ERR	= 1<<0,	/* Queue R2 Parity Error */
 };
 /* Hardware error interrupt mask for Yukon 2 */
 enum {
 	Y2_IS_TIST_OV	= 1<<29,/* Time Stamp Timer overflow interrupt */
 	Y2_IS_SENSOR	= 1<<28, /* Sensor interrupt */
 	Y2_IS_MST_ERR	= 1<<27, /* Master error interrupt */
 	Y2_IS_IRQ_STAT	= 1<<26, /* Status exception interrupt */
 	Y2_IS_PCI_EXP	= 1<<25, /* PCI-Express interrupt */
 	Y2_IS_PCI_NEXP	= 1<<24, /* PCI-Express error similar to PCI error */
 						/* Link 2 */
 	Y2_IS_PAR_RD2	= 1<<13, /* Read RAM parity error interrupt */
 	Y2_IS_PAR_WR2	= 1<<12, /* Write RAM parity error interrupt */
 	Y2_IS_PAR_MAC2	= 1<<11, /* MAC hardware fault interrupt */
 	Y2_IS_PAR_RX2	= 1<<10, /* Parity Error Rx Queue 2 */
 	Y2_IS_TCP_TXS2	= 1<<9, /* TCP length mismatch sync Tx queue IRQ */
 	Y2_IS_TCP_TXA2	= 1<<8, /* TCP length mismatch async Tx queue IRQ */
 						/* Link 1 */
 	Y2_IS_PAR_RD1	= 1<<5, /* Read RAM parity error interrupt */
 	Y2_IS_PAR_WR1	= 1<<4, /* Write RAM parity error interrupt */
 	Y2_IS_PAR_MAC1	= 1<<3, /* MAC hardware fault interrupt */
 	Y2_IS_PAR_RX1	= 1<<2, /* Parity Error Rx Queue 1 */
 	Y2_IS_TCP_TXS1	= 1<<1, /* TCP length mismatch sync Tx queue IRQ */
 	Y2_IS_TCP_TXA1	= 1<<0, /* TCP length mismatch async Tx queue IRQ */
 	Y2_HWE_L1_MASK	= Y2_IS_PAR_RD1 | Y2_IS_PAR_WR1 | Y2_IS_PAR_MAC1 |
 			  Y2_IS_PAR_RX1 | Y2_IS_TCP_TXS1| Y2_IS_TCP_TXA1,
 	Y2_HWE_L2_MASK	= Y2_IS_PAR_RD2 | Y2_IS_PAR_WR2 | Y2_IS_PAR_MAC2 |
 			  Y2_IS_PAR_RX2 | Y2_IS_TCP_TXS2| Y2_IS_TCP_TXA2,
 	Y2_HWE_ALL_MASK	= Y2_IS_TIST_OV | Y2_IS_MST_ERR | Y2_IS_IRQ_STAT |
 			  Y2_IS_PCI_EXP |
 			  Y2_HWE_L1_MASK | Y2_HWE_L2_MASK,
 };
 /*	B28_DPT_CTRL	 8 bit	Descriptor Poll Timer Ctrl Reg */
 enum {
 	DPT_START	= 1<<1,
 	DPT_STOP	= 1<<0,
 };
 /*	B2_TST_CTRL1	 8 bit	Test Control Register 1 */
 enum {
 	TST_FRC_DPERR_MR = 1<<7, /* force DATAPERR on MST RD */
 	TST_FRC_DPERR_MW = 1<<6, /* force DATAPERR on MST WR */
 	TST_FRC_DPERR_TR = 1<<5, /* force DATAPERR on TRG RD */
 	TST_FRC_DPERR_TW = 1<<4, /* force DATAPERR on TRG WR */
 	TST_FRC_APERR_M	 = 1<<3, /* force ADDRPERR on MST */
 	TST_FRC_APERR_T	 = 1<<2, /* force ADDRPERR on TRG */
 	TST_CFG_WRITE_ON = 1<<1, /* Enable  Config Reg WR */
 	TST_CFG_WRITE_OFF= 1<<0, /* Disable Config Reg WR */
 };
 /*	B2_MAC_CFG		 8 bit	MAC Configuration / Chip Revision */
 enum {
 	CFG_CHIP_R_MSK	  = 0xf<<4,	/* Bit 7.. 4: Chip Revision */
 					/* Bit 3.. 2:	reserved */
 	CFG_DIS_M2_CLK	  = 1<<1,	/* Disable Clock for 2nd MAC */
 	CFG_SNG_MAC	  = 1<<0,	/* MAC Config: 0=2 MACs / 1=1 MAC*/
 };
 /*	B2_CHIP_ID		 8 bit 	Chip Identification Number */
 enum {
 	CHIP_ID_GENESIS	   = 0x0a, /* Chip ID for GENESIS */
 	CHIP_ID_YUKON	   = 0xb0, /* Chip ID for YUKON */
 	CHIP_ID_YUKON_LITE = 0xb1, /* Chip ID for YUKON-Lite (Rev. A1-A3) */
 	CHIP_ID_YUKON_LP   = 0xb2, /* Chip ID for YUKON-LP */
 	CHIP_ID_YUKON_XL   = 0xb3, /* Chip ID for YUKON-2 XL */
 	CHIP_ID_YUKON_EC_U = 0xb4, /* Chip ID for YUKON-2 EC Ultra */
 	CHIP_ID_YUKON_EC   = 0xb6, /* Chip ID for YUKON-2 EC */
  	CHIP_ID_YUKON_FE   = 0xb7, /* Chip ID for YUKON-2 FE */
 	CHIP_REV_YU_EC_A1    = 0,  /* Chip Rev. for Yukon-EC A1/A0 */
 	CHIP_REV_YU_EC_A2    = 1,  /* Chip Rev. for Yukon-EC A2 */
 	CHIP_REV_YU_EC_A3    = 2,  /* Chip Rev. for Yukon-EC A3 */
 };
 /*	B2_Y2_CLK_GATE	 8 bit	Clock Gating (Yukon-2 only) */
 enum {
 	Y2_STATUS_LNK2_INAC	= 1<<7, /* Status Link 2 inactive (0 = active) */
 	Y2_CLK_GAT_LNK2_DIS	= 1<<6, /* Disable clock gating Link 2 */
 	Y2_COR_CLK_LNK2_DIS	= 1<<5, /* Disable Core clock Link 2 */
 	Y2_PCI_CLK_LNK2_DIS	= 1<<4, /* Disable PCI clock Link 2 */
 	Y2_STATUS_LNK1_INAC	= 1<<3, /* Status Link 1 inactive (0 = active) */
 	Y2_CLK_GAT_LNK1_DIS	= 1<<2, /* Disable clock gating Link 1 */
 	Y2_COR_CLK_LNK1_DIS	= 1<<1, /* Disable Core clock Link 1 */
 	Y2_PCI_CLK_LNK1_DIS	= 1<<0, /* Disable PCI clock Link 1 */
 };
 /*	B2_Y2_HW_RES	8 bit	HW Resources (Yukon-2 only) */
 enum {
 	CFG_LED_MODE_MSK	= 7<<2,	/* Bit  4.. 2:	LED Mode Mask */
 	CFG_LINK_2_AVAIL	= 1<<1,	/* Link 2 available */
 	CFG_LINK_1_AVAIL	= 1<<0,	/* Link 1 available */
 };
 #define CFG_LED_MODE(x)		(((x) & CFG_LED_MODE_MSK) >> 2)
 #define CFG_DUAL_MAC_MSK	(CFG_LINK_2_AVAIL | CFG_LINK_1_AVAIL)
 /* B2_Y2_CLK_CTRL	32 bit	Clock Frequency Control Register (Yukon-2/EC) */
 enum {
 	Y2_CLK_DIV_VAL_MSK	= 0xff<<16,/* Bit 23..16: Clock Divisor Value */
 #define	Y2_CLK_DIV_VAL(x)	(((x)<<16) & Y2_CLK_DIV_VAL_MSK)
 	Y2_CLK_DIV_VAL2_MSK	= 7<<21,   /* Bit 23..21: Clock Divisor Value */
 	Y2_CLK_SELECT2_MSK	= 0x1f<<16,/* Bit 20..16: Clock Select */
 #define Y2_CLK_DIV_VAL_2(x)	(((x)<<21) & Y2_CLK_DIV_VAL2_MSK)
 #define Y2_CLK_SEL_VAL_2(x)	(((x)<<16) & Y2_CLK_SELECT2_MSK)
 	Y2_CLK_DIV_ENA		= 1<<1, /* Enable  Core Clock Division */
 	Y2_CLK_DIV_DIS		= 1<<0,	/* Disable Core Clock Division */
 };
 /*	B2_TI_CTRL		 8 bit	Timer control */
 /*	B2_IRQM_CTRL	 8 bit	IRQ Moderation Timer Control */
 enum {
 	TIM_START	= 1<<2,	/* Start Timer */
 	TIM_STOP	= 1<<1,	/* Stop  Timer */
 	TIM_CLR_IRQ	= 1<<0,	/* Clear Timer IRQ (!IRQM) */
 };
 /*	B2_TI_TEST		 8 Bit	Timer Test */
 /*	B2_IRQM_TEST	 8 bit	IRQ Moderation Timer Test */
 /*	B28_DPT_TST		 8 bit	Descriptor Poll Timer Test Reg */
 enum {
 	TIM_T_ON	= 1<<2,	/* Test mode on */
 	TIM_T_OFF	= 1<<1,	/* Test mode off */
 	TIM_T_STEP	= 1<<0,	/* Test step */
 };
 /*	B3_RAM_ADDR		32 bit	RAM Address, to read or write */
 					/* Bit 31..19:	reserved */
 #define RAM_ADR_RAN	0x0007ffffL	/* Bit 18.. 0:	RAM Address Range */
 /* RAM Interface Registers */
 /*	B3_RI_CTRL		16 bit	RAM Interface Control Register */
 enum {
 	RI_CLR_RD_PERR	= 1<<9,	/* Clear IRQ RAM Read Parity Err */
 	RI_CLR_WR_PERR	= 1<<8,	/* Clear IRQ RAM Write Parity Err*/
 	RI_RST_CLR	= 1<<1,	/* Clear RAM Interface Reset */
 	RI_RST_SET	= 1<<0,	/* Set   RAM Interface Reset */
 };
 #define SK_RI_TO_53	36		/* RAM interface timeout */
 /* Port related registers FIFO, and Arbiter */
 #define SK_REG(port,reg)	(((port)<<7)+(reg))
 /* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
 /*	TXA_ITI_INI		32 bit	Tx Arb Interval Timer Init Val */
 /*	TXA_ITI_VAL		32 bit	Tx Arb Interval Timer Value */
 /*	TXA_LIM_INI		32 bit	Tx Arb Limit Counter Init Val */
 /*	TXA_LIM_VAL		32 bit	Tx Arb Limit Counter Value */
 #define TXA_MAX_VAL	0x00ffffffUL	/* Bit 23.. 0:	Max TXA Timer/Cnt Val */
 /*	TXA_CTRL		 8 bit	Tx Arbiter Control Register */
 enum {
 	TXA_ENA_FSYNC	= 1<<7,	/* Enable  force of sync Tx queue */
 	TXA_DIS_FSYNC	= 1<<6,	/* Disable force of sync Tx queue */
 	TXA_ENA_ALLOC	= 1<<5,	/* Enable  alloc of free bandwidth */
 	TXA_DIS_ALLOC	= 1<<4,	/* Disable alloc of free bandwidth */
 	TXA_START_RC	= 1<<3,	/* Start sync Rate Control */
 	TXA_STOP_RC	= 1<<2,	/* Stop  sync Rate Control */
 	TXA_ENA_ARB	= 1<<1,	/* Enable  Tx Arbiter */
 	TXA_DIS_ARB	= 1<<0,	/* Disable Tx Arbiter */
 };
 /*
  *	Bank 4 - 5
  */
 /* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
 enum {
 	TXA_ITI_INI	= 0x0200,/* 32 bit	Tx Arb Interval Timer Init Val*/
 	TXA_ITI_VAL	= 0x0204,/* 32 bit	Tx Arb Interval Timer Value */
 	TXA_LIM_INI	= 0x0208,/* 32 bit	Tx Arb Limit Counter Init Val */
 	TXA_LIM_VAL	= 0x020c,/* 32 bit	Tx Arb Limit Counter Value */
 	TXA_CTRL	= 0x0210,/*  8 bit	Tx Arbiter Control Register */
 	TXA_TEST	= 0x0211,/*  8 bit	Tx Arbiter Test Register */
 	TXA_STAT	= 0x0212,/*  8 bit	Tx Arbiter Status Register */
 };
 enum {
 	B6_EXT_REG	= 0x0300,/* External registers (GENESIS only) */
 	B7_CFG_SPC	= 0x0380,/* copy of the Configuration register */
 	B8_RQ1_REGS	= 0x0400,/* Receive Queue 1 */
 	B8_RQ2_REGS	= 0x0480,/* Receive Queue 2 */
 	B8_TS1_REGS	= 0x0600,/* Transmit sync queue 1 */
 	B8_TA1_REGS	= 0x0680,/* Transmit async queue 1 */
 	B8_TS2_REGS	= 0x0700,/* Transmit sync queue 2 */
 	B8_TA2_REGS	= 0x0780,/* Transmit sync queue 2 */
 	B16_RAM_REGS	= 0x0800,/* RAM Buffer Registers */
 };
 /* Queue Register Offsets, use Q_ADDR() to access */
 enum {
 	B8_Q_REGS = 0x0400, /* base of Queue registers */
 	Q_D	= 0x00,	/* 8*32	bit	Current Descriptor */
 	Q_DA_L	= 0x20,	/* 32 bit	Current Descriptor Address Low dWord */
 	Q_DA_H	= 0x24,	/* 32 bit	Current Descriptor Address High dWord */
 	Q_AC_L	= 0x28,	/* 32 bit	Current Address Counter Low dWord */
 	Q_AC_H	= 0x2c,	/* 32 bit	Current Address Counter High dWord */
 	Q_BC	= 0x30,	/* 32 bit	Current Byte Counter */
 	Q_CSR	= 0x34,	/* 32 bit	BMU Control/Status Register */
 	Q_F	= 0x38,	/* 32 bit	Flag Register */
 	Q_T1	= 0x3c,	/* 32 bit	Test Register 1 */
 	Q_T1_TR	= 0x3c,	/*  8 bit	Test Register 1 Transfer SM */
 	Q_T1_WR	= 0x3d,	/*  8 bit	Test Register 1 Write Descriptor SM */
 	Q_T1_RD	= 0x3e,	/*  8 bit	Test Register 1 Read Descriptor SM */
 	Q_T1_SV	= 0x3f,	/*  8 bit	Test Register 1 Supervisor SM */
 	Q_T2	= 0x40,	/* 32 bit	Test Register 2	*/
 	Q_T3	= 0x44,	/* 32 bit	Test Register 3	*/
 /* Yukon-2 */
 	Q_DONE	= 0x24,	/* 16 bit	Done Index 		(Yukon-2 only) */
 	Q_WM	= 0x40,	/* 16 bit	FIFO Watermark */
 	Q_AL	= 0x42,	/*  8 bit	FIFO Alignment */
 	Q_RSP	= 0x44,	/* 16 bit	FIFO Read Shadow Pointer */
 	Q_RSL	= 0x46,	/*  8 bit	FIFO Read Shadow Level */
 	Q_RP	= 0x48,	/*  8 bit	FIFO Read Pointer */
 	Q_RL	= 0x4a,	/*  8 bit	FIFO Read Level */
 	Q_WP	= 0x4c,	/*  8 bit	FIFO Write Pointer */
 	Q_WSP	= 0x4d,	/*  8 bit	FIFO Write Shadow Pointer */
 	Q_WL	= 0x4e,	/*  8 bit	FIFO Write Level */
 	Q_WSL	= 0x4f,	/*  8 bit	FIFO Write Shadow Level */
 };
 #define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs))
 /*	Q_F				32 bit	Flag Register */
 enum {
 	F_ALM_FULL	= 1<<27, /* Rx FIFO: almost full */
 	F_EMPTY		= 1<<27, /* Tx FIFO: empty flag */
 	F_FIFO_EOF	= 1<<26, /* Tag (EOF Flag) bit in FIFO */
 	F_WM_REACHED	= 1<<25, /* Watermark reached */
 	F_M_RX_RAM_DIS	= 1<<24, /* MAC Rx RAM Read Port disable */
 	F_FIFO_LEVEL	= 0x1fL<<16, /* Bit 23..16:	# of Qwords in FIFO */
 	F_WATER_MARK	= 0x0007ffL, /* Bit 10.. 0:	Watermark */
 };
 /* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/
 enum {
 	Y2_B8_PREF_REGS		= 0x0450,
 	PREF_UNIT_CTRL		= 0x00,	/* 32 bit	Control register */
 	PREF_UNIT_LAST_IDX	= 0x04,	/* 16 bit	Last Index */
 	PREF_UNIT_ADDR_LO	= 0x08,	/* 32 bit	List start addr, low part */
 	PREF_UNIT_ADDR_HI	= 0x0c,	/* 32 bit	List start addr, high part*/
 	PREF_UNIT_GET_IDX	= 0x10,	/* 16 bit	Get Index */
 	PREF_UNIT_PUT_IDX	= 0x14,	/* 16 bit	Put Index */
 	PREF_UNIT_FIFO_WP	= 0x20,	/*  8 bit	FIFO write pointer */
 	PREF_UNIT_FIFO_RP	= 0x24,	/*  8 bit	FIFO read pointer */
 	PREF_UNIT_FIFO_WM	= 0x28,	/*  8 bit	FIFO watermark */
 	PREF_UNIT_FIFO_LEV	= 0x2c,	/*  8 bit	FIFO level */
 	PREF_UNIT_MASK_IDX	= 0x0fff,
 };
 #define Y2_QADDR(q,reg)		(Y2_B8_PREF_REGS + (q) + (reg))
 /* RAM Buffer Register Offsets */
 enum {
 	RB_START	= 0x00,/* 32 bit	RAM Buffer Start Address */
 	RB_END	= 0x04,/* 32 bit	RAM Buffer End Address */
 	RB_WP	= 0x08,/* 32 bit	RAM Buffer Write Pointer */
 	RB_RP	= 0x0c,/* 32 bit	RAM Buffer Read Pointer */
 	RB_RX_UTPP	= 0x10,/* 32 bit	Rx Upper Threshold, Pause Packet */
 	RB_RX_LTPP	= 0x14,/* 32 bit	Rx Lower Threshold, Pause Packet */
 	RB_RX_UTHP	= 0x18,/* 32 bit	Rx Upper Threshold, High Prio */
 	RB_RX_LTHP	= 0x1c,/* 32 bit	Rx Lower Threshold, High Prio */
 	/* 0x10 - 0x1f:	reserved at Tx RAM Buffer Registers */
 	RB_PC	= 0x20,/* 32 bit	RAM Buffer Packet Counter */
 	RB_LEV	= 0x24,/* 32 bit	RAM Buffer Level Register */
 	RB_CTRL	= 0x28,/* 32 bit	RAM Buffer Control Register */
 	RB_TST1	= 0x29,/*  8 bit	RAM Buffer Test Register 1 */
 	RB_TST2	= 0x2a,/*  8 bit	RAM Buffer Test Register 2 */
 };
 /* Receive and Transmit Queues */
 enum {
 	Q_R1	= 0x0000,	/* Receive Queue 1 */
 	Q_R2	= 0x0080,	/* Receive Queue 2 */
 	Q_XS1	= 0x0200,	/* Synchronous Transmit Queue 1 */
 	Q_XA1	= 0x0280,	/* Asynchronous Transmit Queue 1 */
 	Q_XS2	= 0x0300,	/* Synchronous Transmit Queue 2 */
 	Q_XA2	= 0x0380,	/* Asynchronous Transmit Queue 2 */
 };
 /* Different PHY Types */
 enum {
 	PHY_ADDR_MARV	= 0,
 };
 #define RB_ADDR(offs, queue) (B16_RAM_REGS + (queue) + (offs))
 enum {
 	LNK_SYNC_INI	= 0x0c30,/* 32 bit	Link Sync Cnt Init Value */
 	LNK_SYNC_VAL	= 0x0c34,/* 32 bit	Link Sync Cnt Current Value */
 	LNK_SYNC_CTRL	= 0x0c38,/*  8 bit	Link Sync Cnt Control Register */
 	LNK_SYNC_TST	= 0x0c39,/*  8 bit	Link Sync Cnt Test Register */
 	LNK_LED_REG	= 0x0c3c,/*  8 bit	Link LED Register */
 /* Receive GMAC FIFO (YUKON and Yukon-2) */
 	RX_GMF_EA	= 0x0c40,/* 32 bit	Rx GMAC FIFO End Address */
 	RX_GMF_AF_THR	= 0x0c44,/* 32 bit	Rx GMAC FIFO Almost Full Thresh. */
 	RX_GMF_CTRL_T	= 0x0c48,/* 32 bit	Rx GMAC FIFO Control/Test */
 	RX_GMF_FL_MSK	= 0x0c4c,/* 32 bit	Rx GMAC FIFO Flush Mask */
 	RX_GMF_FL_THR	= 0x0c50,/* 32 bit	Rx GMAC FIFO Flush Threshold */
 	RX_GMF_TR_THR	= 0x0c54,/* 32 bit	Rx Truncation Threshold (Yukon-2) */
 	RX_GMF_UP_THR	= 0x0c58,/*  8 bit	Rx Upper Pause Thr (Yukon-EC_U) */
 	RX_GMF_LP_THR	= 0x0c5a,/*  8 bit	Rx Lower Pause Thr (Yukon-EC_U) */
 	RX_GMF_VLAN	= 0x0c5c,/* 32 bit	Rx VLAN Type Register (Yukon-2) */
 	RX_GMF_WP	= 0x0c60,/* 32 bit	Rx GMAC FIFO Write Pointer */
 	RX_GMF_WLEV	= 0x0c68,/* 32 bit	Rx GMAC FIFO Write Level */
 	RX_GMF_RP	= 0x0c70,/* 32 bit	Rx GMAC FIFO Read Pointer */
 	RX_GMF_RLEV	= 0x0c78,/* 32 bit	Rx GMAC FIFO Read Level */
 };
 /*	Q_BC			32 bit	Current Byte Counter */
 /* BMU Control Status Registers */
 /*	B0_R1_CSR		32 bit	BMU Ctrl/Stat Rx Queue 1 */
 /*	B0_R2_CSR		32 bit	BMU Ctrl/Stat Rx Queue 2 */
 /*	B0_XA1_CSR		32 bit	BMU Ctrl/Stat Sync Tx Queue 1 */
 /*	B0_XS1_CSR		32 bit	BMU Ctrl/Stat Async Tx Queue 1 */
 /*	B0_XA2_CSR		32 bit	BMU Ctrl/Stat Sync Tx Queue 2 */
 /*	B0_XS2_CSR		32 bit	BMU Ctrl/Stat Async Tx Queue 2 */
 /*	Q_CSR			32 bit	BMU Control/Status Register */
 /* Rx BMU Control / Status Registers (Yukon-2) */
 enum {
 	BMU_IDLE	= 1<<31, /* BMU Idle State */
 	BMU_RX_TCP_PKT	= 1<<30, /* Rx TCP Packet (when RSS Hash enabled) */
 	BMU_RX_IP_PKT	= 1<<29, /* Rx IP  Packet (when RSS Hash enabled) */
 	BMU_ENA_RX_RSS_HASH = 1<<15, /* Enable  Rx RSS Hash */
 	BMU_DIS_RX_RSS_HASH = 1<<14, /* Disable Rx RSS Hash */
 	BMU_ENA_RX_CHKSUM = 1<<13, /* Enable  Rx TCP/IP Checksum Check */
 	BMU_DIS_RX_CHKSUM = 1<<12, /* Disable Rx TCP/IP Checksum Check */
 	BMU_CLR_IRQ_PAR	= 1<<11, /* Clear IRQ on Parity errors (Rx) */
 	BMU_CLR_IRQ_TCP	= 1<<11, /* Clear IRQ on TCP segment. error (Tx) */
 	BMU_CLR_IRQ_CHK	= 1<<10, /* Clear IRQ Check */
 	BMU_STOP	= 1<<9, /* Stop  Rx/Tx Queue */
 	BMU_START	= 1<<8, /* Start Rx/Tx Queue */
 	BMU_FIFO_OP_ON	= 1<<7, /* FIFO Operational On */
 	BMU_FIFO_OP_OFF	= 1<<6, /* FIFO Operational Off */
 	BMU_FIFO_ENA	= 1<<5, /* Enable FIFO */
 	BMU_FIFO_RST	= 1<<4, /* Reset  FIFO */
 	BMU_OP_ON	= 1<<3, /* BMU Operational On */
 	BMU_OP_OFF	= 1<<2, /* BMU Operational Off */
 	BMU_RST_CLR	= 1<<1, /* Clear BMU Reset (Enable) */
 	BMU_RST_SET	= 1<<0, /* Set   BMU Reset */
 	BMU_CLR_RESET	= BMU_FIFO_RST | BMU_OP_OFF | BMU_RST_CLR,
 	BMU_OPER_INIT	= BMU_CLR_IRQ_PAR | BMU_CLR_IRQ_CHK | BMU_START |
 			  BMU_FIFO_ENA | BMU_OP_ON,
 	BMU_WM_DEFAULT = 0x600,
 };
 /* Tx BMU Control / Status Registers (Yukon-2) */
 								/* Bit 31: same as for Rx */
 enum {
 	BMU_TX_IPIDINCR_ON	= 1<<13, /* Enable  IP ID Increment */
 	BMU_TX_IPIDINCR_OFF	= 1<<12, /* Disable IP ID Increment */
 	BMU_TX_CLR_IRQ_TCP	= 1<<11, /* Clear IRQ on TCP segment length mismatch */
 };
 /* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/
 /* PREF_UNIT_CTRL	32 bit	Prefetch Control register */
 enum {
 	PREF_UNIT_OP_ON		= 1<<3,	/* prefetch unit operational */
 	PREF_UNIT_OP_OFF	= 1<<2,	/* prefetch unit not operational */
 	PREF_UNIT_RST_CLR	= 1<<1,	/* Clear Prefetch Unit Reset */
 	PREF_UNIT_RST_SET	= 1<<0,	/* Set   Prefetch Unit Reset */
 };
 /* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */
 /*	RB_START		32 bit	RAM Buffer Start Address */
 /*	RB_END			32 bit	RAM Buffer End Address */
 /*	RB_WP			32 bit	RAM Buffer Write Pointer */
 /*	RB_RP			32 bit	RAM Buffer Read Pointer */
 /*	RB_RX_UTPP		32 bit	Rx Upper Threshold, Pause Pack */
 /*	RB_RX_LTPP		32 bit	Rx Lower Threshold, Pause Pack */
 /*	RB_RX_UTHP		32 bit	Rx Upper Threshold, High Prio */
 /*	RB_RX_LTHP		32 bit	Rx Lower Threshold, High Prio */
 /*	RB_PC			32 bit	RAM Buffer Packet Counter */
 /*	RB_LEV			32 bit	RAM Buffer Level Register */
 #define RB_MSK	0x0007ffff	/* Bit 18.. 0:	RAM Buffer Pointer Bits */
 /*	RB_TST2			 8 bit	RAM Buffer Test Register 2 */
 /*	RB_TST1			 8 bit	RAM Buffer Test Register 1 */
 /*	RB_CTRL			 8 bit	RAM Buffer Control Register */
 enum {
 	RB_ENA_STFWD	= 1<<5,	/* Enable  Store & Forward */
 	RB_DIS_STFWD	= 1<<4,	/* Disable Store & Forward */
 	RB_ENA_OP_MD	= 1<<3,	/* Enable  Operation Mode */
 	RB_DIS_OP_MD	= 1<<2,	/* Disable Operation Mode */
 	RB_RST_CLR	= 1<<1,	/* Clear RAM Buf STM Reset */
 	RB_RST_SET	= 1<<0,	/* Set   RAM Buf STM Reset */
 };
 /* Transmit GMAC FIFO (YUKON only) */
 enum {
 	TX_GMF_EA	= 0x0d40,/* 32 bit	Tx GMAC FIFO End Address */
 	TX_GMF_AE_THR	= 0x0d44,/* 32 bit	Tx GMAC FIFO Almost Empty Thresh.*/
 	TX_GMF_CTRL_T	= 0x0d48,/* 32 bit	Tx GMAC FIFO Control/Test */
 	TX_GMF_WP	= 0x0d60,/* 32 bit 	Tx GMAC FIFO Write Pointer */
 	TX_GMF_WSP	= 0x0d64,/* 32 bit 	Tx GMAC FIFO Write Shadow Ptr. */
 	TX_GMF_WLEV	= 0x0d68,/* 32 bit 	Tx GMAC FIFO Write Level */
 	TX_GMF_RP	= 0x0d70,/* 32 bit 	Tx GMAC FIFO Read Pointer */
 	TX_GMF_RSTP	= 0x0d74,/* 32 bit 	Tx GMAC FIFO Restart Pointer */
 	TX_GMF_RLEV	= 0x0d78,/* 32 bit 	Tx GMAC FIFO Read Level */
 };
 /* Descriptor Poll Timer Registers */
 enum {
 	B28_DPT_INI	= 0x0e00,/* 24 bit	Descriptor Poll Timer Init Val */
 	B28_DPT_VAL	= 0x0e04,/* 24 bit	Descriptor Poll Timer Curr Val */
 	B28_DPT_CTRL	= 0x0e08,/*  8 bit	Descriptor Poll Timer Ctrl Reg */
 	B28_DPT_TST	= 0x0e0a,/*  8 bit	Descriptor Poll Timer Test Reg */
 };
 /* Time Stamp Timer Registers (YUKON only) */
 enum {
 	GMAC_TI_ST_VAL	= 0x0e14,/* 32 bit	Time Stamp Timer Curr Val */
 	GMAC_TI_ST_CTRL	= 0x0e18,/*  8 bit	Time Stamp Timer Ctrl Reg */
 	GMAC_TI_ST_TST	= 0x0e1a,/*  8 bit	Time Stamp Timer Test Reg */
 };
 /* Polling Unit Registers (Yukon-2 only) */
 enum {
 	POLL_CTRL	= 0x0e20, /* 32 bit	Polling Unit Control Reg */
 	POLL_LAST_IDX	= 0x0e24,/* 16 bit	Polling Unit List Last Index */
 	POLL_LIST_ADDR_LO= 0x0e28,/* 32 bit	Poll. List Start Addr (low) */
 	POLL_LIST_ADDR_HI= 0x0e2c,/* 32 bit	Poll. List Start Addr (high) */
 };
 /* ASF Subsystem Registers (Yukon-2 only) */
 enum {
 	B28_Y2_SMB_CONFIG  = 0x0e40,/* 32 bit	ASF SMBus Config Register */
 	B28_Y2_SMB_CSD_REG = 0x0e44,/* 32 bit	ASF SMB Control/Status/Data */
 	B28_Y2_ASF_IRQ_V_BASE=0x0e60,/* 32 bit	ASF IRQ Vector Base */
 	B28_Y2_ASF_STAT_CMD= 0x0e68,/* 32 bit	ASF Status and Command Reg */
 	B28_Y2_ASF_HOST_COM= 0x0e6c,/* 32 bit	ASF Host Communication Reg */
 	B28_Y2_DATA_REG_1  = 0x0e70,/* 32 bit	ASF/Host Data Register 1 */
 	B28_Y2_DATA_REG_2  = 0x0e74,/* 32 bit	ASF/Host Data Register 2 */
 	B28_Y2_DATA_REG_3  = 0x0e78,/* 32 bit	ASF/Host Data Register 3 */
 	B28_Y2_DATA_REG_4  = 0x0e7c,/* 32 bit	ASF/Host Data Register 4 */
 };
 /* Status BMU Registers (Yukon-2 only)*/
 enum {
 	STAT_CTRL	= 0x0e80,/* 32 bit	Status BMU Control Reg */
 	STAT_LAST_IDX	= 0x0e84,/* 16 bit	Status BMU Last Index */
 	STAT_LIST_ADDR_LO= 0x0e88,/* 32 bit	Status List Start Addr (low) */
 	STAT_LIST_ADDR_HI= 0x0e8c,/* 32 bit	Status List Start Addr (high) */
 	STAT_TXA1_RIDX	= 0x0e90,/* 16 bit	Status TxA1 Report Index Reg */
 	STAT_TXS1_RIDX	= 0x0e92,/* 16 bit	Status TxS1 Report Index Reg */
 	STAT_TXA2_RIDX	= 0x0e94,/* 16 bit	Status TxA2 Report Index Reg */
 	STAT_TXS2_RIDX	= 0x0e96,/* 16 bit	Status TxS2 Report Index Reg */
 	STAT_TX_IDX_TH	= 0x0e98,/* 16 bit	Status Tx Index Threshold Reg */
 	STAT_PUT_IDX	= 0x0e9c,/* 16 bit	Status Put Index Reg */
 /* FIFO Control/Status Registers (Yukon-2 only)*/
 	STAT_FIFO_WP	= 0x0ea0,/*  8 bit	Status FIFO Write Pointer Reg */
 	STAT_FIFO_RP	= 0x0ea4,/*  8 bit	Status FIFO Read Pointer Reg */
 	STAT_FIFO_RSP	= 0x0ea6,/*  8 bit	Status FIFO Read Shadow Ptr */
 	STAT_FIFO_LEVEL	= 0x0ea8,/*  8 bit	Status FIFO Level Reg */
 	STAT_FIFO_SHLVL	= 0x0eaa,/*  8 bit	Status FIFO Shadow Level Reg */
 	STAT_FIFO_WM	= 0x0eac,/*  8 bit	Status FIFO Watermark Reg */
 	STAT_FIFO_ISR_WM= 0x0ead,/*  8 bit	Status FIFO ISR Watermark Reg */
 /* Level and ISR Timer Registers (Yukon-2 only)*/
 	STAT_LEV_TIMER_INI= 0x0eb0,/* 32 bit	Level Timer Init. Value Reg */
 	STAT_LEV_TIMER_CNT= 0x0eb4,/* 32 bit	Level Timer Counter Reg */
 	STAT_LEV_TIMER_CTRL= 0x0eb8,/*  8 bit	Level Timer Control Reg */
 	STAT_LEV_TIMER_TEST= 0x0eb9,/*  8 bit	Level Timer Test Reg */
 	STAT_TX_TIMER_INI  = 0x0ec0,/* 32 bit	Tx Timer Init. Value Reg */
 	STAT_TX_TIMER_CNT  = 0x0ec4,/* 32 bit	Tx Timer Counter Reg */
 	STAT_TX_TIMER_CTRL = 0x0ec8,/*  8 bit	Tx Timer Control Reg */
 	STAT_TX_TIMER_TEST = 0x0ec9,/*  8 bit	Tx Timer Test Reg */
 	STAT_ISR_TIMER_INI = 0x0ed0,/* 32 bit	ISR Timer Init. Value Reg */
 	STAT_ISR_TIMER_CNT = 0x0ed4,/* 32 bit	ISR Timer Counter Reg */
 	STAT_ISR_TIMER_CTRL= 0x0ed8,/*  8 bit	ISR Timer Control Reg */
 	STAT_ISR_TIMER_TEST= 0x0ed9,/*  8 bit	ISR Timer Test Reg */
 };
 enum {
 	LINKLED_OFF 	     = 0x01,
 	LINKLED_ON  	     = 0x02,
 	LINKLED_LINKSYNC_OFF = 0x04,
 	LINKLED_LINKSYNC_ON  = 0x08,
 	LINKLED_BLINK_OFF    = 0x10,
 	LINKLED_BLINK_ON     = 0x20,
 };
 /* GMAC and GPHY Control Registers (YUKON only) */
 enum {
 	GMAC_CTRL	= 0x0f00,/* 32 bit	GMAC Control Reg */
 	GPHY_CTRL	= 0x0f04,/* 32 bit	GPHY Control Reg */
 	GMAC_IRQ_SRC	= 0x0f08,/*  8 bit	GMAC Interrupt Source Reg */
 	GMAC_IRQ_MSK	= 0x0f0c,/*  8 bit	GMAC Interrupt Mask Reg */
 	GMAC_LINK_CTRL	= 0x0f10,/* 16 bit	Link Control Reg */
 /* Wake-up Frame Pattern Match Control Registers (YUKON only) */
 	WOL_REG_OFFS	= 0x20,/* HW-Bug: Address is + 0x20 against spec. */
 	WOL_CTRL_STAT	= 0x0f20,/* 16 bit	WOL Control/Status Reg */
 	WOL_MATCH_CTL	= 0x0f22,/*  8 bit	WOL Match Control Reg */
 	WOL_MATCH_RES	= 0x0f23,/*  8 bit	WOL Match Result Reg */
 	WOL_MAC_ADDR	= 0x0f24,/* 32 bit	WOL MAC Address */
 	WOL_PATT_PME	= 0x0f2a,/*  8 bit	WOL PME Match Enable (Yukon-2) */
 	WOL_PATT_ASFM	= 0x0f2b,/*  8 bit	WOL ASF Match Enable (Yukon-2) */
 	WOL_PATT_RPTR	= 0x0f2c,/*  8 bit	WOL Pattern Read Pointer */
 /* WOL Pattern Length Registers (YUKON only) */
 	WOL_PATT_LEN_LO	= 0x0f30,/* 32 bit	WOL Pattern Length 3..0 */
 	WOL_PATT_LEN_HI	= 0x0f34,/* 24 bit	WOL Pattern Length 6..4 */
 /* WOL Pattern Counter Registers (YUKON only) */
 	WOL_PATT_CNT_0	= 0x0f38,/* 32 bit	WOL Pattern Counter 3..0 */
 	WOL_PATT_CNT_4	= 0x0f3c,/* 24 bit	WOL Pattern Counter 6..4 */
 };
 enum {
 	WOL_PATT_RAM_1	= 0x1000,/*  WOL Pattern RAM Link 1 */
 	WOL_PATT_RAM_2	= 0x1400,/*  WOL Pattern RAM Link 2 */
 };
 enum {
 	BASE_GMAC_1	= 0x2800,/* GMAC 1 registers */
 	BASE_GMAC_2	= 0x3800,/* GMAC 2 registers */
 };
 /*
  * Marvel-PHY Registers, indirect addressed over GMAC
  */
 enum {
 	PHY_MARV_CTRL		= 0x00,/* 16 bit r/w	PHY Control Register */
 	PHY_MARV_STAT		= 0x01,/* 16 bit r/o	PHY Status Register */
 	PHY_MARV_ID0		= 0x02,/* 16 bit r/o	PHY ID0 Register */
 	PHY_MARV_ID1		= 0x03,/* 16 bit r/o	PHY ID1 Register */
 	PHY_MARV_AUNE_ADV	= 0x04,/* 16 bit r/w	Auto-Neg. Advertisement */
 	PHY_MARV_AUNE_LP	= 0x05,/* 16 bit r/o	Link Part Ability Reg */
 	PHY_MARV_AUNE_EXP	= 0x06,/* 16 bit r/o	Auto-Neg. Expansion Reg */
 	PHY_MARV_NEPG		= 0x07,/* 16 bit r/w	Next Page Register */
 	PHY_MARV_NEPG_LP	= 0x08,/* 16 bit r/o	Next Page Link Partner */
 	/* Marvel-specific registers */
 	PHY_MARV_1000T_CTRL	= 0x09,/* 16 bit r/w	1000Base-T Control Reg */
 	PHY_MARV_1000T_STAT	= 0x0a,/* 16 bit r/o	1000Base-T Status Reg */
 	PHY_MARV_EXT_STAT	= 0x0f,/* 16 bit r/o	Extended Status Reg */
 	PHY_MARV_PHY_CTRL	= 0x10,/* 16 bit r/w	PHY Specific Ctrl Reg */
 	PHY_MARV_PHY_STAT	= 0x11,/* 16 bit r/o	PHY Specific Stat Reg */
 	PHY_MARV_INT_MASK	= 0x12,/* 16 bit r/w	Interrupt Mask Reg */
 	PHY_MARV_INT_STAT	= 0x13,/* 16 bit r/o	Interrupt Status Reg */
 	PHY_MARV_EXT_CTRL	= 0x14,/* 16 bit r/w	Ext. PHY Specific Ctrl */
 	PHY_MARV_RXE_CNT	= 0x15,/* 16 bit r/w	Receive Error Counter */
 	PHY_MARV_EXT_ADR	= 0x16,/* 16 bit r/w	Ext. Ad. for Cable Diag. */
 	PHY_MARV_PORT_IRQ	= 0x17,/* 16 bit r/o	Port 0 IRQ (88E1111 only) */
 	PHY_MARV_LED_CTRL	= 0x18,/* 16 bit r/w	LED Control Reg */
 	PHY_MARV_LED_OVER	= 0x19,/* 16 bit r/w	Manual LED Override Reg */
 	PHY_MARV_EXT_CTRL_2	= 0x1a,/* 16 bit r/w	Ext. PHY Specific Ctrl 2 */
 	PHY_MARV_EXT_P_STAT	= 0x1b,/* 16 bit r/w	Ext. PHY Spec. Stat Reg */
 	PHY_MARV_CABLE_DIAG	= 0x1c,/* 16 bit r/o	Cable Diagnostic Reg */
 	PHY_MARV_PAGE_ADDR	= 0x1d,/* 16 bit r/w	Extended Page Address Reg */
 	PHY_MARV_PAGE_DATA	= 0x1e,/* 16 bit r/w	Extended Page Data Reg */
 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
 	PHY_MARV_FE_LED_PAR	= 0x16,/* 16 bit r/w	LED Parallel Select Reg. */
 	PHY_MARV_FE_LED_SER	= 0x17,/* 16 bit r/w	LED Stream Select S. LED */
 	PHY_MARV_FE_VCT_TX	= 0x1a,/* 16 bit r/w	VCT Reg. for TXP/N Pins */
 	PHY_MARV_FE_VCT_RX	= 0x1b,/* 16 bit r/o	VCT Reg. for RXP/N Pins */
 	PHY_MARV_FE_SPEC_2	= 0x1c,/* 16 bit r/w	Specific Control Reg. 2 */
 };
 enum {
 	PHY_CT_RESET	= 1<<15, /* Bit 15: (sc)	clear all PHY related regs */
 	PHY_CT_LOOP	= 1<<14, /* Bit 14:	enable Loopback over PHY */
 	PHY_CT_SPS_LSB	= 1<<13, /* Bit 13:	Speed select, lower bit */
 	PHY_CT_ANE	= 1<<12, /* Bit 12:	Auto-Negotiation Enabled */
 	PHY_CT_PDOWN	= 1<<11, /* Bit 11:	Power Down Mode */
 	PHY_CT_ISOL	= 1<<10, /* Bit 10:	Isolate Mode */
 	PHY_CT_RE_CFG	= 1<<9, /* Bit  9:	(sc) Restart Auto-Negotiation */
 	PHY_CT_DUP_MD	= 1<<8, /* Bit  8:	Duplex Mode */
 	PHY_CT_COL_TST	= 1<<7, /* Bit  7:	Collision Test enabled */
 	PHY_CT_SPS_MSB	= 1<<6, /* Bit  6:	Speed select, upper bit */
 };
 enum {
 	PHY_CT_SP1000	= PHY_CT_SPS_MSB, /* enable speed of 1000 Mbps */
 	PHY_CT_SP100	= PHY_CT_SPS_LSB, /* enable speed of  100 Mbps */
 	PHY_CT_SP10	= 0,		  /* enable speed of   10 Mbps */
 };
 enum {
 	PHY_ST_EXT_ST	= 1<<8, /* Bit  8:	Extended Status Present */
 	PHY_ST_PRE_SUP	= 1<<6, /* Bit  6:	Preamble Suppression */
 	PHY_ST_AN_OVER	= 1<<5, /* Bit  5:	Auto-Negotiation Over */
 	PHY_ST_REM_FLT	= 1<<4, /* Bit  4:	Remote Fault Condition Occured */
 	PHY_ST_AN_CAP	= 1<<3, /* Bit  3:	Auto-Negotiation Capability */
 	PHY_ST_LSYNC	= 1<<2, /* Bit  2:	Link Synchronized */
 	PHY_ST_JAB_DET	= 1<<1, /* Bit  1:	Jabber Detected */
 	PHY_ST_EXT_REG	= 1<<0, /* Bit  0:	Extended Register available */
 };
 enum {
 	PHY_I1_OUI_MSK	= 0x3f<<10, /* Bit 15..10:	Organization Unique ID */
 	PHY_I1_MOD_NUM	= 0x3f<<4, /* Bit  9.. 4:	Model Number */
 	PHY_I1_REV_MSK	= 0xf, /* Bit  3.. 0:	Revision Number */
 };
 /* different Marvell PHY Ids */
 enum {
 	PHY_MARV_ID0_VAL= 0x0141, /* Marvell Unique Identifier */
 	PHY_BCOM_ID1_A1	= 0x6041,
 	PHY_BCOM_ID1_B2	= 0x6043,
 	PHY_BCOM_ID1_C0	= 0x6044,
 	PHY_BCOM_ID1_C5	= 0x6047,
 	PHY_MARV_ID1_B0	= 0x0C23, /* Yukon 	(PHY 88E1011) */
 	PHY_MARV_ID1_B2	= 0x0C25, /* Yukon-Plus (PHY 88E1011) */
 	PHY_MARV_ID1_C2	= 0x0CC2, /* Yukon-EC	(PHY 88E1111) */
 	PHY_MARV_ID1_Y2	= 0x0C91, /* Yukon-2	(PHY 88E1112) */
 	PHY_MARV_ID1_FE = 0x0C83, /* Yukon-FE   (PHY 88E3082 Rev.A1) */
 	PHY_MARV_ID1_ECU= 0x0CB0, /* Yukon-ECU  (PHY 88E1149 Rev.B2?) */
 };
 /* Advertisement register bits */
 enum {
 	PHY_AN_NXT_PG	= 1<<15, /* Bit 15:	Request Next Page */
 	PHY_AN_ACK	= 1<<14, /* Bit 14:	(ro) Acknowledge Received */
 	PHY_AN_RF	= 1<<13, /* Bit 13:	Remote Fault Bits */
 	PHY_AN_PAUSE_ASYM = 1<<11,/* Bit 11:	Try for asymmetric */
 	PHY_AN_PAUSE_CAP = 1<<10, /* Bit 10:	Try for pause */
 	PHY_AN_100BASE4	= 1<<9, /* Bit 9:	Try for 100mbps 4k packets */
 	PHY_AN_100FULL	= 1<<8, /* Bit 8:	Try for 100mbps full-duplex */
 	PHY_AN_100HALF	= 1<<7, /* Bit 7:	Try for 100mbps half-duplex */
 	PHY_AN_10FULL	= 1<<6, /* Bit 6:	Try for 10mbps full-duplex */
 	PHY_AN_10HALF	= 1<<5, /* Bit 5:	Try for 10mbps half-duplex */
 	PHY_AN_CSMA	= 1<<0, /* Bit 0:	Only selector supported */
 	PHY_AN_SEL	= 0x1f, /* Bit 4..0:	Selector Field, 00001=Ethernet*/
 	PHY_AN_FULL	= PHY_AN_100FULL | PHY_AN_10FULL | PHY_AN_CSMA,
 	PHY_AN_ALL	= PHY_AN_10HALF | PHY_AN_10FULL |
 		  	  PHY_AN_100HALF | PHY_AN_100FULL,
 };
 /*****  PHY_BCOM_1000T_STAT	16 bit r/o	1000Base-T Status Reg *****/
 /*****  PHY_MARV_1000T_STAT	16 bit r/o	1000Base-T Status Reg *****/
 enum {
 	PHY_B_1000S_MSF	= 1<<15, /* Bit 15:	Master/Slave Fault */
 	PHY_B_1000S_MSR	= 1<<14, /* Bit 14:	Master/Slave Result */
 	PHY_B_1000S_LRS	= 1<<13, /* Bit 13:	Local Receiver Status */
 	PHY_B_1000S_RRS	= 1<<12, /* Bit 12:	Remote Receiver Status */
 	PHY_B_1000S_LP_FD	= 1<<11, /* Bit 11:	Link Partner can FD */
 	PHY_B_1000S_LP_HD	= 1<<10, /* Bit 10:	Link Partner can HD */
 									/* Bit  9..8:	reserved */
 	PHY_B_1000S_IEC	= 0xff, /* Bit  7..0:	Idle Error Count */
 };
 /** Marvell-Specific */
 enum {
 	PHY_M_AN_NXT_PG	= 1<<15, /* Request Next Page */
 	PHY_M_AN_ACK	= 1<<14, /* (ro)	Acknowledge Received */
 	PHY_M_AN_RF	= 1<<13, /* Remote Fault */
 	PHY_M_AN_ASP	= 1<<11, /* Asymmetric Pause */
 	PHY_M_AN_PC	= 1<<10, /* MAC Pause implemented */
 	PHY_M_AN_100_T4	= 1<<9, /* Not cap. 100Base-T4 (always 0) */
 	PHY_M_AN_100_FD	= 1<<8, /* Advertise 100Base-TX Full Duplex */
 	PHY_M_AN_100_HD	= 1<<7, /* Advertise 100Base-TX Half Duplex */
 	PHY_M_AN_10_FD	= 1<<6, /* Advertise 10Base-TX Full Duplex */
 	PHY_M_AN_10_HD	= 1<<5, /* Advertise 10Base-TX Half Duplex */
 	PHY_M_AN_SEL_MSK =0x1f<<4,	/* Bit  4.. 0: Selector Field Mask */
 };
 /* special defines for FIBER (88E1011S only) */
 enum {
 	PHY_M_AN_ASP_X	= 1<<8, /* Asymmetric Pause */
 	PHY_M_AN_PC_X	= 1<<7, /* MAC Pause implemented */
 	PHY_M_AN_1000X_AHD	= 1<<6, /* Advertise 10000Base-X Half Duplex */
 	PHY_M_AN_1000X_AFD	= 1<<5, /* Advertise 10000Base-X Full Duplex */
 };
 /* Pause Bits (PHY_M_AN_ASP_X and PHY_M_AN_PC_X) encoding */
 enum {
 	PHY_M_P_NO_PAUSE_X	= 0<<7,/* Bit  8.. 7:	no Pause Mode */
 	PHY_M_P_SYM_MD_X	= 1<<7, /* Bit  8.. 7:	symmetric Pause Mode */
 	PHY_M_P_ASYM_MD_X	= 2<<7,/* Bit  8.. 7:	asymmetric Pause Mode */
 	PHY_M_P_BOTH_MD_X	= 3<<7,/* Bit  8.. 7:	both Pause Mode */
 };
 /*****  PHY_MARV_1000T_CTRL	16 bit r/w	1000Base-T Control Reg *****/
 enum {
 	PHY_M_1000C_TEST	= 7<<13,/* Bit 15..13:	Test Modes */
 	PHY_M_1000C_MSE	= 1<<12, /* Manual Master/Slave Enable */
 	PHY_M_1000C_MSC	= 1<<11, /* M/S Configuration (1=Master) */
 	PHY_M_1000C_MPD	= 1<<10, /* Multi-Port Device */
 	PHY_M_1000C_AFD	= 1<<9, /* Advertise Full Duplex */
 	PHY_M_1000C_AHD	= 1<<8, /* Advertise Half Duplex */
 };
 /*****  PHY_MARV_PHY_CTRL	16 bit r/w	PHY Specific Ctrl Reg *****/
 enum {
 	PHY_M_PC_TX_FFD_MSK	= 3<<14,/* Bit 15..14: Tx FIFO Depth Mask */
 	PHY_M_PC_RX_FFD_MSK	= 3<<12,/* Bit 13..12: Rx FIFO Depth Mask */
 	PHY_M_PC_ASS_CRS_TX	= 1<<11, /* Assert CRS on Transmit */
 	PHY_M_PC_FL_GOOD	= 1<<10, /* Force Link Good */
 	PHY_M_PC_EN_DET_MSK	= 3<<8,/* Bit  9.. 8: Energy Detect Mask */
 	PHY_M_PC_ENA_EXT_D	= 1<<7, /* Enable Ext. Distance (10BT) */
 	PHY_M_PC_MDIX_MSK	= 3<<5,/* Bit  6.. 5: MDI/MDIX Config. Mask */
 	PHY_M_PC_DIS_125CLK	= 1<<4, /* Disable 125 CLK */
 	PHY_M_PC_MAC_POW_UP	= 1<<3, /* MAC Power up */
 	PHY_M_PC_SQE_T_ENA	= 1<<2, /* SQE Test Enabled */
 	PHY_M_PC_POL_R_DIS	= 1<<1, /* Polarity Reversal Disabled */
 	PHY_M_PC_DIS_JABBER	= 1<<0, /* Disable Jabber */
 };
 enum {
 	PHY_M_PC_EN_DET		= 2<<8,	/* Energy Detect (Mode 1) */
 	PHY_M_PC_EN_DET_PLUS	= 3<<8, /* Energy Detect Plus (Mode 2) */
 };
 #define PHY_M_PC_MDI_XMODE(x)	(((x)<<5) & PHY_M_PC_MDIX_MSK)
 enum {
 	PHY_M_PC_MAN_MDI	= 0, /* 00 = Manual MDI configuration */
 	PHY_M_PC_MAN_MDIX	= 1, /* 01 = Manual MDIX configuration */
 	PHY_M_PC_ENA_AUTO	= 3, /* 11 = Enable Automatic Crossover */
 };
 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
 enum {
 	PHY_M_PC_ENA_DTE_DT	= 1<<15, /* Enable Data Terminal Equ. (DTE) Detect */
 	PHY_M_PC_ENA_ENE_DT	= 1<<14, /* Enable Energy Detect (sense & pulse) */
 	PHY_M_PC_DIS_NLP_CK	= 1<<13, /* Disable Normal Link Puls (NLP) Check */
 	PHY_M_PC_ENA_LIP_NP	= 1<<12, /* Enable Link Partner Next Page Reg. */
 	PHY_M_PC_DIS_NLP_GN	= 1<<11, /* Disable Normal Link Puls Generation */
 	PHY_M_PC_DIS_SCRAMB	= 1<<9, /* Disable Scrambler */
 	PHY_M_PC_DIS_FEFI	= 1<<8, /* Disable Far End Fault Indic. (FEFI) */
 	PHY_M_PC_SH_TP_SEL	= 1<<6, /* Shielded Twisted Pair Select */
 	PHY_M_PC_RX_FD_MSK	= 3<<2,/* Bit  3.. 2: Rx FIFO Depth Mask */
 };
 /*****  PHY_MARV_PHY_STAT	16 bit r/o	PHY Specific Status Reg *****/
 enum {
 	PHY_M_PS_SPEED_MSK	= 3<<14, /* Bit 15..14: Speed Mask */
 	PHY_M_PS_SPEED_1000	= 1<<15, /*		10 = 1000 Mbps */
 	PHY_M_PS_SPEED_100	= 1<<14, /*		01 =  100 Mbps */
 	PHY_M_PS_SPEED_10	= 0,	 /*		00 =   10 Mbps */
 	PHY_M_PS_FULL_DUP	= 1<<13, /* Full Duplex */
 	PHY_M_PS_PAGE_REC	= 1<<12, /* Page Received */
 	PHY_M_PS_SPDUP_RES	= 1<<11, /* Speed & Duplex Resolved */
 	PHY_M_PS_LINK_UP	= 1<<10, /* Link Up */
 	PHY_M_PS_CABLE_MSK	= 7<<7,  /* Bit  9.. 7: Cable Length Mask */
 	PHY_M_PS_MDI_X_STAT	= 1<<6,  /* MDI Crossover Stat (1=MDIX) */
 	PHY_M_PS_DOWNS_STAT	= 1<<5,  /* Downshift Status (1=downsh.) */
 	PHY_M_PS_ENDET_STAT	= 1<<4,  /* Energy Detect Status (1=act) */
 	PHY_M_PS_TX_P_EN	= 1<<3,  /* Tx Pause Enabled */
 	PHY_M_PS_RX_P_EN	= 1<<2,  /* Rx Pause Enabled */
 	PHY_M_PS_POL_REV	= 1<<1,  /* Polarity Reversed */
 	PHY_M_PS_JABBER		= 1<<0,  /* Jabber */
 };
 #define PHY_M_PS_PAUSE_MSK	(PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN)
 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
 enum {
 	PHY_M_PS_DTE_DETECT	= 1<<15, /* Data Terminal Equipment (DTE) Detected */
 	PHY_M_PS_RES_SPEED	= 1<<14, /* Resolved Speed (1=100 Mbps, 0=10 Mbps */
 };
 enum {
 	PHY_M_IS_AN_ERROR	= 1<<15, /* Auto-Negotiation Error */
 	PHY_M_IS_LSP_CHANGE	= 1<<14, /* Link Speed Changed */
 	PHY_M_IS_DUP_CHANGE	= 1<<13, /* Duplex Mode Changed */
 	PHY_M_IS_AN_PR		= 1<<12, /* Page Received */
 	PHY_M_IS_AN_COMPL	= 1<<11, /* Auto-Negotiation Completed */
 	PHY_M_IS_LST_CHANGE	= 1<<10, /* Link Status Changed */
 	PHY_M_IS_SYMB_ERROR	= 1<<9, /* Symbol Error */
 	PHY_M_IS_FALSE_CARR	= 1<<8, /* False Carrier */
 	PHY_M_IS_FIFO_ERROR	= 1<<7, /* FIFO Overflow/Underrun Error */
 	PHY_M_IS_MDI_CHANGE	= 1<<6, /* MDI Crossover Changed */
 	PHY_M_IS_DOWNSH_DET	= 1<<5, /* Downshift Detected */
 	PHY_M_IS_END_CHANGE	= 1<<4, /* Energy Detect Changed */
 	PHY_M_IS_DTE_CHANGE	= 1<<2, /* DTE Power Det. Status Changed */
 	PHY_M_IS_POL_CHANGE	= 1<<1, /* Polarity Changed */
 	PHY_M_IS_JABBER		= 1<<0, /* Jabber */
 	PHY_M_DEF_MSK		= PHY_M_IS_LSP_CHANGE | PHY_M_IS_LST_CHANGE
 				 | PHY_M_IS_FIFO_ERROR,
 	PHY_M_AN_MSK	       = PHY_M_IS_AN_ERROR | PHY_M_IS_AN_COMPL,
 };
 /*****  PHY_MARV_EXT_CTRL	16 bit r/w	Ext. PHY Specific Ctrl *****/
 enum {
 	PHY_M_EC_ENA_BC_EXT = 1<<15, /* Enable Block Carr. Ext. (88E1111 only) */
 	PHY_M_EC_ENA_LIN_LB = 1<<14, /* Enable Line Loopback (88E1111 only) */
 	PHY_M_EC_DIS_LINK_P = 1<<12, /* Disable Link Pulses (88E1111 only) */
 	PHY_M_EC_M_DSC_MSK  = 3<<10, /* Bit 11..10:	Master Downshift Counter */
 					/* (88E1011 only) */
 	PHY_M_EC_S_DSC_MSK  = 3<<8,/* Bit  9.. 8:	Slave  Downshift Counter */
 				       /* (88E1011 only) */
 	PHY_M_EC_M_DSC_MSK2 = 7<<9,/* Bit 11.. 9:	Master Downshift Counter */
 					/* (88E1111 only) */
 	PHY_M_EC_DOWN_S_ENA = 1<<8, /* Downshift Enable (88E1111 only) */
 					/* !!! Errata in spec. (1 = disable) */
 	PHY_M_EC_RX_TIM_CT  = 1<<7, /* RGMII Rx Timing Control*/
 	PHY_M_EC_MAC_S_MSK  = 7<<4,/* Bit  6.. 4:	Def. MAC interface speed */
 	PHY_M_EC_FIB_AN_ENA = 1<<3, /* Fiber Auto-Neg. Enable (88E1011S only) */
 	PHY_M_EC_DTE_D_ENA  = 1<<2, /* DTE Detect Enable (88E1111 only) */
 	PHY_M_EC_TX_TIM_CT  = 1<<1, /* RGMII Tx Timing Control */
 	PHY_M_EC_TRANS_DIS  = 1<<0, /* Transmitter Disable (88E1111 only) */};
 #define PHY_M_EC_M_DSC(x)	((x)<<10 & PHY_M_EC_M_DSC_MSK)
 					/* 00=1x; 01=2x; 10=3x; 11=4x */
 #define PHY_M_EC_S_DSC(x)	((x)<<8 & PHY_M_EC_S_DSC_MSK)
 					/* 00=dis; 01=1x; 10=2x; 11=3x */
 #define PHY_M_EC_DSC_2(x)	((x)<<9 & PHY_M_EC_M_DSC_MSK2)
 					/* 000=1x; 001=2x; 010=3x; 011=4x */
 #define PHY_M_EC_MAC_S(x)	((x)<<4 & PHY_M_EC_MAC_S_MSK)
 					/* 01X=0; 110=2.5; 111=25 (MHz) */
 /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
 enum {
 	PHY_M_PC_DIS_LINK_Pa	= 1<<15,/* Disable Link Pulses */
 	PHY_M_PC_DSC_MSK	= 7<<12,/* Bit 14..12:	Downshift Counter */
 	PHY_M_PC_DOWN_S_ENA	= 1<<11,/* Downshift Enable */
 };
 /* !!! Errata in spec. (1 = disable) */
 #define PHY_M_PC_DSC(x)			(((x)<<12) & PHY_M_PC_DSC_MSK)
 											/* 100=5x; 101=6x; 110=7x; 111=8x */
 enum {
 	MAC_TX_CLK_0_MHZ	= 2,
 	MAC_TX_CLK_2_5_MHZ	= 6,
 	MAC_TX_CLK_25_MHZ 	= 7,
 };
 /*****  PHY_MARV_LED_CTRL	16 bit r/w	LED Control Reg *****/
 enum {
 	PHY_M_LEDC_DIS_LED	= 1<<15, /* Disable LED */
 	PHY_M_LEDC_PULS_MSK	= 7<<12,/* Bit 14..12: Pulse Stretch Mask */
 	PHY_M_LEDC_F_INT	= 1<<11, /* Force Interrupt */
 	PHY_M_LEDC_BL_R_MSK	= 7<<8,/* Bit 10.. 8: Blink Rate Mask */
 	PHY_M_LEDC_DP_C_LSB	= 1<<7, /* Duplex Control (LSB, 88E1111 only) */
 	PHY_M_LEDC_TX_C_LSB	= 1<<6, /* Tx Control (LSB, 88E1111 only) */
 	PHY_M_LEDC_LK_C_MSK	= 7<<3,/* Bit  5.. 3: Link Control Mask */
 					/* (88E1111 only) */
 };
 enum {
 	PHY_M_LEDC_LINK_MSK	= 3<<3,/* Bit  4.. 3: Link Control Mask */
 									/* (88E1011 only) */
 	PHY_M_LEDC_DP_CTRL	= 1<<2, /* Duplex Control */
 	PHY_M_LEDC_DP_C_MSB	= 1<<2, /* Duplex Control (MSB, 88E1111 only) */
 	PHY_M_LEDC_RX_CTRL	= 1<<1, /* Rx Activity / Link */
 	PHY_M_LEDC_TX_CTRL	= 1<<0, /* Tx Activity / Link */
 	PHY_M_LEDC_TX_C_MSB	= 1<<0, /* Tx Control (MSB, 88E1111 only) */
 };
 #define PHY_M_LED_PULS_DUR(x)	(((x)<<12) & PHY_M_LEDC_PULS_MSK)
 /*****  PHY_MARV_PHY_STAT (page 3)16 bit r/w	Polarity Control Reg. *****/
 enum {
 	PHY_M_POLC_LS1M_MSK	= 0xf<<12, /* Bit 15..12: LOS,STAT1 Mix % Mask */
 	PHY_M_POLC_IS0M_MSK	= 0xf<<8,  /* Bit 11.. 8: INIT,STAT0 Mix % Mask */
 	PHY_M_POLC_LOS_MSK	= 0x3<<6,  /* Bit  7.. 6: LOS Pol. Ctrl. Mask */
 	PHY_M_POLC_INIT_MSK	= 0x3<<4,  /* Bit  5.. 4: INIT Pol. Ctrl. Mask */
 	PHY_M_POLC_STA1_MSK	= 0x3<<2,  /* Bit  3.. 2: STAT1 Pol. Ctrl. Mask */
 	PHY_M_POLC_STA0_MSK	= 0x3,     /* Bit  1.. 0: STAT0 Pol. Ctrl. Mask */
 };
 #define PHY_M_POLC_LS1_P_MIX(x)	(((x)<<12) & PHY_M_POLC_LS1M_MSK)
 #define PHY_M_POLC_IS0_P_MIX(x)	(((x)<<8) & PHY_M_POLC_IS0M_MSK)
 #define PHY_M_POLC_LOS_CTRL(x)	(((x)<<6) & PHY_M_POLC_LOS_MSK)
 #define PHY_M_POLC_INIT_CTRL(x)	(((x)<<4) & PHY_M_POLC_INIT_MSK)
 #define PHY_M_POLC_STA1_CTRL(x)	(((x)<<2) & PHY_M_POLC_STA1_MSK)
 #define PHY_M_POLC_STA0_CTRL(x)	(((x)<<0) & PHY_M_POLC_STA0_MSK)
 enum {
 	PULS_NO_STR	= 0,/* no pulse stretching */
 	PULS_21MS	= 1,/* 21 ms to 42 ms */
 	PULS_42MS	= 2,/* 42 ms to 84 ms */
 	PULS_84MS	= 3,/* 84 ms to 170 ms */
 	PULS_170MS	= 4,/* 170 ms to 340 ms */
 	PULS_340MS	= 5,/* 340 ms to 670 ms */
 	PULS_670MS	= 6,/* 670 ms to 1.3 s */
 	PULS_1300MS	= 7,/* 1.3 s to 2.7 s */
 };
 #define PHY_M_LED_BLINK_RT(x)	(((x)<<8) & PHY_M_LEDC_BL_R_MSK)
 enum {
 	BLINK_42MS	= 0,/* 42 ms */
 	BLINK_84MS	= 1,/* 84 ms */
 	BLINK_170MS	= 2,/* 170 ms */
 	BLINK_340MS	= 3,/* 340 ms */
 	BLINK_670MS	= 4,/* 670 ms */
 };
 /*****  PHY_MARV_LED_OVER	16 bit r/w	Manual LED Override Reg *****/
 #define PHY_M_LED_MO_SGMII(x)	((x)<<14) /* Bit 15..14:  SGMII AN Timer */
 										/* Bit 13..12:	reserved */
 #define PHY_M_LED_MO_DUP(x)	((x)<<10) /* Bit 11..10:  Duplex */
 #define PHY_M_LED_MO_10(x)	((x)<<8) /* Bit  9.. 8:  Link 10 */
 #define PHY_M_LED_MO_100(x)	((x)<<6) /* Bit  7.. 6:  Link 100 */
 #define PHY_M_LED_MO_1000(x)	((x)<<4) /* Bit  5.. 4:  Link 1000 */
 #define PHY_M_LED_MO_RX(x)	((x)<<2) /* Bit  3.. 2:  Rx */
 #define PHY_M_LED_MO_TX(x)	((x)<<0) /* Bit  1.. 0:  Tx */
 enum {
 	MO_LED_NORM	= 0,
 	MO_LED_BLINK	= 1,
 	MO_LED_OFF	= 2,
 	MO_LED_ON	= 3,
 };
 /*****  PHY_MARV_EXT_CTRL_2	16 bit r/w	Ext. PHY Specific Ctrl 2 *****/
 enum {
 	PHY_M_EC2_FI_IMPED	= 1<<6, /* Fiber Input  Impedance */
 	PHY_M_EC2_FO_IMPED	= 1<<5, /* Fiber Output Impedance */
 	PHY_M_EC2_FO_M_CLK	= 1<<4, /* Fiber Mode Clock Enable */
 	PHY_M_EC2_FO_BOOST	= 1<<3, /* Fiber Output Boost */
 	PHY_M_EC2_FO_AM_MSK	= 7,/* Bit  2.. 0:	Fiber Output Amplitude */
 };
 /*****  PHY_MARV_EXT_P_STAT 16 bit r/w	Ext. PHY Specific Status *****/
 enum {
 	PHY_M_FC_AUTO_SEL	= 1<<15, /* Fiber/Copper Auto Sel. Dis. */
 	PHY_M_FC_AN_REG_ACC	= 1<<14, /* Fiber/Copper AN Reg. Access */
 	PHY_M_FC_RESOLUTION	= 1<<13, /* Fiber/Copper Resolution */
 	PHY_M_SER_IF_AN_BP	= 1<<12, /* Ser. IF AN Bypass Enable */
 	PHY_M_SER_IF_BP_ST	= 1<<11, /* Ser. IF AN Bypass Status */
 	PHY_M_IRQ_POLARITY	= 1<<10, /* IRQ polarity */
 	PHY_M_DIS_AUT_MED	= 1<<9, /* Disable Aut. Medium Reg. Selection */
 	/* (88E1111 only) */
 	PHY_M_UNDOC1		= 1<<7, /* undocumented bit !! */
 	PHY_M_DTE_POW_STAT	= 1<<4, /* DTE Power Status (88E1111 only) */
 	PHY_M_MODE_MASK	= 0xf, /* Bit  3.. 0: copy of HWCFG MODE[3:0] */
 };
 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
 /*****  PHY_MARV_FE_LED_PAR		16 bit r/w	LED Parallel Select Reg. *****/
 									/* Bit 15..12: reserved (used internally) */
 enum {
 	PHY_M_FELP_LED2_MSK = 0xf<<8,	/* Bit 11.. 8: LED2 Mask (LINK) */
 	PHY_M_FELP_LED1_MSK = 0xf<<4,	/* Bit  7.. 4: LED1 Mask (ACT) */
 	PHY_M_FELP_LED0_MSK = 0xf, /* Bit  3.. 0: LED0 Mask (SPEED) */
 };
 #define PHY_M_FELP_LED2_CTRL(x)	(((x)<<8) & PHY_M_FELP_LED2_MSK)
 #define PHY_M_FELP_LED1_CTRL(x)	(((x)<<4) & PHY_M_FELP_LED1_MSK)
 #define PHY_M_FELP_LED0_CTRL(x)	(((x)<<0) & PHY_M_FELP_LED0_MSK)
 enum {
 	LED_PAR_CTRL_COLX	= 0x00,
 	LED_PAR_CTRL_ERROR	= 0x01,
 	LED_PAR_CTRL_DUPLEX	= 0x02,
 	LED_PAR_CTRL_DP_COL	= 0x03,
 	LED_PAR_CTRL_SPEED	= 0x04,
 	LED_PAR_CTRL_LINK	= 0x05,
 	LED_PAR_CTRL_TX		= 0x06,
 	LED_PAR_CTRL_RX		= 0x07,
 	LED_PAR_CTRL_ACT	= 0x08,
 	LED_PAR_CTRL_LNK_RX	= 0x09,
 	LED_PAR_CTRL_LNK_AC	= 0x0a,
 	LED_PAR_CTRL_ACT_BL	= 0x0b,
 	LED_PAR_CTRL_TX_BL	= 0x0c,
 	LED_PAR_CTRL_RX_BL	= 0x0d,
 	LED_PAR_CTRL_COL_BL	= 0x0e,
 	LED_PAR_CTRL_INACT	= 0x0f
 };
 /*****,PHY_MARV_FE_SPEC_2		16 bit r/w	Specific Control Reg. 2 *****/
 enum {
 	PHY_M_FESC_DIS_WAIT	= 1<<2, /* Disable TDR Waiting Period */
 	PHY_M_FESC_ENA_MCLK	= 1<<1, /* Enable MAC Rx Clock in sleep mode */
 	PHY_M_FESC_SEL_CL_A	= 1<<0, /* Select Class A driver (100B-TX) */
 };
 /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
 /*****  PHY_MARV_PHY_CTRL (page 2)		16 bit r/w	MAC Specific Ctrl *****/
 enum {
 	PHY_M_MAC_MD_MSK	= 7<<7, /* Bit  9.. 7: Mode Select Mask */
 	PHY_M_MAC_MD_AUTO	= 3,/* Auto Copper/1000Base-X */
 	PHY_M_MAC_MD_COPPER	= 5,/* Copper only */
 	PHY_M_MAC_MD_1000BX	= 7,/* 1000Base-X only */
 };
 #define PHY_M_MAC_MODE_SEL(x)	(((x)<<7) & PHY_M_MAC_MD_MSK)
 /*****  PHY_MARV_PHY_CTRL (page 3)		16 bit r/w	LED Control Reg. *****/
 enum {
 	PHY_M_LEDC_LOS_MSK	= 0xf<<12,/* Bit 15..12: LOS LED Ctrl. Mask */
 	PHY_M_LEDC_INIT_MSK	= 0xf<<8, /* Bit 11.. 8: INIT LED Ctrl. Mask */
 	PHY_M_LEDC_STA1_MSK	= 0xf<<4,/* Bit  7.. 4: STAT1 LED Ctrl. Mask */
 	PHY_M_LEDC_STA0_MSK	= 0xf, /* Bit  3.. 0: STAT0 LED Ctrl. Mask */
 };
 #define PHY_M_LEDC_LOS_CTRL(x)	(((x)<<12) & PHY_M_LEDC_LOS_MSK)
 #define PHY_M_LEDC_INIT_CTRL(x)	(((x)<<8) & PHY_M_LEDC_INIT_MSK)
 #define PHY_M_LEDC_STA1_CTRL(x)	(((x)<<4) & PHY_M_LEDC_STA1_MSK)
 #define PHY_M_LEDC_STA0_CTRL(x)	(((x)<<0) & PHY_M_LEDC_STA0_MSK)
 /* GMAC registers  */
 /* Port Registers */
 enum {
 	GM_GP_STAT	= 0x0000,	/* 16 bit r/o	General Purpose Status */
 	GM_GP_CTRL	= 0x0004,	/* 16 bit r/w	General Purpose Control */
 	GM_TX_CTRL	= 0x0008,	/* 16 bit r/w	Transmit Control Reg. */
 	GM_RX_CTRL	= 0x000c,	/* 16 bit r/w	Receive Control Reg. */
 	GM_TX_FLOW_CTRL	= 0x0010,	/* 16 bit r/w	Transmit Flow-Control */
 	GM_TX_PARAM	= 0x0014,	/* 16 bit r/w	Transmit Parameter Reg. */
 	GM_SERIAL_MODE	= 0x0018,	/* 16 bit r/w	Serial Mode Register */
 /* Source Address Registers */
 	GM_SRC_ADDR_1L	= 0x001c,	/* 16 bit r/w	Source Address 1 (low) */
 	GM_SRC_ADDR_1M	= 0x0020,	/* 16 bit r/w	Source Address 1 (middle) */
 	GM_SRC_ADDR_1H	= 0x0024,	/* 16 bit r/w	Source Address 1 (high) */
 	GM_SRC_ADDR_2L	= 0x0028,	/* 16 bit r/w	Source Address 2 (low) */
 	GM_SRC_ADDR_2M	= 0x002c,	/* 16 bit r/w	Source Address 2 (middle) */
 	GM_SRC_ADDR_2H	= 0x0030,	/* 16 bit r/w	Source Address 2 (high) */
 /* Multicast Address Hash Registers */
 	GM_MC_ADDR_H1	= 0x0034,	/* 16 bit r/w	Multicast Address Hash 1 */
 	GM_MC_ADDR_H2	= 0x0038,	/* 16 bit r/w	Multicast Address Hash 2 */
 	GM_MC_ADDR_H3	= 0x003c,	/* 16 bit r/w	Multicast Address Hash 3 */
 	GM_MC_ADDR_H4	= 0x0040,	/* 16 bit r/w	Multicast Address Hash 4 */
 /* Interrupt Source Registers */
 	GM_TX_IRQ_SRC	= 0x0044,	/* 16 bit r/o	Tx Overflow IRQ Source */
 	GM_RX_IRQ_SRC	= 0x0048,	/* 16 bit r/o	Rx Overflow IRQ Source */
 	GM_TR_IRQ_SRC	= 0x004c,	/* 16 bit r/o	Tx/Rx Over. IRQ Source */
 /* Interrupt Mask Registers */
 	GM_TX_IRQ_MSK	= 0x0050,	/* 16 bit r/w	Tx Overflow IRQ Mask */
 	GM_RX_IRQ_MSK	= 0x0054,	/* 16 bit r/w	Rx Overflow IRQ Mask */
 	GM_TR_IRQ_MSK	= 0x0058,	/* 16 bit r/w	Tx/Rx Over. IRQ Mask */
 /* Serial Management Interface (SMI) Registers */
 	GM_SMI_CTRL	= 0x0080,	/* 16 bit r/w	SMI Control Register */
 	GM_SMI_DATA	= 0x0084,	/* 16 bit r/w	SMI Data Register */
 	GM_PHY_ADDR	= 0x0088,	/* 16 bit r/w	GPHY Address Register */
 };
 /* MIB Counters */
 #define GM_MIB_CNT_BASE	0x0100		/* Base Address of MIB Counters */
 #define GM_MIB_CNT_SIZE	44		/* Number of MIB Counters */
 /*
  * MIB Counters base address definitions (low word) -
  * use offset 4 for access to high word	(32 bit r/o)
  */
 enum {
 	GM_RXF_UC_OK  = GM_MIB_CNT_BASE + 0,	/* Unicast Frames Received OK */
 	GM_RXF_BC_OK	= GM_MIB_CNT_BASE + 8,	/* Broadcast Frames Received OK */
 	GM_RXF_MPAUSE	= GM_MIB_CNT_BASE + 16,	/* Pause MAC Ctrl Frames Received */
 	GM_RXF_MC_OK	= GM_MIB_CNT_BASE + 24,	/* Multicast Frames Received OK */
 	GM_RXF_FCS_ERR	= GM_MIB_CNT_BASE + 32,	/* Rx Frame Check Seq. Error */
 	/* GM_MIB_CNT_BASE + 40:	reserved */
 	GM_RXO_OK_LO	= GM_MIB_CNT_BASE + 48,	/* Octets Received OK Low */
 	GM_RXO_OK_HI	= GM_MIB_CNT_BASE + 56,	/* Octets Received OK High */
 	GM_RXO_ERR_LO	= GM_MIB_CNT_BASE + 64,	/* Octets Received Invalid Low */
 	GM_RXO_ERR_HI	= GM_MIB_CNT_BASE + 72,	/* Octets Received Invalid High */
 	GM_RXF_SHT	= GM_MIB_CNT_BASE + 80,	/* Frames <64 Byte Received OK */
 	GM_RXE_FRAG	= GM_MIB_CNT_BASE + 88,	/* Frames <64 Byte Received with FCS Err */
 	GM_RXF_64B	= GM_MIB_CNT_BASE + 96,	/* 64 Byte Rx Frame */
 	GM_RXF_127B	= GM_MIB_CNT_BASE + 104,	/* 65-127 Byte Rx Frame */
 	GM_RXF_255B	= GM_MIB_CNT_BASE + 112,	/* 128-255 Byte Rx Frame */
 	GM_RXF_511B	= GM_MIB_CNT_BASE + 120,	/* 256-511 Byte Rx Frame */
 	GM_RXF_1023B	= GM_MIB_CNT_BASE + 128,	/* 512-1023 Byte Rx Frame */
 	GM_RXF_1518B	= GM_MIB_CNT_BASE + 136,	/* 1024-1518 Byte Rx Frame */
 	GM_RXF_MAX_SZ	= GM_MIB_CNT_BASE + 144,	/* 1519-MaxSize Byte Rx Frame */
 	GM_RXF_LNG_ERR	= GM_MIB_CNT_BASE + 152,	/* Rx Frame too Long Error */
 	GM_RXF_JAB_PKT	= GM_MIB_CNT_BASE + 160,	/* Rx Jabber Packet Frame */
 	/* GM_MIB_CNT_BASE + 168:	reserved */
 	GM_RXE_FIFO_OV	= GM_MIB_CNT_BASE + 176,	/* Rx FIFO overflow Event */
 	/* GM_MIB_CNT_BASE + 184:	reserved */
 	GM_TXF_UC_OK	= GM_MIB_CNT_BASE + 192,	/* Unicast Frames Xmitted OK */
 	GM_TXF_BC_OK	= GM_MIB_CNT_BASE + 200,	/* Broadcast Frames Xmitted OK */
 	GM_TXF_MPAUSE	= GM_MIB_CNT_BASE + 208,	/* Pause MAC Ctrl Frames Xmitted */
 	GM_TXF_MC_OK	= GM_MIB_CNT_BASE + 216,	/* Multicast Frames Xmitted OK */
 	GM_TXO_OK_LO	= GM_MIB_CNT_BASE + 224,	/* Octets Transmitted OK Low */
 	GM_TXO_OK_HI	= GM_MIB_CNT_BASE + 232,	/* Octets Transmitted OK High */
 	GM_TXF_64B	= GM_MIB_CNT_BASE + 240,	/* 64 Byte Tx Frame */
 	GM_TXF_127B	= GM_MIB_CNT_BASE + 248,	/* 65-127 Byte Tx Frame */
 	GM_TXF_255B	= GM_MIB_CNT_BASE + 256,	/* 128-255 Byte Tx Frame */
 	GM_TXF_511B	= GM_MIB_CNT_BASE + 264,	/* 256-511 Byte Tx Frame */
 	GM_TXF_1023B	= GM_MIB_CNT_BASE + 272,	/* 512-1023 Byte Tx Frame */
 	GM_TXF_1518B	= GM_MIB_CNT_BASE + 280,	/* 1024-1518 Byte Tx Frame */
 	GM_TXF_MAX_SZ	= GM_MIB_CNT_BASE + 288,	/* 1519-MaxSize Byte Tx Frame */
 	GM_TXF_COL	= GM_MIB_CNT_BASE + 304,	/* Tx Collision */
 	GM_TXF_LAT_COL	= GM_MIB_CNT_BASE + 312,	/* Tx Late Collision */
 	GM_TXF_ABO_COL	= GM_MIB_CNT_BASE + 320,	/* Tx aborted due to Exces. Col. */
 	GM_TXF_MUL_COL	= GM_MIB_CNT_BASE + 328,	/* Tx Multiple Collision */
 	GM_TXF_SNG_COL	= GM_MIB_CNT_BASE + 336,	/* Tx Single Collision */
 	GM_TXE_FIFO_UR	= GM_MIB_CNT_BASE + 344,	/* Tx FIFO Underrun Event */
 };
 /* GMAC Bit Definitions */
 /*	GM_GP_STAT	16 bit r/o	General Purpose Status Register */
 enum {
 	GM_GPSR_SPEED		= 1<<15, /* Bit 15:	Port Speed (1 = 100 Mbps) */
 	GM_GPSR_DUPLEX		= 1<<14, /* Bit 14:	Duplex Mode (1 = Full) */
 	GM_GPSR_FC_TX_DIS	= 1<<13, /* Bit 13:	Tx Flow-Control Mode Disabled */
 	GM_GPSR_LINK_UP		= 1<<12, /* Bit 12:	Link Up Status */
 	GM_GPSR_PAUSE		= 1<<11, /* Bit 11:	Pause State */
 	GM_GPSR_TX_ACTIVE	= 1<<10, /* Bit 10:	Tx in Progress */
 	GM_GPSR_EXC_COL		= 1<<9,	/* Bit  9:	Excessive Collisions Occured */
 	GM_GPSR_LAT_COL		= 1<<8,	/* Bit  8:	Late Collisions Occured */
 	GM_GPSR_PHY_ST_CH	= 1<<5,	/* Bit  5:	PHY Status Change */
 	GM_GPSR_GIG_SPEED	= 1<<4,	/* Bit  4:	Gigabit Speed (1 = 1000 Mbps) */
 	GM_GPSR_PART_MODE	= 1<<3,	/* Bit  3:	Partition mode */
 	GM_GPSR_FC_RX_DIS	= 1<<2,	/* Bit  2:	Rx Flow-Control Mode Disabled */
 	GM_GPSR_PROM_EN		= 1<<1,	/* Bit  1:	Promiscuous Mode Enabled */
 };
 /*	GM_GP_CTRL	16 bit r/w	General Purpose Control Register */
 enum {
 	GM_GPCR_PROM_ENA	= 1<<14,	/* Bit 14:	Enable Promiscuous Mode */
 	GM_GPCR_FC_TX_DIS	= 1<<13, /* Bit 13:	Disable Tx Flow-Control Mode */
 	GM_GPCR_TX_ENA		= 1<<12, /* Bit 12:	Enable Transmit */
 	GM_GPCR_RX_ENA		= 1<<11, /* Bit 11:	Enable Receive */
 	GM_GPCR_BURST_ENA	= 1<<10, /* Bit 10:	Enable Burst Mode */
 	GM_GPCR_LOOP_ENA	= 1<<9,	/* Bit  9:	Enable MAC Loopback Mode */
 	GM_GPCR_PART_ENA	= 1<<8,	/* Bit  8:	Enable Partition Mode */
 	GM_GPCR_GIGS_ENA	= 1<<7,	/* Bit  7:	Gigabit Speed (1000 Mbps) */
 	GM_GPCR_FL_PASS		= 1<<6,	/* Bit  6:	Force Link Pass */
 	GM_GPCR_DUP_FULL	= 1<<5,	/* Bit  5:	Full Duplex Mode */
 	GM_GPCR_FC_RX_DIS	= 1<<4,	/* Bit  4:	Disable Rx Flow-Control Mode */
 	GM_GPCR_SPEED_100	= 1<<3,   /* Bit  3:	Port Speed 100 Mbps */
 	GM_GPCR_AU_DUP_DIS	= 1<<2,	/* Bit  2:	Disable Auto-Update Duplex */
 	GM_GPCR_AU_FCT_DIS	= 1<<1,	/* Bit  1:	Disable Auto-Update Flow-C. */
 	GM_GPCR_AU_SPD_DIS	= 1<<0,	/* Bit  0:	Disable Auto-Update Speed */
 };
 #define GM_GPCR_SPEED_1000	(GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100)
 #define GM_GPCR_AU_ALL_DIS	(GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS|GM_GPCR_AU_SPD_DIS)
 /*	GM_TX_CTRL			16 bit r/w	Transmit Control Register */
 enum {
 	GM_TXCR_FORCE_JAM	= 1<<15, /* Bit 15:	Force Jam / Flow-Control */
 	GM_TXCR_CRC_DIS		= 1<<14, /* Bit 14:	Disable insertion of CRC */
 	GM_TXCR_PAD_DIS		= 1<<13, /* Bit 13:	Disable padding of packets */
 	GM_TXCR_COL_THR_MSK	= 1<<10, /* Bit 12..10:	Collision Threshold */
 };
 #define TX_COL_THR(x)		(((x)<<10) & GM_TXCR_COL_THR_MSK)
 #define TX_COL_DEF		0x04
 /*	GM_RX_CTRL			16 bit r/w	Receive Control Register */
 enum {
 	GM_RXCR_UCF_ENA	= 1<<15, /* Bit 15:	Enable Unicast filtering */
 	GM_RXCR_MCF_ENA	= 1<<14, /* Bit 14:	Enable Multicast filtering */
 	GM_RXCR_CRC_DIS	= 1<<13, /* Bit 13:	Remove 4-byte CRC */
 	GM_RXCR_PASS_FC	= 1<<12, /* Bit 12:	Pass FC packets to FIFO */
 };
 /*	GM_TX_PARAM		16 bit r/w	Transmit Parameter Register */
 enum {
 	GM_TXPA_JAMLEN_MSK	= 0x03<<14,	/* Bit 15..14:	Jam Length */
 	GM_TXPA_JAMIPG_MSK	= 0x1f<<9,	/* Bit 13..9:	Jam IPG */
 	GM_TXPA_JAMDAT_MSK	= 0x1f<<4,	/* Bit  8..4:	IPG Jam to Data */
 	GM_TXPA_BO_LIM_MSK	= 0x0f,		/* Bit  3.. 0: Backoff Limit Mask */
 	TX_JAM_LEN_DEF		= 0x03,
 	TX_JAM_IPG_DEF		= 0x0b,
 	TX_IPG_JAM_DEF		= 0x1c,
 	TX_BOF_LIM_DEF		= 0x04,
 };
 #define TX_JAM_LEN_VAL(x)	(((x)<<14) & GM_TXPA_JAMLEN_MSK)
 #define TX_JAM_IPG_VAL(x)	(((x)<<9)  & GM_TXPA_JAMIPG_MSK)
 #define TX_IPG_JAM_DATA(x)	(((x)<<4)  & GM_TXPA_JAMDAT_MSK)
 #define TX_BACK_OFF_LIM(x)	((x) & GM_TXPA_BO_LIM_MSK)
 /*	GM_SERIAL_MODE			16 bit r/w	Serial Mode Register */
 enum {
 	GM_SMOD_DATABL_MSK	= 0x1f<<11, /* Bit 15..11:	Data Blinder (r/o) */
 	GM_SMOD_LIMIT_4		= 1<<10, /* Bit 10:	4 consecutive Tx trials */
 	GM_SMOD_VLAN_ENA	= 1<<9,	/* Bit  9:	Enable VLAN  (Max. Frame Len) */
 	GM_SMOD_JUMBO_ENA	= 1<<8,	/* Bit  8:	Enable Jumbo (Max. Frame Len) */
 	 GM_SMOD_IPG_MSK	= 0x1f	/* Bit 4..0:	Inter-Packet Gap (IPG) */
 };
 #define DATA_BLIND_VAL(x)	(((x)<<11) & GM_SMOD_DATABL_MSK)
 #define DATA_BLIND_DEF		0x04
 #define IPG_DATA_VAL(x)		(x & GM_SMOD_IPG_MSK)
 #define IPG_DATA_DEF		0x1e
 /*	GM_SMI_CTRL			16 bit r/w	SMI Control Register */
 enum {
 	GM_SMI_CT_PHY_A_MSK	= 0x1f<<11,/* Bit 15..11:	PHY Device Address */
 	GM_SMI_CT_REG_A_MSK	= 0x1f<<6,/* Bit 10.. 6:	PHY Register Address */
 	GM_SMI_CT_OP_RD		= 1<<5,	/* Bit  5:	OpCode Read (0=Write)*/
 	GM_SMI_CT_RD_VAL	= 1<<4,	/* Bit  4:	Read Valid (Read completed) */
 	GM_SMI_CT_BUSY		= 1<<3,	/* Bit  3:	Busy (Operation in progress) */
 };
 #define GM_SMI_CT_PHY_AD(x)	(((x)<<11) & GM_SMI_CT_PHY_A_MSK)
 #define GM_SMI_CT_REG_AD(x)	(((x)<<6) & GM_SMI_CT_REG_A_MSK)
 /*	GM_PHY_ADDR				16 bit r/w	GPHY Address Register */
 enum {
 	GM_PAR_MIB_CLR	= 1<<5,	/* Bit  5:	Set MIB Clear Counter Mode */
 	GM_PAR_MIB_TST	= 1<<4,	/* Bit  4:	MIB Load Counter (Test Mode) */
 };
 /* Receive Frame Status Encoding */
 enum {
 	GMR_FS_LEN	= 0xffff<<16, /* Bit 31..16:	Rx Frame Length */
 	GMR_FS_VLAN	= 1<<13, /* VLAN Packet */
 	GMR_FS_JABBER	= 1<<12, /* Jabber Packet */
 	GMR_FS_UN_SIZE	= 1<<11, /* Undersize Packet */
 	GMR_FS_MC	= 1<<10, /* Multicast Packet */
 	GMR_FS_BC	= 1<<9,  /* Broadcast Packet */
 	GMR_FS_RX_OK	= 1<<8,  /* Receive OK (Good Packet) */
 	GMR_FS_GOOD_FC	= 1<<7,  /* Good Flow-Control Packet */
 	GMR_FS_BAD_FC	= 1<<6,  /* Bad  Flow-Control Packet */
 	GMR_FS_MII_ERR	= 1<<5,  /* MII Error */
 	GMR_FS_LONG_ERR	= 1<<4,  /* Too Long Packet */
 	GMR_FS_FRAGMENT	= 1<<3,  /* Fragment */
 	GMR_FS_CRC_ERR	= 1<<1,  /* CRC Error */
 	GMR_FS_RX_FF_OV	= 1<<0,  /* Rx FIFO Overflow */
 	GMR_FS_ANY_ERR	= GMR_FS_RX_FF_OV | GMR_FS_CRC_ERR |
 			  GMR_FS_FRAGMENT | GMR_FS_LONG_ERR |
 		  	  GMR_FS_MII_ERR | GMR_FS_BAD_FC | GMR_FS_GOOD_FC |
 			  GMR_FS_UN_SIZE | GMR_FS_JABBER,
 };
 /*	RX_GMF_CTRL_T	32 bit	Rx GMAC FIFO Control/Test */
 enum {
 	RX_TRUNC_ON	= 1<<27,  	/* enable  packet truncation */
 	RX_TRUNC_OFF	= 1<<26, 	/* disable packet truncation */
 	RX_VLAN_STRIP_ON = 1<<25,	/* enable  VLAN stripping */
 	RX_VLAN_STRIP_OFF = 1<<24,	/* disable VLAN stripping */
 	GMF_WP_TST_ON	= 1<<14,	/* Write Pointer Test On */
 	GMF_WP_TST_OFF	= 1<<13,	/* Write Pointer Test Off */
 	GMF_WP_STEP	= 1<<12,	/* Write Pointer Step/Increment */
 	GMF_RP_TST_ON	= 1<<10,	/* Read Pointer Test On */
 	GMF_RP_TST_OFF	= 1<<9,		/* Read Pointer Test Off */
 	GMF_RP_STEP	= 1<<8,		/* Read Pointer Step/Increment */
 	GMF_RX_F_FL_ON	= 1<<7,		/* Rx FIFO Flush Mode On */
 	GMF_RX_F_FL_OFF	= 1<<6,		/* Rx FIFO Flush Mode Off */
 	GMF_CLI_RX_FO	= 1<<5,		/* Clear IRQ Rx FIFO Overrun */
 	GMF_CLI_RX_C	= 1<<4,		/* Clear IRQ Rx Frame Complete */
 	GMF_OPER_ON	= 1<<3,		/* Operational Mode On */
 	GMF_OPER_OFF	= 1<<2,		/* Operational Mode Off */
 	GMF_RST_CLR	= 1<<1,		/* Clear GMAC FIFO Reset */
 	GMF_RST_SET	= 1<<0,		/* Set   GMAC FIFO Reset */
 	RX_GMF_FL_THR_DEF = 0xa,	/* flush threshold (default) */
 	GMF_RX_CTRL_DEF	= GMF_OPER_ON | GMF_RX_F_FL_ON,
 };
 /*	TX_GMF_CTRL_T	32 bit	Tx GMAC FIFO Control/Test */
 enum {
 	TX_STFW_DIS	= 1<<31,/* Disable Store & Forward (Yukon-EC Ultra) */
 	TX_STFW_ENA	= 1<<30,/* Enable  Store & Forward (Yukon-EC Ultra) */
 	TX_VLAN_TAG_ON	= 1<<25,/* enable  VLAN tagging */
 	TX_VLAN_TAG_OFF	= 1<<24,/* disable VLAN tagging */
 	GMF_WSP_TST_ON	= 1<<18,/* Write Shadow Pointer Test On */
 	GMF_WSP_TST_OFF	= 1<<17,/* Write Shadow Pointer Test Off */
 	GMF_WSP_STEP	= 1<<16,/* Write Shadow Pointer Step/Increment */
 	GMF_CLI_TX_FU	= 1<<6,	/* Clear IRQ Tx FIFO Underrun */
 	GMF_CLI_TX_FC	= 1<<5,	/* Clear IRQ Tx Frame Complete */
 	GMF_CLI_TX_PE	= 1<<4,	/* Clear IRQ Tx Parity Error */
 };
 /*	GMAC_TI_ST_CTRL	 8 bit	Time Stamp Timer Ctrl Reg (YUKON only) */
 enum {
 	GMT_ST_START	= 1<<2,	/* Start Time Stamp Timer */
 	GMT_ST_STOP	= 1<<1,	/* Stop  Time Stamp Timer */
 	GMT_ST_CLR_IRQ	= 1<<0,	/* Clear Time Stamp Timer IRQ */
 };
 /* B28_Y2_ASF_STAT_CMD		32 bit	ASF Status and Command Reg */
 enum {
 	Y2_ASF_OS_PRES	= 1<<4,	/* ASF operation system present */
 	Y2_ASF_RESET	= 1<<3,	/* ASF system in reset state */
 	Y2_ASF_RUNNING	= 1<<2,	/* ASF system operational */
 	Y2_ASF_CLR_HSTI = 1<<1,	/* Clear ASF IRQ */
 	Y2_ASF_IRQ	= 1<<0,	/* Issue an IRQ to ASF system */
 	Y2_ASF_UC_STATE = 3<<2,	/* ASF uC State */
 	Y2_ASF_CLK_HALT	= 0,	/* ASF system clock stopped */
 };
 /* B28_Y2_ASF_HOST_COM	32 bit	ASF Host Communication Reg */
 enum {
 	Y2_ASF_CLR_ASFI = 1<<1,	/* Clear host IRQ */
 	Y2_ASF_HOST_IRQ = 1<<0,	/* Issue an IRQ to HOST system */
 };
 /*	STAT_CTRL		32 bit	Status BMU control register (Yukon-2 only) */
 enum {
 	SC_STAT_CLR_IRQ	= 1<<4,	/* Status Burst IRQ clear */
 	SC_STAT_OP_ON	= 1<<3,	/* Operational Mode On */
 	SC_STAT_OP_OFF	= 1<<2,	/* Operational Mode Off */
 	SC_STAT_RST_CLR	= 1<<1,	/* Clear Status Unit Reset (Enable) */
 	SC_STAT_RST_SET	= 1<<0,	/* Set   Status Unit Reset */
 };
 /*	GMAC_CTRL		32 bit	GMAC Control Reg (YUKON only) */
 enum {
 	GMC_H_BURST_ON	= 1<<7,	/* Half Duplex Burst Mode On */
 	GMC_H_BURST_OFF	= 1<<6,	/* Half Duplex Burst Mode Off */
 	GMC_F_LOOPB_ON	= 1<<5,	/* FIFO Loopback On */
 	GMC_F_LOOPB_OFF	= 1<<4,	/* FIFO Loopback Off */
 	GMC_PAUSE_ON	= 1<<3,	/* Pause On */
 	GMC_PAUSE_OFF	= 1<<2,	/* Pause Off */
 	GMC_RST_CLR	= 1<<1,	/* Clear GMAC Reset */
 	GMC_RST_SET	= 1<<0,	/* Set   GMAC Reset */
 };
 /*	GPHY_CTRL		32 bit	GPHY Control Reg (YUKON only) */
 enum {
 	GPC_SEL_BDT	= 1<<28, /* Select Bi-Dir. Transfer for MDC/MDIO */
 	GPC_INT_POL_HI	= 1<<27, /* IRQ Polarity is Active HIGH */
 	GPC_75_OHM	= 1<<26, /* Use 75 Ohm Termination instead of 50 */
 	GPC_DIS_FC	= 1<<25, /* Disable Automatic Fiber/Copper Detection */
 	GPC_DIS_SLEEP	= 1<<24, /* Disable Energy Detect */
 	GPC_HWCFG_M_3	= 1<<23, /* HWCFG_MODE[3] */
 	GPC_HWCFG_M_2	= 1<<22, /* HWCFG_MODE[2] */
 	GPC_HWCFG_M_1	= 1<<21, /* HWCFG_MODE[1] */
 	GPC_HWCFG_M_0	= 1<<20, /* HWCFG_MODE[0] */
 	GPC_ANEG_0	= 1<<19, /* ANEG[0] */
 	GPC_ENA_XC	= 1<<18, /* Enable MDI crossover */
 	GPC_DIS_125	= 1<<17, /* Disable 125 MHz clock */
 	GPC_ANEG_3	= 1<<16, /* ANEG[3] */
 	GPC_ANEG_2	= 1<<15, /* ANEG[2] */
 	GPC_ANEG_1	= 1<<14, /* ANEG[1] */
 	GPC_ENA_PAUSE	= 1<<13, /* Enable Pause (SYM_OR_REM) */
 	GPC_PHYADDR_4	= 1<<12, /* Bit 4 of Phy Addr */
 	GPC_PHYADDR_3	= 1<<11, /* Bit 3 of Phy Addr */
 	GPC_PHYADDR_2	= 1<<10, /* Bit 2 of Phy Addr */
 	GPC_PHYADDR_1	= 1<<9,	 /* Bit 1 of Phy Addr */
 	GPC_PHYADDR_0	= 1<<8,	 /* Bit 0 of Phy Addr */
 						/* Bits  7..2:	reserved */
 	GPC_RST_CLR	= 1<<1,	/* Clear GPHY Reset */
 	GPC_RST_SET	= 1<<0,	/* Set   GPHY Reset */
 };
 /*	GMAC_IRQ_SRC	 8 bit	GMAC Interrupt Source Reg (YUKON only) */
 /*	GMAC_IRQ_MSK	 8 bit	GMAC Interrupt Mask   Reg (YUKON only) */
 enum {
 	GM_IS_TX_CO_OV	= 1<<5,	/* Transmit Counter Overflow IRQ */
 	GM_IS_RX_CO_OV	= 1<<4,	/* Receive Counter Overflow IRQ */
 	GM_IS_TX_FF_UR	= 1<<3,	/* Transmit FIFO Underrun */
 	GM_IS_TX_COMPL	= 1<<2,	/* Frame Transmission Complete */
 	GM_IS_RX_FF_OR	= 1<<1,	/* Receive FIFO Overrun */
 	GM_IS_RX_COMPL	= 1<<0,	/* Frame Reception Complete */
 #define GMAC_DEF_MSK     GM_IS_TX_FF_UR
 /*	GMAC_LINK_CTRL	16 bit	GMAC Link Control Reg (YUKON only) */
 						/* Bits 15.. 2:	reserved */
 	GMLC_RST_CLR	= 1<<1,	/* Clear GMAC Link Reset */
 	GMLC_RST_SET	= 1<<0,	/* Set   GMAC Link Reset */
 /*	WOL_CTRL_STAT	16 bit	WOL Control/Status Reg */
 	WOL_CTL_LINK_CHG_OCC		= 1<<15,
 	WOL_CTL_MAGIC_PKT_OCC		= 1<<14,
 	WOL_CTL_PATTERN_OCC		= 1<<13,
 	WOL_CTL_CLEAR_RESULT		= 1<<12,
 	WOL_CTL_ENA_PME_ON_LINK_CHG	= 1<<11,
 	WOL_CTL_DIS_PME_ON_LINK_CHG	= 1<<10,
 	WOL_CTL_ENA_PME_ON_MAGIC_PKT	= 1<<9,
 	WOL_CTL_DIS_PME_ON_MAGIC_PKT	= 1<<8,
 	WOL_CTL_ENA_PME_ON_PATTERN	= 1<<7,
 	WOL_CTL_DIS_PME_ON_PATTERN	= 1<<6,
 	WOL_CTL_ENA_LINK_CHG_UNIT	= 1<<5,
 	WOL_CTL_DIS_LINK_CHG_UNIT	= 1<<4,
 	WOL_CTL_ENA_MAGIC_PKT_UNIT	= 1<<3,
 	WOL_CTL_DIS_MAGIC_PKT_UNIT	= 1<<2,
 	WOL_CTL_ENA_PATTERN_UNIT	= 1<<1,
 	WOL_CTL_DIS_PATTERN_UNIT	= 1<<0,
 };
 #define WOL_CTL_DEFAULT				\
 	(WOL_CTL_DIS_PME_ON_LINK_CHG |	\
 	WOL_CTL_DIS_PME_ON_PATTERN |	\
 	WOL_CTL_DIS_PME_ON_MAGIC_PKT |	\
 	WOL_CTL_DIS_LINK_CHG_UNIT |		\
 	WOL_CTL_DIS_PATTERN_UNIT |		\
 	WOL_CTL_DIS_MAGIC_PKT_UNIT)
 /*	WOL_MATCH_CTL	 8 bit	WOL Match Control Reg */
 #define WOL_CTL_PATT_ENA(x)	(1 << (x))
 /* Control flags */
 enum {
 	UDPTCP	= 1<<0,
 	CALSUM	= 1<<1,
 	WR_SUM	= 1<<2,
 	INIT_SUM= 1<<3,
 	LOCK_SUM= 1<<4,
 	INS_VLAN= 1<<5,
 	FRC_STAT= 1<<6,
 	EOP	= 1<<7,
 };
 enum {
 	HW_OWNER 	= 1<<7,
 	OP_TCPWRITE	= 0x11,
 	OP_TCPSTART	= 0x12,
 	OP_TCPINIT	= 0x14,
 	OP_TCPLCK	= 0x18,
 	OP_TCPCHKSUM	= OP_TCPSTART,
 	OP_TCPIS	= OP_TCPINIT | OP_TCPSTART,
 	OP_TCPLW	= OP_TCPLCK | OP_TCPWRITE,
 	OP_TCPLSW	= OP_TCPLCK | OP_TCPSTART | OP_TCPWRITE,
 	OP_TCPLISW	= OP_TCPLCK | OP_TCPINIT | OP_TCPSTART | OP_TCPWRITE,
 	OP_ADDR64	= 0x21,
 	OP_VLAN		= 0x22,
 	OP_ADDR64VLAN	= OP_ADDR64 | OP_VLAN,
 	OP_LRGLEN	= 0x24,
 	OP_LRGLENVLAN	= OP_LRGLEN | OP_VLAN,
 	OP_BUFFER	= 0x40,
 	OP_PACKET	= 0x41,
 	OP_LARGESEND	= 0x43,
 /* YUKON-2 STATUS opcodes defines */
 	OP_RXSTAT	= 0x60,
 	OP_RXTIMESTAMP	= 0x61,
 	OP_RXVLAN	= 0x62,
 	OP_RXCHKS	= 0x64,
 	OP_RXCHKSVLAN	= OP_RXCHKS | OP_RXVLAN,
 	OP_RXTIMEVLAN	= OP_RXTIMESTAMP | OP_RXVLAN,
 	OP_RSS_HASH	= 0x65,
 	OP_TXINDEXLE	= 0x68,
 };
 /* Yukon 2 hardware interface
  * Not tested on big endian
  */
 struct sky2_tx_le {
 	union {
 		__le32	addr;
 		struct {
 			__le16	offset;
 			__le16	start;
 		} csum  __attribute((packed));
 		struct {
 			__le16	size;
 			__le16	rsvd;
 		} tso  __attribute((packed));
 	} tx;
 	__le16	length;	/* also vlan tag or checksum start */
 	u8	ctrl;
 	u8	opcode;
 } __attribute((packed));
 struct sky2_rx_le {
 	__le32	addr;
 	__le16	length;
 	u8	ctrl;
 	u8	opcode;
 } __attribute((packed));;
 struct sky2_status_le {
 	__le32	status;	/* also checksum */
 	__le16	length;	/* also vlan tag */
 	u8	link;
 	u8	opcode;
 } __attribute((packed));
 struct tx_ring_info {
 	struct sk_buff	*skb;
 	DECLARE_PCI_UNMAP_ADDR(mapaddr);
 	u16		idx;
 };
 struct ring_info {
 	struct sk_buff	*skb;
 	dma_addr_t	mapaddr;
 };
 struct sky2_port {
 	struct sky2_hw	     *hw;
 	struct net_device    *netdev;
 	unsigned	     port;
 	u32		     msg_enable;
 	spinlock_t	     tx_lock  ____cacheline_aligned_in_smp;
 	struct tx_ring_info  *tx_ring;
 	struct sky2_tx_le    *tx_le;
 	u16		     tx_cons;		/* next le to check */
 	u16		     tx_prod;		/* next le to use */
 	u32		     tx_addr64;
 	u16		     tx_pending;
-	u16		     tx_last_put;
 	u16		     tx_last_mss;
 	struct ring_info     *rx_ring ____cacheline_aligned_in_smp;
 	struct sky2_rx_le    *rx_le;
 	u32		     rx_addr64;
 	u16		     rx_next;		/* next re to check */
 	u16		     rx_put;		/* next le index to use */
 	u16		     rx_pending;
-	u16		     rx_last_put;
 	u16		     rx_bufsize;
 #ifdef SKY2_VLAN_TAG_USED
 	u16		     rx_tag;
 	struct vlan_group    *vlgrp;
 #endif
 	dma_addr_t	     rx_le_map;
 	dma_addr_t	     tx_le_map;
 	u32		     advertising;	/* ADVERTISED_ bits */
 	u16		     speed;	/* SPEED_1000, SPEED_100, ... */
 	u8		     autoneg;	/* AUTONEG_ENABLE, AUTONEG_DISABLE */
 	u8		     duplex;	/* DUPLEX_HALF, DUPLEX_FULL */
 	u8		     rx_pause;
 	u8		     tx_pause;
 	u8		     rx_csum;
 	u8		     wol;
 	struct net_device_stats net_stats;
 	struct work_struct   phy_task;
 	struct semaphore     phy_sema;
 };
 struct sky2_hw {
 	void __iomem  	     *regs;
 	struct pci_dev	     *pdev;
 	struct net_device    *dev[2];
 	spinlock_t	     hw_lock;
 	u32		     intr_mask;
 	int		     pm_cap;
 	u8	     	     chip_id;
 	u8		     chip_rev;
 	u8		     copper;
 	u8		     ports;
 	struct sky2_status_le *st_le;
 	u32		     st_idx;
 	dma_addr_t   	     st_dma;
 };
 /* Register accessor for memory mapped device */
 static inline u32 sky2_read32(const struct sky2_hw *hw, unsigned reg)
 {
 	return readl(hw->regs + reg);
 }
 static inline u16 sky2_read16(const struct sky2_hw *hw, unsigned reg)
 {
 	return readw(hw->regs + reg);
 }
 static inline u8 sky2_read8(const struct sky2_hw *hw, unsigned reg)
 {
 	return readb(hw->regs + reg);
 }
 static inline void sky2_write32(const struct sky2_hw *hw, unsigned reg, u32 val)
 {
 	writel(val, hw->regs + reg);
 }
 static inline void sky2_write16(const struct sky2_hw *hw, unsigned reg, u16 val)
 {
 	writew(val, hw->regs + reg);
 }
 static inline void sky2_write8(const struct sky2_hw *hw, unsigned reg, u8 val)
 {
 	writeb(val, hw->regs + reg);
 }
 /* Yukon PHY related registers */
 #define SK_GMAC_REG(port,reg) \
 	(BASE_GMAC_1 + (port) * (BASE_GMAC_2-BASE_GMAC_1) + (reg))
 #define GM_PHY_RETRIES	100
 static inline u16 gma_read16(const struct sky2_hw *hw, unsigned port, unsigned reg)
 {
 	return sky2_read16(hw, SK_GMAC_REG(port,reg));
 }
 static inline u32 gma_read32(struct sky2_hw *hw, unsigned port, unsigned reg)
 {
 	unsigned base = SK_GMAC_REG(port, reg);
 	return (u32) sky2_read16(hw, base)
 		| (u32) sky2_read16(hw, base+4) << 16;
 }
 static inline void gma_write16(const struct sky2_hw *hw, unsigned port, int r, u16 v)
 {
 	sky2_write16(hw, SK_GMAC_REG(port,r), v);
 }
 static inline void gma_set_addr(struct sky2_hw *hw, unsigned port, unsigned reg,
 				    const u8 *addr)
 {
 	gma_write16(hw, port, reg,  (u16) addr[0] | ((u16) addr[1] << 8));
 	gma_write16(hw, port, reg+4,(u16) addr[2] | ((u16) addr[3] << 8));
 	gma_write16(hw, port, reg+8,(u16) addr[4] | ((u16) addr[5] << 8));
 }
 /* PCI config space access */
 static inline u32 sky2_pci_read32(const struct sky2_hw *hw, unsigned reg)
 {
 	return sky2_read32(hw, Y2_CFG_SPC + reg);
 }
 static inline u16 sky2_pci_read16(const struct sky2_hw *hw, unsigned reg)
 {
 	return sky2_read16(hw, Y2_CFG_SPC + reg);
 }
 static inline void sky2_pci_write32(struct sky2_hw *hw, unsigned reg, u32 val)
 {
 	sky2_write32(hw, Y2_CFG_SPC + reg, val);
 }
 static inline void sky2_pci_write16(struct sky2_hw *hw, unsigned reg, u16 val)
 {
 	sky2_write16(hw, Y2_CFG_SPC + reg, val);
 }
 #endif