Eric Lee / linux-smarc-t335x-v3.2

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Commit 2e8c07c35b3ffee7689406be61fd1448ee45d3cd

Authored by Divy Le Ray
Committed by David S. Miller
1 parent 5e65951556
Exists in master and in 4 other branches v3.2_AM335xPSP_04.06.00.11, v3.2_NEWT335xPSP_04.06.00.11, v3.2_SBC_SMARTMEN, v3.2_SMARCT335xPSP_04.06.00.11

cxgb3: use request_firmware() for the EDC registers setup 

use request_firmware() to load the phy's EDC programmation

Signed-off-by: Divy Le Ray <divy@chelsio.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

Showing 9 changed files with 395 additions and 1051 deletions Inline Diff

drivers/net/cxgb3/adapter.h
Diff comments   View file @ 2e8c07c
1 /* 1 /*
2 * Copyright (c) 2003-2008 Chelsio, Inc. All rights reserved. 2 * Copyright (c) 2003-2008 Chelsio, Inc. All rights reserved.
3 * 3 *
4 * This software is available to you under a choice of one of two 4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU 5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file 6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the 7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below: 8 * OpenIB.org BSD license below:
9 * 9 *
10 * Redistribution and use in source and binary forms, with or 10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following 11 * without modification, are permitted provided that the following
12 * conditions are met: 12 * conditions are met:
13 * 13 *
14 * - Redistributions of source code must retain the above 14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following 15 * copyright notice, this list of conditions and the following
16 * disclaimer. 16 * disclaimer.
17 * 17 *
18 * - Redistributions in binary form must reproduce the above 18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following 19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials 20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution. 21 * provided with the distribution.
22 * 22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE. 30 * SOFTWARE.
31 */ 31 */
32 32
33 /* This file should not be included directly. Include common.h instead. */ 33 /* This file should not be included directly. Include common.h instead. */
34 34
35 #ifndef __T3_ADAPTER_H__ 35 #ifndef __T3_ADAPTER_H__
36 #define __T3_ADAPTER_H__ 36 #define __T3_ADAPTER_H__
37 37
38 #include <linux/pci.h> 38 #include <linux/pci.h>
39 #include <linux/spinlock.h> 39 #include <linux/spinlock.h>
40 #include <linux/interrupt.h> 40 #include <linux/interrupt.h>
41 #include <linux/timer.h> 41 #include <linux/timer.h>
42 #include <linux/cache.h> 42 #include <linux/cache.h>
43 #include <linux/mutex.h> 43 #include <linux/mutex.h>
44 #include <linux/bitops.h> 44 #include <linux/bitops.h>
45 #include "t3cdev.h" 45 #include "t3cdev.h"
46 #include <asm/io.h> 46 #include <asm/io.h>
47 47
48 struct vlan_group; 48 struct vlan_group;
49 struct adapter; 49 struct adapter;
50 struct sge_qset; 50 struct sge_qset;
51 51
52 enum { /* rx_offload flags */ 52 enum { /* rx_offload flags */
53 T3_RX_CSUM = 1 << 0, 53 T3_RX_CSUM = 1 << 0,
54 T3_LRO = 1 << 1, 54 T3_LRO = 1 << 1,
55 }; 55 };
56 56
57 struct port_info { 57 struct port_info {
58 struct adapter *adapter; 58 struct adapter *adapter;
59 struct vlan_group *vlan_grp; 59 struct vlan_group *vlan_grp;
60 struct sge_qset *qs; 60 struct sge_qset *qs;
61 u8 port_id; 61 u8 port_id;
62 u8 rx_offload; 62 u8 rx_offload;
63 u8 nqsets; 63 u8 nqsets;
64 u8 first_qset; 64 u8 first_qset;
65 struct cphy phy; 65 struct cphy phy;
66 struct cmac mac; 66 struct cmac mac;
67 struct link_config link_config; 67 struct link_config link_config;
68 struct net_device_stats netstats; 68 struct net_device_stats netstats;
69 int activity; 69 int activity;
70 __be32 iscsi_ipv4addr; 70 __be32 iscsi_ipv4addr;
71 71
72 int link_fault; /* link fault was detected */ 72 int link_fault; /* link fault was detected */
73 }; 73 };
74 74
75 enum { /* adapter flags */ 75 enum { /* adapter flags */
76 FULL_INIT_DONE = (1 << 0), 76 FULL_INIT_DONE = (1 << 0),
77 USING_MSI = (1 << 1), 77 USING_MSI = (1 << 1),
78 USING_MSIX = (1 << 2), 78 USING_MSIX = (1 << 2),
79 QUEUES_BOUND = (1 << 3), 79 QUEUES_BOUND = (1 << 3),
80 TP_PARITY_INIT = (1 << 4), 80 TP_PARITY_INIT = (1 << 4),
81 NAPI_INIT = (1 << 5), 81 NAPI_INIT = (1 << 5),
82 }; 82 };
83 83
84 struct fl_pg_chunk { 84 struct fl_pg_chunk {
85 struct page *page; 85 struct page *page;
86 void *va; 86 void *va;
87 unsigned int offset; 87 unsigned int offset;
88 unsigned long *p_cnt; 88 unsigned long *p_cnt;
89 dma_addr_t mapping; 89 dma_addr_t mapping;
90 }; 90 };
91 91
92 struct rx_desc; 92 struct rx_desc;
93 struct rx_sw_desc; 93 struct rx_sw_desc;
94 94
95 struct sge_fl { /* SGE per free-buffer list state */ 95 struct sge_fl { /* SGE per free-buffer list state */
96 unsigned int buf_size; /* size of each Rx buffer */ 96 unsigned int buf_size; /* size of each Rx buffer */
97 unsigned int credits; /* # of available Rx buffers */ 97 unsigned int credits; /* # of available Rx buffers */
98 unsigned int pend_cred; /* new buffers since last FL DB ring */ 98 unsigned int pend_cred; /* new buffers since last FL DB ring */
99 unsigned int size; /* capacity of free list */ 99 unsigned int size; /* capacity of free list */
100 unsigned int cidx; /* consumer index */ 100 unsigned int cidx; /* consumer index */
101 unsigned int pidx; /* producer index */ 101 unsigned int pidx; /* producer index */
102 unsigned int gen; /* free list generation */ 102 unsigned int gen; /* free list generation */
103 struct fl_pg_chunk pg_chunk;/* page chunk cache */ 103 struct fl_pg_chunk pg_chunk;/* page chunk cache */
104 unsigned int use_pages; /* whether FL uses pages or sk_buffs */ 104 unsigned int use_pages; /* whether FL uses pages or sk_buffs */
105 unsigned int order; /* order of page allocations */ 105 unsigned int order; /* order of page allocations */
106 unsigned int alloc_size; /* size of allocated buffer */ 106 unsigned int alloc_size; /* size of allocated buffer */
107 struct rx_desc *desc; /* address of HW Rx descriptor ring */ 107 struct rx_desc *desc; /* address of HW Rx descriptor ring */
108 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */ 108 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */
109 dma_addr_t phys_addr; /* physical address of HW ring start */ 109 dma_addr_t phys_addr; /* physical address of HW ring start */
110 unsigned int cntxt_id; /* SGE context id for the free list */ 110 unsigned int cntxt_id; /* SGE context id for the free list */
111 unsigned long empty; /* # of times queue ran out of buffers */ 111 unsigned long empty; /* # of times queue ran out of buffers */
112 unsigned long alloc_failed; /* # of times buffer allocation failed */ 112 unsigned long alloc_failed; /* # of times buffer allocation failed */
113 }; 113 };
114 114
115 /* 115 /*
116 * Bundle size for grouping offload RX packets for delivery to the stack. 116 * Bundle size for grouping offload RX packets for delivery to the stack.
117 * Don't make this too big as we do prefetch on each packet in a bundle. 117 * Don't make this too big as we do prefetch on each packet in a bundle.
118 */ 118 */
119 # define RX_BUNDLE_SIZE 8 119 # define RX_BUNDLE_SIZE 8
120 120
121 struct rsp_desc; 121 struct rsp_desc;
122 122
123 struct sge_rspq { /* state for an SGE response queue */ 123 struct sge_rspq { /* state for an SGE response queue */
124 unsigned int credits; /* # of pending response credits */ 124 unsigned int credits; /* # of pending response credits */
125 unsigned int size; /* capacity of response queue */ 125 unsigned int size; /* capacity of response queue */
126 unsigned int cidx; /* consumer index */ 126 unsigned int cidx; /* consumer index */
127 unsigned int gen; /* current generation bit */ 127 unsigned int gen; /* current generation bit */
128 unsigned int polling; /* is the queue serviced through NAPI? */ 128 unsigned int polling; /* is the queue serviced through NAPI? */
129 unsigned int holdoff_tmr; /* interrupt holdoff timer in 100ns */ 129 unsigned int holdoff_tmr; /* interrupt holdoff timer in 100ns */
130 unsigned int next_holdoff; /* holdoff time for next interrupt */ 130 unsigned int next_holdoff; /* holdoff time for next interrupt */
131 unsigned int rx_recycle_buf; /* whether recycling occurred 131 unsigned int rx_recycle_buf; /* whether recycling occurred
132 within current sop-eop */ 132 within current sop-eop */
133 struct rsp_desc *desc; /* address of HW response ring */ 133 struct rsp_desc *desc; /* address of HW response ring */
134 dma_addr_t phys_addr; /* physical address of the ring */ 134 dma_addr_t phys_addr; /* physical address of the ring */
135 unsigned int cntxt_id; /* SGE context id for the response q */ 135 unsigned int cntxt_id; /* SGE context id for the response q */
136 spinlock_t lock; /* guards response processing */ 136 spinlock_t lock; /* guards response processing */
137 struct sk_buff_head rx_queue; /* offload packet receive queue */ 137 struct sk_buff_head rx_queue; /* offload packet receive queue */
138 struct sk_buff *pg_skb; /* used to build frag list in napi handler */ 138 struct sk_buff *pg_skb; /* used to build frag list in napi handler */
139 139
140 unsigned long offload_pkts; 140 unsigned long offload_pkts;
141 unsigned long offload_bundles; 141 unsigned long offload_bundles;
142 unsigned long eth_pkts; /* # of ethernet packets */ 142 unsigned long eth_pkts; /* # of ethernet packets */
143 unsigned long pure_rsps; /* # of pure (non-data) responses */ 143 unsigned long pure_rsps; /* # of pure (non-data) responses */
144 unsigned long imm_data; /* responses with immediate data */ 144 unsigned long imm_data; /* responses with immediate data */
145 unsigned long rx_drops; /* # of packets dropped due to no mem */ 145 unsigned long rx_drops; /* # of packets dropped due to no mem */
146 unsigned long async_notif; /* # of asynchronous notification events */ 146 unsigned long async_notif; /* # of asynchronous notification events */
147 unsigned long empty; /* # of times queue ran out of credits */ 147 unsigned long empty; /* # of times queue ran out of credits */
148 unsigned long nomem; /* # of responses deferred due to no mem */ 148 unsigned long nomem; /* # of responses deferred due to no mem */
149 unsigned long unhandled_irqs; /* # of spurious intrs */ 149 unsigned long unhandled_irqs; /* # of spurious intrs */
150 unsigned long starved; 150 unsigned long starved;
151 unsigned long restarted; 151 unsigned long restarted;
152 }; 152 };
153 153
154 struct tx_desc; 154 struct tx_desc;
155 struct tx_sw_desc; 155 struct tx_sw_desc;
156 156
157 struct sge_txq { /* state for an SGE Tx queue */ 157 struct sge_txq { /* state for an SGE Tx queue */
158 unsigned long flags; /* HW DMA fetch status */ 158 unsigned long flags; /* HW DMA fetch status */
159 unsigned int in_use; /* # of in-use Tx descriptors */ 159 unsigned int in_use; /* # of in-use Tx descriptors */
160 unsigned int size; /* # of descriptors */ 160 unsigned int size; /* # of descriptors */
161 unsigned int processed; /* total # of descs HW has processed */ 161 unsigned int processed; /* total # of descs HW has processed */
162 unsigned int cleaned; /* total # of descs SW has reclaimed */ 162 unsigned int cleaned; /* total # of descs SW has reclaimed */
163 unsigned int stop_thres; /* SW TX queue suspend threshold */ 163 unsigned int stop_thres; /* SW TX queue suspend threshold */
164 unsigned int cidx; /* consumer index */ 164 unsigned int cidx; /* consumer index */
165 unsigned int pidx; /* producer index */ 165 unsigned int pidx; /* producer index */
166 unsigned int gen; /* current value of generation bit */ 166 unsigned int gen; /* current value of generation bit */
167 unsigned int unacked; /* Tx descriptors used since last COMPL */ 167 unsigned int unacked; /* Tx descriptors used since last COMPL */
168 struct tx_desc *desc; /* address of HW Tx descriptor ring */ 168 struct tx_desc *desc; /* address of HW Tx descriptor ring */
169 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */ 169 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */
170 spinlock_t lock; /* guards enqueueing of new packets */ 170 spinlock_t lock; /* guards enqueueing of new packets */
171 unsigned int token; /* WR token */ 171 unsigned int token; /* WR token */
172 dma_addr_t phys_addr; /* physical address of the ring */ 172 dma_addr_t phys_addr; /* physical address of the ring */
173 struct sk_buff_head sendq; /* List of backpressured offload packets */ 173 struct sk_buff_head sendq; /* List of backpressured offload packets */
174 struct tasklet_struct qresume_tsk; /* restarts the queue */ 174 struct tasklet_struct qresume_tsk; /* restarts the queue */
175 unsigned int cntxt_id; /* SGE context id for the Tx q */ 175 unsigned int cntxt_id; /* SGE context id for the Tx q */
176 unsigned long stops; /* # of times q has been stopped */ 176 unsigned long stops; /* # of times q has been stopped */
177 unsigned long restarts; /* # of queue restarts */ 177 unsigned long restarts; /* # of queue restarts */
178 }; 178 };
179 179
180 enum { /* per port SGE statistics */ 180 enum { /* per port SGE statistics */
181 SGE_PSTAT_TSO, /* # of TSO requests */ 181 SGE_PSTAT_TSO, /* # of TSO requests */
182 SGE_PSTAT_RX_CSUM_GOOD, /* # of successful RX csum offloads */ 182 SGE_PSTAT_RX_CSUM_GOOD, /* # of successful RX csum offloads */
183 SGE_PSTAT_TX_CSUM, /* # of TX checksum offloads */ 183 SGE_PSTAT_TX_CSUM, /* # of TX checksum offloads */
184 SGE_PSTAT_VLANEX, /* # of VLAN tag extractions */ 184 SGE_PSTAT_VLANEX, /* # of VLAN tag extractions */
185 SGE_PSTAT_VLANINS, /* # of VLAN tag insertions */ 185 SGE_PSTAT_VLANINS, /* # of VLAN tag insertions */
186 186
187 SGE_PSTAT_MAX /* must be last */ 187 SGE_PSTAT_MAX /* must be last */
188 }; 188 };
189 189
190 struct napi_gro_fraginfo; 190 struct napi_gro_fraginfo;
191 191
192 struct sge_qset { /* an SGE queue set */ 192 struct sge_qset { /* an SGE queue set */
193 struct adapter *adap; 193 struct adapter *adap;
194 struct napi_struct napi; 194 struct napi_struct napi;
195 struct sge_rspq rspq; 195 struct sge_rspq rspq;
196 struct sge_fl fl[SGE_RXQ_PER_SET]; 196 struct sge_fl fl[SGE_RXQ_PER_SET];
197 struct sge_txq txq[SGE_TXQ_PER_SET]; 197 struct sge_txq txq[SGE_TXQ_PER_SET];
198 int nomem; 198 int nomem;
199 int lro_enabled; 199 int lro_enabled;
200 void *lro_va; 200 void *lro_va;
201 struct net_device *netdev; 201 struct net_device *netdev;
202 struct netdev_queue *tx_q; /* associated netdev TX queue */ 202 struct netdev_queue *tx_q; /* associated netdev TX queue */
203 unsigned long txq_stopped; /* which Tx queues are stopped */ 203 unsigned long txq_stopped; /* which Tx queues are stopped */
204 struct timer_list tx_reclaim_timer; /* reclaims TX buffers */ 204 struct timer_list tx_reclaim_timer; /* reclaims TX buffers */
205 struct timer_list rx_reclaim_timer; /* reclaims RX buffers */ 205 struct timer_list rx_reclaim_timer; /* reclaims RX buffers */
206 unsigned long port_stats[SGE_PSTAT_MAX]; 206 unsigned long port_stats[SGE_PSTAT_MAX];
207 } ____cacheline_aligned; 207 } ____cacheline_aligned;
208 208
209 struct sge { 209 struct sge {
210 struct sge_qset qs[SGE_QSETS]; 210 struct sge_qset qs[SGE_QSETS];
211 spinlock_t reg_lock; /* guards non-atomic SGE registers (eg context) */ 211 spinlock_t reg_lock; /* guards non-atomic SGE registers (eg context) */
212 }; 212 };
213 213
214 struct adapter { 214 struct adapter {
215 struct t3cdev tdev; 215 struct t3cdev tdev;
216 struct list_head adapter_list; 216 struct list_head adapter_list;
217 void __iomem *regs; 217 void __iomem *regs;
218 struct pci_dev *pdev; 218 struct pci_dev *pdev;
219 unsigned long registered_device_map; 219 unsigned long registered_device_map;
220 unsigned long open_device_map; 220 unsigned long open_device_map;
221 unsigned long flags; 221 unsigned long flags;
222 222
223 const char *name; 223 const char *name;
224 int msg_enable; 224 int msg_enable;
225 unsigned int mmio_len; 225 unsigned int mmio_len;
226 226
227 struct adapter_params params; 227 struct adapter_params params;
228 unsigned int slow_intr_mask; 228 unsigned int slow_intr_mask;
229 unsigned long irq_stats[IRQ_NUM_STATS]; 229 unsigned long irq_stats[IRQ_NUM_STATS];
230 230
231 int msix_nvectors; 231 int msix_nvectors;
232 struct { 232 struct {
233 unsigned short vec; 233 unsigned short vec;
234 char desc[22]; 234 char desc[22];
235 } msix_info[SGE_QSETS + 1]; 235 } msix_info[SGE_QSETS + 1];
236 236
237 /* T3 modules */ 237 /* T3 modules */
238 struct sge sge; 238 struct sge sge;
239 struct mc7 pmrx; 239 struct mc7 pmrx;
240 struct mc7 pmtx; 240 struct mc7 pmtx;
241 struct mc7 cm; 241 struct mc7 cm;
242 struct mc5 mc5; 242 struct mc5 mc5;
243 243
244 struct net_device *port[MAX_NPORTS]; 244 struct net_device *port[MAX_NPORTS];
245 unsigned int check_task_cnt; 245 unsigned int check_task_cnt;
246 struct delayed_work adap_check_task; 246 struct delayed_work adap_check_task;
247 struct work_struct ext_intr_handler_task; 247 struct work_struct ext_intr_handler_task;
248 struct work_struct fatal_error_handler_task; 248 struct work_struct fatal_error_handler_task;
249 struct work_struct link_fault_handler_task; 249 struct work_struct link_fault_handler_task;
250 250
251 struct dentry *debugfs_root; 251 struct dentry *debugfs_root;
252 252
253 struct mutex mdio_lock; 253 struct mutex mdio_lock;
254 spinlock_t stats_lock; 254 spinlock_t stats_lock;
255 spinlock_t work_lock; 255 spinlock_t work_lock;
256 256
257 struct sk_buff *nofail_skb; 257 struct sk_buff *nofail_skb;
258 }; 258 };
259 259
260 static inline u32 t3_read_reg(struct adapter *adapter, u32 reg_addr) 260 static inline u32 t3_read_reg(struct adapter *adapter, u32 reg_addr)
261 { 261 {
262 u32 val = readl(adapter->regs + reg_addr); 262 u32 val = readl(adapter->regs + reg_addr);
263 263
264 CH_DBG(adapter, MMIO, "read register 0x%x value 0x%x\n", reg_addr, val); 264 CH_DBG(adapter, MMIO, "read register 0x%x value 0x%x\n", reg_addr, val);
265 return val; 265 return val;
266 } 266 }
267 267
268 static inline void t3_write_reg(struct adapter *adapter, u32 reg_addr, u32 val) 268 static inline void t3_write_reg(struct adapter *adapter, u32 reg_addr, u32 val)
269 { 269 {
270 CH_DBG(adapter, MMIO, "setting register 0x%x to 0x%x\n", reg_addr, val); 270 CH_DBG(adapter, MMIO, "setting register 0x%x to 0x%x\n", reg_addr, val);
271 writel(val, adapter->regs + reg_addr); 271 writel(val, adapter->regs + reg_addr);
272 } 272 }
273 273
274 static inline struct port_info *adap2pinfo(struct adapter *adap, int idx) 274 static inline struct port_info *adap2pinfo(struct adapter *adap, int idx)
275 { 275 {
276 return netdev_priv(adap->port[idx]); 276 return netdev_priv(adap->port[idx]);
277 } 277 }
278 278
279 static inline int phy2portid(struct cphy *phy) 279 static inline int phy2portid(struct cphy *phy)
280 { 280 {
281 struct adapter *adap = phy->adapter; 281 struct adapter *adap = phy->adapter;
282 struct port_info *port0 = adap2pinfo(adap, 0); 282 struct port_info *port0 = adap2pinfo(adap, 0);
283 283
284 return &port0->phy == phy ? 0 : 1; 284 return &port0->phy == phy ? 0 : 1;
285 } 285 }
286 286
287 #define OFFLOAD_DEVMAP_BIT 15 287 #define OFFLOAD_DEVMAP_BIT 15
288 288
289 #define tdev2adap(d) container_of(d, struct adapter, tdev) 289 #define tdev2adap(d) container_of(d, struct adapter, tdev)
290 290
291 static inline int offload_running(struct adapter *adapter) 291 static inline int offload_running(struct adapter *adapter)
292 { 292 {
293 return test_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map); 293 return test_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map);
294 } 294 }
295 295
296 int t3_offload_tx(struct t3cdev *tdev, struct sk_buff *skb); 296 int t3_offload_tx(struct t3cdev *tdev, struct sk_buff *skb);
297 297
298 void t3_os_ext_intr_handler(struct adapter *adapter); 298 void t3_os_ext_intr_handler(struct adapter *adapter);
299 void t3_os_link_changed(struct adapter *adapter, int port_id, int link_status, 299 void t3_os_link_changed(struct adapter *adapter, int port_id, int link_status,
300 int speed, int duplex, int fc); 300 int speed, int duplex, int fc);
301 void t3_os_phymod_changed(struct adapter *adap, int port_id); 301 void t3_os_phymod_changed(struct adapter *adap, int port_id);
302 void t3_os_link_fault(struct adapter *adapter, int port_id, int state); 302 void t3_os_link_fault(struct adapter *adapter, int port_id, int state);
303 void t3_os_link_fault_handler(struct adapter *adapter, int port_id); 303 void t3_os_link_fault_handler(struct adapter *adapter, int port_id);
304 304
305 void t3_sge_start(struct adapter *adap); 305 void t3_sge_start(struct adapter *adap);
306 void t3_sge_stop(struct adapter *adap); 306 void t3_sge_stop(struct adapter *adap);
307 void t3_start_sge_timers(struct adapter *adap); 307 void t3_start_sge_timers(struct adapter *adap);
308 void t3_stop_sge_timers(struct adapter *adap); 308 void t3_stop_sge_timers(struct adapter *adap);
309 void t3_free_sge_resources(struct adapter *adap); 309 void t3_free_sge_resources(struct adapter *adap);
310 void t3_sge_err_intr_handler(struct adapter *adapter); 310 void t3_sge_err_intr_handler(struct adapter *adapter);
311 irq_handler_t t3_intr_handler(struct adapter *adap, int polling); 311 irq_handler_t t3_intr_handler(struct adapter *adap, int polling);
312 int t3_eth_xmit(struct sk_buff *skb, struct net_device *dev); 312 int t3_eth_xmit(struct sk_buff *skb, struct net_device *dev);
313 int t3_mgmt_tx(struct adapter *adap, struct sk_buff *skb); 313 int t3_mgmt_tx(struct adapter *adap, struct sk_buff *skb);
314 void t3_update_qset_coalesce(struct sge_qset *qs, const struct qset_params *p); 314 void t3_update_qset_coalesce(struct sge_qset *qs, const struct qset_params *p);
315 int t3_sge_alloc_qset(struct adapter *adapter, unsigned int id, int nports, 315 int t3_sge_alloc_qset(struct adapter *adapter, unsigned int id, int nports,
316 int irq_vec_idx, const struct qset_params *p, 316 int irq_vec_idx, const struct qset_params *p,
317 int ntxq, struct net_device *dev, 317 int ntxq, struct net_device *dev,
318 struct netdev_queue *netdevq); 318 struct netdev_queue *netdevq);
319 int t3_get_desc(const struct sge_qset *qs, unsigned int qnum, unsigned int idx, 319 int t3_get_desc(const struct sge_qset *qs, unsigned int qnum, unsigned int idx,
320 unsigned char *data); 320 unsigned char *data);
321 irqreturn_t t3_sge_intr_msix(int irq, void *cookie); 321 irqreturn_t t3_sge_intr_msix(int irq, void *cookie);
322 322
323 int t3_get_edc_fw(struct cphy *phy, int edc_idx, int size);
324
323 #endif /* __T3_ADAPTER_H__ */ 325 #endif /* __T3_ADAPTER_H__ */
324 326
drivers/net/cxgb3/ael1002.c
Diff comments   View file @ 2e8c07c
1 /* 1 /*
2 * Copyright (c) 2005-2008 Chelsio, Inc. All rights reserved. 2 * Copyright (c) 2005-2008 Chelsio, Inc. All rights reserved.
3 * 3 *
4 * This software is available to you under a choice of one of two 4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU 5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file 6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the 7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below: 8 * OpenIB.org BSD license below:
9 * 9 *
10 * Redistribution and use in source and binary forms, with or 10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following 11 * without modification, are permitted provided that the following
12 * conditions are met: 12 * conditions are met:
13 * 13 *
14 * - Redistributions of source code must retain the above 14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following 15 * copyright notice, this list of conditions and the following
16 * disclaimer. 16 * disclaimer.
17 * 17 *
18 * - Redistributions in binary form must reproduce the above 18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following 19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials 20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution. 21 * provided with the distribution.
22 * 22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE. 30 * SOFTWARE.
31 */ 31 */
32 #include "common.h" 32 #include "common.h"
33 #include "regs.h" 33 #include "regs.h"
34 34
35 enum { 35 enum {
36 AEL100X_TX_CONFIG1 = 0xc002, 36 AEL100X_TX_CONFIG1 = 0xc002,
37 AEL1002_PWR_DOWN_HI = 0xc011, 37 AEL1002_PWR_DOWN_HI = 0xc011,
38 AEL1002_PWR_DOWN_LO = 0xc012, 38 AEL1002_PWR_DOWN_LO = 0xc012,
39 AEL1002_XFI_EQL = 0xc015, 39 AEL1002_XFI_EQL = 0xc015,
40 AEL1002_LB_EN = 0xc017, 40 AEL1002_LB_EN = 0xc017,
41 AEL_OPT_SETTINGS = 0xc017, 41 AEL_OPT_SETTINGS = 0xc017,
42 AEL_I2C_CTRL = 0xc30a, 42 AEL_I2C_CTRL = 0xc30a,
43 AEL_I2C_DATA = 0xc30b, 43 AEL_I2C_DATA = 0xc30b,
44 AEL_I2C_STAT = 0xc30c, 44 AEL_I2C_STAT = 0xc30c,
45 AEL2005_GPIO_CTRL = 0xc214, 45 AEL2005_GPIO_CTRL = 0xc214,
46 AEL2005_GPIO_STAT = 0xc215, 46 AEL2005_GPIO_STAT = 0xc215,
47 47
48 AEL2020_GPIO_INTR = 0xc103, /* Latch High (LH) */ 48 AEL2020_GPIO_INTR = 0xc103, /* Latch High (LH) */
49 AEL2020_GPIO_CTRL = 0xc108, /* Store Clear (SC) */ 49 AEL2020_GPIO_CTRL = 0xc108, /* Store Clear (SC) */
50 AEL2020_GPIO_STAT = 0xc10c, /* Read Only (RO) */ 50 AEL2020_GPIO_STAT = 0xc10c, /* Read Only (RO) */
51 AEL2020_GPIO_CFG = 0xc110, /* Read Write (RW) */ 51 AEL2020_GPIO_CFG = 0xc110, /* Read Write (RW) */
52 52
53 AEL2020_GPIO_SDA = 0, /* IN: i2c serial data */ 53 AEL2020_GPIO_SDA = 0, /* IN: i2c serial data */
54 AEL2020_GPIO_MODDET = 1, /* IN: Module Detect */ 54 AEL2020_GPIO_MODDET = 1, /* IN: Module Detect */
55 AEL2020_GPIO_0 = 3, /* IN: unassigned */ 55 AEL2020_GPIO_0 = 3, /* IN: unassigned */
56 AEL2020_GPIO_1 = 2, /* OUT: unassigned */ 56 AEL2020_GPIO_1 = 2, /* OUT: unassigned */
57 AEL2020_GPIO_LSTAT = AEL2020_GPIO_1, /* wired to link status LED */ 57 AEL2020_GPIO_LSTAT = AEL2020_GPIO_1, /* wired to link status LED */
58 }; 58 };
59 59
60 enum { edc_none, edc_sr, edc_twinax }; 60 enum { edc_none, edc_sr, edc_twinax };
61 61
62 /* PHY module I2C device address */ 62 /* PHY module I2C device address */
63 enum { 63 enum {
64 MODULE_DEV_ADDR = 0xa0, 64 MODULE_DEV_ADDR = 0xa0,
65 SFF_DEV_ADDR = 0xa2, 65 SFF_DEV_ADDR = 0xa2,
66 }; 66 };
67 67
68 /* PHY transceiver type */ 68 /* PHY transceiver type */
69 enum { 69 enum {
70 phy_transtype_unknown = 0, 70 phy_transtype_unknown = 0,
71 phy_transtype_sfp = 3, 71 phy_transtype_sfp = 3,
72 phy_transtype_xfp = 6, 72 phy_transtype_xfp = 6,
73 }; 73 };
74 74
75 #define AEL2005_MODDET_IRQ 4 75 #define AEL2005_MODDET_IRQ 4
76 76
77 struct reg_val { 77 struct reg_val {
78 unsigned short mmd_addr; 78 unsigned short mmd_addr;
79 unsigned short reg_addr; 79 unsigned short reg_addr;
80 unsigned short clear_bits; 80 unsigned short clear_bits;
81 unsigned short set_bits; 81 unsigned short set_bits;
82 }; 82 };
83 83
84 static int set_phy_regs(struct cphy *phy, const struct reg_val *rv) 84 static int set_phy_regs(struct cphy *phy, const struct reg_val *rv)
85 { 85 {
86 int err; 86 int err;
87 87
88 for (err = 0; rv->mmd_addr && !err; rv++) { 88 for (err = 0; rv->mmd_addr && !err; rv++) {
89 if (rv->clear_bits == 0xffff) 89 if (rv->clear_bits == 0xffff)
90 err = t3_mdio_write(phy, rv->mmd_addr, rv->reg_addr, 90 err = t3_mdio_write(phy, rv->mmd_addr, rv->reg_addr,
91 rv->set_bits); 91 rv->set_bits);
92 else 92 else
93 err = t3_mdio_change_bits(phy, rv->mmd_addr, 93 err = t3_mdio_change_bits(phy, rv->mmd_addr,
94 rv->reg_addr, rv->clear_bits, 94 rv->reg_addr, rv->clear_bits,
95 rv->set_bits); 95 rv->set_bits);
96 } 96 }
97 return err; 97 return err;
98 } 98 }
99 99
100 static void ael100x_txon(struct cphy *phy) 100 static void ael100x_txon(struct cphy *phy)
101 { 101 {
102 int tx_on_gpio = 102 int tx_on_gpio =
103 phy->mdio.prtad == 0 ? F_GPIO7_OUT_VAL : F_GPIO2_OUT_VAL; 103 phy->mdio.prtad == 0 ? F_GPIO7_OUT_VAL : F_GPIO2_OUT_VAL;
104 104
105 msleep(100); 105 msleep(100);
106 t3_set_reg_field(phy->adapter, A_T3DBG_GPIO_EN, 0, tx_on_gpio); 106 t3_set_reg_field(phy->adapter, A_T3DBG_GPIO_EN, 0, tx_on_gpio);
107 msleep(30); 107 msleep(30);
108 } 108 }
109 109
110 /* 110 /*
111 * Read an 8-bit word from a device attached to the PHY's i2c bus. 111 * Read an 8-bit word from a device attached to the PHY's i2c bus.
112 */ 112 */
113 static int ael_i2c_rd(struct cphy *phy, int dev_addr, int word_addr) 113 static int ael_i2c_rd(struct cphy *phy, int dev_addr, int word_addr)
114 { 114 {
115 int i, err; 115 int i, err;
116 unsigned int stat, data; 116 unsigned int stat, data;
117 117
118 err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL_I2C_CTRL, 118 err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL_I2C_CTRL,
119 (dev_addr << 8) | (1 << 8) | word_addr); 119 (dev_addr << 8) | (1 << 8) | word_addr);
120 if (err) 120 if (err)
121 return err; 121 return err;
122 122
123 for (i = 0; i < 200; i++) { 123 for (i = 0; i < 200; i++) {
124 msleep(1); 124 msleep(1);
125 err = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AEL_I2C_STAT, &stat); 125 err = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AEL_I2C_STAT, &stat);
126 if (err) 126 if (err)
127 return err; 127 return err;
128 if ((stat & 3) == 1) { 128 if ((stat & 3) == 1) {
129 err = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AEL_I2C_DATA, 129 err = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AEL_I2C_DATA,
130 &data); 130 &data);
131 if (err) 131 if (err)
132 return err; 132 return err;
133 return data >> 8; 133 return data >> 8;
134 } 134 }
135 } 135 }
136 CH_WARN(phy->adapter, "PHY %u i2c read of dev.addr %#x.%#x timed out\n", 136 CH_WARN(phy->adapter, "PHY %u i2c read of dev.addr %#x.%#x timed out\n",
137 phy->mdio.prtad, dev_addr, word_addr); 137 phy->mdio.prtad, dev_addr, word_addr);
138 return -ETIMEDOUT; 138 return -ETIMEDOUT;
139 } 139 }
140 140
141 static int ael1002_power_down(struct cphy *phy, int enable) 141 static int ael1002_power_down(struct cphy *phy, int enable)
142 { 142 {
143 int err; 143 int err;
144 144
145 err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, MDIO_PMA_TXDIS, !!enable); 145 err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, MDIO_PMA_TXDIS, !!enable);
146 if (!err) 146 if (!err)
147 err = mdio_set_flag(&phy->mdio, phy->mdio.prtad, 147 err = mdio_set_flag(&phy->mdio, phy->mdio.prtad,
148 MDIO_MMD_PMAPMD, MDIO_CTRL1, 148 MDIO_MMD_PMAPMD, MDIO_CTRL1,
149 MDIO_CTRL1_LPOWER, enable); 149 MDIO_CTRL1_LPOWER, enable);
150 return err; 150 return err;
151 } 151 }
152 152
153 static int ael1002_reset(struct cphy *phy, int wait) 153 static int ael1002_reset(struct cphy *phy, int wait)
154 { 154 {
155 int err; 155 int err;
156 156
157 if ((err = ael1002_power_down(phy, 0)) || 157 if ((err = ael1002_power_down(phy, 0)) ||
158 (err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL100X_TX_CONFIG1, 1)) || 158 (err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL100X_TX_CONFIG1, 1)) ||
159 (err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL1002_PWR_DOWN_HI, 0)) || 159 (err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL1002_PWR_DOWN_HI, 0)) ||
160 (err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL1002_PWR_DOWN_LO, 0)) || 160 (err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL1002_PWR_DOWN_LO, 0)) ||
161 (err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL1002_XFI_EQL, 0x18)) || 161 (err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL1002_XFI_EQL, 0x18)) ||
162 (err = t3_mdio_change_bits(phy, MDIO_MMD_PMAPMD, AEL1002_LB_EN, 162 (err = t3_mdio_change_bits(phy, MDIO_MMD_PMAPMD, AEL1002_LB_EN,
163 0, 1 << 5))) 163 0, 1 << 5)))
164 return err; 164 return err;
165 return 0; 165 return 0;
166 } 166 }
167 167
168 static int ael1002_intr_noop(struct cphy *phy) 168 static int ael1002_intr_noop(struct cphy *phy)
169 { 169 {
170 return 0; 170 return 0;
171 } 171 }
172 172
173 /* 173 /*
174 * Get link status for a 10GBASE-R device. 174 * Get link status for a 10GBASE-R device.
175 */ 175 */
176 static int get_link_status_r(struct cphy *phy, int *link_ok, int *speed, 176 static int get_link_status_r(struct cphy *phy, int *link_ok, int *speed,
177 int *duplex, int *fc) 177 int *duplex, int *fc)
178 { 178 {
179 if (link_ok) { 179 if (link_ok) {
180 unsigned int stat0, stat1, stat2; 180 unsigned int stat0, stat1, stat2;
181 int err = t3_mdio_read(phy, MDIO_MMD_PMAPMD, 181 int err = t3_mdio_read(phy, MDIO_MMD_PMAPMD,
182 MDIO_PMA_RXDET, &stat0); 182 MDIO_PMA_RXDET, &stat0);
183 183
184 if (!err) 184 if (!err)
185 err = t3_mdio_read(phy, MDIO_MMD_PCS, 185 err = t3_mdio_read(phy, MDIO_MMD_PCS,
186 MDIO_PCS_10GBRT_STAT1, &stat1); 186 MDIO_PCS_10GBRT_STAT1, &stat1);
187 if (!err) 187 if (!err)
188 err = t3_mdio_read(phy, MDIO_MMD_PHYXS, 188 err = t3_mdio_read(phy, MDIO_MMD_PHYXS,
189 MDIO_PHYXS_LNSTAT, &stat2); 189 MDIO_PHYXS_LNSTAT, &stat2);
190 if (err) 190 if (err)
191 return err; 191 return err;
192 *link_ok = (stat0 & stat1 & (stat2 >> 12)) & 1; 192 *link_ok = (stat0 & stat1 & (stat2 >> 12)) & 1;
193 } 193 }
194 if (speed) 194 if (speed)
195 *speed = SPEED_10000; 195 *speed = SPEED_10000;
196 if (duplex) 196 if (duplex)
197 *duplex = DUPLEX_FULL; 197 *duplex = DUPLEX_FULL;
198 return 0; 198 return 0;
199 } 199 }
200 200
201 static struct cphy_ops ael1002_ops = { 201 static struct cphy_ops ael1002_ops = {
202 .reset = ael1002_reset, 202 .reset = ael1002_reset,
203 .intr_enable = ael1002_intr_noop, 203 .intr_enable = ael1002_intr_noop,
204 .intr_disable = ael1002_intr_noop, 204 .intr_disable = ael1002_intr_noop,
205 .intr_clear = ael1002_intr_noop, 205 .intr_clear = ael1002_intr_noop,
206 .intr_handler = ael1002_intr_noop, 206 .intr_handler = ael1002_intr_noop,
207 .get_link_status = get_link_status_r, 207 .get_link_status = get_link_status_r,
208 .power_down = ael1002_power_down, 208 .power_down = ael1002_power_down,
209 .mmds = MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS | MDIO_DEVS_PHYXS, 209 .mmds = MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS | MDIO_DEVS_PHYXS,
210 }; 210 };
211 211
212 int t3_ael1002_phy_prep(struct cphy *phy, struct adapter *adapter, 212 int t3_ael1002_phy_prep(struct cphy *phy, struct adapter *adapter,
213 int phy_addr, const struct mdio_ops *mdio_ops) 213 int phy_addr, const struct mdio_ops *mdio_ops)
214 { 214 {
215 cphy_init(phy, adapter, phy_addr, &ael1002_ops, mdio_ops, 215 cphy_init(phy, adapter, phy_addr, &ael1002_ops, mdio_ops,
216 SUPPORTED_10000baseT_Full | SUPPORTED_AUI | SUPPORTED_FIBRE, 216 SUPPORTED_10000baseT_Full | SUPPORTED_AUI | SUPPORTED_FIBRE,
217 "10GBASE-R"); 217 "10GBASE-R");
218 ael100x_txon(phy); 218 ael100x_txon(phy);
219 return 0; 219 return 0;
220 } 220 }
221 221
222 static int ael1006_reset(struct cphy *phy, int wait) 222 static int ael1006_reset(struct cphy *phy, int wait)
223 { 223 {
224 return t3_phy_reset(phy, MDIO_MMD_PMAPMD, wait); 224 return t3_phy_reset(phy, MDIO_MMD_PMAPMD, wait);
225 } 225 }
226 226
227 static struct cphy_ops ael1006_ops = { 227 static struct cphy_ops ael1006_ops = {
228 .reset = ael1006_reset, 228 .reset = ael1006_reset,
229 .intr_enable = t3_phy_lasi_intr_enable, 229 .intr_enable = t3_phy_lasi_intr_enable,
230 .intr_disable = t3_phy_lasi_intr_disable, 230 .intr_disable = t3_phy_lasi_intr_disable,
231 .intr_clear = t3_phy_lasi_intr_clear, 231 .intr_clear = t3_phy_lasi_intr_clear,
232 .intr_handler = t3_phy_lasi_intr_handler, 232 .intr_handler = t3_phy_lasi_intr_handler,
233 .get_link_status = get_link_status_r, 233 .get_link_status = get_link_status_r,
234 .power_down = ael1002_power_down, 234 .power_down = ael1002_power_down,
235 .mmds = MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS | MDIO_DEVS_PHYXS, 235 .mmds = MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS | MDIO_DEVS_PHYXS,
236 }; 236 };
237 237
238 int t3_ael1006_phy_prep(struct cphy *phy, struct adapter *adapter, 238 int t3_ael1006_phy_prep(struct cphy *phy, struct adapter *adapter,
239 int phy_addr, const struct mdio_ops *mdio_ops) 239 int phy_addr, const struct mdio_ops *mdio_ops)
240 { 240 {
241 cphy_init(phy, adapter, phy_addr, &ael1006_ops, mdio_ops, 241 cphy_init(phy, adapter, phy_addr, &ael1006_ops, mdio_ops,
242 SUPPORTED_10000baseT_Full | SUPPORTED_AUI | SUPPORTED_FIBRE, 242 SUPPORTED_10000baseT_Full | SUPPORTED_AUI | SUPPORTED_FIBRE,
243 "10GBASE-SR"); 243 "10GBASE-SR");
244 ael100x_txon(phy); 244 ael100x_txon(phy);
245 return 0; 245 return 0;
246 } 246 }
247 247
248 /* 248 /*
249 * Decode our module type. 249 * Decode our module type.
250 */ 250 */
251 static int ael2xxx_get_module_type(struct cphy *phy, int delay_ms) 251 static int ael2xxx_get_module_type(struct cphy *phy, int delay_ms)
252 { 252 {
253 int v; 253 int v;
254 254
255 if (delay_ms) 255 if (delay_ms)
256 msleep(delay_ms); 256 msleep(delay_ms);
257 257
258 /* see SFF-8472 for below */ 258 /* see SFF-8472 for below */
259 v = ael_i2c_rd(phy, MODULE_DEV_ADDR, 3); 259 v = ael_i2c_rd(phy, MODULE_DEV_ADDR, 3);
260 if (v < 0) 260 if (v < 0)
261 return v; 261 return v;
262 262
263 if (v == 0x10) 263 if (v == 0x10)
264 return phy_modtype_sr; 264 return phy_modtype_sr;
265 if (v == 0x20) 265 if (v == 0x20)
266 return phy_modtype_lr; 266 return phy_modtype_lr;
267 if (v == 0x40) 267 if (v == 0x40)
268 return phy_modtype_lrm; 268 return phy_modtype_lrm;
269 269
270 v = ael_i2c_rd(phy, MODULE_DEV_ADDR, 6); 270 v = ael_i2c_rd(phy, MODULE_DEV_ADDR, 6);
271 if (v < 0) 271 if (v < 0)
272 return v; 272 return v;
273 if (v != 4) 273 if (v != 4)
274 goto unknown; 274 goto unknown;
275 275
276 v = ael_i2c_rd(phy, MODULE_DEV_ADDR, 10); 276 v = ael_i2c_rd(phy, MODULE_DEV_ADDR, 10);
277 if (v < 0) 277 if (v < 0)
278 return v; 278 return v;
279 279
280 if (v & 0x80) { 280 if (v & 0x80) {
281 v = ael_i2c_rd(phy, MODULE_DEV_ADDR, 0x12); 281 v = ael_i2c_rd(phy, MODULE_DEV_ADDR, 0x12);
282 if (v < 0) 282 if (v < 0)
283 return v; 283 return v;
284 return v > 10 ? phy_modtype_twinax_long : phy_modtype_twinax; 284 return v > 10 ? phy_modtype_twinax_long : phy_modtype_twinax;
285 } 285 }
286 unknown: 286 unknown:
287 return phy_modtype_unknown; 287 return phy_modtype_unknown;
288 } 288 }
289 289
290 /* 290 /*
291 * Code to support the Aeluros/NetLogic 2005 10Gb PHY. 291 * Code to support the Aeluros/NetLogic 2005 10Gb PHY.
292 */ 292 */
293 static int ael2005_setup_sr_edc(struct cphy *phy) 293 static int ael2005_setup_sr_edc(struct cphy *phy)
294 { 294 {
295 static struct reg_val regs[] = { 295 static struct reg_val regs[] = {
296 { MDIO_MMD_PMAPMD, 0xc003, 0xffff, 0x181 }, 296 { MDIO_MMD_PMAPMD, 0xc003, 0xffff, 0x181 },
297 { MDIO_MMD_PMAPMD, 0xc010, 0xffff, 0x448a }, 297 { MDIO_MMD_PMAPMD, 0xc010, 0xffff, 0x448a },
298 { MDIO_MMD_PMAPMD, 0xc04a, 0xffff, 0x5200 }, 298 { MDIO_MMD_PMAPMD, 0xc04a, 0xffff, 0x5200 },
299 { 0, 0, 0, 0 } 299 { 0, 0, 0, 0 }
300 }; 300 };
301 static u16 sr_edc[] = { 301
302 0xcc00, 0x2ff4,
303 0xcc01, 0x3cd4,
304 0xcc02, 0x2015,
305 0xcc03, 0x3105,
306 0xcc04, 0x6524,
307 0xcc05, 0x27ff,
308 0xcc06, 0x300f,
309 0xcc07, 0x2c8b,
310 0xcc08, 0x300b,
311 0xcc09, 0x4009,
312 0xcc0a, 0x400e,
313 0xcc0b, 0x2f72,
314 0xcc0c, 0x3002,
315 0xcc0d, 0x1002,
316 0xcc0e, 0x2172,
317 0xcc0f, 0x3012,
318 0xcc10, 0x1002,
319 0xcc11, 0x25d2,
320 0xcc12, 0x3012,
321 0xcc13, 0x1002,
322 0xcc14, 0xd01e,
323 0xcc15, 0x27d2,
324 0xcc16, 0x3012,
325 0xcc17, 0x1002,
326 0xcc18, 0x2004,
327 0xcc19, 0x3c84,
328 0xcc1a, 0x6436,
329 0xcc1b, 0x2007,
330 0xcc1c, 0x3f87,
331 0xcc1d, 0x8676,
332 0xcc1e, 0x40b7,
333 0xcc1f, 0xa746,
334 0xcc20, 0x4047,
335 0xcc21, 0x5673,
336 0xcc22, 0x2982,
337 0xcc23, 0x3002,
338 0xcc24, 0x13d2,
339 0xcc25, 0x8bbd,
340 0xcc26, 0x2862,
341 0xcc27, 0x3012,
342 0xcc28, 0x1002,
343 0xcc29, 0x2092,
344 0xcc2a, 0x3012,
345 0xcc2b, 0x1002,
346 0xcc2c, 0x5cc3,
347 0xcc2d, 0x314,
348 0xcc2e, 0x2942,
349 0xcc2f, 0x3002,
350 0xcc30, 0x1002,
351 0xcc31, 0xd019,
352 0xcc32, 0x2032,
353 0xcc33, 0x3012,
354 0xcc34, 0x1002,
355 0xcc35, 0x2a04,
356 0xcc36, 0x3c74,
357 0xcc37, 0x6435,
358 0xcc38, 0x2fa4,
359 0xcc39, 0x3cd4,
360 0xcc3a, 0x6624,
361 0xcc3b, 0x5563,
362 0xcc3c, 0x2d42,
363 0xcc3d, 0x3002,
364 0xcc3e, 0x13d2,
365 0xcc3f, 0x464d,
366 0xcc40, 0x2862,
367 0xcc41, 0x3012,
368 0xcc42, 0x1002,
369 0xcc43, 0x2032,
370 0xcc44, 0x3012,
371 0xcc45, 0x1002,
372 0xcc46, 0x2fb4,
373 0xcc47, 0x3cd4,
374 0xcc48, 0x6624,
375 0xcc49, 0x5563,
376 0xcc4a, 0x2d42,
377 0xcc4b, 0x3002,
378 0xcc4c, 0x13d2,
379 0xcc4d, 0x2ed2,
380 0xcc4e, 0x3002,
381 0xcc4f, 0x1002,
382 0xcc50, 0x2fd2,
383 0xcc51, 0x3002,
384 0xcc52, 0x1002,
385 0xcc53, 0x004,
386 0xcc54, 0x2942,
387 0xcc55, 0x3002,
388 0xcc56, 0x1002,
389 0xcc57, 0x2092,
390 0xcc58, 0x3012,
391 0xcc59, 0x1002,
392 0xcc5a, 0x5cc3,
393 0xcc5b, 0x317,
394 0xcc5c, 0x2f72,
395 0xcc5d, 0x3002,
396 0xcc5e, 0x1002,
397 0xcc5f, 0x2942,
398 0xcc60, 0x3002,
399 0xcc61, 0x1002,
400 0xcc62, 0x22cd,
401 0xcc63, 0x301d,
402 0xcc64, 0x2862,
403 0xcc65, 0x3012,
404 0xcc66, 0x1002,
405 0xcc67, 0x2ed2,
406 0xcc68, 0x3002,
407 0xcc69, 0x1002,
408 0xcc6a, 0x2d72,
409 0xcc6b, 0x3002,
410 0xcc6c, 0x1002,
411 0xcc6d, 0x628f,
412 0xcc6e, 0x2112,
413 0xcc6f, 0x3012,
414 0xcc70, 0x1002,
415 0xcc71, 0x5aa3,
416 0xcc72, 0x2dc2,
417 0xcc73, 0x3002,
418 0xcc74, 0x1312,
419 0xcc75, 0x6f72,
420 0xcc76, 0x1002,
421 0xcc77, 0x2807,
422 0xcc78, 0x31a7,
423 0xcc79, 0x20c4,
424 0xcc7a, 0x3c24,
425 0xcc7b, 0x6724,
426 0xcc7c, 0x1002,
427 0xcc7d, 0x2807,
428 0xcc7e, 0x3187,
429 0xcc7f, 0x20c4,
430 0xcc80, 0x3c24,
431 0xcc81, 0x6724,
432 0xcc82, 0x1002,
433 0xcc83, 0x2514,
434 0xcc84, 0x3c64,
435 0xcc85, 0x6436,
436 0xcc86, 0xdff4,
437 0xcc87, 0x6436,
438 0xcc88, 0x1002,
439 0xcc89, 0x40a4,
440 0xcc8a, 0x643c,
441 0xcc8b, 0x4016,
442 0xcc8c, 0x8c6c,
443 0xcc8d, 0x2b24,
444 0xcc8e, 0x3c24,
445 0xcc8f, 0x6435,
446 0xcc90, 0x1002,
447 0xcc91, 0x2b24,
448 0xcc92, 0x3c24,
449 0xcc93, 0x643a,
450 0xcc94, 0x4025,
451 0xcc95, 0x8a5a,
452 0xcc96, 0x1002,
453 0xcc97, 0x2731,
454 0xcc98, 0x3011,
455 0xcc99, 0x1001,
456 0xcc9a, 0xc7a0,
457 0xcc9b, 0x100,
458 0xcc9c, 0xc502,
459 0xcc9d, 0x53ac,
460 0xcc9e, 0xc503,
461 0xcc9f, 0xd5d5,
462 0xcca0, 0xc600,
463 0xcca1, 0x2a6d,
464 0xcca2, 0xc601,
465 0xcca3, 0x2a4c,
466 0xcca4, 0xc602,
467 0xcca5, 0x111,
468 0xcca6, 0xc60c,
469 0xcca7, 0x5900,
470 0xcca8, 0xc710,
471 0xcca9, 0x700,
472 0xccaa, 0xc718,
473 0xccab, 0x700,
474 0xccac, 0xc720,
475 0xccad, 0x4700,
476 0xccae, 0xc801,
477 0xccaf, 0x7f50,
478 0xccb0, 0xc802,
479 0xccb1, 0x7760,
480 0xccb2, 0xc803,
481 0xccb3, 0x7fce,
482 0xccb4, 0xc804,
483 0xccb5, 0x5700,
484 0xccb6, 0xc805,
485 0xccb7, 0x5f11,
486 0xccb8, 0xc806,
487 0xccb9, 0x4751,
488 0xccba, 0xc807,
489 0xccbb, 0x57e1,
490 0xccbc, 0xc808,
491 0xccbd, 0x2700,
492 0xccbe, 0xc809,
493 0xccbf, 0x000,
494 0xccc0, 0xc821,
495 0xccc1, 0x002,
496 0xccc2, 0xc822,
497 0xccc3, 0x014,
498 0xccc4, 0xc832,
499 0xccc5, 0x1186,
500 0xccc6, 0xc847,
501 0xccc7, 0x1e02,
502 0xccc8, 0xc013,
503 0xccc9, 0xf341,
504 0xccca, 0xc01a,
505 0xcccb, 0x446,
506 0xcccc, 0xc024,
507 0xcccd, 0x1000,
508 0xccce, 0xc025,
509 0xcccf, 0xa00,
510 0xccd0, 0xc026,
511 0xccd1, 0xc0c,
512 0xccd2, 0xc027,
513 0xccd3, 0xc0c,
514 0xccd4, 0xc029,
515 0xccd5, 0x0a0,
516 0xccd6, 0xc030,
517 0xccd7, 0xa00,
518 0xccd8, 0xc03c,
519 0xccd9, 0x01c,
520 0xccda, 0xc005,
521 0xccdb, 0x7a06,
522 0xccdc, 0x000,
523 0xccdd, 0x2731,
524 0xccde, 0x3011,
525 0xccdf, 0x1001,
526 0xcce0, 0xc620,
527 0xcce1, 0x000,
528 0xcce2, 0xc621,
529 0xcce3, 0x03f,
530 0xcce4, 0xc622,
531 0xcce5, 0x000,
532 0xcce6, 0xc623,
533 0xcce7, 0x000,
534 0xcce8, 0xc624,
535 0xcce9, 0x000,
536 0xccea, 0xc625,
537 0xcceb, 0x000,
538 0xccec, 0xc627,
539 0xcced, 0x000,
540 0xccee, 0xc628,
541 0xccef, 0x000,
542 0xccf0, 0xc62c,
543 0xccf1, 0x000,
544 0xccf2, 0x000,
545 0xccf3, 0x2806,
546 0xccf4, 0x3cb6,
547 0xccf5, 0xc161,
548 0xccf6, 0x6134,
549 0xccf7, 0x6135,
550 0xccf8, 0x5443,
551 0xccf9, 0x303,
552 0xccfa, 0x6524,
553 0xccfb, 0x00b,
554 0xccfc, 0x1002,
555 0xccfd, 0x2104,
556 0xccfe, 0x3c24,
557 0xccff, 0x2105,
558 0xcd00, 0x3805,
559 0xcd01, 0x6524,
560 0xcd02, 0xdff4,
561 0xcd03, 0x4005,
562 0xcd04, 0x6524,
563 0xcd05, 0x1002,
564 0xcd06, 0x5dd3,
565 0xcd07, 0x306,
566 0xcd08, 0x2ff7,
567 0xcd09, 0x38f7,
568 0xcd0a, 0x60b7,
569 0xcd0b, 0xdffd,
570 0xcd0c, 0x00a,
571 0xcd0d, 0x1002,
572 0xcd0e, 0
573 };
574 int i, err; 302 int i, err;
575 303
576 err = set_phy_regs(phy, regs); 304 err = set_phy_regs(phy, regs);
577 if (err) 305 if (err)
578 return err; 306 return err;
579 307
580 msleep(50); 308 msleep(50);
581 309
582 for (i = 0; i < ARRAY_SIZE(sr_edc) && !err; i += 2) 310 if (phy->priv != edc_sr)
583 err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, sr_edc[i], 311 err = t3_get_edc_fw(phy, EDC_OPT_AEL2005,
584 sr_edc[i + 1]); 312 EDC_OPT_AEL2005_SIZE);
313 if (err)
314 return err;
315
316 for (i = 0; i < EDC_OPT_AEL2005_SIZE / sizeof(u16) && !err; i += 2)
317 err = t3_mdio_write(phy, MDIO_MMD_PMAPMD,
318 phy->phy_cache[i],
319 phy->phy_cache[i + 1]);
585 if (!err) 320 if (!err)
586 phy->priv = edc_sr; 321 phy->priv = edc_sr;
587 return err; 322 return err;
588 } 323 }
589 324
590 static int ael2005_setup_twinax_edc(struct cphy *phy, int modtype) 325 static int ael2005_setup_twinax_edc(struct cphy *phy, int modtype)
591 { 326 {
592 static struct reg_val regs[] = { 327 static struct reg_val regs[] = {
593 { MDIO_MMD_PMAPMD, 0xc04a, 0xffff, 0x5a00 }, 328 { MDIO_MMD_PMAPMD, 0xc04a, 0xffff, 0x5a00 },
594 { 0, 0, 0, 0 } 329 { 0, 0, 0, 0 }
595 }; 330 };
596 static struct reg_val preemphasis[] = { 331 static struct reg_val preemphasis[] = {
597 { MDIO_MMD_PMAPMD, 0xc014, 0xffff, 0xfe16 }, 332 { MDIO_MMD_PMAPMD, 0xc014, 0xffff, 0xfe16 },
598 { MDIO_MMD_PMAPMD, 0xc015, 0xffff, 0xa000 }, 333 { MDIO_MMD_PMAPMD, 0xc015, 0xffff, 0xa000 },
599 { 0, 0, 0, 0 } 334 { 0, 0, 0, 0 }
600 }; 335 };
601 static u16 twinax_edc[] = {
602 0xcc00, 0x4009,
603 0xcc01, 0x27ff,
604 0xcc02, 0x300f,
605 0xcc03, 0x40aa,
606 0xcc04, 0x401c,
607 0xcc05, 0x401e,
608 0xcc06, 0x2ff4,
609 0xcc07, 0x3cd4,
610 0xcc08, 0x2035,
611 0xcc09, 0x3145,
612 0xcc0a, 0x6524,
613 0xcc0b, 0x26a2,
614 0xcc0c, 0x3012,
615 0xcc0d, 0x1002,
616 0xcc0e, 0x29c2,
617 0xcc0f, 0x3002,
618 0xcc10, 0x1002,
619 0xcc11, 0x2072,
620 0xcc12, 0x3012,
621 0xcc13, 0x1002,
622 0xcc14, 0x22cd,
623 0xcc15, 0x301d,
624 0xcc16, 0x2e52,
625 0xcc17, 0x3012,
626 0xcc18, 0x1002,
627 0xcc19, 0x28e2,
628 0xcc1a, 0x3002,
629 0xcc1b, 0x1002,
630 0xcc1c, 0x628f,
631 0xcc1d, 0x2ac2,
632 0xcc1e, 0x3012,
633 0xcc1f, 0x1002,
634 0xcc20, 0x5553,
635 0xcc21, 0x2ae2,
636 0xcc22, 0x3002,
637 0xcc23, 0x1302,
638 0xcc24, 0x401e,
639 0xcc25, 0x2be2,
640 0xcc26, 0x3012,
641 0xcc27, 0x1002,
642 0xcc28, 0x2da2,
643 0xcc29, 0x3012,
644 0xcc2a, 0x1002,
645 0xcc2b, 0x2ba2,
646 0xcc2c, 0x3002,
647 0xcc2d, 0x1002,
648 0xcc2e, 0x5ee3,
649 0xcc2f, 0x305,
650 0xcc30, 0x400e,
651 0xcc31, 0x2bc2,
652 0xcc32, 0x3002,
653 0xcc33, 0x1002,
654 0xcc34, 0x2b82,
655 0xcc35, 0x3012,
656 0xcc36, 0x1002,
657 0xcc37, 0x5663,
658 0xcc38, 0x302,
659 0xcc39, 0x401e,
660 0xcc3a, 0x6f72,
661 0xcc3b, 0x1002,
662 0xcc3c, 0x628f,
663 0xcc3d, 0x2be2,
664 0xcc3e, 0x3012,
665 0xcc3f, 0x1002,
666 0xcc40, 0x22cd,
667 0xcc41, 0x301d,
668 0xcc42, 0x2e52,
669 0xcc43, 0x3012,
670 0xcc44, 0x1002,
671 0xcc45, 0x2522,
672 0xcc46, 0x3012,
673 0xcc47, 0x1002,
674 0xcc48, 0x2da2,
675 0xcc49, 0x3012,
676 0xcc4a, 0x1002,
677 0xcc4b, 0x2ca2,
678 0xcc4c, 0x3012,
679 0xcc4d, 0x1002,
680 0xcc4e, 0x2fa4,
681 0xcc4f, 0x3cd4,
682 0xcc50, 0x6624,
683 0xcc51, 0x410b,
684 0xcc52, 0x56b3,
685 0xcc53, 0x3c4,
686 0xcc54, 0x2fb2,
687 0xcc55, 0x3002,
688 0xcc56, 0x1002,
689 0xcc57, 0x220b,
690 0xcc58, 0x303b,
691 0xcc59, 0x56b3,
692 0xcc5a, 0x3c3,
693 0xcc5b, 0x866b,
694 0xcc5c, 0x400c,
695 0xcc5d, 0x23a2,
696 0xcc5e, 0x3012,
697 0xcc5f, 0x1002,
698 0xcc60, 0x2da2,
699 0xcc61, 0x3012,
700 0xcc62, 0x1002,
701 0xcc63, 0x2ca2,
702 0xcc64, 0x3012,
703 0xcc65, 0x1002,
704 0xcc66, 0x2fb4,
705 0xcc67, 0x3cd4,
706 0xcc68, 0x6624,
707 0xcc69, 0x56b3,
708 0xcc6a, 0x3c3,
709 0xcc6b, 0x866b,
710 0xcc6c, 0x401c,
711 0xcc6d, 0x2205,
712 0xcc6e, 0x3035,
713 0xcc6f, 0x5b53,
714 0xcc70, 0x2c52,
715 0xcc71, 0x3002,
716 0xcc72, 0x13c2,
717 0xcc73, 0x5cc3,
718 0xcc74, 0x317,
719 0xcc75, 0x2522,
720 0xcc76, 0x3012,
721 0xcc77, 0x1002,
722 0xcc78, 0x2da2,
723 0xcc79, 0x3012,
724 0xcc7a, 0x1002,
725 0xcc7b, 0x2b82,
726 0xcc7c, 0x3012,
727 0xcc7d, 0x1002,
728 0xcc7e, 0x5663,
729 0xcc7f, 0x303,
730 0xcc80, 0x401e,
731 0xcc81, 0x004,
732 0xcc82, 0x2c42,
733 0xcc83, 0x3012,
734 0xcc84, 0x1002,
735 0xcc85, 0x6f72,
736 0xcc86, 0x1002,
737 0xcc87, 0x628f,
738 0xcc88, 0x2304,
739 0xcc89, 0x3c84,
740 0xcc8a, 0x6436,
741 0xcc8b, 0xdff4,
742 0xcc8c, 0x6436,
743 0xcc8d, 0x2ff5,
744 0xcc8e, 0x3005,
745 0xcc8f, 0x8656,
746 0xcc90, 0xdfba,
747 0xcc91, 0x56a3,
748 0xcc92, 0xd05a,
749 0xcc93, 0x21c2,
750 0xcc94, 0x3012,
751 0xcc95, 0x1392,
752 0xcc96, 0xd05a,
753 0xcc97, 0x56a3,
754 0xcc98, 0xdfba,
755 0xcc99, 0x383,
756 0xcc9a, 0x6f72,
757 0xcc9b, 0x1002,
758 0xcc9c, 0x28c5,
759 0xcc9d, 0x3005,
760 0xcc9e, 0x4178,
761 0xcc9f, 0x5653,
762 0xcca0, 0x384,
763 0xcca1, 0x22b2,
764 0xcca2, 0x3012,
765 0xcca3, 0x1002,
766 0xcca4, 0x2be5,
767 0xcca5, 0x3005,
768 0xcca6, 0x41e8,
769 0xcca7, 0x5653,
770 0xcca8, 0x382,
771 0xcca9, 0x002,
772 0xccaa, 0x4258,
773 0xccab, 0x2474,
774 0xccac, 0x3c84,
775 0xccad, 0x6437,
776 0xccae, 0xdff4,
777 0xccaf, 0x6437,
778 0xccb0, 0x2ff5,
779 0xccb1, 0x3c05,
780 0xccb2, 0x8757,
781 0xccb3, 0xb888,
782 0xccb4, 0x9787,
783 0xccb5, 0xdff4,
784 0xccb6, 0x6724,
785 0xccb7, 0x866a,
786 0xccb8, 0x6f72,
787 0xccb9, 0x1002,
788 0xccba, 0x2d01,
789 0xccbb, 0x3011,
790 0xccbc, 0x1001,
791 0xccbd, 0xc620,
792 0xccbe, 0x14e5,
793 0xccbf, 0xc621,
794 0xccc0, 0xc53d,
795 0xccc1, 0xc622,
796 0xccc2, 0x3cbe,
797 0xccc3, 0xc623,
798 0xccc4, 0x4452,
799 0xccc5, 0xc624,
800 0xccc6, 0xc5c5,
801 0xccc7, 0xc625,
802 0xccc8, 0xe01e,
803 0xccc9, 0xc627,
804 0xccca, 0x000,
805 0xcccb, 0xc628,
806 0xcccc, 0x000,
807 0xcccd, 0xc62b,
808 0xccce, 0x000,
809 0xcccf, 0xc62c,
810 0xccd0, 0x000,
811 0xccd1, 0x000,
812 0xccd2, 0x2d01,
813 0xccd3, 0x3011,
814 0xccd4, 0x1001,
815 0xccd5, 0xc620,
816 0xccd6, 0x000,
817 0xccd7, 0xc621,
818 0xccd8, 0x000,
819 0xccd9, 0xc622,
820 0xccda, 0x0ce,
821 0xccdb, 0xc623,
822 0xccdc, 0x07f,
823 0xccdd, 0xc624,
824 0xccde, 0x032,
825 0xccdf, 0xc625,
826 0xcce0, 0x000,
827 0xcce1, 0xc627,
828 0xcce2, 0x000,
829 0xcce3, 0xc628,
830 0xcce4, 0x000,
831 0xcce5, 0xc62b,
832 0xcce6, 0x000,
833 0xcce7, 0xc62c,
834 0xcce8, 0x000,
835 0xcce9, 0x000,
836 0xccea, 0x2d01,
837 0xcceb, 0x3011,
838 0xccec, 0x1001,
839 0xcced, 0xc502,
840 0xccee, 0x609f,
841 0xccef, 0xc600,
842 0xccf0, 0x2a6e,
843 0xccf1, 0xc601,
844 0xccf2, 0x2a2c,
845 0xccf3, 0xc60c,
846 0xccf4, 0x5400,
847 0xccf5, 0xc710,
848 0xccf6, 0x700,
849 0xccf7, 0xc718,
850 0xccf8, 0x700,
851 0xccf9, 0xc720,
852 0xccfa, 0x4700,
853 0xccfb, 0xc728,
854 0xccfc, 0x700,
855 0xccfd, 0xc729,
856 0xccfe, 0x1207,
857 0xccff, 0xc801,
858 0xcd00, 0x7f50,
859 0xcd01, 0xc802,
860 0xcd02, 0x7760,
861 0xcd03, 0xc803,
862 0xcd04, 0x7fce,
863 0xcd05, 0xc804,
864 0xcd06, 0x520e,
865 0xcd07, 0xc805,
866 0xcd08, 0x5c11,
867 0xcd09, 0xc806,
868 0xcd0a, 0x3c51,
869 0xcd0b, 0xc807,
870 0xcd0c, 0x4061,
871 0xcd0d, 0xc808,
872 0xcd0e, 0x49c1,
873 0xcd0f, 0xc809,
874 0xcd10, 0x3840,
875 0xcd11, 0xc80a,
876 0xcd12, 0x000,
877 0xcd13, 0xc821,
878 0xcd14, 0x002,
879 0xcd15, 0xc822,
880 0xcd16, 0x046,
881 0xcd17, 0xc844,
882 0xcd18, 0x182f,
883 0xcd19, 0xc013,
884 0xcd1a, 0xf341,
885 0xcd1b, 0xc01a,
886 0xcd1c, 0x446,
887 0xcd1d, 0xc024,
888 0xcd1e, 0x1000,
889 0xcd1f, 0xc025,
890 0xcd20, 0xa00,
891 0xcd21, 0xc026,
892 0xcd22, 0xc0c,
893 0xcd23, 0xc027,
894 0xcd24, 0xc0c,
895 0xcd25, 0xc029,
896 0xcd26, 0x0a0,
897 0xcd27, 0xc030,
898 0xcd28, 0xa00,
899 0xcd29, 0xc03c,
900 0xcd2a, 0x01c,
901 0xcd2b, 0x000,
902 0xcd2c, 0x2b84,
903 0xcd2d, 0x3c74,
904 0xcd2e, 0x6435,
905 0xcd2f, 0xdff4,
906 0xcd30, 0x6435,
907 0xcd31, 0x2806,
908 0xcd32, 0x3006,
909 0xcd33, 0x8565,
910 0xcd34, 0x2b24,
911 0xcd35, 0x3c24,
912 0xcd36, 0x6436,
913 0xcd37, 0x1002,
914 0xcd38, 0x2b24,
915 0xcd39, 0x3c24,
916 0xcd3a, 0x6436,
917 0xcd3b, 0x4045,
918 0xcd3c, 0x8656,
919 0xcd3d, 0x1002,
920 0xcd3e, 0x2807,
921 0xcd3f, 0x31a7,
922 0xcd40, 0x20c4,
923 0xcd41, 0x3c24,
924 0xcd42, 0x6724,
925 0xcd43, 0x1002,
926 0xcd44, 0x2807,
927 0xcd45, 0x3187,
928 0xcd46, 0x20c4,
929 0xcd47, 0x3c24,
930 0xcd48, 0x6724,
931 0xcd49, 0x1002,
932 0xcd4a, 0x2514,
933 0xcd4b, 0x3c64,
934 0xcd4c, 0x6436,
935 0xcd4d, 0xdff4,
936 0xcd4e, 0x6436,
937 0xcd4f, 0x1002,
938 0xcd50, 0x2806,
939 0xcd51, 0x3cb6,
940 0xcd52, 0xc161,
941 0xcd53, 0x6134,
942 0xcd54, 0x6135,
943 0xcd55, 0x5443,
944 0xcd56, 0x303,
945 0xcd57, 0x6524,
946 0xcd58, 0x00b,
947 0xcd59, 0x1002,
948 0xcd5a, 0xd019,
949 0xcd5b, 0x2104,
950 0xcd5c, 0x3c24,
951 0xcd5d, 0x2105,
952 0xcd5e, 0x3805,
953 0xcd5f, 0x6524,
954 0xcd60, 0xdff4,
955 0xcd61, 0x4005,
956 0xcd62, 0x6524,
957 0xcd63, 0x2e8d,
958 0xcd64, 0x303d,
959 0xcd65, 0x5dd3,
960 0xcd66, 0x306,
961 0xcd67, 0x2ff7,
962 0xcd68, 0x38f7,
963 0xcd69, 0x60b7,
964 0xcd6a, 0xdffd,
965 0xcd6b, 0x00a,
966 0xcd6c, 0x1002,
967 0xcd6d, 0
968 };
969 int i, err; 336 int i, err;
970 337
971 err = set_phy_regs(phy, regs); 338 err = set_phy_regs(phy, regs);
972 if (!err && modtype == phy_modtype_twinax_long) 339 if (!err && modtype == phy_modtype_twinax_long)
973 err = set_phy_regs(phy, preemphasis); 340 err = set_phy_regs(phy, preemphasis);
974 if (err) 341 if (err)
975 return err; 342 return err;
976 343
977 msleep(50); 344 msleep(50);
978 345
979 for (i = 0; i < ARRAY_SIZE(twinax_edc) && !err; i += 2) 346 if (phy->priv != edc_twinax)
980 err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, twinax_edc[i], 347 err = t3_get_edc_fw(phy, EDC_TWX_AEL2005,
981 twinax_edc[i + 1]); 348 EDC_TWX_AEL2005_SIZE);
349 if (err)
350 return err;
351
352 for (i = 0; i < EDC_TWX_AEL2005_SIZE / sizeof(u16) && !err; i += 2)
353 err = t3_mdio_write(phy, MDIO_MMD_PMAPMD,
354 phy->phy_cache[i],
355 phy->phy_cache[i + 1]);
982 if (!err) 356 if (!err)
983 phy->priv = edc_twinax; 357 phy->priv = edc_twinax;
984 return err; 358 return err;
985 } 359 }
986 360
987 static int ael2005_get_module_type(struct cphy *phy, int delay_ms) 361 static int ael2005_get_module_type(struct cphy *phy, int delay_ms)
988 { 362 {
989 int v; 363 int v;
990 unsigned int stat; 364 unsigned int stat;
991 365
992 v = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AEL2005_GPIO_CTRL, &stat); 366 v = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AEL2005_GPIO_CTRL, &stat);
993 if (v) 367 if (v)
994 return v; 368 return v;
995 369
996 if (stat & (1 << 8)) /* module absent */ 370 if (stat & (1 << 8)) /* module absent */
997 return phy_modtype_none; 371 return phy_modtype_none;
998 372
999 return ael2xxx_get_module_type(phy, delay_ms); 373 return ael2xxx_get_module_type(phy, delay_ms);
1000 } 374 }
1001 375
1002 static int ael2005_intr_enable(struct cphy *phy) 376 static int ael2005_intr_enable(struct cphy *phy)
1003 { 377 {
1004 int err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL2005_GPIO_CTRL, 0x200); 378 int err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL2005_GPIO_CTRL, 0x200);
1005 return err ? err : t3_phy_lasi_intr_enable(phy); 379 return err ? err : t3_phy_lasi_intr_enable(phy);
1006 } 380 }
1007 381
1008 static int ael2005_intr_disable(struct cphy *phy) 382 static int ael2005_intr_disable(struct cphy *phy)
1009 { 383 {
1010 int err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL2005_GPIO_CTRL, 0x100); 384 int err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL2005_GPIO_CTRL, 0x100);
1011 return err ? err : t3_phy_lasi_intr_disable(phy); 385 return err ? err : t3_phy_lasi_intr_disable(phy);
1012 } 386 }
1013 387
1014 static int ael2005_intr_clear(struct cphy *phy) 388 static int ael2005_intr_clear(struct cphy *phy)
1015 { 389 {
1016 int err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL2005_GPIO_CTRL, 0xd00); 390 int err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL2005_GPIO_CTRL, 0xd00);
1017 return err ? err : t3_phy_lasi_intr_clear(phy); 391 return err ? err : t3_phy_lasi_intr_clear(phy);
1018 } 392 }
1019 393
1020 static int ael2005_reset(struct cphy *phy, int wait) 394 static int ael2005_reset(struct cphy *phy, int wait)
1021 { 395 {
1022 static struct reg_val regs0[] = { 396 static struct reg_val regs0[] = {
1023 { MDIO_MMD_PMAPMD, 0xc001, 0, 1 << 5 }, 397 { MDIO_MMD_PMAPMD, 0xc001, 0, 1 << 5 },
1024 { MDIO_MMD_PMAPMD, 0xc017, 0, 1 << 5 }, 398 { MDIO_MMD_PMAPMD, 0xc017, 0, 1 << 5 },
1025 { MDIO_MMD_PMAPMD, 0xc013, 0xffff, 0xf341 }, 399 { MDIO_MMD_PMAPMD, 0xc013, 0xffff, 0xf341 },
1026 { MDIO_MMD_PMAPMD, 0xc210, 0xffff, 0x8000 }, 400 { MDIO_MMD_PMAPMD, 0xc210, 0xffff, 0x8000 },
1027 { MDIO_MMD_PMAPMD, 0xc210, 0xffff, 0x8100 }, 401 { MDIO_MMD_PMAPMD, 0xc210, 0xffff, 0x8100 },
1028 { MDIO_MMD_PMAPMD, 0xc210, 0xffff, 0x8000 }, 402 { MDIO_MMD_PMAPMD, 0xc210, 0xffff, 0x8000 },
1029 { MDIO_MMD_PMAPMD, 0xc210, 0xffff, 0 }, 403 { MDIO_MMD_PMAPMD, 0xc210, 0xffff, 0 },
1030 { 0, 0, 0, 0 } 404 { 0, 0, 0, 0 }
1031 }; 405 };
1032 static struct reg_val regs1[] = { 406 static struct reg_val regs1[] = {
1033 { MDIO_MMD_PMAPMD, 0xca00, 0xffff, 0x0080 }, 407 { MDIO_MMD_PMAPMD, 0xca00, 0xffff, 0x0080 },
1034 { MDIO_MMD_PMAPMD, 0xca12, 0xffff, 0 }, 408 { MDIO_MMD_PMAPMD, 0xca12, 0xffff, 0 },
1035 { 0, 0, 0, 0 } 409 { 0, 0, 0, 0 }
1036 }; 410 };
1037 411
1038 int err; 412 int err;
1039 unsigned int lasi_ctrl; 413 unsigned int lasi_ctrl;
1040 414
1041 err = t3_mdio_read(phy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_CTRL, 415 err = t3_mdio_read(phy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_CTRL,
1042 &lasi_ctrl); 416 &lasi_ctrl);
1043 if (err) 417 if (err)
1044 return err; 418 return err;
1045 419
1046 err = t3_phy_reset(phy, MDIO_MMD_PMAPMD, 0); 420 err = t3_phy_reset(phy, MDIO_MMD_PMAPMD, 0);
1047 if (err) 421 if (err)
1048 return err; 422 return err;
1049 423
1050 msleep(125); 424 msleep(125);
1051 phy->priv = edc_none; 425 phy->priv = edc_none;
1052 err = set_phy_regs(phy, regs0); 426 err = set_phy_regs(phy, regs0);
1053 if (err) 427 if (err)
1054 return err; 428 return err;
1055 429
1056 msleep(50); 430 msleep(50);
1057 431
1058 err = ael2005_get_module_type(phy, 0); 432 err = ael2005_get_module_type(phy, 0);
1059 if (err < 0) 433 if (err < 0)
1060 return err; 434 return err;
1061 phy->modtype = err; 435 phy->modtype = err;
1062 436
1063 if (err == phy_modtype_twinax || err == phy_modtype_twinax_long) 437 if (err == phy_modtype_twinax || err == phy_modtype_twinax_long)
1064 err = ael2005_setup_twinax_edc(phy, err); 438 err = ael2005_setup_twinax_edc(phy, err);
1065 else 439 else
1066 err = ael2005_setup_sr_edc(phy); 440 err = ael2005_setup_sr_edc(phy);
1067 if (err) 441 if (err)
1068 return err; 442 return err;
1069 443
1070 err = set_phy_regs(phy, regs1); 444 err = set_phy_regs(phy, regs1);
1071 if (err) 445 if (err)
1072 return err; 446 return err;
1073 447
1074 /* reset wipes out interrupts, reenable them if they were on */ 448 /* reset wipes out interrupts, reenable them if they were on */
1075 if (lasi_ctrl & 1) 449 if (lasi_ctrl & 1)
1076 err = ael2005_intr_enable(phy); 450 err = ael2005_intr_enable(phy);
1077 return err; 451 return err;
1078 } 452 }
1079 453
1080 static int ael2005_intr_handler(struct cphy *phy) 454 static int ael2005_intr_handler(struct cphy *phy)
1081 { 455 {
1082 unsigned int stat; 456 unsigned int stat;
1083 int ret, edc_needed, cause = 0; 457 int ret, edc_needed, cause = 0;
1084 458
1085 ret = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AEL2005_GPIO_STAT, &stat); 459 ret = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AEL2005_GPIO_STAT, &stat);
1086 if (ret) 460 if (ret)
1087 return ret; 461 return ret;
1088 462
1089 if (stat & AEL2005_MODDET_IRQ) { 463 if (stat & AEL2005_MODDET_IRQ) {
1090 ret = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL2005_GPIO_CTRL, 464 ret = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL2005_GPIO_CTRL,
1091 0xd00); 465 0xd00);
1092 if (ret) 466 if (ret)
1093 return ret; 467 return ret;
1094 468
1095 /* modules have max 300 ms init time after hot plug */ 469 /* modules have max 300 ms init time after hot plug */
1096 ret = ael2005_get_module_type(phy, 300); 470 ret = ael2005_get_module_type(phy, 300);
1097 if (ret < 0) 471 if (ret < 0)
1098 return ret; 472 return ret;
1099 473
1100 phy->modtype = ret; 474 phy->modtype = ret;
1101 if (ret == phy_modtype_none) 475 if (ret == phy_modtype_none)
1102 edc_needed = phy->priv; /* on unplug retain EDC */ 476 edc_needed = phy->priv; /* on unplug retain EDC */
1103 else if (ret == phy_modtype_twinax || 477 else if (ret == phy_modtype_twinax ||
1104 ret == phy_modtype_twinax_long) 478 ret == phy_modtype_twinax_long)
1105 edc_needed = edc_twinax; 479 edc_needed = edc_twinax;
1106 else 480 else
1107 edc_needed = edc_sr; 481 edc_needed = edc_sr;
1108 482
1109 if (edc_needed != phy->priv) { 483 if (edc_needed != phy->priv) {
1110 ret = ael2005_reset(phy, 0); 484 ret = ael2005_reset(phy, 0);
1111 return ret ? ret : cphy_cause_module_change; 485 return ret ? ret : cphy_cause_module_change;
1112 } 486 }
1113 cause = cphy_cause_module_change; 487 cause = cphy_cause_module_change;
1114 } 488 }
1115 489
1116 ret = t3_phy_lasi_intr_handler(phy); 490 ret = t3_phy_lasi_intr_handler(phy);
1117 if (ret < 0) 491 if (ret < 0)
1118 return ret; 492 return ret;
1119 493
1120 ret |= cause; 494 ret |= cause;
1121 return ret ? ret : cphy_cause_link_change; 495 return ret ? ret : cphy_cause_link_change;
1122 } 496 }
1123 497
1124 static struct cphy_ops ael2005_ops = { 498 static struct cphy_ops ael2005_ops = {
1125 .reset = ael2005_reset, 499 .reset = ael2005_reset,
1126 .intr_enable = ael2005_intr_enable, 500 .intr_enable = ael2005_intr_enable,
1127 .intr_disable = ael2005_intr_disable, 501 .intr_disable = ael2005_intr_disable,
1128 .intr_clear = ael2005_intr_clear, 502 .intr_clear = ael2005_intr_clear,
1129 .intr_handler = ael2005_intr_handler, 503 .intr_handler = ael2005_intr_handler,
1130 .get_link_status = get_link_status_r, 504 .get_link_status = get_link_status_r,
1131 .power_down = ael1002_power_down, 505 .power_down = ael1002_power_down,
1132 .mmds = MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS | MDIO_DEVS_PHYXS, 506 .mmds = MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS | MDIO_DEVS_PHYXS,
1133 }; 507 };
1134 508
1135 int t3_ael2005_phy_prep(struct cphy *phy, struct adapter *adapter, 509 int t3_ael2005_phy_prep(struct cphy *phy, struct adapter *adapter,
1136 int phy_addr, const struct mdio_ops *mdio_ops) 510 int phy_addr, const struct mdio_ops *mdio_ops)
1137 { 511 {
1138 cphy_init(phy, adapter, phy_addr, &ael2005_ops, mdio_ops, 512 cphy_init(phy, adapter, phy_addr, &ael2005_ops, mdio_ops,
1139 SUPPORTED_10000baseT_Full | SUPPORTED_AUI | SUPPORTED_FIBRE | 513 SUPPORTED_10000baseT_Full | SUPPORTED_AUI | SUPPORTED_FIBRE |
1140 SUPPORTED_IRQ, "10GBASE-R"); 514 SUPPORTED_IRQ, "10GBASE-R");
1141 msleep(125); 515 msleep(125);
1142 return t3_mdio_change_bits(phy, MDIO_MMD_PMAPMD, AEL_OPT_SETTINGS, 0, 516 return t3_mdio_change_bits(phy, MDIO_MMD_PMAPMD, AEL_OPT_SETTINGS, 0,
1143 1 << 5); 517 1 << 5);
1144 } 518 }
1145 519
1146 /* 520 /*
1147 * Setup EDC and other parameters for operation with an optical module. 521 * Setup EDC and other parameters for operation with an optical module.
1148 */ 522 */
1149 static int ael2020_setup_sr_edc(struct cphy *phy) 523 static int ael2020_setup_sr_edc(struct cphy *phy)
1150 { 524 {
1151 static struct reg_val regs[] = { 525 static struct reg_val regs[] = {
1152 /* set CDR offset to 10 */ 526 /* set CDR offset to 10 */
1153 { MDIO_MMD_PMAPMD, 0xcc01, 0xffff, 0x488a }, 527 { MDIO_MMD_PMAPMD, 0xcc01, 0xffff, 0x488a },
1154 528
1155 /* adjust 10G RX bias current */ 529 /* adjust 10G RX bias current */
1156 { MDIO_MMD_PMAPMD, 0xcb1b, 0xffff, 0x0200 }, 530 { MDIO_MMD_PMAPMD, 0xcb1b, 0xffff, 0x0200 },
1157 { MDIO_MMD_PMAPMD, 0xcb1c, 0xffff, 0x00f0 }, 531 { MDIO_MMD_PMAPMD, 0xcb1c, 0xffff, 0x00f0 },
1158 { MDIO_MMD_PMAPMD, 0xcc06, 0xffff, 0x00e0 }, 532 { MDIO_MMD_PMAPMD, 0xcc06, 0xffff, 0x00e0 },
1159 533
1160 /* end */ 534 /* end */
1161 { 0, 0, 0, 0 } 535 { 0, 0, 0, 0 }
1162 }; 536 };
1163 int err; 537 int err;
1164 538
1165 err = set_phy_regs(phy, regs); 539 err = set_phy_regs(phy, regs);
1166 msleep(50); 540 msleep(50);
1167 if (err) 541 if (err)
1168 return err; 542 return err;
1169 543
1170 phy->priv = edc_sr; 544 phy->priv = edc_sr;
1171 return 0; 545 return 0;
1172 } 546 }
1173 547
1174 /* 548 /*
1175 * Setup EDC and other parameters for operation with an TWINAX module. 549 * Setup EDC and other parameters for operation with an TWINAX module.
1176 */ 550 */
1177 static int ael2020_setup_twinax_edc(struct cphy *phy, int modtype) 551 static int ael2020_setup_twinax_edc(struct cphy *phy, int modtype)
1178 { 552 {
1179 /* set uC to 40MHz */ 553 /* set uC to 40MHz */
1180 static struct reg_val uCclock40MHz[] = { 554 static struct reg_val uCclock40MHz[] = {
1181 { MDIO_MMD_PMAPMD, 0xff28, 0xffff, 0x4001 }, 555 { MDIO_MMD_PMAPMD, 0xff28, 0xffff, 0x4001 },
1182 { MDIO_MMD_PMAPMD, 0xff2a, 0xffff, 0x0002 }, 556 { MDIO_MMD_PMAPMD, 0xff2a, 0xffff, 0x0002 },
1183 { 0, 0, 0, 0 } 557 { 0, 0, 0, 0 }
1184 }; 558 };
1185 559
1186 /* activate uC clock */ 560 /* activate uC clock */
1187 static struct reg_val uCclockActivate[] = { 561 static struct reg_val uCclockActivate[] = {
1188 { MDIO_MMD_PMAPMD, 0xd000, 0xffff, 0x5200 }, 562 { MDIO_MMD_PMAPMD, 0xd000, 0xffff, 0x5200 },
1189 { 0, 0, 0, 0 } 563 { 0, 0, 0, 0 }
1190 }; 564 };
1191 565
1192 /* set PC to start of SRAM and activate uC */ 566 /* set PC to start of SRAM and activate uC */
1193 static struct reg_val uCactivate[] = { 567 static struct reg_val uCactivate[] = {
1194 { MDIO_MMD_PMAPMD, 0xd080, 0xffff, 0x0100 }, 568 { MDIO_MMD_PMAPMD, 0xd080, 0xffff, 0x0100 },
1195 { MDIO_MMD_PMAPMD, 0xd092, 0xffff, 0x0000 }, 569 { MDIO_MMD_PMAPMD, 0xd092, 0xffff, 0x0000 },
1196 { 0, 0, 0, 0 } 570 { 0, 0, 0, 0 }
1197 }; 571 };
1198
1199 /* TWINAX EDC firmware */
1200 static u16 twinax_edc[] = {
1201 0xd800, 0x4009,
1202 0xd801, 0x2fff,
1203 0xd802, 0x300f,
1204 0xd803, 0x40aa,
1205 0xd804, 0x401c,
1206 0xd805, 0x401e,
1207 0xd806, 0x2ff4,
1208 0xd807, 0x3dc4,
1209 0xd808, 0x2035,
1210 0xd809, 0x3035,
1211 0xd80a, 0x6524,
1212 0xd80b, 0x2cb2,
1213 0xd80c, 0x3012,
1214 0xd80d, 0x1002,
1215 0xd80e, 0x26e2,
1216 0xd80f, 0x3022,
1217 0xd810, 0x1002,
1218 0xd811, 0x27d2,
1219 0xd812, 0x3022,
1220 0xd813, 0x1002,
1221 0xd814, 0x2822,
1222 0xd815, 0x3012,
1223 0xd816, 0x1002,
1224 0xd817, 0x2492,
1225 0xd818, 0x3022,
1226 0xd819, 0x1002,
1227 0xd81a, 0x2772,
1228 0xd81b, 0x3012,
1229 0xd81c, 0x1002,
1230 0xd81d, 0x23d2,
1231 0xd81e, 0x3022,
1232 0xd81f, 0x1002,
1233 0xd820, 0x22cd,
1234 0xd821, 0x301d,
1235 0xd822, 0x27f2,
1236 0xd823, 0x3022,
1237 0xd824, 0x1002,
1238 0xd825, 0x5553,
1239 0xd826, 0x0307,
1240 0xd827, 0x2522,
1241 0xd828, 0x3022,
1242 0xd829, 0x1002,
1243 0xd82a, 0x2142,
1244 0xd82b, 0x3012,
1245 0xd82c, 0x1002,
1246 0xd82d, 0x4016,
1247 0xd82e, 0x5e63,
1248 0xd82f, 0x0344,
1249 0xd830, 0x2142,
1250 0xd831, 0x3012,
1251 0xd832, 0x1002,
1252 0xd833, 0x400e,
1253 0xd834, 0x2522,
1254 0xd835, 0x3022,
1255 0xd836, 0x1002,
1256 0xd837, 0x2b52,
1257 0xd838, 0x3012,
1258 0xd839, 0x1002,
1259 0xd83a, 0x2742,
1260 0xd83b, 0x3022,
1261 0xd83c, 0x1002,
1262 0xd83d, 0x25e2,
1263 0xd83e, 0x3022,
1264 0xd83f, 0x1002,
1265 0xd840, 0x2fa4,
1266 0xd841, 0x3dc4,
1267 0xd842, 0x6624,
1268 0xd843, 0x414b,
1269 0xd844, 0x56b3,
1270 0xd845, 0x03c6,
1271 0xd846, 0x866b,
1272 0xd847, 0x400c,
1273 0xd848, 0x2712,
1274 0xd849, 0x3012,
1275 0xd84a, 0x1002,
1276 0xd84b, 0x2c4b,
1277 0xd84c, 0x309b,
1278 0xd84d, 0x56b3,
1279 0xd84e, 0x03c3,
1280 0xd84f, 0x866b,
1281 0xd850, 0x400c,
1282 0xd851, 0x2272,
1283 0xd852, 0x3022,
1284 0xd853, 0x1002,
1285 0xd854, 0x2742,
1286 0xd855, 0x3022,
1287 0xd856, 0x1002,
1288 0xd857, 0x25e2,
1289 0xd858, 0x3022,
1290 0xd859, 0x1002,
1291 0xd85a, 0x2fb4,
1292 0xd85b, 0x3dc4,
1293 0xd85c, 0x6624,
1294 0xd85d, 0x56b3,
1295 0xd85e, 0x03c3,
1296 0xd85f, 0x866b,
1297 0xd860, 0x401c,
1298 0xd861, 0x2c45,
1299 0xd862, 0x3095,
1300 0xd863, 0x5b53,
1301 0xd864, 0x2372,
1302 0xd865, 0x3012,
1303 0xd866, 0x13c2,
1304 0xd867, 0x5cc3,
1305 0xd868, 0x2712,
1306 0xd869, 0x3012,
1307 0xd86a, 0x1312,
1308 0xd86b, 0x2b52,
1309 0xd86c, 0x3012,
1310 0xd86d, 0x1002,
1311 0xd86e, 0x2742,
1312 0xd86f, 0x3022,
1313 0xd870, 0x1002,
1314 0xd871, 0x2582,
1315 0xd872, 0x3022,
1316 0xd873, 0x1002,
1317 0xd874, 0x2142,
1318 0xd875, 0x3012,
1319 0xd876, 0x1002,
1320 0xd877, 0x628f,
1321 0xd878, 0x2985,
1322 0xd879, 0x33a5,
1323 0xd87a, 0x25e2,
1324 0xd87b, 0x3022,
1325 0xd87c, 0x1002,
1326 0xd87d, 0x5653,
1327 0xd87e, 0x03d2,
1328 0xd87f, 0x401e,
1329 0xd880, 0x6f72,
1330 0xd881, 0x1002,
1331 0xd882, 0x628f,
1332 0xd883, 0x2304,
1333 0xd884, 0x3c84,
1334 0xd885, 0x6436,
1335 0xd886, 0xdff4,
1336 0xd887, 0x6436,
1337 0xd888, 0x2ff5,
1338 0xd889, 0x3005,
1339 0xd88a, 0x8656,
1340 0xd88b, 0xdfba,
1341 0xd88c, 0x56a3,
1342 0xd88d, 0xd05a,
1343 0xd88e, 0x2972,
1344 0xd88f, 0x3012,
1345 0xd890, 0x1392,
1346 0xd891, 0xd05a,
1347 0xd892, 0x56a3,
1348 0xd893, 0xdfba,
1349 0xd894, 0x0383,
1350 0xd895, 0x6f72,
1351 0xd896, 0x1002,
1352 0xd897, 0x2b45,
1353 0xd898, 0x3005,
1354 0xd899, 0x4178,
1355 0xd89a, 0x5653,
1356 0xd89b, 0x0384,
1357 0xd89c, 0x2a62,
1358 0xd89d, 0x3012,
1359 0xd89e, 0x1002,
1360 0xd89f, 0x2f05,
1361 0xd8a0, 0x3005,
1362 0xd8a1, 0x41c8,
1363 0xd8a2, 0x5653,
1364 0xd8a3, 0x0382,
1365 0xd8a4, 0x0002,
1366 0xd8a5, 0x4218,
1367 0xd8a6, 0x2474,
1368 0xd8a7, 0x3c84,
1369 0xd8a8, 0x6437,
1370 0xd8a9, 0xdff4,
1371 0xd8aa, 0x6437,
1372 0xd8ab, 0x2ff5,
1373 0xd8ac, 0x3c05,
1374 0xd8ad, 0x8757,
1375 0xd8ae, 0xb888,
1376 0xd8af, 0x9787,
1377 0xd8b0, 0xdff4,
1378 0xd8b1, 0x6724,
1379 0xd8b2, 0x866a,
1380 0xd8b3, 0x6f72,
1381 0xd8b4, 0x1002,
1382 0xd8b5, 0x2641,
1383 0xd8b6, 0x3021,
1384 0xd8b7, 0x1001,
1385 0xd8b8, 0xc620,
1386 0xd8b9, 0x0000,
1387 0xd8ba, 0xc621,
1388 0xd8bb, 0x0000,
1389 0xd8bc, 0xc622,
1390 0xd8bd, 0x00ce,
1391 0xd8be, 0xc623,
1392 0xd8bf, 0x007f,
1393 0xd8c0, 0xc624,
1394 0xd8c1, 0x0032,
1395 0xd8c2, 0xc625,
1396 0xd8c3, 0x0000,
1397 0xd8c4, 0xc627,
1398 0xd8c5, 0x0000,
1399 0xd8c6, 0xc628,
1400 0xd8c7, 0x0000,
1401 0xd8c8, 0xc62c,
1402 0xd8c9, 0x0000,
1403 0xd8ca, 0x0000,
1404 0xd8cb, 0x2641,
1405 0xd8cc, 0x3021,
1406 0xd8cd, 0x1001,
1407 0xd8ce, 0xc502,
1408 0xd8cf, 0x53ac,
1409 0xd8d0, 0xc503,
1410 0xd8d1, 0x2cd3,
1411 0xd8d2, 0xc600,
1412 0xd8d3, 0x2a6e,
1413 0xd8d4, 0xc601,
1414 0xd8d5, 0x2a2c,
1415 0xd8d6, 0xc605,
1416 0xd8d7, 0x5557,
1417 0xd8d8, 0xc60c,
1418 0xd8d9, 0x5400,
1419 0xd8da, 0xc710,
1420 0xd8db, 0x0700,
1421 0xd8dc, 0xc711,
1422 0xd8dd, 0x0f06,
1423 0xd8de, 0xc718,
1424 0xd8df, 0x0700,
1425 0xd8e0, 0xc719,
1426 0xd8e1, 0x0f06,
1427 0xd8e2, 0xc720,
1428 0xd8e3, 0x4700,
1429 0xd8e4, 0xc721,
1430 0xd8e5, 0x0f06,
1431 0xd8e6, 0xc728,
1432 0xd8e7, 0x0700,
1433 0xd8e8, 0xc729,
1434 0xd8e9, 0x1207,
1435 0xd8ea, 0xc801,
1436 0xd8eb, 0x7f50,
1437 0xd8ec, 0xc802,
1438 0xd8ed, 0x7760,
1439 0xd8ee, 0xc803,
1440 0xd8ef, 0x7fce,
1441 0xd8f0, 0xc804,
1442 0xd8f1, 0x520e,
1443 0xd8f2, 0xc805,
1444 0xd8f3, 0x5c11,
1445 0xd8f4, 0xc806,
1446 0xd8f5, 0x3c51,
1447 0xd8f6, 0xc807,
1448 0xd8f7, 0x4061,
1449 0xd8f8, 0xc808,
1450 0xd8f9, 0x49c1,
1451 0xd8fa, 0xc809,
1452 0xd8fb, 0x3840,
1453 0xd8fc, 0xc80a,
1454 0xd8fd, 0x0000,
1455 0xd8fe, 0xc821,
1456 0xd8ff, 0x0002,
1457 0xd900, 0xc822,
1458 0xd901, 0x0046,
1459 0xd902, 0xc844,
1460 0xd903, 0x182f,
1461 0xd904, 0xc013,
1462 0xd905, 0xf341,
1463 0xd906, 0xc084,
1464 0xd907, 0x0030,
1465 0xd908, 0xc904,
1466 0xd909, 0x1401,
1467 0xd90a, 0xcb0c,
1468 0xd90b, 0x0004,
1469 0xd90c, 0xcb0e,
1470 0xd90d, 0xa00a,
1471 0xd90e, 0xcb0f,
1472 0xd90f, 0xc0c0,
1473 0xd910, 0xcb10,
1474 0xd911, 0xc0c0,
1475 0xd912, 0xcb11,
1476 0xd913, 0x00a0,
1477 0xd914, 0xcb12,
1478 0xd915, 0x0007,
1479 0xd916, 0xc241,
1480 0xd917, 0xa000,
1481 0xd918, 0xc243,
1482 0xd919, 0x7fe0,
1483 0xd91a, 0xc604,
1484 0xd91b, 0x000e,
1485 0xd91c, 0xc609,
1486 0xd91d, 0x00f5,
1487 0xd91e, 0xc611,
1488 0xd91f, 0x000e,
1489 0xd920, 0xc660,
1490 0xd921, 0x9600,
1491 0xd922, 0xc687,
1492 0xd923, 0x0004,
1493 0xd924, 0xc60a,
1494 0xd925, 0x04f5,
1495 0xd926, 0x0000,
1496 0xd927, 0x2641,
1497 0xd928, 0x3021,
1498 0xd929, 0x1001,
1499 0xd92a, 0xc620,
1500 0xd92b, 0x14e5,
1501 0xd92c, 0xc621,
1502 0xd92d, 0xc53d,
1503 0xd92e, 0xc622,
1504 0xd92f, 0x3cbe,
1505 0xd930, 0xc623,
1506 0xd931, 0x4452,
1507 0xd932, 0xc624,
1508 0xd933, 0xc5c5,
1509 0xd934, 0xc625,
1510 0xd935, 0xe01e,
1511 0xd936, 0xc627,
1512 0xd937, 0x0000,
1513 0xd938, 0xc628,
1514 0xd939, 0x0000,
1515 0xd93a, 0xc62c,
1516 0xd93b, 0x0000,
1517 0xd93c, 0x0000,
1518 0xd93d, 0x2b84,
1519 0xd93e, 0x3c74,
1520 0xd93f, 0x6435,
1521 0xd940, 0xdff4,
1522 0xd941, 0x6435,
1523 0xd942, 0x2806,
1524 0xd943, 0x3006,
1525 0xd944, 0x8565,
1526 0xd945, 0x2b24,
1527 0xd946, 0x3c24,
1528 0xd947, 0x6436,
1529 0xd948, 0x1002,
1530 0xd949, 0x2b24,
1531 0xd94a, 0x3c24,
1532 0xd94b, 0x6436,
1533 0xd94c, 0x4045,
1534 0xd94d, 0x8656,
1535 0xd94e, 0x5663,
1536 0xd94f, 0x0302,
1537 0xd950, 0x401e,
1538 0xd951, 0x1002,
1539 0xd952, 0x2807,
1540 0xd953, 0x31a7,
1541 0xd954, 0x20c4,
1542 0xd955, 0x3c24,
1543 0xd956, 0x6724,
1544 0xd957, 0x1002,
1545 0xd958, 0x2807,
1546 0xd959, 0x3187,
1547 0xd95a, 0x20c4,
1548 0xd95b, 0x3c24,
1549 0xd95c, 0x6724,
1550 0xd95d, 0x1002,
1551 0xd95e, 0x24f4,
1552 0xd95f, 0x3c64,
1553 0xd960, 0x6436,
1554 0xd961, 0xdff4,
1555 0xd962, 0x6436,
1556 0xd963, 0x1002,
1557 0xd964, 0x2006,
1558 0xd965, 0x3d76,
1559 0xd966, 0xc161,
1560 0xd967, 0x6134,
1561 0xd968, 0x6135,
1562 0xd969, 0x5443,
1563 0xd96a, 0x0303,
1564 0xd96b, 0x6524,
1565 0xd96c, 0x00fb,
1566 0xd96d, 0x1002,
1567 0xd96e, 0x20d4,
1568 0xd96f, 0x3c24,
1569 0xd970, 0x2025,
1570 0xd971, 0x3005,
1571 0xd972, 0x6524,
1572 0xd973, 0x1002,
1573 0xd974, 0xd019,
1574 0xd975, 0x2104,
1575 0xd976, 0x3c24,
1576 0xd977, 0x2105,
1577 0xd978, 0x3805,
1578 0xd979, 0x6524,
1579 0xd97a, 0xdff4,
1580 0xd97b, 0x4005,
1581 0xd97c, 0x6524,
1582 0xd97d, 0x2e8d,
1583 0xd97e, 0x303d,
1584 0xd97f, 0x2408,
1585 0xd980, 0x35d8,
1586 0xd981, 0x5dd3,
1587 0xd982, 0x0307,
1588 0xd983, 0x8887,
1589 0xd984, 0x63a7,
1590 0xd985, 0x8887,
1591 0xd986, 0x63a7,
1592 0xd987, 0xdffd,
1593 0xd988, 0x00f9,
1594 0xd989, 0x1002,
1595 0xd98a, 0x0000,
1596 };
1597 int i, err; 572 int i, err;
1598 573
1599 /* set uC clock and activate it */ 574 /* set uC clock and activate it */
1600 err = set_phy_regs(phy, uCclock40MHz); 575 err = set_phy_regs(phy, uCclock40MHz);
1601 msleep(500); 576 msleep(500);
1602 if (err) 577 if (err)
1603 return err; 578 return err;
1604 err = set_phy_regs(phy, uCclockActivate); 579 err = set_phy_regs(phy, uCclockActivate);
1605 msleep(500); 580 msleep(500);
1606 if (err) 581 if (err)
1607 return err; 582 return err;
1608 583
1609 /* write TWINAX EDC firmware into PHY */ 584 if (phy->priv != edc_twinax)
1610 for (i = 0; i < ARRAY_SIZE(twinax_edc) && !err; i += 2) 585 err = t3_get_edc_fw(phy, EDC_TWX_AEL2020,
1611 err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, twinax_edc[i], 586 EDC_TWX_AEL2020_SIZE);
1612 twinax_edc[i + 1]); 587 if (err)
588 return err;
589
590 for (i = 0; i < EDC_TWX_AEL2020_SIZE / sizeof(u16) && !err; i += 2)
591 err = t3_mdio_write(phy, MDIO_MMD_PMAPMD,
592 phy->phy_cache[i],
593 phy->phy_cache[i + 1]);
1613 /* activate uC */ 594 /* activate uC */
1614 err = set_phy_regs(phy, uCactivate); 595 err = set_phy_regs(phy, uCactivate);
1615 if (!err) 596 if (!err)
1616 phy->priv = edc_twinax; 597 phy->priv = edc_twinax;
1617 return err; 598 return err;
1618 } 599 }
1619 600
1620 /* 601 /*
1621 * Return Module Type. 602 * Return Module Type.
1622 */ 603 */
1623 static int ael2020_get_module_type(struct cphy *phy, int delay_ms) 604 static int ael2020_get_module_type(struct cphy *phy, int delay_ms)
1624 { 605 {
1625 int v; 606 int v;
1626 unsigned int stat; 607 unsigned int stat;
1627 608
1628 v = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AEL2020_GPIO_STAT, &stat); 609 v = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AEL2020_GPIO_STAT, &stat);
1629 if (v) 610 if (v)
1630 return v; 611 return v;
1631 612
1632 if (stat & (0x1 << (AEL2020_GPIO_MODDET*4))) { 613 if (stat & (0x1 << (AEL2020_GPIO_MODDET*4))) {
1633 /* module absent */ 614 /* module absent */
1634 return phy_modtype_none; 615 return phy_modtype_none;
1635 } 616 }
1636 617
1637 return ael2xxx_get_module_type(phy, delay_ms); 618 return ael2xxx_get_module_type(phy, delay_ms);
1638 } 619 }
1639 620
1640 /* 621 /*
1641 * Enable PHY interrupts. We enable "Module Detection" interrupts (on any 622 * Enable PHY interrupts. We enable "Module Detection" interrupts (on any
1642 * state transition) and then generic Link Alarm Status Interrupt (LASI). 623 * state transition) and then generic Link Alarm Status Interrupt (LASI).
1643 */ 624 */
1644 static int ael2020_intr_enable(struct cphy *phy) 625 static int ael2020_intr_enable(struct cphy *phy)
1645 { 626 {
1646 struct reg_val regs[] = { 627 struct reg_val regs[] = {
1647 /* output Module's Loss Of Signal (LOS) to LED */ 628 /* output Module's Loss Of Signal (LOS) to LED */
1648 { MDIO_MMD_PMAPMD, AEL2020_GPIO_CFG+AEL2020_GPIO_LSTAT, 629 { MDIO_MMD_PMAPMD, AEL2020_GPIO_CFG+AEL2020_GPIO_LSTAT,
1649 0xffff, 0x4 }, 630 0xffff, 0x4 },
1650 { MDIO_MMD_PMAPMD, AEL2020_GPIO_CTRL, 631 { MDIO_MMD_PMAPMD, AEL2020_GPIO_CTRL,
1651 0xffff, 0x8 << (AEL2020_GPIO_LSTAT*4) }, 632 0xffff, 0x8 << (AEL2020_GPIO_LSTAT*4) },
1652 633
1653 /* enable module detect status change interrupts */ 634 /* enable module detect status change interrupts */
1654 { MDIO_MMD_PMAPMD, AEL2020_GPIO_CTRL, 635 { MDIO_MMD_PMAPMD, AEL2020_GPIO_CTRL,
1655 0xffff, 0x2 << (AEL2020_GPIO_MODDET*4) }, 636 0xffff, 0x2 << (AEL2020_GPIO_MODDET*4) },
1656 637
1657 /* end */ 638 /* end */
1658 { 0, 0, 0, 0 } 639 { 0, 0, 0, 0 }
1659 }; 640 };
1660 int err, link_ok = 0; 641 int err, link_ok = 0;
1661 642
1662 /* set up "link status" LED and enable module change interrupts */ 643 /* set up "link status" LED and enable module change interrupts */
1663 err = set_phy_regs(phy, regs); 644 err = set_phy_regs(phy, regs);
1664 if (err) 645 if (err)
1665 return err; 646 return err;
1666 647
1667 err = get_link_status_r(phy, &link_ok, NULL, NULL, NULL); 648 err = get_link_status_r(phy, &link_ok, NULL, NULL, NULL);
1668 if (err) 649 if (err)
1669 return err; 650 return err;
1670 if (link_ok) 651 if (link_ok)
1671 t3_link_changed(phy->adapter, 652 t3_link_changed(phy->adapter,
1672 phy2portid(phy)); 653 phy2portid(phy));
1673 654
1674 err = t3_phy_lasi_intr_enable(phy); 655 err = t3_phy_lasi_intr_enable(phy);
1675 if (err) 656 if (err)
1676 return err; 657 return err;
1677 658
1678 return 0; 659 return 0;
1679 } 660 }
1680 661
1681 /* 662 /*
1682 * Disable PHY interrupts. The mirror of the above ... 663 * Disable PHY interrupts. The mirror of the above ...
1683 */ 664 */
1684 static int ael2020_intr_disable(struct cphy *phy) 665 static int ael2020_intr_disable(struct cphy *phy)
1685 { 666 {
1686 struct reg_val regs[] = { 667 struct reg_val regs[] = {
1687 /* reset "link status" LED to "off" */ 668 /* reset "link status" LED to "off" */
1688 { MDIO_MMD_PMAPMD, AEL2020_GPIO_CTRL, 669 { MDIO_MMD_PMAPMD, AEL2020_GPIO_CTRL,
1689 0xffff, 0xb << (AEL2020_GPIO_LSTAT*4) }, 670 0xffff, 0xb << (AEL2020_GPIO_LSTAT*4) },
1690 671
1691 /* disable module detect status change interrupts */ 672 /* disable module detect status change interrupts */
1692 { MDIO_MMD_PMAPMD, AEL2020_GPIO_CTRL, 673 { MDIO_MMD_PMAPMD, AEL2020_GPIO_CTRL,
1693 0xffff, 0x1 << (AEL2020_GPIO_MODDET*4) }, 674 0xffff, 0x1 << (AEL2020_GPIO_MODDET*4) },
1694 675
1695 /* end */ 676 /* end */
1696 { 0, 0, 0, 0 } 677 { 0, 0, 0, 0 }
1697 }; 678 };
1698 int err; 679 int err;
1699 680
1700 /* turn off "link status" LED and disable module change interrupts */ 681 /* turn off "link status" LED and disable module change interrupts */
1701 err = set_phy_regs(phy, regs); 682 err = set_phy_regs(phy, regs);
1702 if (err) 683 if (err)
1703 return err; 684 return err;
1704 685
1705 return t3_phy_lasi_intr_disable(phy); 686 return t3_phy_lasi_intr_disable(phy);
1706 } 687 }
1707 688
1708 /* 689 /*
1709 * Clear PHY interrupt state. 690 * Clear PHY interrupt state.
1710 */ 691 */
1711 static int ael2020_intr_clear(struct cphy *phy) 692 static int ael2020_intr_clear(struct cphy *phy)
1712 { 693 {
1713 /* 694 /*
1714 * The GPIO Interrupt register on the AEL2020 is a "Latching High" 695 * The GPIO Interrupt register on the AEL2020 is a "Latching High"
1715 * (LH) register which is cleared to the current state when it's read. 696 * (LH) register which is cleared to the current state when it's read.
1716 * Thus, we simply read the register and discard the result. 697 * Thus, we simply read the register and discard the result.
1717 */ 698 */
1718 unsigned int stat; 699 unsigned int stat;
1719 int err = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AEL2020_GPIO_INTR, &stat); 700 int err = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AEL2020_GPIO_INTR, &stat);
1720 return err ? err : t3_phy_lasi_intr_clear(phy); 701 return err ? err : t3_phy_lasi_intr_clear(phy);
1721 } 702 }
1722 703
1723 static struct reg_val ael2020_reset_regs[] = { 704 static struct reg_val ael2020_reset_regs[] = {
1724 /* Erratum #2: CDRLOL asserted, causing PMA link down status */ 705 /* Erratum #2: CDRLOL asserted, causing PMA link down status */
1725 { MDIO_MMD_PMAPMD, 0xc003, 0xffff, 0x3101 }, 706 { MDIO_MMD_PMAPMD, 0xc003, 0xffff, 0x3101 },
1726 707
1727 /* force XAUI to send LF when RX_LOS is asserted */ 708 /* force XAUI to send LF when RX_LOS is asserted */
1728 { MDIO_MMD_PMAPMD, 0xcd40, 0xffff, 0x0001 }, 709 { MDIO_MMD_PMAPMD, 0xcd40, 0xffff, 0x0001 },
1729 710
1730 /* allow writes to transceiver module EEPROM on i2c bus */ 711 /* allow writes to transceiver module EEPROM on i2c bus */
1731 { MDIO_MMD_PMAPMD, 0xff02, 0xffff, 0x0023 }, 712 { MDIO_MMD_PMAPMD, 0xff02, 0xffff, 0x0023 },
1732 { MDIO_MMD_PMAPMD, 0xff03, 0xffff, 0x0000 }, 713 { MDIO_MMD_PMAPMD, 0xff03, 0xffff, 0x0000 },
1733 { MDIO_MMD_PMAPMD, 0xff04, 0xffff, 0x0000 }, 714 { MDIO_MMD_PMAPMD, 0xff04, 0xffff, 0x0000 },
1734 715
1735 /* end */ 716 /* end */
1736 { 0, 0, 0, 0 } 717 { 0, 0, 0, 0 }
1737 }; 718 };
1738 /* 719 /*
1739 * Reset the PHY and put it into a canonical operating state. 720 * Reset the PHY and put it into a canonical operating state.
1740 */ 721 */
1741 static int ael2020_reset(struct cphy *phy, int wait) 722 static int ael2020_reset(struct cphy *phy, int wait)
1742 { 723 {
1743 int err; 724 int err;
1744 unsigned int lasi_ctrl; 725 unsigned int lasi_ctrl;
1745 726
1746 /* grab current interrupt state */ 727 /* grab current interrupt state */
1747 err = t3_mdio_read(phy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_CTRL, 728 err = t3_mdio_read(phy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_CTRL,
1748 &lasi_ctrl); 729 &lasi_ctrl);
1749 if (err) 730 if (err)
1750 return err; 731 return err;
1751 732
1752 err = t3_phy_reset(phy, MDIO_MMD_PMAPMD, 125); 733 err = t3_phy_reset(phy, MDIO_MMD_PMAPMD, 125);
1753 if (err) 734 if (err)
1754 return err; 735 return err;
1755 msleep(100); 736 msleep(100);
1756 737
1757 /* basic initialization for all module types */ 738 /* basic initialization for all module types */
1758 phy->priv = edc_none; 739 phy->priv = edc_none;
1759 err = set_phy_regs(phy, ael2020_reset_regs); 740 err = set_phy_regs(phy, ael2020_reset_regs);
1760 if (err) 741 if (err)
1761 return err; 742 return err;
1762 743
1763 /* determine module type and perform appropriate initialization */ 744 /* determine module type and perform appropriate initialization */
1764 err = ael2020_get_module_type(phy, 0); 745 err = ael2020_get_module_type(phy, 0);
1765 if (err < 0) 746 if (err < 0)
1766 return err; 747 return err;
1767 phy->modtype = (u8)err; 748 phy->modtype = (u8)err;
1768 if (err == phy_modtype_twinax || err == phy_modtype_twinax_long) 749 if (err == phy_modtype_twinax || err == phy_modtype_twinax_long)
1769 err = ael2020_setup_twinax_edc(phy, err); 750 err = ael2020_setup_twinax_edc(phy, err);
1770 else 751 else
1771 err = ael2020_setup_sr_edc(phy); 752 err = ael2020_setup_sr_edc(phy);
1772 if (err) 753 if (err)
1773 return err; 754 return err;
1774 755
1775 /* reset wipes out interrupts, reenable them if they were on */ 756 /* reset wipes out interrupts, reenable them if they were on */
1776 if (lasi_ctrl & 1) 757 if (lasi_ctrl & 1)
1777 err = ael2005_intr_enable(phy); 758 err = ael2005_intr_enable(phy);
1778 return err; 759 return err;
1779 } 760 }
1780 761
1781 /* 762 /*
1782 * Handle a PHY interrupt. 763 * Handle a PHY interrupt.
1783 */ 764 */
1784 static int ael2020_intr_handler(struct cphy *phy) 765 static int ael2020_intr_handler(struct cphy *phy)
1785 { 766 {
1786 unsigned int stat; 767 unsigned int stat;
1787 int ret, edc_needed, cause = 0; 768 int ret, edc_needed, cause = 0;
1788 769
1789 ret = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AEL2020_GPIO_INTR, &stat); 770 ret = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AEL2020_GPIO_INTR, &stat);
1790 if (ret) 771 if (ret)
1791 return ret; 772 return ret;
1792 773
1793 if (stat & (0x1 << AEL2020_GPIO_MODDET)) { 774 if (stat & (0x1 << AEL2020_GPIO_MODDET)) {
1794 /* modules have max 300 ms init time after hot plug */ 775 /* modules have max 300 ms init time after hot plug */
1795 ret = ael2020_get_module_type(phy, 300); 776 ret = ael2020_get_module_type(phy, 300);
1796 if (ret < 0) 777 if (ret < 0)
1797 return ret; 778 return ret;
1798 779
1799 phy->modtype = (u8)ret; 780 phy->modtype = (u8)ret;
1800 if (ret == phy_modtype_none) 781 if (ret == phy_modtype_none)
1801 edc_needed = phy->priv; /* on unplug retain EDC */ 782 edc_needed = phy->priv; /* on unplug retain EDC */
1802 else if (ret == phy_modtype_twinax || 783 else if (ret == phy_modtype_twinax ||
1803 ret == phy_modtype_twinax_long) 784 ret == phy_modtype_twinax_long)
1804 edc_needed = edc_twinax; 785 edc_needed = edc_twinax;
1805 else 786 else
1806 edc_needed = edc_sr; 787 edc_needed = edc_sr;
1807 788
1808 if (edc_needed != phy->priv) { 789 if (edc_needed != phy->priv) {
1809 ret = ael2020_reset(phy, 0); 790 ret = ael2020_reset(phy, 0);
1810 return ret ? ret : cphy_cause_module_change; 791 return ret ? ret : cphy_cause_module_change;
1811 } 792 }
1812 cause = cphy_cause_module_change; 793 cause = cphy_cause_module_change;
1813 } 794 }
1814 795
1815 ret = t3_phy_lasi_intr_handler(phy); 796 ret = t3_phy_lasi_intr_handler(phy);
1816 if (ret < 0) 797 if (ret < 0)
1817 return ret; 798 return ret;
1818 799
1819 ret |= cause; 800 ret |= cause;
1820 return ret ? ret : cphy_cause_link_change; 801 return ret ? ret : cphy_cause_link_change;
1821 } 802 }
1822 803
1823 static struct cphy_ops ael2020_ops = { 804 static struct cphy_ops ael2020_ops = {
1824 .reset = ael2020_reset, 805 .reset = ael2020_reset,
1825 .intr_enable = ael2020_intr_enable, 806 .intr_enable = ael2020_intr_enable,
1826 .intr_disable = ael2020_intr_disable, 807 .intr_disable = ael2020_intr_disable,
1827 .intr_clear = ael2020_intr_clear, 808 .intr_clear = ael2020_intr_clear,
1828 .intr_handler = ael2020_intr_handler, 809 .intr_handler = ael2020_intr_handler,
1829 .get_link_status = get_link_status_r, 810 .get_link_status = get_link_status_r,
1830 .power_down = ael1002_power_down, 811 .power_down = ael1002_power_down,
1831 .mmds = MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS | MDIO_DEVS_PHYXS, 812 .mmds = MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS | MDIO_DEVS_PHYXS,
1832 }; 813 };
1833 814
1834 int t3_ael2020_phy_prep(struct cphy *phy, struct adapter *adapter, int phy_addr, 815 int t3_ael2020_phy_prep(struct cphy *phy, struct adapter *adapter, int phy_addr,
1835 const struct mdio_ops *mdio_ops) 816 const struct mdio_ops *mdio_ops)
1836 { 817 {
1837 int err; 818 int err;
1838 819
1839 cphy_init(phy, adapter, phy_addr, &ael2020_ops, mdio_ops, 820 cphy_init(phy, adapter, phy_addr, &ael2020_ops, mdio_ops,
1840 SUPPORTED_10000baseT_Full | SUPPORTED_AUI | SUPPORTED_FIBRE | 821 SUPPORTED_10000baseT_Full | SUPPORTED_AUI | SUPPORTED_FIBRE |
1841 SUPPORTED_IRQ, "10GBASE-R"); 822 SUPPORTED_IRQ, "10GBASE-R");
1842 msleep(125); 823 msleep(125);
1843 824
1844 err = set_phy_regs(phy, ael2020_reset_regs); 825 err = set_phy_regs(phy, ael2020_reset_regs);
1845 if (err) 826 if (err)
1846 return err; 827 return err;
1847 return 0; 828 return 0;
1848 } 829 }
1849 830
1850 /* 831 /*
1851 * Get link status for a 10GBASE-X device. 832 * Get link status for a 10GBASE-X device.
1852 */ 833 */
1853 static int get_link_status_x(struct cphy *phy, int *link_ok, int *speed, 834 static int get_link_status_x(struct cphy *phy, int *link_ok, int *speed,
1854 int *duplex, int *fc) 835 int *duplex, int *fc)
1855 { 836 {
1856 if (link_ok) { 837 if (link_ok) {
1857 unsigned int stat0, stat1, stat2; 838 unsigned int stat0, stat1, stat2;
1858 int err = t3_mdio_read(phy, MDIO_MMD_PMAPMD, 839 int err = t3_mdio_read(phy, MDIO_MMD_PMAPMD,
1859 MDIO_PMA_RXDET, &stat0); 840 MDIO_PMA_RXDET, &stat0);
1860 841
1861 if (!err) 842 if (!err)
1862 err = t3_mdio_read(phy, MDIO_MMD_PCS, 843 err = t3_mdio_read(phy, MDIO_MMD_PCS,
1863 MDIO_PCS_10GBX_STAT1, &stat1); 844 MDIO_PCS_10GBX_STAT1, &stat1);
1864 if (!err) 845 if (!err)
1865 err = t3_mdio_read(phy, MDIO_MMD_PHYXS, 846 err = t3_mdio_read(phy, MDIO_MMD_PHYXS,
1866 MDIO_PHYXS_LNSTAT, &stat2); 847 MDIO_PHYXS_LNSTAT, &stat2);
1867 if (err) 848 if (err)
1868 return err; 849 return err;
1869 *link_ok = (stat0 & (stat1 >> 12) & (stat2 >> 12)) & 1; 850 *link_ok = (stat0 & (stat1 >> 12) & (stat2 >> 12)) & 1;
1870 } 851 }
1871 if (speed) 852 if (speed)
1872 *speed = SPEED_10000; 853 *speed = SPEED_10000;
1873 if (duplex) 854 if (duplex)
1874 *duplex = DUPLEX_FULL; 855 *duplex = DUPLEX_FULL;
1875 return 0; 856 return 0;
1876 } 857 }
1877 858
1878 static struct cphy_ops qt2045_ops = { 859 static struct cphy_ops qt2045_ops = {
1879 .reset = ael1006_reset, 860 .reset = ael1006_reset,
1880 .intr_enable = t3_phy_lasi_intr_enable, 861 .intr_enable = t3_phy_lasi_intr_enable,
1881 .intr_disable = t3_phy_lasi_intr_disable, 862 .intr_disable = t3_phy_lasi_intr_disable,
1882 .intr_clear = t3_phy_lasi_intr_clear, 863 .intr_clear = t3_phy_lasi_intr_clear,
1883 .intr_handler = t3_phy_lasi_intr_handler, 864 .intr_handler = t3_phy_lasi_intr_handler,
1884 .get_link_status = get_link_status_x, 865 .get_link_status = get_link_status_x,
1885 .power_down = ael1002_power_down, 866 .power_down = ael1002_power_down,
1886 .mmds = MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS | MDIO_DEVS_PHYXS, 867 .mmds = MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS | MDIO_DEVS_PHYXS,
1887 }; 868 };
1888 869
1889 int t3_qt2045_phy_prep(struct cphy *phy, struct adapter *adapter, 870 int t3_qt2045_phy_prep(struct cphy *phy, struct adapter *adapter,
1890 int phy_addr, const struct mdio_ops *mdio_ops) 871 int phy_addr, const struct mdio_ops *mdio_ops)
1891 { 872 {
1892 unsigned int stat; 873 unsigned int stat;
1893 874
1894 cphy_init(phy, adapter, phy_addr, &qt2045_ops, mdio_ops, 875 cphy_init(phy, adapter, phy_addr, &qt2045_ops, mdio_ops,
1895 SUPPORTED_10000baseT_Full | SUPPORTED_AUI | SUPPORTED_TP, 876 SUPPORTED_10000baseT_Full | SUPPORTED_AUI | SUPPORTED_TP,
1896 "10GBASE-CX4"); 877 "10GBASE-CX4");
1897 878
1898 /* 879 /*
1899 * Some cards where the PHY is supposed to be at address 0 actually 880 * Some cards where the PHY is supposed to be at address 0 actually
1900 * have it at 1. 881 * have it at 1.
1901 */ 882 */
1902 if (!phy_addr && 883 if (!phy_addr &&
1903 !t3_mdio_read(phy, MDIO_MMD_PMAPMD, MDIO_STAT1, &stat) && 884 !t3_mdio_read(phy, MDIO_MMD_PMAPMD, MDIO_STAT1, &stat) &&
1904 stat == 0xffff) 885 stat == 0xffff)
1905 phy->mdio.prtad = 1; 886 phy->mdio.prtad = 1;
1906 return 0; 887 return 0;
1907 } 888 }
1908 889
1909 static int xaui_direct_reset(struct cphy *phy, int wait) 890 static int xaui_direct_reset(struct cphy *phy, int wait)
1910 { 891 {
1911 return 0; 892 return 0;
1912 } 893 }
1913 894
1914 static int xaui_direct_get_link_status(struct cphy *phy, int *link_ok, 895 static int xaui_direct_get_link_status(struct cphy *phy, int *link_ok,
1915 int *speed, int *duplex, int *fc) 896 int *speed, int *duplex, int *fc)
1916 { 897 {
1917 if (link_ok) { 898 if (link_ok) {
1918 unsigned int status; 899 unsigned int status;
1919 int prtad = phy->mdio.prtad; 900 int prtad = phy->mdio.prtad;
1920 901
1921 status = t3_read_reg(phy->adapter, 902 status = t3_read_reg(phy->adapter,
1922 XGM_REG(A_XGM_SERDES_STAT0, prtad)) | 903 XGM_REG(A_XGM_SERDES_STAT0, prtad)) |
1923 t3_read_reg(phy->adapter, 904 t3_read_reg(phy->adapter,
1924 XGM_REG(A_XGM_SERDES_STAT1, prtad)) | 905 XGM_REG(A_XGM_SERDES_STAT1, prtad)) |
1925 t3_read_reg(phy->adapter, 906 t3_read_reg(phy->adapter,
1926 XGM_REG(A_XGM_SERDES_STAT2, prtad)) | 907 XGM_REG(A_XGM_SERDES_STAT2, prtad)) |
1927 t3_read_reg(phy->adapter, 908 t3_read_reg(phy->adapter,
1928 XGM_REG(A_XGM_SERDES_STAT3, prtad)); 909 XGM_REG(A_XGM_SERDES_STAT3, prtad));
1929 *link_ok = !(status & F_LOWSIG0); 910 *link_ok = !(status & F_LOWSIG0);
1930 } 911 }
1931 if (speed) 912 if (speed)
1932 *speed = SPEED_10000; 913 *speed = SPEED_10000;
1933 if (duplex) 914 if (duplex)
1934 *duplex = DUPLEX_FULL; 915 *duplex = DUPLEX_FULL;
1935 return 0; 916 return 0;
1936 } 917 }
1937 918
1938 static int xaui_direct_power_down(struct cphy *phy, int enable) 919 static int xaui_direct_power_down(struct cphy *phy, int enable)
1939 { 920 {
1940 return 0; 921 return 0;
1941 } 922 }
drivers/net/cxgb3/common.h
Diff comments   View file @ 2e8c07c
1 /* 1 /*
2 * Copyright (c) 2005-2008 Chelsio, Inc. All rights reserved. 2 * Copyright (c) 2005-2008 Chelsio, Inc. All rights reserved.
3 * 3 *
4 * This software is available to you under a choice of one of two 4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU 5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file 6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the 7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below: 8 * OpenIB.org BSD license below:
9 * 9 *
10 * Redistribution and use in source and binary forms, with or 10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following 11 * without modification, are permitted provided that the following
12 * conditions are met: 12 * conditions are met:
13 * 13 *
14 * - Redistributions of source code must retain the above 14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following 15 * copyright notice, this list of conditions and the following
16 * disclaimer. 16 * disclaimer.
17 * 17 *
18 * - Redistributions in binary form must reproduce the above 18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following 19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials 20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution. 21 * provided with the distribution.
22 * 22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE. 30 * SOFTWARE.
31 */ 31 */
32 #ifndef __CHELSIO_COMMON_H 32 #ifndef __CHELSIO_COMMON_H
33 #define __CHELSIO_COMMON_H 33 #define __CHELSIO_COMMON_H
34 34
35 #include <linux/kernel.h> 35 #include <linux/kernel.h>
36 #include <linux/types.h> 36 #include <linux/types.h>
37 #include <linux/ctype.h> 37 #include <linux/ctype.h>
38 #include <linux/delay.h> 38 #include <linux/delay.h>
39 #include <linux/init.h> 39 #include <linux/init.h>
40 #include <linux/netdevice.h> 40 #include <linux/netdevice.h>
41 #include <linux/ethtool.h> 41 #include <linux/ethtool.h>
42 #include <linux/mdio.h> 42 #include <linux/mdio.h>
43 #include "version.h" 43 #include "version.h"
44 44
45 #define CH_ERR(adap, fmt, ...) dev_err(&adap->pdev->dev, fmt, ## __VA_ARGS__) 45 #define CH_ERR(adap, fmt, ...) dev_err(&adap->pdev->dev, fmt, ## __VA_ARGS__)
46 #define CH_WARN(adap, fmt, ...) dev_warn(&adap->pdev->dev, fmt, ## __VA_ARGS__) 46 #define CH_WARN(adap, fmt, ...) dev_warn(&adap->pdev->dev, fmt, ## __VA_ARGS__)
47 #define CH_ALERT(adap, fmt, ...) \ 47 #define CH_ALERT(adap, fmt, ...) \
48 dev_printk(KERN_ALERT, &adap->pdev->dev, fmt, ## __VA_ARGS__) 48 dev_printk(KERN_ALERT, &adap->pdev->dev, fmt, ## __VA_ARGS__)
49 49
50 /* 50 /*
51 * More powerful macro that selectively prints messages based on msg_enable. 51 * More powerful macro that selectively prints messages based on msg_enable.
52 * For info and debugging messages. 52 * For info and debugging messages.
53 */ 53 */
54 #define CH_MSG(adapter, level, category, fmt, ...) do { \ 54 #define CH_MSG(adapter, level, category, fmt, ...) do { \
55 if ((adapter)->msg_enable & NETIF_MSG_##category) \ 55 if ((adapter)->msg_enable & NETIF_MSG_##category) \
56 dev_printk(KERN_##level, &adapter->pdev->dev, fmt, \ 56 dev_printk(KERN_##level, &adapter->pdev->dev, fmt, \
57 ## __VA_ARGS__); \ 57 ## __VA_ARGS__); \
58 } while (0) 58 } while (0)
59 59
60 #ifdef DEBUG 60 #ifdef DEBUG
61 # define CH_DBG(adapter, category, fmt, ...) \ 61 # define CH_DBG(adapter, category, fmt, ...) \
62 CH_MSG(adapter, DEBUG, category, fmt, ## __VA_ARGS__) 62 CH_MSG(adapter, DEBUG, category, fmt, ## __VA_ARGS__)
63 #else 63 #else
64 # define CH_DBG(adapter, category, fmt, ...) 64 # define CH_DBG(adapter, category, fmt, ...)
65 #endif 65 #endif
66 66
67 /* Additional NETIF_MSG_* categories */ 67 /* Additional NETIF_MSG_* categories */
68 #define NETIF_MSG_MMIO 0x8000000 68 #define NETIF_MSG_MMIO 0x8000000
69 69
70 struct t3_rx_mode { 70 struct t3_rx_mode {
71 struct net_device *dev; 71 struct net_device *dev;
72 struct dev_mc_list *mclist; 72 struct dev_mc_list *mclist;
73 unsigned int idx; 73 unsigned int idx;
74 }; 74 };
75 75
76 static inline void init_rx_mode(struct t3_rx_mode *p, struct net_device *dev, 76 static inline void init_rx_mode(struct t3_rx_mode *p, struct net_device *dev,
77 struct dev_mc_list *mclist) 77 struct dev_mc_list *mclist)
78 { 78 {
79 p->dev = dev; 79 p->dev = dev;
80 p->mclist = mclist; 80 p->mclist = mclist;
81 p->idx = 0; 81 p->idx = 0;
82 } 82 }
83 83
84 static inline u8 *t3_get_next_mcaddr(struct t3_rx_mode *rm) 84 static inline u8 *t3_get_next_mcaddr(struct t3_rx_mode *rm)
85 { 85 {
86 u8 *addr = NULL; 86 u8 *addr = NULL;
87 87
88 if (rm->mclist && rm->idx < rm->dev->mc_count) { 88 if (rm->mclist && rm->idx < rm->dev->mc_count) {
89 addr = rm->mclist->dmi_addr; 89 addr = rm->mclist->dmi_addr;
90 rm->mclist = rm->mclist->next; 90 rm->mclist = rm->mclist->next;
91 rm->idx++; 91 rm->idx++;
92 } 92 }
93 return addr; 93 return addr;
94 } 94 }
95 95
96 enum { 96 enum {
97 MAX_NPORTS = 2, /* max # of ports */ 97 MAX_NPORTS = 2, /* max # of ports */
98 MAX_FRAME_SIZE = 10240, /* max MAC frame size, including header + FCS */ 98 MAX_FRAME_SIZE = 10240, /* max MAC frame size, including header + FCS */
99 EEPROMSIZE = 8192, /* Serial EEPROM size */ 99 EEPROMSIZE = 8192, /* Serial EEPROM size */
100 SERNUM_LEN = 16, /* Serial # length */ 100 SERNUM_LEN = 16, /* Serial # length */
101 RSS_TABLE_SIZE = 64, /* size of RSS lookup and mapping tables */ 101 RSS_TABLE_SIZE = 64, /* size of RSS lookup and mapping tables */
102 TCB_SIZE = 128, /* TCB size */ 102 TCB_SIZE = 128, /* TCB size */
103 NMTUS = 16, /* size of MTU table */ 103 NMTUS = 16, /* size of MTU table */
104 NCCTRL_WIN = 32, /* # of congestion control windows */ 104 NCCTRL_WIN = 32, /* # of congestion control windows */
105 PROTO_SRAM_LINES = 128, /* size of TP sram */ 105 PROTO_SRAM_LINES = 128, /* size of TP sram */
106 }; 106 };
107 107
108 #define MAX_RX_COALESCING_LEN 12288U 108 #define MAX_RX_COALESCING_LEN 12288U
109 109
110 enum { 110 enum {
111 PAUSE_RX = 1 << 0, 111 PAUSE_RX = 1 << 0,
112 PAUSE_TX = 1 << 1, 112 PAUSE_TX = 1 << 1,
113 PAUSE_AUTONEG = 1 << 2 113 PAUSE_AUTONEG = 1 << 2
114 }; 114 };
115 115
116 enum { 116 enum {
117 SUPPORTED_IRQ = 1 << 24 117 SUPPORTED_IRQ = 1 << 24
118 }; 118 };
119 119
120 enum { /* adapter interrupt-maintained statistics */ 120 enum { /* adapter interrupt-maintained statistics */
121 STAT_ULP_CH0_PBL_OOB, 121 STAT_ULP_CH0_PBL_OOB,
122 STAT_ULP_CH1_PBL_OOB, 122 STAT_ULP_CH1_PBL_OOB,
123 STAT_PCI_CORR_ECC, 123 STAT_PCI_CORR_ECC,
124 124
125 IRQ_NUM_STATS /* keep last */ 125 IRQ_NUM_STATS /* keep last */
126 }; 126 };
127 127
128 enum { 128 enum {
129 TP_VERSION_MAJOR = 1, 129 TP_VERSION_MAJOR = 1,
130 TP_VERSION_MINOR = 1, 130 TP_VERSION_MINOR = 1,
131 TP_VERSION_MICRO = 0 131 TP_VERSION_MICRO = 0
132 }; 132 };
133 133
134 #define S_TP_VERSION_MAJOR 16 134 #define S_TP_VERSION_MAJOR 16
135 #define M_TP_VERSION_MAJOR 0xFF 135 #define M_TP_VERSION_MAJOR 0xFF
136 #define V_TP_VERSION_MAJOR(x) ((x) << S_TP_VERSION_MAJOR) 136 #define V_TP_VERSION_MAJOR(x) ((x) << S_TP_VERSION_MAJOR)
137 #define G_TP_VERSION_MAJOR(x) \ 137 #define G_TP_VERSION_MAJOR(x) \
138 (((x) >> S_TP_VERSION_MAJOR) & M_TP_VERSION_MAJOR) 138 (((x) >> S_TP_VERSION_MAJOR) & M_TP_VERSION_MAJOR)
139 139
140 #define S_TP_VERSION_MINOR 8 140 #define S_TP_VERSION_MINOR 8
141 #define M_TP_VERSION_MINOR 0xFF 141 #define M_TP_VERSION_MINOR 0xFF
142 #define V_TP_VERSION_MINOR(x) ((x) << S_TP_VERSION_MINOR) 142 #define V_TP_VERSION_MINOR(x) ((x) << S_TP_VERSION_MINOR)
143 #define G_TP_VERSION_MINOR(x) \ 143 #define G_TP_VERSION_MINOR(x) \
144 (((x) >> S_TP_VERSION_MINOR) & M_TP_VERSION_MINOR) 144 (((x) >> S_TP_VERSION_MINOR) & M_TP_VERSION_MINOR)
145 145
146 #define S_TP_VERSION_MICRO 0 146 #define S_TP_VERSION_MICRO 0
147 #define M_TP_VERSION_MICRO 0xFF 147 #define M_TP_VERSION_MICRO 0xFF
148 #define V_TP_VERSION_MICRO(x) ((x) << S_TP_VERSION_MICRO) 148 #define V_TP_VERSION_MICRO(x) ((x) << S_TP_VERSION_MICRO)
149 #define G_TP_VERSION_MICRO(x) \ 149 #define G_TP_VERSION_MICRO(x) \
150 (((x) >> S_TP_VERSION_MICRO) & M_TP_VERSION_MICRO) 150 (((x) >> S_TP_VERSION_MICRO) & M_TP_VERSION_MICRO)
151 151
152 enum { 152 enum {
153 SGE_QSETS = 8, /* # of SGE Tx/Rx/RspQ sets */ 153 SGE_QSETS = 8, /* # of SGE Tx/Rx/RspQ sets */
154 SGE_RXQ_PER_SET = 2, /* # of Rx queues per set */ 154 SGE_RXQ_PER_SET = 2, /* # of Rx queues per set */
155 SGE_TXQ_PER_SET = 3 /* # of Tx queues per set */ 155 SGE_TXQ_PER_SET = 3 /* # of Tx queues per set */
156 }; 156 };
157 157
158 enum sge_context_type { /* SGE egress context types */ 158 enum sge_context_type { /* SGE egress context types */
159 SGE_CNTXT_RDMA = 0, 159 SGE_CNTXT_RDMA = 0,
160 SGE_CNTXT_ETH = 2, 160 SGE_CNTXT_ETH = 2,
161 SGE_CNTXT_OFLD = 4, 161 SGE_CNTXT_OFLD = 4,
162 SGE_CNTXT_CTRL = 5 162 SGE_CNTXT_CTRL = 5
163 }; 163 };
164 164
165 enum { 165 enum {
166 AN_PKT_SIZE = 32, /* async notification packet size */ 166 AN_PKT_SIZE = 32, /* async notification packet size */
167 IMMED_PKT_SIZE = 48 /* packet size for immediate data */ 167 IMMED_PKT_SIZE = 48 /* packet size for immediate data */
168 }; 168 };
169 169
170 struct sg_ent { /* SGE scatter/gather entry */ 170 struct sg_ent { /* SGE scatter/gather entry */
171 __be32 len[2]; 171 __be32 len[2];
172 __be64 addr[2]; 172 __be64 addr[2];
173 }; 173 };
174 174
175 #ifndef SGE_NUM_GENBITS 175 #ifndef SGE_NUM_GENBITS
176 /* Must be 1 or 2 */ 176 /* Must be 1 or 2 */
177 # define SGE_NUM_GENBITS 2 177 # define SGE_NUM_GENBITS 2
178 #endif 178 #endif
179 179
180 #define TX_DESC_FLITS 16U 180 #define TX_DESC_FLITS 16U
181 #define WR_FLITS (TX_DESC_FLITS + 1 - SGE_NUM_GENBITS) 181 #define WR_FLITS (TX_DESC_FLITS + 1 - SGE_NUM_GENBITS)
182 182
183 struct cphy; 183 struct cphy;
184 struct adapter; 184 struct adapter;
185 185
186 struct mdio_ops { 186 struct mdio_ops {
187 int (*read)(struct net_device *dev, int phy_addr, int mmd_addr, 187 int (*read)(struct net_device *dev, int phy_addr, int mmd_addr,
188 u16 reg_addr); 188 u16 reg_addr);
189 int (*write)(struct net_device *dev, int phy_addr, int mmd_addr, 189 int (*write)(struct net_device *dev, int phy_addr, int mmd_addr,
190 u16 reg_addr, u16 val); 190 u16 reg_addr, u16 val);
191 unsigned mode_support; 191 unsigned mode_support;
192 }; 192 };
193 193
194 struct adapter_info { 194 struct adapter_info {
195 unsigned char nports0; /* # of ports on channel 0 */ 195 unsigned char nports0; /* # of ports on channel 0 */
196 unsigned char nports1; /* # of ports on channel 1 */ 196 unsigned char nports1; /* # of ports on channel 1 */
197 unsigned char phy_base_addr; /* MDIO PHY base address */ 197 unsigned char phy_base_addr; /* MDIO PHY base address */
198 unsigned int gpio_out; /* GPIO output settings */ 198 unsigned int gpio_out; /* GPIO output settings */
199 unsigned char gpio_intr[MAX_NPORTS]; /* GPIO PHY IRQ pins */ 199 unsigned char gpio_intr[MAX_NPORTS]; /* GPIO PHY IRQ pins */
200 unsigned long caps; /* adapter capabilities */ 200 unsigned long caps; /* adapter capabilities */
201 const struct mdio_ops *mdio_ops; /* MDIO operations */ 201 const struct mdio_ops *mdio_ops; /* MDIO operations */
202 const char *desc; /* product description */ 202 const char *desc; /* product description */
203 }; 203 };
204 204
205 struct mc5_stats { 205 struct mc5_stats {
206 unsigned long parity_err; 206 unsigned long parity_err;
207 unsigned long active_rgn_full; 207 unsigned long active_rgn_full;
208 unsigned long nfa_srch_err; 208 unsigned long nfa_srch_err;
209 unsigned long unknown_cmd; 209 unsigned long unknown_cmd;
210 unsigned long reqq_parity_err; 210 unsigned long reqq_parity_err;
211 unsigned long dispq_parity_err; 211 unsigned long dispq_parity_err;
212 unsigned long del_act_empty; 212 unsigned long del_act_empty;
213 }; 213 };
214 214
215 struct mc7_stats { 215 struct mc7_stats {
216 unsigned long corr_err; 216 unsigned long corr_err;
217 unsigned long uncorr_err; 217 unsigned long uncorr_err;
218 unsigned long parity_err; 218 unsigned long parity_err;
219 unsigned long addr_err; 219 unsigned long addr_err;
220 }; 220 };
221 221
222 struct mac_stats { 222 struct mac_stats {
223 u64 tx_octets; /* total # of octets in good frames */ 223 u64 tx_octets; /* total # of octets in good frames */
224 u64 tx_octets_bad; /* total # of octets in error frames */ 224 u64 tx_octets_bad; /* total # of octets in error frames */
225 u64 tx_frames; /* all good frames */ 225 u64 tx_frames; /* all good frames */
226 u64 tx_mcast_frames; /* good multicast frames */ 226 u64 tx_mcast_frames; /* good multicast frames */
227 u64 tx_bcast_frames; /* good broadcast frames */ 227 u64 tx_bcast_frames; /* good broadcast frames */
228 u64 tx_pause; /* # of transmitted pause frames */ 228 u64 tx_pause; /* # of transmitted pause frames */
229 u64 tx_deferred; /* frames with deferred transmissions */ 229 u64 tx_deferred; /* frames with deferred transmissions */
230 u64 tx_late_collisions; /* # of late collisions */ 230 u64 tx_late_collisions; /* # of late collisions */
231 u64 tx_total_collisions; /* # of total collisions */ 231 u64 tx_total_collisions; /* # of total collisions */
232 u64 tx_excess_collisions; /* frame errors from excessive collissions */ 232 u64 tx_excess_collisions; /* frame errors from excessive collissions */
233 u64 tx_underrun; /* # of Tx FIFO underruns */ 233 u64 tx_underrun; /* # of Tx FIFO underruns */
234 u64 tx_len_errs; /* # of Tx length errors */ 234 u64 tx_len_errs; /* # of Tx length errors */
235 u64 tx_mac_internal_errs; /* # of internal MAC errors on Tx */ 235 u64 tx_mac_internal_errs; /* # of internal MAC errors on Tx */
236 u64 tx_excess_deferral; /* # of frames with excessive deferral */ 236 u64 tx_excess_deferral; /* # of frames with excessive deferral */
237 u64 tx_fcs_errs; /* # of frames with bad FCS */ 237 u64 tx_fcs_errs; /* # of frames with bad FCS */
238 238
239 u64 tx_frames_64; /* # of Tx frames in a particular range */ 239 u64 tx_frames_64; /* # of Tx frames in a particular range */
240 u64 tx_frames_65_127; 240 u64 tx_frames_65_127;
241 u64 tx_frames_128_255; 241 u64 tx_frames_128_255;
242 u64 tx_frames_256_511; 242 u64 tx_frames_256_511;
243 u64 tx_frames_512_1023; 243 u64 tx_frames_512_1023;
244 u64 tx_frames_1024_1518; 244 u64 tx_frames_1024_1518;
245 u64 tx_frames_1519_max; 245 u64 tx_frames_1519_max;
246 246
247 u64 rx_octets; /* total # of octets in good frames */ 247 u64 rx_octets; /* total # of octets in good frames */
248 u64 rx_octets_bad; /* total # of octets in error frames */ 248 u64 rx_octets_bad; /* total # of octets in error frames */
249 u64 rx_frames; /* all good frames */ 249 u64 rx_frames; /* all good frames */
250 u64 rx_mcast_frames; /* good multicast frames */ 250 u64 rx_mcast_frames; /* good multicast frames */
251 u64 rx_bcast_frames; /* good broadcast frames */ 251 u64 rx_bcast_frames; /* good broadcast frames */
252 u64 rx_pause; /* # of received pause frames */ 252 u64 rx_pause; /* # of received pause frames */
253 u64 rx_fcs_errs; /* # of received frames with bad FCS */ 253 u64 rx_fcs_errs; /* # of received frames with bad FCS */
254 u64 rx_align_errs; /* alignment errors */ 254 u64 rx_align_errs; /* alignment errors */
255 u64 rx_symbol_errs; /* symbol errors */ 255 u64 rx_symbol_errs; /* symbol errors */
256 u64 rx_data_errs; /* data errors */ 256 u64 rx_data_errs; /* data errors */
257 u64 rx_sequence_errs; /* sequence errors */ 257 u64 rx_sequence_errs; /* sequence errors */
258 u64 rx_runt; /* # of runt frames */ 258 u64 rx_runt; /* # of runt frames */
259 u64 rx_jabber; /* # of jabber frames */ 259 u64 rx_jabber; /* # of jabber frames */
260 u64 rx_short; /* # of short frames */ 260 u64 rx_short; /* # of short frames */
261 u64 rx_too_long; /* # of oversized frames */ 261 u64 rx_too_long; /* # of oversized frames */
262 u64 rx_mac_internal_errs; /* # of internal MAC errors on Rx */ 262 u64 rx_mac_internal_errs; /* # of internal MAC errors on Rx */
263 263
264 u64 rx_frames_64; /* # of Rx frames in a particular range */ 264 u64 rx_frames_64; /* # of Rx frames in a particular range */
265 u64 rx_frames_65_127; 265 u64 rx_frames_65_127;
266 u64 rx_frames_128_255; 266 u64 rx_frames_128_255;
267 u64 rx_frames_256_511; 267 u64 rx_frames_256_511;
268 u64 rx_frames_512_1023; 268 u64 rx_frames_512_1023;
269 u64 rx_frames_1024_1518; 269 u64 rx_frames_1024_1518;
270 u64 rx_frames_1519_max; 270 u64 rx_frames_1519_max;
271 271
272 u64 rx_cong_drops; /* # of Rx drops due to SGE congestion */ 272 u64 rx_cong_drops; /* # of Rx drops due to SGE congestion */
273 273
274 unsigned long tx_fifo_parity_err; 274 unsigned long tx_fifo_parity_err;
275 unsigned long rx_fifo_parity_err; 275 unsigned long rx_fifo_parity_err;
276 unsigned long tx_fifo_urun; 276 unsigned long tx_fifo_urun;
277 unsigned long rx_fifo_ovfl; 277 unsigned long rx_fifo_ovfl;
278 unsigned long serdes_signal_loss; 278 unsigned long serdes_signal_loss;
279 unsigned long xaui_pcs_ctc_err; 279 unsigned long xaui_pcs_ctc_err;
280 unsigned long xaui_pcs_align_change; 280 unsigned long xaui_pcs_align_change;
281 281
282 unsigned long num_toggled; /* # times toggled TxEn due to stuck TX */ 282 unsigned long num_toggled; /* # times toggled TxEn due to stuck TX */
283 unsigned long num_resets; /* # times reset due to stuck TX */ 283 unsigned long num_resets; /* # times reset due to stuck TX */
284 284
285 unsigned long link_faults; /* # detected link faults */ 285 unsigned long link_faults; /* # detected link faults */
286 }; 286 };
287 287
288 struct tp_mib_stats { 288 struct tp_mib_stats {
289 u32 ipInReceive_hi; 289 u32 ipInReceive_hi;
290 u32 ipInReceive_lo; 290 u32 ipInReceive_lo;
291 u32 ipInHdrErrors_hi; 291 u32 ipInHdrErrors_hi;
292 u32 ipInHdrErrors_lo; 292 u32 ipInHdrErrors_lo;
293 u32 ipInAddrErrors_hi; 293 u32 ipInAddrErrors_hi;
294 u32 ipInAddrErrors_lo; 294 u32 ipInAddrErrors_lo;
295 u32 ipInUnknownProtos_hi; 295 u32 ipInUnknownProtos_hi;
296 u32 ipInUnknownProtos_lo; 296 u32 ipInUnknownProtos_lo;
297 u32 ipInDiscards_hi; 297 u32 ipInDiscards_hi;
298 u32 ipInDiscards_lo; 298 u32 ipInDiscards_lo;
299 u32 ipInDelivers_hi; 299 u32 ipInDelivers_hi;
300 u32 ipInDelivers_lo; 300 u32 ipInDelivers_lo;
301 u32 ipOutRequests_hi; 301 u32 ipOutRequests_hi;
302 u32 ipOutRequests_lo; 302 u32 ipOutRequests_lo;
303 u32 ipOutDiscards_hi; 303 u32 ipOutDiscards_hi;
304 u32 ipOutDiscards_lo; 304 u32 ipOutDiscards_lo;
305 u32 ipOutNoRoutes_hi; 305 u32 ipOutNoRoutes_hi;
306 u32 ipOutNoRoutes_lo; 306 u32 ipOutNoRoutes_lo;
307 u32 ipReasmTimeout; 307 u32 ipReasmTimeout;
308 u32 ipReasmReqds; 308 u32 ipReasmReqds;
309 u32 ipReasmOKs; 309 u32 ipReasmOKs;
310 u32 ipReasmFails; 310 u32 ipReasmFails;
311 311
312 u32 reserved[8]; 312 u32 reserved[8];
313 313
314 u32 tcpActiveOpens; 314 u32 tcpActiveOpens;
315 u32 tcpPassiveOpens; 315 u32 tcpPassiveOpens;
316 u32 tcpAttemptFails; 316 u32 tcpAttemptFails;
317 u32 tcpEstabResets; 317 u32 tcpEstabResets;
318 u32 tcpOutRsts; 318 u32 tcpOutRsts;
319 u32 tcpCurrEstab; 319 u32 tcpCurrEstab;
320 u32 tcpInSegs_hi; 320 u32 tcpInSegs_hi;
321 u32 tcpInSegs_lo; 321 u32 tcpInSegs_lo;
322 u32 tcpOutSegs_hi; 322 u32 tcpOutSegs_hi;
323 u32 tcpOutSegs_lo; 323 u32 tcpOutSegs_lo;
324 u32 tcpRetransSeg_hi; 324 u32 tcpRetransSeg_hi;
325 u32 tcpRetransSeg_lo; 325 u32 tcpRetransSeg_lo;
326 u32 tcpInErrs_hi; 326 u32 tcpInErrs_hi;
327 u32 tcpInErrs_lo; 327 u32 tcpInErrs_lo;
328 u32 tcpRtoMin; 328 u32 tcpRtoMin;
329 u32 tcpRtoMax; 329 u32 tcpRtoMax;
330 }; 330 };
331 331
332 struct tp_params { 332 struct tp_params {
333 unsigned int nchan; /* # of channels */ 333 unsigned int nchan; /* # of channels */
334 unsigned int pmrx_size; /* total PMRX capacity */ 334 unsigned int pmrx_size; /* total PMRX capacity */
335 unsigned int pmtx_size; /* total PMTX capacity */ 335 unsigned int pmtx_size; /* total PMTX capacity */
336 unsigned int cm_size; /* total CM capacity */ 336 unsigned int cm_size; /* total CM capacity */
337 unsigned int chan_rx_size; /* per channel Rx size */ 337 unsigned int chan_rx_size; /* per channel Rx size */
338 unsigned int chan_tx_size; /* per channel Tx size */ 338 unsigned int chan_tx_size; /* per channel Tx size */
339 unsigned int rx_pg_size; /* Rx page size */ 339 unsigned int rx_pg_size; /* Rx page size */
340 unsigned int tx_pg_size; /* Tx page size */ 340 unsigned int tx_pg_size; /* Tx page size */
341 unsigned int rx_num_pgs; /* # of Rx pages */ 341 unsigned int rx_num_pgs; /* # of Rx pages */
342 unsigned int tx_num_pgs; /* # of Tx pages */ 342 unsigned int tx_num_pgs; /* # of Tx pages */
343 unsigned int ntimer_qs; /* # of timer queues */ 343 unsigned int ntimer_qs; /* # of timer queues */
344 }; 344 };
345 345
346 struct qset_params { /* SGE queue set parameters */ 346 struct qset_params { /* SGE queue set parameters */
347 unsigned int polling; /* polling/interrupt service for rspq */ 347 unsigned int polling; /* polling/interrupt service for rspq */
348 unsigned int lro; /* large receive offload */ 348 unsigned int lro; /* large receive offload */
349 unsigned int coalesce_usecs; /* irq coalescing timer */ 349 unsigned int coalesce_usecs; /* irq coalescing timer */
350 unsigned int rspq_size; /* # of entries in response queue */ 350 unsigned int rspq_size; /* # of entries in response queue */
351 unsigned int fl_size; /* # of entries in regular free list */ 351 unsigned int fl_size; /* # of entries in regular free list */
352 unsigned int jumbo_size; /* # of entries in jumbo free list */ 352 unsigned int jumbo_size; /* # of entries in jumbo free list */
353 unsigned int txq_size[SGE_TXQ_PER_SET]; /* Tx queue sizes */ 353 unsigned int txq_size[SGE_TXQ_PER_SET]; /* Tx queue sizes */
354 unsigned int cong_thres; /* FL congestion threshold */ 354 unsigned int cong_thres; /* FL congestion threshold */
355 unsigned int vector; /* Interrupt (line or vector) number */ 355 unsigned int vector; /* Interrupt (line or vector) number */
356 }; 356 };
357 357
358 struct sge_params { 358 struct sge_params {
359 unsigned int max_pkt_size; /* max offload pkt size */ 359 unsigned int max_pkt_size; /* max offload pkt size */
360 struct qset_params qset[SGE_QSETS]; 360 struct qset_params qset[SGE_QSETS];
361 }; 361 };
362 362
363 struct mc5_params { 363 struct mc5_params {
364 unsigned int mode; /* selects MC5 width */ 364 unsigned int mode; /* selects MC5 width */
365 unsigned int nservers; /* size of server region */ 365 unsigned int nservers; /* size of server region */
366 unsigned int nfilters; /* size of filter region */ 366 unsigned int nfilters; /* size of filter region */
367 unsigned int nroutes; /* size of routing region */ 367 unsigned int nroutes; /* size of routing region */
368 }; 368 };
369 369
370 /* Default MC5 region sizes */ 370 /* Default MC5 region sizes */
371 enum { 371 enum {
372 DEFAULT_NSERVERS = 512, 372 DEFAULT_NSERVERS = 512,
373 DEFAULT_NFILTERS = 128 373 DEFAULT_NFILTERS = 128
374 }; 374 };
375 375
376 /* MC5 modes, these must be non-0 */ 376 /* MC5 modes, these must be non-0 */
377 enum { 377 enum {
378 MC5_MODE_144_BIT = 1, 378 MC5_MODE_144_BIT = 1,
379 MC5_MODE_72_BIT = 2 379 MC5_MODE_72_BIT = 2
380 }; 380 };
381 381
382 /* MC5 min active region size */ 382 /* MC5 min active region size */
383 enum { MC5_MIN_TIDS = 16 }; 383 enum { MC5_MIN_TIDS = 16 };
384 384
385 struct vpd_params { 385 struct vpd_params {
386 unsigned int cclk; 386 unsigned int cclk;
387 unsigned int mclk; 387 unsigned int mclk;
388 unsigned int uclk; 388 unsigned int uclk;
389 unsigned int mdc; 389 unsigned int mdc;
390 unsigned int mem_timing; 390 unsigned int mem_timing;
391 u8 sn[SERNUM_LEN + 1]; 391 u8 sn[SERNUM_LEN + 1];
392 u8 eth_base[6]; 392 u8 eth_base[6];
393 u8 port_type[MAX_NPORTS]; 393 u8 port_type[MAX_NPORTS];
394 unsigned short xauicfg[2]; 394 unsigned short xauicfg[2];
395 }; 395 };
396 396
397 struct pci_params { 397 struct pci_params {
398 unsigned int vpd_cap_addr; 398 unsigned int vpd_cap_addr;
399 unsigned int pcie_cap_addr; 399 unsigned int pcie_cap_addr;
400 unsigned short speed; 400 unsigned short speed;
401 unsigned char width; 401 unsigned char width;
402 unsigned char variant; 402 unsigned char variant;
403 }; 403 };
404 404
405 enum { 405 enum {
406 PCI_VARIANT_PCI, 406 PCI_VARIANT_PCI,
407 PCI_VARIANT_PCIX_MODE1_PARITY, 407 PCI_VARIANT_PCIX_MODE1_PARITY,
408 PCI_VARIANT_PCIX_MODE1_ECC, 408 PCI_VARIANT_PCIX_MODE1_ECC,
409 PCI_VARIANT_PCIX_266_MODE2, 409 PCI_VARIANT_PCIX_266_MODE2,
410 PCI_VARIANT_PCIE 410 PCI_VARIANT_PCIE
411 }; 411 };
412 412
413 struct adapter_params { 413 struct adapter_params {
414 struct sge_params sge; 414 struct sge_params sge;
415 struct mc5_params mc5; 415 struct mc5_params mc5;
416 struct tp_params tp; 416 struct tp_params tp;
417 struct vpd_params vpd; 417 struct vpd_params vpd;
418 struct pci_params pci; 418 struct pci_params pci;
419 419
420 const struct adapter_info *info; 420 const struct adapter_info *info;
421 421
422 unsigned short mtus[NMTUS]; 422 unsigned short mtus[NMTUS];
423 unsigned short a_wnd[NCCTRL_WIN]; 423 unsigned short a_wnd[NCCTRL_WIN];
424 unsigned short b_wnd[NCCTRL_WIN]; 424 unsigned short b_wnd[NCCTRL_WIN];
425 425
426 unsigned int nports; /* # of ethernet ports */ 426 unsigned int nports; /* # of ethernet ports */
427 unsigned int chan_map; /* bitmap of in-use Tx channels */ 427 unsigned int chan_map; /* bitmap of in-use Tx channels */
428 unsigned int stats_update_period; /* MAC stats accumulation period */ 428 unsigned int stats_update_period; /* MAC stats accumulation period */
429 unsigned int linkpoll_period; /* link poll period in 0.1s */ 429 unsigned int linkpoll_period; /* link poll period in 0.1s */
430 unsigned int rev; /* chip revision */ 430 unsigned int rev; /* chip revision */
431 unsigned int offload; 431 unsigned int offload;
432 }; 432 };
433 433
434 enum { /* chip revisions */ 434 enum { /* chip revisions */
435 T3_REV_A = 0, 435 T3_REV_A = 0,
436 T3_REV_B = 2, 436 T3_REV_B = 2,
437 T3_REV_B2 = 3, 437 T3_REV_B2 = 3,
438 T3_REV_C = 4, 438 T3_REV_C = 4,
439 }; 439 };
440 440
441 struct trace_params { 441 struct trace_params {
442 u32 sip; 442 u32 sip;
443 u32 sip_mask; 443 u32 sip_mask;
444 u32 dip; 444 u32 dip;
445 u32 dip_mask; 445 u32 dip_mask;
446 u16 sport; 446 u16 sport;
447 u16 sport_mask; 447 u16 sport_mask;
448 u16 dport; 448 u16 dport;
449 u16 dport_mask; 449 u16 dport_mask;
450 u32 vlan:12; 450 u32 vlan:12;
451 u32 vlan_mask:12; 451 u32 vlan_mask:12;
452 u32 intf:4; 452 u32 intf:4;
453 u32 intf_mask:4; 453 u32 intf_mask:4;
454 u8 proto; 454 u8 proto;
455 u8 proto_mask; 455 u8 proto_mask;
456 }; 456 };
457 457
458 struct link_config { 458 struct link_config {
459 unsigned int supported; /* link capabilities */ 459 unsigned int supported; /* link capabilities */
460 unsigned int advertising; /* advertised capabilities */ 460 unsigned int advertising; /* advertised capabilities */
461 unsigned short requested_speed; /* speed user has requested */ 461 unsigned short requested_speed; /* speed user has requested */
462 unsigned short speed; /* actual link speed */ 462 unsigned short speed; /* actual link speed */
463 unsigned char requested_duplex; /* duplex user has requested */ 463 unsigned char requested_duplex; /* duplex user has requested */
464 unsigned char duplex; /* actual link duplex */ 464 unsigned char duplex; /* actual link duplex */
465 unsigned char requested_fc; /* flow control user has requested */ 465 unsigned char requested_fc; /* flow control user has requested */
466 unsigned char fc; /* actual link flow control */ 466 unsigned char fc; /* actual link flow control */
467 unsigned char autoneg; /* autonegotiating? */ 467 unsigned char autoneg; /* autonegotiating? */
468 unsigned int link_ok; /* link up? */ 468 unsigned int link_ok; /* link up? */
469 }; 469 };
470 470
471 #define SPEED_INVALID 0xffff 471 #define SPEED_INVALID 0xffff
472 #define DUPLEX_INVALID 0xff 472 #define DUPLEX_INVALID 0xff
473 473
474 struct mc5 { 474 struct mc5 {
475 struct adapter *adapter; 475 struct adapter *adapter;
476 unsigned int tcam_size; 476 unsigned int tcam_size;
477 unsigned char part_type; 477 unsigned char part_type;
478 unsigned char parity_enabled; 478 unsigned char parity_enabled;
479 unsigned char mode; 479 unsigned char mode;
480 struct mc5_stats stats; 480 struct mc5_stats stats;
481 }; 481 };
482 482
483 static inline unsigned int t3_mc5_size(const struct mc5 *p) 483 static inline unsigned int t3_mc5_size(const struct mc5 *p)
484 { 484 {
485 return p->tcam_size; 485 return p->tcam_size;
486 } 486 }
487 487
488 struct mc7 { 488 struct mc7 {
489 struct adapter *adapter; /* backpointer to adapter */ 489 struct adapter *adapter; /* backpointer to adapter */
490 unsigned int size; /* memory size in bytes */ 490 unsigned int size; /* memory size in bytes */
491 unsigned int width; /* MC7 interface width */ 491 unsigned int width; /* MC7 interface width */
492 unsigned int offset; /* register address offset for MC7 instance */ 492 unsigned int offset; /* register address offset for MC7 instance */
493 const char *name; /* name of MC7 instance */ 493 const char *name; /* name of MC7 instance */
494 struct mc7_stats stats; /* MC7 statistics */ 494 struct mc7_stats stats; /* MC7 statistics */
495 }; 495 };
496 496
497 static inline unsigned int t3_mc7_size(const struct mc7 *p) 497 static inline unsigned int t3_mc7_size(const struct mc7 *p)
498 { 498 {
499 return p->size; 499 return p->size;
500 } 500 }
501 501
502 struct cmac { 502 struct cmac {
503 struct adapter *adapter; 503 struct adapter *adapter;
504 unsigned int offset; 504 unsigned int offset;
505 unsigned int nucast; /* # of address filters for unicast MACs */ 505 unsigned int nucast; /* # of address filters for unicast MACs */
506 unsigned int tx_tcnt; 506 unsigned int tx_tcnt;
507 unsigned int tx_xcnt; 507 unsigned int tx_xcnt;
508 u64 tx_mcnt; 508 u64 tx_mcnt;
509 unsigned int rx_xcnt; 509 unsigned int rx_xcnt;
510 unsigned int rx_ocnt; 510 unsigned int rx_ocnt;
511 u64 rx_mcnt; 511 u64 rx_mcnt;
512 unsigned int toggle_cnt; 512 unsigned int toggle_cnt;
513 unsigned int txen; 513 unsigned int txen;
514 u64 rx_pause; 514 u64 rx_pause;
515 struct mac_stats stats; 515 struct mac_stats stats;
516 }; 516 };
517 517
518 enum { 518 enum {
519 MAC_DIRECTION_RX = 1, 519 MAC_DIRECTION_RX = 1,
520 MAC_DIRECTION_TX = 2, 520 MAC_DIRECTION_TX = 2,
521 MAC_RXFIFO_SIZE = 32768 521 MAC_RXFIFO_SIZE = 32768
522 }; 522 };
523 523
524 /* PHY loopback direction */ 524 /* PHY loopback direction */
525 enum { 525 enum {
526 PHY_LOOPBACK_TX = 1, 526 PHY_LOOPBACK_TX = 1,
527 PHY_LOOPBACK_RX = 2 527 PHY_LOOPBACK_RX = 2
528 }; 528 };
529 529
530 /* PHY interrupt types */ 530 /* PHY interrupt types */
531 enum { 531 enum {
532 cphy_cause_link_change = 1, 532 cphy_cause_link_change = 1,
533 cphy_cause_fifo_error = 2, 533 cphy_cause_fifo_error = 2,
534 cphy_cause_module_change = 4, 534 cphy_cause_module_change = 4,
535 }; 535 };
536 536
537 /* PHY module types */ 537 /* PHY module types */
538 enum { 538 enum {
539 phy_modtype_none, 539 phy_modtype_none,
540 phy_modtype_sr, 540 phy_modtype_sr,
541 phy_modtype_lr, 541 phy_modtype_lr,
542 phy_modtype_lrm, 542 phy_modtype_lrm,
543 phy_modtype_twinax, 543 phy_modtype_twinax,
544 phy_modtype_twinax_long, 544 phy_modtype_twinax_long,
545 phy_modtype_unknown 545 phy_modtype_unknown
546 }; 546 };
547 547
548 /* PHY operations */ 548 /* PHY operations */
549 struct cphy_ops { 549 struct cphy_ops {
550 int (*reset)(struct cphy *phy, int wait); 550 int (*reset)(struct cphy *phy, int wait);
551 551
552 int (*intr_enable)(struct cphy *phy); 552 int (*intr_enable)(struct cphy *phy);
553 int (*intr_disable)(struct cphy *phy); 553 int (*intr_disable)(struct cphy *phy);
554 int (*intr_clear)(struct cphy *phy); 554 int (*intr_clear)(struct cphy *phy);
555 int (*intr_handler)(struct cphy *phy); 555 int (*intr_handler)(struct cphy *phy);
556 556
557 int (*autoneg_enable)(struct cphy *phy); 557 int (*autoneg_enable)(struct cphy *phy);
558 int (*autoneg_restart)(struct cphy *phy); 558 int (*autoneg_restart)(struct cphy *phy);
559 559
560 int (*advertise)(struct cphy *phy, unsigned int advertise_map); 560 int (*advertise)(struct cphy *phy, unsigned int advertise_map);
561 int (*set_loopback)(struct cphy *phy, int mmd, int dir, int enable); 561 int (*set_loopback)(struct cphy *phy, int mmd, int dir, int enable);
562 int (*set_speed_duplex)(struct cphy *phy, int speed, int duplex); 562 int (*set_speed_duplex)(struct cphy *phy, int speed, int duplex);
563 int (*get_link_status)(struct cphy *phy, int *link_ok, int *speed, 563 int (*get_link_status)(struct cphy *phy, int *link_ok, int *speed,
564 int *duplex, int *fc); 564 int *duplex, int *fc);
565 int (*power_down)(struct cphy *phy, int enable); 565 int (*power_down)(struct cphy *phy, int enable);
566 566
567 u32 mmds; 567 u32 mmds;
568 }; 568 };
569 enum {
570 EDC_OPT_AEL2005 = 0,
571 EDC_OPT_AEL2005_SIZE = 1084,
572 EDC_TWX_AEL2005 = 1,
573 EDC_TWX_AEL2005_SIZE = 1464,
574 EDC_TWX_AEL2020 = 2,
575 EDC_TWX_AEL2020_SIZE = 1628,
576 EDC_MAX_SIZE = EDC_TWX_AEL2020_SIZE, /* Max cache size */
577 };
569 578
570 /* A PHY instance */ 579 /* A PHY instance */
571 struct cphy { 580 struct cphy {
572 u8 modtype; /* PHY module type */ 581 u8 modtype; /* PHY module type */
573 short priv; /* scratch pad */ 582 short priv; /* scratch pad */
574 unsigned int caps; /* PHY capabilities */ 583 unsigned int caps; /* PHY capabilities */
575 struct adapter *adapter; /* associated adapter */ 584 struct adapter *adapter; /* associated adapter */
576 const char *desc; /* PHY description */ 585 const char *desc; /* PHY description */
577 unsigned long fifo_errors; /* FIFO over/under-flows */ 586 unsigned long fifo_errors; /* FIFO over/under-flows */
578 const struct cphy_ops *ops; /* PHY operations */ 587 const struct cphy_ops *ops; /* PHY operations */
579 struct mdio_if_info mdio; 588 struct mdio_if_info mdio;
589 u16 phy_cache[EDC_MAX_SIZE]; /* EDC cache */
580 }; 590 };
581 591
582 /* Convenience MDIO read/write wrappers */ 592 /* Convenience MDIO read/write wrappers */
583 static inline int t3_mdio_read(struct cphy *phy, int mmd, int reg, 593 static inline int t3_mdio_read(struct cphy *phy, int mmd, int reg,
584 unsigned int *valp) 594 unsigned int *valp)
585 { 595 {
586 int rc = phy->mdio.mdio_read(phy->mdio.dev, phy->mdio.prtad, mmd, reg); 596 int rc = phy->mdio.mdio_read(phy->mdio.dev, phy->mdio.prtad, mmd, reg);
587 *valp = (rc >= 0) ? rc : -1; 597 *valp = (rc >= 0) ? rc : -1;
588 return (rc >= 0) ? 0 : rc; 598 return (rc >= 0) ? 0 : rc;
589 } 599 }
590 600
591 static inline int t3_mdio_write(struct cphy *phy, int mmd, int reg, 601 static inline int t3_mdio_write(struct cphy *phy, int mmd, int reg,
592 unsigned int val) 602 unsigned int val)
593 { 603 {
594 return phy->mdio.mdio_write(phy->mdio.dev, phy->mdio.prtad, mmd, 604 return phy->mdio.mdio_write(phy->mdio.dev, phy->mdio.prtad, mmd,
595 reg, val); 605 reg, val);
596 } 606 }
597 607
598 /* Convenience initializer */ 608 /* Convenience initializer */
599 static inline void cphy_init(struct cphy *phy, struct adapter *adapter, 609 static inline void cphy_init(struct cphy *phy, struct adapter *adapter,
600 int phy_addr, struct cphy_ops *phy_ops, 610 int phy_addr, struct cphy_ops *phy_ops,
601 const struct mdio_ops *mdio_ops, 611 const struct mdio_ops *mdio_ops,
602 unsigned int caps, const char *desc) 612 unsigned int caps, const char *desc)
603 { 613 {
604 phy->caps = caps; 614 phy->caps = caps;
605 phy->adapter = adapter; 615 phy->adapter = adapter;
606 phy->desc = desc; 616 phy->desc = desc;
607 phy->ops = phy_ops; 617 phy->ops = phy_ops;
608 if (mdio_ops) { 618 if (mdio_ops) {
609 phy->mdio.prtad = phy_addr; 619 phy->mdio.prtad = phy_addr;
610 phy->mdio.mmds = phy_ops->mmds; 620 phy->mdio.mmds = phy_ops->mmds;
611 phy->mdio.mode_support = mdio_ops->mode_support; 621 phy->mdio.mode_support = mdio_ops->mode_support;
612 phy->mdio.mdio_read = mdio_ops->read; 622 phy->mdio.mdio_read = mdio_ops->read;
613 phy->mdio.mdio_write = mdio_ops->write; 623 phy->mdio.mdio_write = mdio_ops->write;
614 } 624 }
615 } 625 }
616 626
617 /* Accumulate MAC statistics every 180 seconds. For 1G we multiply by 10. */ 627 /* Accumulate MAC statistics every 180 seconds. For 1G we multiply by 10. */
618 #define MAC_STATS_ACCUM_SECS 180 628 #define MAC_STATS_ACCUM_SECS 180
619 629
620 #define XGM_REG(reg_addr, idx) \ 630 #define XGM_REG(reg_addr, idx) \
621 ((reg_addr) + (idx) * (XGMAC0_1_BASE_ADDR - XGMAC0_0_BASE_ADDR)) 631 ((reg_addr) + (idx) * (XGMAC0_1_BASE_ADDR - XGMAC0_0_BASE_ADDR))
622 632
623 struct addr_val_pair { 633 struct addr_val_pair {
624 unsigned int reg_addr; 634 unsigned int reg_addr;
625 unsigned int val; 635 unsigned int val;
626 }; 636 };
627 637
628 #include "adapter.h" 638 #include "adapter.h"
629 639
630 #ifndef PCI_VENDOR_ID_CHELSIO 640 #ifndef PCI_VENDOR_ID_CHELSIO
631 # define PCI_VENDOR_ID_CHELSIO 0x1425 641 # define PCI_VENDOR_ID_CHELSIO 0x1425
632 #endif 642 #endif
633 643
634 #define for_each_port(adapter, iter) \ 644 #define for_each_port(adapter, iter) \
635 for (iter = 0; iter < (adapter)->params.nports; ++iter) 645 for (iter = 0; iter < (adapter)->params.nports; ++iter)
636 646
637 #define adapter_info(adap) ((adap)->params.info) 647 #define adapter_info(adap) ((adap)->params.info)
638 648
639 static inline int uses_xaui(const struct adapter *adap) 649 static inline int uses_xaui(const struct adapter *adap)
640 { 650 {
641 return adapter_info(adap)->caps & SUPPORTED_AUI; 651 return adapter_info(adap)->caps & SUPPORTED_AUI;
642 } 652 }
643 653
644 static inline int is_10G(const struct adapter *adap) 654 static inline int is_10G(const struct adapter *adap)
645 { 655 {
646 return adapter_info(adap)->caps & SUPPORTED_10000baseT_Full; 656 return adapter_info(adap)->caps & SUPPORTED_10000baseT_Full;
647 } 657 }
648 658
649 static inline int is_offload(const struct adapter *adap) 659 static inline int is_offload(const struct adapter *adap)
650 { 660 {
651 return adap->params.offload; 661 return adap->params.offload;
652 } 662 }
653 663
654 static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 664 static inline unsigned int core_ticks_per_usec(const struct adapter *adap)
655 { 665 {
656 return adap->params.vpd.cclk / 1000; 666 return adap->params.vpd.cclk / 1000;
657 } 667 }
658 668
659 static inline unsigned int is_pcie(const struct adapter *adap) 669 static inline unsigned int is_pcie(const struct adapter *adap)
660 { 670 {
661 return adap->params.pci.variant == PCI_VARIANT_PCIE; 671 return adap->params.pci.variant == PCI_VARIANT_PCIE;
662 } 672 }
663 673
664 void t3_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, 674 void t3_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask,
665 u32 val); 675 u32 val);
666 void t3_write_regs(struct adapter *adapter, const struct addr_val_pair *p, 676 void t3_write_regs(struct adapter *adapter, const struct addr_val_pair *p,
667 int n, unsigned int offset); 677 int n, unsigned int offset);
668 int t3_wait_op_done_val(struct adapter *adapter, int reg, u32 mask, 678 int t3_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
669 int polarity, int attempts, int delay, u32 *valp); 679 int polarity, int attempts, int delay, u32 *valp);
670 static inline int t3_wait_op_done(struct adapter *adapter, int reg, u32 mask, 680 static inline int t3_wait_op_done(struct adapter *adapter, int reg, u32 mask,
671 int polarity, int attempts, int delay) 681 int polarity, int attempts, int delay)
672 { 682 {
673 return t3_wait_op_done_val(adapter, reg, mask, polarity, attempts, 683 return t3_wait_op_done_val(adapter, reg, mask, polarity, attempts,
674 delay, NULL); 684 delay, NULL);
675 } 685 }
676 int t3_mdio_change_bits(struct cphy *phy, int mmd, int reg, unsigned int clear, 686 int t3_mdio_change_bits(struct cphy *phy, int mmd, int reg, unsigned int clear,
677 unsigned int set); 687 unsigned int set);
678 int t3_phy_reset(struct cphy *phy, int mmd, int wait); 688 int t3_phy_reset(struct cphy *phy, int mmd, int wait);
679 int t3_phy_advertise(struct cphy *phy, unsigned int advert); 689 int t3_phy_advertise(struct cphy *phy, unsigned int advert);
680 int t3_phy_advertise_fiber(struct cphy *phy, unsigned int advert); 690 int t3_phy_advertise_fiber(struct cphy *phy, unsigned int advert);
681 int t3_set_phy_speed_duplex(struct cphy *phy, int speed, int duplex); 691 int t3_set_phy_speed_duplex(struct cphy *phy, int speed, int duplex);
682 int t3_phy_lasi_intr_enable(struct cphy *phy); 692 int t3_phy_lasi_intr_enable(struct cphy *phy);
683 int t3_phy_lasi_intr_disable(struct cphy *phy); 693 int t3_phy_lasi_intr_disable(struct cphy *phy);
684 int t3_phy_lasi_intr_clear(struct cphy *phy); 694 int t3_phy_lasi_intr_clear(struct cphy *phy);
685 int t3_phy_lasi_intr_handler(struct cphy *phy); 695 int t3_phy_lasi_intr_handler(struct cphy *phy);
686 696
687 void t3_intr_enable(struct adapter *adapter); 697 void t3_intr_enable(struct adapter *adapter);
688 void t3_intr_disable(struct adapter *adapter); 698 void t3_intr_disable(struct adapter *adapter);
689 void t3_intr_clear(struct adapter *adapter); 699 void t3_intr_clear(struct adapter *adapter);
690 void t3_xgm_intr_enable(struct adapter *adapter, int idx); 700 void t3_xgm_intr_enable(struct adapter *adapter, int idx);
691 void t3_xgm_intr_disable(struct adapter *adapter, int idx); 701 void t3_xgm_intr_disable(struct adapter *adapter, int idx);
692 void t3_port_intr_enable(struct adapter *adapter, int idx); 702 void t3_port_intr_enable(struct adapter *adapter, int idx);
693 void t3_port_intr_disable(struct adapter *adapter, int idx); 703 void t3_port_intr_disable(struct adapter *adapter, int idx);
694 void t3_port_intr_clear(struct adapter *adapter, int idx); 704 void t3_port_intr_clear(struct adapter *adapter, int idx);
695 int t3_slow_intr_handler(struct adapter *adapter); 705 int t3_slow_intr_handler(struct adapter *adapter);
696 int t3_phy_intr_handler(struct adapter *adapter); 706 int t3_phy_intr_handler(struct adapter *adapter);
697 707
698 void t3_link_changed(struct adapter *adapter, int port_id); 708 void t3_link_changed(struct adapter *adapter, int port_id);
699 void t3_link_fault(struct adapter *adapter, int port_id); 709 void t3_link_fault(struct adapter *adapter, int port_id);
700 int t3_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc); 710 int t3_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc);
701 const struct adapter_info *t3_get_adapter_info(unsigned int board_id); 711 const struct adapter_info *t3_get_adapter_info(unsigned int board_id);
702 int t3_seeprom_read(struct adapter *adapter, u32 addr, __le32 *data); 712 int t3_seeprom_read(struct adapter *adapter, u32 addr, __le32 *data);
703 int t3_seeprom_write(struct adapter *adapter, u32 addr, __le32 data); 713 int t3_seeprom_write(struct adapter *adapter, u32 addr, __le32 data);
704 int t3_seeprom_wp(struct adapter *adapter, int enable); 714 int t3_seeprom_wp(struct adapter *adapter, int enable);
705 int t3_get_tp_version(struct adapter *adapter, u32 *vers); 715 int t3_get_tp_version(struct adapter *adapter, u32 *vers);
706 int t3_check_tpsram_version(struct adapter *adapter); 716 int t3_check_tpsram_version(struct adapter *adapter);
707 int t3_check_tpsram(struct adapter *adapter, const u8 *tp_ram, 717 int t3_check_tpsram(struct adapter *adapter, const u8 *tp_ram,
708 unsigned int size); 718 unsigned int size);
709 int t3_set_proto_sram(struct adapter *adap, const u8 *data); 719 int t3_set_proto_sram(struct adapter *adap, const u8 *data);
710 int t3_read_flash(struct adapter *adapter, unsigned int addr, 720 int t3_read_flash(struct adapter *adapter, unsigned int addr,
711 unsigned int nwords, u32 *data, int byte_oriented); 721 unsigned int nwords, u32 *data, int byte_oriented);
712 int t3_load_fw(struct adapter *adapter, const u8 * fw_data, unsigned int size); 722 int t3_load_fw(struct adapter *adapter, const u8 * fw_data, unsigned int size);
713 int t3_get_fw_version(struct adapter *adapter, u32 *vers); 723 int t3_get_fw_version(struct adapter *adapter, u32 *vers);
714 int t3_check_fw_version(struct adapter *adapter); 724 int t3_check_fw_version(struct adapter *adapter);
715 int t3_init_hw(struct adapter *adapter, u32 fw_params); 725 int t3_init_hw(struct adapter *adapter, u32 fw_params);
716 void mac_prep(struct cmac *mac, struct adapter *adapter, int index); 726 void mac_prep(struct cmac *mac, struct adapter *adapter, int index);
717 void early_hw_init(struct adapter *adapter, const struct adapter_info *ai); 727 void early_hw_init(struct adapter *adapter, const struct adapter_info *ai);
718 int t3_reset_adapter(struct adapter *adapter); 728 int t3_reset_adapter(struct adapter *adapter);
719 int t3_prep_adapter(struct adapter *adapter, const struct adapter_info *ai, 729 int t3_prep_adapter(struct adapter *adapter, const struct adapter_info *ai,
720 int reset); 730 int reset);
721 int t3_replay_prep_adapter(struct adapter *adapter); 731 int t3_replay_prep_adapter(struct adapter *adapter);
722 void t3_led_ready(struct adapter *adapter); 732 void t3_led_ready(struct adapter *adapter);
723 void t3_fatal_err(struct adapter *adapter); 733 void t3_fatal_err(struct adapter *adapter);
724 void t3_set_vlan_accel(struct adapter *adapter, unsigned int ports, int on); 734 void t3_set_vlan_accel(struct adapter *adapter, unsigned int ports, int on);
725 void t3_config_rss(struct adapter *adapter, unsigned int rss_config, 735 void t3_config_rss(struct adapter *adapter, unsigned int rss_config,
726 const u8 * cpus, const u16 *rspq); 736 const u8 * cpus, const u16 *rspq);
727 int t3_read_rss(struct adapter *adapter, u8 * lkup, u16 *map); 737 int t3_read_rss(struct adapter *adapter, u8 * lkup, u16 *map);
728 int t3_mps_set_active_ports(struct adapter *adap, unsigned int port_mask); 738 int t3_mps_set_active_ports(struct adapter *adap, unsigned int port_mask);
729 int t3_cim_ctl_blk_read(struct adapter *adap, unsigned int addr, 739 int t3_cim_ctl_blk_read(struct adapter *adap, unsigned int addr,
730 unsigned int n, unsigned int *valp); 740 unsigned int n, unsigned int *valp);
731 int t3_mc7_bd_read(struct mc7 *mc7, unsigned int start, unsigned int n, 741 int t3_mc7_bd_read(struct mc7 *mc7, unsigned int start, unsigned int n,
732 u64 *buf); 742 u64 *buf);
733 743
734 int t3_mac_reset(struct cmac *mac); 744 int t3_mac_reset(struct cmac *mac);
735 void t3b_pcs_reset(struct cmac *mac); 745 void t3b_pcs_reset(struct cmac *mac);
736 void t3_mac_disable_exact_filters(struct cmac *mac); 746 void t3_mac_disable_exact_filters(struct cmac *mac);
737 void t3_mac_enable_exact_filters(struct cmac *mac); 747 void t3_mac_enable_exact_filters(struct cmac *mac);
738 int t3_mac_enable(struct cmac *mac, int which); 748 int t3_mac_enable(struct cmac *mac, int which);
739 int t3_mac_disable(struct cmac *mac, int which); 749 int t3_mac_disable(struct cmac *mac, int which);
740 int t3_mac_set_mtu(struct cmac *mac, unsigned int mtu); 750 int t3_mac_set_mtu(struct cmac *mac, unsigned int mtu);
741 int t3_mac_set_rx_mode(struct cmac *mac, struct t3_rx_mode *rm); 751 int t3_mac_set_rx_mode(struct cmac *mac, struct t3_rx_mode *rm);
742 int t3_mac_set_address(struct cmac *mac, unsigned int idx, u8 addr[6]); 752 int t3_mac_set_address(struct cmac *mac, unsigned int idx, u8 addr[6]);
743 int t3_mac_set_num_ucast(struct cmac *mac, int n); 753 int t3_mac_set_num_ucast(struct cmac *mac, int n);
744 const struct mac_stats *t3_mac_update_stats(struct cmac *mac); 754 const struct mac_stats *t3_mac_update_stats(struct cmac *mac);
745 int t3_mac_set_speed_duplex_fc(struct cmac *mac, int speed, int duplex, int fc); 755 int t3_mac_set_speed_duplex_fc(struct cmac *mac, int speed, int duplex, int fc);
746 int t3b2_mac_watchdog_task(struct cmac *mac); 756 int t3b2_mac_watchdog_task(struct cmac *mac);
747 757
748 void t3_mc5_prep(struct adapter *adapter, struct mc5 *mc5, int mode); 758 void t3_mc5_prep(struct adapter *adapter, struct mc5 *mc5, int mode);
749 int t3_mc5_init(struct mc5 *mc5, unsigned int nservers, unsigned int nfilters, 759 int t3_mc5_init(struct mc5 *mc5, unsigned int nservers, unsigned int nfilters,
750 unsigned int nroutes); 760 unsigned int nroutes);
751 void t3_mc5_intr_handler(struct mc5 *mc5); 761 void t3_mc5_intr_handler(struct mc5 *mc5);
752 int t3_read_mc5_range(const struct mc5 *mc5, unsigned int start, unsigned int n, 762 int t3_read_mc5_range(const struct mc5 *mc5, unsigned int start, unsigned int n,
753 u32 *buf); 763 u32 *buf);
754 764
755 int t3_tp_set_coalescing_size(struct adapter *adap, unsigned int size, int psh); 765 int t3_tp_set_coalescing_size(struct adapter *adap, unsigned int size, int psh);
756 void t3_tp_set_max_rxsize(struct adapter *adap, unsigned int size); 766 void t3_tp_set_max_rxsize(struct adapter *adap, unsigned int size);
757 void t3_tp_set_offload_mode(struct adapter *adap, int enable); 767 void t3_tp_set_offload_mode(struct adapter *adap, int enable);
758 void t3_tp_get_mib_stats(struct adapter *adap, struct tp_mib_stats *tps); 768 void t3_tp_get_mib_stats(struct adapter *adap, struct tp_mib_stats *tps);
759 void t3_load_mtus(struct adapter *adap, unsigned short mtus[NMTUS], 769 void t3_load_mtus(struct adapter *adap, unsigned short mtus[NMTUS],
760 unsigned short alpha[NCCTRL_WIN], 770 unsigned short alpha[NCCTRL_WIN],
761 unsigned short beta[NCCTRL_WIN], unsigned short mtu_cap); 771 unsigned short beta[NCCTRL_WIN], unsigned short mtu_cap);
762 void t3_read_hw_mtus(struct adapter *adap, unsigned short mtus[NMTUS]); 772 void t3_read_hw_mtus(struct adapter *adap, unsigned short mtus[NMTUS]);
763 void t3_get_cong_cntl_tab(struct adapter *adap, 773 void t3_get_cong_cntl_tab(struct adapter *adap,
764 unsigned short incr[NMTUS][NCCTRL_WIN]); 774 unsigned short incr[NMTUS][NCCTRL_WIN]);
765 void t3_config_trace_filter(struct adapter *adapter, 775 void t3_config_trace_filter(struct adapter *adapter,
766 const struct trace_params *tp, int filter_index, 776 const struct trace_params *tp, int filter_index,
767 int invert, int enable); 777 int invert, int enable);
768 int t3_config_sched(struct adapter *adap, unsigned int kbps, int sched); 778 int t3_config_sched(struct adapter *adap, unsigned int kbps, int sched);
769 779
770 void t3_sge_prep(struct adapter *adap, struct sge_params *p); 780 void t3_sge_prep(struct adapter *adap, struct sge_params *p);
771 void t3_sge_init(struct adapter *adap, struct sge_params *p); 781 void t3_sge_init(struct adapter *adap, struct sge_params *p);
772 int t3_sge_init_ecntxt(struct adapter *adapter, unsigned int id, int gts_enable, 782 int t3_sge_init_ecntxt(struct adapter *adapter, unsigned int id, int gts_enable,
773 enum sge_context_type type, int respq, u64 base_addr, 783 enum sge_context_type type, int respq, u64 base_addr,
774 unsigned int size, unsigned int token, int gen, 784 unsigned int size, unsigned int token, int gen,
775 unsigned int cidx); 785 unsigned int cidx);
776 int t3_sge_init_flcntxt(struct adapter *adapter, unsigned int id, 786 int t3_sge_init_flcntxt(struct adapter *adapter, unsigned int id,
777 int gts_enable, u64 base_addr, unsigned int size, 787 int gts_enable, u64 base_addr, unsigned int size,
778 unsigned int esize, unsigned int cong_thres, int gen, 788 unsigned int esize, unsigned int cong_thres, int gen,
779 unsigned int cidx); 789 unsigned int cidx);
780 int t3_sge_init_rspcntxt(struct adapter *adapter, unsigned int id, 790 int t3_sge_init_rspcntxt(struct adapter *adapter, unsigned int id,
781 int irq_vec_idx, u64 base_addr, unsigned int size, 791 int irq_vec_idx, u64 base_addr, unsigned int size,
782 unsigned int fl_thres, int gen, unsigned int cidx); 792 unsigned int fl_thres, int gen, unsigned int cidx);
783 int t3_sge_init_cqcntxt(struct adapter *adapter, unsigned int id, u64 base_addr, 793 int t3_sge_init_cqcntxt(struct adapter *adapter, unsigned int id, u64 base_addr,
784 unsigned int size, int rspq, int ovfl_mode, 794 unsigned int size, int rspq, int ovfl_mode,
785 unsigned int credits, unsigned int credit_thres); 795 unsigned int credits, unsigned int credit_thres);
786 int t3_sge_enable_ecntxt(struct adapter *adapter, unsigned int id, int enable); 796 int t3_sge_enable_ecntxt(struct adapter *adapter, unsigned int id, int enable);
787 int t3_sge_disable_fl(struct adapter *adapter, unsigned int id); 797 int t3_sge_disable_fl(struct adapter *adapter, unsigned int id);
788 int t3_sge_disable_rspcntxt(struct adapter *adapter, unsigned int id); 798 int t3_sge_disable_rspcntxt(struct adapter *adapter, unsigned int id);
789 int t3_sge_disable_cqcntxt(struct adapter *adapter, unsigned int id); 799 int t3_sge_disable_cqcntxt(struct adapter *adapter, unsigned int id);
790 int t3_sge_read_ecntxt(struct adapter *adapter, unsigned int id, u32 data[4]); 800 int t3_sge_read_ecntxt(struct adapter *adapter, unsigned int id, u32 data[4]);
791 int t3_sge_read_fl(struct adapter *adapter, unsigned int id, u32 data[4]); 801 int t3_sge_read_fl(struct adapter *adapter, unsigned int id, u32 data[4]);
792 int t3_sge_read_cq(struct adapter *adapter, unsigned int id, u32 data[4]); 802 int t3_sge_read_cq(struct adapter *adapter, unsigned int id, u32 data[4]);
793 int t3_sge_read_rspq(struct adapter *adapter, unsigned int id, u32 data[4]); 803 int t3_sge_read_rspq(struct adapter *adapter, unsigned int id, u32 data[4]);
794 int t3_sge_cqcntxt_op(struct adapter *adapter, unsigned int id, unsigned int op, 804 int t3_sge_cqcntxt_op(struct adapter *adapter, unsigned int id, unsigned int op,
795 unsigned int credits); 805 unsigned int credits);
796 806
797 int t3_vsc8211_phy_prep(struct cphy *phy, struct adapter *adapter, 807 int t3_vsc8211_phy_prep(struct cphy *phy, struct adapter *adapter,
798 int phy_addr, const struct mdio_ops *mdio_ops); 808 int phy_addr, const struct mdio_ops *mdio_ops);
799 int t3_ael1002_phy_prep(struct cphy *phy, struct adapter *adapter, 809 int t3_ael1002_phy_prep(struct cphy *phy, struct adapter *adapter,
800 int phy_addr, const struct mdio_ops *mdio_ops); 810 int phy_addr, const struct mdio_ops *mdio_ops);
801 int t3_ael1006_phy_prep(struct cphy *phy, struct adapter *adapter, 811 int t3_ael1006_phy_prep(struct cphy *phy, struct adapter *adapter,
802 int phy_addr, const struct mdio_ops *mdio_ops); 812 int phy_addr, const struct mdio_ops *mdio_ops);
803 int t3_ael2005_phy_prep(struct cphy *phy, struct adapter *adapter, 813 int t3_ael2005_phy_prep(struct cphy *phy, struct adapter *adapter,
804 int phy_addr, const struct mdio_ops *mdio_ops); 814 int phy_addr, const struct mdio_ops *mdio_ops);
805 int t3_ael2020_phy_prep(struct cphy *phy, struct adapter *adapter, 815 int t3_ael2020_phy_prep(struct cphy *phy, struct adapter *adapter,
806 int phy_addr, const struct mdio_ops *mdio_ops); 816 int phy_addr, const struct mdio_ops *mdio_ops);
807 int t3_qt2045_phy_prep(struct cphy *phy, struct adapter *adapter, int phy_addr, 817 int t3_qt2045_phy_prep(struct cphy *phy, struct adapter *adapter, int phy_addr,
808 const struct mdio_ops *mdio_ops); 818 const struct mdio_ops *mdio_ops);
809 int t3_xaui_direct_phy_prep(struct cphy *phy, struct adapter *adapter, 819 int t3_xaui_direct_phy_prep(struct cphy *phy, struct adapter *adapter,
810 int phy_addr, const struct mdio_ops *mdio_ops); 820 int phy_addr, const struct mdio_ops *mdio_ops);
811 int t3_aq100x_phy_prep(struct cphy *phy, struct adapter *adapter, 821 int t3_aq100x_phy_prep(struct cphy *phy, struct adapter *adapter,
812 int phy_addr, const struct mdio_ops *mdio_ops); 822 int phy_addr, const struct mdio_ops *mdio_ops);
813 #endif /* __CHELSIO_COMMON_H */ 823 #endif /* __CHELSIO_COMMON_H */
814 824
drivers/net/cxgb3/cxgb3_main.c
Diff comments   View file @ 2e8c07c
1 /* 1 /*
2 * Copyright (c) 2003-2008 Chelsio, Inc. All rights reserved. 2 * Copyright (c) 2003-2008 Chelsio, Inc. All rights reserved.
3 * 3 *
4 * This software is available to you under a choice of one of two 4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU 5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file 6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the 7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below: 8 * OpenIB.org BSD license below:
9 * 9 *
10 * Redistribution and use in source and binary forms, with or 10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following 11 * without modification, are permitted provided that the following
12 * conditions are met: 12 * conditions are met:
13 * 13 *
14 * - Redistributions of source code must retain the above 14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following 15 * copyright notice, this list of conditions and the following
16 * disclaimer. 16 * disclaimer.
17 * 17 *
18 * - Redistributions in binary form must reproduce the above 18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following 19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials 20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution. 21 * provided with the distribution.
22 * 22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE. 30 * SOFTWARE.
31 */ 31 */
32 #include <linux/module.h> 32 #include <linux/module.h>
33 #include <linux/moduleparam.h> 33 #include <linux/moduleparam.h>
34 #include <linux/init.h> 34 #include <linux/init.h>
35 #include <linux/pci.h> 35 #include <linux/pci.h>
36 #include <linux/dma-mapping.h> 36 #include <linux/dma-mapping.h>
37 #include <linux/netdevice.h> 37 #include <linux/netdevice.h>
38 #include <linux/etherdevice.h> 38 #include <linux/etherdevice.h>
39 #include <linux/if_vlan.h> 39 #include <linux/if_vlan.h>
40 #include <linux/mdio.h> 40 #include <linux/mdio.h>
41 #include <linux/sockios.h> 41 #include <linux/sockios.h>
42 #include <linux/workqueue.h> 42 #include <linux/workqueue.h>
43 #include <linux/proc_fs.h> 43 #include <linux/proc_fs.h>
44 #include <linux/rtnetlink.h> 44 #include <linux/rtnetlink.h>
45 #include <linux/firmware.h> 45 #include <linux/firmware.h>
46 #include <linux/log2.h> 46 #include <linux/log2.h>
47 #include <asm/uaccess.h> 47 #include <asm/uaccess.h>
48 48
49 #include "common.h" 49 #include "common.h"
50 #include "cxgb3_ioctl.h" 50 #include "cxgb3_ioctl.h"
51 #include "regs.h" 51 #include "regs.h"
52 #include "cxgb3_offload.h" 52 #include "cxgb3_offload.h"
53 #include "version.h" 53 #include "version.h"
54 54
55 #include "cxgb3_ctl_defs.h" 55 #include "cxgb3_ctl_defs.h"
56 #include "t3_cpl.h" 56 #include "t3_cpl.h"
57 #include "firmware_exports.h" 57 #include "firmware_exports.h"
58 58
59 enum { 59 enum {
60 MAX_TXQ_ENTRIES = 16384, 60 MAX_TXQ_ENTRIES = 16384,
61 MAX_CTRL_TXQ_ENTRIES = 1024, 61 MAX_CTRL_TXQ_ENTRIES = 1024,
62 MAX_RSPQ_ENTRIES = 16384, 62 MAX_RSPQ_ENTRIES = 16384,
63 MAX_RX_BUFFERS = 16384, 63 MAX_RX_BUFFERS = 16384,
64 MAX_RX_JUMBO_BUFFERS = 16384, 64 MAX_RX_JUMBO_BUFFERS = 16384,
65 MIN_TXQ_ENTRIES = 4, 65 MIN_TXQ_ENTRIES = 4,
66 MIN_CTRL_TXQ_ENTRIES = 4, 66 MIN_CTRL_TXQ_ENTRIES = 4,
67 MIN_RSPQ_ENTRIES = 32, 67 MIN_RSPQ_ENTRIES = 32,
68 MIN_FL_ENTRIES = 32 68 MIN_FL_ENTRIES = 32
69 }; 69 };
70 70
71 #define PORT_MASK ((1 << MAX_NPORTS) - 1) 71 #define PORT_MASK ((1 << MAX_NPORTS) - 1)
72 72
73 #define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \ 73 #define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \
74 NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\ 74 NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\
75 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR) 75 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
76 76
77 #define EEPROM_MAGIC 0x38E2F10C 77 #define EEPROM_MAGIC 0x38E2F10C
78 78
79 #define CH_DEVICE(devid, idx) \ 79 #define CH_DEVICE(devid, idx) \
80 { PCI_VENDOR_ID_CHELSIO, devid, PCI_ANY_ID, PCI_ANY_ID, 0, 0, idx } 80 { PCI_VENDOR_ID_CHELSIO, devid, PCI_ANY_ID, PCI_ANY_ID, 0, 0, idx }
81 81
82 static const struct pci_device_id cxgb3_pci_tbl[] = { 82 static const struct pci_device_id cxgb3_pci_tbl[] = {
83 CH_DEVICE(0x20, 0), /* PE9000 */ 83 CH_DEVICE(0x20, 0), /* PE9000 */
84 CH_DEVICE(0x21, 1), /* T302E */ 84 CH_DEVICE(0x21, 1), /* T302E */
85 CH_DEVICE(0x22, 2), /* T310E */ 85 CH_DEVICE(0x22, 2), /* T310E */
86 CH_DEVICE(0x23, 3), /* T320X */ 86 CH_DEVICE(0x23, 3), /* T320X */
87 CH_DEVICE(0x24, 1), /* T302X */ 87 CH_DEVICE(0x24, 1), /* T302X */
88 CH_DEVICE(0x25, 3), /* T320E */ 88 CH_DEVICE(0x25, 3), /* T320E */
89 CH_DEVICE(0x26, 2), /* T310X */ 89 CH_DEVICE(0x26, 2), /* T310X */
90 CH_DEVICE(0x30, 2), /* T3B10 */ 90 CH_DEVICE(0x30, 2), /* T3B10 */
91 CH_DEVICE(0x31, 3), /* T3B20 */ 91 CH_DEVICE(0x31, 3), /* T3B20 */
92 CH_DEVICE(0x32, 1), /* T3B02 */ 92 CH_DEVICE(0x32, 1), /* T3B02 */
93 CH_DEVICE(0x35, 6), /* T3C20-derived T3C10 */ 93 CH_DEVICE(0x35, 6), /* T3C20-derived T3C10 */
94 CH_DEVICE(0x36, 3), /* S320E-CR */ 94 CH_DEVICE(0x36, 3), /* S320E-CR */
95 CH_DEVICE(0x37, 7), /* N320E-G2 */ 95 CH_DEVICE(0x37, 7), /* N320E-G2 */
96 {0,} 96 {0,}
97 }; 97 };
98 98
99 MODULE_DESCRIPTION(DRV_DESC); 99 MODULE_DESCRIPTION(DRV_DESC);
100 MODULE_AUTHOR("Chelsio Communications"); 100 MODULE_AUTHOR("Chelsio Communications");
101 MODULE_LICENSE("Dual BSD/GPL"); 101 MODULE_LICENSE("Dual BSD/GPL");
102 MODULE_VERSION(DRV_VERSION); 102 MODULE_VERSION(DRV_VERSION);
103 MODULE_DEVICE_TABLE(pci, cxgb3_pci_tbl); 103 MODULE_DEVICE_TABLE(pci, cxgb3_pci_tbl);
104 104
105 static int dflt_msg_enable = DFLT_MSG_ENABLE; 105 static int dflt_msg_enable = DFLT_MSG_ENABLE;
106 106
107 module_param(dflt_msg_enable, int, 0644); 107 module_param(dflt_msg_enable, int, 0644);
108 MODULE_PARM_DESC(dflt_msg_enable, "Chelsio T3 default message enable bitmap"); 108 MODULE_PARM_DESC(dflt_msg_enable, "Chelsio T3 default message enable bitmap");
109 109
110 /* 110 /*
111 * The driver uses the best interrupt scheme available on a platform in the 111 * The driver uses the best interrupt scheme available on a platform in the
112 * order MSI-X, MSI, legacy pin interrupts. This parameter determines which 112 * order MSI-X, MSI, legacy pin interrupts. This parameter determines which
113 * of these schemes the driver may consider as follows: 113 * of these schemes the driver may consider as follows:
114 * 114 *
115 * msi = 2: choose from among all three options 115 * msi = 2: choose from among all three options
116 * msi = 1: only consider MSI and pin interrupts 116 * msi = 1: only consider MSI and pin interrupts
117 * msi = 0: force pin interrupts 117 * msi = 0: force pin interrupts
118 */ 118 */
119 static int msi = 2; 119 static int msi = 2;
120 120
121 module_param(msi, int, 0644); 121 module_param(msi, int, 0644);
122 MODULE_PARM_DESC(msi, "whether to use MSI or MSI-X"); 122 MODULE_PARM_DESC(msi, "whether to use MSI or MSI-X");
123 123
124 /* 124 /*
125 * The driver enables offload as a default. 125 * The driver enables offload as a default.
126 * To disable it, use ofld_disable = 1. 126 * To disable it, use ofld_disable = 1.
127 */ 127 */
128 128
129 static int ofld_disable = 0; 129 static int ofld_disable = 0;
130 130
131 module_param(ofld_disable, int, 0644); 131 module_param(ofld_disable, int, 0644);
132 MODULE_PARM_DESC(ofld_disable, "whether to enable offload at init time or not"); 132 MODULE_PARM_DESC(ofld_disable, "whether to enable offload at init time or not");
133 133
134 /* 134 /*
135 * We have work elements that we need to cancel when an interface is taken 135 * We have work elements that we need to cancel when an interface is taken
136 * down. Normally the work elements would be executed by keventd but that 136 * down. Normally the work elements would be executed by keventd but that
137 * can deadlock because of linkwatch. If our close method takes the rtnl 137 * can deadlock because of linkwatch. If our close method takes the rtnl
138 * lock and linkwatch is ahead of our work elements in keventd, linkwatch 138 * lock and linkwatch is ahead of our work elements in keventd, linkwatch
139 * will block keventd as it needs the rtnl lock, and we'll deadlock waiting 139 * will block keventd as it needs the rtnl lock, and we'll deadlock waiting
140 * for our work to complete. Get our own work queue to solve this. 140 * for our work to complete. Get our own work queue to solve this.
141 */ 141 */
142 static struct workqueue_struct *cxgb3_wq; 142 static struct workqueue_struct *cxgb3_wq;
143 143
144 /** 144 /**
145 * link_report - show link status and link speed/duplex 145 * link_report - show link status and link speed/duplex
146 * @p: the port whose settings are to be reported 146 * @p: the port whose settings are to be reported
147 * 147 *
148 * Shows the link status, speed, and duplex of a port. 148 * Shows the link status, speed, and duplex of a port.
149 */ 149 */
150 static void link_report(struct net_device *dev) 150 static void link_report(struct net_device *dev)
151 { 151 {
152 if (!netif_carrier_ok(dev)) 152 if (!netif_carrier_ok(dev))
153 printk(KERN_INFO "%s: link down\n", dev->name); 153 printk(KERN_INFO "%s: link down\n", dev->name);
154 else { 154 else {
155 const char *s = "10Mbps"; 155 const char *s = "10Mbps";
156 const struct port_info *p = netdev_priv(dev); 156 const struct port_info *p = netdev_priv(dev);
157 157
158 switch (p->link_config.speed) { 158 switch (p->link_config.speed) {
159 case SPEED_10000: 159 case SPEED_10000:
160 s = "10Gbps"; 160 s = "10Gbps";
161 break; 161 break;
162 case SPEED_1000: 162 case SPEED_1000:
163 s = "1000Mbps"; 163 s = "1000Mbps";
164 break; 164 break;
165 case SPEED_100: 165 case SPEED_100:
166 s = "100Mbps"; 166 s = "100Mbps";
167 break; 167 break;
168 } 168 }
169 169
170 printk(KERN_INFO "%s: link up, %s, %s-duplex\n", dev->name, s, 170 printk(KERN_INFO "%s: link up, %s, %s-duplex\n", dev->name, s,
171 p->link_config.duplex == DUPLEX_FULL ? "full" : "half"); 171 p->link_config.duplex == DUPLEX_FULL ? "full" : "half");
172 } 172 }
173 } 173 }
174 174
175 void t3_os_link_fault(struct adapter *adap, int port_id, int state) 175 void t3_os_link_fault(struct adapter *adap, int port_id, int state)
176 { 176 {
177 struct net_device *dev = adap->port[port_id]; 177 struct net_device *dev = adap->port[port_id];
178 struct port_info *pi = netdev_priv(dev); 178 struct port_info *pi = netdev_priv(dev);
179 179
180 if (state == netif_carrier_ok(dev)) 180 if (state == netif_carrier_ok(dev))
181 return; 181 return;
182 182
183 if (state) { 183 if (state) {
184 struct cmac *mac = &pi->mac; 184 struct cmac *mac = &pi->mac;
185 185
186 netif_carrier_on(dev); 186 netif_carrier_on(dev);
187 187
188 /* Clear local faults */ 188 /* Clear local faults */
189 t3_xgm_intr_disable(adap, pi->port_id); 189 t3_xgm_intr_disable(adap, pi->port_id);
190 t3_read_reg(adap, A_XGM_INT_STATUS + 190 t3_read_reg(adap, A_XGM_INT_STATUS +
191 pi->mac.offset); 191 pi->mac.offset);
192 t3_write_reg(adap, 192 t3_write_reg(adap,
193 A_XGM_INT_CAUSE + pi->mac.offset, 193 A_XGM_INT_CAUSE + pi->mac.offset,
194 F_XGM_INT); 194 F_XGM_INT);
195 195
196 t3_set_reg_field(adap, 196 t3_set_reg_field(adap,
197 A_XGM_INT_ENABLE + 197 A_XGM_INT_ENABLE +
198 pi->mac.offset, 198 pi->mac.offset,
199 F_XGM_INT, F_XGM_INT); 199 F_XGM_INT, F_XGM_INT);
200 t3_xgm_intr_enable(adap, pi->port_id); 200 t3_xgm_intr_enable(adap, pi->port_id);
201 201
202 t3_mac_enable(mac, MAC_DIRECTION_TX); 202 t3_mac_enable(mac, MAC_DIRECTION_TX);
203 } else 203 } else
204 netif_carrier_off(dev); 204 netif_carrier_off(dev);
205 205
206 link_report(dev); 206 link_report(dev);
207 } 207 }
208 208
209 /** 209 /**
210 * t3_os_link_changed - handle link status changes 210 * t3_os_link_changed - handle link status changes
211 * @adapter: the adapter associated with the link change 211 * @adapter: the adapter associated with the link change
212 * @port_id: the port index whose limk status has changed 212 * @port_id: the port index whose limk status has changed
213 * @link_stat: the new status of the link 213 * @link_stat: the new status of the link
214 * @speed: the new speed setting 214 * @speed: the new speed setting
215 * @duplex: the new duplex setting 215 * @duplex: the new duplex setting
216 * @pause: the new flow-control setting 216 * @pause: the new flow-control setting
217 * 217 *
218 * This is the OS-dependent handler for link status changes. The OS 218 * This is the OS-dependent handler for link status changes. The OS
219 * neutral handler takes care of most of the processing for these events, 219 * neutral handler takes care of most of the processing for these events,
220 * then calls this handler for any OS-specific processing. 220 * then calls this handler for any OS-specific processing.
221 */ 221 */
222 void t3_os_link_changed(struct adapter *adapter, int port_id, int link_stat, 222 void t3_os_link_changed(struct adapter *adapter, int port_id, int link_stat,
223 int speed, int duplex, int pause) 223 int speed, int duplex, int pause)
224 { 224 {
225 struct net_device *dev = adapter->port[port_id]; 225 struct net_device *dev = adapter->port[port_id];
226 struct port_info *pi = netdev_priv(dev); 226 struct port_info *pi = netdev_priv(dev);
227 struct cmac *mac = &pi->mac; 227 struct cmac *mac = &pi->mac;
228 228
229 /* Skip changes from disabled ports. */ 229 /* Skip changes from disabled ports. */
230 if (!netif_running(dev)) 230 if (!netif_running(dev))
231 return; 231 return;
232 232
233 if (link_stat != netif_carrier_ok(dev)) { 233 if (link_stat != netif_carrier_ok(dev)) {
234 if (link_stat) { 234 if (link_stat) {
235 t3_mac_enable(mac, MAC_DIRECTION_RX); 235 t3_mac_enable(mac, MAC_DIRECTION_RX);
236 236
237 /* Clear local faults */ 237 /* Clear local faults */
238 t3_xgm_intr_disable(adapter, pi->port_id); 238 t3_xgm_intr_disable(adapter, pi->port_id);
239 t3_read_reg(adapter, A_XGM_INT_STATUS + 239 t3_read_reg(adapter, A_XGM_INT_STATUS +
240 pi->mac.offset); 240 pi->mac.offset);
241 t3_write_reg(adapter, 241 t3_write_reg(adapter,
242 A_XGM_INT_CAUSE + pi->mac.offset, 242 A_XGM_INT_CAUSE + pi->mac.offset,
243 F_XGM_INT); 243 F_XGM_INT);
244 244
245 t3_set_reg_field(adapter, 245 t3_set_reg_field(adapter,
246 A_XGM_INT_ENABLE + pi->mac.offset, 246 A_XGM_INT_ENABLE + pi->mac.offset,
247 F_XGM_INT, F_XGM_INT); 247 F_XGM_INT, F_XGM_INT);
248 t3_xgm_intr_enable(adapter, pi->port_id); 248 t3_xgm_intr_enable(adapter, pi->port_id);
249 249
250 netif_carrier_on(dev); 250 netif_carrier_on(dev);
251 } else { 251 } else {
252 netif_carrier_off(dev); 252 netif_carrier_off(dev);
253 253
254 t3_xgm_intr_disable(adapter, pi->port_id); 254 t3_xgm_intr_disable(adapter, pi->port_id);
255 t3_read_reg(adapter, A_XGM_INT_STATUS + pi->mac.offset); 255 t3_read_reg(adapter, A_XGM_INT_STATUS + pi->mac.offset);
256 t3_set_reg_field(adapter, 256 t3_set_reg_field(adapter,
257 A_XGM_INT_ENABLE + pi->mac.offset, 257 A_XGM_INT_ENABLE + pi->mac.offset,
258 F_XGM_INT, 0); 258 F_XGM_INT, 0);
259 259
260 if (is_10G(adapter)) 260 if (is_10G(adapter))
261 pi->phy.ops->power_down(&pi->phy, 1); 261 pi->phy.ops->power_down(&pi->phy, 1);
262 262
263 t3_read_reg(adapter, A_XGM_INT_STATUS + pi->mac.offset); 263 t3_read_reg(adapter, A_XGM_INT_STATUS + pi->mac.offset);
264 t3_mac_disable(mac, MAC_DIRECTION_RX); 264 t3_mac_disable(mac, MAC_DIRECTION_RX);
265 t3_link_start(&pi->phy, mac, &pi->link_config); 265 t3_link_start(&pi->phy, mac, &pi->link_config);
266 } 266 }
267 267
268 link_report(dev); 268 link_report(dev);
269 } 269 }
270 } 270 }
271 271
272 /** 272 /**
273 * t3_os_phymod_changed - handle PHY module changes 273 * t3_os_phymod_changed - handle PHY module changes
274 * @phy: the PHY reporting the module change 274 * @phy: the PHY reporting the module change
275 * @mod_type: new module type 275 * @mod_type: new module type
276 * 276 *
277 * This is the OS-dependent handler for PHY module changes. It is 277 * This is the OS-dependent handler for PHY module changes. It is
278 * invoked when a PHY module is removed or inserted for any OS-specific 278 * invoked when a PHY module is removed or inserted for any OS-specific
279 * processing. 279 * processing.
280 */ 280 */
281 void t3_os_phymod_changed(struct adapter *adap, int port_id) 281 void t3_os_phymod_changed(struct adapter *adap, int port_id)
282 { 282 {
283 static const char *mod_str[] = { 283 static const char *mod_str[] = {
284 NULL, "SR", "LR", "LRM", "TWINAX", "TWINAX", "unknown" 284 NULL, "SR", "LR", "LRM", "TWINAX", "TWINAX", "unknown"
285 }; 285 };
286 286
287 const struct net_device *dev = adap->port[port_id]; 287 const struct net_device *dev = adap->port[port_id];
288 const struct port_info *pi = netdev_priv(dev); 288 const struct port_info *pi = netdev_priv(dev);
289 289
290 if (pi->phy.modtype == phy_modtype_none) 290 if (pi->phy.modtype == phy_modtype_none)
291 printk(KERN_INFO "%s: PHY module unplugged\n", dev->name); 291 printk(KERN_INFO "%s: PHY module unplugged\n", dev->name);
292 else 292 else
293 printk(KERN_INFO "%s: %s PHY module inserted\n", dev->name, 293 printk(KERN_INFO "%s: %s PHY module inserted\n", dev->name,
294 mod_str[pi->phy.modtype]); 294 mod_str[pi->phy.modtype]);
295 } 295 }
296 296
297 static void cxgb_set_rxmode(struct net_device *dev) 297 static void cxgb_set_rxmode(struct net_device *dev)
298 { 298 {
299 struct t3_rx_mode rm; 299 struct t3_rx_mode rm;
300 struct port_info *pi = netdev_priv(dev); 300 struct port_info *pi = netdev_priv(dev);
301 301
302 init_rx_mode(&rm, dev, dev->mc_list); 302 init_rx_mode(&rm, dev, dev->mc_list);
303 t3_mac_set_rx_mode(&pi->mac, &rm); 303 t3_mac_set_rx_mode(&pi->mac, &rm);
304 } 304 }
305 305
306 /** 306 /**
307 * link_start - enable a port 307 * link_start - enable a port
308 * @dev: the device to enable 308 * @dev: the device to enable
309 * 309 *
310 * Performs the MAC and PHY actions needed to enable a port. 310 * Performs the MAC and PHY actions needed to enable a port.
311 */ 311 */
312 static void link_start(struct net_device *dev) 312 static void link_start(struct net_device *dev)
313 { 313 {
314 struct t3_rx_mode rm; 314 struct t3_rx_mode rm;
315 struct port_info *pi = netdev_priv(dev); 315 struct port_info *pi = netdev_priv(dev);
316 struct cmac *mac = &pi->mac; 316 struct cmac *mac = &pi->mac;
317 317
318 init_rx_mode(&rm, dev, dev->mc_list); 318 init_rx_mode(&rm, dev, dev->mc_list);
319 t3_mac_reset(mac); 319 t3_mac_reset(mac);
320 t3_mac_set_mtu(mac, dev->mtu); 320 t3_mac_set_mtu(mac, dev->mtu);
321 t3_mac_set_address(mac, 0, dev->dev_addr); 321 t3_mac_set_address(mac, 0, dev->dev_addr);
322 t3_mac_set_rx_mode(mac, &rm); 322 t3_mac_set_rx_mode(mac, &rm);
323 t3_link_start(&pi->phy, mac, &pi->link_config); 323 t3_link_start(&pi->phy, mac, &pi->link_config);
324 t3_mac_enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX); 324 t3_mac_enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX);
325 } 325 }
326 326
327 static inline void cxgb_disable_msi(struct adapter *adapter) 327 static inline void cxgb_disable_msi(struct adapter *adapter)
328 { 328 {
329 if (adapter->flags & USING_MSIX) { 329 if (adapter->flags & USING_MSIX) {
330 pci_disable_msix(adapter->pdev); 330 pci_disable_msix(adapter->pdev);
331 adapter->flags &= ~USING_MSIX; 331 adapter->flags &= ~USING_MSIX;
332 } else if (adapter->flags & USING_MSI) { 332 } else if (adapter->flags & USING_MSI) {
333 pci_disable_msi(adapter->pdev); 333 pci_disable_msi(adapter->pdev);
334 adapter->flags &= ~USING_MSI; 334 adapter->flags &= ~USING_MSI;
335 } 335 }
336 } 336 }
337 337
338 /* 338 /*
339 * Interrupt handler for asynchronous events used with MSI-X. 339 * Interrupt handler for asynchronous events used with MSI-X.
340 */ 340 */
341 static irqreturn_t t3_async_intr_handler(int irq, void *cookie) 341 static irqreturn_t t3_async_intr_handler(int irq, void *cookie)
342 { 342 {
343 t3_slow_intr_handler(cookie); 343 t3_slow_intr_handler(cookie);
344 return IRQ_HANDLED; 344 return IRQ_HANDLED;
345 } 345 }
346 346
347 /* 347 /*
348 * Name the MSI-X interrupts. 348 * Name the MSI-X interrupts.
349 */ 349 */
350 static void name_msix_vecs(struct adapter *adap) 350 static void name_msix_vecs(struct adapter *adap)
351 { 351 {
352 int i, j, msi_idx = 1, n = sizeof(adap->msix_info[0].desc) - 1; 352 int i, j, msi_idx = 1, n = sizeof(adap->msix_info[0].desc) - 1;
353 353
354 snprintf(adap->msix_info[0].desc, n, "%s", adap->name); 354 snprintf(adap->msix_info[0].desc, n, "%s", adap->name);
355 adap->msix_info[0].desc[n] = 0; 355 adap->msix_info[0].desc[n] = 0;
356 356
357 for_each_port(adap, j) { 357 for_each_port(adap, j) {
358 struct net_device *d = adap->port[j]; 358 struct net_device *d = adap->port[j];
359 const struct port_info *pi = netdev_priv(d); 359 const struct port_info *pi = netdev_priv(d);
360 360
361 for (i = 0; i < pi->nqsets; i++, msi_idx++) { 361 for (i = 0; i < pi->nqsets; i++, msi_idx++) {
362 snprintf(adap->msix_info[msi_idx].desc, n, 362 snprintf(adap->msix_info[msi_idx].desc, n,
363 "%s-%d", d->name, pi->first_qset + i); 363 "%s-%d", d->name, pi->first_qset + i);
364 adap->msix_info[msi_idx].desc[n] = 0; 364 adap->msix_info[msi_idx].desc[n] = 0;
365 } 365 }
366 } 366 }
367 } 367 }
368 368
369 static int request_msix_data_irqs(struct adapter *adap) 369 static int request_msix_data_irqs(struct adapter *adap)
370 { 370 {
371 int i, j, err, qidx = 0; 371 int i, j, err, qidx = 0;
372 372
373 for_each_port(adap, i) { 373 for_each_port(adap, i) {
374 int nqsets = adap2pinfo(adap, i)->nqsets; 374 int nqsets = adap2pinfo(adap, i)->nqsets;
375 375
376 for (j = 0; j < nqsets; ++j) { 376 for (j = 0; j < nqsets; ++j) {
377 err = request_irq(adap->msix_info[qidx + 1].vec, 377 err = request_irq(adap->msix_info[qidx + 1].vec,
378 t3_intr_handler(adap, 378 t3_intr_handler(adap,
379 adap->sge.qs[qidx]. 379 adap->sge.qs[qidx].
380 rspq.polling), 0, 380 rspq.polling), 0,
381 adap->msix_info[qidx + 1].desc, 381 adap->msix_info[qidx + 1].desc,
382 &adap->sge.qs[qidx]); 382 &adap->sge.qs[qidx]);
383 if (err) { 383 if (err) {
384 while (--qidx >= 0) 384 while (--qidx >= 0)
385 free_irq(adap->msix_info[qidx + 1].vec, 385 free_irq(adap->msix_info[qidx + 1].vec,
386 &adap->sge.qs[qidx]); 386 &adap->sge.qs[qidx]);
387 return err; 387 return err;
388 } 388 }
389 qidx++; 389 qidx++;
390 } 390 }
391 } 391 }
392 return 0; 392 return 0;
393 } 393 }
394 394
395 static void free_irq_resources(struct adapter *adapter) 395 static void free_irq_resources(struct adapter *adapter)
396 { 396 {
397 if (adapter->flags & USING_MSIX) { 397 if (adapter->flags & USING_MSIX) {
398 int i, n = 0; 398 int i, n = 0;
399 399
400 free_irq(adapter->msix_info[0].vec, adapter); 400 free_irq(adapter->msix_info[0].vec, adapter);
401 for_each_port(adapter, i) 401 for_each_port(adapter, i)
402 n += adap2pinfo(adapter, i)->nqsets; 402 n += adap2pinfo(adapter, i)->nqsets;
403 403
404 for (i = 0; i < n; ++i) 404 for (i = 0; i < n; ++i)
405 free_irq(adapter->msix_info[i + 1].vec, 405 free_irq(adapter->msix_info[i + 1].vec,
406 &adapter->sge.qs[i]); 406 &adapter->sge.qs[i]);
407 } else 407 } else
408 free_irq(adapter->pdev->irq, adapter); 408 free_irq(adapter->pdev->irq, adapter);
409 } 409 }
410 410
411 static int await_mgmt_replies(struct adapter *adap, unsigned long init_cnt, 411 static int await_mgmt_replies(struct adapter *adap, unsigned long init_cnt,
412 unsigned long n) 412 unsigned long n)
413 { 413 {
414 int attempts = 5; 414 int attempts = 5;
415 415
416 while (adap->sge.qs[0].rspq.offload_pkts < init_cnt + n) { 416 while (adap->sge.qs[0].rspq.offload_pkts < init_cnt + n) {
417 if (!--attempts) 417 if (!--attempts)
418 return -ETIMEDOUT; 418 return -ETIMEDOUT;
419 msleep(10); 419 msleep(10);
420 } 420 }
421 return 0; 421 return 0;
422 } 422 }
423 423
424 static int init_tp_parity(struct adapter *adap) 424 static int init_tp_parity(struct adapter *adap)
425 { 425 {
426 int i; 426 int i;
427 struct sk_buff *skb; 427 struct sk_buff *skb;
428 struct cpl_set_tcb_field *greq; 428 struct cpl_set_tcb_field *greq;
429 unsigned long cnt = adap->sge.qs[0].rspq.offload_pkts; 429 unsigned long cnt = adap->sge.qs[0].rspq.offload_pkts;
430 430
431 t3_tp_set_offload_mode(adap, 1); 431 t3_tp_set_offload_mode(adap, 1);
432 432
433 for (i = 0; i < 16; i++) { 433 for (i = 0; i < 16; i++) {
434 struct cpl_smt_write_req *req; 434 struct cpl_smt_write_req *req;
435 435
436 skb = alloc_skb(sizeof(*req), GFP_KERNEL); 436 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
437 if (!skb) 437 if (!skb)
438 skb = adap->nofail_skb; 438 skb = adap->nofail_skb;
439 if (!skb) 439 if (!skb)
440 goto alloc_skb_fail; 440 goto alloc_skb_fail;
441 441
442 req = (struct cpl_smt_write_req *)__skb_put(skb, sizeof(*req)); 442 req = (struct cpl_smt_write_req *)__skb_put(skb, sizeof(*req));
443 memset(req, 0, sizeof(*req)); 443 memset(req, 0, sizeof(*req));
444 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD)); 444 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
445 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_SMT_WRITE_REQ, i)); 445 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_SMT_WRITE_REQ, i));
446 req->iff = i; 446 req->iff = i;
447 t3_mgmt_tx(adap, skb); 447 t3_mgmt_tx(adap, skb);
448 if (skb == adap->nofail_skb) { 448 if (skb == adap->nofail_skb) {
449 await_mgmt_replies(adap, cnt, i + 1); 449 await_mgmt_replies(adap, cnt, i + 1);
450 adap->nofail_skb = alloc_skb(sizeof(*greq), GFP_KERNEL); 450 adap->nofail_skb = alloc_skb(sizeof(*greq), GFP_KERNEL);
451 if (!adap->nofail_skb) 451 if (!adap->nofail_skb)
452 goto alloc_skb_fail; 452 goto alloc_skb_fail;
453 } 453 }
454 } 454 }
455 455
456 for (i = 0; i < 2048; i++) { 456 for (i = 0; i < 2048; i++) {
457 struct cpl_l2t_write_req *req; 457 struct cpl_l2t_write_req *req;
458 458
459 skb = alloc_skb(sizeof(*req), GFP_KERNEL); 459 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
460 if (!skb) 460 if (!skb)
461 skb = adap->nofail_skb; 461 skb = adap->nofail_skb;
462 if (!skb) 462 if (!skb)
463 goto alloc_skb_fail; 463 goto alloc_skb_fail;
464 464
465 req = (struct cpl_l2t_write_req *)__skb_put(skb, sizeof(*req)); 465 req = (struct cpl_l2t_write_req *)__skb_put(skb, sizeof(*req));
466 memset(req, 0, sizeof(*req)); 466 memset(req, 0, sizeof(*req));
467 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD)); 467 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
468 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_L2T_WRITE_REQ, i)); 468 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_L2T_WRITE_REQ, i));
469 req->params = htonl(V_L2T_W_IDX(i)); 469 req->params = htonl(V_L2T_W_IDX(i));
470 t3_mgmt_tx(adap, skb); 470 t3_mgmt_tx(adap, skb);
471 if (skb == adap->nofail_skb) { 471 if (skb == adap->nofail_skb) {
472 await_mgmt_replies(adap, cnt, 16 + i + 1); 472 await_mgmt_replies(adap, cnt, 16 + i + 1);
473 adap->nofail_skb = alloc_skb(sizeof(*greq), GFP_KERNEL); 473 adap->nofail_skb = alloc_skb(sizeof(*greq), GFP_KERNEL);
474 if (!adap->nofail_skb) 474 if (!adap->nofail_skb)
475 goto alloc_skb_fail; 475 goto alloc_skb_fail;
476 } 476 }
477 } 477 }
478 478
479 for (i = 0; i < 2048; i++) { 479 for (i = 0; i < 2048; i++) {
480 struct cpl_rte_write_req *req; 480 struct cpl_rte_write_req *req;
481 481
482 skb = alloc_skb(sizeof(*req), GFP_KERNEL); 482 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
483 if (!skb) 483 if (!skb)
484 skb = adap->nofail_skb; 484 skb = adap->nofail_skb;
485 if (!skb) 485 if (!skb)
486 goto alloc_skb_fail; 486 goto alloc_skb_fail;
487 487
488 req = (struct cpl_rte_write_req *)__skb_put(skb, sizeof(*req)); 488 req = (struct cpl_rte_write_req *)__skb_put(skb, sizeof(*req));
489 memset(req, 0, sizeof(*req)); 489 memset(req, 0, sizeof(*req));
490 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD)); 490 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
491 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_RTE_WRITE_REQ, i)); 491 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_RTE_WRITE_REQ, i));
492 req->l2t_idx = htonl(V_L2T_W_IDX(i)); 492 req->l2t_idx = htonl(V_L2T_W_IDX(i));
493 t3_mgmt_tx(adap, skb); 493 t3_mgmt_tx(adap, skb);
494 if (skb == adap->nofail_skb) { 494 if (skb == adap->nofail_skb) {
495 await_mgmt_replies(adap, cnt, 16 + 2048 + i + 1); 495 await_mgmt_replies(adap, cnt, 16 + 2048 + i + 1);
496 adap->nofail_skb = alloc_skb(sizeof(*greq), GFP_KERNEL); 496 adap->nofail_skb = alloc_skb(sizeof(*greq), GFP_KERNEL);
497 if (!adap->nofail_skb) 497 if (!adap->nofail_skb)
498 goto alloc_skb_fail; 498 goto alloc_skb_fail;
499 } 499 }
500 } 500 }
501 501
502 skb = alloc_skb(sizeof(*greq), GFP_KERNEL); 502 skb = alloc_skb(sizeof(*greq), GFP_KERNEL);
503 if (!skb) 503 if (!skb)
504 skb = adap->nofail_skb; 504 skb = adap->nofail_skb;
505 if (!skb) 505 if (!skb)
506 goto alloc_skb_fail; 506 goto alloc_skb_fail;
507 507
508 greq = (struct cpl_set_tcb_field *)__skb_put(skb, sizeof(*greq)); 508 greq = (struct cpl_set_tcb_field *)__skb_put(skb, sizeof(*greq));
509 memset(greq, 0, sizeof(*greq)); 509 memset(greq, 0, sizeof(*greq));
510 greq->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD)); 510 greq->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
511 OPCODE_TID(greq) = htonl(MK_OPCODE_TID(CPL_SET_TCB_FIELD, 0)); 511 OPCODE_TID(greq) = htonl(MK_OPCODE_TID(CPL_SET_TCB_FIELD, 0));
512 greq->mask = cpu_to_be64(1); 512 greq->mask = cpu_to_be64(1);
513 t3_mgmt_tx(adap, skb); 513 t3_mgmt_tx(adap, skb);
514 514
515 i = await_mgmt_replies(adap, cnt, 16 + 2048 + 2048 + 1); 515 i = await_mgmt_replies(adap, cnt, 16 + 2048 + 2048 + 1);
516 if (skb == adap->nofail_skb) { 516 if (skb == adap->nofail_skb) {
517 i = await_mgmt_replies(adap, cnt, 16 + 2048 + 2048 + 1); 517 i = await_mgmt_replies(adap, cnt, 16 + 2048 + 2048 + 1);
518 adap->nofail_skb = alloc_skb(sizeof(*greq), GFP_KERNEL); 518 adap->nofail_skb = alloc_skb(sizeof(*greq), GFP_KERNEL);
519 } 519 }
520 520
521 t3_tp_set_offload_mode(adap, 0); 521 t3_tp_set_offload_mode(adap, 0);
522 return i; 522 return i;
523 523
524 alloc_skb_fail: 524 alloc_skb_fail:
525 t3_tp_set_offload_mode(adap, 0); 525 t3_tp_set_offload_mode(adap, 0);
526 return -ENOMEM; 526 return -ENOMEM;
527 } 527 }
528 528
529 /** 529 /**
530 * setup_rss - configure RSS 530 * setup_rss - configure RSS
531 * @adap: the adapter 531 * @adap: the adapter
532 * 532 *
533 * Sets up RSS to distribute packets to multiple receive queues. We 533 * Sets up RSS to distribute packets to multiple receive queues. We
534 * configure the RSS CPU lookup table to distribute to the number of HW 534 * configure the RSS CPU lookup table to distribute to the number of HW
535 * receive queues, and the response queue lookup table to narrow that 535 * receive queues, and the response queue lookup table to narrow that
536 * down to the response queues actually configured for each port. 536 * down to the response queues actually configured for each port.
537 * We always configure the RSS mapping for two ports since the mapping 537 * We always configure the RSS mapping for two ports since the mapping
538 * table has plenty of entries. 538 * table has plenty of entries.
539 */ 539 */
540 static void setup_rss(struct adapter *adap) 540 static void setup_rss(struct adapter *adap)
541 { 541 {
542 int i; 542 int i;
543 unsigned int nq0 = adap2pinfo(adap, 0)->nqsets; 543 unsigned int nq0 = adap2pinfo(adap, 0)->nqsets;
544 unsigned int nq1 = adap->port[1] ? adap2pinfo(adap, 1)->nqsets : 1; 544 unsigned int nq1 = adap->port[1] ? adap2pinfo(adap, 1)->nqsets : 1;
545 u8 cpus[SGE_QSETS + 1]; 545 u8 cpus[SGE_QSETS + 1];
546 u16 rspq_map[RSS_TABLE_SIZE]; 546 u16 rspq_map[RSS_TABLE_SIZE];
547 547
548 for (i = 0; i < SGE_QSETS; ++i) 548 for (i = 0; i < SGE_QSETS; ++i)
549 cpus[i] = i; 549 cpus[i] = i;
550 cpus[SGE_QSETS] = 0xff; /* terminator */ 550 cpus[SGE_QSETS] = 0xff; /* terminator */
551 551
552 for (i = 0; i < RSS_TABLE_SIZE / 2; ++i) { 552 for (i = 0; i < RSS_TABLE_SIZE / 2; ++i) {
553 rspq_map[i] = i % nq0; 553 rspq_map[i] = i % nq0;
554 rspq_map[i + RSS_TABLE_SIZE / 2] = (i % nq1) + nq0; 554 rspq_map[i + RSS_TABLE_SIZE / 2] = (i % nq1) + nq0;
555 } 555 }
556 556
557 t3_config_rss(adap, F_RQFEEDBACKENABLE | F_TNLLKPEN | F_TNLMAPEN | 557 t3_config_rss(adap, F_RQFEEDBACKENABLE | F_TNLLKPEN | F_TNLMAPEN |
558 F_TNLPRTEN | F_TNL2TUPEN | F_TNL4TUPEN | 558 F_TNLPRTEN | F_TNL2TUPEN | F_TNL4TUPEN |
559 V_RRCPLCPUSIZE(6) | F_HASHTOEPLITZ, cpus, rspq_map); 559 V_RRCPLCPUSIZE(6) | F_HASHTOEPLITZ, cpus, rspq_map);
560 } 560 }
561 561
562 static void init_napi(struct adapter *adap) 562 static void init_napi(struct adapter *adap)
563 { 563 {
564 int i; 564 int i;
565 565
566 for (i = 0; i < SGE_QSETS; i++) { 566 for (i = 0; i < SGE_QSETS; i++) {
567 struct sge_qset *qs = &adap->sge.qs[i]; 567 struct sge_qset *qs = &adap->sge.qs[i];
568 568
569 if (qs->adap) 569 if (qs->adap)
570 netif_napi_add(qs->netdev, &qs->napi, qs->napi.poll, 570 netif_napi_add(qs->netdev, &qs->napi, qs->napi.poll,
571 64); 571 64);
572 } 572 }
573 573
574 /* 574 /*
575 * netif_napi_add() can be called only once per napi_struct because it 575 * netif_napi_add() can be called only once per napi_struct because it
576 * adds each new napi_struct to a list. Be careful not to call it a 576 * adds each new napi_struct to a list. Be careful not to call it a
577 * second time, e.g., during EEH recovery, by making a note of it. 577 * second time, e.g., during EEH recovery, by making a note of it.
578 */ 578 */
579 adap->flags |= NAPI_INIT; 579 adap->flags |= NAPI_INIT;
580 } 580 }
581 581
582 /* 582 /*
583 * Wait until all NAPI handlers are descheduled. This includes the handlers of 583 * Wait until all NAPI handlers are descheduled. This includes the handlers of
584 * both netdevices representing interfaces and the dummy ones for the extra 584 * both netdevices representing interfaces and the dummy ones for the extra
585 * queues. 585 * queues.
586 */ 586 */
587 static void quiesce_rx(struct adapter *adap) 587 static void quiesce_rx(struct adapter *adap)
588 { 588 {
589 int i; 589 int i;
590 590
591 for (i = 0; i < SGE_QSETS; i++) 591 for (i = 0; i < SGE_QSETS; i++)
592 if (adap->sge.qs[i].adap) 592 if (adap->sge.qs[i].adap)
593 napi_disable(&adap->sge.qs[i].napi); 593 napi_disable(&adap->sge.qs[i].napi);
594 } 594 }
595 595
596 static void enable_all_napi(struct adapter *adap) 596 static void enable_all_napi(struct adapter *adap)
597 { 597 {
598 int i; 598 int i;
599 for (i = 0; i < SGE_QSETS; i++) 599 for (i = 0; i < SGE_QSETS; i++)
600 if (adap->sge.qs[i].adap) 600 if (adap->sge.qs[i].adap)
601 napi_enable(&adap->sge.qs[i].napi); 601 napi_enable(&adap->sge.qs[i].napi);
602 } 602 }
603 603
604 /** 604 /**
605 * set_qset_lro - Turn a queue set's LRO capability on and off 605 * set_qset_lro - Turn a queue set's LRO capability on and off
606 * @dev: the device the qset is attached to 606 * @dev: the device the qset is attached to
607 * @qset_idx: the queue set index 607 * @qset_idx: the queue set index
608 * @val: the LRO switch 608 * @val: the LRO switch
609 * 609 *
610 * Sets LRO on or off for a particular queue set. 610 * Sets LRO on or off for a particular queue set.
611 * the device's features flag is updated to reflect the LRO 611 * the device's features flag is updated to reflect the LRO
612 * capability when all queues belonging to the device are 612 * capability when all queues belonging to the device are
613 * in the same state. 613 * in the same state.
614 */ 614 */
615 static void set_qset_lro(struct net_device *dev, int qset_idx, int val) 615 static void set_qset_lro(struct net_device *dev, int qset_idx, int val)
616 { 616 {
617 struct port_info *pi = netdev_priv(dev); 617 struct port_info *pi = netdev_priv(dev);
618 struct adapter *adapter = pi->adapter; 618 struct adapter *adapter = pi->adapter;
619 619
620 adapter->params.sge.qset[qset_idx].lro = !!val; 620 adapter->params.sge.qset[qset_idx].lro = !!val;
621 adapter->sge.qs[qset_idx].lro_enabled = !!val; 621 adapter->sge.qs[qset_idx].lro_enabled = !!val;
622 } 622 }
623 623
624 /** 624 /**
625 * setup_sge_qsets - configure SGE Tx/Rx/response queues 625 * setup_sge_qsets - configure SGE Tx/Rx/response queues
626 * @adap: the adapter 626 * @adap: the adapter
627 * 627 *
628 * Determines how many sets of SGE queues to use and initializes them. 628 * Determines how many sets of SGE queues to use and initializes them.
629 * We support multiple queue sets per port if we have MSI-X, otherwise 629 * We support multiple queue sets per port if we have MSI-X, otherwise
630 * just one queue set per port. 630 * just one queue set per port.
631 */ 631 */
632 static int setup_sge_qsets(struct adapter *adap) 632 static int setup_sge_qsets(struct adapter *adap)
633 { 633 {
634 int i, j, err, irq_idx = 0, qset_idx = 0; 634 int i, j, err, irq_idx = 0, qset_idx = 0;
635 unsigned int ntxq = SGE_TXQ_PER_SET; 635 unsigned int ntxq = SGE_TXQ_PER_SET;
636 636
637 if (adap->params.rev > 0 && !(adap->flags & USING_MSI)) 637 if (adap->params.rev > 0 && !(adap->flags & USING_MSI))
638 irq_idx = -1; 638 irq_idx = -1;
639 639
640 for_each_port(adap, i) { 640 for_each_port(adap, i) {
641 struct net_device *dev = adap->port[i]; 641 struct net_device *dev = adap->port[i];
642 struct port_info *pi = netdev_priv(dev); 642 struct port_info *pi = netdev_priv(dev);
643 643
644 pi->qs = &adap->sge.qs[pi->first_qset]; 644 pi->qs = &adap->sge.qs[pi->first_qset];
645 for (j = pi->first_qset; j < pi->first_qset + pi->nqsets; 645 for (j = pi->first_qset; j < pi->first_qset + pi->nqsets;
646 ++j, ++qset_idx) { 646 ++j, ++qset_idx) {
647 set_qset_lro(dev, qset_idx, pi->rx_offload & T3_LRO); 647 set_qset_lro(dev, qset_idx, pi->rx_offload & T3_LRO);
648 err = t3_sge_alloc_qset(adap, qset_idx, 1, 648 err = t3_sge_alloc_qset(adap, qset_idx, 1,
649 (adap->flags & USING_MSIX) ? qset_idx + 1 : 649 (adap->flags & USING_MSIX) ? qset_idx + 1 :
650 irq_idx, 650 irq_idx,
651 &adap->params.sge.qset[qset_idx], ntxq, dev, 651 &adap->params.sge.qset[qset_idx], ntxq, dev,
652 netdev_get_tx_queue(dev, j)); 652 netdev_get_tx_queue(dev, j));
653 if (err) { 653 if (err) {
654 t3_free_sge_resources(adap); 654 t3_free_sge_resources(adap);
655 return err; 655 return err;
656 } 656 }
657 } 657 }
658 } 658 }
659 659
660 return 0; 660 return 0;
661 } 661 }
662 662
663 static ssize_t attr_show(struct device *d, char *buf, 663 static ssize_t attr_show(struct device *d, char *buf,
664 ssize_t(*format) (struct net_device *, char *)) 664 ssize_t(*format) (struct net_device *, char *))
665 { 665 {
666 ssize_t len; 666 ssize_t len;
667 667
668 /* Synchronize with ioctls that may shut down the device */ 668 /* Synchronize with ioctls that may shut down the device */
669 rtnl_lock(); 669 rtnl_lock();
670 len = (*format) (to_net_dev(d), buf); 670 len = (*format) (to_net_dev(d), buf);
671 rtnl_unlock(); 671 rtnl_unlock();
672 return len; 672 return len;
673 } 673 }
674 674
675 static ssize_t attr_store(struct device *d, 675 static ssize_t attr_store(struct device *d,
676 const char *buf, size_t len, 676 const char *buf, size_t len,
677 ssize_t(*set) (struct net_device *, unsigned int), 677 ssize_t(*set) (struct net_device *, unsigned int),
678 unsigned int min_val, unsigned int max_val) 678 unsigned int min_val, unsigned int max_val)
679 { 679 {
680 char *endp; 680 char *endp;
681 ssize_t ret; 681 ssize_t ret;
682 unsigned int val; 682 unsigned int val;
683 683
684 if (!capable(CAP_NET_ADMIN)) 684 if (!capable(CAP_NET_ADMIN))
685 return -EPERM; 685 return -EPERM;
686 686
687 val = simple_strtoul(buf, &endp, 0); 687 val = simple_strtoul(buf, &endp, 0);
688 if (endp == buf || val < min_val || val > max_val) 688 if (endp == buf || val < min_val || val > max_val)
689 return -EINVAL; 689 return -EINVAL;
690 690
691 rtnl_lock(); 691 rtnl_lock();
692 ret = (*set) (to_net_dev(d), val); 692 ret = (*set) (to_net_dev(d), val);
693 if (!ret) 693 if (!ret)
694 ret = len; 694 ret = len;
695 rtnl_unlock(); 695 rtnl_unlock();
696 return ret; 696 return ret;
697 } 697 }
698 698
699 #define CXGB3_SHOW(name, val_expr) \ 699 #define CXGB3_SHOW(name, val_expr) \
700 static ssize_t format_##name(struct net_device *dev, char *buf) \ 700 static ssize_t format_##name(struct net_device *dev, char *buf) \
701 { \ 701 { \
702 struct port_info *pi = netdev_priv(dev); \ 702 struct port_info *pi = netdev_priv(dev); \
703 struct adapter *adap = pi->adapter; \ 703 struct adapter *adap = pi->adapter; \
704 return sprintf(buf, "%u\n", val_expr); \ 704 return sprintf(buf, "%u\n", val_expr); \
705 } \ 705 } \
706 static ssize_t show_##name(struct device *d, struct device_attribute *attr, \ 706 static ssize_t show_##name(struct device *d, struct device_attribute *attr, \
707 char *buf) \ 707 char *buf) \
708 { \ 708 { \
709 return attr_show(d, buf, format_##name); \ 709 return attr_show(d, buf, format_##name); \
710 } 710 }
711 711
712 static ssize_t set_nfilters(struct net_device *dev, unsigned int val) 712 static ssize_t set_nfilters(struct net_device *dev, unsigned int val)
713 { 713 {
714 struct port_info *pi = netdev_priv(dev); 714 struct port_info *pi = netdev_priv(dev);
715 struct adapter *adap = pi->adapter; 715 struct adapter *adap = pi->adapter;
716 int min_tids = is_offload(adap) ? MC5_MIN_TIDS : 0; 716 int min_tids = is_offload(adap) ? MC5_MIN_TIDS : 0;
717 717
718 if (adap->flags & FULL_INIT_DONE) 718 if (adap->flags & FULL_INIT_DONE)
719 return -EBUSY; 719 return -EBUSY;
720 if (val && adap->params.rev == 0) 720 if (val && adap->params.rev == 0)
721 return -EINVAL; 721 return -EINVAL;
722 if (val > t3_mc5_size(&adap->mc5) - adap->params.mc5.nservers - 722 if (val > t3_mc5_size(&adap->mc5) - adap->params.mc5.nservers -
723 min_tids) 723 min_tids)
724 return -EINVAL; 724 return -EINVAL;
725 adap->params.mc5.nfilters = val; 725 adap->params.mc5.nfilters = val;
726 return 0; 726 return 0;
727 } 727 }
728 728
729 static ssize_t store_nfilters(struct device *d, struct device_attribute *attr, 729 static ssize_t store_nfilters(struct device *d, struct device_attribute *attr,
730 const char *buf, size_t len) 730 const char *buf, size_t len)
731 { 731 {
732 return attr_store(d, buf, len, set_nfilters, 0, ~0); 732 return attr_store(d, buf, len, set_nfilters, 0, ~0);
733 } 733 }
734 734
735 static ssize_t set_nservers(struct net_device *dev, unsigned int val) 735 static ssize_t set_nservers(struct net_device *dev, unsigned int val)
736 { 736 {
737 struct port_info *pi = netdev_priv(dev); 737 struct port_info *pi = netdev_priv(dev);
738 struct adapter *adap = pi->adapter; 738 struct adapter *adap = pi->adapter;
739 739
740 if (adap->flags & FULL_INIT_DONE) 740 if (adap->flags & FULL_INIT_DONE)
741 return -EBUSY; 741 return -EBUSY;
742 if (val > t3_mc5_size(&adap->mc5) - adap->params.mc5.nfilters - 742 if (val > t3_mc5_size(&adap->mc5) - adap->params.mc5.nfilters -
743 MC5_MIN_TIDS) 743 MC5_MIN_TIDS)
744 return -EINVAL; 744 return -EINVAL;
745 adap->params.mc5.nservers = val; 745 adap->params.mc5.nservers = val;
746 return 0; 746 return 0;
747 } 747 }
748 748
749 static ssize_t store_nservers(struct device *d, struct device_attribute *attr, 749 static ssize_t store_nservers(struct device *d, struct device_attribute *attr,
750 const char *buf, size_t len) 750 const char *buf, size_t len)
751 { 751 {
752 return attr_store(d, buf, len, set_nservers, 0, ~0); 752 return attr_store(d, buf, len, set_nservers, 0, ~0);
753 } 753 }
754 754
755 #define CXGB3_ATTR_R(name, val_expr) \ 755 #define CXGB3_ATTR_R(name, val_expr) \
756 CXGB3_SHOW(name, val_expr) \ 756 CXGB3_SHOW(name, val_expr) \
757 static DEVICE_ATTR(name, S_IRUGO, show_##name, NULL) 757 static DEVICE_ATTR(name, S_IRUGO, show_##name, NULL)
758 758
759 #define CXGB3_ATTR_RW(name, val_expr, store_method) \ 759 #define CXGB3_ATTR_RW(name, val_expr, store_method) \
760 CXGB3_SHOW(name, val_expr) \ 760 CXGB3_SHOW(name, val_expr) \
761 static DEVICE_ATTR(name, S_IRUGO | S_IWUSR, show_##name, store_method) 761 static DEVICE_ATTR(name, S_IRUGO | S_IWUSR, show_##name, store_method)
762 762
763 CXGB3_ATTR_R(cam_size, t3_mc5_size(&adap->mc5)); 763 CXGB3_ATTR_R(cam_size, t3_mc5_size(&adap->mc5));
764 CXGB3_ATTR_RW(nfilters, adap->params.mc5.nfilters, store_nfilters); 764 CXGB3_ATTR_RW(nfilters, adap->params.mc5.nfilters, store_nfilters);
765 CXGB3_ATTR_RW(nservers, adap->params.mc5.nservers, store_nservers); 765 CXGB3_ATTR_RW(nservers, adap->params.mc5.nservers, store_nservers);
766 766
767 static struct attribute *cxgb3_attrs[] = { 767 static struct attribute *cxgb3_attrs[] = {
768 &dev_attr_cam_size.attr, 768 &dev_attr_cam_size.attr,
769 &dev_attr_nfilters.attr, 769 &dev_attr_nfilters.attr,
770 &dev_attr_nservers.attr, 770 &dev_attr_nservers.attr,
771 NULL 771 NULL
772 }; 772 };
773 773
774 static struct attribute_group cxgb3_attr_group = {.attrs = cxgb3_attrs }; 774 static struct attribute_group cxgb3_attr_group = {.attrs = cxgb3_attrs };
775 775
776 static ssize_t tm_attr_show(struct device *d, 776 static ssize_t tm_attr_show(struct device *d,
777 char *buf, int sched) 777 char *buf, int sched)
778 { 778 {
779 struct port_info *pi = netdev_priv(to_net_dev(d)); 779 struct port_info *pi = netdev_priv(to_net_dev(d));
780 struct adapter *adap = pi->adapter; 780 struct adapter *adap = pi->adapter;
781 unsigned int v, addr, bpt, cpt; 781 unsigned int v, addr, bpt, cpt;
782 ssize_t len; 782 ssize_t len;
783 783
784 addr = A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2; 784 addr = A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2;
785 rtnl_lock(); 785 rtnl_lock();
786 t3_write_reg(adap, A_TP_TM_PIO_ADDR, addr); 786 t3_write_reg(adap, A_TP_TM_PIO_ADDR, addr);
787 v = t3_read_reg(adap, A_TP_TM_PIO_DATA); 787 v = t3_read_reg(adap, A_TP_TM_PIO_DATA);
788 if (sched & 1) 788 if (sched & 1)
789 v >>= 16; 789 v >>= 16;
790 bpt = (v >> 8) & 0xff; 790 bpt = (v >> 8) & 0xff;
791 cpt = v & 0xff; 791 cpt = v & 0xff;
792 if (!cpt) 792 if (!cpt)
793 len = sprintf(buf, "disabled\n"); 793 len = sprintf(buf, "disabled\n");
794 else { 794 else {
795 v = (adap->params.vpd.cclk * 1000) / cpt; 795 v = (adap->params.vpd.cclk * 1000) / cpt;
796 len = sprintf(buf, "%u Kbps\n", (v * bpt) / 125); 796 len = sprintf(buf, "%u Kbps\n", (v * bpt) / 125);
797 } 797 }
798 rtnl_unlock(); 798 rtnl_unlock();
799 return len; 799 return len;
800 } 800 }
801 801
802 static ssize_t tm_attr_store(struct device *d, 802 static ssize_t tm_attr_store(struct device *d,
803 const char *buf, size_t len, int sched) 803 const char *buf, size_t len, int sched)
804 { 804 {
805 struct port_info *pi = netdev_priv(to_net_dev(d)); 805 struct port_info *pi = netdev_priv(to_net_dev(d));
806 struct adapter *adap = pi->adapter; 806 struct adapter *adap = pi->adapter;
807 unsigned int val; 807 unsigned int val;
808 char *endp; 808 char *endp;
809 ssize_t ret; 809 ssize_t ret;
810 810
811 if (!capable(CAP_NET_ADMIN)) 811 if (!capable(CAP_NET_ADMIN))
812 return -EPERM; 812 return -EPERM;
813 813
814 val = simple_strtoul(buf, &endp, 0); 814 val = simple_strtoul(buf, &endp, 0);
815 if (endp == buf || val > 10000000) 815 if (endp == buf || val > 10000000)
816 return -EINVAL; 816 return -EINVAL;
817 817
818 rtnl_lock(); 818 rtnl_lock();
819 ret = t3_config_sched(adap, val, sched); 819 ret = t3_config_sched(adap, val, sched);
820 if (!ret) 820 if (!ret)
821 ret = len; 821 ret = len;
822 rtnl_unlock(); 822 rtnl_unlock();
823 return ret; 823 return ret;
824 } 824 }
825 825
826 #define TM_ATTR(name, sched) \ 826 #define TM_ATTR(name, sched) \
827 static ssize_t show_##name(struct device *d, struct device_attribute *attr, \ 827 static ssize_t show_##name(struct device *d, struct device_attribute *attr, \
828 char *buf) \ 828 char *buf) \
829 { \ 829 { \
830 return tm_attr_show(d, buf, sched); \ 830 return tm_attr_show(d, buf, sched); \
831 } \ 831 } \
832 static ssize_t store_##name(struct device *d, struct device_attribute *attr, \ 832 static ssize_t store_##name(struct device *d, struct device_attribute *attr, \
833 const char *buf, size_t len) \ 833 const char *buf, size_t len) \
834 { \ 834 { \
835 return tm_attr_store(d, buf, len, sched); \ 835 return tm_attr_store(d, buf, len, sched); \
836 } \ 836 } \
837 static DEVICE_ATTR(name, S_IRUGO | S_IWUSR, show_##name, store_##name) 837 static DEVICE_ATTR(name, S_IRUGO | S_IWUSR, show_##name, store_##name)
838 838
839 TM_ATTR(sched0, 0); 839 TM_ATTR(sched0, 0);
840 TM_ATTR(sched1, 1); 840 TM_ATTR(sched1, 1);
841 TM_ATTR(sched2, 2); 841 TM_ATTR(sched2, 2);
842 TM_ATTR(sched3, 3); 842 TM_ATTR(sched3, 3);
843 TM_ATTR(sched4, 4); 843 TM_ATTR(sched4, 4);
844 TM_ATTR(sched5, 5); 844 TM_ATTR(sched5, 5);
845 TM_ATTR(sched6, 6); 845 TM_ATTR(sched6, 6);
846 TM_ATTR(sched7, 7); 846 TM_ATTR(sched7, 7);
847 847
848 static struct attribute *offload_attrs[] = { 848 static struct attribute *offload_attrs[] = {
849 &dev_attr_sched0.attr, 849 &dev_attr_sched0.attr,
850 &dev_attr_sched1.attr, 850 &dev_attr_sched1.attr,
851 &dev_attr_sched2.attr, 851 &dev_attr_sched2.attr,
852 &dev_attr_sched3.attr, 852 &dev_attr_sched3.attr,
853 &dev_attr_sched4.attr, 853 &dev_attr_sched4.attr,
854 &dev_attr_sched5.attr, 854 &dev_attr_sched5.attr,
855 &dev_attr_sched6.attr, 855 &dev_attr_sched6.attr,
856 &dev_attr_sched7.attr, 856 &dev_attr_sched7.attr,
857 NULL 857 NULL
858 }; 858 };
859 859
860 static struct attribute_group offload_attr_group = {.attrs = offload_attrs }; 860 static struct attribute_group offload_attr_group = {.attrs = offload_attrs };
861 861
862 /* 862 /*
863 * Sends an sk_buff to an offload queue driver 863 * Sends an sk_buff to an offload queue driver
864 * after dealing with any active network taps. 864 * after dealing with any active network taps.
865 */ 865 */
866 static inline int offload_tx(struct t3cdev *tdev, struct sk_buff *skb) 866 static inline int offload_tx(struct t3cdev *tdev, struct sk_buff *skb)
867 { 867 {
868 int ret; 868 int ret;
869 869
870 local_bh_disable(); 870 local_bh_disable();
871 ret = t3_offload_tx(tdev, skb); 871 ret = t3_offload_tx(tdev, skb);
872 local_bh_enable(); 872 local_bh_enable();
873 return ret; 873 return ret;
874 } 874 }
875 875
876 static int write_smt_entry(struct adapter *adapter, int idx) 876 static int write_smt_entry(struct adapter *adapter, int idx)
877 { 877 {
878 struct cpl_smt_write_req *req; 878 struct cpl_smt_write_req *req;
879 struct sk_buff *skb = alloc_skb(sizeof(*req), GFP_KERNEL); 879 struct sk_buff *skb = alloc_skb(sizeof(*req), GFP_KERNEL);
880 880
881 if (!skb) 881 if (!skb)
882 return -ENOMEM; 882 return -ENOMEM;
883 883
884 req = (struct cpl_smt_write_req *)__skb_put(skb, sizeof(*req)); 884 req = (struct cpl_smt_write_req *)__skb_put(skb, sizeof(*req));
885 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD)); 885 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
886 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_SMT_WRITE_REQ, idx)); 886 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_SMT_WRITE_REQ, idx));
887 req->mtu_idx = NMTUS - 1; /* should be 0 but there's a T3 bug */ 887 req->mtu_idx = NMTUS - 1; /* should be 0 but there's a T3 bug */
888 req->iff = idx; 888 req->iff = idx;
889 memset(req->src_mac1, 0, sizeof(req->src_mac1)); 889 memset(req->src_mac1, 0, sizeof(req->src_mac1));
890 memcpy(req->src_mac0, adapter->port[idx]->dev_addr, ETH_ALEN); 890 memcpy(req->src_mac0, adapter->port[idx]->dev_addr, ETH_ALEN);
891 skb->priority = 1; 891 skb->priority = 1;
892 offload_tx(&adapter->tdev, skb); 892 offload_tx(&adapter->tdev, skb);
893 return 0; 893 return 0;
894 } 894 }
895 895
896 static int init_smt(struct adapter *adapter) 896 static int init_smt(struct adapter *adapter)
897 { 897 {
898 int i; 898 int i;
899 899
900 for_each_port(adapter, i) 900 for_each_port(adapter, i)
901 write_smt_entry(adapter, i); 901 write_smt_entry(adapter, i);
902 return 0; 902 return 0;
903 } 903 }
904 904
905 static void init_port_mtus(struct adapter *adapter) 905 static void init_port_mtus(struct adapter *adapter)
906 { 906 {
907 unsigned int mtus = adapter->port[0]->mtu; 907 unsigned int mtus = adapter->port[0]->mtu;
908 908
909 if (adapter->port[1]) 909 if (adapter->port[1])
910 mtus |= adapter->port[1]->mtu << 16; 910 mtus |= adapter->port[1]->mtu << 16;
911 t3_write_reg(adapter, A_TP_MTU_PORT_TABLE, mtus); 911 t3_write_reg(adapter, A_TP_MTU_PORT_TABLE, mtus);
912 } 912 }
913 913
914 static int send_pktsched_cmd(struct adapter *adap, int sched, int qidx, int lo, 914 static int send_pktsched_cmd(struct adapter *adap, int sched, int qidx, int lo,
915 int hi, int port) 915 int hi, int port)
916 { 916 {
917 struct sk_buff *skb; 917 struct sk_buff *skb;
918 struct mngt_pktsched_wr *req; 918 struct mngt_pktsched_wr *req;
919 int ret; 919 int ret;
920 920
921 skb = alloc_skb(sizeof(*req), GFP_KERNEL); 921 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
922 if (!skb) 922 if (!skb)
923 skb = adap->nofail_skb; 923 skb = adap->nofail_skb;
924 if (!skb) 924 if (!skb)
925 return -ENOMEM; 925 return -ENOMEM;
926 926
927 req = (struct mngt_pktsched_wr *)skb_put(skb, sizeof(*req)); 927 req = (struct mngt_pktsched_wr *)skb_put(skb, sizeof(*req));
928 req->wr_hi = htonl(V_WR_OP(FW_WROPCODE_MNGT)); 928 req->wr_hi = htonl(V_WR_OP(FW_WROPCODE_MNGT));
929 req->mngt_opcode = FW_MNGTOPCODE_PKTSCHED_SET; 929 req->mngt_opcode = FW_MNGTOPCODE_PKTSCHED_SET;
930 req->sched = sched; 930 req->sched = sched;
931 req->idx = qidx; 931 req->idx = qidx;
932 req->min = lo; 932 req->min = lo;
933 req->max = hi; 933 req->max = hi;
934 req->binding = port; 934 req->binding = port;
935 ret = t3_mgmt_tx(adap, skb); 935 ret = t3_mgmt_tx(adap, skb);
936 if (skb == adap->nofail_skb) { 936 if (skb == adap->nofail_skb) {
937 adap->nofail_skb = alloc_skb(sizeof(struct cpl_set_tcb_field), 937 adap->nofail_skb = alloc_skb(sizeof(struct cpl_set_tcb_field),
938 GFP_KERNEL); 938 GFP_KERNEL);
939 if (!adap->nofail_skb) 939 if (!adap->nofail_skb)
940 ret = -ENOMEM; 940 ret = -ENOMEM;
941 } 941 }
942 942
943 return ret; 943 return ret;
944 } 944 }
945 945
946 static int bind_qsets(struct adapter *adap) 946 static int bind_qsets(struct adapter *adap)
947 { 947 {
948 int i, j, err = 0; 948 int i, j, err = 0;
949 949
950 for_each_port(adap, i) { 950 for_each_port(adap, i) {
951 const struct port_info *pi = adap2pinfo(adap, i); 951 const struct port_info *pi = adap2pinfo(adap, i);
952 952
953 for (j = 0; j < pi->nqsets; ++j) { 953 for (j = 0; j < pi->nqsets; ++j) {
954 int ret = send_pktsched_cmd(adap, 1, 954 int ret = send_pktsched_cmd(adap, 1,
955 pi->first_qset + j, -1, 955 pi->first_qset + j, -1,
956 -1, i); 956 -1, i);
957 if (ret) 957 if (ret)
958 err = ret; 958 err = ret;
959 } 959 }
960 } 960 }
961 961
962 return err; 962 return err;
963 } 963 }
964 964
965 #define FW_FNAME "cxgb3/t3fw-%d.%d.%d.bin" 965 #define FW_FNAME "cxgb3/t3fw-%d.%d.%d.bin"
966 #define TPSRAM_NAME "cxgb3/t3%c_psram-%d.%d.%d.bin" 966 #define TPSRAM_NAME "cxgb3/t3%c_psram-%d.%d.%d.bin"
967 #define AEL2005_OPT_EDC_NAME "cxgb3/ael2005_opt_edc.bin"
968 #define AEL2005_TWX_EDC_NAME "cxgb3/ael2005_twx_edc.bin"
969 #define AEL2020_TWX_EDC_NAME "cxgb3/ael2005_twx_edc.bin"
970
971 static inline const char *get_edc_fw_name(int edc_idx)
972 {
973 const char *fw_name = NULL;
974
975 switch (edc_idx) {
976 case EDC_OPT_AEL2005:
977 fw_name = AEL2005_OPT_EDC_NAME;
978 break;
979 case EDC_TWX_AEL2005:
980 fw_name = AEL2005_TWX_EDC_NAME;
981 break;
982 case EDC_TWX_AEL2020:
983 fw_name = AEL2020_TWX_EDC_NAME;
984 break;
985 }
986 return fw_name;
987 }
988
989 int t3_get_edc_fw(struct cphy *phy, int edc_idx, int size)
990 {
991 struct adapter *adapter = phy->adapter;
992 const struct firmware *fw;
993 char buf[64];
994 u32 csum;
995 const __be32 *p;
996 u16 *cache = phy->phy_cache;
997 int i, ret;
998
999 snprintf(buf, sizeof(buf), get_edc_fw_name(edc_idx));
1000
1001 ret = request_firmware(&fw, buf, &adapter->pdev->dev);
1002 if (ret < 0) {
1003 dev_err(&adapter->pdev->dev,
1004 "could not upgrade firmware: unable to load %s\n",
1005 buf);
1006 return ret;
1007 }
1008
1009 /* check size, take checksum in account */
1010 if (fw->size > size + 4) {
1011 CH_ERR(adapter, "firmware image too large %u, expected %d\n",
1012 (unsigned int)fw->size, size + 4);
1013 ret = -EINVAL;
1014 }
1015
1016 /* compute checksum */
1017 p = (const __be32 *)fw->data;
1018 for (csum = 0, i = 0; i < fw->size / sizeof(csum); i++)
1019 csum += ntohl(p[i]);
1020
1021 if (csum != 0xffffffff) {
1022 CH_ERR(adapter, "corrupted firmware image, checksum %u\n",
1023 csum);
1024 ret = -EINVAL;
1025 }
1026
1027 for (i = 0; i < size / 4 ; i++) {
1028 *cache++ = (be32_to_cpu(p[i]) & 0xffff0000) >> 16;
1029 *cache++ = be32_to_cpu(p[i]) & 0xffff;
1030 }
1031
1032 release_firmware(fw);
1033
1034 return ret;
1035 }
967 1036
968 static int upgrade_fw(struct adapter *adap) 1037 static int upgrade_fw(struct adapter *adap)
969 { 1038 {
970 int ret; 1039 int ret;
971 char buf[64]; 1040 char buf[64];
972 const struct firmware *fw; 1041 const struct firmware *fw;
973 struct device *dev = &adap->pdev->dev; 1042 struct device *dev = &adap->pdev->dev;
974 1043
975 snprintf(buf, sizeof(buf), FW_FNAME, FW_VERSION_MAJOR, 1044 snprintf(buf, sizeof(buf), FW_FNAME, FW_VERSION_MAJOR,
976 FW_VERSION_MINOR, FW_VERSION_MICRO); 1045 FW_VERSION_MINOR, FW_VERSION_MICRO);
977 ret = request_firmware(&fw, buf, dev); 1046 ret = request_firmware(&fw, buf, dev);
978 if (ret < 0) { 1047 if (ret < 0) {
979 dev_err(dev, "could not upgrade firmware: unable to load %s\n", 1048 dev_err(dev, "could not upgrade firmware: unable to load %s\n",
980 buf); 1049 buf);
981 return ret; 1050 return ret;
982 } 1051 }
983 ret = t3_load_fw(adap, fw->data, fw->size); 1052 ret = t3_load_fw(adap, fw->data, fw->size);
984 release_firmware(fw); 1053 release_firmware(fw);
985 1054
986 if (ret == 0) 1055 if (ret == 0)
987 dev_info(dev, "successful upgrade to firmware %d.%d.%d\n", 1056 dev_info(dev, "successful upgrade to firmware %d.%d.%d\n",
988 FW_VERSION_MAJOR, FW_VERSION_MINOR, FW_VERSION_MICRO); 1057 FW_VERSION_MAJOR, FW_VERSION_MINOR, FW_VERSION_MICRO);
989 else 1058 else
990 dev_err(dev, "failed to upgrade to firmware %d.%d.%d\n", 1059 dev_err(dev, "failed to upgrade to firmware %d.%d.%d\n",
991 FW_VERSION_MAJOR, FW_VERSION_MINOR, FW_VERSION_MICRO); 1060 FW_VERSION_MAJOR, FW_VERSION_MINOR, FW_VERSION_MICRO);
992 1061
993 return ret; 1062 return ret;
994 } 1063 }
995 1064
996 static inline char t3rev2char(struct adapter *adapter) 1065 static inline char t3rev2char(struct adapter *adapter)
997 { 1066 {
998 char rev = 0; 1067 char rev = 0;
999 1068
1000 switch(adapter->params.rev) { 1069 switch(adapter->params.rev) {
1001 case T3_REV_B: 1070 case T3_REV_B:
1002 case T3_REV_B2: 1071 case T3_REV_B2:
1003 rev = 'b'; 1072 rev = 'b';
1004 break; 1073 break;
1005 case T3_REV_C: 1074 case T3_REV_C:
1006 rev = 'c'; 1075 rev = 'c';
1007 break; 1076 break;
1008 } 1077 }
1009 return rev; 1078 return rev;
1010 } 1079 }
1011 1080
1012 static int update_tpsram(struct adapter *adap) 1081 static int update_tpsram(struct adapter *adap)
1013 { 1082 {
1014 const struct firmware *tpsram; 1083 const struct firmware *tpsram;
1015 char buf[64]; 1084 char buf[64];
1016 struct device *dev = &adap->pdev->dev; 1085 struct device *dev = &adap->pdev->dev;
1017 int ret; 1086 int ret;
1018 char rev; 1087 char rev;
1019 1088
1020 rev = t3rev2char(adap); 1089 rev = t3rev2char(adap);
1021 if (!rev) 1090 if (!rev)
1022 return 0; 1091 return 0;
1023 1092
1024 snprintf(buf, sizeof(buf), TPSRAM_NAME, rev, 1093 snprintf(buf, sizeof(buf), TPSRAM_NAME, rev,
1025 TP_VERSION_MAJOR, TP_VERSION_MINOR, TP_VERSION_MICRO); 1094 TP_VERSION_MAJOR, TP_VERSION_MINOR, TP_VERSION_MICRO);
1026 1095
1027 ret = request_firmware(&tpsram, buf, dev); 1096 ret = request_firmware(&tpsram, buf, dev);
1028 if (ret < 0) { 1097 if (ret < 0) {
1029 dev_err(dev, "could not load TP SRAM: unable to load %s\n", 1098 dev_err(dev, "could not load TP SRAM: unable to load %s\n",
1030 buf); 1099 buf);
1031 return ret; 1100 return ret;
1032 } 1101 }
1033 1102
1034 ret = t3_check_tpsram(adap, tpsram->data, tpsram->size); 1103 ret = t3_check_tpsram(adap, tpsram->data, tpsram->size);
1035 if (ret) 1104 if (ret)
1036 goto release_tpsram; 1105 goto release_tpsram;
1037 1106
1038 ret = t3_set_proto_sram(adap, tpsram->data); 1107 ret = t3_set_proto_sram(adap, tpsram->data);
1039 if (ret == 0) 1108 if (ret == 0)
1040 dev_info(dev, 1109 dev_info(dev,
1041 "successful update of protocol engine " 1110 "successful update of protocol engine "
1042 "to %d.%d.%d\n", 1111 "to %d.%d.%d\n",
1043 TP_VERSION_MAJOR, TP_VERSION_MINOR, TP_VERSION_MICRO); 1112 TP_VERSION_MAJOR, TP_VERSION_MINOR, TP_VERSION_MICRO);
1044 else 1113 else
1045 dev_err(dev, "failed to update of protocol engine %d.%d.%d\n", 1114 dev_err(dev, "failed to update of protocol engine %d.%d.%d\n",
1046 TP_VERSION_MAJOR, TP_VERSION_MINOR, TP_VERSION_MICRO); 1115 TP_VERSION_MAJOR, TP_VERSION_MINOR, TP_VERSION_MICRO);
1047 if (ret) 1116 if (ret)
1048 dev_err(dev, "loading protocol SRAM failed\n"); 1117 dev_err(dev, "loading protocol SRAM failed\n");
1049 1118
1050 release_tpsram: 1119 release_tpsram:
1051 release_firmware(tpsram); 1120 release_firmware(tpsram);
1052 1121
1053 return ret; 1122 return ret;
1054 } 1123 }
1055 1124
1056 /** 1125 /**
1057 * cxgb_up - enable the adapter 1126 * cxgb_up - enable the adapter
1058 * @adapter: adapter being enabled 1127 * @adapter: adapter being enabled
1059 * 1128 *
1060 * Called when the first port is enabled, this function performs the 1129 * Called when the first port is enabled, this function performs the
1061 * actions necessary to make an adapter operational, such as completing 1130 * actions necessary to make an adapter operational, such as completing
1062 * the initialization of HW modules, and enabling interrupts. 1131 * the initialization of HW modules, and enabling interrupts.
1063 * 1132 *
1064 * Must be called with the rtnl lock held. 1133 * Must be called with the rtnl lock held.
1065 */ 1134 */
1066 static int cxgb_up(struct adapter *adap) 1135 static int cxgb_up(struct adapter *adap)
1067 { 1136 {
1068 int err; 1137 int err;
1069 1138
1070 if (!(adap->flags & FULL_INIT_DONE)) { 1139 if (!(adap->flags & FULL_INIT_DONE)) {
1071 err = t3_check_fw_version(adap); 1140 err = t3_check_fw_version(adap);
1072 if (err == -EINVAL) { 1141 if (err == -EINVAL) {
1073 err = upgrade_fw(adap); 1142 err = upgrade_fw(adap);
1074 CH_WARN(adap, "FW upgrade to %d.%d.%d %s\n", 1143 CH_WARN(adap, "FW upgrade to %d.%d.%d %s\n",
1075 FW_VERSION_MAJOR, FW_VERSION_MINOR, 1144 FW_VERSION_MAJOR, FW_VERSION_MINOR,
1076 FW_VERSION_MICRO, err ? "failed" : "succeeded"); 1145 FW_VERSION_MICRO, err ? "failed" : "succeeded");
1077 } 1146 }
1078 1147
1079 err = t3_check_tpsram_version(adap); 1148 err = t3_check_tpsram_version(adap);
1080 if (err == -EINVAL) { 1149 if (err == -EINVAL) {
1081 err = update_tpsram(adap); 1150 err = update_tpsram(adap);
1082 CH_WARN(adap, "TP upgrade to %d.%d.%d %s\n", 1151 CH_WARN(adap, "TP upgrade to %d.%d.%d %s\n",
1083 TP_VERSION_MAJOR, TP_VERSION_MINOR, 1152 TP_VERSION_MAJOR, TP_VERSION_MINOR,
1084 TP_VERSION_MICRO, err ? "failed" : "succeeded"); 1153 TP_VERSION_MICRO, err ? "failed" : "succeeded");
1085 } 1154 }
1086 1155
1087 /* 1156 /*
1088 * Clear interrupts now to catch errors if t3_init_hw fails. 1157 * Clear interrupts now to catch errors if t3_init_hw fails.
1089 * We clear them again later as initialization may trigger 1158 * We clear them again later as initialization may trigger
1090 * conditions that can interrupt. 1159 * conditions that can interrupt.
1091 */ 1160 */
1092 t3_intr_clear(adap); 1161 t3_intr_clear(adap);
1093 1162
1094 err = t3_init_hw(adap, 0); 1163 err = t3_init_hw(adap, 0);
1095 if (err) 1164 if (err)
1096 goto out; 1165 goto out;
1097 1166
1098 t3_set_reg_field(adap, A_TP_PARA_REG5, 0, F_RXDDPOFFINIT); 1167 t3_set_reg_field(adap, A_TP_PARA_REG5, 0, F_RXDDPOFFINIT);
1099 t3_write_reg(adap, A_ULPRX_TDDP_PSZ, V_HPZ0(PAGE_SHIFT - 12)); 1168 t3_write_reg(adap, A_ULPRX_TDDP_PSZ, V_HPZ0(PAGE_SHIFT - 12));
1100 1169
1101 err = setup_sge_qsets(adap); 1170 err = setup_sge_qsets(adap);
1102 if (err) 1171 if (err)
1103 goto out; 1172 goto out;
1104 1173
1105 setup_rss(adap); 1174 setup_rss(adap);
1106 if (!(adap->flags & NAPI_INIT)) 1175 if (!(adap->flags & NAPI_INIT))
1107 init_napi(adap); 1176 init_napi(adap);
1108 1177
1109 t3_start_sge_timers(adap); 1178 t3_start_sge_timers(adap);
1110 adap->flags |= FULL_INIT_DONE; 1179 adap->flags |= FULL_INIT_DONE;
1111 } 1180 }
1112 1181
1113 t3_intr_clear(adap); 1182 t3_intr_clear(adap);
1114 1183
1115 if (adap->flags & USING_MSIX) { 1184 if (adap->flags & USING_MSIX) {
1116 name_msix_vecs(adap); 1185 name_msix_vecs(adap);
1117 err = request_irq(adap->msix_info[0].vec, 1186 err = request_irq(adap->msix_info[0].vec,
1118 t3_async_intr_handler, 0, 1187 t3_async_intr_handler, 0,
1119 adap->msix_info[0].desc, adap); 1188 adap->msix_info[0].desc, adap);
1120 if (err) 1189 if (err)
1121 goto irq_err; 1190 goto irq_err;
1122 1191
1123 err = request_msix_data_irqs(adap); 1192 err = request_msix_data_irqs(adap);
1124 if (err) { 1193 if (err) {
1125 free_irq(adap->msix_info[0].vec, adap); 1194 free_irq(adap->msix_info[0].vec, adap);
1126 goto irq_err; 1195 goto irq_err;
1127 } 1196 }
1128 } else if ((err = request_irq(adap->pdev->irq, 1197 } else if ((err = request_irq(adap->pdev->irq,
1129 t3_intr_handler(adap, 1198 t3_intr_handler(adap,
1130 adap->sge.qs[0].rspq. 1199 adap->sge.qs[0].rspq.
1131 polling), 1200 polling),
1132 (adap->flags & USING_MSI) ? 1201 (adap->flags & USING_MSI) ?
1133 0 : IRQF_SHARED, 1202 0 : IRQF_SHARED,
1134 adap->name, adap))) 1203 adap->name, adap)))
1135 goto irq_err; 1204 goto irq_err;
1136 1205
1137 enable_all_napi(adap); 1206 enable_all_napi(adap);
1138 t3_sge_start(adap); 1207 t3_sge_start(adap);
1139 t3_intr_enable(adap); 1208 t3_intr_enable(adap);
1140 1209
1141 if (adap->params.rev >= T3_REV_C && !(adap->flags & TP_PARITY_INIT) && 1210 if (adap->params.rev >= T3_REV_C && !(adap->flags & TP_PARITY_INIT) &&
1142 is_offload(adap) && init_tp_parity(adap) == 0) 1211 is_offload(adap) && init_tp_parity(adap) == 0)
1143 adap->flags |= TP_PARITY_INIT; 1212 adap->flags |= TP_PARITY_INIT;
1144 1213
1145 if (adap->flags & TP_PARITY_INIT) { 1214 if (adap->flags & TP_PARITY_INIT) {
1146 t3_write_reg(adap, A_TP_INT_CAUSE, 1215 t3_write_reg(adap, A_TP_INT_CAUSE,
1147 F_CMCACHEPERR | F_ARPLUTPERR); 1216 F_CMCACHEPERR | F_ARPLUTPERR);
1148 t3_write_reg(adap, A_TP_INT_ENABLE, 0x7fbfffff); 1217 t3_write_reg(adap, A_TP_INT_ENABLE, 0x7fbfffff);
1149 } 1218 }
1150 1219
1151 if (!(adap->flags & QUEUES_BOUND)) { 1220 if (!(adap->flags & QUEUES_BOUND)) {
1152 err = bind_qsets(adap); 1221 err = bind_qsets(adap);
1153 if (err) { 1222 if (err) {
1154 CH_ERR(adap, "failed to bind qsets, err %d\n", err); 1223 CH_ERR(adap, "failed to bind qsets, err %d\n", err);
1155 t3_intr_disable(adap); 1224 t3_intr_disable(adap);
1156 free_irq_resources(adap); 1225 free_irq_resources(adap);
1157 goto out; 1226 goto out;
1158 } 1227 }
1159 adap->flags |= QUEUES_BOUND; 1228 adap->flags |= QUEUES_BOUND;
1160 } 1229 }
1161 1230
1162 out: 1231 out:
1163 return err; 1232 return err;
1164 irq_err: 1233 irq_err:
1165 CH_ERR(adap, "request_irq failed, err %d\n", err); 1234 CH_ERR(adap, "request_irq failed, err %d\n", err);
1166 goto out; 1235 goto out;
1167 } 1236 }
1168 1237
1169 /* 1238 /*
1170 * Release resources when all the ports and offloading have been stopped. 1239 * Release resources when all the ports and offloading have been stopped.
1171 */ 1240 */
1172 static void cxgb_down(struct adapter *adapter) 1241 static void cxgb_down(struct adapter *adapter)
1173 { 1242 {
1174 t3_sge_stop(adapter); 1243 t3_sge_stop(adapter);
1175 spin_lock_irq(&adapter->work_lock); /* sync with PHY intr task */ 1244 spin_lock_irq(&adapter->work_lock); /* sync with PHY intr task */
1176 t3_intr_disable(adapter); 1245 t3_intr_disable(adapter);
1177 spin_unlock_irq(&adapter->work_lock); 1246 spin_unlock_irq(&adapter->work_lock);
1178 1247
1179 free_irq_resources(adapter); 1248 free_irq_resources(adapter);
1180 quiesce_rx(adapter); 1249 quiesce_rx(adapter);
1181 flush_workqueue(cxgb3_wq); /* wait for external IRQ handler */ 1250 flush_workqueue(cxgb3_wq); /* wait for external IRQ handler */
1182 } 1251 }
1183 1252
1184 static void schedule_chk_task(struct adapter *adap) 1253 static void schedule_chk_task(struct adapter *adap)
1185 { 1254 {
1186 unsigned int timeo; 1255 unsigned int timeo;
1187 1256
1188 timeo = adap->params.linkpoll_period ? 1257 timeo = adap->params.linkpoll_period ?
1189 (HZ * adap->params.linkpoll_period) / 10 : 1258 (HZ * adap->params.linkpoll_period) / 10 :
1190 adap->params.stats_update_period * HZ; 1259 adap->params.stats_update_period * HZ;
1191 if (timeo) 1260 if (timeo)
1192 queue_delayed_work(cxgb3_wq, &adap->adap_check_task, timeo); 1261 queue_delayed_work(cxgb3_wq, &adap->adap_check_task, timeo);
1193 } 1262 }
1194 1263
1195 static int offload_open(struct net_device *dev) 1264 static int offload_open(struct net_device *dev)
1196 { 1265 {
1197 struct port_info *pi = netdev_priv(dev); 1266 struct port_info *pi = netdev_priv(dev);
1198 struct adapter *adapter = pi->adapter; 1267 struct adapter *adapter = pi->adapter;
1199 struct t3cdev *tdev = dev2t3cdev(dev); 1268 struct t3cdev *tdev = dev2t3cdev(dev);
1200 int adap_up = adapter->open_device_map & PORT_MASK; 1269 int adap_up = adapter->open_device_map & PORT_MASK;
1201 int err; 1270 int err;
1202 1271
1203 if (test_and_set_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map)) 1272 if (test_and_set_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map))
1204 return 0; 1273 return 0;
1205 1274
1206 if (!adap_up && (err = cxgb_up(adapter)) < 0) 1275 if (!adap_up && (err = cxgb_up(adapter)) < 0)
1207 goto out; 1276 goto out;
1208 1277
1209 t3_tp_set_offload_mode(adapter, 1); 1278 t3_tp_set_offload_mode(adapter, 1);
1210 tdev->lldev = adapter->port[0]; 1279 tdev->lldev = adapter->port[0];
1211 err = cxgb3_offload_activate(adapter); 1280 err = cxgb3_offload_activate(adapter);
1212 if (err) 1281 if (err)
1213 goto out; 1282 goto out;
1214 1283
1215 init_port_mtus(adapter); 1284 init_port_mtus(adapter);
1216 t3_load_mtus(adapter, adapter->params.mtus, adapter->params.a_wnd, 1285 t3_load_mtus(adapter, adapter->params.mtus, adapter->params.a_wnd,
1217 adapter->params.b_wnd, 1286 adapter->params.b_wnd,
1218 adapter->params.rev == 0 ? 1287 adapter->params.rev == 0 ?
1219 adapter->port[0]->mtu : 0xffff); 1288 adapter->port[0]->mtu : 0xffff);
1220 init_smt(adapter); 1289 init_smt(adapter);
1221 1290
1222 if (sysfs_create_group(&tdev->lldev->dev.kobj, &offload_attr_group)) 1291 if (sysfs_create_group(&tdev->lldev->dev.kobj, &offload_attr_group))
1223 dev_dbg(&dev->dev, "cannot create sysfs group\n"); 1292 dev_dbg(&dev->dev, "cannot create sysfs group\n");
1224 1293
1225 /* Call back all registered clients */ 1294 /* Call back all registered clients */
1226 cxgb3_add_clients(tdev); 1295 cxgb3_add_clients(tdev);
1227 1296
1228 out: 1297 out:
1229 /* restore them in case the offload module has changed them */ 1298 /* restore them in case the offload module has changed them */
1230 if (err) { 1299 if (err) {
1231 t3_tp_set_offload_mode(adapter, 0); 1300 t3_tp_set_offload_mode(adapter, 0);
1232 clear_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map); 1301 clear_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map);
1233 cxgb3_set_dummy_ops(tdev); 1302 cxgb3_set_dummy_ops(tdev);
1234 } 1303 }
1235 return err; 1304 return err;
1236 } 1305 }
1237 1306
1238 static int offload_close(struct t3cdev *tdev) 1307 static int offload_close(struct t3cdev *tdev)
1239 { 1308 {
1240 struct adapter *adapter = tdev2adap(tdev); 1309 struct adapter *adapter = tdev2adap(tdev);
1241 1310
1242 if (!test_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map)) 1311 if (!test_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map))
1243 return 0; 1312 return 0;
1244 1313
1245 /* Call back all registered clients */ 1314 /* Call back all registered clients */
1246 cxgb3_remove_clients(tdev); 1315 cxgb3_remove_clients(tdev);
1247 1316
1248 sysfs_remove_group(&tdev->lldev->dev.kobj, &offload_attr_group); 1317 sysfs_remove_group(&tdev->lldev->dev.kobj, &offload_attr_group);
1249 1318
1250 /* Flush work scheduled while releasing TIDs */ 1319 /* Flush work scheduled while releasing TIDs */
1251 flush_scheduled_work(); 1320 flush_scheduled_work();
1252 1321
1253 tdev->lldev = NULL; 1322 tdev->lldev = NULL;
1254 cxgb3_set_dummy_ops(tdev); 1323 cxgb3_set_dummy_ops(tdev);
1255 t3_tp_set_offload_mode(adapter, 0); 1324 t3_tp_set_offload_mode(adapter, 0);
1256 clear_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map); 1325 clear_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map);
1257 1326
1258 if (!adapter->open_device_map) 1327 if (!adapter->open_device_map)
1259 cxgb_down(adapter); 1328 cxgb_down(adapter);
1260 1329
1261 cxgb3_offload_deactivate(adapter); 1330 cxgb3_offload_deactivate(adapter);
1262 return 0; 1331 return 0;
1263 } 1332 }
1264 1333
1265 static int cxgb_open(struct net_device *dev) 1334 static int cxgb_open(struct net_device *dev)
1266 { 1335 {
1267 struct port_info *pi = netdev_priv(dev); 1336 struct port_info *pi = netdev_priv(dev);
1268 struct adapter *adapter = pi->adapter; 1337 struct adapter *adapter = pi->adapter;
1269 int other_ports = adapter->open_device_map & PORT_MASK; 1338 int other_ports = adapter->open_device_map & PORT_MASK;
1270 int err; 1339 int err;
1271 1340
1272 if (!adapter->open_device_map && (err = cxgb_up(adapter)) < 0) 1341 if (!adapter->open_device_map && (err = cxgb_up(adapter)) < 0)
1273 return err; 1342 return err;
1274 1343
1275 set_bit(pi->port_id, &adapter->open_device_map); 1344 set_bit(pi->port_id, &adapter->open_device_map);
1276 if (is_offload(adapter) && !ofld_disable) { 1345 if (is_offload(adapter) && !ofld_disable) {
1277 err = offload_open(dev); 1346 err = offload_open(dev);
1278 if (err) 1347 if (err)
1279 printk(KERN_WARNING 1348 printk(KERN_WARNING
1280 "Could not initialize offload capabilities\n"); 1349 "Could not initialize offload capabilities\n");
1281 } 1350 }
1282 1351
1283 dev->real_num_tx_queues = pi->nqsets; 1352 dev->real_num_tx_queues = pi->nqsets;
1284 link_start(dev); 1353 link_start(dev);
1285 t3_port_intr_enable(adapter, pi->port_id); 1354 t3_port_intr_enable(adapter, pi->port_id);
1286 netif_tx_start_all_queues(dev); 1355 netif_tx_start_all_queues(dev);
1287 if (!other_ports) 1356 if (!other_ports)
1288 schedule_chk_task(adapter); 1357 schedule_chk_task(adapter);
1289 1358
1290 return 0; 1359 return 0;
1291 } 1360 }
1292 1361
1293 static int cxgb_close(struct net_device *dev) 1362 static int cxgb_close(struct net_device *dev)
1294 { 1363 {
1295 struct port_info *pi = netdev_priv(dev); 1364 struct port_info *pi = netdev_priv(dev);
1296 struct adapter *adapter = pi->adapter; 1365 struct adapter *adapter = pi->adapter;
1297 1366
1298 1367
1299 if (!adapter->open_device_map) 1368 if (!adapter->open_device_map)
1300 return 0; 1369 return 0;
1301 1370
1302 /* Stop link fault interrupts */ 1371 /* Stop link fault interrupts */
1303 t3_xgm_intr_disable(adapter, pi->port_id); 1372 t3_xgm_intr_disable(adapter, pi->port_id);
1304 t3_read_reg(adapter, A_XGM_INT_STATUS + pi->mac.offset); 1373 t3_read_reg(adapter, A_XGM_INT_STATUS + pi->mac.offset);
1305 1374
1306 t3_port_intr_disable(adapter, pi->port_id); 1375 t3_port_intr_disable(adapter, pi->port_id);
1307 netif_tx_stop_all_queues(dev); 1376 netif_tx_stop_all_queues(dev);
1308 pi->phy.ops->power_down(&pi->phy, 1); 1377 pi->phy.ops->power_down(&pi->phy, 1);
1309 netif_carrier_off(dev); 1378 netif_carrier_off(dev);
1310 t3_mac_disable(&pi->mac, MAC_DIRECTION_TX | MAC_DIRECTION_RX); 1379 t3_mac_disable(&pi->mac, MAC_DIRECTION_TX | MAC_DIRECTION_RX);
1311 1380
1312 spin_lock_irq(&adapter->work_lock); /* sync with update task */ 1381 spin_lock_irq(&adapter->work_lock); /* sync with update task */
1313 clear_bit(pi->port_id, &adapter->open_device_map); 1382 clear_bit(pi->port_id, &adapter->open_device_map);
1314 spin_unlock_irq(&adapter->work_lock); 1383 spin_unlock_irq(&adapter->work_lock);
1315 1384
1316 if (!(adapter->open_device_map & PORT_MASK)) 1385 if (!(adapter->open_device_map & PORT_MASK))
1317 cancel_delayed_work_sync(&adapter->adap_check_task); 1386 cancel_delayed_work_sync(&adapter->adap_check_task);
1318 1387
1319 if (!adapter->open_device_map) 1388 if (!adapter->open_device_map)
1320 cxgb_down(adapter); 1389 cxgb_down(adapter);
1321 1390
1322 return 0; 1391 return 0;
1323 } 1392 }
1324 1393
1325 static struct net_device_stats *cxgb_get_stats(struct net_device *dev) 1394 static struct net_device_stats *cxgb_get_stats(struct net_device *dev)
1326 { 1395 {
1327 struct port_info *pi = netdev_priv(dev); 1396 struct port_info *pi = netdev_priv(dev);
1328 struct adapter *adapter = pi->adapter; 1397 struct adapter *adapter = pi->adapter;
1329 struct net_device_stats *ns = &pi->netstats; 1398 struct net_device_stats *ns = &pi->netstats;
1330 const struct mac_stats *pstats; 1399 const struct mac_stats *pstats;
1331 1400
1332 spin_lock(&adapter->stats_lock); 1401 spin_lock(&adapter->stats_lock);
1333 pstats = t3_mac_update_stats(&pi->mac); 1402 pstats = t3_mac_update_stats(&pi->mac);
1334 spin_unlock(&adapter->stats_lock); 1403 spin_unlock(&adapter->stats_lock);
1335 1404
1336 ns->tx_bytes = pstats->tx_octets; 1405 ns->tx_bytes = pstats->tx_octets;
1337 ns->tx_packets = pstats->tx_frames; 1406 ns->tx_packets = pstats->tx_frames;
1338 ns->rx_bytes = pstats->rx_octets; 1407 ns->rx_bytes = pstats->rx_octets;
1339 ns->rx_packets = pstats->rx_frames; 1408 ns->rx_packets = pstats->rx_frames;
1340 ns->multicast = pstats->rx_mcast_frames; 1409 ns->multicast = pstats->rx_mcast_frames;
1341 1410
1342 ns->tx_errors = pstats->tx_underrun; 1411 ns->tx_errors = pstats->tx_underrun;
1343 ns->rx_errors = pstats->rx_symbol_errs + pstats->rx_fcs_errs + 1412 ns->rx_errors = pstats->rx_symbol_errs + pstats->rx_fcs_errs +
1344 pstats->rx_too_long + pstats->rx_jabber + pstats->rx_short + 1413 pstats->rx_too_long + pstats->rx_jabber + pstats->rx_short +
1345 pstats->rx_fifo_ovfl; 1414 pstats->rx_fifo_ovfl;
1346 1415
1347 /* detailed rx_errors */ 1416 /* detailed rx_errors */
1348 ns->rx_length_errors = pstats->rx_jabber + pstats->rx_too_long; 1417 ns->rx_length_errors = pstats->rx_jabber + pstats->rx_too_long;
1349 ns->rx_over_errors = 0; 1418 ns->rx_over_errors = 0;
1350 ns->rx_crc_errors = pstats->rx_fcs_errs; 1419 ns->rx_crc_errors = pstats->rx_fcs_errs;
1351 ns->rx_frame_errors = pstats->rx_symbol_errs; 1420 ns->rx_frame_errors = pstats->rx_symbol_errs;
1352 ns->rx_fifo_errors = pstats->rx_fifo_ovfl; 1421 ns->rx_fifo_errors = pstats->rx_fifo_ovfl;
1353 ns->rx_missed_errors = pstats->rx_cong_drops; 1422 ns->rx_missed_errors = pstats->rx_cong_drops;
1354 1423
1355 /* detailed tx_errors */ 1424 /* detailed tx_errors */
1356 ns->tx_aborted_errors = 0; 1425 ns->tx_aborted_errors = 0;
1357 ns->tx_carrier_errors = 0; 1426 ns->tx_carrier_errors = 0;
1358 ns->tx_fifo_errors = pstats->tx_underrun; 1427 ns->tx_fifo_errors = pstats->tx_underrun;
1359 ns->tx_heartbeat_errors = 0; 1428 ns->tx_heartbeat_errors = 0;
1360 ns->tx_window_errors = 0; 1429 ns->tx_window_errors = 0;
1361 return ns; 1430 return ns;
1362 } 1431 }
1363 1432
1364 static u32 get_msglevel(struct net_device *dev) 1433 static u32 get_msglevel(struct net_device *dev)
1365 { 1434 {
1366 struct port_info *pi = netdev_priv(dev); 1435 struct port_info *pi = netdev_priv(dev);
1367 struct adapter *adapter = pi->adapter; 1436 struct adapter *adapter = pi->adapter;
1368 1437
1369 return adapter->msg_enable; 1438 return adapter->msg_enable;
1370 } 1439 }
1371 1440
1372 static void set_msglevel(struct net_device *dev, u32 val) 1441 static void set_msglevel(struct net_device *dev, u32 val)
1373 { 1442 {
1374 struct port_info *pi = netdev_priv(dev); 1443 struct port_info *pi = netdev_priv(dev);
1375 struct adapter *adapter = pi->adapter; 1444 struct adapter *adapter = pi->adapter;
1376 1445
1377 adapter->msg_enable = val; 1446 adapter->msg_enable = val;
1378 } 1447 }
1379 1448
1380 static char stats_strings[][ETH_GSTRING_LEN] = { 1449 static char stats_strings[][ETH_GSTRING_LEN] = {
1381 "TxOctetsOK ", 1450 "TxOctetsOK ",
1382 "TxFramesOK ", 1451 "TxFramesOK ",
1383 "TxMulticastFramesOK", 1452 "TxMulticastFramesOK",
1384 "TxBroadcastFramesOK", 1453 "TxBroadcastFramesOK",
1385 "TxPauseFrames ", 1454 "TxPauseFrames ",
1386 "TxUnderrun ", 1455 "TxUnderrun ",
1387 "TxExtUnderrun ", 1456 "TxExtUnderrun ",
1388 1457
1389 "TxFrames64 ", 1458 "TxFrames64 ",
1390 "TxFrames65To127 ", 1459 "TxFrames65To127 ",
1391 "TxFrames128To255 ", 1460 "TxFrames128To255 ",
1392 "TxFrames256To511 ", 1461 "TxFrames256To511 ",
1393 "TxFrames512To1023 ", 1462 "TxFrames512To1023 ",
1394 "TxFrames1024To1518 ", 1463 "TxFrames1024To1518 ",
1395 "TxFrames1519ToMax ", 1464 "TxFrames1519ToMax ",
1396 1465
1397 "RxOctetsOK ", 1466 "RxOctetsOK ",
1398 "RxFramesOK ", 1467 "RxFramesOK ",
1399 "RxMulticastFramesOK", 1468 "RxMulticastFramesOK",
1400 "RxBroadcastFramesOK", 1469 "RxBroadcastFramesOK",
1401 "RxPauseFrames ", 1470 "RxPauseFrames ",
1402 "RxFCSErrors ", 1471 "RxFCSErrors ",
1403 "RxSymbolErrors ", 1472 "RxSymbolErrors ",
1404 "RxShortErrors ", 1473 "RxShortErrors ",
1405 "RxJabberErrors ", 1474 "RxJabberErrors ",
1406 "RxLengthErrors ", 1475 "RxLengthErrors ",
1407 "RxFIFOoverflow ", 1476 "RxFIFOoverflow ",
1408 1477
1409 "RxFrames64 ", 1478 "RxFrames64 ",
1410 "RxFrames65To127 ", 1479 "RxFrames65To127 ",
1411 "RxFrames128To255 ", 1480 "RxFrames128To255 ",
1412 "RxFrames256To511 ", 1481 "RxFrames256To511 ",
1413 "RxFrames512To1023 ", 1482 "RxFrames512To1023 ",
1414 "RxFrames1024To1518 ", 1483 "RxFrames1024To1518 ",
1415 "RxFrames1519ToMax ", 1484 "RxFrames1519ToMax ",
1416 1485
1417 "PhyFIFOErrors ", 1486 "PhyFIFOErrors ",
1418 "TSO ", 1487 "TSO ",
1419 "VLANextractions ", 1488 "VLANextractions ",
1420 "VLANinsertions ", 1489 "VLANinsertions ",
1421 "TxCsumOffload ", 1490 "TxCsumOffload ",
1422 "RxCsumGood ", 1491 "RxCsumGood ",
1423 "LroAggregated ", 1492 "LroAggregated ",
1424 "LroFlushed ", 1493 "LroFlushed ",
1425 "LroNoDesc ", 1494 "LroNoDesc ",
1426 "RxDrops ", 1495 "RxDrops ",
1427 1496
1428 "CheckTXEnToggled ", 1497 "CheckTXEnToggled ",
1429 "CheckResets ", 1498 "CheckResets ",
1430 1499
1431 "LinkFaults ", 1500 "LinkFaults ",
1432 }; 1501 };
1433 1502
1434 static int get_sset_count(struct net_device *dev, int sset) 1503 static int get_sset_count(struct net_device *dev, int sset)
1435 { 1504 {
1436 switch (sset) { 1505 switch (sset) {
1437 case ETH_SS_STATS: 1506 case ETH_SS_STATS:
1438 return ARRAY_SIZE(stats_strings); 1507 return ARRAY_SIZE(stats_strings);
1439 default: 1508 default:
1440 return -EOPNOTSUPP; 1509 return -EOPNOTSUPP;
1441 } 1510 }
1442 } 1511 }
1443 1512
1444 #define T3_REGMAP_SIZE (3 * 1024) 1513 #define T3_REGMAP_SIZE (3 * 1024)
1445 1514
1446 static int get_regs_len(struct net_device *dev) 1515 static int get_regs_len(struct net_device *dev)
1447 { 1516 {
1448 return T3_REGMAP_SIZE; 1517 return T3_REGMAP_SIZE;
1449 } 1518 }
1450 1519
1451 static int get_eeprom_len(struct net_device *dev) 1520 static int get_eeprom_len(struct net_device *dev)
1452 { 1521 {
1453 return EEPROMSIZE; 1522 return EEPROMSIZE;
1454 } 1523 }
1455 1524
1456 static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) 1525 static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1457 { 1526 {
1458 struct port_info *pi = netdev_priv(dev); 1527 struct port_info *pi = netdev_priv(dev);
1459 struct adapter *adapter = pi->adapter; 1528 struct adapter *adapter = pi->adapter;
1460 u32 fw_vers = 0; 1529 u32 fw_vers = 0;
1461 u32 tp_vers = 0; 1530 u32 tp_vers = 0;
1462 1531
1463 spin_lock(&adapter->stats_lock); 1532 spin_lock(&adapter->stats_lock);
1464 t3_get_fw_version(adapter, &fw_vers); 1533 t3_get_fw_version(adapter, &fw_vers);
1465 t3_get_tp_version(adapter, &tp_vers); 1534 t3_get_tp_version(adapter, &tp_vers);
1466 spin_unlock(&adapter->stats_lock); 1535 spin_unlock(&adapter->stats_lock);
1467 1536
1468 strcpy(info->driver, DRV_NAME); 1537 strcpy(info->driver, DRV_NAME);
1469 strcpy(info->version, DRV_VERSION); 1538 strcpy(info->version, DRV_VERSION);
1470 strcpy(info->bus_info, pci_name(adapter->pdev)); 1539 strcpy(info->bus_info, pci_name(adapter->pdev));
1471 if (!fw_vers) 1540 if (!fw_vers)
1472 strcpy(info->fw_version, "N/A"); 1541 strcpy(info->fw_version, "N/A");
1473 else { 1542 else {
1474 snprintf(info->fw_version, sizeof(info->fw_version), 1543 snprintf(info->fw_version, sizeof(info->fw_version),
1475 "%s %u.%u.%u TP %u.%u.%u", 1544 "%s %u.%u.%u TP %u.%u.%u",
1476 G_FW_VERSION_TYPE(fw_vers) ? "T" : "N", 1545 G_FW_VERSION_TYPE(fw_vers) ? "T" : "N",
1477 G_FW_VERSION_MAJOR(fw_vers), 1546 G_FW_VERSION_MAJOR(fw_vers),
1478 G_FW_VERSION_MINOR(fw_vers), 1547 G_FW_VERSION_MINOR(fw_vers),
1479 G_FW_VERSION_MICRO(fw_vers), 1548 G_FW_VERSION_MICRO(fw_vers),
1480 G_TP_VERSION_MAJOR(tp_vers), 1549 G_TP_VERSION_MAJOR(tp_vers),
1481 G_TP_VERSION_MINOR(tp_vers), 1550 G_TP_VERSION_MINOR(tp_vers),
1482 G_TP_VERSION_MICRO(tp_vers)); 1551 G_TP_VERSION_MICRO(tp_vers));
1483 } 1552 }
1484 } 1553 }
1485 1554
1486 static void get_strings(struct net_device *dev, u32 stringset, u8 * data) 1555 static void get_strings(struct net_device *dev, u32 stringset, u8 * data)
1487 { 1556 {
1488 if (stringset == ETH_SS_STATS) 1557 if (stringset == ETH_SS_STATS)
1489 memcpy(data, stats_strings, sizeof(stats_strings)); 1558 memcpy(data, stats_strings, sizeof(stats_strings));
1490 } 1559 }
1491 1560
1492 static unsigned long collect_sge_port_stats(struct adapter *adapter, 1561 static unsigned long collect_sge_port_stats(struct adapter *adapter,
1493 struct port_info *p, int idx) 1562 struct port_info *p, int idx)
1494 { 1563 {
1495 int i; 1564 int i;
1496 unsigned long tot = 0; 1565 unsigned long tot = 0;
1497 1566
1498 for (i = p->first_qset; i < p->first_qset + p->nqsets; ++i) 1567 for (i = p->first_qset; i < p->first_qset + p->nqsets; ++i)
1499 tot += adapter->sge.qs[i].port_stats[idx]; 1568 tot += adapter->sge.qs[i].port_stats[idx];
1500 return tot; 1569 return tot;
1501 } 1570 }
1502 1571
1503 static void get_stats(struct net_device *dev, struct ethtool_stats *stats, 1572 static void get_stats(struct net_device *dev, struct ethtool_stats *stats,
1504 u64 *data) 1573 u64 *data)
1505 { 1574 {
1506 struct port_info *pi = netdev_priv(dev); 1575 struct port_info *pi = netdev_priv(dev);
1507 struct adapter *adapter = pi->adapter; 1576 struct adapter *adapter = pi->adapter;
1508 const struct mac_stats *s; 1577 const struct mac_stats *s;
1509 1578
1510 spin_lock(&adapter->stats_lock); 1579 spin_lock(&adapter->stats_lock);
1511 s = t3_mac_update_stats(&pi->mac); 1580 s = t3_mac_update_stats(&pi->mac);
1512 spin_unlock(&adapter->stats_lock); 1581 spin_unlock(&adapter->stats_lock);
1513 1582
1514 *data++ = s->tx_octets; 1583 *data++ = s->tx_octets;
1515 *data++ = s->tx_frames; 1584 *data++ = s->tx_frames;
1516 *data++ = s->tx_mcast_frames; 1585 *data++ = s->tx_mcast_frames;
1517 *data++ = s->tx_bcast_frames; 1586 *data++ = s->tx_bcast_frames;
1518 *data++ = s->tx_pause; 1587 *data++ = s->tx_pause;
1519 *data++ = s->tx_underrun; 1588 *data++ = s->tx_underrun;
1520 *data++ = s->tx_fifo_urun; 1589 *data++ = s->tx_fifo_urun;
1521 1590
1522 *data++ = s->tx_frames_64; 1591 *data++ = s->tx_frames_64;
1523 *data++ = s->tx_frames_65_127; 1592 *data++ = s->tx_frames_65_127;
1524 *data++ = s->tx_frames_128_255; 1593 *data++ = s->tx_frames_128_255;
1525 *data++ = s->tx_frames_256_511; 1594 *data++ = s->tx_frames_256_511;
1526 *data++ = s->tx_frames_512_1023; 1595 *data++ = s->tx_frames_512_1023;
1527 *data++ = s->tx_frames_1024_1518; 1596 *data++ = s->tx_frames_1024_1518;
1528 *data++ = s->tx_frames_1519_max; 1597 *data++ = s->tx_frames_1519_max;
1529 1598
1530 *data++ = s->rx_octets; 1599 *data++ = s->rx_octets;
1531 *data++ = s->rx_frames; 1600 *data++ = s->rx_frames;
1532 *data++ = s->rx_mcast_frames; 1601 *data++ = s->rx_mcast_frames;
1533 *data++ = s->rx_bcast_frames; 1602 *data++ = s->rx_bcast_frames;
1534 *data++ = s->rx_pause; 1603 *data++ = s->rx_pause;
1535 *data++ = s->rx_fcs_errs; 1604 *data++ = s->rx_fcs_errs;
1536 *data++ = s->rx_symbol_errs; 1605 *data++ = s->rx_symbol_errs;
1537 *data++ = s->rx_short; 1606 *data++ = s->rx_short;
1538 *data++ = s->rx_jabber; 1607 *data++ = s->rx_jabber;
1539 *data++ = s->rx_too_long; 1608 *data++ = s->rx_too_long;
1540 *data++ = s->rx_fifo_ovfl; 1609 *data++ = s->rx_fifo_ovfl;
1541 1610
1542 *data++ = s->rx_frames_64; 1611 *data++ = s->rx_frames_64;
1543 *data++ = s->rx_frames_65_127; 1612 *data++ = s->rx_frames_65_127;
1544 *data++ = s->rx_frames_128_255; 1613 *data++ = s->rx_frames_128_255;
1545 *data++ = s->rx_frames_256_511; 1614 *data++ = s->rx_frames_256_511;
1546 *data++ = s->rx_frames_512_1023; 1615 *data++ = s->rx_frames_512_1023;
1547 *data++ = s->rx_frames_1024_1518; 1616 *data++ = s->rx_frames_1024_1518;
1548 *data++ = s->rx_frames_1519_max; 1617 *data++ = s->rx_frames_1519_max;
1549 1618
1550 *data++ = pi->phy.fifo_errors; 1619 *data++ = pi->phy.fifo_errors;
1551 1620
1552 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_TSO); 1621 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_TSO);
1553 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_VLANEX); 1622 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_VLANEX);
1554 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_VLANINS); 1623 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_VLANINS);
1555 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_TX_CSUM); 1624 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_TX_CSUM);
1556 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_RX_CSUM_GOOD); 1625 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_RX_CSUM_GOOD);
1557 *data++ = 0; 1626 *data++ = 0;
1558 *data++ = 0; 1627 *data++ = 0;
1559 *data++ = 0; 1628 *data++ = 0;
1560 *data++ = s->rx_cong_drops; 1629 *data++ = s->rx_cong_drops;
1561 1630
1562 *data++ = s->num_toggled; 1631 *data++ = s->num_toggled;
1563 *data++ = s->num_resets; 1632 *data++ = s->num_resets;
1564 1633
1565 *data++ = s->link_faults; 1634 *data++ = s->link_faults;
1566 } 1635 }
1567 1636
1568 static inline void reg_block_dump(struct adapter *ap, void *buf, 1637 static inline void reg_block_dump(struct adapter *ap, void *buf,
1569 unsigned int start, unsigned int end) 1638 unsigned int start, unsigned int end)
1570 { 1639 {
1571 u32 *p = buf + start; 1640 u32 *p = buf + start;
1572 1641
1573 for (; start <= end; start += sizeof(u32)) 1642 for (; start <= end; start += sizeof(u32))
1574 *p++ = t3_read_reg(ap, start); 1643 *p++ = t3_read_reg(ap, start);
1575 } 1644 }
1576 1645
1577 static void get_regs(struct net_device *dev, struct ethtool_regs *regs, 1646 static void get_regs(struct net_device *dev, struct ethtool_regs *regs,
1578 void *buf) 1647 void *buf)
1579 { 1648 {
1580 struct port_info *pi = netdev_priv(dev); 1649 struct port_info *pi = netdev_priv(dev);
1581 struct adapter *ap = pi->adapter; 1650 struct adapter *ap = pi->adapter;
1582 1651
1583 /* 1652 /*
1584 * Version scheme: 1653 * Version scheme:
1585 * bits 0..9: chip version 1654 * bits 0..9: chip version
1586 * bits 10..15: chip revision 1655 * bits 10..15: chip revision
1587 * bit 31: set for PCIe cards 1656 * bit 31: set for PCIe cards
1588 */ 1657 */
1589 regs->version = 3 | (ap->params.rev << 10) | (is_pcie(ap) << 31); 1658 regs->version = 3 | (ap->params.rev << 10) | (is_pcie(ap) << 31);
1590 1659
1591 /* 1660 /*
1592 * We skip the MAC statistics registers because they are clear-on-read. 1661 * We skip the MAC statistics registers because they are clear-on-read.
1593 * Also reading multi-register stats would need to synchronize with the 1662 * Also reading multi-register stats would need to synchronize with the
1594 * periodic mac stats accumulation. Hard to justify the complexity. 1663 * periodic mac stats accumulation. Hard to justify the complexity.
1595 */ 1664 */
1596 memset(buf, 0, T3_REGMAP_SIZE); 1665 memset(buf, 0, T3_REGMAP_SIZE);
1597 reg_block_dump(ap, buf, 0, A_SG_RSPQ_CREDIT_RETURN); 1666 reg_block_dump(ap, buf, 0, A_SG_RSPQ_CREDIT_RETURN);
1598 reg_block_dump(ap, buf, A_SG_HI_DRB_HI_THRSH, A_ULPRX_PBL_ULIMIT); 1667 reg_block_dump(ap, buf, A_SG_HI_DRB_HI_THRSH, A_ULPRX_PBL_ULIMIT);
1599 reg_block_dump(ap, buf, A_ULPTX_CONFIG, A_MPS_INT_CAUSE); 1668 reg_block_dump(ap, buf, A_ULPTX_CONFIG, A_MPS_INT_CAUSE);
1600 reg_block_dump(ap, buf, A_CPL_SWITCH_CNTRL, A_CPL_MAP_TBL_DATA); 1669 reg_block_dump(ap, buf, A_CPL_SWITCH_CNTRL, A_CPL_MAP_TBL_DATA);
1601 reg_block_dump(ap, buf, A_SMB_GLOBAL_TIME_CFG, A_XGM_SERDES_STAT3); 1670 reg_block_dump(ap, buf, A_SMB_GLOBAL_TIME_CFG, A_XGM_SERDES_STAT3);
1602 reg_block_dump(ap, buf, A_XGM_SERDES_STATUS0, 1671 reg_block_dump(ap, buf, A_XGM_SERDES_STATUS0,
1603 XGM_REG(A_XGM_SERDES_STAT3, 1)); 1672 XGM_REG(A_XGM_SERDES_STAT3, 1));
1604 reg_block_dump(ap, buf, XGM_REG(A_XGM_SERDES_STATUS0, 1), 1673 reg_block_dump(ap, buf, XGM_REG(A_XGM_SERDES_STATUS0, 1),
1605 XGM_REG(A_XGM_RX_SPI4_SOP_EOP_CNT, 1)); 1674 XGM_REG(A_XGM_RX_SPI4_SOP_EOP_CNT, 1));
1606 } 1675 }
1607 1676
1608 static int restart_autoneg(struct net_device *dev) 1677 static int restart_autoneg(struct net_device *dev)
1609 { 1678 {
1610 struct port_info *p = netdev_priv(dev); 1679 struct port_info *p = netdev_priv(dev);
1611 1680
1612 if (!netif_running(dev)) 1681 if (!netif_running(dev))
1613 return -EAGAIN; 1682 return -EAGAIN;
1614 if (p->link_config.autoneg != AUTONEG_ENABLE) 1683 if (p->link_config.autoneg != AUTONEG_ENABLE)
1615 return -EINVAL; 1684 return -EINVAL;
1616 p->phy.ops->autoneg_restart(&p->phy); 1685 p->phy.ops->autoneg_restart(&p->phy);
1617 return 0; 1686 return 0;
1618 } 1687 }
1619 1688
1620 static int cxgb3_phys_id(struct net_device *dev, u32 data) 1689 static int cxgb3_phys_id(struct net_device *dev, u32 data)
1621 { 1690 {
1622 struct port_info *pi = netdev_priv(dev); 1691 struct port_info *pi = netdev_priv(dev);
1623 struct adapter *adapter = pi->adapter; 1692 struct adapter *adapter = pi->adapter;
1624 int i; 1693 int i;
1625 1694
1626 if (data == 0) 1695 if (data == 0)
1627 data = 2; 1696 data = 2;
1628 1697
1629 for (i = 0; i < data * 2; i++) { 1698 for (i = 0; i < data * 2; i++) {
1630 t3_set_reg_field(adapter, A_T3DBG_GPIO_EN, F_GPIO0_OUT_VAL, 1699 t3_set_reg_field(adapter, A_T3DBG_GPIO_EN, F_GPIO0_OUT_VAL,
1631 (i & 1) ? F_GPIO0_OUT_VAL : 0); 1700 (i & 1) ? F_GPIO0_OUT_VAL : 0);
1632 if (msleep_interruptible(500)) 1701 if (msleep_interruptible(500))
1633 break; 1702 break;
1634 } 1703 }
1635 t3_set_reg_field(adapter, A_T3DBG_GPIO_EN, F_GPIO0_OUT_VAL, 1704 t3_set_reg_field(adapter, A_T3DBG_GPIO_EN, F_GPIO0_OUT_VAL,
1636 F_GPIO0_OUT_VAL); 1705 F_GPIO0_OUT_VAL);
1637 return 0; 1706 return 0;
1638 } 1707 }
1639 1708
1640 static int get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 1709 static int get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1641 { 1710 {
1642 struct port_info *p = netdev_priv(dev); 1711 struct port_info *p = netdev_priv(dev);
1643 1712
1644 cmd->supported = p->link_config.supported; 1713 cmd->supported = p->link_config.supported;
1645 cmd->advertising = p->link_config.advertising; 1714 cmd->advertising = p->link_config.advertising;
1646 1715
1647 if (netif_carrier_ok(dev)) { 1716 if (netif_carrier_ok(dev)) {
1648 cmd->speed = p->link_config.speed; 1717 cmd->speed = p->link_config.speed;
1649 cmd->duplex = p->link_config.duplex; 1718 cmd->duplex = p->link_config.duplex;
1650 } else { 1719 } else {
1651 cmd->speed = -1; 1720 cmd->speed = -1;
1652 cmd->duplex = -1; 1721 cmd->duplex = -1;
1653 } 1722 }
1654 1723
1655 cmd->port = (cmd->supported & SUPPORTED_TP) ? PORT_TP : PORT_FIBRE; 1724 cmd->port = (cmd->supported & SUPPORTED_TP) ? PORT_TP : PORT_FIBRE;
1656 cmd->phy_address = p->phy.mdio.prtad; 1725 cmd->phy_address = p->phy.mdio.prtad;
1657 cmd->transceiver = XCVR_EXTERNAL; 1726 cmd->transceiver = XCVR_EXTERNAL;
1658 cmd->autoneg = p->link_config.autoneg; 1727 cmd->autoneg = p->link_config.autoneg;
1659 cmd->maxtxpkt = 0; 1728 cmd->maxtxpkt = 0;
1660 cmd->maxrxpkt = 0; 1729 cmd->maxrxpkt = 0;
1661 return 0; 1730 return 0;
1662 } 1731 }
1663 1732
1664 static int speed_duplex_to_caps(int speed, int duplex) 1733 static int speed_duplex_to_caps(int speed, int duplex)
1665 { 1734 {
1666 int cap = 0; 1735 int cap = 0;
1667 1736
1668 switch (speed) { 1737 switch (speed) {
1669 case SPEED_10: 1738 case SPEED_10:
1670 if (duplex == DUPLEX_FULL) 1739 if (duplex == DUPLEX_FULL)
1671 cap = SUPPORTED_10baseT_Full; 1740 cap = SUPPORTED_10baseT_Full;
1672 else 1741 else
1673 cap = SUPPORTED_10baseT_Half; 1742 cap = SUPPORTED_10baseT_Half;
1674 break; 1743 break;
1675 case SPEED_100: 1744 case SPEED_100:
1676 if (duplex == DUPLEX_FULL) 1745 if (duplex == DUPLEX_FULL)
1677 cap = SUPPORTED_100baseT_Full; 1746 cap = SUPPORTED_100baseT_Full;
1678 else 1747 else
1679 cap = SUPPORTED_100baseT_Half; 1748 cap = SUPPORTED_100baseT_Half;
1680 break; 1749 break;
1681 case SPEED_1000: 1750 case SPEED_1000:
1682 if (duplex == DUPLEX_FULL) 1751 if (duplex == DUPLEX_FULL)
1683 cap = SUPPORTED_1000baseT_Full; 1752 cap = SUPPORTED_1000baseT_Full;
1684 else 1753 else
1685 cap = SUPPORTED_1000baseT_Half; 1754 cap = SUPPORTED_1000baseT_Half;
1686 break; 1755 break;
1687 case SPEED_10000: 1756 case SPEED_10000:
1688 if (duplex == DUPLEX_FULL) 1757 if (duplex == DUPLEX_FULL)
1689 cap = SUPPORTED_10000baseT_Full; 1758 cap = SUPPORTED_10000baseT_Full;
1690 } 1759 }
1691 return cap; 1760 return cap;
1692 } 1761 }
1693 1762
1694 #define ADVERTISED_MASK (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \ 1763 #define ADVERTISED_MASK (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
1695 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \ 1764 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
1696 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full | \ 1765 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full | \
1697 ADVERTISED_10000baseT_Full) 1766 ADVERTISED_10000baseT_Full)
1698 1767
1699 static int set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 1768 static int set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1700 { 1769 {
1701 struct port_info *p = netdev_priv(dev); 1770 struct port_info *p = netdev_priv(dev);
1702 struct link_config *lc = &p->link_config; 1771 struct link_config *lc = &p->link_config;
1703 1772
1704 if (!(lc->supported & SUPPORTED_Autoneg)) { 1773 if (!(lc->supported & SUPPORTED_Autoneg)) {
1705 /* 1774 /*
1706 * PHY offers a single speed/duplex. See if that's what's 1775 * PHY offers a single speed/duplex. See if that's what's
1707 * being requested. 1776 * being requested.
1708 */ 1777 */
1709 if (cmd->autoneg == AUTONEG_DISABLE) { 1778 if (cmd->autoneg == AUTONEG_DISABLE) {
1710 int cap = speed_duplex_to_caps(cmd->speed, cmd->duplex); 1779 int cap = speed_duplex_to_caps(cmd->speed, cmd->duplex);
1711 if (lc->supported & cap) 1780 if (lc->supported & cap)
1712 return 0; 1781 return 0;
1713 } 1782 }
1714 return -EINVAL; 1783 return -EINVAL;
1715 } 1784 }
1716 1785
1717 if (cmd->autoneg == AUTONEG_DISABLE) { 1786 if (cmd->autoneg == AUTONEG_DISABLE) {
1718 int cap = speed_duplex_to_caps(cmd->speed, cmd->duplex); 1787 int cap = speed_duplex_to_caps(cmd->speed, cmd->duplex);
1719 1788
1720 if (!(lc->supported & cap) || cmd->speed == SPEED_1000) 1789 if (!(lc->supported & cap) || cmd->speed == SPEED_1000)
1721 return -EINVAL; 1790 return -EINVAL;
1722 lc->requested_speed = cmd->speed; 1791 lc->requested_speed = cmd->speed;
1723 lc->requested_duplex = cmd->duplex; 1792 lc->requested_duplex = cmd->duplex;
1724 lc->advertising = 0; 1793 lc->advertising = 0;
1725 } else { 1794 } else {
1726 cmd->advertising &= ADVERTISED_MASK; 1795 cmd->advertising &= ADVERTISED_MASK;
1727 cmd->advertising &= lc->supported; 1796 cmd->advertising &= lc->supported;
1728 if (!cmd->advertising) 1797 if (!cmd->advertising)
1729 return -EINVAL; 1798 return -EINVAL;
1730 lc->requested_speed = SPEED_INVALID; 1799 lc->requested_speed = SPEED_INVALID;
1731 lc->requested_duplex = DUPLEX_INVALID; 1800 lc->requested_duplex = DUPLEX_INVALID;
1732 lc->advertising = cmd->advertising | ADVERTISED_Autoneg; 1801 lc->advertising = cmd->advertising | ADVERTISED_Autoneg;
1733 } 1802 }
1734 lc->autoneg = cmd->autoneg; 1803 lc->autoneg = cmd->autoneg;
1735 if (netif_running(dev)) 1804 if (netif_running(dev))
1736 t3_link_start(&p->phy, &p->mac, lc); 1805 t3_link_start(&p->phy, &p->mac, lc);
1737 return 0; 1806 return 0;
1738 } 1807 }
1739 1808
1740 static void get_pauseparam(struct net_device *dev, 1809 static void get_pauseparam(struct net_device *dev,
1741 struct ethtool_pauseparam *epause) 1810 struct ethtool_pauseparam *epause)
1742 { 1811 {
1743 struct port_info *p = netdev_priv(dev); 1812 struct port_info *p = netdev_priv(dev);
1744 1813
1745 epause->autoneg = (p->link_config.requested_fc & PAUSE_AUTONEG) != 0; 1814 epause->autoneg = (p->link_config.requested_fc & PAUSE_AUTONEG) != 0;
1746 epause->rx_pause = (p->link_config.fc & PAUSE_RX) != 0; 1815 epause->rx_pause = (p->link_config.fc & PAUSE_RX) != 0;
1747 epause->tx_pause = (p->link_config.fc & PAUSE_TX) != 0; 1816 epause->tx_pause = (p->link_config.fc & PAUSE_TX) != 0;
1748 } 1817 }
1749 1818
1750 static int set_pauseparam(struct net_device *dev, 1819 static int set_pauseparam(struct net_device *dev,
1751 struct ethtool_pauseparam *epause) 1820 struct ethtool_pauseparam *epause)
1752 { 1821 {
1753 struct port_info *p = netdev_priv(dev); 1822 struct port_info *p = netdev_priv(dev);
1754 struct link_config *lc = &p->link_config; 1823 struct link_config *lc = &p->link_config;
1755 1824
1756 if (epause->autoneg == AUTONEG_DISABLE) 1825 if (epause->autoneg == AUTONEG_DISABLE)
1757 lc->requested_fc = 0; 1826 lc->requested_fc = 0;
1758 else if (lc->supported & SUPPORTED_Autoneg) 1827 else if (lc->supported & SUPPORTED_Autoneg)
1759 lc->requested_fc = PAUSE_AUTONEG; 1828 lc->requested_fc = PAUSE_AUTONEG;
1760 else 1829 else
1761 return -EINVAL; 1830 return -EINVAL;
1762 1831
1763 if (epause->rx_pause) 1832 if (epause->rx_pause)
1764 lc->requested_fc |= PAUSE_RX; 1833 lc->requested_fc |= PAUSE_RX;
1765 if (epause->tx_pause) 1834 if (epause->tx_pause)
1766 lc->requested_fc |= PAUSE_TX; 1835 lc->requested_fc |= PAUSE_TX;
1767 if (lc->autoneg == AUTONEG_ENABLE) { 1836 if (lc->autoneg == AUTONEG_ENABLE) {
1768 if (netif_running(dev)) 1837 if (netif_running(dev))
1769 t3_link_start(&p->phy, &p->mac, lc); 1838 t3_link_start(&p->phy, &p->mac, lc);
1770 } else { 1839 } else {
1771 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX); 1840 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
1772 if (netif_running(dev)) 1841 if (netif_running(dev))
1773 t3_mac_set_speed_duplex_fc(&p->mac, -1, -1, lc->fc); 1842 t3_mac_set_speed_duplex_fc(&p->mac, -1, -1, lc->fc);
1774 } 1843 }
1775 return 0; 1844 return 0;
1776 } 1845 }
1777 1846
1778 static u32 get_rx_csum(struct net_device *dev) 1847 static u32 get_rx_csum(struct net_device *dev)
1779 { 1848 {
1780 struct port_info *p = netdev_priv(dev); 1849 struct port_info *p = netdev_priv(dev);
1781 1850
1782 return p->rx_offload & T3_RX_CSUM; 1851 return p->rx_offload & T3_RX_CSUM;
1783 } 1852 }
1784 1853
1785 static int set_rx_csum(struct net_device *dev, u32 data) 1854 static int set_rx_csum(struct net_device *dev, u32 data)
1786 { 1855 {
1787 struct port_info *p = netdev_priv(dev); 1856 struct port_info *p = netdev_priv(dev);
1788 1857
1789 if (data) { 1858 if (data) {
1790 p->rx_offload |= T3_RX_CSUM; 1859 p->rx_offload |= T3_RX_CSUM;
1791 } else { 1860 } else {
1792 int i; 1861 int i;
1793 1862
1794 p->rx_offload &= ~(T3_RX_CSUM | T3_LRO); 1863 p->rx_offload &= ~(T3_RX_CSUM | T3_LRO);
1795 for (i = p->first_qset; i < p->first_qset + p->nqsets; i++) 1864 for (i = p->first_qset; i < p->first_qset + p->nqsets; i++)
1796 set_qset_lro(dev, i, 0); 1865 set_qset_lro(dev, i, 0);
1797 } 1866 }
1798 return 0; 1867 return 0;
1799 } 1868 }
1800 1869
1801 static void get_sge_param(struct net_device *dev, struct ethtool_ringparam *e) 1870 static void get_sge_param(struct net_device *dev, struct ethtool_ringparam *e)
1802 { 1871 {
1803 struct port_info *pi = netdev_priv(dev); 1872 struct port_info *pi = netdev_priv(dev);
1804 struct adapter *adapter = pi->adapter; 1873 struct adapter *adapter = pi->adapter;
1805 const struct qset_params *q = &adapter->params.sge.qset[pi->first_qset]; 1874 const struct qset_params *q = &adapter->params.sge.qset[pi->first_qset];
1806 1875
1807 e->rx_max_pending = MAX_RX_BUFFERS; 1876 e->rx_max_pending = MAX_RX_BUFFERS;
1808 e->rx_mini_max_pending = 0; 1877 e->rx_mini_max_pending = 0;
1809 e->rx_jumbo_max_pending = MAX_RX_JUMBO_BUFFERS; 1878 e->rx_jumbo_max_pending = MAX_RX_JUMBO_BUFFERS;
1810 e->tx_max_pending = MAX_TXQ_ENTRIES; 1879 e->tx_max_pending = MAX_TXQ_ENTRIES;
1811 1880
1812 e->rx_pending = q->fl_size; 1881 e->rx_pending = q->fl_size;
1813 e->rx_mini_pending = q->rspq_size; 1882 e->rx_mini_pending = q->rspq_size;
1814 e->rx_jumbo_pending = q->jumbo_size; 1883 e->rx_jumbo_pending = q->jumbo_size;
1815 e->tx_pending = q->txq_size[0]; 1884 e->tx_pending = q->txq_size[0];
1816 } 1885 }
1817 1886
1818 static int set_sge_param(struct net_device *dev, struct ethtool_ringparam *e) 1887 static int set_sge_param(struct net_device *dev, struct ethtool_ringparam *e)
1819 { 1888 {
1820 struct port_info *pi = netdev_priv(dev); 1889 struct port_info *pi = netdev_priv(dev);
1821 struct adapter *adapter = pi->adapter; 1890 struct adapter *adapter = pi->adapter;
1822 struct qset_params *q; 1891 struct qset_params *q;
1823 int i; 1892 int i;
1824 1893
1825 if (e->rx_pending > MAX_RX_BUFFERS || 1894 if (e->rx_pending > MAX_RX_BUFFERS ||
1826 e->rx_jumbo_pending > MAX_RX_JUMBO_BUFFERS || 1895 e->rx_jumbo_pending > MAX_RX_JUMBO_BUFFERS ||
1827 e->tx_pending > MAX_TXQ_ENTRIES || 1896 e->tx_pending > MAX_TXQ_ENTRIES ||
1828 e->rx_mini_pending > MAX_RSPQ_ENTRIES || 1897 e->rx_mini_pending > MAX_RSPQ_ENTRIES ||
1829 e->rx_mini_pending < MIN_RSPQ_ENTRIES || 1898 e->rx_mini_pending < MIN_RSPQ_ENTRIES ||
1830 e->rx_pending < MIN_FL_ENTRIES || 1899 e->rx_pending < MIN_FL_ENTRIES ||
1831 e->rx_jumbo_pending < MIN_FL_ENTRIES || 1900 e->rx_jumbo_pending < MIN_FL_ENTRIES ||
1832 e->tx_pending < adapter->params.nports * MIN_TXQ_ENTRIES) 1901 e->tx_pending < adapter->params.nports * MIN_TXQ_ENTRIES)
1833 return -EINVAL; 1902 return -EINVAL;
1834 1903
1835 if (adapter->flags & FULL_INIT_DONE) 1904 if (adapter->flags & FULL_INIT_DONE)
1836 return -EBUSY; 1905 return -EBUSY;
1837 1906
1838 q = &adapter->params.sge.qset[pi->first_qset]; 1907 q = &adapter->params.sge.qset[pi->first_qset];
1839 for (i = 0; i < pi->nqsets; ++i, ++q) { 1908 for (i = 0; i < pi->nqsets; ++i, ++q) {
1840 q->rspq_size = e->rx_mini_pending; 1909 q->rspq_size = e->rx_mini_pending;
1841 q->fl_size = e->rx_pending; 1910 q->fl_size = e->rx_pending;
1842 q->jumbo_size = e->rx_jumbo_pending; 1911 q->jumbo_size = e->rx_jumbo_pending;
1843 q->txq_size[0] = e->tx_pending; 1912 q->txq_size[0] = e->tx_pending;
1844 q->txq_size[1] = e->tx_pending; 1913 q->txq_size[1] = e->tx_pending;
1845 q->txq_size[2] = e->tx_pending; 1914 q->txq_size[2] = e->tx_pending;
1846 } 1915 }
1847 return 0; 1916 return 0;
1848 } 1917 }
1849 1918
1850 static int set_coalesce(struct net_device *dev, struct ethtool_coalesce *c) 1919 static int set_coalesce(struct net_device *dev, struct ethtool_coalesce *c)
1851 { 1920 {
1852 struct port_info *pi = netdev_priv(dev); 1921 struct port_info *pi = netdev_priv(dev);
1853 struct adapter *adapter = pi->adapter; 1922 struct adapter *adapter = pi->adapter;
1854 struct qset_params *qsp = &adapter->params.sge.qset[0]; 1923 struct qset_params *qsp = &adapter->params.sge.qset[0];
1855 struct sge_qset *qs = &adapter->sge.qs[0]; 1924 struct sge_qset *qs = &adapter->sge.qs[0];
1856 1925
1857 if (c->rx_coalesce_usecs * 10 > M_NEWTIMER) 1926 if (c->rx_coalesce_usecs * 10 > M_NEWTIMER)
1858 return -EINVAL; 1927 return -EINVAL;
1859 1928
1860 qsp->coalesce_usecs = c->rx_coalesce_usecs; 1929 qsp->coalesce_usecs = c->rx_coalesce_usecs;
1861 t3_update_qset_coalesce(qs, qsp); 1930 t3_update_qset_coalesce(qs, qsp);
1862 return 0; 1931 return 0;
1863 } 1932 }
1864 1933
1865 static int get_coalesce(struct net_device *dev, struct ethtool_coalesce *c) 1934 static int get_coalesce(struct net_device *dev, struct ethtool_coalesce *c)
1866 { 1935 {
1867 struct port_info *pi = netdev_priv(dev); 1936 struct port_info *pi = netdev_priv(dev);
1868 struct adapter *adapter = pi->adapter; 1937 struct adapter *adapter = pi->adapter;
1869 struct qset_params *q = adapter->params.sge.qset; 1938 struct qset_params *q = adapter->params.sge.qset;
1870 1939
1871 c->rx_coalesce_usecs = q->coalesce_usecs; 1940 c->rx_coalesce_usecs = q->coalesce_usecs;
1872 return 0; 1941 return 0;
1873 } 1942 }
1874 1943
1875 static int get_eeprom(struct net_device *dev, struct ethtool_eeprom *e, 1944 static int get_eeprom(struct net_device *dev, struct ethtool_eeprom *e,
1876 u8 * data) 1945 u8 * data)
1877 { 1946 {
1878 struct port_info *pi = netdev_priv(dev); 1947 struct port_info *pi = netdev_priv(dev);
1879 struct adapter *adapter = pi->adapter; 1948 struct adapter *adapter = pi->adapter;
1880 int i, err = 0; 1949 int i, err = 0;
1881 1950
1882 u8 *buf = kmalloc(EEPROMSIZE, GFP_KERNEL); 1951 u8 *buf = kmalloc(EEPROMSIZE, GFP_KERNEL);
1883 if (!buf) 1952 if (!buf)
1884 return -ENOMEM; 1953 return -ENOMEM;
1885 1954
1886 e->magic = EEPROM_MAGIC; 1955 e->magic = EEPROM_MAGIC;
1887 for (i = e->offset & ~3; !err && i < e->offset + e->len; i += 4) 1956 for (i = e->offset & ~3; !err && i < e->offset + e->len; i += 4)
1888 err = t3_seeprom_read(adapter, i, (__le32 *) & buf[i]); 1957 err = t3_seeprom_read(adapter, i, (__le32 *) & buf[i]);
1889 1958
1890 if (!err) 1959 if (!err)
1891 memcpy(data, buf + e->offset, e->len); 1960 memcpy(data, buf + e->offset, e->len);
1892 kfree(buf); 1961 kfree(buf);
1893 return err; 1962 return err;
1894 } 1963 }
1895 1964
1896 static int set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, 1965 static int set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
1897 u8 * data) 1966 u8 * data)
1898 { 1967 {
1899 struct port_info *pi = netdev_priv(dev); 1968 struct port_info *pi = netdev_priv(dev);
1900 struct adapter *adapter = pi->adapter; 1969 struct adapter *adapter = pi->adapter;
1901 u32 aligned_offset, aligned_len; 1970 u32 aligned_offset, aligned_len;
1902 __le32 *p; 1971 __le32 *p;
1903 u8 *buf; 1972 u8 *buf;
1904 int err; 1973 int err;
1905 1974
1906 if (eeprom->magic != EEPROM_MAGIC) 1975 if (eeprom->magic != EEPROM_MAGIC)
1907 return -EINVAL; 1976 return -EINVAL;
1908 1977
1909 aligned_offset = eeprom->offset & ~3; 1978 aligned_offset = eeprom->offset & ~3;
1910 aligned_len = (eeprom->len + (eeprom->offset & 3) + 3) & ~3; 1979 aligned_len = (eeprom->len + (eeprom->offset & 3) + 3) & ~3;
1911 1980
1912 if (aligned_offset != eeprom->offset || aligned_len != eeprom->len) { 1981 if (aligned_offset != eeprom->offset || aligned_len != eeprom->len) {
1913 buf = kmalloc(aligned_len, GFP_KERNEL); 1982 buf = kmalloc(aligned_len, GFP_KERNEL);
1914 if (!buf) 1983 if (!buf)
1915 return -ENOMEM; 1984 return -ENOMEM;
1916 err = t3_seeprom_read(adapter, aligned_offset, (__le32 *) buf); 1985 err = t3_seeprom_read(adapter, aligned_offset, (__le32 *) buf);
1917 if (!err && aligned_len > 4) 1986 if (!err && aligned_len > 4)
1918 err = t3_seeprom_read(adapter, 1987 err = t3_seeprom_read(adapter,
1919 aligned_offset + aligned_len - 4, 1988 aligned_offset + aligned_len - 4,
1920 (__le32 *) & buf[aligned_len - 4]); 1989 (__le32 *) & buf[aligned_len - 4]);
1921 if (err) 1990 if (err)
1922 goto out; 1991 goto out;
1923 memcpy(buf + (eeprom->offset & 3), data, eeprom->len); 1992 memcpy(buf + (eeprom->offset & 3), data, eeprom->len);
1924 } else 1993 } else
1925 buf = data; 1994 buf = data;
1926 1995
1927 err = t3_seeprom_wp(adapter, 0); 1996 err = t3_seeprom_wp(adapter, 0);
1928 if (err) 1997 if (err)
1929 goto out; 1998 goto out;
1930 1999
1931 for (p = (__le32 *) buf; !err && aligned_len; aligned_len -= 4, p++) { 2000 for (p = (__le32 *) buf; !err && aligned_len; aligned_len -= 4, p++) {
1932 err = t3_seeprom_write(adapter, aligned_offset, *p); 2001 err = t3_seeprom_write(adapter, aligned_offset, *p);
1933 aligned_offset += 4; 2002 aligned_offset += 4;
1934 } 2003 }
1935 2004
1936 if (!err) 2005 if (!err)
1937 err = t3_seeprom_wp(adapter, 1); 2006 err = t3_seeprom_wp(adapter, 1);
1938 out: 2007 out:
1939 if (buf != data) 2008 if (buf != data)
1940 kfree(buf); 2009 kfree(buf);
1941 return err; 2010 return err;
1942 } 2011 }
1943 2012
1944 static void get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 2013 static void get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1945 { 2014 {
1946 wol->supported = 0; 2015 wol->supported = 0;
1947 wol->wolopts = 0; 2016 wol->wolopts = 0;
1948 memset(&wol->sopass, 0, sizeof(wol->sopass)); 2017 memset(&wol->sopass, 0, sizeof(wol->sopass));
1949 } 2018 }
1950 2019
1951 static const struct ethtool_ops cxgb_ethtool_ops = { 2020 static const struct ethtool_ops cxgb_ethtool_ops = {
1952 .get_settings = get_settings, 2021 .get_settings = get_settings,
1953 .set_settings = set_settings, 2022 .set_settings = set_settings,
1954 .get_drvinfo = get_drvinfo, 2023 .get_drvinfo = get_drvinfo,
1955 .get_msglevel = get_msglevel, 2024 .get_msglevel = get_msglevel,
1956 .set_msglevel = set_msglevel, 2025 .set_msglevel = set_msglevel,
1957 .get_ringparam = get_sge_param, 2026 .get_ringparam = get_sge_param,
1958 .set_ringparam = set_sge_param, 2027 .set_ringparam = set_sge_param,
1959 .get_coalesce = get_coalesce, 2028 .get_coalesce = get_coalesce,
1960 .set_coalesce = set_coalesce, 2029 .set_coalesce = set_coalesce,
1961 .get_eeprom_len = get_eeprom_len, 2030 .get_eeprom_len = get_eeprom_len,
1962 .get_eeprom = get_eeprom, 2031 .get_eeprom = get_eeprom,
1963 .set_eeprom = set_eeprom, 2032 .set_eeprom = set_eeprom,
1964 .get_pauseparam = get_pauseparam, 2033 .get_pauseparam = get_pauseparam,
1965 .set_pauseparam = set_pauseparam, 2034 .set_pauseparam = set_pauseparam,
1966 .get_rx_csum = get_rx_csum, 2035 .get_rx_csum = get_rx_csum,
1967 .set_rx_csum = set_rx_csum, 2036 .set_rx_csum = set_rx_csum,
1968 .set_tx_csum = ethtool_op_set_tx_csum, 2037 .set_tx_csum = ethtool_op_set_tx_csum,
1969 .set_sg = ethtool_op_set_sg, 2038 .set_sg = ethtool_op_set_sg,
1970 .get_link = ethtool_op_get_link, 2039 .get_link = ethtool_op_get_link,
1971 .get_strings = get_strings, 2040 .get_strings = get_strings,
1972 .phys_id = cxgb3_phys_id, 2041 .phys_id = cxgb3_phys_id,
1973 .nway_reset = restart_autoneg, 2042 .nway_reset = restart_autoneg,
1974 .get_sset_count = get_sset_count, 2043 .get_sset_count = get_sset_count,
1975 .get_ethtool_stats = get_stats, 2044 .get_ethtool_stats = get_stats,
1976 .get_regs_len = get_regs_len, 2045 .get_regs_len = get_regs_len,
1977 .get_regs = get_regs, 2046 .get_regs = get_regs,
1978 .get_wol = get_wol, 2047 .get_wol = get_wol,
1979 .set_tso = ethtool_op_set_tso, 2048 .set_tso = ethtool_op_set_tso,
1980 }; 2049 };
1981 2050
1982 static int in_range(int val, int lo, int hi) 2051 static int in_range(int val, int lo, int hi)
1983 { 2052 {
1984 return val < 0 || (val <= hi && val >= lo); 2053 return val < 0 || (val <= hi && val >= lo);
1985 } 2054 }
1986 2055
1987 static int cxgb_extension_ioctl(struct net_device *dev, void __user *useraddr) 2056 static int cxgb_extension_ioctl(struct net_device *dev, void __user *useraddr)
1988 { 2057 {
1989 struct port_info *pi = netdev_priv(dev); 2058 struct port_info *pi = netdev_priv(dev);
1990 struct adapter *adapter = pi->adapter; 2059 struct adapter *adapter = pi->adapter;
1991 u32 cmd; 2060 u32 cmd;
1992 int ret; 2061 int ret;
1993 2062
1994 if (copy_from_user(&cmd, useraddr, sizeof(cmd))) 2063 if (copy_from_user(&cmd, useraddr, sizeof(cmd)))
1995 return -EFAULT; 2064 return -EFAULT;
1996 2065
1997 switch (cmd) { 2066 switch (cmd) {
1998 case CHELSIO_SET_QSET_PARAMS:{ 2067 case CHELSIO_SET_QSET_PARAMS:{
1999 int i; 2068 int i;
2000 struct qset_params *q; 2069 struct qset_params *q;
2001 struct ch_qset_params t; 2070 struct ch_qset_params t;
2002 int q1 = pi->first_qset; 2071 int q1 = pi->first_qset;
2003 int nqsets = pi->nqsets; 2072 int nqsets = pi->nqsets;
2004 2073
2005 if (!capable(CAP_NET_ADMIN)) 2074 if (!capable(CAP_NET_ADMIN))
2006 return -EPERM; 2075 return -EPERM;
2007 if (copy_from_user(&t, useraddr, sizeof(t))) 2076 if (copy_from_user(&t, useraddr, sizeof(t)))
2008 return -EFAULT; 2077 return -EFAULT;
2009 if (t.qset_idx >= SGE_QSETS) 2078 if (t.qset_idx >= SGE_QSETS)
2010 return -EINVAL; 2079 return -EINVAL;
2011 if (!in_range(t.intr_lat, 0, M_NEWTIMER) || 2080 if (!in_range(t.intr_lat, 0, M_NEWTIMER) ||
2012 !in_range(t.cong_thres, 0, 255) || 2081 !in_range(t.cong_thres, 0, 255) ||
2013 !in_range(t.txq_size[0], MIN_TXQ_ENTRIES, 2082 !in_range(t.txq_size[0], MIN_TXQ_ENTRIES,
2014 MAX_TXQ_ENTRIES) || 2083 MAX_TXQ_ENTRIES) ||
2015 !in_range(t.txq_size[1], MIN_TXQ_ENTRIES, 2084 !in_range(t.txq_size[1], MIN_TXQ_ENTRIES,
2016 MAX_TXQ_ENTRIES) || 2085 MAX_TXQ_ENTRIES) ||
2017 !in_range(t.txq_size[2], MIN_CTRL_TXQ_ENTRIES, 2086 !in_range(t.txq_size[2], MIN_CTRL_TXQ_ENTRIES,
2018 MAX_CTRL_TXQ_ENTRIES) || 2087 MAX_CTRL_TXQ_ENTRIES) ||
2019 !in_range(t.fl_size[0], MIN_FL_ENTRIES, 2088 !in_range(t.fl_size[0], MIN_FL_ENTRIES,
2020 MAX_RX_BUFFERS) 2089 MAX_RX_BUFFERS)
2021 || !in_range(t.fl_size[1], MIN_FL_ENTRIES, 2090 || !in_range(t.fl_size[1], MIN_FL_ENTRIES,
2022 MAX_RX_JUMBO_BUFFERS) 2091 MAX_RX_JUMBO_BUFFERS)
2023 || !in_range(t.rspq_size, MIN_RSPQ_ENTRIES, 2092 || !in_range(t.rspq_size, MIN_RSPQ_ENTRIES,
2024 MAX_RSPQ_ENTRIES)) 2093 MAX_RSPQ_ENTRIES))
2025 return -EINVAL; 2094 return -EINVAL;
2026 2095
2027 if ((adapter->flags & FULL_INIT_DONE) && t.lro > 0) 2096 if ((adapter->flags & FULL_INIT_DONE) && t.lro > 0)
2028 for_each_port(adapter, i) { 2097 for_each_port(adapter, i) {
2029 pi = adap2pinfo(adapter, i); 2098 pi = adap2pinfo(adapter, i);
2030 if (t.qset_idx >= pi->first_qset && 2099 if (t.qset_idx >= pi->first_qset &&
2031 t.qset_idx < pi->first_qset + pi->nqsets && 2100 t.qset_idx < pi->first_qset + pi->nqsets &&
2032 !(pi->rx_offload & T3_RX_CSUM)) 2101 !(pi->rx_offload & T3_RX_CSUM))
2033 return -EINVAL; 2102 return -EINVAL;
2034 } 2103 }
2035 2104
2036 if ((adapter->flags & FULL_INIT_DONE) && 2105 if ((adapter->flags & FULL_INIT_DONE) &&
2037 (t.rspq_size >= 0 || t.fl_size[0] >= 0 || 2106 (t.rspq_size >= 0 || t.fl_size[0] >= 0 ||
2038 t.fl_size[1] >= 0 || t.txq_size[0] >= 0 || 2107 t.fl_size[1] >= 0 || t.txq_size[0] >= 0 ||
2039 t.txq_size[1] >= 0 || t.txq_size[2] >= 0 || 2108 t.txq_size[1] >= 0 || t.txq_size[2] >= 0 ||
2040 t.polling >= 0 || t.cong_thres >= 0)) 2109 t.polling >= 0 || t.cong_thres >= 0))
2041 return -EBUSY; 2110 return -EBUSY;
2042 2111
2043 /* Allow setting of any available qset when offload enabled */ 2112 /* Allow setting of any available qset when offload enabled */
2044 if (test_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map)) { 2113 if (test_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map)) {
2045 q1 = 0; 2114 q1 = 0;
2046 for_each_port(adapter, i) { 2115 for_each_port(adapter, i) {
2047 pi = adap2pinfo(adapter, i); 2116 pi = adap2pinfo(adapter, i);
2048 nqsets += pi->first_qset + pi->nqsets; 2117 nqsets += pi->first_qset + pi->nqsets;
2049 } 2118 }
2050 } 2119 }
2051 2120
2052 if (t.qset_idx < q1) 2121 if (t.qset_idx < q1)
2053 return -EINVAL; 2122 return -EINVAL;
2054 if (t.qset_idx > q1 + nqsets - 1) 2123 if (t.qset_idx > q1 + nqsets - 1)
2055 return -EINVAL; 2124 return -EINVAL;
2056 2125
2057 q = &adapter->params.sge.qset[t.qset_idx]; 2126 q = &adapter->params.sge.qset[t.qset_idx];
2058 2127
2059 if (t.rspq_size >= 0) 2128 if (t.rspq_size >= 0)
2060 q->rspq_size = t.rspq_size; 2129 q->rspq_size = t.rspq_size;
2061 if (t.fl_size[0] >= 0) 2130 if (t.fl_size[0] >= 0)
2062 q->fl_size = t.fl_size[0]; 2131 q->fl_size = t.fl_size[0];
2063 if (t.fl_size[1] >= 0) 2132 if (t.fl_size[1] >= 0)
2064 q->jumbo_size = t.fl_size[1]; 2133 q->jumbo_size = t.fl_size[1];
2065 if (t.txq_size[0] >= 0) 2134 if (t.txq_size[0] >= 0)
2066 q->txq_size[0] = t.txq_size[0]; 2135 q->txq_size[0] = t.txq_size[0];
2067 if (t.txq_size[1] >= 0) 2136 if (t.txq_size[1] >= 0)
2068 q->txq_size[1] = t.txq_size[1]; 2137 q->txq_size[1] = t.txq_size[1];
2069 if (t.txq_size[2] >= 0) 2138 if (t.txq_size[2] >= 0)
2070 q->txq_size[2] = t.txq_size[2]; 2139 q->txq_size[2] = t.txq_size[2];
2071 if (t.cong_thres >= 0) 2140 if (t.cong_thres >= 0)
2072 q->cong_thres = t.cong_thres; 2141 q->cong_thres = t.cong_thres;
2073 if (t.intr_lat >= 0) { 2142 if (t.intr_lat >= 0) {
2074 struct sge_qset *qs = 2143 struct sge_qset *qs =
2075 &adapter->sge.qs[t.qset_idx]; 2144 &adapter->sge.qs[t.qset_idx];
2076 2145
2077 q->coalesce_usecs = t.intr_lat; 2146 q->coalesce_usecs = t.intr_lat;
2078 t3_update_qset_coalesce(qs, q); 2147 t3_update_qset_coalesce(qs, q);
2079 } 2148 }
2080 if (t.polling >= 0) { 2149 if (t.polling >= 0) {
2081 if (adapter->flags & USING_MSIX) 2150 if (adapter->flags & USING_MSIX)
2082 q->polling = t.polling; 2151 q->polling = t.polling;
2083 else { 2152 else {
2084 /* No polling with INTx for T3A */ 2153 /* No polling with INTx for T3A */
2085 if (adapter->params.rev == 0 && 2154 if (adapter->params.rev == 0 &&
2086 !(adapter->flags & USING_MSI)) 2155 !(adapter->flags & USING_MSI))
2087 t.polling = 0; 2156 t.polling = 0;
2088 2157
2089 for (i = 0; i < SGE_QSETS; i++) { 2158 for (i = 0; i < SGE_QSETS; i++) {
2090 q = &adapter->params.sge. 2159 q = &adapter->params.sge.
2091 qset[i]; 2160 qset[i];
2092 q->polling = t.polling; 2161 q->polling = t.polling;
2093 } 2162 }
2094 } 2163 }
2095 } 2164 }
2096 if (t.lro >= 0) 2165 if (t.lro >= 0)
2097 set_qset_lro(dev, t.qset_idx, t.lro); 2166 set_qset_lro(dev, t.qset_idx, t.lro);
2098 2167
2099 break; 2168 break;
2100 } 2169 }
2101 case CHELSIO_GET_QSET_PARAMS:{ 2170 case CHELSIO_GET_QSET_PARAMS:{
2102 struct qset_params *q; 2171 struct qset_params *q;
2103 struct ch_qset_params t; 2172 struct ch_qset_params t;
2104 int q1 = pi->first_qset; 2173 int q1 = pi->first_qset;
2105 int nqsets = pi->nqsets; 2174 int nqsets = pi->nqsets;
2106 int i; 2175 int i;
2107 2176
2108 if (copy_from_user(&t, useraddr, sizeof(t))) 2177 if (copy_from_user(&t, useraddr, sizeof(t)))
2109 return -EFAULT; 2178 return -EFAULT;
2110 2179
2111 /* Display qsets for all ports when offload enabled */ 2180 /* Display qsets for all ports when offload enabled */
2112 if (test_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map)) { 2181 if (test_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map)) {
2113 q1 = 0; 2182 q1 = 0;
2114 for_each_port(adapter, i) { 2183 for_each_port(adapter, i) {
2115 pi = adap2pinfo(adapter, i); 2184 pi = adap2pinfo(adapter, i);
2116 nqsets = pi->first_qset + pi->nqsets; 2185 nqsets = pi->first_qset + pi->nqsets;
2117 } 2186 }
2118 } 2187 }
2119 2188
2120 if (t.qset_idx >= nqsets) 2189 if (t.qset_idx >= nqsets)
2121 return -EINVAL; 2190 return -EINVAL;
2122 2191
2123 q = &adapter->params.sge.qset[q1 + t.qset_idx]; 2192 q = &adapter->params.sge.qset[q1 + t.qset_idx];
2124 t.rspq_size = q->rspq_size; 2193 t.rspq_size = q->rspq_size;
2125 t.txq_size[0] = q->txq_size[0]; 2194 t.txq_size[0] = q->txq_size[0];
2126 t.txq_size[1] = q->txq_size[1]; 2195 t.txq_size[1] = q->txq_size[1];
2127 t.txq_size[2] = q->txq_size[2]; 2196 t.txq_size[2] = q->txq_size[2];
2128 t.fl_size[0] = q->fl_size; 2197 t.fl_size[0] = q->fl_size;
2129 t.fl_size[1] = q->jumbo_size; 2198 t.fl_size[1] = q->jumbo_size;
2130 t.polling = q->polling; 2199 t.polling = q->polling;
2131 t.lro = q->lro; 2200 t.lro = q->lro;
2132 t.intr_lat = q->coalesce_usecs; 2201 t.intr_lat = q->coalesce_usecs;
2133 t.cong_thres = q->cong_thres; 2202 t.cong_thres = q->cong_thres;
2134 t.qnum = q1; 2203 t.qnum = q1;
2135 2204
2136 if (adapter->flags & USING_MSIX) 2205 if (adapter->flags & USING_MSIX)
2137 t.vector = adapter->msix_info[q1 + t.qset_idx + 1].vec; 2206 t.vector = adapter->msix_info[q1 + t.qset_idx + 1].vec;
2138 else 2207 else
2139 t.vector = adapter->pdev->irq; 2208 t.vector = adapter->pdev->irq;
2140 2209
2141 if (copy_to_user(useraddr, &t, sizeof(t))) 2210 if (copy_to_user(useraddr, &t, sizeof(t)))
2142 return -EFAULT; 2211 return -EFAULT;
2143 break; 2212 break;
2144 } 2213 }
2145 case CHELSIO_SET_QSET_NUM:{ 2214 case CHELSIO_SET_QSET_NUM:{
2146 struct ch_reg edata; 2215 struct ch_reg edata;
2147 unsigned int i, first_qset = 0, other_qsets = 0; 2216 unsigned int i, first_qset = 0, other_qsets = 0;
2148 2217
2149 if (!capable(CAP_NET_ADMIN)) 2218 if (!capable(CAP_NET_ADMIN))
2150 return -EPERM; 2219 return -EPERM;
2151 if (adapter->flags & FULL_INIT_DONE) 2220 if (adapter->flags & FULL_INIT_DONE)
2152 return -EBUSY; 2221 return -EBUSY;
2153 if (copy_from_user(&edata, useraddr, sizeof(edata))) 2222 if (copy_from_user(&edata, useraddr, sizeof(edata)))
2154 return -EFAULT; 2223 return -EFAULT;
2155 if (edata.val < 1 || 2224 if (edata.val < 1 ||
2156 (edata.val > 1 && !(adapter->flags & USING_MSIX))) 2225 (edata.val > 1 && !(adapter->flags & USING_MSIX)))
2157 return -EINVAL; 2226 return -EINVAL;
2158 2227
2159 for_each_port(adapter, i) 2228 for_each_port(adapter, i)
2160 if (adapter->port[i] && adapter->port[i] != dev) 2229 if (adapter->port[i] && adapter->port[i] != dev)
2161 other_qsets += adap2pinfo(adapter, i)->nqsets; 2230 other_qsets += adap2pinfo(adapter, i)->nqsets;
2162 2231
2163 if (edata.val + other_qsets > SGE_QSETS) 2232 if (edata.val + other_qsets > SGE_QSETS)
2164 return -EINVAL; 2233 return -EINVAL;
2165 2234
2166 pi->nqsets = edata.val; 2235 pi->nqsets = edata.val;
2167 2236
2168 for_each_port(adapter, i) 2237 for_each_port(adapter, i)
2169 if (adapter->port[i]) { 2238 if (adapter->port[i]) {
2170 pi = adap2pinfo(adapter, i); 2239 pi = adap2pinfo(adapter, i);
2171 pi->first_qset = first_qset; 2240 pi->first_qset = first_qset;
2172 first_qset += pi->nqsets; 2241 first_qset += pi->nqsets;
2173 } 2242 }
2174 break; 2243 break;
2175 } 2244 }
2176 case CHELSIO_GET_QSET_NUM:{ 2245 case CHELSIO_GET_QSET_NUM:{
2177 struct ch_reg edata; 2246 struct ch_reg edata;
2178 2247
2179 edata.cmd = CHELSIO_GET_QSET_NUM; 2248 edata.cmd = CHELSIO_GET_QSET_NUM;
2180 edata.val = pi->nqsets; 2249 edata.val = pi->nqsets;
2181 if (copy_to_user(useraddr, &edata, sizeof(edata))) 2250 if (copy_to_user(useraddr, &edata, sizeof(edata)))
2182 return -EFAULT; 2251 return -EFAULT;
2183 break; 2252 break;
2184 } 2253 }
2185 case CHELSIO_LOAD_FW:{ 2254 case CHELSIO_LOAD_FW:{
2186 u8 *fw_data; 2255 u8 *fw_data;
2187 struct ch_mem_range t; 2256 struct ch_mem_range t;
2188 2257
2189 if (!capable(CAP_SYS_RAWIO)) 2258 if (!capable(CAP_SYS_RAWIO))
2190 return -EPERM; 2259 return -EPERM;
2191 if (copy_from_user(&t, useraddr, sizeof(t))) 2260 if (copy_from_user(&t, useraddr, sizeof(t)))
2192 return -EFAULT; 2261 return -EFAULT;
2193 /* Check t.len sanity ? */ 2262 /* Check t.len sanity ? */
2194 fw_data = kmalloc(t.len, GFP_KERNEL); 2263 fw_data = kmalloc(t.len, GFP_KERNEL);
2195 if (!fw_data) 2264 if (!fw_data)
2196 return -ENOMEM; 2265 return -ENOMEM;
2197 2266
2198 if (copy_from_user 2267 if (copy_from_user
2199 (fw_data, useraddr + sizeof(t), t.len)) { 2268 (fw_data, useraddr + sizeof(t), t.len)) {
2200 kfree(fw_data); 2269 kfree(fw_data);
2201 return -EFAULT; 2270 return -EFAULT;
2202 } 2271 }
2203 2272
2204 ret = t3_load_fw(adapter, fw_data, t.len); 2273 ret = t3_load_fw(adapter, fw_data, t.len);
2205 kfree(fw_data); 2274 kfree(fw_data);
2206 if (ret) 2275 if (ret)
2207 return ret; 2276 return ret;
2208 break; 2277 break;
2209 } 2278 }
2210 case CHELSIO_SETMTUTAB:{ 2279 case CHELSIO_SETMTUTAB:{
2211 struct ch_mtus m; 2280 struct ch_mtus m;
2212 int i; 2281 int i;
2213 2282
2214 if (!is_offload(adapter)) 2283 if (!is_offload(adapter))
2215 return -EOPNOTSUPP; 2284 return -EOPNOTSUPP;
2216 if (!capable(CAP_NET_ADMIN)) 2285 if (!capable(CAP_NET_ADMIN))
2217 return -EPERM; 2286 return -EPERM;
2218 if (offload_running(adapter)) 2287 if (offload_running(adapter))
2219 return -EBUSY; 2288 return -EBUSY;
2220 if (copy_from_user(&m, useraddr, sizeof(m))) 2289 if (copy_from_user(&m, useraddr, sizeof(m)))
2221 return -EFAULT; 2290 return -EFAULT;
2222 if (m.nmtus != NMTUS) 2291 if (m.nmtus != NMTUS)
2223 return -EINVAL; 2292 return -EINVAL;
2224 if (m.mtus[0] < 81) /* accommodate SACK */ 2293 if (m.mtus[0] < 81) /* accommodate SACK */
2225 return -EINVAL; 2294 return -EINVAL;
2226 2295
2227 /* MTUs must be in ascending order */ 2296 /* MTUs must be in ascending order */
2228 for (i = 1; i < NMTUS; ++i) 2297 for (i = 1; i < NMTUS; ++i)
2229 if (m.mtus[i] < m.mtus[i - 1]) 2298 if (m.mtus[i] < m.mtus[i - 1])
2230 return -EINVAL; 2299 return -EINVAL;
2231 2300
2232 memcpy(adapter->params.mtus, m.mtus, 2301 memcpy(adapter->params.mtus, m.mtus,
2233 sizeof(adapter->params.mtus)); 2302 sizeof(adapter->params.mtus));
2234 break; 2303 break;
2235 } 2304 }
2236 case CHELSIO_GET_PM:{ 2305 case CHELSIO_GET_PM:{
2237 struct tp_params *p = &adapter->params.tp; 2306 struct tp_params *p = &adapter->params.tp;
2238 struct ch_pm m = {.cmd = CHELSIO_GET_PM }; 2307 struct ch_pm m = {.cmd = CHELSIO_GET_PM };
2239 2308
2240 if (!is_offload(adapter)) 2309 if (!is_offload(adapter))
2241 return -EOPNOTSUPP; 2310 return -EOPNOTSUPP;
2242 m.tx_pg_sz = p->tx_pg_size; 2311 m.tx_pg_sz = p->tx_pg_size;
2243 m.tx_num_pg = p->tx_num_pgs; 2312 m.tx_num_pg = p->tx_num_pgs;
2244 m.rx_pg_sz = p->rx_pg_size; 2313 m.rx_pg_sz = p->rx_pg_size;
2245 m.rx_num_pg = p->rx_num_pgs; 2314 m.rx_num_pg = p->rx_num_pgs;
2246 m.pm_total = p->pmtx_size + p->chan_rx_size * p->nchan; 2315 m.pm_total = p->pmtx_size + p->chan_rx_size * p->nchan;
2247 if (copy_to_user(useraddr, &m, sizeof(m))) 2316 if (copy_to_user(useraddr, &m, sizeof(m)))
2248 return -EFAULT; 2317 return -EFAULT;
2249 break; 2318 break;
2250 } 2319 }
2251 case CHELSIO_SET_PM:{ 2320 case CHELSIO_SET_PM:{
2252 struct ch_pm m; 2321 struct ch_pm m;
2253 struct tp_params *p = &adapter->params.tp; 2322 struct tp_params *p = &adapter->params.tp;
2254 2323
2255 if (!is_offload(adapter)) 2324 if (!is_offload(adapter))
2256 return -EOPNOTSUPP; 2325 return -EOPNOTSUPP;
2257 if (!capable(CAP_NET_ADMIN)) 2326 if (!capable(CAP_NET_ADMIN))
2258 return -EPERM; 2327 return -EPERM;
2259 if (adapter->flags & FULL_INIT_DONE) 2328 if (adapter->flags & FULL_INIT_DONE)
2260 return -EBUSY; 2329 return -EBUSY;
2261 if (copy_from_user(&m, useraddr, sizeof(m))) 2330 if (copy_from_user(&m, useraddr, sizeof(m)))
2262 return -EFAULT; 2331 return -EFAULT;
2263 if (!is_power_of_2(m.rx_pg_sz) || 2332 if (!is_power_of_2(m.rx_pg_sz) ||
2264 !is_power_of_2(m.tx_pg_sz)) 2333 !is_power_of_2(m.tx_pg_sz))
2265 return -EINVAL; /* not power of 2 */ 2334 return -EINVAL; /* not power of 2 */
2266 if (!(m.rx_pg_sz & 0x14000)) 2335 if (!(m.rx_pg_sz & 0x14000))
2267 return -EINVAL; /* not 16KB or 64KB */ 2336 return -EINVAL; /* not 16KB or 64KB */
2268 if (!(m.tx_pg_sz & 0x1554000)) 2337 if (!(m.tx_pg_sz & 0x1554000))
2269 return -EINVAL; 2338 return -EINVAL;
2270 if (m.tx_num_pg == -1) 2339 if (m.tx_num_pg == -1)
2271 m.tx_num_pg = p->tx_num_pgs; 2340 m.tx_num_pg = p->tx_num_pgs;
2272 if (m.rx_num_pg == -1) 2341 if (m.rx_num_pg == -1)
2273 m.rx_num_pg = p->rx_num_pgs; 2342 m.rx_num_pg = p->rx_num_pgs;
2274 if (m.tx_num_pg % 24 || m.rx_num_pg % 24) 2343 if (m.tx_num_pg % 24 || m.rx_num_pg % 24)
2275 return -EINVAL; 2344 return -EINVAL;
2276 if (m.rx_num_pg * m.rx_pg_sz > p->chan_rx_size || 2345 if (m.rx_num_pg * m.rx_pg_sz > p->chan_rx_size ||
2277 m.tx_num_pg * m.tx_pg_sz > p->chan_tx_size) 2346 m.tx_num_pg * m.tx_pg_sz > p->chan_tx_size)
2278 return -EINVAL; 2347 return -EINVAL;
2279 p->rx_pg_size = m.rx_pg_sz; 2348 p->rx_pg_size = m.rx_pg_sz;
2280 p->tx_pg_size = m.tx_pg_sz; 2349 p->tx_pg_size = m.tx_pg_sz;
2281 p->rx_num_pgs = m.rx_num_pg; 2350 p->rx_num_pgs = m.rx_num_pg;
2282 p->tx_num_pgs = m.tx_num_pg; 2351 p->tx_num_pgs = m.tx_num_pg;
2283 break; 2352 break;
2284 } 2353 }
2285 case CHELSIO_GET_MEM:{ 2354 case CHELSIO_GET_MEM:{
2286 struct ch_mem_range t; 2355 struct ch_mem_range t;
2287 struct mc7 *mem; 2356 struct mc7 *mem;
2288 u64 buf[32]; 2357 u64 buf[32];
2289 2358
2290 if (!is_offload(adapter)) 2359 if (!is_offload(adapter))
2291 return -EOPNOTSUPP; 2360 return -EOPNOTSUPP;
2292 if (!(adapter->flags & FULL_INIT_DONE)) 2361 if (!(adapter->flags & FULL_INIT_DONE))
2293 return -EIO; /* need the memory controllers */ 2362 return -EIO; /* need the memory controllers */
2294 if (copy_from_user(&t, useraddr, sizeof(t))) 2363 if (copy_from_user(&t, useraddr, sizeof(t)))
2295 return -EFAULT; 2364 return -EFAULT;
2296 if ((t.addr & 7) || (t.len & 7)) 2365 if ((t.addr & 7) || (t.len & 7))
2297 return -EINVAL; 2366 return -EINVAL;
2298 if (t.mem_id == MEM_CM) 2367 if (t.mem_id == MEM_CM)
2299 mem = &adapter->cm; 2368 mem = &adapter->cm;
2300 else if (t.mem_id == MEM_PMRX) 2369 else if (t.mem_id == MEM_PMRX)
2301 mem = &adapter->pmrx; 2370 mem = &adapter->pmrx;
2302 else if (t.mem_id == MEM_PMTX) 2371 else if (t.mem_id == MEM_PMTX)
2303 mem = &adapter->pmtx; 2372 mem = &adapter->pmtx;
2304 else 2373 else
2305 return -EINVAL; 2374 return -EINVAL;
2306 2375
2307 /* 2376 /*
2308 * Version scheme: 2377 * Version scheme:
2309 * bits 0..9: chip version 2378 * bits 0..9: chip version
2310 * bits 10..15: chip revision 2379 * bits 10..15: chip revision
2311 */ 2380 */
2312 t.version = 3 | (adapter->params.rev << 10); 2381 t.version = 3 | (adapter->params.rev << 10);
2313 if (copy_to_user(useraddr, &t, sizeof(t))) 2382 if (copy_to_user(useraddr, &t, sizeof(t)))
2314 return -EFAULT; 2383 return -EFAULT;
2315 2384
2316 /* 2385 /*
2317 * Read 256 bytes at a time as len can be large and we don't 2386 * Read 256 bytes at a time as len can be large and we don't
2318 * want to use huge intermediate buffers. 2387 * want to use huge intermediate buffers.
2319 */ 2388 */
2320 useraddr += sizeof(t); /* advance to start of buffer */ 2389 useraddr += sizeof(t); /* advance to start of buffer */
2321 while (t.len) { 2390 while (t.len) {
2322 unsigned int chunk = 2391 unsigned int chunk =
2323 min_t(unsigned int, t.len, sizeof(buf)); 2392 min_t(unsigned int, t.len, sizeof(buf));
2324 2393
2325 ret = 2394 ret =
2326 t3_mc7_bd_read(mem, t.addr / 8, chunk / 8, 2395 t3_mc7_bd_read(mem, t.addr / 8, chunk / 8,
2327 buf); 2396 buf);
2328 if (ret) 2397 if (ret)
2329 return ret; 2398 return ret;
2330 if (copy_to_user(useraddr, buf, chunk)) 2399 if (copy_to_user(useraddr, buf, chunk))
2331 return -EFAULT; 2400 return -EFAULT;
2332 useraddr += chunk; 2401 useraddr += chunk;
2333 t.addr += chunk; 2402 t.addr += chunk;
2334 t.len -= chunk; 2403 t.len -= chunk;
2335 } 2404 }
2336 break; 2405 break;
2337 } 2406 }
2338 case CHELSIO_SET_TRACE_FILTER:{ 2407 case CHELSIO_SET_TRACE_FILTER:{
2339 struct ch_trace t; 2408 struct ch_trace t;
2340 const struct trace_params *tp; 2409 const struct trace_params *tp;
2341 2410
2342 if (!capable(CAP_NET_ADMIN)) 2411 if (!capable(CAP_NET_ADMIN))
2343 return -EPERM; 2412 return -EPERM;
2344 if (!offload_running(adapter)) 2413 if (!offload_running(adapter))
2345 return -EAGAIN; 2414 return -EAGAIN;
2346 if (copy_from_user(&t, useraddr, sizeof(t))) 2415 if (copy_from_user(&t, useraddr, sizeof(t)))
2347 return -EFAULT; 2416 return -EFAULT;
2348 2417
2349 tp = (const struct trace_params *)&t.sip; 2418 tp = (const struct trace_params *)&t.sip;
2350 if (t.config_tx) 2419 if (t.config_tx)
2351 t3_config_trace_filter(adapter, tp, 0, 2420 t3_config_trace_filter(adapter, tp, 0,
2352 t.invert_match, 2421 t.invert_match,
2353 t.trace_tx); 2422 t.trace_tx);
2354 if (t.config_rx) 2423 if (t.config_rx)
2355 t3_config_trace_filter(adapter, tp, 1, 2424 t3_config_trace_filter(adapter, tp, 1,
2356 t.invert_match, 2425 t.invert_match,
2357 t.trace_rx); 2426 t.trace_rx);
2358 break; 2427 break;
2359 } 2428 }
2360 default: 2429 default:
2361 return -EOPNOTSUPP; 2430 return -EOPNOTSUPP;
2362 } 2431 }
2363 return 0; 2432 return 0;
2364 } 2433 }
2365 2434
2366 static int cxgb_ioctl(struct net_device *dev, struct ifreq *req, int cmd) 2435 static int cxgb_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
2367 { 2436 {
2368 struct mii_ioctl_data *data = if_mii(req); 2437 struct mii_ioctl_data *data = if_mii(req);
2369 struct port_info *pi = netdev_priv(dev); 2438 struct port_info *pi = netdev_priv(dev);
2370 struct adapter *adapter = pi->adapter; 2439 struct adapter *adapter = pi->adapter;
2371 2440
2372 switch (cmd) { 2441 switch (cmd) {
2373 case SIOCGMIIREG: 2442 case SIOCGMIIREG:
2374 case SIOCSMIIREG: 2443 case SIOCSMIIREG:
2375 /* Convert phy_id from older PRTAD/DEVAD format */ 2444 /* Convert phy_id from older PRTAD/DEVAD format */
2376 if (is_10G(adapter) && 2445 if (is_10G(adapter) &&
2377 !mdio_phy_id_is_c45(data->phy_id) && 2446 !mdio_phy_id_is_c45(data->phy_id) &&
2378 (data->phy_id & 0x1f00) && 2447 (data->phy_id & 0x1f00) &&
2379 !(data->phy_id & 0xe0e0)) 2448 !(data->phy_id & 0xe0e0))
2380 data->phy_id = mdio_phy_id_c45(data->phy_id >> 8, 2449 data->phy_id = mdio_phy_id_c45(data->phy_id >> 8,
2381 data->phy_id & 0x1f); 2450 data->phy_id & 0x1f);
2382 /* FALLTHRU */ 2451 /* FALLTHRU */
2383 case SIOCGMIIPHY: 2452 case SIOCGMIIPHY:
2384 return mdio_mii_ioctl(&pi->phy.mdio, data, cmd); 2453 return mdio_mii_ioctl(&pi->phy.mdio, data, cmd);
2385 case SIOCCHIOCTL: 2454 case SIOCCHIOCTL:
2386 return cxgb_extension_ioctl(dev, req->ifr_data); 2455 return cxgb_extension_ioctl(dev, req->ifr_data);
2387 default: 2456 default:
2388 return -EOPNOTSUPP; 2457 return -EOPNOTSUPP;
2389 } 2458 }
2390 } 2459 }
2391 2460
2392 static int cxgb_change_mtu(struct net_device *dev, int new_mtu) 2461 static int cxgb_change_mtu(struct net_device *dev, int new_mtu)
2393 { 2462 {
2394 struct port_info *pi = netdev_priv(dev); 2463 struct port_info *pi = netdev_priv(dev);
2395 struct adapter *adapter = pi->adapter; 2464 struct adapter *adapter = pi->adapter;
2396 int ret; 2465 int ret;
2397 2466
2398 if (new_mtu < 81) /* accommodate SACK */ 2467 if (new_mtu < 81) /* accommodate SACK */
2399 return -EINVAL; 2468 return -EINVAL;
2400 if ((ret = t3_mac_set_mtu(&pi->mac, new_mtu))) 2469 if ((ret = t3_mac_set_mtu(&pi->mac, new_mtu)))
2401 return ret; 2470 return ret;
2402 dev->mtu = new_mtu; 2471 dev->mtu = new_mtu;
2403 init_port_mtus(adapter); 2472 init_port_mtus(adapter);
2404 if (adapter->params.rev == 0 && offload_running(adapter)) 2473 if (adapter->params.rev == 0 && offload_running(adapter))
2405 t3_load_mtus(adapter, adapter->params.mtus, 2474 t3_load_mtus(adapter, adapter->params.mtus,
2406 adapter->params.a_wnd, adapter->params.b_wnd, 2475 adapter->params.a_wnd, adapter->params.b_wnd,
2407 adapter->port[0]->mtu); 2476 adapter->port[0]->mtu);
2408 return 0; 2477 return 0;
2409 } 2478 }
2410 2479
2411 static int cxgb_set_mac_addr(struct net_device *dev, void *p) 2480 static int cxgb_set_mac_addr(struct net_device *dev, void *p)
2412 { 2481 {
2413 struct port_info *pi = netdev_priv(dev); 2482 struct port_info *pi = netdev_priv(dev);
2414 struct adapter *adapter = pi->adapter; 2483 struct adapter *adapter = pi->adapter;
2415 struct sockaddr *addr = p; 2484 struct sockaddr *addr = p;
2416 2485
2417 if (!is_valid_ether_addr(addr->sa_data)) 2486 if (!is_valid_ether_addr(addr->sa_data))
2418 return -EINVAL; 2487 return -EINVAL;
2419 2488
2420 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); 2489 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2421 t3_mac_set_address(&pi->mac, 0, dev->dev_addr); 2490 t3_mac_set_address(&pi->mac, 0, dev->dev_addr);
2422 if (offload_running(adapter)) 2491 if (offload_running(adapter))
2423 write_smt_entry(adapter, pi->port_id); 2492 write_smt_entry(adapter, pi->port_id);
2424 return 0; 2493 return 0;
2425 } 2494 }
2426 2495
2427 /** 2496 /**
2428 * t3_synchronize_rx - wait for current Rx processing on a port to complete 2497 * t3_synchronize_rx - wait for current Rx processing on a port to complete
2429 * @adap: the adapter 2498 * @adap: the adapter
2430 * @p: the port 2499 * @p: the port
2431 * 2500 *
2432 * Ensures that current Rx processing on any of the queues associated with 2501 * Ensures that current Rx processing on any of the queues associated with
2433 * the given port completes before returning. We do this by acquiring and 2502 * the given port completes before returning. We do this by acquiring and
2434 * releasing the locks of the response queues associated with the port. 2503 * releasing the locks of the response queues associated with the port.
2435 */ 2504 */
2436 static void t3_synchronize_rx(struct adapter *adap, const struct port_info *p) 2505 static void t3_synchronize_rx(struct adapter *adap, const struct port_info *p)
2437 { 2506 {
2438 int i; 2507 int i;
2439 2508
2440 for (i = p->first_qset; i < p->first_qset + p->nqsets; i++) { 2509 for (i = p->first_qset; i < p->first_qset + p->nqsets; i++) {
2441 struct sge_rspq *q = &adap->sge.qs[i].rspq; 2510 struct sge_rspq *q = &adap->sge.qs[i].rspq;
2442 2511
2443 spin_lock_irq(&q->lock); 2512 spin_lock_irq(&q->lock);
2444 spin_unlock_irq(&q->lock); 2513 spin_unlock_irq(&q->lock);
2445 } 2514 }
2446 } 2515 }
2447 2516
2448 static void vlan_rx_register(struct net_device *dev, struct vlan_group *grp) 2517 static void vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
2449 { 2518 {
2450 struct port_info *pi = netdev_priv(dev); 2519 struct port_info *pi = netdev_priv(dev);
2451 struct adapter *adapter = pi->adapter; 2520 struct adapter *adapter = pi->adapter;
2452 2521
2453 pi->vlan_grp = grp; 2522 pi->vlan_grp = grp;
2454 if (adapter->params.rev > 0) 2523 if (adapter->params.rev > 0)
2455 t3_set_vlan_accel(adapter, 1 << pi->port_id, grp != NULL); 2524 t3_set_vlan_accel(adapter, 1 << pi->port_id, grp != NULL);
2456 else { 2525 else {
2457 /* single control for all ports */ 2526 /* single control for all ports */
2458 unsigned int i, have_vlans = 0; 2527 unsigned int i, have_vlans = 0;
2459 for_each_port(adapter, i) 2528 for_each_port(adapter, i)
2460 have_vlans |= adap2pinfo(adapter, i)->vlan_grp != NULL; 2529 have_vlans |= adap2pinfo(adapter, i)->vlan_grp != NULL;
2461 2530
2462 t3_set_vlan_accel(adapter, 1, have_vlans); 2531 t3_set_vlan_accel(adapter, 1, have_vlans);
2463 } 2532 }
2464 t3_synchronize_rx(adapter, pi); 2533 t3_synchronize_rx(adapter, pi);
2465 } 2534 }
2466 2535
2467 #ifdef CONFIG_NET_POLL_CONTROLLER 2536 #ifdef CONFIG_NET_POLL_CONTROLLER
2468 static void cxgb_netpoll(struct net_device *dev) 2537 static void cxgb_netpoll(struct net_device *dev)
2469 { 2538 {
2470 struct port_info *pi = netdev_priv(dev); 2539 struct port_info *pi = netdev_priv(dev);
2471 struct adapter *adapter = pi->adapter; 2540 struct adapter *adapter = pi->adapter;
2472 int qidx; 2541 int qidx;
2473 2542
2474 for (qidx = pi->first_qset; qidx < pi->first_qset + pi->nqsets; qidx++) { 2543 for (qidx = pi->first_qset; qidx < pi->first_qset + pi->nqsets; qidx++) {
2475 struct sge_qset *qs = &adapter->sge.qs[qidx]; 2544 struct sge_qset *qs = &adapter->sge.qs[qidx];
2476 void *source; 2545 void *source;
2477 2546
2478 if (adapter->flags & USING_MSIX) 2547 if (adapter->flags & USING_MSIX)
2479 source = qs; 2548 source = qs;
2480 else 2549 else
2481 source = adapter; 2550 source = adapter;
2482 2551
2483 t3_intr_handler(adapter, qs->rspq.polling) (0, source); 2552 t3_intr_handler(adapter, qs->rspq.polling) (0, source);
2484 } 2553 }
2485 } 2554 }
2486 #endif 2555 #endif
2487 2556
2488 /* 2557 /*
2489 * Periodic accumulation of MAC statistics. 2558 * Periodic accumulation of MAC statistics.
2490 */ 2559 */
2491 static void mac_stats_update(struct adapter *adapter) 2560 static void mac_stats_update(struct adapter *adapter)
2492 { 2561 {
2493 int i; 2562 int i;
2494 2563
2495 for_each_port(adapter, i) { 2564 for_each_port(adapter, i) {
2496 struct net_device *dev = adapter->port[i]; 2565 struct net_device *dev = adapter->port[i];
2497 struct port_info *p = netdev_priv(dev); 2566 struct port_info *p = netdev_priv(dev);
2498 2567
2499 if (netif_running(dev)) { 2568 if (netif_running(dev)) {
2500 spin_lock(&adapter->stats_lock); 2569 spin_lock(&adapter->stats_lock);
2501 t3_mac_update_stats(&p->mac); 2570 t3_mac_update_stats(&p->mac);
2502 spin_unlock(&adapter->stats_lock); 2571 spin_unlock(&adapter->stats_lock);
2503 } 2572 }
2504 } 2573 }
2505 } 2574 }
2506 2575
2507 static void check_link_status(struct adapter *adapter) 2576 static void check_link_status(struct adapter *adapter)
2508 { 2577 {
2509 int i; 2578 int i;
2510 2579
2511 for_each_port(adapter, i) { 2580 for_each_port(adapter, i) {
2512 struct net_device *dev = adapter->port[i]; 2581 struct net_device *dev = adapter->port[i];
2513 struct port_info *p = netdev_priv(dev); 2582 struct port_info *p = netdev_priv(dev);
2514 int link_fault; 2583 int link_fault;
2515 2584
2516 spin_lock_irq(&adapter->work_lock); 2585 spin_lock_irq(&adapter->work_lock);
2517 link_fault = p->link_fault; 2586 link_fault = p->link_fault;
2518 spin_unlock_irq(&adapter->work_lock); 2587 spin_unlock_irq(&adapter->work_lock);
2519 2588
2520 if (link_fault) { 2589 if (link_fault) {
2521 t3_link_fault(adapter, i); 2590 t3_link_fault(adapter, i);
2522 continue; 2591 continue;
2523 } 2592 }
2524 2593
2525 if (!(p->phy.caps & SUPPORTED_IRQ) && netif_running(dev)) { 2594 if (!(p->phy.caps & SUPPORTED_IRQ) && netif_running(dev)) {
2526 t3_xgm_intr_disable(adapter, i); 2595 t3_xgm_intr_disable(adapter, i);
2527 t3_read_reg(adapter, A_XGM_INT_STATUS + p->mac.offset); 2596 t3_read_reg(adapter, A_XGM_INT_STATUS + p->mac.offset);
2528 2597
2529 t3_link_changed(adapter, i); 2598 t3_link_changed(adapter, i);
2530 t3_xgm_intr_enable(adapter, i); 2599 t3_xgm_intr_enable(adapter, i);
2531 } 2600 }
2532 } 2601 }
2533 } 2602 }
2534 2603
2535 static void check_t3b2_mac(struct adapter *adapter) 2604 static void check_t3b2_mac(struct adapter *adapter)
2536 { 2605 {
2537 int i; 2606 int i;
2538 2607
2539 if (!rtnl_trylock()) /* synchronize with ifdown */ 2608 if (!rtnl_trylock()) /* synchronize with ifdown */
2540 return; 2609 return;
2541 2610
2542 for_each_port(adapter, i) { 2611 for_each_port(adapter, i) {
2543 struct net_device *dev = adapter->port[i]; 2612 struct net_device *dev = adapter->port[i];
2544 struct port_info *p = netdev_priv(dev); 2613 struct port_info *p = netdev_priv(dev);
2545 int status; 2614 int status;
2546 2615
2547 if (!netif_running(dev)) 2616 if (!netif_running(dev))
2548 continue; 2617 continue;
2549 2618
2550 status = 0; 2619 status = 0;
2551 if (netif_running(dev) && netif_carrier_ok(dev)) 2620 if (netif_running(dev) && netif_carrier_ok(dev))
2552 status = t3b2_mac_watchdog_task(&p->mac); 2621 status = t3b2_mac_watchdog_task(&p->mac);
2553 if (status == 1) 2622 if (status == 1)
2554 p->mac.stats.num_toggled++; 2623 p->mac.stats.num_toggled++;
2555 else if (status == 2) { 2624 else if (status == 2) {
2556 struct cmac *mac = &p->mac; 2625 struct cmac *mac = &p->mac;
2557 2626
2558 t3_mac_set_mtu(mac, dev->mtu); 2627 t3_mac_set_mtu(mac, dev->mtu);
2559 t3_mac_set_address(mac, 0, dev->dev_addr); 2628 t3_mac_set_address(mac, 0, dev->dev_addr);
2560 cxgb_set_rxmode(dev); 2629 cxgb_set_rxmode(dev);
2561 t3_link_start(&p->phy, mac, &p->link_config); 2630 t3_link_start(&p->phy, mac, &p->link_config);
2562 t3_mac_enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX); 2631 t3_mac_enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX);
2563 t3_port_intr_enable(adapter, p->port_id); 2632 t3_port_intr_enable(adapter, p->port_id);
2564 p->mac.stats.num_resets++; 2633 p->mac.stats.num_resets++;
2565 } 2634 }
2566 } 2635 }
2567 rtnl_unlock(); 2636 rtnl_unlock();
2568 } 2637 }
2569 2638
2570 2639
2571 static void t3_adap_check_task(struct work_struct *work) 2640 static void t3_adap_check_task(struct work_struct *work)
2572 { 2641 {
2573 struct adapter *adapter = container_of(work, struct adapter, 2642 struct adapter *adapter = container_of(work, struct adapter,
2574 adap_check_task.work); 2643 adap_check_task.work);
2575 const struct adapter_params *p = &adapter->params; 2644 const struct adapter_params *p = &adapter->params;
2576 int port; 2645 int port;
2577 unsigned int v, status, reset; 2646 unsigned int v, status, reset;
2578 2647
2579 adapter->check_task_cnt++; 2648 adapter->check_task_cnt++;
2580 2649
2581 check_link_status(adapter); 2650 check_link_status(adapter);
2582 2651
2583 /* Accumulate MAC stats if needed */ 2652 /* Accumulate MAC stats if needed */
2584 if (!p->linkpoll_period || 2653 if (!p->linkpoll_period ||
2585 (adapter->check_task_cnt * p->linkpoll_period) / 10 >= 2654 (adapter->check_task_cnt * p->linkpoll_period) / 10 >=
2586 p->stats_update_period) { 2655 p->stats_update_period) {
2587 mac_stats_update(adapter); 2656 mac_stats_update(adapter);
2588 adapter->check_task_cnt = 0; 2657 adapter->check_task_cnt = 0;
2589 } 2658 }
2590 2659
2591 if (p->rev == T3_REV_B2) 2660 if (p->rev == T3_REV_B2)
2592 check_t3b2_mac(adapter); 2661 check_t3b2_mac(adapter);
2593 2662
2594 /* 2663 /*
2595 * Scan the XGMAC's to check for various conditions which we want to 2664 * Scan the XGMAC's to check for various conditions which we want to
2596 * monitor in a periodic polling manner rather than via an interrupt 2665 * monitor in a periodic polling manner rather than via an interrupt
2597 * condition. This is used for conditions which would otherwise flood 2666 * condition. This is used for conditions which would otherwise flood
2598 * the system with interrupts and we only really need to know that the 2667 * the system with interrupts and we only really need to know that the
2599 * conditions are "happening" ... For each condition we count the 2668 * conditions are "happening" ... For each condition we count the
2600 * detection of the condition and reset it for the next polling loop. 2669 * detection of the condition and reset it for the next polling loop.
2601 */ 2670 */
2602 for_each_port(adapter, port) { 2671 for_each_port(adapter, port) {
2603 struct cmac *mac = &adap2pinfo(adapter, port)->mac; 2672 struct cmac *mac = &adap2pinfo(adapter, port)->mac;
2604 u32 cause; 2673 u32 cause;
2605 2674
2606 cause = t3_read_reg(adapter, A_XGM_INT_CAUSE + mac->offset); 2675 cause = t3_read_reg(adapter, A_XGM_INT_CAUSE + mac->offset);
2607 reset = 0; 2676 reset = 0;
2608 if (cause & F_RXFIFO_OVERFLOW) { 2677 if (cause & F_RXFIFO_OVERFLOW) {
2609 mac->stats.rx_fifo_ovfl++; 2678 mac->stats.rx_fifo_ovfl++;
2610 reset |= F_RXFIFO_OVERFLOW; 2679 reset |= F_RXFIFO_OVERFLOW;
2611 } 2680 }
2612 2681
2613 t3_write_reg(adapter, A_XGM_INT_CAUSE + mac->offset, reset); 2682 t3_write_reg(adapter, A_XGM_INT_CAUSE + mac->offset, reset);
2614 } 2683 }
2615 2684
2616 /* 2685 /*
2617 * We do the same as above for FL_EMPTY interrupts. 2686 * We do the same as above for FL_EMPTY interrupts.
2618 */ 2687 */
2619 status = t3_read_reg(adapter, A_SG_INT_CAUSE); 2688 status = t3_read_reg(adapter, A_SG_INT_CAUSE);
2620 reset = 0; 2689 reset = 0;
2621 2690
2622 if (status & F_FLEMPTY) { 2691 if (status & F_FLEMPTY) {
2623 struct sge_qset *qs = &adapter->sge.qs[0]; 2692 struct sge_qset *qs = &adapter->sge.qs[0];
2624 int i = 0; 2693 int i = 0;
2625 2694
2626 reset |= F_FLEMPTY; 2695 reset |= F_FLEMPTY;
2627 2696
2628 v = (t3_read_reg(adapter, A_SG_RSPQ_FL_STATUS) >> S_FL0EMPTY) & 2697 v = (t3_read_reg(adapter, A_SG_RSPQ_FL_STATUS) >> S_FL0EMPTY) &
2629 0xffff; 2698 0xffff;
2630 2699
2631 while (v) { 2700 while (v) {
2632 qs->fl[i].empty += (v & 1); 2701 qs->fl[i].empty += (v & 1);
2633 if (i) 2702 if (i)
2634 qs++; 2703 qs++;
2635 i ^= 1; 2704 i ^= 1;
2636 v >>= 1; 2705 v >>= 1;
2637 } 2706 }
2638 } 2707 }
2639 2708
2640 t3_write_reg(adapter, A_SG_INT_CAUSE, reset); 2709 t3_write_reg(adapter, A_SG_INT_CAUSE, reset);
2641 2710
2642 /* Schedule the next check update if any port is active. */ 2711 /* Schedule the next check update if any port is active. */
2643 spin_lock_irq(&adapter->work_lock); 2712 spin_lock_irq(&adapter->work_lock);
2644 if (adapter->open_device_map & PORT_MASK) 2713 if (adapter->open_device_map & PORT_MASK)
2645 schedule_chk_task(adapter); 2714 schedule_chk_task(adapter);
2646 spin_unlock_irq(&adapter->work_lock); 2715 spin_unlock_irq(&adapter->work_lock);
2647 } 2716 }
2648 2717
2649 /* 2718 /*
2650 * Processes external (PHY) interrupts in process context. 2719 * Processes external (PHY) interrupts in process context.
2651 */ 2720 */
2652 static void ext_intr_task(struct work_struct *work) 2721 static void ext_intr_task(struct work_struct *work)
2653 { 2722 {
2654 struct adapter *adapter = container_of(work, struct adapter, 2723 struct adapter *adapter = container_of(work, struct adapter,
2655 ext_intr_handler_task); 2724 ext_intr_handler_task);
2656 int i; 2725 int i;
2657 2726
2658 /* Disable link fault interrupts */ 2727 /* Disable link fault interrupts */
2659 for_each_port(adapter, i) { 2728 for_each_port(adapter, i) {
2660 struct net_device *dev = adapter->port[i]; 2729 struct net_device *dev = adapter->port[i];
2661 struct port_info *p = netdev_priv(dev); 2730 struct port_info *p = netdev_priv(dev);
2662 2731
2663 t3_xgm_intr_disable(adapter, i); 2732 t3_xgm_intr_disable(adapter, i);
2664 t3_read_reg(adapter, A_XGM_INT_STATUS + p->mac.offset); 2733 t3_read_reg(adapter, A_XGM_INT_STATUS + p->mac.offset);
2665 } 2734 }
2666 2735
2667 /* Re-enable link fault interrupts */ 2736 /* Re-enable link fault interrupts */
2668 t3_phy_intr_handler(adapter); 2737 t3_phy_intr_handler(adapter);
2669 2738
2670 for_each_port(adapter, i) 2739 for_each_port(adapter, i)
2671 t3_xgm_intr_enable(adapter, i); 2740 t3_xgm_intr_enable(adapter, i);
2672 2741
2673 /* Now reenable external interrupts */ 2742 /* Now reenable external interrupts */
2674 spin_lock_irq(&adapter->work_lock); 2743 spin_lock_irq(&adapter->work_lock);
2675 if (adapter->slow_intr_mask) { 2744 if (adapter->slow_intr_mask) {
2676 adapter->slow_intr_mask |= F_T3DBG; 2745 adapter->slow_intr_mask |= F_T3DBG;
2677 t3_write_reg(adapter, A_PL_INT_CAUSE0, F_T3DBG); 2746 t3_write_reg(adapter, A_PL_INT_CAUSE0, F_T3DBG);
2678 t3_write_reg(adapter, A_PL_INT_ENABLE0, 2747 t3_write_reg(adapter, A_PL_INT_ENABLE0,
2679 adapter->slow_intr_mask); 2748 adapter->slow_intr_mask);
2680 } 2749 }
2681 spin_unlock_irq(&adapter->work_lock); 2750 spin_unlock_irq(&adapter->work_lock);
2682 } 2751 }
2683 2752
2684 /* 2753 /*
2685 * Interrupt-context handler for external (PHY) interrupts. 2754 * Interrupt-context handler for external (PHY) interrupts.
2686 */ 2755 */
2687 void t3_os_ext_intr_handler(struct adapter *adapter) 2756 void t3_os_ext_intr_handler(struct adapter *adapter)
2688 { 2757 {
2689 /* 2758 /*
2690 * Schedule a task to handle external interrupts as they may be slow 2759 * Schedule a task to handle external interrupts as they may be slow
2691 * and we use a mutex to protect MDIO registers. We disable PHY 2760 * and we use a mutex to protect MDIO registers. We disable PHY
2692 * interrupts in the meantime and let the task reenable them when 2761 * interrupts in the meantime and let the task reenable them when
2693 * it's done. 2762 * it's done.
2694 */ 2763 */
2695 spin_lock(&adapter->work_lock); 2764 spin_lock(&adapter->work_lock);
2696 if (adapter->slow_intr_mask) { 2765 if (adapter->slow_intr_mask) {
2697 adapter->slow_intr_mask &= ~F_T3DBG; 2766 adapter->slow_intr_mask &= ~F_T3DBG;
2698 t3_write_reg(adapter, A_PL_INT_ENABLE0, 2767 t3_write_reg(adapter, A_PL_INT_ENABLE0,
2699 adapter->slow_intr_mask); 2768 adapter->slow_intr_mask);
2700 queue_work(cxgb3_wq, &adapter->ext_intr_handler_task); 2769 queue_work(cxgb3_wq, &adapter->ext_intr_handler_task);
2701 } 2770 }
2702 spin_unlock(&adapter->work_lock); 2771 spin_unlock(&adapter->work_lock);
2703 } 2772 }
2704 2773
2705 void t3_os_link_fault_handler(struct adapter *adapter, int port_id) 2774 void t3_os_link_fault_handler(struct adapter *adapter, int port_id)
2706 { 2775 {
2707 struct net_device *netdev = adapter->port[port_id]; 2776 struct net_device *netdev = adapter->port[port_id];
2708 struct port_info *pi = netdev_priv(netdev); 2777 struct port_info *pi = netdev_priv(netdev);
2709 2778
2710 spin_lock(&adapter->work_lock); 2779 spin_lock(&adapter->work_lock);
2711 pi->link_fault = 1; 2780 pi->link_fault = 1;
2712 spin_unlock(&adapter->work_lock); 2781 spin_unlock(&adapter->work_lock);
2713 } 2782 }
2714 2783
2715 static int t3_adapter_error(struct adapter *adapter, int reset) 2784 static int t3_adapter_error(struct adapter *adapter, int reset)
2716 { 2785 {
2717 int i, ret = 0; 2786 int i, ret = 0;
2718 2787
2719 if (is_offload(adapter) && 2788 if (is_offload(adapter) &&
2720 test_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map)) { 2789 test_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map)) {
2721 cxgb3_err_notify(&adapter->tdev, OFFLOAD_STATUS_DOWN, 0); 2790 cxgb3_err_notify(&adapter->tdev, OFFLOAD_STATUS_DOWN, 0);
2722 offload_close(&adapter->tdev); 2791 offload_close(&adapter->tdev);
2723 } 2792 }
2724 2793
2725 /* Stop all ports */ 2794 /* Stop all ports */
2726 for_each_port(adapter, i) { 2795 for_each_port(adapter, i) {
2727 struct net_device *netdev = adapter->port[i]; 2796 struct net_device *netdev = adapter->port[i];
2728 2797
2729 if (netif_running(netdev)) 2798 if (netif_running(netdev))
2730 cxgb_close(netdev); 2799 cxgb_close(netdev);
2731 } 2800 }
2732 2801
2733 /* Stop SGE timers */ 2802 /* Stop SGE timers */
2734 t3_stop_sge_timers(adapter); 2803 t3_stop_sge_timers(adapter);
2735 2804
2736 adapter->flags &= ~FULL_INIT_DONE; 2805 adapter->flags &= ~FULL_INIT_DONE;
2737 2806
2738 if (reset) 2807 if (reset)
2739 ret = t3_reset_adapter(adapter); 2808 ret = t3_reset_adapter(adapter);
2740 2809
2741 pci_disable_device(adapter->pdev); 2810 pci_disable_device(adapter->pdev);
2742 2811
2743 return ret; 2812 return ret;
2744 } 2813 }
2745 2814
2746 static int t3_reenable_adapter(struct adapter *adapter) 2815 static int t3_reenable_adapter(struct adapter *adapter)
2747 { 2816 {
2748 if (pci_enable_device(adapter->pdev)) { 2817 if (pci_enable_device(adapter->pdev)) {
2749 dev_err(&adapter->pdev->dev, 2818 dev_err(&adapter->pdev->dev,
2750 "Cannot re-enable PCI device after reset.\n"); 2819 "Cannot re-enable PCI device after reset.\n");
2751 goto err; 2820 goto err;
2752 } 2821 }
2753 pci_set_master(adapter->pdev); 2822 pci_set_master(adapter->pdev);
2754 pci_restore_state(adapter->pdev); 2823 pci_restore_state(adapter->pdev);
2755 2824
2756 /* Free sge resources */ 2825 /* Free sge resources */
2757 t3_free_sge_resources(adapter); 2826 t3_free_sge_resources(adapter);
2758 2827
2759 if (t3_replay_prep_adapter(adapter)) 2828 if (t3_replay_prep_adapter(adapter))
2760 goto err; 2829 goto err;
2761 2830
2762 return 0; 2831 return 0;
2763 err: 2832 err:
2764 return -1; 2833 return -1;
2765 } 2834 }
2766 2835
2767 static void t3_resume_ports(struct adapter *adapter) 2836 static void t3_resume_ports(struct adapter *adapter)
2768 { 2837 {
2769 int i; 2838 int i;
2770 2839
2771 /* Restart the ports */ 2840 /* Restart the ports */
2772 for_each_port(adapter, i) { 2841 for_each_port(adapter, i) {
2773 struct net_device *netdev = adapter->port[i]; 2842 struct net_device *netdev = adapter->port[i];
2774 2843
2775 if (netif_running(netdev)) { 2844 if (netif_running(netdev)) {
2776 if (cxgb_open(netdev)) { 2845 if (cxgb_open(netdev)) {
2777 dev_err(&adapter->pdev->dev, 2846 dev_err(&adapter->pdev->dev,
2778 "can't bring device back up" 2847 "can't bring device back up"
2779 " after reset\n"); 2848 " after reset\n");
2780 continue; 2849 continue;
2781 } 2850 }
2782 } 2851 }
2783 } 2852 }
2784 2853
2785 if (is_offload(adapter) && !ofld_disable) 2854 if (is_offload(adapter) && !ofld_disable)
2786 cxgb3_err_notify(&adapter->tdev, OFFLOAD_STATUS_UP, 0); 2855 cxgb3_err_notify(&adapter->tdev, OFFLOAD_STATUS_UP, 0);
2787 } 2856 }
2788 2857
2789 /* 2858 /*
2790 * processes a fatal error. 2859 * processes a fatal error.
2791 * Bring the ports down, reset the chip, bring the ports back up. 2860 * Bring the ports down, reset the chip, bring the ports back up.
2792 */ 2861 */
2793 static void fatal_error_task(struct work_struct *work) 2862 static void fatal_error_task(struct work_struct *work)
2794 { 2863 {
2795 struct adapter *adapter = container_of(work, struct adapter, 2864 struct adapter *adapter = container_of(work, struct adapter,
2796 fatal_error_handler_task); 2865 fatal_error_handler_task);
2797 int err = 0; 2866 int err = 0;
2798 2867
2799 rtnl_lock(); 2868 rtnl_lock();
2800 err = t3_adapter_error(adapter, 1); 2869 err = t3_adapter_error(adapter, 1);
2801 if (!err) 2870 if (!err)
2802 err = t3_reenable_adapter(adapter); 2871 err = t3_reenable_adapter(adapter);
2803 if (!err) 2872 if (!err)
2804 t3_resume_ports(adapter); 2873 t3_resume_ports(adapter);
2805 2874
2806 CH_ALERT(adapter, "adapter reset %s\n", err ? "failed" : "succeeded"); 2875 CH_ALERT(adapter, "adapter reset %s\n", err ? "failed" : "succeeded");
2807 rtnl_unlock(); 2876 rtnl_unlock();
2808 } 2877 }
2809 2878
2810 void t3_fatal_err(struct adapter *adapter) 2879 void t3_fatal_err(struct adapter *adapter)
2811 { 2880 {
2812 unsigned int fw_status[4]; 2881 unsigned int fw_status[4];
2813 2882
2814 if (adapter->flags & FULL_INIT_DONE) { 2883 if (adapter->flags & FULL_INIT_DONE) {
2815 t3_sge_stop(adapter); 2884 t3_sge_stop(adapter);
2816 t3_write_reg(adapter, A_XGM_TX_CTRL, 0); 2885 t3_write_reg(adapter, A_XGM_TX_CTRL, 0);
2817 t3_write_reg(adapter, A_XGM_RX_CTRL, 0); 2886 t3_write_reg(adapter, A_XGM_RX_CTRL, 0);
2818 t3_write_reg(adapter, XGM_REG(A_XGM_TX_CTRL, 1), 0); 2887 t3_write_reg(adapter, XGM_REG(A_XGM_TX_CTRL, 1), 0);
2819 t3_write_reg(adapter, XGM_REG(A_XGM_RX_CTRL, 1), 0); 2888 t3_write_reg(adapter, XGM_REG(A_XGM_RX_CTRL, 1), 0);
2820 2889
2821 spin_lock(&adapter->work_lock); 2890 spin_lock(&adapter->work_lock);
2822 t3_intr_disable(adapter); 2891 t3_intr_disable(adapter);
2823 queue_work(cxgb3_wq, &adapter->fatal_error_handler_task); 2892 queue_work(cxgb3_wq, &adapter->fatal_error_handler_task);
2824 spin_unlock(&adapter->work_lock); 2893 spin_unlock(&adapter->work_lock);
2825 } 2894 }
2826 CH_ALERT(adapter, "encountered fatal error, operation suspended\n"); 2895 CH_ALERT(adapter, "encountered fatal error, operation suspended\n");
2827 if (!t3_cim_ctl_blk_read(adapter, 0xa0, 4, fw_status)) 2896 if (!t3_cim_ctl_blk_read(adapter, 0xa0, 4, fw_status))
2828 CH_ALERT(adapter, "FW status: 0x%x, 0x%x, 0x%x, 0x%x\n", 2897 CH_ALERT(adapter, "FW status: 0x%x, 0x%x, 0x%x, 0x%x\n",
2829 fw_status[0], fw_status[1], 2898 fw_status[0], fw_status[1],
2830 fw_status[2], fw_status[3]); 2899 fw_status[2], fw_status[3]);
2831 } 2900 }
2832 2901
2833 /** 2902 /**
2834 * t3_io_error_detected - called when PCI error is detected 2903 * t3_io_error_detected - called when PCI error is detected
2835 * @pdev: Pointer to PCI device 2904 * @pdev: Pointer to PCI device
2836 * @state: The current pci connection state 2905 * @state: The current pci connection state
2837 * 2906 *
2838 * This function is called after a PCI bus error affecting 2907 * This function is called after a PCI bus error affecting
2839 * this device has been detected. 2908 * this device has been detected.
2840 */ 2909 */
2841 static pci_ers_result_t t3_io_error_detected(struct pci_dev *pdev, 2910 static pci_ers_result_t t3_io_error_detected(struct pci_dev *pdev,
2842 pci_channel_state_t state) 2911 pci_channel_state_t state)
2843 { 2912 {
2844 struct adapter *adapter = pci_get_drvdata(pdev); 2913 struct adapter *adapter = pci_get_drvdata(pdev);
2845 int ret; 2914 int ret;
2846 2915
2847 if (state == pci_channel_io_perm_failure) 2916 if (state == pci_channel_io_perm_failure)
2848 return PCI_ERS_RESULT_DISCONNECT; 2917 return PCI_ERS_RESULT_DISCONNECT;
2849 2918
2850 ret = t3_adapter_error(adapter, 0); 2919 ret = t3_adapter_error(adapter, 0);
2851 2920
2852 /* Request a slot reset. */ 2921 /* Request a slot reset. */
2853 return PCI_ERS_RESULT_NEED_RESET; 2922 return PCI_ERS_RESULT_NEED_RESET;
2854 } 2923 }
2855 2924
2856 /** 2925 /**
2857 * t3_io_slot_reset - called after the pci bus has been reset. 2926 * t3_io_slot_reset - called after the pci bus has been reset.
2858 * @pdev: Pointer to PCI device 2927 * @pdev: Pointer to PCI device
2859 * 2928 *
2860 * Restart the card from scratch, as if from a cold-boot. 2929 * Restart the card from scratch, as if from a cold-boot.
2861 */ 2930 */
2862 static pci_ers_result_t t3_io_slot_reset(struct pci_dev *pdev) 2931 static pci_ers_result_t t3_io_slot_reset(struct pci_dev *pdev)
2863 { 2932 {
2864 struct adapter *adapter = pci_get_drvdata(pdev); 2933 struct adapter *adapter = pci_get_drvdata(pdev);
2865 2934
2866 if (!t3_reenable_adapter(adapter)) 2935 if (!t3_reenable_adapter(adapter))
2867 return PCI_ERS_RESULT_RECOVERED; 2936 return PCI_ERS_RESULT_RECOVERED;
2868 2937
2869 return PCI_ERS_RESULT_DISCONNECT; 2938 return PCI_ERS_RESULT_DISCONNECT;
2870 } 2939 }
2871 2940
2872 /** 2941 /**
2873 * t3_io_resume - called when traffic can start flowing again. 2942 * t3_io_resume - called when traffic can start flowing again.
2874 * @pdev: Pointer to PCI device 2943 * @pdev: Pointer to PCI device
2875 * 2944 *
2876 * This callback is called when the error recovery driver tells us that 2945 * This callback is called when the error recovery driver tells us that
2877 * its OK to resume normal operation. 2946 * its OK to resume normal operation.
2878 */ 2947 */
2879 static void t3_io_resume(struct pci_dev *pdev) 2948 static void t3_io_resume(struct pci_dev *pdev)
2880 { 2949 {
2881 struct adapter *adapter = pci_get_drvdata(pdev); 2950 struct adapter *adapter = pci_get_drvdata(pdev);
2882 2951
2883 CH_ALERT(adapter, "adapter recovering, PEX ERR 0x%x\n", 2952 CH_ALERT(adapter, "adapter recovering, PEX ERR 0x%x\n",
2884 t3_read_reg(adapter, A_PCIE_PEX_ERR)); 2953 t3_read_reg(adapter, A_PCIE_PEX_ERR));
2885 2954
2886 t3_resume_ports(adapter); 2955 t3_resume_ports(adapter);
2887 } 2956 }
2888 2957
2889 static struct pci_error_handlers t3_err_handler = { 2958 static struct pci_error_handlers t3_err_handler = {
2890 .error_detected = t3_io_error_detected, 2959 .error_detected = t3_io_error_detected,
2891 .slot_reset = t3_io_slot_reset, 2960 .slot_reset = t3_io_slot_reset,
2892 .resume = t3_io_resume, 2961 .resume = t3_io_resume,
2893 }; 2962 };
2894 2963
2895 /* 2964 /*
2896 * Set the number of qsets based on the number of CPUs and the number of ports, 2965 * Set the number of qsets based on the number of CPUs and the number of ports,
2897 * not to exceed the number of available qsets, assuming there are enough qsets 2966 * not to exceed the number of available qsets, assuming there are enough qsets
2898 * per port in HW. 2967 * per port in HW.
2899 */ 2968 */
2900 static void set_nqsets(struct adapter *adap) 2969 static void set_nqsets(struct adapter *adap)
2901 { 2970 {
2902 int i, j = 0; 2971 int i, j = 0;
2903 int num_cpus = num_online_cpus(); 2972 int num_cpus = num_online_cpus();
2904 int hwports = adap->params.nports; 2973 int hwports = adap->params.nports;
2905 int nqsets = adap->msix_nvectors - 1; 2974 int nqsets = adap->msix_nvectors - 1;
2906 2975
2907 if (adap->params.rev > 0 && adap->flags & USING_MSIX) { 2976 if (adap->params.rev > 0 && adap->flags & USING_MSIX) {
2908 if (hwports == 2 && 2977 if (hwports == 2 &&
2909 (hwports * nqsets > SGE_QSETS || 2978 (hwports * nqsets > SGE_QSETS ||
2910 num_cpus >= nqsets / hwports)) 2979 num_cpus >= nqsets / hwports))
2911 nqsets /= hwports; 2980 nqsets /= hwports;
2912 if (nqsets > num_cpus) 2981 if (nqsets > num_cpus)
2913 nqsets = num_cpus; 2982 nqsets = num_cpus;
2914 if (nqsets < 1 || hwports == 4) 2983 if (nqsets < 1 || hwports == 4)
2915 nqsets = 1; 2984 nqsets = 1;
2916 } else 2985 } else
2917 nqsets = 1; 2986 nqsets = 1;
2918 2987
2919 for_each_port(adap, i) { 2988 for_each_port(adap, i) {
2920 struct port_info *pi = adap2pinfo(adap, i); 2989 struct port_info *pi = adap2pinfo(adap, i);
2921 2990
2922 pi->first_qset = j; 2991 pi->first_qset = j;
2923 pi->nqsets = nqsets; 2992 pi->nqsets = nqsets;
2924 j = pi->first_qset + nqsets; 2993 j = pi->first_qset + nqsets;
2925 2994
2926 dev_info(&adap->pdev->dev, 2995 dev_info(&adap->pdev->dev,
2927 "Port %d using %d queue sets.\n", i, nqsets); 2996 "Port %d using %d queue sets.\n", i, nqsets);
2928 } 2997 }
2929 } 2998 }
2930 2999
2931 static int __devinit cxgb_enable_msix(struct adapter *adap) 3000 static int __devinit cxgb_enable_msix(struct adapter *adap)
2932 { 3001 {
2933 struct msix_entry entries[SGE_QSETS + 1]; 3002 struct msix_entry entries[SGE_QSETS + 1];
2934 int vectors; 3003 int vectors;
2935 int i, err; 3004 int i, err;
2936 3005
2937 vectors = ARRAY_SIZE(entries); 3006 vectors = ARRAY_SIZE(entries);
2938 for (i = 0; i < vectors; ++i) 3007 for (i = 0; i < vectors; ++i)
2939 entries[i].entry = i; 3008 entries[i].entry = i;
2940 3009
2941 while ((err = pci_enable_msix(adap->pdev, entries, vectors)) > 0) 3010 while ((err = pci_enable_msix(adap->pdev, entries, vectors)) > 0)
2942 vectors = err; 3011 vectors = err;
2943 3012
2944 if (err < 0) 3013 if (err < 0)
2945 pci_disable_msix(adap->pdev); 3014 pci_disable_msix(adap->pdev);
2946 3015
2947 if (!err && vectors < (adap->params.nports + 1)) { 3016 if (!err && vectors < (adap->params.nports + 1)) {
2948 pci_disable_msix(adap->pdev); 3017 pci_disable_msix(adap->pdev);
2949 err = -1; 3018 err = -1;
2950 } 3019 }
2951 3020
2952 if (!err) { 3021 if (!err) {
2953 for (i = 0; i < vectors; ++i) 3022 for (i = 0; i < vectors; ++i)
2954 adap->msix_info[i].vec = entries[i].vector; 3023 adap->msix_info[i].vec = entries[i].vector;
2955 adap->msix_nvectors = vectors; 3024 adap->msix_nvectors = vectors;
2956 } 3025 }
2957 3026
2958 return err; 3027 return err;
2959 } 3028 }
2960 3029
2961 static void __devinit print_port_info(struct adapter *adap, 3030 static void __devinit print_port_info(struct adapter *adap,
2962 const struct adapter_info *ai) 3031 const struct adapter_info *ai)
2963 { 3032 {
2964 static const char *pci_variant[] = { 3033 static const char *pci_variant[] = {
2965 "PCI", "PCI-X", "PCI-X ECC", "PCI-X 266", "PCI Express" 3034 "PCI", "PCI-X", "PCI-X ECC", "PCI-X 266", "PCI Express"
2966 }; 3035 };
2967 3036
2968 int i; 3037 int i;
2969 char buf[80]; 3038 char buf[80];
2970 3039
2971 if (is_pcie(adap)) 3040 if (is_pcie(adap))
2972 snprintf(buf, sizeof(buf), "%s x%d", 3041 snprintf(buf, sizeof(buf), "%s x%d",
2973 pci_variant[adap->params.pci.variant], 3042 pci_variant[adap->params.pci.variant],
2974 adap->params.pci.width); 3043 adap->params.pci.width);
2975 else 3044 else
2976 snprintf(buf, sizeof(buf), "%s %dMHz/%d-bit", 3045 snprintf(buf, sizeof(buf), "%s %dMHz/%d-bit",
2977 pci_variant[adap->params.pci.variant], 3046 pci_variant[adap->params.pci.variant],
2978 adap->params.pci.speed, adap->params.pci.width); 3047 adap->params.pci.speed, adap->params.pci.width);
2979 3048
2980 for_each_port(adap, i) { 3049 for_each_port(adap, i) {
2981 struct net_device *dev = adap->port[i]; 3050 struct net_device *dev = adap->port[i];
2982 const struct port_info *pi = netdev_priv(dev); 3051 const struct port_info *pi = netdev_priv(dev);
2983 3052
2984 if (!test_bit(i, &adap->registered_device_map)) 3053 if (!test_bit(i, &adap->registered_device_map))
2985 continue; 3054 continue;
2986 printk(KERN_INFO "%s: %s %s %sNIC (rev %d) %s%s\n", 3055 printk(KERN_INFO "%s: %s %s %sNIC (rev %d) %s%s\n",
2987 dev->name, ai->desc, pi->phy.desc, 3056 dev->name, ai->desc, pi->phy.desc,
2988 is_offload(adap) ? "R" : "", adap->params.rev, buf, 3057 is_offload(adap) ? "R" : "", adap->params.rev, buf,
2989 (adap->flags & USING_MSIX) ? " MSI-X" : 3058 (adap->flags & USING_MSIX) ? " MSI-X" :
2990 (adap->flags & USING_MSI) ? " MSI" : ""); 3059 (adap->flags & USING_MSI) ? " MSI" : "");
2991 if (adap->name == dev->name && adap->params.vpd.mclk) 3060 if (adap->name == dev->name && adap->params.vpd.mclk)
2992 printk(KERN_INFO 3061 printk(KERN_INFO
2993 "%s: %uMB CM, %uMB PMTX, %uMB PMRX, S/N: %s\n", 3062 "%s: %uMB CM, %uMB PMTX, %uMB PMRX, S/N: %s\n",
2994 adap->name, t3_mc7_size(&adap->cm) >> 20, 3063 adap->name, t3_mc7_size(&adap->cm) >> 20,
2995 t3_mc7_size(&adap->pmtx) >> 20, 3064 t3_mc7_size(&adap->pmtx) >> 20,
2996 t3_mc7_size(&adap->pmrx) >> 20, 3065 t3_mc7_size(&adap->pmrx) >> 20,
2997 adap->params.vpd.sn); 3066 adap->params.vpd.sn);
2998 } 3067 }
2999 } 3068 }
3000 3069
3001 static const struct net_device_ops cxgb_netdev_ops = { 3070 static const struct net_device_ops cxgb_netdev_ops = {
3002 .ndo_open = cxgb_open, 3071 .ndo_open = cxgb_open,
3003 .ndo_stop = cxgb_close, 3072 .ndo_stop = cxgb_close,
3004 .ndo_start_xmit = t3_eth_xmit, 3073 .ndo_start_xmit = t3_eth_xmit,
3005 .ndo_get_stats = cxgb_get_stats, 3074 .ndo_get_stats = cxgb_get_stats,
3006 .ndo_validate_addr = eth_validate_addr, 3075 .ndo_validate_addr = eth_validate_addr,
3007 .ndo_set_multicast_list = cxgb_set_rxmode, 3076 .ndo_set_multicast_list = cxgb_set_rxmode,
3008 .ndo_do_ioctl = cxgb_ioctl, 3077 .ndo_do_ioctl = cxgb_ioctl,
3009 .ndo_change_mtu = cxgb_change_mtu, 3078 .ndo_change_mtu = cxgb_change_mtu,
3010 .ndo_set_mac_address = cxgb_set_mac_addr, 3079 .ndo_set_mac_address = cxgb_set_mac_addr,
3011 .ndo_vlan_rx_register = vlan_rx_register, 3080 .ndo_vlan_rx_register = vlan_rx_register,
3012 #ifdef CONFIG_NET_POLL_CONTROLLER 3081 #ifdef CONFIG_NET_POLL_CONTROLLER
3013 .ndo_poll_controller = cxgb_netpoll, 3082 .ndo_poll_controller = cxgb_netpoll,
3014 #endif 3083 #endif
3015 }; 3084 };
3016 3085
3017 static int __devinit init_one(struct pci_dev *pdev, 3086 static int __devinit init_one(struct pci_dev *pdev,
3018 const struct pci_device_id *ent) 3087 const struct pci_device_id *ent)
3019 { 3088 {
3020 static int version_printed; 3089 static int version_printed;
3021 3090
3022 int i, err, pci_using_dac = 0; 3091 int i, err, pci_using_dac = 0;
3023 resource_size_t mmio_start, mmio_len; 3092 resource_size_t mmio_start, mmio_len;
3024 const struct adapter_info *ai; 3093 const struct adapter_info *ai;
3025 struct adapter *adapter = NULL; 3094 struct adapter *adapter = NULL;
3026 struct port_info *pi; 3095 struct port_info *pi;
3027 3096
3028 if (!version_printed) { 3097 if (!version_printed) {
3029 printk(KERN_INFO "%s - version %s\n", DRV_DESC, DRV_VERSION); 3098 printk(KERN_INFO "%s - version %s\n", DRV_DESC, DRV_VERSION);
3030 ++version_printed; 3099 ++version_printed;
3031 } 3100 }
3032 3101
3033 if (!cxgb3_wq) { 3102 if (!cxgb3_wq) {
3034 cxgb3_wq = create_singlethread_workqueue(DRV_NAME); 3103 cxgb3_wq = create_singlethread_workqueue(DRV_NAME);
3035 if (!cxgb3_wq) { 3104 if (!cxgb3_wq) {
3036 printk(KERN_ERR DRV_NAME 3105 printk(KERN_ERR DRV_NAME
3037 ": cannot initialize work queue\n"); 3106 ": cannot initialize work queue\n");
3038 return -ENOMEM; 3107 return -ENOMEM;
3039 } 3108 }
3040 } 3109 }
3041 3110
3042 err = pci_request_regions(pdev, DRV_NAME); 3111 err = pci_request_regions(pdev, DRV_NAME);
3043 if (err) { 3112 if (err) {
3044 /* Just info, some other driver may have claimed the device. */ 3113 /* Just info, some other driver may have claimed the device. */
3045 dev_info(&pdev->dev, "cannot obtain PCI resources\n"); 3114 dev_info(&pdev->dev, "cannot obtain PCI resources\n");
3046 return err; 3115 return err;
3047 } 3116 }
3048 3117
3049 err = pci_enable_device(pdev); 3118 err = pci_enable_device(pdev);
3050 if (err) { 3119 if (err) {
3051 dev_err(&pdev->dev, "cannot enable PCI device\n"); 3120 dev_err(&pdev->dev, "cannot enable PCI device\n");
3052 goto out_release_regions; 3121 goto out_release_regions;
3053 } 3122 }
3054 3123
3055 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { 3124 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
3056 pci_using_dac = 1; 3125 pci_using_dac = 1;
3057 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 3126 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
3058 if (err) { 3127 if (err) {
3059 dev_err(&pdev->dev, "unable to obtain 64-bit DMA for " 3128 dev_err(&pdev->dev, "unable to obtain 64-bit DMA for "
3060 "coherent allocations\n"); 3129 "coherent allocations\n");
3061 goto out_disable_device; 3130 goto out_disable_device;
3062 } 3131 }
3063 } else if ((err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) != 0) { 3132 } else if ((err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) != 0) {
3064 dev_err(&pdev->dev, "no usable DMA configuration\n"); 3133 dev_err(&pdev->dev, "no usable DMA configuration\n");
3065 goto out_disable_device; 3134 goto out_disable_device;
3066 } 3135 }
3067 3136
3068 pci_set_master(pdev); 3137 pci_set_master(pdev);
3069 pci_save_state(pdev); 3138 pci_save_state(pdev);
3070 3139
3071 mmio_start = pci_resource_start(pdev, 0); 3140 mmio_start = pci_resource_start(pdev, 0);
3072 mmio_len = pci_resource_len(pdev, 0); 3141 mmio_len = pci_resource_len(pdev, 0);
3073 ai = t3_get_adapter_info(ent->driver_data); 3142 ai = t3_get_adapter_info(ent->driver_data);
3074 3143
3075 adapter = kzalloc(sizeof(*adapter), GFP_KERNEL); 3144 adapter = kzalloc(sizeof(*adapter), GFP_KERNEL);
3076 if (!adapter) { 3145 if (!adapter) {
3077 err = -ENOMEM; 3146 err = -ENOMEM;
3078 goto out_disable_device; 3147 goto out_disable_device;
3079 } 3148 }
3080 3149
3081 adapter->nofail_skb = 3150 adapter->nofail_skb =
3082 alloc_skb(sizeof(struct cpl_set_tcb_field), GFP_KERNEL); 3151 alloc_skb(sizeof(struct cpl_set_tcb_field), GFP_KERNEL);
3083 if (!adapter->nofail_skb) { 3152 if (!adapter->nofail_skb) {
3084 dev_err(&pdev->dev, "cannot allocate nofail buffer\n"); 3153 dev_err(&pdev->dev, "cannot allocate nofail buffer\n");
3085 err = -ENOMEM; 3154 err = -ENOMEM;
3086 goto out_free_adapter; 3155 goto out_free_adapter;
3087 } 3156 }
3088 3157
3089 adapter->regs = ioremap_nocache(mmio_start, mmio_len); 3158 adapter->regs = ioremap_nocache(mmio_start, mmio_len);
3090 if (!adapter->regs) { 3159 if (!adapter->regs) {
3091 dev_err(&pdev->dev, "cannot map device registers\n"); 3160 dev_err(&pdev->dev, "cannot map device registers\n");
3092 err = -ENOMEM; 3161 err = -ENOMEM;
3093 goto out_free_adapter; 3162 goto out_free_adapter;
3094 } 3163 }
3095 3164
3096 adapter->pdev = pdev; 3165 adapter->pdev = pdev;
3097 adapter->name = pci_name(pdev); 3166 adapter->name = pci_name(pdev);
3098 adapter->msg_enable = dflt_msg_enable; 3167 adapter->msg_enable = dflt_msg_enable;
3099 adapter->mmio_len = mmio_len; 3168 adapter->mmio_len = mmio_len;
3100 3169
3101 mutex_init(&adapter->mdio_lock); 3170 mutex_init(&adapter->mdio_lock);
3102 spin_lock_init(&adapter->work_lock); 3171 spin_lock_init(&adapter->work_lock);
3103 spin_lock_init(&adapter->stats_lock); 3172 spin_lock_init(&adapter->stats_lock);
3104 3173
3105 INIT_LIST_HEAD(&adapter->adapter_list); 3174 INIT_LIST_HEAD(&adapter->adapter_list);
3106 INIT_WORK(&adapter->ext_intr_handler_task, ext_intr_task); 3175 INIT_WORK(&adapter->ext_intr_handler_task, ext_intr_task);
3107 INIT_WORK(&adapter->fatal_error_handler_task, fatal_error_task); 3176 INIT_WORK(&adapter->fatal_error_handler_task, fatal_error_task);
3108 INIT_DELAYED_WORK(&adapter->adap_check_task, t3_adap_check_task); 3177 INIT_DELAYED_WORK(&adapter->adap_check_task, t3_adap_check_task);
3109 3178
3110 for (i = 0; i < ai->nports0 + ai->nports1; ++i) { 3179 for (i = 0; i < ai->nports0 + ai->nports1; ++i) {
3111 struct net_device *netdev; 3180 struct net_device *netdev;
3112 3181
3113 netdev = alloc_etherdev_mq(sizeof(struct port_info), SGE_QSETS); 3182 netdev = alloc_etherdev_mq(sizeof(struct port_info), SGE_QSETS);
3114 if (!netdev) { 3183 if (!netdev) {
3115 err = -ENOMEM; 3184 err = -ENOMEM;
3116 goto out_free_dev; 3185 goto out_free_dev;
3117 } 3186 }
3118 3187
3119 SET_NETDEV_DEV(netdev, &pdev->dev); 3188 SET_NETDEV_DEV(netdev, &pdev->dev);
3120 3189
3121 adapter->port[i] = netdev; 3190 adapter->port[i] = netdev;
3122 pi = netdev_priv(netdev); 3191 pi = netdev_priv(netdev);
3123 pi->adapter = adapter; 3192 pi->adapter = adapter;
3124 pi->rx_offload = T3_RX_CSUM | T3_LRO; 3193 pi->rx_offload = T3_RX_CSUM | T3_LRO;
3125 pi->port_id = i; 3194 pi->port_id = i;
3126 netif_carrier_off(netdev); 3195 netif_carrier_off(netdev);
3127 netif_tx_stop_all_queues(netdev); 3196 netif_tx_stop_all_queues(netdev);
3128 netdev->irq = pdev->irq; 3197 netdev->irq = pdev->irq;
3129 netdev->mem_start = mmio_start; 3198 netdev->mem_start = mmio_start;
3130 netdev->mem_end = mmio_start + mmio_len - 1; 3199 netdev->mem_end = mmio_start + mmio_len - 1;
3131 netdev->features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; 3200 netdev->features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO;
3132 netdev->features |= NETIF_F_GRO; 3201 netdev->features |= NETIF_F_GRO;
3133 if (pci_using_dac) 3202 if (pci_using_dac)
3134 netdev->features |= NETIF_F_HIGHDMA; 3203 netdev->features |= NETIF_F_HIGHDMA;
3135 3204
3136 netdev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; 3205 netdev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3137 netdev->netdev_ops = &cxgb_netdev_ops; 3206 netdev->netdev_ops = &cxgb_netdev_ops;
3138 SET_ETHTOOL_OPS(netdev, &cxgb_ethtool_ops); 3207 SET_ETHTOOL_OPS(netdev, &cxgb_ethtool_ops);
3139 } 3208 }
3140 3209
3141 pci_set_drvdata(pdev, adapter); 3210 pci_set_drvdata(pdev, adapter);
3142 if (t3_prep_adapter(adapter, ai, 1) < 0) { 3211 if (t3_prep_adapter(adapter, ai, 1) < 0) {
3143 err = -ENODEV; 3212 err = -ENODEV;
3144 goto out_free_dev; 3213 goto out_free_dev;
3145 } 3214 }
3146 3215
3147 /* 3216 /*
3148 * The card is now ready to go. If any errors occur during device 3217 * The card is now ready to go. If any errors occur during device
3149 * registration we do not fail the whole card but rather proceed only 3218 * registration we do not fail the whole card but rather proceed only
3150 * with the ports we manage to register successfully. However we must 3219 * with the ports we manage to register successfully. However we must
3151 * register at least one net device. 3220 * register at least one net device.
3152 */ 3221 */
3153 for_each_port(adapter, i) { 3222 for_each_port(adapter, i) {
3154 err = register_netdev(adapter->port[i]); 3223 err = register_netdev(adapter->port[i]);
3155 if (err) 3224 if (err)
3156 dev_warn(&pdev->dev, 3225 dev_warn(&pdev->dev,
3157 "cannot register net device %s, skipping\n", 3226 "cannot register net device %s, skipping\n",
3158 adapter->port[i]->name); 3227 adapter->port[i]->name);
3159 else { 3228 else {
3160 /* 3229 /*
3161 * Change the name we use for messages to the name of 3230 * Change the name we use for messages to the name of
3162 * the first successfully registered interface. 3231 * the first successfully registered interface.
3163 */ 3232 */
3164 if (!adapter->registered_device_map) 3233 if (!adapter->registered_device_map)
3165 adapter->name = adapter->port[i]->name; 3234 adapter->name = adapter->port[i]->name;
3166 3235
3167 __set_bit(i, &adapter->registered_device_map); 3236 __set_bit(i, &adapter->registered_device_map);
3168 } 3237 }
3169 } 3238 }
3170 if (!adapter->registered_device_map) { 3239 if (!adapter->registered_device_map) {
3171 dev_err(&pdev->dev, "could not register any net devices\n"); 3240 dev_err(&pdev->dev, "could not register any net devices\n");
3172 goto out_free_dev; 3241 goto out_free_dev;
3173 } 3242 }
3174 3243
3175 /* Driver's ready. Reflect it on LEDs */ 3244 /* Driver's ready. Reflect it on LEDs */
3176 t3_led_ready(adapter); 3245 t3_led_ready(adapter);
3177 3246
3178 if (is_offload(adapter)) { 3247 if (is_offload(adapter)) {
3179 __set_bit(OFFLOAD_DEVMAP_BIT, &adapter->registered_device_map); 3248 __set_bit(OFFLOAD_DEVMAP_BIT, &adapter->registered_device_map);
3180 cxgb3_adapter_ofld(adapter); 3249 cxgb3_adapter_ofld(adapter);
3181 } 3250 }
3182 3251
3183 /* See what interrupts we'll be using */ 3252 /* See what interrupts we'll be using */
3184 if (msi > 1 && cxgb_enable_msix(adapter) == 0) 3253 if (msi > 1 && cxgb_enable_msix(adapter) == 0)
3185 adapter->flags |= USING_MSIX; 3254 adapter->flags |= USING_MSIX;
3186 else if (msi > 0 && pci_enable_msi(pdev) == 0) 3255 else if (msi > 0 && pci_enable_msi(pdev) == 0)
3187 adapter->flags |= USING_MSI; 3256 adapter->flags |= USING_MSI;
3188 3257
3189 set_nqsets(adapter); 3258 set_nqsets(adapter);
3190 3259
3191 err = sysfs_create_group(&adapter->port[0]->dev.kobj, 3260 err = sysfs_create_group(&adapter->port[0]->dev.kobj,
3192 &cxgb3_attr_group); 3261 &cxgb3_attr_group);
3193 3262
3194 print_port_info(adapter, ai); 3263 print_port_info(adapter, ai);
3195 return 0; 3264 return 0;
3196 3265
3197 out_free_dev: 3266 out_free_dev:
3198 iounmap(adapter->regs); 3267 iounmap(adapter->regs);
3199 for (i = ai->nports0 + ai->nports1 - 1; i >= 0; --i) 3268 for (i = ai->nports0 + ai->nports1 - 1; i >= 0; --i)
3200 if (adapter->port[i]) 3269 if (adapter->port[i])
3201 free_netdev(adapter->port[i]); 3270 free_netdev(adapter->port[i]);
3202 3271
3203 out_free_adapter: 3272 out_free_adapter:
3204 kfree(adapter); 3273 kfree(adapter);
3205 3274
3206 out_disable_device: 3275 out_disable_device:
3207 pci_disable_device(pdev); 3276 pci_disable_device(pdev);
3208 out_release_regions: 3277 out_release_regions:
3209 pci_release_regions(pdev); 3278 pci_release_regions(pdev);
3210 pci_set_drvdata(pdev, NULL); 3279 pci_set_drvdata(pdev, NULL);
3211 return err; 3280 return err;
3212 } 3281 }
3213 3282
3214 static void __devexit remove_one(struct pci_dev *pdev) 3283 static void __devexit remove_one(struct pci_dev *pdev)
3215 { 3284 {
3216 struct adapter *adapter = pci_get_drvdata(pdev); 3285 struct adapter *adapter = pci_get_drvdata(pdev);
3217 3286
3218 if (adapter) { 3287 if (adapter) {
3219 int i; 3288 int i;
3220 3289
3221 t3_sge_stop(adapter); 3290 t3_sge_stop(adapter);
3222 sysfs_remove_group(&adapter->port[0]->dev.kobj, 3291 sysfs_remove_group(&adapter->port[0]->dev.kobj,
3223 &cxgb3_attr_group); 3292 &cxgb3_attr_group);
3224 3293
3225 if (is_offload(adapter)) { 3294 if (is_offload(adapter)) {
3226 cxgb3_adapter_unofld(adapter); 3295 cxgb3_adapter_unofld(adapter);
3227 if (test_bit(OFFLOAD_DEVMAP_BIT, 3296 if (test_bit(OFFLOAD_DEVMAP_BIT,
3228 &adapter->open_device_map)) 3297 &adapter->open_device_map))
3229 offload_close(&adapter->tdev); 3298 offload_close(&adapter->tdev);
3230 } 3299 }
3231 3300
3232 for_each_port(adapter, i) 3301 for_each_port(adapter, i)
3233 if (test_bit(i, &adapter->registered_device_map)) 3302 if (test_bit(i, &adapter->registered_device_map))
3234 unregister_netdev(adapter->port[i]); 3303 unregister_netdev(adapter->port[i]);
3235 3304
3236 t3_stop_sge_timers(adapter); 3305 t3_stop_sge_timers(adapter);
3237 t3_free_sge_resources(adapter); 3306 t3_free_sge_resources(adapter);
3238 cxgb_disable_msi(adapter); 3307 cxgb_disable_msi(adapter);
3239 3308
3240 for_each_port(adapter, i) 3309 for_each_port(adapter, i)
3241 if (adapter->port[i]) 3310 if (adapter->port[i])
3242 free_netdev(adapter->port[i]); 3311 free_netdev(adapter->port[i]);
3243 3312
3244 iounmap(adapter->regs); 3313 iounmap(adapter->regs);
3245 if (adapter->nofail_skb) 3314 if (adapter->nofail_skb)
3246 kfree_skb(adapter->nofail_skb); 3315 kfree_skb(adapter->nofail_skb);
3247 kfree(adapter); 3316 kfree(adapter);
3248 pci_release_regions(pdev); 3317 pci_release_regions(pdev);
3249 pci_disable_device(pdev); 3318 pci_disable_device(pdev);
3250 pci_set_drvdata(pdev, NULL); 3319 pci_set_drvdata(pdev, NULL);
3251 } 3320 }
3252 } 3321 }
3253 3322
3254 static struct pci_driver driver = { 3323 static struct pci_driver driver = {
3255 .name = DRV_NAME, 3324 .name = DRV_NAME,
3256 .id_table = cxgb3_pci_tbl, 3325 .id_table = cxgb3_pci_tbl,
3257 .probe = init_one, 3326 .probe = init_one,
3258 .remove = __devexit_p(remove_one), 3327 .remove = __devexit_p(remove_one),
3259 .err_handler = &t3_err_handler, 3328 .err_handler = &t3_err_handler,
3260 }; 3329 };
3261 3330
3262 static int __init cxgb3_init_module(void) 3331 static int __init cxgb3_init_module(void)
3263 { 3332 {
3264 int ret; 3333 int ret;
3265 3334
3266 cxgb3_offload_init(); 3335 cxgb3_offload_init();
3267 3336
3268 ret = pci_register_driver(&driver); 3337 ret = pci_register_driver(&driver);
3269 return ret; 3338 return ret;
3270 } 3339 }
3271 3340
3272 static void __exit cxgb3_cleanup_module(void) 3341 static void __exit cxgb3_cleanup_module(void)
3273 { 3342 {
3274 pci_unregister_driver(&driver); 3343 pci_unregister_driver(&driver);
3275 if (cxgb3_wq) 3344 if (cxgb3_wq)
3276 destroy_workqueue(cxgb3_wq); 3345 destroy_workqueue(cxgb3_wq);
3277 } 3346 }
3278 3347
3279 module_init(cxgb3_init_module); 3348 module_init(cxgb3_init_module);
3280 module_exit(cxgb3_cleanup_module); 3349 module_exit(cxgb3_cleanup_module);
3281 3350
1 # 1 #
2 # kbuild file for firmware/ 2 # kbuild file for firmware/
3 # 3 #
4 4
5 # Create $(fwabs) from $(CONFIG_EXTRA_FIRMWARE_DIR) -- if it doesn't have a 5 # Create $(fwabs) from $(CONFIG_EXTRA_FIRMWARE_DIR) -- if it doesn't have a
6 # leading /, it's relative to $(srctree). 6 # leading /, it's relative to $(srctree).
7 fwdir := $(subst ",,$(CONFIG_EXTRA_FIRMWARE_DIR)) 7 fwdir := $(subst ",,$(CONFIG_EXTRA_FIRMWARE_DIR))
8 fwabs := $(addprefix $(srctree)/,$(filter-out /%,$(fwdir)))$(filter /%,$(fwdir)) 8 fwabs := $(addprefix $(srctree)/,$(filter-out /%,$(fwdir)))$(filter /%,$(fwdir))
9 9
10 fw-external-y := $(subst ",,$(CONFIG_EXTRA_FIRMWARE)) 10 fw-external-y := $(subst ",,$(CONFIG_EXTRA_FIRMWARE))
11 11
12 # There are three cases to care about: 12 # There are three cases to care about:
13 # 1. Building kernel with CONFIG_FIRMWARE_IN_KERNEL=y -- $(fw-shipped-y) should 13 # 1. Building kernel with CONFIG_FIRMWARE_IN_KERNEL=y -- $(fw-shipped-y) should
14 # include the firmware files to include, according to .config 14 # include the firmware files to include, according to .config
15 # 2. 'make modules_install', which will install firmware for modules, and 15 # 2. 'make modules_install', which will install firmware for modules, and
16 # _also_ for the in-kernel drivers when CONFIG_FIRMWARE_IN_KERNEL=n 16 # _also_ for the in-kernel drivers when CONFIG_FIRMWARE_IN_KERNEL=n
17 # 3. 'make firmware_install', which installs all firmware, unconditionally. 17 # 3. 'make firmware_install', which installs all firmware, unconditionally.
18 18
19 # For the former two cases we want $(fw-shipped-y) and $(fw-shipped-m) to be 19 # For the former two cases we want $(fw-shipped-y) and $(fw-shipped-m) to be
20 # accurate. In the latter case it doesn't matter -- it'll use $(fw-shipped-all). 20 # accurate. In the latter case it doesn't matter -- it'll use $(fw-shipped-all).
21 # But be aware that the config file might not be included at all. 21 # But be aware that the config file might not be included at all.
22 22
23 ifdef CONFIG_ACENIC_OMIT_TIGON_I 23 ifdef CONFIG_ACENIC_OMIT_TIGON_I
24 acenic-objs := acenic/tg2.bin 24 acenic-objs := acenic/tg2.bin
25 fw-shipped- += acenic/tg1.bin 25 fw-shipped- += acenic/tg1.bin
26 else 26 else
27 acenic-objs := acenic/tg1.bin acenic/tg2.bin 27 acenic-objs := acenic/tg1.bin acenic/tg2.bin
28 endif 28 endif
29 fw-shipped-$(CONFIG_3C359) += 3com/3C359.bin 29 fw-shipped-$(CONFIG_3C359) += 3com/3C359.bin
30 fw-shipped-$(CONFIG_ACENIC) += $(acenic-objs) 30 fw-shipped-$(CONFIG_ACENIC) += $(acenic-objs)
31 fw-shipped-$(CONFIG_ADAPTEC_STARFIRE) += adaptec/starfire_rx.bin \ 31 fw-shipped-$(CONFIG_ADAPTEC_STARFIRE) += adaptec/starfire_rx.bin \
32 adaptec/starfire_tx.bin 32 adaptec/starfire_tx.bin
33 fw-shipped-$(CONFIG_ATARI_DSP56K) += dsp56k/bootstrap.bin 33 fw-shipped-$(CONFIG_ATARI_DSP56K) += dsp56k/bootstrap.bin
34 fw-shipped-$(CONFIG_ATM_AMBASSADOR) += atmsar11.fw 34 fw-shipped-$(CONFIG_ATM_AMBASSADOR) += atmsar11.fw
35 fw-shipped-$(CONFIG_BNX2X) += bnx2x-e1-4.8.53.0.fw bnx2x-e1h-4.8.53.0.fw 35 fw-shipped-$(CONFIG_BNX2X) += bnx2x-e1-4.8.53.0.fw bnx2x-e1h-4.8.53.0.fw
36 fw-shipped-$(CONFIG_BNX2) += bnx2/bnx2-mips-09-4.6.17.fw \ 36 fw-shipped-$(CONFIG_BNX2) += bnx2/bnx2-mips-09-4.6.17.fw \
37 bnx2/bnx2-rv2p-09-4.6.15.fw \ 37 bnx2/bnx2-rv2p-09-4.6.15.fw \
38 bnx2/bnx2-mips-06-4.6.16.fw \ 38 bnx2/bnx2-mips-06-4.6.16.fw \
39 bnx2/bnx2-rv2p-06-4.6.16.fw 39 bnx2/bnx2-rv2p-06-4.6.16.fw
40 fw-shipped-$(CONFIG_CASSINI) += sun/cassini.bin 40 fw-shipped-$(CONFIG_CASSINI) += sun/cassini.bin
41 fw-shipped-$(CONFIG_COMPUTONE) += intelliport2.bin 41 fw-shipped-$(CONFIG_COMPUTONE) += intelliport2.bin
42 fw-shipped-$(CONFIG_CHELSIO_T3) += cxgb3/t3b_psram-1.1.0.bin \ 42 fw-shipped-$(CONFIG_CHELSIO_T3) += cxgb3/t3b_psram-1.1.0.bin \
43 cxgb3/t3c_psram-1.1.0.bin \ 43 cxgb3/t3c_psram-1.1.0.bin \
44 cxgb3/t3fw-7.4.0.bin 44 cxgb3/t3fw-7.4.0.bin \
45 cxgb3/ael2005_opt_edc.bin \
46 cxgb3/ael2005_twx_edc.bin \
47 cxgb3/ael2020_twx_edc.bin
45 fw-shipped-$(CONFIG_DVB_AV7110) += av7110/bootcode.bin 48 fw-shipped-$(CONFIG_DVB_AV7110) += av7110/bootcode.bin
46 fw-shipped-$(CONFIG_DVB_TTUSB_BUDGET) += ttusb-budget/dspbootcode.bin 49 fw-shipped-$(CONFIG_DVB_TTUSB_BUDGET) += ttusb-budget/dspbootcode.bin
47 fw-shipped-$(CONFIG_E100) += e100/d101m_ucode.bin e100/d101s_ucode.bin \ 50 fw-shipped-$(CONFIG_E100) += e100/d101m_ucode.bin e100/d101s_ucode.bin \
48 e100/d102e_ucode.bin 51 e100/d102e_ucode.bin
49 fw-shipped-$(CONFIG_MYRI_SBUS) += myricom/lanai.bin 52 fw-shipped-$(CONFIG_MYRI_SBUS) += myricom/lanai.bin
50 fw-shipped-$(CONFIG_PCMCIA_PCNET) += cis/LA-PCM.cis 53 fw-shipped-$(CONFIG_PCMCIA_PCNET) += cis/LA-PCM.cis
51 fw-shipped-$(CONFIG_PCMCIA_3C589) += cis/3CXEM556.cis 54 fw-shipped-$(CONFIG_PCMCIA_3C589) += cis/3CXEM556.cis
52 fw-shipped-$(CONFIG_PCMCIA_3C574) += cis/3CCFEM556.cis 55 fw-shipped-$(CONFIG_PCMCIA_3C574) += cis/3CCFEM556.cis
53 fw-shipped-$(CONFIG_PCMCIA_SMC91C92) += ositech/Xilinx7OD.bin 56 fw-shipped-$(CONFIG_PCMCIA_SMC91C92) += ositech/Xilinx7OD.bin
54 fw-shipped-$(CONFIG_SCSI_ADVANSYS) += advansys/mcode.bin advansys/38C1600.bin \ 57 fw-shipped-$(CONFIG_SCSI_ADVANSYS) += advansys/mcode.bin advansys/38C1600.bin \
55 advansys/3550.bin advansys/38C0800.bin 58 advansys/3550.bin advansys/38C0800.bin
56 fw-shipped-$(CONFIG_SCSI_QLOGIC_1280) += qlogic/1040.bin qlogic/1280.bin \ 59 fw-shipped-$(CONFIG_SCSI_QLOGIC_1280) += qlogic/1040.bin qlogic/1280.bin \
57 qlogic/12160.bin 60 qlogic/12160.bin
58 fw-shipped-$(CONFIG_SCSI_QLOGICPTI) += qlogic/isp1000.bin 61 fw-shipped-$(CONFIG_SCSI_QLOGICPTI) += qlogic/isp1000.bin
59 fw-shipped-$(CONFIG_SMCTR) += tr_smctr.bin 62 fw-shipped-$(CONFIG_SMCTR) += tr_smctr.bin
60 fw-shipped-$(CONFIG_SND_KORG1212) += korg/k1212.dsp 63 fw-shipped-$(CONFIG_SND_KORG1212) += korg/k1212.dsp
61 fw-shipped-$(CONFIG_SND_MAESTRO3) += ess/maestro3_assp_kernel.fw \ 64 fw-shipped-$(CONFIG_SND_MAESTRO3) += ess/maestro3_assp_kernel.fw \
62 ess/maestro3_assp_minisrc.fw 65 ess/maestro3_assp_minisrc.fw
63 fw-shipped-$(CONFIG_SND_SB16_CSP) += sb16/mulaw_main.csp sb16/alaw_main.csp \ 66 fw-shipped-$(CONFIG_SND_SB16_CSP) += sb16/mulaw_main.csp sb16/alaw_main.csp \
64 sb16/ima_adpcm_init.csp \ 67 sb16/ima_adpcm_init.csp \
65 sb16/ima_adpcm_playback.csp \ 68 sb16/ima_adpcm_playback.csp \
66 sb16/ima_adpcm_capture.csp 69 sb16/ima_adpcm_capture.csp
67 fw-shipped-$(CONFIG_SND_YMFPCI) += yamaha/ds1_ctrl.fw yamaha/ds1_dsp.fw \ 70 fw-shipped-$(CONFIG_SND_YMFPCI) += yamaha/ds1_ctrl.fw yamaha/ds1_dsp.fw \
68 yamaha/ds1e_ctrl.fw 71 yamaha/ds1e_ctrl.fw
69 fw-shipped-$(CONFIG_SND_WAVEFRONT) += yamaha/yss225_registers.bin 72 fw-shipped-$(CONFIG_SND_WAVEFRONT) += yamaha/yss225_registers.bin
70 fw-shipped-$(CONFIG_TEHUTI) += tehuti/bdx.bin 73 fw-shipped-$(CONFIG_TEHUTI) += tehuti/bdx.bin
71 fw-shipped-$(CONFIG_TIGON3) += tigon/tg3.bin tigon/tg3_tso.bin \ 74 fw-shipped-$(CONFIG_TIGON3) += tigon/tg3.bin tigon/tg3_tso.bin \
72 tigon/tg3_tso5.bin 75 tigon/tg3_tso5.bin
73 fw-shipped-$(CONFIG_TYPHOON) += 3com/typhoon.bin 76 fw-shipped-$(CONFIG_TYPHOON) += 3com/typhoon.bin
74 fw-shipped-$(CONFIG_USB_DABUSB) += dabusb/firmware.fw dabusb/bitstream.bin 77 fw-shipped-$(CONFIG_USB_DABUSB) += dabusb/firmware.fw dabusb/bitstream.bin
75 fw-shipped-$(CONFIG_USB_EMI26) += emi26/loader.fw emi26/firmware.fw \ 78 fw-shipped-$(CONFIG_USB_EMI26) += emi26/loader.fw emi26/firmware.fw \
76 emi26/bitstream.fw 79 emi26/bitstream.fw
77 fw-shipped-$(CONFIG_USB_EMI62) += emi62/loader.fw emi62/bitstream.fw \ 80 fw-shipped-$(CONFIG_USB_EMI62) += emi62/loader.fw emi62/bitstream.fw \
78 emi62/spdif.fw emi62/midi.fw 81 emi62/spdif.fw emi62/midi.fw
79 fw-shipped-$(CONFIG_USB_KAWETH) += kaweth/new_code.bin kaweth/trigger_code.bin \ 82 fw-shipped-$(CONFIG_USB_KAWETH) += kaweth/new_code.bin kaweth/trigger_code.bin \
80 kaweth/new_code_fix.bin \ 83 kaweth/new_code_fix.bin \
81 kaweth/trigger_code_fix.bin 84 kaweth/trigger_code_fix.bin
82 ifdef CONFIG_FIRMWARE_IN_KERNEL 85 ifdef CONFIG_FIRMWARE_IN_KERNEL
83 fw-shipped-$(CONFIG_USB_SERIAL_KEYSPAN_MPR) += keyspan/mpr.fw 86 fw-shipped-$(CONFIG_USB_SERIAL_KEYSPAN_MPR) += keyspan/mpr.fw
84 fw-shipped-$(CONFIG_USB_SERIAL_KEYSPAN_USA18X) += keyspan/usa18x.fw 87 fw-shipped-$(CONFIG_USB_SERIAL_KEYSPAN_USA18X) += keyspan/usa18x.fw
85 fw-shipped-$(CONFIG_USB_SERIAL_KEYSPAN_USA19) += keyspan/usa19.fw 88 fw-shipped-$(CONFIG_USB_SERIAL_KEYSPAN_USA19) += keyspan/usa19.fw
86 fw-shipped-$(CONFIG_USB_SERIAL_KEYSPAN_USA19QI) += keyspan/usa19qi.fw 89 fw-shipped-$(CONFIG_USB_SERIAL_KEYSPAN_USA19QI) += keyspan/usa19qi.fw
87 fw-shipped-$(CONFIG_USB_SERIAL_KEYSPAN_USA19QW) += keyspan/usa19qw.fw 90 fw-shipped-$(CONFIG_USB_SERIAL_KEYSPAN_USA19QW) += keyspan/usa19qw.fw
88 fw-shipped-$(CONFIG_USB_SERIAL_KEYSPAN_USA19W) += keyspan/usa19w.fw 91 fw-shipped-$(CONFIG_USB_SERIAL_KEYSPAN_USA19W) += keyspan/usa19w.fw
89 fw-shipped-$(CONFIG_USB_SERIAL_KEYSPAN_USA28) += keyspan/usa28.fw 92 fw-shipped-$(CONFIG_USB_SERIAL_KEYSPAN_USA28) += keyspan/usa28.fw
90 fw-shipped-$(CONFIG_USB_SERIAL_KEYSPAN_USA28XA) += keyspan/usa28xa.fw 93 fw-shipped-$(CONFIG_USB_SERIAL_KEYSPAN_USA28XA) += keyspan/usa28xa.fw
91 fw-shipped-$(CONFIG_USB_SERIAL_KEYSPAN_USA28XB) += keyspan/usa28xb.fw 94 fw-shipped-$(CONFIG_USB_SERIAL_KEYSPAN_USA28XB) += keyspan/usa28xb.fw
92 fw-shipped-$(CONFIG_USB_SERIAL_KEYSPAN_USA28X) += keyspan/usa28x.fw 95 fw-shipped-$(CONFIG_USB_SERIAL_KEYSPAN_USA28X) += keyspan/usa28x.fw
93 fw-shipped-$(CONFIG_USB_SERIAL_KEYSPAN_USA49W) += keyspan/usa49w.fw 96 fw-shipped-$(CONFIG_USB_SERIAL_KEYSPAN_USA49W) += keyspan/usa49w.fw
94 fw-shipped-$(CONFIG_USB_SERIAL_KEYSPAN_USA49WLC) += keyspan/usa49wlc.fw 97 fw-shipped-$(CONFIG_USB_SERIAL_KEYSPAN_USA49WLC) += keyspan/usa49wlc.fw
95 else 98 else
96 fw-shipped- += keyspan/mpr.fw keyspan/usa18x.fw keyspan/usa19.fw \ 99 fw-shipped- += keyspan/mpr.fw keyspan/usa18x.fw keyspan/usa19.fw \
97 keyspan/usa19qi.fw keyspan/usa19qw.fw keyspan/usa19w.fw \ 100 keyspan/usa19qi.fw keyspan/usa19qw.fw keyspan/usa19w.fw \
98 keyspan/usa28.fw keyspan/usa28xa.fw keyspan/usa28xb.fw \ 101 keyspan/usa28.fw keyspan/usa28xa.fw keyspan/usa28xb.fw \
99 keyspan/usa28x.fw keyspan/usa49w.fw keyspan/usa49wlc.fw 102 keyspan/usa28x.fw keyspan/usa49w.fw keyspan/usa49wlc.fw
100 endif 103 endif
101 fw-shipped-$(CONFIG_USB_SERIAL_TI) += ti_3410.fw ti_5052.fw \ 104 fw-shipped-$(CONFIG_USB_SERIAL_TI) += ti_3410.fw ti_5052.fw \
102 mts_cdma.fw mts_gsm.fw mts_edge.fw 105 mts_cdma.fw mts_gsm.fw mts_edge.fw
103 fw-shipped-$(CONFIG_USB_SERIAL_EDGEPORT) += edgeport/boot.fw edgeport/boot2.fw \ 106 fw-shipped-$(CONFIG_USB_SERIAL_EDGEPORT) += edgeport/boot.fw edgeport/boot2.fw \
104 edgeport/down.fw edgeport/down2.fw 107 edgeport/down.fw edgeport/down2.fw
105 fw-shipped-$(CONFIG_USB_SERIAL_EDGEPORT_TI) += edgeport/down3.bin 108 fw-shipped-$(CONFIG_USB_SERIAL_EDGEPORT_TI) += edgeport/down3.bin
106 fw-shipped-$(CONFIG_USB_SERIAL_WHITEHEAT) += whiteheat_loader.fw whiteheat.fw \ 109 fw-shipped-$(CONFIG_USB_SERIAL_WHITEHEAT) += whiteheat_loader.fw whiteheat.fw \
107 # whiteheat_loader_debug.fw 110 # whiteheat_loader_debug.fw
108 fw-shipped-$(CONFIG_USB_SERIAL_KEYSPAN_PDA) += keyspan_pda/keyspan_pda.fw 111 fw-shipped-$(CONFIG_USB_SERIAL_KEYSPAN_PDA) += keyspan_pda/keyspan_pda.fw
109 fw-shipped-$(CONFIG_USB_SERIAL_XIRCOM) += keyspan_pda/xircom_pgs.fw 112 fw-shipped-$(CONFIG_USB_SERIAL_XIRCOM) += keyspan_pda/xircom_pgs.fw
110 fw-shipped-$(CONFIG_USB_VICAM) += vicam/firmware.fw 113 fw-shipped-$(CONFIG_USB_VICAM) += vicam/firmware.fw
111 fw-shipped-$(CONFIG_VIDEO_CPIA2) += cpia2/stv0672_vp4.bin 114 fw-shipped-$(CONFIG_VIDEO_CPIA2) += cpia2/stv0672_vp4.bin
112 fw-shipped-$(CONFIG_YAM) += yam/1200.bin yam/9600.bin 115 fw-shipped-$(CONFIG_YAM) += yam/1200.bin yam/9600.bin
113 116
114 fw-shipped-all := $(fw-shipped-y) $(fw-shipped-m) $(fw-shipped-) 117 fw-shipped-all := $(fw-shipped-y) $(fw-shipped-m) $(fw-shipped-)
115 118
116 # Directories which we _might_ need to create, so we have a rule for them. 119 # Directories which we _might_ need to create, so we have a rule for them.
117 firmware-dirs := $(sort $(patsubst %,$(objtree)/$(obj)/%/,$(dir $(fw-external-y) $(fw-shipped-all)))) 120 firmware-dirs := $(sort $(patsubst %,$(objtree)/$(obj)/%/,$(dir $(fw-external-y) $(fw-shipped-all))))
118 121
119 quiet_cmd_mkdir = MKDIR $(patsubst $(objtree)/%,%,$@) 122 quiet_cmd_mkdir = MKDIR $(patsubst $(objtree)/%,%,$@)
120 cmd_mkdir = mkdir -p $@ 123 cmd_mkdir = mkdir -p $@
121 124
122 quiet_cmd_ihex = IHEX $@ 125 quiet_cmd_ihex = IHEX $@
123 cmd_ihex = $(OBJCOPY) -Iihex -Obinary $< $@ 126 cmd_ihex = $(OBJCOPY) -Iihex -Obinary $< $@
124 127
125 quiet_cmd_ihex2fw = IHEX2FW $@ 128 quiet_cmd_ihex2fw = IHEX2FW $@
126 cmd_ihex2fw = $(objtree)/$(obj)/ihex2fw $< $@ 129 cmd_ihex2fw = $(objtree)/$(obj)/ihex2fw $< $@
127 130
128 quiet_cmd_h16tofw = H16TOFW $@ 131 quiet_cmd_h16tofw = H16TOFW $@
129 cmd_h16tofw = $(objtree)/$(obj)/ihex2fw -w $< $@ 132 cmd_h16tofw = $(objtree)/$(obj)/ihex2fw -w $< $@
130 133
131 quiet_cmd_fwbin = MK_FW $@ 134 quiet_cmd_fwbin = MK_FW $@
132 cmd_fwbin = FWNAME="$(patsubst firmware/%.gen.S,%,$@)"; \ 135 cmd_fwbin = FWNAME="$(patsubst firmware/%.gen.S,%,$@)"; \
133 FWSTR="$(subst /,_,$(subst .,_,$(subst -,_,$(patsubst \ 136 FWSTR="$(subst /,_,$(subst .,_,$(subst -,_,$(patsubst \
134 firmware/%.gen.S,%,$@))))"; \ 137 firmware/%.gen.S,%,$@))))"; \
135 ASM_WORD=$(if $(CONFIG_64BIT),.quad,.long); \ 138 ASM_WORD=$(if $(CONFIG_64BIT),.quad,.long); \
136 ASM_ALIGN=$(if $(CONFIG_64BIT),3,2); \ 139 ASM_ALIGN=$(if $(CONFIG_64BIT),3,2); \
137 PROGBITS=$(if $(CONFIG_ARM),%,@)progbits; \ 140 PROGBITS=$(if $(CONFIG_ARM),%,@)progbits; \
138 echo "/* Generated by firmware/Makefile */" > $@;\ 141 echo "/* Generated by firmware/Makefile */" > $@;\
139 echo " .section .rodata" >>$@;\ 142 echo " .section .rodata" >>$@;\
140 echo " .p2align $${ASM_ALIGN}" >>$@;\ 143 echo " .p2align $${ASM_ALIGN}" >>$@;\
141 echo "_fw_$${FWSTR}_bin:" >>$@;\ 144 echo "_fw_$${FWSTR}_bin:" >>$@;\
142 echo " .incbin \"$(2)\"" >>$@;\ 145 echo " .incbin \"$(2)\"" >>$@;\
143 echo "_fw_end:" >>$@;\ 146 echo "_fw_end:" >>$@;\
144 echo " .section .rodata.str,\"aMS\",$${PROGBITS},1" >>$@;\ 147 echo " .section .rodata.str,\"aMS\",$${PROGBITS},1" >>$@;\
145 echo " .p2align $${ASM_ALIGN}" >>$@;\ 148 echo " .p2align $${ASM_ALIGN}" >>$@;\
146 echo "_fw_$${FWSTR}_name:" >>$@;\ 149 echo "_fw_$${FWSTR}_name:" >>$@;\
147 echo " .string \"$$FWNAME\"" >>$@;\ 150 echo " .string \"$$FWNAME\"" >>$@;\
148 echo " .section .builtin_fw,\"a\",$${PROGBITS}" >>$@;\ 151 echo " .section .builtin_fw,\"a\",$${PROGBITS}" >>$@;\
149 echo " .p2align $${ASM_ALIGN}" >>$@;\ 152 echo " .p2align $${ASM_ALIGN}" >>$@;\
150 echo " $${ASM_WORD} _fw_$${FWSTR}_name" >>$@;\ 153 echo " $${ASM_WORD} _fw_$${FWSTR}_name" >>$@;\
151 echo " $${ASM_WORD} _fw_$${FWSTR}_bin" >>$@;\ 154 echo " $${ASM_WORD} _fw_$${FWSTR}_bin" >>$@;\
152 echo " $${ASM_WORD} _fw_end - _fw_$${FWSTR}_bin" >>$@; 155 echo " $${ASM_WORD} _fw_end - _fw_$${FWSTR}_bin" >>$@;
153 156
154 # One of these files will change, or come into existence, whenever 157 # One of these files will change, or come into existence, whenever
155 # the configuration changes between 32-bit and 64-bit. The .S files 158 # the configuration changes between 32-bit and 64-bit. The .S files
156 # need to change when that happens. 159 # need to change when that happens.
157 wordsize_deps := $(wildcard include/config/64bit.h include/config/32bit.h \ 160 wordsize_deps := $(wildcard include/config/64bit.h include/config/32bit.h \
158 include/config/ppc32.h include/config/ppc64.h \ 161 include/config/ppc32.h include/config/ppc64.h \
159 include/config/superh32.h include/config/superh64.h \ 162 include/config/superh32.h include/config/superh64.h \
160 include/config/x86_32.h include/config/x86_64.h) 163 include/config/x86_32.h include/config/x86_64.h)
161 164
162 # Workaround for make < 3.81, where .SECONDEXPANSION doesn't work. 165 # Workaround for make < 3.81, where .SECONDEXPANSION doesn't work.
163 # It'll end up depending on these targets, so make them a PHONY rule which 166 # It'll end up depending on these targets, so make them a PHONY rule which
164 # depends on _all_ the directories in $(firmware-dirs), and it'll work out OK. 167 # depends on _all_ the directories in $(firmware-dirs), and it'll work out OK.
165 PHONY += $(objtree)/$$(%) $(objtree)/$(obj)/$$(%) 168 PHONY += $(objtree)/$$(%) $(objtree)/$(obj)/$$(%)
166 $(objtree)/$$(%) $(objtree)/$(obj)/$$(%): $(firmware-dirs) 169 $(objtree)/$$(%) $(objtree)/$(obj)/$$(%): $(firmware-dirs)
167 @true 170 @true
168 171
169 # For the $$(dir %) trick, where we need % to be expanded first. 172 # For the $$(dir %) trick, where we need % to be expanded first.
170 .SECONDEXPANSION: 173 .SECONDEXPANSION:
171 174
172 $(patsubst %,$(obj)/%.gen.S, $(fw-shipped-y)): %: $(wordsize_deps) \ 175 $(patsubst %,$(obj)/%.gen.S, $(fw-shipped-y)): %: $(wordsize_deps) \
173 | $(objtree)/$$(dir %) 176 | $(objtree)/$$(dir %)
174 $(call cmd,fwbin,$(patsubst %.gen.S,%,$@)) 177 $(call cmd,fwbin,$(patsubst %.gen.S,%,$@))
175 $(patsubst %,$(obj)/%.gen.S, $(fw-external-y)): %: $(wordsize_deps) \ 178 $(patsubst %,$(obj)/%.gen.S, $(fw-external-y)): %: $(wordsize_deps) \
176 include/config/extra/firmware/dir.h | $(objtree)/$$(dir %) 179 include/config/extra/firmware/dir.h | $(objtree)/$$(dir %)
177 $(call cmd,fwbin,$(fwabs)/$(patsubst $(obj)/%.gen.S,%,$@)) 180 $(call cmd,fwbin,$(fwabs)/$(patsubst $(obj)/%.gen.S,%,$@))
178 181
179 # The .o files depend on the binaries directly; the .S files don't. 182 # The .o files depend on the binaries directly; the .S files don't.
180 $(patsubst %,$(obj)/%.gen.o, $(fw-shipped-y)): %.gen.o: % 183 $(patsubst %,$(obj)/%.gen.o, $(fw-shipped-y)): %.gen.o: %
181 $(patsubst %,$(obj)/%.gen.o, $(fw-external-y)): $(obj)/%.gen.o: $(fwdir)/% 184 $(patsubst %,$(obj)/%.gen.o, $(fw-external-y)): $(obj)/%.gen.o: $(fwdir)/%
182 185
183 # .ihex is used just as a simple way to hold binary files in a source tree 186 # .ihex is used just as a simple way to hold binary files in a source tree
184 # where binaries are frowned upon. They are directly converted with objcopy. 187 # where binaries are frowned upon. They are directly converted with objcopy.
185 $(obj)/%: $(obj)/%.ihex | $(objtree)/$(obj)/$$(dir %) 188 $(obj)/%: $(obj)/%.ihex | $(objtree)/$(obj)/$$(dir %)
186 $(call cmd,ihex) 189 $(call cmd,ihex)
187 190
188 # Don't depend on ihex2fw if we're installing and it already exists. 191 # Don't depend on ihex2fw if we're installing and it already exists.
189 # Putting it after | in the dependencies doesn't seem sufficient when 192 # Putting it after | in the dependencies doesn't seem sufficient when
190 # we're installing after a cross-compile, because ihex2fw has dependencies 193 # we're installing after a cross-compile, because ihex2fw has dependencies
191 # on stuff like /usr/lib/gcc/ppc64-redhat-linux/4.3.0/include/stddef.h and 194 # on stuff like /usr/lib/gcc/ppc64-redhat-linux/4.3.0/include/stddef.h and
192 # thus wants to be rebuilt. Which it can't be, if the prebuilt kernel tree 195 # thus wants to be rebuilt. Which it can't be, if the prebuilt kernel tree
193 # is exported read-only for someone to run 'make install'. 196 # is exported read-only for someone to run 'make install'.
194 ifeq ($(INSTALL):$(wildcard $(obj)/ihex2fw),install:$(obj)/ihex2fw) 197 ifeq ($(INSTALL):$(wildcard $(obj)/ihex2fw),install:$(obj)/ihex2fw)
195 ihex2fw_dep := 198 ihex2fw_dep :=
196 else 199 else
197 ihex2fw_dep := $(obj)/ihex2fw 200 ihex2fw_dep := $(obj)/ihex2fw
198 endif 201 endif
199 202
200 # .HEX is also Intel HEX, but where the offset and length in each record 203 # .HEX is also Intel HEX, but where the offset and length in each record
201 # is actually meaningful, because the firmware has to be loaded in a certain 204 # is actually meaningful, because the firmware has to be loaded in a certain
202 # order rather than as a single binary blob. Thus, we convert them into our 205 # order rather than as a single binary blob. Thus, we convert them into our
203 # more compact binary representation of ihex records (<linux/ihex.h>) 206 # more compact binary representation of ihex records (<linux/ihex.h>)
204 $(obj)/%.fw: $(obj)/%.HEX $(ihex2fw_dep) | $(objtree)/$(obj)/$$(dir %) 207 $(obj)/%.fw: $(obj)/%.HEX $(ihex2fw_dep) | $(objtree)/$(obj)/$$(dir %)
205 $(call cmd,ihex2fw) 208 $(call cmd,ihex2fw)
206 209
207 # .H16 is our own modified form of Intel HEX, with 16-bit length for records. 210 # .H16 is our own modified form of Intel HEX, with 16-bit length for records.
208 $(obj)/%.fw: $(obj)/%.H16 $(ihex2fw_dep) | $(objtree)/$(obj)/$$(dir %) 211 $(obj)/%.fw: $(obj)/%.H16 $(ihex2fw_dep) | $(objtree)/$(obj)/$$(dir %)
209 $(call cmd,h16tofw) 212 $(call cmd,h16tofw)
210 213
211 $(firmware-dirs): 214 $(firmware-dirs):
212 $(call cmd,mkdir) 215 $(call cmd,mkdir)
213 216
214 obj-y += $(patsubst %,%.gen.o, $(fw-external-y)) 217 obj-y += $(patsubst %,%.gen.o, $(fw-external-y))
215 obj-$(CONFIG_FIRMWARE_IN_KERNEL) += $(patsubst %,%.gen.o, $(fw-shipped-y)) 218 obj-$(CONFIG_FIRMWARE_IN_KERNEL) += $(patsubst %,%.gen.o, $(fw-shipped-y))
216 219
217 # Remove .S files and binaries created from ihex 220 # Remove .S files and binaries created from ihex
218 # (during 'make clean' .config isn't included so they're all in $(fw-shipped-)) 221 # (during 'make clean' .config isn't included so they're all in $(fw-shipped-))
219 targets := $(fw-shipped-) $(patsubst $(obj)/%,%, \ 222 targets := $(fw-shipped-) $(patsubst $(obj)/%,%, \
220 $(shell find $(obj) -name \*.gen.S 2>/dev/null)) 223 $(shell find $(obj) -name \*.gen.S 2>/dev/null))
221 224
222 # Without this, built-in.o won't be created when it's empty, and the 225 # Without this, built-in.o won't be created when it's empty, and the
223 # final vmlinux link will fail. 226 # final vmlinux link will fail.
224 obj-n := dummy 227 obj-n := dummy
225 228
226 hostprogs-y := ihex2fw 229 hostprogs-y := ihex2fw
227 230
1 ********** 1 **********
2 * WHENCE * 2 * WHENCE *
3 ********** 3 **********
4 4
5 This file attempts to document the origin and licensing information, 5 This file attempts to document the origin and licensing information,
6 if known, for each piece of firmware distributed for use with the Linux 6 if known, for each piece of firmware distributed for use with the Linux
7 kernel. 7 kernel.
8 8
9 -------------------------------------------------------------------------- 9 --------------------------------------------------------------------------
10 10
11 Driver: ambassador -- Madge Ambassador (Collage PCI 155 Server) ATM NIC. 11 Driver: ambassador -- Madge Ambassador (Collage PCI 155 Server) ATM NIC.
12 12
13 File: firmware/atmsar11.fw 13 File: firmware/atmsar11.fw
14 14
15 Licence: Allegedly GPLv2+, but no source visible. Marked: 15 Licence: Allegedly GPLv2+, but no source visible. Marked:
16 16
17 Madge Ambassador ATM Adapter microcode. 17 Madge Ambassador ATM Adapter microcode.
18 Copyright (C) 1995-1999 Madge Networks Ltd. 18 Copyright (C) 1995-1999 Madge Networks Ltd.
19 19
20 This microcode data is placed under the terms of the GNU General 20 This microcode data is placed under the terms of the GNU General
21 Public License. The GPL is contained in /usr/doc/copyright/GPL on a 21 Public License. The GPL is contained in /usr/doc/copyright/GPL on a
22 Debian system and in the file COPYING in the Linux kernel source. 22 Debian system and in the file COPYING in the Linux kernel source.
23 23
24 We would prefer you not to distribute modified versions without 24 We would prefer you not to distribute modified versions without
25 consultation and not to ask for assembly/other microcode source. 25 consultation and not to ask for assembly/other microcode source.
26 26
27 -------------------------------------------------------------------------- 27 --------------------------------------------------------------------------
28 28
29 Driver: korg1212 -- Korg 1212 IO audio device 29 Driver: korg1212 -- Korg 1212 IO audio device
30 30
31 File: korg/k1212.dsp 31 File: korg/k1212.dsp
32 32
33 Licence: Unknown 33 Licence: Unknown
34 34
35 Found in alsa-firmware package in hex form; no licensing information. 35 Found in alsa-firmware package in hex form; no licensing information.
36 36
37 -------------------------------------------------------------------------- 37 --------------------------------------------------------------------------
38 38
39 Driver: maestro3 -- ESS Allegro Maestro3 audio device 39 Driver: maestro3 -- ESS Allegro Maestro3 audio device
40 40
41 File: ess/maestro3_assp_kernel.fw 41 File: ess/maestro3_assp_kernel.fw
42 File: ess/maestro3_assp_minisrc.fw 42 File: ess/maestro3_assp_minisrc.fw
43 43
44 Licence: Unknown 44 Licence: Unknown
45 45
46 Found in alsa-firmware package in hex form with a comment claiming to 46 Found in alsa-firmware package in hex form with a comment claiming to
47 be GPLv2+, but without source -- and with another comment saying "ESS 47 be GPLv2+, but without source -- and with another comment saying "ESS
48 drops binary dsp code images on our heads, but we don't get to see 48 drops binary dsp code images on our heads, but we don't get to see
49 specs on the dsp." 49 specs on the dsp."
50 50
51 -------------------------------------------------------------------------- 51 --------------------------------------------------------------------------
52 52
53 Driver: ymfpci -- Yamaha YMF724/740/744/754 audio devices 53 Driver: ymfpci -- Yamaha YMF724/740/744/754 audio devices
54 54
55 File: yamaha/ds1_ctrl.fw 55 File: yamaha/ds1_ctrl.fw
56 File: yamaha/ds1_dsp.fw 56 File: yamaha/ds1_dsp.fw
57 File: yamaha/ds1e_ctrl.fw 57 File: yamaha/ds1e_ctrl.fw
58 58
59 Licence: Unknown 59 Licence: Unknown
60 60
61 Found alsa-firmware package in hex form, with the following comment: 61 Found alsa-firmware package in hex form, with the following comment:
62 Copyright (c) 1997-1999 Yamaha Corporation. All Rights Reserved. 62 Copyright (c) 1997-1999 Yamaha Corporation. All Rights Reserved.
63 63
64 -------------------------------------------------------------------------- 64 --------------------------------------------------------------------------
65 65
66 Driver: SCSI_ADVANSYS - AdvanSys SCSI 66 Driver: SCSI_ADVANSYS - AdvanSys SCSI
67 67
68 File: advansys/mcode.bin 68 File: advansys/mcode.bin
69 File: advansys/3550.bin 69 File: advansys/3550.bin
70 File: advansys/38C0800.bin 70 File: advansys/38C0800.bin
71 File: advansys/38C1600.bin 71 File: advansys/38C1600.bin
72 72
73 Licence: BSD, no source available. 73 Licence: BSD, no source available.
74 74
75 Found in hex form in kernel source. 75 Found in hex form in kernel source.
76 76
77 -------------------------------------------------------------------------- 77 --------------------------------------------------------------------------
78 78
79 Driver: SCSI_QLOGIC_1280 - Qlogic QLA 1240/1x80/1x160 SCSI support 79 Driver: SCSI_QLOGIC_1280 - Qlogic QLA 1240/1x80/1x160 SCSI support
80 80
81 File: qlogic/1040.bin 81 File: qlogic/1040.bin
82 File: qlogic/1280.bin 82 File: qlogic/1280.bin
83 File: qlogic/12160.bin 83 File: qlogic/12160.bin
84 84
85 Licence: Allegedly GPLv2+, but no source visible. Marked: 85 Licence: Allegedly GPLv2+, but no source visible. Marked:
86 86
87 QLOGIC LINUX SOFTWARE 87 QLOGIC LINUX SOFTWARE
88 QLogic ISP1280/ device driver for Linux 2.2.x and 2.4.x 88 QLogic ISP1280/ device driver for Linux 2.2.x and 2.4.x
89 Copyright (C) 2001 Qlogic Corporation (www.qlogic.com) 89 Copyright (C) 2001 Qlogic Corporation (www.qlogic.com)
90 90
91 -------------------------------------------------------------------------- 91 --------------------------------------------------------------------------
92 Driver: smctr -- SMC ISA/MCA Token Ring adapter 92 Driver: smctr -- SMC ISA/MCA Token Ring adapter
93 93
94 File: tr_smctr.bin 94 File: tr_smctr.bin
95 Info: MCT.BIN v6.3C1 03/01/95 95 Info: MCT.BIN v6.3C1 03/01/95
96 96
97 Original licence info: 97 Original licence info:
98 98
99 * This firmware is licensed to you strictly for use in conjunction 99 * This firmware is licensed to you strictly for use in conjunction
100 * with the use of SMC TokenRing adapters. There is no waranty 100 * with the use of SMC TokenRing adapters. There is no waranty
101 * expressed or implied about its fitness for any purpose. 101 * expressed or implied about its fitness for any purpose.
102 102
103 -------------------------------------------------------------------------- 103 --------------------------------------------------------------------------
104 104
105 Driver: kaweth -- USB KLSI KL5USB101-based Ethernet device 105 Driver: kaweth -- USB KLSI KL5USB101-based Ethernet device
106 106
107 File: kaweth/new_code.bin 107 File: kaweth/new_code.bin
108 File: kaweth/new_code_fix.bin 108 File: kaweth/new_code_fix.bin
109 File: kaweth/trigger_code.bin 109 File: kaweth/trigger_code.bin
110 File: kaweth/trigger_code_fix.bin 110 File: kaweth/trigger_code_fix.bin
111 111
112 Licence: Unknown 112 Licence: Unknown
113 113
114 Found in hex form in the kernel source. 114 Found in hex form in the kernel source.
115 115
116 -------------------------------------------------------------------------- 116 --------------------------------------------------------------------------
117 117
118 Driver: ttusb-budget -- Technotrend/Hauppauge Nova-USB devices 118 Driver: ttusb-budget -- Technotrend/Hauppauge Nova-USB devices
119 119
120 File: ttusb-budget/dspbootcode.bin 120 File: ttusb-budget/dspbootcode.bin
121 121
122 Licence: Unknown 122 Licence: Unknown
123 123
124 Found in hex form in the kernel source. 124 Found in hex form in the kernel source.
125 125
126 -------------------------------------------------------------------------- 126 --------------------------------------------------------------------------
127 127
128 Driver: keyspan -- USB Keyspan USA-xxx serial device 128 Driver: keyspan -- USB Keyspan USA-xxx serial device
129 129
130 File: keyspan/mpr.fw 130 File: keyspan/mpr.fw
131 File: keyspan/usa18x.fw 131 File: keyspan/usa18x.fw
132 File: keyspan/usa19.fw 132 File: keyspan/usa19.fw
133 File: keyspan/usa19qi.fw 133 File: keyspan/usa19qi.fw
134 File: keyspan/usa19qw.fw 134 File: keyspan/usa19qw.fw
135 File: keyspan/usa19w.fw 135 File: keyspan/usa19w.fw
136 File: keyspan/usa28.fw 136 File: keyspan/usa28.fw
137 File: keyspan/usa28xa.fw 137 File: keyspan/usa28xa.fw
138 File: keyspan/usa28xb.fw 138 File: keyspan/usa28xb.fw
139 File: keyspan/usa28x.fw 139 File: keyspan/usa28x.fw
140 File: keyspan/usa49w.fw 140 File: keyspan/usa49w.fw
141 File: keyspan/usa49wlc.fw 141 File: keyspan/usa49wlc.fw
142 142
143 Converted from Intel HEX files, used in our binary representation of ihex. 143 Converted from Intel HEX files, used in our binary representation of ihex.
144 144
145 Original licence information: 145 Original licence information:
146 146
147 Copyright (C) 1999-2001 147 Copyright (C) 1999-2001
148 Keyspan, A division of InnoSys Incorporated ("Keyspan") 148 Keyspan, A division of InnoSys Incorporated ("Keyspan")
149 149
150 as an unpublished work. This notice does not imply unrestricted or 150 as an unpublished work. This notice does not imply unrestricted or
151 public access to the source code from which this firmware image is 151 public access to the source code from which this firmware image is
152 derived. Except as noted below this firmware image may not be 152 derived. Except as noted below this firmware image may not be
153 reproduced, used, sold or transferred to any third party without 153 reproduced, used, sold or transferred to any third party without
154 Keyspan's prior written consent. All Rights Reserved. 154 Keyspan's prior written consent. All Rights Reserved.
155 155
156 Permission is hereby granted for the distribution of this firmware 156 Permission is hereby granted for the distribution of this firmware
157 image as part of a Linux or other Open Source operating system kernel 157 image as part of a Linux or other Open Source operating system kernel
158 in text or binary form as required. 158 in text or binary form as required.
159 159
160 This firmware may not be modified and may only be used with 160 This firmware may not be modified and may only be used with
161 Keyspan hardware. Distribution and/or Modification of the 161 Keyspan hardware. Distribution and/or Modification of the
162 keyspan.c driver which includes this firmware, in whole or in 162 keyspan.c driver which includes this firmware, in whole or in
163 part, requires the inclusion of this statement." 163 part, requires the inclusion of this statement."
164 164
165 -------------------------------------------------------------------------- 165 --------------------------------------------------------------------------
166 166
167 Driver: keyspan_pda -- USB Keyspan PDA single-port serial device 167 Driver: keyspan_pda -- USB Keyspan PDA single-port serial device
168 168
169 File: keyspan_pda/keyspan_pda.fw 169 File: keyspan_pda/keyspan_pda.fw
170 Source: keyspan_pda/keyspan_pda.S 170 Source: keyspan_pda/keyspan_pda.S
171 171
172 File: keyspan_pda/xircom_pgs.fw 172 File: keyspan_pda/xircom_pgs.fw
173 Source: keyspan_pda/xircom_pgs.S 173 Source: keyspan_pda/xircom_pgs.S
174 174
175 Licence: GPLv2+ 175 Licence: GPLv2+
176 176
177 Compiled from original 8051 source into Intel HEX, used in our binary ihex form. 177 Compiled from original 8051 source into Intel HEX, used in our binary ihex form.
178 178
179 -------------------------------------------------------------------------- 179 --------------------------------------------------------------------------
180 180
181 Driver: emi26 -- EMI 2|6 USB Audio interface 181 Driver: emi26 -- EMI 2|6 USB Audio interface
182 182
183 File: emi26/bitstream.fw 183 File: emi26/bitstream.fw
184 Info: VERSION=1.1.1.131 DATE=2001dec06 184 Info: VERSION=1.1.1.131 DATE=2001dec06
185 185
186 File: emi26/firmware.fw 186 File: emi26/firmware.fw
187 Info: VERSION=1.0.2.916 DATE=12.02.2002 187 Info: VERSION=1.0.2.916 DATE=12.02.2002
188 188
189 File: emi26/loader.fw 189 File: emi26/loader.fw
190 190
191 Converted from Intel HEX files, used in our binary representation of ihex. 191 Converted from Intel HEX files, used in our binary representation of ihex.
192 192
193 Original licence information: 193 Original licence information:
194 /* 194 /*
195 * This firmware is for the Emagic EMI 2|6 Audio Interface 195 * This firmware is for the Emagic EMI 2|6 Audio Interface
196 * 196 *
197 * The firmware contained herein is Copyright (c) 1999-2002 Emagic 197 * The firmware contained herein is Copyright (c) 1999-2002 Emagic
198 * as an unpublished work. This notice does not imply unrestricted 198 * as an unpublished work. This notice does not imply unrestricted
199 * or public access to this firmware which is a trade secret of Emagic, 199 * or public access to this firmware which is a trade secret of Emagic,
200 * and which may not be reproduced, used, sold or transferred to 200 * and which may not be reproduced, used, sold or transferred to
201 * any third party without Emagic's written consent. All Rights Reserved. 201 * any third party without Emagic's written consent. All Rights Reserved.
202 * 202 *
203 * Permission is hereby granted for the distribution of this firmware 203 * Permission is hereby granted for the distribution of this firmware
204 * image as part of a Linux or other Open Source operating system kernel 204 * image as part of a Linux or other Open Source operating system kernel
205 * in text or binary form as required. 205 * in text or binary form as required.
206 * 206 *
207 * This firmware may not be modified and may only be used with the 207 * This firmware may not be modified and may only be used with the
208 * Emagic EMI 2|6 Audio Interface. Distribution and/or Modification of 208 * Emagic EMI 2|6 Audio Interface. Distribution and/or Modification of
209 * any driver which includes this firmware, in whole or in part, 209 * any driver which includes this firmware, in whole or in part,
210 * requires the inclusion of this statement. 210 * requires the inclusion of this statement.
211 */ 211 */
212 212
213 -------------------------------------------------------------------------- 213 --------------------------------------------------------------------------
214 214
215 Driver: emi62 -- EMI 6|2m USB Audio interface 215 Driver: emi62 -- EMI 6|2m USB Audio interface
216 216
217 File: emi62/bitstream.fw 217 File: emi62/bitstream.fw
218 Info: VERSION=1.0.0.191 DATE= 2002oct28 218 Info: VERSION=1.0.0.191 DATE= 2002oct28
219 219
220 File: emi62/loader.fw 220 File: emi62/loader.fw
221 Source: EMILOAD.HEX 221 Source: EMILOAD.HEX
222 Info: VERSION=1.0.2.002 DATE=10.01.2002 222 Info: VERSION=1.0.2.002 DATE=10.01.2002
223 223
224 File: emi62/midi.fw 224 File: emi62/midi.fw
225 Source: EMI62MFW.HEX 225 Source: EMI62MFW.HEX
226 Info: VERSION=1.04.062 DATE=16.10.2002 226 Info: VERSION=1.04.062 DATE=16.10.2002
227 227
228 File: emi62/spdif.fw 228 File: emi62/spdif.fw
229 Source: EMI62SFW.HEX 229 Source: EMI62SFW.HEX
230 Info: VERSION=1.04.062 DATE=16.10.2002 230 Info: VERSION=1.04.062 DATE=16.10.2002
231 231
232 Converted from Intel HEX files, used in our binary representation of ihex. 232 Converted from Intel HEX files, used in our binary representation of ihex.
233 233
234 Original licence information: None 234 Original licence information: None
235 235
236 -------------------------------------------------------------------------- 236 --------------------------------------------------------------------------
237 237
238 Driver: ti_usb_3410_5052 -- USB TI 3410/5052 serial device 238 Driver: ti_usb_3410_5052 -- USB TI 3410/5052 serial device
239 239
240 File: ti_3410.fw 240 File: ti_3410.fw
241 Info: firmware 9/10/04 FW3410_Special_StartWdogOnStartPort 241 Info: firmware 9/10/04 FW3410_Special_StartWdogOnStartPort
242 242
243 File: ti_5052.fw 243 File: ti_5052.fw
244 Info: firmware 9/18/04 244 Info: firmware 9/18/04
245 245
246 Licence: Allegedly GPLv2+, but no source visible. Marked: 246 Licence: Allegedly GPLv2+, but no source visible. Marked:
247 Copyright (C) 2004 Texas Instruments 247 Copyright (C) 2004 Texas Instruments
248 248
249 Found in hex form in kernel source. 249 Found in hex form in kernel source.
250 250
251 -------------------------------------------------------------------------- 251 --------------------------------------------------------------------------
252 252
253 Driver: ti_usb_3410_5052 -- Multi-Tech USB cell modems 253 Driver: ti_usb_3410_5052 -- Multi-Tech USB cell modems
254 254
255 File: mts_cdma.fw 255 File: mts_cdma.fw
256 File: mts_gsm.fw 256 File: mts_gsm.fw
257 File: mts_edge.fw 257 File: mts_edge.fw
258 258
259 Licence: "all firmware components are redistributable in binary form" 259 Licence: "all firmware components are redistributable in binary form"
260 per support@multitech.com 260 per support@multitech.com
261 Copyright (C) 2005 Multi-Tech Systems, Inc. 261 Copyright (C) 2005 Multi-Tech Systems, Inc.
262 262
263 Found in hex form in ftp://ftp.multitech.com/wireless/wireless_linux.zip 263 Found in hex form in ftp://ftp.multitech.com/wireless/wireless_linux.zip
264 264
265 -------------------------------------------------------------------------- 265 --------------------------------------------------------------------------
266 266
267 Driver: whiteheat -- USB ConnectTech WhiteHEAT serial device 267 Driver: whiteheat -- USB ConnectTech WhiteHEAT serial device
268 268
269 File: whiteheat.fw 269 File: whiteheat.fw
270 Version: 4.06 270 Version: 4.06
271 271
272 File: whiteheat_loader.fw 272 File: whiteheat_loader.fw
273 File: whiteheat_loader_debug.fw 273 File: whiteheat_loader_debug.fw
274 274
275 Licence: Allegedly GPLv2, but no source visible. Marked: 275 Licence: Allegedly GPLv2, but no source visible. Marked:
276 Copyright (C) 2000-2002 ConnectTech Inc 276 Copyright (C) 2000-2002 ConnectTech Inc
277 277
278 Debug loader claims the following behaviour: 278 Debug loader claims the following behaviour:
279 Port 1 LED flashes when the vend_ax program is running 279 Port 1 LED flashes when the vend_ax program is running
280 Port 2 LED flashes when any SETUP command arrives 280 Port 2 LED flashes when any SETUP command arrives
281 Port 3 LED flashes when any valid VENDOR request occurs 281 Port 3 LED flashes when any valid VENDOR request occurs
282 Port 4 LED flashes when the EXTERNAL RAM DOWNLOAD request occurs 282 Port 4 LED flashes when the EXTERNAL RAM DOWNLOAD request occurs
283 283
284 Converted from Intel HEX files, used in our binary representation of ihex. 284 Converted from Intel HEX files, used in our binary representation of ihex.
285 285
286 -------------------------------------------------------------------------- 286 --------------------------------------------------------------------------
287 287
288 Driver: ip2 -- Computone IntelliPort Plus serial device 288 Driver: ip2 -- Computone IntelliPort Plus serial device
289 289
290 File: intelliport2.bin 290 File: intelliport2.bin
291 291
292 Licence: Unknown 292 Licence: Unknown
293 293
294 Found in hex form in kernel source. 294 Found in hex form in kernel source.
295 295
296 -------------------------------------------------------------------------- 296 --------------------------------------------------------------------------
297 297
298 Driver: CPiA2 -- cameras based on Vision's CPiA2 298 Driver: CPiA2 -- cameras based on Vision's CPiA2
299 299
300 File: cpia2/stv0672_vp4.bin 300 File: cpia2/stv0672_vp4.bin
301 301
302 Licence: Allegedly GPLv2+, but no source visible. Marked: 302 Licence: Allegedly GPLv2+, but no source visible. Marked:
303 Copyright (C) 2001 STMicroelectronics, Inc. 303 Copyright (C) 2001 STMicroelectronics, Inc.
304 Contact: steve.miller@st.com 304 Contact: steve.miller@st.com
305 Description: This file contains patch data for the CPiA2 (stv0672) VP4. 305 Description: This file contains patch data for the CPiA2 (stv0672) VP4.
306 306
307 Found in hex form in kernel source. 307 Found in hex form in kernel source.
308 308
309 -------------------------------------------------------------------------- 309 --------------------------------------------------------------------------
310 310
311 Driver: DABUSB -- Digital Audio Broadcasting (DAB) Receiver for USB and Linux 311 Driver: DABUSB -- Digital Audio Broadcasting (DAB) Receiver for USB and Linux
312 312
313 File: dabusb/firmware.fw 313 File: dabusb/firmware.fw
314 File: dabusb/bitstream.bin 314 File: dabusb/bitstream.bin
315 315
316 Licence: Distributable 316 Licence: Distributable
317 317
318 * Copyright (C) 1999 BayCom GmbH 318 * Copyright (C) 1999 BayCom GmbH
319 * 319 *
320 * Redistribution and use in source and binary forms, with or without 320 * Redistribution and use in source and binary forms, with or without
321 * modification, are permitted provided that redistributions of source 321 * modification, are permitted provided that redistributions of source
322 * code retain the above copyright notice and this comment without 322 * code retain the above copyright notice and this comment without
323 * modification. 323 * modification.
324 324
325 -------------------------------------------------------------------------- 325 --------------------------------------------------------------------------
326 326
327 Driver: USB_VICAM -- USB 3com HomeConnect (aka vicam) 327 Driver: USB_VICAM -- USB 3com HomeConnect (aka vicam)
328 328
329 File: vicam/firmware.fw 329 File: vicam/firmware.fw
330 330
331 Licence: Unknown 331 Licence: Unknown
332 332
333 Found in hex form in kernel source. 333 Found in hex form in kernel source.
334 334
335 -------------------------------------------------------------------------- 335 --------------------------------------------------------------------------
336 336
337 Driver: USB_SERIAL_EDGEPORT - USB Inside Out Edgeport Serial Driver 337 Driver: USB_SERIAL_EDGEPORT - USB Inside Out Edgeport Serial Driver
338 338
339 File: edgeport/boot.fw 339 File: edgeport/boot.fw
340 File: edgeport/boot2.fw 340 File: edgeport/boot2.fw
341 File: edgeport/down.fw 341 File: edgeport/down.fw
342 File: edgeport/down2.fw 342 File: edgeport/down2.fw
343 343
344 Licence: Allegedly GPLv2+, but no source visible. Marked: 344 Licence: Allegedly GPLv2+, but no source visible. Marked:
345 //************************************************************** 345 //**************************************************************
346 //* Edgeport/4 Binary Image 346 //* Edgeport/4 Binary Image
347 //* Generated by HEX2C v1.06 347 //* Generated by HEX2C v1.06
348 //* Copyright (C) 1998 Inside Out Networks, All rights reserved. 348 //* Copyright (C) 1998 Inside Out Networks, All rights reserved.
349 //************************************************************** 349 //**************************************************************
350 350
351 Found in hex form in kernel source. 351 Found in hex form in kernel source.
352 352
353 -------------------------------------------------------------------------- 353 --------------------------------------------------------------------------
354 354
355 Driver: USB_SERIAL_EDGEPORT_TI - USB Inside Out Edgeport Serial Driver 355 Driver: USB_SERIAL_EDGEPORT_TI - USB Inside Out Edgeport Serial Driver
356 (TI Devices) 356 (TI Devices)
357 357
358 File: edgeport/down3.bin 358 File: edgeport/down3.bin
359 359
360 Licence: 360 Licence:
361 //************************************************************** 361 //**************************************************************
362 //* Edgeport Binary Image (for TI based products) 362 //* Edgeport Binary Image (for TI based products)
363 //* Generated by TIBin2C v2.00 (watchport) 363 //* Generated by TIBin2C v2.00 (watchport)
364 //* Copyright (C) 2001 Inside Out Networks, All rights reserved. 364 //* Copyright (C) 2001 Inside Out Networks, All rights reserved.
365 //************************************************************** 365 //**************************************************************
366 366
367 Found in hex form in kernel source. 367 Found in hex form in kernel source.
368 368
369 -------------------------------------------------------------------------- 369 --------------------------------------------------------------------------
370 370
371 Driver: ATARI_DSP56K - Atari DSP56k support 371 Driver: ATARI_DSP56K - Atari DSP56k support
372 372
373 File: dsp56k/bootstrap.bin 373 File: dsp56k/bootstrap.bin
374 Source: dsp56k/bootstrap.asm 374 Source: dsp56k/bootstrap.asm
375 375
376 Licence: GPLv2 or later 376 Licence: GPLv2 or later
377 377
378 DSP56001 assembler, possibly buildable with a56 from 378 DSP56001 assembler, possibly buildable with a56 from
379 http://www.zdomain.com/a56.html 379 http://www.zdomain.com/a56.html
380 380
381 -------------------------------------------------------------------------- 381 --------------------------------------------------------------------------
382 382
383 Driver: SND_SB16_CSP - Sound Blaster 16/AWE CSP support 383 Driver: SND_SB16_CSP - Sound Blaster 16/AWE CSP support
384 384
385 File: sb16/mulaw_main.csp 385 File: sb16/mulaw_main.csp
386 File: sb16/alaw_main.csp 386 File: sb16/alaw_main.csp
387 File: sb16/ima_adpcm_init.csp 387 File: sb16/ima_adpcm_init.csp
388 File: sb16/ima_adpcm_playback.csp 388 File: sb16/ima_adpcm_playback.csp
389 File: sb16/ima_adpcm_capture.csp 389 File: sb16/ima_adpcm_capture.csp
390 390
391 Licence: Allegedly GPLv2+, but no source visible. Marked: 391 Licence: Allegedly GPLv2+, but no source visible. Marked:
392 /* 392 /*
393 * Copyright (c) 1994 Creative Technology Ltd. 393 * Copyright (c) 1994 Creative Technology Ltd.
394 * Microcode files for SB16 Advanced Signal Processor 394 * Microcode files for SB16 Advanced Signal Processor
395 */ 395 */
396 396
397 Found in hex form in kernel source. 397 Found in hex form in kernel source.
398 398
399 -------------------------------------------------------------------------- 399 --------------------------------------------------------------------------
400 400
401 Driver: CASSINI - Sun Cassini 401 Driver: CASSINI - Sun Cassini
402 402
403 File: sun/cassini.bin 403 File: sun/cassini.bin
404 404
405 Licence: Unknown 405 Licence: Unknown
406 406
407 Found in hex form in kernel source. 407 Found in hex form in kernel source.
408 408
409 -------------------------------------------------------------------------- 409 --------------------------------------------------------------------------
410 410
411 Driver: cxgb3 - Chelsio Terminator 3 1G/10G Ethernet adapter 411 Driver: cxgb3 - Chelsio Terminator 3 1G/10G Ethernet adapter
412 412
413 File: cxgb3/t3b_psram-1.1.0.bin.ihex 413 File: cxgb3/t3b_psram-1.1.0.bin.ihex
414 File: cxgb3/t3c_psram-1.1.0.bin.ihex 414 File: cxgb3/t3c_psram-1.1.0.bin.ihex
415 file: cxgb3/t3fw-7.4.0.bin.ihex 415 file: cxgb3/t3fw-7.4.0.bin.ihex
416 416
417 License: GPLv2 or OpenIB.org BSD license, no source visible 417 License: GPLv2 or OpenIB.org BSD license, no source visible
418 418
419 -------------------------------------------------------------------------- 419 --------------------------------------------------------------------------
420 420
421 Driver: cxgb3 - Chelsio Terminator 3 1G/10G Ethernet adapter
422
423 File: cxgb3/ael2005_opt_edc.bin.ihex
424 File: cxgb3/ael2005_twx_edc.bin.ihex
425 File: cxgb3/ael2020_twx_edc.bin.ihex
426
427 Licence:
428 * Copyright (c) 2007-2009 NetLogic Microsystems, Inc.
429 *
430 * Permission is hereby granted for the distribution of this firmware
431 * data in hexadecimal or equivalent format, provided this copyright
432 * notice is accompanying it.
433
434 Found in hex form in kernel source.
435
436 --------------------------------------------------------------------------
437
421 Driver: e100 -- Intel PRO/100 Ethernet NIC 438 Driver: e100 -- Intel PRO/100 Ethernet NIC
422 439
423 File: e100/d101m_ucode.bin 440 File: e100/d101m_ucode.bin
424 File: e100/d101s_ucode.bin 441 File: e100/d101s_ucode.bin
425 File: e100/d102e_ucode.bin 442 File: e100/d102e_ucode.bin
426 443
427 Licence: Unknown 444 Licence: Unknown
428 445
429 Found in hex form in kernel source. 446 Found in hex form in kernel source.
430 447
431 -------------------------------------------------------------------------- 448 --------------------------------------------------------------------------
432 449
433 Driver: acenic -- Alteon AceNIC Gigabit Ethernet card 450 Driver: acenic -- Alteon AceNIC Gigabit Ethernet card
434 451
435 File: acenic/tg1.bin 452 File: acenic/tg1.bin
436 File: acenic/tg2.bin 453 File: acenic/tg2.bin
437 454
438 Licence: Unknown 455 Licence: Unknown
439 456
440 Found in hex form in kernel source, but source allegedly available at 457 Found in hex form in kernel source, but source allegedly available at
441 http://alteon.shareable.org/ 458 http://alteon.shareable.org/
442 459
443 -------------------------------------------------------------------------- 460 --------------------------------------------------------------------------
444 461
445 Driver: tigon3 -- Broadcom Tigon3 based gigabit Ethernet cards 462 Driver: tigon3 -- Broadcom Tigon3 based gigabit Ethernet cards
446 463
447 File: tigon/tg3.bin 464 File: tigon/tg3.bin
448 File: tigon/tg3_tso.bin 465 File: tigon/tg3_tso.bin
449 File: tigon/tg3_tso5.bin 466 File: tigon/tg3_tso5.bin
450 467
451 Licence: 468 Licence:
452 * Firmware is: 469 * Firmware is:
453 * Derived from proprietary unpublished source code, 470 * Derived from proprietary unpublished source code,
454 * Copyright (C) 2000-2003 Broadcom Corporation. 471 * Copyright (C) 2000-2003 Broadcom Corporation.
455 * 472 *
456 * Permission is hereby granted for the distribution of this firmware 473 * Permission is hereby granted for the distribution of this firmware
457 * data in hexadecimal or equivalent format, provided this copyright 474 * data in hexadecimal or equivalent format, provided this copyright
458 * notice is accompanying it. 475 * notice is accompanying it.
459 476
460 Found in hex form in kernel source. 477 Found in hex form in kernel source.
461 478
462 -------------------------------------------------------------------------- 479 --------------------------------------------------------------------------
463 480
464 Driver: ADAPTEC_STARFIRE - Adaptec Starfire/DuraLAN support 481 Driver: ADAPTEC_STARFIRE - Adaptec Starfire/DuraLAN support
465 482
466 File: adaptec/starfire_rx.bin 483 File: adaptec/starfire_rx.bin
467 File: adaptec/starfire_tx.bin 484 File: adaptec/starfire_tx.bin
468 485
469 Licence: Allegedly GPLv2, but no source visible. 486 Licence: Allegedly GPLv2, but no source visible.
470 487
471 Found in hex form in kernel source, with the following notice: 488 Found in hex form in kernel source, with the following notice:
472 489
473 BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE IT IS LICENSED "AS IS" AND 490 BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE IT IS LICENSED "AS IS" AND
474 THERE IS NO WARRANTY FOR THE PROGRAM, INCLUDING BUT NOT LIMITED TO THE 491 THERE IS NO WARRANTY FOR THE PROGRAM, INCLUDING BUT NOT LIMITED TO THE
475 IMPLIED WARRANTIES OF MERCHANTIBILITY OR FITNESS FOR A PARTICULAR PURPOSE 492 IMPLIED WARRANTIES OF MERCHANTIBILITY OR FITNESS FOR A PARTICULAR PURPOSE
476 (TO THE EXTENT PERMITTED BY APPLICABLE LAW). USE OF THE PROGRAM IS AT YOUR 493 (TO THE EXTENT PERMITTED BY APPLICABLE LAW). USE OF THE PROGRAM IS AT YOUR
477 OWN RISK. IN NO EVENT WILL ADAPTEC OR ITS LICENSORS BE LIABLE TO YOU FOR 494 OWN RISK. IN NO EVENT WILL ADAPTEC OR ITS LICENSORS BE LIABLE TO YOU FOR
478 DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES 495 DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES
479 ARISING OUT OF THE USE OR INABILITY TO USE THE PROGRAM. 496 ARISING OUT OF THE USE OR INABILITY TO USE THE PROGRAM.
480 497
481 -------------------------------------------------------------------------- 498 --------------------------------------------------------------------------
482 499
483 Driver: TEHUTI - Tehuti Networks 10G Ethernet 500 Driver: TEHUTI - Tehuti Networks 10G Ethernet
484 501
485 File: tehuti/bdx.bin 502 File: tehuti/bdx.bin
486 503
487 Licence: 504 Licence:
488 505
489 Copyright (C) 2007 Tehuti Networks Ltd. 506 Copyright (C) 2007 Tehuti Networks Ltd.
490 507
491 Permission is hereby granted for the distribution of this firmware data 508 Permission is hereby granted for the distribution of this firmware data
492 in hexadecimal or equivalent format, provided this copyright notice is 509 in hexadecimal or equivalent format, provided this copyright notice is
493 accompanying it. 510 accompanying it.
494 511
495 Found in hex form in kernel source. 512 Found in hex form in kernel source.
496 513
497 -------------------------------------------------------------------------- 514 --------------------------------------------------------------------------
498 515
499 Driver: TYPHOON - 3cr990 series Typhoon 516 Driver: TYPHOON - 3cr990 series Typhoon
500 517
501 File: 3com/typhoon.bin 518 File: 3com/typhoon.bin
502 519
503 Licence: 520 Licence:
504 /* 521 /*
505 * Copyright 1999-2004 3Com Corporation. All Rights Reserved. 522 * Copyright 1999-2004 3Com Corporation. All Rights Reserved.
506 * 523 *
507 * Redistribution and use in source and binary forms of the 3c990img.h 524 * Redistribution and use in source and binary forms of the 3c990img.h
508 * microcode software are permitted provided that the following conditions 525 * microcode software are permitted provided that the following conditions
509 * are met: 526 * are met:
510 * 1. Redistribution of source code must retain the above copyright 527 * 1. Redistribution of source code must retain the above copyright
511 * notice, this list of conditions and the following disclaimer. 528 * notice, this list of conditions and the following disclaimer.
512 * 2. Redistribution in binary form must reproduce the above copyright 529 * 2. Redistribution in binary form must reproduce the above copyright
513 * notice, this list of conditions and the following disclaimer in the 530 * notice, this list of conditions and the following disclaimer in the
514 * documentation and/or other materials provided with the distribution. 531 * documentation and/or other materials provided with the distribution.
515 * 3. The name of 3Com may not be used to endorse or promote products 532 * 3. The name of 3Com may not be used to endorse or promote products
516 * derived from this software without specific prior written permission 533 * derived from this software without specific prior written permission
517 * 534 *
518 * THIS SOFTWARE IS PROVIDED BY 3COM ``AS IS'' AND ANY EXPRESS OR 535 * THIS SOFTWARE IS PROVIDED BY 3COM ``AS IS'' AND ANY EXPRESS OR
519 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 536 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
520 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 537 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
521 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 538 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
522 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 539 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
523 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 540 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
524 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 541 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
525 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 542 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
526 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 543 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
527 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 544 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
528 * 545 *
529 * USER ACKNOWLEDGES AND AGREES THAT PURCHASE OR USE OF THE 3c990img.h 546 * USER ACKNOWLEDGES AND AGREES THAT PURCHASE OR USE OF THE 3c990img.h
530 * MICROCODE SOFTWARE WILL NOT CREATE OR GIVE GROUNDS FOR A LICENSE BY 547 * MICROCODE SOFTWARE WILL NOT CREATE OR GIVE GROUNDS FOR A LICENSE BY
531 * IMPLICATION, ESTOPPEL, OR OTHERWISE IN ANY INTELLECTUAL PROPERTY RIGHTS 548 * IMPLICATION, ESTOPPEL, OR OTHERWISE IN ANY INTELLECTUAL PROPERTY RIGHTS
532 * (PATENT, COPYRIGHT, TRADE SECRET, MASK WORK, OR OTHER PROPRIETARY RIGHT) 549 * (PATENT, COPYRIGHT, TRADE SECRET, MASK WORK, OR OTHER PROPRIETARY RIGHT)
533 * EMBODIED IN ANY OTHER 3COM HARDWARE OR SOFTWARE EITHER SOLELY OR IN 550 * EMBODIED IN ANY OTHER 3COM HARDWARE OR SOFTWARE EITHER SOLELY OR IN
534 * COMBINATION WITH THE 3c990img.h MICROCODE SOFTWARE 551 * COMBINATION WITH THE 3c990img.h MICROCODE SOFTWARE
535 */ 552 */
536 553
537 Found in hex form in kernel source. 554 Found in hex form in kernel source.
538 555
539 -------------------------------------------------------------------------- 556 --------------------------------------------------------------------------
540 557
541 Driver: YAM - YAM driver for AX.25 558 Driver: YAM - YAM driver for AX.25
542 559
543 File: yam/1200.bin 560 File: yam/1200.bin
544 File: yam/9600.bin 561 File: yam/9600.bin
545 562
546 Licence: 563 Licence:
547 * (C) F6FBB 1998 564 * (C) F6FBB 1998
548 565
549 Found in hex form in kernel source. 566 Found in hex form in kernel source.
550 567
551 -------------------------------------------------------------------------- 568 --------------------------------------------------------------------------
552 569
553 Driver: 3C359 - 3Com 3C359 Token Link Velocity XL adapter 570 Driver: 3C359 - 3Com 3C359 Token Link Velocity XL adapter
554 571
555 File: 3com/3C359.bin 572 File: 3com/3C359.bin
556 573
557 Licence: 574 Licence:
558 /* 575 /*
559 * The firmware this driver downloads into the tokenring card is a 576 * The firmware this driver downloads into the tokenring card is a
560 * separate program and is not GPL'd source code, even though the Linux 577 * separate program and is not GPL'd source code, even though the Linux
561 * side driver and the routine that loads this data into the card are. 578 * side driver and the routine that loads this data into the card are.
562 * 579 *
563 * This firmware is licensed to you strictly for use in conjunction 580 * This firmware is licensed to you strictly for use in conjunction
564 * with the use of 3Com 3C359 TokenRing adapters. There is no 581 * with the use of 3Com 3C359 TokenRing adapters. There is no
565 * waranty expressed or implied about its fitness for any purpose. 582 * waranty expressed or implied about its fitness for any purpose.
566 */ 583 */
567 /* 3c359_microcode.mac: 3Com 3C359 Tokenring microcode. 584 /* 3c359_microcode.mac: 3Com 3C359 Tokenring microcode.
568 * 585 *
569 * Notes: 586 * Notes:
570 * - Loaded from xl_init upon adapter initialization. 587 * - Loaded from xl_init upon adapter initialization.
571 * 588 *
572 * Available from 3Com as part of their standard 3C359 driver. 589 * Available from 3Com as part of their standard 3C359 driver.
573 */ 590 */
574 591
575 Found in hex form in kernel source. 592 Found in hex form in kernel source.
576 593
577 -------------------------------------------------------------------------- 594 --------------------------------------------------------------------------
578 595
579 Driver: PCMCIA_PCNET - NE2000 compatible PCMCIA adapter 596 Driver: PCMCIA_PCNET - NE2000 compatible PCMCIA adapter
580 597
581 File: cis/LA-PCM.cis 598 File: cis/LA-PCM.cis
582 599
583 Licence: GPL 600 Licence: GPL
584 601
585 Originally developed by the pcmcia-cs project 602 Originally developed by the pcmcia-cs project
586 603
587 -------------------------------------------------------------------------- 604 --------------------------------------------------------------------------
588 605
589 Driver: PCMCIA_3C589 - 3Com PCMCIA adapter 606 Driver: PCMCIA_3C589 - 3Com PCMCIA adapter
590 607
591 File: cis/3CXEM556.cis 608 File: cis/3CXEM556.cis
592 609
593 Licence: GPL 610 Licence: GPL
594 611
595 Originally developed by the pcmcia-cs project 612 Originally developed by the pcmcia-cs project
596 613
597 -------------------------------------------------------------------------- 614 --------------------------------------------------------------------------
598 615
599 Driver: PCMCIA_3C574 - 3Com PCMCIA adapter 616 Driver: PCMCIA_3C574 - 3Com PCMCIA adapter
600 617
601 File: cis/3CCFEM556.cis 618 File: cis/3CCFEM556.cis
602 619
603 Licence: GPL 620 Licence: GPL
604 621
605 Originally developed by the pcmcia-cs project 622 Originally developed by the pcmcia-cs project
606 623
607 -------------------------------------------------------------------------- 624 --------------------------------------------------------------------------
608 625
609 Driver: PCMCIA_SMC91C92 - SMC 91Cxx PCMCIA 626 Driver: PCMCIA_SMC91C92 - SMC 91Cxx PCMCIA
610 627
611 File: ositech/Xilinx7OD.bin 628 File: ositech/Xilinx7OD.bin
612 629
613 Licence: Allegedly GPL, but no source visible. Marked: 630 Licence: Allegedly GPL, but no source visible. Marked:
614 This file contains the firmware of Seven of Diamonds from OSITECH. 631 This file contains the firmware of Seven of Diamonds from OSITECH.
615 (Special thanks to Kevin MacPherson of OSITECH) 632 (Special thanks to Kevin MacPherson of OSITECH)
616 633
617 Found in hex form in kernel source. 634 Found in hex form in kernel source.
618 635
619 -------------------------------------------------------------------------- 636 --------------------------------------------------------------------------
620 637
621 Driver: SCSI_QLOGICPTI - PTI Qlogic, ISP Driver 638 Driver: SCSI_QLOGICPTI - PTI Qlogic, ISP Driver
622 639
623 File: qlogic/isp1000.bin 640 File: qlogic/isp1000.bin
624 641
625 Licence: Unknown 642 Licence: Unknown
626 643
627 Found in hex form in kernel source. 644 Found in hex form in kernel source.
628 645
629 -------------------------------------------------------------------------- 646 --------------------------------------------------------------------------
630 647
631 Driver: MYRI_SBUS - MyriCOM Gigabit Ethernet 648 Driver: MYRI_SBUS - MyriCOM Gigabit Ethernet
632 649
633 File: myricom/lanai.bin 650 File: myricom/lanai.bin
634 651
635 Licence: Unknown 652 Licence: Unknown
636 653
637 Found in hex form in kernel source. 654 Found in hex form in kernel source.
638 655
639 -------------------------------------------------------------------------- 656 --------------------------------------------------------------------------
640 657
641 Driver: bnx2x: Broadcom Everest 658 Driver: bnx2x: Broadcom Everest
642 659
643 File: bnx2x-e1-4.8.53.0.fw.ihex 660 File: bnx2x-e1-4.8.53.0.fw.ihex
644 File: bnx2x-e1h-4.8.53.0.fw.ihex 661 File: bnx2x-e1h-4.8.53.0.fw.ihex
645 662
646 License: 663 License:
647 Copyright (c) 2007-2009 Broadcom Corporation 664 Copyright (c) 2007-2009 Broadcom Corporation
648 665
649 This file contains firmware data derived from proprietary unpublished 666 This file contains firmware data derived from proprietary unpublished
650 source code, Copyright (c) 2007-2009 Broadcom Corporation. 667 source code, Copyright (c) 2007-2009 Broadcom Corporation.
651 668
652 Permission is hereby granted for the distribution of this firmware data 669 Permission is hereby granted for the distribution of this firmware data
653 in hexadecimal or equivalent format, provided this copyright notice is 670 in hexadecimal or equivalent format, provided this copyright notice is
654 accompanying it. 671 accompanying it.
655 672
656 673
657 Found in hex form in kernel source. 674 Found in hex form in kernel source.
658 675
659 -------------------------------------------------------------------------- 676 --------------------------------------------------------------------------
660 677
661 Driver: BNX2 - Broadcom NetXtremeII 678 Driver: BNX2 - Broadcom NetXtremeII
662 679
663 File: bnx2/bnx2-mips-06-4.6.16.fw 680 File: bnx2/bnx2-mips-06-4.6.16.fw
664 File: bnx2/bnx2-rv2p-06-4.6.16.fw 681 File: bnx2/bnx2-rv2p-06-4.6.16.fw
665 File: bnx2/bnx2-mips-09-4.6.17.fw 682 File: bnx2/bnx2-mips-09-4.6.17.fw
666 File: bnx2/bnx2-rv2p-09-4.6.15.fw 683 File: bnx2/bnx2-rv2p-09-4.6.15.fw
667 684
668 Licence: 685 Licence:
669 686
670 This file contains firmware data derived from proprietary unpublished 687 This file contains firmware data derived from proprietary unpublished
671 source code, Copyright (c) 2004 - 2009 Broadcom Corporation. 688 source code, Copyright (c) 2004 - 2009 Broadcom Corporation.
672 689
673 Permission is hereby granted for the distribution of this firmware data 690 Permission is hereby granted for the distribution of this firmware data
674 in hexadecimal or equivalent format, provided this copyright notice is 691 in hexadecimal or equivalent format, provided this copyright notice is
675 accompanying it. 692 accompanying it.
676 693
677 Found in hex form in kernel source. 694 Found in hex form in kernel source.
678 695
679 -------------------------------------------------------------------------- 696 --------------------------------------------------------------------------
680 697
681 Driver: DVB AV7110 -- AV7110 cards 698 Driver: DVB AV7110 -- AV7110 cards
682 699
683 File: av7110/bootcode.bin 700 File: av7110/bootcode.bin
684 701
685 Licence: GPLv2 or later 702 Licence: GPLv2 or later
686 703
687 ARM assembly source code available at http://www.linuxtv.org/downloads/firmware/Boot.S 704 ARM assembly source code available at http://www.linuxtv.org/downloads/firmware/Boot.S
688 705
689 -------------------------------------------------------------------------- 706 --------------------------------------------------------------------------
690 707
691 Driver: wavefront - ISA WaveFront sound card 708 Driver: wavefront - ISA WaveFront sound card
692 709
693 File: yamaha/yss225_registers.bin 710 File: yamaha/yss225_registers.bin
694 711
695 Licence: Allegedly GPLv2+, but no source visible. 712 Licence: Allegedly GPLv2+, but no source visible.
696 713
697 Found in hex form in kernel source, with the following comment: 714 Found in hex form in kernel source, with the following comment:
698 Copyright (c) 1998-2002 by Paul Davis <pbd@op.net> 715 Copyright (c) 1998-2002 by Paul Davis <pbd@op.net>
699 716
700 -------------------------------------------------------------------------- 717 --------------------------------------------------------------------------
701 718
firmware/cxgb3/ael2005_opt_edc.bin.ihex
Diff comments   View file @ 2e8c07c
File was created 1 :10000000CC002FF4CC013CD4CC022015CC0331051C
2 :10001000CC046524CC0527FFCC06300FCC072C8BF5
3 :10002000CC08300BCC094009CC0A400ECC0B2F7207
4 :10003000CC0C3002CC0D1002CC0E2172CC0F301241
5 :10004000CC101002CC1125D2CC123012CC131002DD
6 :10005000CC14D01ECC1527D2CC163012CC171002DF
7 :10006000CC182004CC193C84CC1A6436CC1B200755
8 :10007000CC1C3F87CC1D8676CC1E40B7CC1FA74634
9 :10008000CC204047CC215673CC222982CC2330028D
10 :10009000CC2413D2CC258BBDCC262862CC273012A1
11 :1000A000CC281002CC292092CC2A3012CC2B100262
12 :1000B000CC2C5CC3CC2D0314CC2E2942CC2F300287
13 :1000C000CC301002CC31D019CC322032CC333012AB
14 :1000D000CC341002CC352A04CC363C74CC37643591
15 :1000E000CC382FA4CC393CD4CC3A6624CC3B5563D5
16 :1000F000CC3C2D42CC3D3002CC3E13D2CC3F464DC1
17 :10010000CC402862CC413012CC421002CC43203289
18 :10011000CC443012CC451002CC462FB4CC473CD452
19 :10012000CC486624CC495563CC4A2D42CC4B300296
20 :10013000CC4C13D2CC4D2ED2CC4E3002CC4F100230
21 :10014000CC502FD2CC513002CC521002CC530004F0
22 :10015000CC542942CC553002CC561002CC572092B8
23 :10016000CC583012CC591002CC5A5CC3CC5B03176C
24 :10017000CC5C2F72CC5D3002CC5E1002CC5F294289
25 :10018000CC603002CC611002CC6222CDCC63301D39
26 :10019000CC642862CC653012CC661002CC672ED2BB
27 :1001A000CC683002CC691002CC6A2D72CC6B300264
28 :1001B000CC6C1002CC6D628FCC6E2112CC6F3012E1
29 :1001C000CC701002CC715AA3CC722DC2CC73300209
30 :1001D000CC741312CC756F72CC761002CC772807D2
31 :1001E000CC7831A7CC7920C4CC7A3C24CC7B672452
32 :1001F000CC7C1002CC7D2807CC7E3187CC7F20C4FC
33 :10020000CC803C24CC816724CC821002CC83251482
34 :10021000CC843C64CC856436CC86DFF4CC876436F1
35 :10022000CC881002CC8940A4CC8A643CCC8B40168C
36 :10023000CC8C8C6CCC8D2B24CC8E3C24CC8F643518
37 :10024000CC901002CC912B24CC923C24CC93643AD9
38 :10025000CC944025CC958A5ACC961002CC97273165
39 :10026000CC983011CC991001CC9AC7A0CC9B01003E
40 :10027000CC9CC502CC9D53ACCC9EC503CC9FD5D5A0
41 :10028000CCA0C600CCA12A6DCCA2C601CCA32A4C1E
42 :10029000CCA4C602CCA50111CCA6C60CCCA7590093
43 :1002A000CCA8C710CCA90700CCAAC718CCAB0700B4
44 :1002B000CCACC720CCAD4700CCAEC801CCAF7F5092
45 :1002C000CCB0C802CCB17760CCB2C803CCB37FCE7F
46 :1002D000CCB4C804CCB55700CCB6C805CCB75F11B8
47 :1002E000CCB8C806CCB94751CCBAC807CCBB57E18B
48 :1002F000CCBCC808CCBD2700CCBEC809CCBF000010
49 :10030000CCC0C821CCC10002CCC2C822CCC30014CE
50 :10031000CCC4C832CCC51186CCC6C847CCC71E02D7
51 :10032000CCC8C013CCC9F341CCCAC01ACCCB04464C
52 :10033000CCCCC024CCCD1000CCCEC025CCCF0A0074
53 :10034000CCD0C026CCD10C0CCCD2C027CCD30C0C3A
54 :10035000CCD4C029CCD500A0CCD6C030CCD70A0094
55 :10036000CCD8C03CCCD9001CCCDAC005CCDB7A069A
56 :10037000CCDC0000CCDD2731CCDE3011CCDF10012D
57 :10038000CCE0C620CCE10000CCE2C621CCE3003FAB
58 :10039000CCE4C622CCE50000CCE6C623CCE70000C6
59 :1003A000CCE8C624CCE90000CCEAC625CCEB0000A2
60 :1003B000CCECC627CCED0000CCEEC628CCEF00007C
61 :1003C000CCF0C62CCCF10000CCF20000CCF3280617
62 :1003D000CCF43CB6CCF5C161CCF66134CCF76135D8
63 :1003E000CCF85443CCF90303CCFA6524CCFB000BC6
64 :1003F000CCFC1002CCFD2104CCFE3C24CCFF21051A
65 :10040000CD003805CD016524CD02DFF4CD034005D4
66 :10041000CD046524CD051002CD065DD3CD070306BE
67 :10042000CD082FF7CD0938F7CD0A60B7CD0BDFFD2A
68 :10043000CD0C000ACD0D1002CD0E00007CC7AE59C8
69 :00000001FF
70
firmware/cxgb3/ael2005_twx_edc.bin.ihex
Diff comments   View file @ 2e8c07c
File was created 1 :10000000CC004009CC0127FFCC02300FCC0340AA22
2 :10001000CC04401CCC05401ECC062FF4CC073CD4AD
3 :10002000CC082035CC093145CC0A6524CC0B26A25E
4 :10003000CC0C3012CC0D1002CC0E29C2CC0F3002E9
5 :10004000CC101002CC112072CC123012CC13100242
6 :10005000CC1422CDCC15301DCC162E52CC1730121C
7 :10006000CC181002CC1928E2CC1A3002CC1B10029A
8 :10007000CC1C628FCC1D2AC2CC1E3012CC1F1002A9
9 :10008000CC205553CC212AE2CC223002CC231302BF
10 :10009000CC24401ECC252BE2CC263012CC271002DB
11 :1000A000CC282DA2CC293012CC2A1002CC2B2BA28A
12 :1000B000CC2C3002CC2D1002CC2E5EE3CC2F0305CD
13 :1000C000CC30400ECC312BC2CC323002CC331002BB
14 :1000D000CC342B82CC353012CC361002CC37566360
15 :1000E000CC380302CC39401ECC3A6F72CC3B1002A4
16 :1000F000CC3C628FCC3D2BE2CC3E3012CC3F100288
17 :10010000CC4022CDCC41301DCC422E52CC433012BB
18 :10011000CC441002CC452522CC463012CC471002EC
19 :10012000CC482DA2CC493012CC4A1002CC4B2CA288
20 :10013000CC4C3012CC4D1002CC4E2FA4CC4F3CD422
21 :10014000CC506624CC51410BCC5256B3CC5303C493
22 :10015000CC542FB2CC553002CC561002CC57220BC7
23 :10016000CC58303BCC5956B3CC5A03C3CC5B866BCE
24 :10017000CC5C400CCC5D23A2CC5E3012CC5F100274
25 :10018000CC602DA2CC613012CC621002CC632CA2C8
26 :10019000CC643012CC651002CC662FB4CC673CD452
27 :1001A000CC686624CC6956B3CC6A03C3CC6B866B2F
28 :1001B000CC6C401CCC6D2205CC6E3035CC6F5B53C3
29 :1001C000CC702C52CC713002CC7213C2CC735CC395
30 :1001D000CC740317CC752522CC763012CC77100264
31 :1001E000CC782DA2CC793012CC7A1002CC7B2B8229
32 :1001F000CC7C3012CC7D1002CC7E5663CC7F0303C6
33 :10020000CC80401ECC810004CC822C42CC833012A6
34 :10021000CC841002CC856F72CC861002CC87628FA2
35 :10022000CC882304CC893C84CC8A6436CC8BDFF424
36 :10023000CC8C6436CC8D2FF5CC8E3005CC8F865689
37 :10024000CC90DFBACC9156A3CC92D05ACC9321C299
38 :10025000CC943012CC951392CC96D05ACC9756A30E
39 :10026000CC98DFBACC990383CC9A6F72CC9B1002E6
40 :10027000CC9C28C5CC9D3005CC9E4178CC9F565354
41 :10028000CCA00384CCA122B2CCA23012CCA3100209
42 :10029000CCA42BE5CCA53005CCA641E8CCA7565381
43 :1002A000CCA80382CCA90002CCAA4258CCAB2474BF
44 :1002B000CCAC3C84CCAD6437CCAEDFF4CCAF64378F
45 :1002C000CCB02FF5CCB13C05CCB28757CCB3B888B5
46 :1002D000CCB49787CCB5DFF4CCB66724CCB7866AAC
47 :1002E000CCB86F72CCB91002CCBA2D01CCBB301196
48 :1002F000CCBC1001CCBDC620CCBE14E5CCBFC62101
49 :10030000CCC0C53DCCC1C622CCC23CBECCC3C623EA
50 :10031000CCC44452CCC5C624CCC6C5C5CCC7C625A2
51 :10032000CCC8E01ECCC9C627CCCA0000CCCBC6289E
52 :10033000CCCC0000CCCDC62BCCCE0000CCCFC62C74
53 :10034000CCD00000CCD10000CCD22D01CCD33011C8
54 :10035000CCD41001CCD5C620CCD60000CCD7C62139
55 :10036000CCD80000CCD9C622CCDA00CECCDBC62358
56 :10037000CCDC007FCCDDC624CCDE0032CCDFC62551
57 :10038000CCE00000CCE1C627CCE20000CCE3C628DC
58 :10039000CCE40000CCE5C62BCCE60000CCE7C62CB4
59 :1003A000CCE80000CCE90000CCEA2D01CCEB301108
60 :1003B000CCEC1001CCEDC502CCEE609FCCEFC600BA
61 :1003C000CCF02A6ECCF1C601CCF22A2CCCF3C60CB0
62 :1003D000CCF45400CCF5C710CCF60700CCF7C71806
63 :1003E000CCF80700CCF9C720CCFA4700CCFBC728D3
64 :1003F000CCFC0700CCFDC729CCFE1207CCFFC801FE
65 :10040000CD007F50CD01C802CD027760CD03C80377
66 :10041000CD047FCECD05C804CD06520ECD07C8054C
67 :10042000CD085C11CD09C806CD0A3C51CD0BC807DB
68 :10043000CD0C4061CD0DC808CD0E49C1CD0FC80906
69 :10044000CD103840CD11C80ACD120000CD13C821FF
70 :10045000CD140002CD15C822CD160046CD17C844D4
71 :10046000CD18182FCD19C013CD1AF341CD1BC01ACA
72 :10047000CD1C0446CD1DC024CD1E1000CD1FC025AF
73 :10048000CD200A00CD21C026CD220C0CCD23C027C3
74 :10049000CD240C0CCD25C029CD2600A0CD27C03001
75 :1004A000CD280A00CD29C03CCD2A001CCD2B000050
76 :1004B000CD2C2B84CD2D3C74CD2E6435CD2FDFF487
77 :1004C000CD306435CD312806CD323006CD3385654B
78 :1004D000CD342B24CD353C24CD366436CD371002B7
79 :1004E000CD382B24CD393C24CD3A6436CD3B404524
80 :1004F000CD3C8656CD3D1002CD3E2807CD3F31A7DD
81 :10050000CD4020C4CD413C24CD426724CD431002D0
82 :10051000CD442807CD453187CD4620C4CD473C2466
83 :10052000CD486724CD491002CD4A2514CD4B3C64FB
84 :10053000CD4C6436CD4DDFF4CD4E6436CD4F100238
85 :10054000CD502806CD513CB6CD52C161CD5361345A
86 :10055000CD546135CD555443CD560303CD57652455
87 :10056000CD58000BCD591002CD5AD019CD5B2104C6
88 :10057000CD5C3C24CD5D2105CD5E3805CD5F652485
89 :10058000CD60DFF4CD614005CD626524CD632E8D55
90 :10059000CD64303DCD655DD3CD660306CD672FF7C5
91 :1005A000CD6838F7CD6960B7CD6ADFFDCD6B000A45
92 :0C05B000CD6C1002CD6D000052A76B0E48
93 :00000001FF
94
firmware/cxgb3/ael2020_twx_edc.bin.ihex
Diff comments   View file @ 2e8c07c
File was created 1 :10000000D8004009D8012FFFD802300FD80340AAEA
2 :10001000D804401CD805401ED8062FF4D8073DC48C
3 :10002000D8082035D8093035D80A6524D80B2CB229
4 :10003000D80C3012D80D1002D80E26E2D80F30227C
5 :10004000D8101002D81127D2D8123022D81310029B
6 :10005000D8142822D8153012D8161002D817249296
7 :10006000D8183022D8191002D81A2772D81B30128B
8 :10007000D81C1002D81D23D2D81E3022D81F10023F
9 :10008000D82022CDD821301DD82227F2D8233022E3
10 :10009000D8241002D8255553D8260307D82725225F
11 :1000A000D8283022D8291002D82A2142D82B301241
12 :1000B000D82C1002D82D4016D82E5E63D82F0344BA
13 :1000C000D8302142D8313012D8321002D833400E05
14 :1000D000D8342522D8353022D8361002D8372B52C2
15 :1000E000D8383012D8391002D83A2742D83B3022BB
16 :1000F000D83C1002D83D25E2D83E3022D83F10022D
17 :10010000D8402FA4D8413DC4D8426624D843414B9F
18 :10011000D84456B3D84503C6D846866BD847400C5A
19 :10012000D8482712D8493012D84A1002D84B2C4B45
20 :10013000D84C309BD84D56B3D84E03C3D84F866B9E
21 :10014000D850400CD8512272D8523022D8531002C5
22 :10015000D8542742D8553022D8561002D85725E215
23 :10016000D8583022D8591002D85A2FB4D85B3DC481
24 :10017000D85C6624D85D56B3D85E03C3D85F866B5F
25 :10018000D860401CD8612C45D8623095D8635B5349
26 :10019000D8642372D8653012D86613C2D8675CC39E
27 :1001A000D8682712D8693012D86A1312D86B2B522C
28 :1001B000D86C3012D86D1002D86E2742D86F30221A
29 :1001C000D8701002D8712582D8723022D8731002EC
30 :1001D000D8742142D8753012D8761002D877628F41
31 :1001E000D8782985D87933A5D87A25E2D87B3022EA
32 :1001F000D87C1002D87D5653D87E03D2D87F401EBB
33 :10020000D8806F72D8811002D882628FD88323047D
34 :10021000D8843C84D8856436D886DFF4D8876436A1
35 :10022000D8882FF5D8893005D88A8656D88BDFBA7A
36 :10023000D88C56A3D88DD05AD88E2972D88F301228
37 :10024000D8901392D891D05AD89256A3D893DFBAA7
38 :10025000D8940383D8956F72D8961002D8972B45FF
39 :10026000D8983005D8994178D89A5653D89B0384AA
40 :10027000D89C2A62D89D3012D89E1002D89F2F0594
41 :10028000D8A03005D8A141C8D8A25653D8A303821C
42 :10029000D8A40002D8A54218D8A62474D8A73C84B4
43 :1002A000D8A86437D8A9DFF4D8AA6437D8AB2FF51B
44 :1002B000D8AC3C05D8AD8757D8AEB888D8AF9787AB
45 :1002C000D8B0DFF4D8B16724D8B2866AD8B36F72D9
46 :1002D000D8B41002D8B52641D8B63021D8B710010D
47 :1002E000D8B8C620D8B90000D8BAC621D8BB0000FB
48 :1002F000D8BCC622D8BD00CED8BEC623D8BF007F8A
49 :10030000D8C0C624D8C10032D8C2C625D8C3000080
50 :10031000D8C4C627D8C50000D8C6C628D8C700008C
51 :10032000D8C8C62CD8C90000D8CA0000D8CB2641EE
52 :10033000D8CC3021D8CD1001D8CEC502D8CF53ACFF
53 :10034000D8D0C503D8D12CD3D8D2C600D8D32A6EE2
54 :10035000D8D4C601D8D52A2CD8D6C605D8D7555753
55 :10036000D8D8C60CD8D95400D8DAC710D8DB0700C3
56 :10037000D8DCC711D8DD0F06D8DEC718D8DF0700D4
57 :10038000D8E0C719D8E10F06D8E2C720D8E3470064
58 :10039000D8E4C721D8E50F06D8E6C728D8E7070074
59 :1003A000D8E8C729D8E91207D8EAC801D8EB7F50A6
60 :1003B000D8ECC802D8ED7760D8EEC803D8EF7FCE6E
61 :1003C000D8F0C804D8F1520ED8F2C805D8F35C11A1
62 :1003D000D8F4C806D8F53C51D8F6C807D8F740611C
63 :1003E000D8F8C808D8F949C1D8FAC809D8FB3840A4
64 :1003F000D8FCC80AD8FD0000D8FEC821D8FF0002EA
65 :10040000D900C822D9010046D902C844D903182FFF
66 :10041000D904C013D905F341D906C084D9070030E7
67 :10042000D908C904D9091401D90ACB0CD90B000485
68 :10043000D90CCB0ED90DA00AD90ECB0FD90FC0C045
69 :10044000D910CB10D911C0C0D912CB11D91300A02B
70 :10045000D914CB12D9150007D916C241D917A0005B
71 :10046000D918C243D9197FE0D91AC604D91B000E86
72 :10047000D91CC609D91D00F5D91EC611D91F000EF9
73 :10048000D920C660D9219600D922C687D923000475
74 :10049000D924C60AD92504F5D9260000D927264132
75 :1004A000D9283021D9291001D92AC620D92B14E501
76 :1004B000D92CC621D92DC53DD92EC622D92F3CBE57
77 :1004C000D930C623D9314452D932C624D933C5C50F
78 :1004D000D934C625D935E01ED936C627D93700000C
79 :1004E000D938C628D9390000D93AC62CD93B0000E2
80 :1004F000D93C0000D93D2B84D93E3C74D93F6435AA
81 :10050000D940DFF4D9416435D9422806D9433006B1
82 :10051000D9448565D9452B24D9463C24D94764362E
83 :10052000D9481002D9492B24D94A3C24D94B6436E6
84 :10053000D94C4045D94D8656D94E5663D94F030202
85 :10054000D950401ED9511002D9522807D95331A78A
86 :10055000D95420C4D9553C24D9566724D957100200
87 :10056000D9582807D9593187D95A20C4D95B3C2496
88 :10057000D95C6724D95D1002D95E24F4D95F3C644C
89 :10058000D9606436D961DFF4D9626436D963100268
90 :10059000D9642006D9653D76D966C161D9676134D1
91 :1005A000D9686135D9695443D96A0303D96B652485
92 :1005B000D96C00FBD96D1002D96E20D4D96F3C24C0
93 :1005C000D9702025D9713005D9726524D9731002EC
94 :1005D000D974D019D9752104D9763C24D97721054D
95 :1005E000D9783805D9796524D97ADFF4D97B4005E3
96 :1005F000D97C6524D97D2E8DD97E303DD97F2408C4
97 :10060000D98035D8D9815DD3D9820307D98388872A
98 :10061000D98463A7D9858887D98663A7D987DFFD61
99 :10062000D98800F9D9891002D98A0000878C30D97D
100 :00000001FF
101