trivial: fix typos "man[ae]g?ment" -> "management"

Signed-off-by: Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> Signed-off-by: Jiri Kosina <jkosina@suse.cz>

trivial: fix typos "man[ae]g?ment" -> "management"
Signed-off-by: Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
Uwe Kleine-Koenig · Jiri Kosina
1 parent 31d0f84591
Showing 18 changed files with 21 additions and 21 deletions Inline Diff
Documentation/DocBook/mtdnand.tmpl
Documentation/DocBook/scsi.tmpl
Documentation/scsi/ChangeLog.megaraid
Documentation/sound/alsa/HD-Audio-Models.txt
Documentation/trace/ftrace.txt
arch/arm/Makefile
arch/frv/lib/cache.S
arch/mn10300/include/asm/cacheflush.h
drivers/media/dvb/siano/smscoreapi.c
drivers/media/dvb/siano/smscoreapi.h
drivers/media/radio/radio-mr800.c
drivers/message/fusion/mptbase.c
drivers/net/macb.c
drivers/net/wireless/ath/ath5k/reg.h
drivers/net/wireless/atmel.c
drivers/usb/host/xhci.h
drivers/usb/wusbcore/wa-hc.h
include/linux/mISDNif.h
 <?xml version="1.0" encoding="UTF-8"?>
 <!DOCTYPE book PUBLIC "-//OASIS//DTD DocBook XML V4.1.2//EN"
 	"http://www.oasis-open.org/docbook/xml/4.1.2/docbookx.dtd" []>
 <book id="MTD-NAND-Guide">
 <bookinfo>
  <title>MTD NAND Driver Programming Interface</title>
  <authorgroup>
   <author>
    <firstname>Thomas</firstname>
    <surname>Gleixner</surname>
    <affiliation>
     <address>
      <email>tglx@linutronix.de</email>
     </address>
    </affiliation>
   </author>
  </authorgroup>
  <copyright>
   <year>2004</year>
   <holder>Thomas Gleixner</holder>
  </copyright>
  <legalnotice>
   <para>
     This documentation is free software; you can redistribute
     it and/or modify it under the terms of the GNU General Public
     License version 2 as published by the Free Software Foundation.
   </para>
   <para>
     This program is distributed in the hope that it will be
     useful, but WITHOUT ANY WARRANTY; without even the implied
     warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
     See the GNU General Public License for more details.
   </para>
   <para>
     You should have received a copy of the GNU General Public
     License along with this program; if not, write to the Free
     Software Foundation, Inc., 59 Temple Place, Suite 330, Boston,
     MA 02111-1307 USA
   </para>
   <para>
     For more details see the file COPYING in the source
     distribution of Linux.
   </para>
  </legalnotice>
 </bookinfo>
 <toc></toc>
  <chapter id="intro">
      <title>Introduction</title>
  <para>
  	The generic NAND driver supports almost all NAND and AG-AND based
 	chips and connects them to the Memory Technology Devices (MTD)
 	subsystem of the Linux Kernel.
  </para>
  <para>
  	This documentation is provided for developers who want to implement
 	board drivers or filesystem drivers suitable for NAND devices.
  </para>
  </chapter>
  <chapter id="bugs">
     <title>Known Bugs And Assumptions</title>
  <para>
 	None.	
  </para>
  </chapter>
  <chapter id="dochints">
     <title>Documentation hints</title>
     <para>
     The function and structure docs are autogenerated. Each function and 
     struct member has a short description which is marked with an [XXX] identifier.
     The following chapters explain the meaning of those identifiers.
     </para>
     <sect1 id="Function_identifiers_XXX">
 	<title>Function identifiers [XXX]</title>
     	<para>
 	The functions are marked with [XXX] identifiers in the short
 	comment. The identifiers explain the usage and scope of the
 	functions. Following identifiers are used:
     	</para>
 	<itemizedlist>
 		<listitem><para>
 	  	[MTD Interface]</para><para>
 		These functions provide the interface to the MTD kernel API. 
 		They are not replacable and provide functionality
 		which is complete hardware independent.
 		</para></listitem>
 		<listitem><para>
 	  	[NAND Interface]</para><para>
 		These functions are exported and provide the interface to the NAND kernel API. 
 		</para></listitem>
 		<listitem><para>
 	  	[GENERIC]</para><para>
 		Generic functions are not replacable and provide functionality
 		which is complete hardware independent.
 		</para></listitem>
 		<listitem><para>
 	  	[DEFAULT]</para><para>
 		Default functions provide hardware related functionality which is suitable
 		for most of the implementations. These functions can be replaced by the
 		board driver if neccecary. Those functions are called via pointers in the
 		NAND chip description structure. The board driver can set the functions which
 		should be replaced by board dependent functions before calling nand_scan().
 		If the function pointer is NULL on entry to nand_scan() then the pointer
 		is set to the default function which is suitable for the detected chip type.
 		</para></listitem>
 	</itemizedlist>
     </sect1>
     <sect1 id="Struct_member_identifiers_XXX">
 	<title>Struct member identifiers [XXX]</title>
     	<para>
 	The struct members are marked with [XXX] identifiers in the 
 	comment. The identifiers explain the usage and scope of the
 	members. Following identifiers are used:
     	</para>
 	<itemizedlist>
 		<listitem><para>
 	  	[INTERN]</para><para>
 		These members are for NAND driver internal use only and must not be
 		modified. Most of these values are calculated from the chip geometry
 		information which is evaluated during nand_scan().
 		</para></listitem>
 		<listitem><para>
 	  	[REPLACEABLE]</para><para>
 		Replaceable members hold hardware related functions which can be 
 		provided by the board driver. The board driver can set the functions which
 		should be replaced by board dependent functions before calling nand_scan().
 		If the function pointer is NULL on entry to nand_scan() then the pointer
 		is set to the default function which is suitable for the detected chip type.
 		</para></listitem>
 		<listitem><para>
 	  	[BOARDSPECIFIC]</para><para>
 		Board specific members hold hardware related information which must
 		be provided by the board driver. The board driver must set the function
 		pointers and datafields before calling nand_scan().
 		</para></listitem>
 		<listitem><para>
 	  	[OPTIONAL]</para><para>
 		Optional members can hold information relevant for the board driver. The
 		generic NAND driver code does not use this information.
 		</para></listitem>
 	</itemizedlist>
     </sect1>
  </chapter>   
  <chapter id="basicboarddriver">
     	<title>Basic board driver</title>
 	<para>
 		For most boards it will be sufficient to provide just the
 		basic functions and fill out some really board dependent
 		members in the nand chip description structure.
 	</para>
 	<sect1 id="Basic_defines">
 		<title>Basic defines</title>
 		<para>
 			At least you have to provide a mtd structure and
 			a storage for the ioremap'ed chip address.
 			You can allocate the mtd structure using kmalloc
 			or you can allocate it statically.
 			In case of static allocation you have to allocate
 			a nand_chip structure too.
 		</para>
 		<para>
 			Kmalloc based example
 		</para>
 		<programlisting>
 static struct mtd_info *board_mtd;
 static unsigned long baseaddr;
 		</programlisting>
 		<para>
 			Static example
 		</para>
 		<programlisting>
 static struct mtd_info board_mtd;
 static struct nand_chip board_chip;
 static unsigned long baseaddr;
 		</programlisting>
 	</sect1>
 	<sect1 id="Partition_defines">
 		<title>Partition defines</title>
 		<para>
 			If you want to divide your device into partitions, then
 			enable the configuration switch CONFIG_MTD_PARTITIONS and define
 			a partitioning scheme suitable to your board.
 		</para>
 		<programlisting>
 #define NUM_PARTITIONS 2
 static struct mtd_partition partition_info[] = {
 	{ .name = "Flash partition 1",
 	  .offset =  0,
 	  .size =    8 * 1024 * 1024 },
 	{ .name = "Flash partition 2",
 	  .offset =  MTDPART_OFS_NEXT,
 	  .size =    MTDPART_SIZ_FULL },
 };
 		</programlisting>
 	</sect1>
 	<sect1 id="Hardware_control_functions">
 		<title>Hardware control function</title>
 		<para>
 			The hardware control function provides access to the 
 			control pins of the NAND chip(s). 
 			The access can be done by GPIO pins or by address lines.
 			If you use address lines, make sure that the timing
 			requirements are met.
 		</para>
 		<para>
 			<emphasis>GPIO based example</emphasis>
 		</para>
 		<programlisting>
 static void board_hwcontrol(struct mtd_info *mtd, int cmd)
 {
 	switch(cmd){
 		case NAND_CTL_SETCLE: /* Set CLE pin high */ break;
 		case NAND_CTL_CLRCLE: /* Set CLE pin low */ break;
 		case NAND_CTL_SETALE: /* Set ALE pin high */ break;
 		case NAND_CTL_CLRALE: /* Set ALE pin low */ break;
 		case NAND_CTL_SETNCE: /* Set nCE pin low */ break;
 		case NAND_CTL_CLRNCE: /* Set nCE pin high */ break;
 	}
 }
 		</programlisting>
 		<para>
 			<emphasis>Address lines based example.</emphasis> It's assumed that the
 			nCE pin is driven by a chip select decoder.
 		</para>
 		<programlisting>
 static void board_hwcontrol(struct mtd_info *mtd, int cmd)
 {
 	struct nand_chip *this = (struct nand_chip *) mtd->priv;
 	switch(cmd){
 		case NAND_CTL_SETCLE: this->IO_ADDR_W |= CLE_ADRR_BIT;  break;
 		case NAND_CTL_CLRCLE: this->IO_ADDR_W &amp;= ~CLE_ADRR_BIT; break;
 		case NAND_CTL_SETALE: this->IO_ADDR_W |= ALE_ADRR_BIT;  break;
 		case NAND_CTL_CLRALE: this->IO_ADDR_W &amp;= ~ALE_ADRR_BIT; break;
 	}
 }
 		</programlisting>
 	</sect1>
 	<sect1 id="Device_ready_function">
 		<title>Device ready function</title>
 		<para>
 			If the hardware interface has the ready busy pin of the NAND chip connected to a
 			GPIO or other accesible I/O pin, this function is used to read back the state of the
 			pin. The function has no arguments and should return 0, if the device is busy (R/B pin 
 			is low) and 1, if the device is ready (R/B pin is high).
 			If the hardware interface does not give access to the ready busy pin, then
 			the function must not be defined and the function pointer this->dev_ready is set to NULL.		
 		</para>
 	</sect1>
 	<sect1 id="Init_function">
 		<title>Init function</title>
 		<para>
 			The init function allocates memory and sets up all the board
 			specific parameters and function pointers. When everything
 			is set up nand_scan() is called. This function tries to
 			detect and identify then chip. If a chip is found all the
 			internal data fields are initialized accordingly.
 			The structure(s) have to be zeroed out first and then filled with the neccecary 
 			information about the device.
 		</para>
 		<programlisting>
 int __init board_init (void)
 {
 	struct nand_chip *this;
 	int err = 0;
 	/* Allocate memory for MTD device structure and private data */
 	board_mtd = kzalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL);
 	if (!board_mtd) {
 		printk ("Unable to allocate NAND MTD device structure.\n");
 		err = -ENOMEM;
 		goto out;
 	}
 	/* map physical address */
 	baseaddr = (unsigned long)ioremap(CHIP_PHYSICAL_ADDRESS, 1024);
 	if(!baseaddr){
 		printk("Ioremap to access NAND chip failed\n");
 		err = -EIO;
 		goto out_mtd;
 	}
 	/* Get pointer to private data */
 	this = (struct nand_chip *) ();
 	/* Link the private data with the MTD structure */
 	board_mtd->priv = this;
 	/* Set address of NAND IO lines */
 	this->IO_ADDR_R = baseaddr;
 	this->IO_ADDR_W = baseaddr;
 	/* Reference hardware control function */
 	this->hwcontrol = board_hwcontrol;
 	/* Set command delay time, see datasheet for correct value */
 	this->chip_delay = CHIP_DEPENDEND_COMMAND_DELAY;
 	/* Assign the device ready function, if available */
 	this->dev_ready = board_dev_ready;
 	this->eccmode = NAND_ECC_SOFT;
 	/* Scan to find existence of the device */
 	if (nand_scan (board_mtd, 1)) {
 		err = -ENXIO;
 		goto out_ior;
 	}
 	add_mtd_partitions(board_mtd, partition_info, NUM_PARTITIONS);
 	goto out;
 out_ior:
 	iounmap((void *)baseaddr);
 out_mtd:
 	kfree (board_mtd);
 out:
 	return err;
 }
 module_init(board_init);
 		</programlisting>
 	</sect1>
 	<sect1 id="Exit_function">
 		<title>Exit function</title>
 		<para>
 			The exit function is only neccecary if the driver is
 			compiled as a module. It releases all resources which
 			are held by the chip driver and unregisters the partitions
 			in the MTD layer.
 		</para>
 		<programlisting>
 #ifdef MODULE
 static void __exit board_cleanup (void)
 {
 	/* Release resources, unregister device */
 	nand_release (board_mtd);
 	/* unmap physical address */
 	iounmap((void *)baseaddr);
 	/* Free the MTD device structure */
 	kfree (board_mtd);
 }
 module_exit(board_cleanup);
 #endif
 		</programlisting>
 	</sect1>
  </chapter>
  <chapter id="boarddriversadvanced">
     	<title>Advanced board driver functions</title>
 	<para>
 		This chapter describes the advanced functionality of the NAND
 		driver. For a list of functions which can be overridden by the board
 		driver see the documentation of the nand_chip structure.
 	</para>
 	<sect1 id="Multiple_chip_control">
 		<title>Multiple chip control</title>
 		<para>
 			The nand driver can control chip arrays. Therefor the
 			board driver must provide an own select_chip function. This
 			function must (de)select the requested chip.
 			The function pointer in the nand_chip structure must
 			be set before calling nand_scan(). The maxchip parameter
 			of nand_scan() defines the maximum number of chips to
 			scan for. Make sure that the select_chip function can
 			handle the requested number of chips.
 		</para>
 		<para>
 			The nand driver concatenates the chips to one virtual
 			chip and provides this virtual chip to the MTD layer.
 		</para>
 		<para>
 			<emphasis>Note: The driver can only handle linear chip arrays
 			of equally sized chips. There is no support for
 			parallel arrays which extend the buswidth.</emphasis>
 		</para>
 		<para>
 			<emphasis>GPIO based example</emphasis>
 		</para>
 		<programlisting>
 static void board_select_chip (struct mtd_info *mtd, int chip)
 {
 	/* Deselect all chips, set all nCE pins high */
 	GPIO(BOARD_NAND_NCE) |= 0xff;	
 	if (chip >= 0)
 		GPIO(BOARD_NAND_NCE) &amp;= ~ (1 &lt;&lt; chip);
 }
 		</programlisting>
 		<para>
 			<emphasis>Address lines based example.</emphasis>
 			Its assumed that the nCE pins are connected to an
 			address decoder.
 		</para>
 		<programlisting>
 static void board_select_chip (struct mtd_info *mtd, int chip)
 {
 	struct nand_chip *this = (struct nand_chip *) mtd->priv;
 	/* Deselect all chips */
 	this->IO_ADDR_R &amp;= ~BOARD_NAND_ADDR_MASK;
 	this->IO_ADDR_W &amp;= ~BOARD_NAND_ADDR_MASK;
 	switch (chip) {
 	case 0:
 		this->IO_ADDR_R |= BOARD_NAND_ADDR_CHIP0;
 		this->IO_ADDR_W |= BOARD_NAND_ADDR_CHIP0;
 		break;
 	....	
 	case n:
 		this->IO_ADDR_R |= BOARD_NAND_ADDR_CHIPn;
 		this->IO_ADDR_W |= BOARD_NAND_ADDR_CHIPn;
 		break;
 	}	
 }
 		</programlisting>
 	</sect1>
 	<sect1 id="Hardware_ECC_support">
 		<title>Hardware ECC support</title>
 		<sect2 id="Functions_and_constants">
 			<title>Functions and constants</title>
 			<para>
 				The nand driver supports three different types of
 				hardware ECC.
 				<itemizedlist>
 				<listitem><para>NAND_ECC_HW3_256</para><para>
 				Hardware ECC generator providing 3 bytes ECC per
 				256 byte.
 				</para>	</listitem>
 				<listitem><para>NAND_ECC_HW3_512</para><para>
 				Hardware ECC generator providing 3 bytes ECC per
 				512 byte.
 				</para>	</listitem>
 				<listitem><para>NAND_ECC_HW6_512</para><para>
 				Hardware ECC generator providing 6 bytes ECC per
 				512 byte.
 				</para>	</listitem>
 				<listitem><para>NAND_ECC_HW8_512</para><para>
 				Hardware ECC generator providing 6 bytes ECC per
 				512 byte.
 				</para>	</listitem>
 				</itemizedlist>
 				If your hardware generator has a different functionality
 				add it at the appropriate place in nand_base.c
 			</para>
 			<para>
 				The board driver must provide following functions:
 				<itemizedlist>
 				<listitem><para>enable_hwecc</para><para>
 				This function is called before reading / writing to
 				the chip. Reset or initialize the hardware generator
 				in this function. The function is called with an
 				argument which let you distinguish between read 
 				and write operations.
 				</para>	</listitem>
 				<listitem><para>calculate_ecc</para><para>
 				This function is called after read / write from / to
 				the chip. Transfer the ECC from the hardware to
 				the buffer. If the option NAND_HWECC_SYNDROME is set
 				then the function is only called on write. See below.
 				</para>	</listitem>
 				<listitem><para>correct_data</para><para>
 				In case of an ECC error this function is called for
 				error detection and correction. Return 1 respectively 2
 				in case the error can be corrected. If the error is
 				not correctable return -1. If your hardware generator
 				matches the default algorithm of the nand_ecc software
 				generator then use the correction function provided
 				by nand_ecc instead of implementing duplicated code.
 				</para>	</listitem>
 				</itemizedlist>
 			</para>
 		</sect2>
 		<sect2 id="Hardware_ECC_with_syndrome_calculation">
 		<title>Hardware ECC with syndrome calculation</title>
 			<para>
 				Many hardware ECC implementations provide Reed-Solomon
 				codes and calculate an error syndrome on read. The syndrome
 				must be converted to a standard Reed-Solomon syndrome
 				before calling the error correction code in the generic
 				Reed-Solomon library.
 			</para>
 			<para>
 				The ECC bytes must be placed immidiately after the data
 				bytes in order to make the syndrome generator work. This
 				is contrary to the usual layout used by software ECC. The
 				seperation of data and out of band area is not longer
 				possible. The nand driver code handles this layout and
 				the remaining free bytes in the oob area are managed by 
 				the autoplacement code. Provide a matching oob-layout
 				in this case. See rts_from4.c and diskonchip.c for 
 				implementation reference. In those cases we must also
 				use bad block tables on FLASH, because the ECC layout is
 				interferring with the bad block marker positions.
 				See bad block table support for details.
 			</para>
 		</sect2>
 	</sect1>
 	<sect1 id="Bad_Block_table_support">
 		<title>Bad block table support</title>
 		<para>
 			Most NAND chips mark the bad blocks at a defined
 			position in the spare area. Those blocks must 
 			not be erased under any circumstances as the bad 
 			block information would be lost.
 			It is possible to check the bad block mark each
 			time when the blocks are accessed by reading the
 			spare area of the first page in the block. This
 			is time consuming so a bad block table is used.
 		</para>
 		<para>
 			The nand driver supports various types of bad block
 			tables.
 			<itemizedlist>
 			<listitem><para>Per device</para><para>
 			The bad block table contains all bad block information
 			of the device which can consist of multiple chips.
 			</para>	</listitem>
 			<listitem><para>Per chip</para><para>
 			A bad block table is used per chip and contains the
 			bad block information for this particular chip.
 			</para>	</listitem>
 			<listitem><para>Fixed offset</para><para>
 			The bad block table is located at a fixed offset
 			in the chip (device). This applies to various
 			DiskOnChip devices.
 			</para>	</listitem>
 			<listitem><para>Automatic placed</para><para>
 			The bad block table is automatically placed and
 			detected either at the end or at the beginning
 			of a chip (device)
 			</para>	</listitem>
 			<listitem><para>Mirrored tables</para><para>
 			The bad block table is mirrored on the chip (device) to
 			allow updates of the bad block table without data loss.
 			</para>	</listitem>
 			</itemizedlist>
 		</para>
 		<para>	
 			nand_scan() calls the function nand_default_bbt(). 
 			nand_default_bbt() selects appropriate default
 			bad block table desriptors depending on the chip information
 			which was retrieved by nand_scan().
 		</para>
 		<para>
 			The standard policy is scanning the device for bad 
 			blocks and build a ram based bad block table which
 			allows faster access than always checking the
 			bad block information on the flash chip itself.
 		</para>
 		<sect2 id="Flash_based_tables">
 			<title>Flash based tables</title>
 			<para>
 				It may be desired or neccecary to keep a bad block table in FLASH. 
 				For AG-AND chips this is mandatory, as they have no factory marked
 				bad blocks. They have factory marked good blocks. The marker pattern
 				is erased when the block is erased to be reused. So in case of
 				powerloss before writing the pattern back to the chip this block 
 				would be lost and added to the bad blocks. Therefor we scan the 
 				chip(s) when we detect them the first time for good blocks and 
 				store this information in a bad block table before erasing any 
 				of the blocks.
 			</para>
 			<para>
 				The blocks in which the tables are stored are procteted against
 				accidental access by marking them bad in the memory bad block
-				table. The bad block table managment functions are allowed
+				table. The bad block table management functions are allowed
 				to circumvernt this protection.
 			</para>
 			<para>
 				The simplest way to activate the FLASH based bad block table support 
 				is to set the option NAND_USE_FLASH_BBT in the option field of
 				the nand chip structure before calling nand_scan(). For AG-AND
 				chips is this done by default.
 				This activates the default FLASH based bad block table functionality 
 				of the NAND driver. The default bad block table options are
 				<itemizedlist>
 				<listitem><para>Store bad block table per chip</para></listitem>
 				<listitem><para>Use 2 bits per block</para></listitem>
 				<listitem><para>Automatic placement at the end of the chip</para></listitem>
 				<listitem><para>Use mirrored tables with version numbers</para></listitem>
 				<listitem><para>Reserve 4 blocks at the end of the chip</para></listitem>
 				</itemizedlist>
 			</para>
 		</sect2>
 		<sect2 id="User_defined_tables">
 			<title>User defined tables</title>
 			<para>
 				User defined tables are created by filling out a 
 				nand_bbt_descr structure and storing the pointer in the
 				nand_chip structure member bbt_td before calling nand_scan(). 
 				If a mirror table is neccecary a second structure must be
 				created and a pointer to this structure must be stored
 				in bbt_md inside the nand_chip structure. If the bbt_md 
 				member is set to NULL then only the main table is used
 				and no scan for the mirrored table is performed.
 			</para>
 			<para>
 				The most important field in the nand_bbt_descr structure
 				is the options field. The options define most of the 
 				table properties. Use the predefined constants from
 				nand.h to define the options.
 				<itemizedlist>
 				<listitem><para>Number of bits per block</para>
 				<para>The supported number of bits is 1, 2, 4, 8.</para></listitem>
 				<listitem><para>Table per chip</para>
 				<para>Setting the constant NAND_BBT_PERCHIP selects that
 				a bad block table is managed for each chip in a chip array.
 				If this option is not set then a per device bad block table
 				is used.</para></listitem>
 				<listitem><para>Table location is absolute</para>
 				<para>Use the option constant NAND_BBT_ABSPAGE and
 				define the absolute page number where the bad block
 				table starts in the field pages. If you have selected bad block
 				tables per chip and you have a multi chip array then the start page
 				must be given for each chip in the chip array. Note: there is no scan
 				for a table ident pattern performed, so the fields 
 				pattern, veroffs, offs, len can be left uninitialized</para></listitem>
 				<listitem><para>Table location is automatically detected</para>
 				<para>The table can either be located in the first or the last good
 				blocks of the chip (device). Set NAND_BBT_LASTBLOCK to place
 				the bad block table at the end of the chip (device). The
 				bad block tables are marked and identified by a pattern which
 				is stored in the spare area of the first page in the block which
 				holds the bad block table. Store a pointer to the pattern  
 				in the pattern field. Further the length of the pattern has to be 
 				stored in len and the offset in the spare area must be given
 				in the offs member of the nand_bbt_descr stucture. For mirrored
 				bad block tables different patterns are mandatory.</para></listitem>
 				<listitem><para>Table creation</para>
 				<para>Set the option NAND_BBT_CREATE to enable the table creation
 				if no table can be found during the scan. Usually this is done only 
 				once if a new chip is found. </para></listitem>
 				<listitem><para>Table write support</para>
 				<para>Set the option NAND_BBT_WRITE to enable the table write support.
 				This allows the update of the bad block table(s) in case a block has
 				to be marked bad due to wear. The MTD interface function block_markbad
 				is calling the update function of the bad block table. If the write
 				support is enabled then the table is updated on FLASH.</para>
 				<para>
 				Note: Write support should only be enabled for mirrored tables with
 				version control.
 				</para></listitem>
 				<listitem><para>Table version control</para>
 				<para>Set the option NAND_BBT_VERSION to enable the table version control.
 				It's highly recommended to enable this for mirrored tables with write
 				support. It makes sure that the risk of loosing the bad block
 				table information is reduced to the loss of the information about the
 				one worn out block which should be marked bad. The version is stored in
 				4 consecutive bytes in the spare area of the device. The position of
 				the version number is defined by the member veroffs in the bad block table
 				descriptor.</para></listitem>
 				<listitem><para>Save block contents on write</para>
 				<para>
 				In case that the block which holds the bad block table does contain
 				other useful information, set the option NAND_BBT_SAVECONTENT. When
 				the bad block table is written then the whole block is read the bad
 				block table is updated and the block is erased and everything is 
 				written back. If this option is not set only the bad block table
 				is written and everything else in the block is ignored and erased.
 				</para></listitem>
 				<listitem><para>Number of reserved blocks</para>
 				<para>
 				For automatic placement some blocks must be reserved for
 				bad block table storage. The number of reserved blocks is defined 
 				in the maxblocks member of the babd block table description structure.
 				Reserving 4 blocks for mirrored tables should be a reasonable number. 
 				This also limits the number of blocks which are scanned for the bad
 				block table ident pattern.
 				</para></listitem>
 				</itemizedlist>
 			</para>
 		</sect2>
 	</sect1>
 	<sect1 id="Spare_area_placement">
 		<title>Spare area (auto)placement</title>
 		<para>
 			The nand driver implements different possibilities for
 			placement of filesystem data in the spare area, 
 			<itemizedlist>
 			<listitem><para>Placement defined by fs driver</para></listitem>
 			<listitem><para>Automatic placement</para></listitem>
 			</itemizedlist>
 			The default placement function is automatic placement. The
 			nand driver has built in default placement schemes for the
 			various chiptypes. If due to hardware ECC functionality the
 			default placement does not fit then the board driver can
 			provide a own placement scheme.
 		</para>
 		<para>
 			File system drivers can provide a own placement scheme which
 			is used instead of the default placement scheme.
 		</para>
 		<para>
 			Placement schemes are defined by a nand_oobinfo structure
 	     		<programlisting>
 struct nand_oobinfo {
 	int	useecc;
 	int	eccbytes;
 	int	eccpos[24];
 	int	oobfree[8][2];
 };
 	     		</programlisting>
 			<itemizedlist>
 			<listitem><para>useecc</para><para>
 				The useecc member controls the ecc and placement function. The header
 				file include/mtd/mtd-abi.h contains constants to select ecc and
 				placement. MTD_NANDECC_OFF switches off the ecc complete. This is
 				not recommended and available for testing and diagnosis only.
 				MTD_NANDECC_PLACE selects caller defined placement, MTD_NANDECC_AUTOPLACE
 				selects automatic placement.
 			</para></listitem>
 			<listitem><para>eccbytes</para><para>
 				The eccbytes member defines the number of ecc bytes per page.
 			</para></listitem>
 			<listitem><para>eccpos</para><para>
 				The eccpos array holds the byte offsets in the spare area where
 				the ecc codes are placed.
 			</para></listitem>
 			<listitem><para>oobfree</para><para>
 				The oobfree array defines the areas in the spare area which can be
 				used for automatic placement. The information is given in the format
 				{offset, size}. offset defines the start of the usable area, size the
 				length in bytes. More than one area can be defined. The list is terminated
 				by an {0, 0} entry.
 			</para></listitem>
 			</itemizedlist>
 		</para>
 		<sect2 id="Placement_defined_by_fs_driver">
 			<title>Placement defined by fs driver</title>
 			<para>
 				The calling function provides a pointer to a nand_oobinfo
 				structure which defines the ecc placement. For writes the
 				caller must provide a spare area buffer along with the
 				data buffer. The spare area buffer size is (number of pages) *
 				(size of spare area). For reads the buffer size is
 				(number of pages) * ((size of spare area) + (number of ecc
 				steps per page) * sizeof (int)). The driver stores the
 				result of the ecc check for each tuple in the spare buffer.
 				The storage sequence is 
 			</para>
 			<para>
 				&lt;spare data page 0&gt;&lt;ecc result 0&gt;...&lt;ecc result n&gt;
 			</para>
 			<para>
 				...
 			</para>
 			<para>
 				&lt;spare data page n&gt;&lt;ecc result 0&gt;...&lt;ecc result n&gt;
 			</para>
 			<para>
 				This is a legacy mode used by YAFFS1.
 			</para>
 			<para>
 				If the spare area buffer is NULL then only the ECC placement is
 				done according to the given scheme in the nand_oobinfo structure.
 			</para>
 		</sect2>
 		<sect2 id="Automatic_placement">
 			<title>Automatic placement</title>
 			<para>
 				Automatic placement uses the built in defaults to place the
 				ecc bytes in the spare area. If filesystem data have to be stored /
 				read into the spare area then the calling function must provide a
 				buffer. The buffer size per page is determined by the oobfree array in
 				the nand_oobinfo structure.
 			</para>
 			<para>
 				If the spare area buffer is NULL then only the ECC placement is
 				done according to the default builtin scheme.
 			</para>
 		</sect2>
 		<sect2 id="User_space_placement_selection">
 			<title>User space placement selection</title>
 		<para>
 			All non ecc functions like mtd->read and mtd->write use an internal 
 			structure, which can be set by an ioctl. This structure is preset 
 			to the autoplacement default.
 	     		<programlisting>
 	ioctl (fd, MEMSETOOBSEL, oobsel);
 	     		</programlisting>
 			oobsel is a pointer to a user supplied structure of type
 			nand_oobconfig. The contents of this structure must match the 
 			criteria of the filesystem, which will be used. See an example in utils/nandwrite.c.
 		</para>
 		</sect2>
 	</sect1>	
 	<sect1 id="Spare_area_autoplacement_default">
 		<title>Spare area autoplacement default schemes</title>
 		<sect2 id="pagesize_256">
 			<title>256 byte pagesize</title>
 <informaltable><tgroup cols="3"><tbody>
 <row>
 <entry>Offset</entry>
 <entry>Content</entry>
 <entry>Comment</entry>
 </row>
 <row>
 <entry>0x00</entry>
 <entry>ECC byte 0</entry>
 <entry>Error correction code byte 0</entry>
 </row>
 <row>
 <entry>0x01</entry>
 <entry>ECC byte 1</entry>
 <entry>Error correction code byte 1</entry>
 </row>
 <row>
 <entry>0x02</entry>
 <entry>ECC byte 2</entry>
 <entry>Error correction code byte 2</entry>
 </row>
 <row>
 <entry>0x03</entry>
 <entry>Autoplace 0</entry>
 <entry></entry>
 </row>
 <row>
 <entry>0x04</entry>
 <entry>Autoplace 1</entry>
 <entry></entry>
 </row>
 <row>
 <entry>0x05</entry>
 <entry>Bad block marker</entry>
 <entry>If any bit in this byte is zero, then this block is bad.
 This applies only to the first page in a block. In the remaining
 pages this byte is reserved</entry>
 </row>
 <row>
 <entry>0x06</entry>
 <entry>Autoplace 2</entry>
 <entry></entry>
 </row>
 <row>
 <entry>0x07</entry>
 <entry>Autoplace 3</entry>
 <entry></entry>
 </row>
 </tbody></tgroup></informaltable>
 		</sect2>
 		<sect2 id="pagesize_512">
 			<title>512 byte pagesize</title>
 <informaltable><tgroup cols="3"><tbody>
 <row>
 <entry>Offset</entry>
 <entry>Content</entry>
 <entry>Comment</entry>
 </row>
 <row>
 <entry>0x00</entry>
 <entry>ECC byte 0</entry>
 <entry>Error correction code byte 0 of the lower 256 Byte data in
 this page</entry>
 </row>
 <row>
 <entry>0x01</entry>
 <entry>ECC byte 1</entry>
 <entry>Error correction code byte 1 of the lower 256 Bytes of data
 in this page</entry>
 </row>
 <row>
 <entry>0x02</entry>
 <entry>ECC byte 2</entry>
 <entry>Error correction code byte 2 of the lower 256 Bytes of data
 in this page</entry>
 </row>
 <row>
 <entry>0x03</entry>
 <entry>ECC byte 3</entry>
 <entry>Error correction code byte 0 of the upper 256 Bytes of data
 in this page</entry>
 </row>
 <row>
 <entry>0x04</entry>
 <entry>reserved</entry>
 <entry>reserved</entry>
 </row>
 <row>
 <entry>0x05</entry>
 <entry>Bad block marker</entry>
 <entry>If any bit in this byte is zero, then this block is bad.
 This applies only to the first page in a block. In the remaining
 pages this byte is reserved</entry>
 </row>
 <row>
 <entry>0x06</entry>
 <entry>ECC byte 4</entry>
 <entry>Error correction code byte 1 of the upper 256 Bytes of data
 in this page</entry>
 </row>
 <row>
 <entry>0x07</entry>
 <entry>ECC byte 5</entry>
 <entry>Error correction code byte 2 of the upper 256 Bytes of data
 in this page</entry>
 </row>
 <row>
 <entry>0x08 - 0x0F</entry>
 <entry>Autoplace 0 - 7</entry>
 <entry></entry>
 </row>
 </tbody></tgroup></informaltable>
 		</sect2>
 		<sect2 id="pagesize_2048">
 			<title>2048 byte pagesize</title>
 <informaltable><tgroup cols="3"><tbody>
 <row>
 <entry>Offset</entry>
 <entry>Content</entry>
 <entry>Comment</entry>
 </row>
 <row>
 <entry>0x00</entry>
 <entry>Bad block marker</entry>
 <entry>If any bit in this byte is zero, then this block is bad.
 This applies only to the first page in a block. In the remaining
 pages this byte is reserved</entry>
 </row>
 <row>
 <entry>0x01</entry>
 <entry>Reserved</entry>
 <entry>Reserved</entry>
 </row>
 <row>
 <entry>0x02-0x27</entry>
 <entry>Autoplace 0 - 37</entry>
 <entry></entry>
 </row>
 <row>
 <entry>0x28</entry>
 <entry>ECC byte 0</entry>
 <entry>Error correction code byte 0 of the first 256 Byte data in
 this page</entry>
 </row>
 <row>
 <entry>0x29</entry>
 <entry>ECC byte 1</entry>
 <entry>Error correction code byte 1 of the first 256 Bytes of data
 in this page</entry>
 </row>
 <row>
 <entry>0x2A</entry>
 <entry>ECC byte 2</entry>
 <entry>Error correction code byte 2 of the first 256 Bytes data in
 this page</entry>
 </row>
 <row>
 <entry>0x2B</entry>
 <entry>ECC byte 3</entry>
 <entry>Error correction code byte 0 of the second 256 Bytes of data
 in this page</entry>
 </row>
 <row>
 <entry>0x2C</entry>
 <entry>ECC byte 4</entry>
 <entry>Error correction code byte 1 of the second 256 Bytes of data
 in this page</entry>
 </row>
 <row>
 <entry>0x2D</entry>
 <entry>ECC byte 5</entry>
 <entry>Error correction code byte 2 of the second 256 Bytes of data
 in this page</entry>
 </row>
 <row>
 <entry>0x2E</entry>
 <entry>ECC byte 6</entry>
 <entry>Error correction code byte 0 of the third 256 Bytes of data
 in this page</entry>
 </row>
 <row>
 <entry>0x2F</entry>
 <entry>ECC byte 7</entry>
 <entry>Error correction code byte 1 of the third 256 Bytes of data
 in this page</entry>
 </row>
 <row>
 <entry>0x30</entry>
 <entry>ECC byte 8</entry>
 <entry>Error correction code byte 2 of the third 256 Bytes of data
 in this page</entry>
 </row>
 <row>
 <entry>0x31</entry>
 <entry>ECC byte 9</entry>
 <entry>Error correction code byte 0 of the fourth 256 Bytes of data
 in this page</entry>
 </row>
 <row>
 <entry>0x32</entry>
 <entry>ECC byte 10</entry>
 <entry>Error correction code byte 1 of the fourth 256 Bytes of data
 in this page</entry>
 </row>
 <row>
 <entry>0x33</entry>
 <entry>ECC byte 11</entry>
 <entry>Error correction code byte 2 of the fourth 256 Bytes of data
 in this page</entry>
 </row>
 <row>
 <entry>0x34</entry>
 <entry>ECC byte 12</entry>
 <entry>Error correction code byte 0 of the fifth 256 Bytes of data
 in this page</entry>
 </row>
 <row>
 <entry>0x35</entry>
 <entry>ECC byte 13</entry>
 <entry>Error correction code byte 1 of the fifth 256 Bytes of data
 in this page</entry>
 </row>
 <row>
 <entry>0x36</entry>
 <entry>ECC byte 14</entry>
 <entry>Error correction code byte 2 of the fifth 256 Bytes of data
 in this page</entry>
 </row>
 <row>
 <entry>0x37</entry>
 <entry>ECC byte 15</entry>
 <entry>Error correction code byte 0 of the sixt 256 Bytes of data
 in this page</entry>
 </row>
 <row>
 <entry>0x38</entry>
 <entry>ECC byte 16</entry>
 <entry>Error correction code byte 1 of the sixt 256 Bytes of data
 in this page</entry>
 </row>
 <row>
 <entry>0x39</entry>
 <entry>ECC byte 17</entry>
 <entry>Error correction code byte 2 of the sixt 256 Bytes of data
 in this page</entry>
 </row>
 <row>
 <entry>0x3A</entry>
 <entry>ECC byte 18</entry>
 <entry>Error correction code byte 0 of the seventh 256 Bytes of
 data in this page</entry>
 </row>
 <row>
 <entry>0x3B</entry>
 <entry>ECC byte 19</entry>
 <entry>Error correction code byte 1 of the seventh 256 Bytes of
 data in this page</entry>
 </row>
 <row>
 <entry>0x3C</entry>
 <entry>ECC byte 20</entry>
 <entry>Error correction code byte 2 of the seventh 256 Bytes of
 data in this page</entry>
 </row>
 <row>
 <entry>0x3D</entry>
 <entry>ECC byte 21</entry>
 <entry>Error correction code byte 0 of the eigth 256 Bytes of data
 in this page</entry>
 </row>
 <row>
 <entry>0x3E</entry>
 <entry>ECC byte 22</entry>
 <entry>Error correction code byte 1 of the eigth 256 Bytes of data
 in this page</entry>
 </row>
 <row>
 <entry>0x3F</entry>
 <entry>ECC byte 23</entry>
 <entry>Error correction code byte 2 of the eigth 256 Bytes of data
 in this page</entry>
 </row>
 </tbody></tgroup></informaltable>
 		</sect2>
     	</sect1>
  </chapter>
  <chapter id="filesystems">
     	<title>Filesystem support</title>
 	<para>
 		The NAND driver provides all neccecary functions for a
 		filesystem via the MTD interface.
 	</para>
 	<para>
 		Filesystems must be aware of the NAND pecularities and
 		restrictions. One major restrictions of NAND Flash is, that you cannot 
 		write as often as you want to a page. The consecutive writes to a page, 
 		before erasing it again, are restricted to 1-3 writes, depending on the 
 		manufacturers specifications. This applies similar to the spare area. 
 	</para>
 	<para>
 		Therefor NAND aware filesystems must either write in page size chunks
 		or hold a writebuffer to collect smaller writes until they sum up to 
 		pagesize. Available NAND aware filesystems: JFFS2, YAFFS. 		
 	</para>
 	<para>
 		The spare area usage to store filesystem data is controlled by
 		the spare area placement functionality which is described in one
 		of the earlier chapters.
 	</para>
  </chapter>	
  <chapter id="tools">
     	<title>Tools</title>
 	<para>
 		The MTD project provides a couple of helpful tools to handle NAND Flash.
 		<itemizedlist>
 		<listitem><para>flasherase, flasheraseall: Erase and format FLASH partitions</para></listitem>
 		<listitem><para>nandwrite: write filesystem images to NAND FLASH</para></listitem>
 		<listitem><para>nanddump: dump the contents of a NAND FLASH partitions</para></listitem>
 		</itemizedlist>
 	</para>
 	<para>
 		These tools are aware of the NAND restrictions. Please use those tools
 		instead of complaining about errors which are caused by non NAND aware
 		access methods.
 	</para>
  </chapter>	
  <chapter id="defines">
     <title>Constants</title>
     <para>
     This chapter describes the constants which might be relevant for a driver developer.
     </para>
     <sect1 id="Chip_option_constants">
 	<title>Chip option constants</title>
     	<sect2 id="Constants_for_chip_id_table">
 		<title>Constants for chip id table</title>
     		<para>
 		These constants are defined in nand.h. They are ored together to describe
 		the chip functionality.
     		<programlisting>
 /* Chip can not auto increment pages */
 #define NAND_NO_AUTOINCR	0x00000001
 /* Buswitdh is 16 bit */
 #define NAND_BUSWIDTH_16	0x00000002
 /* Device supports partial programming without padding */
 #define NAND_NO_PADDING		0x00000004
 /* Chip has cache program function */
 #define NAND_CACHEPRG		0x00000008
 /* Chip has copy back function */
 #define NAND_COPYBACK		0x00000010
 /* AND Chip which has 4 banks and a confusing page / block 
 * assignment. See Renesas datasheet for further information */
 #define NAND_IS_AND		0x00000020
 /* Chip has a array of 4 pages which can be read without
 * additional ready /busy waits */
 #define NAND_4PAGE_ARRAY	0x00000040 
 		</programlisting>
     		</para>
     	</sect2>
     	<sect2 id="Constants_for_runtime_options">
 		<title>Constants for runtime options</title>
     		<para>
 		These constants are defined in nand.h. They are ored together to describe
 		the functionality.
     		<programlisting>
 /* Use a flash based bad block table. This option is parsed by the
 * default bad block table function (nand_default_bbt). */
 #define NAND_USE_FLASH_BBT	0x00010000
 /* The hw ecc generator provides a syndrome instead a ecc value on read 
 * This can only work if we have the ecc bytes directly behind the 
 * data bytes. Applies for DOC and AG-AND Renesas HW Reed Solomon generators */
 #define NAND_HWECC_SYNDROME	0x00020000
 		</programlisting>
     		</para>
     	</sect2>
     </sect1>	
     <sect1 id="EEC_selection_constants">
 	<title>ECC selection constants</title>
 	<para>
 	Use these constants to select the ECC algorithm.
  	<programlisting>
 /* No ECC. Usage is not recommended ! */
 #define NAND_ECC_NONE		0
 /* Software ECC 3 byte ECC per 256 Byte data */
 #define NAND_ECC_SOFT		1
 /* Hardware ECC 3 byte ECC per 256 Byte data */
 #define NAND_ECC_HW3_256	2
 /* Hardware ECC 3 byte ECC per 512 Byte data */
 #define NAND_ECC_HW3_512	3
 /* Hardware ECC 6 byte ECC per 512 Byte data */
 #define NAND_ECC_HW6_512	4
 /* Hardware ECC 6 byte ECC per 512 Byte data */
 #define NAND_ECC_HW8_512	6
 	</programlisting>
 	</para>
     </sect1>	
     <sect1 id="Hardware_control_related_constants">
 	<title>Hardware control related constants</title>
 	<para>
 	These constants describe the requested hardware access function when
 	the boardspecific hardware control function is called
  	<programlisting>
 /* Select the chip by setting nCE to low */
 #define NAND_CTL_SETNCE 	1
 /* Deselect the chip by setting nCE to high */
 #define NAND_CTL_CLRNCE		2
 /* Select the command latch by setting CLE to high */
 #define NAND_CTL_SETCLE		3
 /* Deselect the command latch by setting CLE to low */
 #define NAND_CTL_CLRCLE		4
 /* Select the address latch by setting ALE to high */
 #define NAND_CTL_SETALE		5
 /* Deselect the address latch by setting ALE to low */
 #define NAND_CTL_CLRALE		6
 /* Set write protection by setting WP to high. Not used! */
 #define NAND_CTL_SETWP		7
 /* Clear write protection by setting WP to low. Not used! */
 #define NAND_CTL_CLRWP		8
 	</programlisting>
 	</para>
     </sect1>	
     <sect1 id="Bad_block_table_constants">
 	<title>Bad block table related constants</title>
 	<para>
 	These constants describe the options used for bad block
 	table descriptors.
  	<programlisting>
 /* Options for the bad block table descriptors */
 /* The number of bits used per block in the bbt on the device */
 #define NAND_BBT_NRBITS_MSK	0x0000000F
 #define NAND_BBT_1BIT		0x00000001
 #define NAND_BBT_2BIT		0x00000002
 #define NAND_BBT_4BIT		0x00000004
 #define NAND_BBT_8BIT		0x00000008
 /* The bad block table is in the last good block of the device */
 #define	NAND_BBT_LASTBLOCK	0x00000010
 /* The bbt is at the given page, else we must scan for the bbt */
 #define NAND_BBT_ABSPAGE	0x00000020
 /* The bbt is at the given page, else we must scan for the bbt */
 #define NAND_BBT_SEARCH		0x00000040
 /* bbt is stored per chip on multichip devices */
 #define NAND_BBT_PERCHIP	0x00000080
 /* bbt has a version counter at offset veroffs */
 #define NAND_BBT_VERSION	0x00000100
 /* Create a bbt if none axists */
 #define NAND_BBT_CREATE		0x00000200
 /* Search good / bad pattern through all pages of a block */
 #define NAND_BBT_SCANALLPAGES	0x00000400
 /* Scan block empty during good / bad block scan */
 #define NAND_BBT_SCANEMPTY	0x00000800
 /* Write bbt if neccecary */
 #define NAND_BBT_WRITE		0x00001000
 /* Read and write back block contents when writing bbt */
 #define NAND_BBT_SAVECONTENT	0x00002000
 	</programlisting>
 	</para>
     </sect1>	
  </chapter>
  <chapter id="structs">
     <title>Structures</title>
     <para>
     This chapter contains the autogenerated documentation of the structures which are
     used in the NAND driver and might be relevant for a driver developer. Each  
     struct member has a short description which is marked with an [XXX] identifier.
     See the chapter "Documentation hints" for an explanation.
     </para>
 !Iinclude/linux/mtd/nand.h
  </chapter>
  <chapter id="pubfunctions">
     <title>Public Functions Provided</title>
     <para>
     This chapter contains the autogenerated documentation of the NAND kernel API functions
      which are exported. Each function has a short description which is marked with an [XXX] identifier.
     See the chapter "Documentation hints" for an explanation.
     </para>
 !Edrivers/mtd/nand/nand_base.c
 !Edrivers/mtd/nand/nand_bbt.c
 !Edrivers/mtd/nand/nand_ecc.c
  </chapter>
  <chapter id="intfunctions">
     <title>Internal Functions Provided</title>
     <para>
     This chapter contains the autogenerated documentation of the NAND driver internal functions.
     Each function has a short description which is marked with an [XXX] identifier.
     See the chapter "Documentation hints" for an explanation.
     The functions marked with [DEFAULT] might be relevant for a board driver developer.
     </para>
 !Idrivers/mtd/nand/nand_base.c
 !Idrivers/mtd/nand/nand_bbt.c
 <!-- No internal functions for kernel-doc:
 X!Idrivers/mtd/nand/nand_ecc.c
 -->
  </chapter>
  <chapter id="credits">
     <title>Credits</title>
 	<para>
 		The following people have contributed to the NAND driver:
 		<orderedlist>
 			<listitem><para>Steven J. Hill<email>sjhill@realitydiluted.com</email></para></listitem>
 			<listitem><para>David Woodhouse<email>dwmw2@infradead.org</email></para></listitem>
 			<listitem><para>Thomas Gleixner<email>tglx@linutronix.de</email></para></listitem>
 		</orderedlist>
 		A lot of users have provided bugfixes, improvements and helping hands for testing.
 		Thanks a lot.
 	</para>
 	<para>
 		The following people have contributed to this document:
 		<orderedlist>
 			<listitem><para>Thomas Gleixner<email>tglx@linutronix.de</email></para></listitem>
 		</orderedlist>
 	</para>
  </chapter>
 </book>
 <?xml version="1.0" encoding="UTF-8"?>
 <!DOCTYPE book PUBLIC "-//OASIS//DTD DocBook XML V4.1.2//EN"
 	"http://www.oasis-open.org/docbook/xml/4.1.2/docbookx.dtd" []>
 <book id="scsimid">
  <bookinfo>
    <title>SCSI Interfaces Guide</title>
    <authorgroup>
      <author>
        <firstname>James</firstname>
        <surname>Bottomley</surname>
        <affiliation>
          <address>
            <email>James.Bottomley@hansenpartnership.com</email>
          </address>
        </affiliation>
      </author>
      <author>
        <firstname>Rob</firstname>
        <surname>Landley</surname>
        <affiliation>
          <address>
            <email>rob@landley.net</email>
          </address>
        </affiliation>
      </author>
    </authorgroup>
    <copyright>
      <year>2007</year>
      <holder>Linux Foundation</holder>
    </copyright>
    <legalnotice>
      <para>
        This documentation is free software; you can redistribute
        it and/or modify it under the terms of the GNU General Public
        License version 2.
      </para>
      <para>
        This program is distributed in the hope that it will be
        useful, but WITHOUT ANY WARRANTY; without even the implied
        warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
        For more details see the file COPYING in the source
        distribution of Linux.
      </para>
    </legalnotice>
  </bookinfo>
  <toc></toc>
  <chapter id="intro">
    <title>Introduction</title>
    <sect1 id="protocol_vs_bus">
      <title>Protocol vs bus</title>
      <para>
        Once upon a time, the Small Computer Systems Interface defined both
        a parallel I/O bus and a data protocol to connect a wide variety of
        peripherals (disk drives, tape drives, modems, printers, scanners,
        optical drives, test equipment, and medical devices) to a host
        computer.
      </para>
      <para>
        Although the old parallel (fast/wide/ultra) SCSI bus has largely
        fallen out of use, the SCSI command set is more widely used than ever
        to communicate with devices over a number of different busses.
      </para>
      <para>
        The <ulink url='http://www.t10.org/scsi-3.htm'>SCSI protocol</ulink>
        is a big-endian peer-to-peer packet based protocol.  SCSI commands
        are 6, 10, 12, or 16 bytes long, often followed by an associated data
        payload.
      </para>
      <para>
        SCSI commands can be transported over just about any kind of bus, and
        are the default protocol for storage devices attached to USB, SATA,
        SAS, Fibre Channel, FireWire, and ATAPI devices.  SCSI packets are
        also commonly exchanged over Infiniband,
        <ulink url='http://i2o.shadowconnect.com/faq.php'>I20</ulink>, TCP/IP
        (<ulink url='http://en.wikipedia.org/wiki/ISCSI'>iSCSI</ulink>), even
        <ulink url='http://cyberelk.net/tim/parport/parscsi.html'>Parallel
        ports</ulink>.
      </para>
    </sect1>
    <sect1 id="subsystem_design">
      <title>Design of the Linux SCSI subsystem</title>
      <para>
        The SCSI subsystem uses a three layer design, with upper, mid, and low
        layers.  Every operation involving the SCSI subsystem (such as reading
        a sector from a disk) uses one driver at each of the 3 levels: one
        upper layer driver, one lower layer driver, and the SCSI midlayer.
      </para>
      <para>
        The SCSI upper layer provides the interface between userspace and the
        kernel, in the form of block and char device nodes for I/O and
        ioctl().  The SCSI lower layer contains drivers for specific hardware
        devices.
      </para>
      <para>
        In between is the SCSI mid-layer, analogous to a network routing
        layer such as the IPv4 stack.  The SCSI mid-layer routes a packet
        based data protocol between the upper layer's /dev nodes and the
        corresponding devices in the lower layer.  It manages command queues,
        provides error handling and power management functions, and responds
        to ioctl() requests.
      </para>
    </sect1>
  </chapter>
  <chapter id="upper_layer">
    <title>SCSI upper layer</title>
    <para>
      The upper layer supports the user-kernel interface by providing
      device nodes.
    </para>
    <sect1 id="sd">
      <title>sd (SCSI Disk)</title>
      <para>sd (sd_mod.o)</para>
 <!-- !Idrivers/scsi/sd.c -->
    </sect1>
    <sect1 id="sr">
      <title>sr (SCSI CD-ROM)</title>
      <para>sr (sr_mod.o)</para>
    </sect1>
    <sect1 id="st">
      <title>st (SCSI Tape)</title>
      <para>st (st.o)</para>
    </sect1>
    <sect1 id="sg">
      <title>sg (SCSI Generic)</title>
      <para>sg (sg.o)</para>
    </sect1>
    <sect1 id="ch">
      <title>ch (SCSI Media Changer)</title>
      <para>ch (ch.c)</para>
    </sect1>
  </chapter>
  <chapter id="mid_layer">
    <title>SCSI mid layer</title>
    <sect1 id="midlayer_implementation">
      <title>SCSI midlayer implementation</title>
      <sect2 id="scsi_device.h">
        <title>include/scsi/scsi_device.h</title>
        <para>
        </para>
 !Iinclude/scsi/scsi_device.h
      </sect2>
      <sect2 id="scsi.c">
        <title>drivers/scsi/scsi.c</title>
        <para>Main file for the SCSI midlayer.</para>
 !Edrivers/scsi/scsi.c
      </sect2>
      <sect2 id="scsicam.c">
        <title>drivers/scsi/scsicam.c</title>
        <para>
          <ulink url='http://www.t10.org/ftp/t10/drafts/cam/cam-r12b.pdf'>SCSI
          Common Access Method</ulink> support functions, for use with
          HDIO_GETGEO, etc.
        </para>
 !Edrivers/scsi/scsicam.c
      </sect2>
      <sect2 id="scsi_error.c">
        <title>drivers/scsi/scsi_error.c</title>
        <para>Common SCSI error/timeout handling routines.</para>
 !Edrivers/scsi/scsi_error.c
      </sect2>
      <sect2 id="scsi_devinfo.c">
        <title>drivers/scsi/scsi_devinfo.c</title>
        <para>
          Manage scsi_dev_info_list, which tracks blacklisted and whitelisted
          devices.
        </para>
 !Idrivers/scsi/scsi_devinfo.c
      </sect2>
      <sect2 id="scsi_ioctl.c">
        <title>drivers/scsi/scsi_ioctl.c</title>
        <para>
          Handle ioctl() calls for SCSI devices.
        </para>
 !Edrivers/scsi/scsi_ioctl.c
      </sect2>
      <sect2 id="scsi_lib.c">
        <title>drivers/scsi/scsi_lib.c</title>
        <para>
          SCSI queuing library.
        </para>
 !Edrivers/scsi/scsi_lib.c
      </sect2>
      <sect2 id="scsi_lib_dma.c">
        <title>drivers/scsi/scsi_lib_dma.c</title>
        <para>
          SCSI library functions depending on DMA
          (map and unmap scatter-gather lists).
        </para>
 !Edrivers/scsi/scsi_lib_dma.c
      </sect2>
      <sect2 id="scsi_module.c">
        <title>drivers/scsi/scsi_module.c</title>
        <para>
          The file drivers/scsi/scsi_module.c contains legacy support for
          old-style host templates.  It should never be used by any new driver.
        </para>
      </sect2>
      <sect2 id="scsi_proc.c">
        <title>drivers/scsi/scsi_proc.c</title>
        <para>
          The functions in this file provide an interface between
          the PROC file system and the SCSI device drivers
          It is mainly used for debugging, statistics and to pass
          information directly to the lowlevel driver.
          I.E. plumbing to manage /proc/scsi/*
        </para>
 !Idrivers/scsi/scsi_proc.c
      </sect2>
      <sect2 id="scsi_netlink.c">
        <title>drivers/scsi/scsi_netlink.c</title>
        <para>
          Infrastructure to provide async events from transports to userspace
          via netlink, using a single NETLINK_SCSITRANSPORT protocol for all
          transports.
          See <ulink url='http://marc.info/?l=linux-scsi&amp;m=115507374832500&amp;w=2'>the
          original patch submission</ulink> for more details.
        </para>
 !Idrivers/scsi/scsi_netlink.c
      </sect2>
      <sect2 id="scsi_scan.c">
        <title>drivers/scsi/scsi_scan.c</title>
        <para>
          Scan a host to determine which (if any) devices are attached.
          The general scanning/probing algorithm is as follows, exceptions are
          made to it depending on device specific flags, compilation options,
          and global variable (boot or module load time) settings.
          A specific LUN is scanned via an INQUIRY command; if the LUN has a
          device attached, a scsi_device is allocated and setup for it.
          For every id of every channel on the given host, start by scanning
          LUN 0.  Skip hosts that don't respond at all to a scan of LUN 0.
          Otherwise, if LUN 0 has a device attached, allocate and setup a
          scsi_device for it.  If target is SCSI-3 or up, issue a REPORT LUN,
          and scan all of the LUNs returned by the REPORT LUN; else,
          sequentially scan LUNs up until some maximum is reached, or a LUN is
          seen that cannot have a device attached to it.
        </para>
 !Idrivers/scsi/scsi_scan.c
      </sect2>
      <sect2 id="scsi_sysctl.c">
        <title>drivers/scsi/scsi_sysctl.c</title>
        <para>
          Set up the sysctl entry: "/dev/scsi/logging_level"
          (DEV_SCSI_LOGGING_LEVEL) which sets/returns scsi_logging_level.
        </para>
      </sect2>
      <sect2 id="scsi_sysfs.c">
        <title>drivers/scsi/scsi_sysfs.c</title>
        <para>
          SCSI sysfs interface routines.
        </para>
 !Edrivers/scsi/scsi_sysfs.c
      </sect2>
      <sect2 id="hosts.c">
        <title>drivers/scsi/hosts.c</title>
        <para>
          mid to lowlevel SCSI driver interface
        </para>
 !Edrivers/scsi/hosts.c
      </sect2>
      <sect2 id="constants.c">
        <title>drivers/scsi/constants.c</title>
        <para>
          mid to lowlevel SCSI driver interface
        </para>
 !Edrivers/scsi/constants.c
      </sect2>
    </sect1>
    <sect1 id="Transport_classes">
      <title>Transport classes</title>
      <para>
        Transport classes are service libraries for drivers in the SCSI
        lower layer, which expose transport attributes in sysfs.
      </para>
      <sect2 id="Fibre_Channel_transport">
        <title>Fibre Channel transport</title>
        <para>
          The file drivers/scsi/scsi_transport_fc.c defines transport attributes
          for Fibre Channel.
        </para>
 !Edrivers/scsi/scsi_transport_fc.c
      </sect2>
      <sect2 id="iSCSI_transport">
        <title>iSCSI transport class</title>
        <para>
          The file drivers/scsi/scsi_transport_iscsi.c defines transport
          attributes for the iSCSI class, which sends SCSI packets over TCP/IP
          connections.
        </para>
 !Edrivers/scsi/scsi_transport_iscsi.c
      </sect2>
      <sect2 id="SAS_transport">
        <title>Serial Attached SCSI (SAS) transport class</title>
        <para>
          The file drivers/scsi/scsi_transport_sas.c defines transport
          attributes for Serial Attached SCSI, a variant of SATA aimed at
          large high-end systems.
        </para>
        <para>
          The SAS transport class contains common code to deal with SAS HBAs,
          an aproximated representation of SAS topologies in the driver model,
-          and various sysfs attributes to expose these topologies and managment
+          and various sysfs attributes to expose these topologies and management
          interfaces to userspace.
        </para>
        <para>
          In addition to the basic SCSI core objects this transport class
          introduces two additional intermediate objects:  The SAS PHY
          as represented by struct sas_phy defines an "outgoing" PHY on
          a SAS HBA or Expander, and the SAS remote PHY represented by
          struct sas_rphy defines an "incoming" PHY on a SAS Expander or
          end device.  Note that this is purely a software concept, the
          underlying hardware for a PHY and a remote PHY is the exactly
          the same.
        </para>
        <para>
          There is no concept of a SAS port in this code, users can see
          what PHYs form a wide port based on the port_identifier attribute,
          which is the same for all PHYs in a port.
        </para>
 !Edrivers/scsi/scsi_transport_sas.c
      </sect2>
      <sect2 id="SATA_transport">
        <title>SATA transport class</title>
        <para>
          The SATA transport is handled by libata, which has its own book of
          documentation in this directory.
        </para>
      </sect2>
      <sect2 id="SPI_transport">
        <title>Parallel SCSI (SPI) transport class</title>
        <para>
          The file drivers/scsi/scsi_transport_spi.c defines transport
          attributes for traditional (fast/wide/ultra) SCSI busses.
        </para>
 !Edrivers/scsi/scsi_transport_spi.c
      </sect2>
      <sect2 id="SRP_transport">
        <title>SCSI RDMA (SRP) transport class</title>
        <para>
          The file drivers/scsi/scsi_transport_srp.c defines transport
          attributes for SCSI over Remote Direct Memory Access.
        </para>
 !Edrivers/scsi/scsi_transport_srp.c
      </sect2>
    </sect1>
  </chapter>
  <chapter id="lower_layer">
    <title>SCSI lower layer</title>
    <sect1 id="hba_drivers">
      <title>Host Bus Adapter transport types</title>
      <para>
        Many modern device controllers use the SCSI command set as a protocol to
        communicate with their devices through many different types of physical
        connections.
      </para>
      <para>
        In SCSI language a bus capable of carrying SCSI commands is
        called a "transport", and a controller connecting to such a bus is
        called a "host bus adapter" (HBA).
      </para>
      <sect2 id="scsi_debug.c">
        <title>Debug transport</title>
        <para>
          The file drivers/scsi/scsi_debug.c simulates a host adapter with a
          variable number of disks (or disk like devices) attached, sharing a
          common amount of RAM.  Does a lot of checking to make sure that we are
          not getting blocks mixed up, and panics the kernel if anything out of
          the ordinary is seen.
        </para>
        <para>
          To be more realistic, the simulated devices have the transport
          attributes of SAS disks.
        </para>
        <para>
          For documentation see
          <ulink url='http://www.torque.net/sg/sdebug26.html'>http://www.torque.net/sg/sdebug26.html</ulink>
        </para>
 <!-- !Edrivers/scsi/scsi_debug.c -->
      </sect2>
      <sect2 id="todo">
        <title>todo</title>
        <para>Parallel (fast/wide/ultra) SCSI, USB, SATA,
        SAS, Fibre Channel, FireWire, ATAPI devices, Infiniband,
        I20, iSCSI, Parallel ports, netlink...
        </para>
      </sect2>
    </sect1>
  </chapter>
 </book>
 Release Date	: Thu Nov 16 15:32:35 EST 2006 -
 				Sumant Patro <sumant.patro@lsi.com>
 Current Version : 2.20.5.1 (scsi module), 2.20.2.6 (cmm module)
 Older Version	: 2.20.4.9 (scsi module), 2.20.2.6 (cmm module)
 1.	Changes in Initialization to fix kdump failure.
 	Send SYNC command on loading.
 	This command clears the pending commands in the adapter
 	and re-initialize its internal RAID structure.
 	Without this change, megaraid driver either panics or fails to
 	initialize the adapter during kdump's second kernel boot
 	if there are pending commands or interrupts from other devices
 	sharing the same IRQ.
 2. 	Authors email-id domain name changed from lsil.com to lsi.com.
 	Also modified the MODULE_AUTHOR to megaraidlinux@lsi.com
 Release Date	: Fri May 19 09:31:45 EST 2006 - Seokmann Ju <sju@lsil.com>
 Current Version : 2.20.4.9 (scsi module), 2.20.2.6 (cmm module)
 Older Version	: 2.20.4.8 (scsi module), 2.20.2.6 (cmm module)
 1.	Fixed a bug in megaraid_init_mbox().
 	Customer reported "garbage in file on x86_64 platform".
 	Root Cause: the driver registered controllers as 64-bit DMA capable
 	for those which are not support it.
 	Fix: Made change in the function inserting identification machanism
 	identifying 64-bit DMA capable controllers.
 	> -----Original Message-----
 	> From: Vasily Averin [mailto:vvs@sw.ru]
 	> Sent: Thursday, May 04, 2006 2:49 PM
 	> To: linux-scsi@vger.kernel.org; Kolli, Neela; Mukker, Atul;
 	> Ju, Seokmann; Bagalkote, Sreenivas;
 	> James.Bottomley@SteelEye.com; devel@openvz.org
 	> Subject: megaraid_mbox: garbage in file
 	>
 	> Hello all,
 	>
 	> I've investigated customers claim on the unstable work of
 	> their node and found a
 	> strange effect: reading from some files leads to the
 	>  "attempt to access beyond end of device" messages.
 	>
 	> I've checked filesystem, memory on the node, motherboard BIOS
 	> version, but it
 	> does not help and issue still has been reproduced by simple
 	> file reading.
 	>
 	> Reproducer is simple:
 	>
 	> echo 0xffffffff >/proc/sys/dev/scsi/logging_level ;
 	> cat /vz/private/101/root/etc/ld.so.cache >/tmp/ttt  ;
 	> echo 0 >/proc/sys/dev/scsi/logging
 	>
 	> It leads to the following messages in dmesg
 	>
 	> sd_init_command: disk=sda, block=871769260, count=26
 	> sda : block=871769260
 	> sda : reading 26/26 512 byte blocks.
 	> scsi_add_timer: scmd: f79ed980, time: 7500, (c02b1420)
 	> sd 0:1:0:0: send 0xf79ed980                  sd 0:1:0:0:
 	>         command: Read (10): 28 00 33 f6 24 ac 00 00 1a 00
 	> buffer = 0xf7cfb540, bufflen = 13312, done = 0xc0366b40,
 	> queuecommand 0xc0344010
 	> leaving scsi_dispatch_cmnd()
 	> scsi_delete_timer: scmd: f79ed980, rtn: 1
 	> sd 0:1:0:0: done 0xf79ed980 SUCCESS        0 sd 0:1:0:0:
 	>         command: Read (10): 28 00 33 f6 24 ac 00 00 1a 00
 	> scsi host busy 1 failed 0
 	> sd 0:1:0:0: Notifying upper driver of completion (result 0)
 	> sd_rw_intr: sda: res=0x0
 	> 26 sectors total, 13312 bytes done.
 	> use_sg is 4
 	> attempt to access beyond end of device
 	> sda6: rw=0, want=1044134458, limit=951401367
 	> Buffer I/O error on device sda6, logical block 522067228
 	> attempt to access beyond end of device
 2.	When INQUIRY with EVPD bit set issued to the MegaRAID controller,
 	system memory gets corrupted.
 	Root Cause: MegaRAID F/W handle the INQUIRY with EVPD bit set
 	incorrectly.
 	Fix: MegaRAID F/W has fixed the problem and being process of release,
 	soon. Meanwhile, driver will filter out the request.
 3.	One of member in the data structure of the driver leads unaligne
 	issue on 64-bit platform.
 	Customer reporeted "kernel unaligned access addrss" issue when
 	application communicates with MegaRAID HBA driver.
 	Root Cause: in uioc_t structure, one of member had misaligned and it
 	led system to display the error message.
 	Fix: A patch submitted to community from following folk.
 	> -----Original Message-----
 	> From: linux-scsi-owner@vger.kernel.org
 	> [mailto:linux-scsi-owner@vger.kernel.org] On Behalf Of Sakurai Hiroomi
 	> Sent: Wednesday, July 12, 2006 4:20 AM
 	> To: linux-scsi@vger.kernel.org; linux-kernel@vger.kernel.org
 	> Subject: Re: Help: strange messages from kernel on IA64 platform
 	>
 	> Hi,
 	>
 	> I saw same message.
 	>
 	> When GAM(Global Array Manager) is started, The following
 	> message output.
 	> kernel: kernel unaligned access to 0xe0000001fe1080d4,
 	> ip=0xa000000200053371
 	>
 	> The uioc structure used by ioctl is defined by packed,
 	> the allignment of each member are disturbed.
 	> In a 64 bit structure, the allignment of member doesn't fit 64 bit
 	> boundary. this causes this messages.
 	> In a 32 bit structure, we don't see the message because the allinment
 	> of member fit 32 bit boundary even if packed is specified.
 	>
 	> patch
 	> I Add 32 bit dummy member to fit 64 bit boundary. I tested.
 	> We confirmed this patch fix the problem by IA64 server.
 	>
 	> **************************************************************
 	> ****************
 	> --- linux-2.6.9/drivers/scsi/megaraid/megaraid_ioctl.h.orig
 	> 2006-04-03 17:13:03.000000000 +0900
 	> +++ linux-2.6.9/drivers/scsi/megaraid/megaraid_ioctl.h
 	> 2006-04-03 17:14:09.000000000 +0900
 	> @@ -132,6 +132,10 @@
 	>  /* Driver Data: */
 	>          void __user *           user_data;
 	>          uint32_t                user_data_len;
 	> +
 	> +        /* 64bit alignment */
 	> +        uint32_t                pad_0xBC;
 	> +
 	>          mraid_passthru_t        __user *user_pthru;
 	>
 	>          mraid_passthru_t        *pthru32;
 	> **************************************************************
 	> ****************
 Release Date	: Mon Apr 11 12:27:22 EST 2006 - Seokmann Ju <sju@lsil.com>
 Current Version : 2.20.4.8 (scsi module), 2.20.2.6 (cmm module)
 Older Version	: 2.20.4.7 (scsi module), 2.20.2.6 (cmm module)
 1.	Fixed a bug in megaraid_reset_handler().
 	Customer reported "Unable to handle kernel NULL pointer dereference
 	at virtual address 00000000" when system goes to reset condition
 	for some reason. It happened randomly.
 	Root Cause: in the megaraid_reset_handler(), there is possibility not
 	returning pending packets in the pend_list if there are multiple
 	pending packets.
 	Fix: Made the change in the driver so that it will return all packets
 	in the pend_list.
 2.	Added change request.
 	As found in the following URL, rmb() only didn't help the
 	problem. I had to increase the loop counter to 0xFFFFFF. (6 F's)
 	http://marc.theaimsgroup.com/?l=linux-scsi&m=110971060502497&w=2
 	I attached a patch for your reference, too.
 	Could you check and get this fix in your driver?
 	Best Regards,
 	Jun'ichi Nomura
 Release Date	: Fri Nov 11 12:27:22 EST 2005 - Seokmann Ju <sju@lsil.com>
 Current Version : 2.20.4.7 (scsi module), 2.20.2.6 (cmm module)
 Older Version	: 2.20.4.6 (scsi module), 2.20.2.6 (cmm module)
 1.	Sorted out PCI IDs to remove megaraid support overlaps.
 	Based on the patch from Daniel, sorted out PCI IDs along with
 	charactor node name change from 'megadev' to 'megadev_legacy' to avoid
 	conflict.
 	---
 	Hopefully we'll be getting the build restriction zapped much sooner, 
 	but we should also be thinking about totally removing the hardware 
 	support overlap in the megaraid drivers.
 	This patch pencils in a date of Feb 06 for this, and performs some 
 	printk abuse in hope that existing legacy users might pick up on what's
 	going on.
 	Signed-off-by: Daniel Drake <dsd@gentoo.org>
 	---
 2.	Fixed a issue: megaraid always fails to reset handler.
 	---
 	I found that the megaraid driver always fails to reset the
 	adapter with the following message:
 		megaraid: resetting the host...
 		megaraid mbox: reset sequence completed successfully
 		megaraid: fast sync command timed out
 		megaraid: reservation reset failed
 	when the "Cluster mode" of the adapter BIOS is enabled.
 	So, whenever the reset occurs, the adapter goes to
 	offline and just become unavailable.
 	Jun'ichi Nomura [mailto:jnomura@mtc.biglobe.ne.jp]
 	---
 Release Date	: Mon Mar 07 12:27:22 EST 2005 - Seokmann Ju <sju@lsil.com>
 Current Version : 2.20.4.6 (scsi module), 2.20.2.6 (cmm module)
 Older Version	: 2.20.4.5 (scsi module), 2.20.2.5 (cmm module)
 1.	Added IOCTL backward compatibility.
 	Convert megaraid_mm driver to new compat_ioctl entry points.
 	I don't have easy access to hardware, so only compile tested.
 		- Signed-off-by:Andi Kleen <ak@muc.de>
 2.	megaraid_mbox fix: wrong order of arguments in memset()
 	That, BTW, shows why cross-builds are useful-the only indication of
 	problem had been a new warning showing up in sparse output on alpha
 	build (number of exceeding 256 got truncated).
 		- Signed-off-by: Al Viro
 		<viro@parcelfarce.linux.theplanet.co.uk>
 3.	Convert pci_module_init to pci_register_driver
 	Convert from pci_module_init to pci_register_driver
 	(from:http://kerneljanitors.org/TODO)
 		- Signed-off-by: Domen Puncer <domen@coderock.org>
 4.	Use the pre defined DMA mask constants from dma-mapping.h
 	Use the DMA_{64,32}BIT_MASK constants from dma-mapping.h when calling
 	pci_set_dma_mask() or pci_set_consistend_dma_mask(). See
 	http://marc.theaimsgroup.com/?t=108001993000001&r=1&w=2 for more
 	details.
 		Signed-off-by: Tobias Klauser <tklauser@nuerscht.ch>
 		Signed-off-by: Domen Puncer <domen@coderock.org>
 5.	Remove SSID checking for Dobson, Lindsay, and Verde based products.
 	Checking the SSVID/SSID for controllers which have Dobson, Lindsay,
 	and Verde is unnecessary because device ID has been assigned by LSI
 	and it is unique value. So, all controllers with these IOPs have to be
 	supported by the driver regardless SSVID/SSID.
 6.	Date Thu, 27 Jan 2005 04:31:09 +0100 
 	From Herbert Poetzl <> 
 	Subject RFC: assert_spin_locked() for 2.6 
 	Greetings!
 	overcautious programming will kill your kernel ;)
 	ever thought about checking a spin_lock or even
 	asserting that it must be held (maybe just for
 	spinlock debugging?) ...
 	there are several checks present in the kernel
 	where somebody does a variation on the following:
 	  BUG_ON(!spin_is_locked(&some_lock));
 	so what's wrong about that? nothing, unless you
 	compile the code with CONFIG_DEBUG_SPINLOCK but 
 	without CONFIG_SMP ... in which case the BUG()
 	will kill your kernel ...
 	maybe it's not advised to make such assertions, 
 	but here is a solution which works for me ...
 	(compile tested for sh, x86_64 and x86, boot/run
 	tested for x86 only)
 	best,
 	Herbert
 		- Herbert Poetzl <herbert@13thfloor.at>, Thu, 27 Jan 2005
 Release Date	: Thu Feb 03 12:27:22 EST 2005 - Seokmann Ju <sju@lsil.com>
 Current Version	: 2.20.4.5 (scsi module), 2.20.2.5 (cmm module)
 Older Version	: 2.20.4.4 (scsi module), 2.20.2.4 (cmm module)
 1.	Modified name of two attributes in scsi_host_template.
 	On Wed, 2005-02-02 at 10:56 -0500, Ju, Seokmann wrote:
 	> +	.sdev_attrs			= megaraid_device_attrs,
 	> +	.shost_attrs			= megaraid_class_device_attrs,
 	These are, perhaps, slightly confusing names.
 	The terms device and class_device have well defined meanings in the
 	generic device model, neither of which is what you mean here.
 	Why not simply megaraid_sdev_attrs and megaraid_shost_attrs?
 	Other than this, it looks fine to me too.
 Release Date	: Thu Jan 27 00:01:03 EST 2005 - Atul Mukker <atulm@lsil.com>
 Current Version	: 2.20.4.4 (scsi module), 2.20.2.5 (cmm module)
 Older Version	: 2.20.4.3 (scsi module), 2.20.2.4 (cmm module)
 1.	Bump up the version of scsi module due to its conflict.
 Release Date	: Thu Jan 21 00:01:03 EST 2005 - Atul Mukker <atulm@lsil.com>
 Current Version	: 2.20.4.3 (scsi module), 2.20.2.5 (cmm module)
 Older Version	: 2.20.4.2 (scsi module), 2.20.2.4 (cmm module)
 1.	Remove driver ioctl for logical drive to scsi address translation and
 	replace with the sysfs attribute. To remove drives and change
 	capacity, application shall now use the device attribute to get the
 	logical drive number for a scsi device. For adding newly created
 	logical drives, class device attribute would be required to uniquely
 	identify each controller.
 		- Atul Mukker <atulm@lsil.com>
 	"James, I've been thinking about this a little more, and you may be on
 	to something here. Let each driver add files as such:"
 		- Matt Domsch <Matt_Domsch@dell.com>, 12.15.2004
 		 linux-scsi mailing list
 	"Then, if you simply publish your LD number as an extra parameter of
 	the device, you can look through /sys to find it."
 		- James Bottomley <James.Bottomley@SteelEye.com>, 01.03.2005
 		 linux-scsi mailing list
 	"I don't see why not ... it's your driver, you can publish whatever
 	extra information you need as scsi_device attributes; that was one of
 	the designs of the extensible attribute system."
 		- James Bottomley <James.Bottomley@SteelEye.com>, 01.06.2005
 		 linux-scsi mailing list
 2.	Add AMI megaraid support - Brian King <brking@charter.net>
 		PCI_VENDOR_ID_AMI, PCI_DEVICE_ID_AMI_MEGARAID3,
 		PCI_VENDOR_ID_AMI, PCI_SUBSYS_ID_PERC3_DC,
 3.	Make some code static - Adrian Bunk <bunk@stusta.de>
 	Date:	Mon, 15 Nov 2004 03:14:57 +0100
 	The patch below makes some needlessly global code static.
 	-wait_queue_head_t wait_q;
 	+static wait_queue_head_t wait_q;
 	Signed-off-by: Adrian Bunk <bunk@stusta.de>
 4.	Added NEC ROMB support - NEC MegaRAID PCI Express ROMB controller
 		PCI_VENDOR_ID_LSI_LOGIC, PCI_DEVICE_ID_MEGARAID_NEC_ROMB_2E,
 		PCI_SUBSYS_ID_NEC, PCI_SUBSYS_ID_MEGARAID_NEC_ROMB_2E,
 5.	Fixed Tape drive issue : For any Direct CDB command to physical device
 	including tape, timeout value set by driver was 10 minutes. With this 
 	value, most of command will return within timeout. However, for those
 	command like ERASE or FORMAT, it takes more than an hour depends on
 	capacity of the device and the command could be terminated before it 
 	completes.
 	To address this issue, the 'timeout' field in the DCDB command will 
 	have NO TIMEOUT (i.e., 4) value as its timeout on DCDB command.
 Release Date	: Thu Dec  9 19:10:23 EST 2004
 	- Sreenivas Bagalkote <sreenib@lsil.com>
 Current Version	: 2.20.4.2 (scsi module), 2.20.2.4 (cmm module)
 Older Version	: 2.20.4.1 (scsi module), 2.20.2.3 (cmm module)
 i.	Introduced driver ioctl that returns scsi address for a given ld.
 	"Why can't the existing sysfs interfaces be used to do this?"
 		- Brian King (brking@us.ibm.com)
 	"I've looked into solving this another way, but I cannot see how
 	to get this driver-private mapping of logical drive number-> HCTL
 	without putting code something like this into the driver."
 	"...and by providing a mapping a function to userspace, the driver
 	is free to change its mapping algorithm in the future if necessary .."
 		- Matt Domsch (Matt_Domsch@dell.com)
 Release Date	: Thu Dec  9 19:02:14 EST 2004 - Sreenivas Bagalkote <sreenib@lsil.com>
 Current Version	: 2.20.4.1 (scsi module), 2.20.2.3 (cmm module)
 Older Version	: 2.20.4.1 (scsi module), 2.20.2.2 (cmm module)
 i.	Fix a bug in kioc's dma buffer deallocation
 Release Date	: Thu Nov  4 18:24:56 EST 2004 - Sreenivas Bagalkote <sreenib@lsil.com>
 Current Version	: 2.20.4.1 (scsi module), 2.20.2.2 (cmm module)
 Older Version	: 2.20.4.0 (scsi module), 2.20.2.1 (cmm module)
 i.	Handle IOCTL cmd timeouts more properly.
 ii.	pci_dma_sync_{sg,single}_for_cpu was introduced into megaraid_mbox
 	incorrectly (instead of _for_device). Changed to appropriate 
 	pci_dma_sync_{sg,single}_for_device.
 Release Date	: Wed Oct 06 11:15:29 EDT 2004 - Sreenivas Bagalkote <sreenib@lsil.com>
 Current Version	: 2.20.4.0 (scsi module), 2.20.2.1 (cmm module)
 Older Version	: 2.20.4.0 (scsi module), 2.20.2.0 (cmm module)
 i.	Remove CONFIG_COMPAT around register_ioctl32_conversion
 Release Date	: Mon Sep 27 22:15:07 EDT 2004 - Atul Mukker <atulm@lsil.com>
 Current Version	: 2.20.4.0 (scsi module), 2.20.2.0 (cmm module)
 Older Version	: 2.20.3.1 (scsi module), 2.20.2.0 (cmm module)
 i.	Fix data corruption. Because of a typo in the driver, the IO packets
 	were wrongly shared by the ioctl path. This causes a whole IO command
 	to be replaced by an incoming ioctl command.
 Release Date	: Tue Aug 24 09:43:35 EDT 2004 - Atul Mukker <atulm@lsil.com>
 Current Version	: 2.20.3.1 (scsi module), 2.20.2.0 (cmm module)
 Older Version	: 2.20.3.0 (scsi module), 2.20.2.0 (cmm module)
 i.	Function reordering so that inline functions are defined before they
 	are actually used. It is now mandatory for GCC 3.4.1 (current stable)
 	Declare some heavy-weight functions to be non-inlined,
 	megaraid_mbox_build_cmd, megaraid_mbox_runpendq,
 	megaraid_mbox_prepare_pthru, megaraid_mbox_prepare_epthru,
 	megaraid_busywait_mbox
 		- Andrew Morton, 08.19.2004
 		linux-scsi mailing list
 	"Something else to clean up after inclusion: every instance of an
 	inline function is actually rendered as a full function call, because
 	the function is always used before it is defined.  Atul, please
 	re-arrange the code to eliminate the need for most (all) of the
 	function prototypes at the top of each file, and define (not just
 	declare with a prototype) each inline function before its first use"
 		- Matt Domsch <Matt_Domsch@dell.com>, 07.27.2004
 		linux-scsi mailing list
 ii.	Display elapsed time (countdown) while waiting for FW to boot.
 iii.	Module compilation reorder in Makefile so that unresolved symbols do
 	not occur when driver is compiled non-modular.
 		Patrick J. LoPresti <patl@users.sourceforge.net>, 8.22.2004
 		linux-scsi mailing list
 Release Date	: Thu Aug 19 09:58:33 EDT 2004 - Atul Mukker <atulm@lsil.com>
 Current Version	: 2.20.3.0 (scsi module), 2.20.2.0 (cmm module)
 Older Version	: 2.20.2.0 (scsi module), 2.20.1.0 (cmm module)
 i.	When copying the mailbox packets, copy only first 14 bytes (for 32-bit
 	mailboxes) and only first 22 bytes (for 64-bit mailboxes). This is to
 	avoid getting the stale values for busy bit. We want to set the busy
 	bit just before issuing command to the FW.
 ii.	In the reset handling, if the reseted command is not owned by the
 	driver, do not (wrongly) print information for the "attached" driver
 	packet.
 iii.	Have extended wait when issuing command in synchronous mode. This is
 	required for the cases where the option ROM is disabled and there is
 	no BIOS to start the controller. The FW starts to boot after receiving
 	the first command from the driver. The current driver has 1 second
 	timeout for the synchronous commands, which is far less than what is
 	actually required. We now wait up to MBOX_RESET_TIME (180 seconds) for
 	FW boot process.
 iv.	In megaraid_mbox_product_info, clear the mailbox contents completely
 	before preparing the command for inquiry3. This is to ensure that the
 	FW does not get junk values in the command.
 v.	Do away with the redundant LSI_CONFIG_COMPAT redefinition for
 	CONFIG_COMPAT. Replace <asm/ioctl32.h> with <linux/ioctl32.h>
 		- James Bottomley <James.Bottomley@SteelEye.com>, 08.17.2004
 		 linux-scsi mailing list
 vi.	Add support for 64-bit applications. Current drivers assume only
 	32-bit applications, even on 64-bit platforms. Use the "data" and
 	"buffer" fields of the mimd_t structure, instead of embedded 32-bit
 	addresses in application mailbox and passthru structures.
 vii.	Move the function declarations for the management module from
 	megaraid_mm.h to megaraid_mm.c
 		- Andrew Morton, 08.19.2004
 		linux-scsi mailing list
 viii.	Change default values for MEGARAID_NEWGEN, MEGARAID_MM, and
 	MEGARAID_MAILBOX to 'n' in Kconfig.megaraid
 		- Andrew Morton, 08.19.2004
 		linux-scsi mailing list
 ix.	replace udelay with msleep
 x.	Typos corrected in comments and whitespace adjustments, explicit
 	grouping of expressions.
 Release Date	: Fri Jul 23 15:22:07 EDT 2004 - Atul Mukker <atulm@lsil.com>
 Current Version	: 2.20.2.0 (scsi module), 2.20.1.0 (cmm module)
 Older Version	: 2.20.1.0 (scsi module), 2.20.0.0 (cmm module)
 i.	Add PCI ids for Acer ROMB 2E solution
 ii.	Add PCI ids for I4
 iii.	Typo corrected for subsys id for megaraid sata 300-4x
 iv.	Remove yield() while mailbox handshake in synchronous commands
 	"My other main gripe is things like this:
 	+	// wait for maximum 1 second for status to post
 	+	for (i = 0; i < 40000; i++) {
 	+		if (mbox->numstatus != 0xFF) break;
 	+		udelay(25); yield();
 	+	}
 	which litter the driver.  Use of yield() in drivers is deprecated."
 		- James Bottomley <James.Bottomley@SteelEye.com>, 07.14.2004
 		 linux-scsi mailing list
 v.	Remove redundant __megaraid_busywait_mbox routine
-vi.	Fix bug in the managment module, which causes a system lockup when the
+vi.	Fix bug in the management module, which causes a system lockup when the
 	IO module is loaded and then unloaded, followed by executing any
 	management utility. The current version of management module does not
 	handle the adapter unregister properly.
 	Specifically, it still keeps a reference to the unregistered
 	controllers. To avoid this, the static array adapters has been
 	replaced by a dynamic list, which gets updated every time an adapter
 	is added or removed.
 	Also, during unregistration of the IO module, the resources are
 	now released in the exact reverse order of the allocation time
 	sequence.
 Release Date	: Fri Jun 25 18:58:43 EDT 2004 - Atul Mukker <atulm@lsil.com>
 Current Version	: 2.20.1.0
 Older Version	: megaraid 2.20.0.1
 i.	Stale list pointer in adapter causes kernel panic when module
 	megaraid_mbox is unloaded
 Release Date	: Thu Jun 24 20:37:11 EDT 2004 - Atul Mukker <atulm@lsil.com>
 Current Version	: 2.20.0.1
 Older Version	: megaraid 2.20.0.00
 i.	Modules are not 'y' by default, but depend on current definition of
 	SCSI & PCI.
 ii.	Redundant structure mraid_driver_t removed.
 iii.	Miscellaneous indentation and goto/label fixes.
 		- Christoph Hellwig <hch@infradead.org>, 06.24.2004 linux-scsi
 iv.	scsi_host_put(), do just before completing HBA shutdown.
 Release Date	: Mon Jun 21 19:53:54 EDT 2004 - Atul Mukker <atulm@lsil.com>
 Current Version	: 2.20.0.0
 Older Version	: megaraid 2.20.0.rc2 and 2.00.3
 i.	Independent module to interact with userland applications and
 	multiplex command to low level RAID module(s).
 	"Shared code in a third module, a "library module", is an acceptable
 	solution. modprobe automatically loads dependent modules, so users
 	running "modprobe driver1" or "modprobe driver2" would automatically
 	load the shared library module."
 		- Jeff Garzik <jgarzik@pobox.com> 02.25.2004 LKML
 	"As Jeff hinted, if your userspace<->driver API is consistent between
 	your new MPT-based RAID controllers and your existing megaraid driver,
 	then perhaps you need a single small helper module (lsiioctl or some
 	better name), loaded by both mptraid and megaraid automatically, which
 	handles registering the /dev/megaraid node dynamically. In this case,
 	both mptraid and megaraid would register with lsiioctl for each
 	adapter discovered, and lsiioctl would essentially be a switch,
 	redirecting userspace tool ioctls to the appropriate driver."
 		- Matt Domsch <Matt_Domsch@dell.com> 02.25.2004 LKML
 ii.	Remove C99 initializations from pci_device id.
 	"pci_id_table_g would be much more readable when not using C99
 	initializers.
 	PCI table doesn't change, there's lots of users that prefer the more
 	readable variant.  And it's really far less and much easier to grok
 	lines without C99 initializers."
 		- Christoph Hellwig <hch@infradead.org>, 05.28.2004 linux-scsi
 iii.	Many fixes as suggested by Christoph Hellwig <hch@infradead.org> on
 	linux-scsi, 05.28.2004
 iv.	We now support up to 32 parallel ioctl commands instead of current 1.
 	There is a conscious effort to let memory allocation not fail for ioctl
 	commands.
 v.	Do away with internal memory management. Use pci_pool_(create|alloc)
 	instead.
 vi.	Kill tasklet when unloading the driver.
 vii.	Do not use "host_lock', driver has fine-grain locks now to protect all
 	data structures.
 viii.	Optimize the build scatter-gather list routine. The callers already
 	know the data transfer address and length.
 ix.	Better implementation of error handling and recovery. Driver now
 	performs extended errors recovery for instances like scsi cable pull.
 x.	Disassociate the management commands with an overlaid scsi command.
 	Driver now treats the management packets as special packets and has a
 	dedicated callback routine.
  Model name	Description
  ----------    -----------
 ALC880
 ======
  3stack	3-jack in back and a headphone out
  3stack-digout	3-jack in back, a HP out and a SPDIF out
  5stack	5-jack in back, 2-jack in front
  5stack-digout	5-jack in back, 2-jack in front, a SPDIF out
  6stack	6-jack in back, 2-jack in front
  6stack-digout	6-jack with a SPDIF out
  w810		3-jack
  z71v		3-jack (HP shared SPDIF)
  asus		3-jack (ASUS Mobo)
  asus-w1v	ASUS W1V
  asus-dig	ASUS with SPDIF out
  asus-dig2	ASUS with SPDIF out (using GPIO2)
  uniwill	3-jack
  fujitsu	Fujitsu Laptops (Pi1536)
  F1734		2-jack
  lg		LG laptop (m1 express dual)
  lg-lw		LG LW20/LW25 laptop
  tcl		TCL S700
  clevo		Clevo laptops (m520G, m665n)
  medion	Medion Rim 2150
  test		for testing/debugging purpose, almost all controls can be
 		adjusted.  Appearing only when compiled with
 		$CONFIG_SND_DEBUG=y
  auto		auto-config reading BIOS (default)
 ALC260
 ======
  hp		HP machines
  hp-3013	HP machines (3013-variant)
  hp-dc7600	HP DC7600
  fujitsu	Fujitsu S7020
  acer		Acer TravelMate
  will		Will laptops (PB V7900)
  replacer	Replacer 672V
  favorit100	Maxdata Favorit 100XS
  basic		fixed pin assignment (old default model)
  test		for testing/debugging purpose, almost all controls can
 		adjusted.  Appearing only when compiled with
 		$CONFIG_SND_DEBUG=y
  auto		auto-config reading BIOS (default)
 ALC262
 ======
  fujitsu	Fujitsu Laptop
  hp-bpc	HP xw4400/6400/8400/9400 laptops
  hp-bpc-d7000	HP BPC D7000
  hp-tc-t5735	HP Thin Client T5735
  hp-rp5700	HP RP5700
  benq		Benq ED8
  benq-t31	Benq T31
  hippo		Hippo (ATI) with jack detection, Sony UX-90s
  hippo_1	Hippo (Benq) with jack detection
  sony-assamd	Sony ASSAMD
  toshiba-s06	Toshiba S06
  toshiba-rx1	Toshiba RX1
  tyan		Tyan Thunder n6650W (S2915-E)
  ultra		Samsung Q1 Ultra Vista model
  lenovo-3000	Lenovo 3000 y410
  nec		NEC Versa S9100
  basic		fixed pin assignment w/o SPDIF
  auto		auto-config reading BIOS (default)
 ALC267/268
 ==========
  quanta-il1	Quanta IL1 mini-notebook
  3stack	3-stack model
  toshiba	Toshiba A205
  acer		Acer laptops
  acer-dmic	Acer laptops with digital-mic
  acer-aspire	Acer Aspire One
  dell		Dell OEM laptops (Vostro 1200)
  zepto		Zepto laptops
  test		for testing/debugging purpose, almost all controls can
 		adjusted.  Appearing only when compiled with
 		$CONFIG_SND_DEBUG=y
  auto		auto-config reading BIOS (default)
 ALC269
 ======
  basic		Basic preset
  quanta	Quanta FL1
  eeepc-p703	ASUS Eeepc P703 P900A
  eeepc-p901	ASUS Eeepc P901 S101
  fujitsu	FSC Amilo
  lifebook	Fujitsu Lifebook S6420
  auto		auto-config reading BIOS (default)
 ALC662/663/272
 ==============
  3stack-dig	3-stack (2-channel) with SPDIF
  3stack-6ch	 3-stack (6-channel)
  3stack-6ch-dig 3-stack (6-channel) with SPDIF
  6stack-dig	 6-stack with SPDIF
  lenovo-101e	 Lenovo laptop
  eeepc-p701	ASUS Eeepc P701
  eeepc-ep20	ASUS Eeepc EP20
  ecs		ECS/Foxconn mobo
  m51va		ASUS M51VA
  g71v		ASUS G71V
  h13		ASUS H13
  g50v		ASUS G50V
  asus-mode1	ASUS
  asus-mode2	ASUS
  asus-mode3	ASUS
  asus-mode4	ASUS
  asus-mode5	ASUS
  asus-mode6	ASUS
  dell		Dell with ALC272
  dell-zm1	Dell ZM1 with ALC272
  samsung-nc10	Samsung NC10 mini notebook
  auto		auto-config reading BIOS (default)
 ALC882/883/885/888/889
 ======================
  3stack-dig	3-jack with SPDIF I/O
  6stack-dig	6-jack digital with SPDIF I/O
  arima		Arima W820Di1
  targa		Targa T8, MSI-1049 T8
  asus-a7j	ASUS A7J
  asus-a7m	ASUS A7M
  macpro	MacPro support
  mb5		Macbook 5,1
  mbp3		Macbook Pro rev3
  imac24	iMac 24'' with jack detection
  w2jc		ASUS W2JC
  3stack-2ch-dig	3-jack with SPDIF I/O (ALC883)
  alc883-6stack-dig	6-jack digital with SPDIF I/O (ALC883)
  3stack-6ch    3-jack 6-channel
  3stack-6ch-dig 3-jack 6-channel with SPDIF I/O
  6stack-dig-demo  6-jack digital for Intel demo board
  acer		Acer laptops (Travelmate 3012WTMi, Aspire 5600, etc)
  acer-aspire	Acer Aspire 9810
  acer-aspire-4930g Acer Aspire 4930G
  acer-aspire-6530g Acer Aspire 6530G
  acer-aspire-7730g Acer Aspire 7730G
  acer-aspire-8930g Acer Aspire 8930G
  medion	Medion Laptops
  medion-md2	Medion MD2
  targa-dig	Targa/MSI
  targa-2ch-dig	Targa/MSI with 2-channel
  targa-8ch-dig Targa/MSI with 8-channel (MSI GX620)
  laptop-eapd   3-jack with SPDIF I/O and EAPD (Clevo M540JE, M550JE)
  lenovo-101e	Lenovo 101E
  lenovo-nb0763	Lenovo NB0763
  lenovo-ms7195-dig Lenovo MS7195
  lenovo-sky	Lenovo Sky
  haier-w66	Haier W66
  3stack-hp	HP machines with 3stack (Lucknow, Samba boards)
  6stack-dell	Dell machines with 6stack (Inspiron 530)
  mitac		Mitac 8252D
  clevo-m540r	Clevo M540R (6ch + digital)
  clevo-m720	Clevo M720 laptop series
  fujitsu-pi2515 Fujitsu AMILO Pi2515
  fujitsu-xa3530 Fujitsu AMILO XA3530
  3stack-6ch-intel Intel DG33* boards
  intel-alc889a	Intel IbexPeak with ALC889A
  intel-x58	Intel DX58 with ALC889
  asus-p5q	ASUS P5Q-EM boards
  mb31		MacBook 3,1
  sony-vaio-tt  Sony VAIO TT
  auto		auto-config reading BIOS (default)
 ALC861/660
 ==========
  3stack	3-jack
  3stack-dig	3-jack with SPDIF I/O
  6stack-dig	6-jack with SPDIF I/O
  3stack-660	3-jack (for ALC660)
  uniwill-m31	Uniwill M31 laptop
  toshiba	Toshiba laptop support
  asus		Asus laptop support
  asus-laptop	ASUS F2/F3 laptops
  auto		auto-config reading BIOS (default)
 ALC861VD/660VD
 ==============
  3stack	3-jack
  3stack-dig	3-jack with SPDIF OUT
  6stack-dig	6-jack with SPDIF OUT
  3stack-660	3-jack (for ALC660VD)
  3stack-660-digout 3-jack with SPDIF OUT (for ALC660VD)
  lenovo	Lenovo 3000 C200
  dallas	Dallas laptops
  hp		HP TX1000
  asus-v1s	ASUS V1Sn
  auto		auto-config reading BIOS (default)
 CMI9880
 =======
  minimal	3-jack in back
  min_fp	3-jack in back, 2-jack in front
  full		6-jack in back, 2-jack in front
  full_dig	6-jack in back, 2-jack in front, SPDIF I/O
  allout	5-jack in back, 2-jack in front, SPDIF out
  auto		auto-config reading BIOS (default)
 AD1882 / AD1882A
 ================
  3stack	3-stack mode (default)
  6stack	6-stack mode
 AD1884A / AD1883 / AD1984A / AD1984B
 ====================================
  desktop	3-stack desktop (default)
  laptop	laptop with HP jack sensing
  mobile	mobile devices with HP jack sensing
  thinkpad	Lenovo Thinkpad X300
 AD1884
 ======
  N/A
 AD1981
 ======
  basic		3-jack (default)
  hp		HP nx6320
  thinkpad	Lenovo Thinkpad T60/X60/Z60
  toshiba	Toshiba U205
 AD1983
 ======
  N/A
 AD1984
 ======
  basic		default configuration
  thinkpad	Lenovo Thinkpad T61/X61
  dell_desktop	Dell T3400
 AD1986A
 =======
  6stack	6-jack, separate surrounds (default)
  3stack	3-stack, shared surrounds
  laptop	2-channel only (FSC V2060, Samsung M50)
  laptop-eapd	2-channel with EAPD (ASUS A6J)
  laptop-automute 2-channel with EAPD and HP-automute (Lenovo N100)
  ultra		2-channel with EAPD (Samsung Ultra tablet PC)
  samsung	2-channel with EAPD (Samsung R65)
  samsung-p50	2-channel with HP-automute (Samsung P50)
 AD1988/AD1988B/AD1989A/AD1989B
 ==============================
  6stack	6-jack
  6stack-dig	ditto with SPDIF
  3stack	3-jack
  3stack-dig	ditto with SPDIF
  laptop	3-jack with hp-jack automute
  laptop-dig	ditto with SPDIF
  auto		auto-config reading BIOS (default)
 Conexant 5045
 =============
  laptop-hpsense    Laptop with HP sense (old model laptop)
  laptop-micsense   Laptop with Mic sense (old model fujitsu)
  laptop-hpmicsense Laptop with HP and Mic senses
  benq		Benq R55E
  laptop-hp530	HP 530 laptop
  test		for testing/debugging purpose, almost all controls
 		can be adjusted.  Appearing only when compiled with
 		$CONFIG_SND_DEBUG=y
 Conexant 5047
 =============
  laptop	Basic Laptop config 
  laptop-hp	Laptop config for some HP models (subdevice 30A5)
  laptop-eapd	Laptop config with EAPD support
  test		for testing/debugging purpose, almost all controls
 		can be adjusted.  Appearing only when compiled with
 		$CONFIG_SND_DEBUG=y
 Conexant 5051
 =============
  laptop	Basic Laptop config (default)
  hp		HP Spartan laptop
  hp-dv6736	HP dv6736
  lenovo-x200	Lenovo X200 laptop
 Conexant 5066
 =============
  laptop	Basic Laptop config (default)
  dell-laptop	Dell laptops
  olpc-xo-1_5	OLPC XO 1.5
 STAC9200
 ========
  ref		Reference board
  oqo		OQO Model 2
  dell-d21	Dell (unknown)
  dell-d22	Dell (unknown)
  dell-d23	Dell (unknown)
  dell-m21	Dell Inspiron 630m, Dell Inspiron 640m
  dell-m22	Dell Latitude D620, Dell Latitude D820
  dell-m23	Dell XPS M1710, Dell Precision M90
  dell-m24	Dell Latitude 120L
  dell-m25	Dell Inspiron E1505n
  dell-m26	Dell Inspiron 1501
  dell-m27	Dell Inspiron E1705/9400
  gateway-m4	Gateway laptops with EAPD control
  gateway-m4-2	Gateway laptops with EAPD control
  panasonic	Panasonic CF-74
  auto		BIOS setup (default)
 STAC9205/9254
 =============
  ref		Reference board
  dell-m42	Dell (unknown)
  dell-m43	Dell Precision
  dell-m44	Dell Inspiron
  eapd		Keep EAPD on (e.g. Gateway T1616)
  auto		BIOS setup (default)
 STAC9220/9221
 =============
  ref		Reference board
  3stack	D945 3stack
  5stack	D945 5stack + SPDIF
  intel-mac-v1	Intel Mac Type 1
  intel-mac-v2	Intel Mac Type 2
  intel-mac-v3	Intel Mac Type 3
  intel-mac-v4	Intel Mac Type 4
  intel-mac-v5	Intel Mac Type 5
  intel-mac-auto Intel Mac (detect type according to subsystem id)
  macmini	Intel Mac Mini (equivalent with type 3)
  macbook	Intel Mac Book (eq. type 5)
  macbook-pro-v1 Intel Mac Book Pro 1st generation (eq. type 3)
  macbook-pro	Intel Mac Book Pro 2nd generation (eq. type 3)
  imac-intel	Intel iMac (eq. type 2)
  imac-intel-20	Intel iMac (newer version) (eq. type 3)
  ecs202	ECS/PC chips
  dell-d81	Dell (unknown)
  dell-d82	Dell (unknown)
  dell-m81	Dell (unknown)
  dell-m82	Dell XPS M1210
  auto		BIOS setup (default)
 STAC9202/9250/9251
 ==================
  ref		Reference board, base config
  m1		Some Gateway MX series laptops (NX560XL)
  m1-2		Some Gateway MX series laptops (MX6453)
  m2		Some Gateway MX series laptops (M255)
  m2-2		Some Gateway MX series laptops
  m3		Some Gateway MX series laptops
  m5		Some Gateway MX series laptops (MP6954)
  m6		Some Gateway NX series laptops
  auto		BIOS setup (default)
 STAC9227/9228/9229/927x
 =======================
  ref		Reference board
  ref-no-jd	Reference board without HP/Mic jack detection
  3stack	D965 3stack
  5stack	D965 5stack + SPDIF
  5stack-no-fp	D965 5stack without front panel
  dell-3stack	Dell Dimension E520
  dell-bios	Fixes with Dell BIOS setup
  auto		BIOS setup (default)
 STAC92HD71B*
 ============
  ref		Reference board
  dell-m4-1	Dell desktops
  dell-m4-2	Dell desktops
  dell-m4-3	Dell desktops
  hp-m4		HP mini 1000
  hp-dv5	HP dv series
  hp-hdx	HP HDX series
  hp-dv4-1222nr	HP dv4-1222nr (with LED support)
  auto		BIOS setup (default)
 STAC92HD73*
 ===========
  ref		Reference board
  no-jd		BIOS setup but without jack-detection
  intel		Intel DG45* mobos
  dell-m6-amic	Dell desktops/laptops with analog mics
  dell-m6-dmic	Dell desktops/laptops with digital mics
  dell-m6	Dell desktops/laptops with both type of mics
  dell-eq	Dell desktops/laptops
  alienware	Alienware M17x
  auto		BIOS setup (default)
 STAC92HD83*
 ===========
  ref		Reference board
-  mic-ref	Reference board with power managment for ports
+  mic-ref	Reference board with power management for ports
  dell-s14	Dell laptop
  auto		BIOS setup (default)
 STAC9872
 ========
  vaio		VAIO laptop without SPDIF
  auto		BIOS setup (default)
 Cirrus Logic CS4206/4207
 ========================
  mbp55		MacBook Pro 5,5
  auto		BIOS setup (default)
 		ftrace - Function Tracer
 		========================
 Copyright 2008 Red Hat Inc.
   Author:   Steven Rostedt <srostedt@redhat.com>
  License:   The GNU Free Documentation License, Version 1.2
               (dual licensed under the GPL v2)
 Reviewers:   Elias Oltmanns, Randy Dunlap, Andrew Morton,
 	     John Kacur, and David Teigland.
 Written for: 2.6.28-rc2
 Introduction
 ------------
 Ftrace is an internal tracer designed to help out developers and
 designers of systems to find what is going on inside the kernel.
 It can be used for debugging or analyzing latencies and
 performance issues that take place outside of user-space.
 Although ftrace is the function tracer, it also includes an
 infrastructure that allows for other types of tracing. Some of
 the tracers that are currently in ftrace include a tracer to
 trace context switches, the time it takes for a high priority
 task to run after it was woken up, the time interrupts are
 disabled, and more (ftrace allows for tracer plugins, which
 means that the list of tracers can always grow).
 Implementation Details
 ----------------------
 See ftrace-design.txt for details for arch porters and such.
 The File System
 ---------------
 Ftrace uses the debugfs file system to hold the control files as
 well as the files to display output.
 When debugfs is configured into the kernel (which selecting any ftrace
 option will do) the directory /sys/kernel/debug will be created. To mount
 this directory, you can add to your /etc/fstab file:
 debugfs       /sys/kernel/debug          debugfs defaults        0       0
 Or you can mount it at run time with:
 mount -t debugfs nodev /sys/kernel/debug
 For quicker access to that directory you may want to make a soft link to
 it:
 ln -s /sys/kernel/debug /debug
 Any selected ftrace option will also create a directory called tracing
 within the debugfs. The rest of the document will assume that you are in
 the ftrace directory (cd /sys/kernel/debug/tracing) and will only concentrate
 on the files within that directory and not distract from the content with
 the extended "/sys/kernel/debug/tracing" path name.
 That's it! (assuming that you have ftrace configured into your kernel)
 After mounting the debugfs, you can see a directory called
 "tracing".  This directory contains the control and output files
 of ftrace. Here is a list of some of the key files:
 Note: all time values are in microseconds.
  current_tracer:
 	This is used to set or display the current tracer
 	that is configured.
  available_tracers:
 	This holds the different types of tracers that
 	have been compiled into the kernel. The
 	tracers listed here can be configured by
 	echoing their name into current_tracer.
  tracing_enabled:
 	This sets or displays whether the current_tracer
 	is activated and tracing or not. Echo 0 into this
 	file to disable the tracer or 1 to enable it.
  trace:
 	This file holds the output of the trace in a human
 	readable format (described below).
  trace_pipe:
 	The output is the same as the "trace" file but this
 	file is meant to be streamed with live tracing.
 	Reads from this file will block until new data is
 	retrieved.  Unlike the "trace" file, this file is a
 	consumer. This means reading from this file causes
 	sequential reads to display more current data. Once
 	data is read from this file, it is consumed, and
 	will not be read again with a sequential read. The
 	"trace" file is static, and if the tracer is not
 	adding more data,they will display the same
 	information every time they are read.
  trace_options:
 	This file lets the user control the amount of data
 	that is displayed in one of the above output
 	files.
  tracing_max_latency:
 	Some of the tracers record the max latency.
 	For example, the time interrupts are disabled.
 	This time is saved in this file. The max trace
 	will also be stored, and displayed by "trace".
 	A new max trace will only be recorded if the
 	latency is greater than the value in this
 	file. (in microseconds)
  buffer_size_kb:
 	This sets or displays the number of kilobytes each CPU
 	buffer can hold. The tracer buffers are the same size
 	for each CPU. The displayed number is the size of the
 	CPU buffer and not total size of all buffers. The
 	trace buffers are allocated in pages (blocks of memory
 	that the kernel uses for allocation, usually 4 KB in size).
 	If the last page allocated has room for more bytes
 	than requested, the rest of the page will be used,
 	making the actual allocation bigger than requested.
 	( Note, the size may not be a multiple of the page size
-	  due to buffer managment overhead. )
+	  due to buffer management overhead. )
 	This can only be updated when the current_tracer
 	is set to "nop".
  tracing_cpumask:
 	This is a mask that lets the user only trace
 	on specified CPUS. The format is a hex string
 	representing the CPUS.
  set_ftrace_filter:
 	When dynamic ftrace is configured in (see the
 	section below "dynamic ftrace"), the code is dynamically
 	modified (code text rewrite) to disable calling of the
 	function profiler (mcount). This lets tracing be configured
 	in with practically no overhead in performance.  This also
 	has a side effect of enabling or disabling specific functions
 	to be traced. Echoing names of functions into this file
 	will limit the trace to only those functions.
  set_ftrace_notrace:
 	This has an effect opposite to that of
 	set_ftrace_filter. Any function that is added here will not
 	be traced. If a function exists in both set_ftrace_filter
 	and set_ftrace_notrace,	the function will _not_ be traced.
  set_ftrace_pid:
 	Have the function tracer only trace a single thread.
  set_graph_function:
 	Set a "trigger" function where tracing should start
 	with the function graph tracer (See the section
 	"dynamic ftrace" for more details).
  available_filter_functions:
 	This lists the functions that ftrace
 	has processed and can trace. These are the function
 	names that you can pass to "set_ftrace_filter" or
 	"set_ftrace_notrace". (See the section "dynamic ftrace"
 	below for more details.)
 The Tracers
 -----------
 Here is the list of current tracers that may be configured.
  "function"
 	Function call tracer to trace all kernel functions.
  "function_graph"
 	Similar to the function tracer except that the
 	function tracer probes the functions on their entry
 	whereas the function graph tracer traces on both entry
 	and exit of the functions. It then provides the ability
 	to draw a graph of function calls similar to C code
 	source.
  "sched_switch"
 	Traces the context switches and wakeups between tasks.
  "irqsoff"
 	Traces the areas that disable interrupts and saves
 	the trace with the longest max latency.
 	See tracing_max_latency. When a new max is recorded,
 	it replaces the old trace. It is best to view this
 	trace with the latency-format option enabled.
  "preemptoff"
 	Similar to irqsoff but traces and records the amount of
 	time for which preemption is disabled.
  "preemptirqsoff"
 	Similar to irqsoff and preemptoff, but traces and
 	records the largest time for which irqs and/or preemption
 	is disabled.
  "wakeup"
 	Traces and records the max latency that it takes for
 	the highest priority task to get scheduled after
 	it has been woken up.
  "hw-branch-tracer"
 	Uses the BTS CPU feature on x86 CPUs to traces all
 	branches executed.
  "nop"
 	This is the "trace nothing" tracer. To remove all
 	tracers from tracing simply echo "nop" into
 	current_tracer.
 Examples of using the tracer
 ----------------------------
 Here are typical examples of using the tracers when controlling
 them only with the debugfs interface (without using any
 user-land utilities).
 Output format:
 --------------
 Here is an example of the output format of the file "trace"
                             --------
 # tracer: function
 #
 #           TASK-PID   CPU#    TIMESTAMP  FUNCTION
 #              | |      |          |         |
            bash-4251  [01] 10152.583854: path_put <-path_walk
            bash-4251  [01] 10152.583855: dput <-path_put
            bash-4251  [01] 10152.583855: _atomic_dec_and_lock <-dput
                             --------
 A header is printed with the tracer name that is represented by
 the trace. In this case the tracer is "function". Then a header
 showing the format. Task name "bash", the task PID "4251", the
 CPU that it was running on "01", the timestamp in <secs>.<usecs>
 format, the function name that was traced "path_put" and the
 parent function that called this function "path_walk". The
 timestamp is the time at which the function was entered.
 The sched_switch tracer also includes tracing of task wakeups
 and context switches.
     ksoftirqd/1-7     [01]  1453.070013:      7:115:R   +  2916:115:S
     ksoftirqd/1-7     [01]  1453.070013:      7:115:R   +    10:115:S
     ksoftirqd/1-7     [01]  1453.070013:      7:115:R ==>    10:115:R
        events/1-10    [01]  1453.070013:     10:115:S ==>  2916:115:R
     kondemand/1-2916  [01]  1453.070013:   2916:115:S ==>     7:115:R
     ksoftirqd/1-7     [01]  1453.070013:      7:115:S ==>     0:140:R
 Wake ups are represented by a "+" and the context switches are
 shown as "==>".  The format is:
 Context switches:
       Previous task              Next Task
  <pid>:<prio>:<state>  ==>  <pid>:<prio>:<state>
 Wake ups:
       Current task               Task waking up
  <pid>:<prio>:<state>    +  <pid>:<prio>:<state>
 The prio is the internal kernel priority, which is the inverse
 of the priority that is usually displayed by user-space tools.
 Zero represents the highest priority (99). Prio 100 starts the
 "nice" priorities with 100 being equal to nice -20 and 139 being
 nice 19. The prio "140" is reserved for the idle task which is
 the lowest priority thread (pid 0).
 Latency trace format
 --------------------
 When the latency-format option is enabled, the trace file gives
 somewhat more information to see why a latency happened.
 Here is a typical trace.
 # tracer: irqsoff
 #
 irqsoff latency trace v1.1.5 on 2.6.26-rc8
 --------------------------------------------------------------------
 latency: 97 us, #3/3, CPU#0 | (M:preempt VP:0, KP:0, SP:0 HP:0 #P:2)
    -----------------
    | task: swapper-0 (uid:0 nice:0 policy:0 rt_prio:0)
    -----------------
 => started at: apic_timer_interrupt
 => ended at:   do_softirq
 #                _------=> CPU#
 #               / _-----=> irqs-off
 #              | / _----=> need-resched
 #              || / _---=> hardirq/softirq
 #              ||| / _--=> preempt-depth
 #              |||| /
 #              |||||     delay
 #  cmd     pid ||||| time  |   caller
 #     \   /    |||||   \   |   /
  <idle>-0     0d..1    0us+: trace_hardirqs_off_thunk (apic_timer_interrupt)
  <idle>-0     0d.s.   97us : __do_softirq (do_softirq)
  <idle>-0     0d.s1   98us : trace_hardirqs_on (do_softirq)
 This shows that the current tracer is "irqsoff" tracing the time
 for which interrupts were disabled. It gives the trace version
 and the version of the kernel upon which this was executed on
 (2.6.26-rc8). Then it displays the max latency in microsecs (97
 us). The number of trace entries displayed and the total number
 recorded (both are three: #3/3). The type of preemption that was
 used (PREEMPT). VP, KP, SP, and HP are always zero and are
 reserved for later use. #P is the number of online CPUS (#P:2).
 The task is the process that was running when the latency
 occurred. (swapper pid: 0).
 The start and stop (the functions in which the interrupts were
 disabled and enabled respectively) that caused the latencies:
  apic_timer_interrupt is where the interrupts were disabled.
  do_softirq is where they were enabled again.
 The next lines after the header are the trace itself. The header
 explains which is which.
  cmd: The name of the process in the trace.
  pid: The PID of that process.
  CPU#: The CPU which the process was running on.
  irqs-off: 'd' interrupts are disabled. '.' otherwise.
 	    Note: If the architecture does not support a way to
 		  read the irq flags variable, an 'X' will always
 		  be printed here.
  need-resched: 'N' task need_resched is set, '.' otherwise.
  hardirq/softirq:
 	'H' - hard irq occurred inside a softirq.
 	'h' - hard irq is running
 	's' - soft irq is running
 	'.' - normal context.
  preempt-depth: The level of preempt_disabled
 The above is mostly meaningful for kernel developers.
  time: When the latency-format option is enabled, the trace file
 	output includes a timestamp relative to the start of the
 	trace. This differs from the output when latency-format
 	is disabled, which includes an absolute timestamp.
  delay: This is just to help catch your eye a bit better. And
 	 needs to be fixed to be only relative to the same CPU.
 	 The marks are determined by the difference between this
 	 current trace and the next trace.
 	  '!' - greater than preempt_mark_thresh (default 100)
 	  '+' - greater than 1 microsecond
 	  ' ' - less than or equal to 1 microsecond.
  The rest is the same as the 'trace' file.
 trace_options
 -------------
 The trace_options file is used to control what gets printed in
 the trace output. To see what is available, simply cat the file:
  cat trace_options
  print-parent nosym-offset nosym-addr noverbose noraw nohex nobin \
  noblock nostacktrace nosched-tree nouserstacktrace nosym-userobj
 To disable one of the options, echo in the option prepended with
 "no".
  echo noprint-parent > trace_options
 To enable an option, leave off the "no".
  echo sym-offset > trace_options
 Here are the available options:
  print-parent - On function traces, display the calling (parent)
 		 function as well as the function being traced.
  print-parent:
   bash-4000  [01]  1477.606694: simple_strtoul <-strict_strtoul
  noprint-parent:
   bash-4000  [01]  1477.606694: simple_strtoul
  sym-offset - Display not only the function name, but also the
 	       offset in the function. For example, instead of
 	       seeing just "ktime_get", you will see
 	       "ktime_get+0xb/0x20".
  sym-offset:
   bash-4000  [01]  1477.606694: simple_strtoul+0x6/0xa0
  sym-addr - this will also display the function address as well
 	     as the function name.
  sym-addr:
   bash-4000  [01]  1477.606694: simple_strtoul <c0339346>
  verbose - This deals with the trace file when the
            latency-format option is enabled.
    bash  4000 1 0 00000000 00010a95 [58127d26] 1720.415ms \
    (+0.000ms): simple_strtoul (strict_strtoul)
  raw - This will display raw numbers. This option is best for
 	use with user applications that can translate the raw
 	numbers better than having it done in the kernel.
  hex - Similar to raw, but the numbers will be in a hexadecimal
 	format.
  bin - This will print out the formats in raw binary.
  block - TBD (needs update)
  stacktrace - This is one of the options that changes the trace
 	       itself. When a trace is recorded, so is the stack
 	       of functions. This allows for back traces of
 	       trace sites.
  userstacktrace - This option changes the trace. It records a
 		   stacktrace of the current userspace thread.
  sym-userobj - when user stacktrace are enabled, look up which
 		object the address belongs to, and print a
 		relative address. This is especially useful when
 		ASLR is on, otherwise you don't get a chance to
 		resolve the address to object/file/line after
 		the app is no longer running
 		The lookup is performed when you read
 		trace,trace_pipe. Example:
 		a.out-1623  [000] 40874.465068: /root/a.out[+0x480] <-/root/a.out[+0
 x494] <- /root/a.out[+0x4a8] <- /lib/libc-2.7.so[+0x1e1a6]
  sched-tree - trace all tasks that are on the runqueue, at
 	       every scheduling event. Will add overhead if
 	       there's a lot of tasks running at once.
  latency-format - This option changes the trace. When
                   it is enabled, the trace displays
                   additional information about the
                   latencies, as described in "Latency
                   trace format".
 sched_switch
 ------------
 This tracer simply records schedule switches. Here is an example
 of how to use it.
 # echo sched_switch > current_tracer
 # echo 1 > tracing_enabled
 # sleep 1
 # echo 0 > tracing_enabled
 # cat trace
 # tracer: sched_switch
 #
 #           TASK-PID   CPU#    TIMESTAMP  FUNCTION
 #              | |      |          |         |
            bash-3997  [01]   240.132281:   3997:120:R   +  4055:120:R
            bash-3997  [01]   240.132284:   3997:120:R ==>  4055:120:R
           sleep-4055  [01]   240.132371:   4055:120:S ==>  3997:120:R
            bash-3997  [01]   240.132454:   3997:120:R   +  4055:120:S
            bash-3997  [01]   240.132457:   3997:120:R ==>  4055:120:R
           sleep-4055  [01]   240.132460:   4055:120:D ==>  3997:120:R
            bash-3997  [01]   240.132463:   3997:120:R   +  4055:120:D
            bash-3997  [01]   240.132465:   3997:120:R ==>  4055:120:R
          <idle>-0     [00]   240.132589:      0:140:R   +     4:115:S
          <idle>-0     [00]   240.132591:      0:140:R ==>     4:115:R
     ksoftirqd/0-4     [00]   240.132595:      4:115:S ==>     0:140:R
          <idle>-0     [00]   240.132598:      0:140:R   +     4:115:S
          <idle>-0     [00]   240.132599:      0:140:R ==>     4:115:R
     ksoftirqd/0-4     [00]   240.132603:      4:115:S ==>     0:140:R
           sleep-4055  [01]   240.133058:   4055:120:S ==>  3997:120:R
 [...]
 As we have discussed previously about this format, the header
 shows the name of the trace and points to the options. The
 "FUNCTION" is a misnomer since here it represents the wake ups
 and context switches.
 The sched_switch file only lists the wake ups (represented with
 '+') and context switches ('==>') with the previous task or
 current task first followed by the next task or task waking up.
 The format for both of these is PID:KERNEL-PRIO:TASK-STATE.
 Remember that the KERNEL-PRIO is the inverse of the actual
 priority with zero (0) being the highest priority and the nice
 values starting at 100 (nice -20). Below is a quick chart to map
 the kernel priority to user land priorities.
   Kernel Space                     User Space
 ===============================================================
   0(high) to  98(low)     user RT priority 99(high) to 1(low)
                           with SCHED_RR or SCHED_FIFO
 ---------------------------------------------------------------
  99                       sched_priority is not used in scheduling
                           decisions(it must be specified as 0)
 ---------------------------------------------------------------
 100(high) to 139(low)     user nice -20(high) to 19(low)
 ---------------------------------------------------------------
 140                       idle task priority
 ---------------------------------------------------------------
 The task states are:
 R - running : wants to run, may not actually be running
 S - sleep   : process is waiting to be woken up (handles signals)
 D - disk sleep (uninterruptible sleep) : process must be woken up
 					(ignores signals)
 T - stopped : process suspended
 t - traced  : process is being traced (with something like gdb)
 Z - zombie  : process waiting to be cleaned up
 X - unknown
 ftrace_enabled
 --------------
 The following tracers (listed below) give different output
 depending on whether or not the sysctl ftrace_enabled is set. To
 set ftrace_enabled, one can either use the sysctl function or
 set it via the proc file system interface.
  sysctl kernel.ftrace_enabled=1
 or
  echo 1 > /proc/sys/kernel/ftrace_enabled
 To disable ftrace_enabled simply replace the '1' with '0' in the
 above commands.
 When ftrace_enabled is set the tracers will also record the
 functions that are within the trace. The descriptions of the
 tracers will also show an example with ftrace enabled.
 irqsoff
 -------
 When interrupts are disabled, the CPU can not react to any other
 external event (besides NMIs and SMIs). This prevents the timer
 interrupt from triggering or the mouse interrupt from letting
 the kernel know of a new mouse event. The result is a latency
 with the reaction time.
 The irqsoff tracer tracks the time for which interrupts are
 disabled. When a new maximum latency is hit, the tracer saves
 the trace leading up to that latency point so that every time a
 new maximum is reached, the old saved trace is discarded and the
 new trace is saved.
 To reset the maximum, echo 0 into tracing_max_latency. Here is
 an example:
 # echo irqsoff > current_tracer
 # echo latency-format > trace_options
 # echo 0 > tracing_max_latency
 # echo 1 > tracing_enabled
 # ls -ltr
 [...]
 # echo 0 > tracing_enabled
 # cat trace
 # tracer: irqsoff
 #
 irqsoff latency trace v1.1.5 on 2.6.26
 --------------------------------------------------------------------
 latency: 12 us, #3/3, CPU#1 | (M:preempt VP:0, KP:0, SP:0 HP:0 #P:2)
    -----------------
    | task: bash-3730 (uid:0 nice:0 policy:0 rt_prio:0)
    -----------------
 => started at: sys_setpgid
 => ended at:   sys_setpgid
 #                _------=> CPU#
 #               / _-----=> irqs-off
 #              | / _----=> need-resched
 #              || / _---=> hardirq/softirq
 #              ||| / _--=> preempt-depth
 #              |||| /
 #              |||||     delay
 #  cmd     pid ||||| time  |   caller
 #     \   /    |||||   \   |   /
    bash-3730  1d...    0us : _write_lock_irq (sys_setpgid)
    bash-3730  1d..1    1us+: _write_unlock_irq (sys_setpgid)
    bash-3730  1d..2   14us : trace_hardirqs_on (sys_setpgid)
 Here we see that that we had a latency of 12 microsecs (which is
 very good). The _write_lock_irq in sys_setpgid disabled
 interrupts. The difference between the 12 and the displayed
 timestamp 14us occurred because the clock was incremented
 between the time of recording the max latency and the time of
 recording the function that had that latency.
 Note the above example had ftrace_enabled not set. If we set the
 ftrace_enabled, we get a much larger output:
 # tracer: irqsoff
 #
 irqsoff latency trace v1.1.5 on 2.6.26-rc8
 --------------------------------------------------------------------
 latency: 50 us, #101/101, CPU#0 | (M:preempt VP:0, KP:0, SP:0 HP:0 #P:2)
    -----------------
    | task: ls-4339 (uid:0 nice:0 policy:0 rt_prio:0)
    -----------------
 => started at: __alloc_pages_internal
 => ended at:   __alloc_pages_internal
 #                _------=> CPU#
 #               / _-----=> irqs-off
 #              | / _----=> need-resched
 #              || / _---=> hardirq/softirq
 #              ||| / _--=> preempt-depth
 #              |||| /
 #              |||||     delay
 #  cmd     pid ||||| time  |   caller
 #     \   /    |||||   \   |   /
      ls-4339  0...1    0us+: get_page_from_freelist (__alloc_pages_internal)
      ls-4339  0d..1    3us : rmqueue_bulk (get_page_from_freelist)
      ls-4339  0d..1    3us : _spin_lock (rmqueue_bulk)
      ls-4339  0d..1    4us : add_preempt_count (_spin_lock)
      ls-4339  0d..2    4us : __rmqueue (rmqueue_bulk)
      ls-4339  0d..2    5us : __rmqueue_smallest (__rmqueue)
      ls-4339  0d..2    5us : __mod_zone_page_state (__rmqueue_smallest)
      ls-4339  0d..2    6us : __rmqueue (rmqueue_bulk)
      ls-4339  0d..2    6us : __rmqueue_smallest (__rmqueue)
      ls-4339  0d..2    7us : __mod_zone_page_state (__rmqueue_smallest)
      ls-4339  0d..2    7us : __rmqueue (rmqueue_bulk)
      ls-4339  0d..2    8us : __rmqueue_smallest (__rmqueue)
 [...]
      ls-4339  0d..2   46us : __rmqueue_smallest (__rmqueue)
      ls-4339  0d..2   47us : __mod_zone_page_state (__rmqueue_smallest)
      ls-4339  0d..2   47us : __rmqueue (rmqueue_bulk)
      ls-4339  0d..2   48us : __rmqueue_smallest (__rmqueue)
      ls-4339  0d..2   48us : __mod_zone_page_state (__rmqueue_smallest)
      ls-4339  0d..2   49us : _spin_unlock (rmqueue_bulk)
      ls-4339  0d..2   49us : sub_preempt_count (_spin_unlock)
      ls-4339  0d..1   50us : get_page_from_freelist (__alloc_pages_internal)
      ls-4339  0d..2   51us : trace_hardirqs_on (__alloc_pages_internal)
 Here we traced a 50 microsecond latency. But we also see all the
 functions that were called during that time. Note that by
 enabling function tracing, we incur an added overhead. This
 overhead may extend the latency times. But nevertheless, this
 trace has provided some very helpful debugging information.
 preemptoff
 ----------
 When preemption is disabled, we may be able to receive
 interrupts but the task cannot be preempted and a higher
 priority task must wait for preemption to be enabled again
 before it can preempt a lower priority task.
 The preemptoff tracer traces the places that disable preemption.
 Like the irqsoff tracer, it records the maximum latency for
 which preemption was disabled. The control of preemptoff tracer
 is much like the irqsoff tracer.
 # echo preemptoff > current_tracer
 # echo latency-format > trace_options
 # echo 0 > tracing_max_latency
 # echo 1 > tracing_enabled
 # ls -ltr
 [...]
 # echo 0 > tracing_enabled
 # cat trace
 # tracer: preemptoff
 #
 preemptoff latency trace v1.1.5 on 2.6.26-rc8
 --------------------------------------------------------------------
 latency: 29 us, #3/3, CPU#0 | (M:preempt VP:0, KP:0, SP:0 HP:0 #P:2)
    -----------------
    | task: sshd-4261 (uid:0 nice:0 policy:0 rt_prio:0)
    -----------------
 => started at: do_IRQ
 => ended at:   __do_softirq
 #                _------=> CPU#
 #               / _-----=> irqs-off
 #              | / _----=> need-resched
 #              || / _---=> hardirq/softirq
 #              ||| / _--=> preempt-depth
 #              |||| /
 #              |||||     delay
 #  cmd     pid ||||| time  |   caller
 #     \   /    |||||   \   |   /
    sshd-4261  0d.h.    0us+: irq_enter (do_IRQ)
    sshd-4261  0d.s.   29us : _local_bh_enable (__do_softirq)
    sshd-4261  0d.s1   30us : trace_preempt_on (__do_softirq)
 This has some more changes. Preemption was disabled when an
 interrupt came in (notice the 'h'), and was enabled while doing
 a softirq. (notice the 's'). But we also see that interrupts
 have been disabled when entering the preempt off section and
 leaving it (the 'd'). We do not know if interrupts were enabled
 in the mean time.
 # tracer: preemptoff
 #
 preemptoff latency trace v1.1.5 on 2.6.26-rc8
 --------------------------------------------------------------------
 latency: 63 us, #87/87, CPU#0 | (M:preempt VP:0, KP:0, SP:0 HP:0 #P:2)
    -----------------
    | task: sshd-4261 (uid:0 nice:0 policy:0 rt_prio:0)
    -----------------
 => started at: remove_wait_queue
 => ended at:   __do_softirq
 #                _------=> CPU#
 #               / _-----=> irqs-off
 #              | / _----=> need-resched
 #              || / _---=> hardirq/softirq
 #              ||| / _--=> preempt-depth
 #              |||| /
 #              |||||     delay
 #  cmd     pid ||||| time  |   caller
 #     \   /    |||||   \   |   /
    sshd-4261  0d..1    0us : _spin_lock_irqsave (remove_wait_queue)
    sshd-4261  0d..1    1us : _spin_unlock_irqrestore (remove_wait_queue)
    sshd-4261  0d..1    2us : do_IRQ (common_interrupt)
    sshd-4261  0d..1    2us : irq_enter (do_IRQ)
    sshd-4261  0d..1    2us : idle_cpu (irq_enter)
    sshd-4261  0d..1    3us : add_preempt_count (irq_enter)
    sshd-4261  0d.h1    3us : idle_cpu (irq_enter)
    sshd-4261  0d.h.    4us : handle_fasteoi_irq (do_IRQ)
 [...]
    sshd-4261  0d.h.   12us : add_preempt_count (_spin_lock)
    sshd-4261  0d.h1   12us : ack_ioapic_quirk_irq (handle_fasteoi_irq)
    sshd-4261  0d.h1   13us : move_native_irq (ack_ioapic_quirk_irq)
    sshd-4261  0d.h1   13us : _spin_unlock (handle_fasteoi_irq)
    sshd-4261  0d.h1   14us : sub_preempt_count (_spin_unlock)
    sshd-4261  0d.h1   14us : irq_exit (do_IRQ)
    sshd-4261  0d.h1   15us : sub_preempt_count (irq_exit)
    sshd-4261  0d..2   15us : do_softirq (irq_exit)
    sshd-4261  0d...   15us : __do_softirq (do_softirq)
    sshd-4261  0d...   16us : __local_bh_disable (__do_softirq)
    sshd-4261  0d...   16us+: add_preempt_count (__local_bh_disable)
    sshd-4261  0d.s4   20us : add_preempt_count (__local_bh_disable)
    sshd-4261  0d.s4   21us : sub_preempt_count (local_bh_enable)
    sshd-4261  0d.s5   21us : sub_preempt_count (local_bh_enable)
 [...]
    sshd-4261  0d.s6   41us : add_preempt_count (__local_bh_disable)
    sshd-4261  0d.s6   42us : sub_preempt_count (local_bh_enable)
    sshd-4261  0d.s7   42us : sub_preempt_count (local_bh_enable)
    sshd-4261  0d.s5   43us : add_preempt_count (__local_bh_disable)
    sshd-4261  0d.s5   43us : sub_preempt_count (local_bh_enable_ip)
    sshd-4261  0d.s6   44us : sub_preempt_count (local_bh_enable_ip)
    sshd-4261  0d.s5   44us : add_preempt_count (__local_bh_disable)
    sshd-4261  0d.s5   45us : sub_preempt_count (local_bh_enable)
 [...]
    sshd-4261  0d.s.   63us : _local_bh_enable (__do_softirq)
    sshd-4261  0d.s1   64us : trace_preempt_on (__do_softirq)
 The above is an example of the preemptoff trace with
 ftrace_enabled set. Here we see that interrupts were disabled
 the entire time. The irq_enter code lets us know that we entered
 an interrupt 'h'. Before that, the functions being traced still
 show that it is not in an interrupt, but we can see from the
 functions themselves that this is not the case.
 Notice that __do_softirq when called does not have a
 preempt_count. It may seem that we missed a preempt enabling.
 What really happened is that the preempt count is held on the
 thread's stack and we switched to the softirq stack (4K stacks
 in effect). The code does not copy the preempt count, but
 because interrupts are disabled, we do not need to worry about
 it. Having a tracer like this is good for letting people know
 what really happens inside the kernel.
 preemptirqsoff
 --------------
 Knowing the locations that have interrupts disabled or
 preemption disabled for the longest times is helpful. But
 sometimes we would like to know when either preemption and/or
 interrupts are disabled.
 Consider the following code:
    local_irq_disable();
    call_function_with_irqs_off();
    preempt_disable();
    call_function_with_irqs_and_preemption_off();
    local_irq_enable();
    call_function_with_preemption_off();
    preempt_enable();
 The irqsoff tracer will record the total length of
 call_function_with_irqs_off() and
 call_function_with_irqs_and_preemption_off().
 The preemptoff tracer will record the total length of
 call_function_with_irqs_and_preemption_off() and
 call_function_with_preemption_off().
 But neither will trace the time that interrupts and/or
 preemption is disabled. This total time is the time that we can
 not schedule. To record this time, use the preemptirqsoff
 tracer.
 Again, using this trace is much like the irqsoff and preemptoff
 tracers.
 # echo preemptirqsoff > current_tracer
 # echo latency-format > trace_options
 # echo 0 > tracing_max_latency
 # echo 1 > tracing_enabled
 # ls -ltr
 [...]
 # echo 0 > tracing_enabled
 # cat trace
 # tracer: preemptirqsoff
 #
 preemptirqsoff latency trace v1.1.5 on 2.6.26-rc8
 --------------------------------------------------------------------
 latency: 293 us, #3/3, CPU#0 | (M:preempt VP:0, KP:0, SP:0 HP:0 #P:2)
    -----------------
    | task: ls-4860 (uid:0 nice:0 policy:0 rt_prio:0)
    -----------------
 => started at: apic_timer_interrupt
 => ended at:   __do_softirq
 #                _------=> CPU#
 #               / _-----=> irqs-off
 #              | / _----=> need-resched
 #              || / _---=> hardirq/softirq
 #              ||| / _--=> preempt-depth
 #              |||| /
 #              |||||     delay
 #  cmd     pid ||||| time  |   caller
 #     \   /    |||||   \   |   /
      ls-4860  0d...    0us!: trace_hardirqs_off_thunk (apic_timer_interrupt)
      ls-4860  0d.s.  294us : _local_bh_enable (__do_softirq)
      ls-4860  0d.s1  294us : trace_preempt_on (__do_softirq)
 The trace_hardirqs_off_thunk is called from assembly on x86 when
 interrupts are disabled in the assembly code. Without the
 function tracing, we do not know if interrupts were enabled
 within the preemption points. We do see that it started with
 preemption enabled.
 Here is a trace with ftrace_enabled set:
 # tracer: preemptirqsoff
 #
 preemptirqsoff latency trace v1.1.5 on 2.6.26-rc8
 --------------------------------------------------------------------
 latency: 105 us, #183/183, CPU#0 | (M:preempt VP:0, KP:0, SP:0 HP:0 #P:2)
    -----------------
    | task: sshd-4261 (uid:0 nice:0 policy:0 rt_prio:0)
    -----------------
 => started at: write_chan
 => ended at:   __do_softirq
 #                _------=> CPU#
 #               / _-----=> irqs-off
 #              | / _----=> need-resched
 #              || / _---=> hardirq/softirq
 #              ||| / _--=> preempt-depth
 #              |||| /
 #              |||||     delay
 #  cmd     pid ||||| time  |   caller
 #     \   /    |||||   \   |   /
      ls-4473  0.N..    0us : preempt_schedule (write_chan)
      ls-4473  0dN.1    1us : _spin_lock (schedule)
      ls-4473  0dN.1    2us : add_preempt_count (_spin_lock)
      ls-4473  0d..2    2us : put_prev_task_fair (schedule)
 [...]
      ls-4473  0d..2   13us : set_normalized_timespec (ktime_get_ts)
      ls-4473  0d..2   13us : __switch_to (schedule)
    sshd-4261  0d..2   14us : finish_task_switch (schedule)
    sshd-4261  0d..2   14us : _spin_unlock_irq (finish_task_switch)
    sshd-4261  0d..1   15us : add_preempt_count (_spin_lock_irqsave)
    sshd-4261  0d..2   16us : _spin_unlock_irqrestore (hrtick_set)
    sshd-4261  0d..2   16us : do_IRQ (common_interrupt)
    sshd-4261  0d..2   17us : irq_enter (do_IRQ)
    sshd-4261  0d..2   17us : idle_cpu (irq_enter)
    sshd-4261  0d..2   18us : add_preempt_count (irq_enter)
    sshd-4261  0d.h2   18us : idle_cpu (irq_enter)
    sshd-4261  0d.h.   18us : handle_fasteoi_irq (do_IRQ)
    sshd-4261  0d.h.   19us : _spin_lock (handle_fasteoi_irq)
    sshd-4261  0d.h.   19us : add_preempt_count (_spin_lock)
    sshd-4261  0d.h1   20us : _spin_unlock (handle_fasteoi_irq)
    sshd-4261  0d.h1   20us : sub_preempt_count (_spin_unlock)
 [...]
    sshd-4261  0d.h1   28us : _spin_unlock (handle_fasteoi_irq)
    sshd-4261  0d.h1   29us : sub_preempt_count (_spin_unlock)
    sshd-4261  0d.h2   29us : irq_exit (do_IRQ)
    sshd-4261  0d.h2   29us : sub_preempt_count (irq_exit)
    sshd-4261  0d..3   30us : do_softirq (irq_exit)
    sshd-4261  0d...   30us : __do_softirq (do_softirq)
    sshd-4261  0d...   31us : __local_bh_disable (__do_softirq)
    sshd-4261  0d...   31us+: add_preempt_count (__local_bh_disable)
    sshd-4261  0d.s4   34us : add_preempt_count (__local_bh_disable)
 [...]
    sshd-4261  0d.s3   43us : sub_preempt_count (local_bh_enable_ip)
    sshd-4261  0d.s4   44us : sub_preempt_count (local_bh_enable_ip)
    sshd-4261  0d.s3   44us : smp_apic_timer_interrupt (apic_timer_interrupt)
    sshd-4261  0d.s3   45us : irq_enter (smp_apic_timer_interrupt)
    sshd-4261  0d.s3   45us : idle_cpu (irq_enter)
    sshd-4261  0d.s3   46us : add_preempt_count (irq_enter)
    sshd-4261  0d.H3   46us : idle_cpu (irq_enter)
    sshd-4261  0d.H3   47us : hrtimer_interrupt (smp_apic_timer_interrupt)
    sshd-4261  0d.H3   47us : ktime_get (hrtimer_interrupt)
 [...]
    sshd-4261  0d.H3   81us : tick_program_event (hrtimer_interrupt)
    sshd-4261  0d.H3   82us : ktime_get (tick_program_event)
    sshd-4261  0d.H3   82us : ktime_get_ts (ktime_get)
    sshd-4261  0d.H3   83us : getnstimeofday (ktime_get_ts)
    sshd-4261  0d.H3   83us : set_normalized_timespec (ktime_get_ts)
    sshd-4261  0d.H3   84us : clockevents_program_event (tick_program_event)
    sshd-4261  0d.H3   84us : lapic_next_event (clockevents_program_event)
    sshd-4261  0d.H3   85us : irq_exit (smp_apic_timer_interrupt)
    sshd-4261  0d.H3   85us : sub_preempt_count (irq_exit)
    sshd-4261  0d.s4   86us : sub_preempt_count (irq_exit)
    sshd-4261  0d.s3   86us : add_preempt_count (__local_bh_disable)
 [...]
    sshd-4261  0d.s1   98us : sub_preempt_count (net_rx_action)
    sshd-4261  0d.s.   99us : add_preempt_count (_spin_lock_irq)
    sshd-4261  0d.s1   99us+: _spin_unlock_irq (run_timer_softirq)
    sshd-4261  0d.s.  104us : _local_bh_enable (__do_softirq)
    sshd-4261  0d.s.  104us : sub_preempt_count (_local_bh_enable)
    sshd-4261  0d.s.  105us : _local_bh_enable (__do_softirq)
    sshd-4261  0d.s1  105us : trace_preempt_on (__do_softirq)
 This is a very interesting trace. It started with the preemption
 of the ls task. We see that the task had the "need_resched" bit
 set via the 'N' in the trace.  Interrupts were disabled before
 the spin_lock at the beginning of the trace. We see that a
 schedule took place to run sshd.  When the interrupts were
 enabled, we took an interrupt. On return from the interrupt
 handler, the softirq ran. We took another interrupt while
 running the softirq as we see from the capital 'H'.
 wakeup
 ------
 In a Real-Time environment it is very important to know the
 wakeup time it takes for the highest priority task that is woken
 up to the time that it executes. This is also known as "schedule
 latency". I stress the point that this is about RT tasks. It is
 also important to know the scheduling latency of non-RT tasks,
 but the average schedule latency is better for non-RT tasks.
 Tools like LatencyTop are more appropriate for such
 measurements.
 Real-Time environments are interested in the worst case latency.
 That is the longest latency it takes for something to happen,
 and not the average. We can have a very fast scheduler that may
 only have a large latency once in a while, but that would not
 work well with Real-Time tasks.  The wakeup tracer was designed
 to record the worst case wakeups of RT tasks. Non-RT tasks are
 not recorded because the tracer only records one worst case and
 tracing non-RT tasks that are unpredictable will overwrite the
 worst case latency of RT tasks.
 Since this tracer only deals with RT tasks, we will run this
 slightly differently than we did with the previous tracers.
 Instead of performing an 'ls', we will run 'sleep 1' under
 'chrt' which changes the priority of the task.
 # echo wakeup > current_tracer
 # echo latency-format > trace_options
 # echo 0 > tracing_max_latency
 # echo 1 > tracing_enabled
 # chrt -f 5 sleep 1
 # echo 0 > tracing_enabled
 # cat trace
 # tracer: wakeup
 #
 wakeup latency trace v1.1.5 on 2.6.26-rc8
 --------------------------------------------------------------------
 latency: 4 us, #2/2, CPU#1 | (M:preempt VP:0, KP:0, SP:0 HP:0 #P:2)
    -----------------
    | task: sleep-4901 (uid:0 nice:0 policy:1 rt_prio:5)
    -----------------
 #                _------=> CPU#
 #               / _-----=> irqs-off
 #              | / _----=> need-resched
 #              || / _---=> hardirq/softirq
 #              ||| / _--=> preempt-depth
 #              |||| /
 #              |||||     delay
 #  cmd     pid ||||| time  |   caller
 #     \   /    |||||   \   |   /
  <idle>-0     1d.h4    0us+: try_to_wake_up (wake_up_process)
  <idle>-0     1d..4    4us : schedule (cpu_idle)
 Running this on an idle system, we see that it only took 4
 microseconds to perform the task switch.  Note, since the trace
 marker in the schedule is before the actual "switch", we stop
 the tracing when the recorded task is about to schedule in. This
 may change if we add a new marker at the end of the scheduler.
 Notice that the recorded task is 'sleep' with the PID of 4901
 and it has an rt_prio of 5. This priority is user-space priority
 and not the internal kernel priority. The policy is 1 for
 SCHED_FIFO and 2 for SCHED_RR.
 Doing the same with chrt -r 5 and ftrace_enabled set.
 # tracer: wakeup
 #
 wakeup latency trace v1.1.5 on 2.6.26-rc8
 --------------------------------------------------------------------
 latency: 50 us, #60/60, CPU#1 | (M:preempt VP:0, KP:0, SP:0 HP:0 #P:2)
    -----------------
    | task: sleep-4068 (uid:0 nice:0 policy:2 rt_prio:5)
    -----------------
 #                _------=> CPU#
 #               / _-----=> irqs-off
 #              | / _----=> need-resched
 #              || / _---=> hardirq/softirq
 #              ||| / _--=> preempt-depth
 #              |||| /
 #              |||||     delay
 #  cmd     pid ||||| time  |   caller
 #     \   /    |||||   \   |   /
 ksoftirq-7     1d.H3    0us : try_to_wake_up (wake_up_process)
 ksoftirq-7     1d.H4    1us : sub_preempt_count (marker_probe_cb)
 ksoftirq-7     1d.H3    2us : check_preempt_wakeup (try_to_wake_up)
 ksoftirq-7     1d.H3    3us : update_curr (check_preempt_wakeup)
 ksoftirq-7     1d.H3    4us : calc_delta_mine (update_curr)
 ksoftirq-7     1d.H3    5us : __resched_task (check_preempt_wakeup)
 ksoftirq-7     1d.H3    6us : task_wake_up_rt (try_to_wake_up)
 ksoftirq-7     1d.H3    7us : _spin_unlock_irqrestore (try_to_wake_up)
 [...]
 ksoftirq-7     1d.H2   17us : irq_exit (smp_apic_timer_interrupt)
 ksoftirq-7     1d.H2   18us : sub_preempt_count (irq_exit)
 ksoftirq-7     1d.s3   19us : sub_preempt_count (irq_exit)
 ksoftirq-7     1..s2   20us : rcu_process_callbacks (__do_softirq)
 [...]
 ksoftirq-7     1..s2   26us : __rcu_process_callbacks (rcu_process_callbacks)
 ksoftirq-7     1d.s2   27us : _local_bh_enable (__do_softirq)
 ksoftirq-7     1d.s2   28us : sub_preempt_count (_local_bh_enable)
 ksoftirq-7     1.N.3   29us : sub_preempt_count (ksoftirqd)
 ksoftirq-7     1.N.2   30us : _cond_resched (ksoftirqd)
 ksoftirq-7     1.N.2   31us : __cond_resched (_cond_resched)
 ksoftirq-7     1.N.2   32us : add_preempt_count (__cond_resched)
 ksoftirq-7     1.N.2   33us : schedule (__cond_resched)
 ksoftirq-7     1.N.2   33us : add_preempt_count (schedule)
 ksoftirq-7     1.N.3   34us : hrtick_clear (schedule)
 ksoftirq-7     1dN.3   35us : _spin_lock (schedule)
 ksoftirq-7     1dN.3   36us : add_preempt_count (_spin_lock)
 ksoftirq-7     1d..4   37us : put_prev_task_fair (schedule)
 ksoftirq-7     1d..4   38us : update_curr (put_prev_task_fair)
 [...]
 ksoftirq-7     1d..5   47us : _spin_trylock (tracing_record_cmdline)
 ksoftirq-7     1d..5   48us : add_preempt_count (_spin_trylock)
 ksoftirq-7     1d..6   49us : _spin_unlock (tracing_record_cmdline)
 ksoftirq-7     1d..6   49us : sub_preempt_count (_spin_unlock)
 ksoftirq-7     1d..4   50us : schedule (__cond_resched)
 The interrupt went off while running ksoftirqd. This task runs
 at SCHED_OTHER. Why did not we see the 'N' set early? This may
 be a harmless bug with x86_32 and 4K stacks. On x86_32 with 4K
 stacks configured, the interrupt and softirq run with their own
 stack. Some information is held on the top of the task's stack
 (need_resched and preempt_count are both stored there). The
 setting of the NEED_RESCHED bit is done directly to the task's
 stack, but the reading of the NEED_RESCHED is done by looking at
 the current stack, which in this case is the stack for the hard
 interrupt. This hides the fact that NEED_RESCHED has been set.
 We do not see the 'N' until we switch back to the task's
 assigned stack.
 function
 --------
 This tracer is the function tracer. Enabling the function tracer
 can be done from the debug file system. Make sure the
 ftrace_enabled is set; otherwise this tracer is a nop.
 # sysctl kernel.ftrace_enabled=1
 # echo function > current_tracer
 # echo 1 > tracing_enabled
 # usleep 1
 # echo 0 > tracing_enabled
 # cat trace
 # tracer: function
 #
 #           TASK-PID   CPU#    TIMESTAMP  FUNCTION
 #              | |      |          |         |
            bash-4003  [00]   123.638713: finish_task_switch <-schedule
            bash-4003  [00]   123.638714: _spin_unlock_irq <-finish_task_switch
            bash-4003  [00]   123.638714: sub_preempt_count <-_spin_unlock_irq
            bash-4003  [00]   123.638715: hrtick_set <-schedule
            bash-4003  [00]   123.638715: _spin_lock_irqsave <-hrtick_set
            bash-4003  [00]   123.638716: add_preempt_count <-_spin_lock_irqsave
            bash-4003  [00]   123.638716: _spin_unlock_irqrestore <-hrtick_set
            bash-4003  [00]   123.638717: sub_preempt_count <-_spin_unlock_irqrestore
            bash-4003  [00]   123.638717: hrtick_clear <-hrtick_set
            bash-4003  [00]   123.638718: sub_preempt_count <-schedule
            bash-4003  [00]   123.638718: sub_preempt_count <-preempt_schedule
            bash-4003  [00]   123.638719: wait_for_completion <-__stop_machine_run
            bash-4003  [00]   123.638719: wait_for_common <-wait_for_completion
            bash-4003  [00]   123.638720: _spin_lock_irq <-wait_for_common
            bash-4003  [00]   123.638720: add_preempt_count <-_spin_lock_irq
 [...]
 Note: function tracer uses ring buffers to store the above
 entries. The newest data may overwrite the oldest data.
 Sometimes using echo to stop the trace is not sufficient because
 the tracing could have overwritten the data that you wanted to
 record. For this reason, it is sometimes better to disable
 tracing directly from a program. This allows you to stop the
 tracing at the point that you hit the part that you are
 interested in. To disable the tracing directly from a C program,
 something like following code snippet can be used:
 int trace_fd;
 [...]
 int main(int argc, char *argv[]) {
 	[...]
 	trace_fd = open(tracing_file("tracing_enabled"), O_WRONLY);
 	[...]
 	if (condition_hit()) {
 		write(trace_fd, "0", 1);
 	}
 	[...]
 }
 Single thread tracing
 ---------------------
 By writing into set_ftrace_pid you can trace a
 single thread. For example:
 # cat set_ftrace_pid
 no pid
 # echo 3111 > set_ftrace_pid
 # cat set_ftrace_pid
 3111
 # echo function > current_tracer
 # cat trace | head
 # tracer: function
 #
 #           TASK-PID    CPU#    TIMESTAMP  FUNCTION
 #              | |       |          |         |
     yum-updatesd-3111  [003]  1637.254676: finish_task_switch <-thread_return
     yum-updatesd-3111  [003]  1637.254681: hrtimer_cancel <-schedule_hrtimeout_range
     yum-updatesd-3111  [003]  1637.254682: hrtimer_try_to_cancel <-hrtimer_cancel
     yum-updatesd-3111  [003]  1637.254683: lock_hrtimer_base <-hrtimer_try_to_cancel
     yum-updatesd-3111  [003]  1637.254685: fget_light <-do_sys_poll
     yum-updatesd-3111  [003]  1637.254686: pipe_poll <-do_sys_poll
 # echo -1 > set_ftrace_pid
 # cat trace |head
 # tracer: function
 #
 #           TASK-PID    CPU#    TIMESTAMP  FUNCTION
 #              | |       |          |         |
 ##### CPU 3 buffer started ####
     yum-updatesd-3111  [003]  1701.957688: free_poll_entry <-poll_freewait
     yum-updatesd-3111  [003]  1701.957689: remove_wait_queue <-free_poll_entry
     yum-updatesd-3111  [003]  1701.957691: fput <-free_poll_entry
     yum-updatesd-3111  [003]  1701.957692: audit_syscall_exit <-sysret_audit
     yum-updatesd-3111  [003]  1701.957693: path_put <-audit_syscall_exit
 If you want to trace a function when executing, you could use
 something like this simple program:
 #include <stdio.h>
 #include <stdlib.h>
 #include <sys/types.h>
 #include <sys/stat.h>
 #include <fcntl.h>
 #include <unistd.h>
 #define _STR(x) #x
 #define STR(x) _STR(x)
 #define MAX_PATH 256
 const char *find_debugfs(void)
 {
       static char debugfs[MAX_PATH+1];
       static int debugfs_found;
       char type[100];
       FILE *fp;
       if (debugfs_found)
               return debugfs;
       if ((fp = fopen("/proc/mounts","r")) == NULL) {
               perror("/proc/mounts");
               return NULL;
       }
       while (fscanf(fp, "%*s %"
                     STR(MAX_PATH)
                     "s %99s %*s %*d %*d\n",
                     debugfs, type) == 2) {
               if (strcmp(type, "debugfs") == 0)
                       break;
       }
       fclose(fp);
       if (strcmp(type, "debugfs") != 0) {
               fprintf(stderr, "debugfs not mounted");
               return NULL;
       }
       debugfs_found = 1;
       return debugfs;
 }
 const char *tracing_file(const char *file_name)
 {
       static char trace_file[MAX_PATH+1];
       snprintf(trace_file, MAX_PATH, "%s/%s", find_debugfs(), file_name);
       return trace_file;
 }
 int main (int argc, char **argv)
 {
        if (argc < 1)
                exit(-1);
        if (fork() > 0) {
                int fd, ffd;
                char line[64];
                int s;
                ffd = open(tracing_file("current_tracer"), O_WRONLY);
                if (ffd < 0)
                        exit(-1);
                write(ffd, "nop", 3);
                fd = open(tracing_file("set_ftrace_pid"), O_WRONLY);
                s = sprintf(line, "%d\n", getpid());
                write(fd, line, s);
                write(ffd, "function", 8);
                close(fd);
                close(ffd);
                execvp(argv[1], argv+1);
        }
        return 0;
 }
 hw-branch-tracer (x86 only)
 ---------------------------
 This tracer uses the x86 last branch tracing hardware feature to
 collect a branch trace on all cpus with relatively low overhead.
 The tracer uses a fixed-size circular buffer per cpu and only
 traces ring 0 branches. The trace file dumps that buffer in the
 following format:
 # tracer: hw-branch-tracer
 #
 # CPU#        TO  <-  FROM
   0  scheduler_tick+0xb5/0x1bf	  <-  task_tick_idle+0x5/0x6
   2  run_posix_cpu_timers+0x2b/0x72a	  <-  run_posix_cpu_timers+0x25/0x72a
   0  scheduler_tick+0x139/0x1bf	  <-  scheduler_tick+0xed/0x1bf
   0  scheduler_tick+0x17c/0x1bf	  <-  scheduler_tick+0x148/0x1bf
   2  run_posix_cpu_timers+0x9e/0x72a	  <-  run_posix_cpu_timers+0x5e/0x72a
   0  scheduler_tick+0x1b6/0x1bf	  <-  scheduler_tick+0x1aa/0x1bf
 The tracer may be used to dump the trace for the oops'ing cpu on
 a kernel oops into the system log. To enable this,
 ftrace_dump_on_oops must be set. To set ftrace_dump_on_oops, one
 can either use the sysctl function or set it via the proc system
 interface.
  sysctl kernel.ftrace_dump_on_oops=1
 or
  echo 1 > /proc/sys/kernel/ftrace_dump_on_oops
 Here's an example of such a dump after a null pointer
 dereference in a kernel module:
 [57848.105921] BUG: unable to handle kernel NULL pointer dereference at 0000000000000000
 [57848.106019] IP: [<ffffffffa0000006>] open+0x6/0x14 [oops]
 [57848.106019] PGD 2354e9067 PUD 2375e7067 PMD 0
 [57848.106019] Oops: 0002 [#1] SMP
 [57848.106019] last sysfs file: /sys/devices/pci0000:00/0000:00:1e.0/0000:20:05.0/local_cpus
 [57848.106019] Dumping ftrace buffer:
 [57848.106019] ---------------------------------
 [...]
 [57848.106019]    0  chrdev_open+0xe6/0x165	  <-  cdev_put+0x23/0x24
 [57848.106019]    0  chrdev_open+0x117/0x165	  <-  chrdev_open+0xfa/0x165
 [57848.106019]    0  chrdev_open+0x120/0x165	  <-  chrdev_open+0x11c/0x165
 [57848.106019]    0  chrdev_open+0x134/0x165	  <-  chrdev_open+0x12b/0x165
 [57848.106019]    0  open+0x0/0x14 [oops]	  <-  chrdev_open+0x144/0x165
 [57848.106019]    0  page_fault+0x0/0x30	  <-  open+0x6/0x14 [oops]
 [57848.106019]    0  error_entry+0x0/0x5b	  <-  page_fault+0x4/0x30
 [57848.106019]    0  error_kernelspace+0x0/0x31	  <-  error_entry+0x59/0x5b
 [57848.106019]    0  error_sti+0x0/0x1	  <-  error_kernelspace+0x2d/0x31
 [57848.106019]    0  page_fault+0x9/0x30	  <-  error_sti+0x0/0x1
 [57848.106019]    0  do_page_fault+0x0/0x881	  <-  page_fault+0x1a/0x30
 [...]
 [57848.106019]    0  do_page_fault+0x66b/0x881	  <-  is_prefetch+0x1ee/0x1f2
 [57848.106019]    0  do_page_fault+0x6e0/0x881	  <-  do_page_fault+0x67a/0x881
 [57848.106019]    0  oops_begin+0x0/0x96	  <-  do_page_fault+0x6e0/0x881
 [57848.106019]    0  trace_hw_branch_oops+0x0/0x2d	  <-  oops_begin+0x9/0x96
 [...]
 [57848.106019]    0  ds_suspend_bts+0x2a/0xe3	  <-  ds_suspend_bts+0x1a/0xe3
 [57848.106019] ---------------------------------
 [57848.106019] CPU 0
 [57848.106019] Modules linked in: oops
 [57848.106019] Pid: 5542, comm: cat Tainted: G        W  2.6.28 #23
 [57848.106019] RIP: 0010:[<ffffffffa0000006>]  [<ffffffffa0000006>] open+0x6/0x14 [oops]
 [57848.106019] RSP: 0018:ffff880235457d48  EFLAGS: 00010246
 [...]
 function graph tracer
 ---------------------------
 This tracer is similar to the function tracer except that it
 probes a function on its entry and its exit. This is done by
 using a dynamically allocated stack of return addresses in each
 task_struct. On function entry the tracer overwrites the return
 address of each function traced to set a custom probe. Thus the
 original return address is stored on the stack of return address
 in the task_struct.
 Probing on both ends of a function leads to special features
 such as:
 - measure of a function's time execution
 - having a reliable call stack to draw function calls graph
 This tracer is useful in several situations:
 - you want to find the reason of a strange kernel behavior and
  need to see what happens in detail on any areas (or specific
  ones).
 - you are experiencing weird latencies but it's difficult to
  find its origin.
 - you want to find quickly which path is taken by a specific
  function
 - you just want to peek inside a working kernel and want to see
  what happens there.
 # tracer: function_graph
 #
 # CPU  DURATION                  FUNCTION CALLS
 # |     |   |                     |   |   |   |
 0)               |  sys_open() {
 0)               |    do_sys_open() {
 0)               |      getname() {
 0)               |        kmem_cache_alloc() {
 0)   1.382 us    |          __might_sleep();
 0)   2.478 us    |        }
 0)               |        strncpy_from_user() {
 0)               |          might_fault() {
 0)   1.389 us    |            __might_sleep();
 0)   2.553 us    |          }
 0)   3.807 us    |        }
 0)   7.876 us    |      }
 0)               |      alloc_fd() {
 0)   0.668 us    |        _spin_lock();
 0)   0.570 us    |        expand_files();
 0)   0.586 us    |        _spin_unlock();
 There are several columns that can be dynamically
 enabled/disabled. You can use every combination of options you
 want, depending on your needs.
 - The cpu number on which the function executed is default
  enabled.  It is sometimes better to only trace one cpu (see
  tracing_cpu_mask file) or you might sometimes see unordered
  function calls while cpu tracing switch.
 	hide: echo nofuncgraph-cpu > trace_options
 	show: echo funcgraph-cpu > trace_options
 - The duration (function's time of execution) is displayed on
  the closing bracket line of a function or on the same line
  than the current function in case of a leaf one. It is default
  enabled.
 	hide: echo nofuncgraph-duration > trace_options
 	show: echo funcgraph-duration > trace_options
 - The overhead field precedes the duration field in case of
  reached duration thresholds.
 	hide: echo nofuncgraph-overhead > trace_options
 	show: echo funcgraph-overhead > trace_options
 	depends on: funcgraph-duration
  ie:
  0)               |    up_write() {
  0)   0.646 us    |      _spin_lock_irqsave();
  0)   0.684 us    |      _spin_unlock_irqrestore();
  0)   3.123 us    |    }
  0)   0.548 us    |    fput();
  0) + 58.628 us   |  }
  [...]
  0)               |      putname() {
  0)               |        kmem_cache_free() {
  0)   0.518 us    |          __phys_addr();
  0)   1.757 us    |        }
  0)   2.861 us    |      }
  0) ! 115.305 us  |    }
  0) ! 116.402 us  |  }
  + means that the function exceeded 10 usecs.
  ! means that the function exceeded 100 usecs.
 - The task/pid field displays the thread cmdline and pid which
  executed the function. It is default disabled.
 	hide: echo nofuncgraph-proc > trace_options
 	show: echo funcgraph-proc > trace_options
  ie:
  # tracer: function_graph
  #
  # CPU  TASK/PID        DURATION                  FUNCTION CALLS
  # |    |    |           |   |                     |   |   |   |
  0)    sh-4802     |               |                  d_free() {
  0)    sh-4802     |               |                    call_rcu() {
  0)    sh-4802     |               |                      __call_rcu() {
  0)    sh-4802     |   0.616 us    |                        rcu_process_gp_end();
  0)    sh-4802     |   0.586 us    |                        check_for_new_grace_period();
  0)    sh-4802     |   2.899 us    |                      }
  0)    sh-4802     |   4.040 us    |                    }
  0)    sh-4802     |   5.151 us    |                  }
  0)    sh-4802     | + 49.370 us   |                }
 - The absolute time field is an absolute timestamp given by the
  system clock since it started. A snapshot of this time is
  given on each entry/exit of functions
 	hide: echo nofuncgraph-abstime > trace_options
 	show: echo funcgraph-abstime > trace_options
  ie:
  #
  #      TIME       CPU  DURATION                  FUNCTION CALLS
  #       |         |     |   |                     |   |   |   |
  360.774522 |   1)   0.541 us    |                                          }
  360.774522 |   1)   4.663 us    |                                        }
  360.774523 |   1)   0.541 us    |                                        __wake_up_bit();
  360.774524 |   1)   6.796 us    |                                      }
  360.774524 |   1)   7.952 us    |                                    }
  360.774525 |   1)   9.063 us    |                                  }
  360.774525 |   1)   0.615 us    |                                  journal_mark_dirty();
  360.774527 |   1)   0.578 us    |                                  __brelse();
  360.774528 |   1)               |                                  reiserfs_prepare_for_journal() {
  360.774528 |   1)               |                                    unlock_buffer() {
  360.774529 |   1)               |                                      wake_up_bit() {
  360.774529 |   1)               |                                        bit_waitqueue() {
  360.774530 |   1)   0.594 us    |                                          __phys_addr();
 You can put some comments on specific functions by using
 trace_printk() For example, if you want to put a comment inside
 the __might_sleep() function, you just have to include
 <linux/ftrace.h> and call trace_printk() inside __might_sleep()
 trace_printk("I'm a comment!\n")
 will produce:
 1)               |             __might_sleep() {
 1)               |                /* I'm a comment! */
 1)   1.449 us    |             }
 You might find other useful features for this tracer in the
 following "dynamic ftrace" section such as tracing only specific
 functions or tasks.
 dynamic ftrace
 --------------
 If CONFIG_DYNAMIC_FTRACE is set, the system will run with
 virtually no overhead when function tracing is disabled. The way
 this works is the mcount function call (placed at the start of
 every kernel function, produced by the -pg switch in gcc),
 starts of pointing to a simple return. (Enabling FTRACE will
 include the -pg switch in the compiling of the kernel.)
 At compile time every C file object is run through the
 recordmcount.pl script (located in the scripts directory). This
 script will process the C object using objdump to find all the
 locations in the .text section that call mcount. (Note, only the
 .text section is processed, since processing other sections like
 .init.text may cause races due to those sections being freed).
 A new section called "__mcount_loc" is created that holds
 references to all the mcount call sites in the .text section.
 This section is compiled back into the original object. The
 final linker will add all these references into a single table.
 On boot up, before SMP is initialized, the dynamic ftrace code
 scans this table and updates all the locations into nops. It
 also records the locations, which are added to the
 available_filter_functions list.  Modules are processed as they
 are loaded and before they are executed.  When a module is
 unloaded, it also removes its functions from the ftrace function
 list. This is automatic in the module unload code, and the
 module author does not need to worry about it.
 When tracing is enabled, kstop_machine is called to prevent
 races with the CPUS executing code being modified (which can
 cause the CPU to do undesireable things), and the nops are
 patched back to calls. But this time, they do not call mcount
 (which is just a function stub). They now call into the ftrace
 infrastructure.
 One special side-effect to the recording of the functions being
 traced is that we can now selectively choose which functions we
 wish to trace and which ones we want the mcount calls to remain
 as nops.
 Two files are used, one for enabling and one for disabling the
 tracing of specified functions. They are:
  set_ftrace_filter
 and
  set_ftrace_notrace
 A list of available functions that you can add to these files is
 listed in:
   available_filter_functions
 # cat available_filter_functions
 put_prev_task_idle
 kmem_cache_create
 pick_next_task_rt
 get_online_cpus
 pick_next_task_fair
 mutex_lock
 [...]
 If I am only interested in sys_nanosleep and hrtimer_interrupt:
 # echo sys_nanosleep hrtimer_interrupt \
 		> set_ftrace_filter
 # echo ftrace > current_tracer
 # echo 1 > tracing_enabled
 # usleep 1
 # echo 0 > tracing_enabled
 # cat trace
 # tracer: ftrace
 #
 #           TASK-PID   CPU#    TIMESTAMP  FUNCTION
 #              | |      |          |         |
          usleep-4134  [00]  1317.070017: hrtimer_interrupt <-smp_apic_timer_interrupt
          usleep-4134  [00]  1317.070111: sys_nanosleep <-syscall_call
          <idle>-0     [00]  1317.070115: hrtimer_interrupt <-smp_apic_timer_interrupt
 To see which functions are being traced, you can cat the file:
 # cat set_ftrace_filter
 hrtimer_interrupt
 sys_nanosleep
 Perhaps this is not enough. The filters also allow simple wild
 cards. Only the following are currently available
  <match>*  - will match functions that begin with <match>
  *<match>  - will match functions that end with <match>
  *<match>* - will match functions that have <match> in it
 These are the only wild cards which are supported.
  <match>*<match> will not work.
 Note: It is better to use quotes to enclose the wild cards,
      otherwise the shell may expand the parameters into names
      of files in the local directory.
 # echo 'hrtimer_*' > set_ftrace_filter
 Produces:
 # tracer: ftrace
 #
 #           TASK-PID   CPU#    TIMESTAMP  FUNCTION
 #              | |      |          |         |
            bash-4003  [00]  1480.611794: hrtimer_init <-copy_process
            bash-4003  [00]  1480.611941: hrtimer_start <-hrtick_set
            bash-4003  [00]  1480.611956: hrtimer_cancel <-hrtick_clear
            bash-4003  [00]  1480.611956: hrtimer_try_to_cancel <-hrtimer_cancel
          <idle>-0     [00]  1480.612019: hrtimer_get_next_event <-get_next_timer_interrupt
          <idle>-0     [00]  1480.612025: hrtimer_get_next_event <-get_next_timer_interrupt
          <idle>-0     [00]  1480.612032: hrtimer_get_next_event <-get_next_timer_interrupt
          <idle>-0     [00]  1480.612037: hrtimer_get_next_event <-get_next_timer_interrupt
          <idle>-0     [00]  1480.612382: hrtimer_get_next_event <-get_next_timer_interrupt
 Notice that we lost the sys_nanosleep.
 # cat set_ftrace_filter
 hrtimer_run_queues
 hrtimer_run_pending
 hrtimer_init
 hrtimer_cancel
 hrtimer_try_to_cancel
 hrtimer_forward
 hrtimer_start
 hrtimer_reprogram
 hrtimer_force_reprogram
 hrtimer_get_next_event
 hrtimer_interrupt
 hrtimer_nanosleep
 hrtimer_wakeup
 hrtimer_get_remaining
 hrtimer_get_res
 hrtimer_init_sleeper
 This is because the '>' and '>>' act just like they do in bash.
 To rewrite the filters, use '>'
 To append to the filters, use '>>'
 To clear out a filter so that all functions will be recorded
 again:
 # echo > set_ftrace_filter
 # cat set_ftrace_filter
 #
 Again, now we want to append.
 # echo sys_nanosleep > set_ftrace_filter
 # cat set_ftrace_filter
 sys_nanosleep
 # echo 'hrtimer_*' >> set_ftrace_filter
 # cat set_ftrace_filter
 hrtimer_run_queues
 hrtimer_run_pending
 hrtimer_init
 hrtimer_cancel
 hrtimer_try_to_cancel
 hrtimer_forward
 hrtimer_start
 hrtimer_reprogram
 hrtimer_force_reprogram
 hrtimer_get_next_event
 hrtimer_interrupt
 sys_nanosleep
 hrtimer_nanosleep
 hrtimer_wakeup
 hrtimer_get_remaining
 hrtimer_get_res
 hrtimer_init_sleeper
 The set_ftrace_notrace prevents those functions from being
 traced.
 # echo '*preempt*' '*lock*' > set_ftrace_notrace
 Produces:
 # tracer: ftrace
 #
 #           TASK-PID   CPU#    TIMESTAMP  FUNCTION
 #              | |      |          |         |
            bash-4043  [01]   115.281644: finish_task_switch <-schedule
            bash-4043  [01]   115.281645: hrtick_set <-schedule
            bash-4043  [01]   115.281645: hrtick_clear <-hrtick_set
            bash-4043  [01]   115.281646: wait_for_completion <-__stop_machine_run
            bash-4043  [01]   115.281647: wait_for_common <-wait_for_completion
            bash-4043  [01]   115.281647: kthread_stop <-stop_machine_run
            bash-4043  [01]   115.281648: init_waitqueue_head <-kthread_stop
            bash-4043  [01]   115.281648: wake_up_process <-kthread_stop
            bash-4043  [01]   115.281649: try_to_wake_up <-wake_up_process
 We can see that there's no more lock or preempt tracing.
 Dynamic ftrace with the function graph tracer
 ---------------------------------------------
 Although what has been explained above concerns both the
 function tracer and the function-graph-tracer, there are some
 special features only available in the function-graph tracer.
 If you want to trace only one function and all of its children,
 you just have to echo its name into set_graph_function:
 echo __do_fault > set_graph_function
 will produce the following "expanded" trace of the __do_fault()
 function:
 0)               |  __do_fault() {
 0)               |    filemap_fault() {
 0)               |      find_lock_page() {
 0)   0.804 us    |        find_get_page();
 0)               |        __might_sleep() {
 0)   1.329 us    |        }
 0)   3.904 us    |      }
 0)   4.979 us    |    }
 0)   0.653 us    |    _spin_lock();
 0)   0.578 us    |    page_add_file_rmap();
 0)   0.525 us    |    native_set_pte_at();
 0)   0.585 us    |    _spin_unlock();
 0)               |    unlock_page() {
 0)   0.541 us    |      page_waitqueue();
 0)   0.639 us    |      __wake_up_bit();
 0)   2.786 us    |    }
 0) + 14.237 us   |  }
 0)               |  __do_fault() {
 0)               |    filemap_fault() {
 0)               |      find_lock_page() {
 0)   0.698 us    |        find_get_page();
 0)               |        __might_sleep() {
 0)   1.412 us    |        }
 0)   3.950 us    |      }
 0)   5.098 us    |    }
 0)   0.631 us    |    _spin_lock();
 0)   0.571 us    |    page_add_file_rmap();
 0)   0.526 us    |    native_set_pte_at();
 0)   0.586 us    |    _spin_unlock();
 0)               |    unlock_page() {
 0)   0.533 us    |      page_waitqueue();
 0)   0.638 us    |      __wake_up_bit();
 0)   2.793 us    |    }
 0) + 14.012 us   |  }
 You can also expand several functions at once:
 echo sys_open > set_graph_function
 echo sys_close >> set_graph_function
 Now if you want to go back to trace all functions you can clear
 this special filter via:
 echo > set_graph_function
 trace_pipe
 ----------
 The trace_pipe outputs the same content as the trace file, but
 the effect on the tracing is different. Every read from
 trace_pipe is consumed. This means that subsequent reads will be
 different. The trace is live.
 # echo function > current_tracer
 # cat trace_pipe > /tmp/trace.out &
 [1] 4153
 # echo 1 > tracing_enabled
 # usleep 1
 # echo 0 > tracing_enabled
 # cat trace
 # tracer: function
 #
 #           TASK-PID   CPU#    TIMESTAMP  FUNCTION
 #              | |      |          |         |
 #
 # cat /tmp/trace.out
            bash-4043  [00] 41.267106: finish_task_switch <-schedule
            bash-4043  [00] 41.267106: hrtick_set <-schedule
            bash-4043  [00] 41.267107: hrtick_clear <-hrtick_set
            bash-4043  [00] 41.267108: wait_for_completion <-__stop_machine_run
            bash-4043  [00] 41.267108: wait_for_common <-wait_for_completion
            bash-4043  [00] 41.267109: kthread_stop <-stop_machine_run
            bash-4043  [00] 41.267109: init_waitqueue_head <-kthread_stop
            bash-4043  [00] 41.267110: wake_up_process <-kthread_stop
            bash-4043  [00] 41.267110: try_to_wake_up <-wake_up_process
            bash-4043  [00] 41.267111: select_task_rq_rt <-try_to_wake_up
 Note, reading the trace_pipe file will block until more input is
 added. By changing the tracer, trace_pipe will issue an EOF. We
 needed to set the function tracer _before_ we "cat" the
 trace_pipe file.
 trace entries
 -------------
 Having too much or not enough data can be troublesome in
 diagnosing an issue in the kernel. The file buffer_size_kb is
 used to modify the size of the internal trace buffers. The
 number listed is the number of entries that can be recorded per
 CPU. To know the full size, multiply the number of possible CPUS
 with the number of entries.
 # cat buffer_size_kb
 1408 (units kilobytes)
 Note, to modify this, you must have tracing completely disabled.
 To do that, echo "nop" into the current_tracer. If the
 current_tracer is not set to "nop", an EINVAL error will be
 returned.
 # echo nop > current_tracer
 # echo 10000 > buffer_size_kb
 # cat buffer_size_kb
 10000 (units kilobytes)
 The number of pages which will be allocated is limited to a
 percentage of available memory. Allocating too much will produce
 an error.
 # echo 1000000000000 > buffer_size_kb
 -bash: echo: write error: Cannot allocate memory
 # cat buffer_size_kb
 85
 -----------
 More details can be found in the source code, in the
 kernel/trace/*.c files.
 #
 # arch/arm/Makefile
 #
 # This file is included by the global makefile so that you can add your own
 # architecture-specific flags and dependencies.
 #
 # This file is subject to the terms and conditions of the GNU General Public
 # License.  See the file "COPYING" in the main directory of this archive
 # for more details.
 #
 # Copyright (C) 1995-2001 by Russell King
 LDFLAGS_vmlinux	:=-p --no-undefined -X
 ifeq ($(CONFIG_CPU_ENDIAN_BE8),y)
 LDFLAGS_vmlinux	+= --be8
 endif
 CPPFLAGS_vmlinux.lds = -DTEXT_OFFSET=$(TEXT_OFFSET)
 OBJCOPYFLAGS	:=-O binary -R .note -R .note.gnu.build-id -R .comment -S
 GZFLAGS		:=-9
 #KBUILD_CFLAGS	+=-pipe
 # Explicitly specifiy 32-bit ARM ISA since toolchain default can be -mthumb:
 KBUILD_CFLAGS	+=$(call cc-option,-marm,)
 # Do not use arch/arm/defconfig - it's always outdated.
 # Select a platform tht is kept up-to-date
 KBUILD_DEFCONFIG := versatile_defconfig
-# defines filename extension depending memory manement type.
+# defines filename extension depending memory management type.
 ifeq ($(CONFIG_MMU),)
 MMUEXT		:= -nommu
 endif
 ifeq ($(CONFIG_FRAME_POINTER),y)
 KBUILD_CFLAGS	+=-fno-omit-frame-pointer -mapcs -mno-sched-prolog
 endif
 ifeq ($(CONFIG_CPU_BIG_ENDIAN),y)
 KBUILD_CPPFLAGS	+= -mbig-endian
 AS		+= -EB
 LD		+= -EB
 else
 KBUILD_CPPFLAGS	+= -mlittle-endian
 AS		+= -EL
 LD		+= -EL
 endif
 comma = ,
 # This selects which instruction set is used.
 # Note that GCC does not numerically define an architecture version
 # macro, but instead defines a whole series of macros which makes
 # testing for a specific architecture or later rather impossible.
 arch-$(CONFIG_CPU_32v7)		:=-D__LINUX_ARM_ARCH__=7 $(call cc-option,-march=armv7-a,-march=armv5t -Wa$(comma)-march=armv7-a)
 arch-$(CONFIG_CPU_32v6)		:=-D__LINUX_ARM_ARCH__=6 $(call cc-option,-march=armv6,-march=armv5t -Wa$(comma)-march=armv6)
 # Only override the compiler option if ARMv6. The ARMv6K extensions are
 # always available in ARMv7
 ifeq ($(CONFIG_CPU_32v6),y)
 arch-$(CONFIG_CPU_32v6K)	:=-D__LINUX_ARM_ARCH__=6 $(call cc-option,-march=armv6k,-march=armv5t -Wa$(comma)-march=armv6k)
 endif
 arch-$(CONFIG_CPU_32v5)		:=-D__LINUX_ARM_ARCH__=5 $(call cc-option,-march=armv5te,-march=armv4t)
 arch-$(CONFIG_CPU_32v4T)	:=-D__LINUX_ARM_ARCH__=4 -march=armv4t
 arch-$(CONFIG_CPU_32v4)		:=-D__LINUX_ARM_ARCH__=4 -march=armv4
 arch-$(CONFIG_CPU_32v3)		:=-D__LINUX_ARM_ARCH__=3 -march=armv3
 # This selects how we optimise for the processor.
 tune-$(CONFIG_CPU_ARM610)	:=-mtune=arm610
 tune-$(CONFIG_CPU_ARM710)	:=-mtune=arm710
 tune-$(CONFIG_CPU_ARM7TDMI)	:=-mtune=arm7tdmi
 tune-$(CONFIG_CPU_ARM720T)	:=-mtune=arm7tdmi
 tune-$(CONFIG_CPU_ARM740T)	:=-mtune=arm7tdmi
 tune-$(CONFIG_CPU_ARM9TDMI)	:=-mtune=arm9tdmi
 tune-$(CONFIG_CPU_ARM940T)	:=-mtune=arm9tdmi
 tune-$(CONFIG_CPU_ARM946E)	:=$(call cc-option,-mtune=arm9e,-mtune=arm9tdmi)
 tune-$(CONFIG_CPU_ARM920T)	:=-mtune=arm9tdmi
 tune-$(CONFIG_CPU_ARM922T)	:=-mtune=arm9tdmi
 tune-$(CONFIG_CPU_ARM925T)	:=-mtune=arm9tdmi
 tune-$(CONFIG_CPU_ARM926T)	:=-mtune=arm9tdmi
 tune-$(CONFIG_CPU_FA526)	:=-mtune=arm9tdmi
 tune-$(CONFIG_CPU_SA110)	:=-mtune=strongarm110
 tune-$(CONFIG_CPU_SA1100)	:=-mtune=strongarm1100
 tune-$(CONFIG_CPU_XSCALE)	:=$(call cc-option,-mtune=xscale,-mtune=strongarm110) -Wa,-mcpu=xscale
 tune-$(CONFIG_CPU_XSC3)		:=$(call cc-option,-mtune=xscale,-mtune=strongarm110) -Wa,-mcpu=xscale
 tune-$(CONFIG_CPU_FEROCEON)	:=$(call cc-option,-mtune=marvell-f,-mtune=xscale)
 tune-$(CONFIG_CPU_V6)		:=$(call cc-option,-mtune=arm1136j-s,-mtune=strongarm)
 ifeq ($(CONFIG_AEABI),y)
 CFLAGS_ABI	:=-mabi=aapcs-linux -mno-thumb-interwork
 else
 CFLAGS_ABI	:=$(call cc-option,-mapcs-32,-mabi=apcs-gnu) $(call cc-option,-mno-thumb-interwork,)
 endif
 ifeq ($(CONFIG_ARM_UNWIND),y)
 CFLAGS_ABI	+=-funwind-tables
 endif
 ifeq ($(CONFIG_THUMB2_KERNEL),y)
 AFLAGS_AUTOIT	:=$(call as-option,-Wa$(comma)-mimplicit-it=thumb,-Wa$(comma)-mauto-it)
 AFLAGS_NOWARN	:=$(call as-option,-Wa$(comma)-mno-warn-deprecated,-Wa$(comma)-W)
 CFLAGS_THUMB2	:=-mthumb $(AFLAGS_AUTOIT) $(AFLAGS_NOWARN)
 AFLAGS_THUMB2	:=$(CFLAGS_THUMB2) -Wa$(comma)-mthumb
 endif
 # Need -Uarm for gcc < 3.x
 KBUILD_CFLAGS	+=$(CFLAGS_ABI) $(CFLAGS_THUMB2) $(arch-y) $(tune-y) $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) -msoft-float -Uarm
 KBUILD_AFLAGS	+=$(CFLAGS_ABI) $(AFLAGS_THUMB2) $(arch-y) $(tune-y) -include asm/unified.h -msoft-float
 CHECKFLAGS	+= -D__arm__
 #Default value
 head-y		:= arch/arm/kernel/head$(MMUEXT).o arch/arm/kernel/init_task.o
 textofs-y	:= 0x00008000
 textofs-$(CONFIG_ARCH_CLPS711X) := 0x00028000
 # SA1111 DMA bug: we don't want the kernel to live in precious DMA-able memory
 ifeq ($(CONFIG_ARCH_SA1100),y)
 textofs-$(CONFIG_SA1111) := 0x00208000
 endif
 # Machine directory name.  This list is sorted alphanumerically
 # by CONFIG_* macro name.
 machine-$(CONFIG_ARCH_AAEC2000)		:= aaec2000
 machine-$(CONFIG_ARCH_AT91)		:= at91
 machine-$(CONFIG_ARCH_BCMRING)		:= bcmring
 machine-$(CONFIG_ARCH_CLPS711X)		:= clps711x
 machine-$(CONFIG_ARCH_DAVINCI)		:= davinci
 machine-$(CONFIG_ARCH_EBSA110)		:= ebsa110
 machine-$(CONFIG_ARCH_EP93XX)		:= ep93xx
 machine-$(CONFIG_ARCH_GEMINI)		:= gemini
 machine-$(CONFIG_ARCH_H720X)		:= h720x
 machine-$(CONFIG_ARCH_INTEGRATOR)	:= integrator
 machine-$(CONFIG_ARCH_IOP13XX)		:= iop13xx
 machine-$(CONFIG_ARCH_IOP32X)		:= iop32x
 machine-$(CONFIG_ARCH_IOP33X)		:= iop33x
 machine-$(CONFIG_ARCH_IXP2000)		:= ixp2000
 machine-$(CONFIG_ARCH_IXP23XX)		:= ixp23xx
 machine-$(CONFIG_ARCH_IXP4XX)		:= ixp4xx
 machine-$(CONFIG_ARCH_KIRKWOOD)		:= kirkwood
 machine-$(CONFIG_ARCH_KS8695)		:= ks8695
 machine-$(CONFIG_ARCH_L7200)		:= l7200
 machine-$(CONFIG_ARCH_LH7A40X)		:= lh7a40x
 machine-$(CONFIG_ARCH_LOKI) 		:= loki
 machine-$(CONFIG_ARCH_MMP)		:= mmp
 machine-$(CONFIG_ARCH_MSM)		:= msm
 machine-$(CONFIG_ARCH_MV78XX0)		:= mv78xx0
 machine-$(CONFIG_ARCH_MX1)		:= mx1
 machine-$(CONFIG_ARCH_MX2)		:= mx2
 machine-$(CONFIG_ARCH_MX25)		:= mx25
 machine-$(CONFIG_ARCH_MX3)		:= mx3
 machine-$(CONFIG_ARCH_NETX)		:= netx
 machine-$(CONFIG_ARCH_NOMADIK)		:= nomadik
 machine-$(CONFIG_ARCH_NS9XXX)		:= ns9xxx
 machine-$(CONFIG_ARCH_OMAP1)		:= omap1
 machine-$(CONFIG_ARCH_OMAP2)		:= omap2
 machine-$(CONFIG_ARCH_OMAP3)		:= omap2
 machine-$(CONFIG_ARCH_OMAP4)		:= omap2
 machine-$(CONFIG_ARCH_ORION5X)		:= orion5x
 machine-$(CONFIG_ARCH_PNX4008)		:= pnx4008
 machine-$(CONFIG_ARCH_PXA)		:= pxa
 machine-$(CONFIG_ARCH_REALVIEW)		:= realview
 machine-$(CONFIG_ARCH_RPC)		:= rpc
 machine-$(CONFIG_ARCH_S3C2410)		:= s3c2410 s3c2400 s3c2412 s3c2440 s3c2442 s3c2443
 machine-$(CONFIG_ARCH_S3C24A0)		:= s3c24a0
 machine-$(CONFIG_ARCH_S3C64XX)		:= s3c6400 s3c6410
 machine-$(CONFIG_ARCH_S5PC1XX)		:= s5pc100
 machine-$(CONFIG_ARCH_SA1100)		:= sa1100
 machine-$(CONFIG_ARCH_SHARK)		:= shark
 machine-$(CONFIG_ARCH_STMP378X)		:= stmp378x
 machine-$(CONFIG_ARCH_STMP37XX)		:= stmp37xx
 machine-$(CONFIG_ARCH_U300)		:= u300
 machine-$(CONFIG_ARCH_VERSATILE)	:= versatile
 machine-$(CONFIG_ARCH_W90X900)		:= w90x900
 machine-$(CONFIG_FOOTBRIDGE)		:= footbridge
 machine-$(CONFIG_ARCH_MXC91231)		:= mxc91231
 # Platform directory name.  This list is sorted alphanumerically
 # by CONFIG_* macro name.
 plat-$(CONFIG_ARCH_MXC)		:= mxc
 plat-$(CONFIG_ARCH_OMAP)	:= omap
 plat-$(CONFIG_PLAT_IOP)		:= iop
 plat-$(CONFIG_PLAT_ORION)	:= orion
 plat-$(CONFIG_PLAT_PXA)		:= pxa
 plat-$(CONFIG_PLAT_S3C24XX)	:= s3c24xx s3c
 plat-$(CONFIG_PLAT_S3C64XX)	:= s3c64xx s3c
 plat-$(CONFIG_PLAT_S5PC1XX)	:= s5pc1xx s3c
 plat-$(CONFIG_ARCH_STMP3XXX)	:= stmp3xxx
 ifeq ($(CONFIG_ARCH_EBSA110),y)
 # This is what happens if you forget the IOCS16 line.
 # PCMCIA cards stop working.
 CFLAGS_3c589_cs.o :=-DISA_SIXTEEN_BIT_PERIPHERAL
 export CFLAGS_3c589_cs.o
 endif
 # The byte offset of the kernel image in RAM from the start of RAM.
 TEXT_OFFSET := $(textofs-y)
 # The first directory contains additional information for the boot setup code
 ifneq ($(machine-y),)
 MACHINE  := arch/arm/mach-$(word 1,$(machine-y))/
 else
 MACHINE  :=
 endif
 machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
 platdirs := $(patsubst %,arch/arm/plat-%/,$(plat-y))
 ifeq ($(KBUILD_SRC),)
 KBUILD_CPPFLAGS += $(patsubst %,-I%include,$(machdirs) $(platdirs))
 else
 KBUILD_CPPFLAGS += $(patsubst %,-I$(srctree)/%include,$(machdirs) $(platdirs))
 endif
 export	TEXT_OFFSET GZFLAGS MMUEXT
 # Do we have FASTFPE?
 FASTFPE		:=arch/arm/fastfpe
 ifeq ($(FASTFPE),$(wildcard $(FASTFPE)))
 FASTFPE_OBJ	:=$(FASTFPE)/
 endif
 # If we have a machine-specific directory, then include it in the build.
 core-y				+= arch/arm/kernel/ arch/arm/mm/ arch/arm/common/
 core-y				+= $(machdirs) $(platdirs)
 core-$(CONFIG_FPE_NWFPE)	+= arch/arm/nwfpe/
 core-$(CONFIG_FPE_FASTFPE)	+= $(FASTFPE_OBJ)
 core-$(CONFIG_VFP)		+= arch/arm/vfp/
 drivers-$(CONFIG_OPROFILE)      += arch/arm/oprofile/
 libs-y				:= arch/arm/lib/ $(libs-y)
 # Default target when executing plain make
 ifeq ($(CONFIG_XIP_KERNEL),y)
 KBUILD_IMAGE := xipImage
 else
 KBUILD_IMAGE := zImage
 endif
 all:	$(KBUILD_IMAGE)
 boot := arch/arm/boot
 #	Update machine arch and proc symlinks if something which affects
 #	them changed.  We use .arch to indicate when they were updated
 #	last, otherwise make uses the target directory mtime.
 archprepare: maketools
 PHONY += maketools FORCE
 maketools: include/linux/version.h FORCE
 	$(Q)$(MAKE) $(build)=arch/arm/tools include/asm-arm/mach-types.h
 # Convert bzImage to zImage
 bzImage: zImage
 zImage Image xipImage bootpImage uImage: vmlinux
 	$(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $(boot)/$@
 zinstall install: vmlinux
 	$(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $@
 CLEAN_FILES += include/asm-arm/mach-types.h \
 	       include/asm-arm/arch include/asm-arm/.arch
 # We use MRPROPER_FILES and CLEAN_FILES now
 archclean:
 	$(Q)$(MAKE) $(clean)=$(boot)
 # My testing targets (bypasses dependencies)
 bp:;	$(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $(boot)/bootpImage
 i zi:;	$(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $@
 define archhelp
  echo  '* zImage        - Compressed kernel image (arch/$(ARCH)/boot/zImage)'
  echo  '  Image         - Uncompressed kernel image (arch/$(ARCH)/boot/Image)'
  echo  '* xipImage      - XIP kernel image, if configured (arch/$(ARCH)/boot/xipImage)'
  echo  '  uImage        - U-Boot wrapped zImage'
  echo  '  bootpImage    - Combined zImage and initial RAM disk' 
  echo  '                  (supply initrd image via make variable INITRD=<path>)'
  echo  '  install       - Install uncompressed kernel'
  echo  '  zinstall      - Install compressed kernel'
  echo  '                  Install using (your) ~/bin/installkernel or'
  echo  '                  (distribution) /sbin/installkernel or'
  echo  '                  install to $$(INSTALL_PATH) and run lilo'
 endef
-/* cache.S: cache managment routines
+/* cache.S: cache management routines
 *
 * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
 * Written by David Howells (dhowells@redhat.com)
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */
 #include <asm/spr-regs.h>
 #include <asm/cache.h>
        .text
        .p2align	4
 ###############################################################################
 #
 # Write back a range of dcache
 # - void frv_dcache_writeback(unsigned long start [GR8], unsigned long size [GR9])
 #
 ###############################################################################
        .globl		frv_dcache_writeback
        .type		frv_dcache_writeback,@function
 frv_dcache_writeback:
 	andi		gr8,~(L1_CACHE_BYTES-1),gr8
 2:	dcf		@(gr8,gr0)
 	addi		gr8,#L1_CACHE_BYTES,gr8
 	cmp		gr9,gr8,icc0
 	bhi		icc0,#2,2b
 	membar
 	bralr
 	.size		frv_dcache_writeback, .-frv_dcache_writeback
 ##############################################################################
 #
 # Invalidate a range of dcache and icache
 # - void frv_cache_invalidate(unsigned long start [GR8], unsigned long end [GR9]);
 #
 ###############################################################################
        .globl		frv_cache_invalidate
        .type		frv_cache_invalidate,@function
 frv_cache_invalidate:
 	andi		gr8,~(L1_CACHE_BYTES-1),gr8
 2:	dci		@(gr8,gr0)
 	ici		@(gr8,gr0)
 	addi		gr8,#L1_CACHE_BYTES,gr8
 	cmp		gr9,gr8,icc0
 	bhi		icc0,#2,2b
 	membar
 	bralr
 	.size		frv_cache_invalidate, .-frv_cache_invalidate
 ##############################################################################
 #
 # Invalidate a range of icache
 # - void frv_icache_invalidate(unsigned long start [GR8], unsigned long end [GR9]);
 #
 ###############################################################################
        .globl		frv_icache_invalidate
        .type		frv_icache_invalidate,@function
 frv_icache_invalidate:
 	andi		gr8,~(L1_CACHE_BYTES-1),gr8
 2:	ici		@(gr8,gr0)
 	addi		gr8,#L1_CACHE_BYTES,gr8
 	cmp		gr9,gr8,icc0
 	bhi		icc0,#2,2b
 	membar
 	bralr
 	.size		frv_icache_invalidate, .-frv_icache_invalidate
 ###############################################################################
 #
 # Write back and invalidate a range of dcache and icache
 # - void frv_cache_wback_inv(unsigned long start [GR8], unsigned long end [GR9])
 #
 ###############################################################################
        .globl		frv_cache_wback_inv
        .type		frv_cache_wback_inv,@function
 frv_cache_wback_inv:
 	andi		gr8,~(L1_CACHE_BYTES-1),gr8
 2:	dcf		@(gr8,gr0)
 	ici		@(gr8,gr0)
 	addi		gr8,#L1_CACHE_BYTES,gr8
 	cmp		gr9,gr8,icc0
 	bhi		icc0,#2,2b
 	membar
 	bralr
 	.size		frv_cache_wback_inv, .-frv_cache_wback_inv
 /* MN10300 Cache flushing
 *
 * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
 * Written by David Howells (dhowells@redhat.com)
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public Licence
 * as published by the Free Software Foundation; either version
 * 2 of the Licence, or (at your option) any later version.
 */
 #ifndef _ASM_CACHEFLUSH_H
 #define _ASM_CACHEFLUSH_H
 #ifndef __ASSEMBLY__
 /* Keep includes the same across arches.  */
 #include <linux/mm.h>
 /*
- * virtually-indexed cache managment (our cache is physically indexed)
+ * virtually-indexed cache management (our cache is physically indexed)
 */
 #define flush_cache_all()			do {} while (0)
 #define flush_cache_mm(mm)			do {} while (0)
 #define flush_cache_dup_mm(mm)			do {} while (0)
 #define flush_cache_range(mm, start, end)	do {} while (0)
 #define flush_cache_page(vma, vmaddr, pfn)	do {} while (0)
 #define flush_cache_vmap(start, end)		do {} while (0)
 #define flush_cache_vunmap(start, end)		do {} while (0)
 #define flush_dcache_page(page)			do {} while (0)
 #define flush_dcache_mmap_lock(mapping)		do {} while (0)
 #define flush_dcache_mmap_unlock(mapping)	do {} while (0)
 /*
- * physically-indexed cache managment
+ * physically-indexed cache management
 */
 #ifndef CONFIG_MN10300_CACHE_DISABLED
 extern void flush_icache_range(unsigned long start, unsigned long end);
 extern void flush_icache_page(struct vm_area_struct *vma, struct page *pg);
 #else
 #define flush_icache_range(start, end)		do {} while (0)
 #define flush_icache_page(vma, pg)		do {} while (0)
 #endif
 #define flush_icache_user_range(vma, pg, adr, len) \
 	flush_icache_range(adr, adr + len)
 #define copy_to_user_page(vma, page, vaddr, dst, src, len) \
 	do {					\
 		memcpy(dst, src, len);		\
 		flush_icache_page(vma, page);	\
 	} while (0)
 #define copy_from_user_page(vma, page, vaddr, dst, src, len) \
 	memcpy(dst, src, len)
 /*
 * primitive routines
 */
 #ifndef CONFIG_MN10300_CACHE_DISABLED
 extern void mn10300_icache_inv(void);
 extern void mn10300_dcache_inv(void);
 extern void mn10300_dcache_inv_page(unsigned start);
 extern void mn10300_dcache_inv_range(unsigned start, unsigned end);
 extern void mn10300_dcache_inv_range2(unsigned start, unsigned size);
 #ifdef CONFIG_MN10300_CACHE_WBACK
 extern void mn10300_dcache_flush(void);
 extern void mn10300_dcache_flush_page(unsigned start);
 extern void mn10300_dcache_flush_range(unsigned start, unsigned end);
 extern void mn10300_dcache_flush_range2(unsigned start, unsigned size);
 extern void mn10300_dcache_flush_inv(void);
 extern void mn10300_dcache_flush_inv_page(unsigned start);
 extern void mn10300_dcache_flush_inv_range(unsigned start, unsigned end);
 extern void mn10300_dcache_flush_inv_range2(unsigned start, unsigned size);
 #else
 #define mn10300_dcache_flush()				do {} while (0)
 #define mn10300_dcache_flush_page(start)		do {} while (0)
 #define mn10300_dcache_flush_range(start, end)		do {} while (0)
 #define mn10300_dcache_flush_range2(start, size)	do {} while (0)
 #define mn10300_dcache_flush_inv()			mn10300_dcache_inv()
 #define mn10300_dcache_flush_inv_page(start) \
 	mn10300_dcache_inv_page((start))
 #define mn10300_dcache_flush_inv_range(start, end) \
 	mn10300_dcache_inv_range((start), (end))
 #define mn10300_dcache_flush_inv_range2(start, size) \
 	mn10300_dcache_inv_range2((start), (size))
 #endif /* CONFIG_MN10300_CACHE_WBACK */
 #else
 #define mn10300_icache_inv()				do {} while (0)
 #define mn10300_dcache_inv()				do {} while (0)
 #define mn10300_dcache_inv_page(start)			do {} while (0)
 #define mn10300_dcache_inv_range(start, end)		do {} while (0)
 #define mn10300_dcache_inv_range2(start, size)		do {} while (0)
 #define mn10300_dcache_flush()				do {} while (0)
 #define mn10300_dcache_flush_inv_page(start)		do {} while (0)
 #define mn10300_dcache_flush_inv()			do {} while (0)
 #define mn10300_dcache_flush_inv_range(start, end)	do {} while (0)
 #define mn10300_dcache_flush_inv_range2(start, size)	do {} while (0)
 #define mn10300_dcache_flush_page(start)		do {} while (0)
 #define mn10300_dcache_flush_range(start, end)		do {} while (0)
 #define mn10300_dcache_flush_range2(start, size)	do {} while (0)
 #endif /* CONFIG_MN10300_CACHE_DISABLED */
 /*
 * internal debugging function
 */
 #ifdef CONFIG_DEBUG_PAGEALLOC
 extern void kernel_map_pages(struct page *page, int numpages, int enable);
 #endif
 #endif /* __ASSEMBLY__ */
 #endif /* _ASM_CACHEFLUSH_H */
 /*
 *  Siano core API module
 *
 *  This file contains implementation for the interface to sms core component
 *
 *  author: Uri Shkolnik
 *
 *  Copyright (c), 2005-2008 Siano Mobile Silicon, Inc.
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License version 2 as
 *  published by the Free Software Foundation;
 *
 *  Software distributed under the License is distributed on an "AS IS"
 *  basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.
 *
 *  See the GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; if not, write to the Free Software
 *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/module.h>
 #include <linux/moduleparam.h>
 #include <linux/dma-mapping.h>
 #include <linux/delay.h>
 #include <linux/io.h>
 #include <linux/firmware.h>
 #include <linux/wait.h>
 #include <asm/byteorder.h>
 #include "smscoreapi.h"
 #include "sms-cards.h"
 #include "smsir.h"
 #include "smsendian.h"
 static int sms_dbg;
 module_param_named(debug, sms_dbg, int, 0644);
 MODULE_PARM_DESC(debug, "set debug level (info=1, adv=2 (or-able))");
 struct smscore_device_notifyee_t {
 	struct list_head entry;
 	hotplug_t hotplug;
 };
 struct smscore_idlist_t {
 	struct list_head entry;
 	int		id;
 	int		data_type;
 };
 struct smscore_client_t {
 	struct list_head entry;
 	struct smscore_device_t *coredev;
 	void			*context;
 	struct list_head 	idlist;
 	onresponse_t	onresponse_handler;
 	onremove_t		onremove_handler;
 };
 void smscore_set_board_id(struct smscore_device_t *core, int id)
 {
 	core->board_id = id;
 }
 int smscore_led_state(struct smscore_device_t *core, int led)
 {
 	if (led >= 0)
 		core->led_state = led;
 	return core->led_state;
 }
 EXPORT_SYMBOL_GPL(smscore_set_board_id);
 int smscore_get_board_id(struct smscore_device_t *core)
 {
 	return core->board_id;
 }
 EXPORT_SYMBOL_GPL(smscore_get_board_id);
 struct smscore_registry_entry_t {
 	struct list_head entry;
 	char			devpath[32];
 	int				mode;
 	enum sms_device_type_st	type;
 };
 static struct list_head g_smscore_notifyees;
 static struct list_head g_smscore_devices;
 static struct mutex g_smscore_deviceslock;
 static struct list_head g_smscore_registry;
 static struct mutex g_smscore_registrylock;
 static int default_mode = 4;
 module_param(default_mode, int, 0644);
 MODULE_PARM_DESC(default_mode, "default firmware id (device mode)");
 static struct smscore_registry_entry_t *smscore_find_registry(char *devpath)
 {
 	struct smscore_registry_entry_t *entry;
 	struct list_head *next;
 	kmutex_lock(&g_smscore_registrylock);
 	for (next = g_smscore_registry.next;
 	     next != &g_smscore_registry;
 	     next = next->next) {
 		entry = (struct smscore_registry_entry_t *) next;
 		if (!strcmp(entry->devpath, devpath)) {
 			kmutex_unlock(&g_smscore_registrylock);
 			return entry;
 		}
 	}
 	entry = (struct smscore_registry_entry_t *)
 			kmalloc(sizeof(struct smscore_registry_entry_t),
 				GFP_KERNEL);
 	if (entry) {
 		entry->mode = default_mode;
 		strcpy(entry->devpath, devpath);
 		list_add(&entry->entry, &g_smscore_registry);
 	} else
 		sms_err("failed to create smscore_registry.");
 	kmutex_unlock(&g_smscore_registrylock);
 	return entry;
 }
 int smscore_registry_getmode(char *devpath)
 {
 	struct smscore_registry_entry_t *entry;
 	entry = smscore_find_registry(devpath);
 	if (entry)
 		return entry->mode;
 	else
 		sms_err("No registry found.");
 	return default_mode;
 }
 EXPORT_SYMBOL_GPL(smscore_registry_getmode);
 static enum sms_device_type_st smscore_registry_gettype(char *devpath)
 {
 	struct smscore_registry_entry_t *entry;
 	entry = smscore_find_registry(devpath);
 	if (entry)
 		return entry->type;
 	else
 		sms_err("No registry found.");
 	return -1;
 }
 void smscore_registry_setmode(char *devpath, int mode)
 {
 	struct smscore_registry_entry_t *entry;
 	entry = smscore_find_registry(devpath);
 	if (entry)
 		entry->mode = mode;
 	else
 		sms_err("No registry found.");
 }
 static void smscore_registry_settype(char *devpath,
 				     enum sms_device_type_st type)
 {
 	struct smscore_registry_entry_t *entry;
 	entry = smscore_find_registry(devpath);
 	if (entry)
 		entry->type = type;
 	else
 		sms_err("No registry found.");
 }
 static void list_add_locked(struct list_head *new, struct list_head *head,
 			    spinlock_t *lock)
 {
 	unsigned long flags;
 	spin_lock_irqsave(lock, flags);
 	list_add(new, head);
 	spin_unlock_irqrestore(lock, flags);
 }
 /**
 * register a client callback that called when device plugged in/unplugged
 * NOTE: if devices exist callback is called immediately for each device
 *
 * @param hotplug callback
 *
 * @return 0 on success, <0 on error.
 */
 int smscore_register_hotplug(hotplug_t hotplug)
 {
 	struct smscore_device_notifyee_t *notifyee;
 	struct list_head *next, *first;
 	int rc = 0;
 	kmutex_lock(&g_smscore_deviceslock);
 	notifyee = kmalloc(sizeof(struct smscore_device_notifyee_t),
 			   GFP_KERNEL);
 	if (notifyee) {
 		/* now notify callback about existing devices */
 		first = &g_smscore_devices;
 		for (next = first->next;
 		     next != first && !rc;
 		     next = next->next) {
 			struct smscore_device_t *coredev =
 				(struct smscore_device_t *) next;
 			rc = hotplug(coredev, coredev->device, 1);
 		}
 		if (rc >= 0) {
 			notifyee->hotplug = hotplug;
 			list_add(&notifyee->entry, &g_smscore_notifyees);
 		} else
 			kfree(notifyee);
 	} else
 		rc = -ENOMEM;
 	kmutex_unlock(&g_smscore_deviceslock);
 	return rc;
 }
 EXPORT_SYMBOL_GPL(smscore_register_hotplug);
 /**
 * unregister a client callback that called when device plugged in/unplugged
 *
 * @param hotplug callback
 *
 */
 void smscore_unregister_hotplug(hotplug_t hotplug)
 {
 	struct list_head *next, *first;
 	kmutex_lock(&g_smscore_deviceslock);
 	first = &g_smscore_notifyees;
 	for (next = first->next; next != first;) {
 		struct smscore_device_notifyee_t *notifyee =
 			(struct smscore_device_notifyee_t *) next;
 		next = next->next;
 		if (notifyee->hotplug == hotplug) {
 			list_del(&notifyee->entry);
 			kfree(notifyee);
 		}
 	}
 	kmutex_unlock(&g_smscore_deviceslock);
 }
 EXPORT_SYMBOL_GPL(smscore_unregister_hotplug);
 static void smscore_notify_clients(struct smscore_device_t *coredev)
 {
 	struct smscore_client_t *client;
 	/* the client must call smscore_unregister_client from remove handler */
 	while (!list_empty(&coredev->clients)) {
 		client = (struct smscore_client_t *) coredev->clients.next;
 		client->onremove_handler(client->context);
 	}
 }
 static int smscore_notify_callbacks(struct smscore_device_t *coredev,
 				    struct device *device, int arrival)
 {
 	struct list_head *next, *first;
 	int rc = 0;
 	/* note: must be called under g_deviceslock */
 	first = &g_smscore_notifyees;
 	for (next = first->next; next != first; next = next->next) {
 		rc = ((struct smscore_device_notifyee_t *) next)->
 				hotplug(coredev, device, arrival);
 		if (rc < 0)
 			break;
 	}
 	return rc;
 }
 static struct
 smscore_buffer_t *smscore_createbuffer(u8 *buffer, void *common_buffer,
 				       dma_addr_t common_buffer_phys)
 {
 	struct smscore_buffer_t *cb =
 		kmalloc(sizeof(struct smscore_buffer_t), GFP_KERNEL);
 	if (!cb) {
 		sms_info("kmalloc(...) failed");
 		return NULL;
 	}
 	cb->p = buffer;
 	cb->offset_in_common = buffer - (u8 *) common_buffer;
 	cb->phys = common_buffer_phys + cb->offset_in_common;
 	return cb;
 }
 /**
 * creates coredev object for a device, prepares buffers,
 * creates buffer mappings, notifies registered hotplugs about new device.
 *
 * @param params device pointer to struct with device specific parameters
 *               and handlers
 * @param coredev pointer to a value that receives created coredev object
 *
 * @return 0 on success, <0 on error.
 */
 int smscore_register_device(struct smsdevice_params_t *params,
 			    struct smscore_device_t **coredev)
 {
 	struct smscore_device_t *dev;
 	u8 *buffer;
 	dev = kzalloc(sizeof(struct smscore_device_t), GFP_KERNEL);
 	if (!dev) {
 		sms_info("kzalloc(...) failed");
 		return -ENOMEM;
 	}
 	/* init list entry so it could be safe in smscore_unregister_device */
 	INIT_LIST_HEAD(&dev->entry);
 	/* init queues */
 	INIT_LIST_HEAD(&dev->clients);
 	INIT_LIST_HEAD(&dev->buffers);
 	/* init locks */
 	spin_lock_init(&dev->clientslock);
 	spin_lock_init(&dev->bufferslock);
 	/* init completion events */
 	init_completion(&dev->version_ex_done);
 	init_completion(&dev->data_download_done);
 	init_completion(&dev->trigger_done);
 	init_completion(&dev->init_device_done);
 	init_completion(&dev->reload_start_done);
 	init_completion(&dev->resume_done);
 	init_completion(&dev->gpio_configuration_done);
 	init_completion(&dev->gpio_set_level_done);
 	init_completion(&dev->gpio_get_level_done);
 	init_completion(&dev->ir_init_done);
 	/* Buffer management */
 	init_waitqueue_head(&dev->buffer_mng_waitq);
 	/* alloc common buffer */
 	dev->common_buffer_size = params->buffer_size * params->num_buffers;
 	dev->common_buffer = dma_alloc_coherent(NULL, dev->common_buffer_size,
 						&dev->common_buffer_phys,
 						GFP_KERNEL | GFP_DMA);
 	if (!dev->common_buffer) {
 		smscore_unregister_device(dev);
 		return -ENOMEM;
 	}
 	/* prepare dma buffers */
 	for (buffer = dev->common_buffer;
 	     dev->num_buffers < params->num_buffers;
 	     dev->num_buffers++, buffer += params->buffer_size) {
 		struct smscore_buffer_t *cb =
 			smscore_createbuffer(buffer, dev->common_buffer,
 					     dev->common_buffer_phys);
 		if (!cb) {
 			smscore_unregister_device(dev);
 			return -ENOMEM;
 		}
 		smscore_putbuffer(dev, cb);
 	}
 	sms_info("allocated %d buffers", dev->num_buffers);
 	dev->mode = DEVICE_MODE_NONE;
 	dev->context = params->context;
 	dev->device = params->device;
 	dev->setmode_handler = params->setmode_handler;
 	dev->detectmode_handler = params->detectmode_handler;
 	dev->sendrequest_handler = params->sendrequest_handler;
 	dev->preload_handler = params->preload_handler;
 	dev->postload_handler = params->postload_handler;
 	dev->device_flags = params->flags;
 	strcpy(dev->devpath, params->devpath);
 	smscore_registry_settype(dev->devpath, params->device_type);
 	/* add device to devices list */
 	kmutex_lock(&g_smscore_deviceslock);
 	list_add(&dev->entry, &g_smscore_devices);
 	kmutex_unlock(&g_smscore_deviceslock);
 	*coredev = dev;
 	sms_info("device %p created", dev);
 	return 0;
 }
 EXPORT_SYMBOL_GPL(smscore_register_device);
 static int smscore_sendrequest_and_wait(struct smscore_device_t *coredev,
 		void *buffer, size_t size, struct completion *completion) {
 	int rc = coredev->sendrequest_handler(coredev->context, buffer, size);
 	if (rc < 0) {
 		sms_info("sendrequest returned error %d", rc);
 		return rc;
 	}
 	return wait_for_completion_timeout(completion,
 			msecs_to_jiffies(SMS_PROTOCOL_MAX_RAOUNDTRIP_MS)) ?
 			0 : -ETIME;
 }
 /**
 * Starts & enables IR operations
 *
 * @return 0 on success, < 0 on error.
 */
 static int smscore_init_ir(struct smscore_device_t *coredev)
 {
 	int ir_io;
 	int rc;
 	void *buffer;
 	coredev->ir.input_dev = NULL;
 	ir_io = sms_get_board(smscore_get_board_id(coredev))->board_cfg.ir;
 	if (ir_io) {/* only if IR port exist we use IR sub-module */
 		sms_info("IR loading");
 		rc = sms_ir_init(coredev);
 		if	(rc != 0)
 			sms_err("Error initialization DTV IR sub-module");
 		else {
 			buffer = kmalloc(sizeof(struct SmsMsgData_ST2) +
 						SMS_DMA_ALIGNMENT,
 						GFP_KERNEL | GFP_DMA);
 			if (buffer) {
 				struct SmsMsgData_ST2 *msg =
 				(struct SmsMsgData_ST2 *)
 				SMS_ALIGN_ADDRESS(buffer);
 				SMS_INIT_MSG(&msg->xMsgHeader,
 						MSG_SMS_START_IR_REQ,
 						sizeof(struct SmsMsgData_ST2));
 				msg->msgData[0] = coredev->ir.controller;
 				msg->msgData[1] = coredev->ir.timeout;
 				smsendian_handle_tx_message(
 					(struct SmsMsgHdr_ST2 *)msg);
 				rc = smscore_sendrequest_and_wait(coredev, msg,
 						msg->xMsgHeader. msgLength,
 						&coredev->ir_init_done);
 				kfree(buffer);
 			} else
 				sms_err
 				("Sending IR initialization message failed");
 		}
 	} else
 		sms_info("IR port has not been detected");
 	return 0;
 }
 /**
 * sets initial device mode and notifies client hotplugs that device is ready
 *
 * @param coredev pointer to a coredev object returned by
 * 		  smscore_register_device
 *
 * @return 0 on success, <0 on error.
 */
 int smscore_start_device(struct smscore_device_t *coredev)
 {
 	int rc = smscore_set_device_mode(
 			coredev, smscore_registry_getmode(coredev->devpath));
 	if (rc < 0) {
 		sms_info("set device mode faile , rc %d", rc);
 		return rc;
 	}
 	kmutex_lock(&g_smscore_deviceslock);
 	rc = smscore_notify_callbacks(coredev, coredev->device, 1);
 	smscore_init_ir(coredev);
 	sms_info("device %p started, rc %d", coredev, rc);
 	kmutex_unlock(&g_smscore_deviceslock);
 	return rc;
 }
 EXPORT_SYMBOL_GPL(smscore_start_device);
 static int smscore_load_firmware_family2(struct smscore_device_t *coredev,
 					 void *buffer, size_t size)
 {
 	struct SmsFirmware_ST *firmware = (struct SmsFirmware_ST *) buffer;
 	struct SmsMsgHdr_ST *msg;
 	u32 mem_address;
 	u8 *payload = firmware->Payload;
 	int rc = 0;
 	firmware->StartAddress = le32_to_cpu(firmware->StartAddress);
 	firmware->Length = le32_to_cpu(firmware->Length);
 	mem_address = firmware->StartAddress;
 	sms_info("loading FW to addr 0x%x size %d",
 		 mem_address, firmware->Length);
 	if (coredev->preload_handler) {
 		rc = coredev->preload_handler(coredev->context);
 		if (rc < 0)
 			return rc;
 	}
 	/* PAGE_SIZE buffer shall be enough and dma aligned */
 	msg = kmalloc(PAGE_SIZE, GFP_KERNEL | GFP_DMA);
 	if (!msg)
 		return -ENOMEM;
 	if (coredev->mode != DEVICE_MODE_NONE) {
 		sms_debug("sending reload command.");
 		SMS_INIT_MSG(msg, MSG_SW_RELOAD_START_REQ,
 			     sizeof(struct SmsMsgHdr_ST));
 		rc = smscore_sendrequest_and_wait(coredev, msg,
 						  msg->msgLength,
 						  &coredev->reload_start_done);
 		mem_address = *(u32 *) &payload[20];
 	}
 	while (size && rc >= 0) {
 		struct SmsDataDownload_ST *DataMsg =
 			(struct SmsDataDownload_ST *) msg;
 		int payload_size = min((int) size, SMS_MAX_PAYLOAD_SIZE);
 		SMS_INIT_MSG(msg, MSG_SMS_DATA_DOWNLOAD_REQ,
 			     (u16)(sizeof(struct SmsMsgHdr_ST) +
 				      sizeof(u32) + payload_size));
 		DataMsg->MemAddr = mem_address;
 		memcpy(DataMsg->Payload, payload, payload_size);
 		if ((coredev->device_flags & SMS_ROM_NO_RESPONSE) &&
 		    (coredev->mode == DEVICE_MODE_NONE))
 			rc = coredev->sendrequest_handler(
 				coredev->context, DataMsg,
 				DataMsg->xMsgHeader.msgLength);
 		else
 			rc = smscore_sendrequest_and_wait(
 				coredev, DataMsg,
 				DataMsg->xMsgHeader.msgLength,
 				&coredev->data_download_done);
 		payload += payload_size;
 		size -= payload_size;
 		mem_address += payload_size;
 	}
 	if (rc >= 0) {
 		if (coredev->mode == DEVICE_MODE_NONE) {
 			struct SmsMsgData_ST *TriggerMsg =
 				(struct SmsMsgData_ST *) msg;
 			SMS_INIT_MSG(msg, MSG_SMS_SWDOWNLOAD_TRIGGER_REQ,
 				     sizeof(struct SmsMsgHdr_ST) +
 				     sizeof(u32) * 5);
 			TriggerMsg->msgData[0] = firmware->StartAddress;
 						/* Entry point */
 			TriggerMsg->msgData[1] = 5; /* Priority */
 			TriggerMsg->msgData[2] = 0x200; /* Stack size */
 			TriggerMsg->msgData[3] = 0; /* Parameter */
 			TriggerMsg->msgData[4] = 4; /* Task ID */
 			if (coredev->device_flags & SMS_ROM_NO_RESPONSE) {
 				rc = coredev->sendrequest_handler(
 					coredev->context, TriggerMsg,
 					TriggerMsg->xMsgHeader.msgLength);
 				msleep(100);
 			} else
 				rc = smscore_sendrequest_and_wait(
 					coredev, TriggerMsg,
 					TriggerMsg->xMsgHeader.msgLength,
 					&coredev->trigger_done);
 		} else {
 			SMS_INIT_MSG(msg, MSG_SW_RELOAD_EXEC_REQ,
 				     sizeof(struct SmsMsgHdr_ST));
 			rc = coredev->sendrequest_handler(coredev->context,
 							  msg, msg->msgLength);
 		}
 		msleep(500);
 	}
 	sms_debug("rc=%d, postload=%p ", rc,
 		  coredev->postload_handler);
 	kfree(msg);
 	return ((rc >= 0) && coredev->postload_handler) ?
 		coredev->postload_handler(coredev->context) :
 		rc;
 }
 /**
 * loads specified firmware into a buffer and calls device loadfirmware_handler
 *
 * @param coredev pointer to a coredev object returned by
 *                smscore_register_device
 * @param filename null-terminated string specifies firmware file name
 * @param loadfirmware_handler device handler that loads firmware
 *
 * @return 0 on success, <0 on error.
 */
 static int smscore_load_firmware_from_file(struct smscore_device_t *coredev,
 					   char *filename,
 					   loadfirmware_t loadfirmware_handler)
 {
 	int rc = -ENOENT;
 	const struct firmware *fw;
 	u8 *fw_buffer;
 	if (loadfirmware_handler == NULL && !(coredev->device_flags &
 					      SMS_DEVICE_FAMILY2))
 		return -EINVAL;
 	rc = request_firmware(&fw, filename, coredev->device);
 	if (rc < 0) {
 		sms_info("failed to open \"%s\"", filename);
 		return rc;
 	}
 	sms_info("read FW %s, size=%zd", filename, fw->size);
 	fw_buffer = kmalloc(ALIGN(fw->size, SMS_ALLOC_ALIGNMENT),
 			    GFP_KERNEL | GFP_DMA);
 	if (fw_buffer) {
 		memcpy(fw_buffer, fw->data, fw->size);
 		rc = (coredev->device_flags & SMS_DEVICE_FAMILY2) ?
 		      smscore_load_firmware_family2(coredev,
 						    fw_buffer,
 						    fw->size) :
 		      loadfirmware_handler(coredev->context,
 					   fw_buffer, fw->size);
 		kfree(fw_buffer);
 	} else {
 		sms_info("failed to allocate firmware buffer");
 		rc = -ENOMEM;
 	}
 	release_firmware(fw);
 	return rc;
 }
 /**
 * notifies all clients registered with the device, notifies hotplugs,
 * frees all buffers and coredev object
 *
 * @param coredev pointer to a coredev object returned by
 *                smscore_register_device
 *
 * @return 0 on success, <0 on error.
 */
 void smscore_unregister_device(struct smscore_device_t *coredev)
 {
 	struct smscore_buffer_t *cb;
 	int num_buffers = 0;
 	int retry = 0;
 	kmutex_lock(&g_smscore_deviceslock);
 	/* Release input device (IR) resources */
 	sms_ir_exit(coredev);
 	smscore_notify_clients(coredev);
 	smscore_notify_callbacks(coredev, NULL, 0);
 	/* at this point all buffers should be back
 	 * onresponse must no longer be called */
 	while (1) {
 		while (!list_empty(&coredev->buffers)) {
 			cb = (struct smscore_buffer_t *) coredev->buffers.next;
 			list_del(&cb->entry);
 			kfree(cb);
 			num_buffers++;
 		}
 		if (num_buffers == coredev->num_buffers)
 			break;
 		if (++retry > 10) {
 			sms_info("exiting although "
 				 "not all buffers released.");
 			break;
 		}
 		sms_info("waiting for %d buffer(s)",
 			 coredev->num_buffers - num_buffers);
 		msleep(100);
 	}
 	sms_info("freed %d buffers", num_buffers);
 	if (coredev->common_buffer)
 		dma_free_coherent(NULL, coredev->common_buffer_size,
 			coredev->common_buffer, coredev->common_buffer_phys);
 	if (coredev->fw_buf != NULL)
 		kfree(coredev->fw_buf);
 	list_del(&coredev->entry);
 	kfree(coredev);
 	kmutex_unlock(&g_smscore_deviceslock);
 	sms_info("device %p destroyed", coredev);
 }
 EXPORT_SYMBOL_GPL(smscore_unregister_device);
 static int smscore_detect_mode(struct smscore_device_t *coredev)
 {
 	void *buffer = kmalloc(sizeof(struct SmsMsgHdr_ST) + SMS_DMA_ALIGNMENT,
 			       GFP_KERNEL | GFP_DMA);
 	struct SmsMsgHdr_ST *msg =
 		(struct SmsMsgHdr_ST *) SMS_ALIGN_ADDRESS(buffer);
 	int rc;
 	if (!buffer)
 		return -ENOMEM;
 	SMS_INIT_MSG(msg, MSG_SMS_GET_VERSION_EX_REQ,
 		     sizeof(struct SmsMsgHdr_ST));
 	rc = smscore_sendrequest_and_wait(coredev, msg, msg->msgLength,
 					  &coredev->version_ex_done);
 	if (rc == -ETIME) {
 		sms_err("MSG_SMS_GET_VERSION_EX_REQ failed first try");
 		if (wait_for_completion_timeout(&coredev->resume_done,
 						msecs_to_jiffies(5000))) {
 			rc = smscore_sendrequest_and_wait(
 				coredev, msg, msg->msgLength,
 				&coredev->version_ex_done);
 			if (rc < 0)
 				sms_err("MSG_SMS_GET_VERSION_EX_REQ failed "
 					"second try, rc %d", rc);
 		} else
 			rc = -ETIME;
 	}
 	kfree(buffer);
 	return rc;
 }
 static char *smscore_fw_lkup[][SMS_NUM_OF_DEVICE_TYPES] = {
 	/*Stellar		NOVA A0		Nova B0		VEGA*/
 	/*DVBT*/
 	{"none", "dvb_nova_12mhz.inp", "dvb_nova_12mhz_b0.inp", "none"},
 	/*DVBH*/
 	{"none", "dvb_nova_12mhz.inp", "dvb_nova_12mhz_b0.inp", "none"},
 	/*TDMB*/
 	{"none", "tdmb_nova_12mhz.inp", "tdmb_nova_12mhz_b0.inp", "none"},
 	/*DABIP*/
 	{"none", "none", "none", "none"},
 	/*BDA*/
 	{"none", "dvb_nova_12mhz.inp", "dvb_nova_12mhz_b0.inp", "none"},
 	/*ISDBT*/
 	{"none", "isdbt_nova_12mhz.inp", "isdbt_nova_12mhz_b0.inp", "none"},
 	/*ISDBTBDA*/
 	{"none", "isdbt_nova_12mhz.inp", "isdbt_nova_12mhz_b0.inp", "none"},
 	/*CMMB*/
 	{"none", "none", "none", "cmmb_vega_12mhz.inp"}
 };
 static inline char *sms_get_fw_name(struct smscore_device_t *coredev,
 				    int mode, enum sms_device_type_st type)
 {
 	char **fw = sms_get_board(smscore_get_board_id(coredev))->fw;
 	return (fw && fw[mode]) ? fw[mode] : smscore_fw_lkup[mode][type];
 }
 /**
 * calls device handler to change mode of operation
 * NOTE: stellar/usb may disconnect when changing mode
 *
 * @param coredev pointer to a coredev object returned by
 *                smscore_register_device
 * @param mode requested mode of operation
 *
 * @return 0 on success, <0 on error.
 */
 int smscore_set_device_mode(struct smscore_device_t *coredev, int mode)
 {
 	void *buffer;
 	int rc = 0;
 	enum sms_device_type_st type;
 	sms_debug("set device mode to %d", mode);
 	if (coredev->device_flags & SMS_DEVICE_FAMILY2) {
 		if (mode < DEVICE_MODE_DVBT || mode >= DEVICE_MODE_RAW_TUNER) {
 			sms_err("invalid mode specified %d", mode);
 			return -EINVAL;
 		}
 		smscore_registry_setmode(coredev->devpath, mode);
 		if (!(coredev->device_flags & SMS_DEVICE_NOT_READY)) {
 			rc = smscore_detect_mode(coredev);
 			if (rc < 0) {
 				sms_err("mode detect failed %d", rc);
 				return rc;
 			}
 		}
 		if (coredev->mode == mode) {
 			sms_info("device mode %d already set", mode);
 			return 0;
 		}
 		if (!(coredev->modes_supported & (1 << mode))) {
 			char *fw_filename;
 			type = smscore_registry_gettype(coredev->devpath);
 			fw_filename = sms_get_fw_name(coredev, mode, type);
 			rc = smscore_load_firmware_from_file(coredev,
 							     fw_filename, NULL);
 			if (rc < 0) {
 				sms_warn("error %d loading firmware: %s, "
 					 "trying again with default firmware",
 					 rc, fw_filename);
 				/* try again with the default firmware */
 				fw_filename = smscore_fw_lkup[mode][type];
 				rc = smscore_load_firmware_from_file(coredev,
 							     fw_filename, NULL);
 				if (rc < 0) {
 					sms_warn("error %d loading "
 						 "firmware: %s", rc,
 						 fw_filename);
 					return rc;
 				}
 			}
 			sms_log("firmware download success: %s", fw_filename);
 		} else
 			sms_info("mode %d supported by running "
 				 "firmware", mode);
 		buffer = kmalloc(sizeof(struct SmsMsgData_ST) +
 				 SMS_DMA_ALIGNMENT, GFP_KERNEL | GFP_DMA);
 		if (buffer) {
 			struct SmsMsgData_ST *msg =
 				(struct SmsMsgData_ST *)
 					SMS_ALIGN_ADDRESS(buffer);
 			SMS_INIT_MSG(&msg->xMsgHeader, MSG_SMS_INIT_DEVICE_REQ,
 				     sizeof(struct SmsMsgData_ST));
 			msg->msgData[0] = mode;
 			rc = smscore_sendrequest_and_wait(
 				coredev, msg, msg->xMsgHeader.msgLength,
 				&coredev->init_device_done);
 			kfree(buffer);
 		} else {
 			sms_err("Could not allocate buffer for "
 				"init device message.");
 			rc = -ENOMEM;
 		}
 	} else {
 		if (mode < DEVICE_MODE_DVBT || mode > DEVICE_MODE_DVBT_BDA) {
 			sms_err("invalid mode specified %d", mode);
 			return -EINVAL;
 		}
 		smscore_registry_setmode(coredev->devpath, mode);
 		if (coredev->detectmode_handler)
 			coredev->detectmode_handler(coredev->context,
 						    &coredev->mode);
 		if (coredev->mode != mode && coredev->setmode_handler)
 			rc = coredev->setmode_handler(coredev->context, mode);
 	}
 	if (rc >= 0) {
 		coredev->mode = mode;
 		coredev->device_flags &= ~SMS_DEVICE_NOT_READY;
 	}
 	if (rc < 0)
 		sms_err("return error code %d.", rc);
 	return rc;
 }
 /**
 * calls device handler to get current mode of operation
 *
 * @param coredev pointer to a coredev object returned by
 *                smscore_register_device
 *
 * @return current mode
 */
 int smscore_get_device_mode(struct smscore_device_t *coredev)
 {
 	return coredev->mode;
 }
 EXPORT_SYMBOL_GPL(smscore_get_device_mode);
 /**
 * find client by response id & type within the clients list.
 * return client handle or NULL.
 *
 * @param coredev pointer to a coredev object returned by
 *                smscore_register_device
 * @param data_type client data type (SMS_DONT_CARE for all types)
 * @param id client id (SMS_DONT_CARE for all id)
 *
 */
 static struct
 smscore_client_t *smscore_find_client(struct smscore_device_t *coredev,
 				      int data_type, int id)
 {
 	struct smscore_client_t *client = NULL;
 	struct list_head *next, *first;
 	unsigned long flags;
 	struct list_head *firstid, *nextid;
 	spin_lock_irqsave(&coredev->clientslock, flags);
 	first = &coredev->clients;
 	for (next = first->next;
 	     (next != first) && !client;
 	     next = next->next) {
 		firstid = &((struct smscore_client_t *)next)->idlist;
 		for (nextid = firstid->next;
 		     nextid != firstid;
 		     nextid = nextid->next) {
 			if ((((struct smscore_idlist_t *)nextid)->id == id) &&
 			    (((struct smscore_idlist_t *)nextid)->data_type == data_type ||
 			    (((struct smscore_idlist_t *)nextid)->data_type == 0))) {
 				client = (struct smscore_client_t *) next;
 				break;
 			}
 		}
 	}
 	spin_unlock_irqrestore(&coredev->clientslock, flags);
 	return client;
 }
 /**
 * find client by response id/type, call clients onresponse handler
 * return buffer to pool on error
 *
 * @param coredev pointer to a coredev object returned by
 *                smscore_register_device
 * @param cb pointer to response buffer descriptor
 *
 */
 void smscore_onresponse(struct smscore_device_t *coredev,
 		struct smscore_buffer_t *cb) {
 	struct SmsMsgHdr_ST *phdr = (struct SmsMsgHdr_ST *) ((u8 *) cb->p
 			+ cb->offset);
 	struct smscore_client_t *client;
 	int rc = -EBUSY;
 	static unsigned long last_sample_time; /* = 0; */
 	static int data_total; /* = 0; */
 	unsigned long time_now = jiffies_to_msecs(jiffies);
 	if (!last_sample_time)
 		last_sample_time = time_now;
 	if (time_now - last_sample_time > 10000) {
 		sms_debug("\ndata rate %d bytes/secs",
 			  (int)((data_total * 1000) /
 				(time_now - last_sample_time)));
 		last_sample_time = time_now;
 		data_total = 0;
 	}
 	data_total += cb->size;
 	/* Do we need to re-route? */
 	if ((phdr->msgType == MSG_SMS_HO_PER_SLICES_IND) ||
 			(phdr->msgType == MSG_SMS_TRANSMISSION_IND)) {
 		if (coredev->mode == DEVICE_MODE_DVBT_BDA)
 			phdr->msgDstId = DVBT_BDA_CONTROL_MSG_ID;
 	}
 	client = smscore_find_client(coredev, phdr->msgType, phdr->msgDstId);
 	/* If no client registered for type & id,
 	 * check for control client where type is not registered */
 	if (client)
 		rc = client->onresponse_handler(client->context, cb);
 	if (rc < 0) {
 		switch (phdr->msgType) {
 		case MSG_SMS_GET_VERSION_EX_RES:
 		{
 			struct SmsVersionRes_ST *ver =
 				(struct SmsVersionRes_ST *) phdr;
 			sms_debug("MSG_SMS_GET_VERSION_EX_RES "
 				  "id %d prots 0x%x ver %d.%d",
 				  ver->FirmwareId, ver->SupportedProtocols,
 				  ver->RomVersionMajor, ver->RomVersionMinor);
 			coredev->mode = ver->FirmwareId == 255 ?
 				DEVICE_MODE_NONE : ver->FirmwareId;
 			coredev->modes_supported = ver->SupportedProtocols;
 			complete(&coredev->version_ex_done);
 			break;
 		}
 		case MSG_SMS_INIT_DEVICE_RES:
 			sms_debug("MSG_SMS_INIT_DEVICE_RES");
 			complete(&coredev->init_device_done);
 			break;
 		case MSG_SW_RELOAD_START_RES:
 			sms_debug("MSG_SW_RELOAD_START_RES");
 			complete(&coredev->reload_start_done);
 			break;
 		case MSG_SMS_DATA_DOWNLOAD_RES:
 			complete(&coredev->data_download_done);
 			break;
 		case MSG_SW_RELOAD_EXEC_RES:
 			sms_debug("MSG_SW_RELOAD_EXEC_RES");
 			break;
 		case MSG_SMS_SWDOWNLOAD_TRIGGER_RES:
 			sms_debug("MSG_SMS_SWDOWNLOAD_TRIGGER_RES");
 			complete(&coredev->trigger_done);
 			break;
 		case MSG_SMS_SLEEP_RESUME_COMP_IND:
 			complete(&coredev->resume_done);
 			break;
 		case MSG_SMS_GPIO_CONFIG_EX_RES:
 			sms_debug("MSG_SMS_GPIO_CONFIG_EX_RES");
 			complete(&coredev->gpio_configuration_done);
 			break;
 		case MSG_SMS_GPIO_SET_LEVEL_RES:
 			sms_debug("MSG_SMS_GPIO_SET_LEVEL_RES");
 			complete(&coredev->gpio_set_level_done);
 			break;
 		case MSG_SMS_GPIO_GET_LEVEL_RES:
 		{
 			u32 *msgdata = (u32 *) phdr;
 			coredev->gpio_get_res = msgdata[1];
 			sms_debug("MSG_SMS_GPIO_GET_LEVEL_RES gpio level %d",
 					coredev->gpio_get_res);
 			complete(&coredev->gpio_get_level_done);
 			break;
 		}
 		case MSG_SMS_START_IR_RES:
 			complete(&coredev->ir_init_done);
 			break;
 		case MSG_SMS_IR_SAMPLES_IND:
 			sms_ir_event(coredev,
 				(const char *)
 				((char *)phdr
 				+ sizeof(struct SmsMsgHdr_ST)),
 				(int)phdr->msgLength
 				- sizeof(struct SmsMsgHdr_ST));
 			break;
 		default:
 			break;
 		}
 		smscore_putbuffer(coredev, cb);
 	}
 }
 EXPORT_SYMBOL_GPL(smscore_onresponse);
 /**
 * return pointer to next free buffer descriptor from core pool
 *
 * @param coredev pointer to a coredev object returned by
 *                smscore_register_device
 *
 * @return pointer to descriptor on success, NULL on error.
 */
 struct smscore_buffer_t *smscore_getbuffer(struct smscore_device_t *coredev)
 {
 	struct smscore_buffer_t *cb = NULL;
 	unsigned long flags;
 	DEFINE_WAIT(wait);
 	spin_lock_irqsave(&coredev->bufferslock, flags);
 	/* This function must return a valid buffer, since the buffer list is
 	 * finite, we check that there is an available buffer, if not, we wait
 	 * until such buffer become available.
 	 */
 	prepare_to_wait(&coredev->buffer_mng_waitq, &wait, TASK_INTERRUPTIBLE);
 	if (list_empty(&coredev->buffers))
 		schedule();
 	finish_wait(&coredev->buffer_mng_waitq, &wait);
 	cb = (struct smscore_buffer_t *) coredev->buffers.next;
 	list_del(&cb->entry);
 	spin_unlock_irqrestore(&coredev->bufferslock, flags);
 	return cb;
 }
 EXPORT_SYMBOL_GPL(smscore_getbuffer);
 /**
 * return buffer descriptor to a pool
 *
 * @param coredev pointer to a coredev object returned by
 *                smscore_register_device
 * @param cb pointer buffer descriptor
 *
 */
 void smscore_putbuffer(struct smscore_device_t *coredev,
 		struct smscore_buffer_t *cb) {
 	wake_up_interruptible(&coredev->buffer_mng_waitq);
 	list_add_locked(&cb->entry, &coredev->buffers, &coredev->bufferslock);
 }
 EXPORT_SYMBOL_GPL(smscore_putbuffer);
 static int smscore_validate_client(struct smscore_device_t *coredev,
 				   struct smscore_client_t *client,
 				   int data_type, int id)
 {
 	struct smscore_idlist_t *listentry;
 	struct smscore_client_t *registered_client;
 	if (!client) {
 		sms_err("bad parameter.");
 		return -EFAULT;
 	}
 	registered_client = smscore_find_client(coredev, data_type, id);
 	if (registered_client == client)
 		return 0;
 	if (registered_client) {
 		sms_err("The msg ID already registered to another client.");
 		return -EEXIST;
 	}
 	listentry = kzalloc(sizeof(struct smscore_idlist_t), GFP_KERNEL);
 	if (!listentry) {
 		sms_err("Can't allocate memory for client id.");
 		return -ENOMEM;
 	}
 	listentry->id = id;
 	listentry->data_type = data_type;
 	list_add_locked(&listentry->entry, &client->idlist,
 			&coredev->clientslock);
 	return 0;
 }
 /**
 * creates smsclient object, check that id is taken by another client
 *
 * @param coredev pointer to a coredev object from clients hotplug
 * @param initial_id all messages with this id would be sent to this client
 * @param data_type all messages of this type would be sent to this client
 * @param onresponse_handler client handler that is called to
 *                           process incoming messages
 * @param onremove_handler client handler that is called when device is removed
 * @param context client-specific context
 * @param client pointer to a value that receives created smsclient object
 *
 * @return 0 on success, <0 on error.
 */
 int smscore_register_client(struct smscore_device_t *coredev,
 			    struct smsclient_params_t *params,
 			    struct smscore_client_t **client)
 {
 	struct smscore_client_t *newclient;
 	/* check that no other channel with same parameters exists */
 	if (smscore_find_client(coredev, params->data_type,
 				params->initial_id)) {
 		sms_err("Client already exist.");
 		return -EEXIST;
 	}
 	newclient = kzalloc(sizeof(struct smscore_client_t), GFP_KERNEL);
 	if (!newclient) {
 		sms_err("Failed to allocate memory for client.");
 		return -ENOMEM;
 	}
 	INIT_LIST_HEAD(&newclient->idlist);
 	newclient->coredev = coredev;
 	newclient->onresponse_handler = params->onresponse_handler;
 	newclient->onremove_handler = params->onremove_handler;
 	newclient->context = params->context;
 	list_add_locked(&newclient->entry, &coredev->clients,
 			&coredev->clientslock);
 	smscore_validate_client(coredev, newclient, params->data_type,
 				params->initial_id);
 	*client = newclient;
 	sms_debug("%p %d %d", params->context, params->data_type,
 		  params->initial_id);
 	return 0;
 }
 EXPORT_SYMBOL_GPL(smscore_register_client);
 /**
 * frees smsclient object and all subclients associated with it
 *
 * @param client pointer to smsclient object returned by
 *               smscore_register_client
 *
 */
 void smscore_unregister_client(struct smscore_client_t *client)
 {
 	struct smscore_device_t *coredev = client->coredev;
 	unsigned long flags;
 	spin_lock_irqsave(&coredev->clientslock, flags);
 	while (!list_empty(&client->idlist)) {
 		struct smscore_idlist_t *identry =
 			(struct smscore_idlist_t *) client->idlist.next;
 		list_del(&identry->entry);
 		kfree(identry);
 	}
 	sms_info("%p", client->context);
 	list_del(&client->entry);
 	kfree(client);
 	spin_unlock_irqrestore(&coredev->clientslock, flags);
 }
 EXPORT_SYMBOL_GPL(smscore_unregister_client);
 /**
 * verifies that source id is not taken by another client,
 * calls device handler to send requests to the device
 *
 * @param client pointer to smsclient object returned by
 *               smscore_register_client
 * @param buffer pointer to a request buffer
 * @param size size (in bytes) of request buffer
 *
 * @return 0 on success, <0 on error.
 */
 int smsclient_sendrequest(struct smscore_client_t *client,
 			  void *buffer, size_t size)
 {
 	struct smscore_device_t *coredev;
 	struct SmsMsgHdr_ST *phdr = (struct SmsMsgHdr_ST *) buffer;
 	int rc;
 	if (client == NULL) {
 		sms_err("Got NULL client");
 		return -EINVAL;
 	}
 	coredev = client->coredev;
 	/* check that no other channel with same id exists */
 	if (coredev == NULL) {
 		sms_err("Got NULL coredev");
 		return -EINVAL;
 	}
 	rc = smscore_validate_client(client->coredev, client, 0,
 				     phdr->msgSrcId);
 	if (rc < 0)
 		return rc;
 	return coredev->sendrequest_handler(coredev->context, buffer, size);
 }
 EXPORT_SYMBOL_GPL(smsclient_sendrequest);
 /* old GPIO managments implementation */
 int smscore_configure_gpio(struct smscore_device_t *coredev, u32 pin,
 			   struct smscore_config_gpio *pinconfig)
 {
 	struct {
 		struct SmsMsgHdr_ST hdr;
 		u32 data[6];
 	} msg;
 	if (coredev->device_flags & SMS_DEVICE_FAMILY2) {
 		msg.hdr.msgSrcId = DVBT_BDA_CONTROL_MSG_ID;
 		msg.hdr.msgDstId = HIF_TASK;
 		msg.hdr.msgFlags = 0;
 		msg.hdr.msgType  = MSG_SMS_GPIO_CONFIG_EX_REQ;
 		msg.hdr.msgLength = sizeof(msg);
 		msg.data[0] = pin;
 		msg.data[1] = pinconfig->pullupdown;
 		/* Convert slew rate for Nova: Fast(0) = 3 / Slow(1) = 0; */
 		msg.data[2] = pinconfig->outputslewrate == 0 ? 3 : 0;
 		switch (pinconfig->outputdriving) {
 		case SMS_GPIO_OUTPUTDRIVING_16mA:
 			msg.data[3] = 7; /* Nova - 16mA */
 			break;
 		case SMS_GPIO_OUTPUTDRIVING_12mA:
 			msg.data[3] = 5; /* Nova - 11mA */
 			break;
 		case SMS_GPIO_OUTPUTDRIVING_8mA:
 			msg.data[3] = 3; /* Nova - 7mA */
 			break;
 		case SMS_GPIO_OUTPUTDRIVING_4mA:
 		default:
 			msg.data[3] = 2; /* Nova - 4mA */
 			break;
 		}
 		msg.data[4] = pinconfig->direction;
 		msg.data[5] = 0;
 	} else /* TODO: SMS_DEVICE_FAMILY1 */
 		return -EINVAL;
 	return coredev->sendrequest_handler(coredev->context,
 					    &msg, sizeof(msg));
 }
 int smscore_set_gpio(struct smscore_device_t *coredev, u32 pin, int level)
 {
 	struct {
 		struct SmsMsgHdr_ST hdr;
 		u32 data[3];
 	} msg;
 	if (pin > MAX_GPIO_PIN_NUMBER)
 		return -EINVAL;
 	msg.hdr.msgSrcId = DVBT_BDA_CONTROL_MSG_ID;
 	msg.hdr.msgDstId = HIF_TASK;
 	msg.hdr.msgFlags = 0;
 	msg.hdr.msgType  = MSG_SMS_GPIO_SET_LEVEL_REQ;
 	msg.hdr.msgLength = sizeof(msg);
 	msg.data[0] = pin;
 	msg.data[1] = level ? 1 : 0;
 	msg.data[2] = 0;
 	return coredev->sendrequest_handler(coredev->context,
 					    &msg, sizeof(msg));
 }
-/* new GPIO managment implementation */
+/* new GPIO management implementation */
 static int GetGpioPinParams(u32 PinNum, u32 *pTranslatedPinNum,
 		u32 *pGroupNum, u32 *pGroupCfg) {
 	*pGroupCfg = 1;
 	if (PinNum >= 0 && PinNum <= 1)	{
 		*pTranslatedPinNum = 0;
 		*pGroupNum = 9;
 		*pGroupCfg = 2;
 	} else if (PinNum >= 2 && PinNum <= 6) {
 		*pTranslatedPinNum = 2;
 		*pGroupNum = 0;
 		*pGroupCfg = 2;
 	} else if (PinNum >= 7 && PinNum <= 11) {
 		*pTranslatedPinNum = 7;
 		*pGroupNum = 1;
 	} else if (PinNum >= 12 && PinNum <= 15) {
 		*pTranslatedPinNum = 12;
 		*pGroupNum = 2;
 		*pGroupCfg = 3;
 	} else if (PinNum == 16) {
 		*pTranslatedPinNum = 16;
 		*pGroupNum = 23;
 	} else if (PinNum >= 17 && PinNum <= 24) {
 		*pTranslatedPinNum = 17;
 		*pGroupNum = 3;
 	} else if (PinNum == 25) {
 		*pTranslatedPinNum = 25;
 		*pGroupNum = 6;
 	} else if (PinNum >= 26 && PinNum <= 28) {
 		*pTranslatedPinNum = 26;
 		*pGroupNum = 4;
 	} else if (PinNum == 29) {
 		*pTranslatedPinNum = 29;
 		*pGroupNum = 5;
 		*pGroupCfg = 2;
 	} else if (PinNum == 30) {
 		*pTranslatedPinNum = 30;
 		*pGroupNum = 8;
 	} else if (PinNum == 31) {
 		*pTranslatedPinNum = 31;
 		*pGroupNum = 17;
 	} else
 		return -1;
 	*pGroupCfg <<= 24;
 	return 0;
 }
 int smscore_gpio_configure(struct smscore_device_t *coredev, u8 PinNum,
 		struct smscore_gpio_config *pGpioConfig) {
 	u32 totalLen;
 	u32 TranslatedPinNum = 0;
 	u32 GroupNum = 0;
 	u32 ElectricChar;
 	u32 groupCfg;
 	void *buffer;
 	int rc;
 	struct SetGpioMsg {
 		struct SmsMsgHdr_ST xMsgHeader;
 		u32 msgData[6];
 	} *pMsg;
 	if (PinNum > MAX_GPIO_PIN_NUMBER)
 		return -EINVAL;
 	if (pGpioConfig == NULL)
 		return -EINVAL;
 	totalLen = sizeof(struct SmsMsgHdr_ST) + (sizeof(u32) * 6);
 	buffer = kmalloc(totalLen + SMS_DMA_ALIGNMENT,
 			GFP_KERNEL | GFP_DMA);
 	if (!buffer)
 		return -ENOMEM;
 	pMsg = (struct SetGpioMsg *) SMS_ALIGN_ADDRESS(buffer);
 	pMsg->xMsgHeader.msgSrcId = DVBT_BDA_CONTROL_MSG_ID;
 	pMsg->xMsgHeader.msgDstId = HIF_TASK;
 	pMsg->xMsgHeader.msgFlags = 0;
 	pMsg->xMsgHeader.msgLength = (u16) totalLen;
 	pMsg->msgData[0] = PinNum;
 	if (!(coredev->device_flags & SMS_DEVICE_FAMILY2)) {
 		pMsg->xMsgHeader.msgType = MSG_SMS_GPIO_CONFIG_REQ;
 		if (GetGpioPinParams(PinNum, &TranslatedPinNum, &GroupNum,
 				&groupCfg) != 0)
 			return -EINVAL;
 		pMsg->msgData[1] = TranslatedPinNum;
 		pMsg->msgData[2] = GroupNum;
 		ElectricChar = (pGpioConfig->PullUpDown)
 				| (pGpioConfig->InputCharacteristics << 2)
 				| (pGpioConfig->OutputSlewRate << 3)
 				| (pGpioConfig->OutputDriving << 4);
 		pMsg->msgData[3] = ElectricChar;
 		pMsg->msgData[4] = pGpioConfig->Direction;
 		pMsg->msgData[5] = groupCfg;
 	} else {
 		pMsg->xMsgHeader.msgType = MSG_SMS_GPIO_CONFIG_EX_REQ;
 		pMsg->msgData[1] = pGpioConfig->PullUpDown;
 		pMsg->msgData[2] = pGpioConfig->OutputSlewRate;
 		pMsg->msgData[3] = pGpioConfig->OutputDriving;
 		pMsg->msgData[4] = pGpioConfig->Direction;
 		pMsg->msgData[5] = 0;
 	}
 	smsendian_handle_tx_message((struct SmsMsgHdr_ST *)pMsg);
 	rc = smscore_sendrequest_and_wait(coredev, pMsg, totalLen,
 			&coredev->gpio_configuration_done);
 	if (rc != 0) {
 		if (rc == -ETIME)
 			sms_err("smscore_gpio_configure timeout");
 		else
 			sms_err("smscore_gpio_configure error");
 	}
 	kfree(buffer);
 	return rc;
 }
 int smscore_gpio_set_level(struct smscore_device_t *coredev, u8 PinNum,
 		u8 NewLevel) {
 	u32 totalLen;
 	int rc;
 	void *buffer;
 	struct SetGpioMsg {
 		struct SmsMsgHdr_ST xMsgHeader;
 		u32 msgData[3]; /* keep it 3 ! */
 	} *pMsg;
 	if ((NewLevel > 1) || (PinNum > MAX_GPIO_PIN_NUMBER) ||
 			(PinNum > MAX_GPIO_PIN_NUMBER))
 		return -EINVAL;
 	totalLen = sizeof(struct SmsMsgHdr_ST) +
 			(3 * sizeof(u32)); /* keep it 3 ! */
 	buffer = kmalloc(totalLen + SMS_DMA_ALIGNMENT,
 			GFP_KERNEL | GFP_DMA);
 	if (!buffer)
 		return -ENOMEM;
 	pMsg = (struct SetGpioMsg *) SMS_ALIGN_ADDRESS(buffer);
 	pMsg->xMsgHeader.msgSrcId = DVBT_BDA_CONTROL_MSG_ID;
 	pMsg->xMsgHeader.msgDstId = HIF_TASK;
 	pMsg->xMsgHeader.msgFlags = 0;
 	pMsg->xMsgHeader.msgType = MSG_SMS_GPIO_SET_LEVEL_REQ;
 	pMsg->xMsgHeader.msgLength = (u16) totalLen;
 	pMsg->msgData[0] = PinNum;
 	pMsg->msgData[1] = NewLevel;
 	/* Send message to SMS */
 	smsendian_handle_tx_message((struct SmsMsgHdr_ST *)pMsg);
 	rc = smscore_sendrequest_and_wait(coredev, pMsg, totalLen,
 			&coredev->gpio_set_level_done);
 	if (rc != 0) {
 		if (rc == -ETIME)
 			sms_err("smscore_gpio_set_level timeout");
 		else
 			sms_err("smscore_gpio_set_level error");
 	}
 	kfree(buffer);
 	return rc;
 }
 int smscore_gpio_get_level(struct smscore_device_t *coredev, u8 PinNum,
 		u8 *level) {
 	u32 totalLen;
 	int rc;
 	void *buffer;
 	struct SetGpioMsg {
 		struct SmsMsgHdr_ST xMsgHeader;
 		u32 msgData[2];
 	} *pMsg;
 	if (PinNum > MAX_GPIO_PIN_NUMBER)
 		return -EINVAL;
 	totalLen = sizeof(struct SmsMsgHdr_ST) + (2 * sizeof(u32));
 	buffer = kmalloc(totalLen + SMS_DMA_ALIGNMENT,
 			GFP_KERNEL | GFP_DMA);
 	if (!buffer)
 		return -ENOMEM;
 	pMsg = (struct SetGpioMsg *) SMS_ALIGN_ADDRESS(buffer);
 	pMsg->xMsgHeader.msgSrcId = DVBT_BDA_CONTROL_MSG_ID;
 	pMsg->xMsgHeader.msgDstId = HIF_TASK;
 	pMsg->xMsgHeader.msgFlags = 0;
 	pMsg->xMsgHeader.msgType = MSG_SMS_GPIO_GET_LEVEL_REQ;
 	pMsg->xMsgHeader.msgLength = (u16) totalLen;
 	pMsg->msgData[0] = PinNum;
 	pMsg->msgData[1] = 0;
 	/* Send message to SMS */
 	smsendian_handle_tx_message((struct SmsMsgHdr_ST *)pMsg);
 	rc = smscore_sendrequest_and_wait(coredev, pMsg, totalLen,
 			&coredev->gpio_get_level_done);
 	if (rc != 0) {
 		if (rc == -ETIME)
 			sms_err("smscore_gpio_get_level timeout");
 		else
 			sms_err("smscore_gpio_get_level error");
 	}
 	kfree(buffer);
 	/* Its a race between other gpio_get_level() and the copy of the single
 	 * global 'coredev->gpio_get_res' to  the function's variable 'level'
 	 */
 	*level = coredev->gpio_get_res;
 	return rc;
 }
 static int __init smscore_module_init(void)
 {
 	int rc = 0;
 	INIT_LIST_HEAD(&g_smscore_notifyees);
 	INIT_LIST_HEAD(&g_smscore_devices);
 	kmutex_init(&g_smscore_deviceslock);
 	INIT_LIST_HEAD(&g_smscore_registry);
 	kmutex_init(&g_smscore_registrylock);
 	return rc;
 }
 static void __exit smscore_module_exit(void)
 {
 	kmutex_lock(&g_smscore_deviceslock);
 	while (!list_empty(&g_smscore_notifyees)) {
 		struct smscore_device_notifyee_t *notifyee =
 			(struct smscore_device_notifyee_t *)
 				g_smscore_notifyees.next;
 		list_del(&notifyee->entry);
 		kfree(notifyee);
 	}
 	kmutex_unlock(&g_smscore_deviceslock);
 	kmutex_lock(&g_smscore_registrylock);
 	while (!list_empty(&g_smscore_registry)) {
 		struct smscore_registry_entry_t *entry =
 			(struct smscore_registry_entry_t *)
 				g_smscore_registry.next;
 		list_del(&entry->entry);
 		kfree(entry);
 	}
 	kmutex_unlock(&g_smscore_registrylock);
 	sms_debug("");
 }
 module_init(smscore_module_init);
 module_exit(smscore_module_exit);
 MODULE_DESCRIPTION("Siano MDTV Core module");
 MODULE_AUTHOR("Siano Mobile Silicon, Inc. (uris@siano-ms.com)");
 MODULE_LICENSE("GPL");
 /****************************************************************
 Siano Mobile Silicon, Inc.
 MDTV receiver kernel modules.
 Copyright (C) 2006-2008, Uri Shkolnik, Anatoly Greenblat
 This program is free software: you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
 the Free Software Foundation, either version 2 of the License, or
 (at your option) any later version.
 This program is distributed in the hope that it will be useful,
 but WITHOUT ANY WARRANTY; without even the implied warranty of
 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 GNU General Public License for more details.
 You should have received a copy of the GNU General Public License
 along with this program.  If not, see <http://www.gnu.org/licenses/>.
 ****************************************************************/
 #ifndef __SMS_CORE_API_H__
 #define __SMS_CORE_API_H__
 #include <linux/version.h>
 #include <linux/device.h>
 #include <linux/list.h>
 #include <linux/mm.h>
 #include <linux/scatterlist.h>
 #include <linux/types.h>
 #include <linux/mutex.h>
 #include <linux/wait.h>
 #include <linux/timer.h>
 #include <asm/page.h>
 #include "smsir.h"
 #define kmutex_init(_p_) mutex_init(_p_)
 #define kmutex_lock(_p_) mutex_lock(_p_)
 #define kmutex_trylock(_p_) mutex_trylock(_p_)
 #define kmutex_unlock(_p_) mutex_unlock(_p_)
 #ifndef min
 #define min(a, b) (((a) < (b)) ? (a) : (b))
 #endif
 #define SMS_PROTOCOL_MAX_RAOUNDTRIP_MS			(10000)
 #define SMS_ALLOC_ALIGNMENT				128
 #define SMS_DMA_ALIGNMENT				16
 #define SMS_ALIGN_ADDRESS(addr) \
 	((((uintptr_t)(addr)) + (SMS_DMA_ALIGNMENT-1)) & ~(SMS_DMA_ALIGNMENT-1))
 #define SMS_DEVICE_FAMILY2				1
 #define SMS_ROM_NO_RESPONSE				2
 #define SMS_DEVICE_NOT_READY				0x8000000
 enum sms_device_type_st {
 	SMS_STELLAR = 0,
 	SMS_NOVA_A0,
 	SMS_NOVA_B0,
 	SMS_VEGA,
 	SMS_NUM_OF_DEVICE_TYPES
 };
 struct smscore_device_t;
 struct smscore_client_t;
 struct smscore_buffer_t;
 typedef int (*hotplug_t)(struct smscore_device_t *coredev,
 			 struct device *device, int arrival);
 typedef int (*setmode_t)(void *context, int mode);
 typedef void (*detectmode_t)(void *context, int *mode);
 typedef int (*sendrequest_t)(void *context, void *buffer, size_t size);
 typedef int (*loadfirmware_t)(void *context, void *buffer, size_t size);
 typedef int (*preload_t)(void *context);
 typedef int (*postload_t)(void *context);
 typedef int (*onresponse_t)(void *context, struct smscore_buffer_t *cb);
 typedef void (*onremove_t)(void *context);
 struct smscore_buffer_t {
 	/* public members, once passed to clients can be changed freely */
 	struct list_head entry;
 	int size;
 	int offset;
 	/* private members, read-only for clients */
 	void *p;
 	dma_addr_t phys;
 	unsigned long offset_in_common;
 };
 struct smsdevice_params_t {
 	struct device	*device;
 	int				buffer_size;
 	int				num_buffers;
 	char			devpath[32];
 	unsigned long	flags;
 	setmode_t		setmode_handler;
 	detectmode_t	detectmode_handler;
 	sendrequest_t	sendrequest_handler;
 	preload_t		preload_handler;
 	postload_t		postload_handler;
 	void			*context;
 	enum sms_device_type_st device_type;
 };
 struct smsclient_params_t {
 	int				initial_id;
 	int				data_type;
 	onresponse_t	onresponse_handler;
 	onremove_t		onremove_handler;
 	void			*context;
 };
 struct smscore_device_t {
 	struct list_head entry;
 	struct list_head clients;
 	struct list_head subclients;
 	spinlock_t clientslock;
 	struct list_head buffers;
 	spinlock_t bufferslock;
 	int num_buffers;
 	void *common_buffer;
 	int common_buffer_size;
 	dma_addr_t common_buffer_phys;
 	void *context;
 	struct device *device;
 	char devpath[32];
 	unsigned long device_flags;
 	setmode_t setmode_handler;
 	detectmode_t detectmode_handler;
 	sendrequest_t sendrequest_handler;
 	preload_t preload_handler;
 	postload_t postload_handler;
 	int mode, modes_supported;
 	/* host <--> device messages */
 	struct completion version_ex_done, data_download_done, trigger_done;
 	struct completion init_device_done, reload_start_done, resume_done;
 	struct completion gpio_configuration_done, gpio_set_level_done;
 	struct completion gpio_get_level_done, ir_init_done;
 	/* Buffer management */
 	wait_queue_head_t buffer_mng_waitq;
 	/* GPIO */
 	int gpio_get_res;
 	/* Target hardware board */
 	int board_id;
 	/* Firmware */
 	u8 *fw_buf;
 	u32 fw_buf_size;
 	/* Infrared (IR) */
 	struct ir_t ir;
 	int led_state;
 };
 /* GPIO definitions for antenna frequency domain control (SMS8021) */
 #define SMS_ANTENNA_GPIO_0					1
 #define SMS_ANTENNA_GPIO_1					0
 #define BW_8_MHZ							0
 #define BW_7_MHZ							1
 #define BW_6_MHZ							2
 #define BW_5_MHZ							3
 #define BW_ISDBT_1SEG						4
 #define BW_ISDBT_3SEG						5
 #define MSG_HDR_FLAG_SPLIT_MSG				4
 #define MAX_GPIO_PIN_NUMBER					31
 #define HIF_TASK							11
 #define SMS_HOST_LIB						150
 #define DVBT_BDA_CONTROL_MSG_ID				201
 #define SMS_MAX_PAYLOAD_SIZE				240
 #define SMS_TUNE_TIMEOUT					500
 #define MSG_SMS_GPIO_CONFIG_REQ				507
 #define MSG_SMS_GPIO_CONFIG_RES				508
 #define MSG_SMS_GPIO_SET_LEVEL_REQ			509
 #define MSG_SMS_GPIO_SET_LEVEL_RES			510
 #define MSG_SMS_GPIO_GET_LEVEL_REQ			511
 #define MSG_SMS_GPIO_GET_LEVEL_RES			512
 #define MSG_SMS_RF_TUNE_REQ					561
 #define MSG_SMS_RF_TUNE_RES					562
 #define MSG_SMS_INIT_DEVICE_REQ				578
 #define MSG_SMS_INIT_DEVICE_RES				579
 #define MSG_SMS_ADD_PID_FILTER_REQ			601
 #define MSG_SMS_ADD_PID_FILTER_RES			602
 #define MSG_SMS_REMOVE_PID_FILTER_REQ			603
 #define MSG_SMS_REMOVE_PID_FILTER_RES			604
 #define MSG_SMS_DAB_CHANNEL				607
 #define MSG_SMS_GET_PID_FILTER_LIST_REQ			608
 #define MSG_SMS_GET_PID_FILTER_LIST_RES			609
 #define MSG_SMS_HO_PER_SLICES_IND			630
 #define MSG_SMS_SET_ANTENNA_CONFIG_REQ			651
 #define MSG_SMS_SET_ANTENNA_CONFIG_RES			652
 #define MSG_SMS_SLEEP_RESUME_COMP_IND			655
 #define MSG_SMS_DATA_DOWNLOAD_REQ			660
 #define MSG_SMS_DATA_DOWNLOAD_RES			661
 #define MSG_SMS_SWDOWNLOAD_TRIGGER_REQ		664
 #define MSG_SMS_SWDOWNLOAD_TRIGGER_RES		665
 #define MSG_SMS_SWDOWNLOAD_BACKDOOR_REQ		666
 #define MSG_SMS_SWDOWNLOAD_BACKDOOR_RES		667
 #define MSG_SMS_GET_VERSION_EX_REQ			668
 #define MSG_SMS_GET_VERSION_EX_RES			669
 #define MSG_SMS_SET_CLOCK_OUTPUT_REQ		670
 #define MSG_SMS_I2C_SET_FREQ_REQ			685
 #define MSG_SMS_GENERIC_I2C_REQ				687
 #define MSG_SMS_GENERIC_I2C_RES				688
 #define MSG_SMS_DVBT_BDA_DATA				693
 #define MSG_SW_RELOAD_REQ					697
 #define MSG_SMS_DATA_MSG					699
 #define MSG_SW_RELOAD_START_REQ				702
 #define MSG_SW_RELOAD_START_RES				703
 #define MSG_SW_RELOAD_EXEC_REQ				704
 #define MSG_SW_RELOAD_EXEC_RES				705
 #define MSG_SMS_SPI_INT_LINE_SET_REQ		710
 #define MSG_SMS_GPIO_CONFIG_EX_REQ			712
 #define MSG_SMS_GPIO_CONFIG_EX_RES			713
 #define MSG_SMS_ISDBT_TUNE_REQ				776
 #define MSG_SMS_ISDBT_TUNE_RES				777
 #define MSG_SMS_TRANSMISSION_IND			782
 #define MSG_SMS_START_IR_REQ				800
 #define MSG_SMS_START_IR_RES				801
 #define MSG_SMS_IR_SAMPLES_IND				802
 #define MSG_SMS_SIGNAL_DETECTED_IND			827
 #define MSG_SMS_NO_SIGNAL_IND				828
 #define SMS_INIT_MSG_EX(ptr, type, src, dst, len) do { \
 	(ptr)->msgType = type; (ptr)->msgSrcId = src; (ptr)->msgDstId = dst; \
 	(ptr)->msgLength = len; (ptr)->msgFlags = 0; \
 } while (0)
 #define SMS_INIT_MSG(ptr, type, len) \
 	SMS_INIT_MSG_EX(ptr, type, 0, HIF_TASK, len)
 enum SMS_DVB3_EVENTS {
 	DVB3_EVENT_INIT = 0,
 	DVB3_EVENT_SLEEP,
 	DVB3_EVENT_HOTPLUG,
 	DVB3_EVENT_FE_LOCK,
 	DVB3_EVENT_FE_UNLOCK,
 	DVB3_EVENT_UNC_OK,
 	DVB3_EVENT_UNC_ERR
 };
 enum SMS_DEVICE_MODE {
 	DEVICE_MODE_NONE = -1,
 	DEVICE_MODE_DVBT = 0,
 	DEVICE_MODE_DVBH,
 	DEVICE_MODE_DAB_TDMB,
 	DEVICE_MODE_DAB_TDMB_DABIP,
 	DEVICE_MODE_DVBT_BDA,
 	DEVICE_MODE_ISDBT,
 	DEVICE_MODE_ISDBT_BDA,
 	DEVICE_MODE_CMMB,
 	DEVICE_MODE_RAW_TUNER,
 	DEVICE_MODE_MAX,
 };
 struct SmsMsgHdr_ST {
 	u16	msgType;
 	u8	msgSrcId;
 	u8	msgDstId;
 	u16	msgLength; /* Length of entire message, including header */
 	u16	msgFlags;
 };
 struct SmsMsgData_ST {
 	struct SmsMsgHdr_ST xMsgHeader;
 	u32 msgData[1];
 };
 struct SmsMsgData_ST2 {
 	struct SmsMsgHdr_ST xMsgHeader;
 	u32 msgData[2];
 };
 struct SmsDataDownload_ST {
 	struct SmsMsgHdr_ST	xMsgHeader;
 	u32			MemAddr;
 	u8			Payload[SMS_MAX_PAYLOAD_SIZE];
 };
 struct SmsVersionRes_ST {
 	struct SmsMsgHdr_ST	xMsgHeader;
 	u16		ChipModel; /* e.g. 0x1102 for SMS-1102 "Nova" */
 	u8		Step; /* 0 - Step A */
 	u8		MetalFix; /* 0 - Metal 0 */
 	/* FirmwareId 0xFF if ROM, otherwise the
 	 * value indicated by SMSHOSTLIB_DEVICE_MODES_E */
 	u8 FirmwareId;
 	/* SupportedProtocols Bitwise OR combination of
 					     * supported protocols */
 	u8 SupportedProtocols;
 	u8		VersionMajor;
 	u8		VersionMinor;
 	u8		VersionPatch;
 	u8		VersionFieldPatch;
 	u8		RomVersionMajor;
 	u8		RomVersionMinor;
 	u8		RomVersionPatch;
 	u8		RomVersionFieldPatch;
 	u8		TextLabel[34];
 };
 struct SmsFirmware_ST {
 	u32			CheckSum;
 	u32			Length;
 	u32			StartAddress;
 	u8			Payload[1];
 };
 /* Statistics information returned as response for
 * SmsHostApiGetStatistics_Req */
 struct SMSHOSTLIB_STATISTICS_S {
 	u32 Reserved;		/* Reserved */
 	/* Common parameters */
 	u32 IsRfLocked;		/* 0 - not locked, 1 - locked */
 	u32 IsDemodLocked;	/* 0 - not locked, 1 - locked */
 	u32 IsExternalLNAOn;	/* 0 - external LNA off, 1 - external LNA on */
 	/* Reception quality */
 	s32 SNR;		/* dB */
 	u32 BER;		/* Post Viterbi BER [1E-5] */
 	u32 FIB_CRC;		/* CRC errors percentage, valid only for DAB */
 	u32 TS_PER;		/* Transport stream PER,
 	0xFFFFFFFF indicate N/A, valid only for DVB-T/H */
 	u32 MFER;		/* DVB-H frame error rate in percentage,
 	0xFFFFFFFF indicate N/A, valid only for DVB-H */
 	s32 RSSI;		/* dBm */
 	s32 InBandPwr;		/* In band power in dBM */
 	s32 CarrierOffset;	/* Carrier Offset in bin/1024 */
 	/* Transmission parameters */
 	u32 Frequency;		/* Frequency in Hz */
 	u32 Bandwidth;		/* Bandwidth in MHz, valid only for DVB-T/H */
 	u32 TransmissionMode;	/* Transmission Mode, for DAB modes 1-4,
 	for DVB-T/H FFT mode carriers in Kilos */
 	u32 ModemState;		/* from SMSHOSTLIB_DVB_MODEM_STATE_ET,
 	valid only for DVB-T/H */
 	u32 GuardInterval;	/* Guard Interval from
 	SMSHOSTLIB_GUARD_INTERVALS_ET, 	valid only for DVB-T/H */
 	u32 CodeRate;		/* Code Rate from SMSHOSTLIB_CODE_RATE_ET,
 	valid only for DVB-T/H */
 	u32 LPCodeRate;		/* Low Priority Code Rate from
 	SMSHOSTLIB_CODE_RATE_ET, valid only for DVB-T/H */
 	u32 Hierarchy;		/* Hierarchy from SMSHOSTLIB_HIERARCHY_ET,
 	valid only for DVB-T/H */
 	u32 Constellation;	/* Constellation from
 	SMSHOSTLIB_CONSTELLATION_ET, valid only for DVB-T/H */
 	/* Burst parameters, valid only for DVB-H */
 	u32 BurstSize;		/* Current burst size in bytes,
 	valid only for DVB-H */
 	u32 BurstDuration;	/* Current burst duration in mSec,
 	valid only for DVB-H */
 	u32 BurstCycleTime;	/* Current burst cycle time in mSec,
 	valid only for DVB-H */
 	u32 CalculatedBurstCycleTime;/* Current burst cycle time in mSec,
 	as calculated by demodulator, valid only for DVB-H */
 	u32 NumOfRows;		/* Number of rows in MPE table,
 	valid only for DVB-H */
 	u32 NumOfPaddCols;	/* Number of padding columns in MPE table,
 	valid only for DVB-H */
 	u32 NumOfPunctCols;	/* Number of puncturing columns in MPE table,
 	valid only for DVB-H */
 	u32 ErrorTSPackets;	/* Number of erroneous
 	transport-stream packets */
 	u32 TotalTSPackets;	/* Total number of transport-stream packets */
 	u32 NumOfValidMpeTlbs;	/* Number of MPE tables which do not include
 	errors after MPE RS decoding */
 	u32 NumOfInvalidMpeTlbs;/* Number of MPE tables which include errors
 	after MPE RS decoding */
 	u32 NumOfCorrectedMpeTlbs;/* Number of MPE tables which were
 	corrected by MPE RS decoding */
 	/* Common params */
 	u32 BERErrorCount;	/* Number of errornous SYNC bits. */
 	u32 BERBitCount;	/* Total number of SYNC bits. */
 	/* Interface information */
 	u32 SmsToHostTxErrors;	/* Total number of transmission errors. */
 	/* DAB/T-DMB */
 	u32 PreBER; 		/* DAB/T-DMB only: Pre Viterbi BER [1E-5] */
 	/* DVB-H TPS parameters */
 	u32 CellId;		/* TPS Cell ID in bits 15..0, bits 31..16 zero;
 	 if set to 0xFFFFFFFF cell_id not yet recovered */
 	u32 DvbhSrvIndHP;	/* DVB-H service indication info, bit 1 -
 	Time Slicing indicator, bit 0 - MPE-FEC indicator */
 	u32 DvbhSrvIndLP;	/* DVB-H service indication info, bit 1 -
 	Time Slicing indicator, bit 0 - MPE-FEC indicator */
 	u32 NumMPEReceived;	/* DVB-H, Num MPE section received */
 	u32 ReservedFields[10];	/* Reserved */
 };
 struct PID_STATISTICS_DATA_S {
 	struct PID_BURST_S {
 		u32 size;
 		u32 padding_cols;
 		u32 punct_cols;
 		u32 duration;
 		u32 cycle;
 		u32 calc_cycle;
 	} burst;
 	u32 tot_tbl_cnt;
 	u32 invalid_tbl_cnt;
 	u32 tot_cor_tbl;
 };
 struct PID_DATA_S {
 	u32 pid;
 	u32 num_rows;
 	struct PID_STATISTICS_DATA_S pid_statistics;
 };
 #define CORRECT_STAT_RSSI(_stat) ((_stat).RSSI *= -1)
 #define CORRECT_STAT_BANDWIDTH(_stat) (_stat.Bandwidth = 8 - _stat.Bandwidth)
 #define CORRECT_STAT_TRANSMISSON_MODE(_stat) \
 	if (_stat.TransmissionMode == 0) \
 		_stat.TransmissionMode = 2; \
 	else if (_stat.TransmissionMode == 1) \
 		_stat.TransmissionMode = 8; \
 		else \
 			_stat.TransmissionMode = 4;
 struct TRANSMISSION_STATISTICS_S {
 	u32 Frequency;		/* Frequency in Hz */
 	u32 Bandwidth;		/* Bandwidth in MHz */
 	u32 TransmissionMode;	/* FFT mode carriers in Kilos */
 	u32 GuardInterval;	/* Guard Interval from
 	SMSHOSTLIB_GUARD_INTERVALS_ET */
 	u32 CodeRate;		/* Code Rate from SMSHOSTLIB_CODE_RATE_ET */
 	u32 LPCodeRate;		/* Low Priority Code Rate from
 	SMSHOSTLIB_CODE_RATE_ET */
 	u32 Hierarchy;		/* Hierarchy from SMSHOSTLIB_HIERARCHY_ET */
 	u32 Constellation;	/* Constellation from
 	SMSHOSTLIB_CONSTELLATION_ET */
 	/* DVB-H TPS parameters */
 	u32 CellId;		/* TPS Cell ID in bits 15..0, bits 31..16 zero;
 	 if set to 0xFFFFFFFF cell_id not yet recovered */
 	u32 DvbhSrvIndHP;	/* DVB-H service indication info, bit 1 -
 	 Time Slicing indicator, bit 0 - MPE-FEC indicator */
 	u32 DvbhSrvIndLP;	/* DVB-H service indication info, bit 1 -
 	 Time Slicing indicator, bit 0 - MPE-FEC indicator */
 	u32 IsDemodLocked;	/* 0 - not locked, 1 - locked */
 };
 struct RECEPTION_STATISTICS_S {
 	u32 IsRfLocked;		/* 0 - not locked, 1 - locked */
 	u32 IsDemodLocked;	/* 0 - not locked, 1 - locked */
 	u32 IsExternalLNAOn;	/* 0 - external LNA off, 1 - external LNA on */
 	u32 ModemState;		/* from SMSHOSTLIB_DVB_MODEM_STATE_ET */
 	s32 SNR;		/* dB */
 	u32 BER;		/* Post Viterbi BER [1E-5] */
 	u32 BERErrorCount;	/* Number of erronous SYNC bits. */
 	u32 BERBitCount;	/* Total number of SYNC bits. */
 	u32 TS_PER;		/* Transport stream PER,
 	0xFFFFFFFF indicate N/A */
 	u32 MFER;		/* DVB-H frame error rate in percentage,
 	0xFFFFFFFF indicate N/A, valid only for DVB-H */
 	s32 RSSI;		/* dBm */
 	s32 InBandPwr;		/* In band power in dBM */
 	s32 CarrierOffset;	/* Carrier Offset in bin/1024 */
 	u32 ErrorTSPackets;	/* Number of erroneous
 	transport-stream packets */
 	u32 TotalTSPackets;	/* Total number of transport-stream packets */
 	s32 MRC_SNR;		/* dB */
 	s32 MRC_RSSI;		/* dBm */
 	s32 MRC_InBandPwr;	/* In band power in dBM */
 };
 /* Statistics information returned as response for
 * SmsHostApiGetStatisticsEx_Req for DVB applications, SMS1100 and up */
 struct SMSHOSTLIB_STATISTICS_DVB_S {
 	/* Reception */
 	struct RECEPTION_STATISTICS_S ReceptionData;
 	/* Transmission parameters */
 	struct TRANSMISSION_STATISTICS_S TransmissionData;
 	/* Burst parameters, valid only for DVB-H */
 #define	SRVM_MAX_PID_FILTERS 8
 	struct PID_DATA_S PidData[SRVM_MAX_PID_FILTERS];
 };
 struct SRVM_SIGNAL_STATUS_S {
 	u32 result;
 	u32 snr;
 	u32 tsPackets;
 	u32 etsPackets;
 	u32 constellation;
 	u32 hpCode;
 	u32 tpsSrvIndLP;
 	u32 tpsSrvIndHP;
 	u32 cellId;
 	u32 reason;
 	s32 inBandPower;
 	u32 requestId;
 };
 struct SMSHOSTLIB_I2C_REQ_ST {
 	u32	DeviceAddress; /* I2c device address */
 	u32	WriteCount; /* number of bytes to write */
 	u32	ReadCount; /* number of bytes to read */
 	u8	Data[1];
 };
 struct SMSHOSTLIB_I2C_RES_ST {
 	u32	Status; /* non-zero value in case of failure */
 	u32	ReadCount; /* number of bytes read */
 	u8	Data[1];
 };
 struct smscore_config_gpio {
 #define SMS_GPIO_DIRECTION_INPUT  0
 #define SMS_GPIO_DIRECTION_OUTPUT 1
 	u8 direction;
 #define SMS_GPIO_PULLUPDOWN_NONE     0
 #define SMS_GPIO_PULLUPDOWN_PULLDOWN 1
 #define SMS_GPIO_PULLUPDOWN_PULLUP   2
 #define SMS_GPIO_PULLUPDOWN_KEEPER   3
 	u8 pullupdown;
 #define SMS_GPIO_INPUTCHARACTERISTICS_NORMAL  0
 #define SMS_GPIO_INPUTCHARACTERISTICS_SCHMITT 1
 	u8 inputcharacteristics;
 #define SMS_GPIO_OUTPUTSLEWRATE_FAST 0
 #define SMS_GPIO_OUTPUTSLEWRATE_SLOW 1
 	u8 outputslewrate;
 #define SMS_GPIO_OUTPUTDRIVING_4mA  0
 #define SMS_GPIO_OUTPUTDRIVING_8mA  1
 #define SMS_GPIO_OUTPUTDRIVING_12mA 2
 #define SMS_GPIO_OUTPUTDRIVING_16mA 3
 	u8 outputdriving;
 };
 struct smscore_gpio_config {
 #define SMS_GPIO_DIRECTION_INPUT  0
 #define SMS_GPIO_DIRECTION_OUTPUT 1
 	u8 Direction;
 #define SMS_GPIO_PULL_UP_DOWN_NONE     0
 #define SMS_GPIO_PULL_UP_DOWN_PULLDOWN 1
 #define SMS_GPIO_PULL_UP_DOWN_PULLUP   2
 #define SMS_GPIO_PULL_UP_DOWN_KEEPER   3
 	u8 PullUpDown;
 #define SMS_GPIO_INPUT_CHARACTERISTICS_NORMAL  0
 #define SMS_GPIO_INPUT_CHARACTERISTICS_SCHMITT 1
 	u8 InputCharacteristics;
 #define SMS_GPIO_OUTPUT_SLEW_RATE_SLOW		1 /* 10xx */
 #define SMS_GPIO_OUTPUT_SLEW_RATE_FAST		0 /* 10xx */
 #define SMS_GPIO_OUTPUT_SLEW_RATE_0_45_V_NS	0 /* 11xx */
 #define SMS_GPIO_OUTPUT_SLEW_RATE_0_9_V_NS	1 /* 11xx */
 #define SMS_GPIO_OUTPUT_SLEW_RATE_1_7_V_NS	2 /* 11xx */
 #define SMS_GPIO_OUTPUT_SLEW_RATE_3_3_V_NS	3 /* 11xx */
 	u8 OutputSlewRate;
 #define SMS_GPIO_OUTPUT_DRIVING_S_4mA		0 /* 10xx */
 #define SMS_GPIO_OUTPUT_DRIVING_S_8mA		1 /* 10xx */
 #define SMS_GPIO_OUTPUT_DRIVING_S_12mA		2 /* 10xx */
 #define SMS_GPIO_OUTPUT_DRIVING_S_16mA		3 /* 10xx */
 #define SMS_GPIO_OUTPUT_DRIVING_1_5mA		0 /* 11xx */
 #define SMS_GPIO_OUTPUT_DRIVING_2_8mA		1 /* 11xx */
 #define SMS_GPIO_OUTPUT_DRIVING_4mA		2 /* 11xx */
 #define SMS_GPIO_OUTPUT_DRIVING_7mA		3 /* 11xx */
 #define SMS_GPIO_OUTPUT_DRIVING_10mA		4 /* 11xx */
 #define SMS_GPIO_OUTPUT_DRIVING_11mA		5 /* 11xx */
 #define SMS_GPIO_OUTPUT_DRIVING_14mA		6 /* 11xx */
 #define SMS_GPIO_OUTPUT_DRIVING_16mA		7 /* 11xx */
 	u8 OutputDriving;
 };
 extern void smscore_registry_setmode(char *devpath, int mode);
 extern int smscore_registry_getmode(char *devpath);
 extern int smscore_register_hotplug(hotplug_t hotplug);
 extern void smscore_unregister_hotplug(hotplug_t hotplug);
 extern int smscore_register_device(struct smsdevice_params_t *params,
 				   struct smscore_device_t **coredev);
 extern void smscore_unregister_device(struct smscore_device_t *coredev);
 extern int smscore_start_device(struct smscore_device_t *coredev);
 extern int smscore_load_firmware(struct smscore_device_t *coredev,
 				 char *filename,
 				 loadfirmware_t loadfirmware_handler);
 extern int smscore_set_device_mode(struct smscore_device_t *coredev, int mode);
 extern int smscore_get_device_mode(struct smscore_device_t *coredev);
 extern int smscore_register_client(struct smscore_device_t *coredev,
 				    struct smsclient_params_t *params,
 				    struct smscore_client_t **client);
 extern void smscore_unregister_client(struct smscore_client_t *client);
 extern int smsclient_sendrequest(struct smscore_client_t *client,
 				 void *buffer, size_t size);
 extern void smscore_onresponse(struct smscore_device_t *coredev,
 			       struct smscore_buffer_t *cb);
 extern int smscore_get_common_buffer_size(struct smscore_device_t *coredev);
 extern int smscore_map_common_buffer(struct smscore_device_t *coredev,
 				      struct vm_area_struct *vma);
 extern int smscore_get_fw_filename(struct smscore_device_t *coredev,
 				   int mode, char *filename);
 extern int smscore_send_fw_file(struct smscore_device_t *coredev,
 				u8 *ufwbuf, int size);
 extern
 struct smscore_buffer_t *smscore_getbuffer(struct smscore_device_t *coredev);
 extern void smscore_putbuffer(struct smscore_device_t *coredev,
 			      struct smscore_buffer_t *cb);
-/* old GPIO managment */
+/* old GPIO management */
 int smscore_configure_gpio(struct smscore_device_t *coredev, u32 pin,
 			   struct smscore_config_gpio *pinconfig);
 int smscore_set_gpio(struct smscore_device_t *coredev, u32 pin, int level);
-/* new GPIO managment */
+/* new GPIO management */
 extern int smscore_gpio_configure(struct smscore_device_t *coredev, u8 PinNum,
 		struct smscore_gpio_config *pGpioConfig);
 extern int smscore_gpio_set_level(struct smscore_device_t *coredev, u8 PinNum,
 		u8 NewLevel);
 extern int smscore_gpio_get_level(struct smscore_device_t *coredev, u8 PinNum,
 		u8 *level);
 void smscore_set_board_id(struct smscore_device_t *core, int id);
 int smscore_get_board_id(struct smscore_device_t *core);
 int smscore_led_state(struct smscore_device_t *core, int led);
 /* ------------------------------------------------------------------------ */
 #define DBG_INFO 1
 #define DBG_ADV  2
 #define sms_printk(kern, fmt, arg...) \
 	printk(kern "%s: " fmt "\n", __func__, ##arg)
 #define dprintk(kern, lvl, fmt, arg...) do {\
 	if (sms_dbg & lvl) \
 		sms_printk(kern, fmt, ##arg); } while (0)
 #define sms_log(fmt, arg...) sms_printk(KERN_INFO, fmt, ##arg)
 #define sms_err(fmt, arg...) \
 	sms_printk(KERN_ERR, "line: %d: " fmt, __LINE__, ##arg)
 #define sms_warn(fmt, arg...)  sms_printk(KERN_WARNING, fmt, ##arg)
 #define sms_info(fmt, arg...) \
 	dprintk(KERN_INFO, DBG_INFO, fmt, ##arg)
 #define sms_debug(fmt, arg...) \
 	dprintk(KERN_DEBUG, DBG_ADV, fmt, ##arg)
 #endif /* __SMS_CORE_API_H__ */
 /*
 * A driver for the AverMedia MR 800 USB FM radio. This device plugs
 * into both the USB and an analog audio input, so this thing
 * only deals with initialization and frequency setting, the
 * audio data has to be handled by a sound driver.
 *
 * Copyright (c) 2008 Alexey Klimov <klimov.linux@gmail.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 */
 /*
 * Big thanks to authors and contributors of dsbr100.c and radio-si470x.c
 *
 * When work was looked pretty good, i discover this:
 * http://av-usbradio.sourceforge.net/index.php
 * http://sourceforge.net/projects/av-usbradio/
 * Latest release of theirs project was in 2005.
 * Probably, this driver could be improved trough using their
 * achievements (specifications given).
 * Also, Faidon Liambotis <paravoid@debian.org> wrote nice driver for this radio
 * in 2007. He allowed to use his driver to improve current mr800 radio driver.
 * http://kerneltrap.org/mailarchive/linux-usb-devel/2007/10/11/342492
 *
 * Version 0.01:	First working version.
 * 			It's required to blacklist AverMedia USB Radio
 * 			in usbhid/hid-quirks.c
 * Version 0.10:	A lot of cleanups and fixes: unpluging the device,
 * 			few mutex locks were added, codinstyle issues, etc.
 * 			Added stereo support. Thanks to
 * 			Douglas Schilling Landgraf <dougsland@gmail.com> and
 * 			David Ellingsworth <david@identd.dyndns.org>
 * 			for discussion, help and support.
 * Version 0.11:	Converted to v4l2_device.
 *
 * Many things to do:
- * 	- Correct power managment of device (suspend & resume)
+ * 	- Correct power management of device (suspend & resume)
 * 	- Add code for scanning and smooth tuning
 * 	- Add code for sensitivity value
 * 	- Correct mistakes
 * 	- In Japan another FREQ_MIN and FREQ_MAX
 */
 /* kernel includes */
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/init.h>
 #include <linux/slab.h>
 #include <linux/smp_lock.h>
 #include <linux/input.h>
 #include <linux/videodev2.h>
 #include <media/v4l2-device.h>
 #include <media/v4l2-ioctl.h>
 #include <linux/usb.h>
 #include <linux/version.h>	/* for KERNEL_VERSION MACRO */
 #include <linux/mutex.h>
 /* driver and module definitions */
 #define DRIVER_AUTHOR "Alexey Klimov <klimov.linux@gmail.com>"
 #define DRIVER_DESC "AverMedia MR 800 USB FM radio driver"
 #define DRIVER_VERSION "0.11"
 #define RADIO_VERSION KERNEL_VERSION(0, 1, 1)
 MODULE_AUTHOR(DRIVER_AUTHOR);
 MODULE_DESCRIPTION(DRIVER_DESC);
 MODULE_LICENSE("GPL");
 #define USB_AMRADIO_VENDOR 0x07ca
 #define USB_AMRADIO_PRODUCT 0xb800
 /* dev_warn macro with driver name */
 #define MR800_DRIVER_NAME "radio-mr800"
 #define amradio_dev_warn(dev, fmt, arg...)				\
 		dev_warn(dev, MR800_DRIVER_NAME " - " fmt, ##arg)
 /* Probably USB_TIMEOUT should be modified in module parameter */
 #define BUFFER_LENGTH 8
 #define USB_TIMEOUT 500
 /* Frequency limits in MHz -- these are European values.  For Japanese
 devices, that would be 76 and 91.  */
 #define FREQ_MIN  87.5
 #define FREQ_MAX 108.0
 #define FREQ_MUL 16000
 /*
 * Commands that device should understand
 * List isnt full and will be updated with implementation of new functions
 */
 #define AMRADIO_SET_FREQ	0xa4
 #define AMRADIO_SET_MUTE	0xab
 #define AMRADIO_SET_MONO	0xae
 /* Comfortable defines for amradio_set_mute */
 #define AMRADIO_START		0x00
 #define AMRADIO_STOP		0x01
 /* Comfortable defines for amradio_set_stereo */
 #define WANT_STEREO		0x00
 #define WANT_MONO		0x01
 /* module parameter */
 static int radio_nr = -1;
 module_param(radio_nr, int, 0);
 MODULE_PARM_DESC(radio_nr, "Radio Nr");
 static int usb_amradio_probe(struct usb_interface *intf,
 			     const struct usb_device_id *id);
 static void usb_amradio_disconnect(struct usb_interface *intf);
 static int usb_amradio_open(struct file *file);
 static int usb_amradio_close(struct file *file);
 static int usb_amradio_suspend(struct usb_interface *intf,
 				pm_message_t message);
 static int usb_amradio_resume(struct usb_interface *intf);
 /* Data for one (physical) device */
 struct amradio_device {
 	/* reference to USB and video device */
 	struct usb_device *usbdev;
 	struct video_device *videodev;
 	struct v4l2_device v4l2_dev;
 	unsigned char *buffer;
 	struct mutex lock;	/* buffer locking */
 	int curfreq;
 	int stereo;
 	int users;
 	int removed;
 	int muted;
 };
 /* USB Device ID List */
 static struct usb_device_id usb_amradio_device_table[] = {
 	{USB_DEVICE_AND_INTERFACE_INFO(USB_AMRADIO_VENDOR, USB_AMRADIO_PRODUCT,
 							USB_CLASS_HID, 0, 0) },
 	{ }						/* Terminating entry */
 };
 MODULE_DEVICE_TABLE(usb, usb_amradio_device_table);
 /* USB subsystem interface */
 static struct usb_driver usb_amradio_driver = {
 	.name			= MR800_DRIVER_NAME,
 	.probe			= usb_amradio_probe,
 	.disconnect		= usb_amradio_disconnect,
 	.suspend		= usb_amradio_suspend,
 	.resume			= usb_amradio_resume,
 	.reset_resume		= usb_amradio_resume,
 	.id_table		= usb_amradio_device_table,
 	.supports_autosuspend	= 0,
 };
 /* switch on/off the radio. Send 8 bytes to device */
 static int amradio_set_mute(struct amradio_device *radio, char argument)
 {
 	int retval;
 	int size;
 	/* safety check */
 	if (radio->removed)
 		return -EIO;
 	mutex_lock(&radio->lock);
 	radio->buffer[0] = 0x00;
 	radio->buffer[1] = 0x55;
 	radio->buffer[2] = 0xaa;
 	radio->buffer[3] = 0x00;
 	radio->buffer[4] = AMRADIO_SET_MUTE;
 	radio->buffer[5] = argument;
 	radio->buffer[6] = 0x00;
 	radio->buffer[7] = 0x00;
 	retval = usb_bulk_msg(radio->usbdev, usb_sndintpipe(radio->usbdev, 2),
 		(void *) (radio->buffer), BUFFER_LENGTH, &size, USB_TIMEOUT);
 	if (retval < 0 || size != BUFFER_LENGTH) {
 		mutex_unlock(&radio->lock);
 		return retval;
 	}
 	radio->muted = argument;
 	mutex_unlock(&radio->lock);
 	return retval;
 }
 /* set a frequency, freq is defined by v4l's TUNER_LOW, i.e. 1/16th kHz */
 static int amradio_setfreq(struct amradio_device *radio, int freq)
 {
 	int retval;
 	int size;
 	unsigned short freq_send = 0x10 + (freq >> 3) / 25;
 	/* safety check */
 	if (radio->removed)
 		return -EIO;
 	mutex_lock(&radio->lock);
 	radio->buffer[0] = 0x00;
 	radio->buffer[1] = 0x55;
 	radio->buffer[2] = 0xaa;
 	radio->buffer[3] = 0x03;
 	radio->buffer[4] = AMRADIO_SET_FREQ;
 	radio->buffer[5] = 0x00;
 	radio->buffer[6] = 0x00;
 	radio->buffer[7] = 0x08;
 	retval = usb_bulk_msg(radio->usbdev, usb_sndintpipe(radio->usbdev, 2),
 		(void *) (radio->buffer), BUFFER_LENGTH, &size, USB_TIMEOUT);
 	if (retval < 0 || size != BUFFER_LENGTH) {
 		mutex_unlock(&radio->lock);
 		return retval;
 	}
 	/* frequency is calculated from freq_send and placed in first 2 bytes */
 	radio->buffer[0] = (freq_send >> 8) & 0xff;
 	radio->buffer[1] = freq_send & 0xff;
 	radio->buffer[2] = 0x01;
 	radio->buffer[3] = 0x00;
 	radio->buffer[4] = 0x00;
 	/* 5 and 6 bytes of buffer already = 0x00 */
 	radio->buffer[7] = 0x00;
 	retval = usb_bulk_msg(radio->usbdev, usb_sndintpipe(radio->usbdev, 2),
 		(void *) (radio->buffer), BUFFER_LENGTH, &size, USB_TIMEOUT);
 	if (retval < 0 || size != BUFFER_LENGTH) {
 		mutex_unlock(&radio->lock);
 		return retval;
 	}
 	mutex_unlock(&radio->lock);
 	return retval;
 }
 static int amradio_set_stereo(struct amradio_device *radio, char argument)
 {
 	int retval;
 	int size;
 	/* safety check */
 	if (radio->removed)
 		return -EIO;
 	mutex_lock(&radio->lock);
 	radio->buffer[0] = 0x00;
 	radio->buffer[1] = 0x55;
 	radio->buffer[2] = 0xaa;
 	radio->buffer[3] = 0x00;
 	radio->buffer[4] = AMRADIO_SET_MONO;
 	radio->buffer[5] = argument;
 	radio->buffer[6] = 0x00;
 	radio->buffer[7] = 0x00;
 	retval = usb_bulk_msg(radio->usbdev, usb_sndintpipe(radio->usbdev, 2),
 		(void *) (radio->buffer), BUFFER_LENGTH, &size, USB_TIMEOUT);
 	if (retval < 0 || size != BUFFER_LENGTH) {
 		radio->stereo = -1;
 		mutex_unlock(&radio->lock);
 		return retval;
 	}
 	radio->stereo = 1;
 	mutex_unlock(&radio->lock);
 	return retval;
 }
 /* Handle unplugging the device.
 * We call video_unregister_device in any case.
 * The last function called in this procedure is
 * usb_amradio_device_release.
 */
 static void usb_amradio_disconnect(struct usb_interface *intf)
 {
 	struct amradio_device *radio = usb_get_intfdata(intf);
 	mutex_lock(&radio->lock);
 	radio->removed = 1;
 	mutex_unlock(&radio->lock);
 	usb_set_intfdata(intf, NULL);
 	video_unregister_device(radio->videodev);
 	v4l2_device_disconnect(&radio->v4l2_dev);
 }
 /* vidioc_querycap - query device capabilities */
 static int vidioc_querycap(struct file *file, void *priv,
 					struct v4l2_capability *v)
 {
 	struct amradio_device *radio = video_drvdata(file);
 	strlcpy(v->driver, "radio-mr800", sizeof(v->driver));
 	strlcpy(v->card, "AverMedia MR 800 USB FM Radio", sizeof(v->card));
 	usb_make_path(radio->usbdev, v->bus_info, sizeof(v->bus_info));
 	v->version = RADIO_VERSION;
 	v->capabilities = V4L2_CAP_TUNER;
 	return 0;
 }
 /* vidioc_g_tuner - get tuner attributes */
 static int vidioc_g_tuner(struct file *file, void *priv,
 				struct v4l2_tuner *v)
 {
 	struct amradio_device *radio = video_get_drvdata(video_devdata(file));
 	int retval;
 	/* safety check */
 	if (radio->removed)
 		return -EIO;
 	if (v->index > 0)
 		return -EINVAL;
 /* TODO: Add function which look is signal stereo or not
 * 	amradio_getstat(radio);
 */
 /* we call amradio_set_stereo to set radio->stereo
 * Honestly, amradio_getstat should cover this in future and
 * amradio_set_stereo shouldn't be here
 */
 	retval = amradio_set_stereo(radio, WANT_STEREO);
 	if (retval < 0)
 		amradio_dev_warn(&radio->videodev->dev,
 			"set stereo failed\n");
 	strcpy(v->name, "FM");
 	v->type = V4L2_TUNER_RADIO;
 	v->rangelow = FREQ_MIN * FREQ_MUL;
 	v->rangehigh = FREQ_MAX * FREQ_MUL;
 	v->rxsubchans = V4L2_TUNER_SUB_MONO | V4L2_TUNER_SUB_STEREO;
 	v->capability = V4L2_TUNER_CAP_LOW;
 	if (radio->stereo)
 		v->audmode = V4L2_TUNER_MODE_STEREO;
 	else
 		v->audmode = V4L2_TUNER_MODE_MONO;
 	v->signal = 0xffff;     /* Can't get the signal strength, sad.. */
 	v->afc = 0; /* Don't know what is this */
 	return 0;
 }
 /* vidioc_s_tuner - set tuner attributes */
 static int vidioc_s_tuner(struct file *file, void *priv,
 				struct v4l2_tuner *v)
 {
 	struct amradio_device *radio = video_get_drvdata(video_devdata(file));
 	int retval;
 	/* safety check */
 	if (radio->removed)
 		return -EIO;
 	if (v->index > 0)
 		return -EINVAL;
 	/* mono/stereo selector */
 	switch (v->audmode) {
 	case V4L2_TUNER_MODE_MONO:
 		retval = amradio_set_stereo(radio, WANT_MONO);
 		if (retval < 0)
 			amradio_dev_warn(&radio->videodev->dev,
 				"set mono failed\n");
 		break;
 	case V4L2_TUNER_MODE_STEREO:
 		retval = amradio_set_stereo(radio, WANT_STEREO);
 		if (retval < 0)
 			amradio_dev_warn(&radio->videodev->dev,
 				"set stereo failed\n");
 		break;
 	default:
 		return -EINVAL;
 	}
 	return 0;
 }
 /* vidioc_s_frequency - set tuner radio frequency */
 static int vidioc_s_frequency(struct file *file, void *priv,
 				struct v4l2_frequency *f)
 {
 	struct amradio_device *radio = video_get_drvdata(video_devdata(file));
 	int retval;
 	/* safety check */
 	if (radio->removed)
 		return -EIO;
 	mutex_lock(&radio->lock);
 	radio->curfreq = f->frequency;
 	mutex_unlock(&radio->lock);
 	retval = amradio_setfreq(radio, radio->curfreq);
 	if (retval < 0)
 		amradio_dev_warn(&radio->videodev->dev,
 			"set frequency failed\n");
 	return 0;
 }
 /* vidioc_g_frequency - get tuner radio frequency */
 static int vidioc_g_frequency(struct file *file, void *priv,
 				struct v4l2_frequency *f)
 {
 	struct amradio_device *radio = video_get_drvdata(video_devdata(file));
 	/* safety check */
 	if (radio->removed)
 		return -EIO;
 	f->type = V4L2_TUNER_RADIO;
 	f->frequency = radio->curfreq;
 	return 0;
 }
 /* vidioc_queryctrl - enumerate control items */
 static int vidioc_queryctrl(struct file *file, void *priv,
 				struct v4l2_queryctrl *qc)
 {
 	switch (qc->id) {
 	case V4L2_CID_AUDIO_MUTE:
 		return v4l2_ctrl_query_fill(qc, 0, 1, 1, 1);
 	}
 	return -EINVAL;
 }
 /* vidioc_g_ctrl - get the value of a control */
 static int vidioc_g_ctrl(struct file *file, void *priv,
 				struct v4l2_control *ctrl)
 {
 	struct amradio_device *radio = video_get_drvdata(video_devdata(file));
 	/* safety check */
 	if (radio->removed)
 		return -EIO;
 	switch (ctrl->id) {
 	case V4L2_CID_AUDIO_MUTE:
 		ctrl->value = radio->muted;
 		return 0;
 	}
 	return -EINVAL;
 }
 /* vidioc_s_ctrl - set the value of a control */
 static int vidioc_s_ctrl(struct file *file, void *priv,
 				struct v4l2_control *ctrl)
 {
 	struct amradio_device *radio = video_get_drvdata(video_devdata(file));
 	int retval;
 	/* safety check */
 	if (radio->removed)
 		return -EIO;
 	switch (ctrl->id) {
 	case V4L2_CID_AUDIO_MUTE:
 		if (ctrl->value) {
 			retval = amradio_set_mute(radio, AMRADIO_STOP);
 			if (retval < 0) {
 				amradio_dev_warn(&radio->videodev->dev,
 					"amradio_stop failed\n");
 				return -1;
 			}
 		} else {
 			retval = amradio_set_mute(radio, AMRADIO_START);
 			if (retval < 0) {
 				amradio_dev_warn(&radio->videodev->dev,
 					"amradio_start failed\n");
 				return -1;
 			}
 		}
 		return 0;
 	}
 	return -EINVAL;
 }
 /* vidioc_g_audio - get audio attributes */
 static int vidioc_g_audio(struct file *file, void *priv,
 				struct v4l2_audio *a)
 {
 	if (a->index > 1)
 		return -EINVAL;
 	strcpy(a->name, "Radio");
 	a->capability = V4L2_AUDCAP_STEREO;
 	return 0;
 }
 /* vidioc_s_audio - set audio attributes  */
 static int vidioc_s_audio(struct file *file, void *priv,
 					struct v4l2_audio *a)
 {
 	if (a->index != 0)
 		return -EINVAL;
 	return 0;
 }
 /* vidioc_g_input - get input */
 static int vidioc_g_input(struct file *filp, void *priv, unsigned int *i)
 {
 	*i = 0;
 	return 0;
 }
 /* vidioc_s_input - set input */
 static int vidioc_s_input(struct file *filp, void *priv, unsigned int i)
 {
 	if (i != 0)
 		return -EINVAL;
 	return 0;
 }
 /* open device - amradio_start() and amradio_setfreq() */
 static int usb_amradio_open(struct file *file)
 {
 	struct amradio_device *radio = video_get_drvdata(video_devdata(file));
 	int retval;
 	lock_kernel();
 	radio->users = 1;
 	radio->muted = 1;
 	retval = amradio_set_mute(radio, AMRADIO_START);
 	if (retval < 0) {
 		amradio_dev_warn(&radio->videodev->dev,
 			"radio did not start up properly\n");
 		radio->users = 0;
 		unlock_kernel();
 		return -EIO;
 	}
 	retval = amradio_set_stereo(radio, WANT_STEREO);
 	if (retval < 0)
 		amradio_dev_warn(&radio->videodev->dev,
 			"set stereo failed\n");
 	retval = amradio_setfreq(radio, radio->curfreq);
 	if (retval < 0)
 		amradio_dev_warn(&radio->videodev->dev,
 			"set frequency failed\n");
 	unlock_kernel();
 	return 0;
 }
 /*close device */
 static int usb_amradio_close(struct file *file)
 {
 	struct amradio_device *radio = video_get_drvdata(video_devdata(file));
 	int retval;
 	if (!radio)
 		return -ENODEV;
 	mutex_lock(&radio->lock);
 	radio->users = 0;
 	mutex_unlock(&radio->lock);
 	if (!radio->removed) {
 		retval = amradio_set_mute(radio, AMRADIO_STOP);
 		if (retval < 0)
 			amradio_dev_warn(&radio->videodev->dev,
 				"amradio_stop failed\n");
 	}
 	return 0;
 }
 /* Suspend device - stop device. Need to be checked and fixed */
 static int usb_amradio_suspend(struct usb_interface *intf, pm_message_t message)
 {
 	struct amradio_device *radio = usb_get_intfdata(intf);
 	int retval;
 	retval = amradio_set_mute(radio, AMRADIO_STOP);
 	if (retval < 0)
 		dev_warn(&intf->dev, "amradio_stop failed\n");
 	dev_info(&intf->dev, "going into suspend..\n");
 	return 0;
 }
 /* Resume device - start device. Need to be checked and fixed */
 static int usb_amradio_resume(struct usb_interface *intf)
 {
 	struct amradio_device *radio = usb_get_intfdata(intf);
 	int retval;
 	retval = amradio_set_mute(radio, AMRADIO_START);
 	if (retval < 0)
 		dev_warn(&intf->dev, "amradio_start failed\n");
 	dev_info(&intf->dev, "coming out of suspend..\n");
 	return 0;
 }
 /* File system interface */
 static const struct v4l2_file_operations usb_amradio_fops = {
 	.owner		= THIS_MODULE,
 	.open		= usb_amradio_open,
 	.release	= usb_amradio_close,
 	.ioctl		= video_ioctl2,
 };
 static const struct v4l2_ioctl_ops usb_amradio_ioctl_ops = {
 	.vidioc_querycap    = vidioc_querycap,
 	.vidioc_g_tuner     = vidioc_g_tuner,
 	.vidioc_s_tuner     = vidioc_s_tuner,
 	.vidioc_g_frequency = vidioc_g_frequency,
 	.vidioc_s_frequency = vidioc_s_frequency,
 	.vidioc_queryctrl   = vidioc_queryctrl,
 	.vidioc_g_ctrl      = vidioc_g_ctrl,
 	.vidioc_s_ctrl      = vidioc_s_ctrl,
 	.vidioc_g_audio     = vidioc_g_audio,
 	.vidioc_s_audio     = vidioc_s_audio,
 	.vidioc_g_input     = vidioc_g_input,
 	.vidioc_s_input     = vidioc_s_input,
 };
 static void usb_amradio_video_device_release(struct video_device *videodev)
 {
 	struct amradio_device *radio = video_get_drvdata(videodev);
 	/* we call v4l to free radio->videodev */
 	video_device_release(videodev);
 	v4l2_device_unregister(&radio->v4l2_dev);
 	/* free rest memory */
 	kfree(radio->buffer);
 	kfree(radio);
 }
 /* check if the device is present and register with v4l and usb if it is */
 static int usb_amradio_probe(struct usb_interface *intf,
 				const struct usb_device_id *id)
 {
 	struct amradio_device *radio;
 	struct v4l2_device *v4l2_dev;
 	int retval;
 	radio = kzalloc(sizeof(struct amradio_device), GFP_KERNEL);
 	if (!radio) {
 		dev_err(&intf->dev, "kmalloc for amradio_device failed\n");
 		return -ENOMEM;
 	}
 	radio->buffer = kmalloc(BUFFER_LENGTH, GFP_KERNEL);
 	if (!radio->buffer) {
 		dev_err(&intf->dev, "kmalloc for radio->buffer failed\n");
 		kfree(radio);
 		return -ENOMEM;
 	}
 	v4l2_dev = &radio->v4l2_dev;
 	retval = v4l2_device_register(&intf->dev, v4l2_dev);
 	if (retval < 0) {
 		dev_err(&intf->dev, "couldn't register v4l2_device\n");
 		kfree(radio->buffer);
 		kfree(radio);
 		return retval;
 	}
 	radio->videodev = video_device_alloc();
 	if (!radio->videodev) {
 		dev_err(&intf->dev, "video_device_alloc failed\n");
 		kfree(radio->buffer);
 		kfree(radio);
 		return -ENOMEM;
 	}
 	strlcpy(radio->videodev->name, v4l2_dev->name, sizeof(radio->videodev->name));
 	radio->videodev->v4l2_dev = v4l2_dev;
 	radio->videodev->fops = &usb_amradio_fops;
 	radio->videodev->ioctl_ops = &usb_amradio_ioctl_ops;
 	radio->videodev->release = usb_amradio_video_device_release;
 	radio->removed = 0;
 	radio->users = 0;
 	radio->usbdev = interface_to_usbdev(intf);
 	radio->curfreq = 95.16 * FREQ_MUL;
 	radio->stereo = -1;
 	mutex_init(&radio->lock);
 	video_set_drvdata(radio->videodev, radio);
 	retval = video_register_device(radio->videodev,	VFL_TYPE_RADIO,	radio_nr);
 	if (retval < 0) {
 		dev_err(&intf->dev, "could not register video device\n");
 		video_device_release(radio->videodev);
 		v4l2_device_unregister(v4l2_dev);
 		kfree(radio->buffer);
 		kfree(radio);
 		return -EIO;
 	}
 	usb_set_intfdata(intf, radio);
 	return 0;
 }
 static int __init amradio_init(void)
 {
 	int retval = usb_register(&usb_amradio_driver);
 	pr_info(KBUILD_MODNAME
 		": version " DRIVER_VERSION " " DRIVER_DESC "\n");
 	if (retval)
 		pr_err(KBUILD_MODNAME
 			": usb_register failed. Error number %d\n", retval);
 	return retval;
 }
 static void __exit amradio_exit(void)
 {
 	usb_deregister(&usb_amradio_driver);
 }
 module_init(amradio_init);
 module_exit(amradio_exit);
 /*
 *  linux/drivers/message/fusion/mptbase.c
 *      This is the Fusion MPT base driver which supports multiple
 *      (SCSI + LAN) specialized protocol drivers.
 *      For use with LSI PCI chip/adapter(s)
 *      running LSI Fusion MPT (Message Passing Technology) firmware.
 *
 *  Copyright (c) 1999-2008 LSI Corporation
 *  (mailto:DL-MPTFusionLinux@lsi.com)
 *
 */
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /*
    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; version 2 of the License.
    This program is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.
    NO WARRANTY
    THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
    CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
    LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
    MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
    solely responsible for determining the appropriateness of using and
    distributing the Program and assumes all risks associated with its
    exercise of rights under this Agreement, including but not limited to
    the risks and costs of program errors, damage to or loss of data,
    programs or equipment, and unavailability or interruption of operations.
    DISCLAIMER OF LIABILITY
    NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
    DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
    DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
    ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
    TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
    USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
    HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/errno.h>
 #include <linux/init.h>
 #include <linux/slab.h>
 #include <linux/types.h>
 #include <linux/pci.h>
 #include <linux/kdev_t.h>
 #include <linux/blkdev.h>
 #include <linux/delay.h>
 #include <linux/interrupt.h>		/* needed for in_interrupt() proto */
 #include <linux/dma-mapping.h>
 #include <asm/io.h>
 #ifdef CONFIG_MTRR
 #include <asm/mtrr.h>
 #endif
 #include "mptbase.h"
 #include "lsi/mpi_log_fc.h"
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 #define my_NAME		"Fusion MPT base driver"
 #define my_VERSION	MPT_LINUX_VERSION_COMMON
 #define MYNAM		"mptbase"
 MODULE_AUTHOR(MODULEAUTHOR);
 MODULE_DESCRIPTION(my_NAME);
 MODULE_LICENSE("GPL");
 MODULE_VERSION(my_VERSION);
 /*
 *  cmd line parameters
 */
 static int mpt_msi_enable_spi;
 module_param(mpt_msi_enable_spi, int, 0);
 MODULE_PARM_DESC(mpt_msi_enable_spi, " Enable MSI Support for SPI \
 		controllers (default=0)");
 static int mpt_msi_enable_fc;
 module_param(mpt_msi_enable_fc, int, 0);
 MODULE_PARM_DESC(mpt_msi_enable_fc, " Enable MSI Support for FC \
 		controllers (default=0)");
 static int mpt_msi_enable_sas;
 module_param(mpt_msi_enable_sas, int, 0);
 MODULE_PARM_DESC(mpt_msi_enable_sas, " Enable MSI Support for SAS \
 		controllers (default=0)");
 static int mpt_channel_mapping;
 module_param(mpt_channel_mapping, int, 0);
 MODULE_PARM_DESC(mpt_channel_mapping, " Mapping id's to channels (default=0)");
 static int mpt_debug_level;
 static int mpt_set_debug_level(const char *val, struct kernel_param *kp);
 module_param_call(mpt_debug_level, mpt_set_debug_level, param_get_int,
 		  &mpt_debug_level, 0600);
 MODULE_PARM_DESC(mpt_debug_level, " debug level - refer to mptdebug.h \
 	- (default=0)");
 int mpt_fwfault_debug;
 EXPORT_SYMBOL(mpt_fwfault_debug);
 module_param_call(mpt_fwfault_debug, param_set_int, param_get_int,
 	  &mpt_fwfault_debug, 0600);
 MODULE_PARM_DESC(mpt_fwfault_debug, "Enable detection of Firmware fault"
 	" and halt Firmware on fault - (default=0)");
 #ifdef MFCNT
 static int mfcounter = 0;
 #define PRINT_MF_COUNT 20000
 #endif
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /*
 *  Public data...
 */
 static struct proc_dir_entry *mpt_proc_root_dir;
 #define WHOINIT_UNKNOWN		0xAA
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /*
 *  Private data...
 */
 					/* Adapter link list */
 LIST_HEAD(ioc_list);
 					/* Callback lookup table */
 static MPT_CALLBACK		 MptCallbacks[MPT_MAX_PROTOCOL_DRIVERS];
 					/* Protocol driver class lookup table */
 static int			 MptDriverClass[MPT_MAX_PROTOCOL_DRIVERS];
 					/* Event handler lookup table */
 static MPT_EVHANDLER		 MptEvHandlers[MPT_MAX_PROTOCOL_DRIVERS];
 					/* Reset handler lookup table */
 static MPT_RESETHANDLER		 MptResetHandlers[MPT_MAX_PROTOCOL_DRIVERS];
 static struct mpt_pci_driver 	*MptDeviceDriverHandlers[MPT_MAX_PROTOCOL_DRIVERS];
 /*
 *  Driver Callback Index's
 */
 static u8 mpt_base_index = MPT_MAX_PROTOCOL_DRIVERS;
 static u8 last_drv_idx;
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /*
 *  Forward protos...
 */
 static irqreturn_t mpt_interrupt(int irq, void *bus_id);
 static int	mptbase_reply(MPT_ADAPTER *ioc, MPT_FRAME_HDR *req,
 		MPT_FRAME_HDR *reply);
 static int	mpt_handshake_req_reply_wait(MPT_ADAPTER *ioc, int reqBytes,
 			u32 *req, int replyBytes, u16 *u16reply, int maxwait,
 			int sleepFlag);
 static int	mpt_do_ioc_recovery(MPT_ADAPTER *ioc, u32 reason, int sleepFlag);
 static void	mpt_detect_bound_ports(MPT_ADAPTER *ioc, struct pci_dev *pdev);
 static void	mpt_adapter_disable(MPT_ADAPTER *ioc);
 static void	mpt_adapter_dispose(MPT_ADAPTER *ioc);
 static void	MptDisplayIocCapabilities(MPT_ADAPTER *ioc);
 static int	MakeIocReady(MPT_ADAPTER *ioc, int force, int sleepFlag);
 static int	GetIocFacts(MPT_ADAPTER *ioc, int sleepFlag, int reason);
 static int	GetPortFacts(MPT_ADAPTER *ioc, int portnum, int sleepFlag);
 static int	SendIocInit(MPT_ADAPTER *ioc, int sleepFlag);
 static int	SendPortEnable(MPT_ADAPTER *ioc, int portnum, int sleepFlag);
 static int	mpt_do_upload(MPT_ADAPTER *ioc, int sleepFlag);
 static int	mpt_downloadboot(MPT_ADAPTER *ioc, MpiFwHeader_t *pFwHeader, int sleepFlag);
 static int	mpt_diag_reset(MPT_ADAPTER *ioc, int ignore, int sleepFlag);
 static int	KickStart(MPT_ADAPTER *ioc, int ignore, int sleepFlag);
 static int	SendIocReset(MPT_ADAPTER *ioc, u8 reset_type, int sleepFlag);
 static int	PrimeIocFifos(MPT_ADAPTER *ioc);
 static int	WaitForDoorbellAck(MPT_ADAPTER *ioc, int howlong, int sleepFlag);
 static int	WaitForDoorbellInt(MPT_ADAPTER *ioc, int howlong, int sleepFlag);
 static int	WaitForDoorbellReply(MPT_ADAPTER *ioc, int howlong, int sleepFlag);
 static int	GetLanConfigPages(MPT_ADAPTER *ioc);
 static int	GetIoUnitPage2(MPT_ADAPTER *ioc);
 int		mptbase_sas_persist_operation(MPT_ADAPTER *ioc, u8 persist_opcode);
 static int	mpt_GetScsiPortSettings(MPT_ADAPTER *ioc, int portnum);
 static int	mpt_readScsiDevicePageHeaders(MPT_ADAPTER *ioc, int portnum);
 static void 	mpt_read_ioc_pg_1(MPT_ADAPTER *ioc);
 static void 	mpt_read_ioc_pg_4(MPT_ADAPTER *ioc);
 static void	mpt_get_manufacturing_pg_0(MPT_ADAPTER *ioc);
 static int	SendEventNotification(MPT_ADAPTER *ioc, u8 EvSwitch,
 	int sleepFlag);
 static int	SendEventAck(MPT_ADAPTER *ioc, EventNotificationReply_t *evnp);
 static int	mpt_host_page_access_control(MPT_ADAPTER *ioc, u8 access_control_value, int sleepFlag);
 static int	mpt_host_page_alloc(MPT_ADAPTER *ioc, pIOCInit_t ioc_init);
 #ifdef CONFIG_PROC_FS
 static int	procmpt_summary_read(char *buf, char **start, off_t offset,
 				int request, int *eof, void *data);
 static int	procmpt_version_read(char *buf, char **start, off_t offset,
 				int request, int *eof, void *data);
 static int	procmpt_iocinfo_read(char *buf, char **start, off_t offset,
 				int request, int *eof, void *data);
 #endif
 static void	mpt_get_fw_exp_ver(char *buf, MPT_ADAPTER *ioc);
 static int	ProcessEventNotification(MPT_ADAPTER *ioc,
 		EventNotificationReply_t *evReply, int *evHandlers);
 static void	mpt_iocstatus_info(MPT_ADAPTER *ioc, u32 ioc_status, MPT_FRAME_HDR *mf);
 static void	mpt_fc_log_info(MPT_ADAPTER *ioc, u32 log_info);
 static void	mpt_spi_log_info(MPT_ADAPTER *ioc, u32 log_info);
 static void	mpt_sas_log_info(MPT_ADAPTER *ioc, u32 log_info);
 static int	mpt_read_ioc_pg_3(MPT_ADAPTER *ioc);
 static void	mpt_inactive_raid_list_free(MPT_ADAPTER *ioc);
 /* module entry point */
 static int  __init    fusion_init  (void);
 static void __exit    fusion_exit  (void);
 #define CHIPREG_READ32(addr) 		readl_relaxed(addr)
 #define CHIPREG_READ32_dmasync(addr)	readl(addr)
 #define CHIPREG_WRITE32(addr,val) 	writel(val, addr)
 #define CHIPREG_PIO_WRITE32(addr,val)	outl(val, (unsigned long)addr)
 #define CHIPREG_PIO_READ32(addr) 	inl((unsigned long)addr)
 static void
 pci_disable_io_access(struct pci_dev *pdev)
 {
 	u16 command_reg;
 	pci_read_config_word(pdev, PCI_COMMAND, &command_reg);
 	command_reg &= ~1;
 	pci_write_config_word(pdev, PCI_COMMAND, command_reg);
 }
 static void
 pci_enable_io_access(struct pci_dev *pdev)
 {
 	u16 command_reg;
 	pci_read_config_word(pdev, PCI_COMMAND, &command_reg);
 	command_reg |= 1;
 	pci_write_config_word(pdev, PCI_COMMAND, command_reg);
 }
 static int mpt_set_debug_level(const char *val, struct kernel_param *kp)
 {
 	int ret = param_set_int(val, kp);
 	MPT_ADAPTER *ioc;
 	if (ret)
 		return ret;
 	list_for_each_entry(ioc, &ioc_list, list)
 		ioc->debug_level = mpt_debug_level;
 	return 0;
 }
 /**
 *	mpt_get_cb_idx - obtain cb_idx for registered driver
 *	@dclass: class driver enum
 *
 *	Returns cb_idx, or zero means it wasn't found
 **/
 static u8
 mpt_get_cb_idx(MPT_DRIVER_CLASS dclass)
 {
 	u8 cb_idx;
 	for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--)
 		if (MptDriverClass[cb_idx] == dclass)
 			return cb_idx;
 	return 0;
 }
 /**
 * mpt_is_discovery_complete - determine if discovery has completed
 * @ioc: per adatper instance
 *
 * Returns 1 when discovery completed, else zero.
 */
 static int
 mpt_is_discovery_complete(MPT_ADAPTER *ioc)
 {
 	ConfigExtendedPageHeader_t hdr;
 	CONFIGPARMS cfg;
 	SasIOUnitPage0_t *buffer;
 	dma_addr_t dma_handle;
 	int rc = 0;
 	memset(&hdr, 0, sizeof(ConfigExtendedPageHeader_t));
 	memset(&cfg, 0, sizeof(CONFIGPARMS));
 	hdr.PageVersion = MPI_SASIOUNITPAGE0_PAGEVERSION;
 	hdr.PageType = MPI_CONFIG_PAGETYPE_EXTENDED;
 	hdr.ExtPageType = MPI_CONFIG_EXTPAGETYPE_SAS_IO_UNIT;
 	cfg.cfghdr.ehdr = &hdr;
 	cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
 	if ((mpt_config(ioc, &cfg)))
 		goto out;
 	if (!hdr.ExtPageLength)
 		goto out;
 	buffer = pci_alloc_consistent(ioc->pcidev, hdr.ExtPageLength * 4,
 	    &dma_handle);
 	if (!buffer)
 		goto out;
 	cfg.physAddr = dma_handle;
 	cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
 	if ((mpt_config(ioc, &cfg)))
 		goto out_free_consistent;
 	if (!(buffer->PhyData[0].PortFlags &
 	    MPI_SAS_IOUNIT0_PORT_FLAGS_DISCOVERY_IN_PROGRESS))
 		rc = 1;
 out_free_consistent:
 	pci_free_consistent(ioc->pcidev, hdr.ExtPageLength * 4,
 	    buffer, dma_handle);
 out:
 	return rc;
 }
 /**
 *	mpt_fault_reset_work - work performed on workq after ioc fault
 *	@work: input argument, used to derive ioc
 *
 **/
 static void
 mpt_fault_reset_work(struct work_struct *work)
 {
 	MPT_ADAPTER	*ioc =
 	    container_of(work, MPT_ADAPTER, fault_reset_work.work);
 	u32		 ioc_raw_state;
 	int		 rc;
 	unsigned long	 flags;
 	if (ioc->ioc_reset_in_progress || !ioc->active)
 		goto out;
 	ioc_raw_state = mpt_GetIocState(ioc, 0);
 	if ((ioc_raw_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_FAULT) {
 		printk(MYIOC_s_WARN_FMT "IOC is in FAULT state (%04xh)!!!\n",
 		       ioc->name, ioc_raw_state & MPI_DOORBELL_DATA_MASK);
 		printk(MYIOC_s_WARN_FMT "Issuing HardReset from %s!!\n",
 		       ioc->name, __func__);
 		rc = mpt_HardResetHandler(ioc, CAN_SLEEP);
 		printk(MYIOC_s_WARN_FMT "%s: HardReset: %s\n", ioc->name,
 		       __func__, (rc == 0) ? "success" : "failed");
 		ioc_raw_state = mpt_GetIocState(ioc, 0);
 		if ((ioc_raw_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_FAULT)
 			printk(MYIOC_s_WARN_FMT "IOC is in FAULT state after "
 			    "reset (%04xh)\n", ioc->name, ioc_raw_state &
 			    MPI_DOORBELL_DATA_MASK);
 	} else if (ioc->bus_type == SAS && ioc->sas_discovery_quiesce_io) {
 		if ((mpt_is_discovery_complete(ioc))) {
 			devtprintk(ioc, printk(MYIOC_s_DEBUG_FMT "clearing "
 			    "discovery_quiesce_io flag\n", ioc->name));
 			ioc->sas_discovery_quiesce_io = 0;
 		}
 	}
 out:
 	/*
 	 * Take turns polling alternate controller
 	 */
 	if (ioc->alt_ioc)
 		ioc = ioc->alt_ioc;
 	/* rearm the timer */
 	spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
 	if (ioc->reset_work_q)
 		queue_delayed_work(ioc->reset_work_q, &ioc->fault_reset_work,
 			msecs_to_jiffies(MPT_POLLING_INTERVAL));
 	spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
 }
 /*
 *  Process turbo (context) reply...
 */
 static void
 mpt_turbo_reply(MPT_ADAPTER *ioc, u32 pa)
 {
 	MPT_FRAME_HDR *mf = NULL;
 	MPT_FRAME_HDR *mr = NULL;
 	u16 req_idx = 0;
 	u8 cb_idx;
 	dmfprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Got TURBO reply req_idx=%08x\n",
 				ioc->name, pa));
 	switch (pa >> MPI_CONTEXT_REPLY_TYPE_SHIFT) {
 	case MPI_CONTEXT_REPLY_TYPE_SCSI_INIT:
 		req_idx = pa & 0x0000FFFF;
 		cb_idx = (pa & 0x00FF0000) >> 16;
 		mf = MPT_INDEX_2_MFPTR(ioc, req_idx);
 		break;
 	case MPI_CONTEXT_REPLY_TYPE_LAN:
 		cb_idx = mpt_get_cb_idx(MPTLAN_DRIVER);
 		/*
 		 *  Blind set of mf to NULL here was fatal
 		 *  after lan_reply says "freeme"
 		 *  Fix sort of combined with an optimization here;
 		 *  added explicit check for case where lan_reply
 		 *  was just returning 1 and doing nothing else.
 		 *  For this case skip the callback, but set up
 		 *  proper mf value first here:-)
 		 */
 		if ((pa & 0x58000000) == 0x58000000) {
 			req_idx = pa & 0x0000FFFF;
 			mf = MPT_INDEX_2_MFPTR(ioc, req_idx);
 			mpt_free_msg_frame(ioc, mf);
 			mb();
 			return;
 			break;
 		}
 		mr = (MPT_FRAME_HDR *) CAST_U32_TO_PTR(pa);
 		break;
 	case MPI_CONTEXT_REPLY_TYPE_SCSI_TARGET:
 		cb_idx = mpt_get_cb_idx(MPTSTM_DRIVER);
 		mr = (MPT_FRAME_HDR *) CAST_U32_TO_PTR(pa);
 		break;
 	default:
 		cb_idx = 0;
 		BUG();
 	}
 	/*  Check for (valid) IO callback!  */
 	if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS ||
 		MptCallbacks[cb_idx] == NULL) {
 		printk(MYIOC_s_WARN_FMT "%s: Invalid cb_idx (%d)!\n",
 				__func__, ioc->name, cb_idx);
 		goto out;
 	}
 	if (MptCallbacks[cb_idx](ioc, mf, mr))
 		mpt_free_msg_frame(ioc, mf);
 out:
 	mb();
 }
 static void
 mpt_reply(MPT_ADAPTER *ioc, u32 pa)
 {
 	MPT_FRAME_HDR	*mf;
 	MPT_FRAME_HDR	*mr;
 	u16		 req_idx;
 	u8		 cb_idx;
 	int		 freeme;
 	u32 reply_dma_low;
 	u16 ioc_stat;
 	/* non-TURBO reply!  Hmmm, something may be up...
 	 *  Newest turbo reply mechanism; get address
 	 *  via left shift 1 (get rid of MPI_ADDRESS_REPLY_A_BIT)!
 	 */
 	/* Map DMA address of reply header to cpu address.
 	 * pa is 32 bits - but the dma address may be 32 or 64 bits
 	 * get offset based only only the low addresses
 	 */
 	reply_dma_low = (pa <<= 1);
 	mr = (MPT_FRAME_HDR *)((u8 *)ioc->reply_frames +
 			 (reply_dma_low - ioc->reply_frames_low_dma));
 	req_idx = le16_to_cpu(mr->u.frame.hwhdr.msgctxu.fld.req_idx);
 	cb_idx = mr->u.frame.hwhdr.msgctxu.fld.cb_idx;
 	mf = MPT_INDEX_2_MFPTR(ioc, req_idx);
 	dmfprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Got non-TURBO reply=%p req_idx=%x cb_idx=%x Function=%x\n",
 			ioc->name, mr, req_idx, cb_idx, mr->u.hdr.Function));
 	DBG_DUMP_REPLY_FRAME(ioc, (u32 *)mr);
 	 /*  Check/log IOC log info
 	 */
 	ioc_stat = le16_to_cpu(mr->u.reply.IOCStatus);
 	if (ioc_stat & MPI_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) {
 		u32	 log_info = le32_to_cpu(mr->u.reply.IOCLogInfo);
 		if (ioc->bus_type == FC)
 			mpt_fc_log_info(ioc, log_info);
 		else if (ioc->bus_type == SPI)
 			mpt_spi_log_info(ioc, log_info);
 		else if (ioc->bus_type == SAS)
 			mpt_sas_log_info(ioc, log_info);
 	}
 	if (ioc_stat & MPI_IOCSTATUS_MASK)
 		mpt_iocstatus_info(ioc, (u32)ioc_stat, mf);
 	/*  Check for (valid) IO callback!  */
 	if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS ||
 		MptCallbacks[cb_idx] == NULL) {
 		printk(MYIOC_s_WARN_FMT "%s: Invalid cb_idx (%d)!\n",
 				__func__, ioc->name, cb_idx);
 		freeme = 0;
 		goto out;
 	}
 	freeme = MptCallbacks[cb_idx](ioc, mf, mr);
 out:
 	/*  Flush (non-TURBO) reply with a WRITE!  */
 	CHIPREG_WRITE32(&ioc->chip->ReplyFifo, pa);
 	if (freeme)
 		mpt_free_msg_frame(ioc, mf);
 	mb();
 }
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /**
 *	mpt_interrupt - MPT adapter (IOC) specific interrupt handler.
 *	@irq: irq number (not used)
 *	@bus_id: bus identifier cookie == pointer to MPT_ADAPTER structure
 *
 *	This routine is registered via the request_irq() kernel API call,
 *	and handles all interrupts generated from a specific MPT adapter
 *	(also referred to as a IO Controller or IOC).
 *	This routine must clear the interrupt from the adapter and does
 *	so by reading the reply FIFO.  Multiple replies may be processed
 *	per single call to this routine.
 *
 *	This routine handles register-level access of the adapter but
 *	dispatches (calls) a protocol-specific callback routine to handle
 *	the protocol-specific details of the MPT request completion.
 */
 static irqreturn_t
 mpt_interrupt(int irq, void *bus_id)
 {
 	MPT_ADAPTER *ioc = bus_id;
 	u32 pa = CHIPREG_READ32_dmasync(&ioc->chip->ReplyFifo);
 	if (pa == 0xFFFFFFFF)
 		return IRQ_NONE;
 	/*
 	 *  Drain the reply FIFO!
 	 */
 	do {
 		if (pa & MPI_ADDRESS_REPLY_A_BIT)
 			mpt_reply(ioc, pa);
 		else
 			mpt_turbo_reply(ioc, pa);
 		pa = CHIPREG_READ32_dmasync(&ioc->chip->ReplyFifo);
 	} while (pa != 0xFFFFFFFF);
 	return IRQ_HANDLED;
 }
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /**
 *	mptbase_reply - MPT base driver's callback routine
 *	@ioc: Pointer to MPT_ADAPTER structure
 *	@req: Pointer to original MPT request frame
 *	@reply: Pointer to MPT reply frame (NULL if TurboReply)
 *
 *	MPT base driver's callback routine; all base driver
 *	"internal" request/reply processing is routed here.
 *	Currently used for EventNotification and EventAck handling.
 *
 *	Returns 1 indicating original alloc'd request frame ptr
 *	should be freed, or 0 if it shouldn't.
 */
 static int
 mptbase_reply(MPT_ADAPTER *ioc, MPT_FRAME_HDR *req, MPT_FRAME_HDR *reply)
 {
 	EventNotificationReply_t *pEventReply;
 	u8 event;
 	int evHandlers;
 	int freereq = 1;
 	switch (reply->u.hdr.Function) {
 	case MPI_FUNCTION_EVENT_NOTIFICATION:
 		pEventReply = (EventNotificationReply_t *)reply;
 		evHandlers = 0;
 		ProcessEventNotification(ioc, pEventReply, &evHandlers);
 		event = le32_to_cpu(pEventReply->Event) & 0xFF;
 		if (pEventReply->MsgFlags & MPI_MSGFLAGS_CONTINUATION_REPLY)
 			freereq = 0;
 		if (event != MPI_EVENT_EVENT_CHANGE)
 			break;
 	case MPI_FUNCTION_CONFIG:
 	case MPI_FUNCTION_SAS_IO_UNIT_CONTROL:
 		ioc->mptbase_cmds.status |= MPT_MGMT_STATUS_COMMAND_GOOD;
 		if (reply) {
 			ioc->mptbase_cmds.status |= MPT_MGMT_STATUS_RF_VALID;
 			memcpy(ioc->mptbase_cmds.reply, reply,
 			    min(MPT_DEFAULT_FRAME_SIZE,
 				4 * reply->u.reply.MsgLength));
 		}
 		if (ioc->mptbase_cmds.status & MPT_MGMT_STATUS_PENDING) {
 			ioc->mptbase_cmds.status &= ~MPT_MGMT_STATUS_PENDING;
 			complete(&ioc->mptbase_cmds.done);
 		} else
 			freereq = 0;
 		if (ioc->mptbase_cmds.status & MPT_MGMT_STATUS_FREE_MF)
 			freereq = 1;
 		break;
 	case MPI_FUNCTION_EVENT_ACK:
 		devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT
 		    "EventAck reply received\n", ioc->name));
 		break;
 	default:
 		printk(MYIOC_s_ERR_FMT
 		    "Unexpected msg function (=%02Xh) reply received!\n",
 		    ioc->name, reply->u.hdr.Function);
 		break;
 	}
 	/*
 	 *	Conditionally tell caller to free the original
 	 *	EventNotification/EventAck/unexpected request frame!
 	 */
 	return freereq;
 }
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /**
 *	mpt_register - Register protocol-specific main callback handler.
 *	@cbfunc: callback function pointer
 *	@dclass: Protocol driver's class (%MPT_DRIVER_CLASS enum value)
 *
 *	This routine is called by a protocol-specific driver (SCSI host,
 *	LAN, SCSI target) to register its reply callback routine.  Each
 *	protocol-specific driver must do this before it will be able to
 *	use any IOC resources, such as obtaining request frames.
 *
 *	NOTES: The SCSI protocol driver currently calls this routine thrice
 *	in order to register separate callbacks; one for "normal" SCSI IO;
 *	one for MptScsiTaskMgmt requests; one for Scan/DV requests.
 *
 *	Returns u8 valued "handle" in the range (and S.O.D. order)
 *	{N,...,7,6,5,...,1} if successful.
 *	A return value of MPT_MAX_PROTOCOL_DRIVERS (including zero!) should be
 *	considered an error by the caller.
 */
 u8
 mpt_register(MPT_CALLBACK cbfunc, MPT_DRIVER_CLASS dclass)
 {
 	u8 cb_idx;
 	last_drv_idx = MPT_MAX_PROTOCOL_DRIVERS;
 	/*
 	 *  Search for empty callback slot in this order: {N,...,7,6,5,...,1}
 	 *  (slot/handle 0 is reserved!)
 	 */
 	for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
 		if (MptCallbacks[cb_idx] == NULL) {
 			MptCallbacks[cb_idx] = cbfunc;
 			MptDriverClass[cb_idx] = dclass;
 			MptEvHandlers[cb_idx] = NULL;
 			last_drv_idx = cb_idx;
 			break;
 		}
 	}
 	return last_drv_idx;
 }
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /**
 *	mpt_deregister - Deregister a protocol drivers resources.
 *	@cb_idx: previously registered callback handle
 *
 *	Each protocol-specific driver should call this routine when its
 *	module is unloaded.
 */
 void
 mpt_deregister(u8 cb_idx)
 {
 	if (cb_idx && (cb_idx < MPT_MAX_PROTOCOL_DRIVERS)) {
 		MptCallbacks[cb_idx] = NULL;
 		MptDriverClass[cb_idx] = MPTUNKNOWN_DRIVER;
 		MptEvHandlers[cb_idx] = NULL;
 		last_drv_idx++;
 	}
 }
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /**
 *	mpt_event_register - Register protocol-specific event callback handler.
 *	@cb_idx: previously registered (via mpt_register) callback handle
 *	@ev_cbfunc: callback function
 *
 *	This routine can be called by one or more protocol-specific drivers
 *	if/when they choose to be notified of MPT events.
 *
 *	Returns 0 for success.
 */
 int
 mpt_event_register(u8 cb_idx, MPT_EVHANDLER ev_cbfunc)
 {
 	if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS)
 		return -1;
 	MptEvHandlers[cb_idx] = ev_cbfunc;
 	return 0;
 }
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /**
 *	mpt_event_deregister - Deregister protocol-specific event callback handler
 *	@cb_idx: previously registered callback handle
 *
 *	Each protocol-specific driver should call this routine
 *	when it does not (or can no longer) handle events,
 *	or when its module is unloaded.
 */
 void
 mpt_event_deregister(u8 cb_idx)
 {
 	if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS)
 		return;
 	MptEvHandlers[cb_idx] = NULL;
 }
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /**
 *	mpt_reset_register - Register protocol-specific IOC reset handler.
 *	@cb_idx: previously registered (via mpt_register) callback handle
 *	@reset_func: reset function
 *
 *	This routine can be called by one or more protocol-specific drivers
 *	if/when they choose to be notified of IOC resets.
 *
 *	Returns 0 for success.
 */
 int
 mpt_reset_register(u8 cb_idx, MPT_RESETHANDLER reset_func)
 {
 	if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS)
 		return -1;
 	MptResetHandlers[cb_idx] = reset_func;
 	return 0;
 }
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /**
 *	mpt_reset_deregister - Deregister protocol-specific IOC reset handler.
 *	@cb_idx: previously registered callback handle
 *
 *	Each protocol-specific driver should call this routine
 *	when it does not (or can no longer) handle IOC reset handling,
 *	or when its module is unloaded.
 */
 void
 mpt_reset_deregister(u8 cb_idx)
 {
 	if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS)
 		return;
 	MptResetHandlers[cb_idx] = NULL;
 }
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /**
 *	mpt_device_driver_register - Register device driver hooks
 *	@dd_cbfunc: driver callbacks struct
 *	@cb_idx: MPT protocol driver index
 */
 int
 mpt_device_driver_register(struct mpt_pci_driver * dd_cbfunc, u8 cb_idx)
 {
 	MPT_ADAPTER	*ioc;
 	const struct pci_device_id *id;
 	if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS)
 		return -EINVAL;
 	MptDeviceDriverHandlers[cb_idx] = dd_cbfunc;
 	/* call per pci device probe entry point */
 	list_for_each_entry(ioc, &ioc_list, list) {
 		id = ioc->pcidev->driver ?
 		    ioc->pcidev->driver->id_table : NULL;
 		if (dd_cbfunc->probe)
 			dd_cbfunc->probe(ioc->pcidev, id);
 	 }
 	return 0;
 }
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /**
 *	mpt_device_driver_deregister - DeRegister device driver hooks
 *	@cb_idx: MPT protocol driver index
 */
 void
 mpt_device_driver_deregister(u8 cb_idx)
 {
 	struct mpt_pci_driver *dd_cbfunc;
 	MPT_ADAPTER	*ioc;
 	if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS)
 		return;
 	dd_cbfunc = MptDeviceDriverHandlers[cb_idx];
 	list_for_each_entry(ioc, &ioc_list, list) {
 		if (dd_cbfunc->remove)
 			dd_cbfunc->remove(ioc->pcidev);
 	}
 	MptDeviceDriverHandlers[cb_idx] = NULL;
 }
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /**
 *	mpt_get_msg_frame - Obtain an MPT request frame from the pool
 *	@cb_idx: Handle of registered MPT protocol driver
 *	@ioc: Pointer to MPT adapter structure
 *
 *	Obtain an MPT request frame from the pool (of 1024) that are
 *	allocated per MPT adapter.
 *
 *	Returns pointer to a MPT request frame or %NULL if none are available
 *	or IOC is not active.
 */
 MPT_FRAME_HDR*
 mpt_get_msg_frame(u8 cb_idx, MPT_ADAPTER *ioc)
 {
 	MPT_FRAME_HDR *mf;
 	unsigned long flags;
 	u16	 req_idx;	/* Request index */
 	/* validate handle and ioc identifier */
 #ifdef MFCNT
 	if (!ioc->active)
 		printk(MYIOC_s_WARN_FMT "IOC Not Active! mpt_get_msg_frame "
 		    "returning NULL!\n", ioc->name);
 #endif
 	/* If interrupts are not attached, do not return a request frame */
 	if (!ioc->active)
 		return NULL;
 	spin_lock_irqsave(&ioc->FreeQlock, flags);
 	if (!list_empty(&ioc->FreeQ)) {
 		int req_offset;
 		mf = list_entry(ioc->FreeQ.next, MPT_FRAME_HDR,
 				u.frame.linkage.list);
 		list_del(&mf->u.frame.linkage.list);
 		mf->u.frame.linkage.arg1 = 0;
 		mf->u.frame.hwhdr.msgctxu.fld.cb_idx = cb_idx;	/* byte */
 		req_offset = (u8 *)mf - (u8 *)ioc->req_frames;
 								/* u16! */
 		req_idx = req_offset / ioc->req_sz;
 		mf->u.frame.hwhdr.msgctxu.fld.req_idx = cpu_to_le16(req_idx);
 		mf->u.frame.hwhdr.msgctxu.fld.rsvd = 0;
 		/* Default, will be changed if necessary in SG generation */
 		ioc->RequestNB[req_idx] = ioc->NB_for_64_byte_frame;
 #ifdef MFCNT
 		ioc->mfcnt++;
 #endif
 	}
 	else
 		mf = NULL;
 	spin_unlock_irqrestore(&ioc->FreeQlock, flags);
 #ifdef MFCNT
 	if (mf == NULL)
 		printk(MYIOC_s_WARN_FMT "IOC Active. No free Msg Frames! "
 		    "Count 0x%x Max 0x%x\n", ioc->name, ioc->mfcnt,
 		    ioc->req_depth);
 	mfcounter++;
 	if (mfcounter == PRINT_MF_COUNT)
 		printk(MYIOC_s_INFO_FMT "MF Count 0x%x Max 0x%x \n", ioc->name,
 		    ioc->mfcnt, ioc->req_depth);
 #endif
 	dmfprintk(ioc, printk(MYIOC_s_DEBUG_FMT "mpt_get_msg_frame(%d,%d), got mf=%p\n",
 	    ioc->name, cb_idx, ioc->id, mf));
 	return mf;
 }
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /**
 *	mpt_put_msg_frame - Send a protocol-specific MPT request frame to an IOC
 *	@cb_idx: Handle of registered MPT protocol driver
 *	@ioc: Pointer to MPT adapter structure
 *	@mf: Pointer to MPT request frame
 *
 *	This routine posts an MPT request frame to the request post FIFO of a
 *	specific MPT adapter.
 */
 void
 mpt_put_msg_frame(u8 cb_idx, MPT_ADAPTER *ioc, MPT_FRAME_HDR *mf)
 {
 	u32 mf_dma_addr;
 	int req_offset;
 	u16	 req_idx;	/* Request index */
 	/* ensure values are reset properly! */
 	mf->u.frame.hwhdr.msgctxu.fld.cb_idx = cb_idx;		/* byte */
 	req_offset = (u8 *)mf - (u8 *)ioc->req_frames;
 								/* u16! */
 	req_idx = req_offset / ioc->req_sz;
 	mf->u.frame.hwhdr.msgctxu.fld.req_idx = cpu_to_le16(req_idx);
 	mf->u.frame.hwhdr.msgctxu.fld.rsvd = 0;
 	DBG_DUMP_PUT_MSG_FRAME(ioc, (u32 *)mf);
 	mf_dma_addr = (ioc->req_frames_low_dma + req_offset) | ioc->RequestNB[req_idx];
 	dsgprintk(ioc, printk(MYIOC_s_DEBUG_FMT "mf_dma_addr=%x req_idx=%d "
 	    "RequestNB=%x\n", ioc->name, mf_dma_addr, req_idx,
 	    ioc->RequestNB[req_idx]));
 	CHIPREG_WRITE32(&ioc->chip->RequestFifo, mf_dma_addr);
 }
 /**
 *	mpt_put_msg_frame_hi_pri - Send a hi-pri protocol-specific MPT request frame
 *	@cb_idx: Handle of registered MPT protocol driver
 *	@ioc: Pointer to MPT adapter structure
 *	@mf: Pointer to MPT request frame
 *
 *	Send a protocol-specific MPT request frame to an IOC using
 *	hi-priority request queue.
 *
 *	This routine posts an MPT request frame to the request post FIFO of a
 *	specific MPT adapter.
 **/
 void
 mpt_put_msg_frame_hi_pri(u8 cb_idx, MPT_ADAPTER *ioc, MPT_FRAME_HDR *mf)
 {
 	u32 mf_dma_addr;
 	int req_offset;
 	u16	 req_idx;	/* Request index */
 	/* ensure values are reset properly! */
 	mf->u.frame.hwhdr.msgctxu.fld.cb_idx = cb_idx;
 	req_offset = (u8 *)mf - (u8 *)ioc->req_frames;
 	req_idx = req_offset / ioc->req_sz;
 	mf->u.frame.hwhdr.msgctxu.fld.req_idx = cpu_to_le16(req_idx);
 	mf->u.frame.hwhdr.msgctxu.fld.rsvd = 0;
 	DBG_DUMP_PUT_MSG_FRAME(ioc, (u32 *)mf);
 	mf_dma_addr = (ioc->req_frames_low_dma + req_offset);
 	dsgprintk(ioc, printk(MYIOC_s_DEBUG_FMT "mf_dma_addr=%x req_idx=%d\n",
 		ioc->name, mf_dma_addr, req_idx));
 	CHIPREG_WRITE32(&ioc->chip->RequestHiPriFifo, mf_dma_addr);
 }
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /**
 *	mpt_free_msg_frame - Place MPT request frame back on FreeQ.
 *	@ioc: Pointer to MPT adapter structure
 *	@mf: Pointer to MPT request frame
 *
 *	This routine places a MPT request frame back on the MPT adapter's
 *	FreeQ.
 */
 void
 mpt_free_msg_frame(MPT_ADAPTER *ioc, MPT_FRAME_HDR *mf)
 {
 	unsigned long flags;
 	/*  Put Request back on FreeQ!  */
 	spin_lock_irqsave(&ioc->FreeQlock, flags);
 	if (cpu_to_le32(mf->u.frame.linkage.arg1) == 0xdeadbeaf)
 		goto out;
 	/* signature to know if this mf is freed */
 	mf->u.frame.linkage.arg1 = cpu_to_le32(0xdeadbeaf);
 	list_add_tail(&mf->u.frame.linkage.list, &ioc->FreeQ);
 #ifdef MFCNT
 	ioc->mfcnt--;
 #endif
 out:
 	spin_unlock_irqrestore(&ioc->FreeQlock, flags);
 }
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /**
 *	mpt_add_sge - Place a simple 32 bit SGE at address pAddr.
 *	@pAddr: virtual address for SGE
 *	@flagslength: SGE flags and data transfer length
 *	@dma_addr: Physical address
 *
 *	This routine places a MPT request frame back on the MPT adapter's
 *	FreeQ.
 */
 static void
 mpt_add_sge(void *pAddr, u32 flagslength, dma_addr_t dma_addr)
 {
 	SGESimple32_t *pSge = (SGESimple32_t *) pAddr;
 	pSge->FlagsLength = cpu_to_le32(flagslength);
 	pSge->Address = cpu_to_le32(dma_addr);
 }
 /**
 *	mpt_add_sge_64bit - Place a simple 64 bit SGE at address pAddr.
 *	@pAddr: virtual address for SGE
 *	@flagslength: SGE flags and data transfer length
 *	@dma_addr: Physical address
 *
 *	This routine places a MPT request frame back on the MPT adapter's
 *	FreeQ.
 **/
 static void
 mpt_add_sge_64bit(void *pAddr, u32 flagslength, dma_addr_t dma_addr)
 {
 	SGESimple64_t *pSge = (SGESimple64_t *) pAddr;
 	pSge->Address.Low = cpu_to_le32
 			(lower_32_bits(dma_addr));
 	pSge->Address.High = cpu_to_le32
 			(upper_32_bits(dma_addr));
 	pSge->FlagsLength = cpu_to_le32
 			((flagslength | MPT_SGE_FLAGS_64_BIT_ADDRESSING));
 }
 /**
 *	mpt_add_sge_64bit_1078 - Place a simple 64 bit SGE at address pAddr (1078 workaround).
 *	@pAddr: virtual address for SGE
 *	@flagslength: SGE flags and data transfer length
 *	@dma_addr: Physical address
 *
 *	This routine places a MPT request frame back on the MPT adapter's
 *	FreeQ.
 **/
 static void
 mpt_add_sge_64bit_1078(void *pAddr, u32 flagslength, dma_addr_t dma_addr)
 {
 	SGESimple64_t *pSge = (SGESimple64_t *) pAddr;
 	u32 tmp;
 	pSge->Address.Low = cpu_to_le32
 			(lower_32_bits(dma_addr));
 	tmp = (u32)(upper_32_bits(dma_addr));
 	/*
 	 * 1078 errata workaround for the 36GB limitation
 	 */
 	if ((((u64)dma_addr + MPI_SGE_LENGTH(flagslength)) >> 32)  == 9) {
 		flagslength |=
 		    MPI_SGE_SET_FLAGS(MPI_SGE_FLAGS_LOCAL_ADDRESS);
 		tmp |= (1<<31);
 		if (mpt_debug_level & MPT_DEBUG_36GB_MEM)
 			printk(KERN_DEBUG "1078 P0M2 addressing for "
 			    "addr = 0x%llx len = %d\n",
 			    (unsigned long long)dma_addr,
 			    MPI_SGE_LENGTH(flagslength));
 	}
 	pSge->Address.High = cpu_to_le32(tmp);
 	pSge->FlagsLength = cpu_to_le32(
 		(flagslength | MPT_SGE_FLAGS_64_BIT_ADDRESSING));
 }
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /**
 *	mpt_add_chain - Place a 32 bit chain SGE at address pAddr.
 *	@pAddr: virtual address for SGE
 *	@next: nextChainOffset value (u32's)
 *	@length: length of next SGL segment
 *	@dma_addr: Physical address
 *
 */
 static void
 mpt_add_chain(void *pAddr, u8 next, u16 length, dma_addr_t dma_addr)
 {
 		SGEChain32_t *pChain = (SGEChain32_t *) pAddr;
 		pChain->Length = cpu_to_le16(length);
 		pChain->Flags = MPI_SGE_FLAGS_CHAIN_ELEMENT;
 		pChain->NextChainOffset = next;
 		pChain->Address = cpu_to_le32(dma_addr);
 }
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /**
 *	mpt_add_chain_64bit - Place a 64 bit chain SGE at address pAddr.
 *	@pAddr: virtual address for SGE
 *	@next: nextChainOffset value (u32's)
 *	@length: length of next SGL segment
 *	@dma_addr: Physical address
 *
 */
 static void
 mpt_add_chain_64bit(void *pAddr, u8 next, u16 length, dma_addr_t dma_addr)
 {
 		SGEChain64_t *pChain = (SGEChain64_t *) pAddr;
 		u32 tmp = dma_addr & 0xFFFFFFFF;
 		pChain->Length = cpu_to_le16(length);
 		pChain->Flags = (MPI_SGE_FLAGS_CHAIN_ELEMENT |
 				 MPI_SGE_FLAGS_64_BIT_ADDRESSING);
 		pChain->NextChainOffset = next;
 		pChain->Address.Low = cpu_to_le32(tmp);
 		tmp = (u32)(upper_32_bits(dma_addr));
 		pChain->Address.High = cpu_to_le32(tmp);
 }
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /**
 *	mpt_send_handshake_request - Send MPT request via doorbell handshake method.
 *	@cb_idx: Handle of registered MPT protocol driver
 *	@ioc: Pointer to MPT adapter structure
 *	@reqBytes: Size of the request in bytes
 *	@req: Pointer to MPT request frame
 *	@sleepFlag: Use schedule if CAN_SLEEP else use udelay.
 *
 *	This routine is used exclusively to send MptScsiTaskMgmt
 *	requests since they are required to be sent via doorbell handshake.
 *
 *	NOTE: It is the callers responsibility to byte-swap fields in the
 *	request which are greater than 1 byte in size.
 *
 *	Returns 0 for success, non-zero for failure.
 */
 int
 mpt_send_handshake_request(u8 cb_idx, MPT_ADAPTER *ioc, int reqBytes, u32 *req, int sleepFlag)
 {
 	int	r = 0;
 	u8	*req_as_bytes;
 	int	 ii;
 	/* State is known to be good upon entering
 	 * this function so issue the bus reset
 	 * request.
 	 */
 	/*
 	 * Emulate what mpt_put_msg_frame() does /wrt to sanity
 	 * setting cb_idx/req_idx.  But ONLY if this request
 	 * is in proper (pre-alloc'd) request buffer range...
 	 */
 	ii = MFPTR_2_MPT_INDEX(ioc,(MPT_FRAME_HDR*)req);
 	if (reqBytes >= 12 && ii >= 0 && ii < ioc->req_depth) {
 		MPT_FRAME_HDR *mf = (MPT_FRAME_HDR*)req;
 		mf->u.frame.hwhdr.msgctxu.fld.req_idx = cpu_to_le16(ii);
 		mf->u.frame.hwhdr.msgctxu.fld.cb_idx = cb_idx;
 	}
 	/* Make sure there are no doorbells */
 	CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
 	CHIPREG_WRITE32(&ioc->chip->Doorbell,
 			((MPI_FUNCTION_HANDSHAKE<<MPI_DOORBELL_FUNCTION_SHIFT) |
 			 ((reqBytes/4)<<MPI_DOORBELL_ADD_DWORDS_SHIFT)));
 	/* Wait for IOC doorbell int */
 	if ((ii = WaitForDoorbellInt(ioc, 5, sleepFlag)) < 0) {
 		return ii;
 	}
 	/* Read doorbell and check for active bit */
 	if (!(CHIPREG_READ32(&ioc->chip->Doorbell) & MPI_DOORBELL_ACTIVE))
 		return -5;
 	dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "mpt_send_handshake_request start, WaitCnt=%d\n",
 		ioc->name, ii));
 	CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
 	if ((r = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0) {
 		return -2;
 	}
 	/* Send request via doorbell handshake */
 	req_as_bytes = (u8 *) req;
 	for (ii = 0; ii < reqBytes/4; ii++) {
 		u32 word;
 		word = ((req_as_bytes[(ii*4) + 0] <<  0) |
 			(req_as_bytes[(ii*4) + 1] <<  8) |
 			(req_as_bytes[(ii*4) + 2] << 16) |
 			(req_as_bytes[(ii*4) + 3] << 24));
 		CHIPREG_WRITE32(&ioc->chip->Doorbell, word);
 		if ((r = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0) {
 			r = -3;
 			break;
 		}
 	}
 	if (r >= 0 && WaitForDoorbellInt(ioc, 10, sleepFlag) >= 0)
 		r = 0;
 	else
 		r = -4;
 	/* Make sure there are no doorbells */
 	CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
 	return r;
 }
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /**
 * mpt_host_page_access_control - control the IOC's Host Page Buffer access
 * @ioc: Pointer to MPT adapter structure
 * @access_control_value: define bits below
 * @sleepFlag: Specifies whether the process can sleep
 *
 * Provides mechanism for the host driver to control the IOC's
 * Host Page Buffer access.
 *
 * Access Control Value - bits[15:12]
 * 0h Reserved
 * 1h Enable Access { MPI_DB_HPBAC_ENABLE_ACCESS }
 * 2h Disable Access { MPI_DB_HPBAC_DISABLE_ACCESS }
 * 3h Free Buffer { MPI_DB_HPBAC_FREE_BUFFER }
 *
 * Returns 0 for success, non-zero for failure.
 */
 static int
 mpt_host_page_access_control(MPT_ADAPTER *ioc, u8 access_control_value, int sleepFlag)
 {
 	int	 r = 0;
 	/* return if in use */
 	if (CHIPREG_READ32(&ioc->chip->Doorbell)
 	    & MPI_DOORBELL_ACTIVE)
 	    return -1;
 	CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
 	CHIPREG_WRITE32(&ioc->chip->Doorbell,
 		((MPI_FUNCTION_HOST_PAGEBUF_ACCESS_CONTROL
 		 <<MPI_DOORBELL_FUNCTION_SHIFT) |
 		 (access_control_value<<12)));
 	/* Wait for IOC to clear Doorbell Status bit */
 	if ((r = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0) {
 		return -2;
 	}else
 		return 0;
 }
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /**
 *	mpt_host_page_alloc - allocate system memory for the fw
 *	@ioc: Pointer to pointer to IOC adapter
 *	@ioc_init: Pointer to ioc init config page
 *
 *	If we already allocated memory in past, then resend the same pointer.
 *	Returns 0 for success, non-zero for failure.
 */
 static int
 mpt_host_page_alloc(MPT_ADAPTER *ioc, pIOCInit_t ioc_init)
 {
 	char	*psge;
 	int	flags_length;
 	u32	host_page_buffer_sz=0;
 	if(!ioc->HostPageBuffer) {
 		host_page_buffer_sz =
 		    le32_to_cpu(ioc->facts.HostPageBufferSGE.FlagsLength) & 0xFFFFFF;
 		if(!host_page_buffer_sz)
 			return 0; /* fw doesn't need any host buffers */
 		/* spin till we get enough memory */
 		while(host_page_buffer_sz > 0) {
 			if((ioc->HostPageBuffer = pci_alloc_consistent(
 			    ioc->pcidev,
 			    host_page_buffer_sz,
 			    &ioc->HostPageBuffer_dma)) != NULL) {
 				dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT
 				    "host_page_buffer @ %p, dma @ %x, sz=%d bytes\n",
 				    ioc->name, ioc->HostPageBuffer,
 				    (u32)ioc->HostPageBuffer_dma,
 				    host_page_buffer_sz));
 				ioc->alloc_total += host_page_buffer_sz;
 				ioc->HostPageBuffer_sz = host_page_buffer_sz;
 				break;
 			}
 			host_page_buffer_sz -= (4*1024);
 		}
 	}
 	if(!ioc->HostPageBuffer) {
 		printk(MYIOC_s_ERR_FMT
 		    "Failed to alloc memory for host_page_buffer!\n",
 		    ioc->name);
 		return -999;
 	}
 	psge = (char *)&ioc_init->HostPageBufferSGE;
 	flags_length = MPI_SGE_FLAGS_SIMPLE_ELEMENT |
 	    MPI_SGE_FLAGS_SYSTEM_ADDRESS |
 	    MPI_SGE_FLAGS_HOST_TO_IOC |
 	    MPI_SGE_FLAGS_END_OF_BUFFER;
 	flags_length = flags_length << MPI_SGE_FLAGS_SHIFT;
 	flags_length |= ioc->HostPageBuffer_sz;
 	ioc->add_sge(psge, flags_length, ioc->HostPageBuffer_dma);
 	ioc->facts.HostPageBufferSGE = ioc_init->HostPageBufferSGE;
 return 0;
 }
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /**
 *	mpt_verify_adapter - Given IOC identifier, set pointer to its adapter structure.
 *	@iocid: IOC unique identifier (integer)
 *	@iocpp: Pointer to pointer to IOC adapter
 *
 *	Given a unique IOC identifier, set pointer to the associated MPT
 *	adapter structure.
 *
 *	Returns iocid and sets iocpp if iocid is found.
 *	Returns -1 if iocid is not found.
 */
 int
 mpt_verify_adapter(int iocid, MPT_ADAPTER **iocpp)
 {
 	MPT_ADAPTER *ioc;
 	list_for_each_entry(ioc,&ioc_list,list) {
 		if (ioc->id == iocid) {
 			*iocpp =ioc;
 			return iocid;
 		}
 	}
 	*iocpp = NULL;
 	return -1;
 }
 /**
 *	mpt_get_product_name - returns product string
 *	@vendor: pci vendor id
 *	@device: pci device id
 *	@revision: pci revision id
 *	@prod_name: string returned
 *
 *	Returns product string displayed when driver loads,
 *	in /proc/mpt/summary and /sysfs/class/scsi_host/host<X>/version_product
 *
 **/
 static void
 mpt_get_product_name(u16 vendor, u16 device, u8 revision, char *prod_name)
 {
 	char *product_str = NULL;
 	if (vendor == PCI_VENDOR_ID_BROCADE) {
 		switch (device)
 		{
 		case MPI_MANUFACTPAGE_DEVICEID_FC949E:
 			switch (revision)
 			{
 			case 0x00:
 				product_str = "BRE040 A0";
 				break;
 			case 0x01:
 				product_str = "BRE040 A1";
 				break;
 			default:
 				product_str = "BRE040";
 				break;
 			}
 			break;
 		}
 		goto out;
 	}
 	switch (device)
 	{
 	case MPI_MANUFACTPAGE_DEVICEID_FC909:
 		product_str = "LSIFC909 B1";
 		break;
 	case MPI_MANUFACTPAGE_DEVICEID_FC919:
 		product_str = "LSIFC919 B0";
 		break;
 	case MPI_MANUFACTPAGE_DEVICEID_FC929:
 		product_str = "LSIFC929 B0";
 		break;
 	case MPI_MANUFACTPAGE_DEVICEID_FC919X:
 		if (revision < 0x80)
 			product_str = "LSIFC919X A0";
 		else
 			product_str = "LSIFC919XL A1";
 		break;
 	case MPI_MANUFACTPAGE_DEVICEID_FC929X:
 		if (revision < 0x80)
 			product_str = "LSIFC929X A0";
 		else
 			product_str = "LSIFC929XL A1";
 		break;
 	case MPI_MANUFACTPAGE_DEVICEID_FC939X:
 		product_str = "LSIFC939X A1";
 		break;
 	case MPI_MANUFACTPAGE_DEVICEID_FC949X:
 		product_str = "LSIFC949X A1";
 		break;
 	case MPI_MANUFACTPAGE_DEVICEID_FC949E:
 		switch (revision)
 		{
 		case 0x00:
 			product_str = "LSIFC949E A0";
 			break;
 		case 0x01:
 			product_str = "LSIFC949E A1";
 			break;
 		default:
 			product_str = "LSIFC949E";
 			break;
 		}
 		break;
 	case MPI_MANUFACTPAGE_DEVID_53C1030:
 		switch (revision)
 		{
 		case 0x00:
 			product_str = "LSI53C1030 A0";
 			break;
 		case 0x01:
 			product_str = "LSI53C1030 B0";
 			break;
 		case 0x03:
 			product_str = "LSI53C1030 B1";
 			break;
 		case 0x07:
 			product_str = "LSI53C1030 B2";
 			break;
 		case 0x08:
 			product_str = "LSI53C1030 C0";
 			break;
 		case 0x80:
 			product_str = "LSI53C1030T A0";
 			break;
 		case 0x83:
 			product_str = "LSI53C1030T A2";
 			break;
 		case 0x87:
 			product_str = "LSI53C1030T A3";
 			break;
 		case 0xc1:
 			product_str = "LSI53C1020A A1";
 			break;
 		default:
 			product_str = "LSI53C1030";
 			break;
 		}
 		break;
 	case MPI_MANUFACTPAGE_DEVID_1030_53C1035:
 		switch (revision)
 		{
 		case 0x03:
 			product_str = "LSI53C1035 A2";
 			break;
 		case 0x04:
 			product_str = "LSI53C1035 B0";
 			break;
 		default:
 			product_str = "LSI53C1035";
 			break;
 		}
 		break;
 	case MPI_MANUFACTPAGE_DEVID_SAS1064:
 		switch (revision)
 		{
 		case 0x00:
 			product_str = "LSISAS1064 A1";
 			break;
 		case 0x01:
 			product_str = "LSISAS1064 A2";
 			break;
 		case 0x02:
 			product_str = "LSISAS1064 A3";
 			break;
 		case 0x03:
 			product_str = "LSISAS1064 A4";
 			break;
 		default:
 			product_str = "LSISAS1064";
 			break;
 		}
 		break;
 	case MPI_MANUFACTPAGE_DEVID_SAS1064E:
 		switch (revision)
 		{
 		case 0x00:
 			product_str = "LSISAS1064E A0";
 			break;
 		case 0x01:
 			product_str = "LSISAS1064E B0";
 			break;
 		case 0x02:
 			product_str = "LSISAS1064E B1";
 			break;
 		case 0x04:
 			product_str = "LSISAS1064E B2";
 			break;
 		case 0x08:
 			product_str = "LSISAS1064E B3";
 			break;
 		default:
 			product_str = "LSISAS1064E";
 			break;
 		}
 		break;
 	case MPI_MANUFACTPAGE_DEVID_SAS1068:
 		switch (revision)
 		{
 		case 0x00:
 			product_str = "LSISAS1068 A0";
 			break;
 		case 0x01:
 			product_str = "LSISAS1068 B0";
 			break;
 		case 0x02:
 			product_str = "LSISAS1068 B1";
 			break;
 		default:
 			product_str = "LSISAS1068";
 			break;
 		}
 		break;
 	case MPI_MANUFACTPAGE_DEVID_SAS1068E:
 		switch (revision)
 		{
 		case 0x00:
 			product_str = "LSISAS1068E A0";
 			break;
 		case 0x01:
 			product_str = "LSISAS1068E B0";
 			break;
 		case 0x02:
 			product_str = "LSISAS1068E B1";
 			break;
 		case 0x04:
 			product_str = "LSISAS1068E B2";
 			break;
 		case 0x08:
 			product_str = "LSISAS1068E B3";
 			break;
 		default:
 			product_str = "LSISAS1068E";
 			break;
 		}
 		break;
 	case MPI_MANUFACTPAGE_DEVID_SAS1078:
 		switch (revision)
 		{
 		case 0x00:
 			product_str = "LSISAS1078 A0";
 			break;
 		case 0x01:
 			product_str = "LSISAS1078 B0";
 			break;
 		case 0x02:
 			product_str = "LSISAS1078 C0";
 			break;
 		case 0x03:
 			product_str = "LSISAS1078 C1";
 			break;
 		case 0x04:
 			product_str = "LSISAS1078 C2";
 			break;
 		default:
 			product_str = "LSISAS1078";
 			break;
 		}
 		break;
 	}
 out:
 	if (product_str)
 		sprintf(prod_name, "%s", product_str);
 }
 /**
 *	mpt_mapresources - map in memory mapped io
 *	@ioc: Pointer to pointer to IOC adapter
 *
 **/
 static int
 mpt_mapresources(MPT_ADAPTER *ioc)
 {
 	u8		__iomem *mem;
 	int		 ii;
 	unsigned long	 mem_phys;
 	unsigned long	 port;
 	u32		 msize;
 	u32		 psize;
 	u8		 revision;
 	int		 r = -ENODEV;
 	struct pci_dev *pdev;
 	pdev = ioc->pcidev;
 	ioc->bars = pci_select_bars(pdev, IORESOURCE_MEM);
 	if (pci_enable_device_mem(pdev)) {
 		printk(MYIOC_s_ERR_FMT "pci_enable_device_mem() "
 		    "failed\n", ioc->name);
 		return r;
 	}
 	if (pci_request_selected_regions(pdev, ioc->bars, "mpt")) {
 		printk(MYIOC_s_ERR_FMT "pci_request_selected_regions() with "
 		    "MEM failed\n", ioc->name);
 		return r;
 	}
 	pci_read_config_byte(pdev, PCI_CLASS_REVISION, &revision);
 	if (sizeof(dma_addr_t) > 4) {
 		const uint64_t required_mask = dma_get_required_mask
 		    (&pdev->dev);
 		if (required_mask > DMA_BIT_MASK(32)
 			&& !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
 			&& !pci_set_consistent_dma_mask(pdev,
 						 DMA_BIT_MASK(64))) {
 			ioc->dma_mask = DMA_BIT_MASK(64);
 			dinitprintk(ioc, printk(MYIOC_s_INFO_FMT
 				": 64 BIT PCI BUS DMA ADDRESSING SUPPORTED\n",
 				ioc->name));
 		} else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))
 			&& !pci_set_consistent_dma_mask(pdev,
 						DMA_BIT_MASK(32))) {
 			ioc->dma_mask = DMA_BIT_MASK(32);
 			dinitprintk(ioc, printk(MYIOC_s_INFO_FMT
 				": 32 BIT PCI BUS DMA ADDRESSING SUPPORTED\n",
 				ioc->name));
 		} else {
 			printk(MYIOC_s_WARN_FMT "no suitable DMA mask for %s\n",
 			    ioc->name, pci_name(pdev));
 			return r;
 		}
 	} else {
 		if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))
 			&& !pci_set_consistent_dma_mask(pdev,
 						DMA_BIT_MASK(32))) {
 			ioc->dma_mask = DMA_BIT_MASK(32);
 			dinitprintk(ioc, printk(MYIOC_s_INFO_FMT
 				": 32 BIT PCI BUS DMA ADDRESSING SUPPORTED\n",
 				ioc->name));
 		} else {
 			printk(MYIOC_s_WARN_FMT "no suitable DMA mask for %s\n",
 			    ioc->name, pci_name(pdev));
 			return r;
 		}
 	}
 	mem_phys = msize = 0;
 	port = psize = 0;
 	for (ii = 0; ii < DEVICE_COUNT_RESOURCE; ii++) {
 		if (pci_resource_flags(pdev, ii) & PCI_BASE_ADDRESS_SPACE_IO) {
 			if (psize)
 				continue;
 			/* Get I/O space! */
 			port = pci_resource_start(pdev, ii);
 			psize = pci_resource_len(pdev, ii);
 		} else {
 			if (msize)
 				continue;
 			/* Get memmap */
 			mem_phys = pci_resource_start(pdev, ii);
 			msize = pci_resource_len(pdev, ii);
 		}
 	}
 	ioc->mem_size = msize;
 	mem = NULL;
 	/* Get logical ptr for PciMem0 space */
 	/*mem = ioremap(mem_phys, msize);*/
 	mem = ioremap(mem_phys, msize);
 	if (mem == NULL) {
 		printk(MYIOC_s_ERR_FMT ": ERROR - Unable to map adapter"
 			" memory!\n", ioc->name);
 		return -EINVAL;
 	}
 	ioc->memmap = mem;
 	dinitprintk(ioc, printk(MYIOC_s_INFO_FMT "mem = %p, mem_phys = %lx\n",
 	    ioc->name, mem, mem_phys));
 	ioc->mem_phys = mem_phys;
 	ioc->chip = (SYSIF_REGS __iomem *)mem;
 	/* Save Port IO values in case we need to do downloadboot */
 	ioc->pio_mem_phys = port;
 	ioc->pio_chip = (SYSIF_REGS __iomem *)port;
 	return 0;
 }
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /**
 *	mpt_attach - Install a PCI intelligent MPT adapter.
 *	@pdev: Pointer to pci_dev structure
 *	@id: PCI device ID information
 *
 *	This routine performs all the steps necessary to bring the IOC of
 *	a MPT adapter to a OPERATIONAL state.  This includes registering
 *	memory regions, registering the interrupt, and allocating request
 *	and reply memory pools.
 *
 *	This routine also pre-fetches the LAN MAC address of a Fibre Channel
 *	MPT adapter.
 *
 *	Returns 0 for success, non-zero for failure.
 *
 *	TODO: Add support for polled controllers
 */
 int
 mpt_attach(struct pci_dev *pdev, const struct pci_device_id *id)
 {
 	MPT_ADAPTER	*ioc;
 	u8		 cb_idx;
 	int		 r = -ENODEV;
 	u8		 revision;
 	u8		 pcixcmd;
 	static int	 mpt_ids = 0;
 #ifdef CONFIG_PROC_FS
 	struct proc_dir_entry *dent, *ent;
 #endif
 	ioc = kzalloc(sizeof(MPT_ADAPTER), GFP_ATOMIC);
 	if (ioc == NULL) {
 		printk(KERN_ERR MYNAM ": ERROR - Insufficient memory to add adapter!\n");
 		return -ENOMEM;
 	}
 	ioc->id = mpt_ids++;
 	sprintf(ioc->name, "ioc%d", ioc->id);
 	dinitprintk(ioc, printk(KERN_WARNING MYNAM ": mpt_adapter_install\n"));
 	/*
 	 * set initial debug level
 	 * (refer to mptdebug.h)
 	 *
 	 */
 	ioc->debug_level = mpt_debug_level;
 	if (mpt_debug_level)
 		printk(KERN_INFO "mpt_debug_level=%xh\n", mpt_debug_level);
 	dinitprintk(ioc, printk(MYIOC_s_INFO_FMT ": mpt_adapter_install\n", ioc->name));
 	ioc->pcidev = pdev;
 	if (mpt_mapresources(ioc)) {
 		kfree(ioc);
 		return r;
 	}
 	/*
 	 * Setting up proper handlers for scatter gather handling
 	 */
 	if (ioc->dma_mask == DMA_BIT_MASK(64)) {
 		if (pdev->device == MPI_MANUFACTPAGE_DEVID_SAS1078)
 			ioc->add_sge = &mpt_add_sge_64bit_1078;
 		else
 			ioc->add_sge = &mpt_add_sge_64bit;
 		ioc->add_chain = &mpt_add_chain_64bit;
 		ioc->sg_addr_size = 8;
 	} else {
 		ioc->add_sge = &mpt_add_sge;
 		ioc->add_chain = &mpt_add_chain;
 		ioc->sg_addr_size = 4;
 	}
 	ioc->SGE_size = sizeof(u32) + ioc->sg_addr_size;
 	ioc->alloc_total = sizeof(MPT_ADAPTER);
 	ioc->req_sz = MPT_DEFAULT_FRAME_SIZE;		/* avoid div by zero! */
 	ioc->reply_sz = MPT_REPLY_FRAME_SIZE;
 	ioc->pcidev = pdev;
 	spin_lock_init(&ioc->taskmgmt_lock);
 	mutex_init(&ioc->internal_cmds.mutex);
 	init_completion(&ioc->internal_cmds.done);
 	mutex_init(&ioc->mptbase_cmds.mutex);
 	init_completion(&ioc->mptbase_cmds.done);
 	mutex_init(&ioc->taskmgmt_cmds.mutex);
 	init_completion(&ioc->taskmgmt_cmds.done);
 	/* Initialize the event logging.
 	 */
 	ioc->eventTypes = 0;	/* None */
 	ioc->eventContext = 0;
 	ioc->eventLogSize = 0;
 	ioc->events = NULL;
 #ifdef MFCNT
 	ioc->mfcnt = 0;
 #endif
 	ioc->sh = NULL;
 	ioc->cached_fw = NULL;
 	/* Initilize SCSI Config Data structure
 	 */
 	memset(&ioc->spi_data, 0, sizeof(SpiCfgData));
 	/* Initialize the fc rport list head.
 	 */
 	INIT_LIST_HEAD(&ioc->fc_rports);
 	/* Find lookup slot. */
 	INIT_LIST_HEAD(&ioc->list);
 	/* Initialize workqueue */
 	INIT_DELAYED_WORK(&ioc->fault_reset_work, mpt_fault_reset_work);
 	snprintf(ioc->reset_work_q_name, MPT_KOBJ_NAME_LEN,
 		 "mpt_poll_%d", ioc->id);
 	ioc->reset_work_q =
 		create_singlethread_workqueue(ioc->reset_work_q_name);
 	if (!ioc->reset_work_q) {
 		printk(MYIOC_s_ERR_FMT "Insufficient memory to add adapter!\n",
 		    ioc->name);
 		pci_release_selected_regions(pdev, ioc->bars);
 		kfree(ioc);
 		return -ENOMEM;
 	}
 	dinitprintk(ioc, printk(MYIOC_s_INFO_FMT "facts @ %p, pfacts[0] @ %p\n",
 	    ioc->name, &ioc->facts, &ioc->pfacts[0]));
 	pci_read_config_byte(pdev, PCI_CLASS_REVISION, &revision);
 	mpt_get_product_name(pdev->vendor, pdev->device, revision, ioc->prod_name);
 	switch (pdev->device)
 	{
 	case MPI_MANUFACTPAGE_DEVICEID_FC939X:
 	case MPI_MANUFACTPAGE_DEVICEID_FC949X:
 		ioc->errata_flag_1064 = 1;
 	case MPI_MANUFACTPAGE_DEVICEID_FC909:
 	case MPI_MANUFACTPAGE_DEVICEID_FC929:
 	case MPI_MANUFACTPAGE_DEVICEID_FC919:
 	case MPI_MANUFACTPAGE_DEVICEID_FC949E:
 		ioc->bus_type = FC;
 		break;
 	case MPI_MANUFACTPAGE_DEVICEID_FC929X:
 		if (revision < XL_929) {
 			/* 929X Chip Fix. Set Split transactions level
 		 	* for PCIX. Set MOST bits to zero.
 		 	*/
 			pci_read_config_byte(pdev, 0x6a, &pcixcmd);
 			pcixcmd &= 0x8F;
 			pci_write_config_byte(pdev, 0x6a, pcixcmd);
 		} else {
 			/* 929XL Chip Fix. Set MMRBC to 0x08.
 		 	*/
 			pci_read_config_byte(pdev, 0x6a, &pcixcmd);
 			pcixcmd |= 0x08;
 			pci_write_config_byte(pdev, 0x6a, pcixcmd);
 		}
 		ioc->bus_type = FC;
 		break;
 	case MPI_MANUFACTPAGE_DEVICEID_FC919X:
 		/* 919X Chip Fix. Set Split transactions level
 		 * for PCIX. Set MOST bits to zero.
 		 */
 		pci_read_config_byte(pdev, 0x6a, &pcixcmd);
 		pcixcmd &= 0x8F;
 		pci_write_config_byte(pdev, 0x6a, pcixcmd);
 		ioc->bus_type = FC;
 		break;
 	case MPI_MANUFACTPAGE_DEVID_53C1030:
 		/* 1030 Chip Fix. Disable Split transactions
 		 * for PCIX. Set MOST bits to zero if Rev < C0( = 8).
 		 */
 		if (revision < C0_1030) {
 			pci_read_config_byte(pdev, 0x6a, &pcixcmd);
 			pcixcmd &= 0x8F;
 			pci_write_config_byte(pdev, 0x6a, pcixcmd);
 		}
 	case MPI_MANUFACTPAGE_DEVID_1030_53C1035:
 		ioc->bus_type = SPI;
 		break;
 	case MPI_MANUFACTPAGE_DEVID_SAS1064:
 	case MPI_MANUFACTPAGE_DEVID_SAS1068:
 		ioc->errata_flag_1064 = 1;
 		ioc->bus_type = SAS;
 		break;
 	case MPI_MANUFACTPAGE_DEVID_SAS1064E:
 	case MPI_MANUFACTPAGE_DEVID_SAS1068E:
 	case MPI_MANUFACTPAGE_DEVID_SAS1078:
 		ioc->bus_type = SAS;
 		break;
 	}
 	switch (ioc->bus_type) {
 	case SAS:
 		ioc->msi_enable = mpt_msi_enable_sas;
 		break;
 	case SPI:
 		ioc->msi_enable = mpt_msi_enable_spi;
 		break;
 	case FC:
 		ioc->msi_enable = mpt_msi_enable_fc;
 		break;
 	default:
 		ioc->msi_enable = 0;
 		break;
 	}
 	if (ioc->errata_flag_1064)
 		pci_disable_io_access(pdev);
 	spin_lock_init(&ioc->FreeQlock);
 	/* Disable all! */
 	CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF);
 	ioc->active = 0;
 	CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
 	/* Set IOC ptr in the pcidev's driver data. */
 	pci_set_drvdata(ioc->pcidev, ioc);
 	/* Set lookup ptr. */
 	list_add_tail(&ioc->list, &ioc_list);
 	/* Check for "bound ports" (929, 929X, 1030, 1035) to reduce redundant resets.
 	 */
 	mpt_detect_bound_ports(ioc, pdev);
 	INIT_LIST_HEAD(&ioc->fw_event_list);
 	spin_lock_init(&ioc->fw_event_lock);
 	snprintf(ioc->fw_event_q_name, MPT_KOBJ_NAME_LEN, "mpt/%d", ioc->id);
 	ioc->fw_event_q = create_singlethread_workqueue(ioc->fw_event_q_name);
 	if ((r = mpt_do_ioc_recovery(ioc, MPT_HOSTEVENT_IOC_BRINGUP,
 	    CAN_SLEEP)) != 0){
 		printk(MYIOC_s_ERR_FMT "didn't initialize properly! (%d)\n",
 		    ioc->name, r);
 		list_del(&ioc->list);
 		if (ioc->alt_ioc)
 			ioc->alt_ioc->alt_ioc = NULL;
 		iounmap(ioc->memmap);
 		if (r != -5)
 			pci_release_selected_regions(pdev, ioc->bars);
 		destroy_workqueue(ioc->reset_work_q);
 		ioc->reset_work_q = NULL;
 		kfree(ioc);
 		pci_set_drvdata(pdev, NULL);
 		return r;
 	}
 	/* call per device driver probe entry point */
 	for(cb_idx = 0; cb_idx < MPT_MAX_PROTOCOL_DRIVERS; cb_idx++) {
 		if(MptDeviceDriverHandlers[cb_idx] &&
 		  MptDeviceDriverHandlers[cb_idx]->probe) {
 			MptDeviceDriverHandlers[cb_idx]->probe(pdev,id);
 		}
 	}
 #ifdef CONFIG_PROC_FS
 	/*
 	 *  Create "/proc/mpt/iocN" subdirectory entry for each MPT adapter.
 	 */
 	dent = proc_mkdir(ioc->name, mpt_proc_root_dir);
 	if (dent) {
 		ent = create_proc_entry("info", S_IFREG|S_IRUGO, dent);
 		if (ent) {
 			ent->read_proc = procmpt_iocinfo_read;
 			ent->data = ioc;
 		}
 		ent = create_proc_entry("summary", S_IFREG|S_IRUGO, dent);
 		if (ent) {
 			ent->read_proc = procmpt_summary_read;
 			ent->data = ioc;
 		}
 	}
 #endif
 	if (!ioc->alt_ioc)
 		queue_delayed_work(ioc->reset_work_q, &ioc->fault_reset_work,
 			msecs_to_jiffies(MPT_POLLING_INTERVAL));
 	return 0;
 }
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /**
 *	mpt_detach - Remove a PCI intelligent MPT adapter.
 *	@pdev: Pointer to pci_dev structure
 */
 void
 mpt_detach(struct pci_dev *pdev)
 {
 	MPT_ADAPTER 	*ioc = pci_get_drvdata(pdev);
 	char pname[32];
 	u8 cb_idx;
 	unsigned long flags;
 	struct workqueue_struct *wq;
 	/*
 	 * Stop polling ioc for fault condition
 	 */
 	spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
 	wq = ioc->reset_work_q;
 	ioc->reset_work_q = NULL;
 	spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
 	cancel_delayed_work(&ioc->fault_reset_work);
 	destroy_workqueue(wq);
 	spin_lock_irqsave(&ioc->fw_event_lock, flags);
 	wq = ioc->fw_event_q;
 	ioc->fw_event_q = NULL;
 	spin_unlock_irqrestore(&ioc->fw_event_lock, flags);
 	destroy_workqueue(wq);
 	sprintf(pname, MPT_PROCFS_MPTBASEDIR "/%s/summary", ioc->name);
 	remove_proc_entry(pname, NULL);
 	sprintf(pname, MPT_PROCFS_MPTBASEDIR "/%s/info", ioc->name);
 	remove_proc_entry(pname, NULL);
 	sprintf(pname, MPT_PROCFS_MPTBASEDIR "/%s", ioc->name);
 	remove_proc_entry(pname, NULL);
 	/* call per device driver remove entry point */
 	for(cb_idx = 0; cb_idx < MPT_MAX_PROTOCOL_DRIVERS; cb_idx++) {
 		if(MptDeviceDriverHandlers[cb_idx] &&
 		  MptDeviceDriverHandlers[cb_idx]->remove) {
 			MptDeviceDriverHandlers[cb_idx]->remove(pdev);
 		}
 	}
 	/* Disable interrupts! */
 	CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF);
 	ioc->active = 0;
 	synchronize_irq(pdev->irq);
 	/* Clear any lingering interrupt */
 	CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
 	CHIPREG_READ32(&ioc->chip->IntStatus);
 	mpt_adapter_dispose(ioc);
 	pci_set_drvdata(pdev, NULL);
 }
 /**************************************************************************
 * Power Management
 */
 #ifdef CONFIG_PM
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /**
 *	mpt_suspend - Fusion MPT base driver suspend routine.
 *	@pdev: Pointer to pci_dev structure
 *	@state: new state to enter
 */
 int
 mpt_suspend(struct pci_dev *pdev, pm_message_t state)
 {
 	u32 device_state;
 	MPT_ADAPTER *ioc = pci_get_drvdata(pdev);
 	device_state = pci_choose_state(pdev, state);
 	printk(MYIOC_s_INFO_FMT "pci-suspend: pdev=0x%p, slot=%s, Entering "
 	    "operating state [D%d]\n", ioc->name, pdev, pci_name(pdev),
 	    device_state);
 	/* put ioc into READY_STATE */
 	if(SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET, CAN_SLEEP)) {
 		printk(MYIOC_s_ERR_FMT
 		"pci-suspend:  IOC msg unit reset failed!\n", ioc->name);
 	}
 	/* disable interrupts */
 	CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF);
 	ioc->active = 0;
 	/* Clear any lingering interrupt */
 	CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
 	free_irq(ioc->pci_irq, ioc);
 	if (ioc->msi_enable)
 		pci_disable_msi(ioc->pcidev);
 	ioc->pci_irq = -1;
 	pci_save_state(pdev);
 	pci_disable_device(pdev);
 	pci_release_selected_regions(pdev, ioc->bars);
 	pci_set_power_state(pdev, device_state);
 	return 0;
 }
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /**
 *	mpt_resume - Fusion MPT base driver resume routine.
 *	@pdev: Pointer to pci_dev structure
 */
 int
 mpt_resume(struct pci_dev *pdev)
 {
 	MPT_ADAPTER *ioc = pci_get_drvdata(pdev);
 	u32 device_state = pdev->current_state;
 	int recovery_state;
 	int err;
 	printk(MYIOC_s_INFO_FMT "pci-resume: pdev=0x%p, slot=%s, Previous "
 	    "operating state [D%d]\n", ioc->name, pdev, pci_name(pdev),
 	    device_state);
 	pci_set_power_state(pdev, PCI_D0);
 	pci_enable_wake(pdev, PCI_D0, 0);
 	pci_restore_state(pdev);
 	ioc->pcidev = pdev;
 	err = mpt_mapresources(ioc);
 	if (err)
 		return err;
 	if (ioc->dma_mask == DMA_BIT_MASK(64)) {
 		if (pdev->device == MPI_MANUFACTPAGE_DEVID_SAS1078)
 			ioc->add_sge = &mpt_add_sge_64bit_1078;
 		else
 			ioc->add_sge = &mpt_add_sge_64bit;
 		ioc->add_chain = &mpt_add_chain_64bit;
 		ioc->sg_addr_size = 8;
 	} else {
 		ioc->add_sge = &mpt_add_sge;
 		ioc->add_chain = &mpt_add_chain;
 		ioc->sg_addr_size = 4;
 	}
 	ioc->SGE_size = sizeof(u32) + ioc->sg_addr_size;
 	printk(MYIOC_s_INFO_FMT "pci-resume: ioc-state=0x%x,doorbell=0x%x\n",
 	    ioc->name, (mpt_GetIocState(ioc, 1) >> MPI_IOC_STATE_SHIFT),
 	    CHIPREG_READ32(&ioc->chip->Doorbell));
 	/*
 	 * Errata workaround for SAS pci express:
 	 * Upon returning to the D0 state, the contents of the doorbell will be
 	 * stale data, and this will incorrectly signal to the host driver that
 	 * the firmware is ready to process mpt commands.   The workaround is
 	 * to issue a diagnostic reset.
 	 */
 	if (ioc->bus_type == SAS && (pdev->device ==
 	    MPI_MANUFACTPAGE_DEVID_SAS1068E || pdev->device ==
 	    MPI_MANUFACTPAGE_DEVID_SAS1064E)) {
 		if (KickStart(ioc, 1, CAN_SLEEP) < 0) {
 			printk(MYIOC_s_WARN_FMT "pci-resume: Cannot recover\n",
 			    ioc->name);
 			goto out;
 		}
 	}
 	/* bring ioc to operational state */
 	printk(MYIOC_s_INFO_FMT "Sending mpt_do_ioc_recovery\n", ioc->name);
 	recovery_state = mpt_do_ioc_recovery(ioc, MPT_HOSTEVENT_IOC_BRINGUP,
 						 CAN_SLEEP);
 	if (recovery_state != 0)
 		printk(MYIOC_s_WARN_FMT "pci-resume: Cannot recover, "
 		    "error:[%x]\n", ioc->name, recovery_state);
 	else
 		printk(MYIOC_s_INFO_FMT
 		    "pci-resume: success\n", ioc->name);
 out:
 	return 0;
 }
 #endif
 static int
 mpt_signal_reset(u8 index, MPT_ADAPTER *ioc, int reset_phase)
 {
 	if ((MptDriverClass[index] == MPTSPI_DRIVER &&
 	     ioc->bus_type != SPI) ||
 	    (MptDriverClass[index] == MPTFC_DRIVER &&
 	     ioc->bus_type != FC) ||
 	    (MptDriverClass[index] == MPTSAS_DRIVER &&
 	     ioc->bus_type != SAS))
 		/* make sure we only call the relevant reset handler
 		 * for the bus */
 		return 0;
 	return (MptResetHandlers[index])(ioc, reset_phase);
 }
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /**
 *	mpt_do_ioc_recovery - Initialize or recover MPT adapter.
 *	@ioc: Pointer to MPT adapter structure
 *	@reason: Event word / reason
 *	@sleepFlag: Use schedule if CAN_SLEEP else use udelay.
 *
 *	This routine performs all the steps necessary to bring the IOC
 *	to a OPERATIONAL state.
 *
 *	This routine also pre-fetches the LAN MAC address of a Fibre Channel
 *	MPT adapter.
 *
 *	Returns:
 *		 0 for success
 *		-1 if failed to get board READY
 *		-2 if READY but IOCFacts Failed
 *		-3 if READY but PrimeIOCFifos Failed
 *		-4 if READY but IOCInit Failed
 *		-5 if failed to enable_device and/or request_selected_regions
 *		-6 if failed to upload firmware
 */
 static int
 mpt_do_ioc_recovery(MPT_ADAPTER *ioc, u32 reason, int sleepFlag)
 {
 	int	 hard_reset_done = 0;
 	int	 alt_ioc_ready = 0;
 	int	 hard;
 	int	 rc=0;
 	int	 ii;
 	int	 ret = 0;
 	int	 reset_alt_ioc_active = 0;
 	int	 irq_allocated = 0;
 	u8	*a;
 	printk(MYIOC_s_INFO_FMT "Initiating %s\n", ioc->name,
 	    reason == MPT_HOSTEVENT_IOC_BRINGUP ? "bringup" : "recovery");
 	/* Disable reply interrupts (also blocks FreeQ) */
 	CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF);
 	ioc->active = 0;
 	if (ioc->alt_ioc) {
 		if (ioc->alt_ioc->active ||
 		    reason == MPT_HOSTEVENT_IOC_RECOVER) {
 			reset_alt_ioc_active = 1;
 			/* Disable alt-IOC's reply interrupts
 			 *  (and FreeQ) for a bit
 			 **/
 			CHIPREG_WRITE32(&ioc->alt_ioc->chip->IntMask,
 				0xFFFFFFFF);
 			ioc->alt_ioc->active = 0;
 		}
 	}
 	hard = 1;
 	if (reason == MPT_HOSTEVENT_IOC_BRINGUP)
 		hard = 0;
 	if ((hard_reset_done = MakeIocReady(ioc, hard, sleepFlag)) < 0) {
 		if (hard_reset_done == -4) {
 			printk(MYIOC_s_WARN_FMT "Owned by PEER..skipping!\n",
 			    ioc->name);
 			if (reset_alt_ioc_active && ioc->alt_ioc) {
 				/* (re)Enable alt-IOC! (reply interrupt, FreeQ) */
 				dprintk(ioc, printk(MYIOC_s_INFO_FMT
 				    "alt_ioc reply irq re-enabled\n", ioc->alt_ioc->name));
 				CHIPREG_WRITE32(&ioc->alt_ioc->chip->IntMask, MPI_HIM_DIM);
 				ioc->alt_ioc->active = 1;
 			}
 		} else {
 			printk(MYIOC_s_WARN_FMT
 			    "NOT READY WARNING!\n", ioc->name);
 		}
 		ret = -1;
 		goto out;
 	}
 	/* hard_reset_done = 0 if a soft reset was performed
 	 * and 1 if a hard reset was performed.
 	 */
 	if (hard_reset_done && reset_alt_ioc_active && ioc->alt_ioc) {
 		if ((rc = MakeIocReady(ioc->alt_ioc, 0, sleepFlag)) == 0)
 			alt_ioc_ready = 1;
 		else
 			printk(MYIOC_s_WARN_FMT
 			    ": alt-ioc Not ready WARNING!\n",
 			    ioc->alt_ioc->name);
 	}
 	for (ii=0; ii<5; ii++) {
 		/* Get IOC facts! Allow 5 retries */
 		if ((rc = GetIocFacts(ioc, sleepFlag, reason)) == 0)
 			break;
 	}
 	if (ii == 5) {
 		dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT
 		    "Retry IocFacts failed rc=%x\n", ioc->name, rc));
 		ret = -2;
 	} else if (reason == MPT_HOSTEVENT_IOC_BRINGUP) {
 		MptDisplayIocCapabilities(ioc);
 	}
 	if (alt_ioc_ready) {
 		if ((rc = GetIocFacts(ioc->alt_ioc, sleepFlag, reason)) != 0) {
 			dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT
 			    "Initial Alt IocFacts failed rc=%x\n",
 			    ioc->name, rc));
 			/* Retry - alt IOC was initialized once
 			 */
 			rc = GetIocFacts(ioc->alt_ioc, sleepFlag, reason);
 		}
 		if (rc) {
 			dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT
 			    "Retry Alt IocFacts failed rc=%x\n", ioc->name, rc));
 			alt_ioc_ready = 0;
 			reset_alt_ioc_active = 0;
 		} else if (reason == MPT_HOSTEVENT_IOC_BRINGUP) {
 			MptDisplayIocCapabilities(ioc->alt_ioc);
 		}
 	}
 	if ((ret == 0) && (reason == MPT_HOSTEVENT_IOC_BRINGUP) &&
 	    (ioc->facts.Flags & MPI_IOCFACTS_FLAGS_FW_DOWNLOAD_BOOT)) {
 		pci_release_selected_regions(ioc->pcidev, ioc->bars);
 		ioc->bars = pci_select_bars(ioc->pcidev, IORESOURCE_MEM |
 		    IORESOURCE_IO);
 		if (pci_enable_device(ioc->pcidev))
 			return -5;
 		if (pci_request_selected_regions(ioc->pcidev, ioc->bars,
 			"mpt"))
 			return -5;
 	}
 	/*
 	 * Device is reset now. It must have de-asserted the interrupt line
 	 * (if it was asserted) and it should be safe to register for the
 	 * interrupt now.
 	 */
 	if ((ret == 0) && (reason == MPT_HOSTEVENT_IOC_BRINGUP)) {
 		ioc->pci_irq = -1;
 		if (ioc->pcidev->irq) {
 			if (ioc->msi_enable && !pci_enable_msi(ioc->pcidev))
 				printk(MYIOC_s_INFO_FMT "PCI-MSI enabled\n",
 				    ioc->name);
 			else
 				ioc->msi_enable = 0;
 			rc = request_irq(ioc->pcidev->irq, mpt_interrupt,
 			    IRQF_SHARED, ioc->name, ioc);
 			if (rc < 0) {
 				printk(MYIOC_s_ERR_FMT "Unable to allocate "
 				    "interrupt %d!\n",
 				    ioc->name, ioc->pcidev->irq);
 				if (ioc->msi_enable)
 					pci_disable_msi(ioc->pcidev);
 				ret = -EBUSY;
 				goto out;
 			}
 			irq_allocated = 1;
 			ioc->pci_irq = ioc->pcidev->irq;
 			pci_set_master(ioc->pcidev);		/* ?? */
 			pci_set_drvdata(ioc->pcidev, ioc);
 			dinitprintk(ioc, printk(MYIOC_s_INFO_FMT
 			    "installed at interrupt %d\n", ioc->name,
 			    ioc->pcidev->irq));
 		}
 	}
 	/* Prime reply & request queues!
 	 * (mucho alloc's) Must be done prior to
 	 * init as upper addresses are needed for init.
 	 * If fails, continue with alt-ioc processing
 	 */
 	dinitprintk(ioc, printk(MYIOC_s_INFO_FMT "PrimeIocFifos\n",
 	    ioc->name));
 	if ((ret == 0) && ((rc = PrimeIocFifos(ioc)) != 0))
 		ret = -3;
 	/* May need to check/upload firmware & data here!
 	 * If fails, continue with alt-ioc processing
 	 */
 	dinitprintk(ioc, printk(MYIOC_s_INFO_FMT "SendIocInit\n",
 	    ioc->name));
 	if ((ret == 0) && ((rc = SendIocInit(ioc, sleepFlag)) != 0))
 		ret = -4;
 // NEW!
 	if (alt_ioc_ready && ((rc = PrimeIocFifos(ioc->alt_ioc)) != 0)) {
 		printk(MYIOC_s_WARN_FMT
 		    ": alt-ioc (%d) FIFO mgmt alloc WARNING!\n",
 		    ioc->alt_ioc->name, rc);
 		alt_ioc_ready = 0;
 		reset_alt_ioc_active = 0;
 	}
 	if (alt_ioc_ready) {
 		if ((rc = SendIocInit(ioc->alt_ioc, sleepFlag)) != 0) {
 			alt_ioc_ready = 0;
 			reset_alt_ioc_active = 0;
 			printk(MYIOC_s_WARN_FMT
 				": alt-ioc: (%d) init failure WARNING!\n",
 					ioc->alt_ioc->name, rc);
 		}
 	}
 	if (reason == MPT_HOSTEVENT_IOC_BRINGUP){
 		if (ioc->upload_fw) {
 			ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT
 			    "firmware upload required!\n", ioc->name));
 			/* Controller is not operational, cannot do upload
 			 */
 			if (ret == 0) {
 				rc = mpt_do_upload(ioc, sleepFlag);
 				if (rc == 0) {
 					if (ioc->alt_ioc && ioc->alt_ioc->cached_fw) {
 						/*
 						 * Maintain only one pointer to FW memory
 						 * so there will not be two attempt to
 						 * downloadboot onboard dual function
 						 * chips (mpt_adapter_disable,
 						 * mpt_diag_reset)
 						 */
 						ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT
 						    "mpt_upload:  alt_%s has cached_fw=%p \n",
 						    ioc->name, ioc->alt_ioc->name, ioc->alt_ioc->cached_fw));
 						ioc->cached_fw = NULL;
 					}
 				} else {
 					printk(MYIOC_s_WARN_FMT
 					    "firmware upload failure!\n", ioc->name);
 					ret = -6;
 				}
 			}
 		}
 	}
 	/*  Enable MPT base driver management of EventNotification
 	 *  and EventAck handling.
 	 */
 	if ((ret == 0) && (!ioc->facts.EventState)) {
 		dinitprintk(ioc, printk(MYIOC_s_INFO_FMT
 			"SendEventNotification\n",
 		    ioc->name));
 		ret = SendEventNotification(ioc, 1, sleepFlag);	/* 1=Enable */
 	}
 	if (ioc->alt_ioc && alt_ioc_ready && !ioc->alt_ioc->facts.EventState)
 		rc = SendEventNotification(ioc->alt_ioc, 1, sleepFlag);
 	if (ret == 0) {
 		/* Enable! (reply interrupt) */
 		CHIPREG_WRITE32(&ioc->chip->IntMask, MPI_HIM_DIM);
 		ioc->active = 1;
 	}
 	if (rc == 0) {	/* alt ioc */
 		if (reset_alt_ioc_active && ioc->alt_ioc) {
 			/* (re)Enable alt-IOC! (reply interrupt) */
 			dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "alt-ioc"
 				"reply irq re-enabled\n",
 				ioc->alt_ioc->name));
 			CHIPREG_WRITE32(&ioc->alt_ioc->chip->IntMask,
 				MPI_HIM_DIM);
 			ioc->alt_ioc->active = 1;
 		}
 	}
 	/*	Add additional "reason" check before call to GetLanConfigPages
 	 *	(combined with GetIoUnitPage2 call).  This prevents a somewhat
 	 *	recursive scenario; GetLanConfigPages times out, timer expired
 	 *	routine calls HardResetHandler, which calls into here again,
 	 *	and we try GetLanConfigPages again...
 	 */
 	if ((ret == 0) && (reason == MPT_HOSTEVENT_IOC_BRINGUP)) {
 		/*
 		 * Initalize link list for inactive raid volumes.
 		 */
 		mutex_init(&ioc->raid_data.inactive_list_mutex);
 		INIT_LIST_HEAD(&ioc->raid_data.inactive_list);
 		switch (ioc->bus_type) {
 		case SAS:
 			/* clear persistency table */
 			if(ioc->facts.IOCExceptions &
 			    MPI_IOCFACTS_EXCEPT_PERSISTENT_TABLE_FULL) {
 				ret = mptbase_sas_persist_operation(ioc,
 				    MPI_SAS_OP_CLEAR_NOT_PRESENT);
 				if(ret != 0)
 					goto out;
 			}
 			/* Find IM volumes
 			 */
 			mpt_findImVolumes(ioc);
 			/* Check, and possibly reset, the coalescing value
 			 */
 			mpt_read_ioc_pg_1(ioc);
 			break;
 		case FC:
 			if ((ioc->pfacts[0].ProtocolFlags &
 				MPI_PORTFACTS_PROTOCOL_LAN) &&
 			    (ioc->lan_cnfg_page0.Header.PageLength == 0)) {
 				/*
 				 *  Pre-fetch the ports LAN MAC address!
 				 *  (LANPage1_t stuff)
 				 */
 				(void) GetLanConfigPages(ioc);
 				a = (u8*)&ioc->lan_cnfg_page1.HardwareAddressLow;
 				dprintk(ioc, printk(MYIOC_s_DEBUG_FMT
 					"LanAddr = %02X:%02X:%02X"
 					":%02X:%02X:%02X\n",
 					ioc->name, a[5], a[4],
 					a[3], a[2], a[1], a[0]));
 			}
 			break;
 		case SPI:
 			/* Get NVRAM and adapter maximums from SPP 0 and 2
 			 */
 			mpt_GetScsiPortSettings(ioc, 0);
 			/* Get version and length of SDP 1
 			 */
 			mpt_readScsiDevicePageHeaders(ioc, 0);
 			/* Find IM volumes
 			 */
 			if (ioc->facts.MsgVersion >= MPI_VERSION_01_02)
 				mpt_findImVolumes(ioc);
 			/* Check, and possibly reset, the coalescing value
 			 */
 			mpt_read_ioc_pg_1(ioc);
 			mpt_read_ioc_pg_4(ioc);
 			break;
 		}
 		GetIoUnitPage2(ioc);
 		mpt_get_manufacturing_pg_0(ioc);
 	}
 out:
 	if ((ret != 0) && irq_allocated) {
 		free_irq(ioc->pci_irq, ioc);
 		if (ioc->msi_enable)
 			pci_disable_msi(ioc->pcidev);
 	}
 	return ret;
 }
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /**
 *	mpt_detect_bound_ports - Search for matching PCI bus/dev_function
 *	@ioc: Pointer to MPT adapter structure
 *	@pdev: Pointer to (struct pci_dev) structure
 *
 *	Search for PCI bus/dev_function which matches
 *	PCI bus/dev_function (+/-1) for newly discovered 929,
 *	929X, 1030 or 1035.
 *
 *	If match on PCI dev_function +/-1 is found, bind the two MPT adapters
 *	using alt_ioc pointer fields in their %MPT_ADAPTER structures.
 */
 static void
 mpt_detect_bound_ports(MPT_ADAPTER *ioc, struct pci_dev *pdev)
 {
 	struct pci_dev *peer=NULL;
 	unsigned int slot = PCI_SLOT(pdev->devfn);
 	unsigned int func = PCI_FUNC(pdev->devfn);
 	MPT_ADAPTER *ioc_srch;
 	dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "PCI device %s devfn=%x/%x,"
 	    " searching for devfn match on %x or %x\n",
 	    ioc->name, pci_name(pdev), pdev->bus->number,
 	    pdev->devfn, func-1, func+1));
 	peer = pci_get_slot(pdev->bus, PCI_DEVFN(slot,func-1));
 	if (!peer) {
 		peer = pci_get_slot(pdev->bus, PCI_DEVFN(slot,func+1));
 		if (!peer)
 			return;
 	}
 	list_for_each_entry(ioc_srch, &ioc_list, list) {
 		struct pci_dev *_pcidev = ioc_srch->pcidev;
 		if (_pcidev == peer) {
 			/* Paranoia checks */
 			if (ioc->alt_ioc != NULL) {
 				printk(MYIOC_s_WARN_FMT
 				    "Oops, already bound (%s <==> %s)!\n",
 				    ioc->name, ioc->name, ioc->alt_ioc->name);
 				break;
 			} else if (ioc_srch->alt_ioc != NULL) {
 				printk(MYIOC_s_WARN_FMT
 				    "Oops, already bound (%s <==> %s)!\n",
 				    ioc_srch->name, ioc_srch->name,
 				    ioc_srch->alt_ioc->name);
 				break;
 			}
 			dprintk(ioc, printk(MYIOC_s_DEBUG_FMT
 				"FOUND! binding %s <==> %s\n",
 				ioc->name, ioc->name, ioc_srch->name));
 			ioc_srch->alt_ioc = ioc;
 			ioc->alt_ioc = ioc_srch;
 		}
 	}
 	pci_dev_put(peer);
 }
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /**
 *	mpt_adapter_disable - Disable misbehaving MPT adapter.
 *	@ioc: Pointer to MPT adapter structure
 */
 static void
 mpt_adapter_disable(MPT_ADAPTER *ioc)
 {
 	int sz;
 	int ret;
 	if (ioc->cached_fw != NULL) {
 		ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT
 			"%s: Pushing FW onto adapter\n", __func__, ioc->name));
 		if ((ret = mpt_downloadboot(ioc, (MpiFwHeader_t *)
 		    ioc->cached_fw, CAN_SLEEP)) < 0) {
 			printk(MYIOC_s_WARN_FMT
 			    ": firmware downloadboot failure (%d)!\n",
 			    ioc->name, ret);
 		}
 	}
 	/*
 	 * Put the controller into ready state (if its not already)
 	 */
 	if (mpt_GetIocState(ioc, 1) != MPI_IOC_STATE_READY) {
 		if (!SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET,
 		    CAN_SLEEP)) {
 			if (mpt_GetIocState(ioc, 1) != MPI_IOC_STATE_READY)
 				printk(MYIOC_s_ERR_FMT "%s:  IOC msg unit "
 				    "reset failed to put ioc in ready state!\n",
 				    ioc->name, __func__);
 		} else
 			printk(MYIOC_s_ERR_FMT "%s:  IOC msg unit reset "
 			    "failed!\n", ioc->name, __func__);
 	}
 	/* Disable adapter interrupts! */
 	synchronize_irq(ioc->pcidev->irq);
 	CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF);
 	ioc->active = 0;
 	/* Clear any lingering interrupt */
 	CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
 	CHIPREG_READ32(&ioc->chip->IntStatus);
 	if (ioc->alloc != NULL) {
 		sz = ioc->alloc_sz;
 		dexitprintk(ioc, printk(MYIOC_s_INFO_FMT "free  @ %p, sz=%d bytes\n",
 		    ioc->name, ioc->alloc, ioc->alloc_sz));
 		pci_free_consistent(ioc->pcidev, sz,
 				ioc->alloc, ioc->alloc_dma);
 		ioc->reply_frames = NULL;
 		ioc->req_frames = NULL;
 		ioc->alloc = NULL;
 		ioc->alloc_total -= sz;
 	}
 	if (ioc->sense_buf_pool != NULL) {
 		sz = (ioc->req_depth * MPT_SENSE_BUFFER_ALLOC);
 		pci_free_consistent(ioc->pcidev, sz,
 				ioc->sense_buf_pool, ioc->sense_buf_pool_dma);
 		ioc->sense_buf_pool = NULL;
 		ioc->alloc_total -= sz;
 	}
 	if (ioc->events != NULL){
 		sz = MPTCTL_EVENT_LOG_SIZE * sizeof(MPT_IOCTL_EVENTS);
 		kfree(ioc->events);
 		ioc->events = NULL;
 		ioc->alloc_total -= sz;
 	}
 	mpt_free_fw_memory(ioc);
 	kfree(ioc->spi_data.nvram);
 	mpt_inactive_raid_list_free(ioc);
 	kfree(ioc->raid_data.pIocPg2);
 	kfree(ioc->raid_data.pIocPg3);
 	ioc->spi_data.nvram = NULL;
 	ioc->raid_data.pIocPg3 = NULL;
 	if (ioc->spi_data.pIocPg4 != NULL) {
 		sz = ioc->spi_data.IocPg4Sz;
 		pci_free_consistent(ioc->pcidev, sz,
 			ioc->spi_data.pIocPg4,
 			ioc->spi_data.IocPg4_dma);
 		ioc->spi_data.pIocPg4 = NULL;
 		ioc->alloc_total -= sz;
 	}
 	if (ioc->ReqToChain != NULL) {
 		kfree(ioc->ReqToChain);
 		kfree(ioc->RequestNB);
 		ioc->ReqToChain = NULL;
 	}
 	kfree(ioc->ChainToChain);
 	ioc->ChainToChain = NULL;
 	if (ioc->HostPageBuffer != NULL) {
 		if((ret = mpt_host_page_access_control(ioc,
 		    MPI_DB_HPBAC_FREE_BUFFER, NO_SLEEP)) != 0) {
 			printk(MYIOC_s_ERR_FMT
 			   ": %s: host page buffers free failed (%d)!\n",
 			    ioc->name, __func__, ret);
 		}
 		dexitprintk(ioc, printk(MYIOC_s_DEBUG_FMT
 			"HostPageBuffer free  @ %p, sz=%d bytes\n",
 			ioc->name, ioc->HostPageBuffer,
 			ioc->HostPageBuffer_sz));
 		pci_free_consistent(ioc->pcidev, ioc->HostPageBuffer_sz,
 		    ioc->HostPageBuffer, ioc->HostPageBuffer_dma);
 		ioc->HostPageBuffer = NULL;
 		ioc->HostPageBuffer_sz = 0;
 		ioc->alloc_total -= ioc->HostPageBuffer_sz;
 	}
 	pci_set_drvdata(ioc->pcidev, NULL);
 }
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /**
 *	mpt_adapter_dispose - Free all resources associated with an MPT adapter
 *	@ioc: Pointer to MPT adapter structure
 *
 *	This routine unregisters h/w resources and frees all alloc'd memory
 *	associated with a MPT adapter structure.
 */
 static void
 mpt_adapter_dispose(MPT_ADAPTER *ioc)
 {
 	int sz_first, sz_last;
 	if (ioc == NULL)
 		return;
 	sz_first = ioc->alloc_total;
 	mpt_adapter_disable(ioc);
 	if (ioc->pci_irq != -1) {
 		free_irq(ioc->pci_irq, ioc);
 		if (ioc->msi_enable)
 			pci_disable_msi(ioc->pcidev);
 		ioc->pci_irq = -1;
 	}
 	if (ioc->memmap != NULL) {
 		iounmap(ioc->memmap);
 		ioc->memmap = NULL;
 	}
 	pci_disable_device(ioc->pcidev);
 	pci_release_selected_regions(ioc->pcidev, ioc->bars);
 #if defined(CONFIG_MTRR) && 0
 	if (ioc->mtrr_reg > 0) {
 		mtrr_del(ioc->mtrr_reg, 0, 0);
 		dprintk(ioc, printk(MYIOC_s_INFO_FMT "MTRR region de-registered\n", ioc->name));
 	}
 #endif
 	/*  Zap the adapter lookup ptr!  */
 	list_del(&ioc->list);
 	sz_last = ioc->alloc_total;
 	dprintk(ioc, printk(MYIOC_s_INFO_FMT "free'd %d of %d bytes\n",
 	    ioc->name, sz_first-sz_last+(int)sizeof(*ioc), sz_first));
 	if (ioc->alt_ioc)
 		ioc->alt_ioc->alt_ioc = NULL;
 	kfree(ioc);
 }
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /**
 *	MptDisplayIocCapabilities - Disply IOC's capabilities.
 *	@ioc: Pointer to MPT adapter structure
 */
 static void
 MptDisplayIocCapabilities(MPT_ADAPTER *ioc)
 {
 	int i = 0;
 	printk(KERN_INFO "%s: ", ioc->name);
 	if (ioc->prod_name)
 		printk("%s: ", ioc->prod_name);
 	printk("Capabilities={");
 	if (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_INITIATOR) {
 		printk("Initiator");
 		i++;
 	}
 	if (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_TARGET) {
 		printk("%sTarget", i ? "," : "");
 		i++;
 	}
 	if (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_LAN) {
 		printk("%sLAN", i ? "," : "");
 		i++;
 	}
 #if 0
 	/*
 	 *  This would probably evoke more questions than it's worth
 	 */
 	if (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_TARGET) {
 		printk("%sLogBusAddr", i ? "," : "");
 		i++;
 	}
 #endif
 	printk("}\n");
 }
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /**
 *	MakeIocReady - Get IOC to a READY state, using KickStart if needed.
 *	@ioc: Pointer to MPT_ADAPTER structure
 *	@force: Force hard KickStart of IOC
 *	@sleepFlag: Specifies whether the process can sleep
 *
 *	Returns:
 *		 1 - DIAG reset and READY
 *		 0 - READY initially OR soft reset and READY
 *		-1 - Any failure on KickStart
 *		-2 - Msg Unit Reset Failed
 *		-3 - IO Unit Reset Failed
 *		-4 - IOC owned by a PEER
 */
 static int
 MakeIocReady(MPT_ADAPTER *ioc, int force, int sleepFlag)
 {
 	u32	 ioc_state;
 	int	 statefault = 0;
 	int	 cntdn;
 	int	 hard_reset_done = 0;
 	int	 r;
 	int	 ii;
 	int	 whoinit;
 	/* Get current [raw] IOC state  */
 	ioc_state = mpt_GetIocState(ioc, 0);
 	dhsprintk(ioc, printk(MYIOC_s_INFO_FMT "MakeIocReady [raw] state=%08x\n", ioc->name, ioc_state));
 	/*
 	 *	Check to see if IOC got left/stuck in doorbell handshake
 	 *	grip of death.  If so, hard reset the IOC.
 	 */
 	if (ioc_state & MPI_DOORBELL_ACTIVE) {
 		statefault = 1;
 		printk(MYIOC_s_WARN_FMT "Unexpected doorbell active!\n",
 				ioc->name);
 	}
 	/* Is it already READY? */
 	if (!statefault &&
 	    ((ioc_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_READY)) {
 		dinitprintk(ioc, printk(MYIOC_s_INFO_FMT
 		    "IOC is in READY state\n", ioc->name));
 		return 0;
 	}
 	/*
 	 *	Check to see if IOC is in FAULT state.
 	 */
 	if ((ioc_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_FAULT) {
 		statefault = 2;
 		printk(MYIOC_s_WARN_FMT "IOC is in FAULT state!!!\n",
 		    ioc->name);
 		printk(MYIOC_s_WARN_FMT "           FAULT code = %04xh\n",
 		    ioc->name, ioc_state & MPI_DOORBELL_DATA_MASK);
 	}
 	/*
 	 *	Hmmm...  Did it get left operational?
 	 */
 	if ((ioc_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_OPERATIONAL) {
 		dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "IOC operational unexpected\n",
 				ioc->name));
 		/* Check WhoInit.
 		 * If PCI Peer, exit.
 		 * Else, if no fault conditions are present, issue a MessageUnitReset
 		 * Else, fall through to KickStart case
 		 */
 		whoinit = (ioc_state & MPI_DOORBELL_WHO_INIT_MASK) >> MPI_DOORBELL_WHO_INIT_SHIFT;
 		dinitprintk(ioc, printk(MYIOC_s_INFO_FMT
 			"whoinit 0x%x statefault %d force %d\n",
 			ioc->name, whoinit, statefault, force));
 		if (whoinit == MPI_WHOINIT_PCI_PEER)
 			return -4;
 		else {
 			if ((statefault == 0 ) && (force == 0)) {
 				if ((r = SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET, sleepFlag)) == 0)
 					return 0;
 			}
 			statefault = 3;
 		}
 	}
 	hard_reset_done = KickStart(ioc, statefault||force, sleepFlag);
 	if (hard_reset_done < 0)
 		return -1;
 	/*
 	 *  Loop here waiting for IOC to come READY.
 	 */
 	ii = 0;
 	cntdn = ((sleepFlag == CAN_SLEEP) ? HZ : 1000) * 5;	/* 5 seconds */
 	while ((ioc_state = mpt_GetIocState(ioc, 1)) != MPI_IOC_STATE_READY) {
 		if (ioc_state == MPI_IOC_STATE_OPERATIONAL) {
 			/*
 			 *  BIOS or previous driver load left IOC in OP state.
 			 *  Reset messaging FIFOs.
 			 */
 			if ((r = SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET, sleepFlag)) != 0) {
 				printk(MYIOC_s_ERR_FMT "IOC msg unit reset failed!\n", ioc->name);
 				return -2;
 			}
 		} else if (ioc_state == MPI_IOC_STATE_RESET) {
 			/*
 			 *  Something is wrong.  Try to get IOC back
 			 *  to a known state.
 			 */
 			if ((r = SendIocReset(ioc, MPI_FUNCTION_IO_UNIT_RESET, sleepFlag)) != 0) {
 				printk(MYIOC_s_ERR_FMT "IO unit reset failed!\n", ioc->name);
 				return -3;
 			}
 		}
 		ii++; cntdn--;
 		if (!cntdn) {
 			printk(MYIOC_s_ERR_FMT
 				"Wait IOC_READY state (0x%x) timeout(%d)!\n",
 				ioc->name, ioc_state, (int)((ii+5)/HZ));
 			return -ETIME;
 		}
 		if (sleepFlag == CAN_SLEEP) {
 			msleep(1);
 		} else {
 			mdelay (1);	/* 1 msec delay */
 		}
 	}
 	if (statefault < 3) {
 		printk(MYIOC_s_INFO_FMT "Recovered from %s\n", ioc->name,
 			statefault == 1 ? "stuck handshake" : "IOC FAULT");
 	}
 	return hard_reset_done;
 }
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /**
 *	mpt_GetIocState - Get the current state of a MPT adapter.
 *	@ioc: Pointer to MPT_ADAPTER structure
 *	@cooked: Request raw or cooked IOC state
 *
 *	Returns all IOC Doorbell register bits if cooked==0, else just the
 *	Doorbell bits in MPI_IOC_STATE_MASK.
 */
 u32
 mpt_GetIocState(MPT_ADAPTER *ioc, int cooked)
 {
 	u32 s, sc;
 	/*  Get!  */
 	s = CHIPREG_READ32(&ioc->chip->Doorbell);
 	sc = s & MPI_IOC_STATE_MASK;
 	/*  Save!  */
 	ioc->last_state = sc;
 	return cooked ? sc : s;
 }
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /**
 *	GetIocFacts - Send IOCFacts request to MPT adapter.
 *	@ioc: Pointer to MPT_ADAPTER structure
 *	@sleepFlag: Specifies whether the process can sleep
 *	@reason: If recovery, only update facts.
 *
 *	Returns 0 for success, non-zero for failure.
 */
 static int
 GetIocFacts(MPT_ADAPTER *ioc, int sleepFlag, int reason)
 {
 	IOCFacts_t		 get_facts;
 	IOCFactsReply_t		*facts;
 	int			 r;
 	int			 req_sz;
 	int			 reply_sz;
 	int			 sz;
 	u32			 status, vv;
 	u8			 shiftFactor=1;
 	/* IOC *must* NOT be in RESET state! */
 	if (ioc->last_state == MPI_IOC_STATE_RESET) {
 		printk(KERN_ERR MYNAM
 		    ": ERROR - Can't get IOCFacts, %s NOT READY! (%08x)\n",
 		    ioc->name, ioc->last_state);
 		return -44;
 	}
 	facts = &ioc->facts;
 	/* Destination (reply area)... */
 	reply_sz = sizeof(*facts);
 	memset(facts, 0, reply_sz);
 	/* Request area (get_facts on the stack right now!) */
 	req_sz = sizeof(get_facts);
 	memset(&get_facts, 0, req_sz);
 	get_facts.Function = MPI_FUNCTION_IOC_FACTS;
 	/* Assert: All other get_facts fields are zero! */
 	dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT
 	    "Sending get IocFacts request req_sz=%d reply_sz=%d\n",
 	    ioc->name, req_sz, reply_sz));
 	/* No non-zero fields in the get_facts request are greater than
 	 * 1 byte in size, so we can just fire it off as is.
 	 */
 	r = mpt_handshake_req_reply_wait(ioc, req_sz, (u32*)&get_facts,
 			reply_sz, (u16*)facts, 5 /*seconds*/, sleepFlag);
 	if (r != 0)
 		return r;
 	/*
 	 * Now byte swap (GRRR) the necessary fields before any further
 	 * inspection of reply contents.
 	 *
 	 * But need to do some sanity checks on MsgLength (byte) field
 	 * to make sure we don't zero IOC's req_sz!
 	 */
 	/* Did we get a valid reply? */
 	if (facts->MsgLength > offsetof(IOCFactsReply_t, RequestFrameSize)/sizeof(u32)) {
 		if (reason == MPT_HOSTEVENT_IOC_BRINGUP) {
 			/*
 			 * If not been here, done that, save off first WhoInit value
 			 */
 			if (ioc->FirstWhoInit == WHOINIT_UNKNOWN)
 				ioc->FirstWhoInit = facts->WhoInit;
 		}
 		facts->MsgVersion = le16_to_cpu(facts->MsgVersion);
 		facts->MsgContext = le32_to_cpu(facts->MsgContext);
 		facts->IOCExceptions = le16_to_cpu(facts->IOCExceptions);
 		facts->IOCStatus = le16_to_cpu(facts->IOCStatus);
 		facts->IOCLogInfo = le32_to_cpu(facts->IOCLogInfo);
 		status = le16_to_cpu(facts->IOCStatus) & MPI_IOCSTATUS_MASK;
 		/* CHECKME! IOCStatus, IOCLogInfo */
 		facts->ReplyQueueDepth = le16_to_cpu(facts->ReplyQueueDepth);
 		facts->RequestFrameSize = le16_to_cpu(facts->RequestFrameSize);
 		/*
 		 * FC f/w version changed between 1.1 and 1.2
 		 *	Old: u16{Major(4),Minor(4),SubMinor(8)}
 		 *	New: u32{Major(8),Minor(8),Unit(8),Dev(8)}
 		 */
 		if (facts->MsgVersion < MPI_VERSION_01_02) {
 			/*
 			 *	Handle old FC f/w style, convert to new...
 			 */
 			u16	 oldv = le16_to_cpu(facts->Reserved_0101_FWVersion);
 			facts->FWVersion.Word =
 					((oldv<<12) & 0xFF000000) |
 					((oldv<<8)  & 0x000FFF00);
 		} else
 			facts->FWVersion.Word = le32_to_cpu(facts->FWVersion.Word);
 		facts->ProductID = le16_to_cpu(facts->ProductID);
 		if ((ioc->facts.ProductID & MPI_FW_HEADER_PID_PROD_MASK)
 		    > MPI_FW_HEADER_PID_PROD_TARGET_SCSI)
 			ioc->ir_firmware = 1;
 		facts->CurrentHostMfaHighAddr =
 				le32_to_cpu(facts->CurrentHostMfaHighAddr);
 		facts->GlobalCredits = le16_to_cpu(facts->GlobalCredits);
 		facts->CurrentSenseBufferHighAddr =
 				le32_to_cpu(facts->CurrentSenseBufferHighAddr);
 		facts->CurReplyFrameSize =
 				le16_to_cpu(facts->CurReplyFrameSize);
 		facts->IOCCapabilities = le32_to_cpu(facts->IOCCapabilities);
 		/*
 		 * Handle NEW (!) IOCFactsReply fields in MPI-1.01.xx
 		 * Older MPI-1.00.xx struct had 13 dwords, and enlarged
 		 * to 14 in MPI-1.01.0x.
 		 */
 		if (facts->MsgLength >= (offsetof(IOCFactsReply_t,FWImageSize) + 7)/4 &&
 		    facts->MsgVersion > MPI_VERSION_01_00) {
 			facts->FWImageSize = le32_to_cpu(facts->FWImageSize);
 		}
 		sz = facts->FWImageSize;
 		if ( sz & 0x01 )
 			sz += 1;
 		if ( sz & 0x02 )
 			sz += 2;
 		facts->FWImageSize = sz;
 		if (!facts->RequestFrameSize) {
 			/*  Something is wrong!  */
 			printk(MYIOC_s_ERR_FMT "IOC reported invalid 0 request size!\n",
 					ioc->name);
 			return -55;
 		}
 		r = sz = facts->BlockSize;
 		vv = ((63 / (sz * 4)) + 1) & 0x03;
 		ioc->NB_for_64_byte_frame = vv;
 		while ( sz )
 		{
 			shiftFactor++;
 			sz = sz >> 1;
 		}
 		ioc->NBShiftFactor  = shiftFactor;
 		dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT
 		    "NB_for_64_byte_frame=%x NBShiftFactor=%x BlockSize=%x\n",
 		    ioc->name, vv, shiftFactor, r));
 		if (reason == MPT_HOSTEVENT_IOC_BRINGUP) {
 			/*
 			 * Set values for this IOC's request & reply frame sizes,
 			 * and request & reply queue depths...
 			 */
 			ioc->req_sz = min(MPT_DEFAULT_FRAME_SIZE, facts->RequestFrameSize * 4);
 			ioc->req_depth = min_t(int, MPT_MAX_REQ_DEPTH, facts->GlobalCredits);
 			ioc->reply_sz = MPT_REPLY_FRAME_SIZE;
 			ioc->reply_depth = min_t(int, MPT_DEFAULT_REPLY_DEPTH, facts->ReplyQueueDepth);
 			dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "reply_sz=%3d, reply_depth=%4d\n",
 				ioc->name, ioc->reply_sz, ioc->reply_depth));
 			dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "req_sz  =%3d, req_depth  =%4d\n",
 				ioc->name, ioc->req_sz, ioc->req_depth));
 			/* Get port facts! */
 			if ( (r = GetPortFacts(ioc, 0, sleepFlag)) != 0 )
 				return r;
 		}
 	} else {
 		printk(MYIOC_s_ERR_FMT
 		     "Invalid IOC facts reply, msgLength=%d offsetof=%zd!\n",
 		     ioc->name, facts->MsgLength, (offsetof(IOCFactsReply_t,
 		     RequestFrameSize)/sizeof(u32)));
 		return -66;
 	}
 	return 0;
 }
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /**
 *	GetPortFacts - Send PortFacts request to MPT adapter.
 *	@ioc: Pointer to MPT_ADAPTER structure
 *	@portnum: Port number
 *	@sleepFlag: Specifies whether the process can sleep
 *
 *	Returns 0 for success, non-zero for failure.
 */
 static int
 GetPortFacts(MPT_ADAPTER *ioc, int portnum, int sleepFlag)
 {
 	PortFacts_t		 get_pfacts;
 	PortFactsReply_t	*pfacts;
 	int			 ii;
 	int			 req_sz;
 	int			 reply_sz;
 	int			 max_id;
 	/* IOC *must* NOT be in RESET state! */
 	if (ioc->last_state == MPI_IOC_STATE_RESET) {
 		printk(MYIOC_s_ERR_FMT "Can't get PortFacts NOT READY! (%08x)\n",
 		    ioc->name, ioc->last_state );
 		return -4;
 	}
 	pfacts = &ioc->pfacts[portnum];
 	/* Destination (reply area)...  */
 	reply_sz = sizeof(*pfacts);
 	memset(pfacts, 0, reply_sz);
 	/* Request area (get_pfacts on the stack right now!) */
 	req_sz = sizeof(get_pfacts);
 	memset(&get_pfacts, 0, req_sz);
 	get_pfacts.Function = MPI_FUNCTION_PORT_FACTS;
 	get_pfacts.PortNumber = portnum;
 	/* Assert: All other get_pfacts fields are zero! */
 	dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending get PortFacts(%d) request\n",
 			ioc->name, portnum));
 	/* No non-zero fields in the get_pfacts request are greater than
 	 * 1 byte in size, so we can just fire it off as is.
 	 */
 	ii = mpt_handshake_req_reply_wait(ioc, req_sz, (u32*)&get_pfacts,
 				reply_sz, (u16*)pfacts, 5 /*seconds*/, sleepFlag);
 	if (ii != 0)
 		return ii;
 	/* Did we get a valid reply? */
 	/* Now byte swap the necessary fields in the response. */
 	pfacts->MsgContext = le32_to_cpu(pfacts->MsgContext);
 	pfacts->IOCStatus = le16_to_cpu(pfacts->IOCStatus);
 	pfacts->IOCLogInfo = le32_to_cpu(pfacts->IOCLogInfo);
 	pfacts->MaxDevices = le16_to_cpu(pfacts->MaxDevices);
 	pfacts->PortSCSIID = le16_to_cpu(pfacts->PortSCSIID);
 	pfacts->ProtocolFlags = le16_to_cpu(pfacts->ProtocolFlags);
 	pfacts->MaxPostedCmdBuffers = le16_to_cpu(pfacts->MaxPostedCmdBuffers);
 	pfacts->MaxPersistentIDs = le16_to_cpu(pfacts->MaxPersistentIDs);
 	pfacts->MaxLanBuckets = le16_to_cpu(pfacts->MaxLanBuckets);
 	max_id = (ioc->bus_type == SAS) ? pfacts->PortSCSIID :
 	    pfacts->MaxDevices;
 	ioc->devices_per_bus = (max_id > 255) ? 256 : max_id;
 	ioc->number_of_buses = (ioc->devices_per_bus < 256) ? 1 : max_id/256;
 	/*
 	 * Place all the devices on channels
 	 *
 	 * (for debuging)
 	 */
 	if (mpt_channel_mapping) {
 		ioc->devices_per_bus = 1;
 		ioc->number_of_buses = (max_id > 255) ? 255 : max_id;
 	}
 	return 0;
 }
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /**
 *	SendIocInit - Send IOCInit request to MPT adapter.
 *	@ioc: Pointer to MPT_ADAPTER structure
 *	@sleepFlag: Specifies whether the process can sleep
 *
 *	Send IOCInit followed by PortEnable to bring IOC to OPERATIONAL state.
 *
 *	Returns 0 for success, non-zero for failure.
 */
 static int
 SendIocInit(MPT_ADAPTER *ioc, int sleepFlag)
 {
 	IOCInit_t		 ioc_init;
 	MPIDefaultReply_t	 init_reply;
 	u32			 state;
 	int			 r;
 	int			 count;
 	int			 cntdn;
 	memset(&ioc_init, 0, sizeof(ioc_init));
 	memset(&init_reply, 0, sizeof(init_reply));
 	ioc_init.WhoInit = MPI_WHOINIT_HOST_DRIVER;
 	ioc_init.Function = MPI_FUNCTION_IOC_INIT;
 	/* If we are in a recovery mode and we uploaded the FW image,
 	 * then this pointer is not NULL. Skip the upload a second time.
 	 * Set this flag if cached_fw set for either IOC.
 	 */
 	if (ioc->facts.Flags & MPI_IOCFACTS_FLAGS_FW_DOWNLOAD_BOOT)
 		ioc->upload_fw = 1;
 	else
 		ioc->upload_fw = 0;
 	ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "upload_fw %d facts.Flags=%x\n",
 		   ioc->name, ioc->upload_fw, ioc->facts.Flags));
 	ioc_init.MaxDevices = (U8)ioc->devices_per_bus;
 	ioc_init.MaxBuses = (U8)ioc->number_of_buses;
 	dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "facts.MsgVersion=%x\n",
 		   ioc->name, ioc->facts.MsgVersion));
 	if (ioc->facts.MsgVersion >= MPI_VERSION_01_05) {
 		// set MsgVersion and HeaderVersion host driver was built with
 		ioc_init.MsgVersion = cpu_to_le16(MPI_VERSION);
 	        ioc_init.HeaderVersion = cpu_to_le16(MPI_HEADER_VERSION);
 		if (ioc->facts.Flags & MPI_IOCFACTS_FLAGS_HOST_PAGE_BUFFER_PERSISTENT) {
 			ioc_init.HostPageBufferSGE = ioc->facts.HostPageBufferSGE;
 		} else if(mpt_host_page_alloc(ioc, &ioc_init))
 			return -99;
 	}
 	ioc_init.ReplyFrameSize = cpu_to_le16(ioc->reply_sz);	/* in BYTES */
 	if (ioc->sg_addr_size == sizeof(u64)) {
 		/* Save the upper 32-bits of the request
 		 * (reply) and sense buffers.
 		 */
 		ioc_init.HostMfaHighAddr = cpu_to_le32((u32)((u64)ioc->alloc_dma >> 32));
 		ioc_init.SenseBufferHighAddr = cpu_to_le32((u32)((u64)ioc->sense_buf_pool_dma >> 32));
 	} else {
 		/* Force 32-bit addressing */
 		ioc_init.HostMfaHighAddr = cpu_to_le32(0);
 		ioc_init.SenseBufferHighAddr = cpu_to_le32(0);
 	}
 	ioc->facts.CurrentHostMfaHighAddr = ioc_init.HostMfaHighAddr;
 	ioc->facts.CurrentSenseBufferHighAddr = ioc_init.SenseBufferHighAddr;
 	ioc->facts.MaxDevices = ioc_init.MaxDevices;
 	ioc->facts.MaxBuses = ioc_init.MaxBuses;
 	dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending IOCInit (req @ %p)\n",
 			ioc->name, &ioc_init));
 	r = mpt_handshake_req_reply_wait(ioc, sizeof(IOCInit_t), (u32*)&ioc_init,
 				sizeof(MPIDefaultReply_t), (u16*)&init_reply, 10 /*seconds*/, sleepFlag);
 	if (r != 0) {
 		printk(MYIOC_s_ERR_FMT "Sending IOCInit failed(%d)!\n",ioc->name, r);
 		return r;
 	}
 	/* No need to byte swap the multibyte fields in the reply
 	 * since we don't even look at its contents.
 	 */
 	dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending PortEnable (req @ %p)\n",
 			ioc->name, &ioc_init));
 	if ((r = SendPortEnable(ioc, 0, sleepFlag)) != 0) {
 		printk(MYIOC_s_ERR_FMT "Sending PortEnable failed(%d)!\n",ioc->name, r);
 		return r;
 	}
 	/* YIKES!  SUPER IMPORTANT!!!
 	 *  Poll IocState until _OPERATIONAL while IOC is doing
 	 *  LoopInit and TargetDiscovery!
 	 */
 	count = 0;
 	cntdn = ((sleepFlag == CAN_SLEEP) ? HZ : 1000) * 60;	/* 60 seconds */
 	state = mpt_GetIocState(ioc, 1);
 	while (state != MPI_IOC_STATE_OPERATIONAL && --cntdn) {
 		if (sleepFlag == CAN_SLEEP) {
 			msleep(1);
 		} else {
 			mdelay(1);
 		}
 		if (!cntdn) {
 			printk(MYIOC_s_ERR_FMT "Wait IOC_OP state timeout(%d)!\n",
 					ioc->name, (int)((count+5)/HZ));
 			return -9;
 		}
 		state = mpt_GetIocState(ioc, 1);
 		count++;
 	}
 	dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Wait IOC_OPERATIONAL state (cnt=%d)\n",
 			ioc->name, count));
 	ioc->aen_event_read_flag=0;
 	return r;
 }
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /**
 *	SendPortEnable - Send PortEnable request to MPT adapter port.
 *	@ioc: Pointer to MPT_ADAPTER structure
 *	@portnum: Port number to enable
 *	@sleepFlag: Specifies whether the process can sleep
 *
 *	Send PortEnable to bring IOC to OPERATIONAL state.
 *
 *	Returns 0 for success, non-zero for failure.
 */
 static int
 SendPortEnable(MPT_ADAPTER *ioc, int portnum, int sleepFlag)
 {
 	PortEnable_t		 port_enable;
 	MPIDefaultReply_t	 reply_buf;
 	int	 rc;
 	int	 req_sz;
 	int	 reply_sz;
 	/*  Destination...  */
 	reply_sz = sizeof(MPIDefaultReply_t);
 	memset(&reply_buf, 0, reply_sz);
 	req_sz = sizeof(PortEnable_t);
 	memset(&port_enable, 0, req_sz);
 	port_enable.Function = MPI_FUNCTION_PORT_ENABLE;
 	port_enable.PortNumber = portnum;
 /*	port_enable.ChainOffset = 0;		*/
 /*	port_enable.MsgFlags = 0;		*/
 /*	port_enable.MsgContext = 0;		*/
 	dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending Port(%d)Enable (req @ %p)\n",
 			ioc->name, portnum, &port_enable));
 	/* RAID FW may take a long time to enable
 	 */
 	if (ioc->ir_firmware || ioc->bus_type == SAS) {
 		rc = mpt_handshake_req_reply_wait(ioc, req_sz,
 		(u32*)&port_enable, reply_sz, (u16*)&reply_buf,
 		300 /*seconds*/, sleepFlag);
 	} else {
 		rc = mpt_handshake_req_reply_wait(ioc, req_sz,
 		(u32*)&port_enable, reply_sz, (u16*)&reply_buf,
 		30 /*seconds*/, sleepFlag);
 	}
 	return rc;
 }
 /**
 *	mpt_alloc_fw_memory - allocate firmware memory
 *	@ioc: Pointer to MPT_ADAPTER structure
 *      @size: total FW bytes
 *
 *	If memory has already been allocated, the same (cached) value
 *	is returned.
 *
 *	Return 0 if successfull, or non-zero for failure
 **/
 int
 mpt_alloc_fw_memory(MPT_ADAPTER *ioc, int size)
 {
 	int rc;
 	if (ioc->cached_fw) {
 		rc = 0;  /* use already allocated memory */
 		goto out;
 	}
 	else if (ioc->alt_ioc && ioc->alt_ioc->cached_fw) {
 		ioc->cached_fw = ioc->alt_ioc->cached_fw;  /* use alt_ioc's memory */
 		ioc->cached_fw_dma = ioc->alt_ioc->cached_fw_dma;
 		rc = 0;
 		goto out;
 	}
 	ioc->cached_fw = pci_alloc_consistent(ioc->pcidev, size, &ioc->cached_fw_dma);
 	if (!ioc->cached_fw) {
 		printk(MYIOC_s_ERR_FMT "Unable to allocate memory for the cached firmware image!\n",
 		    ioc->name);
 		rc = -1;
 	} else {
 		dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "FW Image  @ %p[%p], sz=%d[%x] bytes\n",
 		    ioc->name, ioc->cached_fw, (void *)(ulong)ioc->cached_fw_dma, size, size));
 		ioc->alloc_total += size;
 		rc = 0;
 	}
 out:
 	return rc;
 }
 /**
 *	mpt_free_fw_memory - free firmware memory
 *	@ioc: Pointer to MPT_ADAPTER structure
 *
 *	If alt_img is NULL, delete from ioc structure.
 *	Else, delete a secondary image in same format.
 **/
 void
 mpt_free_fw_memory(MPT_ADAPTER *ioc)
 {
 	int sz;
 	if (!ioc->cached_fw)
 		return;
 	sz = ioc->facts.FWImageSize;
 	dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "free_fw_memory: FW Image  @ %p[%p], sz=%d[%x] bytes\n",
 		 ioc->name, ioc->cached_fw, (void *)(ulong)ioc->cached_fw_dma, sz, sz));
 	pci_free_consistent(ioc->pcidev, sz, ioc->cached_fw, ioc->cached_fw_dma);
 	ioc->alloc_total -= sz;
 	ioc->cached_fw = NULL;
 }
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /**
 *	mpt_do_upload - Construct and Send FWUpload request to MPT adapter port.
 *	@ioc: Pointer to MPT_ADAPTER structure
 *	@sleepFlag: Specifies whether the process can sleep
 *
 *	Returns 0 for success, >0 for handshake failure
 *		<0 for fw upload failure.
 *
 *	Remark: If bound IOC and a successful FWUpload was performed
 *	on the bound IOC, the second image is discarded
 *	and memory is free'd. Both channels must upload to prevent
 *	IOC from running in degraded mode.
 */
 static int
 mpt_do_upload(MPT_ADAPTER *ioc, int sleepFlag)
 {
 	u8			 reply[sizeof(FWUploadReply_t)];
 	FWUpload_t		*prequest;
 	FWUploadReply_t		*preply;
 	FWUploadTCSGE_t		*ptcsge;
 	u32			 flagsLength;
 	int			 ii, sz, reply_sz;
 	int			 cmdStatus;
 	int			request_size;
 	/* If the image size is 0, we are done.
 	 */
 	if ((sz = ioc->facts.FWImageSize) == 0)
 		return 0;
 	if (mpt_alloc_fw_memory(ioc, ioc->facts.FWImageSize) != 0)
 		return -ENOMEM;
 	dinitprintk(ioc, printk(MYIOC_s_INFO_FMT ": FW Image  @ %p[%p], sz=%d[%x] bytes\n",
 	    ioc->name, ioc->cached_fw, (void *)(ulong)ioc->cached_fw_dma, sz, sz));
 	prequest = (sleepFlag == NO_SLEEP) ? kzalloc(ioc->req_sz, GFP_ATOMIC) :
 	    kzalloc(ioc->req_sz, GFP_KERNEL);
 	if (!prequest) {
 		dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "fw upload failed "
 		    "while allocating memory \n", ioc->name));
 		mpt_free_fw_memory(ioc);
 		return -ENOMEM;
 	}
 	preply = (FWUploadReply_t *)&reply;
 	reply_sz = sizeof(reply);
 	memset(preply, 0, reply_sz);
 	prequest->ImageType = MPI_FW_UPLOAD_ITYPE_FW_IOC_MEM;
 	prequest->Function = MPI_FUNCTION_FW_UPLOAD;
 	ptcsge = (FWUploadTCSGE_t *) &prequest->SGL;
 	ptcsge->DetailsLength = 12;
 	ptcsge->Flags = MPI_SGE_FLAGS_TRANSACTION_ELEMENT;
 	ptcsge->ImageSize = cpu_to_le32(sz);
 	ptcsge++;
 	flagsLength = MPT_SGE_FLAGS_SSIMPLE_READ | sz;
 	ioc->add_sge((char *)ptcsge, flagsLength, ioc->cached_fw_dma);
 	request_size = offsetof(FWUpload_t, SGL) + sizeof(FWUploadTCSGE_t) +
 	    ioc->SGE_size;
 	dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending FW Upload "
 	    " (req @ %p) fw_size=%d mf_request_size=%d\n", ioc->name, prequest,
 	    ioc->facts.FWImageSize, request_size));
 	DBG_DUMP_FW_REQUEST_FRAME(ioc, (u32 *)prequest);
 	ii = mpt_handshake_req_reply_wait(ioc, request_size, (u32 *)prequest,
 	    reply_sz, (u16 *)preply, 65 /*seconds*/, sleepFlag);
 	dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "FW Upload completed "
 	    "rc=%x \n", ioc->name, ii));
 	cmdStatus = -EFAULT;
 	if (ii == 0) {
 		/* Handshake transfer was complete and successful.
 		 * Check the Reply Frame.
 		 */
 		int status;
 		status = le16_to_cpu(preply->IOCStatus) &
 				MPI_IOCSTATUS_MASK;
 		if (status == MPI_IOCSTATUS_SUCCESS &&
 		    ioc->facts.FWImageSize ==
 		    le32_to_cpu(preply->ActualImageSize))
 				cmdStatus = 0;
 	}
 	dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT ": do_upload cmdStatus=%d \n",
 			ioc->name, cmdStatus));
 	if (cmdStatus) {
 		ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "fw upload failed, "
 		    "freeing image \n", ioc->name));
 		mpt_free_fw_memory(ioc);
 	}
 	kfree(prequest);
 	return cmdStatus;
 }
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /**
 *	mpt_downloadboot - DownloadBoot code
 *	@ioc: Pointer to MPT_ADAPTER structure
 *	@pFwHeader: Pointer to firmware header info
 *	@sleepFlag: Specifies whether the process can sleep
 *
 *	FwDownloadBoot requires Programmed IO access.
 *
 *	Returns 0 for success
 *		-1 FW Image size is 0
 *		-2 No valid cached_fw Pointer
 *		<0 for fw upload failure.
 */
 static int
 mpt_downloadboot(MPT_ADAPTER *ioc, MpiFwHeader_t *pFwHeader, int sleepFlag)
 {
 	MpiExtImageHeader_t	*pExtImage;
 	u32			 fwSize;
 	u32			 diag0val;
 	int			 count;
 	u32			*ptrFw;
 	u32			 diagRwData;
 	u32			 nextImage;
 	u32			 load_addr;
 	u32 			 ioc_state=0;
 	ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "downloadboot: fw size 0x%x (%d), FW Ptr %p\n",
 				ioc->name, pFwHeader->ImageSize, pFwHeader->ImageSize, pFwHeader));
 	CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF);
 	CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_1ST_KEY_VALUE);
 	CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_2ND_KEY_VALUE);
 	CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_3RD_KEY_VALUE);
 	CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_4TH_KEY_VALUE);
 	CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_5TH_KEY_VALUE);
 	CHIPREG_WRITE32(&ioc->chip->Diagnostic, (MPI_DIAG_PREVENT_IOC_BOOT | MPI_DIAG_DISABLE_ARM));
 	/* wait 1 msec */
 	if (sleepFlag == CAN_SLEEP) {
 		msleep(1);
 	} else {
 		mdelay (1);
 	}
 	diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
 	CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val | MPI_DIAG_RESET_ADAPTER);
 	for (count = 0; count < 30; count ++) {
 		diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
 		if (!(diag0val & MPI_DIAG_RESET_ADAPTER)) {
 			ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "RESET_ADAPTER cleared, count=%d\n",
 				ioc->name, count));
 			break;
 		}
 		/* wait .1 sec */
 		if (sleepFlag == CAN_SLEEP) {
 			msleep (100);
 		} else {
 			mdelay (100);
 		}
 	}
 	if ( count == 30 ) {
 		ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "downloadboot failed! "
 		"Unable to get MPI_DIAG_DRWE mode, diag0val=%x\n",
 		ioc->name, diag0val));
 		return -3;
 	}
 	CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF);
 	CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_1ST_KEY_VALUE);
 	CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_2ND_KEY_VALUE);
 	CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_3RD_KEY_VALUE);
 	CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_4TH_KEY_VALUE);
 	CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_5TH_KEY_VALUE);
 	/* Set the DiagRwEn and Disable ARM bits */
 	CHIPREG_WRITE32(&ioc->chip->Diagnostic, (MPI_DIAG_RW_ENABLE | MPI_DIAG_DISABLE_ARM));
 	fwSize = (pFwHeader->ImageSize + 3)/4;
 	ptrFw = (u32 *) pFwHeader;
 	/* Write the LoadStartAddress to the DiagRw Address Register
 	 * using Programmed IO
 	 */
 	if (ioc->errata_flag_1064)
 		pci_enable_io_access(ioc->pcidev);
 	CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, pFwHeader->LoadStartAddress);
 	ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "LoadStart addr written 0x%x \n",
 		ioc->name, pFwHeader->LoadStartAddress));
 	ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Write FW Image: 0x%x bytes @ %p\n",
 				ioc->name, fwSize*4, ptrFw));
 	while (fwSize--) {
 		CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwData, *ptrFw++);
 	}
 	nextImage = pFwHeader->NextImageHeaderOffset;
 	while (nextImage) {
 		pExtImage = (MpiExtImageHeader_t *) ((char *)pFwHeader + nextImage);
 		load_addr = pExtImage->LoadStartAddress;
 		fwSize = (pExtImage->ImageSize + 3) >> 2;
 		ptrFw = (u32 *)pExtImage;
 		ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Write Ext Image: 0x%x (%d) bytes @ %p load_addr=%x\n",
 						ioc->name, fwSize*4, fwSize*4, ptrFw, load_addr));
 		CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, load_addr);
 		while (fwSize--) {
 			CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwData, *ptrFw++);
 		}
 		nextImage = pExtImage->NextImageHeaderOffset;
 	}
 	/* Write the IopResetVectorRegAddr */
 	ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Write IopResetVector Addr=%x! \n", ioc->name, 	pFwHeader->IopResetRegAddr));
 	CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, pFwHeader->IopResetRegAddr);
 	/* Write the IopResetVectorValue */
 	ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Write IopResetVector Value=%x! \n", ioc->name, pFwHeader->IopResetVectorValue));
 	CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwData, pFwHeader->IopResetVectorValue);
 	/* Clear the internal flash bad bit - autoincrementing register,
 	 * so must do two writes.
 	 */
 	if (ioc->bus_type == SPI) {
 		/*
 		 * 1030 and 1035 H/W errata, workaround to access
 		 * the ClearFlashBadSignatureBit
 		 */
 		CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, 0x3F000000);
 		diagRwData = CHIPREG_PIO_READ32(&ioc->pio_chip->DiagRwData);
 		diagRwData |= 0x40000000;
 		CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, 0x3F000000);
 		CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwData, diagRwData);
 	} else /* if((ioc->bus_type == SAS) || (ioc->bus_type == FC)) */ {
 		diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
 		CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val |
 		    MPI_DIAG_CLEAR_FLASH_BAD_SIG);
 		/* wait 1 msec */
 		if (sleepFlag == CAN_SLEEP) {
 			msleep (1);
 		} else {
 			mdelay (1);
 		}
 	}
 	if (ioc->errata_flag_1064)
 		pci_disable_io_access(ioc->pcidev);
 	diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
 	ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "downloadboot diag0val=%x, "
 		"turning off PREVENT_IOC_BOOT, DISABLE_ARM, RW_ENABLE\n",
 		ioc->name, diag0val));
 	diag0val &= ~(MPI_DIAG_PREVENT_IOC_BOOT | MPI_DIAG_DISABLE_ARM | MPI_DIAG_RW_ENABLE);
 	ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "downloadboot now diag0val=%x\n",
 		ioc->name, diag0val));
 	CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val);
 	/* Write 0xFF to reset the sequencer */
 	CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF);
 	if (ioc->bus_type == SAS) {
 		ioc_state = mpt_GetIocState(ioc, 0);
 		if ( (GetIocFacts(ioc, sleepFlag,
 				MPT_HOSTEVENT_IOC_BRINGUP)) != 0 ) {
 			ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "GetIocFacts failed: IocState=%x\n",
 					ioc->name, ioc_state));
 			return -EFAULT;
 		}
 	}
 	for (count=0; count<HZ*20; count++) {
 		if ((ioc_state = mpt_GetIocState(ioc, 0)) & MPI_IOC_STATE_READY) {
 			ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT
 				"downloadboot successful! (count=%d) IocState=%x\n",
 				ioc->name, count, ioc_state));
 			if (ioc->bus_type == SAS) {
 				return 0;
 			}
 			if ((SendIocInit(ioc, sleepFlag)) != 0) {
 				ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT
 					"downloadboot: SendIocInit failed\n",
 					ioc->name));
 				return -EFAULT;
 			}
 			ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT
 					"downloadboot: SendIocInit successful\n",
 					ioc->name));
 			return 0;
 		}
 		if (sleepFlag == CAN_SLEEP) {
 			msleep (10);
 		} else {
 			mdelay (10);
 		}
 	}
 	ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT
 		"downloadboot failed! IocState=%x\n",ioc->name, ioc_state));
 	return -EFAULT;
 }
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /**
 *	KickStart - Perform hard reset of MPT adapter.
 *	@ioc: Pointer to MPT_ADAPTER structure
 *	@force: Force hard reset
 *	@sleepFlag: Specifies whether the process can sleep
 *
 *	This routine places MPT adapter in diagnostic mode via the
 *	WriteSequence register, and then performs a hard reset of adapter
 *	via the Diagnostic register.
 *
 *	Inputs:   sleepflag - CAN_SLEEP (non-interrupt thread)
 *			or NO_SLEEP (interrupt thread, use mdelay)
 *		  force - 1 if doorbell active, board fault state
 *				board operational, IOC_RECOVERY or
 *				IOC_BRINGUP and there is an alt_ioc.
 *			  0 else
 *
 *	Returns:
 *		 1 - hard reset, READY
 *		 0 - no reset due to History bit, READY
 *		-1 - no reset due to History bit but not READY
 *		     OR reset but failed to come READY
 *		-2 - no reset, could not enter DIAG mode
 *		-3 - reset but bad FW bit
 */
 static int
 KickStart(MPT_ADAPTER *ioc, int force, int sleepFlag)
 {
 	int hard_reset_done = 0;
 	u32 ioc_state=0;
 	int cnt,cntdn;
 	dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "KickStarting!\n", ioc->name));
 	if (ioc->bus_type == SPI) {
 		/* Always issue a Msg Unit Reset first. This will clear some
 		 * SCSI bus hang conditions.
 		 */
 		SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET, sleepFlag);
 		if (sleepFlag == CAN_SLEEP) {
 			msleep (1000);
 		} else {
 			mdelay (1000);
 		}
 	}
 	hard_reset_done = mpt_diag_reset(ioc, force, sleepFlag);
 	if (hard_reset_done < 0)
 		return hard_reset_done;
 	dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Diagnostic reset successful!\n",
 		ioc->name));
 	cntdn = ((sleepFlag == CAN_SLEEP) ? HZ : 1000) * 2;	/* 2 seconds */
 	for (cnt=0; cnt<cntdn; cnt++) {
 		ioc_state = mpt_GetIocState(ioc, 1);
 		if ((ioc_state == MPI_IOC_STATE_READY) || (ioc_state == MPI_IOC_STATE_OPERATIONAL)) {
 			dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "KickStart successful! (cnt=%d)\n",
 					ioc->name, cnt));
 			return hard_reset_done;
 		}
 		if (sleepFlag == CAN_SLEEP) {
 			msleep (10);
 		} else {
 			mdelay (10);
 		}
 	}
 	dinitprintk(ioc, printk(MYIOC_s_ERR_FMT "Failed to come READY after reset! IocState=%x\n",
 		ioc->name, mpt_GetIocState(ioc, 0)));
 	return -1;
 }
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /**
 *	mpt_diag_reset - Perform hard reset of the adapter.
 *	@ioc: Pointer to MPT_ADAPTER structure
 *	@ignore: Set if to honor and clear to ignore
 *		the reset history bit
 *	@sleepFlag: CAN_SLEEP if called in a non-interrupt thread,
 *		else set to NO_SLEEP (use mdelay instead)
 *
 *	This routine places the adapter in diagnostic mode via the
 *	WriteSequence register and then performs a hard reset of adapter
 *	via the Diagnostic register. Adapter should be in ready state
 *	upon successful completion.
 *
 *	Returns:  1  hard reset successful
 *		  0  no reset performed because reset history bit set
 *		 -2  enabling diagnostic mode failed
 *		 -3  diagnostic reset failed
 */
 static int
 mpt_diag_reset(MPT_ADAPTER *ioc, int ignore, int sleepFlag)
 {
 	u32 diag0val;
 	u32 doorbell;
 	int hard_reset_done = 0;
 	int count = 0;
 	u32 diag1val = 0;
 	MpiFwHeader_t *cached_fw;	/* Pointer to FW */
 	u8	 cb_idx;
 	/* Clear any existing interrupts */
 	CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
 	if (ioc->pcidev->device == MPI_MANUFACTPAGE_DEVID_SAS1078) {
 		if (!ignore)
 			return 0;
 		drsprintk(ioc, printk(MYIOC_s_WARN_FMT "%s: Doorbell=%p; 1078 reset "
 			"address=%p\n",  ioc->name, __func__,
 			&ioc->chip->Doorbell, &ioc->chip->Reset_1078));
 		CHIPREG_WRITE32(&ioc->chip->Reset_1078, 0x07);
 		if (sleepFlag == CAN_SLEEP)
 			msleep(1);
 		else
 			mdelay(1);
 		/*
 		 * Call each currently registered protocol IOC reset handler
 		 * with pre-reset indication.
 		 * NOTE: If we're doing _IOC_BRINGUP, there can be no
 		 * MptResetHandlers[] registered yet.
 		 */
 		for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
 			if (MptResetHandlers[cb_idx])
 				(*(MptResetHandlers[cb_idx]))(ioc,
 						MPT_IOC_PRE_RESET);
 		}
 		for (count = 0; count < 60; count ++) {
 			doorbell = CHIPREG_READ32(&ioc->chip->Doorbell);
 			doorbell &= MPI_IOC_STATE_MASK;
 			drsprintk(ioc, printk(MYIOC_s_DEBUG_FMT
 				"looking for READY STATE: doorbell=%x"
 			        " count=%d\n",
 				ioc->name, doorbell, count));
 			if (doorbell == MPI_IOC_STATE_READY) {
 				return 1;
 			}
 			/* wait 1 sec */
 			if (sleepFlag == CAN_SLEEP)
 				msleep(1000);
 			else
 				mdelay(1000);
 		}
 		return -1;
 	}
 	/* Use "Diagnostic reset" method! (only thing available!) */
 	diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
 	if (ioc->debug_level & MPT_DEBUG) {
 		if (ioc->alt_ioc)
 			diag1val = CHIPREG_READ32(&ioc->alt_ioc->chip->Diagnostic);
 		dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "DbG1: diag0=%08x, diag1=%08x\n",
 			ioc->name, diag0val, diag1val));
 	}
 	/* Do the reset if we are told to ignore the reset history
 	 * or if the reset history is 0
 	 */
 	if (ignore || !(diag0val & MPI_DIAG_RESET_HISTORY)) {
 		while ((diag0val & MPI_DIAG_DRWE) == 0) {
 			/* Write magic sequence to WriteSequence register
 			 * Loop until in diagnostic mode
 			 */
 			CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF);
 			CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_1ST_KEY_VALUE);
 			CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_2ND_KEY_VALUE);
 			CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_3RD_KEY_VALUE);
 			CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_4TH_KEY_VALUE);
 			CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_5TH_KEY_VALUE);
 			/* wait 100 msec */
 			if (sleepFlag == CAN_SLEEP) {
 				msleep (100);
 			} else {
 				mdelay (100);
 			}
 			count++;
 			if (count > 20) {
 				printk(MYIOC_s_ERR_FMT "Enable Diagnostic mode FAILED! (%02xh)\n",
 						ioc->name, diag0val);
 				return -2;
 			}
 			diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
 			dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Wrote magic DiagWriteEn sequence (%x)\n",
 					ioc->name, diag0val));
 		}
 		if (ioc->debug_level & MPT_DEBUG) {
 			if (ioc->alt_ioc)
 				diag1val = CHIPREG_READ32(&ioc->alt_ioc->chip->Diagnostic);
 			dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "DbG2: diag0=%08x, diag1=%08x\n",
 				ioc->name, diag0val, diag1val));
 		}
 		/*
 		 * Disable the ARM (Bug fix)
 		 *
 		 */
 		CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val | MPI_DIAG_DISABLE_ARM);
 		mdelay(1);
 		/*
 		 * Now hit the reset bit in the Diagnostic register
 		 * (THE BIG HAMMER!) (Clears DRWE bit).
 		 */
 		CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val | MPI_DIAG_RESET_ADAPTER);
 		hard_reset_done = 1;
 		dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Diagnostic reset performed\n",
 				ioc->name));
 		/*
 		 * Call each currently registered protocol IOC reset handler
 		 * with pre-reset indication.
 		 * NOTE: If we're doing _IOC_BRINGUP, there can be no
 		 * MptResetHandlers[] registered yet.
 		 */
 		for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
 			if (MptResetHandlers[cb_idx]) {
 				mpt_signal_reset(cb_idx,
 					ioc, MPT_IOC_PRE_RESET);
 				if (ioc->alt_ioc) {
 					mpt_signal_reset(cb_idx,
 					ioc->alt_ioc, MPT_IOC_PRE_RESET);
 				}
 			}
 		}
 		if (ioc->cached_fw)
 			cached_fw = (MpiFwHeader_t *)ioc->cached_fw;
 		else if (ioc->alt_ioc && ioc->alt_ioc->cached_fw)
 			cached_fw = (MpiFwHeader_t *)ioc->alt_ioc->cached_fw;
 		else
 			cached_fw = NULL;
 		if (cached_fw) {
 			/* If the DownloadBoot operation fails, the
 			 * IOC will be left unusable. This is a fatal error
 			 * case.  _diag_reset will return < 0
 			 */
 			for (count = 0; count < 30; count ++) {
 				diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
 				if (!(diag0val & MPI_DIAG_RESET_ADAPTER)) {
 					break;
 				}
 				dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "cached_fw: diag0val=%x count=%d\n",
 					ioc->name, diag0val, count));
 				/* wait 1 sec */
 				if (sleepFlag == CAN_SLEEP) {
 					msleep (1000);
 				} else {
 					mdelay (1000);
 				}
 			}
 			if ((count = mpt_downloadboot(ioc, cached_fw, sleepFlag)) < 0) {
 				printk(MYIOC_s_WARN_FMT
 					"firmware downloadboot failure (%d)!\n", ioc->name, count);
 			}
 		} else {
 			/* Wait for FW to reload and for board
 			 * to go to the READY state.
 			 * Maximum wait is 60 seconds.
 			 * If fail, no error will check again
 			 * with calling program.
 			 */
 			for (count = 0; count < 60; count ++) {
 				doorbell = CHIPREG_READ32(&ioc->chip->Doorbell);
 				doorbell &= MPI_IOC_STATE_MASK;
 				drsprintk(ioc, printk(MYIOC_s_DEBUG_FMT
 				    "looking for READY STATE: doorbell=%x"
 				    " count=%d\n", ioc->name, doorbell, count));
 				if (doorbell == MPI_IOC_STATE_READY) {
 					break;
 				}
 				/* wait 1 sec */
 				if (sleepFlag == CAN_SLEEP) {
 					msleep (1000);
 				} else {
 					mdelay (1000);
 				}
 			}
 			if (doorbell != MPI_IOC_STATE_READY)
 				printk(MYIOC_s_ERR_FMT "Failed to come READY "
 				    "after reset! IocState=%x", ioc->name,
 				    doorbell);
 		}
 	}
 	diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
 	if (ioc->debug_level & MPT_DEBUG) {
 		if (ioc->alt_ioc)
 			diag1val = CHIPREG_READ32(&ioc->alt_ioc->chip->Diagnostic);
 		dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "DbG3: diag0=%08x, diag1=%08x\n",
 			ioc->name, diag0val, diag1val));
 	}
 	/* Clear RESET_HISTORY bit!  Place board in the
 	 * diagnostic mode to update the diag register.
 	 */
 	diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
 	count = 0;
 	while ((diag0val & MPI_DIAG_DRWE) == 0) {
 		/* Write magic sequence to WriteSequence register
 		 * Loop until in diagnostic mode
 		 */
 		CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF);
 		CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_1ST_KEY_VALUE);
 		CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_2ND_KEY_VALUE);
 		CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_3RD_KEY_VALUE);
 		CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_4TH_KEY_VALUE);
 		CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_5TH_KEY_VALUE);
 		/* wait 100 msec */
 		if (sleepFlag == CAN_SLEEP) {
 			msleep (100);
 		} else {
 			mdelay (100);
 		}
 		count++;
 		if (count > 20) {
 			printk(MYIOC_s_ERR_FMT "Enable Diagnostic mode FAILED! (%02xh)\n",
 					ioc->name, diag0val);
 			break;
 		}
 		diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
 	}
 	diag0val &= ~MPI_DIAG_RESET_HISTORY;
 	CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val);
 	diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
 	if (diag0val & MPI_DIAG_RESET_HISTORY) {
 		printk(MYIOC_s_WARN_FMT "ResetHistory bit failed to clear!\n",
 				ioc->name);
 	}
 	/* Disable Diagnostic Mode
 	 */
 	CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFFFFFFFF);
 	/* Check FW reload status flags.
 	 */
 	diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
 	if (diag0val & (MPI_DIAG_FLASH_BAD_SIG | MPI_DIAG_RESET_ADAPTER | MPI_DIAG_DISABLE_ARM)) {
 		printk(MYIOC_s_ERR_FMT "Diagnostic reset FAILED! (%02xh)\n",
 				ioc->name, diag0val);
 		return -3;
 	}
 	if (ioc->debug_level & MPT_DEBUG) {
 		if (ioc->alt_ioc)
 			diag1val = CHIPREG_READ32(&ioc->alt_ioc->chip->Diagnostic);
 		dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "DbG4: diag0=%08x, diag1=%08x\n",
 			ioc->name, diag0val, diag1val));
 	}
 	/*
 	 * Reset flag that says we've enabled event notification
 	 */
 	ioc->facts.EventState = 0;
 	if (ioc->alt_ioc)
 		ioc->alt_ioc->facts.EventState = 0;
 	return hard_reset_done;
 }
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /**
 *	SendIocReset - Send IOCReset request to MPT adapter.
 *	@ioc: Pointer to MPT_ADAPTER structure
 *	@reset_type: reset type, expected values are
 *	%MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET or %MPI_FUNCTION_IO_UNIT_RESET
 *	@sleepFlag: Specifies whether the process can sleep
 *
 *	Send IOCReset request to the MPT adapter.
 *
 *	Returns 0 for success, non-zero for failure.
 */
 static int
 SendIocReset(MPT_ADAPTER *ioc, u8 reset_type, int sleepFlag)
 {
 	int r;
 	u32 state;
 	int cntdn, count;
 	drsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending IOC reset(0x%02x)!\n",
 			ioc->name, reset_type));
 	CHIPREG_WRITE32(&ioc->chip->Doorbell, reset_type<<MPI_DOORBELL_FUNCTION_SHIFT);
 	if ((r = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0)
 		return r;
 	/* FW ACK'd request, wait for READY state
 	 */
 	count = 0;
 	cntdn = ((sleepFlag == CAN_SLEEP) ? HZ : 1000) * 15;	/* 15 seconds */
 	while ((state = mpt_GetIocState(ioc, 1)) != MPI_IOC_STATE_READY) {
 		cntdn--;
 		count++;
 		if (!cntdn) {
 			if (sleepFlag != CAN_SLEEP)
 				count *= 10;
 			printk(MYIOC_s_ERR_FMT
 			    "Wait IOC_READY state (0x%x) timeout(%d)!\n",
 			    ioc->name, state, (int)((count+5)/HZ));
 			return -ETIME;
 		}
 		if (sleepFlag == CAN_SLEEP) {
 			msleep(1);
 		} else {
 			mdelay (1);	/* 1 msec delay */
 		}
 	}
 	/* TODO!
 	 *  Cleanup all event stuff for this IOC; re-issue EventNotification
 	 *  request if needed.
 	 */
 	if (ioc->facts.Function)
 		ioc->facts.EventState = 0;
 	return 0;
 }
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /**
 *	initChainBuffers - Allocate memory for and initialize chain buffers
 *	@ioc: Pointer to MPT_ADAPTER structure
 *
 *	Allocates memory for and initializes chain buffers,
 *	chain buffer control arrays and spinlock.
 */
 static int
 initChainBuffers(MPT_ADAPTER *ioc)
 {
 	u8		*mem;
 	int		sz, ii, num_chain;
 	int 		scale, num_sge, numSGE;
 	/* ReqToChain size must equal the req_depth
 	 * index = req_idx
 	 */
 	if (ioc->ReqToChain == NULL) {
 		sz = ioc->req_depth * sizeof(int);
 		mem = kmalloc(sz, GFP_ATOMIC);
 		if (mem == NULL)
 			return -1;
 		ioc->ReqToChain = (int *) mem;
 		dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ReqToChain alloc  @ %p, sz=%d bytes\n",
 			 	ioc->name, mem, sz));
 		mem = kmalloc(sz, GFP_ATOMIC);
 		if (mem == NULL)
 			return -1;
 		ioc->RequestNB = (int *) mem;
 		dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "RequestNB alloc  @ %p, sz=%d bytes\n",
 			 	ioc->name, mem, sz));
 	}
 	for (ii = 0; ii < ioc->req_depth; ii++) {
 		ioc->ReqToChain[ii] = MPT_HOST_NO_CHAIN;
 	}
 	/* ChainToChain size must equal the total number
 	 * of chain buffers to be allocated.
 	 * index = chain_idx
 	 *
 	 * Calculate the number of chain buffers needed(plus 1) per I/O
 	 * then multiply the maximum number of simultaneous cmds
 	 *
 	 * num_sge = num sge in request frame + last chain buffer
 	 * scale = num sge per chain buffer if no chain element
 	 */
 	scale = ioc->req_sz / ioc->SGE_size;
 	if (ioc->sg_addr_size == sizeof(u64))
 		num_sge =  scale + (ioc->req_sz - 60) / ioc->SGE_size;
 	else
 		num_sge =  1 + scale + (ioc->req_sz - 64) / ioc->SGE_size;
 	if (ioc->sg_addr_size == sizeof(u64)) {
 		numSGE = (scale - 1) * (ioc->facts.MaxChainDepth-1) + scale +
 			(ioc->req_sz - 60) / ioc->SGE_size;
 	} else {
 		numSGE = 1 + (scale - 1) * (ioc->facts.MaxChainDepth-1) +
 		    scale + (ioc->req_sz - 64) / ioc->SGE_size;
 	}
 	dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "num_sge=%d numSGE=%d\n",
 		ioc->name, num_sge, numSGE));
 	if (ioc->bus_type == FC) {
 		if (numSGE > MPT_SCSI_FC_SG_DEPTH)
 			numSGE = MPT_SCSI_FC_SG_DEPTH;
 	} else {
 		if (numSGE > MPT_SCSI_SG_DEPTH)
 			numSGE = MPT_SCSI_SG_DEPTH;
 	}
 	num_chain = 1;
 	while (numSGE - num_sge > 0) {
 		num_chain++;
 		num_sge += (scale - 1);
 	}
 	num_chain++;
 	dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Now numSGE=%d num_sge=%d num_chain=%d\n",
 		ioc->name, numSGE, num_sge, num_chain));
 	if (ioc->bus_type == SPI)
 		num_chain *= MPT_SCSI_CAN_QUEUE;
 	else
 		num_chain *= MPT_FC_CAN_QUEUE;
 	ioc->num_chain = num_chain;
 	sz = num_chain * sizeof(int);
 	if (ioc->ChainToChain == NULL) {
 		mem = kmalloc(sz, GFP_ATOMIC);
 		if (mem == NULL)
 			return -1;
 		ioc->ChainToChain = (int *) mem;
 		dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ChainToChain alloc @ %p, sz=%d bytes\n",
 			 	ioc->name, mem, sz));
 	} else {
 		mem = (u8 *) ioc->ChainToChain;
 	}
 	memset(mem, 0xFF, sz);
 	return num_chain;
 }
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /**
 *	PrimeIocFifos - Initialize IOC request and reply FIFOs.
 *	@ioc: Pointer to MPT_ADAPTER structure
 *
 *	This routine allocates memory for the MPT reply and request frame
 *	pools (if necessary), and primes the IOC reply FIFO with
 *	reply frames.
 *
 *	Returns 0 for success, non-zero for failure.
 */
 static int
 PrimeIocFifos(MPT_ADAPTER *ioc)
 {
 	MPT_FRAME_HDR *mf;
 	unsigned long flags;
 	dma_addr_t alloc_dma;
 	u8 *mem;
 	int i, reply_sz, sz, total_size, num_chain;
 	u64	dma_mask;
 	dma_mask = 0;
 	/*  Prime reply FIFO...  */
 	if (ioc->reply_frames == NULL) {
 		if ( (num_chain = initChainBuffers(ioc)) < 0)
 			return -1;
 		/*
 		 * 1078 errata workaround for the 36GB limitation
 		 */
 		if (ioc->pcidev->device == MPI_MANUFACTPAGE_DEVID_SAS1078 &&
 		    ioc->dma_mask > DMA_BIT_MASK(35)) {
 			if (!pci_set_dma_mask(ioc->pcidev, DMA_BIT_MASK(32))
 			    && !pci_set_consistent_dma_mask(ioc->pcidev,
 			    DMA_BIT_MASK(32))) {
 				dma_mask = DMA_BIT_MASK(35);
 				d36memprintk(ioc, printk(MYIOC_s_DEBUG_FMT
 				    "setting 35 bit addressing for "
 				    "Request/Reply/Chain and Sense Buffers\n",
 				    ioc->name));
 			} else {
 				/*Reseting DMA mask to 64 bit*/
 				pci_set_dma_mask(ioc->pcidev,
 					DMA_BIT_MASK(64));
 				pci_set_consistent_dma_mask(ioc->pcidev,
 					DMA_BIT_MASK(64));
 				printk(MYIOC_s_ERR_FMT
 				    "failed setting 35 bit addressing for "
 				    "Request/Reply/Chain and Sense Buffers\n",
 				    ioc->name);
 				return -1;
 			}
 		}
 		total_size = reply_sz = (ioc->reply_sz * ioc->reply_depth);
 		dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ReplyBuffer sz=%d bytes, ReplyDepth=%d\n",
 			 	ioc->name, ioc->reply_sz, ioc->reply_depth));
 		dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ReplyBuffer sz=%d[%x] bytes\n",
 			 	ioc->name, reply_sz, reply_sz));
 		sz = (ioc->req_sz * ioc->req_depth);
 		dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "RequestBuffer sz=%d bytes, RequestDepth=%d\n",
 			 	ioc->name, ioc->req_sz, ioc->req_depth));
 		dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "RequestBuffer sz=%d[%x] bytes\n",
 			 	ioc->name, sz, sz));
 		total_size += sz;
 		sz = num_chain * ioc->req_sz; /* chain buffer pool size */
 		dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ChainBuffer sz=%d bytes, ChainDepth=%d\n",
 			 	ioc->name, ioc->req_sz, num_chain));
 		dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ChainBuffer sz=%d[%x] bytes num_chain=%d\n",
 			 	ioc->name, sz, sz, num_chain));
 		total_size += sz;
 		mem = pci_alloc_consistent(ioc->pcidev, total_size, &alloc_dma);
 		if (mem == NULL) {
 			printk(MYIOC_s_ERR_FMT "Unable to allocate Reply, Request, Chain Buffers!\n",
 				ioc->name);
 			goto out_fail;
 		}
 		dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Total alloc @ %p[%p], sz=%d[%x] bytes\n",
 			 	ioc->name, mem, (void *)(ulong)alloc_dma, total_size, total_size));
 		memset(mem, 0, total_size);
 		ioc->alloc_total += total_size;
 		ioc->alloc = mem;
 		ioc->alloc_dma = alloc_dma;
 		ioc->alloc_sz = total_size;
 		ioc->reply_frames = (MPT_FRAME_HDR *) mem;
 		ioc->reply_frames_low_dma = (u32) (alloc_dma & 0xFFFFFFFF);
 		dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ReplyBuffers @ %p[%p]\n",
 	 		ioc->name, ioc->reply_frames, (void *)(ulong)alloc_dma));
 		alloc_dma += reply_sz;
 		mem += reply_sz;
 		/*  Request FIFO - WE manage this!  */
 		ioc->req_frames = (MPT_FRAME_HDR *) mem;
 		ioc->req_frames_dma = alloc_dma;
 		dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "RequestBuffers @ %p[%p]\n",
 			 	ioc->name, mem, (void *)(ulong)alloc_dma));
 		ioc->req_frames_low_dma = (u32) (alloc_dma & 0xFFFFFFFF);
 #if defined(CONFIG_MTRR) && 0
 		/*
 		 *  Enable Write Combining MTRR for IOC's memory region.
 		 *  (at least as much as we can; "size and base must be
 		 *  multiples of 4 kiB"
 		 */
 		ioc->mtrr_reg = mtrr_add(ioc->req_frames_dma,
 					 sz,
 					 MTRR_TYPE_WRCOMB, 1);
 		dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "MTRR region registered (base:size=%08x:%x)\n",
 				ioc->name, ioc->req_frames_dma, sz));
 #endif
 		for (i = 0; i < ioc->req_depth; i++) {
 			alloc_dma += ioc->req_sz;
 			mem += ioc->req_sz;
 		}
 		ioc->ChainBuffer = mem;
 		ioc->ChainBufferDMA = alloc_dma;
 		dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ChainBuffers @ %p(%p)\n",
 			ioc->name, ioc->ChainBuffer, (void *)(ulong)ioc->ChainBufferDMA));
 		/* Initialize the free chain Q.
 	 	*/
 		INIT_LIST_HEAD(&ioc->FreeChainQ);
 		/* Post the chain buffers to the FreeChainQ.
 	 	*/
 		mem = (u8 *)ioc->ChainBuffer;
 		for (i=0; i < num_chain; i++) {
 			mf = (MPT_FRAME_HDR *) mem;
 			list_add_tail(&mf->u.frame.linkage.list, &ioc->FreeChainQ);
 			mem += ioc->req_sz;
 		}
 		/* Initialize Request frames linked list
 		 */
 		alloc_dma = ioc->req_frames_dma;
 		mem = (u8 *) ioc->req_frames;
 		spin_lock_irqsave(&ioc->FreeQlock, flags);
 		INIT_LIST_HEAD(&ioc->FreeQ);
 		for (i = 0; i < ioc->req_depth; i++) {
 			mf = (MPT_FRAME_HDR *) mem;
 			/*  Queue REQUESTs *internally*!  */
 			list_add_tail(&mf->u.frame.linkage.list, &ioc->FreeQ);
 			mem += ioc->req_sz;
 		}
 		spin_unlock_irqrestore(&ioc->FreeQlock, flags);
 		sz = (ioc->req_depth * MPT_SENSE_BUFFER_ALLOC);
 		ioc->sense_buf_pool =
 			pci_alloc_consistent(ioc->pcidev, sz, &ioc->sense_buf_pool_dma);
 		if (ioc->sense_buf_pool == NULL) {
 			printk(MYIOC_s_ERR_FMT "Unable to allocate Sense Buffers!\n",
 				ioc->name);
 			goto out_fail;
 		}
 		ioc->sense_buf_low_dma = (u32) (ioc->sense_buf_pool_dma & 0xFFFFFFFF);
 		ioc->alloc_total += sz;
 		dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "SenseBuffers @ %p[%p]\n",
 			ioc->name, ioc->sense_buf_pool, (void *)(ulong)ioc->sense_buf_pool_dma));
 	}
 	/* Post Reply frames to FIFO
 	 */
 	alloc_dma = ioc->alloc_dma;
 	dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ReplyBuffers @ %p[%p]\n",
 	 	ioc->name, ioc->reply_frames, (void *)(ulong)alloc_dma));
 	for (i = 0; i < ioc->reply_depth; i++) {
 		/*  Write each address to the IOC!  */
 		CHIPREG_WRITE32(&ioc->chip->ReplyFifo, alloc_dma);
 		alloc_dma += ioc->reply_sz;
 	}
 	if (dma_mask == DMA_BIT_MASK(35) && !pci_set_dma_mask(ioc->pcidev,
 	    ioc->dma_mask) && !pci_set_consistent_dma_mask(ioc->pcidev,
 	    ioc->dma_mask))
 		d36memprintk(ioc, printk(MYIOC_s_DEBUG_FMT
 		    "restoring 64 bit addressing\n", ioc->name));
 	return 0;
 out_fail:
 	if (ioc->alloc != NULL) {
 		sz = ioc->alloc_sz;
 		pci_free_consistent(ioc->pcidev,
 				sz,
 				ioc->alloc, ioc->alloc_dma);
 		ioc->reply_frames = NULL;
 		ioc->req_frames = NULL;
 		ioc->alloc_total -= sz;
 	}
 	if (ioc->sense_buf_pool != NULL) {
 		sz = (ioc->req_depth * MPT_SENSE_BUFFER_ALLOC);
 		pci_free_consistent(ioc->pcidev,
 				sz,
 				ioc->sense_buf_pool, ioc->sense_buf_pool_dma);
 		ioc->sense_buf_pool = NULL;
 	}
 	if (dma_mask == DMA_BIT_MASK(35) && !pci_set_dma_mask(ioc->pcidev,
 	    DMA_BIT_MASK(64)) && !pci_set_consistent_dma_mask(ioc->pcidev,
 	    DMA_BIT_MASK(64)))
 		d36memprintk(ioc, printk(MYIOC_s_DEBUG_FMT
 		    "restoring 64 bit addressing\n", ioc->name));
 	return -1;
 }
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /**
 *	mpt_handshake_req_reply_wait - Send MPT request to and receive reply
 *	from IOC via doorbell handshake method.
 *	@ioc: Pointer to MPT_ADAPTER structure
 *	@reqBytes: Size of the request in bytes
 *	@req: Pointer to MPT request frame
 *	@replyBytes: Expected size of the reply in bytes
 *	@u16reply: Pointer to area where reply should be written
 *	@maxwait: Max wait time for a reply (in seconds)
 *	@sleepFlag: Specifies whether the process can sleep
 *
 *	NOTES: It is the callers responsibility to byte-swap fields in the
 *	request which are greater than 1 byte in size.  It is also the
 *	callers responsibility to byte-swap response fields which are
 *	greater than 1 byte in size.
 *
 *	Returns 0 for success, non-zero for failure.
 */
 static int
 mpt_handshake_req_reply_wait(MPT_ADAPTER *ioc, int reqBytes, u32 *req,
 		int replyBytes, u16 *u16reply, int maxwait, int sleepFlag)
 {
 	MPIDefaultReply_t *mptReply;
 	int failcnt = 0;
 	int t;
 	/*
 	 * Get ready to cache a handshake reply
 	 */
 	ioc->hs_reply_idx = 0;
 	mptReply = (MPIDefaultReply_t *) ioc->hs_reply;
 	mptReply->MsgLength = 0;
 	/*
 	 * Make sure there are no doorbells (WRITE 0 to IntStatus reg),
 	 * then tell IOC that we want to handshake a request of N words.
 	 * (WRITE u32val to Doorbell reg).
 	 */
 	CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
 	CHIPREG_WRITE32(&ioc->chip->Doorbell,
 			((MPI_FUNCTION_HANDSHAKE<<MPI_DOORBELL_FUNCTION_SHIFT) |
 			 ((reqBytes/4)<<MPI_DOORBELL_ADD_DWORDS_SHIFT)));
 	/*
 	 * Wait for IOC's doorbell handshake int
 	 */
 	if ((t = WaitForDoorbellInt(ioc, 5, sleepFlag)) < 0)
 		failcnt++;
 	dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "HandShake request start reqBytes=%d, WaitCnt=%d%s\n",
 			ioc->name, reqBytes, t, failcnt ? " - MISSING DOORBELL HANDSHAKE!" : ""));
 	/* Read doorbell and check for active bit */
 	if (!(CHIPREG_READ32(&ioc->chip->Doorbell) & MPI_DOORBELL_ACTIVE))
 			return -1;
 	/*
 	 * Clear doorbell int (WRITE 0 to IntStatus reg),
 	 * then wait for IOC to ACKnowledge that it's ready for
 	 * our handshake request.
 	 */
 	CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
 	if (!failcnt && (t = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0)
 		failcnt++;
 	if (!failcnt) {
 		int	 ii;
 		u8	*req_as_bytes = (u8 *) req;
 		/*
 		 * Stuff request words via doorbell handshake,
 		 * with ACK from IOC for each.
 		 */
 		for (ii = 0; !failcnt && ii < reqBytes/4; ii++) {
 			u32 word = ((req_as_bytes[(ii*4) + 0] <<  0) |
 				    (req_as_bytes[(ii*4) + 1] <<  8) |
 				    (req_as_bytes[(ii*4) + 2] << 16) |
 				    (req_as_bytes[(ii*4) + 3] << 24));
 			CHIPREG_WRITE32(&ioc->chip->Doorbell, word);
 			if ((t = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0)
 				failcnt++;
 		}
 		dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Handshake request frame (@%p) header\n", ioc->name, req));
 		DBG_DUMP_REQUEST_FRAME_HDR(ioc, (u32 *)req);
 		dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "HandShake request post done, WaitCnt=%d%s\n",
 				ioc->name, t, failcnt ? " - MISSING DOORBELL ACK!" : ""));
 		/*
 		 * Wait for completion of doorbell handshake reply from the IOC
 		 */
 		if (!failcnt && (t = WaitForDoorbellReply(ioc, maxwait, sleepFlag)) < 0)
 			failcnt++;
 		dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "HandShake reply count=%d%s\n",
 				ioc->name, t, failcnt ? " - MISSING DOORBELL REPLY!" : ""));
 		/*
 		 * Copy out the cached reply...
 		 */
 		for (ii=0; ii < min(replyBytes/2,mptReply->MsgLength*2); ii++)
 			u16reply[ii] = ioc->hs_reply[ii];
 	} else {
 		return -99;
 	}
 	return -failcnt;
 }
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /**
 *	WaitForDoorbellAck - Wait for IOC doorbell handshake acknowledge
 *	@ioc: Pointer to MPT_ADAPTER structure
 *	@howlong: How long to wait (in seconds)
 *	@sleepFlag: Specifies whether the process can sleep
 *
 *	This routine waits (up to ~2 seconds max) for IOC doorbell
 *	handshake ACKnowledge, indicated by the IOP_DOORBELL_STATUS
 *	bit in its IntStatus register being clear.
 *
 *	Returns a negative value on failure, else wait loop count.
 */
 static int
 WaitForDoorbellAck(MPT_ADAPTER *ioc, int howlong, int sleepFlag)
 {
 	int cntdn;
 	int count = 0;
 	u32 intstat=0;
 	cntdn = 1000 * howlong;
 	if (sleepFlag == CAN_SLEEP) {
 		while (--cntdn) {
 			msleep (1);
 			intstat = CHIPREG_READ32(&ioc->chip->IntStatus);
 			if (! (intstat & MPI_HIS_IOP_DOORBELL_STATUS))
 				break;
 			count++;
 		}
 	} else {
 		while (--cntdn) {
 			udelay (1000);
 			intstat = CHIPREG_READ32(&ioc->chip->IntStatus);
 			if (! (intstat & MPI_HIS_IOP_DOORBELL_STATUS))
 				break;
 			count++;
 		}
 	}
 	if (cntdn) {
 		dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "WaitForDoorbell ACK (count=%d)\n",
 				ioc->name, count));
 		return count;
 	}
 	printk(MYIOC_s_ERR_FMT "Doorbell ACK timeout (count=%d), IntStatus=%x!\n",
 			ioc->name, count, intstat);
 	return -1;
 }
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /**
 *	WaitForDoorbellInt - Wait for IOC to set its doorbell interrupt bit
 *	@ioc: Pointer to MPT_ADAPTER structure
 *	@howlong: How long to wait (in seconds)
 *	@sleepFlag: Specifies whether the process can sleep
 *
 *	This routine waits (up to ~2 seconds max) for IOC doorbell interrupt
 *	(MPI_HIS_DOORBELL_INTERRUPT) to be set in the IntStatus register.
 *
 *	Returns a negative value on failure, else wait loop count.
 */
 static int
 WaitForDoorbellInt(MPT_ADAPTER *ioc, int howlong, int sleepFlag)
 {
 	int cntdn;
 	int count = 0;
 	u32 intstat=0;
 	cntdn = 1000 * howlong;
 	if (sleepFlag == CAN_SLEEP) {
 		while (--cntdn) {
 			intstat = CHIPREG_READ32(&ioc->chip->IntStatus);
 			if (intstat & MPI_HIS_DOORBELL_INTERRUPT)
 				break;
 			msleep(1);
 			count++;
 		}
 	} else {
 		while (--cntdn) {
 			intstat = CHIPREG_READ32(&ioc->chip->IntStatus);
 			if (intstat & MPI_HIS_DOORBELL_INTERRUPT)
 				break;
 			udelay (1000);
 			count++;
 		}
 	}
 	if (cntdn) {
 		dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "WaitForDoorbell INT (cnt=%d) howlong=%d\n",
 				ioc->name, count, howlong));
 		return count;
 	}
 	printk(MYIOC_s_ERR_FMT "Doorbell INT timeout (count=%d), IntStatus=%x!\n",
 			ioc->name, count, intstat);
 	return -1;
 }
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /**
 *	WaitForDoorbellReply - Wait for and capture an IOC handshake reply.
 *	@ioc: Pointer to MPT_ADAPTER structure
 *	@howlong: How long to wait (in seconds)
 *	@sleepFlag: Specifies whether the process can sleep
 *
 *	This routine polls the IOC for a handshake reply, 16 bits at a time.
 *	Reply is cached to IOC private area large enough to hold a maximum
 *	of 128 bytes of reply data.
 *
 *	Returns a negative value on failure, else size of reply in WORDS.
 */
 static int
 WaitForDoorbellReply(MPT_ADAPTER *ioc, int howlong, int sleepFlag)
 {
 	int u16cnt = 0;
 	int failcnt = 0;
 	int t;
 	u16 *hs_reply = ioc->hs_reply;
 	volatile MPIDefaultReply_t *mptReply = (MPIDefaultReply_t *) ioc->hs_reply;
 	u16 hword;
 	hs_reply[0] = hs_reply[1] = hs_reply[7] = 0;
 	/*
 	 * Get first two u16's so we can look at IOC's intended reply MsgLength
 	 */
 	u16cnt=0;
 	if ((t = WaitForDoorbellInt(ioc, howlong, sleepFlag)) < 0) {
 		failcnt++;
 	} else {
 		hs_reply[u16cnt++] = le16_to_cpu(CHIPREG_READ32(&ioc->chip->Doorbell) & 0x0000FFFF);
 		CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
 		if ((t = WaitForDoorbellInt(ioc, 5, sleepFlag)) < 0)
 			failcnt++;
 		else {
 			hs_reply[u16cnt++] = le16_to_cpu(CHIPREG_READ32(&ioc->chip->Doorbell) & 0x0000FFFF);
 			CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
 		}
 	}
 	dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "WaitCnt=%d First handshake reply word=%08x%s\n",
 			ioc->name, t, le32_to_cpu(*(u32 *)hs_reply),
 			failcnt ? " - MISSING DOORBELL HANDSHAKE!" : ""));
 	/*
 	 * If no error (and IOC said MsgLength is > 0), piece together
 	 * reply 16 bits at a time.
 	 */
 	for (u16cnt=2; !failcnt && u16cnt < (2 * mptReply->MsgLength); u16cnt++) {
 		if ((t = WaitForDoorbellInt(ioc, 5, sleepFlag)) < 0)
 			failcnt++;
 		hword = le16_to_cpu(CHIPREG_READ32(&ioc->chip->Doorbell) & 0x0000FFFF);
 		/* don't overflow our IOC hs_reply[] buffer! */
 		if (u16cnt < ARRAY_SIZE(ioc->hs_reply))
 			hs_reply[u16cnt] = hword;
 		CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
 	}
 	if (!failcnt && (t = WaitForDoorbellInt(ioc, 5, sleepFlag)) < 0)
 		failcnt++;
 	CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
 	if (failcnt) {
 		printk(MYIOC_s_ERR_FMT "Handshake reply failure!\n",
 				ioc->name);
 		return -failcnt;
 	}
 #if 0
 	else if (u16cnt != (2 * mptReply->MsgLength)) {
 		return -101;
 	}
 	else if ((mptReply->IOCStatus & MPI_IOCSTATUS_MASK) != MPI_IOCSTATUS_SUCCESS) {
 		return -102;
 	}
 #endif
 	dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Got Handshake reply:\n", ioc->name));
 	DBG_DUMP_REPLY_FRAME(ioc, (u32 *)mptReply);
 	dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "WaitForDoorbell REPLY WaitCnt=%d (sz=%d)\n",
 			ioc->name, t, u16cnt/2));
 	return u16cnt/2;
 }
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /**
 *	GetLanConfigPages - Fetch LANConfig pages.
 *	@ioc: Pointer to MPT_ADAPTER structure
 *
 *	Return: 0 for success
 *	-ENOMEM if no memory available
 *		-EPERM if not allowed due to ISR context
 *		-EAGAIN if no msg frames currently available
 *		-EFAULT for non-successful reply or no reply (timeout)
 */
 static int
 GetLanConfigPages(MPT_ADAPTER *ioc)
 {
 	ConfigPageHeader_t	 hdr;
 	CONFIGPARMS		 cfg;
 	LANPage0_t		*ppage0_alloc;
 	dma_addr_t		 page0_dma;
 	LANPage1_t		*ppage1_alloc;
 	dma_addr_t		 page1_dma;
 	int			 rc = 0;
 	int			 data_sz;
 	int			 copy_sz;
 	/* Get LAN Page 0 header */
 	hdr.PageVersion = 0;
 	hdr.PageLength = 0;
 	hdr.PageNumber = 0;
 	hdr.PageType = MPI_CONFIG_PAGETYPE_LAN;
 	cfg.cfghdr.hdr = &hdr;
 	cfg.physAddr = -1;
 	cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
 	cfg.dir = 0;
 	cfg.pageAddr = 0;
 	cfg.timeout = 0;
 	if ((rc = mpt_config(ioc, &cfg)) != 0)
 		return rc;
 	if (hdr.PageLength > 0) {
 		data_sz = hdr.PageLength * 4;
 		ppage0_alloc = (LANPage0_t *) pci_alloc_consistent(ioc->pcidev, data_sz, &page0_dma);
 		rc = -ENOMEM;
 		if (ppage0_alloc) {
 			memset((u8 *)ppage0_alloc, 0, data_sz);
 			cfg.physAddr = page0_dma;
 			cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
 			if ((rc = mpt_config(ioc, &cfg)) == 0) {
 				/* save the data */
 				copy_sz = min_t(int, sizeof(LANPage0_t), data_sz);
 				memcpy(&ioc->lan_cnfg_page0, ppage0_alloc, copy_sz);
 			}
 			pci_free_consistent(ioc->pcidev, data_sz, (u8 *) ppage0_alloc, page0_dma);
 			/* FIXME!
 			 *	Normalize endianness of structure data,
 			 *	by byte-swapping all > 1 byte fields!
 			 */
 		}
 		if (rc)
 			return rc;
 	}
 	/* Get LAN Page 1 header */
 	hdr.PageVersion = 0;
 	hdr.PageLength = 0;
 	hdr.PageNumber = 1;
 	hdr.PageType = MPI_CONFIG_PAGETYPE_LAN;
 	cfg.cfghdr.hdr = &hdr;
 	cfg.physAddr = -1;
 	cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
 	cfg.dir = 0;
 	cfg.pageAddr = 0;
 	if ((rc = mpt_config(ioc, &cfg)) != 0)
 		return rc;
 	if (hdr.PageLength == 0)
 		return 0;
 	data_sz = hdr.PageLength * 4;
 	rc = -ENOMEM;
 	ppage1_alloc = (LANPage1_t *) pci_alloc_consistent(ioc->pcidev, data_sz, &page1_dma);
 	if (ppage1_alloc) {
 		memset((u8 *)ppage1_alloc, 0, data_sz);
 		cfg.physAddr = page1_dma;
 		cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
 		if ((rc = mpt_config(ioc, &cfg)) == 0) {
 			/* save the data */
 			copy_sz = min_t(int, sizeof(LANPage1_t), data_sz);
 			memcpy(&ioc->lan_cnfg_page1, ppage1_alloc, copy_sz);
 		}
 		pci_free_consistent(ioc->pcidev, data_sz, (u8 *) ppage1_alloc, page1_dma);
 		/* FIXME!
 		 *	Normalize endianness of structure data,
 		 *	by byte-swapping all > 1 byte fields!
 		 */
 	}
 	return rc;
 }
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /**
 *	mptbase_sas_persist_operation - Perform operation on SAS Persistent Table
 *	@ioc: Pointer to MPT_ADAPTER structure
 *	@persist_opcode: see below
 *
 *	MPI_SAS_OP_CLEAR_NOT_PRESENT - Free all persist TargetID mappings for
 *		devices not currently present.
 *	MPI_SAS_OP_CLEAR_ALL_PERSISTENT - Clear al persist TargetID mappings
 *
 *	NOTE: Don't use not this function during interrupt time.
 *
 *	Returns 0 for success, non-zero error
 */
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 int
 mptbase_sas_persist_operation(MPT_ADAPTER *ioc, u8 persist_opcode)
 {
 	SasIoUnitControlRequest_t	*sasIoUnitCntrReq;
 	SasIoUnitControlReply_t		*sasIoUnitCntrReply;
 	MPT_FRAME_HDR			*mf = NULL;
 	MPIHeader_t			*mpi_hdr;
 	int				ret = 0;
 	unsigned long 	 		timeleft;
 	mutex_lock(&ioc->mptbase_cmds.mutex);
 	/* init the internal cmd struct */
 	memset(ioc->mptbase_cmds.reply, 0 , MPT_DEFAULT_FRAME_SIZE);
 	INITIALIZE_MGMT_STATUS(ioc->mptbase_cmds.status)
 	/* insure garbage is not sent to fw */
 	switch(persist_opcode) {
 	case MPI_SAS_OP_CLEAR_NOT_PRESENT:
 	case MPI_SAS_OP_CLEAR_ALL_PERSISTENT:
 		break;
 	default:
 		ret = -1;
 		goto out;
 	}
 	printk(KERN_DEBUG  "%s: persist_opcode=%x\n",
 		__func__, persist_opcode);
 	/* Get a MF for this command.
 	 */
 	if ((mf = mpt_get_msg_frame(mpt_base_index, ioc)) == NULL) {
 		printk(KERN_DEBUG "%s: no msg frames!\n", __func__);
 		ret = -1;
 		goto out;
        }
 	mpi_hdr = (MPIHeader_t *) mf;
 	sasIoUnitCntrReq = (SasIoUnitControlRequest_t *)mf;
 	memset(sasIoUnitCntrReq,0,sizeof(SasIoUnitControlRequest_t));
 	sasIoUnitCntrReq->Function = MPI_FUNCTION_SAS_IO_UNIT_CONTROL;
 	sasIoUnitCntrReq->MsgContext = mpi_hdr->MsgContext;
 	sasIoUnitCntrReq->Operation = persist_opcode;
 	mpt_put_msg_frame(mpt_base_index, ioc, mf);
 	timeleft = wait_for_completion_timeout(&ioc->mptbase_cmds.done, 10*HZ);
 	if (!(ioc->mptbase_cmds.status & MPT_MGMT_STATUS_COMMAND_GOOD)) {
 		ret = -ETIME;
 		printk(KERN_DEBUG "%s: failed\n", __func__);
 		if (ioc->mptbase_cmds.status & MPT_MGMT_STATUS_DID_IOCRESET)
 			goto out;
 		if (!timeleft) {
 			printk(KERN_DEBUG "%s: Issuing Reset from %s!!\n",
 			    ioc->name, __func__);
 			mpt_HardResetHandler(ioc, CAN_SLEEP);
 			mpt_free_msg_frame(ioc, mf);
 		}
 		goto out;
 	}
 	if (!(ioc->mptbase_cmds.status & MPT_MGMT_STATUS_RF_VALID)) {
 		ret = -1;
 		goto out;
 	}
 	sasIoUnitCntrReply =
 	    (SasIoUnitControlReply_t *)ioc->mptbase_cmds.reply;
 	if (le16_to_cpu(sasIoUnitCntrReply->IOCStatus) != MPI_IOCSTATUS_SUCCESS) {
 		printk(KERN_DEBUG "%s: IOCStatus=0x%X IOCLogInfo=0x%X\n",
 		    __func__, sasIoUnitCntrReply->IOCStatus,
 		    sasIoUnitCntrReply->IOCLogInfo);
 		printk(KERN_DEBUG "%s: failed\n", __func__);
 		ret = -1;
 	} else
 		printk(KERN_DEBUG "%s: success\n", __func__);
 out:
 	CLEAR_MGMT_STATUS(ioc->mptbase_cmds.status)
 	mutex_unlock(&ioc->mptbase_cmds.mutex);
 	return ret;
 }
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 static void
 mptbase_raid_process_event_data(MPT_ADAPTER *ioc,
    MpiEventDataRaid_t * pRaidEventData)
 {
 	int 	volume;
 	int 	reason;
 	int 	disk;
 	int 	status;
 	int 	flags;
 	int 	state;
 	volume	= pRaidEventData->VolumeID;
 	reason	= pRaidEventData->ReasonCode;
 	disk	= pRaidEventData->PhysDiskNum;
 	status	= le32_to_cpu(pRaidEventData->SettingsStatus);
 	flags	= (status >> 0) & 0xff;
 	state	= (status >> 8) & 0xff;
 	if (reason == MPI_EVENT_RAID_RC_DOMAIN_VAL_NEEDED) {
 		return;
 	}
 	if ((reason >= MPI_EVENT_RAID_RC_PHYSDISK_CREATED &&
 	     reason <= MPI_EVENT_RAID_RC_PHYSDISK_STATUS_CHANGED) ||
 	    (reason == MPI_EVENT_RAID_RC_SMART_DATA)) {
 		printk(MYIOC_s_INFO_FMT "RAID STATUS CHANGE for PhysDisk %d id=%d\n",
 			ioc->name, disk, volume);
 	} else {
 		printk(MYIOC_s_INFO_FMT "RAID STATUS CHANGE for VolumeID %d\n",
 			ioc->name, volume);
 	}
 	switch(reason) {
 	case MPI_EVENT_RAID_RC_VOLUME_CREATED:
 		printk(MYIOC_s_INFO_FMT "  volume has been created\n",
 			ioc->name);
 		break;
 	case MPI_EVENT_RAID_RC_VOLUME_DELETED:
 		printk(MYIOC_s_INFO_FMT "  volume has been deleted\n",
 			ioc->name);
 		break;
 	case MPI_EVENT_RAID_RC_VOLUME_SETTINGS_CHANGED:
 		printk(MYIOC_s_INFO_FMT "  volume settings have been changed\n",
 			ioc->name);
 		break;
 	case MPI_EVENT_RAID_RC_VOLUME_STATUS_CHANGED:
 		printk(MYIOC_s_INFO_FMT "  volume is now %s%s%s%s\n",
 			ioc->name,
 			state == MPI_RAIDVOL0_STATUS_STATE_OPTIMAL
 			 ? "optimal"
 			 : state == MPI_RAIDVOL0_STATUS_STATE_DEGRADED
 			  ? "degraded"
 			  : state == MPI_RAIDVOL0_STATUS_STATE_FAILED
 			   ? "failed"
 			   : "state unknown",
 			flags & MPI_RAIDVOL0_STATUS_FLAG_ENABLED
 			 ? ", enabled" : "",
 			flags & MPI_RAIDVOL0_STATUS_FLAG_QUIESCED
 			 ? ", quiesced" : "",
 			flags & MPI_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS
 			 ? ", resync in progress" : "" );
 		break;
 	case MPI_EVENT_RAID_RC_VOLUME_PHYSDISK_CHANGED:
 		printk(MYIOC_s_INFO_FMT "  volume membership of PhysDisk %d has changed\n",
 			ioc->name, disk);
 		break;
 	case MPI_EVENT_RAID_RC_PHYSDISK_CREATED:
 		printk(MYIOC_s_INFO_FMT "  PhysDisk has been created\n",
 			ioc->name);
 		break;
 	case MPI_EVENT_RAID_RC_PHYSDISK_DELETED:
 		printk(MYIOC_s_INFO_FMT "  PhysDisk has been deleted\n",
 			ioc->name);
 		break;
 	case MPI_EVENT_RAID_RC_PHYSDISK_SETTINGS_CHANGED:
 		printk(MYIOC_s_INFO_FMT "  PhysDisk settings have been changed\n",
 			ioc->name);
 		break;
 	case MPI_EVENT_RAID_RC_PHYSDISK_STATUS_CHANGED:
 		printk(MYIOC_s_INFO_FMT "  PhysDisk is now %s%s%s\n",
 			ioc->name,
 			state == MPI_PHYSDISK0_STATUS_ONLINE
 			 ? "online"
 			 : state == MPI_PHYSDISK0_STATUS_MISSING
 			  ? "missing"
 			  : state == MPI_PHYSDISK0_STATUS_NOT_COMPATIBLE
 			   ? "not compatible"
 			   : state == MPI_PHYSDISK0_STATUS_FAILED
 			    ? "failed"
 			    : state == MPI_PHYSDISK0_STATUS_INITIALIZING
 			     ? "initializing"
 			     : state == MPI_PHYSDISK0_STATUS_OFFLINE_REQUESTED
 			      ? "offline requested"
 			      : state == MPI_PHYSDISK0_STATUS_FAILED_REQUESTED
 			       ? "failed requested"
 			       : state == MPI_PHYSDISK0_STATUS_OTHER_OFFLINE
 			        ? "offline"
 			        : "state unknown",
 			flags & MPI_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC
 			 ? ", out of sync" : "",
 			flags & MPI_PHYSDISK0_STATUS_FLAG_QUIESCED
 			 ? ", quiesced" : "" );
 		break;
 	case MPI_EVENT_RAID_RC_DOMAIN_VAL_NEEDED:
 		printk(MYIOC_s_INFO_FMT "  Domain Validation needed for PhysDisk %d\n",
 			ioc->name, disk);
 		break;
 	case MPI_EVENT_RAID_RC_SMART_DATA:
 		printk(MYIOC_s_INFO_FMT "  SMART data received, ASC/ASCQ = %02xh/%02xh\n",
 			ioc->name, pRaidEventData->ASC, pRaidEventData->ASCQ);
 		break;
 	case MPI_EVENT_RAID_RC_REPLACE_ACTION_STARTED:
 		printk(MYIOC_s_INFO_FMT "  replacement of PhysDisk %d has started\n",
 			ioc->name, disk);
 		break;
 	}
 }
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /**
 *	GetIoUnitPage2 - Retrieve BIOS version and boot order information.
 *	@ioc: Pointer to MPT_ADAPTER structure
 *
 *	Returns: 0 for success
 *	-ENOMEM if no memory available
 *		-EPERM if not allowed due to ISR context
 *		-EAGAIN if no msg frames currently available
 *		-EFAULT for non-successful reply or no reply (timeout)
 */
 static int
 GetIoUnitPage2(MPT_ADAPTER *ioc)
 {
 	ConfigPageHeader_t	 hdr;
 	CONFIGPARMS		 cfg;
 	IOUnitPage2_t		*ppage_alloc;
 	dma_addr_t		 page_dma;
 	int			 data_sz;
 	int			 rc;
 	/* Get the page header */
 	hdr.PageVersion = 0;
 	hdr.PageLength = 0;
 	hdr.PageNumber = 2;
 	hdr.PageType = MPI_CONFIG_PAGETYPE_IO_UNIT;
 	cfg.cfghdr.hdr = &hdr;
 	cfg.physAddr = -1;
 	cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
 	cfg.dir = 0;
 	cfg.pageAddr = 0;
 	cfg.timeout = 0;
 	if ((rc = mpt_config(ioc, &cfg)) != 0)
 		return rc;
 	if (hdr.PageLength == 0)
 		return 0;
 	/* Read the config page */
 	data_sz = hdr.PageLength * 4;
 	rc = -ENOMEM;
 	ppage_alloc = (IOUnitPage2_t *) pci_alloc_consistent(ioc->pcidev, data_sz, &page_dma);
 	if (ppage_alloc) {
 		memset((u8 *)ppage_alloc, 0, data_sz);
 		cfg.physAddr = page_dma;
 		cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
 		/* If Good, save data */
 		if ((rc = mpt_config(ioc, &cfg)) == 0)
 			ioc->biosVersion = le32_to_cpu(ppage_alloc->BiosVersion);
 		pci_free_consistent(ioc->pcidev, data_sz, (u8 *) ppage_alloc, page_dma);
 	}
 	return rc;
 }
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /**
 *	mpt_GetScsiPortSettings - read SCSI Port Page 0 and 2
 *	@ioc: Pointer to a Adapter Strucutre
 *	@portnum: IOC port number
 *
 *	Return: -EFAULT if read of config page header fails
 *			or if no nvram
 *	If read of SCSI Port Page 0 fails,
 *		NVRAM = MPT_HOST_NVRAM_INVALID  (0xFFFFFFFF)
 *		Adapter settings: async, narrow
 *		Return 1
 *	If read of SCSI Port Page 2 fails,
 *		Adapter settings valid
 *		NVRAM = MPT_HOST_NVRAM_INVALID  (0xFFFFFFFF)
 *		Return 1
 *	Else
 *		Both valid
 *		Return 0
 *	CHECK - what type of locking mechanisms should be used????
 */
 static int
 mpt_GetScsiPortSettings(MPT_ADAPTER *ioc, int portnum)
 {
 	u8			*pbuf;
 	dma_addr_t		 buf_dma;
 	CONFIGPARMS		 cfg;
 	ConfigPageHeader_t	 header;
 	int			 ii;
 	int			 data, rc = 0;
 	/* Allocate memory
 	 */
 	if (!ioc->spi_data.nvram) {
 		int	 sz;
 		u8	*mem;
 		sz = MPT_MAX_SCSI_DEVICES * sizeof(int);
 		mem = kmalloc(sz, GFP_ATOMIC);
 		if (mem == NULL)
 			return -EFAULT;
 		ioc->spi_data.nvram = (int *) mem;
 		dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "SCSI device NVRAM settings @ %p, sz=%d\n",
 			ioc->name, ioc->spi_data.nvram, sz));
 	}
 	/* Invalidate NVRAM information
 	 */
 	for (ii=0; ii < MPT_MAX_SCSI_DEVICES; ii++) {
 		ioc->spi_data.nvram[ii] = MPT_HOST_NVRAM_INVALID;
 	}
 	/* Read SPP0 header, allocate memory, then read page.
 	 */
 	header.PageVersion = 0;
 	header.PageLength = 0;
 	header.PageNumber = 0;
 	header.PageType = MPI_CONFIG_PAGETYPE_SCSI_PORT;
 	cfg.cfghdr.hdr = &header;
 	cfg.physAddr = -1;
 	cfg.pageAddr = portnum;
 	cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
 	cfg.dir = 0;
 	cfg.timeout = 0;	/* use default */
 	if (mpt_config(ioc, &cfg) != 0)
 		 return -EFAULT;
 	if (header.PageLength > 0) {
 		pbuf = pci_alloc_consistent(ioc->pcidev, header.PageLength * 4, &buf_dma);
 		if (pbuf) {
 			cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
 			cfg.physAddr = buf_dma;
 			if (mpt_config(ioc, &cfg) != 0) {
 				ioc->spi_data.maxBusWidth = MPT_NARROW;
 				ioc->spi_data.maxSyncOffset = 0;
 				ioc->spi_data.minSyncFactor = MPT_ASYNC;
 				ioc->spi_data.busType = MPT_HOST_BUS_UNKNOWN;
 				rc = 1;
 				ddvprintk(ioc, printk(MYIOC_s_DEBUG_FMT
 					"Unable to read PortPage0 minSyncFactor=%x\n",
 					ioc->name, ioc->spi_data.minSyncFactor));
 			} else {
 				/* Save the Port Page 0 data
 				 */
 				SCSIPortPage0_t  *pPP0 = (SCSIPortPage0_t  *) pbuf;
 				pPP0->Capabilities = le32_to_cpu(pPP0->Capabilities);
 				pPP0->PhysicalInterface = le32_to_cpu(pPP0->PhysicalInterface);
 				if ( (pPP0->Capabilities & MPI_SCSIPORTPAGE0_CAP_QAS) == 0 ) {
 					ioc->spi_data.noQas |= MPT_TARGET_NO_NEGO_QAS;
 					ddvprintk(ioc, printk(MYIOC_s_DEBUG_FMT
 						"noQas due to Capabilities=%x\n",
 						ioc->name, pPP0->Capabilities));
 				}
 				ioc->spi_data.maxBusWidth = pPP0->Capabilities & MPI_SCSIPORTPAGE0_CAP_WIDE ? 1 : 0;
 				data = pPP0->Capabilities & MPI_SCSIPORTPAGE0_CAP_MAX_SYNC_OFFSET_MASK;
 				if (data) {
 					ioc->spi_data.maxSyncOffset = (u8) (data >> 16);
 					data = pPP0->Capabilities & MPI_SCSIPORTPAGE0_CAP_MIN_SYNC_PERIOD_MASK;
 					ioc->spi_data.minSyncFactor = (u8) (data >> 8);
 					ddvprintk(ioc, printk(MYIOC_s_DEBUG_FMT
 						"PortPage0 minSyncFactor=%x\n",
 						ioc->name, ioc->spi_data.minSyncFactor));
 				} else {
 					ioc->spi_data.maxSyncOffset = 0;
 					ioc->spi_data.minSyncFactor = MPT_ASYNC;
 				}
 				ioc->spi_data.busType = pPP0->PhysicalInterface & MPI_SCSIPORTPAGE0_PHY_SIGNAL_TYPE_MASK;
 				/* Update the minSyncFactor based on bus type.
 				 */
 				if ((ioc->spi_data.busType == MPI_SCSIPORTPAGE0_PHY_SIGNAL_HVD) ||
 					(ioc->spi_data.busType == MPI_SCSIPORTPAGE0_PHY_SIGNAL_SE))  {
 					if (ioc->spi_data.minSyncFactor < MPT_ULTRA) {
 						ioc->spi_data.minSyncFactor = MPT_ULTRA;
 						ddvprintk(ioc, printk(MYIOC_s_DEBUG_FMT
 							"HVD or SE detected, minSyncFactor=%x\n",
 							ioc->name, ioc->spi_data.minSyncFactor));
 					}
 				}
 			}
 			if (pbuf) {
 				pci_free_consistent(ioc->pcidev, header.PageLength * 4, pbuf, buf_dma);
 			}
 		}
 	}
 	/* SCSI Port Page 2 - Read the header then the page.
 	 */
 	header.PageVersion = 0;
 	header.PageLength = 0;
 	header.PageNumber = 2;
 	header.PageType = MPI_CONFIG_PAGETYPE_SCSI_PORT;
 	cfg.cfghdr.hdr = &header;
 	cfg.physAddr = -1;
 	cfg.pageAddr = portnum;
 	cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
 	cfg.dir = 0;
 	if (mpt_config(ioc, &cfg) != 0)
 		return -EFAULT;
 	if (header.PageLength > 0) {
 		/* Allocate memory and read SCSI Port Page 2
 		 */
 		pbuf = pci_alloc_consistent(ioc->pcidev, header.PageLength * 4, &buf_dma);
 		if (pbuf) {
 			cfg.action = MPI_CONFIG_ACTION_PAGE_READ_NVRAM;
 			cfg.physAddr = buf_dma;
 			if (mpt_config(ioc, &cfg) != 0) {
 				/* Nvram data is left with INVALID mark
 				 */
 				rc = 1;
 			} else if (ioc->pcidev->vendor == PCI_VENDOR_ID_ATTO) {
 				/* This is an ATTO adapter, read Page2 accordingly
 				*/
 				ATTO_SCSIPortPage2_t *pPP2 = (ATTO_SCSIPortPage2_t  *) pbuf;
 				ATTODeviceInfo_t *pdevice = NULL;
 				u16 ATTOFlags;
 				/* Save the Port Page 2 data
 				 * (reformat into a 32bit quantity)
 				 */
 				for (ii=0; ii < MPT_MAX_SCSI_DEVICES; ii++) {
 				  pdevice = &pPP2->DeviceSettings[ii];
 				  ATTOFlags = le16_to_cpu(pdevice->ATTOFlags);
 				  data = 0;
 				  /* Translate ATTO device flags to LSI format
 				   */
 				  if (ATTOFlags & ATTOFLAG_DISC)
 				    data |= (MPI_SCSIPORTPAGE2_DEVICE_DISCONNECT_ENABLE);
 				  if (ATTOFlags & ATTOFLAG_ID_ENB)
 				    data |= (MPI_SCSIPORTPAGE2_DEVICE_ID_SCAN_ENABLE);
 				  if (ATTOFlags & ATTOFLAG_LUN_ENB)
 				    data |= (MPI_SCSIPORTPAGE2_DEVICE_LUN_SCAN_ENABLE);
 				  if (ATTOFlags & ATTOFLAG_TAGGED)
 				    data |= (MPI_SCSIPORTPAGE2_DEVICE_TAG_QUEUE_ENABLE);
 				  if (!(ATTOFlags & ATTOFLAG_WIDE_ENB))
 				    data |= (MPI_SCSIPORTPAGE2_DEVICE_WIDE_DISABLE);
 				  data = (data << 16) | (pdevice->Period << 8) | 10;
 				  ioc->spi_data.nvram[ii] = data;
 				}
 			} else {
 				SCSIPortPage2_t *pPP2 = (SCSIPortPage2_t  *) pbuf;
 				MpiDeviceInfo_t	*pdevice = NULL;
 				/*
 				 * Save "Set to Avoid SCSI Bus Resets" flag
 				 */
 				ioc->spi_data.bus_reset =
 				    (le32_to_cpu(pPP2->PortFlags) &
 			        MPI_SCSIPORTPAGE2_PORT_FLAGS_AVOID_SCSI_RESET) ?
 				    0 : 1 ;
 				/* Save the Port Page 2 data
 				 * (reformat into a 32bit quantity)
 				 */
 				data = le32_to_cpu(pPP2->PortFlags) & MPI_SCSIPORTPAGE2_PORT_FLAGS_DV_MASK;
 				ioc->spi_data.PortFlags = data;
 				for (ii=0; ii < MPT_MAX_SCSI_DEVICES; ii++) {
 					pdevice = &pPP2->DeviceSettings[ii];
 					data = (le16_to_cpu(pdevice->DeviceFlags) << 16) |
 						(pdevice->SyncFactor << 8) | pdevice->Timeout;
 					ioc->spi_data.nvram[ii] = data;
 				}
 			}
 			pci_free_consistent(ioc->pcidev, header.PageLength * 4, pbuf, buf_dma);
 		}
 	}
 	/* Update Adapter limits with those from NVRAM
 	 * Comment: Don't need to do this. Target performance
 	 * parameters will never exceed the adapters limits.
 	 */
 	return rc;
 }
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /**
 *	mpt_readScsiDevicePageHeaders - save version and length of SDP1
 *	@ioc: Pointer to a Adapter Strucutre
 *	@portnum: IOC port number
 *
 *	Return: -EFAULT if read of config page header fails
 *		or 0 if success.
 */
 static int
 mpt_readScsiDevicePageHeaders(MPT_ADAPTER *ioc, int portnum)
 {
 	CONFIGPARMS		 cfg;
 	ConfigPageHeader_t	 header;
 	/* Read the SCSI Device Page 1 header
 	 */
 	header.PageVersion = 0;
 	header.PageLength = 0;
 	header.PageNumber = 1;
 	header.PageType = MPI_CONFIG_PAGETYPE_SCSI_DEVICE;
 	cfg.cfghdr.hdr = &header;
 	cfg.physAddr = -1;
 	cfg.pageAddr = portnum;
 	cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
 	cfg.dir = 0;
 	cfg.timeout = 0;
 	if (mpt_config(ioc, &cfg) != 0)
 		 return -EFAULT;
 	ioc->spi_data.sdp1version = cfg.cfghdr.hdr->PageVersion;
 	ioc->spi_data.sdp1length = cfg.cfghdr.hdr->PageLength;
 	header.PageVersion = 0;
 	header.PageLength = 0;
 	header.PageNumber = 0;
 	header.PageType = MPI_CONFIG_PAGETYPE_SCSI_DEVICE;
 	if (mpt_config(ioc, &cfg) != 0)
 		 return -EFAULT;
 	ioc->spi_data.sdp0version = cfg.cfghdr.hdr->PageVersion;
 	ioc->spi_data.sdp0length = cfg.cfghdr.hdr->PageLength;
 	dcprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Headers: 0: version %d length %d\n",
 			ioc->name, ioc->spi_data.sdp0version, ioc->spi_data.sdp0length));
 	dcprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Headers: 1: version %d length %d\n",
 			ioc->name, ioc->spi_data.sdp1version, ioc->spi_data.sdp1length));
 	return 0;
 }
 /**
 * mpt_inactive_raid_list_free - This clears this link list.
 * @ioc : pointer to per adapter structure
 **/
 static void
 mpt_inactive_raid_list_free(MPT_ADAPTER *ioc)
 {
 	struct inactive_raid_component_info *component_info, *pNext;
 	if (list_empty(&ioc->raid_data.inactive_list))
 		return;
 	mutex_lock(&ioc->raid_data.inactive_list_mutex);
 	list_for_each_entry_safe(component_info, pNext,
 	    &ioc->raid_data.inactive_list, list) {
 		list_del(&component_info->list);
 		kfree(component_info);
 	}
 	mutex_unlock(&ioc->raid_data.inactive_list_mutex);
 }
 /**
 * mpt_inactive_raid_volumes - sets up link list of phy_disk_nums for devices belonging in an inactive volume
 *
 * @ioc : pointer to per adapter structure
 * @channel : volume channel
 * @id : volume target id
 **/
 static void
 mpt_inactive_raid_volumes(MPT_ADAPTER *ioc, u8 channel, u8 id)
 {
 	CONFIGPARMS			cfg;
 	ConfigPageHeader_t		hdr;
 	dma_addr_t			dma_handle;
 	pRaidVolumePage0_t		buffer = NULL;
 	int				i;
 	RaidPhysDiskPage0_t 		phys_disk;
 	struct inactive_raid_component_info *component_info;
 	int				handle_inactive_volumes;
 	memset(&cfg, 0 , sizeof(CONFIGPARMS));
 	memset(&hdr, 0 , sizeof(ConfigPageHeader_t));
 	hdr.PageType = MPI_CONFIG_PAGETYPE_RAID_VOLUME;
 	cfg.pageAddr = (channel << 8) + id;
 	cfg.cfghdr.hdr = &hdr;
 	cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
 	if (mpt_config(ioc, &cfg) != 0)
 		goto out;
 	if (!hdr.PageLength)
 		goto out;
 	buffer = pci_alloc_consistent(ioc->pcidev, hdr.PageLength * 4,
 	    &dma_handle);
 	if (!buffer)
 		goto out;
 	cfg.physAddr = dma_handle;
 	cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
 	if (mpt_config(ioc, &cfg) != 0)
 		goto out;
 	if (!buffer->NumPhysDisks)
 		goto out;
 	handle_inactive_volumes =
 	   (buffer->VolumeStatus.Flags & MPI_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE ||
 	   (buffer->VolumeStatus.Flags & MPI_RAIDVOL0_STATUS_FLAG_ENABLED) == 0 ||
 	    buffer->VolumeStatus.State == MPI_RAIDVOL0_STATUS_STATE_FAILED ||
 	    buffer->VolumeStatus.State == MPI_RAIDVOL0_STATUS_STATE_MISSING) ? 1 : 0;
 	if (!handle_inactive_volumes)
 		goto out;
 	mutex_lock(&ioc->raid_data.inactive_list_mutex);
 	for (i = 0; i < buffer->NumPhysDisks; i++) {
 		if(mpt_raid_phys_disk_pg0(ioc,
 		    buffer->PhysDisk[i].PhysDiskNum, &phys_disk) != 0)
 			continue;
 		if ((component_info = kmalloc(sizeof (*component_info),
 		 GFP_KERNEL)) == NULL)
 			continue;
 		component_info->volumeID = id;
 		component_info->volumeBus = channel;
 		component_info->d.PhysDiskNum = phys_disk.PhysDiskNum;
 		component_info->d.PhysDiskBus = phys_disk.PhysDiskBus;
 		component_info->d.PhysDiskID = phys_disk.PhysDiskID;
 		component_info->d.PhysDiskIOC = phys_disk.PhysDiskIOC;
 		list_add_tail(&component_info->list,
 		    &ioc->raid_data.inactive_list);
 	}
 	mutex_unlock(&ioc->raid_data.inactive_list_mutex);
 out:
 	if (buffer)
 		pci_free_consistent(ioc->pcidev, hdr.PageLength * 4, buffer,
 		    dma_handle);
 }
 /**
 *	mpt_raid_phys_disk_pg0 - returns phys disk page zero
 *	@ioc: Pointer to a Adapter Structure
 *	@phys_disk_num: io unit unique phys disk num generated by the ioc
 *	@phys_disk: requested payload data returned
 *
 *	Return:
 *	0 on success
 *	-EFAULT if read of config page header fails or data pointer not NULL
 *	-ENOMEM if pci_alloc failed
 **/
 int
 mpt_raid_phys_disk_pg0(MPT_ADAPTER *ioc, u8 phys_disk_num,
 			RaidPhysDiskPage0_t *phys_disk)
 {
 	CONFIGPARMS			cfg;
 	ConfigPageHeader_t		hdr;
 	dma_addr_t			dma_handle;
 	pRaidPhysDiskPage0_t		buffer = NULL;
 	int				rc;
 	memset(&cfg, 0 , sizeof(CONFIGPARMS));
 	memset(&hdr, 0 , sizeof(ConfigPageHeader_t));
 	memset(phys_disk, 0, sizeof(RaidPhysDiskPage0_t));
 	hdr.PageVersion = MPI_RAIDPHYSDISKPAGE0_PAGEVERSION;
 	hdr.PageType = MPI_CONFIG_PAGETYPE_RAID_PHYSDISK;
 	cfg.cfghdr.hdr = &hdr;
 	cfg.physAddr = -1;
 	cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
 	if (mpt_config(ioc, &cfg) != 0) {
 		rc = -EFAULT;
 		goto out;
 	}
 	if (!hdr.PageLength) {
 		rc = -EFAULT;
 		goto out;
 	}
 	buffer = pci_alloc_consistent(ioc->pcidev, hdr.PageLength * 4,
 	    &dma_handle);
 	if (!buffer) {
 		rc = -ENOMEM;
 		goto out;
 	}
 	cfg.physAddr = dma_handle;
 	cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
 	cfg.pageAddr = phys_disk_num;
 	if (mpt_config(ioc, &cfg) != 0) {
 		rc = -EFAULT;
 		goto out;
 	}
 	rc = 0;
 	memcpy(phys_disk, buffer, sizeof(*buffer));
 	phys_disk->MaxLBA = le32_to_cpu(buffer->MaxLBA);
 out:
 	if (buffer)
 		pci_free_consistent(ioc->pcidev, hdr.PageLength * 4, buffer,
 		    dma_handle);
 	return rc;
 }
 /**
 *	mpt_raid_phys_disk_get_num_paths - returns number paths associated to this phys_num
 *	@ioc: Pointer to a Adapter Structure
 *	@phys_disk_num: io unit unique phys disk num generated by the ioc
 *
 *	Return:
 *	returns number paths
 **/
 int
 mpt_raid_phys_disk_get_num_paths(MPT_ADAPTER *ioc, u8 phys_disk_num)
 {
 	CONFIGPARMS		 	cfg;
 	ConfigPageHeader_t	 	hdr;
 	dma_addr_t			dma_handle;
 	pRaidPhysDiskPage1_t		buffer = NULL;
 	int				rc;
 	memset(&cfg, 0 , sizeof(CONFIGPARMS));
 	memset(&hdr, 0 , sizeof(ConfigPageHeader_t));
 	hdr.PageVersion = MPI_RAIDPHYSDISKPAGE1_PAGEVERSION;
 	hdr.PageType = MPI_CONFIG_PAGETYPE_RAID_PHYSDISK;
 	hdr.PageNumber = 1;
 	cfg.cfghdr.hdr = &hdr;
 	cfg.physAddr = -1;
 	cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
 	if (mpt_config(ioc, &cfg) != 0) {
 		rc = 0;
 		goto out;
 	}
 	if (!hdr.PageLength) {
 		rc = 0;
 		goto out;
 	}
 	buffer = pci_alloc_consistent(ioc->pcidev, hdr.PageLength * 4,
 	    &dma_handle);
 	if (!buffer) {
 		rc = 0;
 		goto out;
 	}
 	cfg.physAddr = dma_handle;
 	cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
 	cfg.pageAddr = phys_disk_num;
 	if (mpt_config(ioc, &cfg) != 0) {
 		rc = 0;
 		goto out;
 	}
 	rc = buffer->NumPhysDiskPaths;
 out:
 	if (buffer)
 		pci_free_consistent(ioc->pcidev, hdr.PageLength * 4, buffer,
 		    dma_handle);
 	return rc;
 }
 EXPORT_SYMBOL(mpt_raid_phys_disk_get_num_paths);
 /**
 *	mpt_raid_phys_disk_pg1 - returns phys disk page 1
 *	@ioc: Pointer to a Adapter Structure
 *	@phys_disk_num: io unit unique phys disk num generated by the ioc
 *	@phys_disk: requested payload data returned
 *
 *	Return:
 *	0 on success
 *	-EFAULT if read of config page header fails or data pointer not NULL
 *	-ENOMEM if pci_alloc failed
 **/
 int
 mpt_raid_phys_disk_pg1(MPT_ADAPTER *ioc, u8 phys_disk_num,
 		RaidPhysDiskPage1_t *phys_disk)
 {
 	CONFIGPARMS		 	cfg;
 	ConfigPageHeader_t	 	hdr;
 	dma_addr_t			dma_handle;
 	pRaidPhysDiskPage1_t		buffer = NULL;
 	int				rc;
 	int				i;
 	__le64				sas_address;
 	memset(&cfg, 0 , sizeof(CONFIGPARMS));
 	memset(&hdr, 0 , sizeof(ConfigPageHeader_t));
 	rc = 0;
 	hdr.PageVersion = MPI_RAIDPHYSDISKPAGE1_PAGEVERSION;
 	hdr.PageType = MPI_CONFIG_PAGETYPE_RAID_PHYSDISK;
 	hdr.PageNumber = 1;
 	cfg.cfghdr.hdr = &hdr;
 	cfg.physAddr = -1;
 	cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
 	if (mpt_config(ioc, &cfg) != 0) {
 		rc = -EFAULT;
 		goto out;
 	}
 	if (!hdr.PageLength) {
 		rc = -EFAULT;
 		goto out;
 	}
 	buffer = pci_alloc_consistent(ioc->pcidev, hdr.PageLength * 4,
 	    &dma_handle);
 	if (!buffer) {
 		rc = -ENOMEM;
 		goto out;
 	}
 	cfg.physAddr = dma_handle;
 	cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
 	cfg.pageAddr = phys_disk_num;
 	if (mpt_config(ioc, &cfg) != 0) {
 		rc = -EFAULT;
 		goto out;
 	}
 	phys_disk->NumPhysDiskPaths = buffer->NumPhysDiskPaths;
 	phys_disk->PhysDiskNum = phys_disk_num;
 	for (i = 0; i < phys_disk->NumPhysDiskPaths; i++) {
 		phys_disk->Path[i].PhysDiskID = buffer->Path[i].PhysDiskID;
 		phys_disk->Path[i].PhysDiskBus = buffer->Path[i].PhysDiskBus;
 		phys_disk->Path[i].OwnerIdentifier =
 				buffer->Path[i].OwnerIdentifier;
 		phys_disk->Path[i].Flags = le16_to_cpu(buffer->Path[i].Flags);
 		memcpy(&sas_address, &buffer->Path[i].WWID, sizeof(__le64));
 		sas_address = le64_to_cpu(sas_address);
 		memcpy(&phys_disk->Path[i].WWID, &sas_address, sizeof(__le64));
 		memcpy(&sas_address,
 				&buffer->Path[i].OwnerWWID, sizeof(__le64));
 		sas_address = le64_to_cpu(sas_address);
 		memcpy(&phys_disk->Path[i].OwnerWWID,
 				&sas_address, sizeof(__le64));
 	}
 out:
 	if (buffer)
 		pci_free_consistent(ioc->pcidev, hdr.PageLength * 4, buffer,
 		    dma_handle);
 	return rc;
 }
 EXPORT_SYMBOL(mpt_raid_phys_disk_pg1);
 /**
 *	mpt_findImVolumes - Identify IDs of hidden disks and RAID Volumes
 *	@ioc: Pointer to a Adapter Strucutre
 *
 *	Return:
 *	0 on success
 *	-EFAULT if read of config page header fails or data pointer not NULL
 *	-ENOMEM if pci_alloc failed
 **/
 int
 mpt_findImVolumes(MPT_ADAPTER *ioc)
 {
 	IOCPage2_t		*pIoc2;
 	u8			*mem;
 	dma_addr_t		 ioc2_dma;
 	CONFIGPARMS		 cfg;
 	ConfigPageHeader_t	 header;
 	int			 rc = 0;
 	int			 iocpage2sz;
 	int			 i;
 	if (!ioc->ir_firmware)
 		return 0;
 	/* Free the old page
 	 */
 	kfree(ioc->raid_data.pIocPg2);
 	ioc->raid_data.pIocPg2 = NULL;
 	mpt_inactive_raid_list_free(ioc);
 	/* Read IOCP2 header then the page.
 	 */
 	header.PageVersion = 0;
 	header.PageLength = 0;
 	header.PageNumber = 2;
 	header.PageType = MPI_CONFIG_PAGETYPE_IOC;
 	cfg.cfghdr.hdr = &header;
 	cfg.physAddr = -1;
 	cfg.pageAddr = 0;
 	cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
 	cfg.dir = 0;
 	cfg.timeout = 0;
 	if (mpt_config(ioc, &cfg) != 0)
 		 return -EFAULT;
 	if (header.PageLength == 0)
 		return -EFAULT;
 	iocpage2sz = header.PageLength * 4;
 	pIoc2 = pci_alloc_consistent(ioc->pcidev, iocpage2sz, &ioc2_dma);
 	if (!pIoc2)
 		return -ENOMEM;
 	cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
 	cfg.physAddr = ioc2_dma;
 	if (mpt_config(ioc, &cfg) != 0)
 		goto out;
 	mem = kmalloc(iocpage2sz, GFP_KERNEL);
 	if (!mem)
 		goto out;
 	memcpy(mem, (u8 *)pIoc2, iocpage2sz);
 	ioc->raid_data.pIocPg2 = (IOCPage2_t *) mem;
 	mpt_read_ioc_pg_3(ioc);
 	for (i = 0; i < pIoc2->NumActiveVolumes ; i++)
 		mpt_inactive_raid_volumes(ioc,
 		    pIoc2->RaidVolume[i].VolumeBus,
 		    pIoc2->RaidVolume[i].VolumeID);
 out:
 	pci_free_consistent(ioc->pcidev, iocpage2sz, pIoc2, ioc2_dma);
 	return rc;
 }
 static int
 mpt_read_ioc_pg_3(MPT_ADAPTER *ioc)
 {
 	IOCPage3_t		*pIoc3;
 	u8			*mem;
 	CONFIGPARMS		 cfg;
 	ConfigPageHeader_t	 header;
 	dma_addr_t		 ioc3_dma;
 	int			 iocpage3sz = 0;
 	/* Free the old page
 	 */
 	kfree(ioc->raid_data.pIocPg3);
 	ioc->raid_data.pIocPg3 = NULL;
 	/* There is at least one physical disk.
 	 * Read and save IOC Page 3
 	 */
 	header.PageVersion = 0;
 	header.PageLength = 0;
 	header.PageNumber = 3;
 	header.PageType = MPI_CONFIG_PAGETYPE_IOC;
 	cfg.cfghdr.hdr = &header;
 	cfg.physAddr = -1;
 	cfg.pageAddr = 0;
 	cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
 	cfg.dir = 0;
 	cfg.timeout = 0;
 	if (mpt_config(ioc, &cfg) != 0)
 		return 0;
 	if (header.PageLength == 0)
 		return 0;
 	/* Read Header good, alloc memory
 	 */
 	iocpage3sz = header.PageLength * 4;
 	pIoc3 = pci_alloc_consistent(ioc->pcidev, iocpage3sz, &ioc3_dma);
 	if (!pIoc3)
 		return 0;
 	/* Read the Page and save the data
 	 * into malloc'd memory.
 	 */
 	cfg.physAddr = ioc3_dma;
 	cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
 	if (mpt_config(ioc, &cfg) == 0) {
 		mem = kmalloc(iocpage3sz, GFP_KERNEL);
 		if (mem) {
 			memcpy(mem, (u8 *)pIoc3, iocpage3sz);
 			ioc->raid_data.pIocPg3 = (IOCPage3_t *) mem;
 		}
 	}
 	pci_free_consistent(ioc->pcidev, iocpage3sz, pIoc3, ioc3_dma);
 	return 0;
 }
 static void
 mpt_read_ioc_pg_4(MPT_ADAPTER *ioc)
 {
 	IOCPage4_t		*pIoc4;
 	CONFIGPARMS		 cfg;
 	ConfigPageHeader_t	 header;
 	dma_addr_t		 ioc4_dma;
 	int			 iocpage4sz;
 	/* Read and save IOC Page 4
 	 */
 	header.PageVersion = 0;
 	header.PageLength = 0;
 	header.PageNumber = 4;
 	header.PageType = MPI_CONFIG_PAGETYPE_IOC;
 	cfg.cfghdr.hdr = &header;
 	cfg.physAddr = -1;
 	cfg.pageAddr = 0;
 	cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
 	cfg.dir = 0;
 	cfg.timeout = 0;
 	if (mpt_config(ioc, &cfg) != 0)
 		return;
 	if (header.PageLength == 0)
 		return;
 	if ( (pIoc4 = ioc->spi_data.pIocPg4) == NULL ) {
 		iocpage4sz = (header.PageLength + 4) * 4; /* Allow 4 additional SEP's */
 		pIoc4 = pci_alloc_consistent(ioc->pcidev, iocpage4sz, &ioc4_dma);
 		if (!pIoc4)
 			return;
 		ioc->alloc_total += iocpage4sz;
 	} else {
 		ioc4_dma = ioc->spi_data.IocPg4_dma;
 		iocpage4sz = ioc->spi_data.IocPg4Sz;
 	}
 	/* Read the Page into dma memory.
 	 */
 	cfg.physAddr = ioc4_dma;
 	cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
 	if (mpt_config(ioc, &cfg) == 0) {
 		ioc->spi_data.pIocPg4 = (IOCPage4_t *) pIoc4;
 		ioc->spi_data.IocPg4_dma = ioc4_dma;
 		ioc->spi_data.IocPg4Sz = iocpage4sz;
 	} else {
 		pci_free_consistent(ioc->pcidev, iocpage4sz, pIoc4, ioc4_dma);
 		ioc->spi_data.pIocPg4 = NULL;
 		ioc->alloc_total -= iocpage4sz;
 	}
 }
 static void
 mpt_read_ioc_pg_1(MPT_ADAPTER *ioc)
 {
 	IOCPage1_t		*pIoc1;
 	CONFIGPARMS		 cfg;
 	ConfigPageHeader_t	 header;
 	dma_addr_t		 ioc1_dma;
 	int			 iocpage1sz = 0;
 	u32			 tmp;
 	/* Check the Coalescing Timeout in IOC Page 1
 	 */
 	header.PageVersion = 0;
 	header.PageLength = 0;
 	header.PageNumber = 1;
 	header.PageType = MPI_CONFIG_PAGETYPE_IOC;
 	cfg.cfghdr.hdr = &header;
 	cfg.physAddr = -1;
 	cfg.pageAddr = 0;
 	cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
 	cfg.dir = 0;
 	cfg.timeout = 0;
 	if (mpt_config(ioc, &cfg) != 0)
 		return;
 	if (header.PageLength == 0)
 		return;
 	/* Read Header good, alloc memory
 	 */
 	iocpage1sz = header.PageLength * 4;
 	pIoc1 = pci_alloc_consistent(ioc->pcidev, iocpage1sz, &ioc1_dma);
 	if (!pIoc1)
 		return;
 	/* Read the Page and check coalescing timeout
 	 */
 	cfg.physAddr = ioc1_dma;
 	cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
 	if (mpt_config(ioc, &cfg) == 0) {
 		tmp = le32_to_cpu(pIoc1->Flags) & MPI_IOCPAGE1_REPLY_COALESCING;
 		if (tmp == MPI_IOCPAGE1_REPLY_COALESCING) {
 			tmp = le32_to_cpu(pIoc1->CoalescingTimeout);
 			dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Coalescing Enabled Timeout = %d\n",
 					ioc->name, tmp));
 			if (tmp > MPT_COALESCING_TIMEOUT) {
 				pIoc1->CoalescingTimeout = cpu_to_le32(MPT_COALESCING_TIMEOUT);
 				/* Write NVRAM and current
 				 */
 				cfg.dir = 1;
 				cfg.action = MPI_CONFIG_ACTION_PAGE_WRITE_CURRENT;
 				if (mpt_config(ioc, &cfg) == 0) {
 					dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Reset Current Coalescing Timeout to = %d\n",
 							ioc->name, MPT_COALESCING_TIMEOUT));
 					cfg.action = MPI_CONFIG_ACTION_PAGE_WRITE_NVRAM;
 					if (mpt_config(ioc, &cfg) == 0) {
 						dprintk(ioc, printk(MYIOC_s_DEBUG_FMT
 								"Reset NVRAM Coalescing Timeout to = %d\n",
 								ioc->name, MPT_COALESCING_TIMEOUT));
 					} else {
 						dprintk(ioc, printk(MYIOC_s_DEBUG_FMT
 								"Reset NVRAM Coalescing Timeout Failed\n",
 								ioc->name));
 					}
 				} else {
 					dprintk(ioc, printk(MYIOC_s_WARN_FMT
 						"Reset of Current Coalescing Timeout Failed!\n",
 						ioc->name));
 				}
 			}
 		} else {
 			dprintk(ioc, printk(MYIOC_s_WARN_FMT "Coalescing Disabled\n", ioc->name));
 		}
 	}
 	pci_free_consistent(ioc->pcidev, iocpage1sz, pIoc1, ioc1_dma);
 	return;
 }
 static void
 mpt_get_manufacturing_pg_0(MPT_ADAPTER *ioc)
 {
 	CONFIGPARMS		cfg;
 	ConfigPageHeader_t	hdr;
 	dma_addr_t		buf_dma;
 	ManufacturingPage0_t	*pbuf = NULL;
 	memset(&cfg, 0 , sizeof(CONFIGPARMS));
 	memset(&hdr, 0 , sizeof(ConfigPageHeader_t));
 	hdr.PageType = MPI_CONFIG_PAGETYPE_MANUFACTURING;
 	cfg.cfghdr.hdr = &hdr;
 	cfg.physAddr = -1;
 	cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
 	cfg.timeout = 10;
 	if (mpt_config(ioc, &cfg) != 0)
 		goto out;
 	if (!cfg.cfghdr.hdr->PageLength)
 		goto out;
 	cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
 	pbuf = pci_alloc_consistent(ioc->pcidev, hdr.PageLength * 4, &buf_dma);
 	if (!pbuf)
 		goto out;
 	cfg.physAddr = buf_dma;
 	if (mpt_config(ioc, &cfg) != 0)
 		goto out;
 	memcpy(ioc->board_name, pbuf->BoardName, sizeof(ioc->board_name));
 	memcpy(ioc->board_assembly, pbuf->BoardAssembly, sizeof(ioc->board_assembly));
 	memcpy(ioc->board_tracer, pbuf->BoardTracerNumber, sizeof(ioc->board_tracer));
 	out:
 	if (pbuf)
 		pci_free_consistent(ioc->pcidev, hdr.PageLength * 4, pbuf, buf_dma);
 }
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /**
 *	SendEventNotification - Send EventNotification (on or off) request to adapter
 *	@ioc: Pointer to MPT_ADAPTER structure
 *	@EvSwitch: Event switch flags
 *	@sleepFlag: Specifies whether the process can sleep
 */
 static int
 SendEventNotification(MPT_ADAPTER *ioc, u8 EvSwitch, int sleepFlag)
 {
 	EventNotification_t	evn;
 	MPIDefaultReply_t	reply_buf;
 	memset(&evn, 0, sizeof(EventNotification_t));
 	memset(&reply_buf, 0, sizeof(MPIDefaultReply_t));
 	evn.Function = MPI_FUNCTION_EVENT_NOTIFICATION;
 	evn.Switch = EvSwitch;
 	evn.MsgContext = cpu_to_le32(mpt_base_index << 16);
 	devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT
 	    "Sending EventNotification (%d) request %p\n",
 	    ioc->name, EvSwitch, &evn));
 	return mpt_handshake_req_reply_wait(ioc, sizeof(EventNotification_t),
 	    (u32 *)&evn, sizeof(MPIDefaultReply_t), (u16 *)&reply_buf, 30,
 	    sleepFlag);
 }
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /**
 *	SendEventAck - Send EventAck request to MPT adapter.
 *	@ioc: Pointer to MPT_ADAPTER structure
 *	@evnp: Pointer to original EventNotification request
 */
 static int
 SendEventAck(MPT_ADAPTER *ioc, EventNotificationReply_t *evnp)
 {
 	EventAck_t	*pAck;
 	if ((pAck = (EventAck_t *) mpt_get_msg_frame(mpt_base_index, ioc)) == NULL) {
 		dfailprintk(ioc, printk(MYIOC_s_WARN_FMT "%s, no msg frames!!\n",
 		    ioc->name, __func__));
 		return -1;
 	}
 	devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending EventAck\n", ioc->name));
 	pAck->Function     = MPI_FUNCTION_EVENT_ACK;
 	pAck->ChainOffset  = 0;
 	pAck->Reserved[0]  = pAck->Reserved[1] = 0;
 	pAck->MsgFlags     = 0;
 	pAck->Reserved1[0] = pAck->Reserved1[1] = pAck->Reserved1[2] = 0;
 	pAck->Event        = evnp->Event;
 	pAck->EventContext = evnp->EventContext;
 	mpt_put_msg_frame(mpt_base_index, ioc, (MPT_FRAME_HDR *)pAck);
 	return 0;
 }
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /**
 *	mpt_config - Generic function to issue config message
 *	@ioc:   Pointer to an adapter structure
 *	@pCfg:  Pointer to a configuration structure. Struct contains
 *		action, page address, direction, physical address
 *		and pointer to a configuration page header
 *		Page header is updated.
 *
 *	Returns 0 for success
 *	-EPERM if not allowed due to ISR context
 *	-EAGAIN if no msg frames currently available
 *	-EFAULT for non-successful reply or no reply (timeout)
 */
 int
 mpt_config(MPT_ADAPTER *ioc, CONFIGPARMS *pCfg)
 {
 	Config_t	*pReq;
 	ConfigReply_t	*pReply;
 	ConfigExtendedPageHeader_t  *pExtHdr = NULL;
 	MPT_FRAME_HDR	*mf;
 	int		 ii;
 	int		 flagsLength;
 	long		 timeout;
 	int		 ret;
 	u8		 page_type = 0, extend_page;
 	unsigned long 	 timeleft;
 	unsigned long	 flags;
    int		 in_isr;
 	u8		 issue_hard_reset = 0;
 	u8		 retry_count = 0;
 	/*	Prevent calling wait_event() (below), if caller happens
 	 *	to be in ISR context, because that is fatal!
 	 */
 	in_isr = in_interrupt();
 	if (in_isr) {
 		dcprintk(ioc, printk(MYIOC_s_WARN_FMT "Config request not allowed in ISR context!\n",
 				ioc->name));
 		return -EPERM;
    }
 	/* don't send a config page during diag reset */
 	spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
 	if (ioc->ioc_reset_in_progress) {
 		dfailprintk(ioc, printk(MYIOC_s_DEBUG_FMT
 		    "%s: busy with host reset\n", ioc->name, __func__));
 		spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
 		return -EBUSY;
 	}
 	spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
 	/* don't send if no chance of success */
 	if (!ioc->active ||
 	    mpt_GetIocState(ioc, 1) != MPI_IOC_STATE_OPERATIONAL) {
 		dfailprintk(ioc, printk(MYIOC_s_DEBUG_FMT
 		    "%s: ioc not operational, %d, %xh\n",
 		    ioc->name, __func__, ioc->active,
 		    mpt_GetIocState(ioc, 0)));
 		return -EFAULT;
 	}
 retry_config:
 	mutex_lock(&ioc->mptbase_cmds.mutex);
 	/* init the internal cmd struct */
 	memset(ioc->mptbase_cmds.reply, 0 , MPT_DEFAULT_FRAME_SIZE);
 	INITIALIZE_MGMT_STATUS(ioc->mptbase_cmds.status)
 	/* Get and Populate a free Frame
 	 */
 	if ((mf = mpt_get_msg_frame(mpt_base_index, ioc)) == NULL) {
 		dcprintk(ioc, printk(MYIOC_s_WARN_FMT
 		"mpt_config: no msg frames!\n", ioc->name));
 		ret = -EAGAIN;
 		goto out;
 	}
 	pReq = (Config_t *)mf;
 	pReq->Action = pCfg->action;
 	pReq->Reserved = 0;
 	pReq->ChainOffset = 0;
 	pReq->Function = MPI_FUNCTION_CONFIG;
 	/* Assume page type is not extended and clear "reserved" fields. */
 	pReq->ExtPageLength = 0;
 	pReq->ExtPageType = 0;
 	pReq->MsgFlags = 0;
 	for (ii=0; ii < 8; ii++)
 		pReq->Reserved2[ii] = 0;
 	pReq->Header.PageVersion = pCfg->cfghdr.hdr->PageVersion;
 	pReq->Header.PageLength = pCfg->cfghdr.hdr->PageLength;
 	pReq->Header.PageNumber = pCfg->cfghdr.hdr->PageNumber;
 	pReq->Header.PageType = (pCfg->cfghdr.hdr->PageType & MPI_CONFIG_PAGETYPE_MASK);
 	if ((pCfg->cfghdr.hdr->PageType & MPI_CONFIG_PAGETYPE_MASK) == MPI_CONFIG_PAGETYPE_EXTENDED) {
 		pExtHdr = (ConfigExtendedPageHeader_t *)pCfg->cfghdr.ehdr;
 		pReq->ExtPageLength = cpu_to_le16(pExtHdr->ExtPageLength);
 		pReq->ExtPageType = pExtHdr->ExtPageType;
 		pReq->Header.PageType = MPI_CONFIG_PAGETYPE_EXTENDED;
 		/* Page Length must be treated as a reserved field for the
 		 * extended header.
 		 */
 		pReq->Header.PageLength = 0;
 	}
 	pReq->PageAddress = cpu_to_le32(pCfg->pageAddr);
 	/* Add a SGE to the config request.
 	 */
 	if (pCfg->dir)
 		flagsLength = MPT_SGE_FLAGS_SSIMPLE_WRITE;
 	else
 		flagsLength = MPT_SGE_FLAGS_SSIMPLE_READ;
 	if ((pCfg->cfghdr.hdr->PageType & MPI_CONFIG_PAGETYPE_MASK) ==
 	    MPI_CONFIG_PAGETYPE_EXTENDED) {
 		flagsLength |= pExtHdr->ExtPageLength * 4;
 		page_type = pReq->ExtPageType;
 		extend_page = 1;
 	} else {
 		flagsLength |= pCfg->cfghdr.hdr->PageLength * 4;
 		page_type = pReq->Header.PageType;
 		extend_page = 0;
 	}
 	dcprintk(ioc, printk(MYIOC_s_DEBUG_FMT
 	    "Sending Config request type 0x%x, page 0x%x and action %d\n",
 	    ioc->name, page_type, pReq->Header.PageNumber, pReq->Action));
 	ioc->add_sge((char *)&pReq->PageBufferSGE, flagsLength, pCfg->physAddr);
 	timeout = (pCfg->timeout < 15) ? HZ*15 : HZ*pCfg->timeout;
 	mpt_put_msg_frame(mpt_base_index, ioc, mf);
 	timeleft = wait_for_completion_timeout(&ioc->mptbase_cmds.done,
 		timeout);
 	if (!(ioc->mptbase_cmds.status & MPT_MGMT_STATUS_COMMAND_GOOD)) {
 		ret = -ETIME;
 		dfailprintk(ioc, printk(MYIOC_s_DEBUG_FMT
 		    "Failed Sending Config request type 0x%x, page 0x%x,"
 		    " action %d, status %xh, time left %ld\n\n",
 			ioc->name, page_type, pReq->Header.PageNumber,
 			pReq->Action, ioc->mptbase_cmds.status, timeleft));
 		if (ioc->mptbase_cmds.status & MPT_MGMT_STATUS_DID_IOCRESET)
 			goto out;
 		if (!timeleft)
 			issue_hard_reset = 1;
 		goto out;
 	}
 	if (!(ioc->mptbase_cmds.status & MPT_MGMT_STATUS_RF_VALID)) {
 		ret = -1;
 		goto out;
 	}
 	pReply = (ConfigReply_t	*)ioc->mptbase_cmds.reply;
 	ret = le16_to_cpu(pReply->IOCStatus) & MPI_IOCSTATUS_MASK;
 	if (ret == MPI_IOCSTATUS_SUCCESS) {
 		if (extend_page) {
 			pCfg->cfghdr.ehdr->ExtPageLength =
 			    le16_to_cpu(pReply->ExtPageLength);
 			pCfg->cfghdr.ehdr->ExtPageType =
 			    pReply->ExtPageType;
 		}
 		pCfg->cfghdr.hdr->PageVersion = pReply->Header.PageVersion;
 		pCfg->cfghdr.hdr->PageLength = pReply->Header.PageLength;
 		pCfg->cfghdr.hdr->PageNumber = pReply->Header.PageNumber;
 		pCfg->cfghdr.hdr->PageType = pReply->Header.PageType;
 	}
 	if (retry_count)
 		printk(MYIOC_s_INFO_FMT "Retry completed "
 		    "ret=0x%x timeleft=%ld\n",
 		    ioc->name, ret, timeleft);
 	dcprintk(ioc, printk(KERN_DEBUG "IOCStatus=%04xh, IOCLogInfo=%08xh\n",
 	     ret, le32_to_cpu(pReply->IOCLogInfo)));
 out:
 	CLEAR_MGMT_STATUS(ioc->mptbase_cmds.status)
 	mutex_unlock(&ioc->mptbase_cmds.mutex);
 	if (issue_hard_reset) {
 		issue_hard_reset = 0;
 		printk(MYIOC_s_WARN_FMT "Issuing Reset from %s!!\n",
 		    ioc->name, __func__);
 		mpt_HardResetHandler(ioc, CAN_SLEEP);
 		mpt_free_msg_frame(ioc, mf);
 		/* attempt one retry for a timed out command */
 		if (!retry_count) {
 			printk(MYIOC_s_INFO_FMT
 			    "Attempting Retry Config request"
 			    " type 0x%x, page 0x%x,"
 			    " action %d\n", ioc->name, page_type,
 			    pCfg->cfghdr.hdr->PageNumber, pCfg->action);
 			retry_count++;
 			goto retry_config;
 		}
 	}
 	return ret;
 }
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /**
 *	mpt_ioc_reset - Base cleanup for hard reset
 *	@ioc: Pointer to the adapter structure
 *	@reset_phase: Indicates pre- or post-reset functionality
 *
 *	Remark: Frees resources with internally generated commands.
 */
 static int
 mpt_ioc_reset(MPT_ADAPTER *ioc, int reset_phase)
 {
 	switch (reset_phase) {
 	case MPT_IOC_SETUP_RESET:
 		ioc->taskmgmt_quiesce_io = 1;
 		dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT
 		    "%s: MPT_IOC_SETUP_RESET\n", ioc->name, __func__));
 		break;
 	case MPT_IOC_PRE_RESET:
 		dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT
 		    "%s: MPT_IOC_PRE_RESET\n", ioc->name, __func__));
 		break;
 	case MPT_IOC_POST_RESET:
 		dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT
 		    "%s: MPT_IOC_POST_RESET\n",  ioc->name, __func__));
 /* wake up mptbase_cmds */
 		if (ioc->mptbase_cmds.status & MPT_MGMT_STATUS_PENDING) {
 			ioc->mptbase_cmds.status |=
 			    MPT_MGMT_STATUS_DID_IOCRESET;
 			complete(&ioc->mptbase_cmds.done);
 		}
 /* wake up taskmgmt_cmds */
 		if (ioc->taskmgmt_cmds.status & MPT_MGMT_STATUS_PENDING) {
 			ioc->taskmgmt_cmds.status |=
 				MPT_MGMT_STATUS_DID_IOCRESET;
 			complete(&ioc->taskmgmt_cmds.done);
 		}
 		break;
 	default:
 		break;
 	}
 	return 1;		/* currently means nothing really */
 }
 #ifdef CONFIG_PROC_FS		/* { */
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /*
 *	procfs (%MPT_PROCFS_MPTBASEDIR/...) support stuff...
 */
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /**
 *	procmpt_create - Create %MPT_PROCFS_MPTBASEDIR entries.
 *
 *	Returns 0 for success, non-zero for failure.
 */
 static int
 procmpt_create(void)
 {
 	struct proc_dir_entry	*ent;
 	mpt_proc_root_dir = proc_mkdir(MPT_PROCFS_MPTBASEDIR, NULL);
 	if (mpt_proc_root_dir == NULL)
 		return -ENOTDIR;
 	ent = create_proc_entry("summary", S_IFREG|S_IRUGO, mpt_proc_root_dir);
 	if (ent)
 		ent->read_proc = procmpt_summary_read;
 	ent = create_proc_entry("version", S_IFREG|S_IRUGO, mpt_proc_root_dir);
 	if (ent)
 		ent->read_proc = procmpt_version_read;
 	return 0;
 }
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /**
 *	procmpt_destroy - Tear down %MPT_PROCFS_MPTBASEDIR entries.
 *
 *	Returns 0 for success, non-zero for failure.
 */
 static void
 procmpt_destroy(void)
 {
 	remove_proc_entry("version", mpt_proc_root_dir);
 	remove_proc_entry("summary", mpt_proc_root_dir);
 	remove_proc_entry(MPT_PROCFS_MPTBASEDIR, NULL);
 }
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /**
 *	procmpt_summary_read - Handle read request of a summary file
 *	@buf: Pointer to area to write information
 *	@start: Pointer to start pointer
 *	@offset: Offset to start writing
 *	@request: Amount of read data requested
 *	@eof: Pointer to EOF integer
 *	@data: Pointer
 *
 *	Handles read request from /proc/mpt/summary or /proc/mpt/iocN/summary.
 *	Returns number of characters written to process performing the read.
 */
 static int
 procmpt_summary_read(char *buf, char **start, off_t offset, int request, int *eof, void *data)
 {
 	MPT_ADAPTER *ioc;
 	char *out = buf;
 	int len;
 	if (data) {
 		int more = 0;
 		ioc = data;
 		mpt_print_ioc_summary(ioc, out, &more, 0, 1);
 		out += more;
 	} else {
 		list_for_each_entry(ioc, &ioc_list, list) {
 			int	more = 0;
 			mpt_print_ioc_summary(ioc, out, &more, 0, 1);
 			out += more;
 			if ((out-buf) >= request)
 				break;
 		}
 	}
 	len = out - buf;
 	MPT_PROC_READ_RETURN(buf,start,offset,request,eof,len);
 }
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /**
 *	procmpt_version_read - Handle read request from /proc/mpt/version.
 *	@buf: Pointer to area to write information
 *	@start: Pointer to start pointer
 *	@offset: Offset to start writing
 *	@request: Amount of read data requested
 *	@eof: Pointer to EOF integer
 *	@data: Pointer
 *
 *	Returns number of characters written to process performing the read.
 */
 static int
 procmpt_version_read(char *buf, char **start, off_t offset, int request, int *eof, void *data)
 {
 	u8	 cb_idx;
 	int	 scsi, fc, sas, lan, ctl, targ, dmp;
 	char	*drvname;
 	int	 len;
 	len = sprintf(buf, "%s-%s\n", "mptlinux", MPT_LINUX_VERSION_COMMON);
 	len += sprintf(buf+len, "  Fusion MPT base driver\n");
 	scsi = fc = sas = lan = ctl = targ = dmp = 0;
 	for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
 		drvname = NULL;
 		if (MptCallbacks[cb_idx]) {
 			switch (MptDriverClass[cb_idx]) {
 			case MPTSPI_DRIVER:
 				if (!scsi++) drvname = "SPI host";
 				break;
 			case MPTFC_DRIVER:
 				if (!fc++) drvname = "FC host";
 				break;
 			case MPTSAS_DRIVER:
 				if (!sas++) drvname = "SAS host";
 				break;
 			case MPTLAN_DRIVER:
 				if (!lan++) drvname = "LAN";
 				break;
 			case MPTSTM_DRIVER:
 				if (!targ++) drvname = "SCSI target";
 				break;
 			case MPTCTL_DRIVER:
 				if (!ctl++) drvname = "ioctl";
 				break;
 			}
 			if (drvname)
 				len += sprintf(buf+len, "  Fusion MPT %s driver\n", drvname);
 		}
 	}
 	MPT_PROC_READ_RETURN(buf,start,offset,request,eof,len);
 }
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /**
 *	procmpt_iocinfo_read - Handle read request from /proc/mpt/iocN/info.
 *	@buf: Pointer to area to write information
 *	@start: Pointer to start pointer
 *	@offset: Offset to start writing
 *	@request: Amount of read data requested
 *	@eof: Pointer to EOF integer
 *	@data: Pointer
 *
 *	Returns number of characters written to process performing the read.
 */
 static int
 procmpt_iocinfo_read(char *buf, char **start, off_t offset, int request, int *eof, void *data)
 {
 	MPT_ADAPTER	*ioc = data;
 	int		 len;
 	char		 expVer[32];
 	int		 sz;
 	int		 p;
 	mpt_get_fw_exp_ver(expVer, ioc);
 	len = sprintf(buf, "%s:", ioc->name);
 	if (ioc->facts.Flags & MPI_IOCFACTS_FLAGS_FW_DOWNLOAD_BOOT)
 		len += sprintf(buf+len, "  (f/w download boot flag set)");
 //	if (ioc->facts.IOCExceptions & MPI_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL)
 //		len += sprintf(buf+len, "  CONFIG_CHECKSUM_FAIL!");
 	len += sprintf(buf+len, "\n  ProductID = 0x%04x (%s)\n",
 			ioc->facts.ProductID,
 			ioc->prod_name);
 	len += sprintf(buf+len, "  FWVersion = 0x%08x%s", ioc->facts.FWVersion.Word, expVer);
 	if (ioc->facts.FWImageSize)
 		len += sprintf(buf+len, " (fw_size=%d)", ioc->facts.FWImageSize);
 	len += sprintf(buf+len, "\n  MsgVersion = 0x%04x\n", ioc->facts.MsgVersion);
 	len += sprintf(buf+len, "  FirstWhoInit = 0x%02x\n", ioc->FirstWhoInit);
 	len += sprintf(buf+len, "  EventState = 0x%02x\n", ioc->facts.EventState);
 	len += sprintf(buf+len, "  CurrentHostMfaHighAddr = 0x%08x\n",
 			ioc->facts.CurrentHostMfaHighAddr);
 	len += sprintf(buf+len, "  CurrentSenseBufferHighAddr = 0x%08x\n",
 			ioc->facts.CurrentSenseBufferHighAddr);
 	len += sprintf(buf+len, "  MaxChainDepth = 0x%02x frames\n", ioc->facts.MaxChainDepth);
 	len += sprintf(buf+len, "  MinBlockSize = 0x%02x bytes\n", 4*ioc->facts.BlockSize);
 	len += sprintf(buf+len, "  RequestFrames @ 0x%p (Dma @ 0x%p)\n",
 					(void *)ioc->req_frames, (void *)(ulong)ioc->req_frames_dma);
 	/*
 	 *  Rounding UP to nearest 4-kB boundary here...
 	 */
 	sz = (ioc->req_sz * ioc->req_depth) + 128;
 	sz = ((sz + 0x1000UL - 1UL) / 0x1000) * 0x1000;
 	len += sprintf(buf+len, "    {CurReqSz=%d} x {CurReqDepth=%d} = %d bytes ^= 0x%x\n",
 					ioc->req_sz, ioc->req_depth, ioc->req_sz*ioc->req_depth, sz);
 	len += sprintf(buf+len, "    {MaxReqSz=%d}   {MaxReqDepth=%d}\n",
 					4*ioc->facts.RequestFrameSize,
 					ioc->facts.GlobalCredits);
 	len += sprintf(buf+len, "  Frames   @ 0x%p (Dma @ 0x%p)\n",
 					(void *)ioc->alloc, (void *)(ulong)ioc->alloc_dma);
 	sz = (ioc->reply_sz * ioc->reply_depth) + 128;
 	len += sprintf(buf+len, "    {CurRepSz=%d} x {CurRepDepth=%d} = %d bytes ^= 0x%x\n",
 					ioc->reply_sz, ioc->reply_depth, ioc->reply_sz*ioc->reply_depth, sz);
 	len += sprintf(buf+len, "    {MaxRepSz=%d}   {MaxRepDepth=%d}\n",
 					ioc->facts.CurReplyFrameSize,
 					ioc->facts.ReplyQueueDepth);
 	len += sprintf(buf+len, "  MaxDevices = %d\n",
 			(ioc->facts.MaxDevices==0) ? 255 : ioc->facts.MaxDevices);
 	len += sprintf(buf+len, "  MaxBuses = %d\n", ioc->facts.MaxBuses);
 	/* per-port info */
 	for (p=0; p < ioc->facts.NumberOfPorts; p++) {
 		len += sprintf(buf+len, "  PortNumber = %d (of %d)\n",
 				p+1,
 				ioc->facts.NumberOfPorts);
 		if (ioc->bus_type == FC) {
 			if (ioc->pfacts[p].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_LAN) {
 				u8 *a = (u8*)&ioc->lan_cnfg_page1.HardwareAddressLow;
 				len += sprintf(buf+len, "    LanAddr = %02X:%02X:%02X:%02X:%02X:%02X\n",
 						a[5], a[4], a[3], a[2], a[1], a[0]);
 			}
 			len += sprintf(buf+len, "    WWN = %08X%08X:%08X%08X\n",
 					ioc->fc_port_page0[p].WWNN.High,
 					ioc->fc_port_page0[p].WWNN.Low,
 					ioc->fc_port_page0[p].WWPN.High,
 					ioc->fc_port_page0[p].WWPN.Low);
 		}
 	}
 	MPT_PROC_READ_RETURN(buf,start,offset,request,eof,len);
 }
 #endif		/* CONFIG_PROC_FS } */
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 static void
 mpt_get_fw_exp_ver(char *buf, MPT_ADAPTER *ioc)
 {
 	buf[0] ='\0';
 	if ((ioc->facts.FWVersion.Word >> 24) == 0x0E) {
 		sprintf(buf, " (Exp %02d%02d)",
 			(ioc->facts.FWVersion.Word >> 16) & 0x00FF,	/* Month */
 			(ioc->facts.FWVersion.Word >> 8) & 0x1F);	/* Day */
 		/* insider hack! */
 		if ((ioc->facts.FWVersion.Word >> 8) & 0x80)
 			strcat(buf, " [MDBG]");
 	}
 }
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /**
 *	mpt_print_ioc_summary - Write ASCII summary of IOC to a buffer.
 *	@ioc: Pointer to MPT_ADAPTER structure
 *	@buffer: Pointer to buffer where IOC summary info should be written
 *	@size: Pointer to number of bytes we wrote (set by this routine)
 *	@len: Offset at which to start writing in buffer
 *	@showlan: Display LAN stuff?
 *
 *	This routine writes (english readable) ASCII text, which represents
 *	a summary of IOC information, to a buffer.
 */
 void
 mpt_print_ioc_summary(MPT_ADAPTER *ioc, char *buffer, int *size, int len, int showlan)
 {
 	char expVer[32];
 	int y;
 	mpt_get_fw_exp_ver(expVer, ioc);
 	/*
 	 *  Shorter summary of attached ioc's...
 	 */
 	y = sprintf(buffer+len, "%s: %s, %s%08xh%s, Ports=%d, MaxQ=%d",
 			ioc->name,
 			ioc->prod_name,
 			MPT_FW_REV_MAGIC_ID_STRING,	/* "FwRev=" or somesuch */
 			ioc->facts.FWVersion.Word,
 			expVer,
 			ioc->facts.NumberOfPorts,
 			ioc->req_depth);
 	if (showlan && (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_LAN)) {
 		u8 *a = (u8*)&ioc->lan_cnfg_page1.HardwareAddressLow;
 		y += sprintf(buffer+len+y, ", LanAddr=%02X:%02X:%02X:%02X:%02X:%02X",
 			a[5], a[4], a[3], a[2], a[1], a[0]);
 	}
 	y += sprintf(buffer+len+y, ", IRQ=%d", ioc->pci_irq);
 	if (!ioc->active)
 		y += sprintf(buffer+len+y, " (disabled)");
 	y += sprintf(buffer+len+y, "\n");
 	*size = y;
 }
 /**
- *	mpt_set_taskmgmt_in_progress_flag - set flags associated with task managment
+ *	mpt_set_taskmgmt_in_progress_flag - set flags associated with task management
 *	@ioc: Pointer to MPT_ADAPTER structure
 *
 *	Returns 0 for SUCCESS or -1 if FAILED.
 *
 *	If -1 is return, then it was not possible to set the flags
 **/
 int
 mpt_set_taskmgmt_in_progress_flag(MPT_ADAPTER *ioc)
 {
 	unsigned long	 flags;
 	int		 retval;
 	spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
 	if (ioc->ioc_reset_in_progress || ioc->taskmgmt_in_progress ||
 	    (ioc->alt_ioc && ioc->alt_ioc->taskmgmt_in_progress)) {
 		retval = -1;
 		goto out;
 	}
 	retval = 0;
 	ioc->taskmgmt_in_progress = 1;
 	ioc->taskmgmt_quiesce_io = 1;
 	if (ioc->alt_ioc) {
 		ioc->alt_ioc->taskmgmt_in_progress = 1;
 		ioc->alt_ioc->taskmgmt_quiesce_io = 1;
 	}
 out:
 	spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
 	return retval;
 }
 EXPORT_SYMBOL(mpt_set_taskmgmt_in_progress_flag);
 /**
- *	mpt_clear_taskmgmt_in_progress_flag - clear flags associated with task managment
+ *	mpt_clear_taskmgmt_in_progress_flag - clear flags associated with task management
 *	@ioc: Pointer to MPT_ADAPTER structure
 *
 **/
 void
 mpt_clear_taskmgmt_in_progress_flag(MPT_ADAPTER *ioc)
 {
 	unsigned long	 flags;
 	spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
 	ioc->taskmgmt_in_progress = 0;
 	ioc->taskmgmt_quiesce_io = 0;
 	if (ioc->alt_ioc) {
 		ioc->alt_ioc->taskmgmt_in_progress = 0;
 		ioc->alt_ioc->taskmgmt_quiesce_io = 0;
 	}
 	spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
 }
 EXPORT_SYMBOL(mpt_clear_taskmgmt_in_progress_flag);
 /**
 *	mpt_halt_firmware - Halts the firmware if it is operational and panic
 *	the kernel
 *	@ioc: Pointer to MPT_ADAPTER structure
 *
 **/
 void
 mpt_halt_firmware(MPT_ADAPTER *ioc)
 {
 	u32	 ioc_raw_state;
 	ioc_raw_state = mpt_GetIocState(ioc, 0);
 	if ((ioc_raw_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_FAULT) {
 		printk(MYIOC_s_ERR_FMT "IOC is in FAULT state (%04xh)!!!\n",
 			ioc->name, ioc_raw_state & MPI_DOORBELL_DATA_MASK);
 		panic("%s: IOC Fault (%04xh)!!!\n", ioc->name,
 			ioc_raw_state & MPI_DOORBELL_DATA_MASK);
 	} else {
 		CHIPREG_WRITE32(&ioc->chip->Doorbell, 0xC0FFEE00);
 		panic("%s: Firmware is halted due to command timeout\n",
 			ioc->name);
 	}
 }
 EXPORT_SYMBOL(mpt_halt_firmware);
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /*
 *	Reset Handling
 */
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /**
 *	mpt_HardResetHandler - Generic reset handler
 *	@ioc: Pointer to MPT_ADAPTER structure
 *	@sleepFlag: Indicates if sleep or schedule must be called.
 *
 *	Issues SCSI Task Management call based on input arg values.
 *	If TaskMgmt fails, returns associated SCSI request.
 *
 *	Remark: _HardResetHandler can be invoked from an interrupt thread (timer)
 *	or a non-interrupt thread.  In the former, must not call schedule().
 *
 *	Note: A return of -1 is a FATAL error case, as it means a
 *	FW reload/initialization failed.
 *
 *	Returns 0 for SUCCESS or -1 if FAILED.
 */
 int
 mpt_HardResetHandler(MPT_ADAPTER *ioc, int sleepFlag)
 {
 	int	 rc;
 	u8	 cb_idx;
 	unsigned long	 flags;
 	unsigned long	 time_count;
 	dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT "HardResetHandler Entered!\n", ioc->name));
 #ifdef MFCNT
 	printk(MYIOC_s_INFO_FMT "HardResetHandler Entered!\n", ioc->name);
 	printk("MF count 0x%x !\n", ioc->mfcnt);
 #endif
 	if (mpt_fwfault_debug)
 		mpt_halt_firmware(ioc);
 	/* Reset the adapter. Prevent more than 1 call to
 	 * mpt_do_ioc_recovery at any instant in time.
 	 */
 	spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
 	if (ioc->ioc_reset_in_progress) {
 		spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
 		return 0;
 	}
 	ioc->ioc_reset_in_progress = 1;
 	if (ioc->alt_ioc)
 		ioc->alt_ioc->ioc_reset_in_progress = 1;
 	spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
 	/* The SCSI driver needs to adjust timeouts on all current
 	 * commands prior to the diagnostic reset being issued.
 	 * Prevents timeouts occurring during a diagnostic reset...very bad.
 	 * For all other protocol drivers, this is a no-op.
 	 */
 	for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
 		if (MptResetHandlers[cb_idx]) {
 			mpt_signal_reset(cb_idx, ioc, MPT_IOC_SETUP_RESET);
 			if (ioc->alt_ioc)
 				mpt_signal_reset(cb_idx, ioc->alt_ioc,
 					MPT_IOC_SETUP_RESET);
 		}
 	}
 	time_count = jiffies;
 	rc = mpt_do_ioc_recovery(ioc, MPT_HOSTEVENT_IOC_RECOVER, sleepFlag);
 	if (rc != 0) {
 		printk(KERN_WARNING MYNAM
 		    ": WARNING - (%d) Cannot recover %s\n", rc, ioc->name);
 	} else {
 		if (ioc->hard_resets < -1)
 			ioc->hard_resets++;
 	}
 	spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
 	ioc->ioc_reset_in_progress = 0;
 	ioc->taskmgmt_quiesce_io = 0;
 	ioc->taskmgmt_in_progress = 0;
 	if (ioc->alt_ioc) {
 		ioc->alt_ioc->ioc_reset_in_progress = 0;
 		ioc->alt_ioc->taskmgmt_quiesce_io = 0;
 		ioc->alt_ioc->taskmgmt_in_progress = 0;
 	}
 	spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
 	for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
 		if (MptResetHandlers[cb_idx]) {
 			mpt_signal_reset(cb_idx, ioc, MPT_IOC_POST_RESET);
 			if (ioc->alt_ioc)
 				mpt_signal_reset(cb_idx,
 					ioc->alt_ioc, MPT_IOC_POST_RESET);
 		}
 	}
 	dtmprintk(ioc,
 	    printk(MYIOC_s_DEBUG_FMT
 		"HardResetHandler: completed (%d seconds): %s\n", ioc->name,
 		jiffies_to_msecs(jiffies - time_count)/1000, ((rc == 0) ?
 		"SUCCESS" : "FAILED")));
 	return rc;
 }
 #ifdef CONFIG_FUSION_LOGGING
 static void
 mpt_display_event_info(MPT_ADAPTER *ioc, EventNotificationReply_t *pEventReply)
 {
 	char *ds = NULL;
 	u32 evData0;
 	int ii;
 	u8 event;
 	char *evStr = ioc->evStr;
 	event = le32_to_cpu(pEventReply->Event) & 0xFF;
 	evData0 = le32_to_cpu(pEventReply->Data[0]);
 	switch(event) {
 	case MPI_EVENT_NONE:
 		ds = "None";
 		break;
 	case MPI_EVENT_LOG_DATA:
 		ds = "Log Data";
 		break;
 	case MPI_EVENT_STATE_CHANGE:
 		ds = "State Change";
 		break;
 	case MPI_EVENT_UNIT_ATTENTION:
 		ds = "Unit Attention";
 		break;
 	case MPI_EVENT_IOC_BUS_RESET:
 		ds = "IOC Bus Reset";
 		break;
 	case MPI_EVENT_EXT_BUS_RESET:
 		ds = "External Bus Reset";
 		break;
 	case MPI_EVENT_RESCAN:
 		ds = "Bus Rescan Event";
 		break;
 	case MPI_EVENT_LINK_STATUS_CHANGE:
 		if (evData0 == MPI_EVENT_LINK_STATUS_FAILURE)
 			ds = "Link Status(FAILURE) Change";
 		else
 			ds = "Link Status(ACTIVE) Change";
 		break;
 	case MPI_EVENT_LOOP_STATE_CHANGE:
 		if (evData0 == MPI_EVENT_LOOP_STATE_CHANGE_LIP)
 			ds = "Loop State(LIP) Change";
 		else if (evData0 == MPI_EVENT_LOOP_STATE_CHANGE_LPE)
 			ds = "Loop State(LPE) Change";
 		else
 			ds = "Loop State(LPB) Change";
 		break;
 	case MPI_EVENT_LOGOUT:
 		ds = "Logout";
 		break;
 	case MPI_EVENT_EVENT_CHANGE:
 		if (evData0)
 			ds = "Events ON";
 		else
 			ds = "Events OFF";
 		break;
 	case MPI_EVENT_INTEGRATED_RAID:
 	{
 		u8 ReasonCode = (u8)(evData0 >> 16);
 		switch (ReasonCode) {
 		case MPI_EVENT_RAID_RC_VOLUME_CREATED :
 			ds = "Integrated Raid: Volume Created";
 			break;
 		case MPI_EVENT_RAID_RC_VOLUME_DELETED :
 			ds = "Integrated Raid: Volume Deleted";
 			break;
 		case MPI_EVENT_RAID_RC_VOLUME_SETTINGS_CHANGED :
 			ds = "Integrated Raid: Volume Settings Changed";
 			break;
 		case MPI_EVENT_RAID_RC_VOLUME_STATUS_CHANGED :
 			ds = "Integrated Raid: Volume Status Changed";
 			break;
 		case MPI_EVENT_RAID_RC_VOLUME_PHYSDISK_CHANGED :
 			ds = "Integrated Raid: Volume Physdisk Changed";
 			break;
 		case MPI_EVENT_RAID_RC_PHYSDISK_CREATED :
 			ds = "Integrated Raid: Physdisk Created";
 			break;
 		case MPI_EVENT_RAID_RC_PHYSDISK_DELETED :
 			ds = "Integrated Raid: Physdisk Deleted";
 			break;
 		case MPI_EVENT_RAID_RC_PHYSDISK_SETTINGS_CHANGED :
 			ds = "Integrated Raid: Physdisk Settings Changed";
 			break;
 		case MPI_EVENT_RAID_RC_PHYSDISK_STATUS_CHANGED :
 			ds = "Integrated Raid: Physdisk Status Changed";
 			break;
 		case MPI_EVENT_RAID_RC_DOMAIN_VAL_NEEDED :
 			ds = "Integrated Raid: Domain Validation Needed";
 			break;
 		case MPI_EVENT_RAID_RC_SMART_DATA :
 			ds = "Integrated Raid; Smart Data";
 			break;
 		case MPI_EVENT_RAID_RC_REPLACE_ACTION_STARTED :
 			ds = "Integrated Raid: Replace Action Started";
 			break;
 		default:
 			ds = "Integrated Raid";
 		break;
 		}
 		break;
 	}
 	case MPI_EVENT_SCSI_DEVICE_STATUS_CHANGE:
 		ds = "SCSI Device Status Change";
 		break;
 	case MPI_EVENT_SAS_DEVICE_STATUS_CHANGE:
 	{
 		u8 id = (u8)(evData0);
 		u8 channel = (u8)(evData0 >> 8);
 		u8 ReasonCode = (u8)(evData0 >> 16);
 		switch (ReasonCode) {
 		case MPI_EVENT_SAS_DEV_STAT_RC_ADDED:
 			snprintf(evStr, EVENT_DESCR_STR_SZ,
 			    "SAS Device Status Change: Added: "
 			    "id=%d channel=%d", id, channel);
 			break;
 		case MPI_EVENT_SAS_DEV_STAT_RC_NOT_RESPONDING:
 			snprintf(evStr, EVENT_DESCR_STR_SZ,
 			    "SAS Device Status Change: Deleted: "
 			    "id=%d channel=%d", id, channel);
 			break;
 		case MPI_EVENT_SAS_DEV_STAT_RC_SMART_DATA:
 			snprintf(evStr, EVENT_DESCR_STR_SZ,
 			    "SAS Device Status Change: SMART Data: "
 			    "id=%d channel=%d", id, channel);
 			break;
 		case MPI_EVENT_SAS_DEV_STAT_RC_NO_PERSIST_ADDED:
 			snprintf(evStr, EVENT_DESCR_STR_SZ,
 			    "SAS Device Status Change: No Persistancy: "
 			    "id=%d channel=%d", id, channel);
 			break;
 		case MPI_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED:
 			snprintf(evStr, EVENT_DESCR_STR_SZ,
 			    "SAS Device Status Change: Unsupported Device "
 			    "Discovered : id=%d channel=%d", id, channel);
 			break;
 		case MPI_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET:
 			snprintf(evStr, EVENT_DESCR_STR_SZ,
 			    "SAS Device Status Change: Internal Device "
 			    "Reset : id=%d channel=%d", id, channel);
 			break;
 		case MPI_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL:
 			snprintf(evStr, EVENT_DESCR_STR_SZ,
 			    "SAS Device Status Change: Internal Task "
 			    "Abort : id=%d channel=%d", id, channel);
 			break;
 		case MPI_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL:
 			snprintf(evStr, EVENT_DESCR_STR_SZ,
 			    "SAS Device Status Change: Internal Abort "
 			    "Task Set : id=%d channel=%d", id, channel);
 			break;
 		case MPI_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL:
 			snprintf(evStr, EVENT_DESCR_STR_SZ,
 			    "SAS Device Status Change: Internal Clear "
 			    "Task Set : id=%d channel=%d", id, channel);
 			break;
 		case MPI_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL:
 			snprintf(evStr, EVENT_DESCR_STR_SZ,
 			    "SAS Device Status Change: Internal Query "
 			    "Task : id=%d channel=%d", id, channel);
 			break;
 		default:
 			snprintf(evStr, EVENT_DESCR_STR_SZ,
 			    "SAS Device Status Change: Unknown: "
 			    "id=%d channel=%d", id, channel);
 			break;
 		}
 		break;
 	}
 	case MPI_EVENT_ON_BUS_TIMER_EXPIRED:
 		ds = "Bus Timer Expired";
 		break;
 	case MPI_EVENT_QUEUE_FULL:
 	{
 		u16 curr_depth = (u16)(evData0 >> 16);
 		u8 channel = (u8)(evData0 >> 8);
 		u8 id = (u8)(evData0);
 		snprintf(evStr, EVENT_DESCR_STR_SZ,
 		   "Queue Full: channel=%d id=%d depth=%d",
 		   channel, id, curr_depth);
 		break;
 	}
 	case MPI_EVENT_SAS_SES:
 		ds = "SAS SES Event";
 		break;
 	case MPI_EVENT_PERSISTENT_TABLE_FULL:
 		ds = "Persistent Table Full";
 		break;
 	case MPI_EVENT_SAS_PHY_LINK_STATUS:
 	{
 		u8 LinkRates = (u8)(evData0 >> 8);
 		u8 PhyNumber = (u8)(evData0);
 		LinkRates = (LinkRates & MPI_EVENT_SAS_PLS_LR_CURRENT_MASK) >>
 			MPI_EVENT_SAS_PLS_LR_CURRENT_SHIFT;
 		switch (LinkRates) {
 		case MPI_EVENT_SAS_PLS_LR_RATE_UNKNOWN:
 			snprintf(evStr, EVENT_DESCR_STR_SZ,
 			   "SAS PHY Link Status: Phy=%d:"
 			   " Rate Unknown",PhyNumber);
 			break;
 		case MPI_EVENT_SAS_PLS_LR_RATE_PHY_DISABLED:
 			snprintf(evStr, EVENT_DESCR_STR_SZ,
 			   "SAS PHY Link Status: Phy=%d:"
 			   " Phy Disabled",PhyNumber);
 			break;
 		case MPI_EVENT_SAS_PLS_LR_RATE_FAILED_SPEED_NEGOTIATION:
 			snprintf(evStr, EVENT_DESCR_STR_SZ,
 			   "SAS PHY Link Status: Phy=%d:"
 			   " Failed Speed Nego",PhyNumber);
 			break;
 		case MPI_EVENT_SAS_PLS_LR_RATE_SATA_OOB_COMPLETE:
 			snprintf(evStr, EVENT_DESCR_STR_SZ,
 			   "SAS PHY Link Status: Phy=%d:"
 			   " Sata OOB Completed",PhyNumber);
 			break;
 		case MPI_EVENT_SAS_PLS_LR_RATE_1_5:
 			snprintf(evStr, EVENT_DESCR_STR_SZ,
 			   "SAS PHY Link Status: Phy=%d:"
 			   " Rate 1.5 Gbps",PhyNumber);
 			break;
 		case MPI_EVENT_SAS_PLS_LR_RATE_3_0:
 			snprintf(evStr, EVENT_DESCR_STR_SZ,
 			   "SAS PHY Link Status: Phy=%d:"
 			   " Rate 3.0 Gpbs",PhyNumber);
 			break;
 		default:
 			snprintf(evStr, EVENT_DESCR_STR_SZ,
 			   "SAS PHY Link Status: Phy=%d", PhyNumber);
 			break;
 		}
 		break;
 	}
 	case MPI_EVENT_SAS_DISCOVERY_ERROR:
 		ds = "SAS Discovery Error";
 		break;
 	case MPI_EVENT_IR_RESYNC_UPDATE:
 	{
 		u8 resync_complete = (u8)(evData0 >> 16);
 		snprintf(evStr, EVENT_DESCR_STR_SZ,
 		    "IR Resync Update: Complete = %d:",resync_complete);
 		break;
 	}
 	case MPI_EVENT_IR2:
 	{
 		u8 id = (u8)(evData0);
 		u8 channel = (u8)(evData0 >> 8);
 		u8 phys_num = (u8)(evData0 >> 24);
 		u8 ReasonCode = (u8)(evData0 >> 16);
 		switch (ReasonCode) {
 		case MPI_EVENT_IR2_RC_LD_STATE_CHANGED:
 			snprintf(evStr, EVENT_DESCR_STR_SZ,
 			    "IR2: LD State Changed: "
 			    "id=%d channel=%d phys_num=%d",
 			    id, channel, phys_num);
 			break;
 		case MPI_EVENT_IR2_RC_PD_STATE_CHANGED:
 			snprintf(evStr, EVENT_DESCR_STR_SZ,
 			    "IR2: PD State Changed "
 			    "id=%d channel=%d phys_num=%d",
 			    id, channel, phys_num);
 			break;
 		case MPI_EVENT_IR2_RC_BAD_BLOCK_TABLE_FULL:
 			snprintf(evStr, EVENT_DESCR_STR_SZ,
 			    "IR2: Bad Block Table Full: "
 			    "id=%d channel=%d phys_num=%d",
 			    id, channel, phys_num);
 			break;
 		case MPI_EVENT_IR2_RC_PD_INSERTED:
 			snprintf(evStr, EVENT_DESCR_STR_SZ,
 			    "IR2: PD Inserted: "
 			    "id=%d channel=%d phys_num=%d",
 			    id, channel, phys_num);
 			break;
 		case MPI_EVENT_IR2_RC_PD_REMOVED:
 			snprintf(evStr, EVENT_DESCR_STR_SZ,
 			    "IR2: PD Removed: "
 			    "id=%d channel=%d phys_num=%d",
 			    id, channel, phys_num);
 			break;
 		case MPI_EVENT_IR2_RC_FOREIGN_CFG_DETECTED:
 			snprintf(evStr, EVENT_DESCR_STR_SZ,
 			    "IR2: Foreign CFG Detected: "
 			    "id=%d channel=%d phys_num=%d",
 			    id, channel, phys_num);
 			break;
 		case MPI_EVENT_IR2_RC_REBUILD_MEDIUM_ERROR:
 			snprintf(evStr, EVENT_DESCR_STR_SZ,
 			    "IR2: Rebuild Medium Error: "
 			    "id=%d channel=%d phys_num=%d",
 			    id, channel, phys_num);
 			break;
 		case MPI_EVENT_IR2_RC_DUAL_PORT_ADDED:
 			snprintf(evStr, EVENT_DESCR_STR_SZ,
 			    "IR2: Dual Port Added: "
 			    "id=%d channel=%d phys_num=%d",
 			    id, channel, phys_num);
 			break;
 		case MPI_EVENT_IR2_RC_DUAL_PORT_REMOVED:
 			snprintf(evStr, EVENT_DESCR_STR_SZ,
 			    "IR2: Dual Port Removed: "
 			    "id=%d channel=%d phys_num=%d",
 			    id, channel, phys_num);
 			break;
 		default:
 			ds = "IR2";
 		break;
 		}
 		break;
 	}
 	case MPI_EVENT_SAS_DISCOVERY:
 	{
 		if (evData0)
 			ds = "SAS Discovery: Start";
 		else
 			ds = "SAS Discovery: Stop";
 		break;
 	}
 	case MPI_EVENT_LOG_ENTRY_ADDED:
 		ds = "SAS Log Entry Added";
 		break;
 	case MPI_EVENT_SAS_BROADCAST_PRIMITIVE:
 	{
 		u8 phy_num = (u8)(evData0);
 		u8 port_num = (u8)(evData0 >> 8);
 		u8 port_width = (u8)(evData0 >> 16);
 		u8 primative = (u8)(evData0 >> 24);
 		snprintf(evStr, EVENT_DESCR_STR_SZ,
 		    "SAS Broadcase Primative: phy=%d port=%d "
 		    "width=%d primative=0x%02x",
 		    phy_num, port_num, port_width, primative);
 		break;
 	}
 	case MPI_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE:
 	{
 		u8 reason = (u8)(evData0);
 		switch (reason) {
 		case MPI_EVENT_SAS_INIT_RC_ADDED:
 			ds = "SAS Initiator Status Change: Added";
 			break;
 		case MPI_EVENT_SAS_INIT_RC_REMOVED:
 			ds = "SAS Initiator Status Change: Deleted";
 			break;
 		default:
 			ds = "SAS Initiator Status Change";
 			break;
 		}
 		break;
 	}
 	case MPI_EVENT_SAS_INIT_TABLE_OVERFLOW:
 	{
 		u8 max_init = (u8)(evData0);
 		u8 current_init = (u8)(evData0 >> 8);
 		snprintf(evStr, EVENT_DESCR_STR_SZ,
 		    "SAS Initiator Device Table Overflow: max initiators=%02d "
 		    "current initators=%02d",
 		    max_init, current_init);
 		break;
 	}
 	case MPI_EVENT_SAS_SMP_ERROR:
 	{
 		u8 status = (u8)(evData0);
 		u8 port_num = (u8)(evData0 >> 8);
 		u8 result = (u8)(evData0 >> 16);
 		if (status == MPI_EVENT_SAS_SMP_FUNCTION_RESULT_VALID)
 			snprintf(evStr, EVENT_DESCR_STR_SZ,
 			    "SAS SMP Error: port=%d result=0x%02x",
 			    port_num, result);
 		else if (status == MPI_EVENT_SAS_SMP_CRC_ERROR)
 			snprintf(evStr, EVENT_DESCR_STR_SZ,
 			    "SAS SMP Error: port=%d : CRC Error",
 			    port_num);
 		else if (status == MPI_EVENT_SAS_SMP_TIMEOUT)
 			snprintf(evStr, EVENT_DESCR_STR_SZ,
 			    "SAS SMP Error: port=%d : Timeout",
 			    port_num);
 		else if (status == MPI_EVENT_SAS_SMP_NO_DESTINATION)
 			snprintf(evStr, EVENT_DESCR_STR_SZ,
 			    "SAS SMP Error: port=%d : No Destination",
 			    port_num);
 		else if (status == MPI_EVENT_SAS_SMP_BAD_DESTINATION)
 			snprintf(evStr, EVENT_DESCR_STR_SZ,
 			    "SAS SMP Error: port=%d : Bad Destination",
 			    port_num);
 		else
 			snprintf(evStr, EVENT_DESCR_STR_SZ,
 			    "SAS SMP Error: port=%d : status=0x%02x",
 			    port_num, status);
 		break;
 	}
 	case MPI_EVENT_SAS_EXPANDER_STATUS_CHANGE:
 	{
 		u8 reason = (u8)(evData0);
 		switch (reason) {
 		case MPI_EVENT_SAS_EXP_RC_ADDED:
 			ds = "Expander Status Change: Added";
 			break;
 		case MPI_EVENT_SAS_EXP_RC_NOT_RESPONDING:
 			ds = "Expander Status Change: Deleted";
 			break;
 		default:
 			ds = "Expander Status Change";
 			break;
 		}
 		break;
 	}
 	/*
 	 *  MPT base "custom" events may be added here...
 	 */
 	default:
 		ds = "Unknown";
 		break;
 	}
 	if (ds)
 		strncpy(evStr, ds, EVENT_DESCR_STR_SZ);
 	devtprintk(ioc, printk(MYIOC_s_DEBUG_FMT
 	    "MPT event:(%02Xh) : %s\n",
 	    ioc->name, event, evStr));
 	devtverboseprintk(ioc, printk(KERN_DEBUG MYNAM
 	    ": Event data:\n"));
 	for (ii = 0; ii < le16_to_cpu(pEventReply->EventDataLength); ii++)
 		devtverboseprintk(ioc, printk(" %08x",
 		    le32_to_cpu(pEventReply->Data[ii])));
 	devtverboseprintk(ioc, printk(KERN_DEBUG "\n"));
 }
 #endif
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /**
 *	ProcessEventNotification - Route EventNotificationReply to all event handlers
 *	@ioc: Pointer to MPT_ADAPTER structure
 *	@pEventReply: Pointer to EventNotification reply frame
 *	@evHandlers: Pointer to integer, number of event handlers
 *
 *	Routes a received EventNotificationReply to all currently registered
 *	event handlers.
 *	Returns sum of event handlers return values.
 */
 static int
 ProcessEventNotification(MPT_ADAPTER *ioc, EventNotificationReply_t *pEventReply, int *evHandlers)
 {
 	u16 evDataLen;
 	u32 evData0 = 0;
 	int ii;
 	u8 cb_idx;
 	int r = 0;
 	int handlers = 0;
 	u8 event;
 	/*
 	 *  Do platform normalization of values
 	 */
 	event = le32_to_cpu(pEventReply->Event) & 0xFF;
 	evDataLen = le16_to_cpu(pEventReply->EventDataLength);
 	if (evDataLen) {
 		evData0 = le32_to_cpu(pEventReply->Data[0]);
 	}
 #ifdef CONFIG_FUSION_LOGGING
 	if (evDataLen)
 		mpt_display_event_info(ioc, pEventReply);
 #endif
 	/*
 	 *  Do general / base driver event processing
 	 */
 	switch(event) {
 	case MPI_EVENT_EVENT_CHANGE:		/* 0A */
 		if (evDataLen) {
 			u8 evState = evData0 & 0xFF;
 			/* CHECKME! What if evState unexpectedly says OFF (0)? */
 			/* Update EventState field in cached IocFacts */
 			if (ioc->facts.Function) {
 				ioc->facts.EventState = evState;
 			}
 		}
 		break;
 	case MPI_EVENT_INTEGRATED_RAID:
 		mptbase_raid_process_event_data(ioc,
 		    (MpiEventDataRaid_t *)pEventReply->Data);
 		break;
 	default:
 		break;
 	}
 	/*
 	 * Should this event be logged? Events are written sequentially.
 	 * When buffer is full, start again at the top.
 	 */
 	if (ioc->events && (ioc->eventTypes & ( 1 << event))) {
 		int idx;
 		idx = ioc->eventContext % MPTCTL_EVENT_LOG_SIZE;
 		ioc->events[idx].event = event;
 		ioc->events[idx].eventContext = ioc->eventContext;
 		for (ii = 0; ii < 2; ii++) {
 			if (ii < evDataLen)
 				ioc->events[idx].data[ii] = le32_to_cpu(pEventReply->Data[ii]);
 			else
 				ioc->events[idx].data[ii] =  0;
 		}
 		ioc->eventContext++;
 	}
 	/*
 	 *  Call each currently registered protocol event handler.
 	 */
 	for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
 		if (MptEvHandlers[cb_idx]) {
 			devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT
 			    "Routing Event to event handler #%d\n",
 			    ioc->name, cb_idx));
 			r += (*(MptEvHandlers[cb_idx]))(ioc, pEventReply);
 			handlers++;
 		}
 	}
 	/* FIXME?  Examine results here? */
 	/*
 	 *  If needed, send (a single) EventAck.
 	 */
 	if (pEventReply->AckRequired == MPI_EVENT_NOTIFICATION_ACK_REQUIRED) {
 		devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT
 			"EventAck required\n",ioc->name));
 		if ((ii = SendEventAck(ioc, pEventReply)) != 0) {
 			devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT "SendEventAck returned %d\n",
 					ioc->name, ii));
 		}
 	}
 	*evHandlers = handlers;
 	return r;
 }
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /**
 *	mpt_fc_log_info - Log information returned from Fibre Channel IOC.
 *	@ioc: Pointer to MPT_ADAPTER structure
 *	@log_info: U32 LogInfo reply word from the IOC
 *
 *	Refer to lsi/mpi_log_fc.h.
 */
 static void
 mpt_fc_log_info(MPT_ADAPTER *ioc, u32 log_info)
 {
 	char *desc = "unknown";
 	switch (log_info & 0xFF000000) {
 	case MPI_IOCLOGINFO_FC_INIT_BASE:
 		desc = "FCP Initiator";
 		break;
 	case MPI_IOCLOGINFO_FC_TARGET_BASE:
 		desc = "FCP Target";
 		break;
 	case MPI_IOCLOGINFO_FC_LAN_BASE:
 		desc = "LAN";
 		break;
 	case MPI_IOCLOGINFO_FC_MSG_BASE:
 		desc = "MPI Message Layer";
 		break;
 	case MPI_IOCLOGINFO_FC_LINK_BASE:
 		desc = "FC Link";
 		break;
 	case MPI_IOCLOGINFO_FC_CTX_BASE:
 		desc = "Context Manager";
 		break;
 	case MPI_IOCLOGINFO_FC_INVALID_FIELD_BYTE_OFFSET:
 		desc = "Invalid Field Offset";
 		break;
 	case MPI_IOCLOGINFO_FC_STATE_CHANGE:
 		desc = "State Change Info";
 		break;
 	}
 	printk(MYIOC_s_INFO_FMT "LogInfo(0x%08x): SubClass={%s}, Value=(0x%06x)\n",
 			ioc->name, log_info, desc, (log_info & 0xFFFFFF));
 }
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /**
 *	mpt_spi_log_info - Log information returned from SCSI Parallel IOC.
 *	@ioc: Pointer to MPT_ADAPTER structure
 *	@log_info: U32 LogInfo word from the IOC
 *
 *	Refer to lsi/sp_log.h.
 */
 static void
 mpt_spi_log_info(MPT_ADAPTER *ioc, u32 log_info)
 {
 	u32 info = log_info & 0x00FF0000;
 	char *desc = "unknown";
 	switch (info) {
 	case 0x00010000:
 		desc = "bug! MID not found";
 		break;
 	case 0x00020000:
 		desc = "Parity Error";
 		break;
 	case 0x00030000:
 		desc = "ASYNC Outbound Overrun";
 		break;
 	case 0x00040000:
 		desc = "SYNC Offset Error";
 		break;
 	case 0x00050000:
 		desc = "BM Change";
 		break;
 	case 0x00060000:
 		desc = "Msg In Overflow";
 		break;
 	case 0x00070000:
 		desc = "DMA Error";
 		break;
 	case 0x00080000:
 		desc = "Outbound DMA Overrun";
 		break;
 	case 0x00090000:
 		desc = "Task Management";
 		break;
 	case 0x000A0000:
 		desc = "Device Problem";
 		break;
 	case 0x000B0000:
 		desc = "Invalid Phase Change";
 		break;
 	case 0x000C0000:
 		desc = "Untagged Table Size";
 		break;
 	}
 	printk(MYIOC_s_INFO_FMT "LogInfo(0x%08x): F/W: %s\n", ioc->name, log_info, desc);
 }
 /* strings for sas loginfo */
 	static char *originator_str[] = {
 		"IOP",						/* 00h */
 		"PL",						/* 01h */
 		"IR"						/* 02h */
 	};
 	static char *iop_code_str[] = {
 		NULL,						/* 00h */
 		"Invalid SAS Address",				/* 01h */
 		NULL,						/* 02h */
 		"Invalid Page",					/* 03h */
 		"Diag Message Error",				/* 04h */
 		"Task Terminated",				/* 05h */
 		"Enclosure Management",				/* 06h */
 		"Target Mode"					/* 07h */
 	};
 	static char *pl_code_str[] = {
 		NULL,						/* 00h */
 		"Open Failure",					/* 01h */
 		"Invalid Scatter Gather List",			/* 02h */
 		"Wrong Relative Offset or Frame Length",	/* 03h */
 		"Frame Transfer Error",				/* 04h */
 		"Transmit Frame Connected Low",			/* 05h */
 		"SATA Non-NCQ RW Error Bit Set",		/* 06h */
 		"SATA Read Log Receive Data Error",		/* 07h */
 		"SATA NCQ Fail All Commands After Error",	/* 08h */
 		"SATA Error in Receive Set Device Bit FIS",	/* 09h */
 		"Receive Frame Invalid Message",		/* 0Ah */
 		"Receive Context Message Valid Error",		/* 0Bh */
 		"Receive Frame Current Frame Error",		/* 0Ch */
 		"SATA Link Down",				/* 0Dh */
 		"Discovery SATA Init W IOS",			/* 0Eh */
 		"Config Invalid Page",				/* 0Fh */
 		"Discovery SATA Init Timeout",			/* 10h */
 		"Reset",					/* 11h */
 		"Abort",					/* 12h */
 		"IO Not Yet Executed",				/* 13h */
 		"IO Executed",					/* 14h */
 		"Persistent Reservation Out Not Affiliation "
 		    "Owner", 					/* 15h */
 		"Open Transmit DMA Abort",			/* 16h */
 		"IO Device Missing Delay Retry",		/* 17h */
 		"IO Cancelled Due to Recieve Error",		/* 18h */
 		NULL,						/* 19h */
 		NULL,						/* 1Ah */
 		NULL,						/* 1Bh */
 		NULL,						/* 1Ch */
 		NULL,						/* 1Dh */
 		NULL,						/* 1Eh */
 		NULL,						/* 1Fh */
 		"Enclosure Management"				/* 20h */
 	};
 	static char *ir_code_str[] = {
 		"Raid Action Error",				/* 00h */
 		NULL,						/* 00h */
 		NULL,						/* 01h */
 		NULL,						/* 02h */
 		NULL,						/* 03h */
 		NULL,						/* 04h */
 		NULL,						/* 05h */
 		NULL,						/* 06h */
 		NULL						/* 07h */
 	};
 	static char *raid_sub_code_str[] = {
 		NULL, 						/* 00h */
 		"Volume Creation Failed: Data Passed too "
 		    "Large", 					/* 01h */
 		"Volume Creation Failed: Duplicate Volumes "
 		    "Attempted", 				/* 02h */
 		"Volume Creation Failed: Max Number "
 		    "Supported Volumes Exceeded",		/* 03h */
 		"Volume Creation Failed: DMA Error",		/* 04h */
 		"Volume Creation Failed: Invalid Volume Type",	/* 05h */
 		"Volume Creation Failed: Error Reading "
 		    "MFG Page 4", 				/* 06h */
 		"Volume Creation Failed: Creating Internal "
 		    "Structures", 				/* 07h */
 		NULL,						/* 08h */
 		NULL,						/* 09h */
 		NULL,						/* 0Ah */
 		NULL,						/* 0Bh */
 		NULL,						/* 0Ch */
 		NULL,						/* 0Dh */
 		NULL,						/* 0Eh */
 		NULL,						/* 0Fh */
 		"Activation failed: Already Active Volume", 	/* 10h */
 		"Activation failed: Unsupported Volume Type", 	/* 11h */
 		"Activation failed: Too Many Active Volumes", 	/* 12h */
 		"Activation failed: Volume ID in Use", 		/* 13h */
 		"Activation failed: Reported Failure", 		/* 14h */
 		"Activation failed: Importing a Volume", 	/* 15h */
 		NULL,						/* 16h */
 		NULL,						/* 17h */
 		NULL,						/* 18h */
 		NULL,						/* 19h */
 		NULL,						/* 1Ah */
 		NULL,						/* 1Bh */
 		NULL,						/* 1Ch */
 		NULL,						/* 1Dh */
 		NULL,						/* 1Eh */
 		NULL,						/* 1Fh */
 		"Phys Disk failed: Too Many Phys Disks", 	/* 20h */
 		"Phys Disk failed: Data Passed too Large",	/* 21h */
 		"Phys Disk failed: DMA Error", 			/* 22h */
 		"Phys Disk failed: Invalid <channel:id>", 	/* 23h */
 		"Phys Disk failed: Creating Phys Disk Config "
 		    "Page", 					/* 24h */
 		NULL,						/* 25h */
 		NULL,						/* 26h */
 		NULL,						/* 27h */
 		NULL,						/* 28h */
 		NULL,						/* 29h */
 		NULL,						/* 2Ah */
 		NULL,						/* 2Bh */
 		NULL,						/* 2Ch */
 		NULL,						/* 2Dh */
 		NULL,						/* 2Eh */
 		NULL,						/* 2Fh */
 		"Compatibility Error: IR Disabled",		/* 30h */
 		"Compatibility Error: Inquiry Comand Failed",	/* 31h */
 		"Compatibility Error: Device not Direct Access "
 		    "Device ",					/* 32h */
 		"Compatibility Error: Removable Device Found",	/* 33h */
 		"Compatibility Error: Device SCSI Version not "
 		    "2 or Higher", 				/* 34h */
 		"Compatibility Error: SATA Device, 48 BIT LBA "
 		    "not Supported", 				/* 35h */
 		"Compatibility Error: Device doesn't have "
 		    "512 Byte Block Sizes", 			/* 36h */
 		"Compatibility Error: Volume Type Check Failed", /* 37h */
 		"Compatibility Error: Volume Type is "
 		    "Unsupported by FW", 			/* 38h */
 		"Compatibility Error: Disk Drive too Small for "
 		    "use in Volume", 				/* 39h */
 		"Compatibility Error: Phys Disk for Create "
 		    "Volume not Found", 			/* 3Ah */
 		"Compatibility Error: Too Many or too Few "
 		    "Disks for Volume Type", 			/* 3Bh */
 		"Compatibility Error: Disk stripe Sizes "
 		    "Must be 64KB", 				/* 3Ch */
 		"Compatibility Error: IME Size Limited to < 2TB", /* 3Dh */
 	};
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /**
 *	mpt_sas_log_info - Log information returned from SAS IOC.
 *	@ioc: Pointer to MPT_ADAPTER structure
 *	@log_info: U32 LogInfo reply word from the IOC
 *
 *	Refer to lsi/mpi_log_sas.h.
 **/
 static void
 mpt_sas_log_info(MPT_ADAPTER *ioc, u32 log_info)
 {
 union loginfo_type {
 	u32	loginfo;
 	struct {
 		u32	subcode:16;
 		u32	code:8;
 		u32	originator:4;
 		u32	bus_type:4;
 	}dw;
 };
 	union loginfo_type sas_loginfo;
 	char *originator_desc = NULL;
 	char *code_desc = NULL;
 	char *sub_code_desc = NULL;
 	sas_loginfo.loginfo = log_info;
 	if ((sas_loginfo.dw.bus_type != 3 /*SAS*/) &&
 	    (sas_loginfo.dw.originator < ARRAY_SIZE(originator_str)))
 		return;
 	originator_desc = originator_str[sas_loginfo.dw.originator];
 	switch (sas_loginfo.dw.originator) {
 		case 0:  /* IOP */
 			if (sas_loginfo.dw.code <
 			    ARRAY_SIZE(iop_code_str))
 				code_desc = iop_code_str[sas_loginfo.dw.code];
 			break;
 		case 1:  /* PL */
 			if (sas_loginfo.dw.code <
 			    ARRAY_SIZE(pl_code_str))
 				code_desc = pl_code_str[sas_loginfo.dw.code];
 			break;
 		case 2:  /* IR */
 			if (sas_loginfo.dw.code >=
 			    ARRAY_SIZE(ir_code_str))
 				break;
 			code_desc = ir_code_str[sas_loginfo.dw.code];
 			if (sas_loginfo.dw.subcode >=
 			    ARRAY_SIZE(raid_sub_code_str))
 			break;
 			if (sas_loginfo.dw.code == 0)
 				sub_code_desc =
 				    raid_sub_code_str[sas_loginfo.dw.subcode];
 			break;
 		default:
 			return;
 	}
 	if (sub_code_desc != NULL)
 		printk(MYIOC_s_INFO_FMT
 			"LogInfo(0x%08x): Originator={%s}, Code={%s},"
 			" SubCode={%s}\n",
 			ioc->name, log_info, originator_desc, code_desc,
 			sub_code_desc);
 	else if (code_desc != NULL)
 		printk(MYIOC_s_INFO_FMT
 			"LogInfo(0x%08x): Originator={%s}, Code={%s},"
 			" SubCode(0x%04x)\n",
 			ioc->name, log_info, originator_desc, code_desc,
 			sas_loginfo.dw.subcode);
 	else
 		printk(MYIOC_s_INFO_FMT
 			"LogInfo(0x%08x): Originator={%s}, Code=(0x%02x),"
 			" SubCode(0x%04x)\n",
 			ioc->name, log_info, originator_desc,
 			sas_loginfo.dw.code, sas_loginfo.dw.subcode);
 }
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /**
 *	mpt_iocstatus_info_config - IOCSTATUS information for config pages
 *	@ioc: Pointer to MPT_ADAPTER structure
 *	@ioc_status: U32 IOCStatus word from IOC
 *	@mf: Pointer to MPT request frame
 *
 *	Refer to lsi/mpi.h.
 **/
 static void
 mpt_iocstatus_info_config(MPT_ADAPTER *ioc, u32 ioc_status, MPT_FRAME_HDR *mf)
 {
 	Config_t *pReq = (Config_t *)mf;
 	char extend_desc[EVENT_DESCR_STR_SZ];
 	char *desc = NULL;
 	u32 form;
 	u8 page_type;
 	if (pReq->Header.PageType == MPI_CONFIG_PAGETYPE_EXTENDED)
 		page_type = pReq->ExtPageType;
 	else
 		page_type = pReq->Header.PageType;
 	/*
 	 * ignore invalid page messages for GET_NEXT_HANDLE
 	 */
 	form = le32_to_cpu(pReq->PageAddress);
 	if (ioc_status == MPI_IOCSTATUS_CONFIG_INVALID_PAGE) {
 		if (page_type == MPI_CONFIG_EXTPAGETYPE_SAS_DEVICE ||
 		    page_type == MPI_CONFIG_EXTPAGETYPE_SAS_EXPANDER ||
 		    page_type == MPI_CONFIG_EXTPAGETYPE_ENCLOSURE) {
 			if ((form >> MPI_SAS_DEVICE_PGAD_FORM_SHIFT) ==
 				MPI_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE)
 				return;
 		}
 		if (page_type == MPI_CONFIG_PAGETYPE_FC_DEVICE)
 			if ((form & MPI_FC_DEVICE_PGAD_FORM_MASK) ==
 				MPI_FC_DEVICE_PGAD_FORM_NEXT_DID)
 				return;
 	}
 	snprintf(extend_desc, EVENT_DESCR_STR_SZ,
 	    "type=%02Xh, page=%02Xh, action=%02Xh, form=%08Xh",
 	    page_type, pReq->Header.PageNumber, pReq->Action, form);
 	switch (ioc_status) {
 	case MPI_IOCSTATUS_CONFIG_INVALID_ACTION: /* 0x0020 */
 		desc = "Config Page Invalid Action";
 		break;
 	case MPI_IOCSTATUS_CONFIG_INVALID_TYPE:   /* 0x0021 */
 		desc = "Config Page Invalid Type";
 		break;
 	case MPI_IOCSTATUS_CONFIG_INVALID_PAGE:   /* 0x0022 */
 		desc = "Config Page Invalid Page";
 		break;
 	case MPI_IOCSTATUS_CONFIG_INVALID_DATA:   /* 0x0023 */
 		desc = "Config Page Invalid Data";
 		break;
 	case MPI_IOCSTATUS_CONFIG_NO_DEFAULTS:    /* 0x0024 */
 		desc = "Config Page No Defaults";
 		break;
 	case MPI_IOCSTATUS_CONFIG_CANT_COMMIT:    /* 0x0025 */
 		desc = "Config Page Can't Commit";
 		break;
 	}
 	if (!desc)
 		return;
 	dreplyprintk(ioc, printk(MYIOC_s_DEBUG_FMT "IOCStatus(0x%04X): %s: %s\n",
 	    ioc->name, ioc_status, desc, extend_desc));
 }
 /**
 *	mpt_iocstatus_info - IOCSTATUS information returned from IOC.
 *	@ioc: Pointer to MPT_ADAPTER structure
 *	@ioc_status: U32 IOCStatus word from IOC
 *	@mf: Pointer to MPT request frame
 *
 *	Refer to lsi/mpi.h.
 **/
 static void
 mpt_iocstatus_info(MPT_ADAPTER *ioc, u32 ioc_status, MPT_FRAME_HDR *mf)
 {
 	u32 status = ioc_status & MPI_IOCSTATUS_MASK;
 	char *desc = NULL;
 	switch (status) {
 /****************************************************************************/
 /*  Common IOCStatus values for all replies                                 */
 /****************************************************************************/
 	case MPI_IOCSTATUS_INVALID_FUNCTION: /* 0x0001 */
 		desc = "Invalid Function";
 		break;
 	case MPI_IOCSTATUS_BUSY: /* 0x0002 */
 		desc = "Busy";
 		break;
 	case MPI_IOCSTATUS_INVALID_SGL: /* 0x0003 */
 		desc = "Invalid SGL";
 		break;
 	case MPI_IOCSTATUS_INTERNAL_ERROR: /* 0x0004 */
 		desc = "Internal Error";
 		break;
 	case MPI_IOCSTATUS_RESERVED: /* 0x0005 */
 		desc = "Reserved";
 		break;
 	case MPI_IOCSTATUS_INSUFFICIENT_RESOURCES: /* 0x0006 */
 		desc = "Insufficient Resources";
 		break;
 	case MPI_IOCSTATUS_INVALID_FIELD: /* 0x0007 */
 		desc = "Invalid Field";
 		break;
 	case MPI_IOCSTATUS_INVALID_STATE: /* 0x0008 */
 		desc = "Invalid State";
 		break;
 /****************************************************************************/
 /*  Config IOCStatus values                                                 */
 /****************************************************************************/
 	case MPI_IOCSTATUS_CONFIG_INVALID_ACTION: /* 0x0020 */
 	case MPI_IOCSTATUS_CONFIG_INVALID_TYPE:   /* 0x0021 */
 	case MPI_IOCSTATUS_CONFIG_INVALID_PAGE:   /* 0x0022 */
 	case MPI_IOCSTATUS_CONFIG_INVALID_DATA:   /* 0x0023 */
 	case MPI_IOCSTATUS_CONFIG_NO_DEFAULTS:    /* 0x0024 */
 	case MPI_IOCSTATUS_CONFIG_CANT_COMMIT:    /* 0x0025 */
 		mpt_iocstatus_info_config(ioc, status, mf);
 		break;
 /****************************************************************************/
 /*  SCSIIO Reply (SPI, FCP, SAS) initiator values                           */
 /*                                                                          */
 /*  Look at mptscsih_iocstatus_info_scsiio in mptscsih.c */
 /*                                                                          */
 /****************************************************************************/
 	case MPI_IOCSTATUS_SCSI_RECOVERED_ERROR: /* 0x0040 */
 	case MPI_IOCSTATUS_SCSI_DATA_UNDERRUN: /* 0x0045 */
 	case MPI_IOCSTATUS_SCSI_INVALID_BUS: /* 0x0041 */
 	case MPI_IOCSTATUS_SCSI_INVALID_TARGETID: /* 0x0042 */
 	case MPI_IOCSTATUS_SCSI_DEVICE_NOT_THERE: /* 0x0043 */
 	case MPI_IOCSTATUS_SCSI_DATA_OVERRUN: /* 0x0044 */
 	case MPI_IOCSTATUS_SCSI_IO_DATA_ERROR: /* 0x0046 */
 	case MPI_IOCSTATUS_SCSI_PROTOCOL_ERROR: /* 0x0047 */
 	case MPI_IOCSTATUS_SCSI_TASK_TERMINATED: /* 0x0048 */
 	case MPI_IOCSTATUS_SCSI_RESIDUAL_MISMATCH: /* 0x0049 */
 	case MPI_IOCSTATUS_SCSI_TASK_MGMT_FAILED: /* 0x004A */
 	case MPI_IOCSTATUS_SCSI_IOC_TERMINATED: /* 0x004B */
 	case MPI_IOCSTATUS_SCSI_EXT_TERMINATED: /* 0x004C */
 		break;
 /****************************************************************************/
 /*  SCSI Target values                                                      */
 /****************************************************************************/
 	case MPI_IOCSTATUS_TARGET_PRIORITY_IO: /* 0x0060 */
 		desc = "Target: Priority IO";
 		break;
 	case MPI_IOCSTATUS_TARGET_INVALID_PORT: /* 0x0061 */
 		desc = "Target: Invalid Port";
 		break;
 	case MPI_IOCSTATUS_TARGET_INVALID_IO_INDEX: /* 0x0062 */
 		desc = "Target Invalid IO Index:";
 		break;
 	case MPI_IOCSTATUS_TARGET_ABORTED: /* 0x0063 */
 		desc = "Target: Aborted";
 		break;
 	case MPI_IOCSTATUS_TARGET_NO_CONN_RETRYABLE: /* 0x0064 */
 		desc = "Target: No Conn Retryable";
 		break;
 	case MPI_IOCSTATUS_TARGET_NO_CONNECTION: /* 0x0065 */
 		desc = "Target: No Connection";
 		break;
 	case MPI_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH: /* 0x006A */
 		desc = "Target: Transfer Count Mismatch";
 		break;
 	case MPI_IOCSTATUS_TARGET_STS_DATA_NOT_SENT: /* 0x006B */
 		desc = "Target: STS Data not Sent";
 		break;
 	case MPI_IOCSTATUS_TARGET_DATA_OFFSET_ERROR: /* 0x006D */
 		desc = "Target: Data Offset Error";
 		break;
 	case MPI_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA: /* 0x006E */
 		desc = "Target: Too Much Write Data";
 		break;
 	case MPI_IOCSTATUS_TARGET_IU_TOO_SHORT: /* 0x006F */
 		desc = "Target: IU Too Short";
 		break;
 	case MPI_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT: /* 0x0070 */
 		desc = "Target: ACK NAK Timeout";
 		break;
 	case MPI_IOCSTATUS_TARGET_NAK_RECEIVED: /* 0x0071 */
 		desc = "Target: Nak Received";
 		break;
 /****************************************************************************/
 /*  Fibre Channel Direct Access values                                      */
 /****************************************************************************/
 	case MPI_IOCSTATUS_FC_ABORTED: /* 0x0066 */
 		desc = "FC: Aborted";
 		break;
 	case MPI_IOCSTATUS_FC_RX_ID_INVALID: /* 0x0067 */
 		desc = "FC: RX ID Invalid";
 		break;
 	case MPI_IOCSTATUS_FC_DID_INVALID: /* 0x0068 */
 		desc = "FC: DID Invalid";
 		break;
 	case MPI_IOCSTATUS_FC_NODE_LOGGED_OUT: /* 0x0069 */
 		desc = "FC: Node Logged Out";
 		break;
 	case MPI_IOCSTATUS_FC_EXCHANGE_CANCELED: /* 0x006C */
 		desc = "FC: Exchange Canceled";
 		break;
 /****************************************************************************/
 /*  LAN values                                                              */
 /****************************************************************************/
 	case MPI_IOCSTATUS_LAN_DEVICE_NOT_FOUND: /* 0x0080 */
 		desc = "LAN: Device not Found";
 		break;
 	case MPI_IOCSTATUS_LAN_DEVICE_FAILURE: /* 0x0081 */
 		desc = "LAN: Device Failure";
 		break;
 	case MPI_IOCSTATUS_LAN_TRANSMIT_ERROR: /* 0x0082 */
 		desc = "LAN: Transmit Error";
 		break;
 	case MPI_IOCSTATUS_LAN_TRANSMIT_ABORTED: /* 0x0083 */
 		desc = "LAN: Transmit Aborted";
 		break;
 	case MPI_IOCSTATUS_LAN_RECEIVE_ERROR: /* 0x0084 */
 		desc = "LAN: Receive Error";
 		break;
 	case MPI_IOCSTATUS_LAN_RECEIVE_ABORTED: /* 0x0085 */
 		desc = "LAN: Receive Aborted";
 		break;
 	case MPI_IOCSTATUS_LAN_PARTIAL_PACKET: /* 0x0086 */
 		desc = "LAN: Partial Packet";
 		break;
 	case MPI_IOCSTATUS_LAN_CANCELED: /* 0x0087 */
 		desc = "LAN: Canceled";
 		break;
 /****************************************************************************/
 /*  Serial Attached SCSI values                                             */
 /****************************************************************************/
 	case MPI_IOCSTATUS_SAS_SMP_REQUEST_FAILED: /* 0x0090 */
 		desc = "SAS: SMP Request Failed";
 		break;
 	case MPI_IOCSTATUS_SAS_SMP_DATA_OVERRUN: /* 0x0090 */
 		desc = "SAS: SMP Data Overrun";
 		break;
 	default:
 		desc = "Others";
 		break;
 	}
 	if (!desc)
 		return;
 	dreplyprintk(ioc, printk(MYIOC_s_DEBUG_FMT "IOCStatus(0x%04X): %s\n",
 	    ioc->name, status, desc));
 }
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 EXPORT_SYMBOL(mpt_attach);
 EXPORT_SYMBOL(mpt_detach);
 #ifdef CONFIG_PM
 EXPORT_SYMBOL(mpt_resume);
 EXPORT_SYMBOL(mpt_suspend);
 #endif
 EXPORT_SYMBOL(ioc_list);
 EXPORT_SYMBOL(mpt_register);
 EXPORT_SYMBOL(mpt_deregister);
 EXPORT_SYMBOL(mpt_event_register);
 EXPORT_SYMBOL(mpt_event_deregister);
 EXPORT_SYMBOL(mpt_reset_register);
 EXPORT_SYMBOL(mpt_reset_deregister);
 EXPORT_SYMBOL(mpt_device_driver_register);
 EXPORT_SYMBOL(mpt_device_driver_deregister);
 EXPORT_SYMBOL(mpt_get_msg_frame);
 EXPORT_SYMBOL(mpt_put_msg_frame);
 EXPORT_SYMBOL(mpt_put_msg_frame_hi_pri);
 EXPORT_SYMBOL(mpt_free_msg_frame);
 EXPORT_SYMBOL(mpt_send_handshake_request);
 EXPORT_SYMBOL(mpt_verify_adapter);
 EXPORT_SYMBOL(mpt_GetIocState);
 EXPORT_SYMBOL(mpt_print_ioc_summary);
 EXPORT_SYMBOL(mpt_HardResetHandler);
 EXPORT_SYMBOL(mpt_config);
 EXPORT_SYMBOL(mpt_findImVolumes);
 EXPORT_SYMBOL(mpt_alloc_fw_memory);
 EXPORT_SYMBOL(mpt_free_fw_memory);
 EXPORT_SYMBOL(mptbase_sas_persist_operation);
 EXPORT_SYMBOL(mpt_raid_phys_disk_pg0);
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /**
 *	fusion_init - Fusion MPT base driver initialization routine.
 *
 *	Returns 0 for success, non-zero for failure.
 */
 static int __init
 fusion_init(void)
 {
 	u8 cb_idx;
 	show_mptmod_ver(my_NAME, my_VERSION);
 	printk(KERN_INFO COPYRIGHT "\n");
 	for (cb_idx = 0; cb_idx < MPT_MAX_PROTOCOL_DRIVERS; cb_idx++) {
 		MptCallbacks[cb_idx] = NULL;
 		MptDriverClass[cb_idx] = MPTUNKNOWN_DRIVER;
 		MptEvHandlers[cb_idx] = NULL;
 		MptResetHandlers[cb_idx] = NULL;
 	}
 	/*  Register ourselves (mptbase) in order to facilitate
 	 *  EventNotification handling.
 	 */
 	mpt_base_index = mpt_register(mptbase_reply, MPTBASE_DRIVER);
 	/* Register for hard reset handling callbacks.
 	 */
 	mpt_reset_register(mpt_base_index, mpt_ioc_reset);
 #ifdef CONFIG_PROC_FS
 	(void) procmpt_create();
 #endif
 	return 0;
 }
 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
 /**
 *	fusion_exit - Perform driver unload cleanup.
 *
 *	This routine frees all resources associated with each MPT adapter
 *	and removes all %MPT_PROCFS_MPTBASEDIR entries.
 */
 static void __exit
 fusion_exit(void)
 {
 	mpt_reset_deregister(mpt_base_index);
 #ifdef CONFIG_PROC_FS
 	procmpt_destroy();
 #endif
 }
 module_init(fusion_init);
 module_exit(fusion_exit);
 /*
 * Atmel MACB Ethernet Controller driver
 *
 * Copyright (C) 2004-2006 Atmel Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
 #include <linux/clk.h>
 #include <linux/module.h>
 #include <linux/moduleparam.h>
 #include <linux/kernel.h>
 #include <linux/types.h>
 #include <linux/slab.h>
 #include <linux/init.h>
 #include <linux/netdevice.h>
 #include <linux/etherdevice.h>
 #include <linux/dma-mapping.h>
 #include <linux/platform_device.h>
 #include <linux/phy.h>
 #include <mach/board.h>
 #include <mach/cpu.h>
 #include "macb.h"
 #define RX_BUFFER_SIZE		128
 #define RX_RING_SIZE		512
 #define RX_RING_BYTES		(sizeof(struct dma_desc) * RX_RING_SIZE)
 /* Make the IP header word-aligned (the ethernet header is 14 bytes) */
 #define RX_OFFSET		2
 #define TX_RING_SIZE		128
 #define DEF_TX_RING_PENDING	(TX_RING_SIZE - 1)
 #define TX_RING_BYTES		(sizeof(struct dma_desc) * TX_RING_SIZE)
 #define TX_RING_GAP(bp)						\
 	(TX_RING_SIZE - (bp)->tx_pending)
 #define TX_BUFFS_AVAIL(bp)					\
 	(((bp)->tx_tail <= (bp)->tx_head) ?			\
 	 (bp)->tx_tail + (bp)->tx_pending - (bp)->tx_head :	\
 	 (bp)->tx_tail - (bp)->tx_head - TX_RING_GAP(bp))
 #define NEXT_TX(n)		(((n) + 1) & (TX_RING_SIZE - 1))
 #define NEXT_RX(n)		(((n) + 1) & (RX_RING_SIZE - 1))
 /* minimum number of free TX descriptors before waking up TX process */
 #define MACB_TX_WAKEUP_THRESH	(TX_RING_SIZE / 4)
 #define MACB_RX_INT_FLAGS	(MACB_BIT(RCOMP) | MACB_BIT(RXUBR)	\
 				 | MACB_BIT(ISR_ROVR))
 static void __macb_set_hwaddr(struct macb *bp)
 {
 	u32 bottom;
 	u16 top;
 	bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
 	macb_writel(bp, SA1B, bottom);
 	top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
 	macb_writel(bp, SA1T, top);
 }
 static void __init macb_get_hwaddr(struct macb *bp)
 {
 	u32 bottom;
 	u16 top;
 	u8 addr[6];
 	bottom = macb_readl(bp, SA1B);
 	top = macb_readl(bp, SA1T);
 	addr[0] = bottom & 0xff;
 	addr[1] = (bottom >> 8) & 0xff;
 	addr[2] = (bottom >> 16) & 0xff;
 	addr[3] = (bottom >> 24) & 0xff;
 	addr[4] = top & 0xff;
 	addr[5] = (top >> 8) & 0xff;
 	if (is_valid_ether_addr(addr)) {
 		memcpy(bp->dev->dev_addr, addr, sizeof(addr));
 	} else {
 		dev_info(&bp->pdev->dev, "invalid hw address, using random\n");
 		random_ether_addr(bp->dev->dev_addr);
 	}
 }
 static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
 {
 	struct macb *bp = bus->priv;
 	int value;
 	macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
 			      | MACB_BF(RW, MACB_MAN_READ)
 			      | MACB_BF(PHYA, mii_id)
 			      | MACB_BF(REGA, regnum)
 			      | MACB_BF(CODE, MACB_MAN_CODE)));
 	/* wait for end of transfer */
 	while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
 		cpu_relax();
 	value = MACB_BFEXT(DATA, macb_readl(bp, MAN));
 	return value;
 }
 static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
 			   u16 value)
 {
 	struct macb *bp = bus->priv;
 	macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
 			      | MACB_BF(RW, MACB_MAN_WRITE)
 			      | MACB_BF(PHYA, mii_id)
 			      | MACB_BF(REGA, regnum)
 			      | MACB_BF(CODE, MACB_MAN_CODE)
 			      | MACB_BF(DATA, value)));
 	/* wait for end of transfer */
 	while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
 		cpu_relax();
 	return 0;
 }
 static int macb_mdio_reset(struct mii_bus *bus)
 {
 	return 0;
 }
 static void macb_handle_link_change(struct net_device *dev)
 {
 	struct macb *bp = netdev_priv(dev);
 	struct phy_device *phydev = bp->phy_dev;
 	unsigned long flags;
 	int status_change = 0;
 	spin_lock_irqsave(&bp->lock, flags);
 	if (phydev->link) {
 		if ((bp->speed != phydev->speed) ||
 		    (bp->duplex != phydev->duplex)) {
 			u32 reg;
 			reg = macb_readl(bp, NCFGR);
 			reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
 			if (phydev->duplex)
 				reg |= MACB_BIT(FD);
 			if (phydev->speed == SPEED_100)
 				reg |= MACB_BIT(SPD);
 			macb_writel(bp, NCFGR, reg);
 			bp->speed = phydev->speed;
 			bp->duplex = phydev->duplex;
 			status_change = 1;
 		}
 	}
 	if (phydev->link != bp->link) {
 		if (!phydev->link) {
 			bp->speed = 0;
 			bp->duplex = -1;
 		}
 		bp->link = phydev->link;
 		status_change = 1;
 	}
 	spin_unlock_irqrestore(&bp->lock, flags);
 	if (status_change) {
 		if (phydev->link)
 			printk(KERN_INFO "%s: link up (%d/%s)\n",
 			       dev->name, phydev->speed,
 			       DUPLEX_FULL == phydev->duplex ? "Full":"Half");
 		else
 			printk(KERN_INFO "%s: link down\n", dev->name);
 	}
 }
 /* based on au1000_eth. c*/
 static int macb_mii_probe(struct net_device *dev)
 {
 	struct macb *bp = netdev_priv(dev);
 	struct phy_device *phydev = NULL;
 	struct eth_platform_data *pdata;
 	int phy_addr;
 	/* find the first phy */
 	for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
 		if (bp->mii_bus->phy_map[phy_addr]) {
 			phydev = bp->mii_bus->phy_map[phy_addr];
 			break;
 		}
 	}
 	if (!phydev) {
 		printk (KERN_ERR "%s: no PHY found\n", dev->name);
 		return -1;
 	}
 	pdata = bp->pdev->dev.platform_data;
 	/* TODO : add pin_irq */
 	/* attach the mac to the phy */
 	if (pdata && pdata->is_rmii) {
 		phydev = phy_connect(dev, dev_name(&phydev->dev),
 			&macb_handle_link_change, 0, PHY_INTERFACE_MODE_RMII);
 	} else {
 		phydev = phy_connect(dev, dev_name(&phydev->dev),
 			&macb_handle_link_change, 0, PHY_INTERFACE_MODE_MII);
 	}
 	if (IS_ERR(phydev)) {
 		printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
 		return PTR_ERR(phydev);
 	}
 	/* mask with MAC supported features */
 	phydev->supported &= PHY_BASIC_FEATURES;
 	phydev->advertising = phydev->supported;
 	bp->link = 0;
 	bp->speed = 0;
 	bp->duplex = -1;
 	bp->phy_dev = phydev;
 	return 0;
 }
 static int macb_mii_init(struct macb *bp)
 {
 	struct eth_platform_data *pdata;
 	int err = -ENXIO, i;
-	/* Enable managment port */
+	/* Enable management port */
 	macb_writel(bp, NCR, MACB_BIT(MPE));
 	bp->mii_bus = mdiobus_alloc();
 	if (bp->mii_bus == NULL) {
 		err = -ENOMEM;
 		goto err_out;
 	}
 	bp->mii_bus->name = "MACB_mii_bus";
 	bp->mii_bus->read = &macb_mdio_read;
 	bp->mii_bus->write = &macb_mdio_write;
 	bp->mii_bus->reset = &macb_mdio_reset;
 	snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%x", bp->pdev->id);
 	bp->mii_bus->priv = bp;
 	bp->mii_bus->parent = &bp->dev->dev;
 	pdata = bp->pdev->dev.platform_data;
 	if (pdata)
 		bp->mii_bus->phy_mask = pdata->phy_mask;
 	bp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
 	if (!bp->mii_bus->irq) {
 		err = -ENOMEM;
 		goto err_out_free_mdiobus;
 	}
 	for (i = 0; i < PHY_MAX_ADDR; i++)
 		bp->mii_bus->irq[i] = PHY_POLL;
 	platform_set_drvdata(bp->dev, bp->mii_bus);
 	if (mdiobus_register(bp->mii_bus))
 		goto err_out_free_mdio_irq;
 	if (macb_mii_probe(bp->dev) != 0) {
 		goto err_out_unregister_bus;
 	}
 	return 0;
 err_out_unregister_bus:
 	mdiobus_unregister(bp->mii_bus);
 err_out_free_mdio_irq:
 	kfree(bp->mii_bus->irq);
 err_out_free_mdiobus:
 	mdiobus_free(bp->mii_bus);
 err_out:
 	return err;
 }
 static void macb_update_stats(struct macb *bp)
 {
 	u32 __iomem *reg = bp->regs + MACB_PFR;
 	u32 *p = &bp->hw_stats.rx_pause_frames;
 	u32 *end = &bp->hw_stats.tx_pause_frames + 1;
 	WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
 	for(; p < end; p++, reg++)
 		*p += __raw_readl(reg);
 }
 static void macb_tx(struct macb *bp)
 {
 	unsigned int tail;
 	unsigned int head;
 	u32 status;
 	status = macb_readl(bp, TSR);
 	macb_writel(bp, TSR, status);
 	dev_dbg(&bp->pdev->dev, "macb_tx status = %02lx\n",
 		(unsigned long)status);
 	if (status & (MACB_BIT(UND) | MACB_BIT(TSR_RLE))) {
 		int i;
 		printk(KERN_ERR "%s: TX %s, resetting buffers\n",
 			bp->dev->name, status & MACB_BIT(UND) ?
 			"underrun" : "retry limit exceeded");
 		/* Transfer ongoing, disable transmitter, to avoid confusion */
 		if (status & MACB_BIT(TGO))
 			macb_writel(bp, NCR, macb_readl(bp, NCR) & ~MACB_BIT(TE));
 		head = bp->tx_head;
 		/*Mark all the buffer as used to avoid sending a lost buffer*/
 		for (i = 0; i < TX_RING_SIZE; i++)
 			bp->tx_ring[i].ctrl = MACB_BIT(TX_USED);
 		/* free transmit buffer in upper layer*/
 		for (tail = bp->tx_tail; tail != head; tail = NEXT_TX(tail)) {
 			struct ring_info *rp = &bp->tx_skb[tail];
 			struct sk_buff *skb = rp->skb;
 			BUG_ON(skb == NULL);
 			rmb();
 			dma_unmap_single(&bp->pdev->dev, rp->mapping, skb->len,
 							 DMA_TO_DEVICE);
 			rp->skb = NULL;
 			dev_kfree_skb_irq(skb);
 		}
 		bp->tx_head = bp->tx_tail = 0;
 		/* Enable the transmitter again */
 		if (status & MACB_BIT(TGO))
 			macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TE));
 	}
 	if (!(status & MACB_BIT(COMP)))
 		/*
 		 * This may happen when a buffer becomes complete
 		 * between reading the ISR and scanning the
 		 * descriptors.  Nothing to worry about.
 		 */
 		return;
 	head = bp->tx_head;
 	for (tail = bp->tx_tail; tail != head; tail = NEXT_TX(tail)) {
 		struct ring_info *rp = &bp->tx_skb[tail];
 		struct sk_buff *skb = rp->skb;
 		u32 bufstat;
 		BUG_ON(skb == NULL);
 		rmb();
 		bufstat = bp->tx_ring[tail].ctrl;
 		if (!(bufstat & MACB_BIT(TX_USED)))
 			break;
 		dev_dbg(&bp->pdev->dev, "skb %u (data %p) TX complete\n",
 			tail, skb->data);
 		dma_unmap_single(&bp->pdev->dev, rp->mapping, skb->len,
 				 DMA_TO_DEVICE);
 		bp->stats.tx_packets++;
 		bp->stats.tx_bytes += skb->len;
 		rp->skb = NULL;
 		dev_kfree_skb_irq(skb);
 	}
 	bp->tx_tail = tail;
 	if (netif_queue_stopped(bp->dev) &&
 	    TX_BUFFS_AVAIL(bp) > MACB_TX_WAKEUP_THRESH)
 		netif_wake_queue(bp->dev);
 }
 static int macb_rx_frame(struct macb *bp, unsigned int first_frag,
 			 unsigned int last_frag)
 {
 	unsigned int len;
 	unsigned int frag;
 	unsigned int offset = 0;
 	struct sk_buff *skb;
 	len = MACB_BFEXT(RX_FRMLEN, bp->rx_ring[last_frag].ctrl);
 	dev_dbg(&bp->pdev->dev, "macb_rx_frame frags %u - %u (len %u)\n",
 		first_frag, last_frag, len);
 	skb = dev_alloc_skb(len + RX_OFFSET);
 	if (!skb) {
 		bp->stats.rx_dropped++;
 		for (frag = first_frag; ; frag = NEXT_RX(frag)) {
 			bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED);
 			if (frag == last_frag)
 				break;
 		}
 		wmb();
 		return 1;
 	}
 	skb_reserve(skb, RX_OFFSET);
 	skb->ip_summed = CHECKSUM_NONE;
 	skb_put(skb, len);
 	for (frag = first_frag; ; frag = NEXT_RX(frag)) {
 		unsigned int frag_len = RX_BUFFER_SIZE;
 		if (offset + frag_len > len) {
 			BUG_ON(frag != last_frag);
 			frag_len = len - offset;
 		}
 		skb_copy_to_linear_data_offset(skb, offset,
 					       (bp->rx_buffers +
 					        (RX_BUFFER_SIZE * frag)),
 					       frag_len);
 		offset += RX_BUFFER_SIZE;
 		bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED);
 		wmb();
 		if (frag == last_frag)
 			break;
 	}
 	skb->protocol = eth_type_trans(skb, bp->dev);
 	bp->stats.rx_packets++;
 	bp->stats.rx_bytes += len;
 	dev_dbg(&bp->pdev->dev, "received skb of length %u, csum: %08x\n",
 		skb->len, skb->csum);
 	netif_receive_skb(skb);
 	return 0;
 }
 /* Mark DMA descriptors from begin up to and not including end as unused */
 static void discard_partial_frame(struct macb *bp, unsigned int begin,
 				  unsigned int end)
 {
 	unsigned int frag;
 	for (frag = begin; frag != end; frag = NEXT_RX(frag))
 		bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED);
 	wmb();
 	/*
 	 * When this happens, the hardware stats registers for
 	 * whatever caused this is updated, so we don't have to record
 	 * anything.
 	 */
 }
 static int macb_rx(struct macb *bp, int budget)
 {
 	int received = 0;
 	unsigned int tail = bp->rx_tail;
 	int first_frag = -1;
 	for (; budget > 0; tail = NEXT_RX(tail)) {
 		u32 addr, ctrl;
 		rmb();
 		addr = bp->rx_ring[tail].addr;
 		ctrl = bp->rx_ring[tail].ctrl;
 		if (!(addr & MACB_BIT(RX_USED)))
 			break;
 		if (ctrl & MACB_BIT(RX_SOF)) {
 			if (first_frag != -1)
 				discard_partial_frame(bp, first_frag, tail);
 			first_frag = tail;
 		}
 		if (ctrl & MACB_BIT(RX_EOF)) {
 			int dropped;
 			BUG_ON(first_frag == -1);
 			dropped = macb_rx_frame(bp, first_frag, tail);
 			first_frag = -1;
 			if (!dropped) {
 				received++;
 				budget--;
 			}
 		}
 	}
 	if (first_frag != -1)
 		bp->rx_tail = first_frag;
 	else
 		bp->rx_tail = tail;
 	return received;
 }
 static int macb_poll(struct napi_struct *napi, int budget)
 {
 	struct macb *bp = container_of(napi, struct macb, napi);
 	int work_done;
 	u32 status;
 	status = macb_readl(bp, RSR);
 	macb_writel(bp, RSR, status);
 	work_done = 0;
 	dev_dbg(&bp->pdev->dev, "poll: status = %08lx, budget = %d\n",
 		(unsigned long)status, budget);
 	work_done = macb_rx(bp, budget);
 	if (work_done < budget)
 		napi_complete(napi);
 	/*
 	 * We've done what we can to clean the buffers. Make sure we
 	 * get notified when new packets arrive.
 	 */
 	macb_writel(bp, IER, MACB_RX_INT_FLAGS);
 	/* TODO: Handle errors */
 	return work_done;
 }
 static irqreturn_t macb_interrupt(int irq, void *dev_id)
 {
 	struct net_device *dev = dev_id;
 	struct macb *bp = netdev_priv(dev);
 	u32 status;
 	status = macb_readl(bp, ISR);
 	if (unlikely(!status))
 		return IRQ_NONE;
 	spin_lock(&bp->lock);
 	while (status) {
 		/* close possible race with dev_close */
 		if (unlikely(!netif_running(dev))) {
 			macb_writel(bp, IDR, ~0UL);
 			break;
 		}
 		if (status & MACB_RX_INT_FLAGS) {
 			if (napi_schedule_prep(&bp->napi)) {
 				/*
 				 * There's no point taking any more interrupts
 				 * until we have processed the buffers
 				 */
 				macb_writel(bp, IDR, MACB_RX_INT_FLAGS);
 				dev_dbg(&bp->pdev->dev,
 					"scheduling RX softirq\n");
 				__napi_schedule(&bp->napi);
 			}
 		}
 		if (status & (MACB_BIT(TCOMP) | MACB_BIT(ISR_TUND) |
 			    MACB_BIT(ISR_RLE)))
 			macb_tx(bp);
 		/*
 		 * Link change detection isn't possible with RMII, so we'll
 		 * add that if/when we get our hands on a full-blown MII PHY.
 		 */
 		if (status & MACB_BIT(HRESP)) {
 			/*
 			 * TODO: Reset the hardware, and maybe move the printk
 			 * to a lower-priority context as well (work queue?)
 			 */
 			printk(KERN_ERR "%s: DMA bus error: HRESP not OK\n",
 			       dev->name);
 		}
 		status = macb_readl(bp, ISR);
 	}
 	spin_unlock(&bp->lock);
 	return IRQ_HANDLED;
 }
 #ifdef CONFIG_NET_POLL_CONTROLLER
 /*
 * Polling receive - used by netconsole and other diagnostic tools
 * to allow network i/o with interrupts disabled.
 */
 static void macb_poll_controller(struct net_device *dev)
 {
 	unsigned long flags;
 	local_irq_save(flags);
 	macb_interrupt(dev->irq, dev);
 	local_irq_restore(flags);
 }
 #endif
 static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
 {
 	struct macb *bp = netdev_priv(dev);
 	dma_addr_t mapping;
 	unsigned int len, entry;
 	u32 ctrl;
 	unsigned long flags;
 #ifdef DEBUG
 	int i;
 	dev_dbg(&bp->pdev->dev,
 		"start_xmit: len %u head %p data %p tail %p end %p\n",
 		skb->len, skb->head, skb->data,
 		skb_tail_pointer(skb), skb_end_pointer(skb));
 	dev_dbg(&bp->pdev->dev,
 		"data:");
 	for (i = 0; i < 16; i++)
 		printk(" %02x", (unsigned int)skb->data[i]);
 	printk("\n");
 #endif
 	len = skb->len;
 	spin_lock_irqsave(&bp->lock, flags);
 	/* This is a hard error, log it. */
 	if (TX_BUFFS_AVAIL(bp) < 1) {
 		netif_stop_queue(dev);
 		spin_unlock_irqrestore(&bp->lock, flags);
 		dev_err(&bp->pdev->dev,
 			"BUG! Tx Ring full when queue awake!\n");
 		dev_dbg(&bp->pdev->dev, "tx_head = %u, tx_tail = %u\n",
 			bp->tx_head, bp->tx_tail);
 		return NETDEV_TX_BUSY;
 	}
 	entry = bp->tx_head;
 	dev_dbg(&bp->pdev->dev, "Allocated ring entry %u\n", entry);
 	mapping = dma_map_single(&bp->pdev->dev, skb->data,
 				 len, DMA_TO_DEVICE);
 	bp->tx_skb[entry].skb = skb;
 	bp->tx_skb[entry].mapping = mapping;
 	dev_dbg(&bp->pdev->dev, "Mapped skb data %p to DMA addr %08lx\n",
 		skb->data, (unsigned long)mapping);
 	ctrl = MACB_BF(TX_FRMLEN, len);
 	ctrl |= MACB_BIT(TX_LAST);
 	if (entry == (TX_RING_SIZE - 1))
 		ctrl |= MACB_BIT(TX_WRAP);
 	bp->tx_ring[entry].addr = mapping;
 	bp->tx_ring[entry].ctrl = ctrl;
 	wmb();
 	entry = NEXT_TX(entry);
 	bp->tx_head = entry;
 	macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
 	if (TX_BUFFS_AVAIL(bp) < 1)
 		netif_stop_queue(dev);
 	spin_unlock_irqrestore(&bp->lock, flags);
 	dev->trans_start = jiffies;
 	return NETDEV_TX_OK;
 }
 static void macb_free_consistent(struct macb *bp)
 {
 	if (bp->tx_skb) {
 		kfree(bp->tx_skb);
 		bp->tx_skb = NULL;
 	}
 	if (bp->rx_ring) {
 		dma_free_coherent(&bp->pdev->dev, RX_RING_BYTES,
 				  bp->rx_ring, bp->rx_ring_dma);
 		bp->rx_ring = NULL;
 	}
 	if (bp->tx_ring) {
 		dma_free_coherent(&bp->pdev->dev, TX_RING_BYTES,
 				  bp->tx_ring, bp->tx_ring_dma);
 		bp->tx_ring = NULL;
 	}
 	if (bp->rx_buffers) {
 		dma_free_coherent(&bp->pdev->dev,
 				  RX_RING_SIZE * RX_BUFFER_SIZE,
 				  bp->rx_buffers, bp->rx_buffers_dma);
 		bp->rx_buffers = NULL;
 	}
 }
 static int macb_alloc_consistent(struct macb *bp)
 {
 	int size;
 	size = TX_RING_SIZE * sizeof(struct ring_info);
 	bp->tx_skb = kmalloc(size, GFP_KERNEL);
 	if (!bp->tx_skb)
 		goto out_err;
 	size = RX_RING_BYTES;
 	bp->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
 					 &bp->rx_ring_dma, GFP_KERNEL);
 	if (!bp->rx_ring)
 		goto out_err;
 	dev_dbg(&bp->pdev->dev,
 		"Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
 		size, (unsigned long)bp->rx_ring_dma, bp->rx_ring);
 	size = TX_RING_BYTES;
 	bp->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
 					 &bp->tx_ring_dma, GFP_KERNEL);
 	if (!bp->tx_ring)
 		goto out_err;
 	dev_dbg(&bp->pdev->dev,
 		"Allocated TX ring of %d bytes at %08lx (mapped %p)\n",
 		size, (unsigned long)bp->tx_ring_dma, bp->tx_ring);
 	size = RX_RING_SIZE * RX_BUFFER_SIZE;
 	bp->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
 					    &bp->rx_buffers_dma, GFP_KERNEL);
 	if (!bp->rx_buffers)
 		goto out_err;
 	dev_dbg(&bp->pdev->dev,
 		"Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
 		size, (unsigned long)bp->rx_buffers_dma, bp->rx_buffers);
 	return 0;
 out_err:
 	macb_free_consistent(bp);
 	return -ENOMEM;
 }
 static void macb_init_rings(struct macb *bp)
 {
 	int i;
 	dma_addr_t addr;
 	addr = bp->rx_buffers_dma;
 	for (i = 0; i < RX_RING_SIZE; i++) {
 		bp->rx_ring[i].addr = addr;
 		bp->rx_ring[i].ctrl = 0;
 		addr += RX_BUFFER_SIZE;
 	}
 	bp->rx_ring[RX_RING_SIZE - 1].addr |= MACB_BIT(RX_WRAP);
 	for (i = 0; i < TX_RING_SIZE; i++) {
 		bp->tx_ring[i].addr = 0;
 		bp->tx_ring[i].ctrl = MACB_BIT(TX_USED);
 	}
 	bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
 	bp->rx_tail = bp->tx_head = bp->tx_tail = 0;
 }
 static void macb_reset_hw(struct macb *bp)
 {
 	/* Make sure we have the write buffer for ourselves */
 	wmb();
 	/*
 	 * Disable RX and TX (XXX: Should we halt the transmission
 	 * more gracefully?)
 	 */
 	macb_writel(bp, NCR, 0);
 	/* Clear the stats registers (XXX: Update stats first?) */
 	macb_writel(bp, NCR, MACB_BIT(CLRSTAT));
 	/* Clear all status flags */
 	macb_writel(bp, TSR, ~0UL);
 	macb_writel(bp, RSR, ~0UL);
 	/* Disable all interrupts */
 	macb_writel(bp, IDR, ~0UL);
 	macb_readl(bp, ISR);
 }
 static void macb_init_hw(struct macb *bp)
 {
 	u32 config;
 	macb_reset_hw(bp);
 	__macb_set_hwaddr(bp);
 	config = macb_readl(bp, NCFGR) & MACB_BF(CLK, -1L);
 	config |= MACB_BIT(PAE);		/* PAuse Enable */
 	config |= MACB_BIT(DRFCS);		/* Discard Rx FCS */
 	if (bp->dev->flags & IFF_PROMISC)
 		config |= MACB_BIT(CAF);	/* Copy All Frames */
 	if (!(bp->dev->flags & IFF_BROADCAST))
 		config |= MACB_BIT(NBC);	/* No BroadCast */
 	macb_writel(bp, NCFGR, config);
 	/* Initialize TX and RX buffers */
 	macb_writel(bp, RBQP, bp->rx_ring_dma);
 	macb_writel(bp, TBQP, bp->tx_ring_dma);
 	/* Enable TX and RX */
 	macb_writel(bp, NCR, MACB_BIT(RE) | MACB_BIT(TE) | MACB_BIT(MPE));
 	/* Enable interrupts */
 	macb_writel(bp, IER, (MACB_BIT(RCOMP)
 			      | MACB_BIT(RXUBR)
 			      | MACB_BIT(ISR_TUND)
 			      | MACB_BIT(ISR_RLE)
 			      | MACB_BIT(TXERR)
 			      | MACB_BIT(TCOMP)
 			      | MACB_BIT(ISR_ROVR)
 			      | MACB_BIT(HRESP)));
 }
 /*
 * The hash address register is 64 bits long and takes up two
 * locations in the memory map.  The least significant bits are stored
 * in EMAC_HSL and the most significant bits in EMAC_HSH.
 *
 * The unicast hash enable and the multicast hash enable bits in the
 * network configuration register enable the reception of hash matched
 * frames. The destination address is reduced to a 6 bit index into
 * the 64 bit hash register using the following hash function.  The
 * hash function is an exclusive or of every sixth bit of the
 * destination address.
 *
 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
 *
 * da[0] represents the least significant bit of the first byte
 * received, that is, the multicast/unicast indicator, and da[47]
 * represents the most significant bit of the last byte received.  If
 * the hash index, hi[n], points to a bit that is set in the hash
 * register then the frame will be matched according to whether the
 * frame is multicast or unicast.  A multicast match will be signalled
 * if the multicast hash enable bit is set, da[0] is 1 and the hash
 * index points to a bit set in the hash register.  A unicast match
 * will be signalled if the unicast hash enable bit is set, da[0] is 0
 * and the hash index points to a bit set in the hash register.  To
 * receive all multicast frames, the hash register should be set with
 * all ones and the multicast hash enable bit should be set in the
 * network configuration register.
 */
 static inline int hash_bit_value(int bitnr, __u8 *addr)
 {
 	if (addr[bitnr / 8] & (1 << (bitnr % 8)))
 		return 1;
 	return 0;
 }
 /*
 * Return the hash index value for the specified address.
 */
 static int hash_get_index(__u8 *addr)
 {
 	int i, j, bitval;
 	int hash_index = 0;
 	for (j = 0; j < 6; j++) {
 		for (i = 0, bitval = 0; i < 8; i++)
 			bitval ^= hash_bit_value(i*6 + j, addr);
 		hash_index |= (bitval << j);
 	}
 	return hash_index;
 }
 /*
 * Add multicast addresses to the internal multicast-hash table.
 */
 static void macb_sethashtable(struct net_device *dev)
 {
 	struct dev_mc_list *curr;
 	unsigned long mc_filter[2];
 	unsigned int i, bitnr;
 	struct macb *bp = netdev_priv(dev);
 	mc_filter[0] = mc_filter[1] = 0;
 	curr = dev->mc_list;
 	for (i = 0; i < dev->mc_count; i++, curr = curr->next) {
 		if (!curr) break;	/* unexpected end of list */
 		bitnr = hash_get_index(curr->dmi_addr);
 		mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
 	}
 	macb_writel(bp, HRB, mc_filter[0]);
 	macb_writel(bp, HRT, mc_filter[1]);
 }
 /*
 * Enable/Disable promiscuous and multicast modes.
 */
 static void macb_set_rx_mode(struct net_device *dev)
 {
 	unsigned long cfg;
 	struct macb *bp = netdev_priv(dev);
 	cfg = macb_readl(bp, NCFGR);
 	if (dev->flags & IFF_PROMISC)
 		/* Enable promiscuous mode */
 		cfg |= MACB_BIT(CAF);
 	else if (dev->flags & (~IFF_PROMISC))
 		 /* Disable promiscuous mode */
 		cfg &= ~MACB_BIT(CAF);
 	if (dev->flags & IFF_ALLMULTI) {
 		/* Enable all multicast mode */
 		macb_writel(bp, HRB, -1);
 		macb_writel(bp, HRT, -1);
 		cfg |= MACB_BIT(NCFGR_MTI);
 	} else if (dev->mc_count > 0) {
 		/* Enable specific multicasts */
 		macb_sethashtable(dev);
 		cfg |= MACB_BIT(NCFGR_MTI);
 	} else if (dev->flags & (~IFF_ALLMULTI)) {
 		/* Disable all multicast mode */
 		macb_writel(bp, HRB, 0);
 		macb_writel(bp, HRT, 0);
 		cfg &= ~MACB_BIT(NCFGR_MTI);
 	}
 	macb_writel(bp, NCFGR, cfg);
 }
 static int macb_open(struct net_device *dev)
 {
 	struct macb *bp = netdev_priv(dev);
 	int err;
 	dev_dbg(&bp->pdev->dev, "open\n");
 	/* if the phy is not yet register, retry later*/
 	if (!bp->phy_dev)
 		return -EAGAIN;
 	if (!is_valid_ether_addr(dev->dev_addr))
 		return -EADDRNOTAVAIL;
 	err = macb_alloc_consistent(bp);
 	if (err) {
 		printk(KERN_ERR
 		       "%s: Unable to allocate DMA memory (error %d)\n",
 		       dev->name, err);
 		return err;
 	}
 	napi_enable(&bp->napi);
 	macb_init_rings(bp);
 	macb_init_hw(bp);
 	/* schedule a link state check */
 	phy_start(bp->phy_dev);
 	netif_start_queue(dev);
 	return 0;
 }
 static int macb_close(struct net_device *dev)
 {
 	struct macb *bp = netdev_priv(dev);
 	unsigned long flags;
 	netif_stop_queue(dev);
 	napi_disable(&bp->napi);
 	if (bp->phy_dev)
 		phy_stop(bp->phy_dev);
 	spin_lock_irqsave(&bp->lock, flags);
 	macb_reset_hw(bp);
 	netif_carrier_off(dev);
 	spin_unlock_irqrestore(&bp->lock, flags);
 	macb_free_consistent(bp);
 	return 0;
 }
 static struct net_device_stats *macb_get_stats(struct net_device *dev)
 {
 	struct macb *bp = netdev_priv(dev);
 	struct net_device_stats *nstat = &bp->stats;
 	struct macb_stats *hwstat = &bp->hw_stats;
 	/* read stats from hardware */
 	macb_update_stats(bp);
 	/* Convert HW stats into netdevice stats */
 	nstat->rx_errors = (hwstat->rx_fcs_errors +
 			    hwstat->rx_align_errors +
 			    hwstat->rx_resource_errors +
 			    hwstat->rx_overruns +
 			    hwstat->rx_oversize_pkts +
 			    hwstat->rx_jabbers +
 			    hwstat->rx_undersize_pkts +
 			    hwstat->sqe_test_errors +
 			    hwstat->rx_length_mismatch);
 	nstat->tx_errors = (hwstat->tx_late_cols +
 			    hwstat->tx_excessive_cols +
 			    hwstat->tx_underruns +
 			    hwstat->tx_carrier_errors);
 	nstat->collisions = (hwstat->tx_single_cols +
 			     hwstat->tx_multiple_cols +
 			     hwstat->tx_excessive_cols);
 	nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
 				   hwstat->rx_jabbers +
 				   hwstat->rx_undersize_pkts +
 				   hwstat->rx_length_mismatch);
 	nstat->rx_over_errors = hwstat->rx_resource_errors;
 	nstat->rx_crc_errors = hwstat->rx_fcs_errors;
 	nstat->rx_frame_errors = hwstat->rx_align_errors;
 	nstat->rx_fifo_errors = hwstat->rx_overruns;
 	/* XXX: What does "missed" mean? */
 	nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
 	nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
 	nstat->tx_fifo_errors = hwstat->tx_underruns;
 	/* Don't know about heartbeat or window errors... */
 	return nstat;
 }
 static int macb_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 {
 	struct macb *bp = netdev_priv(dev);
 	struct phy_device *phydev = bp->phy_dev;
 	if (!phydev)
 		return -ENODEV;
 	return phy_ethtool_gset(phydev, cmd);
 }
 static int macb_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 {
 	struct macb *bp = netdev_priv(dev);
 	struct phy_device *phydev = bp->phy_dev;
 	if (!phydev)
 		return -ENODEV;
 	return phy_ethtool_sset(phydev, cmd);
 }
 static void macb_get_drvinfo(struct net_device *dev,
 			     struct ethtool_drvinfo *info)
 {
 	struct macb *bp = netdev_priv(dev);
 	strcpy(info->driver, bp->pdev->dev.driver->name);
 	strcpy(info->version, "$Revision: 1.14 $");
 	strcpy(info->bus_info, dev_name(&bp->pdev->dev));
 }
 static const struct ethtool_ops macb_ethtool_ops = {
 	.get_settings		= macb_get_settings,
 	.set_settings		= macb_set_settings,
 	.get_drvinfo		= macb_get_drvinfo,
 	.get_link		= ethtool_op_get_link,
 };
 static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 {
 	struct macb *bp = netdev_priv(dev);
 	struct phy_device *phydev = bp->phy_dev;
 	if (!netif_running(dev))
 		return -EINVAL;
 	if (!phydev)
 		return -ENODEV;
 	return phy_mii_ioctl(phydev, if_mii(rq), cmd);
 }
 static const struct net_device_ops macb_netdev_ops = {
 	.ndo_open		= macb_open,
 	.ndo_stop		= macb_close,
 	.ndo_start_xmit		= macb_start_xmit,
 	.ndo_set_multicast_list	= macb_set_rx_mode,
 	.ndo_get_stats		= macb_get_stats,
 	.ndo_do_ioctl		= macb_ioctl,
 	.ndo_validate_addr	= eth_validate_addr,
 	.ndo_change_mtu		= eth_change_mtu,
 	.ndo_set_mac_address	= eth_mac_addr,
 #ifdef CONFIG_NET_POLL_CONTROLLER
 	.ndo_poll_controller	= macb_poll_controller,
 #endif
 };
 static int __init macb_probe(struct platform_device *pdev)
 {
 	struct eth_platform_data *pdata;
 	struct resource *regs;
 	struct net_device *dev;
 	struct macb *bp;
 	struct phy_device *phydev;
 	unsigned long pclk_hz;
 	u32 config;
 	int err = -ENXIO;
 	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (!regs) {
 		dev_err(&pdev->dev, "no mmio resource defined\n");
 		goto err_out;
 	}
 	err = -ENOMEM;
 	dev = alloc_etherdev(sizeof(*bp));
 	if (!dev) {
 		dev_err(&pdev->dev, "etherdev alloc failed, aborting.\n");
 		goto err_out;
 	}
 	SET_NETDEV_DEV(dev, &pdev->dev);
 	/* TODO: Actually, we have some interesting features... */
 	dev->features |= 0;
 	bp = netdev_priv(dev);
 	bp->pdev = pdev;
 	bp->dev = dev;
 	spin_lock_init(&bp->lock);
 #if defined(CONFIG_ARCH_AT91)
 	bp->pclk = clk_get(&pdev->dev, "macb_clk");
 	if (IS_ERR(bp->pclk)) {
 		dev_err(&pdev->dev, "failed to get macb_clk\n");
 		goto err_out_free_dev;
 	}
 	clk_enable(bp->pclk);
 #else
 	bp->pclk = clk_get(&pdev->dev, "pclk");
 	if (IS_ERR(bp->pclk)) {
 		dev_err(&pdev->dev, "failed to get pclk\n");
 		goto err_out_free_dev;
 	}
 	bp->hclk = clk_get(&pdev->dev, "hclk");
 	if (IS_ERR(bp->hclk)) {
 		dev_err(&pdev->dev, "failed to get hclk\n");
 		goto err_out_put_pclk;
 	}
 	clk_enable(bp->pclk);
 	clk_enable(bp->hclk);
 #endif
 	bp->regs = ioremap(regs->start, regs->end - regs->start + 1);
 	if (!bp->regs) {
 		dev_err(&pdev->dev, "failed to map registers, aborting.\n");
 		err = -ENOMEM;
 		goto err_out_disable_clocks;
 	}
 	dev->irq = platform_get_irq(pdev, 0);
 	err = request_irq(dev->irq, macb_interrupt, IRQF_SAMPLE_RANDOM,
 			  dev->name, dev);
 	if (err) {
 		printk(KERN_ERR
 		       "%s: Unable to request IRQ %d (error %d)\n",
 		       dev->name, dev->irq, err);
 		goto err_out_iounmap;
 	}
 	dev->netdev_ops = &macb_netdev_ops;
 	netif_napi_add(dev, &bp->napi, macb_poll, 64);
 	dev->ethtool_ops = &macb_ethtool_ops;
 	dev->base_addr = regs->start;
 	/* Set MII management clock divider */
 	pclk_hz = clk_get_rate(bp->pclk);
 	if (pclk_hz <= 20000000)
 		config = MACB_BF(CLK, MACB_CLK_DIV8);
 	else if (pclk_hz <= 40000000)
 		config = MACB_BF(CLK, MACB_CLK_DIV16);
 	else if (pclk_hz <= 80000000)
 		config = MACB_BF(CLK, MACB_CLK_DIV32);
 	else
 		config = MACB_BF(CLK, MACB_CLK_DIV64);
 	macb_writel(bp, NCFGR, config);
 	macb_get_hwaddr(bp);
 	pdata = pdev->dev.platform_data;
 	if (pdata && pdata->is_rmii)
 #if defined(CONFIG_ARCH_AT91)
 		macb_writel(bp, USRIO, (MACB_BIT(RMII) | MACB_BIT(CLKEN)) );
 #else
 		macb_writel(bp, USRIO, 0);
 #endif
 	else
 #if defined(CONFIG_ARCH_AT91)
 		macb_writel(bp, USRIO, MACB_BIT(CLKEN));
 #else
 		macb_writel(bp, USRIO, MACB_BIT(MII));
 #endif
 	bp->tx_pending = DEF_TX_RING_PENDING;
 	err = register_netdev(dev);
 	if (err) {
 		dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
 		goto err_out_free_irq;
 	}
 	if (macb_mii_init(bp) != 0) {
 		goto err_out_unregister_netdev;
 	}
 	platform_set_drvdata(pdev, dev);
 	printk(KERN_INFO "%s: Atmel MACB at 0x%08lx irq %d (%pM)\n",
 	       dev->name, dev->base_addr, dev->irq, dev->dev_addr);
 	phydev = bp->phy_dev;
 	printk(KERN_INFO "%s: attached PHY driver [%s] "
 		"(mii_bus:phy_addr=%s, irq=%d)\n", dev->name,
 		phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
 	return 0;
 err_out_unregister_netdev:
 	unregister_netdev(dev);
 err_out_free_irq:
 	free_irq(dev->irq, dev);
 err_out_iounmap:
 	iounmap(bp->regs);
 err_out_disable_clocks:
 #ifndef CONFIG_ARCH_AT91
 	clk_disable(bp->hclk);
 	clk_put(bp->hclk);
 #endif
 	clk_disable(bp->pclk);
 #ifndef CONFIG_ARCH_AT91
 err_out_put_pclk:
 #endif
 	clk_put(bp->pclk);
 err_out_free_dev:
 	free_netdev(dev);
 err_out:
 	platform_set_drvdata(pdev, NULL);
 	return err;
 }
 static int __exit macb_remove(struct platform_device *pdev)
 {
 	struct net_device *dev;
 	struct macb *bp;
 	dev = platform_get_drvdata(pdev);
 	if (dev) {
 		bp = netdev_priv(dev);
 		if (bp->phy_dev)
 			phy_disconnect(bp->phy_dev);
 		mdiobus_unregister(bp->mii_bus);
 		kfree(bp->mii_bus->irq);
 		mdiobus_free(bp->mii_bus);
 		unregister_netdev(dev);
 		free_irq(dev->irq, dev);
 		iounmap(bp->regs);
 #ifndef CONFIG_ARCH_AT91
 		clk_disable(bp->hclk);
 		clk_put(bp->hclk);
 #endif
 		clk_disable(bp->pclk);
 		clk_put(bp->pclk);
 		free_netdev(dev);
 		platform_set_drvdata(pdev, NULL);
 	}
 	return 0;
 }
 #ifdef CONFIG_PM
 static int macb_suspend(struct platform_device *pdev, pm_message_t state)
 {
 	struct net_device *netdev = platform_get_drvdata(pdev);
 	struct macb *bp = netdev_priv(netdev);
 	netif_device_detach(netdev);
 #ifndef CONFIG_ARCH_AT91
 	clk_disable(bp->hclk);
 #endif
 	clk_disable(bp->pclk);
 	return 0;
 }
 static int macb_resume(struct platform_device *pdev)
 {
 	struct net_device *netdev = platform_get_drvdata(pdev);
 	struct macb *bp = netdev_priv(netdev);
 	clk_enable(bp->pclk);
 #ifndef CONFIG_ARCH_AT91
 	clk_enable(bp->hclk);
 #endif
 	netif_device_attach(netdev);
 	return 0;
 }
 #else
 #define macb_suspend	NULL
 #define macb_resume	NULL
 #endif
 static struct platform_driver macb_driver = {
 	.remove		= __exit_p(macb_remove),
 	.suspend	= macb_suspend,
 	.resume		= macb_resume,
 	.driver		= {
 		.name		= "macb",
 		.owner	= THIS_MODULE,
 	},
 };
 static int __init macb_init(void)
 {
 	return platform_driver_probe(&macb_driver, macb_probe);
 }
 static void __exit macb_exit(void)
 {
 	platform_driver_unregister(&macb_driver);
 }
 module_init(macb_init);
 module_exit(macb_exit);
 MODULE_LICENSE("GPL");
 MODULE_DESCRIPTION("Atmel MACB Ethernet driver");
 MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>");
 MODULE_ALIAS("platform:macb");
 /*
 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
 * Copyright (c) 2007-2008 Michael Taylor <mike.taylor@apprion.com>
 *
 * Permission to use, copy, modify, and distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 *
 */
 /*
 * Register values for Atheros 5210/5211/5212 cards from OpenBSD's ar5k
 * maintained by Reyk Floeter
 *
 * I tried to document those registers by looking at ar5k code, some
 * 802.11 (802.11e mostly) papers and by reading various public available
 * Atheros presentations and papers like these:
 *
 * 5210 - http://nova.stanford.edu/~bbaas/ps/isscc2002_slides.pdf
 *        http://www.it.iitb.ac.in/~janak/wifire/01222734.pdf
 *
 * 5211 - http://www.hotchips.org/archives/hc14/3_Tue/16_mcfarland.pdf
 *
 * This file also contains register values found on a memory dump of
 * Atheros's ART program (Atheros Radio Test), on ath9k, on legacy-hal
 * released by Atheros and on various debug messages found on the net.
 */
 /*====MAC DMA REGISTERS====*/
 /*
 * AR5210-Specific TXDP registers
 * 5210 has only 2 transmit queues so no DCU/QCU, just
 * 2 transmit descriptor pointers...
 */
 #define AR5K_NOQCU_TXDP0	0x0000		/* Queue 0 - data */
 #define AR5K_NOQCU_TXDP1	0x0004		/* Queue 1 - beacons */
 /*
 * Mac Control Register
 */
 #define	AR5K_CR		0x0008			/* Register Address */
 #define AR5K_CR_TXE0	0x00000001	/* TX Enable for queue 0 on 5210 */
 #define AR5K_CR_TXE1	0x00000002	/* TX Enable for queue 1 on 5210 */
 #define	AR5K_CR_RXE	0x00000004	/* RX Enable */
 #define AR5K_CR_TXD0	0x00000008	/* TX Disable for queue 0 on 5210 */
 #define AR5K_CR_TXD1	0x00000010	/* TX Disable for queue 1 on 5210 */
 #define	AR5K_CR_RXD	0x00000020	/* RX Disable */
 #define	AR5K_CR_SWI	0x00000040	/* Software Interrupt */
 /*
 * RX Descriptor Pointer register
 */
 #define	AR5K_RXDP	0x000c
 /*
 * Configuration and status register
 */
 #define	AR5K_CFG		0x0014			/* Register Address */
 #define	AR5K_CFG_SWTD		0x00000001	/* Byte-swap TX descriptor (for big endian archs) */
 #define	AR5K_CFG_SWTB		0x00000002	/* Byte-swap TX buffer */
 #define	AR5K_CFG_SWRD		0x00000004	/* Byte-swap RX descriptor */
 #define	AR5K_CFG_SWRB		0x00000008	/* Byte-swap RX buffer */
 #define	AR5K_CFG_SWRG		0x00000010	/* Byte-swap Register access */
 #define AR5K_CFG_IBSS		0x00000020 	/* 0-BSS, 1-IBSS [5211+] */
 #define AR5K_CFG_PHY_OK		0x00000100	/* [5211+] */
 #define AR5K_CFG_EEBS		0x00000200	/* EEPROM is busy */
 #define	AR5K_CFG_CLKGD		0x00000400	/* Clock gated (Disable dynamic clock) */
 #define AR5K_CFG_TXCNT		0x00007800	/* Tx frame count (?) [5210] */
 #define AR5K_CFG_TXCNT_S	11
 #define AR5K_CFG_TXFSTAT	0x00008000	/* Tx frame status (?) [5210] */
 #define AR5K_CFG_TXFSTRT	0x00010000	/* [5210] */
 #define	AR5K_CFG_PCI_THRES	0x00060000	/* PCI Master req q threshold [5211+] */
 #define	AR5K_CFG_PCI_THRES_S	17
 /*
 * Interrupt enable register
 */
 #define AR5K_IER		0x0024		/* Register Address */
 #define AR5K_IER_DISABLE	0x00000000	/* Disable card interrupts */
 #define AR5K_IER_ENABLE		0x00000001	/* Enable card interrupts */
 /*
 * 0x0028 is Beacon Control Register on 5210
 * and first RTS duration register on 5211
 */
 /*
 * Beacon control register [5210]
 */
 #define AR5K_BCR		0x0028		/* Register Address */
 #define AR5K_BCR_AP		0x00000000	/* AP mode */
 #define AR5K_BCR_ADHOC		0x00000001	/* Ad-Hoc mode */
 #define AR5K_BCR_BDMAE		0x00000002	/* DMA enable */
 #define AR5K_BCR_TQ1FV		0x00000004	/* Use Queue1 for CAB traffic */
 #define AR5K_BCR_TQ1V		0x00000008	/* Use Queue1 for Beacon traffic */
 #define AR5K_BCR_BCGET		0x00000010
 /*
 * First RTS duration register [5211]
 */
 #define AR5K_RTSD0		0x0028		/* Register Address */
 #define	AR5K_RTSD0_6		0x000000ff	/* 6Mb RTS duration mask (?) */
 #define	AR5K_RTSD0_6_S		0		/* 6Mb RTS duration shift (?) */
 #define	AR5K_RTSD0_9		0x0000ff00	/* 9Mb*/
 #define	AR5K_RTSD0_9_S		8
 #define	AR5K_RTSD0_12		0x00ff0000	/* 12Mb*/
 #define	AR5K_RTSD0_12_S		16
 #define	AR5K_RTSD0_18		0xff000000	/* 16Mb*/
 #define	AR5K_RTSD0_18_S		24
 /*
 * 0x002c is Beacon Status Register on 5210
 * and second RTS duration register on 5211
 */
 /*
 * Beacon status register [5210]
 *
 * As i can see in ar5k_ar5210_tx_start Reyk uses some of the values of BCR
 * for this register, so i guess TQ1V,TQ1FV and BDMAE have the same meaning
 * here and SNP/SNAP means "snapshot" (so this register gets synced with BCR).
 * So SNAPPEDBCRVALID sould also stand for "snapped BCR -values- valid", so i
 * renamed it to SNAPSHOTSVALID to make more sense. I realy have no idea what
 * else can it be. I also renamed SNPBCMD to SNPADHOC to match BCR.
 */
 #define AR5K_BSR		0x002c			/* Register Address */
 #define AR5K_BSR_BDLYSW		0x00000001	/* SW Beacon delay (?) */
 #define AR5K_BSR_BDLYDMA	0x00000002	/* DMA Beacon delay (?) */
 #define AR5K_BSR_TXQ1F		0x00000004	/* Beacon queue (1) finished */
 #define AR5K_BSR_ATIMDLY	0x00000008	/* ATIM delay (?) */
 #define AR5K_BSR_SNPADHOC	0x00000100	/* Ad-hoc mode set (?) */
 #define AR5K_BSR_SNPBDMAE	0x00000200	/* Beacon DMA enabled (?) */
 #define AR5K_BSR_SNPTQ1FV	0x00000400	/* Queue1 is used for CAB traffic (?) */
 #define AR5K_BSR_SNPTQ1V	0x00000800	/* Queue1 is used for Beacon traffic (?) */
 #define AR5K_BSR_SNAPSHOTSVALID	0x00001000	/* BCR snapshots are valid (?) */
 #define AR5K_BSR_SWBA_CNT	0x00ff0000
 /*
 * Second RTS duration register [5211]
 */
 #define AR5K_RTSD1		0x002c			/* Register Address */
 #define	AR5K_RTSD1_24		0x000000ff	/* 24Mb */
 #define	AR5K_RTSD1_24_S		0
 #define	AR5K_RTSD1_36		0x0000ff00	/* 36Mb */
 #define	AR5K_RTSD1_36_S		8
 #define	AR5K_RTSD1_48		0x00ff0000	/* 48Mb */
 #define	AR5K_RTSD1_48_S		16
 #define	AR5K_RTSD1_54		0xff000000	/* 54Mb */
 #define	AR5K_RTSD1_54_S		24
 /*
 * Transmit configuration register
 */
 #define AR5K_TXCFG			0x0030			/* Register Address */
 #define AR5K_TXCFG_SDMAMR		0x00000007	/* DMA size (read) */
 #define AR5K_TXCFG_SDMAMR_S		0
 #define AR5K_TXCFG_B_MODE		0x00000008	/* Set b mode for 5111 (enable 2111) */
 #define AR5K_TXCFG_TXFSTP		0x00000008	/* TX DMA full Stop [5210] */
 #define AR5K_TXCFG_TXFULL		0x000003f0	/* TX Triger level mask */
 #define AR5K_TXCFG_TXFULL_S		4
 #define AR5K_TXCFG_TXFULL_0B		0x00000000
 #define AR5K_TXCFG_TXFULL_64B		0x00000010
 #define AR5K_TXCFG_TXFULL_128B		0x00000020
 #define AR5K_TXCFG_TXFULL_192B		0x00000030
 #define AR5K_TXCFG_TXFULL_256B		0x00000040
 #define AR5K_TXCFG_TXCONT_EN		0x00000080
 #define AR5K_TXCFG_DMASIZE		0x00000100	/* Flag for passing DMA size [5210] */
 #define AR5K_TXCFG_JUMBO_DESC_EN	0x00000400	/* Enable jumbo tx descriptors [5211+] */
 #define AR5K_TXCFG_ADHOC_BCN_ATIM	0x00000800	/* Adhoc Beacon ATIM Policy */
 #define AR5K_TXCFG_ATIM_WINDOW_DEF_DIS	0x00001000	/* Disable ATIM window defer [5211+] */
 #define AR5K_TXCFG_RTSRND		0x00001000	/* [5211+] */
 #define AR5K_TXCFG_FRMPAD_DIS		0x00002000	/* [5211+] */
 #define AR5K_TXCFG_RDY_CBR_DIS		0x00004000	/* Ready time CBR disable [5211+] */
 #define AR5K_TXCFG_JUMBO_FRM_MODE	0x00008000	/* Jumbo frame mode [5211+] */
 #define	AR5K_TXCFG_DCU_DBL_BUF_DIS	0x00008000	/* Disable double buffering on DCU */
 #define AR5K_TXCFG_DCU_CACHING_DIS	0x00010000	/* Disable DCU caching */
 /*
 * Receive configuration register
 */
 #define AR5K_RXCFG		0x0034			/* Register Address */
 #define AR5K_RXCFG_SDMAMW	0x00000007	/* DMA size (write) */
 #define AR5K_RXCFG_SDMAMW_S	0
 #define AR5K_RXCFG_ZLFDMA	0x00000008	/* Enable Zero-length frame DMA */
 #define	AR5K_RXCFG_DEF_ANTENNA	0x00000010	/* Default antenna (?) */
 #define AR5K_RXCFG_JUMBO_RXE	0x00000020	/* Enable jumbo rx descriptors [5211+] */
 #define AR5K_RXCFG_JUMBO_WRAP	0x00000040	/* Wrap jumbo frames [5211+] */
 #define AR5K_RXCFG_SLE_ENTRY	0x00000080	/* Sleep entry policy */
 /*
 * Receive jumbo descriptor last address register
 * Only found in 5211 (?)
 */
 #define AR5K_RXJLA		0x0038
 /*
 * MIB control register
 */
 #define AR5K_MIBC		0x0040			/* Register Address */
 #define AR5K_MIBC_COW		0x00000001	/* Warn test indicator */
 #define AR5K_MIBC_FMC		0x00000002	/* Freeze MIB Counters  */
 #define AR5K_MIBC_CMC		0x00000004	/* Clean MIB Counters  */
 #define AR5K_MIBC_MCS		0x00000008	/* MIB counter strobe */
 /*
 * Timeout prescale register
 */
 #define AR5K_TOPS		0x0044
 #define	AR5K_TOPS_M		0x0000ffff
 /*
 * Receive timeout register (no frame received)
 */
 #define AR5K_RXNOFRM		0x0048
 #define	AR5K_RXNOFRM_M		0x000003ff
 /*
 * Transmit timeout register (no frame sent)
 */
 #define AR5K_TXNOFRM		0x004c
 #define	AR5K_TXNOFRM_M		0x000003ff
 #define	AR5K_TXNOFRM_QCU	0x000ffc00
 #define	AR5K_TXNOFRM_QCU_S	10
 /*
 * Receive frame gap timeout register
 */
 #define AR5K_RPGTO		0x0050
 #define AR5K_RPGTO_M		0x000003ff
 /*
 * Receive frame count limit register
 */
 #define AR5K_RFCNT		0x0054
 #define AR5K_RFCNT_M		0x0000001f	/* [5211+] (?) */
 #define AR5K_RFCNT_RFCL		0x0000000f	/* [5210] */
 /*
 * Misc settings register
 * (reserved0-3)
 */
 #define AR5K_MISC		0x0058			/* Register Address */
 #define	AR5K_MISC_DMA_OBS_M	0x000001e0
 #define	AR5K_MISC_DMA_OBS_S	5
 #define	AR5K_MISC_MISC_OBS_M	0x00000e00
 #define	AR5K_MISC_MISC_OBS_S	9
 #define	AR5K_MISC_MAC_OBS_LSB_M	0x00007000
 #define	AR5K_MISC_MAC_OBS_LSB_S	12
 #define	AR5K_MISC_MAC_OBS_MSB_M	0x00038000
 #define	AR5K_MISC_MAC_OBS_MSB_S	15
 #define AR5K_MISC_LED_DECAY	0x001c0000	/* [5210] */
 #define AR5K_MISC_LED_BLINK	0x00e00000	/* [5210] */
 /*
 * QCU/DCU clock gating register (5311)
 * (reserved4-5)
 */
 #define	AR5K_QCUDCU_CLKGT	0x005c			/* Register Address (?) */
 #define	AR5K_QCUDCU_CLKGT_QCU	0x0000ffff	/* Mask for QCU clock */
 #define	AR5K_QCUDCU_CLKGT_DCU	0x07ff0000	/* Mask for DCU clock */
 /*
 * Interrupt Status Registers
 *
 * For 5210 there is only one status register but for
 * 5211/5212 we have one primary and 4 secondary registers.
 * So we have AR5K_ISR for 5210 and AR5K_PISR /SISRx for 5211/5212.
 * Most of these bits are common for all chipsets.
 */
 #define AR5K_ISR		0x001c			/* Register Address [5210] */
 #define AR5K_PISR		0x0080			/* Register Address [5211+] */
 #define AR5K_ISR_RXOK		0x00000001	/* Frame successfuly recieved */
 #define AR5K_ISR_RXDESC		0x00000002	/* RX descriptor request */
 #define AR5K_ISR_RXERR		0x00000004	/* Receive error */
 #define AR5K_ISR_RXNOFRM	0x00000008	/* No frame received (receive timeout) */
 #define AR5K_ISR_RXEOL		0x00000010	/* Empty RX descriptor */
 #define AR5K_ISR_RXORN		0x00000020	/* Receive FIFO overrun */
 #define AR5K_ISR_TXOK		0x00000040	/* Frame successfuly transmited */
 #define AR5K_ISR_TXDESC		0x00000080	/* TX descriptor request */
 #define AR5K_ISR_TXERR		0x00000100	/* Transmit error */
 #define AR5K_ISR_TXNOFRM	0x00000200	/* No frame transmited (transmit timeout) */
 #define AR5K_ISR_TXEOL		0x00000400	/* Empty TX descriptor */
 #define AR5K_ISR_TXURN		0x00000800	/* Transmit FIFO underrun */
 #define AR5K_ISR_MIB		0x00001000	/* Update MIB counters */
 #define AR5K_ISR_SWI		0x00002000	/* Software interrupt */
 #define AR5K_ISR_RXPHY		0x00004000	/* PHY error */
 #define AR5K_ISR_RXKCM		0x00008000	/* RX Key cache miss */
 #define AR5K_ISR_SWBA		0x00010000	/* Software beacon alert */
 #define AR5K_ISR_BRSSI		0x00020000	/* Beacon rssi below threshold (?) */
 #define AR5K_ISR_BMISS		0x00040000	/* Beacon missed */
 #define AR5K_ISR_HIUERR		0x00080000	/* Host Interface Unit error [5211+] */
 #define AR5K_ISR_BNR		0x00100000 	/* Beacon not ready [5211+] */
 #define AR5K_ISR_MCABT		0x00100000	/* Master Cycle Abort [5210] */
 #define AR5K_ISR_RXCHIRP	0x00200000	/* CHIRP Received [5212+] */
 #define AR5K_ISR_SSERR		0x00200000	/* Signaled System Error [5210] */
 #define AR5K_ISR_DPERR		0x00400000	/* Det par Error (?) [5210] */
 #define AR5K_ISR_RXDOPPLER	0x00400000	/* Doppler chirp received [5212+] */
 #define AR5K_ISR_TIM		0x00800000	/* [5211+] */
 #define AR5K_ISR_BCNMISC	0x00800000	/* 'or' of TIM, CAB_END, DTIM_SYNC, BCN_TIMEOUT,
 						CAB_TIMEOUT and DTIM bits from SISR2 [5212+] */
 #define AR5K_ISR_GPIO		0x01000000	/* GPIO (rf kill) */
 #define AR5K_ISR_QCBRORN	0x02000000	/* QCU CBR overrun [5211+] */
 #define AR5K_ISR_QCBRURN	0x04000000	/* QCU CBR underrun [5211+] */
 #define AR5K_ISR_QTRIG		0x08000000	/* QCU scheduling trigger [5211+] */
 /*
 * Secondary status registers [5211+] (0 - 4)
 *
 * These give the status for each QCU, only QCUs 0-9 are
 * represented.
 */
 #define AR5K_SISR0		0x0084			/* Register Address [5211+] */
 #define AR5K_SISR0_QCU_TXOK	0x000003ff	/* Mask for QCU_TXOK */
 #define AR5K_SISR0_QCU_TXOK_S	0
 #define AR5K_SISR0_QCU_TXDESC	0x03ff0000	/* Mask for QCU_TXDESC */
 #define AR5K_SISR0_QCU_TXDESC_S	16
 #define AR5K_SISR1		0x0088			/* Register Address [5211+] */
 #define AR5K_SISR1_QCU_TXERR	0x000003ff	/* Mask for QCU_TXERR */
 #define AR5K_SISR1_QCU_TXERR_S	0
 #define AR5K_SISR1_QCU_TXEOL	0x03ff0000	/* Mask for QCU_TXEOL */
 #define AR5K_SISR1_QCU_TXEOL_S	16
 #define AR5K_SISR2		0x008c			/* Register Address [5211+] */
 #define AR5K_SISR2_QCU_TXURN	0x000003ff	/* Mask for QCU_TXURN */
 #define	AR5K_SISR2_QCU_TXURN_S	0
 #define	AR5K_SISR2_MCABT	0x00010000	/* Master Cycle Abort */
 #define	AR5K_SISR2_SSERR	0x00020000	/* Signaled System Error */
 #define	AR5K_SISR2_DPERR	0x00040000	/* Bus parity error */
 #define	AR5K_SISR2_TIM		0x01000000	/* [5212+] */
 #define	AR5K_SISR2_CAB_END	0x02000000	/* [5212+] */
 #define	AR5K_SISR2_DTIM_SYNC	0x04000000	/* DTIM sync lost [5212+] */
 #define	AR5K_SISR2_BCN_TIMEOUT	0x08000000	/* Beacon Timeout [5212+] */
 #define	AR5K_SISR2_CAB_TIMEOUT	0x10000000	/* CAB Timeout [5212+] */
 #define	AR5K_SISR2_DTIM		0x20000000	/* [5212+] */
 #define	AR5K_SISR2_TSFOOR	0x80000000	/* TSF OOR (?) */
 #define AR5K_SISR3		0x0090			/* Register Address [5211+] */
 #define AR5K_SISR3_QCBRORN	0x000003ff	/* Mask for QCBRORN */
 #define AR5K_SISR3_QCBRORN_S	0
 #define AR5K_SISR3_QCBRURN	0x03ff0000	/* Mask for QCBRURN */
 #define AR5K_SISR3_QCBRURN_S	16
 #define AR5K_SISR4		0x0094			/* Register Address [5211+] */
 #define AR5K_SISR4_QTRIG	0x000003ff	/* Mask for QTRIG */
 #define AR5K_SISR4_QTRIG_S	0
 /*
 * Shadow read-and-clear interrupt status registers [5211+]
 */
 #define AR5K_RAC_PISR		0x00c0		/* Read and clear PISR */
 #define AR5K_RAC_SISR0		0x00c4		/* Read and clear SISR0 */
 #define AR5K_RAC_SISR1		0x00c8		/* Read and clear SISR1 */
 #define AR5K_RAC_SISR2		0x00cc		/* Read and clear SISR2 */
 #define AR5K_RAC_SISR3		0x00d0		/* Read and clear SISR3 */
 #define AR5K_RAC_SISR4		0x00d4		/* Read and clear SISR4 */
 /*
 * Interrupt Mask Registers
 *
 * As whith ISRs 5210 has one IMR (AR5K_IMR) and 5211/5212 has one primary
 * (AR5K_PIMR) and 4 secondary IMRs (AR5K_SIMRx). Note that ISR/IMR flags match.
 */
 #define	AR5K_IMR		0x0020			/* Register Address [5210] */
 #define AR5K_PIMR		0x00a0			/* Register Address [5211+] */
 #define AR5K_IMR_RXOK		0x00000001	/* Frame successfuly recieved*/
 #define AR5K_IMR_RXDESC		0x00000002	/* RX descriptor request*/
 #define AR5K_IMR_RXERR		0x00000004	/* Receive error*/
 #define AR5K_IMR_RXNOFRM	0x00000008	/* No frame received (receive timeout)*/
 #define AR5K_IMR_RXEOL		0x00000010	/* Empty RX descriptor*/
 #define AR5K_IMR_RXORN		0x00000020	/* Receive FIFO overrun*/
 #define AR5K_IMR_TXOK		0x00000040	/* Frame successfuly transmited*/
 #define AR5K_IMR_TXDESC		0x00000080	/* TX descriptor request*/
 #define AR5K_IMR_TXERR		0x00000100	/* Transmit error*/
 #define AR5K_IMR_TXNOFRM	0x00000200	/* No frame transmited (transmit timeout)*/
 #define AR5K_IMR_TXEOL		0x00000400	/* Empty TX descriptor*/
 #define AR5K_IMR_TXURN		0x00000800	/* Transmit FIFO underrun*/
 #define AR5K_IMR_MIB		0x00001000	/* Update MIB counters*/
 #define AR5K_IMR_SWI		0x00002000	/* Software interrupt */
 #define AR5K_IMR_RXPHY		0x00004000	/* PHY error*/
 #define AR5K_IMR_RXKCM		0x00008000	/* RX Key cache miss */
 #define AR5K_IMR_SWBA		0x00010000	/* Software beacon alert*/
 #define AR5K_IMR_BRSSI		0x00020000	/* Beacon rssi below threshold (?) */
 #define AR5K_IMR_BMISS		0x00040000	/* Beacon missed*/
 #define AR5K_IMR_HIUERR		0x00080000	/* Host Interface Unit error [5211+] */
 #define AR5K_IMR_BNR		0x00100000 	/* Beacon not ready [5211+] */
 #define AR5K_IMR_MCABT		0x00100000	/* Master Cycle Abort [5210] */
 #define AR5K_IMR_RXCHIRP	0x00200000	/* CHIRP Received [5212+]*/
 #define AR5K_IMR_SSERR		0x00200000	/* Signaled System Error [5210] */
 #define AR5K_IMR_DPERR		0x00400000	/* Det par Error (?) [5210] */
 #define AR5K_IMR_RXDOPPLER	0x00400000	/* Doppler chirp received [5212+] */
 #define AR5K_IMR_TIM		0x00800000	/* [5211+] */
 #define AR5K_IMR_BCNMISC	0x00800000	/* 'or' of TIM, CAB_END, DTIM_SYNC, BCN_TIMEOUT,
 						CAB_TIMEOUT and DTIM bits from SISR2 [5212+] */
 #define AR5K_IMR_GPIO		0x01000000	/* GPIO (rf kill)*/
 #define AR5K_IMR_QCBRORN	0x02000000	/* QCU CBR overrun (?) [5211+] */
 #define AR5K_IMR_QCBRURN	0x04000000	/* QCU CBR underrun (?) [5211+] */
 #define AR5K_IMR_QTRIG		0x08000000	/* QCU scheduling trigger [5211+] */
 /*
 * Secondary interrupt mask registers [5211+] (0 - 4)
 */
 #define AR5K_SIMR0		0x00a4			/* Register Address [5211+] */
 #define AR5K_SIMR0_QCU_TXOK	0x000003ff	/* Mask for QCU_TXOK */
 #define AR5K_SIMR0_QCU_TXOK_S	0
 #define AR5K_SIMR0_QCU_TXDESC	0x03ff0000	/* Mask for QCU_TXDESC */
 #define AR5K_SIMR0_QCU_TXDESC_S	16
 #define AR5K_SIMR1		0x00a8			/* Register Address [5211+] */
 #define AR5K_SIMR1_QCU_TXERR	0x000003ff	/* Mask for QCU_TXERR */
 #define AR5K_SIMR1_QCU_TXERR_S	0
 #define AR5K_SIMR1_QCU_TXEOL	0x03ff0000	/* Mask for QCU_TXEOL */
 #define AR5K_SIMR1_QCU_TXEOL_S	16
 #define AR5K_SIMR2		0x00ac			/* Register Address [5211+] */
 #define AR5K_SIMR2_QCU_TXURN	0x000003ff	/* Mask for QCU_TXURN */
 #define AR5K_SIMR2_QCU_TXURN_S	0
 #define	AR5K_SIMR2_MCABT	0x00010000	/* Master Cycle Abort */
 #define	AR5K_SIMR2_SSERR	0x00020000	/* Signaled System Error */
 #define	AR5K_SIMR2_DPERR	0x00040000	/* Bus parity error */
 #define	AR5K_SIMR2_TIM		0x01000000	/* [5212+] */
 #define	AR5K_SIMR2_CAB_END	0x02000000	/* [5212+] */
 #define	AR5K_SIMR2_DTIM_SYNC	0x04000000	/* DTIM Sync lost [5212+] */
 #define	AR5K_SIMR2_BCN_TIMEOUT	0x08000000	/* Beacon Timeout [5212+] */
 #define	AR5K_SIMR2_CAB_TIMEOUT	0x10000000	/* CAB Timeout [5212+] */
 #define	AR5K_SIMR2_DTIM		0x20000000	/* [5212+] */
 #define	AR5K_SIMR2_TSFOOR	0x80000000	/* TSF OOR (?) */
 #define AR5K_SIMR3		0x00b0			/* Register Address [5211+] */
 #define AR5K_SIMR3_QCBRORN	0x000003ff	/* Mask for QCBRORN */
 #define AR5K_SIMR3_QCBRORN_S	0
 #define AR5K_SIMR3_QCBRURN	0x03ff0000	/* Mask for QCBRURN */
 #define AR5K_SIMR3_QCBRURN_S	16
 #define AR5K_SIMR4		0x00b4			/* Register Address [5211+] */
 #define AR5K_SIMR4_QTRIG	0x000003ff	/* Mask for QTRIG */
 #define AR5K_SIMR4_QTRIG_S	0
 /*
 * DMA Debug registers 0-7
 * 0xe0 - 0xfc
 */
 /*
 * Decompression mask registers [5212+]
 */
 #define AR5K_DCM_ADDR		0x0400		/*Decompression mask address (index) */
 #define AR5K_DCM_DATA		0x0404		/*Decompression mask data */
 /*
 * Wake On Wireless pattern control register [5212+]
 */
 #define	AR5K_WOW_PCFG			0x0410			/* Register Address */
 #define	AR5K_WOW_PCFG_PAT_MATCH_EN	0x00000001	/* Pattern match enable */
 #define	AR5K_WOW_PCFG_LONG_FRAME_POL	0x00000002	/* Long frame policy */
 #define	AR5K_WOW_PCFG_WOBMISS		0x00000004	/* Wake on bea(con) miss (?) */
 #define	AR5K_WOW_PCFG_PAT_0_EN		0x00000100	/* Enable pattern 0 */
 #define	AR5K_WOW_PCFG_PAT_1_EN		0x00000200	/* Enable pattern 1 */
 #define	AR5K_WOW_PCFG_PAT_2_EN		0x00000400	/* Enable pattern 2 */
 #define	AR5K_WOW_PCFG_PAT_3_EN		0x00000800	/* Enable pattern 3 */
 #define	AR5K_WOW_PCFG_PAT_4_EN		0x00001000	/* Enable pattern 4 */
 #define	AR5K_WOW_PCFG_PAT_5_EN		0x00002000	/* Enable pattern 5 */
 /*
 * Wake On Wireless pattern index register (?) [5212+]
 */
 #define	AR5K_WOW_PAT_IDX	0x0414
 /*
 * Wake On Wireless pattern data register [5212+]
 */
 #define	AR5K_WOW_PAT_DATA	0x0418			/* Register Address */
 #define	AR5K_WOW_PAT_DATA_0_3_V	0x00000001	/* Pattern 0, 3 value */
 #define	AR5K_WOW_PAT_DATA_1_4_V	0x00000100	/* Pattern 1, 4 value */
 #define	AR5K_WOW_PAT_DATA_2_5_V	0x00010000	/* Pattern 2, 5 value */
 #define	AR5K_WOW_PAT_DATA_0_3_M	0x01000000	/* Pattern 0, 3 mask */
 #define	AR5K_WOW_PAT_DATA_1_4_M	0x04000000	/* Pattern 1, 4 mask */
 #define	AR5K_WOW_PAT_DATA_2_5_M	0x10000000	/* Pattern 2, 5 mask */
 /*
 * Decompression configuration registers [5212+]
 */
 #define AR5K_DCCFG		0x0420			/* Register Address */
 #define AR5K_DCCFG_GLOBAL_EN	0x00000001	/* Enable decompression on all queues */
 #define AR5K_DCCFG_BYPASS_EN	0x00000002	/* Bypass decompression */
 #define AR5K_DCCFG_BCAST_EN	0x00000004	/* Enable decompression for bcast frames */
 #define AR5K_DCCFG_MCAST_EN	0x00000008	/* Enable decompression for mcast frames */
 /*
 * Compression configuration registers [5212+]
 */
 #define AR5K_CCFG		0x0600			/* Register Address */
 #define	AR5K_CCFG_WINDOW_SIZE	0x00000007	/* Compression window size */
 #define	AR5K_CCFG_CPC_EN	0x00000008	/* Enable performance counters */
 #define AR5K_CCFG_CCU		0x0604			/* Register Address */
 #define AR5K_CCFG_CCU_CUP_EN	0x00000001	/* CCU Catchup enable */
 #define AR5K_CCFG_CCU_CREDIT	0x00000002	/* CCU Credit (field) */
 #define AR5K_CCFG_CCU_CD_THRES	0x00000080	/* CCU Cyc(lic?) debt threshold (field) */
 #define AR5K_CCFG_CCU_CUP_LCNT	0x00010000	/* CCU Catchup lit(?) count */
 #define	AR5K_CCFG_CCU_INIT	0x00100200	/* Initial value during reset */
 /*
 * Compression performance counter registers [5212+]
 */
 #define AR5K_CPC0		0x0610		/* Compression performance counter 0 */
 #define AR5K_CPC1		0x0614		/* Compression performance counter 1*/
 #define AR5K_CPC2		0x0618		/* Compression performance counter 2 */
 #define AR5K_CPC3		0x061c		/* Compression performance counter 3 */
 #define AR5K_CPCOVF		0x0620		/* Compression performance overflow */
 /*
 * Queue control unit (QCU) registers [5211+]
 *
 * Card has 12 TX Queues but i see that only 0-9 are used (?)
 * both in binary HAL (see ah.h) and ar5k. Each queue has it's own
 * TXDP at addresses 0x0800 - 0x082c, a CBR (Constant Bit Rate)
 * configuration register (0x08c0 - 0x08ec), a ready time configuration
 * register (0x0900 - 0x092c), a misc configuration register (0x09c0 -
 * 0x09ec) and a status register (0x0a00 - 0x0a2c). We also have some
 * global registers, QCU transmit enable/disable and "one shot arm (?)"
 * set/clear, which contain status for all queues (we shift by 1 for each
 * queue). To access these registers easily we define some macros here
 * that are used inside HAL. For more infos check out *_tx_queue functs.
 */
 /*
 * Generic QCU Register access macros
 */
 #define	AR5K_QUEUE_REG(_r, _q)		(((_q) << 2) + _r)
 #define AR5K_QCU_GLOBAL_READ(_r, _q)	(AR5K_REG_READ(_r) & (1 << _q))
 #define AR5K_QCU_GLOBAL_WRITE(_r, _q)	AR5K_REG_WRITE(_r, (1 << _q))
 /*
 * QCU Transmit descriptor pointer registers
 */
 #define AR5K_QCU_TXDP_BASE	0x0800		/* Register Address - Queue0 TXDP */
 #define AR5K_QUEUE_TXDP(_q)	AR5K_QUEUE_REG(AR5K_QCU_TXDP_BASE, _q)
 /*
 * QCU Transmit enable register
 */
 #define AR5K_QCU_TXE		0x0840
 #define AR5K_ENABLE_QUEUE(_q)	AR5K_QCU_GLOBAL_WRITE(AR5K_QCU_TXE, _q)
 #define AR5K_QUEUE_ENABLED(_q)	AR5K_QCU_GLOBAL_READ(AR5K_QCU_TXE, _q)
 /*
 * QCU Transmit disable register
 */
 #define AR5K_QCU_TXD		0x0880
 #define AR5K_DISABLE_QUEUE(_q)	AR5K_QCU_GLOBAL_WRITE(AR5K_QCU_TXD, _q)
 #define AR5K_QUEUE_DISABLED(_q)	AR5K_QCU_GLOBAL_READ(AR5K_QCU_TXD, _q)
 /*
 * QCU Constant Bit Rate configuration registers
 */
 #define	AR5K_QCU_CBRCFG_BASE		0x08c0	/* Register Address - Queue0 CBRCFG */
 #define	AR5K_QCU_CBRCFG_INTVAL		0x00ffffff	/* CBR Interval mask */
 #define AR5K_QCU_CBRCFG_INTVAL_S	0
 #define	AR5K_QCU_CBRCFG_ORN_THRES	0xff000000	/* CBR overrun threshold mask */
 #define AR5K_QCU_CBRCFG_ORN_THRES_S	24
 #define	AR5K_QUEUE_CBRCFG(_q)		AR5K_QUEUE_REG(AR5K_QCU_CBRCFG_BASE, _q)
 /*
 * QCU Ready time configuration registers
 */
 #define	AR5K_QCU_RDYTIMECFG_BASE	0x0900	/* Register Address - Queue0 RDYTIMECFG */
 #define	AR5K_QCU_RDYTIMECFG_INTVAL	0x00ffffff	/* Ready time interval mask */
 #define AR5K_QCU_RDYTIMECFG_INTVAL_S	0
 #define	AR5K_QCU_RDYTIMECFG_ENABLE	0x01000000	/* Ready time enable mask */
 #define AR5K_QUEUE_RDYTIMECFG(_q)	AR5K_QUEUE_REG(AR5K_QCU_RDYTIMECFG_BASE, _q)
 /*
 * QCU one shot arm set registers
 */
 #define	AR5K_QCU_ONESHOTARM_SET		0x0940	/* Register Address -QCU "one shot arm set (?)" */
 #define	AR5K_QCU_ONESHOTARM_SET_M	0x0000ffff
 /*
 * QCU one shot arm clear registers
 */
 #define	AR5K_QCU_ONESHOTARM_CLEAR	0x0980	/* Register Address -QCU "one shot arm clear (?)" */
 #define	AR5K_QCU_ONESHOTARM_CLEAR_M	0x0000ffff
 /*
 * QCU misc registers
 */
 #define AR5K_QCU_MISC_BASE		0x09c0			/* Register Address -Queue0 MISC */
 #define	AR5K_QCU_MISC_FRSHED_M		0x0000000f	/* Frame sheduling mask */
 #define	AR5K_QCU_MISC_FRSHED_ASAP		0	/* ASAP */
 #define	AR5K_QCU_MISC_FRSHED_CBR		1	/* Constant Bit Rate */
 #define	AR5K_QCU_MISC_FRSHED_DBA_GT		2	/* DMA Beacon alert gated */
 #define	AR5K_QCU_MISC_FRSHED_TIM_GT		3	/* TIMT gated */
 #define	AR5K_QCU_MISC_FRSHED_BCN_SENT_GT	4	/* Beacon sent gated */
 #define	AR5K_QCU_MISC_ONESHOT_ENABLE	0x00000010	/* Oneshot enable */
 #define	AR5K_QCU_MISC_CBREXP_DIS	0x00000020	/* Disable CBR expired counter (normal queue) */
 #define	AR5K_QCU_MISC_CBREXP_BCN_DIS	0x00000040	/* Disable CBR expired counter (beacon queue) */
 #define	AR5K_QCU_MISC_BCN_ENABLE	0x00000080	/* Enable Beacon use */
 #define	AR5K_QCU_MISC_CBR_THRES_ENABLE	0x00000100	/* CBR expired threshold enabled */
 #define	AR5K_QCU_MISC_RDY_VEOL_POLICY	0x00000200	/* TXE reset when RDYTIME expired or VEOL */
 #define	AR5K_QCU_MISC_CBR_RESET_CNT	0x00000400	/* CBR threshold (counter) reset */
 #define	AR5K_QCU_MISC_DCU_EARLY		0x00000800	/* DCU early termination */
 #define AR5K_QCU_MISC_DCU_CMP_EN	0x00001000	/* Enable frame compression */
 #define AR5K_QUEUE_MISC(_q)		AR5K_QUEUE_REG(AR5K_QCU_MISC_BASE, _q)
 /*
 * QCU status registers
 */
 #define AR5K_QCU_STS_BASE	0x0a00			/* Register Address - Queue0 STS */
 #define	AR5K_QCU_STS_FRMPENDCNT	0x00000003	/* Frames pending counter */
 #define	AR5K_QCU_STS_CBREXPCNT	0x0000ff00	/* CBR expired counter */
 #define	AR5K_QUEUE_STATUS(_q)	AR5K_QUEUE_REG(AR5K_QCU_STS_BASE, _q)
 /*
 * QCU ready time shutdown register
 */
 #define AR5K_QCU_RDYTIMESHDN	0x0a40
 #define AR5K_QCU_RDYTIMESHDN_M	0x000003ff
 /*
 * QCU compression buffer base registers [5212+]
 */
 #define AR5K_QCU_CBB_SELECT	0x0b00
 #define AR5K_QCU_CBB_ADDR	0x0b04
 #define AR5K_QCU_CBB_ADDR_S	9
 /*
 * QCU compression buffer configuration register [5212+]
 * (buffer size)
 */
 #define AR5K_QCU_CBCFG		0x0b08
 /*
 * Distributed Coordination Function (DCF) control unit (DCU)
 * registers [5211+]
 *
 * These registers control the various characteristics of each queue
 * for 802.11e (WME) combatibility so they go together with
 * QCU registers in pairs. For each queue we have a QCU mask register,
 * (0x1000 - 0x102c), a local-IFS settings register (0x1040 - 0x106c),
 * a retry limit register (0x1080 - 0x10ac), a channel time register
 * (0x10c0 - 0x10ec), a misc-settings register (0x1100 - 0x112c) and
 * a sequence number register (0x1140 - 0x116c). It seems that "global"
 * registers here afect all queues (see use of DCU_GBL_IFS_SLOT in ar5k).
 * We use the same macros here for easier register access.
 *
 */
 /*
 * DCU QCU mask registers
 */
 #define AR5K_DCU_QCUMASK_BASE	0x1000		/* Register Address -Queue0 DCU_QCUMASK */
 #define AR5K_DCU_QCUMASK_M	0x000003ff
 #define AR5K_QUEUE_QCUMASK(_q)	AR5K_QUEUE_REG(AR5K_DCU_QCUMASK_BASE, _q)
 /*
 * DCU local Inter Frame Space settings register
 */
 #define AR5K_DCU_LCL_IFS_BASE		0x1040			/* Register Address -Queue0 DCU_LCL_IFS */
 #define	AR5K_DCU_LCL_IFS_CW_MIN	        0x000003ff	/* Minimum Contention Window */
 #define	AR5K_DCU_LCL_IFS_CW_MIN_S	0
 #define	AR5K_DCU_LCL_IFS_CW_MAX	        0x000ffc00	/* Maximum Contention Window */
 #define	AR5K_DCU_LCL_IFS_CW_MAX_S	10
 #define	AR5K_DCU_LCL_IFS_AIFS		0x0ff00000	/* Arbitrated Interframe Space */
 #define	AR5K_DCU_LCL_IFS_AIFS_S		20
 #define	AR5K_DCU_LCL_IFS_AIFS_MAX	0xfc		/* Anything above that can cause DCU to hang */
 #define	AR5K_QUEUE_DFS_LOCAL_IFS(_q)	AR5K_QUEUE_REG(AR5K_DCU_LCL_IFS_BASE, _q)
 /*
 * DCU retry limit registers
 */
 #define AR5K_DCU_RETRY_LMT_BASE		0x1080			/* Register Address -Queue0 DCU_RETRY_LMT */
 #define AR5K_DCU_RETRY_LMT_SH_RETRY	0x0000000f	/* Short retry limit mask */
 #define AR5K_DCU_RETRY_LMT_SH_RETRY_S	0
 #define AR5K_DCU_RETRY_LMT_LG_RETRY	0x000000f0	/* Long retry limit mask */
 #define AR5K_DCU_RETRY_LMT_LG_RETRY_S	4
 #define AR5K_DCU_RETRY_LMT_SSH_RETRY	0x00003f00	/* Station short retry limit mask (?) */
 #define AR5K_DCU_RETRY_LMT_SSH_RETRY_S	8
 #define AR5K_DCU_RETRY_LMT_SLG_RETRY	0x000fc000	/* Station long retry limit mask (?) */
 #define AR5K_DCU_RETRY_LMT_SLG_RETRY_S	14
 #define	AR5K_QUEUE_DFS_RETRY_LIMIT(_q)	AR5K_QUEUE_REG(AR5K_DCU_RETRY_LMT_BASE, _q)
 /*
 * DCU channel time registers
 */
 #define AR5K_DCU_CHAN_TIME_BASE		0x10c0			/* Register Address -Queue0 DCU_CHAN_TIME */
 #define	AR5K_DCU_CHAN_TIME_DUR		0x000fffff	/* Channel time duration */
 #define	AR5K_DCU_CHAN_TIME_DUR_S	0
 #define	AR5K_DCU_CHAN_TIME_ENABLE	0x00100000	/* Enable channel time */
 #define AR5K_QUEUE_DFS_CHANNEL_TIME(_q)	AR5K_QUEUE_REG(AR5K_DCU_CHAN_TIME_BASE, _q)
 /*
 * DCU misc registers [5211+]
 *
 * Note: Arbiter lockout control controls the
 * behaviour on low priority queues when we have multiple queues
 * with pending frames. Intra-frame lockout means we wait until
 * the queue's current frame transmits (with post frame backoff and bursting)
 * before we transmit anything else and global lockout means we
 * wait for the whole queue to finish before higher priority queues
 * can transmit (this is used on beacon and CAB queues).
 * No lockout means there is no special handling.
 */
 #define AR5K_DCU_MISC_BASE		0x1100			/* Register Address -Queue0 DCU_MISC */
 #define	AR5K_DCU_MISC_BACKOFF		0x0000003f	/* Mask for backoff threshold */
 #define	AR5K_DCU_MISC_ETS_RTS_POL	0x00000040	/* End of transmission series
 							station RTS/data failure count
 							reset policy (?) */
 #define AR5K_DCU_MISC_ETS_CW_POL	0x00000080	/* End of transmission series
 							CW reset policy */
 #define	AR5K_DCU_MISC_FRAG_WAIT		0x00000100	/* Wait for next fragment */
 #define AR5K_DCU_MISC_BACKOFF_FRAG	0x00000200	/* Enable backoff while bursting */
 #define	AR5K_DCU_MISC_HCFPOLL_ENABLE	0x00000800	/* CF - Poll enable */
 #define	AR5K_DCU_MISC_BACKOFF_PERSIST	0x00001000	/* Persistent backoff */
 #define	AR5K_DCU_MISC_FRMPRFTCH_ENABLE	0x00002000	/* Enable frame pre-fetch */
 #define	AR5K_DCU_MISC_VIRTCOL		0x0000c000	/* Mask for Virtual Collision (?) */
 #define	AR5K_DCU_MISC_VIRTCOL_NORMAL	0
 #define	AR5K_DCU_MISC_VIRTCOL_IGNORE	1
 #define	AR5K_DCU_MISC_BCN_ENABLE	0x00010000	/* Enable Beacon use */
 #define	AR5K_DCU_MISC_ARBLOCK_CTL	0x00060000	/* Arbiter lockout control mask */
 #define	AR5K_DCU_MISC_ARBLOCK_CTL_S	17
 #define	AR5K_DCU_MISC_ARBLOCK_CTL_NONE		0	/* No arbiter lockout */
 #define	AR5K_DCU_MISC_ARBLOCK_CTL_INTFRM	1	/* Intra-frame lockout */
 #define	AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL	2	/* Global lockout */
 #define	AR5K_DCU_MISC_ARBLOCK_IGNORE	0x00080000	/* Ignore Arbiter lockout */
 #define	AR5K_DCU_MISC_SEQ_NUM_INCR_DIS	0x00100000	/* Disable sequence number increment */
 #define	AR5K_DCU_MISC_POST_FR_BKOFF_DIS	0x00200000	/* Disable post-frame backoff */
 #define	AR5K_DCU_MISC_VIRT_COLL_POLICY	0x00400000	/* Virtual Collision cw policy */
 #define	AR5K_DCU_MISC_BLOWN_IFS_POLICY	0x00800000	/* Blown IFS policy (?) */
 #define	AR5K_DCU_MISC_SEQNUM_CTL	0x01000000	/* Sequence number control (?) */
 #define AR5K_QUEUE_DFS_MISC(_q)		AR5K_QUEUE_REG(AR5K_DCU_MISC_BASE, _q)
 /*
 * DCU frame sequence number registers
 */
 #define AR5K_DCU_SEQNUM_BASE		0x1140
 #define	AR5K_DCU_SEQNUM_M		0x00000fff
 #define	AR5K_QUEUE_DCU_SEQNUM(_q)	AR5K_QUEUE_REG(AR5K_DCU_SEQNUM_BASE, _q)
 /*
 * DCU global IFS SIFS register
 */
 #define AR5K_DCU_GBL_IFS_SIFS	0x1030
 #define AR5K_DCU_GBL_IFS_SIFS_M	0x0000ffff
 /*
 * DCU global IFS slot interval register
 */
 #define AR5K_DCU_GBL_IFS_SLOT	0x1070
 #define AR5K_DCU_GBL_IFS_SLOT_M	0x0000ffff
 /*
 * DCU global IFS EIFS register
 */
 #define AR5K_DCU_GBL_IFS_EIFS	0x10b0
 #define AR5K_DCU_GBL_IFS_EIFS_M	0x0000ffff
 /*
 * DCU global IFS misc register
 *
 * LFSR stands for Linear Feedback Shift Register
 * and it's used for generating pseudo-random
 * number sequences.
 *
 * (If i understand corectly, random numbers are
 * used for idle sensing -multiplied with cwmin/max etc-)
 */
 #define AR5K_DCU_GBL_IFS_MISC			0x10f0			/* Register Address */
 #define	AR5K_DCU_GBL_IFS_MISC_LFSR_SLICE	0x00000007	/* LFSR Slice Select */
 #define	AR5K_DCU_GBL_IFS_MISC_TURBO_MODE	0x00000008	/* Turbo mode */
 #define	AR5K_DCU_GBL_IFS_MISC_SIFS_DUR_USEC	0x000003f0	/* SIFS Duration mask */
 #define	AR5K_DCU_GBL_IFS_MISC_USEC_DUR		0x000ffc00	/* USEC Duration mask */
 #define	AR5K_DCU_GBL_IFS_MISC_USEC_DUR_S	10
 #define	AR5K_DCU_GBL_IFS_MISC_DCU_ARB_DELAY	0x00300000	/* DCU Arbiter delay mask */
 #define AR5K_DCU_GBL_IFS_MISC_SIFS_CNT_RST	0x00400000	/* SIFS cnt reset policy (?) */
 #define AR5K_DCU_GBL_IFS_MISC_AIFS_CNT_RST	0x00800000	/* AIFS cnt reset policy (?) */
 #define AR5K_DCU_GBL_IFS_MISC_RND_LFSR_SL_DIS	0x01000000	/* Disable random LFSR slice */
 /*
 * DCU frame prefetch control register
 */
 #define AR5K_DCU_FP			0x1230			/* Register Address */
 #define AR5K_DCU_FP_NOBURST_DCU_EN	0x00000001	/* Enable non-burst prefetch on DCU (?) */
 #define AR5K_DCU_FP_NOBURST_EN		0x00000010	/* Enable non-burst prefetch (?) */
 #define AR5K_DCU_FP_BURST_DCU_EN	0x00000020	/* Enable burst prefetch on DCU (?) */
 /*
 * DCU transmit pause control/status register
 */
 #define AR5K_DCU_TXP		0x1270			/* Register Address */
 #define	AR5K_DCU_TXP_M		0x000003ff	/* Tx pause mask */
 #define	AR5K_DCU_TXP_STATUS	0x00010000	/* Tx pause status */
 /*
 * DCU transmit filter table 0 (32 entries)
 * each entry contains a 32bit slice of the
 * 128bit tx filter for each DCU (4 slices per DCU)
 */
 #define AR5K_DCU_TX_FILTER_0_BASE	0x1038
 #define	AR5K_DCU_TX_FILTER_0(_n)	(AR5K_DCU_TX_FILTER_0_BASE + (_n * 64))
 /*
 * DCU transmit filter table 1 (16 entries)
 */
 #define AR5K_DCU_TX_FILTER_1_BASE	0x103c
 #define	AR5K_DCU_TX_FILTER_1(_n)	(AR5K_DCU_TX_FILTER_1_BASE + (_n * 64))
 /*
 * DCU clear transmit filter register
 */
 #define AR5K_DCU_TX_FILTER_CLR	0x143c
 /*
 * DCU set transmit filter register
 */
 #define AR5K_DCU_TX_FILTER_SET	0x147c
 /*
 * Reset control register
 */
 #define AR5K_RESET_CTL		0x4000			/* Register Address */
 #define AR5K_RESET_CTL_PCU	0x00000001	/* Protocol Control Unit reset */
 #define AR5K_RESET_CTL_DMA	0x00000002	/* DMA (Rx/Tx) reset [5210] */
 #define	AR5K_RESET_CTL_BASEBAND	0x00000002	/* Baseband reset [5211+] */
 #define AR5K_RESET_CTL_MAC	0x00000004	/* MAC reset (PCU+Baseband ?) [5210] */
 #define AR5K_RESET_CTL_PHY	0x00000008	/* PHY reset [5210] */
 #define AR5K_RESET_CTL_PCI	0x00000010	/* PCI Core reset (interrupts etc) */
 /*
 * Sleep control register
 */
 #define AR5K_SLEEP_CTL			0x4004			/* Register Address */
 #define AR5K_SLEEP_CTL_SLDUR		0x0000ffff	/* Sleep duration mask */
 #define AR5K_SLEEP_CTL_SLDUR_S		0
 #define AR5K_SLEEP_CTL_SLE		0x00030000	/* Sleep enable mask */
 #define AR5K_SLEEP_CTL_SLE_S		16
 #define AR5K_SLEEP_CTL_SLE_WAKE		0x00000000	/* Force chip awake */
 #define AR5K_SLEEP_CTL_SLE_SLP		0x00010000	/* Force chip sleep */
 #define AR5K_SLEEP_CTL_SLE_ALLOW	0x00020000	/* Normal sleep policy */
 #define AR5K_SLEEP_CTL_SLE_UNITS	0x00000008	/* [5211+] */
 #define AR5K_SLEEP_CTL_DUR_TIM_POL	0x00040000	/* Sleep duration timing policy */
 #define AR5K_SLEEP_CTL_DUR_WRITE_POL	0x00080000	/* Sleep duration write policy */
 #define AR5K_SLEEP_CTL_SLE_POL		0x00100000	/* Sleep policy mode */
 /*
 * Interrupt pending register
 */
 #define AR5K_INTPEND	0x4008
 #define AR5K_INTPEND_M	0x00000001
 /*
 * Sleep force register
 */
 #define AR5K_SFR	0x400c
 #define AR5K_SFR_EN	0x00000001
 /*
 * PCI configuration register
 * TODO: Fix LED stuff
 */
 #define AR5K_PCICFG			0x4010			/* Register Address */
 #define AR5K_PCICFG_EEAE		0x00000001	/* Eeprom access enable [5210] */
 #define AR5K_PCICFG_SLEEP_CLOCK_EN	0x00000002	/* Enable sleep clock */
 #define AR5K_PCICFG_CLKRUNEN		0x00000004	/* CLKRUN enable [5211+] */
 #define AR5K_PCICFG_EESIZE		0x00000018	/* Mask for EEPROM size [5211+] */
 #define AR5K_PCICFG_EESIZE_S		3
 #define AR5K_PCICFG_EESIZE_4K		0		/* 4K */
 #define AR5K_PCICFG_EESIZE_8K		1		/* 8K */
 #define AR5K_PCICFG_EESIZE_16K		2		/* 16K */
 #define AR5K_PCICFG_EESIZE_FAIL		3		/* Failed to get size [5211+] */
 #define AR5K_PCICFG_LED			0x00000060	/* Led status [5211+] */
 #define AR5K_PCICFG_LED_NONE		0x00000000	/* Default [5211+] */
 #define AR5K_PCICFG_LED_PEND		0x00000020	/* Scan / Auth pending */
 #define AR5K_PCICFG_LED_ASSOC		0x00000040	/* Associated */
 #define	AR5K_PCICFG_BUS_SEL		0x00000380	/* Mask for "bus select" [5211+] (?) */
 #define AR5K_PCICFG_CBEFIX_DIS		0x00000400	/* Disable CBE fix */
 #define AR5K_PCICFG_SL_INTEN		0x00000800	/* Enable interrupts when asleep */
 #define AR5K_PCICFG_LED_BCTL		0x00001000	/* Led blink (?) [5210] */
 #define AR5K_PCICFG_RETRY_FIX		0x00001000	/* Enable pci core retry fix */
 #define AR5K_PCICFG_SL_INPEN		0x00002000	/* Sleep even whith pending interrupts*/
 #define AR5K_PCICFG_SPWR_DN		0x00010000	/* Mask for power status */
 #define AR5K_PCICFG_LEDMODE		0x000e0000	/* Ledmode [5211+] */
 #define AR5K_PCICFG_LEDMODE_PROP	0x00000000	/* Blink on standard traffic [5211+] */
 #define AR5K_PCICFG_LEDMODE_PROM	0x00020000	/* Default mode (blink on any traffic) [5211+] */
 #define AR5K_PCICFG_LEDMODE_PWR		0x00040000	/* Some other blinking mode  (?) [5211+] */
 #define AR5K_PCICFG_LEDMODE_RAND	0x00060000	/* Random blinking (?) [5211+] */
 #define AR5K_PCICFG_LEDBLINK		0x00700000	/* Led blink rate */
 #define AR5K_PCICFG_LEDBLINK_S		20
 #define AR5K_PCICFG_LEDSLOW		0x00800000	/* Slowest led blink rate [5211+] */
 #define AR5K_PCICFG_LEDSTATE				\
 	(AR5K_PCICFG_LED | AR5K_PCICFG_LEDMODE |	\
 	AR5K_PCICFG_LEDBLINK | AR5K_PCICFG_LEDSLOW)
 #define	AR5K_PCICFG_SLEEP_CLOCK_RATE	0x03000000	/* Sleep clock rate */
 #define	AR5K_PCICFG_SLEEP_CLOCK_RATE_S	24
 /*
 * "General Purpose Input/Output" (GPIO) control register
 *
 * I'm not sure about this but after looking at the code
 * for all chipsets here is what i got.
 *
 * We have 6 GPIOs (pins), each GPIO has 4 modes (2 bits)
 * Mode 0 -> always input
 * Mode 1 -> output when GPIODO for this GPIO is set to 0
 * Mode 2 -> output when GPIODO for this GPIO is set to 1
 * Mode 3 -> always output
 *
 * For more infos check out get_gpio/set_gpio and
 * set_gpio_input/set_gpio_output functs.
 * For more infos on gpio interrupt check out set_gpio_intr.
 */
 #define AR5K_NUM_GPIO	6
 #define AR5K_GPIOCR		0x4014				/* Register Address */
 #define AR5K_GPIOCR_INT_ENA	0x00008000		/* Enable GPIO interrupt */
 #define AR5K_GPIOCR_INT_SELL	0x00000000		/* Generate interrupt when pin is low */
 #define AR5K_GPIOCR_INT_SELH	0x00010000		/* Generate interrupt when pin is high */
 #define AR5K_GPIOCR_IN(n)	(0 << ((n) * 2))	/* Mode 0 for pin n */
 #define AR5K_GPIOCR_OUT0(n)	(1 << ((n) * 2))	/* Mode 1 for pin n */
 #define AR5K_GPIOCR_OUT1(n)	(2 << ((n) * 2))	/* Mode 2 for pin n */
 #define AR5K_GPIOCR_OUT(n)	(3 << ((n) * 2))	/* Mode 3 for pin n */
 #define AR5K_GPIOCR_INT_SEL(n)	((n) << 12)		/* Interrupt for GPIO pin n */
 /*
 * "General Purpose Input/Output" (GPIO) data output register
 */
 #define AR5K_GPIODO	0x4018
 /*
 * "General Purpose Input/Output" (GPIO) data input register
 */
 #define AR5K_GPIODI	0x401c
 #define AR5K_GPIODI_M	0x0000002f
 /*
 * Silicon revision register
 */
 #define AR5K_SREV		0x4020			/* Register Address */
 #define AR5K_SREV_REV		0x0000000f	/* Mask for revision */
 #define AR5K_SREV_REV_S		0
 #define AR5K_SREV_VER		0x000000ff	/* Mask for version */
 #define AR5K_SREV_VER_S		4
 /*
 * TXE write posting register
 */
 #define	AR5K_TXEPOST	0x4028
 /*
 * QCU sleep mask
 */
 #define	AR5K_QCU_SLEEP_MASK	0x402c
 /* 0x4068 is compression buffer configuration
 * register on 5414 and pm configuration register
 * on 5424 and newer pci-e chips. */
 /*
 * Compression buffer configuration
 * register (enable/disable) [5414]
 */
 #define AR5K_5414_CBCFG		0x4068
 #define AR5K_5414_CBCFG_BUF_DIS	0x10	/* Disable buffer */
 /*
- * PCI-E Power managment configuration
+ * PCI-E Power management configuration
 * and status register [5424+]
 */
 #define	AR5K_PCIE_PM_CTL		0x4068			/* Register address */
 /* Only 5424 */
 #define	AR5K_PCIE_PM_CTL_L1_WHEN_D2	0x00000001	/* enable PCIe core enter L1
 							when d2_sleep_en is asserted */
 #define	AR5K_PCIE_PM_CTL_L0_L0S_CLEAR	0x00000002	/* Clear L0 and L0S counters */
 #define	AR5K_PCIE_PM_CTL_L0_L0S_EN	0x00000004	/* Start L0 nd L0S counters */
 #define	AR5K_PCIE_PM_CTL_LDRESET_EN	0x00000008	/* Enable reset when link goes
 							down */
 /* Wake On Wireless */
 #define	AR5K_PCIE_PM_CTL_PME_EN		0x00000010	/* PME Enable */
 #define	AR5K_PCIE_PM_CTL_AUX_PWR_DET	0x00000020	/* Aux power detect */
 #define	AR5K_PCIE_PM_CTL_PME_CLEAR	0x00000040	/* Clear PME */
 #define	AR5K_PCIE_PM_CTL_PSM_D0		0x00000080
 #define	AR5K_PCIE_PM_CTL_PSM_D1		0x00000100
 #define	AR5K_PCIE_PM_CTL_PSM_D2		0x00000200
 #define	AR5K_PCIE_PM_CTL_PSM_D3		0x00000400
 /*
 * PCI-E Workaround enable register
 */
 #define	AR5K_PCIE_WAEN	0x407c
 /*
 * PCI-E Serializer/Desirializer
 * registers
 */
 #define	AR5K_PCIE_SERDES	0x4080
 #define	AR5K_PCIE_SERDES_RESET	0x4084
 /*====EEPROM REGISTERS====*/
 /*
 * EEPROM access registers
 *
 * Here we got a difference between 5210/5211-12
 * read data register for 5210 is at 0x6800 and
 * status register is at 0x6c00. There is also
 * no eeprom command register on 5210 and the
 * offsets are different.
 *
 * To read eeprom data for a specific offset:
 * 5210 - enable eeprom access (AR5K_PCICFG_EEAE)
 *        read AR5K_EEPROM_BASE +(4 * offset)
 *        check the eeprom status register
 *        and read eeprom data register.
 *
 * 5211 - write offset to AR5K_EEPROM_BASE
 * 5212   write AR5K_EEPROM_CMD_READ on AR5K_EEPROM_CMD
 *        check the eeprom status register
 *        and read eeprom data register.
 *
 * To write eeprom data for a specific offset:
 * 5210 - enable eeprom access (AR5K_PCICFG_EEAE)
 *        write data to AR5K_EEPROM_BASE +(4 * offset)
 *        check the eeprom status register
 * 5211 - write AR5K_EEPROM_CMD_RESET on AR5K_EEPROM_CMD
 * 5212   write offset to AR5K_EEPROM_BASE
 *        write data to data register
 *	  write AR5K_EEPROM_CMD_WRITE on AR5K_EEPROM_CMD
 *        check the eeprom status register
 *
 * For more infos check eeprom_* functs and the ar5k.c
 * file posted in madwifi-devel mailing list.
 * http://sourceforge.net/mailarchive/message.php?msg_id=8966525
 *
 */
 #define AR5K_EEPROM_BASE	0x6000
 /*
 * EEPROM data register
 */
 #define AR5K_EEPROM_DATA_5211	0x6004
 #define AR5K_EEPROM_DATA_5210	0x6800
 #define	AR5K_EEPROM_DATA	(ah->ah_version == AR5K_AR5210 ? \
 				AR5K_EEPROM_DATA_5210 : AR5K_EEPROM_DATA_5211)
 /*
 * EEPROM command register
 */
 #define AR5K_EEPROM_CMD		0x6008			/* Register Addres */
 #define AR5K_EEPROM_CMD_READ	0x00000001	/* EEPROM read */
 #define AR5K_EEPROM_CMD_WRITE	0x00000002	/* EEPROM write */
 #define AR5K_EEPROM_CMD_RESET	0x00000004	/* EEPROM reset */
 /*
 * EEPROM status register
 */
 #define AR5K_EEPROM_STAT_5210	0x6c00			/* Register Address [5210] */
 #define AR5K_EEPROM_STAT_5211	0x600c			/* Register Address [5211+] */
 #define	AR5K_EEPROM_STATUS	(ah->ah_version == AR5K_AR5210 ? \
 				AR5K_EEPROM_STAT_5210 : AR5K_EEPROM_STAT_5211)
 #define AR5K_EEPROM_STAT_RDERR	0x00000001	/* EEPROM read failed */
 #define AR5K_EEPROM_STAT_RDDONE	0x00000002	/* EEPROM read successful */
 #define AR5K_EEPROM_STAT_WRERR	0x00000004	/* EEPROM write failed */
 #define AR5K_EEPROM_STAT_WRDONE	0x00000008	/* EEPROM write successful */
 /*
 * EEPROM config register
 */
 #define AR5K_EEPROM_CFG			0x6010			/* Register Addres */
 #define AR5K_EEPROM_CFG_SIZE		0x00000003		/* Size determination override */
 #define AR5K_EEPROM_CFG_SIZE_AUTO	0
 #define AR5K_EEPROM_CFG_SIZE_4KBIT	1
 #define AR5K_EEPROM_CFG_SIZE_8KBIT	2
 #define AR5K_EEPROM_CFG_SIZE_16KBIT	3
 #define AR5K_EEPROM_CFG_WR_WAIT_DIS	0x00000004	/* Disable write wait */
 #define AR5K_EEPROM_CFG_CLK_RATE	0x00000018	/* Clock rate */
 #define AR5K_EEPROM_CFG_CLK_RATE_S		3
 #define AR5K_EEPROM_CFG_CLK_RATE_156KHZ	0
 #define AR5K_EEPROM_CFG_CLK_RATE_312KHZ	1
 #define AR5K_EEPROM_CFG_CLK_RATE_625KHZ	2
 #define AR5K_EEPROM_CFG_PROT_KEY	0x00ffff00      /* Protection key */
 #define AR5K_EEPROM_CFG_PROT_KEY_S	8
 #define AR5K_EEPROM_CFG_LIND_EN		0x01000000	/* Enable length indicator (?) */
 /*
 * TODO: Wake On Wireless registers
 * Range 0x7000 - 0x7ce0
 */
 /*
 * Protocol Control Unit (PCU) registers
 */
 /*
 * Used for checking initial register writes
 * during channel reset (see reset func)
 */
 #define AR5K_PCU_MIN	0x8000
 #define AR5K_PCU_MAX	0x8fff
 /*
 * First station id register (Lower 32 bits of MAC address)
 */
 #define AR5K_STA_ID0		0x8000
 #define	AR5K_STA_ID0_ARRD_L32	0xffffffff
 /*
 * Second station id register (Upper 16 bits of MAC address + PCU settings)
 */
 #define AR5K_STA_ID1			0x8004			/* Register Address */
 #define	AR5K_STA_ID1_ADDR_U16		0x0000ffff	/* Upper 16 bits of MAC addres */
 #define AR5K_STA_ID1_AP			0x00010000	/* Set AP mode */
 #define AR5K_STA_ID1_ADHOC		0x00020000	/* Set Ad-Hoc mode */
 #define AR5K_STA_ID1_PWR_SV		0x00040000	/* Power save reporting */
 #define AR5K_STA_ID1_NO_KEYSRCH		0x00080000	/* No key search */
 #define AR5K_STA_ID1_NO_PSPOLL		0x00100000	/* No power save polling [5210] */
 #define AR5K_STA_ID1_PCF_5211		0x00100000	/* Enable PCF on [5211+] */
 #define AR5K_STA_ID1_PCF_5210		0x00200000	/* Enable PCF on [5210]*/
 #define	AR5K_STA_ID1_PCF		(ah->ah_version == AR5K_AR5210 ? \
 					AR5K_STA_ID1_PCF_5210 : AR5K_STA_ID1_PCF_5211)
 #define AR5K_STA_ID1_DEFAULT_ANTENNA	0x00200000	/* Use default antenna */
 #define AR5K_STA_ID1_DESC_ANTENNA	0x00400000	/* Update antenna from descriptor */
 #define AR5K_STA_ID1_RTS_DEF_ANTENNA	0x00800000	/* Use default antenna for RTS */
 #define AR5K_STA_ID1_ACKCTS_6MB		0x01000000	/* Use 6Mbit/s for ACK/CTS */
 #define AR5K_STA_ID1_BASE_RATE_11B	0x02000000	/* Use 11b base rate for ACK/CTS [5211+] */
 #define AR5K_STA_ID1_SELFGEN_DEF_ANT	0x04000000	/* Use def. antenna for self generated frames */
 #define AR5K_STA_ID1_CRYPT_MIC_EN	0x08000000	/* Enable MIC */
 #define AR5K_STA_ID1_KEYSRCH_MODE	0x10000000	/* Look up key when key id != 0 */
 #define AR5K_STA_ID1_PRESERVE_SEQ_NUM	0x20000000	/* Preserve sequence number */
 #define AR5K_STA_ID1_CBCIV_ENDIAN	0x40000000	/* ??? */
 #define AR5K_STA_ID1_KEYSRCH_MCAST	0x80000000	/* Do key cache search for mcast frames */
 #define	AR5K_STA_ID1_ANTENNA_SETTINGS	(AR5K_STA_ID1_DEFAULT_ANTENNA | \
 					AR5K_STA_ID1_DESC_ANTENNA | \
 					AR5K_STA_ID1_RTS_DEF_ANTENNA | \
 					AR5K_STA_ID1_SELFGEN_DEF_ANT)
 /*
 * First BSSID register (MAC address, lower 32bits)
 */
 #define AR5K_BSS_ID0	0x8008
 /*
 * Second BSSID register (MAC address in upper 16 bits)
 *
 * AID: Association ID
 */
 #define AR5K_BSS_ID1		0x800c
 #define AR5K_BSS_ID1_AID	0xffff0000
 #define AR5K_BSS_ID1_AID_S	16
 /*
 * Backoff slot time register
 */
 #define AR5K_SLOT_TIME	0x8010
 /*
 * ACK/CTS timeout register
 */
 #define AR5K_TIME_OUT		0x8014			/* Register Address */
 #define AR5K_TIME_OUT_ACK	0x00001fff	/* ACK timeout mask */
 #define AR5K_TIME_OUT_ACK_S	0
 #define AR5K_TIME_OUT_CTS	0x1fff0000	/* CTS timeout mask */
 #define AR5K_TIME_OUT_CTS_S	16
 /*
 * RSSI threshold register
 */
 #define AR5K_RSSI_THR			0x8018		/* Register Address */
 #define AR5K_RSSI_THR_M			0x000000ff	/* Mask for RSSI threshold [5211+] */
 #define AR5K_RSSI_THR_BMISS_5210	0x00000700	/* Mask for Beacon Missed threshold [5210] */
 #define AR5K_RSSI_THR_BMISS_5210_S	8
 #define AR5K_RSSI_THR_BMISS_5211	0x0000ff00	/* Mask for Beacon Missed threshold [5211+] */
 #define AR5K_RSSI_THR_BMISS_5211_S	8
 #define	AR5K_RSSI_THR_BMISS		(ah->ah_version == AR5K_AR5210 ? \
 					AR5K_RSSI_THR_BMISS_5210 : AR5K_RSSI_THR_BMISS_5211)
 #define	AR5K_RSSI_THR_BMISS_S		8
 /*
 * 5210 has more PCU registers because there is no QCU/DCU
 * so queue parameters are set here, this way a lot common
 * registers have different address for 5210. To make things
 * easier we define a macro based on ah->ah_version for common
 * registers with different addresses and common flags.
 */
 /*
 * Retry limit register
 *
 * Retry limit register for 5210 (no QCU/DCU so it's done in PCU)
 */
 #define AR5K_NODCU_RETRY_LMT		0x801c			/* Register Address */
 #define AR5K_NODCU_RETRY_LMT_SH_RETRY	0x0000000f	/* Short retry limit mask */
 #define AR5K_NODCU_RETRY_LMT_SH_RETRY_S	0
 #define AR5K_NODCU_RETRY_LMT_LG_RETRY	0x000000f0	/* Long retry mask */
 #define AR5K_NODCU_RETRY_LMT_LG_RETRY_S	4
 #define AR5K_NODCU_RETRY_LMT_SSH_RETRY	0x00003f00	/* Station short retry limit mask */
 #define AR5K_NODCU_RETRY_LMT_SSH_RETRY_S	8
 #define AR5K_NODCU_RETRY_LMT_SLG_RETRY	0x000fc000	/* Station long retry limit mask */
 #define AR5K_NODCU_RETRY_LMT_SLG_RETRY_S	14
 #define AR5K_NODCU_RETRY_LMT_CW_MIN	0x3ff00000	/* Minimum contention window mask */
 #define AR5K_NODCU_RETRY_LMT_CW_MIN_S	20
 /*
 * Transmit latency register
 */
 #define AR5K_USEC_5210			0x8020			/* Register Address [5210] */
 #define AR5K_USEC_5211			0x801c			/* Register Address [5211+] */
 #define AR5K_USEC			(ah->ah_version == AR5K_AR5210 ? \
 					AR5K_USEC_5210 : AR5K_USEC_5211)
 #define AR5K_USEC_1			0x0000007f	/* clock cycles for 1us */
 #define AR5K_USEC_1_S			0
 #define AR5K_USEC_32			0x00003f80	/* clock cycles for 1us while on 32Mhz clock */
 #define AR5K_USEC_32_S			7
 #define AR5K_USEC_TX_LATENCY_5211	0x007fc000
 #define AR5K_USEC_TX_LATENCY_5211_S	14
 #define AR5K_USEC_RX_LATENCY_5211	0x1f800000
 #define AR5K_USEC_RX_LATENCY_5211_S	23
 #define AR5K_USEC_TX_LATENCY_5210	0x000fc000	/* also for 5311 */
 #define AR5K_USEC_TX_LATENCY_5210_S	14
 #define AR5K_USEC_RX_LATENCY_5210	0x03f00000	/* also for 5311 */
 #define AR5K_USEC_RX_LATENCY_5210_S	20
 /*
 * PCU beacon control register
 */
 #define AR5K_BEACON_5210	0x8024			/*Register Address [5210] */
 #define AR5K_BEACON_5211	0x8020			/*Register Address [5211+] */
 #define AR5K_BEACON		(ah->ah_version == AR5K_AR5210 ? \
 				AR5K_BEACON_5210 : AR5K_BEACON_5211)
 #define AR5K_BEACON_PERIOD	0x0000ffff	/* Mask for beacon period */
 #define AR5K_BEACON_PERIOD_S	0
 #define AR5K_BEACON_TIM		0x007f0000	/* Mask for TIM offset */
 #define AR5K_BEACON_TIM_S	16
 #define AR5K_BEACON_ENABLE	0x00800000	/* Enable beacons */
 #define AR5K_BEACON_RESET_TSF	0x01000000	/* Force TSF reset */
 /*
 * CFP period register
 */
 #define AR5K_CFP_PERIOD_5210	0x8028
 #define AR5K_CFP_PERIOD_5211	0x8024
 #define AR5K_CFP_PERIOD		(ah->ah_version == AR5K_AR5210 ? \
 				AR5K_CFP_PERIOD_5210 : AR5K_CFP_PERIOD_5211)
 /*
 * Next beacon time register
 */
 #define AR5K_TIMER0_5210	0x802c
 #define AR5K_TIMER0_5211	0x8028
 #define AR5K_TIMER0		(ah->ah_version == AR5K_AR5210 ? \
 				AR5K_TIMER0_5210 : AR5K_TIMER0_5211)
 /*
 * Next DMA beacon alert register
 */
 #define AR5K_TIMER1_5210	0x8030
 #define AR5K_TIMER1_5211	0x802c
 #define AR5K_TIMER1		(ah->ah_version == AR5K_AR5210 ? \
 				AR5K_TIMER1_5210 : AR5K_TIMER1_5211)
 /*
 * Next software beacon alert register
 */
 #define AR5K_TIMER2_5210	0x8034
 #define AR5K_TIMER2_5211	0x8030
 #define AR5K_TIMER2		(ah->ah_version == AR5K_AR5210 ? \
 				AR5K_TIMER2_5210 : AR5K_TIMER2_5211)
 /*
 * Next ATIM window time register
 */
 #define AR5K_TIMER3_5210	0x8038
 #define AR5K_TIMER3_5211	0x8034
 #define AR5K_TIMER3		(ah->ah_version == AR5K_AR5210 ? \
 				AR5K_TIMER3_5210 : AR5K_TIMER3_5211)
 /*
 * 5210 First inter frame spacing register (IFS)
 */
 #define AR5K_IFS0		0x8040
 #define AR5K_IFS0_SIFS		0x000007ff
 #define AR5K_IFS0_SIFS_S	0
 #define AR5K_IFS0_DIFS		0x007ff800
 #define AR5K_IFS0_DIFS_S	11
 /*
 * 5210 Second inter frame spacing register (IFS)
 */
 #define AR5K_IFS1		0x8044
 #define AR5K_IFS1_PIFS		0x00000fff
 #define AR5K_IFS1_PIFS_S	0
 #define AR5K_IFS1_EIFS		0x03fff000
 #define AR5K_IFS1_EIFS_S	12
 #define AR5K_IFS1_CS_EN		0x04000000
 /*
 * CFP duration register
 */
 #define AR5K_CFP_DUR_5210	0x8048
 #define AR5K_CFP_DUR_5211	0x8038
 #define AR5K_CFP_DUR		(ah->ah_version == AR5K_AR5210 ? \
 				AR5K_CFP_DUR_5210 : AR5K_CFP_DUR_5211)
 /*
 * Receive filter register
 */
 #define AR5K_RX_FILTER_5210	0x804c			/* Register Address [5210] */
 #define AR5K_RX_FILTER_5211	0x803c			/* Register Address [5211+] */
 #define AR5K_RX_FILTER		(ah->ah_version == AR5K_AR5210 ? \
 				AR5K_RX_FILTER_5210 : AR5K_RX_FILTER_5211)
 #define	AR5K_RX_FILTER_UCAST 	0x00000001	/* Don't filter unicast frames */
 #define	AR5K_RX_FILTER_MCAST 	0x00000002	/* Don't filter multicast frames */
 #define	AR5K_RX_FILTER_BCAST 	0x00000004	/* Don't filter broadcast frames */
 #define	AR5K_RX_FILTER_CONTROL 	0x00000008	/* Don't filter control frames */
 #define	AR5K_RX_FILTER_BEACON 	0x00000010	/* Don't filter beacon frames */
 #define	AR5K_RX_FILTER_PROM 	0x00000020	/* Set promiscuous mode */
 #define	AR5K_RX_FILTER_XRPOLL 	0x00000040	/* Don't filter XR poll frame [5212+] */
 #define	AR5K_RX_FILTER_PROBEREQ 0x00000080	/* Don't filter probe requests [5212+] */
 #define	AR5K_RX_FILTER_PHYERR_5212	0x00000100	/* Don't filter phy errors [5212+] */
 #define	AR5K_RX_FILTER_RADARERR_5212 	0x00000200	/* Don't filter phy radar errors [5212+] */
 #define AR5K_RX_FILTER_PHYERR_5211	0x00000040	/* [5211] */
 #define AR5K_RX_FILTER_RADARERR_5211	0x00000080	/* [5211] */
 #define AR5K_RX_FILTER_PHYERR  \
 	((ah->ah_version == AR5K_AR5211 ? \
 	AR5K_RX_FILTER_PHYERR_5211 : AR5K_RX_FILTER_PHYERR_5212))
 #define        AR5K_RX_FILTER_RADARERR \
 	((ah->ah_version == AR5K_AR5211 ? \
 	AR5K_RX_FILTER_RADARERR_5211 : AR5K_RX_FILTER_RADARERR_5212))
 /*
 * Multicast filter register (lower 32 bits)
 */
 #define AR5K_MCAST_FILTER0_5210	0x8050
 #define AR5K_MCAST_FILTER0_5211	0x8040
 #define AR5K_MCAST_FILTER0	(ah->ah_version == AR5K_AR5210 ? \
 				AR5K_MCAST_FILTER0_5210 : AR5K_MCAST_FILTER0_5211)
 /*
 * Multicast filter register (higher 16 bits)
 */
 #define AR5K_MCAST_FILTER1_5210	0x8054
 #define AR5K_MCAST_FILTER1_5211	0x8044
 #define AR5K_MCAST_FILTER1	(ah->ah_version == AR5K_AR5210 ? \
 				AR5K_MCAST_FILTER1_5210 : AR5K_MCAST_FILTER1_5211)
 /*
 * Transmit mask register (lower 32 bits) [5210]
 */
 #define AR5K_TX_MASK0	0x8058
 /*
 * Transmit mask register (higher 16 bits) [5210]
 */
 #define AR5K_TX_MASK1	0x805c
 /*
 * Clear transmit mask [5210]
 */
 #define AR5K_CLR_TMASK	0x8060
 /*
 * Trigger level register (before transmission) [5210]
 */
 #define AR5K_TRIG_LVL	0x8064
 /*
 * PCU control register
 *
 * Only DIS_RX is used in the code, the rest i guess are
 * for tweaking/diagnostics.
 */
 #define AR5K_DIAG_SW_5210		0x8068			/* Register Address [5210] */
 #define AR5K_DIAG_SW_5211		0x8048			/* Register Address [5211+] */
 #define AR5K_DIAG_SW			(ah->ah_version == AR5K_AR5210 ? \
 					AR5K_DIAG_SW_5210 : AR5K_DIAG_SW_5211)
 #define AR5K_DIAG_SW_DIS_WEP_ACK	0x00000001	/* Disable ACKs if WEP key is invalid */
 #define AR5K_DIAG_SW_DIS_ACK		0x00000002	/* Disable ACKs */
 #define AR5K_DIAG_SW_DIS_CTS		0x00000004	/* Disable CTSs */
 #define AR5K_DIAG_SW_DIS_ENC		0x00000008	/* Disable encryption */
 #define AR5K_DIAG_SW_DIS_DEC		0x00000010	/* Disable decryption */
 #define AR5K_DIAG_SW_DIS_TX		0x00000020	/* Disable transmit [5210] */
 #define AR5K_DIAG_SW_DIS_RX_5210	0x00000040	/* Disable recieve */
 #define AR5K_DIAG_SW_DIS_RX_5211	0x00000020
 #define	AR5K_DIAG_SW_DIS_RX		(ah->ah_version == AR5K_AR5210 ? \
 					AR5K_DIAG_SW_DIS_RX_5210 : AR5K_DIAG_SW_DIS_RX_5211)
 #define AR5K_DIAG_SW_LOOP_BACK_5210	0x00000080	/* Loopback (i guess it goes with DIS_TX) [5210] */
 #define AR5K_DIAG_SW_LOOP_BACK_5211	0x00000040
 #define AR5K_DIAG_SW_LOOP_BACK		(ah->ah_version == AR5K_AR5210 ? \
 					AR5K_DIAG_SW_LOOP_BACK_5210 : AR5K_DIAG_SW_LOOP_BACK_5211)
 #define AR5K_DIAG_SW_CORR_FCS_5210	0x00000100	/* Corrupted FCS */
 #define AR5K_DIAG_SW_CORR_FCS_5211	0x00000080
 #define AR5K_DIAG_SW_CORR_FCS		(ah->ah_version == AR5K_AR5210 ? \
 					AR5K_DIAG_SW_CORR_FCS_5210 : AR5K_DIAG_SW_CORR_FCS_5211)
 #define AR5K_DIAG_SW_CHAN_INFO_5210	0x00000200	/* Dump channel info */
 #define AR5K_DIAG_SW_CHAN_INFO_5211	0x00000100
 #define AR5K_DIAG_SW_CHAN_INFO		(ah->ah_version == AR5K_AR5210 ? \
 					AR5K_DIAG_SW_CHAN_INFO_5210 : AR5K_DIAG_SW_CHAN_INFO_5211)
 #define AR5K_DIAG_SW_EN_SCRAM_SEED_5210	0x00000400	/* Enable fixed scrambler seed */
 #define AR5K_DIAG_SW_EN_SCRAM_SEED_5211	0x00000200
 #define AR5K_DIAG_SW_EN_SCRAM_SEED	(ah->ah_version == AR5K_AR5210 ? \
 					AR5K_DIAG_SW_EN_SCRAM_SEED_5210 : AR5K_DIAG_SW_EN_SCRAM_SEED_5211)
 #define AR5K_DIAG_SW_ECO_ENABLE		0x00000400	/* [5211+] */
 #define AR5K_DIAG_SW_SCVRAM_SEED	0x0003f800	/* [5210] */
 #define AR5K_DIAG_SW_SCRAM_SEED_M	0x0001fc00	/* Scrambler seed mask */
 #define AR5K_DIAG_SW_SCRAM_SEED_S	10
 #define AR5K_DIAG_SW_DIS_SEQ_INC	0x00040000	/* Disable seqnum increment (?)[5210] */
 #define AR5K_DIAG_SW_FRAME_NV0_5210	0x00080000
 #define AR5K_DIAG_SW_FRAME_NV0_5211	0x00020000	/* Accept frames of non-zero protocol number */
 #define	AR5K_DIAG_SW_FRAME_NV0		(ah->ah_version == AR5K_AR5210 ? \
 					AR5K_DIAG_SW_FRAME_NV0_5210 : AR5K_DIAG_SW_FRAME_NV0_5211)
 #define AR5K_DIAG_SW_OBSPT_M		0x000c0000	/* Observation point select (?) */
 #define AR5K_DIAG_SW_OBSPT_S		18
 #define AR5K_DIAG_SW_RX_CLEAR_HIGH	0x0010000	/* Force RX Clear high */
 #define AR5K_DIAG_SW_IGNORE_CARR_SENSE	0x0020000	/* Ignore virtual carrier sense */
 #define AR5K_DIAG_SW_CHANEL_IDLE_HIGH	0x0040000	/* Force channel idle high */
 #define AR5K_DIAG_SW_PHEAR_ME		0x0080000	/* ??? */
 /*
 * TSF (clock) register (lower 32 bits)
 */
 #define AR5K_TSF_L32_5210	0x806c
 #define AR5K_TSF_L32_5211	0x804c
 #define	AR5K_TSF_L32		(ah->ah_version == AR5K_AR5210 ? \
 				AR5K_TSF_L32_5210 : AR5K_TSF_L32_5211)
 /*
 * TSF (clock) register (higher 32 bits)
 */
 #define AR5K_TSF_U32_5210	0x8070
 #define AR5K_TSF_U32_5211	0x8050
 #define	AR5K_TSF_U32		(ah->ah_version == AR5K_AR5210 ? \
 				AR5K_TSF_U32_5210 : AR5K_TSF_U32_5211)
 /*
 * Last beacon timestamp register (Read Only)
 */
 #define AR5K_LAST_TSTP	0x8080
 /*
 * ADDAC test register [5211+]
 */
 #define AR5K_ADDAC_TEST			0x8054			/* Register Address */
 #define AR5K_ADDAC_TEST_TXCONT 		0x00000001	/* Test continuous tx */
 #define AR5K_ADDAC_TEST_TST_MODE	0x00000002	/* Test mode */
 #define AR5K_ADDAC_TEST_LOOP_EN		0x00000004	/* Enable loop */
 #define AR5K_ADDAC_TEST_LOOP_LEN	0x00000008	/* Loop length (field) */
 #define AR5K_ADDAC_TEST_USE_U8		0x00004000	/* Use upper 8 bits */
 #define AR5K_ADDAC_TEST_MSB		0x00008000	/* State of MSB */
 #define AR5K_ADDAC_TEST_TRIG_SEL	0x00010000	/* Trigger select */
 #define AR5K_ADDAC_TEST_TRIG_PTY	0x00020000	/* Trigger polarity */
 #define AR5K_ADDAC_TEST_RXCONT		0x00040000	/* Continuous capture */
 #define AR5K_ADDAC_TEST_CAPTURE		0x00080000	/* Begin capture */
 #define AR5K_ADDAC_TEST_TST_ARM		0x00100000	/* ARM rx buffer for capture */
 /*
 * Default antenna register [5211+]
 */
 #define AR5K_DEFAULT_ANTENNA	0x8058
 /*
 * Frame control QoS mask register (?) [5211+]
 * (FC_QOS_MASK)
 */
 #define AR5K_FRAME_CTL_QOSM	0x805c
 /*
 * Seq mask register (?) [5211+]
 */
 #define AR5K_SEQ_MASK	0x8060
 /*
 * Retry count register [5210]
 */
 #define AR5K_RETRY_CNT		0x8084			/* Register Address [5210] */
 #define AR5K_RETRY_CNT_SSH	0x0000003f	/* Station short retry count (?) */
 #define AR5K_RETRY_CNT_SLG	0x00000fc0	/* Station long retry count (?) */
 /*
 * Back-off status register [5210]
 */
 #define AR5K_BACKOFF		0x8088			/* Register Address [5210] */
 #define AR5K_BACKOFF_CW		0x000003ff	/* Backoff Contention Window (?) */
 #define AR5K_BACKOFF_CNT	0x03ff0000	/* Backoff count (?) */
 /*
 * NAV register (current)
 */
 #define AR5K_NAV_5210		0x808c
 #define AR5K_NAV_5211		0x8084
 #define	AR5K_NAV		(ah->ah_version == AR5K_AR5210 ? \
 				AR5K_NAV_5210 : AR5K_NAV_5211)
 /*
 * RTS success register
 */
 #define AR5K_RTS_OK_5210	0x8090
 #define AR5K_RTS_OK_5211	0x8088
 #define	AR5K_RTS_OK		(ah->ah_version == AR5K_AR5210 ? \
 				AR5K_RTS_OK_5210 : AR5K_RTS_OK_5211)
 /*
 * RTS failure register
 */
 #define AR5K_RTS_FAIL_5210	0x8094
 #define AR5K_RTS_FAIL_5211	0x808c
 #define	AR5K_RTS_FAIL		(ah->ah_version == AR5K_AR5210 ? \
 				AR5K_RTS_FAIL_5210 : AR5K_RTS_FAIL_5211)
 /*
 * ACK failure register
 */
 #define AR5K_ACK_FAIL_5210	0x8098
 #define AR5K_ACK_FAIL_5211	0x8090
 #define	AR5K_ACK_FAIL		(ah->ah_version == AR5K_AR5210 ? \
 				AR5K_ACK_FAIL_5210 : AR5K_ACK_FAIL_5211)
 /*
 * FCS failure register
 */
 #define AR5K_FCS_FAIL_5210	0x809c
 #define AR5K_FCS_FAIL_5211	0x8094
 #define	AR5K_FCS_FAIL		(ah->ah_version == AR5K_AR5210 ? \
 				AR5K_FCS_FAIL_5210 : AR5K_FCS_FAIL_5211)
 /*
 * Beacon count register
 */
 #define AR5K_BEACON_CNT_5210	0x80a0
 #define AR5K_BEACON_CNT_5211	0x8098
 #define	AR5K_BEACON_CNT		(ah->ah_version == AR5K_AR5210 ? \
 				AR5K_BEACON_CNT_5210 : AR5K_BEACON_CNT_5211)
 /*===5212 Specific PCU registers===*/
 /*
 * Transmit power control register
 */
 #define AR5K_TPC			0x80e8
 #define AR5K_TPC_ACK			0x0000003f	/* ack frames */
 #define AR5K_TPC_ACK_S			0
 #define AR5K_TPC_CTS			0x00003f00	/* cts frames */
 #define AR5K_TPC_CTS_S			8
 #define AR5K_TPC_CHIRP			0x003f0000	/* chirp frames */
 #define AR5K_TPC_CHIRP_S		16
 #define AR5K_TPC_DOPPLER		0x0f000000	/* doppler chirp span */
 #define AR5K_TPC_DOPPLER_S		24
 /*
 * XR (eXtended Range) mode register
 */
 #define AR5K_XRMODE			0x80c0			/* Register Address */
 #define	AR5K_XRMODE_POLL_TYPE_M		0x0000003f	/* Mask for Poll type (?) */
 #define	AR5K_XRMODE_POLL_TYPE_S		0
 #define	AR5K_XRMODE_POLL_SUBTYPE_M	0x0000003c	/* Mask for Poll subtype (?) */
 #define	AR5K_XRMODE_POLL_SUBTYPE_S	2
 #define	AR5K_XRMODE_POLL_WAIT_ALL	0x00000080	/* Wait for poll */
 #define	AR5K_XRMODE_SIFS_DELAY		0x000fff00	/* Mask for SIFS delay */
 #define	AR5K_XRMODE_FRAME_HOLD_M	0xfff00000	/* Mask for frame hold (?) */
 #define	AR5K_XRMODE_FRAME_HOLD_S	20
 /*
 * XR delay register
 */
 #define AR5K_XRDELAY			0x80c4			/* Register Address */
 #define AR5K_XRDELAY_SLOT_DELAY_M	0x0000ffff	/* Mask for slot delay */
 #define AR5K_XRDELAY_SLOT_DELAY_S	0
 #define AR5K_XRDELAY_CHIRP_DELAY_M	0xffff0000	/* Mask for CHIRP data delay */
 #define AR5K_XRDELAY_CHIRP_DELAY_S	16
 /*
 * XR timeout register
 */
 #define AR5K_XRTIMEOUT			0x80c8			/* Register Address */
 #define AR5K_XRTIMEOUT_CHIRP_M		0x0000ffff	/* Mask for CHIRP timeout */
 #define AR5K_XRTIMEOUT_CHIRP_S		0
 #define AR5K_XRTIMEOUT_POLL_M		0xffff0000	/* Mask for Poll timeout */
 #define AR5K_XRTIMEOUT_POLL_S		16
 /*
 * XR chirp register
 */
 #define AR5K_XRCHIRP			0x80cc			/* Register Address */
 #define AR5K_XRCHIRP_SEND		0x00000001	/* Send CHIRP */
 #define AR5K_XRCHIRP_GAP		0xffff0000	/* Mask for CHIRP gap (?) */
 /*
 * XR stomp register
 */
 #define AR5K_XRSTOMP			0x80d0			/* Register Address */
 #define AR5K_XRSTOMP_TX			0x00000001	/* Stomp Tx (?) */
 #define AR5K_XRSTOMP_RX			0x00000002	/* Stomp Rx (?) */
 #define AR5K_XRSTOMP_TX_RSSI		0x00000004	/* Stomp Tx RSSI (?) */
 #define AR5K_XRSTOMP_TX_BSSID		0x00000008	/* Stomp Tx BSSID (?) */
 #define AR5K_XRSTOMP_DATA		0x00000010	/* Stomp data (?)*/
 #define AR5K_XRSTOMP_RSSI_THRES		0x0000ff00	/* Mask for XR RSSI threshold */
 /*
 * First enhanced sleep register
 */
 #define AR5K_SLEEP0			0x80d4			/* Register Address */
 #define AR5K_SLEEP0_NEXT_DTIM		0x0007ffff	/* Mask for next DTIM (?) */
 #define AR5K_SLEEP0_NEXT_DTIM_S		0
 #define AR5K_SLEEP0_ASSUME_DTIM		0x00080000	/* Assume DTIM */
 #define AR5K_SLEEP0_ENH_SLEEP_EN	0x00100000	/* Enable enchanced sleep control */
 #define AR5K_SLEEP0_CABTO		0xff000000	/* Mask for CAB Time Out */
 #define AR5K_SLEEP0_CABTO_S		24
 /*
 * Second enhanced sleep register
 */
 #define AR5K_SLEEP1			0x80d8			/* Register Address */
 #define AR5K_SLEEP1_NEXT_TIM		0x0007ffff	/* Mask for next TIM (?) */
 #define AR5K_SLEEP1_NEXT_TIM_S		0
 #define AR5K_SLEEP1_BEACON_TO		0xff000000	/* Mask for Beacon Time Out */
 #define AR5K_SLEEP1_BEACON_TO_S		24
 /*
 * Third enhanced sleep register
 */
 #define AR5K_SLEEP2			0x80dc			/* Register Address */
 #define AR5K_SLEEP2_TIM_PER		0x0000ffff	/* Mask for TIM period (?) */
 #define AR5K_SLEEP2_TIM_PER_S		0
 #define AR5K_SLEEP2_DTIM_PER		0xffff0000	/* Mask for DTIM period (?) */
 #define AR5K_SLEEP2_DTIM_PER_S		16
 /*
 * BSSID mask registers
 */
 #define AR5K_BSS_IDM0			0x80e0	/* Upper bits */
 #define AR5K_BSS_IDM1			0x80e4	/* Lower bits */
 /*
 * TX power control (TPC) register
 *
 * XXX: PCDAC steps (0.5dbm) or DBM ?
 *
 */
 #define AR5K_TXPC			0x80e8			/* Register Address */
 #define AR5K_TXPC_ACK_M			0x0000003f	/* ACK tx power */
 #define AR5K_TXPC_ACK_S			0
 #define AR5K_TXPC_CTS_M			0x00003f00	/* CTS tx power */
 #define AR5K_TXPC_CTS_S			8
 #define AR5K_TXPC_CHIRP_M		0x003f0000	/* CHIRP tx power */
 #define AR5K_TXPC_CHIRP_S		16
 #define AR5K_TXPC_DOPPLER		0x0f000000	/* Doppler chirp span (?) */
 #define AR5K_TXPC_DOPPLER_S		24
 /*
 * Profile count registers
 */
 #define AR5K_PROFCNT_TX			0x80ec	/* Tx count */
 #define AR5K_PROFCNT_RX			0x80f0	/* Rx count */
 #define AR5K_PROFCNT_RXCLR		0x80f4	/* Clear Rx count */
 #define AR5K_PROFCNT_CYCLE		0x80f8	/* Cycle count (?) */
 /*
 * Quiet period control registers
 */
 #define AR5K_QUIET_CTL1			0x80fc			/* Register Address */
 #define AR5K_QUIET_CTL1_NEXT_QT_TSF	0x0000ffff	/* Next quiet period TSF (TU) */
 #define AR5K_QUIET_CTL1_NEXT_QT_TSF_S	0
 #define AR5K_QUIET_CTL1_QT_EN		0x00010000	/* Enable quiet period */
 #define AR5K_QUIET_CTL1_ACK_CTS_EN	0x00020000	/* Send ACK/CTS during quiet period */
 #define AR5K_QUIET_CTL2			0x8100			/* Register Address */
 #define AR5K_QUIET_CTL2_QT_PER		0x0000ffff	/* Mask for quiet period periodicity */
 #define AR5K_QUIET_CTL2_QT_PER_S	0
 #define AR5K_QUIET_CTL2_QT_DUR		0xffff0000	/* Mask for quiet period duration */
 #define AR5K_QUIET_CTL2_QT_DUR_S	16
 /*
 * TSF parameter register
 */
 #define AR5K_TSF_PARM			0x8104			/* Register Address */
 #define AR5K_TSF_PARM_INC		0x000000ff	/* Mask for TSF increment */
 #define AR5K_TSF_PARM_INC_S		0
 /*
 * QoS NOACK policy
 */
 #define AR5K_QOS_NOACK			0x8108			/* Register Address */
 #define AR5K_QOS_NOACK_2BIT_VALUES	0x0000000f	/* ??? */
 #define AR5K_QOS_NOACK_2BIT_VALUES_S	0
 #define AR5K_QOS_NOACK_BIT_OFFSET	0x00000070	/* ??? */
 #define AR5K_QOS_NOACK_BIT_OFFSET_S	4
 #define AR5K_QOS_NOACK_BYTE_OFFSET	0x00000180	/* ??? */
 #define AR5K_QOS_NOACK_BYTE_OFFSET_S	7
 /*
 * PHY error filter register
 */
 #define AR5K_PHY_ERR_FIL		0x810c
 #define AR5K_PHY_ERR_FIL_RADAR		0x00000020	/* Radar signal */
 #define AR5K_PHY_ERR_FIL_OFDM		0x00020000	/* OFDM false detect (ANI) */
 #define AR5K_PHY_ERR_FIL_CCK		0x02000000	/* CCK false detect (ANI) */
 /*
 * XR latency register
 */
 #define AR5K_XRLAT_TX		0x8110
 /*
 * ACK SIFS register
 */
 #define AR5K_ACKSIFS		0x8114			/* Register Address */
 #define AR5K_ACKSIFS_INC	0x00000000	/* ACK SIFS Increment (field) */
 /*
 * MIC QoS control register (?)
 */
 #define	AR5K_MIC_QOS_CTL		0x8118			/* Register Address */
 #define	AR5K_MIC_QOS_CTL_OFF(_n)	(1 << (_n * 2))
 #define	AR5K_MIC_QOS_CTL_MQ_EN		0x00010000	/* Enable MIC QoS */
 /*
 * MIC QoS select register (?)
 */
 #define	AR5K_MIC_QOS_SEL		0x811c
 #define	AR5K_MIC_QOS_SEL_OFF(_n)	(1 << (_n * 4))
 /*
 * Misc mode control register (?)
 */
 #define	AR5K_MISC_MODE			0x8120			/* Register Address */
 #define	AR5K_MISC_MODE_FBSSID_MATCH	0x00000001	/* Force BSSID match */
 #define	AR5K_MISC_MODE_ACKSIFS_MEM	0x00000002	/* ACK SIFS memory (?) */
 #define	AR5K_MISC_MODE_COMBINED_MIC	0x00000004	/* use rx/tx MIC key */
 /* more bits */
 /*
 * OFDM Filter counter
 */
 #define	AR5K_OFDM_FIL_CNT		0x8124
 /*
 * CCK Filter counter
 */
 #define	AR5K_CCK_FIL_CNT		0x8128
 /*
 * PHY Error Counters (?)
 */
 #define	AR5K_PHYERR_CNT1		0x812c
 #define	AR5K_PHYERR_CNT1_MASK		0x8130
 #define	AR5K_PHYERR_CNT2		0x8134
 #define	AR5K_PHYERR_CNT2_MASK		0x8138
 /*
 * TSF Threshold register (?)
 */
 #define	AR5K_TSF_THRES			0x813c
 /*
 * TODO: Wake On Wireless registers
 * Range: 0x8147 - 0x818c
 */
 /*
 * Rate -> ACK SIFS mapping table (32 entries)
 */
 #define	AR5K_RATE_ACKSIFS_BASE		0x8680			/* Register Address */
 #define	AR5K_RATE_ACKSIFS(_n)		(AR5K_RATE_ACKSIFS_BSE + ((_n) << 2))
 #define	AR5K_RATE_ACKSIFS_NORMAL	0x00000001	/* Normal SIFS (field) */
 #define	AR5K_RATE_ACKSIFS_TURBO		0x00000400	/* Turbo SIFS (field) */
 /*
 * Rate -> duration mapping table (32 entries)
 */
 #define AR5K_RATE_DUR_BASE		0x8700
 #define AR5K_RATE_DUR(_n)		(AR5K_RATE_DUR_BASE + ((_n) << 2))
 /*
 * Rate -> db mapping table
 * (8 entries, each one has 4 8bit fields)
 */
 #define AR5K_RATE2DB_BASE		0x87c0
 #define AR5K_RATE2DB(_n)		(AR5K_RATE2DB_BASE + ((_n) << 2))
 /*
 * db -> Rate mapping table
 * (8 entries, each one has 4 8bit fields)
 */
 #define AR5K_DB2RATE_BASE		0x87e0
 #define AR5K_DB2RATE(_n)		(AR5K_DB2RATE_BASE + ((_n) << 2))
 /*===5212 end===*/
 /*
 * Key table (WEP) register
 */
 #define AR5K_KEYTABLE_0_5210		0x9000
 #define AR5K_KEYTABLE_0_5211		0x8800
 #define AR5K_KEYTABLE_5210(_n)		(AR5K_KEYTABLE_0_5210 + ((_n) << 5))
 #define AR5K_KEYTABLE_5211(_n)		(AR5K_KEYTABLE_0_5211 + ((_n) << 5))
 #define	AR5K_KEYTABLE(_n)		(ah->ah_version == AR5K_AR5210 ? \
 					AR5K_KEYTABLE_5210(_n) : AR5K_KEYTABLE_5211(_n))
 #define AR5K_KEYTABLE_OFF(_n, x)	(AR5K_KEYTABLE(_n) + (x << 2))
 #define AR5K_KEYTABLE_TYPE(_n)		AR5K_KEYTABLE_OFF(_n, 5)
 #define AR5K_KEYTABLE_TYPE_40		0x00000000
 #define AR5K_KEYTABLE_TYPE_104		0x00000001
 #define AR5K_KEYTABLE_TYPE_128		0x00000003
 #define AR5K_KEYTABLE_TYPE_TKIP		0x00000004	/* [5212+] */
 #define AR5K_KEYTABLE_TYPE_AES		0x00000005	/* [5211+] */
 #define AR5K_KEYTABLE_TYPE_CCM		0x00000006	/* [5212+] */
 #define AR5K_KEYTABLE_TYPE_NULL		0x00000007	/* [5211+] */
 #define AR5K_KEYTABLE_ANTENNA		0x00000008	/* [5212+] */
 #define AR5K_KEYTABLE_MAC0(_n)		AR5K_KEYTABLE_OFF(_n, 6)
 #define AR5K_KEYTABLE_MAC1(_n)		AR5K_KEYTABLE_OFF(_n, 7)
 #define AR5K_KEYTABLE_VALID		0x00008000
 /* If key type is TKIP and MIC is enabled
 * MIC key goes in offset entry + 64 */
 #define	AR5K_KEYTABLE_MIC_OFFSET	64
 /* WEP 40-bit	= 40-bit  entered key + 24 bit IV = 64-bit
 * WEP 104-bit	= 104-bit entered key + 24-bit IV = 128-bit
 * WEP 128-bit	= 128-bit entered key + 24 bit IV = 152-bit
 *
 * Some vendors have introduced bigger WEP keys to address
 * security vulnerabilities in WEP. This includes:
 *
 * WEP 232-bit = 232-bit entered key + 24 bit IV = 256-bit
 *
 * We can expand this if we find ar5k Atheros cards with a larger
 * key table size.
 */
 #define AR5K_KEYTABLE_SIZE_5210		64
 #define AR5K_KEYTABLE_SIZE_5211		128
 #define	AR5K_KEYTABLE_SIZE		(ah->ah_version == AR5K_AR5210 ? \
 					AR5K_KEYTABLE_SIZE_5210 : AR5K_KEYTABLE_SIZE_5211)
 /*===PHY REGISTERS===*/
 /*
 * PHY registers start
 */
 #define	AR5K_PHY_BASE			0x9800
 #define	AR5K_PHY(_n)			(AR5K_PHY_BASE + ((_n) << 2))
 /*
 * TST_2 (Misc config parameters)
 */
 #define	AR5K_PHY_TST2			0x9800			/* Register Address */
 #define AR5K_PHY_TST2_TRIG_SEL		0x00000007	/* Trigger select (?)*/
 #define AR5K_PHY_TST2_TRIG		0x00000010	/* Trigger (?) */
 #define AR5K_PHY_TST2_CBUS_MODE		0x00000060	/* Cardbus mode (?) */
 #define AR5K_PHY_TST2_CLK32		0x00000400	/* CLK_OUT is CLK32 (32Khz external) */
 #define AR5K_PHY_TST2_CHANCOR_DUMP_EN	0x00000800	/* Enable Chancor dump (?) */
 #define AR5K_PHY_TST2_EVEN_CHANCOR_DUMP	0x00001000	/* Even Chancor dump (?) */
 #define AR5K_PHY_TST2_RFSILENT_EN	0x00002000	/* Enable RFSILENT */
 #define AR5K_PHY_TST2_ALT_RFDATA	0x00004000	/* Alternate RFDATA (5-2GHz switch ?) */
 #define AR5K_PHY_TST2_MINI_OBS_EN	0x00008000	/* Enable mini OBS (?) */
 #define AR5K_PHY_TST2_RX2_IS_RX5_INV	0x00010000	/* 2GHz rx path is the 5GHz path inverted (?) */
 #define AR5K_PHY_TST2_SLOW_CLK160	0x00020000	/* Slow CLK160 (?) */
 #define AR5K_PHY_TST2_AGC_OBS_SEL_3	0x00040000	/* AGC OBS Select 3 (?) */
 #define AR5K_PHY_TST2_BBB_OBS_SEL	0x00080000	/* BB OBS Select (field ?) */
 #define AR5K_PHY_TST2_ADC_OBS_SEL	0x00800000	/* ADC OBS Select (field ?) */
 #define AR5K_PHY_TST2_RX_CLR_SEL	0x08000000	/* RX Clear Select (?) */
 #define AR5K_PHY_TST2_FORCE_AGC_CLR	0x10000000	/* Force AGC clear (?) */
 #define AR5K_PHY_SHIFT_2GHZ		0x00004007	/* Used to access 2GHz radios */
 #define AR5K_PHY_SHIFT_5GHZ		0x00000007	/* Used to access 5GHz radios (default) */
 /*
 * PHY frame control register [5110] /turbo mode register [5111+]
 *
 * There is another frame control register for [5111+]
 * at address 0x9944 (see below) but the 2 first flags
 * are common here between 5110 frame control register
 * and [5111+] turbo mode register, so this also works as
 * a "turbo mode register" for 5110. We treat this one as
 * a frame control register for 5110 below.
 */
 #define	AR5K_PHY_TURBO			0x9804			/* Register Address */
 #define	AR5K_PHY_TURBO_MODE		0x00000001	/* Enable turbo mode */
 #define	AR5K_PHY_TURBO_SHORT		0x00000002	/* Set short symbols to turbo mode */
 #define	AR5K_PHY_TURBO_MIMO		0x00000004	/* Set turbo for mimo mimo */
 /*
 * PHY agility command register
 * (aka TST_1)
 */
 #define	AR5K_PHY_AGC			0x9808			/* Register Address */
 #define	AR5K_PHY_TST1			0x9808
 #define	AR5K_PHY_AGC_DISABLE		0x08000000	/* Disable AGC to A2 (?)*/
 #define	AR5K_PHY_TST1_TXHOLD		0x00003800	/* Set tx hold (?) */
 #define	AR5K_PHY_TST1_TXSRC_SRC		0x00000002	/* Used with bit 7 (?) */
 #define	AR5K_PHY_TST1_TXSRC_SRC_S	1
 #define	AR5K_PHY_TST1_TXSRC_ALT		0x00000080	/* Set input to tsdac (?) */
 #define	AR5K_PHY_TST1_TXSRC_ALT_S	7
 /*
 * PHY timing register 3 [5112+]
 */
 #define	AR5K_PHY_TIMING_3		0x9814
 #define	AR5K_PHY_TIMING_3_DSC_MAN	0xfffe0000
 #define	AR5K_PHY_TIMING_3_DSC_MAN_S	17
 #define	AR5K_PHY_TIMING_3_DSC_EXP	0x0001e000
 #define	AR5K_PHY_TIMING_3_DSC_EXP_S	13
 /*
 * PHY chip revision register
 */
 #define	AR5K_PHY_CHIP_ID		0x9818
 /*
 * PHY activation register
 */
 #define	AR5K_PHY_ACT			0x981c			/* Register Address */
 #define	AR5K_PHY_ACT_ENABLE		0x00000001	/* Activate PHY */
 #define	AR5K_PHY_ACT_DISABLE		0x00000002	/* Deactivate PHY */
 /*
 * PHY RF control registers
 */
 #define AR5K_PHY_RF_CTL2		0x9824			/* Register Address */
 #define	AR5K_PHY_RF_CTL2_TXF2TXD_START	0x0000000f	/* TX frame to TX data start */
 #define	AR5K_PHY_RF_CTL2_TXF2TXD_START_S	0
 #define AR5K_PHY_RF_CTL3		0x9828			/* Register Address */
 #define AR5K_PHY_RF_CTL3_TXE2XLNA_ON	0x0000ff00	/* TX end to XLNA on */
 #define	AR5K_PHY_RF_CTL3_TXE2XLNA_ON_S	8
 #define	AR5K_PHY_ADC_CTL			0x982c
 #define	AR5K_PHY_ADC_CTL_INBUFGAIN_OFF		0x00000003
 #define	AR5K_PHY_ADC_CTL_INBUFGAIN_OFF_S	0
 #define	AR5K_PHY_ADC_CTL_PWD_DAC_OFF		0x00002000
 #define	AR5K_PHY_ADC_CTL_PWD_BAND_GAP_OFF	0x00004000
 #define	AR5K_PHY_ADC_CTL_PWD_ADC_OFF		0x00008000
 #define	AR5K_PHY_ADC_CTL_INBUFGAIN_ON		0x00030000
 #define	AR5K_PHY_ADC_CTL_INBUFGAIN_ON_S		16
 #define AR5K_PHY_RF_CTL4		0x9834			/* Register Address */
 #define AR5K_PHY_RF_CTL4_TXF2XPA_A_ON	0x00000001	/* TX frame to XPA A on (field) */
 #define AR5K_PHY_RF_CTL4_TXF2XPA_B_ON	0x00000100	/* TX frame to XPA B on (field) */
 #define	AR5K_PHY_RF_CTL4_TXE2XPA_A_OFF	0x00010000	/* TX end to XPA A off (field) */
 #define AR5K_PHY_RF_CTL4_TXE2XPA_B_OFF	0x01000000	/* TX end to XPA B off (field) */
 /*
 * Pre-Amplifier control register
 * (XPA -> external pre-amplifier)
 */
 #define	AR5K_PHY_PA_CTL			0x9838			/* Register Address */
 #define	AR5K_PHY_PA_CTL_XPA_A_HI	0x00000001	/* XPA A high (?) */
 #define	AR5K_PHY_PA_CTL_XPA_B_HI	0x00000002	/* XPA B high (?) */
 #define	AR5K_PHY_PA_CTL_XPA_A_EN	0x00000004	/* Enable XPA A */
 #define	AR5K_PHY_PA_CTL_XPA_B_EN	0x00000008	/* Enable XPA B */
 /*
 * PHY settling register
 */
 #define AR5K_PHY_SETTLING		0x9844			/* Register Address */
 #define	AR5K_PHY_SETTLING_AGC		0x0000007f	/* AGC settling time */
 #define	AR5K_PHY_SETTLING_AGC_S		0
 #define	AR5K_PHY_SETTLING_SWITCH	0x00003f80	/* Switch settlig time */
 #define	AR5K_PHY_SETTLING_SWITCH_S	7
 /*
 * PHY Gain registers
 */
 #define AR5K_PHY_GAIN			0x9848			/* Register Address */
 #define	AR5K_PHY_GAIN_TXRX_ATTEN	0x0003f000	/* TX-RX Attenuation */
 #define	AR5K_PHY_GAIN_TXRX_ATTEN_S	12
 #define	AR5K_PHY_GAIN_TXRX_RF_MAX	0x007c0000
 #define	AR5K_PHY_GAIN_TXRX_RF_MAX_S	18
 #define	AR5K_PHY_GAIN_OFFSET		0x984c			/* Register Address */
 #define	AR5K_PHY_GAIN_OFFSET_RXTX_FLAG	0x00020000	/* RX-TX flag (?) */
 /*
 * Desired ADC/PGA size register
 * (for more infos read ANI patent)
 */
 #define AR5K_PHY_DESIRED_SIZE		0x9850			/* Register Address */
 #define	AR5K_PHY_DESIRED_SIZE_ADC	0x000000ff	/* ADC desired size */
 #define	AR5K_PHY_DESIRED_SIZE_ADC_S	0
 #define	AR5K_PHY_DESIRED_SIZE_PGA	0x0000ff00	/* PGA desired size */
 #define	AR5K_PHY_DESIRED_SIZE_PGA_S	8
 #define	AR5K_PHY_DESIRED_SIZE_TOT	0x0ff00000	/* Total desired size */
 #define	AR5K_PHY_DESIRED_SIZE_TOT_S	20
 /*
 * PHY signal register
 * (for more infos read ANI patent)
 */
 #define	AR5K_PHY_SIG			0x9858			/* Register Address */
 #define	AR5K_PHY_SIG_FIRSTEP		0x0003f000	/* FIRSTEP */
 #define	AR5K_PHY_SIG_FIRSTEP_S		12
 #define	AR5K_PHY_SIG_FIRPWR		0x03fc0000	/* FIPWR */
 #define	AR5K_PHY_SIG_FIRPWR_S		18
 /*
 * PHY coarse agility control register
 * (for more infos read ANI patent)
 */
 #define	AR5K_PHY_AGCCOARSE		0x985c			/* Register Address */
 #define	AR5K_PHY_AGCCOARSE_LO		0x00007f80	/* AGC Coarse low */
 #define	AR5K_PHY_AGCCOARSE_LO_S		7
 #define	AR5K_PHY_AGCCOARSE_HI		0x003f8000	/* AGC Coarse high */
 #define	AR5K_PHY_AGCCOARSE_HI_S		15
 /*
 * PHY agility control register
 */
 #define	AR5K_PHY_AGCCTL			0x9860			/* Register address */
 #define	AR5K_PHY_AGCCTL_CAL		0x00000001	/* Enable PHY calibration */
 #define	AR5K_PHY_AGCCTL_NF		0x00000002	/* Enable Noise Floor calibration */
 #define	AR5K_PHY_AGCCTL_OFDM_DIV_DIS	0x00000008	/* Disable antenna diversity on OFDM modes */
 #define	AR5K_PHY_AGCCTL_NF_EN		0x00008000	/* Enable nf calibration to happen (?) */
 #define	AR5K_PHY_AGCTL_FLTR_CAL		0x00010000	/* Allow filter calibration (?) */
 #define	AR5K_PHY_AGCCTL_NF_NOUPDATE	0x00020000	/* Don't update nf automaticaly */
 /*
 * PHY noise floor status register
 */
 #define AR5K_PHY_NF			0x9864			/* Register address */
 #define AR5K_PHY_NF_M			0x000001ff	/* Noise floor mask */
 #define AR5K_PHY_NF_ACTIVE		0x00000100	/* Noise floor calibration still active */
 #define AR5K_PHY_NF_RVAL(_n)		(((_n) >> 19) & AR5K_PHY_NF_M)
 #define AR5K_PHY_NF_AVAL(_n)		(-((_n) ^ AR5K_PHY_NF_M) + 1)
 #define AR5K_PHY_NF_SVAL(_n)		(((_n) & AR5K_PHY_NF_M) | (1 << 9))
 #define	AR5K_PHY_NF_THRESH62		0x0007f000	/* Thresh62 -check ANI patent- (field) */
 #define	AR5K_PHY_NF_THRESH62_S		12
 #define	AR5K_PHY_NF_MINCCA_PWR		0x0ff80000	/* ??? */
 #define	AR5K_PHY_NF_MINCCA_PWR_S	19
 /*
 * PHY ADC saturation register [5110]
 */
 #define	AR5K_PHY_ADCSAT			0x9868
 #define	AR5K_PHY_ADCSAT_ICNT		0x0001f800
 #define	AR5K_PHY_ADCSAT_ICNT_S		11
 #define	AR5K_PHY_ADCSAT_THR		0x000007e0
 #define	AR5K_PHY_ADCSAT_THR_S		5
 /*
 * PHY Weak ofdm signal detection threshold registers (ANI) [5212+]
 */
 /* High thresholds */
 #define AR5K_PHY_WEAK_OFDM_HIGH_THR		0x9868
 #define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_COUNT	0x0000001f
 #define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_COUNT_S	0
 #define AR5K_PHY_WEAK_OFDM_HIGH_THR_M1		0x00fe0000
 #define AR5K_PHY_WEAK_OFDM_HIGH_THR_M1_S	17
 #define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2		0x7f000000
 #define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_S	24
 /* Low thresholds */
 #define AR5K_PHY_WEAK_OFDM_LOW_THR 		0x986c
 #define AR5K_PHY_WEAK_OFDM_LOW_THR_SELFCOR_EN	0x00000001
 #define AR5K_PHY_WEAK_OFDM_LOW_THR_M2_COUNT	0x00003f00
 #define AR5K_PHY_WEAK_OFDM_LOW_THR_M2_COUNT_S	8
 #define AR5K_PHY_WEAK_OFDM_LOW_THR_M1		0x001fc000
 #define AR5K_PHY_WEAK_OFDM_LOW_THR_M1_S		14
 #define AR5K_PHY_WEAK_OFDM_LOW_THR_M2		0x0fe00000
 #define AR5K_PHY_WEAK_OFDM_LOW_THR_M2_S		21
 /*
 * PHY sleep registers [5112+]
 */
 #define AR5K_PHY_SCR			0x9870
 #define AR5K_PHY_SLMT			0x9874
 #define AR5K_PHY_SLMT_32MHZ		0x0000007f
 #define AR5K_PHY_SCAL			0x9878
 #define AR5K_PHY_SCAL_32MHZ		0x0000000e
 #define	AR5K_PHY_SCAL_32MHZ_2417	0x0000000a
 #define	AR5K_PHY_SCAL_32MHZ_HB63	0x00000032
 /*
 * PHY PLL (Phase Locked Loop) control register
 */
 #define	AR5K_PHY_PLL			0x987c
 #define	AR5K_PHY_PLL_20MHZ		0x00000013	/* For half rate (?) */
 /* 40MHz -> 5GHz band */
 #define	AR5K_PHY_PLL_40MHZ_5211		0x00000018
 #define	AR5K_PHY_PLL_40MHZ_5212		0x000000aa
 #define	AR5K_PHY_PLL_40MHZ_5413		0x00000004
 #define	AR5K_PHY_PLL_40MHZ		(ah->ah_version == AR5K_AR5211 ? \
 					AR5K_PHY_PLL_40MHZ_5211 : AR5K_PHY_PLL_40MHZ_5212)
 /* 44MHz -> 2.4GHz band */
 #define	AR5K_PHY_PLL_44MHZ_5211		0x00000019
 #define	AR5K_PHY_PLL_44MHZ_5212		0x000000ab
 #define	AR5K_PHY_PLL_44MHZ		(ah->ah_version == AR5K_AR5211 ? \
 					AR5K_PHY_PLL_44MHZ_5211 : AR5K_PHY_PLL_44MHZ_5212)
 #define AR5K_PHY_PLL_RF5111		0x00000000
 #define AR5K_PHY_PLL_RF5112		0x00000040
 #define	AR5K_PHY_PLL_HALF_RATE		0x00000100
 #define	AR5K_PHY_PLL_QUARTER_RATE	0x00000200
 /*
 * RF Buffer register
 *
 * It's obvious from the code that 0x989c is the buffer register but
 * for the other special registers that we write to after sending each
 * packet, i have no idea. So i'll name them BUFFER_CONTROL_X registers
 * for now. It's interesting that they are also used for some other operations.
 */
 #define AR5K_RF_BUFFER			0x989c
 #define AR5K_RF_BUFFER_CONTROL_0	0x98c0	/* Channel on 5110 */
 #define AR5K_RF_BUFFER_CONTROL_1	0x98c4	/* Bank 7 on 5112 */
 #define AR5K_RF_BUFFER_CONTROL_2	0x98cc	/* Bank 7 on 5111 */
 #define AR5K_RF_BUFFER_CONTROL_3	0x98d0	/* Bank 2 on 5112 */
 						/* Channel set on 5111 */
 						/* Used to read radio revision*/
 #define AR5K_RF_BUFFER_CONTROL_4	0x98d4  /* RF Stage register on 5110 */
 						/* Bank 0,1,2,6 on 5111 */
 						/* Bank 1 on 5112 */
 						/* Used during activation on 5111 */
 #define AR5K_RF_BUFFER_CONTROL_5	0x98d8	/* Bank 3 on 5111 */
 						/* Used during activation on 5111 */
 						/* Channel on 5112 */
 						/* Bank 6 on 5112 */
 #define AR5K_RF_BUFFER_CONTROL_6	0x98dc	/* Bank 3 on 5112 */
 /*
 * PHY RF stage register [5210]
 */
 #define AR5K_PHY_RFSTG			0x98d4
 #define AR5K_PHY_RFSTG_DISABLE		0x00000021
 /*
 * BIN masks (?)
 */
 #define	AR5K_PHY_BIN_MASK_1	0x9900
 #define	AR5K_PHY_BIN_MASK_2	0x9904
 #define	AR5K_PHY_BIN_MASK_3	0x9908
 #define	AR5K_PHY_BIN_MASK_CTL		0x990c
 #define	AR5K_PHY_BIN_MASK_CTL_MASK_4	0x00003fff
 #define	AR5K_PHY_BIN_MASK_CTL_MASK_4_S	0
 #define	AR5K_PHY_BIN_MASK_CTL_RATE	0xff000000
 #define	AR5K_PHY_BIN_MASK_CTL_RATE_S	24
 /*
 * PHY Antenna control register
 */
 #define AR5K_PHY_ANT_CTL		0x9910			/* Register Address */
 #define	AR5K_PHY_ANT_CTL_TXRX_EN	0x00000001	/* Enable TX/RX (?) */
 #define	AR5K_PHY_ANT_CTL_SECTORED_ANT	0x00000004	/* Sectored Antenna */
 #define	AR5K_PHY_ANT_CTL_HITUNE5	0x00000008	/* Hitune5 (?) */
 #define	AR5K_PHY_ANT_CTL_SWTABLE_IDLE	0x000003f0	/* Switch table idle (?) */
 #define	AR5K_PHY_ANT_CTL_SWTABLE_IDLE_S	4
 /*
 * PHY receiver delay register [5111+]
 */
 #define	AR5K_PHY_RX_DELAY		0x9914			/* Register Address */
 #define	AR5K_PHY_RX_DELAY_M		0x00003fff	/* Mask for RX activate to receive delay (/100ns) */
 /*
 * PHY max rx length register (?) [5111]
 */
 #define	AR5K_PHY_MAX_RX_LEN		0x991c
 /*
 * PHY timing register 4
 * I(nphase)/Q(adrature) calibration register [5111+]
 */
 #define	AR5K_PHY_IQ			0x9920			/* Register Address */
 #define	AR5K_PHY_IQ_CORR_Q_Q_COFF	0x0000001f	/* Mask for q correction info */
 #define	AR5K_PHY_IQ_CORR_Q_I_COFF	0x000007e0	/* Mask for i correction info */
 #define	AR5K_PHY_IQ_CORR_Q_I_COFF_S	5
 #define	AR5K_PHY_IQ_CORR_ENABLE		0x00000800	/* Enable i/q correction */
 #define	AR5K_PHY_IQ_CAL_NUM_LOG_MAX	0x0000f000	/* Mask for max number of samples in log scale */
 #define	AR5K_PHY_IQ_CAL_NUM_LOG_MAX_S	12
 #define	AR5K_PHY_IQ_RUN			0x00010000	/* Run i/q calibration */
 #define	AR5K_PHY_IQ_USE_PT_DF		0x00020000	/* Use pilot track df (?) */
 #define	AR5K_PHY_IQ_EARLY_TRIG_THR	0x00200000	/* Early trigger threshold (?) (field) */
 #define	AR5K_PHY_IQ_PILOT_MASK_EN	0x10000000	/* Enable pilot mask (?) */
 #define	AR5K_PHY_IQ_CHAN_MASK_EN	0x20000000	/* Enable channel mask (?) */
 #define	AR5K_PHY_IQ_SPUR_FILT_EN	0x40000000	/* Enable spur filter */
 #define	AR5K_PHY_IQ_SPUR_RSSI_EN	0x80000000	/* Enable spur rssi */
 /*
 * PHY timing register 5
 * OFDM Self-correlator Cyclic RSSI threshold params
 * (Check out bb_cycpwr_thr1 on ANI patent)
 */
 #define	AR5K_PHY_OFDM_SELFCORR			0x9924			/* Register Address */
 #define	AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1_EN	0x00000001	/* Enable cyclic RSSI thr 1 */
 #define	AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1	0x000000fe	/* Mask for Cyclic RSSI threshold 1 */
 #define	AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1_S	1
 #define	AR5K_PHY_OFDM_SELFCORR_CYPWR_THR3	0x00000100	/* Cyclic RSSI threshold 3 (field) (?) */
 #define	AR5K_PHY_OFDM_SELFCORR_RSSI_1ATHR_EN	0x00008000	/* Enable 1A RSSI threshold (?) */
 #define	AR5K_PHY_OFDM_SELFCORR_RSSI_1ATHR	0x00010000	/* 1A RSSI threshold (field) (?) */
 #define	AR5K_PHY_OFDM_SELFCORR_LSCTHR_HIRSSI	0x00800000	/* Long sc threshold hi rssi (?) */
 /*
 * PHY-only warm reset register
 */
 #define	AR5K_PHY_WARM_RESET		0x9928
 /*
 * PHY-only control register
 */
 #define AR5K_PHY_CTL			0x992c			/* Register Address */
 #define	AR5K_PHY_CTL_RX_DRAIN_RATE	0x00000001	/* RX drain rate (?) */
 #define	AR5K_PHY_CTL_LATE_TX_SIG_SYM	0x00000002	/* Late tx signal symbol (?) */
 #define	AR5K_PHY_CTL_GEN_SCRAMBLER	0x00000004	/* Generate scrambler */
 #define	AR5K_PHY_CTL_TX_ANT_SEL		0x00000008	/* TX antenna select */
 #define	AR5K_PHY_CTL_TX_ANT_STATIC	0x00000010	/* Static TX antenna */
 #define	AR5K_PHY_CTL_RX_ANT_SEL		0x00000020	/* RX antenna select */
 #define	AR5K_PHY_CTL_RX_ANT_STATIC	0x00000040	/* Static RX antenna */
 #define	AR5K_PHY_CTL_LOW_FREQ_SLE_EN	0x00000080	/* Enable low freq sleep */
 /*
 * PHY PAPD probe register [5111+]
 */
 #define	AR5K_PHY_PAPD_PROBE		0x9930
 #define	AR5K_PHY_PAPD_PROBE_SH_HI_PAR	0x00000001
 #define	AR5K_PHY_PAPD_PROBE_PCDAC_BIAS	0x00000002
 #define	AR5K_PHY_PAPD_PROBE_COMP_GAIN	0x00000040
 #define	AR5K_PHY_PAPD_PROBE_TXPOWER	0x00007e00
 #define	AR5K_PHY_PAPD_PROBE_TXPOWER_S	9
 #define	AR5K_PHY_PAPD_PROBE_TX_NEXT	0x00008000
 #define	AR5K_PHY_PAPD_PROBE_PREDIST_EN	0x00010000
 #define	AR5K_PHY_PAPD_PROBE_TYPE	0x01800000	/* [5112+] */
 #define	AR5K_PHY_PAPD_PROBE_TYPE_S	23
 #define	AR5K_PHY_PAPD_PROBE_TYPE_OFDM	0
 #define	AR5K_PHY_PAPD_PROBE_TYPE_XR	1
 #define	AR5K_PHY_PAPD_PROBE_TYPE_CCK	2
 #define	AR5K_PHY_PAPD_PROBE_GAINF	0xfe000000
 #define	AR5K_PHY_PAPD_PROBE_GAINF_S	25
 #define	AR5K_PHY_PAPD_PROBE_INI_5111	0x00004883	/* [5212+] */
 #define	AR5K_PHY_PAPD_PROBE_INI_5112	0x00004882	/* [5212+] */
 /*
 * PHY TX rate power registers [5112+]
 */
 #define	AR5K_PHY_TXPOWER_RATE1			0x9934
 #define	AR5K_PHY_TXPOWER_RATE2			0x9938
 #define	AR5K_PHY_TXPOWER_RATE_MAX		0x993c
 #define	AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE	0x00000040
 #define	AR5K_PHY_TXPOWER_RATE3			0xa234
 #define	AR5K_PHY_TXPOWER_RATE4			0xa238
 /*
 * PHY frame control register [5111+]
 */
 #define	AR5K_PHY_FRAME_CTL_5210		0x9804
 #define	AR5K_PHY_FRAME_CTL_5211		0x9944
 #define	AR5K_PHY_FRAME_CTL		(ah->ah_version == AR5K_AR5210 ? \
 					AR5K_PHY_FRAME_CTL_5210 : AR5K_PHY_FRAME_CTL_5211)
 /*---[5111+]---*/
 #define	AR5K_PHY_FRAME_CTL_TX_CLIP	0x00000038	/* Mask for tx clip (?) */
 #define	AR5K_PHY_FRAME_CTL_TX_CLIP_S	3
 #define	AR5K_PHY_FRAME_CTL_PREP_CHINFO	0x00010000	/* Prepend chan info */
 #define	AR5K_PHY_FRAME_CTL_EMU		0x80000000
 #define	AR5K_PHY_FRAME_CTL_EMU_S	31
 /*---[5110/5111]---*/
 #define	AR5K_PHY_FRAME_CTL_TIMING_ERR	0x01000000	/* PHY timing error */
 #define	AR5K_PHY_FRAME_CTL_PARITY_ERR	0x02000000	/* Parity error */
 #define	AR5K_PHY_FRAME_CTL_ILLRATE_ERR	0x04000000	/* Illegal rate */
 #define	AR5K_PHY_FRAME_CTL_ILLLEN_ERR	0x08000000	/* Illegal length */
 #define	AR5K_PHY_FRAME_CTL_SERVICE_ERR	0x20000000
 #define	AR5K_PHY_FRAME_CTL_TXURN_ERR	0x40000000	/* TX underrun */
 #define AR5K_PHY_FRAME_CTL_INI		AR5K_PHY_FRAME_CTL_SERVICE_ERR | \
 			AR5K_PHY_FRAME_CTL_TXURN_ERR | \
 			AR5K_PHY_FRAME_CTL_ILLLEN_ERR | \
 			AR5K_PHY_FRAME_CTL_ILLRATE_ERR | \
 			AR5K_PHY_FRAME_CTL_PARITY_ERR | \
 			AR5K_PHY_FRAME_CTL_TIMING_ERR
 /*
 * PHY Tx Power adjustment register [5212A+]
 */
 #define	AR5K_PHY_TX_PWR_ADJ			0x994c
 #define	AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DELTA	0x00000fc0
 #define	AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DELTA_S	6
 #define	AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_INDEX	0x00fc0000
 #define	AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_INDEX_S	18
 /*
 * PHY radar detection register [5111+]
 */
 #define	AR5K_PHY_RADAR			0x9954
 #define	AR5K_PHY_RADAR_ENABLE		0x00000001
 #define	AR5K_PHY_RADAR_DISABLE		0x00000000
 #define AR5K_PHY_RADAR_INBANDTHR    	0x0000003e	/* Inband threshold
 							5-bits, units unknown {0..31}
 							(? MHz ?) */
 #define AR5K_PHY_RADAR_INBANDTHR_S	1
 #define AR5K_PHY_RADAR_PRSSI_THR    	0x00000fc0	/* Pulse RSSI/SNR threshold
 							6-bits, dBm range {0..63}
 							in dBm units. */
 #define AR5K_PHY_RADAR_PRSSI_THR_S	6
 #define AR5K_PHY_RADAR_PHEIGHT_THR   	0x0003f000	/* Pulse height threshold
 							6-bits, dBm range {0..63}
 							in dBm units. */
 #define AR5K_PHY_RADAR_PHEIGHT_THR_S	12
 #define AR5K_PHY_RADAR_RSSI_THR    	0x00fc0000	/* Radar RSSI/SNR threshold.
 							6-bits, dBm range {0..63}
 							in dBm units. */
 #define AR5K_PHY_RADAR_RSSI_THR_S	18
 #define AR5K_PHY_RADAR_FIRPWR_THR	0x7f000000	/* Finite Impulse Response
 							filter power out threshold.
 							7-bits, standard power range
 							{0..127} in 1/2 dBm units. */
 #define AR5K_PHY_RADAR_FIRPWR_THRS	24
 /*
 * PHY antenna switch table registers
 */
 #define AR5K_PHY_ANT_SWITCH_TABLE_0	0x9960
 #define AR5K_PHY_ANT_SWITCH_TABLE_1	0x9964
 /*
 * PHY Noise floor threshold
 */
 #define AR5K_PHY_NFTHRES		0x9968
 /*
 * Sigma Delta register (?) [5213]
 */
 #define AR5K_PHY_SIGMA_DELTA		0x996C
 #define AR5K_PHY_SIGMA_DELTA_ADC_SEL	0x00000003
 #define AR5K_PHY_SIGMA_DELTA_ADC_SEL_S	0
 #define AR5K_PHY_SIGMA_DELTA_FILT2	0x000000f8
 #define AR5K_PHY_SIGMA_DELTA_FILT2_S	3
 #define AR5K_PHY_SIGMA_DELTA_FILT1	0x00001f00
 #define AR5K_PHY_SIGMA_DELTA_FILT1_S	8
 #define AR5K_PHY_SIGMA_DELTA_ADC_CLIP	0x01ffe000
 #define AR5K_PHY_SIGMA_DELTA_ADC_CLIP_S	13
 /*
 * RF restart register [5112+] (?)
 */
 #define AR5K_PHY_RESTART		0x9970		/* restart */
 #define AR5K_PHY_RESTART_DIV_GC		0x001c0000	/* Fast diversity gc_limit (?) */
 #define AR5K_PHY_RESTART_DIV_GC_S	18
 /*
 * RF Bus access request register (for synth-oly channel switching)
 */
 #define AR5K_PHY_RFBUS_REQ		0x997C
 #define AR5K_PHY_RFBUS_REQ_REQUEST	0x00000001
 /*
 * Spur mitigation masks (?)
 */
 #define AR5K_PHY_TIMING_7		0x9980
 #define AR5K_PHY_TIMING_8		0x9984
 #define AR5K_PHY_TIMING_8_PILOT_MASK_2		0x000fffff
 #define AR5K_PHY_TIMING_8_PILOT_MASK_2_S	0
 #define AR5K_PHY_BIN_MASK2_1		0x9988
 #define AR5K_PHY_BIN_MASK2_2		0x998c
 #define AR5K_PHY_BIN_MASK2_3		0x9990
 #define AR5K_PHY_BIN_MASK2_4		0x9994
 #define AR5K_PHY_BIN_MASK2_4_MASK_4	0x00003fff
 #define AR5K_PHY_BIN_MASK2_4_MASK_4_S	0
 #define AR5K_PHY_TIMING_9			0x9998
 #define AR5K_PHY_TIMING_10			0x999c
 #define AR5K_PHY_TIMING_10_PILOT_MASK_2		0x000fffff
 #define AR5K_PHY_TIMING_10_PILOT_MASK_2_S	0
 /*
 * Spur mitigation control
 */
 #define AR5K_PHY_TIMING_11			0x99a0		/* Register address */
 #define AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE	0x000fffff	/* Spur delta phase */
 #define AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE_S	0
 #define AR5K_PHY_TIMING_11_SPUR_FREQ_SD		0x3ff00000	/* Freq sigma delta */
 #define AR5K_PHY_TIMING_11_SPUR_FREQ_SD_S	20
 #define AR5K_PHY_TIMING_11_USE_SPUR_IN_AGC	0x40000000	/* Spur filter in AGC detector */
 #define AR5K_PHY_TIMING_11_USE_SPUR_IN_SELFCOR	0x80000000	/* Spur filter in OFDM self correlator */
 /*
 * Gain tables
 */
 #define	AR5K_BB_GAIN_BASE		0x9b00	/* BaseBand Amplifier Gain table base address */
 #define AR5K_BB_GAIN(_n)		(AR5K_BB_GAIN_BASE + ((_n) << 2))
 #define	AR5K_RF_GAIN_BASE		0x9a00	/* RF Amplrifier Gain table base address */
 #define AR5K_RF_GAIN(_n)		(AR5K_RF_GAIN_BASE + ((_n) << 2))
 /*
 * PHY timing IQ calibration result register [5111+]
 */
 #define	AR5K_PHY_IQRES_CAL_PWR_I	0x9c10	/* I (Inphase) power value */
 #define	AR5K_PHY_IQRES_CAL_PWR_Q	0x9c14	/* Q (Quadrature) power value */
 #define	AR5K_PHY_IQRES_CAL_CORR		0x9c18	/* I/Q Correlation */
 /*
 * PHY current RSSI register [5111+]
 */
 #define	AR5K_PHY_CURRENT_RSSI	0x9c1c
 /*
 * PHY RF Bus grant register
 */
 #define	AR5K_PHY_RFBUS_GRANT	0x9c20
 #define	AR5K_PHY_RFBUS_GRANT_OK	0x00000001
 /*
 * PHY ADC test register
 */
 #define	AR5K_PHY_ADC_TEST	0x9c24
 #define	AR5K_PHY_ADC_TEST_I	0x00000001
 #define	AR5K_PHY_ADC_TEST_Q	0x00000200
 /*
 * PHY DAC test register
 */
 #define	AR5K_PHY_DAC_TEST	0x9c28
 #define	AR5K_PHY_DAC_TEST_I	0x00000001
 #define	AR5K_PHY_DAC_TEST_Q	0x00000200
 /*
 * PHY PTAT register (?)
 */
 #define	AR5K_PHY_PTAT		0x9c2c
 /*
 * PHY Illegal TX rate register [5112+]
 */
 #define	AR5K_PHY_BAD_TX_RATE	0x9c30
 /*
 * PHY SPUR Power register [5112+]
 */
 #define	AR5K_PHY_SPUR_PWR	0x9c34			/* Register Address */
 #define	AR5K_PHY_SPUR_PWR_I	0x00000001	/* SPUR Power estimate for I (field) */
 #define	AR5K_PHY_SPUR_PWR_Q	0x00000100	/* SPUR Power estimate for Q (field) */
 #define	AR5K_PHY_SPUR_PWR_FILT	0x00010000	/* Power with SPUR removed (field) */
 /*
 * PHY Channel status register [5112+] (?)
 */
 #define	AR5K_PHY_CHAN_STATUS		0x9c38
 #define	AR5K_PHY_CHAN_STATUS_BT_ACT	0x00000001
 #define	AR5K_PHY_CHAN_STATUS_RX_CLR_RAW	0x00000002
 #define	AR5K_PHY_CHAN_STATUS_RX_CLR_MAC	0x00000004
 #define	AR5K_PHY_CHAN_STATUS_RX_CLR_PAP	0x00000008
 /*
 * Heavy clip enable register
 */
 #define	AR5K_PHY_HEAVY_CLIP_ENABLE	0x99e0
 /*
 * PHY clock sleep registers [5112+]
 */
 #define AR5K_PHY_SCLOCK			0x99f0
 #define AR5K_PHY_SCLOCK_32MHZ		0x0000000c
 #define AR5K_PHY_SDELAY			0x99f4
 #define AR5K_PHY_SDELAY_32MHZ		0x000000ff
 #define AR5K_PHY_SPENDING		0x99f8
 /*
 * PHY PAPD I (power?) table (?)
 * (92! entries)
 */
 #define	AR5K_PHY_PAPD_I_BASE	0xa000
 #define	AR5K_PHY_PAPD_I(_n)	(AR5K_PHY_PAPD_I_BASE + ((_n) << 2))
 /*
 * PHY PCDAC TX power table
 */
 #define	AR5K_PHY_PCDAC_TXPOWER_BASE	0xa180
 #define	AR5K_PHY_PCDAC_TXPOWER(_n)	(AR5K_PHY_PCDAC_TXPOWER_BASE + ((_n) << 2))
 /*
 * PHY mode register [5111+]
 */
 #define	AR5K_PHY_MODE			0x0a200			/* Register Address */
 #define	AR5K_PHY_MODE_MOD		0x00000001	/* PHY Modulation bit */
 #define AR5K_PHY_MODE_MOD_OFDM		0
 #define AR5K_PHY_MODE_MOD_CCK		1
 #define AR5K_PHY_MODE_FREQ		0x00000002	/* Freq mode bit */
 #define	AR5K_PHY_MODE_FREQ_5GHZ		0
 #define	AR5K_PHY_MODE_FREQ_2GHZ		2
 #define AR5K_PHY_MODE_MOD_DYN		0x00000004	/* Enable Dynamic OFDM/CCK mode [5112+] */
 #define AR5K_PHY_MODE_RAD		0x00000008	/* [5212+] */
 #define AR5K_PHY_MODE_RAD_RF5111	0
 #define AR5K_PHY_MODE_RAD_RF5112	8
 #define AR5K_PHY_MODE_XR		0x00000010	/* Enable XR mode [5112+] */
 #define	AR5K_PHY_MODE_HALF_RATE		0x00000020	/* Enable Half rate (test) */
 #define	AR5K_PHY_MODE_QUARTER_RATE	0x00000040	/* Enable Quarter rat (test) */
 /*
 * PHY CCK transmit control register [5111+ (?)]
 */
 #define AR5K_PHY_CCKTXCTL		0xa204
 #define AR5K_PHY_CCKTXCTL_WORLD		0x00000000
 #define AR5K_PHY_CCKTXCTL_JAPAN		0x00000010
 #define	AR5K_PHY_CCKTXCTL_SCRAMBLER_DIS	0x00000001
 #define	AR5K_PHY_CCKTXCTK_DAC_SCALE	0x00000004
 /*
 * PHY CCK Cross-correlator Barker RSSI threshold register [5212+]
 */
 #define AR5K_PHY_CCK_CROSSCORR			0xa208
 #define AR5K_PHY_CCK_CROSSCORR_WEAK_SIG_THR	0x0000003f
 #define AR5K_PHY_CCK_CROSSCORR_WEAK_SIG_THR_S	0
 /* Same address is used for antenna diversity activation */
 #define	AR5K_PHY_FAST_ANT_DIV		0xa208
 #define	AR5K_PHY_FAST_ANT_DIV_EN	0x00002000
 /*
 * PHY 2GHz gain register [5111+]
 */
 #define	AR5K_PHY_GAIN_2GHZ			0xa20c
 #define	AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX		0x00fc0000
 #define	AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX_S	18
 #define	AR5K_PHY_GAIN_2GHZ_INI_5111		0x6480416c
 #define	AR5K_PHY_CCK_RX_CTL_4			0xa21c
 #define	AR5K_PHY_CCK_RX_CTL_4_FREQ_EST_SHORT	0x01f80000
 #define	AR5K_PHY_CCK_RX_CTL_4_FREQ_EST_SHORT_S	19
 #define	AR5K_PHY_DAG_CCK_CTL			0xa228
 #define	AR5K_PHY_DAG_CCK_CTL_EN_RSSI_THR	0x00000200
 #define	AR5K_PHY_DAG_CCK_CTL_RSSI_THR		0x0001fc00
 #define	AR5K_PHY_DAG_CCK_CTL_RSSI_THR_S		10
 #define	AR5K_PHY_FAST_ADC	0xa24c
 #define	AR5K_PHY_BLUETOOTH	0xa254
 /*
 * Transmit Power Control register
 * [2413+]
 */
 #define	AR5K_PHY_TPC_RG1		0xa258
 #define	AR5K_PHY_TPC_RG1_NUM_PD_GAIN	0x0000c000
 #define	AR5K_PHY_TPC_RG1_NUM_PD_GAIN_S	14
 #define AR5K_PHY_TPC_RG1_PDGAIN_1	0x00030000
 #define AR5K_PHY_TPC_RG1_PDGAIN_1_S	16
 #define AR5K_PHY_TPC_RG1_PDGAIN_2	0x000c0000
 #define AR5K_PHY_TPC_RG1_PDGAIN_2_S	18
 #define AR5K_PHY_TPC_RG1_PDGAIN_3	0x00300000
 #define AR5K_PHY_TPC_RG1_PDGAIN_3_S	20
 #define	AR5K_PHY_TPC_RG5			0xa26C
 #define	AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP	0x0000000F
 #define	AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP_S	0
 #define	AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1	0x000003F0
 #define	AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1_S	4
 #define	AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2	0x0000FC00
 #define	AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2_S	10
 #define	AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3	0x003F0000
 #define	AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3_S	16
 #define	AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4	0x0FC00000
 #define	AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4_S	22
 /*
 * PHY PDADC Tx power table
 */
 #define AR5K_PHY_PDADC_TXPOWER_BASE	0xa280
 #define	AR5K_PHY_PDADC_TXPOWER(_n)	(AR5K_PHY_PDADC_TXPOWER_BASE + ((_n) << 2))
 /*** -*- linux-c -*- **********************************************************
     Driver for Atmel at76c502 at76c504 and at76c506 wireless cards.
 	Copyright 2000-2001 ATMEL Corporation.
 	Copyright 2003-2004 Simon Kelley.
    This code was developed from version 2.1.1 of the Atmel drivers,
    released by Atmel corp. under the GPL in December 2002. It also
    includes code from the Linux aironet drivers (C) Benjamin Reed,
    and the Linux PCMCIA package, (C) David Hinds and the Linux wireless
    extensions, (C) Jean Tourrilhes.
    The firmware module for reading the MAC address of the card comes from
    net.russotto.AtmelMACFW, written by Matthew T. Russotto and copyright
    by him. net.russotto.AtmelMACFW is used under the GPL license version 2.
    This file contains the module in binary form and, under the terms
    of the GPL, in source form. The source is located at the end of the file.
    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 2 of the License, or
    (at your option) any later version.
    This software is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.
    You should have received a copy of the GNU General Public License
    along with Atmel wireless lan drivers; if not, write to the Free Software
    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
    For all queries about this code, please contact the current author,
    Simon Kelley <simon@thekelleys.org.uk> and not Atmel Corporation.
    Credit is due to HP UK and Cambridge Online Systems Ltd for supplying
    hardware used during development of this driver.
 ******************************************************************************/
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/ptrace.h>
 #include <linux/slab.h>
 #include <linux/string.h>
 #include <linux/ctype.h>
 #include <linux/timer.h>
 #include <asm/byteorder.h>
 #include <asm/io.h>
 #include <asm/system.h>
 #include <asm/uaccess.h>
 #include <linux/module.h>
 #include <linux/netdevice.h>
 #include <linux/etherdevice.h>
 #include <linux/skbuff.h>
 #include <linux/if_arp.h>
 #include <linux/ioport.h>
 #include <linux/fcntl.h>
 #include <linux/delay.h>
 #include <linux/wireless.h>
 #include <net/iw_handler.h>
 #include <linux/crc32.h>
 #include <linux/proc_fs.h>
 #include <linux/device.h>
 #include <linux/moduleparam.h>
 #include <linux/firmware.h>
 #include <linux/jiffies.h>
 #include <linux/ieee80211.h>
 #include "atmel.h"
 #define DRIVER_MAJOR 0
 #define DRIVER_MINOR 98
 MODULE_AUTHOR("Simon Kelley");
 MODULE_DESCRIPTION("Support for Atmel at76c50x 802.11 wireless ethernet cards.");
 MODULE_LICENSE("GPL");
 MODULE_SUPPORTED_DEVICE("Atmel at76c50x wireless cards");
 /* The name of the firmware file to be loaded
   over-rides any automatic selection */
 static char *firmware = NULL;
 module_param(firmware, charp, 0);
 /* table of firmware file names */
 static struct {
 	AtmelFWType fw_type;
 	const char *fw_file;
 	const char *fw_file_ext;
 } fw_table[] = {
 	{ ATMEL_FW_TYPE_502,		"atmel_at76c502",	"bin" },
 	{ ATMEL_FW_TYPE_502D,		"atmel_at76c502d",	"bin" },
 	{ ATMEL_FW_TYPE_502E,		"atmel_at76c502e",	"bin" },
 	{ ATMEL_FW_TYPE_502_3COM,	"atmel_at76c502_3com",	"bin" },
 	{ ATMEL_FW_TYPE_504,		"atmel_at76c504",	"bin" },
 	{ ATMEL_FW_TYPE_504_2958,	"atmel_at76c504_2958",	"bin" },
 	{ ATMEL_FW_TYPE_504A_2958,	"atmel_at76c504a_2958",	"bin" },
 	{ ATMEL_FW_TYPE_506,		"atmel_at76c506",	"bin" },
 	{ ATMEL_FW_TYPE_NONE,		NULL,			NULL }
 };
 #define MAX_SSID_LENGTH 32
 #define MGMT_JIFFIES (256 * HZ / 100)
 #define MAX_BSS_ENTRIES	64
 /* registers */
 #define GCR  0x00    /* (SIR0)  General Configuration Register */
 #define BSR  0x02    /* (SIR1)  Bank Switching Select Register */
 #define AR   0x04
 #define DR   0x08
 #define MR1  0x12    /* Mirror Register 1 */
 #define MR2  0x14    /* Mirror Register 2 */
 #define MR3  0x16    /* Mirror Register 3 */
 #define MR4  0x18    /* Mirror Register 4 */
 #define GPR1                            0x0c
 #define GPR2                            0x0e
 #define GPR3                            0x10
 /*
 * Constants for the GCR register.
 */
 #define GCR_REMAP     0x0400          /* Remap internal SRAM to 0 */
 #define GCR_SWRES     0x0080          /* BIU reset (ARM and PAI are NOT reset) */
 #define GCR_CORES     0x0060          /* Core Reset (ARM and PAI are reset) */
 #define GCR_ENINT     0x0002          /* Enable Interrupts */
 #define GCR_ACKINT    0x0008          /* Acknowledge Interrupts */
 #define BSS_SRAM      0x0200          /* AMBA module selection --> SRAM */
 #define BSS_IRAM      0x0100          /* AMBA module selection --> IRAM */
 /*
 *Constants for the MR registers.
 */
 #define MAC_INIT_COMPLETE       0x0001        /* MAC init has been completed */
 #define MAC_BOOT_COMPLETE       0x0010        /* MAC boot has been completed */
 #define MAC_INIT_OK             0x0002        /* MAC boot has been completed */
 #define MIB_MAX_DATA_BYTES    212
 #define MIB_HEADER_SIZE       4    /* first four fields */
 struct get_set_mib {
 	u8 type;
 	u8 size;
 	u8 index;
 	u8 reserved;
 	u8 data[MIB_MAX_DATA_BYTES];
 };
 struct rx_desc {
 	u32          Next;
 	u16          MsduPos;
 	u16          MsduSize;
 	u8           State;
 	u8           Status;
 	u8           Rate;
 	u8           Rssi;
 	u8           LinkQuality;
 	u8           PreambleType;
 	u16          Duration;
 	u32          RxTime;
 };
 #define RX_DESC_FLAG_VALID       0x80
 #define RX_DESC_FLAG_CONSUMED    0x40
 #define RX_DESC_FLAG_IDLE        0x00
 #define RX_STATUS_SUCCESS        0x00
 #define RX_DESC_MSDU_POS_OFFSET      4
 #define RX_DESC_MSDU_SIZE_OFFSET     6
 #define RX_DESC_FLAGS_OFFSET         8
 #define RX_DESC_STATUS_OFFSET        9
 #define RX_DESC_RSSI_OFFSET          11
 #define RX_DESC_LINK_QUALITY_OFFSET  12
 #define RX_DESC_PREAMBLE_TYPE_OFFSET 13
 #define RX_DESC_DURATION_OFFSET      14
 #define RX_DESC_RX_TIME_OFFSET       16
 struct tx_desc {
 	u32       NextDescriptor;
 	u16       TxStartOfFrame;
 	u16       TxLength;
 	u8        TxState;
 	u8        TxStatus;
 	u8        RetryCount;
 	u8        TxRate;
 	u8        KeyIndex;
 	u8        ChiperType;
 	u8        ChipreLength;
 	u8        Reserved1;
 	u8        Reserved;
 	u8        PacketType;
 	u16       HostTxLength;
 };
 #define TX_DESC_NEXT_OFFSET          0
 #define TX_DESC_POS_OFFSET           4
 #define TX_DESC_SIZE_OFFSET          6
 #define TX_DESC_FLAGS_OFFSET         8
 #define TX_DESC_STATUS_OFFSET        9
 #define TX_DESC_RETRY_OFFSET         10
 #define TX_DESC_RATE_OFFSET          11
 #define TX_DESC_KEY_INDEX_OFFSET     12
 #define TX_DESC_CIPHER_TYPE_OFFSET   13
 #define TX_DESC_CIPHER_LENGTH_OFFSET 14
 #define TX_DESC_PACKET_TYPE_OFFSET   17
 #define TX_DESC_HOST_LENGTH_OFFSET   18
 /*
 * Host-MAC interface
 */
 #define TX_STATUS_SUCCESS       0x00
 #define TX_FIRM_OWN             0x80
 #define TX_DONE                 0x40
 #define TX_ERROR                0x01
 #define TX_PACKET_TYPE_DATA     0x01
 #define TX_PACKET_TYPE_MGMT     0x02
 #define ISR_EMPTY               0x00        /* no bits set in ISR */
 #define ISR_TxCOMPLETE          0x01        /* packet transmitted */
 #define ISR_RxCOMPLETE          0x02        /* packet received */
 #define ISR_RxFRAMELOST         0x04        /* Rx Frame lost */
 #define ISR_FATAL_ERROR         0x08        /* Fatal error */
 #define ISR_COMMAND_COMPLETE    0x10        /* command completed */
 #define ISR_OUT_OF_RANGE        0x20        /* command completed */
 #define ISR_IBSS_MERGE          0x40        /* (4.1.2.30): IBSS merge */
 #define ISR_GENERIC_IRQ         0x80
 #define Local_Mib_Type          0x01
 #define Mac_Address_Mib_Type    0x02
 #define Mac_Mib_Type            0x03
 #define Statistics_Mib_Type     0x04
 #define Mac_Mgmt_Mib_Type       0x05
 #define Mac_Wep_Mib_Type        0x06
 #define Phy_Mib_Type            0x07
 #define Multi_Domain_MIB        0x08
 #define MAC_MGMT_MIB_CUR_BSSID_POS            14
 #define MAC_MIB_FRAG_THRESHOLD_POS            8
 #define MAC_MIB_RTS_THRESHOLD_POS             10
 #define MAC_MIB_SHORT_RETRY_POS               16
 #define MAC_MIB_LONG_RETRY_POS                17
 #define MAC_MIB_SHORT_RETRY_LIMIT_POS         16
 #define MAC_MGMT_MIB_BEACON_PER_POS           0
 #define MAC_MGMT_MIB_STATION_ID_POS           6
 #define MAC_MGMT_MIB_CUR_PRIVACY_POS          11
 #define MAC_MGMT_MIB_CUR_BSSID_POS            14
 #define MAC_MGMT_MIB_PS_MODE_POS              53
 #define MAC_MGMT_MIB_LISTEN_INTERVAL_POS      54
 #define MAC_MGMT_MIB_MULTI_DOMAIN_IMPLEMENTED 56
 #define MAC_MGMT_MIB_MULTI_DOMAIN_ENABLED     57
 #define PHY_MIB_CHANNEL_POS                   14
 #define PHY_MIB_RATE_SET_POS                  20
 #define PHY_MIB_REG_DOMAIN_POS                26
 #define LOCAL_MIB_AUTO_TX_RATE_POS            3
 #define LOCAL_MIB_SSID_SIZE                   5
 #define LOCAL_MIB_TX_PROMISCUOUS_POS          6
 #define LOCAL_MIB_TX_MGMT_RATE_POS            7
 #define LOCAL_MIB_TX_CONTROL_RATE_POS         8
 #define LOCAL_MIB_PREAMBLE_TYPE               9
 #define MAC_ADDR_MIB_MAC_ADDR_POS             0
 #define         CMD_Set_MIB_Vars              0x01
 #define         CMD_Get_MIB_Vars              0x02
 #define         CMD_Scan                      0x03
 #define         CMD_Join                      0x04
 #define         CMD_Start                     0x05
 #define         CMD_EnableRadio               0x06
 #define         CMD_DisableRadio              0x07
 #define         CMD_SiteSurvey                0x0B
 #define         CMD_STATUS_IDLE                   0x00
 #define         CMD_STATUS_COMPLETE               0x01
 #define         CMD_STATUS_UNKNOWN                0x02
 #define         CMD_STATUS_INVALID_PARAMETER      0x03
 #define         CMD_STATUS_FUNCTION_NOT_SUPPORTED 0x04
 #define         CMD_STATUS_TIME_OUT               0x07
 #define         CMD_STATUS_IN_PROGRESS            0x08
 #define         CMD_STATUS_REJECTED_RADIO_OFF     0x09
 #define         CMD_STATUS_HOST_ERROR             0xFF
 #define         CMD_STATUS_BUSY                   0xFE
 #define CMD_BLOCK_COMMAND_OFFSET        0
 #define CMD_BLOCK_STATUS_OFFSET         1
 #define CMD_BLOCK_PARAMETERS_OFFSET     4
 #define SCAN_OPTIONS_SITE_SURVEY        0x80
 #define MGMT_FRAME_BODY_OFFSET		24
 #define MAX_AUTHENTICATION_RETRIES	3
 #define MAX_ASSOCIATION_RETRIES		3
 #define AUTHENTICATION_RESPONSE_TIME_OUT  1000
 #define MAX_WIRELESS_BODY  2316 /* mtu is 2312, CRC is 4 */
 #define LOOP_RETRY_LIMIT   500000
 #define ACTIVE_MODE	1
 #define PS_MODE		2
 #define MAX_ENCRYPTION_KEYS 4
 #define MAX_ENCRYPTION_KEY_SIZE 40
 /*
 * 802.11 related definitions
 */
 /*
 * Regulatory Domains
 */
 #define REG_DOMAIN_FCC		0x10	/* Channels	1-11	USA				*/
 #define REG_DOMAIN_DOC		0x20	/* Channel	1-11	Canada				*/
 #define REG_DOMAIN_ETSI		0x30	/* Channel	1-13	Europe (ex Spain/France)	*/
 #define REG_DOMAIN_SPAIN	0x31	/* Channel	10-11	Spain				*/
 #define REG_DOMAIN_FRANCE	0x32	/* Channel	10-13	France				*/
 #define REG_DOMAIN_MKK		0x40	/* Channel	14	Japan				*/
 #define REG_DOMAIN_MKK1		0x41	/* Channel	1-14	Japan(MKK1)			*/
 #define REG_DOMAIN_ISRAEL	0x50	/* Channel	3-9	ISRAEL				*/
 #define BSS_TYPE_AD_HOC		1
 #define BSS_TYPE_INFRASTRUCTURE 2
 #define SCAN_TYPE_ACTIVE	0
 #define SCAN_TYPE_PASSIVE	1
 #define LONG_PREAMBLE		0
 #define SHORT_PREAMBLE		1
 #define AUTO_PREAMBLE		2
 #define DATA_FRAME_WS_HEADER_SIZE   30
 /* promiscuous mode control */
 #define PROM_MODE_OFF			0x0
 #define PROM_MODE_UNKNOWN		0x1
 #define PROM_MODE_CRC_FAILED		0x2
 #define PROM_MODE_DUPLICATED		0x4
 #define PROM_MODE_MGMT			0x8
 #define PROM_MODE_CTRL			0x10
 #define PROM_MODE_BAD_PROTOCOL		0x20
 #define IFACE_INT_STATUS_OFFSET		0
 #define IFACE_INT_MASK_OFFSET		1
 #define IFACE_LOCKOUT_HOST_OFFSET	2
 #define IFACE_LOCKOUT_MAC_OFFSET	3
 #define IFACE_FUNC_CTRL_OFFSET		28
 #define IFACE_MAC_STAT_OFFSET		30
 #define IFACE_GENERIC_INT_TYPE_OFFSET	32
 #define CIPHER_SUITE_NONE     0
 #define CIPHER_SUITE_WEP_64   1
 #define CIPHER_SUITE_TKIP     2
 #define CIPHER_SUITE_AES      3
 #define CIPHER_SUITE_CCX      4
 #define CIPHER_SUITE_WEP_128  5
 /*
 * IFACE MACROS & definitions
 */
 /*
 * FuncCtrl field:
 */
 #define FUNC_CTRL_TxENABLE		0x10
 #define FUNC_CTRL_RxENABLE		0x20
 #define FUNC_CTRL_INIT_COMPLETE		0x01
 /* A stub firmware image which reads the MAC address from NVRAM on the card.
   For copyright information and source see the end of this file. */
 static u8 mac_reader[] = {
 	0x06, 0x00, 0x00, 0xea, 0x04, 0x00, 0x00, 0xea, 0x03, 0x00, 0x00, 0xea, 0x02, 0x00, 0x00, 0xea,
 	0x01, 0x00, 0x00, 0xea, 0x00, 0x00, 0x00, 0xea, 0xff, 0xff, 0xff, 0xea, 0xfe, 0xff, 0xff, 0xea,
 	0xd3, 0x00, 0xa0, 0xe3, 0x00, 0xf0, 0x21, 0xe1, 0x0e, 0x04, 0xa0, 0xe3, 0x00, 0x10, 0xa0, 0xe3,
 	0x81, 0x11, 0xa0, 0xe1, 0x00, 0x10, 0x81, 0xe3, 0x00, 0x10, 0x80, 0xe5, 0x1c, 0x10, 0x90, 0xe5,
 	0x10, 0x10, 0xc1, 0xe3, 0x1c, 0x10, 0x80, 0xe5, 0x01, 0x10, 0xa0, 0xe3, 0x08, 0x10, 0x80, 0xe5,
 	0x02, 0x03, 0xa0, 0xe3, 0x00, 0x10, 0xa0, 0xe3, 0xb0, 0x10, 0xc0, 0xe1, 0xb4, 0x10, 0xc0, 0xe1,
 	0xb8, 0x10, 0xc0, 0xe1, 0xbc, 0x10, 0xc0, 0xe1, 0x56, 0xdc, 0xa0, 0xe3, 0x21, 0x00, 0x00, 0xeb,
 	0x0a, 0x00, 0xa0, 0xe3, 0x1a, 0x00, 0x00, 0xeb, 0x10, 0x00, 0x00, 0xeb, 0x07, 0x00, 0x00, 0xeb,
 	0x02, 0x03, 0xa0, 0xe3, 0x02, 0x14, 0xa0, 0xe3, 0xb4, 0x10, 0xc0, 0xe1, 0x4c, 0x10, 0x9f, 0xe5,
 	0xbc, 0x10, 0xc0, 0xe1, 0x10, 0x10, 0xa0, 0xe3, 0xb8, 0x10, 0xc0, 0xe1, 0xfe, 0xff, 0xff, 0xea,
 	0x00, 0x40, 0x2d, 0xe9, 0x00, 0x20, 0xa0, 0xe3, 0x02, 0x3c, 0xa0, 0xe3, 0x00, 0x10, 0xa0, 0xe3,
 	0x28, 0x00, 0x9f, 0xe5, 0x37, 0x00, 0x00, 0xeb, 0x00, 0x40, 0xbd, 0xe8, 0x1e, 0xff, 0x2f, 0xe1,
 	0x00, 0x40, 0x2d, 0xe9, 0x12, 0x2e, 0xa0, 0xe3, 0x06, 0x30, 0xa0, 0xe3, 0x00, 0x10, 0xa0, 0xe3,
 	0x02, 0x04, 0xa0, 0xe3, 0x2f, 0x00, 0x00, 0xeb, 0x00, 0x40, 0xbd, 0xe8, 0x1e, 0xff, 0x2f, 0xe1,
 	0x00, 0x02, 0x00, 0x02, 0x80, 0x01, 0x90, 0xe0, 0x01, 0x00, 0x00, 0x0a, 0x01, 0x00, 0x50, 0xe2,
 	0xfc, 0xff, 0xff, 0xea, 0x1e, 0xff, 0x2f, 0xe1, 0x80, 0x10, 0xa0, 0xe3, 0xf3, 0x06, 0xa0, 0xe3,
 	0x00, 0x10, 0x80, 0xe5, 0x00, 0x10, 0xa0, 0xe3, 0x00, 0x10, 0x80, 0xe5, 0x01, 0x10, 0xa0, 0xe3,
 	0x04, 0x10, 0x80, 0xe5, 0x00, 0x10, 0x80, 0xe5, 0x0e, 0x34, 0xa0, 0xe3, 0x1c, 0x10, 0x93, 0xe5,
 	0x02, 0x1a, 0x81, 0xe3, 0x1c, 0x10, 0x83, 0xe5, 0x58, 0x11, 0x9f, 0xe5, 0x30, 0x10, 0x80, 0xe5,
 	0x54, 0x11, 0x9f, 0xe5, 0x34, 0x10, 0x80, 0xe5, 0x38, 0x10, 0x80, 0xe5, 0x3c, 0x10, 0x80, 0xe5,
 	0x10, 0x10, 0x90, 0xe5, 0x08, 0x00, 0x90, 0xe5, 0x1e, 0xff, 0x2f, 0xe1, 0xf3, 0x16, 0xa0, 0xe3,
 	0x08, 0x00, 0x91, 0xe5, 0x05, 0x00, 0xa0, 0xe3, 0x0c, 0x00, 0x81, 0xe5, 0x10, 0x00, 0x91, 0xe5,
 	0x02, 0x00, 0x10, 0xe3, 0xfc, 0xff, 0xff, 0x0a, 0xff, 0x00, 0xa0, 0xe3, 0x0c, 0x00, 0x81, 0xe5,
 	0x10, 0x00, 0x91, 0xe5, 0x02, 0x00, 0x10, 0xe3, 0xfc, 0xff, 0xff, 0x0a, 0x08, 0x00, 0x91, 0xe5,
 	0x10, 0x00, 0x91, 0xe5, 0x01, 0x00, 0x10, 0xe3, 0xfc, 0xff, 0xff, 0x0a, 0x08, 0x00, 0x91, 0xe5,
 	0xff, 0x00, 0x00, 0xe2, 0x1e, 0xff, 0x2f, 0xe1, 0x30, 0x40, 0x2d, 0xe9, 0x00, 0x50, 0xa0, 0xe1,
 	0x03, 0x40, 0xa0, 0xe1, 0xa2, 0x02, 0xa0, 0xe1, 0x08, 0x00, 0x00, 0xe2, 0x03, 0x00, 0x80, 0xe2,
 	0xd8, 0x10, 0x9f, 0xe5, 0x00, 0x00, 0xc1, 0xe5, 0x01, 0x20, 0xc1, 0xe5, 0xe2, 0xff, 0xff, 0xeb,
 	0x01, 0x00, 0x10, 0xe3, 0xfc, 0xff, 0xff, 0x1a, 0x14, 0x00, 0xa0, 0xe3, 0xc4, 0xff, 0xff, 0xeb,
 	0x04, 0x20, 0xa0, 0xe1, 0x05, 0x10, 0xa0, 0xe1, 0x02, 0x00, 0xa0, 0xe3, 0x01, 0x00, 0x00, 0xeb,
 	0x30, 0x40, 0xbd, 0xe8, 0x1e, 0xff, 0x2f, 0xe1, 0x70, 0x40, 0x2d, 0xe9, 0xf3, 0x46, 0xa0, 0xe3,
 	0x00, 0x30, 0xa0, 0xe3, 0x00, 0x00, 0x50, 0xe3, 0x08, 0x00, 0x00, 0x9a, 0x8c, 0x50, 0x9f, 0xe5,
 	0x03, 0x60, 0xd5, 0xe7, 0x0c, 0x60, 0x84, 0xe5, 0x10, 0x60, 0x94, 0xe5, 0x02, 0x00, 0x16, 0xe3,
 	0xfc, 0xff, 0xff, 0x0a, 0x01, 0x30, 0x83, 0xe2, 0x00, 0x00, 0x53, 0xe1, 0xf7, 0xff, 0xff, 0x3a,
 	0xff, 0x30, 0xa0, 0xe3, 0x0c, 0x30, 0x84, 0xe5, 0x08, 0x00, 0x94, 0xe5, 0x10, 0x00, 0x94, 0xe5,
 	0x01, 0x00, 0x10, 0xe3, 0xfc, 0xff, 0xff, 0x0a, 0x08, 0x00, 0x94, 0xe5, 0x00, 0x00, 0xa0, 0xe3,
 	0x00, 0x00, 0x52, 0xe3, 0x0b, 0x00, 0x00, 0x9a, 0x10, 0x50, 0x94, 0xe5, 0x02, 0x00, 0x15, 0xe3,
 	0xfc, 0xff, 0xff, 0x0a, 0x0c, 0x30, 0x84, 0xe5, 0x10, 0x50, 0x94, 0xe5, 0x01, 0x00, 0x15, 0xe3,
 	0xfc, 0xff, 0xff, 0x0a, 0x08, 0x50, 0x94, 0xe5, 0x01, 0x50, 0xc1, 0xe4, 0x01, 0x00, 0x80, 0xe2,
 	0x02, 0x00, 0x50, 0xe1, 0xf3, 0xff, 0xff, 0x3a, 0xc8, 0x00, 0xa0, 0xe3, 0x98, 0xff, 0xff, 0xeb,
 	0x70, 0x40, 0xbd, 0xe8, 0x1e, 0xff, 0x2f, 0xe1, 0x01, 0x0c, 0x00, 0x02, 0x01, 0x02, 0x00, 0x02,
 	0x00, 0x01, 0x00, 0x02
 };
 struct atmel_private {
 	void *card; /* Bus dependent stucture varies for PCcard */
 	int (*present_callback)(void *); /* And callback which uses it */
 	char firmware_id[32];
 	AtmelFWType firmware_type;
 	u8 *firmware;
 	int firmware_length;
 	struct timer_list management_timer;
 	struct net_device *dev;
 	struct device *sys_dev;
 	struct iw_statistics wstats;
 	spinlock_t irqlock, timerlock;	/* spinlocks */
 	enum { BUS_TYPE_PCCARD, BUS_TYPE_PCI } bus_type;
 	enum {
 		CARD_TYPE_PARALLEL_FLASH,
 		CARD_TYPE_SPI_FLASH,
 		CARD_TYPE_EEPROM
 	} card_type;
 	int do_rx_crc; /* If we need to CRC incoming packets */
 	int probe_crc; /* set if we don't yet know */
 	int crc_ok_cnt, crc_ko_cnt; /* counters for probing */
 	u16 rx_desc_head;
 	u16 tx_desc_free, tx_desc_head, tx_desc_tail, tx_desc_previous;
 	u16 tx_free_mem, tx_buff_head, tx_buff_tail;
 	u16 frag_seq, frag_len, frag_no;
 	u8 frag_source[6];
 	u8 wep_is_on, default_key, exclude_unencrypted, encryption_level;
 	u8 group_cipher_suite, pairwise_cipher_suite;
 	u8 wep_keys[MAX_ENCRYPTION_KEYS][MAX_ENCRYPTION_KEY_SIZE];
 	int wep_key_len[MAX_ENCRYPTION_KEYS];
 	int use_wpa, radio_on_broken; /* firmware dependent stuff. */
 	u16 host_info_base;
 	struct host_info_struct {
 		/* NB this is matched to the hardware, don't change. */
 		u8 volatile int_status;
 		u8 volatile int_mask;
 		u8 volatile lockout_host;
 		u8 volatile lockout_mac;
 		u16 tx_buff_pos;
 		u16 tx_buff_size;
 		u16 tx_desc_pos;
 		u16 tx_desc_count;
 		u16 rx_buff_pos;
 		u16 rx_buff_size;
 		u16 rx_desc_pos;
 		u16 rx_desc_count;
 		u16 build_version;
 		u16 command_pos;
 		u16 major_version;
 		u16 minor_version;
 		u16 func_ctrl;
 		u16 mac_status;
 		u16 generic_IRQ_type;
 		u8  reserved[2];
 	} host_info;
 	enum {
 		STATION_STATE_SCANNING,
 		STATION_STATE_JOINNING,
 		STATION_STATE_AUTHENTICATING,
 		STATION_STATE_ASSOCIATING,
 		STATION_STATE_READY,
 		STATION_STATE_REASSOCIATING,
 		STATION_STATE_DOWN,
 		STATION_STATE_MGMT_ERROR
 	} station_state;
 	int operating_mode, power_mode;
 	time_t last_qual;
 	int beacons_this_sec;
 	int channel;
 	int reg_domain, config_reg_domain;
 	int tx_rate;
 	int auto_tx_rate;
 	int rts_threshold;
 	int frag_threshold;
 	int long_retry, short_retry;
 	int preamble;
 	int default_beacon_period, beacon_period, listen_interval;
 	int CurrentAuthentTransactionSeqNum, ExpectedAuthentTransactionSeqNum;
 	int AuthenticationRequestRetryCnt, AssociationRequestRetryCnt, ReAssociationRequestRetryCnt;
 	enum {
 		SITE_SURVEY_IDLE,
 		SITE_SURVEY_IN_PROGRESS,
 		SITE_SURVEY_COMPLETED
 	} site_survey_state;
 	unsigned long last_survey;
 	int station_was_associated, station_is_associated;
 	int fast_scan;
 	struct bss_info {
 		int channel;
 		int SSIDsize;
 		int RSSI;
 		int UsingWEP;
 		int preamble;
 		int beacon_period;
 		int BSStype;
 		u8 BSSID[6];
 		u8 SSID[MAX_SSID_LENGTH];
 	} BSSinfo[MAX_BSS_ENTRIES];
 	int BSS_list_entries, current_BSS;
 	int connect_to_any_BSS;
 	int SSID_size, new_SSID_size;
 	u8 CurrentBSSID[6], BSSID[6];
 	u8 SSID[MAX_SSID_LENGTH], new_SSID[MAX_SSID_LENGTH];
 	u64 last_beacon_timestamp;
 	u8 rx_buf[MAX_WIRELESS_BODY];
 };
 static u8 atmel_basic_rates[4] = {0x82, 0x84, 0x0b, 0x16};
 static const struct {
 	int reg_domain;
 	int min, max;
 	char *name;
 } channel_table[] = { { REG_DOMAIN_FCC, 1, 11, "USA" },
 		      { REG_DOMAIN_DOC, 1, 11, "Canada" },
 		      { REG_DOMAIN_ETSI, 1, 13, "Europe" },
 		      { REG_DOMAIN_SPAIN, 10, 11, "Spain" },
 		      { REG_DOMAIN_FRANCE, 10, 13, "France" },
 		      { REG_DOMAIN_MKK, 14, 14, "MKK" },
 		      { REG_DOMAIN_MKK1, 1, 14, "MKK1" },
 		      { REG_DOMAIN_ISRAEL, 3, 9, "Israel"} };
 static void build_wpa_mib(struct atmel_private *priv);
 static int atmel_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
 static void atmel_copy_to_card(struct net_device *dev, u16 dest,
 			       const unsigned char *src, u16 len);
 static void atmel_copy_to_host(struct net_device *dev, unsigned char *dest,
 			       u16 src, u16 len);
 static void atmel_set_gcr(struct net_device *dev, u16 mask);
 static void atmel_clear_gcr(struct net_device *dev, u16 mask);
 static int atmel_lock_mac(struct atmel_private *priv);
 static void atmel_wmem32(struct atmel_private *priv, u16 pos, u32 data);
 static void atmel_command_irq(struct atmel_private *priv);
 static int atmel_validate_channel(struct atmel_private *priv, int channel);
 static void atmel_management_frame(struct atmel_private *priv,
 				   struct ieee80211_hdr *header,
 				   u16 frame_len, u8 rssi);
 static void atmel_management_timer(u_long a);
 static void atmel_send_command(struct atmel_private *priv, int command,
 			       void *cmd, int cmd_size);
 static int atmel_send_command_wait(struct atmel_private *priv, int command,
 				   void *cmd, int cmd_size);
 static void atmel_transmit_management_frame(struct atmel_private *priv,
 					    struct ieee80211_hdr *header,
 					    u8 *body, int body_len);
 static u8 atmel_get_mib8(struct atmel_private *priv, u8 type, u8 index);
 static void atmel_set_mib8(struct atmel_private *priv, u8 type, u8 index,
 			   u8 data);
 static void atmel_set_mib16(struct atmel_private *priv, u8 type, u8 index,
 			    u16 data);
 static void atmel_set_mib(struct atmel_private *priv, u8 type, u8 index,
 			  u8 *data, int data_len);
 static void atmel_get_mib(struct atmel_private *priv, u8 type, u8 index,
 			  u8 *data, int data_len);
 static void atmel_scan(struct atmel_private *priv, int specific_ssid);
 static void atmel_join_bss(struct atmel_private *priv, int bss_index);
 static void atmel_smooth_qual(struct atmel_private *priv);
 static void atmel_writeAR(struct net_device *dev, u16 data);
 static int probe_atmel_card(struct net_device *dev);
 static int reset_atmel_card(struct net_device *dev);
 static void atmel_enter_state(struct atmel_private *priv, int new_state);
 int atmel_open (struct net_device *dev);
 static inline u16 atmel_hi(struct atmel_private *priv, u16 offset)
 {
 	return priv->host_info_base + offset;
 }
 static inline u16 atmel_co(struct atmel_private *priv, u16 offset)
 {
 	return priv->host_info.command_pos + offset;
 }
 static inline u16 atmel_rx(struct atmel_private *priv, u16 offset, u16 desc)
 {
 	return priv->host_info.rx_desc_pos + (sizeof(struct rx_desc) * desc) + offset;
 }
 static inline u16 atmel_tx(struct atmel_private *priv, u16 offset, u16 desc)
 {
 	return priv->host_info.tx_desc_pos + (sizeof(struct tx_desc) * desc) + offset;
 }
 static inline u8 atmel_read8(struct net_device *dev, u16 offset)
 {
 	return inb(dev->base_addr + offset);
 }
 static inline void atmel_write8(struct net_device *dev, u16 offset, u8 data)
 {
 	outb(data, dev->base_addr + offset);
 }
 static inline u16 atmel_read16(struct net_device *dev, u16 offset)
 {
 	return inw(dev->base_addr + offset);
 }
 static inline void atmel_write16(struct net_device *dev, u16 offset, u16 data)
 {
 	outw(data, dev->base_addr + offset);
 }
 static inline u8 atmel_rmem8(struct atmel_private *priv, u16 pos)
 {
 	atmel_writeAR(priv->dev, pos);
 	return atmel_read8(priv->dev, DR);
 }
 static inline void atmel_wmem8(struct atmel_private *priv, u16 pos, u16 data)
 {
 	atmel_writeAR(priv->dev, pos);
 	atmel_write8(priv->dev, DR, data);
 }
 static inline u16 atmel_rmem16(struct atmel_private *priv, u16 pos)
 {
 	atmel_writeAR(priv->dev, pos);
 	return atmel_read16(priv->dev, DR);
 }
 static inline void atmel_wmem16(struct atmel_private *priv, u16 pos, u16 data)
 {
 	atmel_writeAR(priv->dev, pos);
 	atmel_write16(priv->dev, DR, data);
 }
 static const struct iw_handler_def atmel_handler_def;
 static void tx_done_irq(struct atmel_private *priv)
 {
 	int i;
 	for (i = 0;
 	     atmel_rmem8(priv, atmel_tx(priv, TX_DESC_FLAGS_OFFSET, priv->tx_desc_head)) == TX_DONE &&
 		     i < priv->host_info.tx_desc_count;
 	     i++) {
 		u8 status = atmel_rmem8(priv, atmel_tx(priv, TX_DESC_STATUS_OFFSET, priv->tx_desc_head));
 		u16 msdu_size = atmel_rmem16(priv, atmel_tx(priv, TX_DESC_SIZE_OFFSET, priv->tx_desc_head));
 		u8 type = atmel_rmem8(priv, atmel_tx(priv, TX_DESC_PACKET_TYPE_OFFSET, priv->tx_desc_head));
 		atmel_wmem8(priv, atmel_tx(priv, TX_DESC_FLAGS_OFFSET, priv->tx_desc_head), 0);
 		priv->tx_free_mem += msdu_size;
 		priv->tx_desc_free++;
 		if (priv->tx_buff_head + msdu_size > (priv->host_info.tx_buff_pos + priv->host_info.tx_buff_size))
 			priv->tx_buff_head = 0;
 		else
 			priv->tx_buff_head += msdu_size;
 		if (priv->tx_desc_head < (priv->host_info.tx_desc_count - 1))
 			priv->tx_desc_head++ ;
 		else
 			priv->tx_desc_head = 0;
 		if (type == TX_PACKET_TYPE_DATA) {
 			if (status == TX_STATUS_SUCCESS)
 				priv->dev->stats.tx_packets++;
 			else
 				priv->dev->stats.tx_errors++;
 			netif_wake_queue(priv->dev);
 		}
 	}
 }
 static u16 find_tx_buff(struct atmel_private *priv, u16 len)
 {
 	u16 bottom_free = priv->host_info.tx_buff_size - priv->tx_buff_tail;
 	if (priv->tx_desc_free == 3 || priv->tx_free_mem < len)
 		return 0;
 	if (bottom_free >= len)
 		return priv->host_info.tx_buff_pos + priv->tx_buff_tail;
 	if (priv->tx_free_mem - bottom_free >= len) {
 		priv->tx_buff_tail = 0;
 		return priv->host_info.tx_buff_pos;
 	}
 	return 0;
 }
 static void tx_update_descriptor(struct atmel_private *priv, int is_bcast,
 				 u16 len, u16 buff, u8 type)
 {
 	atmel_wmem16(priv, atmel_tx(priv, TX_DESC_POS_OFFSET, priv->tx_desc_tail), buff);
 	atmel_wmem16(priv, atmel_tx(priv, TX_DESC_SIZE_OFFSET, priv->tx_desc_tail), len);
 	if (!priv->use_wpa)
 		atmel_wmem16(priv, atmel_tx(priv, TX_DESC_HOST_LENGTH_OFFSET, priv->tx_desc_tail), len);
 	atmel_wmem8(priv, atmel_tx(priv, TX_DESC_PACKET_TYPE_OFFSET, priv->tx_desc_tail), type);
 	atmel_wmem8(priv, atmel_tx(priv, TX_DESC_RATE_OFFSET, priv->tx_desc_tail), priv->tx_rate);
 	atmel_wmem8(priv, atmel_tx(priv, TX_DESC_RETRY_OFFSET, priv->tx_desc_tail), 0);
 	if (priv->use_wpa) {
 		int cipher_type, cipher_length;
 		if (is_bcast) {
 			cipher_type = priv->group_cipher_suite;
 			if (cipher_type == CIPHER_SUITE_WEP_64 ||
 			    cipher_type == CIPHER_SUITE_WEP_128)
 				cipher_length = 8;
 			else if (cipher_type == CIPHER_SUITE_TKIP)
 				cipher_length = 12;
 			else if (priv->pairwise_cipher_suite == CIPHER_SUITE_WEP_64 ||
 				 priv->pairwise_cipher_suite == CIPHER_SUITE_WEP_128) {
 				cipher_type = priv->pairwise_cipher_suite;
 				cipher_length = 8;
 			} else {
 				cipher_type = CIPHER_SUITE_NONE;
 				cipher_length = 0;
 			}
 		} else {
 			cipher_type = priv->pairwise_cipher_suite;
 			if (cipher_type == CIPHER_SUITE_WEP_64 ||
 			    cipher_type == CIPHER_SUITE_WEP_128)
 				cipher_length = 8;
 			else if (cipher_type == CIPHER_SUITE_TKIP)
 				cipher_length = 12;
 			else if (priv->group_cipher_suite == CIPHER_SUITE_WEP_64 ||
 				 priv->group_cipher_suite == CIPHER_SUITE_WEP_128) {
 				cipher_type = priv->group_cipher_suite;
 				cipher_length = 8;
 			} else {
 				cipher_type = CIPHER_SUITE_NONE;
 				cipher_length = 0;
 			}
 		}
 		atmel_wmem8(priv, atmel_tx(priv, TX_DESC_CIPHER_TYPE_OFFSET, priv->tx_desc_tail),
 			    cipher_type);
 		atmel_wmem8(priv, atmel_tx(priv, TX_DESC_CIPHER_LENGTH_OFFSET, priv->tx_desc_tail),
 			    cipher_length);
 	}
 	atmel_wmem32(priv, atmel_tx(priv, TX_DESC_NEXT_OFFSET, priv->tx_desc_tail), 0x80000000L);
 	atmel_wmem8(priv, atmel_tx(priv, TX_DESC_FLAGS_OFFSET, priv->tx_desc_tail), TX_FIRM_OWN);
 	if (priv->tx_desc_previous != priv->tx_desc_tail)
 		atmel_wmem32(priv, atmel_tx(priv, TX_DESC_NEXT_OFFSET, priv->tx_desc_previous), 0);
 	priv->tx_desc_previous = priv->tx_desc_tail;
 	if (priv->tx_desc_tail < (priv->host_info.tx_desc_count - 1))
 		priv->tx_desc_tail++;
 	else
 		priv->tx_desc_tail = 0;
 	priv->tx_desc_free--;
 	priv->tx_free_mem -= len;
 }
 static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev)
 {
 	static const u8 SNAP_RFC1024[6] = { 0xaa, 0xaa, 0x03, 0x00, 0x00, 0x00 };
 	struct atmel_private *priv = netdev_priv(dev);
 	struct ieee80211_hdr header;
 	unsigned long flags;
 	u16 buff, frame_ctl, len = (ETH_ZLEN < skb->len) ? skb->len : ETH_ZLEN;
 	if (priv->card && priv->present_callback &&
 	    !(*priv->present_callback)(priv->card)) {
 		dev->stats.tx_errors++;
 		dev_kfree_skb(skb);
 		return NETDEV_TX_OK;
 	}
 	if (priv->station_state != STATION_STATE_READY) {
 		dev->stats.tx_errors++;
 		dev_kfree_skb(skb);
 		return NETDEV_TX_OK;
 	}
 	/* first ensure the timer func cannot run */
 	spin_lock_bh(&priv->timerlock);
 	/* then stop the hardware ISR */
 	spin_lock_irqsave(&priv->irqlock, flags);
 	/* nb doing the above in the opposite order will deadlock */
 	/* The Wireless Header is 30 bytes. In the Ethernet packet we "cut" the
 	   12 first bytes (containing DA/SA) and put them in the appropriate
 	   fields of the Wireless Header. Thus the packet length is then the
 	   initial + 18 (+30-12) */
 	if (!(buff = find_tx_buff(priv, len + 18))) {
 		dev->stats.tx_dropped++;
 		spin_unlock_irqrestore(&priv->irqlock, flags);
 		spin_unlock_bh(&priv->timerlock);
 		netif_stop_queue(dev);
 		return NETDEV_TX_BUSY;
 	}
 	frame_ctl = IEEE80211_FTYPE_DATA;
 	header.duration_id = 0;
 	header.seq_ctrl = 0;
 	if (priv->wep_is_on)
 		frame_ctl |= IEEE80211_FCTL_PROTECTED;
 	if (priv->operating_mode == IW_MODE_ADHOC) {
 		skb_copy_from_linear_data(skb, &header.addr1, 6);
 		memcpy(&header.addr2, dev->dev_addr, 6);
 		memcpy(&header.addr3, priv->BSSID, 6);
 	} else {
 		frame_ctl |= IEEE80211_FCTL_TODS;
 		memcpy(&header.addr1, priv->CurrentBSSID, 6);
 		memcpy(&header.addr2, dev->dev_addr, 6);
 		skb_copy_from_linear_data(skb, &header.addr3, 6);
 	}
 	if (priv->use_wpa)
 		memcpy(&header.addr4, SNAP_RFC1024, 6);
 	header.frame_control = cpu_to_le16(frame_ctl);
 	/* Copy the wireless header into the card */
 	atmel_copy_to_card(dev, buff, (unsigned char *)&header, DATA_FRAME_WS_HEADER_SIZE);
 	/* Copy the packet sans its 802.3 header addresses which have been replaced */
 	atmel_copy_to_card(dev, buff + DATA_FRAME_WS_HEADER_SIZE, skb->data + 12, len - 12);
 	priv->tx_buff_tail += len - 12 + DATA_FRAME_WS_HEADER_SIZE;
 	/* low bit of first byte of destination tells us if broadcast */
 	tx_update_descriptor(priv, *(skb->data) & 0x01, len + 18, buff, TX_PACKET_TYPE_DATA);
 	dev->trans_start = jiffies;
 	dev->stats.tx_bytes += len;
 	spin_unlock_irqrestore(&priv->irqlock, flags);
 	spin_unlock_bh(&priv->timerlock);
 	dev_kfree_skb(skb);
 	return NETDEV_TX_OK;
 }
 static void atmel_transmit_management_frame(struct atmel_private *priv,
 					    struct ieee80211_hdr *header,
 					    u8 *body, int body_len)
 {
 	u16 buff;
 	int len = MGMT_FRAME_BODY_OFFSET + body_len;
 	if (!(buff = find_tx_buff(priv, len)))
 		return;
 	atmel_copy_to_card(priv->dev, buff, (u8 *)header, MGMT_FRAME_BODY_OFFSET);
 	atmel_copy_to_card(priv->dev, buff + MGMT_FRAME_BODY_OFFSET, body, body_len);
 	priv->tx_buff_tail += len;
 	tx_update_descriptor(priv, header->addr1[0] & 0x01, len, buff, TX_PACKET_TYPE_MGMT);
 }
 static void fast_rx_path(struct atmel_private *priv,
 			 struct ieee80211_hdr *header,
 			 u16 msdu_size, u16 rx_packet_loc, u32 crc)
 {
 	/* fast path: unfragmented packet copy directly into skbuf */
 	u8 mac4[6];
 	struct sk_buff	*skb;
 	unsigned char *skbp;
 	/* get the final, mac 4 header field, this tells us encapsulation */
 	atmel_copy_to_host(priv->dev, mac4, rx_packet_loc + 24, 6);
 	msdu_size -= 6;
 	if (priv->do_rx_crc) {
 		crc = crc32_le(crc, mac4, 6);
 		msdu_size -= 4;
 	}
 	if (!(skb = dev_alloc_skb(msdu_size + 14))) {
 		priv->dev->stats.rx_dropped++;
 		return;
 	}
 	skb_reserve(skb, 2);
 	skbp = skb_put(skb, msdu_size + 12);
 	atmel_copy_to_host(priv->dev, skbp + 12, rx_packet_loc + 30, msdu_size);
 	if (priv->do_rx_crc) {
 		u32 netcrc;
 		crc = crc32_le(crc, skbp + 12, msdu_size);
 		atmel_copy_to_host(priv->dev, (void *)&netcrc, rx_packet_loc + 30 + msdu_size, 4);
 		if ((crc ^ 0xffffffff) != netcrc) {
 			priv->dev->stats.rx_crc_errors++;
 			dev_kfree_skb(skb);
 			return;
 		}
 	}
 	memcpy(skbp, header->addr1, 6); /* destination address */
 	if (le16_to_cpu(header->frame_control) & IEEE80211_FCTL_FROMDS)
 		memcpy(&skbp[6], header->addr3, 6);
 	else
 		memcpy(&skbp[6], header->addr2, 6); /* source address */
 	skb->protocol = eth_type_trans(skb, priv->dev);
 	skb->ip_summed = CHECKSUM_NONE;
 	netif_rx(skb);
 	priv->dev->stats.rx_bytes += 12 + msdu_size;
 	priv->dev->stats.rx_packets++;
 }
 /* Test to see if the packet in card memory at packet_loc has a valid CRC
   It doesn't matter that this is slow: it is only used to proble the first few
   packets. */
 static int probe_crc(struct atmel_private *priv, u16 packet_loc, u16 msdu_size)
 {
 	int i = msdu_size - 4;
 	u32 netcrc, crc = 0xffffffff;
 	if (msdu_size < 4)
 		return 0;
 	atmel_copy_to_host(priv->dev, (void *)&netcrc, packet_loc + i, 4);
 	atmel_writeAR(priv->dev, packet_loc);
 	while (i--) {
 		u8 octet = atmel_read8(priv->dev, DR);
 		crc = crc32_le(crc, &octet, 1);
 	}
 	return (crc ^ 0xffffffff) == netcrc;
 }
 static void frag_rx_path(struct atmel_private *priv,
 			 struct ieee80211_hdr *header,
 			 u16 msdu_size, u16 rx_packet_loc, u32 crc, u16 seq_no,
 			 u8 frag_no, int more_frags)
 {
 	u8 mac4[6];
 	u8 source[6];
 	struct sk_buff *skb;
 	if (le16_to_cpu(header->frame_control) & IEEE80211_FCTL_FROMDS)
 		memcpy(source, header->addr3, 6);
 	else
 		memcpy(source, header->addr2, 6);
 	rx_packet_loc += 24; /* skip header */
 	if (priv->do_rx_crc)
 		msdu_size -= 4;
 	if (frag_no == 0) { /* first fragment */
 		atmel_copy_to_host(priv->dev, mac4, rx_packet_loc, 6);
 		msdu_size -= 6;
 		rx_packet_loc += 6;
 		if (priv->do_rx_crc)
 			crc = crc32_le(crc, mac4, 6);
 		priv->frag_seq = seq_no;
 		priv->frag_no = 1;
 		priv->frag_len = msdu_size;
 		memcpy(priv->frag_source, source, 6);
 		memcpy(&priv->rx_buf[6], source, 6);
 		memcpy(priv->rx_buf, header->addr1, 6);
 		atmel_copy_to_host(priv->dev, &priv->rx_buf[12], rx_packet_loc, msdu_size);
 		if (priv->do_rx_crc) {
 			u32 netcrc;
 			crc = crc32_le(crc, &priv->rx_buf[12], msdu_size);
 			atmel_copy_to_host(priv->dev, (void *)&netcrc, rx_packet_loc + msdu_size, 4);
 			if ((crc ^ 0xffffffff) != netcrc) {
 				priv->dev->stats.rx_crc_errors++;
 				memset(priv->frag_source, 0xff, 6);
 			}
 		}
 	} else if (priv->frag_no == frag_no &&
 		   priv->frag_seq == seq_no &&
 		   memcmp(priv->frag_source, source, 6) == 0) {
 		atmel_copy_to_host(priv->dev, &priv->rx_buf[12 + priv->frag_len],
 				   rx_packet_loc, msdu_size);
 		if (priv->do_rx_crc) {
 			u32 netcrc;
 			crc = crc32_le(crc,
 				       &priv->rx_buf[12 + priv->frag_len],
 				       msdu_size);
 			atmel_copy_to_host(priv->dev, (void *)&netcrc, rx_packet_loc + msdu_size, 4);
 			if ((crc ^ 0xffffffff) != netcrc) {
 				priv->dev->stats.rx_crc_errors++;
 				memset(priv->frag_source, 0xff, 6);
 				more_frags = 1; /* don't send broken assembly */
 			}
 		}
 		priv->frag_len += msdu_size;
 		priv->frag_no++;
 		if (!more_frags) { /* last one */
 			memset(priv->frag_source, 0xff, 6);
 			if (!(skb = dev_alloc_skb(priv->frag_len + 14))) {
 				priv->dev->stats.rx_dropped++;
 			} else {
 				skb_reserve(skb, 2);
 				memcpy(skb_put(skb, priv->frag_len + 12),
 				       priv->rx_buf,
 				       priv->frag_len + 12);
 				skb->protocol = eth_type_trans(skb, priv->dev);
 				skb->ip_summed = CHECKSUM_NONE;
 				netif_rx(skb);
 				priv->dev->stats.rx_bytes += priv->frag_len + 12;
 				priv->dev->stats.rx_packets++;
 			}
 		}
 	} else
 		priv->wstats.discard.fragment++;
 }
 static void rx_done_irq(struct atmel_private *priv)
 {
 	int i;
 	struct ieee80211_hdr header;
 	for (i = 0;
 	     atmel_rmem8(priv, atmel_rx(priv, RX_DESC_FLAGS_OFFSET, priv->rx_desc_head)) == RX_DESC_FLAG_VALID &&
 		     i < priv->host_info.rx_desc_count;
 	     i++) {
 		u16 msdu_size, rx_packet_loc, frame_ctl, seq_control;
 		u8 status = atmel_rmem8(priv, atmel_rx(priv, RX_DESC_STATUS_OFFSET, priv->rx_desc_head));
 		u32 crc = 0xffffffff;
 		if (status != RX_STATUS_SUCCESS) {
 			if (status == 0xc1) /* determined by experiment */
 				priv->wstats.discard.nwid++;
 			else
 				priv->dev->stats.rx_errors++;
 			goto next;
 		}
 		msdu_size = atmel_rmem16(priv, atmel_rx(priv, RX_DESC_MSDU_SIZE_OFFSET, priv->rx_desc_head));
 		rx_packet_loc = atmel_rmem16(priv, atmel_rx(priv, RX_DESC_MSDU_POS_OFFSET, priv->rx_desc_head));
 		if (msdu_size < 30) {
 			priv->dev->stats.rx_errors++;
 			goto next;
 		}
 		/* Get header as far as end of seq_ctrl */
 		atmel_copy_to_host(priv->dev, (char *)&header, rx_packet_loc, 24);
 		frame_ctl = le16_to_cpu(header.frame_control);
 		seq_control = le16_to_cpu(header.seq_ctrl);
 		/* probe for CRC use here if needed  once five packets have
 		   arrived with the same crc status, we assume we know what's
 		   happening and stop probing */
 		if (priv->probe_crc) {
 			if (!priv->wep_is_on || !(frame_ctl & IEEE80211_FCTL_PROTECTED)) {
 				priv->do_rx_crc = probe_crc(priv, rx_packet_loc, msdu_size);
 			} else {
 				priv->do_rx_crc = probe_crc(priv, rx_packet_loc + 24, msdu_size - 24);
 			}
 			if (priv->do_rx_crc) {
 				if (priv->crc_ok_cnt++ > 5)
 					priv->probe_crc = 0;
 			} else {
 				if (priv->crc_ko_cnt++ > 5)
 					priv->probe_crc = 0;
 			}
 		}
 		/* don't CRC header when WEP in use */
 		if (priv->do_rx_crc && (!priv->wep_is_on || !(frame_ctl & IEEE80211_FCTL_PROTECTED))) {
 			crc = crc32_le(0xffffffff, (unsigned char *)&header, 24);
 		}
 		msdu_size -= 24; /* header */
 		if ((frame_ctl & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_DATA) {
 			int more_fragments = frame_ctl & IEEE80211_FCTL_MOREFRAGS;
 			u8 packet_fragment_no = seq_control & IEEE80211_SCTL_FRAG;
 			u16 packet_sequence_no = (seq_control & IEEE80211_SCTL_SEQ) >> 4;
 			if (!more_fragments && packet_fragment_no == 0) {
 				fast_rx_path(priv, &header, msdu_size, rx_packet_loc, crc);
 			} else {
 				frag_rx_path(priv, &header, msdu_size, rx_packet_loc, crc,
 					     packet_sequence_no, packet_fragment_no, more_fragments);
 			}
 		}
 		if ((frame_ctl & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT) {
 			/* copy rest of packet into buffer */
 			atmel_copy_to_host(priv->dev, (unsigned char *)&priv->rx_buf, rx_packet_loc + 24, msdu_size);
 			/* we use the same buffer for frag reassembly and control packets */
 			memset(priv->frag_source, 0xff, 6);
 			if (priv->do_rx_crc) {
 				/* last 4 octets is crc */
 				msdu_size -= 4;
 				crc = crc32_le(crc, (unsigned char *)&priv->rx_buf, msdu_size);
 				if ((crc ^ 0xffffffff) != (*((u32 *)&priv->rx_buf[msdu_size]))) {
 					priv->dev->stats.rx_crc_errors++;
 					goto next;
 				}
 			}
 			atmel_management_frame(priv, &header, msdu_size,
 					       atmel_rmem8(priv, atmel_rx(priv, RX_DESC_RSSI_OFFSET, priv->rx_desc_head)));
 		}
 next:
 		/* release descriptor */
 		atmel_wmem8(priv, atmel_rx(priv, RX_DESC_FLAGS_OFFSET, priv->rx_desc_head), RX_DESC_FLAG_CONSUMED);
 		if (priv->rx_desc_head < (priv->host_info.rx_desc_count - 1))
 			priv->rx_desc_head++;
 		else
 			priv->rx_desc_head = 0;
 	}
 }
 static irqreturn_t service_interrupt(int irq, void *dev_id)
 {
 	struct net_device *dev = (struct net_device *) dev_id;
 	struct atmel_private *priv = netdev_priv(dev);
 	u8 isr;
 	int i = -1;
 	static u8 irq_order[] = {
 		ISR_OUT_OF_RANGE,
 		ISR_RxCOMPLETE,
 		ISR_TxCOMPLETE,
 		ISR_RxFRAMELOST,
 		ISR_FATAL_ERROR,
 		ISR_COMMAND_COMPLETE,
 		ISR_IBSS_MERGE,
 		ISR_GENERIC_IRQ
 	};
 	if (priv->card && priv->present_callback &&
 	    !(*priv->present_callback)(priv->card))
 		return IRQ_HANDLED;
 	/* In this state upper-level code assumes it can mess with
 	   the card unhampered by interrupts which may change register state.
 	   Note that even though the card shouldn't generate interrupts
 	   the inturrupt line may be shared. This allows card setup
 	   to go on without disabling interrupts for a long time. */
 	if (priv->station_state == STATION_STATE_DOWN)
 		return IRQ_NONE;
 	atmel_clear_gcr(dev, GCR_ENINT); /* disable interrupts */
 	while (1) {
 		if (!atmel_lock_mac(priv)) {
 			/* failed to contact card */
 			printk(KERN_ALERT "%s: failed to contact MAC.\n", dev->name);
 			return IRQ_HANDLED;
 		}
 		isr = atmel_rmem8(priv, atmel_hi(priv, IFACE_INT_STATUS_OFFSET));
 		atmel_wmem8(priv, atmel_hi(priv, IFACE_LOCKOUT_MAC_OFFSET), 0);
 		if (!isr) {
 			atmel_set_gcr(dev, GCR_ENINT); /* enable interrupts */
 			return i == -1 ? IRQ_NONE : IRQ_HANDLED;
 		}
 		atmel_set_gcr(dev, GCR_ACKINT); /* acknowledge interrupt */
 		for (i = 0; i < ARRAY_SIZE(irq_order); i++)
 			if (isr & irq_order[i])
 				break;
 		if (!atmel_lock_mac(priv)) {
 			/* failed to contact card */
 			printk(KERN_ALERT "%s: failed to contact MAC.\n", dev->name);
 			return IRQ_HANDLED;
 		}
 		isr = atmel_rmem8(priv, atmel_hi(priv, IFACE_INT_STATUS_OFFSET));
 		isr ^= irq_order[i];
 		atmel_wmem8(priv, atmel_hi(priv, IFACE_INT_STATUS_OFFSET), isr);
 		atmel_wmem8(priv, atmel_hi(priv, IFACE_LOCKOUT_MAC_OFFSET), 0);
 		switch (irq_order[i]) {
 		case ISR_OUT_OF_RANGE:
 			if (priv->operating_mode == IW_MODE_INFRA &&
 			    priv->station_state == STATION_STATE_READY) {
 				priv->station_is_associated = 0;
 				atmel_scan(priv, 1);
 			}
 			break;
 		case ISR_RxFRAMELOST:
 			priv->wstats.discard.misc++;
 			/* fall through */
 		case ISR_RxCOMPLETE:
 			rx_done_irq(priv);
 			break;
 		case ISR_TxCOMPLETE:
 			tx_done_irq(priv);
 			break;
 		case ISR_FATAL_ERROR:
 			printk(KERN_ALERT "%s: *** FATAL error interrupt ***\n", dev->name);
 			atmel_enter_state(priv, STATION_STATE_MGMT_ERROR);
 			break;
 		case ISR_COMMAND_COMPLETE:
 			atmel_command_irq(priv);
 			break;
 		case ISR_IBSS_MERGE:
 			atmel_get_mib(priv, Mac_Mgmt_Mib_Type, MAC_MGMT_MIB_CUR_BSSID_POS,
 				      priv->CurrentBSSID, 6);
 			/* The WPA stuff cares about the current AP address */
 			if (priv->use_wpa)
 				build_wpa_mib(priv);
 			break;
 		case ISR_GENERIC_IRQ:
 			printk(KERN_INFO "%s: Generic_irq received.\n", dev->name);
 			break;
 		}
 	}
 }
 static struct iw_statistics *atmel_get_wireless_stats(struct net_device *dev)
 {
 	struct atmel_private *priv = netdev_priv(dev);
 	/* update the link quality here in case we are seeing no beacons
 	   at all to drive the process */
 	atmel_smooth_qual(priv);
 	priv->wstats.status = priv->station_state;
 	if (priv->operating_mode == IW_MODE_INFRA) {
 		if (priv->station_state != STATION_STATE_READY) {
 			priv->wstats.qual.qual = 0;
 			priv->wstats.qual.level = 0;
 			priv->wstats.qual.updated = (IW_QUAL_QUAL_INVALID
 					| IW_QUAL_LEVEL_INVALID);
 		}
 		priv->wstats.qual.noise = 0;
 		priv->wstats.qual.updated |= IW_QUAL_NOISE_INVALID;
 	} else {
 		/* Quality levels cannot be determined in ad-hoc mode,
 		   because we can 'hear' more that one remote station. */
 		priv->wstats.qual.qual = 0;
 		priv->wstats.qual.level	= 0;
 		priv->wstats.qual.noise	= 0;
 		priv->wstats.qual.updated = IW_QUAL_QUAL_INVALID
 					| IW_QUAL_LEVEL_INVALID
 					| IW_QUAL_NOISE_INVALID;
 		priv->wstats.miss.beacon = 0;
 	}
 	return &priv->wstats;
 }
 static int atmel_change_mtu(struct net_device *dev, int new_mtu)
 {
 	if ((new_mtu < 68) || (new_mtu > 2312))
 		return -EINVAL;
 	dev->mtu = new_mtu;
 	return 0;
 }
 static int atmel_set_mac_address(struct net_device *dev, void *p)
 {
 	struct sockaddr *addr = p;
 	memcpy (dev->dev_addr, addr->sa_data, dev->addr_len);
 	return atmel_open(dev);
 }
 EXPORT_SYMBOL(atmel_open);
 int atmel_open(struct net_device *dev)
 {
 	struct atmel_private *priv = netdev_priv(dev);
 	int i, channel, err;
 	/* any scheduled timer is no longer needed and might screw things up.. */
 	del_timer_sync(&priv->management_timer);
 	/* Interrupts will not touch the card once in this state... */
 	priv->station_state = STATION_STATE_DOWN;
 	if (priv->new_SSID_size) {
 		memcpy(priv->SSID, priv->new_SSID, priv->new_SSID_size);
 		priv->SSID_size = priv->new_SSID_size;
 		priv->new_SSID_size = 0;
 	}
 	priv->BSS_list_entries = 0;
 	priv->AuthenticationRequestRetryCnt = 0;
 	priv->AssociationRequestRetryCnt = 0;
 	priv->ReAssociationRequestRetryCnt = 0;
 	priv->CurrentAuthentTransactionSeqNum = 0x0001;
 	priv->ExpectedAuthentTransactionSeqNum = 0x0002;
 	priv->site_survey_state = SITE_SURVEY_IDLE;
 	priv->station_is_associated = 0;
 	err = reset_atmel_card(dev);
 	if (err)
 		return err;
 	if (priv->config_reg_domain) {
 		priv->reg_domain = priv->config_reg_domain;
 		atmel_set_mib8(priv, Phy_Mib_Type, PHY_MIB_REG_DOMAIN_POS, priv->reg_domain);
 	} else {
 		priv->reg_domain = atmel_get_mib8(priv, Phy_Mib_Type, PHY_MIB_REG_DOMAIN_POS);
 		for (i = 0; i < ARRAY_SIZE(channel_table); i++)
 			if (priv->reg_domain == channel_table[i].reg_domain)
 				break;
 		if (i == ARRAY_SIZE(channel_table)) {
 			priv->reg_domain = REG_DOMAIN_MKK1;
 			printk(KERN_ALERT "%s: failed to get regulatory domain: assuming MKK1.\n", dev->name);
 		}
 	}
 	if ((channel = atmel_validate_channel(priv, priv->channel)))
 		priv->channel = channel;
 	/* this moves station_state on.... */
 	atmel_scan(priv, 1);
 	atmel_set_gcr(priv->dev, GCR_ENINT); /* enable interrupts */
 	return 0;
 }
 static int atmel_close(struct net_device *dev)
 {
 	struct atmel_private *priv = netdev_priv(dev);
 	/* Send event to userspace that we are disassociating */
 	if (priv->station_state == STATION_STATE_READY) {
 		union iwreq_data wrqu;
 		wrqu.data.length = 0;
 		wrqu.data.flags = 0;
 		wrqu.ap_addr.sa_family = ARPHRD_ETHER;
 		memset(wrqu.ap_addr.sa_data, 0, ETH_ALEN);
 		wireless_send_event(priv->dev, SIOCGIWAP, &wrqu, NULL);
 	}
 	atmel_enter_state(priv, STATION_STATE_DOWN);
 	if (priv->bus_type == BUS_TYPE_PCCARD)
 		atmel_write16(dev, GCR, 0x0060);
 	atmel_write16(dev, GCR, 0x0040);
 	return 0;
 }
 static int atmel_validate_channel(struct atmel_private *priv, int channel)
 {
 	/* check that channel is OK, if so return zero,
 	   else return suitable default channel */
 	int i;
 	for (i = 0; i < ARRAY_SIZE(channel_table); i++)
 		if (priv->reg_domain == channel_table[i].reg_domain) {
 			if (channel >= channel_table[i].min &&
 			    channel <= channel_table[i].max)
 				return 0;
 			else
 				return channel_table[i].min;
 		}
 	return 0;
 }
 static int atmel_proc_output (char *buf, struct atmel_private *priv)
 {
 	int i;
 	char *p = buf;
 	char *s, *r, *c;
 	p += sprintf(p, "Driver version:\t\t%d.%d\n",
 		     DRIVER_MAJOR, DRIVER_MINOR);
 	if (priv->station_state != STATION_STATE_DOWN) {
 		p += sprintf(p, "Firmware version:\t%d.%d build %d\n"
 				"Firmware location:\t",
 			     priv->host_info.major_version,
 			     priv->host_info.minor_version,
 			     priv->host_info.build_version);
 		if (priv->card_type != CARD_TYPE_EEPROM)
 			p += sprintf(p, "on card\n");
 		else if (priv->firmware)
 			p += sprintf(p, "%s loaded by host\n",
 				     priv->firmware_id);
 		else
 			p += sprintf(p, "%s loaded by hotplug\n",
 				     priv->firmware_id);
 		switch (priv->card_type) {
 		case CARD_TYPE_PARALLEL_FLASH:
 			c = "Parallel flash";
 			break;
 		case CARD_TYPE_SPI_FLASH:
 			c = "SPI flash\n";
 			break;
 		case CARD_TYPE_EEPROM:
 			c = "EEPROM";
 			break;
 		default:
 			c = "<unknown>";
 		}
 		r = "<unknown>";
 		for (i = 0; i < ARRAY_SIZE(channel_table); i++)
 			if (priv->reg_domain == channel_table[i].reg_domain)
 				r = channel_table[i].name;
 		p += sprintf(p, "MAC memory type:\t%s\n", c);
 		p += sprintf(p, "Regulatory domain:\t%s\n", r);
 		p += sprintf(p, "Host CRC checking:\t%s\n",
 			     priv->do_rx_crc ? "On" : "Off");
 		p += sprintf(p, "WPA-capable firmware:\t%s\n",
 			     priv->use_wpa ? "Yes" : "No");
 	}
 	switch (priv->station_state) {
 	case STATION_STATE_SCANNING:
 		s = "Scanning";
 		break;
 	case STATION_STATE_JOINNING:
 		s = "Joining";
 		break;
 	case STATION_STATE_AUTHENTICATING:
 		s = "Authenticating";
 		break;
 	case STATION_STATE_ASSOCIATING:
 		s = "Associating";
 		break;
 	case STATION_STATE_READY:
 		s = "Ready";
 		break;
 	case STATION_STATE_REASSOCIATING:
 		s = "Reassociating";
 		break;
 	case STATION_STATE_MGMT_ERROR:
 		s = "Management error";
 		break;
 	case STATION_STATE_DOWN:
 		s = "Down";
 		break;
 	default:
 		s = "<unknown>";
 	}
 	p += sprintf(p, "Current state:\t\t%s\n", s);
 	return p - buf;
 }
 static int atmel_read_proc(char *page, char **start, off_t off,
 			   int count, int *eof, void *data)
 {
 	struct atmel_private *priv = data;
 	int len = atmel_proc_output (page, priv);
 	if (len <= off+count)
 		*eof = 1;
 	*start = page + off;
 	len -= off;
 	if (len > count)
 		len = count;
 	if (len < 0)
 		len = 0;
 	return len;
 }
 static const struct net_device_ops atmel_netdev_ops = {
 	.ndo_open 		= atmel_open,
 	.ndo_stop		= atmel_close,
 	.ndo_change_mtu 	= atmel_change_mtu,
 	.ndo_set_mac_address 	= atmel_set_mac_address,
 	.ndo_start_xmit 	= start_tx,
 	.ndo_do_ioctl 		= atmel_ioctl,
 	.ndo_validate_addr	= eth_validate_addr,
 };
 struct net_device *init_atmel_card(unsigned short irq, unsigned long port,
 				   const AtmelFWType fw_type,
 				   struct device *sys_dev,
 				   int (*card_present)(void *), void *card)
 {
 	struct proc_dir_entry *ent;
 	struct net_device *dev;
 	struct atmel_private *priv;
 	int rc;
 	/* Create the network device object. */
 	dev = alloc_etherdev(sizeof(*priv));
 	if (!dev) {
 		printk(KERN_ERR "atmel: Couldn't alloc_etherdev\n");
 		return NULL;
 	}
 	if (dev_alloc_name(dev, dev->name) < 0) {
 		printk(KERN_ERR "atmel: Couldn't get name!\n");
 		goto err_out_free;
 	}
 	priv = netdev_priv(dev);
 	priv->dev = dev;
 	priv->sys_dev = sys_dev;
 	priv->present_callback = card_present;
 	priv->card = card;
 	priv->firmware = NULL;
 	priv->firmware_id[0] = '\0';
 	priv->firmware_type = fw_type;
 	if (firmware) /* module parameter */
 		strcpy(priv->firmware_id, firmware);
 	priv->bus_type = card_present ? BUS_TYPE_PCCARD : BUS_TYPE_PCI;
 	priv->station_state = STATION_STATE_DOWN;
 	priv->do_rx_crc = 0;
 	/* For PCMCIA cards, some chips need CRC, some don't
 	   so we have to probe. */
 	if (priv->bus_type == BUS_TYPE_PCCARD) {
 		priv->probe_crc = 1;
 		priv->crc_ok_cnt = priv->crc_ko_cnt = 0;
 	} else
 		priv->probe_crc = 0;
 	priv->last_qual = jiffies;
 	priv->last_beacon_timestamp = 0;
 	memset(priv->frag_source, 0xff, sizeof(priv->frag_source));
 	memset(priv->BSSID, 0, 6);
 	priv->CurrentBSSID[0] = 0xFF; /* Initialize to something invalid.... */
 	priv->station_was_associated = 0;
 	priv->last_survey = jiffies;
 	priv->preamble = LONG_PREAMBLE;
 	priv->operating_mode = IW_MODE_INFRA;
 	priv->connect_to_any_BSS = 0;
 	priv->config_reg_domain = 0;
 	priv->reg_domain = 0;
 	priv->tx_rate = 3;
 	priv->auto_tx_rate = 1;
 	priv->channel = 4;
 	priv->power_mode = 0;
 	priv->SSID[0] = '\0';
 	priv->SSID_size = 0;
 	priv->new_SSID_size = 0;
 	priv->frag_threshold = 2346;
 	priv->rts_threshold = 2347;
 	priv->short_retry = 7;
 	priv->long_retry = 4;
 	priv->wep_is_on = 0;
 	priv->default_key = 0;
 	priv->encryption_level = 0;
 	priv->exclude_unencrypted = 0;
 	priv->group_cipher_suite = priv->pairwise_cipher_suite = CIPHER_SUITE_NONE;
 	priv->use_wpa = 0;
 	memset(priv->wep_keys, 0, sizeof(priv->wep_keys));
 	memset(priv->wep_key_len, 0, sizeof(priv->wep_key_len));
 	priv->default_beacon_period = priv->beacon_period = 100;
 	priv->listen_interval = 1;
 	init_timer(&priv->management_timer);
 	spin_lock_init(&priv->irqlock);
 	spin_lock_init(&priv->timerlock);
 	priv->management_timer.function = atmel_management_timer;
 	priv->management_timer.data = (unsigned long) dev;
 	dev->netdev_ops = &atmel_netdev_ops;
 	dev->wireless_handlers = &atmel_handler_def;
 	dev->irq = irq;
 	dev->base_addr = port;
 	SET_NETDEV_DEV(dev, sys_dev);
 	if ((rc = request_irq(dev->irq, service_interrupt, IRQF_SHARED, dev->name, dev))) {
 		printk(KERN_ERR "%s: register interrupt %d failed, rc %d\n", dev->name, irq, rc);
 		goto err_out_free;
 	}
 	if (!request_region(dev->base_addr, 32,
 			    priv->bus_type == BUS_TYPE_PCCARD ?  "atmel_cs" : "atmel_pci")) {
 		goto err_out_irq;
 	}
 	if (register_netdev(dev))
 		goto err_out_res;
 	if (!probe_atmel_card(dev)) {
 		unregister_netdev(dev);
 		goto err_out_res;
 	}
 	netif_carrier_off(dev);
 	ent = create_proc_read_entry ("driver/atmel", 0, NULL, atmel_read_proc, priv);
 	if (!ent)
 		printk(KERN_WARNING "atmel: unable to create /proc entry.\n");
 	printk(KERN_INFO "%s: Atmel at76c50x. Version %d.%d. MAC %pM\n",
 	       dev->name, DRIVER_MAJOR, DRIVER_MINOR, dev->dev_addr);
 	return dev;
 err_out_res:
 	release_region(dev->base_addr, 32);
 err_out_irq:
 	free_irq(dev->irq, dev);
 err_out_free:
 	free_netdev(dev);
 	return NULL;
 }
 EXPORT_SYMBOL(init_atmel_card);
 void stop_atmel_card(struct net_device *dev)
 {
 	struct atmel_private *priv = netdev_priv(dev);
 	/* put a brick on it... */
 	if (priv->bus_type == BUS_TYPE_PCCARD)
 		atmel_write16(dev, GCR, 0x0060);
 	atmel_write16(dev, GCR, 0x0040);
 	del_timer_sync(&priv->management_timer);
 	unregister_netdev(dev);
 	remove_proc_entry("driver/atmel", NULL);
 	free_irq(dev->irq, dev);
 	kfree(priv->firmware);
 	release_region(dev->base_addr, 32);
 	free_netdev(dev);
 }
 EXPORT_SYMBOL(stop_atmel_card);
 static int atmel_set_essid(struct net_device *dev,
 			   struct iw_request_info *info,
 			   struct iw_point *dwrq,
 			   char *extra)
 {
 	struct atmel_private *priv = netdev_priv(dev);
 	/* Check if we asked for `any' */
 	if (dwrq->flags == 0) {
 		priv->connect_to_any_BSS = 1;
 	} else {
 		int index = (dwrq->flags & IW_ENCODE_INDEX) - 1;
 		priv->connect_to_any_BSS = 0;
 		/* Check the size of the string */
 		if (dwrq->length > MAX_SSID_LENGTH)
 			 return -E2BIG;
 		if (index != 0)
 			return -EINVAL;
 		memcpy(priv->new_SSID, extra, dwrq->length);
 		priv->new_SSID_size = dwrq->length;
 	}
 	return -EINPROGRESS;
 }
 static int atmel_get_essid(struct net_device *dev,
 			   struct iw_request_info *info,
 			   struct iw_point *dwrq,
 			   char *extra)
 {
 	struct atmel_private *priv = netdev_priv(dev);
 	/* Get the current SSID */
 	if (priv->new_SSID_size != 0) {
 		memcpy(extra, priv->new_SSID, priv->new_SSID_size);
 		dwrq->length = priv->new_SSID_size;
 	} else {
 		memcpy(extra, priv->SSID, priv->SSID_size);
 		dwrq->length = priv->SSID_size;
 	}
 	dwrq->flags = !priv->connect_to_any_BSS; /* active */
 	return 0;
 }
 static int atmel_get_wap(struct net_device *dev,
 			 struct iw_request_info *info,
 			 struct sockaddr *awrq,
 			 char *extra)
 {
 	struct atmel_private *priv = netdev_priv(dev);
 	memcpy(awrq->sa_data, priv->CurrentBSSID, 6);
 	awrq->sa_family = ARPHRD_ETHER;
 	return 0;
 }
 static int atmel_set_encode(struct net_device *dev,
 			    struct iw_request_info *info,
 			    struct iw_point *dwrq,
 			    char *extra)
 {
 	struct atmel_private *priv = netdev_priv(dev);
 	/* Basic checking: do we have a key to set ?
 	 * Note : with the new API, it's impossible to get a NULL pointer.
 	 * Therefore, we need to check a key size == 0 instead.
 	 * New version of iwconfig properly set the IW_ENCODE_NOKEY flag
 	 * when no key is present (only change flags), but older versions
 	 * don't do it. - Jean II */
 	if (dwrq->length > 0) {
 		int index = (dwrq->flags & IW_ENCODE_INDEX) - 1;
 		int current_index = priv->default_key;
 		/* Check the size of the key */
 		if (dwrq->length > 13) {
 			return -EINVAL;
 		}
 		/* Check the index (none -> use current) */
 		if (index < 0 || index >= 4)
 			index = current_index;
 		else
 			priv->default_key = index;
 		/* Set the length */
 		if (dwrq->length > 5)
 			priv->wep_key_len[index] = 13;
 		else
 			if (dwrq->length > 0)
 				priv->wep_key_len[index] = 5;
 			else
 				/* Disable the key */
 				priv->wep_key_len[index] = 0;
 		/* Check if the key is not marked as invalid */
 		if (!(dwrq->flags & IW_ENCODE_NOKEY)) {
 			/* Cleanup */
 			memset(priv->wep_keys[index], 0, 13);
 			/* Copy the key in the driver */
 			memcpy(priv->wep_keys[index], extra, dwrq->length);
 		}
 		/* WE specify that if a valid key is set, encryption
 		 * should be enabled (user may turn it off later)
 		 * This is also how "iwconfig ethX key on" works */
 		if (index == current_index &&
 		    priv->wep_key_len[index] > 0) {
 			priv->wep_is_on = 1;
 			priv->exclude_unencrypted = 1;
 			if (priv->wep_key_len[index] > 5) {
 				priv->pairwise_cipher_suite = CIPHER_SUITE_WEP_128;
 				priv->encryption_level = 2;
 			} else {
 				priv->pairwise_cipher_suite = CIPHER_SUITE_WEP_64;
 				priv->encryption_level = 1;
 			}
 		}
 	} else {
 		/* Do we want to just set the transmit key index ? */
 		int index = (dwrq->flags & IW_ENCODE_INDEX) - 1;
 		if (index >= 0 && index < 4) {
 			priv->default_key = index;
 		} else
 			/* Don't complain if only change the mode */
 			if (!(dwrq->flags & IW_ENCODE_MODE))
 				return -EINVAL;
 	}
 	/* Read the flags */
 	if (dwrq->flags & IW_ENCODE_DISABLED) {
 		priv->wep_is_on = 0;
 		priv->encryption_level = 0;
 		priv->pairwise_cipher_suite = CIPHER_SUITE_NONE;
 	} else {
 		priv->wep_is_on = 1;
 		if (priv->wep_key_len[priv->default_key] > 5) {
 			priv->pairwise_cipher_suite = CIPHER_SUITE_WEP_128;
 			priv->encryption_level = 2;
 		} else {
 			priv->pairwise_cipher_suite = CIPHER_SUITE_WEP_64;
 			priv->encryption_level = 1;
 		}
 	}
 	if (dwrq->flags & IW_ENCODE_RESTRICTED)
 		priv->exclude_unencrypted = 1;
 	if (dwrq->flags & IW_ENCODE_OPEN)
 		priv->exclude_unencrypted = 0;
 	return -EINPROGRESS;		/* Call commit handler */
 }
 static int atmel_get_encode(struct net_device *dev,
 			    struct iw_request_info *info,
 			    struct iw_point *dwrq,
 			    char *extra)
 {
 	struct atmel_private *priv = netdev_priv(dev);
 	int index = (dwrq->flags & IW_ENCODE_INDEX) - 1;
 	if (!priv->wep_is_on)
 		dwrq->flags = IW_ENCODE_DISABLED;
 	else {
 		if (priv->exclude_unencrypted)
 			dwrq->flags = IW_ENCODE_RESTRICTED;
 		else
 			dwrq->flags = IW_ENCODE_OPEN;
 	}
 		/* Which key do we want ? -1 -> tx index */
 	if (index < 0 || index >= 4)
 		index = priv->default_key;
 	dwrq->flags |= index + 1;
 	/* Copy the key to the user buffer */
 	dwrq->length = priv->wep_key_len[index];
 	if (dwrq->length > 16) {
 		dwrq->length = 0;
 	} else {
 		memset(extra, 0, 16);
 		memcpy(extra, priv->wep_keys[index], dwrq->length);
 	}
 	return 0;
 }
 static int atmel_set_encodeext(struct net_device *dev,
 			    struct iw_request_info *info,
 			    union iwreq_data *wrqu,
 			    char *extra)
 {
 	struct atmel_private *priv = netdev_priv(dev);
 	struct iw_point *encoding = &wrqu->encoding;
 	struct iw_encode_ext *ext = (struct iw_encode_ext *)extra;
 	int idx, key_len, alg = ext->alg, set_key = 1;
 	/* Determine and validate the key index */
 	idx = encoding->flags & IW_ENCODE_INDEX;
 	if (idx) {
 		if (idx < 1 || idx > 4)
 			return -EINVAL;
 		idx--;
 	} else
 		idx = priv->default_key;
 	if (encoding->flags & IW_ENCODE_DISABLED)
 	    alg = IW_ENCODE_ALG_NONE;
 	if (ext->ext_flags & IW_ENCODE_EXT_SET_TX_KEY) {
 		priv->default_key = idx;
 		set_key = ext->key_len > 0 ? 1 : 0;
 	}
 	if (set_key) {
 		/* Set the requested key first */
 		switch (alg) {
 		case IW_ENCODE_ALG_NONE:
 			priv->wep_is_on = 0;
 			priv->encryption_level = 0;
 			priv->pairwise_cipher_suite = CIPHER_SUITE_NONE;
 			break;
 		case IW_ENCODE_ALG_WEP:
 			if (ext->key_len > 5) {
 				priv->wep_key_len[idx] = 13;
 				priv->pairwise_cipher_suite = CIPHER_SUITE_WEP_128;
 				priv->encryption_level = 2;
 			} else if (ext->key_len > 0) {
 				priv->wep_key_len[idx] = 5;
 				priv->pairwise_cipher_suite = CIPHER_SUITE_WEP_64;
 				priv->encryption_level = 1;
 			} else {
 				return -EINVAL;
 			}
 			priv->wep_is_on = 1;
 			memset(priv->wep_keys[idx], 0, 13);
 			key_len = min ((int)ext->key_len, priv->wep_key_len[idx]);
 			memcpy(priv->wep_keys[idx], ext->key, key_len);
 			break;
 		default:
 			return -EINVAL;
 		}
 	}
 	return -EINPROGRESS;
 }
 static int atmel_get_encodeext(struct net_device *dev,
 			    struct iw_request_info *info,
 			    union iwreq_data *wrqu,
 			    char *extra)
 {
 	struct atmel_private *priv = netdev_priv(dev);
 	struct iw_point *encoding = &wrqu->encoding;
 	struct iw_encode_ext *ext = (struct iw_encode_ext *)extra;
 	int idx, max_key_len;
 	max_key_len = encoding->length - sizeof(*ext);
 	if (max_key_len < 0)
 		return -EINVAL;
 	idx = encoding->flags & IW_ENCODE_INDEX;
 	if (idx) {
 		if (idx < 1 || idx > 4)
 			return -EINVAL;
 		idx--;
 	} else
 		idx = priv->default_key;
 	encoding->flags = idx + 1;
 	memset(ext, 0, sizeof(*ext));
 	if (!priv->wep_is_on) {
 		ext->alg = IW_ENCODE_ALG_NONE;
 		ext->key_len = 0;
 		encoding->flags |= IW_ENCODE_DISABLED;
 	} else {
 		if (priv->encryption_level > 0)
 			ext->alg = IW_ENCODE_ALG_WEP;
 		else
 			return -EINVAL;
 		ext->key_len = priv->wep_key_len[idx];
 		memcpy(ext->key, priv->wep_keys[idx], ext->key_len);
 		encoding->flags |= IW_ENCODE_ENABLED;
 	}
 	return 0;
 }
 static int atmel_set_auth(struct net_device *dev,
 			       struct iw_request_info *info,
 			       union iwreq_data *wrqu, char *extra)
 {
 	struct atmel_private *priv = netdev_priv(dev);
 	struct iw_param *param = &wrqu->param;
 	switch (param->flags & IW_AUTH_INDEX) {
 	case IW_AUTH_WPA_VERSION:
 	case IW_AUTH_CIPHER_PAIRWISE:
 	case IW_AUTH_CIPHER_GROUP:
 	case IW_AUTH_KEY_MGMT:
 	case IW_AUTH_RX_UNENCRYPTED_EAPOL:
 	case IW_AUTH_PRIVACY_INVOKED:
 		/*
 		 * atmel does not use these parameters
 		 */
 		break;
 	case IW_AUTH_DROP_UNENCRYPTED:
 		priv->exclude_unencrypted = param->value ? 1 : 0;
 		break;
 	case IW_AUTH_80211_AUTH_ALG: {
 			if (param->value & IW_AUTH_ALG_SHARED_KEY) {
 				priv->exclude_unencrypted = 1;
 			} else if (param->value & IW_AUTH_ALG_OPEN_SYSTEM) {
 				priv->exclude_unencrypted = 0;
 			} else
 				return -EINVAL;
 			break;
 		}
 	case IW_AUTH_WPA_ENABLED:
 		/* Silently accept disable of WPA */
 		if (param->value > 0)
 			return -EOPNOTSUPP;
 		break;
 	default:
 		return -EOPNOTSUPP;
 	}
 	return -EINPROGRESS;
 }
 static int atmel_get_auth(struct net_device *dev,
 			       struct iw_request_info *info,
 			       union iwreq_data *wrqu, char *extra)
 {
 	struct atmel_private *priv = netdev_priv(dev);
 	struct iw_param *param = &wrqu->param;
 	switch (param->flags & IW_AUTH_INDEX) {
 	case IW_AUTH_DROP_UNENCRYPTED:
 		param->value = priv->exclude_unencrypted;
 		break;
 	case IW_AUTH_80211_AUTH_ALG:
 		if (priv->exclude_unencrypted == 1)
 			param->value = IW_AUTH_ALG_SHARED_KEY;
 		else
 			param->value = IW_AUTH_ALG_OPEN_SYSTEM;
 		break;
 	case IW_AUTH_WPA_ENABLED:
 		param->value = 0;
 		break;
 	default:
 		return -EOPNOTSUPP;
 	}
 	return 0;
 }
 static int atmel_get_name(struct net_device *dev,
 			  struct iw_request_info *info,
 			  char *cwrq,
 			  char *extra)
 {
 	strcpy(cwrq, "IEEE 802.11-DS");
 	return 0;
 }
 static int atmel_set_rate(struct net_device *dev,
 			  struct iw_request_info *info,
 			  struct iw_param *vwrq,
 			  char *extra)
 {
 	struct atmel_private *priv = netdev_priv(dev);
 	if (vwrq->fixed == 0) {
 		priv->tx_rate = 3;
 		priv->auto_tx_rate = 1;
 	} else {
 		priv->auto_tx_rate = 0;
 		/* Which type of value ? */
 		if ((vwrq->value < 4) && (vwrq->value >= 0)) {
 			/* Setting by rate index */
 			priv->tx_rate = vwrq->value;
 		} else {
 		/* Setting by frequency value */
 			switch (vwrq->value) {
 			case  1000000:
 				priv->tx_rate = 0;
 				break;
 			case  2000000:
 				priv->tx_rate = 1;
 				break;
 			case  5500000:
 				priv->tx_rate = 2;
 				break;
 			case 11000000:
 				priv->tx_rate = 3;
 				break;
 			default:
 				return -EINVAL;
 			}
 		}
 	}
 	return -EINPROGRESS;
 }
 static int atmel_set_mode(struct net_device *dev,
 			  struct iw_request_info *info,
 			  __u32 *uwrq,
 			  char *extra)
 {
 	struct atmel_private *priv = netdev_priv(dev);
 	if (*uwrq != IW_MODE_ADHOC && *uwrq != IW_MODE_INFRA)
 		return -EINVAL;
 	priv->operating_mode = *uwrq;
 	return -EINPROGRESS;
 }
 static int atmel_get_mode(struct net_device *dev,
 			  struct iw_request_info *info,
 			  __u32 *uwrq,
 			  char *extra)
 {
 	struct atmel_private *priv = netdev_priv(dev);
 	*uwrq = priv->operating_mode;
 	return 0;
 }
 static int atmel_get_rate(struct net_device *dev,
 			 struct iw_request_info *info,
 			 struct iw_param *vwrq,
 			 char *extra)
 {
 	struct atmel_private *priv = netdev_priv(dev);
 	if (priv->auto_tx_rate) {
 		vwrq->fixed = 0;
 		vwrq->value = 11000000;
 	} else {
 		vwrq->fixed = 1;
 		switch (priv->tx_rate) {
 		case 0:
 			vwrq->value =  1000000;
 			break;
 		case 1:
 			vwrq->value =  2000000;
 			break;
 		case 2:
 			vwrq->value =  5500000;
 			break;
 		case 3:
 			vwrq->value = 11000000;
 			break;
 		}
 	}
 	return 0;
 }
 static int atmel_set_power(struct net_device *dev,
 			   struct iw_request_info *info,
 			   struct iw_param *vwrq,
 			   char *extra)
 {
 	struct atmel_private *priv = netdev_priv(dev);
 	priv->power_mode = vwrq->disabled ? 0 : 1;
 	return -EINPROGRESS;
 }
 static int atmel_get_power(struct net_device *dev,
 			   struct iw_request_info *info,
 			   struct iw_param *vwrq,
 			   char *extra)
 {
 	struct atmel_private *priv = netdev_priv(dev);
 	vwrq->disabled = priv->power_mode ? 0 : 1;
 	vwrq->flags = IW_POWER_ON;
 	return 0;
 }
 static int atmel_set_retry(struct net_device *dev,
 			   struct iw_request_info *info,
 			   struct iw_param *vwrq,
 			   char *extra)
 {
 	struct atmel_private *priv = netdev_priv(dev);
 	if (!vwrq->disabled && (vwrq->flags & IW_RETRY_LIMIT)) {
 		if (vwrq->flags & IW_RETRY_LONG)
 			priv->long_retry = vwrq->value;
 		else if (vwrq->flags & IW_RETRY_SHORT)
 			priv->short_retry = vwrq->value;
 		else {
 			/* No modifier : set both */
 			priv->long_retry = vwrq->value;
 			priv->short_retry = vwrq->value;
 		}
 		return -EINPROGRESS;
 	}
 	return -EINVAL;
 }
 static int atmel_get_retry(struct net_device *dev,
 			   struct iw_request_info *info,
 			   struct iw_param *vwrq,
 			   char *extra)
 {
 	struct atmel_private *priv = netdev_priv(dev);
 	vwrq->disabled = 0;      /* Can't be disabled */
 	/* Note : by default, display the short retry number */
 	if (vwrq->flags & IW_RETRY_LONG) {
 		vwrq->flags = IW_RETRY_LIMIT | IW_RETRY_LONG;
 		vwrq->value = priv->long_retry;
 	} else {
 		vwrq->flags = IW_RETRY_LIMIT;
 		vwrq->value = priv->short_retry;
 		if (priv->long_retry != priv->short_retry)
 			vwrq->flags |= IW_RETRY_SHORT;
 	}
 	return 0;
 }
 static int atmel_set_rts(struct net_device *dev,
 			 struct iw_request_info *info,
 			 struct iw_param *vwrq,
 			 char *extra)
 {
 	struct atmel_private *priv = netdev_priv(dev);
 	int rthr = vwrq->value;
 	if (vwrq->disabled)
 		rthr = 2347;
 	if ((rthr < 0) || (rthr > 2347)) {
 		return -EINVAL;
 	}
 	priv->rts_threshold = rthr;
 	return -EINPROGRESS;		/* Call commit handler */
 }
 static int atmel_get_rts(struct net_device *dev,
 			 struct iw_request_info *info,
 			 struct iw_param *vwrq,
 			 char *extra)
 {
 	struct atmel_private *priv = netdev_priv(dev);
 	vwrq->value = priv->rts_threshold;
 	vwrq->disabled = (vwrq->value >= 2347);
 	vwrq->fixed = 1;
 	return 0;
 }
 static int atmel_set_frag(struct net_device *dev,
 			  struct iw_request_info *info,
 			  struct iw_param *vwrq,
 			  char *extra)
 {
 	struct atmel_private *priv = netdev_priv(dev);
 	int fthr = vwrq->value;
 	if (vwrq->disabled)
 		fthr = 2346;
 	if ((fthr < 256) || (fthr > 2346)) {
 		return -EINVAL;
 	}
 	fthr &= ~0x1;	/* Get an even value - is it really needed ??? */
 	priv->frag_threshold = fthr;
 	return -EINPROGRESS;		/* Call commit handler */
 }
 static int atmel_get_frag(struct net_device *dev,
 			  struct iw_request_info *info,
 			  struct iw_param *vwrq,
 			  char *extra)
 {
 	struct atmel_private *priv = netdev_priv(dev);
 	vwrq->value = priv->frag_threshold;
 	vwrq->disabled = (vwrq->value >= 2346);
 	vwrq->fixed = 1;
 	return 0;
 }
 static int atmel_set_freq(struct net_device *dev,
 			  struct iw_request_info *info,
 			  struct iw_freq *fwrq,
 			  char *extra)
 {
 	struct atmel_private *priv = netdev_priv(dev);
 	int rc = -EINPROGRESS;		/* Call commit handler */
 	/* If setting by frequency, convert to a channel */
 	if (fwrq->e == 1) {
 		int f = fwrq->m / 100000;
 		/* Hack to fall through... */
 		fwrq->e = 0;
 		fwrq->m = ieee80211_freq_to_dsss_chan(f);
 	}
 	/* Setting by channel number */
 	if ((fwrq->m > 1000) || (fwrq->e > 0))
 		rc = -EOPNOTSUPP;
 	else {
 		int channel = fwrq->m;
 		if (atmel_validate_channel(priv, channel) == 0) {
 			priv->channel = channel;
 		} else {
 			rc = -EINVAL;
 		}
 	}
 	return rc;
 }
 static int atmel_get_freq(struct net_device *dev,
 			  struct iw_request_info *info,
 			  struct iw_freq *fwrq,
 			  char *extra)
 {
 	struct atmel_private *priv = netdev_priv(dev);
 	fwrq->m = priv->channel;
 	fwrq->e = 0;
 	return 0;
 }
 static int atmel_set_scan(struct net_device *dev,
 			  struct iw_request_info *info,
 			  struct iw_point *dwrq,
 			  char *extra)
 {
 	struct atmel_private *priv = netdev_priv(dev);
 	unsigned long flags;
 	/* Note : you may have realised that, as this is a SET operation,
 	 * this is privileged and therefore a normal user can't
 	 * perform scanning.
 	 * This is not an error, while the device perform scanning,
 	 * traffic doesn't flow, so it's a perfect DoS...
 	 * Jean II */
 	if (priv->station_state == STATION_STATE_DOWN)
 		return -EAGAIN;
 	/* Timeout old surveys. */
 	if (time_after(jiffies, priv->last_survey + 20 * HZ))
 		priv->site_survey_state = SITE_SURVEY_IDLE;
 	priv->last_survey = jiffies;
 	/* Initiate a scan command */
 	if (priv->site_survey_state == SITE_SURVEY_IN_PROGRESS)
 		return -EBUSY;
 	del_timer_sync(&priv->management_timer);
 	spin_lock_irqsave(&priv->irqlock, flags);
 	priv->site_survey_state = SITE_SURVEY_IN_PROGRESS;
 	priv->fast_scan = 0;
 	atmel_scan(priv, 0);
 	spin_unlock_irqrestore(&priv->irqlock, flags);
 	return 0;
 }
 static int atmel_get_scan(struct net_device *dev,
 			  struct iw_request_info *info,
 			  struct iw_point *dwrq,
 			  char *extra)
 {
 	struct atmel_private *priv = netdev_priv(dev);
 	int i;
 	char *current_ev = extra;
 	struct iw_event	iwe;
 	if (priv->site_survey_state != SITE_SURVEY_COMPLETED)
 		return -EAGAIN;
 	for (i = 0; i < priv->BSS_list_entries; i++) {
 		iwe.cmd = SIOCGIWAP;
 		iwe.u.ap_addr.sa_family = ARPHRD_ETHER;
 		memcpy(iwe.u.ap_addr.sa_data, priv->BSSinfo[i].BSSID, 6);
 		current_ev = iwe_stream_add_event(info, current_ev,
 						  extra + IW_SCAN_MAX_DATA,
 						  &iwe, IW_EV_ADDR_LEN);
 		iwe.u.data.length =  priv->BSSinfo[i].SSIDsize;
 		if (iwe.u.data.length > 32)
 			iwe.u.data.length = 32;
 		iwe.cmd = SIOCGIWESSID;
 		iwe.u.data.flags = 1;
 		current_ev = iwe_stream_add_point(info, current_ev,
 						  extra + IW_SCAN_MAX_DATA,
 						  &iwe, priv->BSSinfo[i].SSID);
 		iwe.cmd = SIOCGIWMODE;
 		iwe.u.mode = priv->BSSinfo[i].BSStype;
 		current_ev = iwe_stream_add_event(info, current_ev,
 						  extra + IW_SCAN_MAX_DATA,
 						  &iwe, IW_EV_UINT_LEN);
 		iwe.cmd = SIOCGIWFREQ;
 		iwe.u.freq.m = priv->BSSinfo[i].channel;
 		iwe.u.freq.e = 0;
 		current_ev = iwe_stream_add_event(info, current_ev,
 						  extra + IW_SCAN_MAX_DATA,
 						  &iwe, IW_EV_FREQ_LEN);
 		/* Add quality statistics */
 		iwe.cmd = IWEVQUAL;
 		iwe.u.qual.level = priv->BSSinfo[i].RSSI;
 		iwe.u.qual.qual  = iwe.u.qual.level;
 		/* iwe.u.qual.noise  = SOMETHING */
 		current_ev = iwe_stream_add_event(info, current_ev,
 						  extra + IW_SCAN_MAX_DATA,
 						  &iwe, IW_EV_QUAL_LEN);
 		iwe.cmd = SIOCGIWENCODE;
 		if (priv->BSSinfo[i].UsingWEP)
 			iwe.u.data.flags = IW_ENCODE_ENABLED | IW_ENCODE_NOKEY;
 		else
 			iwe.u.data.flags = IW_ENCODE_DISABLED;
 		iwe.u.data.length = 0;
 		current_ev = iwe_stream_add_point(info, current_ev,
 						  extra + IW_SCAN_MAX_DATA,
 						  &iwe, NULL);
 	}
 	/* Length of data */
 	dwrq->length = (current_ev - extra);
 	dwrq->flags = 0;
 	return 0;
 }
 static int atmel_get_range(struct net_device *dev,
 			   struct iw_request_info *info,
 			   struct iw_point *dwrq,
 			   char *extra)
 {
 	struct atmel_private *priv = netdev_priv(dev);
 	struct iw_range *range = (struct iw_range *) extra;
 	int k, i, j;
 	dwrq->length = sizeof(struct iw_range);
 	memset(range, 0, sizeof(struct iw_range));
 	range->min_nwid = 0x0000;
 	range->max_nwid = 0x0000;
 	range->num_channels = 0;
 	for (j = 0; j < ARRAY_SIZE(channel_table); j++)
 		if (priv->reg_domain == channel_table[j].reg_domain) {
 			range->num_channels = channel_table[j].max - channel_table[j].min + 1;
 			break;
 		}
 	if (range->num_channels != 0) {
 		for (k = 0, i = channel_table[j].min; i <= channel_table[j].max; i++) {
 			range->freq[k].i = i; /* List index */
 			/* Values in MHz -> * 10^5 * 10 */
 			range->freq[k].m = (ieee80211_dsss_chan_to_freq(i) *
 					    100000);
 			range->freq[k++].e = 1;
 		}
 		range->num_frequency = k;
 	}
 	range->max_qual.qual = 100;
 	range->max_qual.level = 100;
 	range->max_qual.noise = 0;
 	range->max_qual.updated = IW_QUAL_NOISE_INVALID;
 	range->avg_qual.qual = 50;
 	range->avg_qual.level = 50;
 	range->avg_qual.noise = 0;
 	range->avg_qual.updated = IW_QUAL_NOISE_INVALID;
 	range->sensitivity = 0;
 	range->bitrate[0] =  1000000;
 	range->bitrate[1] =  2000000;
 	range->bitrate[2] =  5500000;
 	range->bitrate[3] = 11000000;
 	range->num_bitrates = 4;
 	range->min_rts = 0;
 	range->max_rts = 2347;
 	range->min_frag = 256;
 	range->max_frag = 2346;
 	range->encoding_size[0] = 5;
 	range->encoding_size[1] = 13;
 	range->num_encoding_sizes = 2;
 	range->max_encoding_tokens = 4;
 	range->pmp_flags = IW_POWER_ON;
 	range->pmt_flags = IW_POWER_ON;
 	range->pm_capa = 0;
 	range->we_version_source = WIRELESS_EXT;
 	range->we_version_compiled = WIRELESS_EXT;
 	range->retry_capa = IW_RETRY_LIMIT ;
 	range->retry_flags = IW_RETRY_LIMIT;
 	range->r_time_flags = 0;
 	range->min_retry = 1;
 	range->max_retry = 65535;
 	return 0;
 }
 static int atmel_set_wap(struct net_device *dev,
 			 struct iw_request_info *info,
 			 struct sockaddr *awrq,
 			 char *extra)
 {
 	struct atmel_private *priv = netdev_priv(dev);
 	int i;
 	static const u8 any[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
 	static const u8 off[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
 	unsigned long flags;
 	if (awrq->sa_family != ARPHRD_ETHER)
 		return -EINVAL;
 	if (!memcmp(any, awrq->sa_data, 6) ||
 	    !memcmp(off, awrq->sa_data, 6)) {
 		del_timer_sync(&priv->management_timer);
 		spin_lock_irqsave(&priv->irqlock, flags);
 		atmel_scan(priv, 1);
 		spin_unlock_irqrestore(&priv->irqlock, flags);
 		return 0;
 	}
 	for (i = 0; i < priv->BSS_list_entries; i++) {
 		if (memcmp(priv->BSSinfo[i].BSSID, awrq->sa_data, 6) == 0) {
 			if (!priv->wep_is_on && priv->BSSinfo[i].UsingWEP) {
 				return -EINVAL;
 			} else if  (priv->wep_is_on && !priv->BSSinfo[i].UsingWEP) {
 				return -EINVAL;
 			} else {
 				del_timer_sync(&priv->management_timer);
 				spin_lock_irqsave(&priv->irqlock, flags);
 				atmel_join_bss(priv, i);
 				spin_unlock_irqrestore(&priv->irqlock, flags);
 				return 0;
 			}
 		}
 	}
 	return -EINVAL;
 }
 static int atmel_config_commit(struct net_device *dev,
 			       struct iw_request_info *info,	/* NULL */
 			       void *zwrq,			/* NULL */
 			       char *extra)			/* NULL */
 {
 	return atmel_open(dev);
 }
 static const iw_handler atmel_handler[] =
 {
 	(iw_handler) atmel_config_commit,	/* SIOCSIWCOMMIT */
 	(iw_handler) atmel_get_name,		/* SIOCGIWNAME */
 	(iw_handler) NULL,			/* SIOCSIWNWID */
 	(iw_handler) NULL,			/* SIOCGIWNWID */
 	(iw_handler) atmel_set_freq,		/* SIOCSIWFREQ */
 	(iw_handler) atmel_get_freq,		/* SIOCGIWFREQ */
 	(iw_handler) atmel_set_mode,		/* SIOCSIWMODE */
 	(iw_handler) atmel_get_mode,		/* SIOCGIWMODE */
 	(iw_handler) NULL,			/* SIOCSIWSENS */
 	(iw_handler) NULL,			/* SIOCGIWSENS */
 	(iw_handler) NULL,			/* SIOCSIWRANGE */
 	(iw_handler) atmel_get_range,           /* SIOCGIWRANGE */
 	(iw_handler) NULL,			/* SIOCSIWPRIV */
 	(iw_handler) NULL,			/* SIOCGIWPRIV */
 	(iw_handler) NULL,			/* SIOCSIWSTATS */
 	(iw_handler) NULL,			/* SIOCGIWSTATS */
 	(iw_handler) NULL,			/* SIOCSIWSPY */
 	(iw_handler) NULL,			/* SIOCGIWSPY */
 	(iw_handler) NULL,			/* -- hole -- */
 	(iw_handler) NULL,			/* -- hole -- */
 	(iw_handler) atmel_set_wap,		/* SIOCSIWAP */
 	(iw_handler) atmel_get_wap,		/* SIOCGIWAP */
 	(iw_handler) NULL,			/* -- hole -- */
 	(iw_handler) NULL,			/* SIOCGIWAPLIST */
 	(iw_handler) atmel_set_scan,		/* SIOCSIWSCAN */
 	(iw_handler) atmel_get_scan,		/* SIOCGIWSCAN */
 	(iw_handler) atmel_set_essid,		/* SIOCSIWESSID */
 	(iw_handler) atmel_get_essid,		/* SIOCGIWESSID */
 	(iw_handler) NULL,			/* SIOCSIWNICKN */
 	(iw_handler) NULL,			/* SIOCGIWNICKN */
 	(iw_handler) NULL,			/* -- hole -- */
 	(iw_handler) NULL,			/* -- hole -- */
 	(iw_handler) atmel_set_rate,		/* SIOCSIWRATE */
 	(iw_handler) atmel_get_rate,		/* SIOCGIWRATE */
 	(iw_handler) atmel_set_rts,		/* SIOCSIWRTS */
 	(iw_handler) atmel_get_rts,		/* SIOCGIWRTS */
 	(iw_handler) atmel_set_frag,		/* SIOCSIWFRAG */
 	(iw_handler) atmel_get_frag,		/* SIOCGIWFRAG */
 	(iw_handler) NULL,			/* SIOCSIWTXPOW */
 	(iw_handler) NULL,			/* SIOCGIWTXPOW */
 	(iw_handler) atmel_set_retry,		/* SIOCSIWRETRY */
 	(iw_handler) atmel_get_retry,		/* SIOCGIWRETRY */
 	(iw_handler) atmel_set_encode,		/* SIOCSIWENCODE */
 	(iw_handler) atmel_get_encode,		/* SIOCGIWENCODE */
 	(iw_handler) atmel_set_power,		/* SIOCSIWPOWER */
 	(iw_handler) atmel_get_power,		/* SIOCGIWPOWER */
 	(iw_handler) NULL,			/* -- hole -- */
 	(iw_handler) NULL,			/* -- hole -- */
 	(iw_handler) NULL,			/* SIOCSIWGENIE */
 	(iw_handler) NULL,			/* SIOCGIWGENIE */
 	(iw_handler) atmel_set_auth,		/* SIOCSIWAUTH */
 	(iw_handler) atmel_get_auth,		/* SIOCGIWAUTH */
 	(iw_handler) atmel_set_encodeext,	/* SIOCSIWENCODEEXT */
 	(iw_handler) atmel_get_encodeext,	/* SIOCGIWENCODEEXT */
 	(iw_handler) NULL,			/* SIOCSIWPMKSA */
 };
 static const iw_handler atmel_private_handler[] =
 {
 	NULL,				/* SIOCIWFIRSTPRIV */
 };
 typedef struct atmel_priv_ioctl {
 	char id[32];
 	unsigned char __user *data;
 	unsigned short len;
 } atmel_priv_ioctl;
 #define ATMELFWL	SIOCIWFIRSTPRIV
 #define ATMELIDIFC	ATMELFWL + 1
 #define ATMELRD		ATMELFWL + 2
 #define ATMELMAGIC 0x51807
 #define REGDOMAINSZ 20
 static const struct iw_priv_args atmel_private_args[] = {
 	{
 		.cmd = ATMELFWL,
 		.set_args = IW_PRIV_TYPE_BYTE
 				| IW_PRIV_SIZE_FIXED
 				| sizeof (atmel_priv_ioctl),
 		.get_args = IW_PRIV_TYPE_NONE,
 		.name = "atmelfwl"
 	}, {
 		.cmd = ATMELIDIFC,
 		.set_args = IW_PRIV_TYPE_NONE,
 		.get_args = IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
 		.name = "atmelidifc"
 	}, {
 		.cmd = ATMELRD,
 		.set_args = IW_PRIV_TYPE_CHAR | REGDOMAINSZ,
 		.get_args = IW_PRIV_TYPE_NONE,
 		.name = "regdomain"
 	},
 };
 static const struct iw_handler_def atmel_handler_def = {
 	.num_standard	= ARRAY_SIZE(atmel_handler),
 	.num_private	= ARRAY_SIZE(atmel_private_handler),
 	.num_private_args = ARRAY_SIZE(atmel_private_args),
 	.standard	= (iw_handler *) atmel_handler,
 	.private	= (iw_handler *) atmel_private_handler,
 	.private_args	= (struct iw_priv_args *) atmel_private_args,
 	.get_wireless_stats = atmel_get_wireless_stats
 };
 static int atmel_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 {
 	int i, rc = 0;
 	struct atmel_private *priv = netdev_priv(dev);
 	atmel_priv_ioctl com;
 	struct iwreq *wrq = (struct iwreq *) rq;
 	unsigned char *new_firmware;
 	char domain[REGDOMAINSZ + 1];
 	switch (cmd) {
 	case ATMELIDIFC:
 		wrq->u.param.value = ATMELMAGIC;
 		break;
 	case ATMELFWL:
 		if (copy_from_user(&com, rq->ifr_data, sizeof(com))) {
 			rc = -EFAULT;
 			break;
 		}
 		if (!capable(CAP_NET_ADMIN)) {
 			rc = -EPERM;
 			break;
 		}
 		if (!(new_firmware = kmalloc(com.len, GFP_KERNEL))) {
 			rc = -ENOMEM;
 			break;
 		}
 		if (copy_from_user(new_firmware, com.data, com.len)) {
 			kfree(new_firmware);
 			rc = -EFAULT;
 			break;
 		}
 		kfree(priv->firmware);
 		priv->firmware = new_firmware;
 		priv->firmware_length = com.len;
 		strncpy(priv->firmware_id, com.id, 31);
 		priv->firmware_id[31] = '\0';
 		break;
 	case ATMELRD:
 		if (copy_from_user(domain, rq->ifr_data, REGDOMAINSZ)) {
 			rc = -EFAULT;
 			break;
 		}
 		if (!capable(CAP_NET_ADMIN)) {
 			rc = -EPERM;
 			break;
 		}
 		domain[REGDOMAINSZ] = 0;
 		rc = -EINVAL;
 		for (i = 0; i < ARRAY_SIZE(channel_table); i++) {
 			/* strcasecmp doesn't exist in the library */
 			char *a = channel_table[i].name;
 			char *b = domain;
 			while (*a) {
 				char c1 = *a++;
 				char c2 = *b++;
 				if (tolower(c1) != tolower(c2))
 					break;
 			}
 			if (!*a && !*b) {
 				priv->config_reg_domain = channel_table[i].reg_domain;
 				rc = 0;
 			}
 		}
 		if (rc == 0 &&  priv->station_state != STATION_STATE_DOWN)
 			rc = atmel_open(dev);
 		break;
 	default:
 		rc = -EOPNOTSUPP;
 	}
 	return rc;
 }
 struct auth_body {
 	__le16 alg;
 	__le16 trans_seq;
 	__le16 status;
 	u8 el_id;
 	u8 chall_text_len;
 	u8 chall_text[253];
 };
 static void atmel_enter_state(struct atmel_private *priv, int new_state)
 {
 	int old_state = priv->station_state;
 	if (new_state == old_state)
 		return;
 	priv->station_state = new_state;
 	if (new_state == STATION_STATE_READY) {
 		netif_start_queue(priv->dev);
 		netif_carrier_on(priv->dev);
 	}
 	if (old_state == STATION_STATE_READY) {
 		netif_carrier_off(priv->dev);
 		if (netif_running(priv->dev))
 			netif_stop_queue(priv->dev);
 		priv->last_beacon_timestamp = 0;
 	}
 }
 static void atmel_scan(struct atmel_private *priv, int specific_ssid)
 {
 	struct {
 		u8 BSSID[6];
 		u8 SSID[MAX_SSID_LENGTH];
 		u8 scan_type;
 		u8 channel;
 		__le16 BSS_type;
 		__le16 min_channel_time;
 		__le16 max_channel_time;
 		u8 options;
 		u8 SSID_size;
 	} cmd;
 	memset(cmd.BSSID, 0xff, 6);
 	if (priv->fast_scan) {
 		cmd.SSID_size = priv->SSID_size;
 		memcpy(cmd.SSID, priv->SSID, priv->SSID_size);
 		cmd.min_channel_time = cpu_to_le16(10);
 		cmd.max_channel_time = cpu_to_le16(50);
 	} else {
 		priv->BSS_list_entries = 0;
 		cmd.SSID_size = 0;
 		cmd.min_channel_time = cpu_to_le16(10);
 		cmd.max_channel_time = cpu_to_le16(120);
 	}
 	cmd.options = 0;
 	if (!specific_ssid)
 		cmd.options |= SCAN_OPTIONS_SITE_SURVEY;
 	cmd.channel = (priv->channel & 0x7f);
 	cmd.scan_type = SCAN_TYPE_ACTIVE;
 	cmd.BSS_type = cpu_to_le16(priv->operating_mode == IW_MODE_ADHOC ?
 		BSS_TYPE_AD_HOC : BSS_TYPE_INFRASTRUCTURE);
 	atmel_send_command(priv, CMD_Scan, &cmd, sizeof(cmd));
 	/* This must come after all hardware access to avoid being messed up
 	   by stuff happening in interrupt context after we leave STATE_DOWN */
 	atmel_enter_state(priv, STATION_STATE_SCANNING);
 }
 static void join(struct atmel_private *priv, int type)
 {
 	struct {
 		u8 BSSID[6];
 		u8 SSID[MAX_SSID_LENGTH];
 		u8 BSS_type; /* this is a short in a scan command - weird */
 		u8 channel;
 		__le16 timeout;
 		u8 SSID_size;
 		u8 reserved;
 	} cmd;
 	cmd.SSID_size = priv->SSID_size;
 	memcpy(cmd.SSID, priv->SSID, priv->SSID_size);
 	memcpy(cmd.BSSID, priv->CurrentBSSID, 6);
 	cmd.channel = (priv->channel & 0x7f);
 	cmd.BSS_type = type;
 	cmd.timeout = cpu_to_le16(2000);
 	atmel_send_command(priv, CMD_Join, &cmd, sizeof(cmd));
 }
 static void start(struct atmel_private *priv, int type)
 {
 	struct {
 		u8 BSSID[6];
 		u8 SSID[MAX_SSID_LENGTH];
 		u8 BSS_type;
 		u8 channel;
 		u8 SSID_size;
 		u8 reserved[3];
 	} cmd;
 	cmd.SSID_size = priv->SSID_size;
 	memcpy(cmd.SSID, priv->SSID, priv->SSID_size);
 	memcpy(cmd.BSSID, priv->BSSID, 6);
 	cmd.BSS_type = type;
 	cmd.channel = (priv->channel & 0x7f);
 	atmel_send_command(priv, CMD_Start, &cmd, sizeof(cmd));
 }
 static void handle_beacon_probe(struct atmel_private *priv, u16 capability,
 				u8 channel)
 {
 	int rejoin = 0;
 	int new = capability & WLAN_CAPABILITY_SHORT_PREAMBLE ?
 		SHORT_PREAMBLE : LONG_PREAMBLE;
 	if (priv->preamble != new) {
 		priv->preamble = new;
 		rejoin = 1;
 		atmel_set_mib8(priv, Local_Mib_Type, LOCAL_MIB_PREAMBLE_TYPE, new);
 	}
 	if (priv->channel != channel) {
 		priv->channel = channel;
 		rejoin = 1;
 		atmel_set_mib8(priv, Phy_Mib_Type, PHY_MIB_CHANNEL_POS, channel);
 	}
 	if (rejoin) {
 		priv->station_is_associated = 0;
 		atmel_enter_state(priv, STATION_STATE_JOINNING);
 		if (priv->operating_mode == IW_MODE_INFRA)
 			join(priv, BSS_TYPE_INFRASTRUCTURE);
 		else
 			join(priv, BSS_TYPE_AD_HOC);
 	}
 }
 static void send_authentication_request(struct atmel_private *priv, u16 system,
 					u8 *challenge, int challenge_len)
 {
 	struct ieee80211_hdr header;
 	struct auth_body auth;
 	header.frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT | IEEE80211_STYPE_AUTH);
 	header.duration_id = cpu_to_le16(0x8000);
 	header.seq_ctrl = 0;
 	memcpy(header.addr1, priv->CurrentBSSID, 6);
 	memcpy(header.addr2, priv->dev->dev_addr, 6);
 	memcpy(header.addr3, priv->CurrentBSSID, 6);
 	if (priv->wep_is_on && priv->CurrentAuthentTransactionSeqNum != 1)
 		/* no WEP for authentication frames with TrSeqNo 1 */
 		header.frame_control |=  cpu_to_le16(IEEE80211_FCTL_PROTECTED);
 	auth.alg = cpu_to_le16(system);
 	auth.status = 0;
 	auth.trans_seq = cpu_to_le16(priv->CurrentAuthentTransactionSeqNum);
 	priv->ExpectedAuthentTransactionSeqNum = priv->CurrentAuthentTransactionSeqNum+1;
 	priv->CurrentAuthentTransactionSeqNum += 2;
 	if (challenge_len != 0)	{
 		auth.el_id = 16; /* challenge_text */
 		auth.chall_text_len = challenge_len;
 		memcpy(auth.chall_text, challenge, challenge_len);
 		atmel_transmit_management_frame(priv, &header, (u8 *)&auth, 8 + challenge_len);
 	} else {
 		atmel_transmit_management_frame(priv, &header, (u8 *)&auth, 6);
 	}
 }
 static void send_association_request(struct atmel_private *priv, int is_reassoc)
 {
 	u8 *ssid_el_p;
 	int bodysize;
 	struct ieee80211_hdr header;
 	struct ass_req_format {
 		__le16 capability;
 		__le16 listen_interval;
 		u8 ap[6]; /* nothing after here directly accessible */
 		u8 ssid_el_id;
 		u8 ssid_len;
 		u8 ssid[MAX_SSID_LENGTH];
 		u8 sup_rates_el_id;
 		u8 sup_rates_len;
 		u8 rates[4];
 	} body;
 	header.frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
 		(is_reassoc ? IEEE80211_STYPE_REASSOC_REQ : IEEE80211_STYPE_ASSOC_REQ));
 	header.duration_id = cpu_to_le16(0x8000);
 	header.seq_ctrl = 0;
 	memcpy(header.addr1, priv->CurrentBSSID, 6);
 	memcpy(header.addr2, priv->dev->dev_addr, 6);
 	memcpy(header.addr3, priv->CurrentBSSID, 6);
 	body.capability = cpu_to_le16(WLAN_CAPABILITY_ESS);
 	if (priv->wep_is_on)
 		body.capability |= cpu_to_le16(WLAN_CAPABILITY_PRIVACY);
 	if (priv->preamble == SHORT_PREAMBLE)
 		body.capability |= cpu_to_le16(WLAN_CAPABILITY_SHORT_PREAMBLE);
 	body.listen_interval = cpu_to_le16(priv->listen_interval * priv->beacon_period);
 	/* current AP address - only in reassoc frame */
 	if (is_reassoc) {
 		memcpy(body.ap, priv->CurrentBSSID, 6);
 		ssid_el_p = (u8 *)&body.ssid_el_id;
 		bodysize = 18 + priv->SSID_size;
 	} else {
 		ssid_el_p = (u8 *)&body.ap[0];
 		bodysize = 12 + priv->SSID_size;
 	}
 	ssid_el_p[0] = WLAN_EID_SSID;
 	ssid_el_p[1] = priv->SSID_size;
 	memcpy(ssid_el_p + 2, priv->SSID, priv->SSID_size);
 	ssid_el_p[2 + priv->SSID_size] = WLAN_EID_SUPP_RATES;
 	ssid_el_p[3 + priv->SSID_size] = 4; /* len of suported rates */
 	memcpy(ssid_el_p + 4 + priv->SSID_size, atmel_basic_rates, 4);
 	atmel_transmit_management_frame(priv, &header, (void *)&body, bodysize);
 }
 static int is_frame_from_current_bss(struct atmel_private *priv,
 				     struct ieee80211_hdr *header)
 {
 	if (le16_to_cpu(header->frame_control) & IEEE80211_FCTL_FROMDS)
 		return memcmp(header->addr3, priv->CurrentBSSID, 6) == 0;
 	else
 		return memcmp(header->addr2, priv->CurrentBSSID, 6) == 0;
 }
 static int retrieve_bss(struct atmel_private *priv)
 {
 	int i;
 	int max_rssi = -128;
 	int max_index = -1;
 	if (priv->BSS_list_entries == 0)
 		return -1;
 	if (priv->connect_to_any_BSS) {
 		/* Select a BSS with the max-RSSI but of the same type and of
 		   the same WEP mode and that it is not marked as 'bad' (i.e.
 		   we had previously failed to connect to this BSS with the
 		   settings that we currently use) */
 		priv->current_BSS = 0;
 		for (i = 0; i < priv->BSS_list_entries; i++) {
 			if (priv->operating_mode == priv->BSSinfo[i].BSStype &&
 			    ((!priv->wep_is_on && !priv->BSSinfo[i].UsingWEP) ||
 			     (priv->wep_is_on && priv->BSSinfo[i].UsingWEP)) &&
 			    !(priv->BSSinfo[i].channel & 0x80)) {
 				max_rssi = priv->BSSinfo[i].RSSI;
 				priv->current_BSS = max_index = i;
 			}
 		}
 		return max_index;
 	}
 	for (i = 0; i < priv->BSS_list_entries; i++) {
 		if (priv->SSID_size == priv->BSSinfo[i].SSIDsize &&
 		    memcmp(priv->SSID, priv->BSSinfo[i].SSID, priv->SSID_size) == 0 &&
 		    priv->operating_mode == priv->BSSinfo[i].BSStype &&
 		    atmel_validate_channel(priv, priv->BSSinfo[i].channel) == 0) {
 			if (priv->BSSinfo[i].RSSI >= max_rssi) {
 				max_rssi = priv->BSSinfo[i].RSSI;
 				max_index = i;
 			}
 		}
 	}
 	return max_index;
 }
 static void store_bss_info(struct atmel_private *priv,
 			   struct ieee80211_hdr *header, u16 capability,
 			   u16 beacon_period, u8 channel, u8 rssi, u8 ssid_len,
 			   u8 *ssid, int is_beacon)
 {
 	u8 *bss = capability & WLAN_CAPABILITY_ESS ? header->addr2 : header->addr3;
 	int i, index;
 	for (index = -1, i = 0; i < priv->BSS_list_entries; i++)
 		if (memcmp(bss, priv->BSSinfo[i].BSSID, 6) == 0)
 			index = i;
 	/* If we process a probe and an entry from this BSS exists
 	   we will update the BSS entry with the info from this BSS.
 	   If we process a beacon we will only update RSSI */
 	if (index == -1) {
 		if (priv->BSS_list_entries == MAX_BSS_ENTRIES)
 			return;
 		index = priv->BSS_list_entries++;
 		memcpy(priv->BSSinfo[index].BSSID, bss, 6);
 		priv->BSSinfo[index].RSSI = rssi;
 	} else {
 		if (rssi > priv->BSSinfo[index].RSSI)
 			priv->BSSinfo[index].RSSI = rssi;
 		if (is_beacon)
 			return;
 	}
 	priv->BSSinfo[index].channel = channel;
 	priv->BSSinfo[index].beacon_period = beacon_period;
 	priv->BSSinfo[index].UsingWEP = capability & WLAN_CAPABILITY_PRIVACY;
 	memcpy(priv->BSSinfo[index].SSID, ssid, ssid_len);
 	priv->BSSinfo[index].SSIDsize = ssid_len;
 	if (capability & WLAN_CAPABILITY_IBSS)
 		priv->BSSinfo[index].BSStype = IW_MODE_ADHOC;
 	else if (capability & WLAN_CAPABILITY_ESS)
 		priv->BSSinfo[index].BSStype = IW_MODE_INFRA;
 	priv->BSSinfo[index].preamble = capability & WLAN_CAPABILITY_SHORT_PREAMBLE ?
 		SHORT_PREAMBLE : LONG_PREAMBLE;
 }
 static void authenticate(struct atmel_private *priv, u16 frame_len)
 {
 	struct auth_body *auth = (struct auth_body *)priv->rx_buf;
 	u16 status = le16_to_cpu(auth->status);
 	u16 trans_seq_no = le16_to_cpu(auth->trans_seq);
 	u16 system = le16_to_cpu(auth->alg);
 	if (status == WLAN_STATUS_SUCCESS && !priv->wep_is_on) {
 		/* no WEP */
 		if (priv->station_was_associated) {
 			atmel_enter_state(priv, STATION_STATE_REASSOCIATING);
 			send_association_request(priv, 1);
 			return;
 		} else {
 			atmel_enter_state(priv, STATION_STATE_ASSOCIATING);
 			send_association_request(priv, 0);
 			return;
 		}
 	}
 	if (status == WLAN_STATUS_SUCCESS && priv->wep_is_on) {
 		int should_associate = 0;
 		/* WEP */
 		if (trans_seq_no != priv->ExpectedAuthentTransactionSeqNum)
 			return;
 		if (system == WLAN_AUTH_OPEN) {
 			if (trans_seq_no == 0x0002) {
 				should_associate = 1;
 			}
 		} else if (system == WLAN_AUTH_SHARED_KEY) {
 			if (trans_seq_no == 0x0002 &&
 			    auth->el_id == WLAN_EID_CHALLENGE) {
 				send_authentication_request(priv, system, auth->chall_text, auth->chall_text_len);
 				return;
 			} else if (trans_seq_no == 0x0004) {
 				should_associate = 1;
 			}
 		}
 		if (should_associate) {
 			if (priv->station_was_associated) {
 				atmel_enter_state(priv, STATION_STATE_REASSOCIATING);
 				send_association_request(priv, 1);
 				return;
 			} else {
 				atmel_enter_state(priv, STATION_STATE_ASSOCIATING);
 				send_association_request(priv, 0);
 				return;
 			}
 		}
 	}
 	if (status == WLAN_STATUS_NOT_SUPPORTED_AUTH_ALG) {
 		/* Flip back and forth between WEP auth modes until the max
 		 * authentication tries has been exceeded.
 		 */
 		if (system == WLAN_AUTH_OPEN) {
 			priv->CurrentAuthentTransactionSeqNum = 0x001;
 			priv->exclude_unencrypted = 1;
 			send_authentication_request(priv, WLAN_AUTH_SHARED_KEY, NULL, 0);
 			return;
 		} else if (system == WLAN_AUTH_SHARED_KEY
 			   && priv->wep_is_on) {
 			priv->CurrentAuthentTransactionSeqNum = 0x001;
 			priv->exclude_unencrypted = 0;
 			send_authentication_request(priv, WLAN_AUTH_OPEN, NULL, 0);
 			return;
 		} else if (priv->connect_to_any_BSS) {
 			int bss_index;
 			priv->BSSinfo[(int)(priv->current_BSS)].channel |= 0x80;
 			if ((bss_index  = retrieve_bss(priv)) != -1) {
 				atmel_join_bss(priv, bss_index);
 				return;
 			}
 		}
 	}
 	priv->AuthenticationRequestRetryCnt = 0;
 	atmel_enter_state(priv,  STATION_STATE_MGMT_ERROR);
 	priv->station_is_associated = 0;
 }
 static void associate(struct atmel_private *priv, u16 frame_len, u16 subtype)
 {
 	struct ass_resp_format {
 		__le16 capability;
 		__le16 status;
 		__le16 ass_id;
 		u8 el_id;
 		u8 length;
 		u8 rates[4];
 	} *ass_resp = (struct ass_resp_format *)priv->rx_buf;
 	u16 status = le16_to_cpu(ass_resp->status);
 	u16 ass_id = le16_to_cpu(ass_resp->ass_id);
 	u16 rates_len = ass_resp->length > 4 ? 4 : ass_resp->length;
 	union iwreq_data wrqu;
 	if (frame_len < 8 + rates_len)
 		return;
 	if (status == WLAN_STATUS_SUCCESS) {
 		if (subtype == IEEE80211_STYPE_ASSOC_RESP)
 			priv->AssociationRequestRetryCnt = 0;
 		else
 			priv->ReAssociationRequestRetryCnt = 0;
 		atmel_set_mib16(priv, Mac_Mgmt_Mib_Type,
 				MAC_MGMT_MIB_STATION_ID_POS, ass_id & 0x3fff);
 		atmel_set_mib(priv, Phy_Mib_Type,
 			      PHY_MIB_RATE_SET_POS, ass_resp->rates, rates_len);
 		if (priv->power_mode == 0) {
 			priv->listen_interval = 1;
 			atmel_set_mib8(priv, Mac_Mgmt_Mib_Type,
 				       MAC_MGMT_MIB_PS_MODE_POS, ACTIVE_MODE);
 			atmel_set_mib16(priv, Mac_Mgmt_Mib_Type,
 					MAC_MGMT_MIB_LISTEN_INTERVAL_POS, 1);
 		} else {
 			priv->listen_interval = 2;
 			atmel_set_mib8(priv, Mac_Mgmt_Mib_Type,
 				       MAC_MGMT_MIB_PS_MODE_POS,  PS_MODE);
 			atmel_set_mib16(priv, Mac_Mgmt_Mib_Type,
 					MAC_MGMT_MIB_LISTEN_INTERVAL_POS, 2);
 		}
 		priv->station_is_associated = 1;
 		priv->station_was_associated = 1;
 		atmel_enter_state(priv, STATION_STATE_READY);
 		/* Send association event to userspace */
 		wrqu.data.length = 0;
 		wrqu.data.flags = 0;
 		memcpy(wrqu.ap_addr.sa_data, priv->CurrentBSSID, ETH_ALEN);
 		wrqu.ap_addr.sa_family = ARPHRD_ETHER;
 		wireless_send_event(priv->dev, SIOCGIWAP, &wrqu, NULL);
 		return;
 	}
 	if (subtype == IEEE80211_STYPE_ASSOC_RESP &&
 	    status != WLAN_STATUS_ASSOC_DENIED_RATES &&
 	    status != WLAN_STATUS_CAPS_UNSUPPORTED &&
 	    priv->AssociationRequestRetryCnt < MAX_ASSOCIATION_RETRIES) {
 		mod_timer(&priv->management_timer, jiffies + MGMT_JIFFIES);
 		priv->AssociationRequestRetryCnt++;
 		send_association_request(priv, 0);
 		return;
 	}
 	if (subtype == IEEE80211_STYPE_REASSOC_RESP &&
 	    status != WLAN_STATUS_ASSOC_DENIED_RATES &&
 	    status != WLAN_STATUS_CAPS_UNSUPPORTED &&
 	    priv->AssociationRequestRetryCnt < MAX_ASSOCIATION_RETRIES) {
 		mod_timer(&priv->management_timer, jiffies + MGMT_JIFFIES);
 		priv->ReAssociationRequestRetryCnt++;
 		send_association_request(priv, 1);
 		return;
 	}
 	atmel_enter_state(priv,  STATION_STATE_MGMT_ERROR);
 	priv->station_is_associated = 0;
 	if (priv->connect_to_any_BSS) {
 		int bss_index;
 		priv->BSSinfo[(int)(priv->current_BSS)].channel |= 0x80;
 		if ((bss_index = retrieve_bss(priv)) != -1)
 			atmel_join_bss(priv, bss_index);
 	}
 }
 static void atmel_join_bss(struct atmel_private *priv, int bss_index)
 {
 	struct bss_info *bss =  &priv->BSSinfo[bss_index];
 	memcpy(priv->CurrentBSSID, bss->BSSID, 6);
 	memcpy(priv->SSID, bss->SSID, priv->SSID_size = bss->SSIDsize);
 	/* The WPA stuff cares about the current AP address */
 	if (priv->use_wpa)
 		build_wpa_mib(priv);
 	/* When switching to AdHoc turn OFF Power Save if needed */
 	if (bss->BSStype == IW_MODE_ADHOC &&
 	    priv->operating_mode != IW_MODE_ADHOC &&
 	    priv->power_mode) {
 		priv->power_mode = 0;
 		priv->listen_interval = 1;
 		atmel_set_mib8(priv, Mac_Mgmt_Mib_Type,
 			       MAC_MGMT_MIB_PS_MODE_POS,  ACTIVE_MODE);
 		atmel_set_mib16(priv, Mac_Mgmt_Mib_Type,
 				MAC_MGMT_MIB_LISTEN_INTERVAL_POS, 1);
 	}
 	priv->operating_mode = bss->BSStype;
 	priv->channel = bss->channel & 0x7f;
 	priv->beacon_period = bss->beacon_period;
 	if (priv->preamble != bss->preamble) {
 		priv->preamble = bss->preamble;
 		atmel_set_mib8(priv, Local_Mib_Type,
 			       LOCAL_MIB_PREAMBLE_TYPE, bss->preamble);
 	}
 	if (!priv->wep_is_on && bss->UsingWEP) {
 		atmel_enter_state(priv, STATION_STATE_MGMT_ERROR);
 		priv->station_is_associated = 0;
 		return;
 	}
 	if (priv->wep_is_on && !bss->UsingWEP) {
 		atmel_enter_state(priv, STATION_STATE_MGMT_ERROR);
 		priv->station_is_associated = 0;
 		return;
 	}
 	atmel_enter_state(priv, STATION_STATE_JOINNING);
 	if (priv->operating_mode == IW_MODE_INFRA)
 		join(priv, BSS_TYPE_INFRASTRUCTURE);
 	else
 		join(priv, BSS_TYPE_AD_HOC);
 }
 static void restart_search(struct atmel_private *priv)
 {
 	int bss_index;
 	if (!priv->connect_to_any_BSS) {
 		atmel_scan(priv, 1);
 	} else {
 		priv->BSSinfo[(int)(priv->current_BSS)].channel |= 0x80;
 		if ((bss_index = retrieve_bss(priv)) != -1)
 			atmel_join_bss(priv, bss_index);
 		else
 			atmel_scan(priv, 0);
 	}
 }
 static void smooth_rssi(struct atmel_private *priv, u8 rssi)
 {
 	u8 old = priv->wstats.qual.level;
 	u8 max_rssi = 42; /* 502-rmfd-revd max by experiment, default for now */
 	switch (priv->firmware_type) {
 	case ATMEL_FW_TYPE_502E:
 		max_rssi = 63; /* 502-rmfd-reve max by experiment */
 		break;
 	default:
 		break;
 	}
 	rssi = rssi * 100 / max_rssi;
 	if ((rssi + old) % 2)
 		priv->wstats.qual.level = (rssi + old) / 2 + 1;
 	else
 		priv->wstats.qual.level = (rssi + old) / 2;
 	priv->wstats.qual.updated |= IW_QUAL_LEVEL_UPDATED;
 	priv->wstats.qual.updated &= ~IW_QUAL_LEVEL_INVALID;
 }
 static void atmel_smooth_qual(struct atmel_private *priv)
 {
 	unsigned long time_diff = (jiffies - priv->last_qual) / HZ;
 	while (time_diff--) {
 		priv->last_qual += HZ;
 		priv->wstats.qual.qual = priv->wstats.qual.qual / 2;
 		priv->wstats.qual.qual +=
 			priv->beacons_this_sec * priv->beacon_period * (priv->wstats.qual.level + 100) / 4000;
 		priv->beacons_this_sec = 0;
 	}
 	priv->wstats.qual.updated |= IW_QUAL_QUAL_UPDATED;
 	priv->wstats.qual.updated &= ~IW_QUAL_QUAL_INVALID;
 }
-/* deals with incoming managment frames. */
+/* deals with incoming management frames. */
 static void atmel_management_frame(struct atmel_private *priv,
 				   struct ieee80211_hdr *header,
 				   u16 frame_len, u8 rssi)
 {
 	u16 subtype;
 	subtype = le16_to_cpu(header->frame_control) & IEEE80211_FCTL_STYPE;
 	switch (subtype) {
 	case IEEE80211_STYPE_BEACON:
 	case IEEE80211_STYPE_PROBE_RESP:
 		/* beacon frame has multiple variable-length fields -
 		   never let an engineer loose with a data structure design. */
 		{
 			struct beacon_format {
 				__le64 timestamp;
 				__le16 interval;
 				__le16 capability;
 				u8 ssid_el_id;
 				u8 ssid_length;
 				/* ssid here */
 				u8 rates_el_id;
 				u8 rates_length;
 				/* rates here */
 				u8 ds_el_id;
 				u8 ds_length;
 				/* ds here */
 			} *beacon = (struct beacon_format *)priv->rx_buf;
 			u8 channel, rates_length, ssid_length;
 			u64 timestamp = le64_to_cpu(beacon->timestamp);
 			u16 beacon_interval = le16_to_cpu(beacon->interval);
 			u16 capability = le16_to_cpu(beacon->capability);
 			u8 *beaconp = priv->rx_buf;
 			ssid_length = beacon->ssid_length;
 			/* this blows chunks. */
 			if (frame_len < 14 || frame_len < ssid_length + 15)
 				return;
 			rates_length = beaconp[beacon->ssid_length + 15];
 			if (frame_len < ssid_length + rates_length + 18)
 				return;
 			if (ssid_length >  MAX_SSID_LENGTH)
 				return;
 			channel = beaconp[ssid_length + rates_length + 18];
 			if (priv->station_state == STATION_STATE_READY) {
 				smooth_rssi(priv, rssi);
 				if (is_frame_from_current_bss(priv, header)) {
 					priv->beacons_this_sec++;
 					atmel_smooth_qual(priv);
 					if (priv->last_beacon_timestamp) {
 						/* Note truncate this to 32 bits - kernel can't divide a long long */
 						u32 beacon_delay = timestamp - priv->last_beacon_timestamp;
 						int beacons = beacon_delay / (beacon_interval * 1000);
 						if (beacons > 1)
 							priv->wstats.miss.beacon += beacons - 1;
 					}
 					priv->last_beacon_timestamp = timestamp;
 					handle_beacon_probe(priv, capability, channel);
 				}
 			}
 			if (priv->station_state == STATION_STATE_SCANNING)
 				store_bss_info(priv, header, capability,
 					       beacon_interval, channel, rssi,
 					       ssid_length,
 					       &beacon->rates_el_id,
 					       subtype == IEEE80211_STYPE_BEACON);
 		}
 		break;
 	case IEEE80211_STYPE_AUTH:
 		if (priv->station_state == STATION_STATE_AUTHENTICATING)
 			authenticate(priv, frame_len);
 		break;
 	case IEEE80211_STYPE_ASSOC_RESP:
 	case IEEE80211_STYPE_REASSOC_RESP:
 		if (priv->station_state == STATION_STATE_ASSOCIATING ||
 		    priv->station_state == STATION_STATE_REASSOCIATING)
 			associate(priv, frame_len, subtype);
 		break;
 	case IEEE80211_STYPE_DISASSOC:
 		if (priv->station_is_associated &&
 		    priv->operating_mode == IW_MODE_INFRA &&
 		    is_frame_from_current_bss(priv, header)) {
 			priv->station_was_associated = 0;
 			priv->station_is_associated = 0;
 			atmel_enter_state(priv, STATION_STATE_JOINNING);
 			join(priv, BSS_TYPE_INFRASTRUCTURE);
 		}
 		break;
 	case IEEE80211_STYPE_DEAUTH:
 		if (priv->operating_mode == IW_MODE_INFRA &&
 		    is_frame_from_current_bss(priv, header)) {
 			priv->station_was_associated = 0;
 			atmel_enter_state(priv, STATION_STATE_JOINNING);
 			join(priv, BSS_TYPE_INFRASTRUCTURE);
 		}
 		break;
 	}
 }
 /* run when timer expires */
 static void atmel_management_timer(u_long a)
 {
 	struct net_device *dev = (struct net_device *) a;
 	struct atmel_private *priv = netdev_priv(dev);
 	unsigned long flags;
 	/* Check if the card has been yanked. */
 	if (priv->card && priv->present_callback &&
 		!(*priv->present_callback)(priv->card))
 		return;
 	spin_lock_irqsave(&priv->irqlock, flags);
 	switch (priv->station_state) {
 	case STATION_STATE_AUTHENTICATING:
 		if (priv->AuthenticationRequestRetryCnt >= MAX_AUTHENTICATION_RETRIES) {
 			atmel_enter_state(priv, STATION_STATE_MGMT_ERROR);
 			priv->station_is_associated = 0;
 			priv->AuthenticationRequestRetryCnt = 0;
 			restart_search(priv);
 		} else {
 			int auth = WLAN_AUTH_OPEN;
 			priv->AuthenticationRequestRetryCnt++;
 			priv->CurrentAuthentTransactionSeqNum = 0x0001;
 			mod_timer(&priv->management_timer, jiffies + MGMT_JIFFIES);
 			if (priv->wep_is_on && priv->exclude_unencrypted)
 				auth = WLAN_AUTH_SHARED_KEY;
 			send_authentication_request(priv, auth, NULL, 0);
 	  }
 	  break;
 	case STATION_STATE_ASSOCIATING:
 		if (priv->AssociationRequestRetryCnt == MAX_ASSOCIATION_RETRIES) {
 			atmel_enter_state(priv, STATION_STATE_MGMT_ERROR);
 			priv->station_is_associated = 0;
 			priv->AssociationRequestRetryCnt = 0;
 			restart_search(priv);
 		} else {
 			priv->AssociationRequestRetryCnt++;
 			mod_timer(&priv->management_timer, jiffies + MGMT_JIFFIES);
 			send_association_request(priv, 0);
 		}
 	  break;
 	case STATION_STATE_REASSOCIATING:
 		if (priv->ReAssociationRequestRetryCnt == MAX_ASSOCIATION_RETRIES) {
 			atmel_enter_state(priv, STATION_STATE_MGMT_ERROR);
 			priv->station_is_associated = 0;
 			priv->ReAssociationRequestRetryCnt = 0;
 			restart_search(priv);
 		} else {
 			priv->ReAssociationRequestRetryCnt++;
 			mod_timer(&priv->management_timer, jiffies + MGMT_JIFFIES);
 			send_association_request(priv, 1);
 		}
 		break;
 	default:
 		break;
 	}
 	spin_unlock_irqrestore(&priv->irqlock, flags);
 }
 static void atmel_command_irq(struct atmel_private *priv)
 {
 	u8 status = atmel_rmem8(priv, atmel_co(priv, CMD_BLOCK_STATUS_OFFSET));
 	u8 command = atmel_rmem8(priv, atmel_co(priv, CMD_BLOCK_COMMAND_OFFSET));
 	int fast_scan;
 	union iwreq_data wrqu;
 	if (status == CMD_STATUS_IDLE ||
 	    status == CMD_STATUS_IN_PROGRESS)
 		return;
 	switch (command) {
 	case CMD_Start:
 		if (status == CMD_STATUS_COMPLETE) {
 			priv->station_was_associated = priv->station_is_associated;
 			atmel_get_mib(priv, Mac_Mgmt_Mib_Type, MAC_MGMT_MIB_CUR_BSSID_POS,
 				      (u8 *)priv->CurrentBSSID, 6);
 			atmel_enter_state(priv, STATION_STATE_READY);
 		}
 		break;
 	case CMD_Scan:
 		fast_scan = priv->fast_scan;
 		priv->fast_scan = 0;
 		if (status != CMD_STATUS_COMPLETE) {
 			atmel_scan(priv, 1);
 		} else {
 			int bss_index = retrieve_bss(priv);
 			int notify_scan_complete = 1;
 			if (bss_index != -1) {
 				atmel_join_bss(priv, bss_index);
 			} else if (priv->operating_mode == IW_MODE_ADHOC &&
 				   priv->SSID_size != 0) {
 				start(priv, BSS_TYPE_AD_HOC);
 			} else {
 				priv->fast_scan = !fast_scan;
 				atmel_scan(priv, 1);
 				notify_scan_complete = 0;
 			}
 			priv->site_survey_state = SITE_SURVEY_COMPLETED;
 			if (notify_scan_complete) {
 				wrqu.data.length = 0;
 				wrqu.data.flags = 0;
 				wireless_send_event(priv->dev, SIOCGIWSCAN, &wrqu, NULL);
 			}
 		}
 		break;
 	case CMD_SiteSurvey:
 		priv->fast_scan = 0;
 		if (status != CMD_STATUS_COMPLETE)
 			return;
 		priv->site_survey_state = SITE_SURVEY_COMPLETED;
 		if (priv->station_is_associated) {
 			atmel_enter_state(priv, STATION_STATE_READY);
 			wrqu.data.length = 0;
 			wrqu.data.flags = 0;
 			wireless_send_event(priv->dev, SIOCGIWSCAN, &wrqu, NULL);
 		} else {
 			atmel_scan(priv, 1);
 		}
 		break;
 	case CMD_Join:
 		if (status == CMD_STATUS_COMPLETE) {
 			if (priv->operating_mode == IW_MODE_ADHOC) {
 				priv->station_was_associated = priv->station_is_associated;
 				atmel_enter_state(priv, STATION_STATE_READY);
 			} else {
 				int auth = WLAN_AUTH_OPEN;
 				priv->AuthenticationRequestRetryCnt = 0;
 				atmel_enter_state(priv, STATION_STATE_AUTHENTICATING);
 				mod_timer(&priv->management_timer, jiffies + MGMT_JIFFIES);
 				priv->CurrentAuthentTransactionSeqNum = 0x0001;
 				if (priv->wep_is_on && priv->exclude_unencrypted)
 					auth = WLAN_AUTH_SHARED_KEY;
 				send_authentication_request(priv, auth, NULL, 0);
 			}
 			return;
 		}
 		atmel_scan(priv, 1);
 	}
 }
 static int atmel_wakeup_firmware(struct atmel_private *priv)
 {
 	struct host_info_struct *iface = &priv->host_info;
 	u16 mr1, mr3;
 	int i;
 	if (priv->card_type == CARD_TYPE_SPI_FLASH)
 		atmel_set_gcr(priv->dev, GCR_REMAP);
 	/* wake up on-board processor */
 	atmel_clear_gcr(priv->dev, 0x0040);
 	atmel_write16(priv->dev, BSR, BSS_SRAM);
 	if (priv->card_type == CARD_TYPE_SPI_FLASH)
 		mdelay(100);
 	/* and wait for it */
 	for (i = LOOP_RETRY_LIMIT; i; i--) {
 		mr1 = atmel_read16(priv->dev, MR1);
 		mr3 = atmel_read16(priv->dev, MR3);
 		if (mr3 & MAC_BOOT_COMPLETE)
 			break;
 		if (mr1 & MAC_BOOT_COMPLETE &&
 		    priv->bus_type == BUS_TYPE_PCCARD)
 			break;
 	}
 	if (i == 0) {
 		printk(KERN_ALERT "%s: MAC failed to boot.\n", priv->dev->name);
 		return -EIO;
 	}
 	if ((priv->host_info_base = atmel_read16(priv->dev, MR2)) == 0xffff) {
 		printk(KERN_ALERT "%s: card missing.\n", priv->dev->name);
 		return -ENODEV;
 	}
 	/* now check for completion of MAC initialization through
 	   the FunCtrl field of the IFACE, poll MR1 to detect completion of
 	   MAC initialization, check completion status, set interrupt mask,
 	   enables interrupts and calls Tx and Rx initialization functions */
 	atmel_wmem8(priv, atmel_hi(priv, IFACE_FUNC_CTRL_OFFSET), FUNC_CTRL_INIT_COMPLETE);
 	for (i = LOOP_RETRY_LIMIT; i; i--) {
 		mr1 = atmel_read16(priv->dev, MR1);
 		mr3 = atmel_read16(priv->dev, MR3);
 		if (mr3 & MAC_INIT_COMPLETE)
 			break;
 		if (mr1 & MAC_INIT_COMPLETE &&
 		    priv->bus_type == BUS_TYPE_PCCARD)
 			break;
 	}
 	if (i == 0) {
 		printk(KERN_ALERT "%s: MAC failed to initialise.\n",
 				priv->dev->name);
 		return -EIO;
 	}
 	/* Check for MAC_INIT_OK only on the register that the MAC_INIT_OK was set */
 	if ((mr3 & MAC_INIT_COMPLETE) &&
 	    !(atmel_read16(priv->dev, MR3) & MAC_INIT_OK)) {
 		printk(KERN_ALERT "%s: MAC failed MR3 self-test.\n", priv->dev->name);
 		return -EIO;
 	}
 	if ((mr1 & MAC_INIT_COMPLETE) &&
 	    !(atmel_read16(priv->dev, MR1) & MAC_INIT_OK)) {
 		printk(KERN_ALERT "%s: MAC failed MR1 self-test.\n", priv->dev->name);
 		return -EIO;
 	}
 	atmel_copy_to_host(priv->dev, (unsigned char *)iface,
 			   priv->host_info_base, sizeof(*iface));
 	iface->tx_buff_pos = le16_to_cpu(iface->tx_buff_pos);
 	iface->tx_buff_size = le16_to_cpu(iface->tx_buff_size);
 	iface->tx_desc_pos = le16_to_cpu(iface->tx_desc_pos);
 	iface->tx_desc_count = le16_to_cpu(iface->tx_desc_count);
 	iface->rx_buff_pos = le16_to_cpu(iface->rx_buff_pos);
 	iface->rx_buff_size = le16_to_cpu(iface->rx_buff_size);
 	iface->rx_desc_pos = le16_to_cpu(iface->rx_desc_pos);
 	iface->rx_desc_count = le16_to_cpu(iface->rx_desc_count);
 	iface->build_version = le16_to_cpu(iface->build_version);
 	iface->command_pos = le16_to_cpu(iface->command_pos);
 	iface->major_version = le16_to_cpu(iface->major_version);
 	iface->minor_version = le16_to_cpu(iface->minor_version);
 	iface->func_ctrl = le16_to_cpu(iface->func_ctrl);
 	iface->mac_status = le16_to_cpu(iface->mac_status);
 	return 0;
 }
 /* determine type of memory and MAC address */
 static int probe_atmel_card(struct net_device *dev)
 {
 	int rc = 0;
 	struct atmel_private *priv = netdev_priv(dev);
 	/* reset pccard */
 	if (priv->bus_type == BUS_TYPE_PCCARD)
 		atmel_write16(dev, GCR, 0x0060);
 	atmel_write16(dev, GCR, 0x0040);
 	mdelay(500);
 	if (atmel_read16(dev, MR2) == 0) {
 		/* No stored firmware so load a small stub which just
 		   tells us the MAC address */
 		int i;
 		priv->card_type = CARD_TYPE_EEPROM;
 		atmel_write16(dev, BSR, BSS_IRAM);
 		atmel_copy_to_card(dev, 0, mac_reader, sizeof(mac_reader));
 		atmel_set_gcr(dev, GCR_REMAP);
 		atmel_clear_gcr(priv->dev, 0x0040);
 		atmel_write16(dev, BSR, BSS_SRAM);
 		for (i = LOOP_RETRY_LIMIT; i; i--)
 			if (atmel_read16(dev, MR3) & MAC_BOOT_COMPLETE)
 				break;
 		if (i == 0) {
 			printk(KERN_ALERT "%s: MAC failed to boot MAC address reader.\n", dev->name);
 		} else {
 			atmel_copy_to_host(dev, dev->dev_addr, atmel_read16(dev, MR2), 6);
 			/* got address, now squash it again until the network
 			   interface is opened */
 			if (priv->bus_type == BUS_TYPE_PCCARD)
 				atmel_write16(dev, GCR, 0x0060);
 			atmel_write16(dev, GCR, 0x0040);
 			rc = 1;
 		}
 	} else if (atmel_read16(dev, MR4) == 0) {
 		/* Mac address easy in this case. */
 		priv->card_type = CARD_TYPE_PARALLEL_FLASH;
 		atmel_write16(dev,  BSR, 1);
 		atmel_copy_to_host(dev, dev->dev_addr, 0xc000, 6);
 		atmel_write16(dev,  BSR, 0x200);
 		rc = 1;
 	} else {
 		/* Standard firmware in flash, boot it up and ask
 		   for the Mac Address */
 		priv->card_type = CARD_TYPE_SPI_FLASH;
 		if (atmel_wakeup_firmware(priv) == 0) {
 			atmel_get_mib(priv, Mac_Address_Mib_Type, 0, dev->dev_addr, 6);
 			/* got address, now squash it again until the network
 			   interface is opened */
 			if (priv->bus_type == BUS_TYPE_PCCARD)
 				atmel_write16(dev, GCR, 0x0060);
 			atmel_write16(dev, GCR, 0x0040);
 			rc = 1;
 		}
 	}
 	if (rc) {
 		if (dev->dev_addr[0] == 0xFF) {
 			u8 default_mac[] = {0x00, 0x04, 0x25, 0x00, 0x00, 0x00};
 			printk(KERN_ALERT "%s: *** Invalid MAC address. UPGRADE Firmware ****\n", dev->name);
 			memcpy(dev->dev_addr, default_mac, 6);
 		}
 	}
 	return rc;
 }
 /* Move the encyption information on the MIB structure.
   This routine is for the pre-WPA firmware: later firmware has
   a different format MIB and a different routine. */
 static void build_wep_mib(struct atmel_private *priv)
 {
 	struct { /* NB this is matched to the hardware, don't change. */
 		u8 wep_is_on;
 		u8 default_key; /* 0..3 */
 		u8 reserved;
 		u8 exclude_unencrypted;
 		u32 WEPICV_error_count;
 		u32 WEP_excluded_count;
 		u8 wep_keys[MAX_ENCRYPTION_KEYS][13];
 		u8 encryption_level; /* 0, 1, 2 */
 		u8 reserved2[3];
 	} mib;
 	int i;
 	mib.wep_is_on = priv->wep_is_on;
 	if (priv->wep_is_on) {
 		if (priv->wep_key_len[priv->default_key] > 5)
 			mib.encryption_level = 2;
 		else
 			mib.encryption_level = 1;
 	} else {
 		mib.encryption_level = 0;
 	}
 	mib.default_key = priv->default_key;
 	mib.exclude_unencrypted = priv->exclude_unencrypted;
 	for (i = 0; i < MAX_ENCRYPTION_KEYS; i++)
 		memcpy(mib.wep_keys[i], priv->wep_keys[i], 13);
 	atmel_set_mib(priv, Mac_Wep_Mib_Type, 0, (u8 *)&mib, sizeof(mib));
 }
 static void build_wpa_mib(struct atmel_private *priv)
 {
 	/* This is for the later (WPA enabled) firmware. */
 	struct { /* NB this is matched to the hardware, don't change. */
 		u8 cipher_default_key_value[MAX_ENCRYPTION_KEYS][MAX_ENCRYPTION_KEY_SIZE];
 		u8 receiver_address[6];
 		u8 wep_is_on;
 		u8 default_key; /* 0..3 */
 		u8 group_key;
 		u8 exclude_unencrypted;
 		u8 encryption_type;
 		u8 reserved;
 		u32 WEPICV_error_count;
 		u32 WEP_excluded_count;
 		u8 key_RSC[4][8];
 	} mib;
 	int i;
 	mib.wep_is_on = priv->wep_is_on;
 	mib.exclude_unencrypted = priv->exclude_unencrypted;
 	memcpy(mib.receiver_address, priv->CurrentBSSID, 6);
 	/* zero all the keys before adding in valid ones. */
 	memset(mib.cipher_default_key_value, 0, sizeof(mib.cipher_default_key_value));
 	if (priv->wep_is_on) {
 		/* There's a comment in the Atmel code to the effect that this
 		   is only valid when still using WEP, it may need to be set to
 		   something to use WPA */
 		memset(mib.key_RSC, 0, sizeof(mib.key_RSC));
 		mib.default_key = mib.group_key = 255;
 		for (i = 0; i < MAX_ENCRYPTION_KEYS; i++) {
 			if (priv->wep_key_len[i] > 0) {
 				memcpy(mib.cipher_default_key_value[i], priv->wep_keys[i], MAX_ENCRYPTION_KEY_SIZE);
 				if (i == priv->default_key) {
 					mib.default_key = i;
 					mib.cipher_default_key_value[i][MAX_ENCRYPTION_KEY_SIZE-1] = 7;
 					mib.cipher_default_key_value[i][MAX_ENCRYPTION_KEY_SIZE-2] = priv->pairwise_cipher_suite;
 				} else {
 					mib.group_key = i;
 					priv->group_cipher_suite = priv->pairwise_cipher_suite;
 					mib.cipher_default_key_value[i][MAX_ENCRYPTION_KEY_SIZE-1] = 1;
 					mib.cipher_default_key_value[i][MAX_ENCRYPTION_KEY_SIZE-2] = priv->group_cipher_suite;
 				}
 			}
 		}
 		if (mib.default_key == 255)
 			mib.default_key = mib.group_key != 255 ? mib.group_key : 0;
 		if (mib.group_key == 255)
 			mib.group_key = mib.default_key;
 	}
 	atmel_set_mib(priv, Mac_Wep_Mib_Type, 0, (u8 *)&mib, sizeof(mib));
 }
 static int reset_atmel_card(struct net_device *dev)
 {
 	/* do everything necessary to wake up the hardware, including
 	   waiting for the lightning strike and throwing the knife switch....
 	   set all the Mib values which matter in the card to match
 	   their settings in the atmel_private structure. Some of these
 	   can be altered on the fly, but many (WEP, infrastucture or ad-hoc)
 	   can only be changed by tearing down the world and coming back through
 	   here.
 	   This routine is also responsible for initialising some
 	   hardware-specific fields in the atmel_private structure,
 	   including a copy of the firmware's hostinfo stucture
 	   which is the route into the rest of the firmware datastructures. */
 	struct atmel_private *priv = netdev_priv(dev);
 	u8 configuration;
 	int old_state = priv->station_state;
 	int err = 0;
 	/* data to add to the firmware names, in priority order
 	   this implemenents firmware versioning */
 	static char *firmware_modifier[] = {
 		"-wpa",
 		"",
 		NULL
 	};
 	/* reset pccard */
 	if (priv->bus_type == BUS_TYPE_PCCARD)
 		atmel_write16(priv->dev, GCR, 0x0060);
 	/* stop card , disable interrupts */
 	atmel_write16(priv->dev, GCR, 0x0040);
 	if (priv->card_type == CARD_TYPE_EEPROM) {
 		/* copy in firmware if needed */
 		const struct firmware *fw_entry = NULL;
 		const unsigned char *fw;
 		int len = priv->firmware_length;
 		if (!(fw = priv->firmware)) {
 			if (priv->firmware_type == ATMEL_FW_TYPE_NONE) {
 				if (strlen(priv->firmware_id) == 0) {
 					printk(KERN_INFO
 					       "%s: card type is unknown: assuming at76c502 firmware is OK.\n",
 					       dev->name);
 					printk(KERN_INFO
 					       "%s: if not, use the firmware= module parameter.\n",
 					       dev->name);
 					strcpy(priv->firmware_id, "atmel_at76c502.bin");
 				}
 				err = request_firmware(&fw_entry, priv->firmware_id, priv->sys_dev);
 				if (err != 0) {
 					printk(KERN_ALERT
 					       "%s: firmware %s is missing, cannot continue.\n",
 					       dev->name, priv->firmware_id);
 					return err;
 				}
 			} else {
 				int fw_index = 0;
 				int success = 0;
 				/* get firmware filename entry based on firmware type ID */
 				while (fw_table[fw_index].fw_type != priv->firmware_type
 						&& fw_table[fw_index].fw_type != ATMEL_FW_TYPE_NONE)
 					fw_index++;
 				/* construct the actual firmware file name */
 				if (fw_table[fw_index].fw_type != ATMEL_FW_TYPE_NONE) {
 					int i;
 					for (i = 0; firmware_modifier[i]; i++) {
 						snprintf(priv->firmware_id, 32, "%s%s.%s", fw_table[fw_index].fw_file,
 							firmware_modifier[i], fw_table[fw_index].fw_file_ext);
 						priv->firmware_id[31] = '\0';
 						if (request_firmware(&fw_entry, priv->firmware_id, priv->sys_dev) == 0) {
 							success = 1;
 							break;
 						}
 					}
 				}
 				if (!success) {
 					printk(KERN_ALERT
 					       "%s: firmware %s is missing, cannot start.\n",
 					       dev->name, priv->firmware_id);
 					priv->firmware_id[0] = '\0';
 					return -ENOENT;
 				}
 			}
 			fw = fw_entry->data;
 			len = fw_entry->size;
 		}
 		if (len <= 0x6000) {
 			atmel_write16(priv->dev, BSR, BSS_IRAM);
 			atmel_copy_to_card(priv->dev, 0, fw, len);
 			atmel_set_gcr(priv->dev, GCR_REMAP);
 		} else {
 			/* Remap */
 			atmel_set_gcr(priv->dev, GCR_REMAP);
 			atmel_write16(priv->dev, BSR, BSS_IRAM);
 			atmel_copy_to_card(priv->dev, 0, fw, 0x6000);
 			atmel_write16(priv->dev, BSR, 0x2ff);
 			atmel_copy_to_card(priv->dev, 0x8000, &fw[0x6000], len - 0x6000);
 		}
 		if (fw_entry)
 			release_firmware(fw_entry);
 	}
 	err = atmel_wakeup_firmware(priv);
 	if (err != 0)
 		return err;
 	/* Check the version and set the correct flag for wpa stuff,
 	   old and new firmware is incompatible.
 	   The pre-wpa 3com firmware reports major version 5,
 	   the wpa 3com firmware is major version 4 and doesn't need
 	   the 3com broken-ness filter. */
 	priv->use_wpa = (priv->host_info.major_version == 4);
 	priv->radio_on_broken = (priv->host_info.major_version == 5);
 	/* unmask all irq sources */
 	atmel_wmem8(priv, atmel_hi(priv, IFACE_INT_MASK_OFFSET), 0xff);
 	/* int Tx system and enable Tx */
 	atmel_wmem8(priv, atmel_tx(priv, TX_DESC_FLAGS_OFFSET, 0), 0);
 	atmel_wmem32(priv, atmel_tx(priv, TX_DESC_NEXT_OFFSET, 0), 0x80000000L);
 	atmel_wmem16(priv, atmel_tx(priv, TX_DESC_POS_OFFSET, 0), 0);
 	atmel_wmem16(priv, atmel_tx(priv, TX_DESC_SIZE_OFFSET, 0), 0);
 	priv->tx_desc_free = priv->host_info.tx_desc_count;
 	priv->tx_desc_head = 0;
 	priv->tx_desc_tail = 0;
 	priv->tx_desc_previous = 0;
 	priv->tx_free_mem = priv->host_info.tx_buff_size;
 	priv->tx_buff_head = 0;
 	priv->tx_buff_tail = 0;
 	configuration = atmel_rmem8(priv, atmel_hi(priv, IFACE_FUNC_CTRL_OFFSET));
 	atmel_wmem8(priv, atmel_hi(priv, IFACE_FUNC_CTRL_OFFSET),
 				   configuration | FUNC_CTRL_TxENABLE);
 	/* init Rx system and enable */
 	priv->rx_desc_head = 0;
 	configuration = atmel_rmem8(priv, atmel_hi(priv, IFACE_FUNC_CTRL_OFFSET));
 	atmel_wmem8(priv, atmel_hi(priv, IFACE_FUNC_CTRL_OFFSET),
 				   configuration | FUNC_CTRL_RxENABLE);
 	if (!priv->radio_on_broken) {
 		if (atmel_send_command_wait(priv, CMD_EnableRadio, NULL, 0) ==
 		    CMD_STATUS_REJECTED_RADIO_OFF) {
 			printk(KERN_INFO "%s: cannot turn the radio on.\n",
 			       dev->name);
 			return -EIO;
 		}
 	}
 	/* set up enough MIB values to run. */
 	atmel_set_mib8(priv, Local_Mib_Type, LOCAL_MIB_AUTO_TX_RATE_POS, priv->auto_tx_rate);
 	atmel_set_mib8(priv, Local_Mib_Type,  LOCAL_MIB_TX_PROMISCUOUS_POS,  PROM_MODE_OFF);
 	atmel_set_mib16(priv, Mac_Mib_Type, MAC_MIB_RTS_THRESHOLD_POS, priv->rts_threshold);
 	atmel_set_mib16(priv, Mac_Mib_Type, MAC_MIB_FRAG_THRESHOLD_POS, priv->frag_threshold);
 	atmel_set_mib8(priv, Mac_Mib_Type, MAC_MIB_SHORT_RETRY_POS, priv->short_retry);
 	atmel_set_mib8(priv, Mac_Mib_Type, MAC_MIB_LONG_RETRY_POS, priv->long_retry);
 	atmel_set_mib8(priv, Local_Mib_Type, LOCAL_MIB_PREAMBLE_TYPE, priv->preamble);
 	atmel_set_mib(priv, Mac_Address_Mib_Type, MAC_ADDR_MIB_MAC_ADDR_POS,
 		      priv->dev->dev_addr, 6);
 	atmel_set_mib8(priv, Mac_Mgmt_Mib_Type, MAC_MGMT_MIB_PS_MODE_POS, ACTIVE_MODE);
 	atmel_set_mib16(priv, Mac_Mgmt_Mib_Type, MAC_MGMT_MIB_LISTEN_INTERVAL_POS, 1);
 	atmel_set_mib16(priv, Mac_Mgmt_Mib_Type, MAC_MGMT_MIB_BEACON_PER_POS, priv->default_beacon_period);
 	atmel_set_mib(priv, Phy_Mib_Type, PHY_MIB_RATE_SET_POS, atmel_basic_rates, 4);
 	atmel_set_mib8(priv, Mac_Mgmt_Mib_Type, MAC_MGMT_MIB_CUR_PRIVACY_POS, priv->wep_is_on);
 	if (priv->use_wpa)
 		build_wpa_mib(priv);
 	else
 		build_wep_mib(priv);
 	if (old_state == STATION_STATE_READY) {
 		union iwreq_data wrqu;
 		wrqu.data.length = 0;
 		wrqu.data.flags = 0;
 		wrqu.ap_addr.sa_family = ARPHRD_ETHER;
 		memset(wrqu.ap_addr.sa_data, 0, ETH_ALEN);
 		wireless_send_event(priv->dev, SIOCGIWAP, &wrqu, NULL);
 	}
 	return 0;
 }
 static void atmel_send_command(struct atmel_private *priv, int command,
 			       void *cmd, int cmd_size)
 {
 	if (cmd)
 		atmel_copy_to_card(priv->dev, atmel_co(priv, CMD_BLOCK_PARAMETERS_OFFSET),
 				   cmd, cmd_size);
 	atmel_wmem8(priv, atmel_co(priv, CMD_BLOCK_COMMAND_OFFSET), command);
 	atmel_wmem8(priv, atmel_co(priv, CMD_BLOCK_STATUS_OFFSET), 0);
 }
 static int atmel_send_command_wait(struct atmel_private *priv, int command,
 				   void *cmd, int cmd_size)
 {
 	int i, status;
 	atmel_send_command(priv, command, cmd, cmd_size);
 	for (i = 5000; i; i--) {
 		status = atmel_rmem8(priv, atmel_co(priv, CMD_BLOCK_STATUS_OFFSET));
 		if (status != CMD_STATUS_IDLE &&
 		    status != CMD_STATUS_IN_PROGRESS)
 			break;
 		udelay(20);
 	}
 	if (i == 0) {
 		printk(KERN_ALERT "%s: failed to contact MAC.\n", priv->dev->name);
 		status =  CMD_STATUS_HOST_ERROR;
 	} else {
 		if (command != CMD_EnableRadio)
 			status = CMD_STATUS_COMPLETE;
 	}
 	return status;
 }
 static u8 atmel_get_mib8(struct atmel_private *priv, u8 type, u8 index)
 {
 	struct get_set_mib m;
 	m.type = type;
 	m.size = 1;
 	m.index = index;
 	atmel_send_command_wait(priv, CMD_Get_MIB_Vars, &m, MIB_HEADER_SIZE + 1);
 	return atmel_rmem8(priv, atmel_co(priv, CMD_BLOCK_PARAMETERS_OFFSET + MIB_HEADER_SIZE));
 }
 static void atmel_set_mib8(struct atmel_private *priv, u8 type, u8 index, u8 data)
 {
 	struct get_set_mib m;
 	m.type = type;
 	m.size = 1;
 	m.index = index;
 	m.data[0] = data;
 	atmel_send_command_wait(priv, CMD_Set_MIB_Vars, &m, MIB_HEADER_SIZE + 1);
 }
 static void atmel_set_mib16(struct atmel_private *priv, u8 type, u8 index,
 			    u16 data)
 {
 	struct get_set_mib m;
 	m.type = type;
 	m.size = 2;
 	m.index = index;
 	m.data[0] = data;
 	m.data[1] = data >> 8;
 	atmel_send_command_wait(priv, CMD_Set_MIB_Vars, &m, MIB_HEADER_SIZE + 2);
 }
 static void atmel_set_mib(struct atmel_private *priv, u8 type, u8 index,
 			  u8 *data, int data_len)
 {
 	struct get_set_mib m;
 	m.type = type;
 	m.size = data_len;
 	m.index = index;
 	if (data_len > MIB_MAX_DATA_BYTES)
 		printk(KERN_ALERT "%s: MIB buffer too small.\n", priv->dev->name);
 	memcpy(m.data, data, data_len);
 	atmel_send_command_wait(priv, CMD_Set_MIB_Vars, &m, MIB_HEADER_SIZE + data_len);
 }
 static void atmel_get_mib(struct atmel_private *priv, u8 type, u8 index,
 			  u8 *data, int data_len)
 {
 	struct get_set_mib m;
 	m.type = type;
 	m.size = data_len;
 	m.index = index;
 	if (data_len > MIB_MAX_DATA_BYTES)
 		printk(KERN_ALERT "%s: MIB buffer too small.\n", priv->dev->name);
 	atmel_send_command_wait(priv, CMD_Get_MIB_Vars, &m, MIB_HEADER_SIZE + data_len);
 	atmel_copy_to_host(priv->dev, data,
 			   atmel_co(priv, CMD_BLOCK_PARAMETERS_OFFSET + MIB_HEADER_SIZE), data_len);
 }
 static void atmel_writeAR(struct net_device *dev, u16 data)
 {
 	int i;
 	outw(data, dev->base_addr + AR);
 	/* Address register appears to need some convincing..... */
 	for (i = 0; data != inw(dev->base_addr + AR) && i < 10; i++)
 		outw(data, dev->base_addr + AR);
 }
 static void atmel_copy_to_card(struct net_device *dev, u16 dest,
 			       const unsigned char *src, u16 len)
 {
 	int i;
 	atmel_writeAR(dev, dest);
 	if (dest % 2) {
 		atmel_write8(dev, DR, *src);
 		src++; len--;
 	}
 	for (i = len; i > 1 ; i -= 2) {
 		u8 lb = *src++;
 		u8 hb = *src++;
 		atmel_write16(dev, DR, lb | (hb << 8));
 	}
 	if (i)
 		atmel_write8(dev, DR, *src);
 }
 static void atmel_copy_to_host(struct net_device *dev, unsigned char *dest,
 			       u16 src, u16 len)
 {
 	int i;
 	atmel_writeAR(dev, src);
 	if (src % 2) {
 		*dest = atmel_read8(dev, DR);
 		dest++; len--;
 	}
 	for (i = len; i > 1 ; i -= 2) {
 		u16 hw = atmel_read16(dev, DR);
 		*dest++ = hw;
 		*dest++ = hw >> 8;
 	}
 	if (i)
 		*dest = atmel_read8(dev, DR);
 }
 static void atmel_set_gcr(struct net_device *dev, u16 mask)
 {
 	outw(inw(dev->base_addr + GCR) | mask, dev->base_addr + GCR);
 }
 static void atmel_clear_gcr(struct net_device *dev, u16 mask)
 {
 	outw(inw(dev->base_addr + GCR) & ~mask, dev->base_addr + GCR);
 }
 static int atmel_lock_mac(struct atmel_private *priv)
 {
 	int i, j = 20;
 retry:
 	for (i = 5000; i; i--) {
 		if (!atmel_rmem8(priv, atmel_hi(priv, IFACE_LOCKOUT_HOST_OFFSET)))
 			break;
 		udelay(20);
 	}
 	if (!i)
 		return 0; /* timed out */
 	atmel_wmem8(priv, atmel_hi(priv, IFACE_LOCKOUT_MAC_OFFSET), 1);
 	if (atmel_rmem8(priv, atmel_hi(priv, IFACE_LOCKOUT_HOST_OFFSET))) {
 		atmel_wmem8(priv, atmel_hi(priv, IFACE_LOCKOUT_MAC_OFFSET), 0);
 		if (!j--)
 			return 0; /* timed out */
 		goto retry;
 	}
 	return 1;
 }
 static void atmel_wmem32(struct atmel_private *priv, u16 pos, u32 data)
 {
 	atmel_writeAR(priv->dev, pos);
 	atmel_write16(priv->dev, DR, data); /* card is little-endian */
 	atmel_write16(priv->dev, DR, data >> 16);
 }
 /***************************************************************************/
 /* There follows the source form of the MAC address reading firmware       */
 /***************************************************************************/
 #if 0
 /* Copyright 2003 Matthew T. Russotto                                      */
 /* But derived from the Atmel 76C502 firmware written by Atmel and         */
 /* included in "atmel wireless lan drivers" package                        */
 /**
    This file is part of net.russotto.AtmelMACFW, hereto referred to
    as AtmelMACFW
    AtmelMACFW is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License version 2
    as published by the Free Software Foundation.
    AtmelMACFW is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.
    You should have received a copy of the GNU General Public License
    along with AtmelMACFW; if not, write to the Free Software
    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 ****************************************************************************/
 /* This firmware should work on the 76C502 RFMD, RFMD_D, and RFMD_E        */
 /* It will probably work on the 76C504 and 76C502 RFMD_3COM                */
 /* It only works on SPI EEPROM versions of the card.                       */
 /* This firmware initializes the SPI controller and clock, reads the MAC   */
 /* address from the EEPROM into SRAM, and puts the SRAM offset of the MAC  */
 /* address in MR2, and sets MR3 to 0x10 to indicate it is done             */
 /* It also puts a complete copy of the EEPROM in SRAM with the offset in   */
 /* MR4, for investigational purposes (maybe we can determine chip type     */
 /* from that?)                                                             */
 	.org 0
    .set MRBASE, 0x8000000
 	.set CPSR_INITIAL, 0xD3 /* IRQ/FIQ disabled, ARM mode, Supervisor state */
 	.set CPSR_USER, 0xD1 /* IRQ/FIQ disabled, ARM mode, USER state */
 	.set SRAM_BASE,  0x02000000
 	.set SP_BASE,    0x0F300000
 	.set UNK_BASE,   0x0F000000 /* Some internal device, but which one? */
 	.set SPI_CGEN_BASE,  0x0E000000 /* Some internal device, but which one? */
 	.set UNK3_BASE,  0x02014000 /* Some internal device, but which one? */
 	.set STACK_BASE, 0x5600
 	.set SP_SR, 0x10
 	.set SP_TDRE, 2 /* status register bit -- TDR empty */
 	.set SP_RDRF, 1 /* status register bit -- RDR full */
 	.set SP_SWRST, 0x80
 	.set SP_SPIEN, 0x1
 	.set SP_CR, 0   /* control register */
 	.set SP_MR, 4   /* mode register */
 	.set SP_RDR, 0x08 /* Read Data Register */
 	.set SP_TDR, 0x0C /* Transmit Data Register */
 	.set SP_CSR0, 0x30 /* chip select registers */
 	.set SP_CSR1, 0x34
 	.set SP_CSR2, 0x38
 	.set SP_CSR3, 0x3C
 	.set NVRAM_CMD_RDSR, 5 /* read status register */
 	.set NVRAM_CMD_READ, 3 /* read data */
 	.set NVRAM_SR_RDY, 1 /* RDY bit.  This bit is inverted */
 	.set SPI_8CLOCKS, 0xFF /* Writing this to the TDR doesn't do anything to the
 				  serial output, since SO is normally high.  But it
 				  does cause 8 clock cycles and thus 8 bits to be
 				  clocked in to the chip.  See Atmel's SPI
 				  controller (e.g. AT91M55800) timing and 4K
 				  SPI EEPROM manuals */
 	.set NVRAM_SCRATCH, 0x02000100  /* arbitrary area for scratchpad memory */
 	.set NVRAM_IMAGE, 0x02000200
 	.set NVRAM_LENGTH, 0x0200
 	.set MAC_ADDRESS_MIB, SRAM_BASE
 	.set MAC_ADDRESS_LENGTH, 6
 	.set MAC_BOOT_FLAG, 0x10
 	.set MR1, 0
 	.set MR2, 4
 	.set MR3, 8
 	.set MR4, 0xC
 RESET_VECTOR:
 	b RESET_HANDLER
 UNDEF_VECTOR:
 	b HALT1
 SWI_VECTOR:
 	b HALT1
 IABORT_VECTOR:
 	b HALT1
 DABORT_VECTOR:
 RESERVED_VECTOR:
 	b HALT1
 IRQ_VECTOR:
 	b HALT1
 FIQ_VECTOR:
 	b HALT1
 HALT1:	b HALT1
 RESET_HANDLER:
 	mov     r0, #CPSR_INITIAL
 	msr	CPSR_c, r0	/* This is probably unnecessary */
 /* I'm guessing this is initializing clock generator electronics for SPI */
 	ldr	r0, =SPI_CGEN_BASE
 	mov	r1, #0
 	mov	r1, r1, lsl #3
 	orr	r1, r1, #0
 	str	r1, [r0]
 	ldr	r1, [r0, #28]
 	bic	r1, r1, #16
 	str	r1, [r0, #28]
 	mov	r1, #1
 	str	r1, [r0, #8]
 	ldr	r0, =MRBASE
 	mov	r1, #0
 	strh	r1, [r0, #MR1]
 	strh	r1, [r0, #MR2]
 	strh	r1, [r0, #MR3]
 	strh	r1, [r0, #MR4]
 	mov	sp, #STACK_BASE
 	bl	SP_INIT
 	mov	r0, #10
 	bl	DELAY9
 	bl	GET_MAC_ADDR
 	bl	GET_WHOLE_NVRAM
 	ldr	r0, =MRBASE
 	ldr	r1, =MAC_ADDRESS_MIB
 	strh	r1, [r0, #MR2]
 	ldr	r1, =NVRAM_IMAGE
 	strh	r1, [r0, #MR4]
 	mov	r1, #MAC_BOOT_FLAG
 	strh	r1, [r0, #MR3]
 HALT2:	b HALT2
 .func Get_Whole_NVRAM, GET_WHOLE_NVRAM
 GET_WHOLE_NVRAM:
 	stmdb	sp!, {lr}
 	mov	r2, #0 /* 0th bytes of NVRAM */
 	mov	r3, #NVRAM_LENGTH
 	mov	r1, #0		/* not used in routine */
 	ldr	r0, =NVRAM_IMAGE
 	bl	NVRAM_XFER
 	ldmia	sp!, {lr}
 	bx	lr
 .endfunc
 .func Get_MAC_Addr, GET_MAC_ADDR
 GET_MAC_ADDR:
 	stmdb	sp!, {lr}
 	mov	r2, #0x120	/* address of MAC Address within NVRAM */
 	mov	r3, #MAC_ADDRESS_LENGTH
 	mov	r1, #0		/* not used in routine */
 	ldr	r0, =MAC_ADDRESS_MIB
 	bl	NVRAM_XFER
 	ldmia	sp!, {lr}
 	bx	lr
 .endfunc
 .ltorg
 .func Delay9, DELAY9
 DELAY9:
 	adds	r0, r0, r0, LSL #3   /* r0 = r0 * 9 */
 DELAYLOOP:
 	beq	DELAY9_done
 	subs	r0, r0, #1
 	b	DELAYLOOP
 DELAY9_done:
 	bx	lr
 .endfunc
 .func SP_Init, SP_INIT
 SP_INIT:
 	mov	r1, #SP_SWRST
 	ldr	r0, =SP_BASE
 	str	r1, [r0, #SP_CR] /* reset the SPI */
 	mov	r1, #0
 	str	r1, [r0, #SP_CR] /* release SPI from reset state */
 	mov	r1, #SP_SPIEN
 	str	r1, [r0, #SP_MR] /* set the SPI to MASTER mode*/
 	str	r1, [r0, #SP_CR] /* enable the SPI */
 /*  My guess would be this turns on the SPI clock */
 	ldr	r3, =SPI_CGEN_BASE
 	ldr	r1, [r3, #28]
 	orr	r1, r1, #0x2000
 	str	r1, [r3, #28]
 	ldr	r1, =0x2000c01
 	str	r1, [r0, #SP_CSR0]
 	ldr	r1, =0x2000201
 	str	r1, [r0, #SP_CSR1]
 	str	r1, [r0, #SP_CSR2]
 	str	r1, [r0, #SP_CSR3]
 	ldr	r1, [r0, #SP_SR]
 	ldr	r0, [r0, #SP_RDR]
 	bx	lr
 .endfunc
 .func NVRAM_Init, NVRAM_INIT
 NVRAM_INIT:
 	ldr	r1, =SP_BASE
 	ldr	r0, [r1, #SP_RDR]
 	mov	r0, #NVRAM_CMD_RDSR
 	str	r0, [r1, #SP_TDR]
 SP_loop1:
 	ldr	r0, [r1, #SP_SR]
 	tst	r0, #SP_TDRE
 	beq	SP_loop1
 	mov	r0, #SPI_8CLOCKS
 	str	r0, [r1, #SP_TDR]
 SP_loop2:
 	ldr	r0, [r1, #SP_SR]
 	tst	r0, #SP_TDRE
 	beq	SP_loop2
 	ldr	r0, [r1, #SP_RDR]
 SP_loop3:
 	ldr	r0, [r1, #SP_SR]
 	tst	r0, #SP_RDRF
 	beq	SP_loop3
 	ldr	r0, [r1, #SP_RDR]
 	and	r0, r0, #255
 	bx	lr
 .endfunc
 .func NVRAM_Xfer, NVRAM_XFER
 	/* r0 = dest address */
 	/* r1 = not used */
 	/* r2 = src address within NVRAM */
 	/* r3 = length */
 NVRAM_XFER:
 	stmdb	sp!, {r4, r5, lr}
 	mov	r5, r0		/* save r0 (dest address) */
 	mov	r4, r3		/* save r3 (length) */
 	mov	r0, r2, LSR #5 /*  SPI memories put A8 in the command field */
 	and	r0, r0, #8
 	add	r0, r0, #NVRAM_CMD_READ
 	ldr	r1, =NVRAM_SCRATCH
 	strb	r0, [r1, #0]	/* save command in NVRAM_SCRATCH[0] */
 	strb	r2, [r1, #1]    /* save low byte of source address in NVRAM_SCRATCH[1] */
 _local1:
 	bl	NVRAM_INIT
 	tst	r0, #NVRAM_SR_RDY
 	bne	_local1
 	mov	r0, #20
 	bl	DELAY9
 	mov	r2, r4		/* length */
 	mov	r1, r5		/* dest address */
 	mov	r0, #2		/* bytes to transfer in command */
 	bl	NVRAM_XFER2
 	ldmia	sp!, {r4, r5, lr}
 	bx	lr
 .endfunc
 .func NVRAM_Xfer2, NVRAM_XFER2
 NVRAM_XFER2:
 	stmdb	sp!, {r4, r5, r6, lr}
 	ldr	r4, =SP_BASE
 	mov	r3, #0
 	cmp	r0, #0
 	bls	_local2
 	ldr	r5, =NVRAM_SCRATCH
 _local4:
 	ldrb	r6, [r5, r3]
 	str	r6, [r4, #SP_TDR]
 _local3:
 	ldr	r6, [r4, #SP_SR]
 	tst	r6, #SP_TDRE
 	beq	_local3
 	add	r3, r3, #1
 	cmp	r3, r0 /* r0 is # of bytes to send out (command+addr) */
 	blo	_local4
 _local2:
 	mov	r3, #SPI_8CLOCKS
 	str	r3, [r4, #SP_TDR]
 	ldr	r0, [r4, #SP_RDR]
 _local5:
 	ldr	r0, [r4, #SP_SR]
 	tst	r0, #SP_RDRF
 	beq	_local5
 	ldr	r0, [r4, #SP_RDR] /* what's this byte?  It's the byte read while writing the TDR -- nonsense, because the NVRAM doesn't read and write at the same time */
 	mov	r0, #0
 	cmp	r2, #0  /* r2 is # of bytes to copy in */
 	bls	_local6
 _local7:
 	ldr	r5, [r4, #SP_SR]
 	tst	r5, #SP_TDRE
 	beq	_local7
 	str	r3, [r4, #SP_TDR]  /* r3 has SPI_8CLOCKS */
 _local8:
 	ldr	r5, [r4, #SP_SR]
 	tst	r5, #SP_RDRF
 	beq	_local8
 	ldr	r5, [r4, #SP_RDR] /* but didn't we read this byte above? */
 	strb	r5, [r1], #1 /* postindexed */
 	add	r0, r0, #1
 	cmp	r0, r2
 	blo	_local7 /* since we don't send another address, the NVRAM must be capable of sequential reads */
 _local6:
 	mov	r0, #200
 	bl	DELAY9
 	ldmia	sp!, {r4, r5, r6, lr}
 	bx	lr
 #endif
 /*
 * xHCI host controller driver
 *
 * Copyright (C) 2008 Intel Corp.
 *
 * Author: Sarah Sharp
 * Some code borrowed from the Linux EHCI driver.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
 * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 * for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software Foundation,
 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */
 #ifndef __LINUX_XHCI_HCD_H
 #define __LINUX_XHCI_HCD_H
 #include <linux/usb.h>
 #include <linux/timer.h>
 #include <linux/kernel.h>
 #include "../core/hcd.h"
 /* Code sharing between pci-quirks and xhci hcd */
 #include	"xhci-ext-caps.h"
 /* xHCI PCI Configuration Registers */
 #define XHCI_SBRN_OFFSET	(0x60)
 /* Max number of USB devices for any host controller - limit in section 6.1 */
 #define MAX_HC_SLOTS		256
 /* Section 5.3.3 - MaxPorts */
 #define MAX_HC_PORTS		127
 /*
 * xHCI register interface.
 * This corresponds to the eXtensible Host Controller Interface (xHCI)
 * Revision 0.95 specification
 */
 /**
 * struct xhci_cap_regs - xHCI Host Controller Capability Registers.
 * @hc_capbase:		length of the capabilities register and HC version number
 * @hcs_params1:	HCSPARAMS1 - Structural Parameters 1
 * @hcs_params2:	HCSPARAMS2 - Structural Parameters 2
 * @hcs_params3:	HCSPARAMS3 - Structural Parameters 3
 * @hcc_params:		HCCPARAMS - Capability Parameters
 * @db_off:		DBOFF - Doorbell array offset
 * @run_regs_off:	RTSOFF - Runtime register space offset
 */
 struct xhci_cap_regs {
 	u32	hc_capbase;
 	u32	hcs_params1;
 	u32	hcs_params2;
 	u32	hcs_params3;
 	u32	hcc_params;
 	u32	db_off;
 	u32	run_regs_off;
 	/* Reserved up to (CAPLENGTH - 0x1C) */
 };
 /* hc_capbase bitmasks */
 /* bits 7:0 - how long is the Capabilities register */
 #define HC_LENGTH(p)		XHCI_HC_LENGTH(p)
 /* bits 31:16	*/
 #define HC_VERSION(p)		(((p) >> 16) & 0xffff)
 /* HCSPARAMS1 - hcs_params1 - bitmasks */
 /* bits 0:7, Max Device Slots */
 #define HCS_MAX_SLOTS(p)	(((p) >> 0) & 0xff)
 #define HCS_SLOTS_MASK		0xff
 /* bits 8:18, Max Interrupters */
 #define HCS_MAX_INTRS(p)	(((p) >> 8) & 0x7ff)
 /* bits 24:31, Max Ports - max value is 0x7F = 127 ports */
 #define HCS_MAX_PORTS(p)	(((p) >> 24) & 0x7f)
 /* HCSPARAMS2 - hcs_params2 - bitmasks */
 /* bits 0:3, frames or uframes that SW needs to queue transactions
 * ahead of the HW to meet periodic deadlines */
 #define HCS_IST(p)		(((p) >> 0) & 0xf)
 /* bits 4:7, max number of Event Ring segments */
 #define HCS_ERST_MAX(p)		(((p) >> 4) & 0xf)
 /* bit 26 Scratchpad restore - for save/restore HW state - not used yet */
 /* bits 27:31 number of Scratchpad buffers SW must allocate for the HW */
 #define HCS_MAX_SCRATCHPAD(p)   (((p) >> 27) & 0x1f)
 /* HCSPARAMS3 - hcs_params3 - bitmasks */
 /* bits 0:7, Max U1 to U0 latency for the roothub ports */
 #define HCS_U1_LATENCY(p)	(((p) >> 0) & 0xff)
 /* bits 16:31, Max U2 to U0 latency for the roothub ports */
 #define HCS_U2_LATENCY(p)	(((p) >> 16) & 0xffff)
 /* HCCPARAMS - hcc_params - bitmasks */
 /* true: HC can use 64-bit address pointers */
 #define HCC_64BIT_ADDR(p)	((p) & (1 << 0))
 /* true: HC can do bandwidth negotiation */
 #define HCC_BANDWIDTH_NEG(p)	((p) & (1 << 1))
 /* true: HC uses 64-byte Device Context structures
 * FIXME 64-byte context structures aren't supported yet.
 */
 #define HCC_64BYTE_CONTEXT(p)	((p) & (1 << 2))
 /* true: HC has port power switches */
 #define HCC_PPC(p)		((p) & (1 << 3))
 /* true: HC has port indicators */
 #define HCS_INDICATOR(p)	((p) & (1 << 4))
 /* true: HC has Light HC Reset Capability */
 #define HCC_LIGHT_RESET(p)	((p) & (1 << 5))
 /* true: HC supports latency tolerance messaging */
 #define HCC_LTC(p)		((p) & (1 << 6))
 /* true: no secondary Stream ID Support */
 #define HCC_NSS(p)		((p) & (1 << 7))
 /* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */
 #define HCC_MAX_PSA		(1 << ((((p) >> 12) & 0xf) + 1))
 /* Extended Capabilities pointer from PCI base - section 5.3.6 */
 #define HCC_EXT_CAPS(p)		XHCI_HCC_EXT_CAPS(p)
 /* db_off bitmask - bits 0:1 reserved */
 #define	DBOFF_MASK	(~0x3)
 /* run_regs_off bitmask - bits 0:4 reserved */
 #define	RTSOFF_MASK	(~0x1f)
 /* Number of registers per port */
 #define	NUM_PORT_REGS	4
 /**
 * struct xhci_op_regs - xHCI Host Controller Operational Registers.
 * @command:		USBCMD - xHC command register
 * @status:		USBSTS - xHC status register
 * @page_size:		This indicates the page size that the host controller
 * 			supports.  If bit n is set, the HC supports a page size
 * 			of 2^(n+12), up to a 128MB page size.
 * 			4K is the minimum page size.
 * @cmd_ring:		CRP - 64-bit Command Ring Pointer
 * @dcbaa_ptr:		DCBAAP - 64-bit Device Context Base Address Array Pointer
 * @config_reg:		CONFIG - Configure Register
 * @port_status_base:	PORTSCn - base address for Port Status and Control
 * 			Each port has a Port Status and Control register,
 * 			followed by a Port Power Management Status and Control
 * 			register, a Port Link Info register, and a reserved
 * 			register.
 * @port_power_base:	PORTPMSCn - base address for
 * 			Port Power Management Status and Control
 * @port_link_base:	PORTLIn - base address for Port Link Info (current
 * 			Link PM state and control) for USB 2.1 and USB 3.0
 * 			devices.
 */
 struct xhci_op_regs {
 	u32	command;
 	u32	status;
 	u32	page_size;
 	u32	reserved1;
 	u32	reserved2;
 	u32	dev_notification;
 	u64	cmd_ring;
 	/* rsvd: offset 0x20-2F */
 	u32	reserved3[4];
 	u64	dcbaa_ptr;
 	u32	config_reg;
 	/* rsvd: offset 0x3C-3FF */
 	u32	reserved4[241];
 	/* port 1 registers, which serve as a base address for other ports */
 	u32	port_status_base;
 	u32	port_power_base;
 	u32	port_link_base;
 	u32	reserved5;
 	/* registers for ports 2-255 */
 	u32	reserved6[NUM_PORT_REGS*254];
 };
 /* USBCMD - USB command - command bitmasks */
 /* start/stop HC execution - do not write unless HC is halted*/
 #define CMD_RUN		XHCI_CMD_RUN
 /* Reset HC - resets internal HC state machine and all registers (except
 * PCI config regs).  HC does NOT drive a USB reset on the downstream ports.
 * The xHCI driver must reinitialize the xHC after setting this bit.
 */
 #define CMD_RESET	(1 << 1)
 /* Event Interrupt Enable - a '1' allows interrupts from the host controller */
 #define CMD_EIE		XHCI_CMD_EIE
 /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */
 #define CMD_HSEIE	XHCI_CMD_HSEIE
 /* bits 4:6 are reserved (and should be preserved on writes). */
 /* light reset (port status stays unchanged) - reset completed when this is 0 */
 #define CMD_LRESET	(1 << 7)
 /* FIXME: ignoring host controller save/restore state for now. */
 #define CMD_CSS		(1 << 8)
 #define CMD_CRS		(1 << 9)
 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
 #define CMD_EWE		XHCI_CMD_EWE
 /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root
 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off.
 * '0' means the xHC can power it off if all ports are in the disconnect,
 * disabled, or powered-off state.
 */
 #define CMD_PM_INDEX	(1 << 11)
 /* bits 12:31 are reserved (and should be preserved on writes). */
 /* USBSTS - USB status - status bitmasks */
 /* HC not running - set to 1 when run/stop bit is cleared. */
 #define STS_HALT	XHCI_STS_HALT
 /* serious error, e.g. PCI parity error.  The HC will clear the run/stop bit. */
 #define STS_FATAL	(1 << 2)
 /* event interrupt - clear this prior to clearing any IP flags in IR set*/
 #define STS_EINT	(1 << 3)
 /* port change detect */
 #define STS_PORT	(1 << 4)
 /* bits 5:7 reserved and zeroed */
 /* save state status - '1' means xHC is saving state */
 #define STS_SAVE	(1 << 8)
 /* restore state status - '1' means xHC is restoring state */
 #define STS_RESTORE	(1 << 9)
 /* true: save or restore error */
 #define STS_SRE		(1 << 10)
 /* true: Controller Not Ready to accept doorbell or op reg writes after reset */
 #define STS_CNR		XHCI_STS_CNR
 /* true: internal Host Controller Error - SW needs to reset and reinitialize */
 #define STS_HCE		(1 << 12)
 /* bits 13:31 reserved and should be preserved */
 /*
 * DNCTRL - Device Notification Control Register - dev_notification bitmasks
 * Generate a device notification event when the HC sees a transaction with a
 * notification type that matches a bit set in this bit field.
 */
 #define	DEV_NOTE_MASK		(0xffff)
 #define ENABLE_DEV_NOTE(x)	(1 << x)
 /* Most of the device notification types should only be used for debug.
 * SW does need to pay attention to function wake notifications.
 */
 #define	DEV_NOTE_FWAKE		ENABLE_DEV_NOTE(1)
 /* CRCR - Command Ring Control Register - cmd_ring bitmasks */
 /* bit 0 is the command ring cycle state */
 /* stop ring operation after completion of the currently executing command */
 #define CMD_RING_PAUSE		(1 << 1)
 /* stop ring immediately - abort the currently executing command */
 #define CMD_RING_ABORT		(1 << 2)
 /* true: command ring is running */
 #define CMD_RING_RUNNING	(1 << 3)
 /* bits 4:5 reserved and should be preserved */
 /* Command Ring pointer - bit mask for the lower 32 bits. */
 #define CMD_RING_RSVD_BITS	(0x3f)
 /* CONFIG - Configure Register - config_reg bitmasks */
 /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */
 #define MAX_DEVS(p)	((p) & 0xff)
 /* bits 8:31 - reserved and should be preserved */
 /* PORTSC - Port Status and Control Register - port_status_base bitmasks */
 /* true: device connected */
 #define PORT_CONNECT	(1 << 0)
 /* true: port enabled */
 #define PORT_PE		(1 << 1)
 /* bit 2 reserved and zeroed */
 /* true: port has an over-current condition */
 #define PORT_OC		(1 << 3)
 /* true: port reset signaling asserted */
 #define PORT_RESET	(1 << 4)
 /* Port Link State - bits 5:8
 * A read gives the current link PM state of the port,
 * a write with Link State Write Strobe set sets the link state.
 */
 /* true: port has power (see HCC_PPC) */
 #define PORT_POWER	(1 << 9)
 /* bits 10:13 indicate device speed:
 * 0 - undefined speed - port hasn't be initialized by a reset yet
 * 1 - full speed
 * 2 - low speed
 * 3 - high speed
 * 4 - super speed
 * 5-15 reserved
 */
 #define DEV_SPEED_MASK		(0xf << 10)
 #define	XDEV_FS			(0x1 << 10)
 #define	XDEV_LS			(0x2 << 10)
 #define	XDEV_HS			(0x3 << 10)
 #define	XDEV_SS			(0x4 << 10)
 #define DEV_UNDEFSPEED(p)	(((p) & DEV_SPEED_MASK) == (0x0<<10))
 #define DEV_FULLSPEED(p)	(((p) & DEV_SPEED_MASK) == XDEV_FS)
 #define DEV_LOWSPEED(p)		(((p) & DEV_SPEED_MASK) == XDEV_LS)
 #define DEV_HIGHSPEED(p)	(((p) & DEV_SPEED_MASK) == XDEV_HS)
 #define DEV_SUPERSPEED(p)	(((p) & DEV_SPEED_MASK) == XDEV_SS)
 /* Bits 20:23 in the Slot Context are the speed for the device */
 #define	SLOT_SPEED_FS		(XDEV_FS << 10)
 #define	SLOT_SPEED_LS		(XDEV_LS << 10)
 #define	SLOT_SPEED_HS		(XDEV_HS << 10)
 #define	SLOT_SPEED_SS		(XDEV_SS << 10)
 /* Port Indicator Control */
 #define PORT_LED_OFF	(0 << 14)
 #define PORT_LED_AMBER	(1 << 14)
 #define PORT_LED_GREEN	(2 << 14)
 #define PORT_LED_MASK	(3 << 14)
 /* Port Link State Write Strobe - set this when changing link state */
 #define PORT_LINK_STROBE	(1 << 16)
 /* true: connect status change */
 #define PORT_CSC	(1 << 17)
 /* true: port enable change */
 #define PORT_PEC	(1 << 18)
 /* true: warm reset for a USB 3.0 device is done.  A "hot" reset puts the port
 * into an enabled state, and the device into the default state.  A "warm" reset
 * also resets the link, forcing the device through the link training sequence.
 * SW can also look at the Port Reset register to see when warm reset is done.
 */
 #define PORT_WRC	(1 << 19)
 /* true: over-current change */
 #define PORT_OCC	(1 << 20)
 /* true: reset change - 1 to 0 transition of PORT_RESET */
 #define PORT_RC		(1 << 21)
 /* port link status change - set on some port link state transitions:
 *  Transition				Reason
 *  ------------------------------------------------------------------------------
 *  - U3 to Resume			Wakeup signaling from a device
 *  - Resume to Recovery to U0		USB 3.0 device resume
 *  - Resume to U0			USB 2.0 device resume
 *  - U3 to Recovery to U0		Software resume of USB 3.0 device complete
 *  - U3 to U0				Software resume of USB 2.0 device complete
 *  - U2 to U0				L1 resume of USB 2.1 device complete
 *  - U0 to U0 (???)			L1 entry rejection by USB 2.1 device
 *  - U0 to disabled			L1 entry error with USB 2.1 device
 *  - Any state to inactive		Error on USB 3.0 port
 */
 #define PORT_PLC	(1 << 22)
 /* port configure error change - port failed to configure its link partner */
 #define PORT_CEC	(1 << 23)
 /* bit 24 reserved */
 /* wake on connect (enable) */
 #define PORT_WKCONN_E	(1 << 25)
 /* wake on disconnect (enable) */
 #define PORT_WKDISC_E	(1 << 26)
 /* wake on over-current (enable) */
 #define PORT_WKOC_E	(1 << 27)
 /* bits 28:29 reserved */
 /* true: device is removable - for USB 3.0 roothub emulation */
 #define PORT_DEV_REMOVE	(1 << 30)
 /* Initiate a warm port reset - complete when PORT_WRC is '1' */
 #define PORT_WR		(1 << 31)
 /* Port Power Management Status and Control - port_power_base bitmasks */
 /* Inactivity timer value for transitions into U1, in microseconds.
 * Timeout can be up to 127us.  0xFF means an infinite timeout.
 */
 #define PORT_U1_TIMEOUT(p)	((p) & 0xff)
 /* Inactivity timer value for transitions into U2 */
 #define PORT_U2_TIMEOUT(p)	(((p) & 0xff) << 8)
 /* Bits 24:31 for port testing */
 /**
 * struct xhci_intr_reg - Interrupt Register Set
 * @irq_pending:	IMAN - Interrupt Management Register.  Used to enable
 *			interrupts and check for pending interrupts.
 * @irq_control:	IMOD - Interrupt Moderation Register.
 * 			Used to throttle interrupts.
 * @erst_size:		Number of segments in the Event Ring Segment Table (ERST).
 * @erst_base:		ERST base address.
 * @erst_dequeue:	Event ring dequeue pointer.
 *
 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event
 * Ring Segment Table (ERST) associated with it.  The event ring is comprised of
 * multiple segments of the same size.  The HC places events on the ring and
 * "updates the Cycle bit in the TRBs to indicate to software the current
 * position of the Enqueue Pointer." The HCD (Linux) processes those events and
 * updates the dequeue pointer.
 */
 struct xhci_intr_reg {
 	u32	irq_pending;
 	u32	irq_control;
 	u32	erst_size;
 	u32	rsvd;
 	u64	erst_base;
 	u64	erst_dequeue;
 };
 /* irq_pending bitmasks */
 #define	ER_IRQ_PENDING(p)	((p) & 0x1)
 /* bits 2:31 need to be preserved */
 /* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */
 #define	ER_IRQ_CLEAR(p)		((p) & 0xfffffffe)
 #define	ER_IRQ_ENABLE(p)	((ER_IRQ_CLEAR(p)) | 0x2)
 #define	ER_IRQ_DISABLE(p)	((ER_IRQ_CLEAR(p)) & ~(0x2))
 /* irq_control bitmasks */
 /* Minimum interval between interrupts (in 250ns intervals).  The interval
 * between interrupts will be longer if there are no events on the event ring.
 * Default is 4000 (1 ms).
 */
 #define ER_IRQ_INTERVAL_MASK	(0xffff)
 /* Counter used to count down the time to the next interrupt - HW use only */
 #define ER_IRQ_COUNTER_MASK	(0xffff << 16)
 /* erst_size bitmasks */
 /* Preserve bits 16:31 of erst_size */
 #define	ERST_SIZE_MASK		(0xffff << 16)
 /* erst_dequeue bitmasks */
 /* Dequeue ERST Segment Index (DESI) - Segment number (or alias)
 * where the current dequeue pointer lies.  This is an optional HW hint.
 */
 #define ERST_DESI_MASK		(0x7)
 /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by
 * a work queue (or delayed service routine)?
 */
 #define ERST_EHB		(1 << 3)
 #define ERST_PTR_MASK		(0xf)
 /**
 * struct xhci_run_regs
 * @microframe_index:
 * 		MFINDEX - current microframe number
 *
 * Section 5.5 Host Controller Runtime Registers:
 * "Software should read and write these registers using only Dword (32 bit)
 * or larger accesses"
 */
 struct xhci_run_regs {
 	u32			microframe_index;
 	u32			rsvd[7];
 	struct xhci_intr_reg	ir_set[128];
 };
 /**
 * struct doorbell_array
 *
 * Section 5.6
 */
 struct xhci_doorbell_array {
 	u32	doorbell[256];
 };
 #define	DB_TARGET_MASK		0xFFFFFF00
 #define	DB_STREAM_ID_MASK	0x0000FFFF
 #define	DB_TARGET_HOST		0x0
 #define	DB_STREAM_ID_HOST	0x0
 #define	DB_MASK			(0xff << 8)
 /* Endpoint Target - bits 0:7 */
 #define EPI_TO_DB(p)		(((p) + 1) & 0xff)
 /**
 * struct xhci_container_ctx
 * @type: Type of context.  Used to calculated offsets to contained contexts.
 * @size: Size of the context data
 * @bytes: The raw context data given to HW
 * @dma: dma address of the bytes
 *
 * Represents either a Device or Input context.  Holds a pointer to the raw
 * memory used for the context (bytes) and dma address of it (dma).
 */
 struct xhci_container_ctx {
 	unsigned type;
 #define XHCI_CTX_TYPE_DEVICE  0x1
 #define XHCI_CTX_TYPE_INPUT   0x2
 	int size;
 	u8 *bytes;
 	dma_addr_t dma;
 };
 /**
 * struct xhci_slot_ctx
 * @dev_info:	Route string, device speed, hub info, and last valid endpoint
 * @dev_info2:	Max exit latency for device number, root hub port number
 * @tt_info:	tt_info is used to construct split transaction tokens
 * @dev_state:	slot state and device address
 *
 * Slot Context - section 6.2.1.1.  This assumes the HC uses 32-byte context
 * structures.  If the HC uses 64-byte contexts, there is an additional 32 bytes
 * reserved at the end of the slot context for HC internal use.
 */
 struct xhci_slot_ctx {
 	u32	dev_info;
 	u32	dev_info2;
 	u32	tt_info;
 	u32	dev_state;
 	/* offset 0x10 to 0x1f reserved for HC internal use */
 	u32	reserved[4];
 };
 /* dev_info bitmasks */
 /* Route String - 0:19 */
 #define ROUTE_STRING_MASK	(0xfffff)
 /* Device speed - values defined by PORTSC Device Speed field - 20:23 */
 #define DEV_SPEED	(0xf << 20)
 /* bit 24 reserved */
 /* Is this LS/FS device connected through a HS hub? - bit 25 */
 #define DEV_MTT		(0x1 << 25)
 /* Set if the device is a hub - bit 26 */
 #define DEV_HUB		(0x1 << 26)
 /* Index of the last valid endpoint context in this device context - 27:31 */
 #define LAST_CTX_MASK	(0x1f << 27)
 #define LAST_CTX(p)	((p) << 27)
 #define LAST_CTX_TO_EP_NUM(p)	(((p) >> 27) - 1)
 #define SLOT_FLAG	(1 << 0)
 #define EP0_FLAG	(1 << 1)
 /* dev_info2 bitmasks */
 /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */
 #define MAX_EXIT	(0xffff)
 /* Root hub port number that is needed to access the USB device */
 #define ROOT_HUB_PORT(p)	(((p) & 0xff) << 16)
 /* tt_info bitmasks */
 /*
 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub
 * The Slot ID of the hub that isolates the high speed signaling from
 * this low or full-speed device.  '0' if attached to root hub port.
 */
 #define TT_SLOT		(0xff)
 /*
 * The number of the downstream facing port of the high-speed hub
 * '0' if the device is not low or full speed.
 */
 #define TT_PORT		(0xff << 8)
 /* dev_state bitmasks */
 /* USB device address - assigned by the HC */
 #define DEV_ADDR_MASK	(0xff)
 /* bits 8:26 reserved */
 /* Slot state */
 #define SLOT_STATE	(0x1f << 27)
 #define GET_SLOT_STATE(p)	(((p) & (0x1f << 27)) >> 27)
 /**
 * struct xhci_ep_ctx
 * @ep_info:	endpoint state, streams, mult, and interval information.
 * @ep_info2:	information on endpoint type, max packet size, max burst size,
 * 		error count, and whether the HC will force an event for all
 * 		transactions.
 * @deq:	64-bit ring dequeue pointer address.  If the endpoint only
 * 		defines one stream, this points to the endpoint transfer ring.
 * 		Otherwise, it points to a stream context array, which has a
 * 		ring pointer for each flow.
 * @tx_info:
 * 		Average TRB lengths for the endpoint ring and
 * 		max payload within an Endpoint Service Interval Time (ESIT).
 *
 * Endpoint Context - section 6.2.1.2.  This assumes the HC uses 32-byte context
 * structures.  If the HC uses 64-byte contexts, there is an additional 32 bytes
 * reserved at the end of the endpoint context for HC internal use.
 */
 struct xhci_ep_ctx {
 	u32	ep_info;
 	u32	ep_info2;
 	u64	deq;
 	u32	tx_info;
 	/* offset 0x14 - 0x1f reserved for HC internal use */
 	u32	reserved[3];
 };
 /* ep_info bitmasks */
 /*
 * Endpoint State - bits 0:2
 * 0 - disabled
 * 1 - running
 * 2 - halted due to halt condition - ok to manipulate endpoint ring
 * 3 - stopped
 * 4 - TRB error
 * 5-7 - reserved
 */
 #define EP_STATE_MASK		(0xf)
 #define EP_STATE_DISABLED	0
 #define EP_STATE_RUNNING	1
 #define EP_STATE_HALTED		2
 #define EP_STATE_STOPPED	3
 #define EP_STATE_ERROR		4
 /* Mult - Max number of burtst within an interval, in EP companion desc. */
 #define EP_MULT(p)		((p & 0x3) << 8)
 /* bits 10:14 are Max Primary Streams */
 /* bit 15 is Linear Stream Array */
 /* Interval - period between requests to an endpoint - 125u increments. */
 #define EP_INTERVAL(p)		((p & 0xff) << 16)
 /* ep_info2 bitmasks */
 /*
 * Force Event - generate transfer events for all TRBs for this endpoint
 * This will tell the HC to ignore the IOC and ISP flags (for debugging only).
 */
 #define	FORCE_EVENT	(0x1)
 #define ERROR_COUNT(p)	(((p) & 0x3) << 1)
 #define EP_TYPE(p)	((p) << 3)
 #define ISOC_OUT_EP	1
 #define BULK_OUT_EP	2
 #define INT_OUT_EP	3
 #define CTRL_EP		4
 #define ISOC_IN_EP	5
 #define BULK_IN_EP	6
 #define INT_IN_EP	7
 /* bit 6 reserved */
 /* bit 7 is Host Initiate Disable - for disabling stream selection */
 #define MAX_BURST(p)	(((p)&0xff) << 8)
 #define MAX_PACKET(p)	(((p)&0xffff) << 16)
 /**
 * struct xhci_input_control_context
 * Input control context; see section 6.2.5.
 *
 * @drop_context:	set the bit of the endpoint context you want to disable
 * @add_context:	set the bit of the endpoint context you want to enable
 */
 struct xhci_input_control_ctx {
 	u32	drop_flags;
 	u32	add_flags;
 	u32	rsvd2[6];
 };
 /* drop context bitmasks */
 #define	DROP_EP(x)	(0x1 << x)
 /* add context bitmasks */
 #define	ADD_EP(x)	(0x1 << x)
 struct xhci_virt_device {
 	/*
 	 * Commands to the hardware are passed an "input context" that
 	 * tells the hardware what to change in its data structures.
 	 * The hardware will return changes in an "output context" that
 	 * software must allocate for the hardware.  We need to keep
 	 * track of input and output contexts separately because
 	 * these commands might fail and we don't trust the hardware.
 	 */
 	struct xhci_container_ctx       *out_ctx;
 	/* Used for addressing devices and configuration changes */
 	struct xhci_container_ctx       *in_ctx;
 	/* FIXME when stream support is added */
 	struct xhci_ring		*ep_rings[31];
 	/* Temporary storage in case the configure endpoint command fails and we
 	 * have to restore the device state to the previous state
 	 */
 	struct xhci_ring		*new_ep_rings[31];
 	struct completion		cmd_completion;
 	/* Status of the last command issued for this device */
 	u32				cmd_status;
 };
 /**
 * struct xhci_device_context_array
 * @dev_context_ptr	array of 64-bit DMA addresses for device contexts
 */
 struct xhci_device_context_array {
 	/* 64-bit device addresses; we only write 32-bit addresses */
 	u64			dev_context_ptrs[MAX_HC_SLOTS];
 	/* private xHCD pointers */
 	dma_addr_t	dma;
 };
 /* TODO: write function to set the 64-bit device DMA address */
 /*
 * TODO: change this to be dynamically sized at HC mem init time since the HC
 * might not be able to handle the maximum number of devices possible.
 */
 struct xhci_stream_ctx {
 	/* 64-bit stream ring address, cycle state, and stream type */
 	u64	stream_ring;
 	/* offset 0x14 - 0x1f reserved for HC internal use */
 	u32	reserved[2];
 };
 struct xhci_transfer_event {
 	/* 64-bit buffer address, or immediate data */
 	u64	buffer;
 	u32	transfer_len;
 	/* This field is interpreted differently based on the type of TRB */
 	u32	flags;
 };
 /** Transfer Event bit fields **/
 #define	TRB_TO_EP_ID(p)	(((p) >> 16) & 0x1f)
 /* Completion Code - only applicable for some types of TRBs */
 #define	COMP_CODE_MASK		(0xff << 24)
 #define GET_COMP_CODE(p)	(((p) & COMP_CODE_MASK) >> 24)
 #define COMP_SUCCESS	1
 /* Data Buffer Error */
 #define COMP_DB_ERR	2
 /* Babble Detected Error */
 #define COMP_BABBLE	3
 /* USB Transaction Error */
 #define COMP_TX_ERR	4
 /* TRB Error - some TRB field is invalid */
 #define COMP_TRB_ERR	5
 /* Stall Error - USB device is stalled */
 #define COMP_STALL	6
 /* Resource Error - HC doesn't have memory for that device configuration */
 #define COMP_ENOMEM	7
 /* Bandwidth Error - not enough room in schedule for this dev config */
 #define COMP_BW_ERR	8
 /* No Slots Available Error - HC ran out of device slots */
 #define COMP_ENOSLOTS	9
 /* Invalid Stream Type Error */
 #define COMP_STREAM_ERR	10
 /* Slot Not Enabled Error - doorbell rung for disabled device slot */
 #define COMP_EBADSLT	11
 /* Endpoint Not Enabled Error */
 #define COMP_EBADEP	12
 /* Short Packet */
 #define COMP_SHORT_TX	13
 /* Ring Underrun - doorbell rung for an empty isoc OUT ep ring */
 #define COMP_UNDERRUN	14
 /* Ring Overrun - isoc IN ep ring is empty when ep is scheduled to RX */
 #define COMP_OVERRUN	15
 /* Virtual Function Event Ring Full Error */
 #define COMP_VF_FULL	16
 /* Parameter Error - Context parameter is invalid */
 #define COMP_EINVAL	17
 /* Bandwidth Overrun Error - isoc ep exceeded its allocated bandwidth */
 #define COMP_BW_OVER	18
 /* Context State Error - illegal context state transition requested */
 #define COMP_CTX_STATE	19
 /* No Ping Response Error - HC didn't get PING_RESPONSE in time to TX */
 #define COMP_PING_ERR	20
 /* Event Ring is full */
 #define COMP_ER_FULL	21
 /* Missed Service Error - HC couldn't service an isoc ep within interval */
 #define COMP_MISSED_INT	23
 /* Successfully stopped command ring */
 #define COMP_CMD_STOP	24
 /* Successfully aborted current command and stopped command ring */
 #define COMP_CMD_ABORT	25
 /* Stopped - transfer was terminated by a stop endpoint command */
 #define COMP_STOP	26
 /* Same as COMP_EP_STOPPED, but the transfered length in the event is invalid */
 #define COMP_STOP_INVAL	27
 /* Control Abort Error - Debug Capability - control pipe aborted */
 #define COMP_DBG_ABORT	28
 /* TRB type 29 and 30 reserved */
 /* Isoc Buffer Overrun - an isoc IN ep sent more data than could fit in TD */
 #define COMP_BUFF_OVER	31
 /* Event Lost Error - xHC has an "internal event overrun condition" */
 #define COMP_ISSUES	32
 /* Undefined Error - reported when other error codes don't apply */
 #define COMP_UNKNOWN	33
 /* Invalid Stream ID Error */
 #define COMP_STRID_ERR	34
 /* Secondary Bandwidth Error - may be returned by a Configure Endpoint cmd */
 /* FIXME - check for this */
 #define COMP_2ND_BW_ERR	35
 /* Split Transaction Error */
 #define	COMP_SPLIT_ERR	36
 struct xhci_link_trb {
 	/* 64-bit segment pointer*/
 	u64 segment_ptr;
 	u32 intr_target;
 	u32 control;
 };
 /* control bitfields */
 #define LINK_TOGGLE	(0x1<<1)
 /* Command completion event TRB */
 struct xhci_event_cmd {
 	/* Pointer to command TRB, or the value passed by the event data trb */
 	u64 cmd_trb;
 	u32 status;
 	u32 flags;
 };
 /* flags bitmasks */
 /* bits 16:23 are the virtual function ID */
 /* bits 24:31 are the slot ID */
 #define TRB_TO_SLOT_ID(p)	(((p) & (0xff<<24)) >> 24)
 #define SLOT_ID_FOR_TRB(p)	(((p) & 0xff) << 24)
 /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */
 #define TRB_TO_EP_INDEX(p)		((((p) & (0x1f << 16)) >> 16) - 1)
 #define	EP_ID_FOR_TRB(p)		((((p) + 1) & 0x1f) << 16)
 /* Port Status Change Event TRB fields */
 /* Port ID - bits 31:24 */
 #define GET_PORT_ID(p)		(((p) & (0xff << 24)) >> 24)
 /* Normal TRB fields */
 /* transfer_len bitmasks - bits 0:16 */
 #define	TRB_LEN(p)		((p) & 0x1ffff)
 /* TD size - number of bytes remaining in the TD (including this TRB):
 * bits 17 - 21.  Shift the number of bytes by 10. */
 #define TD_REMAINDER(p)		((((p) >> 10) & 0x1f) << 17)
 /* Interrupter Target - which MSI-X vector to target the completion event at */
 #define TRB_INTR_TARGET(p)	(((p) & 0x3ff) << 22)
 #define GET_INTR_TARGET(p)	(((p) >> 22) & 0x3ff)
 /* Cycle bit - indicates TRB ownership by HC or HCD */
 #define TRB_CYCLE		(1<<0)
 /*
 * Force next event data TRB to be evaluated before task switch.
 * Used to pass OS data back after a TD completes.
 */
 #define TRB_ENT			(1<<1)
 /* Interrupt on short packet */
 #define TRB_ISP			(1<<2)
 /* Set PCIe no snoop attribute */
 #define TRB_NO_SNOOP		(1<<3)
 /* Chain multiple TRBs into a TD */
 #define TRB_CHAIN		(1<<4)
 /* Interrupt on completion */
 #define TRB_IOC			(1<<5)
 /* The buffer pointer contains immediate data */
 #define TRB_IDT			(1<<6)
 /* Control transfer TRB specific fields */
 #define TRB_DIR_IN		(1<<16)
 struct xhci_generic_trb {
 	u32 field[4];
 };
 union xhci_trb {
 	struct xhci_link_trb		link;
 	struct xhci_transfer_event	trans_event;
 	struct xhci_event_cmd		event_cmd;
 	struct xhci_generic_trb		generic;
 };
 /* TRB bit mask */
 #define	TRB_TYPE_BITMASK	(0xfc00)
 #define TRB_TYPE(p)		((p) << 10)
 /* TRB type IDs */
 /* bulk, interrupt, isoc scatter/gather, and control data stage */
 #define TRB_NORMAL		1
 /* setup stage for control transfers */
 #define TRB_SETUP		2
 /* data stage for control transfers */
 #define TRB_DATA		3
 /* status stage for control transfers */
 #define TRB_STATUS		4
 /* isoc transfers */
 #define TRB_ISOC		5
 /* TRB for linking ring segments */
 #define TRB_LINK		6
 #define TRB_EVENT_DATA		7
 /* Transfer Ring No-op (not for the command ring) */
 #define TRB_TR_NOOP		8
 /* Command TRBs */
 /* Enable Slot Command */
 #define TRB_ENABLE_SLOT		9
 /* Disable Slot Command */
 #define TRB_DISABLE_SLOT	10
 /* Address Device Command */
 #define TRB_ADDR_DEV		11
 /* Configure Endpoint Command */
 #define TRB_CONFIG_EP		12
 /* Evaluate Context Command */
 #define TRB_EVAL_CONTEXT	13
 /* Reset Endpoint Command */
 #define TRB_RESET_EP		14
 /* Stop Transfer Ring Command */
 #define TRB_STOP_RING		15
 /* Set Transfer Ring Dequeue Pointer Command */
 #define TRB_SET_DEQ		16
 /* Reset Device Command */
 #define TRB_RESET_DEV		17
 /* Force Event Command (opt) */
 #define TRB_FORCE_EVENT		18
 /* Negotiate Bandwidth Command (opt) */
 #define TRB_NEG_BANDWIDTH	19
 /* Set Latency Tolerance Value Command (opt) */
 #define TRB_SET_LT		20
 /* Get port bandwidth Command */
 #define TRB_GET_BW		21
 /* Force Header Command - generate a transaction or link management packet */
 #define TRB_FORCE_HEADER	22
 /* No-op Command - not for transfer rings */
 #define TRB_CMD_NOOP		23
 /* TRB IDs 24-31 reserved */
 /* Event TRBS */
 /* Transfer Event */
 #define TRB_TRANSFER		32
 /* Command Completion Event */
 #define TRB_COMPLETION		33
 /* Port Status Change Event */
 #define TRB_PORT_STATUS		34
 /* Bandwidth Request Event (opt) */
 #define TRB_BANDWIDTH_EVENT	35
 /* Doorbell Event (opt) */
 #define TRB_DOORBELL		36
 /* Host Controller Event */
 #define TRB_HC_EVENT		37
 /* Device Notification Event - device sent function wake notification */
 #define TRB_DEV_NOTE		38
 /* MFINDEX Wrap Event - microframe counter wrapped */
 #define TRB_MFINDEX_WRAP	39
 /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */
 /*
 * TRBS_PER_SEGMENT must be a multiple of 4,
 * since the command ring is 64-byte aligned.
 * It must also be greater than 16.
 */
 #define TRBS_PER_SEGMENT	64
 #define SEGMENT_SIZE		(TRBS_PER_SEGMENT*16)
 /* TRB buffer pointers can't cross 64KB boundaries */
 #define TRB_MAX_BUFF_SHIFT		16
 #define TRB_MAX_BUFF_SIZE	(1 << TRB_MAX_BUFF_SHIFT)
 struct xhci_segment {
 	union xhci_trb		*trbs;
 	/* private to HCD */
 	struct xhci_segment	*next;
 	dma_addr_t		dma;
 };
 struct xhci_td {
 	struct list_head	td_list;
 	struct list_head	cancelled_td_list;
 	struct urb		*urb;
 	struct xhci_segment	*start_seg;
 	union xhci_trb		*first_trb;
 	union xhci_trb		*last_trb;
 };
 struct xhci_ring {
 	struct xhci_segment	*first_seg;
 	union  xhci_trb		*enqueue;
 	struct xhci_segment	*enq_seg;
 	unsigned int		enq_updates;
 	union  xhci_trb		*dequeue;
 	struct xhci_segment	*deq_seg;
 	unsigned int		deq_updates;
 	struct list_head	td_list;
 	/* ----  Related to URB cancellation ---- */
 	struct list_head	cancelled_td_list;
 	unsigned int		cancels_pending;
 	unsigned int		state;
 #define SET_DEQ_PENDING		(1 << 0)
 #define EP_HALTED		(1 << 1)
 	/* The TRB that was last reported in a stopped endpoint ring */
 	union xhci_trb		*stopped_trb;
 	struct xhci_td		*stopped_td;
 	/*
 	 * Write the cycle state into the TRB cycle field to give ownership of
 	 * the TRB to the host controller (if we are the producer), or to check
 	 * if we own the TRB (if we are the consumer).  See section 4.9.1.
 	 */
 	u32			cycle_state;
 };
 struct xhci_dequeue_state {
 	struct xhci_segment *new_deq_seg;
 	union xhci_trb *new_deq_ptr;
 	int new_cycle_state;
 };
 struct xhci_erst_entry {
 	/* 64-bit event ring segment address */
 	u64	seg_addr;
 	u32	seg_size;
 	/* Set to zero */
 	u32	rsvd;
 };
 struct xhci_erst {
 	struct xhci_erst_entry	*entries;
 	unsigned int		num_entries;
 	/* xhci->event_ring keeps track of segment dma addresses */
 	dma_addr_t		erst_dma_addr;
 	/* Num entries the ERST can contain */
 	unsigned int		erst_size;
 };
 struct xhci_scratchpad {
 	u64 *sp_array;
 	dma_addr_t sp_dma;
 	void **sp_buffers;
 	dma_addr_t *sp_dma_buffers;
 };
 /*
 * Each segment table entry is 4*32bits long.  1K seems like an ok size:
 * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table,
 * meaning 64 ring segments.
 * Initial allocated size of the ERST, in number of entries */
 #define	ERST_NUM_SEGS	1
 /* Initial allocated size of the ERST, in number of entries */
 #define	ERST_SIZE	64
 /* Initial number of event segment rings allocated */
 #define	ERST_ENTRIES	1
 /* Poll every 60 seconds */
 #define	POLL_TIMEOUT	60
 /* XXX: Make these module parameters */
 /* There is one ehci_hci structure per controller */
 struct xhci_hcd {
 	/* glue to PCI and HCD framework */
 	struct xhci_cap_regs __iomem *cap_regs;
 	struct xhci_op_regs __iomem *op_regs;
 	struct xhci_run_regs __iomem *run_regs;
 	struct xhci_doorbell_array __iomem *dba;
 	/* Our HCD's current interrupter register set */
 	struct	xhci_intr_reg __iomem *ir_set;
 	/* Cached register copies of read-only HC data */
 	__u32		hcs_params1;
 	__u32		hcs_params2;
 	__u32		hcs_params3;
 	__u32		hcc_params;
 	spinlock_t	lock;
 	/* packed release number */
 	u8		sbrn;
 	u16		hci_version;
 	u8		max_slots;
 	u8		max_interrupters;
 	u8		max_ports;
 	u8		isoc_threshold;
 	int		event_ring_max;
 	int		addr_64;
 	/* 4KB min, 128MB max */
 	int		page_size;
 	/* Valid values are 12 to 20, inclusive */
 	int		page_shift;
 	/* only one MSI vector for now, but might need more later */
 	int		msix_count;
 	struct msix_entry	*msix_entries;
 	/* data structures */
 	struct xhci_device_context_array *dcbaa;
 	struct xhci_ring	*cmd_ring;
 	struct xhci_ring	*event_ring;
 	struct xhci_erst	erst;
 	/* Scratchpad */
 	struct xhci_scratchpad  *scratchpad;
 	/* slot enabling and address device helpers */
 	struct completion	addr_dev;
 	int slot_id;
 	/* Internal mirror of the HW's dcbaa */
 	struct xhci_virt_device	*devs[MAX_HC_SLOTS];
 	/* DMA pools */
 	struct dma_pool	*device_pool;
 	struct dma_pool	*segment_pool;
 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
 	/* Poll the rings - for debugging */
 	struct timer_list	event_ring_timer;
 	int			zombie;
 #endif
 	/* Statistics */
 	int			noops_submitted;
 	int			noops_handled;
 	int			error_bitmask;
 };
 /* For testing purposes */
 #define NUM_TEST_NOOPS	0
 /* convert between an HCD pointer and the corresponding EHCI_HCD */
 static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd)
 {
 	return (struct xhci_hcd *) (hcd->hcd_priv);
 }
 static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci)
 {
 	return container_of((void *) xhci, struct usb_hcd, hcd_priv);
 }
 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
 #define XHCI_DEBUG	1
 #else
 #define XHCI_DEBUG	0
 #endif
 #define xhci_dbg(xhci, fmt, args...) \
 	do { if (XHCI_DEBUG) dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0)
 #define xhci_info(xhci, fmt, args...) \
 	do { if (XHCI_DEBUG) dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0)
 #define xhci_err(xhci, fmt, args...) \
 	dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
 #define xhci_warn(xhci, fmt, args...) \
 	dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
 /* TODO: copied from ehci.h - can be refactored? */
 /* xHCI spec says all registers are little endian */
 static inline unsigned int xhci_readl(const struct xhci_hcd *xhci,
 		__u32 __iomem *regs)
 {
 	return readl(regs);
 }
 static inline void xhci_writel(struct xhci_hcd *xhci,
 		const unsigned int val, __u32 __iomem *regs)
 {
 	xhci_dbg(xhci,
 			"`MEM_WRITE_DWORD(3'b000, 32'h%p, 32'h%0x, 4'hf);\n",
 			regs, val);
 	writel(val, regs);
 }
 /*
 * Registers should always be accessed with double word or quad word accesses.
 *
 * Some xHCI implementations may support 64-bit address pointers.  Registers
 * with 64-bit address pointers should be written to with dword accesses by
 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second.
 * xHCI implementations that do not support 64-bit address pointers will ignore
 * the high dword, and write order is irrelevant.
 */
 static inline u64 xhci_read_64(const struct xhci_hcd *xhci,
 		__u64 __iomem *regs)
 {
 	__u32 __iomem *ptr = (__u32 __iomem *) regs;
 	u64 val_lo = readl(ptr);
 	u64 val_hi = readl(ptr + 1);
 	return val_lo + (val_hi << 32);
 }
 static inline void xhci_write_64(struct xhci_hcd *xhci,
 		const u64 val, __u64 __iomem *regs)
 {
 	__u32 __iomem *ptr = (__u32 __iomem *) regs;
 	u32 val_lo = lower_32_bits(val);
 	u32 val_hi = upper_32_bits(val);
 	xhci_dbg(xhci,
 			"`MEM_WRITE_DWORD(3'b000, 64'h%p, 64'h%0lx, 4'hf);\n",
 			regs, (long unsigned int) val);
 	writel(val_lo, ptr);
 	writel(val_hi, ptr + 1);
 }
 /* xHCI debugging */
 void xhci_print_ir_set(struct xhci_hcd *xhci, struct xhci_intr_reg *ir_set, int set_num);
 void xhci_print_registers(struct xhci_hcd *xhci);
 void xhci_dbg_regs(struct xhci_hcd *xhci);
 void xhci_print_run_regs(struct xhci_hcd *xhci);
 void xhci_print_trb_offsets(struct xhci_hcd *xhci, union xhci_trb *trb);
 void xhci_debug_trb(struct xhci_hcd *xhci, union xhci_trb *trb);
 void xhci_debug_segment(struct xhci_hcd *xhci, struct xhci_segment *seg);
 void xhci_debug_ring(struct xhci_hcd *xhci, struct xhci_ring *ring);
 void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst);
 void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci);
 void xhci_dbg_ring_ptrs(struct xhci_hcd *xhci, struct xhci_ring *ring);
 void xhci_dbg_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int last_ep);
-/* xHCI memory managment */
+/* xHCI memory management */
 void xhci_mem_cleanup(struct xhci_hcd *xhci);
 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags);
 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id);
 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags);
 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev);
 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc);
 unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc);
 void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep);
 int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev,
 		struct usb_device *udev, struct usb_host_endpoint *ep,
 		gfp_t mem_flags);
 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring);
 #ifdef CONFIG_PCI
 /* xHCI PCI glue */
 int xhci_register_pci(void);
 void xhci_unregister_pci(void);
 #endif
 /* xHCI host controller glue */
 int xhci_halt(struct xhci_hcd *xhci);
 int xhci_reset(struct xhci_hcd *xhci);
 int xhci_init(struct usb_hcd *hcd);
 int xhci_run(struct usb_hcd *hcd);
 void xhci_stop(struct usb_hcd *hcd);
 void xhci_shutdown(struct usb_hcd *hcd);
 int xhci_get_frame(struct usb_hcd *hcd);
 irqreturn_t xhci_irq(struct usb_hcd *hcd);
 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev);
 void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev);
 int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev);
 int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags);
 int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status);
 int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep);
 int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep);
 void xhci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep);
 int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
 void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
 /* xHCI ring, segment, TRB, and TD functions */
 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb);
 void xhci_ring_cmd_db(struct xhci_hcd *xhci);
 void *xhci_setup_one_noop(struct xhci_hcd *xhci);
 void xhci_handle_event(struct xhci_hcd *xhci);
 void xhci_set_hc_event_deq(struct xhci_hcd *xhci);
 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id);
 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
 		u32 slot_id);
 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
 		unsigned int ep_index);
 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
 		int slot_id, unsigned int ep_index);
 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
 		int slot_id, unsigned int ep_index);
 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
 		u32 slot_id);
 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
 		unsigned int ep_index);
 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
 		unsigned int slot_id, unsigned int ep_index,
 		struct xhci_td *cur_td, struct xhci_dequeue_state *state);
 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
 		struct xhci_ring *ep_ring, unsigned int slot_id,
 		unsigned int ep_index, struct xhci_dequeue_state *deq_state);
 /* xHCI roothub code */
 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex,
 		char *buf, u16 wLength);
 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf);
 /* xHCI contexts */
 struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index);
 #endif /* __LINUX_XHCI_HCD_H */
 /*
 * HWA Host Controller Driver
 * Wire Adapter Control/Data Streaming Iface (WUSB1.0[8])
 *
 * Copyright (C) 2005-2006 Intel Corporation
 * Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License version
 * 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
 * 02110-1301, USA.
 *
 *
 * This driver implements a USB Host Controller (struct usb_hcd) for a
 * Wireless USB Host Controller based on the Wireless USB 1.0
 * Host-Wire-Adapter specification (in layman terms, a USB-dongle that
 * implements a Wireless USB host).
 *
 * Check out the Design-overview.txt file in the source documentation
 * for other details on the implementation.
 *
 * Main blocks:
 *
 *  driver     glue with the driver API, workqueue daemon
 *
 *  lc         RC instance life cycle management (create, destroy...)
 *
 *  hcd        glue with the USB API Host Controller Interface API.
 *
 *  nep        Notification EndPoint managent: collect notifications
 *             and queue them with the workqueue daemon.
 *
 *             Handle notifications as coming from the NEP. Sends them
 *             off others to their respective modules (eg: connect,
 *             disconnect and reset go to devconnect).
 *
 *  rpipe      Remote Pipe management; rpipe is what we use to write
 *             to an endpoint on a WUSB device that is connected to a
 *             HWA RC.
 *
- *  xfer       Transfer managment -- this is all the code that gets a
+ *  xfer       Transfer management -- this is all the code that gets a
 *             buffer and pushes it to a device (or viceversa). *
 *
 * Some day a lot of this code will be shared between this driver and
 * the drivers for DWA (xfer, rpipe).
 *
 * All starts at driver.c:hwahc_probe(), when one of this guys is
 * connected. hwahc_disconnect() stops it.
 *
 * During operation, the main driver is devices connecting or
 * disconnecting. They cause the HWA RC to send notifications into
 * nep.c:hwahc_nep_cb() that will dispatch them to
 * notif.c:wa_notif_dispatch(). From there they will fan to cause
 * device connects, disconnects, etc.
 *
 * Note much of the activity is difficult to follow. For example a
 * device connect goes to devconnect, which will cause the "fake" root
 * hub port to show a connect and stop there. Then khubd will notice
 * and call into the rh.c:hwahc_rc_port_reset() code to authenticate
 * the device (and this might require user intervention) and enable
 * the port.
 *
 * We also have a timer workqueue going from devconnect.c that
 * schedules in hwahc_devconnect_create().
 *
 * The rest of the traffic is in the usual entry points of a USB HCD,
 * which are hooked up in driver.c:hwahc_rc_driver, and defined in
 * hcd.c.
 */
 #ifndef __HWAHC_INTERNAL_H__
 #define __HWAHC_INTERNAL_H__
 #include <linux/completion.h>
 #include <linux/usb.h>
 #include <linux/mutex.h>
 #include <linux/spinlock.h>
 #include <linux/uwb.h>
 #include <linux/usb/wusb.h>
 #include <linux/usb/wusb-wa.h>
 struct wusbhc;
 struct wahc;
 extern void wa_urb_enqueue_run(struct work_struct *ws);
 /**
 * RPipe instance
 *
 * @descr's fields are kept in LE, as we need to send it back and
 * forth.
 *
 * @wa is referenced when set
 *
 * @segs_available is the number of requests segments that still can
 *                 be submitted to the controller without overloading
 *                 it. It is initialized to descr->wRequests when
 *                 aiming.
 *
 * A rpipe supports a max of descr->wRequests at the same time; before
 * submitting seg_lock has to be taken. If segs_avail > 0, then we can
 * submit; if not, we have to queue them.
 */
 struct wa_rpipe {
 	struct kref refcnt;
 	struct usb_rpipe_descriptor descr;
 	struct usb_host_endpoint *ep;
 	struct wahc *wa;
 	spinlock_t seg_lock;
 	struct list_head seg_list;
 	atomic_t segs_available;
 	u8 buffer[1];	/* For reads/writes on USB */
 };
 /**
 * Instance of a HWA Host Controller
 *
 * Except where a more specific lock/mutex applies or atomic, all
 * fields protected by @mutex.
 *
 * @wa_descr  Can be accessed without locking because it is in
 *            the same area where the device descriptors were
 *            read, so it is guaranteed to exist umodified while
 *            the device exists.
 *
 *            Endianess has been converted to CPU's.
 *
 * @nep_* can be accessed without locking as its processing is
 *        serialized; we submit a NEP URB and it comes to
 *        hwahc_nep_cb(), which won't issue another URB until it is
 *        done processing it.
 *
 * @xfer_list:
 *
 *   List of active transfers to verify existence from a xfer id
 *   gotten from the xfer result message. Can't use urb->list because
 *   it goes by endpoint, and we don't know the endpoint at the time
 *   when we get the xfer result message. We can't really rely on the
 *   pointer (will have to change for 64 bits) as the xfer id is 32 bits.
 *
 * @xfer_delayed_list:   List of transfers that need to be started
 *                       (with a workqueue, because they were
 *                       submitted from an atomic context).
 *
 * FIXME: this needs to be layered up: a wusbhc layer (for sharing
 *        comonalities with WHCI), a wa layer (for sharing
 *        comonalities with DWA-RC).
 */
 struct wahc {
 	struct usb_device *usb_dev;
 	struct usb_interface *usb_iface;
 	/* HC to deliver notifications */
 	union {
 		struct wusbhc *wusb;
 		struct dwahc *dwa;
 	};
 	const struct usb_endpoint_descriptor *dto_epd, *dti_epd;
 	const struct usb_wa_descriptor *wa_descr;
 	struct urb *nep_urb;		/* Notification EndPoint [lockless] */
 	struct edc nep_edc;
 	void *nep_buffer;
 	size_t nep_buffer_size;
 	atomic_t notifs_queued;
 	u16 rpipes;
 	unsigned long *rpipe_bm;	/* rpipe usage bitmap */
 	spinlock_t rpipe_bm_lock;	/* protect rpipe_bm */
 	struct mutex rpipe_mutex;	/* assigning resources to endpoints */
 	struct urb *dti_urb;		/* URB for reading xfer results */
 	struct urb *buf_in_urb;		/* URB for reading data in */
 	struct edc dti_edc;		/* DTI error density counter */
 	struct wa_xfer_result *xfer_result; /* real size = dti_ep maxpktsize */
 	size_t xfer_result_size;
 	s32 status;			/* For reading status */
 	struct list_head xfer_list;
 	struct list_head xfer_delayed_list;
 	spinlock_t xfer_list_lock;
 	struct work_struct xfer_work;
 	atomic_t xfer_id_count;
 };
 extern int wa_create(struct wahc *wa, struct usb_interface *iface);
 extern void __wa_destroy(struct wahc *wa);
 void wa_reset_all(struct wahc *wa);
 /* Miscellaneous constants */
 enum {
 	/** Max number of EPROTO errors we tolerate on the NEP in a
 	 * period of time */
 	HWAHC_EPROTO_MAX = 16,
 	/** Period of time for EPROTO errors (in jiffies) */
 	HWAHC_EPROTO_PERIOD = 4 * HZ,
 };
 /* Notification endpoint handling */
 extern int wa_nep_create(struct wahc *, struct usb_interface *);
 extern void wa_nep_destroy(struct wahc *);
 static inline int wa_nep_arm(struct wahc *wa, gfp_t gfp_mask)
 {
 	struct urb *urb = wa->nep_urb;
 	urb->transfer_buffer = wa->nep_buffer;
 	urb->transfer_buffer_length = wa->nep_buffer_size;
 	return usb_submit_urb(urb, gfp_mask);
 }
 static inline void wa_nep_disarm(struct wahc *wa)
 {
 	usb_kill_urb(wa->nep_urb);
 }
 /* RPipes */
 static inline void wa_rpipe_init(struct wahc *wa)
 {
 	spin_lock_init(&wa->rpipe_bm_lock);
 	mutex_init(&wa->rpipe_mutex);
 }
 static inline void wa_init(struct wahc *wa)
 {
 	edc_init(&wa->nep_edc);
 	atomic_set(&wa->notifs_queued, 0);
 	wa_rpipe_init(wa);
 	edc_init(&wa->dti_edc);
 	INIT_LIST_HEAD(&wa->xfer_list);
 	INIT_LIST_HEAD(&wa->xfer_delayed_list);
 	spin_lock_init(&wa->xfer_list_lock);
 	INIT_WORK(&wa->xfer_work, wa_urb_enqueue_run);
 	atomic_set(&wa->xfer_id_count, 1);
 }
 /**
 * Destroy a pipe (when refcount drops to zero)
 *
 * Assumes it has been moved to the "QUIESCING" state.
 */
 struct wa_xfer;
 extern void rpipe_destroy(struct kref *_rpipe);
 static inline
 void __rpipe_get(struct wa_rpipe *rpipe)
 {
 	kref_get(&rpipe->refcnt);
 }
 extern int rpipe_get_by_ep(struct wahc *, struct usb_host_endpoint *,
 			   struct urb *, gfp_t);
 static inline void rpipe_put(struct wa_rpipe *rpipe)
 {
 	kref_put(&rpipe->refcnt, rpipe_destroy);
 }
 extern void rpipe_ep_disable(struct wahc *, struct usb_host_endpoint *);
 extern int wa_rpipes_create(struct wahc *);
 extern void wa_rpipes_destroy(struct wahc *);
 static inline void rpipe_avail_dec(struct wa_rpipe *rpipe)
 {
 	atomic_dec(&rpipe->segs_available);
 }
 /**
 * Returns true if the rpipe is ready to submit more segments.
 */
 static inline int rpipe_avail_inc(struct wa_rpipe *rpipe)
 {
 	return atomic_inc_return(&rpipe->segs_available) > 0
 		&& !list_empty(&rpipe->seg_list);
 }
 /* Transferring data */
 extern int wa_urb_enqueue(struct wahc *, struct usb_host_endpoint *,
 			  struct urb *, gfp_t);
 extern int wa_urb_dequeue(struct wahc *, struct urb *);
 extern void wa_handle_notif_xfer(struct wahc *, struct wa_notif_hdr *);
 /* Misc
 *
 * FIXME: Refcounting for the actual @hwahc object is not correct; I
 *        mean, this should be refcounting on the HCD underneath, but
 *        it is not. In any case, the semantics for HCD refcounting
 *        are *weird*...on refcount reaching zero it just frees
 *        it...no RC specific function is called...unless I miss
 *        something.
 *
 * FIXME: has to go away in favour of an 'struct' hcd based sollution
 */
 static inline struct wahc *wa_get(struct wahc *wa)
 {
 	usb_get_intf(wa->usb_iface);
 	return wa;
 }
 static inline void wa_put(struct wahc *wa)
 {
 	usb_put_intf(wa->usb_iface);
 }
 static inline int __wa_feature(struct wahc *wa, unsigned op, u16 feature)
 {
 	return usb_control_msg(wa->usb_dev, usb_sndctrlpipe(wa->usb_dev, 0),
 			op ? USB_REQ_SET_FEATURE : USB_REQ_CLEAR_FEATURE,
 			USB_DIR_OUT | USB_TYPE_CLASS | USB_RECIP_INTERFACE,
 			feature,
 			wa->usb_iface->cur_altsetting->desc.bInterfaceNumber,
 			NULL, 0, 1000 /* FIXME: arbitrary */);
 }
 static inline int __wa_set_feature(struct wahc *wa, u16 feature)
 {
 	return  __wa_feature(wa, 1, feature);
 }
 static inline int __wa_clear_feature(struct wahc *wa, u16 feature)
 {
 	return __wa_feature(wa, 0, feature);
 }
 /**
 * Return the status of a Wire Adapter
 *
 * @wa:		Wire Adapter instance
 * @returns     < 0 errno code on error, or status bitmap as described
 *              in WUSB1.0[8.3.1.6].
 *
 * NOTE: need malloc, some arches don't take USB from the stack
 */
 static inline
 s32 __wa_get_status(struct wahc *wa)
 {
 	s32 result;
 	result = usb_control_msg(
 		wa->usb_dev, usb_rcvctrlpipe(wa->usb_dev, 0),
 		USB_REQ_GET_STATUS,
 		USB_DIR_IN | USB_TYPE_CLASS | USB_RECIP_INTERFACE,
 		0, wa->usb_iface->cur_altsetting->desc.bInterfaceNumber,
 		&wa->status, sizeof(wa->status),
 		1000 /* FIXME: arbitrary */);
 	if (result >= 0)
 		result = wa->status;
 	return result;
 }
 /**
 * Waits until the Wire Adapter's status matches @mask/@value
 *
 * @wa:		Wire Adapter instance.
 * @returns     < 0 errno code on error, otherwise status.
 *
 * Loop until the WAs status matches the mask and value (status & mask
 * == value). Timeout if it doesn't happen.
 *
 * FIXME: is there an official specification on how long status
 *        changes can take?
 */
 static inline s32 __wa_wait_status(struct wahc *wa, u32 mask, u32 value)
 {
 	s32 result;
 	unsigned loops = 10;
 	do {
 		msleep(50);
 		result = __wa_get_status(wa);
 		if ((result & mask) == value)
 			break;
 		if (loops-- == 0) {
 			result = -ETIMEDOUT;
 			break;
 		}
 	} while (result >= 0);
 	return result;
 }
 /** Command @hwahc to stop, @returns 0 if ok, < 0 errno code on error */
 static inline int __wa_stop(struct wahc *wa)
 {
 	int result;
 	struct device *dev = &wa->usb_iface->dev;
 	result = __wa_clear_feature(wa, WA_ENABLE);
 	if (result < 0 && result != -ENODEV) {
 		dev_err(dev, "error commanding HC to stop: %d\n", result);
 		goto out;
 	}
 	result = __wa_wait_status(wa, WA_ENABLE, 0);
 	if (result < 0 && result != -ENODEV)
 		dev_err(dev, "error waiting for HC to stop: %d\n", result);
 out:
 	return 0;
 }
 #endif /* #ifndef __HWAHC_INTERNAL_H__ */
 /*
 *
 * Author	Karsten Keil <kkeil@novell.com>
 *
 * Copyright 2008  by Karsten Keil <kkeil@novell.com>
 *
 * This code is free software; you can redistribute it and/or modify
 * it under the terms of the GNU LESSER GENERAL PUBLIC LICENSE
 * version 2.1 as published by the Free Software Foundation.
 *
 * This code is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU LESSER GENERAL PUBLIC LICENSE for more details.
 *
 */
 #ifndef mISDNIF_H
 #define mISDNIF_H
 #include <stdarg.h>
 #include <linux/types.h>
 #include <linux/errno.h>
 #include <linux/socket.h>
 /*
 * ABI Version 32 bit
 *
 * <8 bit> Major version
 *		- changed if any interface become backwards incompatible
 *
 * <8 bit> Minor version
 *              - changed if any interface is extended but backwards compatible
 *
 * <16 bit> Release number
 *              - should be incremented on every checkin
 */
 #define	MISDN_MAJOR_VERSION	1
 #define	MISDN_MINOR_VERSION	1
 #define MISDN_RELEASE		21
 /* primitives for information exchange
 * generell format
 * <16  bit  0 >
 * <8  bit command>
 *    BIT 8 = 1 LAYER private
 *    BIT 7 = 1 answer
 *    BIT 6 = 1 DATA
 * <8  bit target layer mask>
 *
 * Layer = 00 is reserved for general commands
   Layer = 01  L2 -> HW
   Layer = 02  HW -> L2
   Layer = 04  L3 -> L2
   Layer = 08  L2 -> L3
 * Layer = FF is reserved for broadcast commands
 */
 #define MISDN_CMDMASK		0xff00
 #define MISDN_LAYERMASK		0x00ff
 /* generell commands */
 #define OPEN_CHANNEL		0x0100
 #define CLOSE_CHANNEL		0x0200
 #define CONTROL_CHANNEL		0x0300
 #define CHECK_DATA		0x0400
 /* layer 2 -> layer 1 */
 #define PH_ACTIVATE_REQ		0x0101
 #define PH_DEACTIVATE_REQ	0x0201
 #define PH_DATA_REQ		0x2001
 #define MPH_ACTIVATE_REQ	0x0501
 #define MPH_DEACTIVATE_REQ	0x0601
 #define MPH_INFORMATION_REQ	0x0701
 #define PH_CONTROL_REQ		0x0801
 /* layer 1 -> layer 2 */
 #define PH_ACTIVATE_IND		0x0102
 #define PH_ACTIVATE_CNF		0x4102
 #define PH_DEACTIVATE_IND	0x0202
 #define PH_DEACTIVATE_CNF	0x4202
 #define PH_DATA_IND		0x2002
 #define PH_DATA_E_IND		0x3002
 #define MPH_ACTIVATE_IND	0x0502
 #define MPH_DEACTIVATE_IND	0x0602
 #define MPH_INFORMATION_IND	0x0702
 #define PH_DATA_CNF		0x6002
 #define PH_CONTROL_IND		0x0802
 #define PH_CONTROL_CNF		0x4802
 /* layer 3 -> layer 2 */
 #define DL_ESTABLISH_REQ	0x1004
 #define DL_RELEASE_REQ		0x1104
 #define DL_DATA_REQ		0x3004
 #define DL_UNITDATA_REQ		0x3104
 #define DL_INFORMATION_REQ	0x0004
 /* layer 2 -> layer 3 */
 #define DL_ESTABLISH_IND	0x1008
 #define DL_ESTABLISH_CNF	0x5008
 #define DL_RELEASE_IND		0x1108
 #define DL_RELEASE_CNF		0x5108
 #define DL_DATA_IND		0x3008
 #define DL_UNITDATA_IND		0x3108
 #define DL_INFORMATION_IND	0x0008
-/* intern layer 2 managment */
+/* intern layer 2 management */
 #define MDL_ASSIGN_REQ		0x1804
 #define MDL_ASSIGN_IND		0x1904
 #define MDL_REMOVE_REQ		0x1A04
 #define MDL_REMOVE_IND		0x1B04
 #define MDL_STATUS_UP_IND	0x1C04
 #define MDL_STATUS_DOWN_IND	0x1D04
 #define MDL_STATUS_UI_IND	0x1E04
 #define MDL_ERROR_IND		0x1F04
 #define MDL_ERROR_RSP		0x5F04
 /* DL_INFORMATION_IND types */
 #define DL_INFO_L2_CONNECT	0x0001
 #define DL_INFO_L2_REMOVED	0x0002
 /* PH_CONTROL types */
 /* TOUCH TONE IS 0x20XX  XX "0"..."9", "A","B","C","D","*","#" */
 #define DTMF_TONE_VAL		0x2000
 #define DTMF_TONE_MASK		0x007F
 #define DTMF_TONE_START		0x2100
 #define DTMF_TONE_STOP		0x2200
 #define DTMF_HFC_COEF		0x4000
 #define DSP_CONF_JOIN		0x2403
 #define DSP_CONF_SPLIT		0x2404
 #define DSP_RECEIVE_OFF		0x2405
 #define DSP_RECEIVE_ON		0x2406
 #define DSP_ECHO_ON		0x2407
 #define DSP_ECHO_OFF		0x2408
 #define DSP_MIX_ON		0x2409
 #define DSP_MIX_OFF		0x240a
 #define DSP_DELAY		0x240b
 #define DSP_JITTER		0x240c
 #define DSP_TXDATA_ON		0x240d
 #define DSP_TXDATA_OFF		0x240e
 #define DSP_TX_DEJITTER		0x240f
 #define DSP_TX_DEJ_OFF		0x2410
 #define DSP_TONE_PATT_ON	0x2411
 #define DSP_TONE_PATT_OFF	0x2412
 #define DSP_VOL_CHANGE_TX	0x2413
 #define DSP_VOL_CHANGE_RX	0x2414
 #define DSP_BF_ENABLE_KEY	0x2415
 #define DSP_BF_DISABLE		0x2416
 #define DSP_BF_ACCEPT		0x2416
 #define DSP_BF_REJECT		0x2417
 #define DSP_PIPELINE_CFG	0x2418
 #define HFC_VOL_CHANGE_TX	0x2601
 #define HFC_VOL_CHANGE_RX	0x2602
 #define HFC_SPL_LOOP_ON		0x2603
 #define HFC_SPL_LOOP_OFF	0x2604
 /* for T30 FAX and analog modem */
 #define HW_MOD_FRM		0x4000
 #define HW_MOD_FRH		0x4001
 #define HW_MOD_FTM		0x4002
 #define HW_MOD_FTH		0x4003
 #define HW_MOD_FTS		0x4004
 #define HW_MOD_CONNECT		0x4010
 #define HW_MOD_OK		0x4011
 #define HW_MOD_NOCARR		0x4012
 #define HW_MOD_FCERROR		0x4013
 #define HW_MOD_READY		0x4014
 #define HW_MOD_LASTDATA		0x4015
 /* DSP_TONE_PATT_ON parameter */
 #define TONE_OFF			0x0000
 #define TONE_GERMAN_DIALTONE		0x0001
 #define TONE_GERMAN_OLDDIALTONE		0x0002
 #define TONE_AMERICAN_DIALTONE		0x0003
 #define TONE_GERMAN_DIALPBX		0x0004
 #define TONE_GERMAN_OLDDIALPBX		0x0005
 #define TONE_AMERICAN_DIALPBX		0x0006
 #define TONE_GERMAN_RINGING		0x0007
 #define TONE_GERMAN_OLDRINGING		0x0008
 #define TONE_AMERICAN_RINGPBX		0x000b
 #define TONE_GERMAN_RINGPBX		0x000c
 #define TONE_GERMAN_OLDRINGPBX		0x000d
 #define TONE_AMERICAN_RINGING		0x000e
 #define TONE_GERMAN_BUSY		0x000f
 #define TONE_GERMAN_OLDBUSY		0x0010
 #define TONE_AMERICAN_BUSY		0x0011
 #define TONE_GERMAN_HANGUP		0x0012
 #define TONE_GERMAN_OLDHANGUP		0x0013
 #define TONE_AMERICAN_HANGUP		0x0014
 #define TONE_SPECIAL_INFO		0x0015
 #define TONE_GERMAN_GASSENBESETZT	0x0016
 #define TONE_GERMAN_AUFSCHALTTON	0x0016
 /* MPH_INFORMATION_IND */
 #define L1_SIGNAL_LOS_OFF	0x0010
 #define L1_SIGNAL_LOS_ON	0x0011
 #define L1_SIGNAL_AIS_OFF	0x0012
 #define L1_SIGNAL_AIS_ON	0x0013
 #define L1_SIGNAL_RDI_OFF	0x0014
 #define L1_SIGNAL_RDI_ON	0x0015
 #define L1_SIGNAL_SLIP_RX	0x0020
 #define L1_SIGNAL_SLIP_TX	0x0021
 /*
 * protocol ids
 * D channel 1-31
 * B channel 33 - 63
 */
 #define ISDN_P_NONE		0
 #define ISDN_P_BASE		0
 #define ISDN_P_TE_S0		0x01
 #define ISDN_P_NT_S0  		0x02
 #define ISDN_P_TE_E1		0x03
 #define ISDN_P_NT_E1  		0x04
 #define ISDN_P_TE_UP0		0x05
 #define ISDN_P_NT_UP0		0x06
 #define IS_ISDN_P_TE(p) ((p == ISDN_P_TE_S0) || (p == ISDN_P_TE_E1) || \
 				(p == ISDN_P_TE_UP0) || (p == ISDN_P_LAPD_TE))
 #define IS_ISDN_P_NT(p) ((p == ISDN_P_NT_S0) || (p == ISDN_P_NT_E1) || \
 				(p == ISDN_P_NT_UP0) || (p == ISDN_P_LAPD_NT))
 #define IS_ISDN_P_S0(p) ((p == ISDN_P_TE_S0) || (p == ISDN_P_NT_S0))
 #define IS_ISDN_P_E1(p) ((p == ISDN_P_TE_E1) || (p == ISDN_P_NT_E1))
 #define IS_ISDN_P_UP0(p) ((p == ISDN_P_TE_UP0) || (p == ISDN_P_NT_UP0))
 #define ISDN_P_LAPD_TE		0x10
 #define	ISDN_P_LAPD_NT		0x11
 #define ISDN_P_B_MASK		0x1f
 #define ISDN_P_B_START		0x20
 #define ISDN_P_B_RAW		0x21
 #define ISDN_P_B_HDLC		0x22
 #define ISDN_P_B_X75SLP		0x23
 #define ISDN_P_B_L2DTMF		0x24
 #define ISDN_P_B_L2DSP		0x25
 #define ISDN_P_B_L2DSPHDLC	0x26
 #define ISDN_P_B_T30_FAX	0x27
 #define ISDN_P_B_MODEM_ASYNC	0x28
 #define OPTION_L2_PMX		1
 #define OPTION_L2_PTP		2
 #define OPTION_L2_FIXEDTEI	3
 #define OPTION_L2_CLEANUP	4
 #define OPTION_L1_HOLD		5
 /* should be in sync with linux/kobject.h:KOBJ_NAME_LEN */
 #define MISDN_MAX_IDLEN		20
 struct mISDNhead {
 	unsigned int	prim;
 	unsigned int	id;
 }  __attribute__((packed));
 #define MISDN_HEADER_LEN	sizeof(struct mISDNhead)
 #define MAX_DATA_SIZE		2048
 #define MAX_DATA_MEM		(MAX_DATA_SIZE + MISDN_HEADER_LEN)
 #define MAX_DFRAME_LEN		260
 #define MISDN_ID_ADDR_MASK	0xFFFF
 #define MISDN_ID_TEI_MASK	0xFF00
 #define MISDN_ID_SAPI_MASK	0x00FF
 #define MISDN_ID_TEI_ANY	0x7F00
 #define MISDN_ID_ANY		0xFFFF
 #define MISDN_ID_NONE		0xFFFE
 #define GROUP_TEI		127
 #define TEI_SAPI		63
 #define CTRL_SAPI		0
 #define MISDN_MAX_CHANNEL	127
 #define MISDN_CHMAP_SIZE	((MISDN_MAX_CHANNEL + 1) >> 3)
 #define SOL_MISDN	0
 struct sockaddr_mISDN {
 	sa_family_t    family;
 	unsigned char	dev;
 	unsigned char	channel;
 	unsigned char	sapi;
 	unsigned char	tei;
 };
 struct mISDNversion {
 	unsigned char	major;
 	unsigned char	minor;
 	unsigned short	release;
 };
 struct mISDN_devinfo {
 	u_int			id;
 	u_int			Dprotocols;
 	u_int			Bprotocols;
 	u_int			protocol;
 	u_char			channelmap[MISDN_CHMAP_SIZE];
 	u_int			nrbchan;
 	char			name[MISDN_MAX_IDLEN];
 };
 struct mISDN_devrename {
 	u_int			id;
 	char			name[MISDN_MAX_IDLEN]; /* new name */
 };
 /* MPH_INFORMATION_REQ payload */
 struct ph_info_ch {
 	__u32 protocol;
 	__u64 Flags;
 };
 struct ph_info_dch {
 	struct ph_info_ch ch;
 	__u16 state;
 	__u16 num_bch;
 };
 struct ph_info {
 	struct ph_info_dch dch;
 	struct ph_info_ch  bch[];
 };
 /* timer device ioctl */
 #define IMADDTIMER	_IOR('I', 64, int)
 #define IMDELTIMER	_IOR('I', 65, int)
 /* socket ioctls */
 #define	IMGETVERSION	_IOR('I', 66, int)
 #define	IMGETCOUNT	_IOR('I', 67, int)
 #define IMGETDEVINFO	_IOR('I', 68, int)
 #define IMCTRLREQ	_IOR('I', 69, int)
 #define IMCLEAR_L2	_IOR('I', 70, int)
 #define IMSETDEVNAME	_IOR('I', 71, struct mISDN_devrename)
 #define IMHOLD_L1	_IOR('I', 72, int)
 static inline int
 test_channelmap(u_int nr, u_char *map)
 {
 	if (nr <= MISDN_MAX_CHANNEL)
 		return map[nr >> 3] & (1 << (nr & 7));
 	else
 		return 0;
 }
 static inline void
 set_channelmap(u_int nr, u_char *map)
 {
 	map[nr >> 3] |= (1 << (nr & 7));
 }
 static inline void
 clear_channelmap(u_int nr, u_char *map)
 {
 	map[nr >> 3] &= ~(1 << (nr & 7));
 }
 /* CONTROL_CHANNEL parameters */
 #define MISDN_CTRL_GETOP		0x0000
 #define MISDN_CTRL_LOOP			0x0001
 #define MISDN_CTRL_CONNECT		0x0002
 #define MISDN_CTRL_DISCONNECT		0x0004
 #define MISDN_CTRL_PCMCONNECT		0x0010
 #define MISDN_CTRL_PCMDISCONNECT	0x0020
 #define MISDN_CTRL_SETPEER		0x0040
 #define MISDN_CTRL_UNSETPEER		0x0080
 #define MISDN_CTRL_RX_OFF		0x0100
 #define MISDN_CTRL_FILL_EMPTY		0x0200
 #define MISDN_CTRL_GETPEER		0x0400
 #define MISDN_CTRL_HW_FEATURES_OP	0x2000
 #define MISDN_CTRL_HW_FEATURES		0x2001
 #define MISDN_CTRL_HFC_OP		0x4000
 #define MISDN_CTRL_HFC_PCM_CONN		0x4001
 #define MISDN_CTRL_HFC_PCM_DISC		0x4002
 #define MISDN_CTRL_HFC_CONF_JOIN	0x4003
 #define MISDN_CTRL_HFC_CONF_SPLIT	0x4004
 #define MISDN_CTRL_HFC_RECEIVE_OFF	0x4005
 #define MISDN_CTRL_HFC_RECEIVE_ON	0x4006
 #define MISDN_CTRL_HFC_ECHOCAN_ON 	0x4007
 #define MISDN_CTRL_HFC_ECHOCAN_OFF 	0x4008
 #define MISDN_CTRL_HFC_WD_INIT		0x4009
 #define MISDN_CTRL_HFC_WD_RESET		0x400A
 /* socket options */
 #define MISDN_TIME_STAMP		0x0001
 struct mISDN_ctrl_req {
 	int		op;
 	int		channel;
 	int		p1;
 	int		p2;
 };
 /* muxer options */
 #define MISDN_OPT_ALL		1
 #define MISDN_OPT_TEIMGR	2
 #ifdef __KERNEL__
 #include <linux/list.h>
 #include <linux/skbuff.h>
 #include <linux/net.h>
 #include <net/sock.h>
 #include <linux/completion.h>
 #define DEBUG_CORE		0x000000ff
 #define DEBUG_CORE_FUNC		0x00000002
 #define DEBUG_SOCKET		0x00000004
 #define DEBUG_MANAGER		0x00000008
 #define DEBUG_SEND_ERR		0x00000010
 #define DEBUG_MSG_THREAD	0x00000020
 #define DEBUG_QUEUE_FUNC	0x00000040
 #define DEBUG_L1		0x0000ff00
 #define DEBUG_L1_FSM		0x00000200
 #define DEBUG_L2		0x00ff0000
 #define DEBUG_L2_FSM		0x00020000
 #define DEBUG_L2_CTRL		0x00040000
 #define DEBUG_L2_RECV		0x00080000
 #define DEBUG_L2_TEI		0x00100000
 #define DEBUG_L2_TEIFSM		0x00200000
 #define DEBUG_TIMER		0x01000000
 #define DEBUG_CLOCK		0x02000000
 #define mISDN_HEAD_P(s)		((struct mISDNhead *)&s->cb[0])
 #define mISDN_HEAD_PRIM(s)	(((struct mISDNhead *)&s->cb[0])->prim)
 #define mISDN_HEAD_ID(s)	(((struct mISDNhead *)&s->cb[0])->id)
 /* socket states */
 #define MISDN_OPEN	1
 #define MISDN_BOUND	2
 #define MISDN_CLOSED	3
 struct mISDNchannel;
 struct mISDNdevice;
 struct mISDNstack;
 struct mISDNclock;
 struct channel_req {
 	u_int			protocol;
 	struct sockaddr_mISDN	adr;
 	struct mISDNchannel	*ch;
 };
 typedef	int	(ctrl_func_t)(struct mISDNchannel *, u_int, void *);
 typedef	int	(send_func_t)(struct mISDNchannel *, struct sk_buff *);
 typedef int	(create_func_t)(struct channel_req *);
 struct Bprotocol {
 	struct list_head	list;
 	char			*name;
 	u_int			Bprotocols;
 	create_func_t		*create;
 };
 struct mISDNchannel {
 	struct list_head	list;
 	u_int			protocol;
 	u_int			nr;
 	u_long			opt;
 	u_int			addr;
 	struct mISDNstack	*st;
 	struct mISDNchannel	*peer;
 	send_func_t		*send;
 	send_func_t		*recv;
 	ctrl_func_t		*ctrl;
 };
 struct mISDN_sock_list {
 	struct hlist_head	head;
 	rwlock_t		lock;
 };
 struct mISDN_sock {
 	struct sock		sk;
 	struct mISDNchannel	ch;
 	u_int			cmask;
 	struct mISDNdevice	*dev;
 };
 struct mISDNdevice {
 	struct mISDNchannel	D;
 	u_int			id;
 	u_int			Dprotocols;
 	u_int			Bprotocols;
 	u_int			nrbchan;
 	u_char			channelmap[MISDN_CHMAP_SIZE];
 	struct list_head	bchannels;
 	struct mISDNchannel	*teimgr;
 	struct device		dev;
 };
 struct mISDNstack {
 	u_long			status;
 	struct mISDNdevice	*dev;
 	struct task_struct	*thread;
 	struct completion	*notify;
 	wait_queue_head_t	workq;
 	struct sk_buff_head	msgq;
 	struct list_head	layer2;
 	struct mISDNchannel	*layer1;
 	struct mISDNchannel	own;
 	struct mutex		lmutex; /* protect lists */
 	struct mISDN_sock_list	l1sock;
 #ifdef MISDN_MSG_STATS
 	u_int			msg_cnt;
 	u_int			sleep_cnt;
 	u_int			stopped_cnt;
 #endif
 };
 typedef	int	(clockctl_func_t)(void *, int);
 struct	mISDNclock {
 	struct list_head	list;
 	char			name[64];
 	int			pri;
 	clockctl_func_t		*ctl;
 	void			*priv;
 };
 /* global alloc/queue functions */
 static inline struct sk_buff *
 mI_alloc_skb(unsigned int len, gfp_t gfp_mask)
 {
 	struct sk_buff	*skb;
 	skb = alloc_skb(len + MISDN_HEADER_LEN, gfp_mask);
 	if (likely(skb))
 		skb_reserve(skb, MISDN_HEADER_LEN);
 	return skb;
 }
 static inline struct sk_buff *
 _alloc_mISDN_skb(u_int prim, u_int id, u_int len, void *dp, gfp_t gfp_mask)
 {
 	struct sk_buff	*skb = mI_alloc_skb(len, gfp_mask);
 	struct mISDNhead *hh;
 	if (!skb)
 		return NULL;
 	if (len)
 		memcpy(skb_put(skb, len), dp, len);
 	hh = mISDN_HEAD_P(skb);
 	hh->prim = prim;
 	hh->id = id;
 	return skb;
 }
 static inline void
 _queue_data(struct mISDNchannel *ch, u_int prim,
    u_int id, u_int len, void *dp, gfp_t gfp_mask)
 {
 	struct sk_buff		*skb;
 	if (!ch->peer)
 		return;
 	skb = _alloc_mISDN_skb(prim, id, len, dp, gfp_mask);
 	if (!skb)
 		return;
 	if (ch->recv(ch->peer, skb))
 		dev_kfree_skb(skb);
 }
 /* global register/unregister functions */
 extern int	mISDN_register_device(struct mISDNdevice *,
 					struct device *parent, char *name);
 extern void	mISDN_unregister_device(struct mISDNdevice *);
 extern int	mISDN_register_Bprotocol(struct Bprotocol *);
 extern void	mISDN_unregister_Bprotocol(struct Bprotocol *);
 extern struct mISDNclock *mISDN_register_clock(char *, int, clockctl_func_t *,
 						void *);
 extern void	mISDN_unregister_clock(struct mISDNclock *);
 static inline struct mISDNdevice *dev_to_mISDN(struct device *dev)
 {
 	if (dev)
 		return dev_get_drvdata(dev);
 	else
 		return NULL;
 }
 extern void	set_channel_address(struct mISDNchannel *, u_int, u_int);
 extern void	mISDN_clock_update(struct mISDNclock *, int, struct timeval *);
 extern unsigned short mISDN_clock_get(void);
 #endif /* __KERNEL__ */
 #endif /* mISDNIF_H */
1	/* cache.S: cache managment routines	1	/* cache.S: cache management routines
2	*	2	*
3	* Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.	3	* Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
4	* Written by David Howells (dhowells@redhat.com)	4	* Written by David Howells (dhowells@redhat.com)
5	*	5	*
6	* This program is free software; you can redistribute it and/or	6	* This program is free software; you can redistribute it and/or
7	* modify it under the terms of the GNU General Public License	7	* modify it under the terms of the GNU General Public License
8	* as published by the Free Software Foundation; either version	8	* as published by the Free Software Foundation; either version
9	* 2 of the License, or (at your option) any later version.	9	* 2 of the License, or (at your option) any later version.
10	*/	10	*/
11		11
12	#include <asm/spr-regs.h>	12	#include <asm/spr-regs.h>
13	#include <asm/cache.h>	13	#include <asm/cache.h>
14		14
15	.text	15	.text
16	.p2align 4	16	.p2align 4
17		17
18	###############################################################################	18	###############################################################################
19	#	19	#
20	# Write back a range of dcache	20	# Write back a range of dcache
21	# - void frv_dcache_writeback(unsigned long start [GR8], unsigned long size [GR9])	21	# - void frv_dcache_writeback(unsigned long start [GR8], unsigned long size [GR9])
22	#	22	#
23	###############################################################################	23	###############################################################################
24	.globl frv_dcache_writeback	24	.globl frv_dcache_writeback
25	.type frv_dcache_writeback,@function	25	.type frv_dcache_writeback,@function
26	frv_dcache_writeback:	26	frv_dcache_writeback:
27	andi gr8,~(L1_CACHE_BYTES-1),gr8	27	andi gr8,~(L1_CACHE_BYTES-1),gr8
28		28
29	2: dcf @(gr8,gr0)	29	2: dcf @(gr8,gr0)
30	addi gr8,#L1_CACHE_BYTES,gr8	30	addi gr8,#L1_CACHE_BYTES,gr8
31	cmp gr9,gr8,icc0	31	cmp gr9,gr8,icc0
32	bhi icc0,#2,2b	32	bhi icc0,#2,2b
33		33
34	membar	34	membar
35	bralr	35	bralr
36	.size frv_dcache_writeback, .-frv_dcache_writeback	36	.size frv_dcache_writeback, .-frv_dcache_writeback
37		37
38	##############################################################################	38	##############################################################################
39	#	39	#
40	# Invalidate a range of dcache and icache	40	# Invalidate a range of dcache and icache
41	# - void frv_cache_invalidate(unsigned long start [GR8], unsigned long end [GR9]);	41	# - void frv_cache_invalidate(unsigned long start [GR8], unsigned long end [GR9]);
42	#	42	#
43	###############################################################################	43	###############################################################################
44	.globl frv_cache_invalidate	44	.globl frv_cache_invalidate
45	.type frv_cache_invalidate,@function	45	.type frv_cache_invalidate,@function
46	frv_cache_invalidate:	46	frv_cache_invalidate:
47	andi gr8,~(L1_CACHE_BYTES-1),gr8	47	andi gr8,~(L1_CACHE_BYTES-1),gr8
48		48
49	2: dci @(gr8,gr0)	49	2: dci @(gr8,gr0)
50	ici @(gr8,gr0)	50	ici @(gr8,gr0)
51	addi gr8,#L1_CACHE_BYTES,gr8	51	addi gr8,#L1_CACHE_BYTES,gr8
52	cmp gr9,gr8,icc0	52	cmp gr9,gr8,icc0
53	bhi icc0,#2,2b	53	bhi icc0,#2,2b
54		54
55	membar	55	membar
56	bralr	56	bralr
57	.size frv_cache_invalidate, .-frv_cache_invalidate	57	.size frv_cache_invalidate, .-frv_cache_invalidate
58		58
59	##############################################################################	59	##############################################################################
60	#	60	#
61	# Invalidate a range of icache	61	# Invalidate a range of icache
62	# - void frv_icache_invalidate(unsigned long start [GR8], unsigned long end [GR9]);	62	# - void frv_icache_invalidate(unsigned long start [GR8], unsigned long end [GR9]);
63	#	63	#
64	###############################################################################	64	###############################################################################
65	.globl frv_icache_invalidate	65	.globl frv_icache_invalidate
66	.type frv_icache_invalidate,@function	66	.type frv_icache_invalidate,@function
67	frv_icache_invalidate:	67	frv_icache_invalidate:
68	andi gr8,~(L1_CACHE_BYTES-1),gr8	68	andi gr8,~(L1_CACHE_BYTES-1),gr8
69		69
70	2: ici @(gr8,gr0)	70	2: ici @(gr8,gr0)
71	addi gr8,#L1_CACHE_BYTES,gr8	71	addi gr8,#L1_CACHE_BYTES,gr8
72	cmp gr9,gr8,icc0	72	cmp gr9,gr8,icc0
73	bhi icc0,#2,2b	73	bhi icc0,#2,2b
74		74
75	membar	75	membar
76	bralr	76	bralr
77	.size frv_icache_invalidate, .-frv_icache_invalidate	77	.size frv_icache_invalidate, .-frv_icache_invalidate
78		78
79	###############################################################################	79	###############################################################################
80	#	80	#
81	# Write back and invalidate a range of dcache and icache	81	# Write back and invalidate a range of dcache and icache
82	# - void frv_cache_wback_inv(unsigned long start [GR8], unsigned long end [GR9])	82	# - void frv_cache_wback_inv(unsigned long start [GR8], unsigned long end [GR9])
83	#	83	#
84	###############################################################################	84	###############################################################################
85	.globl frv_cache_wback_inv	85	.globl frv_cache_wback_inv
86	.type frv_cache_wback_inv,@function	86	.type frv_cache_wback_inv,@function
87	frv_cache_wback_inv:	87	frv_cache_wback_inv:
88	andi gr8,~(L1_CACHE_BYTES-1),gr8	88	andi gr8,~(L1_CACHE_BYTES-1),gr8
89		89
90	2: dcf @(gr8,gr0)	90	2: dcf @(gr8,gr0)
91	ici @(gr8,gr0)	91	ici @(gr8,gr0)
92	addi gr8,#L1_CACHE_BYTES,gr8	92	addi gr8,#L1_CACHE_BYTES,gr8
93	cmp gr9,gr8,icc0	93	cmp gr9,gr8,icc0
94	bhi icc0,#2,2b	94	bhi icc0,#2,2b
95		95
96	membar	96	membar
97	bralr	97	bralr
98	.size frv_cache_wback_inv, .-frv_cache_wback_inv	98	.size frv_cache_wback_inv, .-frv_cache_wback_inv
99		99
1	/* MN10300 Cache flushing	1	/* MN10300 Cache flushing
2	*	2	*
3	* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.	3	* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
4	* Written by David Howells (dhowells@redhat.com)	4	* Written by David Howells (dhowells@redhat.com)
5	*	5	*
6	* This program is free software; you can redistribute it and/or	6	* This program is free software; you can redistribute it and/or
7	* modify it under the terms of the GNU General Public Licence	7	* modify it under the terms of the GNU General Public Licence
8	* as published by the Free Software Foundation; either version	8	* as published by the Free Software Foundation; either version
9	* 2 of the Licence, or (at your option) any later version.	9	* 2 of the Licence, or (at your option) any later version.
10	*/	10	*/
11	#ifndef _ASM_CACHEFLUSH_H	11	#ifndef _ASM_CACHEFLUSH_H
12	#define _ASM_CACHEFLUSH_H	12	#define _ASM_CACHEFLUSH_H
13		13
14	#ifndef __ASSEMBLY__	14	#ifndef __ASSEMBLY__
15		15
16	/* Keep includes the same across arches. */	16	/* Keep includes the same across arches. */
17	#include <linux/mm.h>	17	#include <linux/mm.h>
18		18
19	/*	19	/*
20	* virtually-indexed cache managment (our cache is physically indexed)	20	* virtually-indexed cache management (our cache is physically indexed)
21	*/	21	*/
22	#define flush_cache_all() do {} while (0)	22	#define flush_cache_all() do {} while (0)
23	#define flush_cache_mm(mm) do {} while (0)	23	#define flush_cache_mm(mm) do {} while (0)
24	#define flush_cache_dup_mm(mm) do {} while (0)	24	#define flush_cache_dup_mm(mm) do {} while (0)
25	#define flush_cache_range(mm, start, end) do {} while (0)	25	#define flush_cache_range(mm, start, end) do {} while (0)
26	#define flush_cache_page(vma, vmaddr, pfn) do {} while (0)	26	#define flush_cache_page(vma, vmaddr, pfn) do {} while (0)
27	#define flush_cache_vmap(start, end) do {} while (0)	27	#define flush_cache_vmap(start, end) do {} while (0)
28	#define flush_cache_vunmap(start, end) do {} while (0)	28	#define flush_cache_vunmap(start, end) do {} while (0)
29	#define flush_dcache_page(page) do {} while (0)	29	#define flush_dcache_page(page) do {} while (0)
30	#define flush_dcache_mmap_lock(mapping) do {} while (0)	30	#define flush_dcache_mmap_lock(mapping) do {} while (0)
31	#define flush_dcache_mmap_unlock(mapping) do {} while (0)	31	#define flush_dcache_mmap_unlock(mapping) do {} while (0)
32		32
33	/*	33	/*
34	* physically-indexed cache managment	34	* physically-indexed cache management
35	*/	35	*/
36	#ifndef CONFIG_MN10300_CACHE_DISABLED	36	#ifndef CONFIG_MN10300_CACHE_DISABLED
37		37
38	extern void flush_icache_range(unsigned long start, unsigned long end);	38	extern void flush_icache_range(unsigned long start, unsigned long end);
39	extern void flush_icache_page(struct vm_area_struct vma, struct page pg);	39	extern void flush_icache_page(struct vm_area_struct vma, struct page pg);
40		40
41	#else	41	#else
42		42
43	#define flush_icache_range(start, end) do {} while (0)	43	#define flush_icache_range(start, end) do {} while (0)
44	#define flush_icache_page(vma, pg) do {} while (0)	44	#define flush_icache_page(vma, pg) do {} while (0)
45		45
46	#endif	46	#endif
47		47
48	#define flush_icache_user_range(vma, pg, adr, len) \	48	#define flush_icache_user_range(vma, pg, adr, len) \
49	flush_icache_range(adr, adr + len)	49	flush_icache_range(adr, adr + len)
50		50
51	#define copy_to_user_page(vma, page, vaddr, dst, src, len) \	51	#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
52	do { \	52	do { \
53	memcpy(dst, src, len); \	53	memcpy(dst, src, len); \
54	flush_icache_page(vma, page); \	54	flush_icache_page(vma, page); \
55	} while (0)	55	} while (0)
56		56
57	#define copy_from_user_page(vma, page, vaddr, dst, src, len) \	57	#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
58	memcpy(dst, src, len)	58	memcpy(dst, src, len)
59		59
60	/*	60	/*
61	* primitive routines	61	* primitive routines
62	*/	62	*/
63	#ifndef CONFIG_MN10300_CACHE_DISABLED	63	#ifndef CONFIG_MN10300_CACHE_DISABLED
64	extern void mn10300_icache_inv(void);	64	extern void mn10300_icache_inv(void);
65	extern void mn10300_dcache_inv(void);	65	extern void mn10300_dcache_inv(void);
66	extern void mn10300_dcache_inv_page(unsigned start);	66	extern void mn10300_dcache_inv_page(unsigned start);
67	extern void mn10300_dcache_inv_range(unsigned start, unsigned end);	67	extern void mn10300_dcache_inv_range(unsigned start, unsigned end);
68	extern void mn10300_dcache_inv_range2(unsigned start, unsigned size);	68	extern void mn10300_dcache_inv_range2(unsigned start, unsigned size);
69	#ifdef CONFIG_MN10300_CACHE_WBACK	69	#ifdef CONFIG_MN10300_CACHE_WBACK
70	extern void mn10300_dcache_flush(void);	70	extern void mn10300_dcache_flush(void);
71	extern void mn10300_dcache_flush_page(unsigned start);	71	extern void mn10300_dcache_flush_page(unsigned start);
72	extern void mn10300_dcache_flush_range(unsigned start, unsigned end);	72	extern void mn10300_dcache_flush_range(unsigned start, unsigned end);
73	extern void mn10300_dcache_flush_range2(unsigned start, unsigned size);	73	extern void mn10300_dcache_flush_range2(unsigned start, unsigned size);
74	extern void mn10300_dcache_flush_inv(void);	74	extern void mn10300_dcache_flush_inv(void);
75	extern void mn10300_dcache_flush_inv_page(unsigned start);	75	extern void mn10300_dcache_flush_inv_page(unsigned start);
76	extern void mn10300_dcache_flush_inv_range(unsigned start, unsigned end);	76	extern void mn10300_dcache_flush_inv_range(unsigned start, unsigned end);
77	extern void mn10300_dcache_flush_inv_range2(unsigned start, unsigned size);	77	extern void mn10300_dcache_flush_inv_range2(unsigned start, unsigned size);
78	#else	78	#else
79	#define mn10300_dcache_flush() do {} while (0)	79	#define mn10300_dcache_flush() do {} while (0)
80	#define mn10300_dcache_flush_page(start) do {} while (0)	80	#define mn10300_dcache_flush_page(start) do {} while (0)
81	#define mn10300_dcache_flush_range(start, end) do {} while (0)	81	#define mn10300_dcache_flush_range(start, end) do {} while (0)
82	#define mn10300_dcache_flush_range2(start, size) do {} while (0)	82	#define mn10300_dcache_flush_range2(start, size) do {} while (0)
83	#define mn10300_dcache_flush_inv() mn10300_dcache_inv()	83	#define mn10300_dcache_flush_inv() mn10300_dcache_inv()
84	#define mn10300_dcache_flush_inv_page(start) \	84	#define mn10300_dcache_flush_inv_page(start) \
85	mn10300_dcache_inv_page((start))	85	mn10300_dcache_inv_page((start))
86	#define mn10300_dcache_flush_inv_range(start, end) \	86	#define mn10300_dcache_flush_inv_range(start, end) \
87	mn10300_dcache_inv_range((start), (end))	87	mn10300_dcache_inv_range((start), (end))
88	#define mn10300_dcache_flush_inv_range2(start, size) \	88	#define mn10300_dcache_flush_inv_range2(start, size) \
89	mn10300_dcache_inv_range2((start), (size))	89	mn10300_dcache_inv_range2((start), (size))
90	#endif /* CONFIG_MN10300_CACHE_WBACK */	90	#endif /* CONFIG_MN10300_CACHE_WBACK */
91	#else	91	#else
92	#define mn10300_icache_inv() do {} while (0)	92	#define mn10300_icache_inv() do {} while (0)
93	#define mn10300_dcache_inv() do {} while (0)	93	#define mn10300_dcache_inv() do {} while (0)
94	#define mn10300_dcache_inv_page(start) do {} while (0)	94	#define mn10300_dcache_inv_page(start) do {} while (0)
95	#define mn10300_dcache_inv_range(start, end) do {} while (0)	95	#define mn10300_dcache_inv_range(start, end) do {} while (0)
96	#define mn10300_dcache_inv_range2(start, size) do {} while (0)	96	#define mn10300_dcache_inv_range2(start, size) do {} while (0)
97	#define mn10300_dcache_flush() do {} while (0)	97	#define mn10300_dcache_flush() do {} while (0)
98	#define mn10300_dcache_flush_inv_page(start) do {} while (0)	98	#define mn10300_dcache_flush_inv_page(start) do {} while (0)
99	#define mn10300_dcache_flush_inv() do {} while (0)	99	#define mn10300_dcache_flush_inv() do {} while (0)
100	#define mn10300_dcache_flush_inv_range(start, end) do {} while (0)	100	#define mn10300_dcache_flush_inv_range(start, end) do {} while (0)
101	#define mn10300_dcache_flush_inv_range2(start, size) do {} while (0)	101	#define mn10300_dcache_flush_inv_range2(start, size) do {} while (0)
102	#define mn10300_dcache_flush_page(start) do {} while (0)	102	#define mn10300_dcache_flush_page(start) do {} while (0)
103	#define mn10300_dcache_flush_range(start, end) do {} while (0)	103	#define mn10300_dcache_flush_range(start, end) do {} while (0)
104	#define mn10300_dcache_flush_range2(start, size) do {} while (0)	104	#define mn10300_dcache_flush_range2(start, size) do {} while (0)
105	#endif /* CONFIG_MN10300_CACHE_DISABLED */	105	#endif /* CONFIG_MN10300_CACHE_DISABLED */
106		106
107	/*	107	/*
108	* internal debugging function	108	* internal debugging function
109	*/	109	*/
110	#ifdef CONFIG_DEBUG_PAGEALLOC	110	#ifdef CONFIG_DEBUG_PAGEALLOC
111	extern void kernel_map_pages(struct page *page, int numpages, int enable);	111	extern void kernel_map_pages(struct page *page, int numpages, int enable);
112	#endif	112	#endif
113		113
114	#endif /* __ASSEMBLY__ */	114	#endif /* __ASSEMBLY__ */
115		115
116	#endif /* _ASM_CACHEFLUSH_H */	116	#endif /* _ASM_CACHEFLUSH_H */
117		117