Eric Lee / linux-smarc-t335x-v3.2

Download as
Browse Code ยป

Commit 3feb24e03d057ea36e09f79402ed67b4c2397ece

Authored by Hebbar, Gururaja
1 parent 99fb0d852a
Exists in master

arm:omap:am335x: fix module build support for Audio 

Module build adds CONFIG_xxx_MODULE config option which different than
regular CONFIG_xxxx option.

This patch corrects the same for audio by checking both options.

Signed-off-by: Hebbar, Gururaja <gururaja.hebbar@ti.com>

Showing 3 changed files with 6 additions and 3 deletions Inline Diff

arch/arm/include/asm/hardware/asp.h
Diff comments   View file @ 3feb24e
1 /* 1 /*
2 * <asm/hardware/asp.h> - DaVinci Audio Serial Port support 2 * <asm/hardware/asp.h> - DaVinci Audio Serial Port support
3 */ 3 */
4 #ifndef __ASM_HARDWARE_MCASP_H 4 #ifndef __ASM_HARDWARE_MCASP_H
5 #define __ASM_HARDWARE_MCASP_H 5 #define __ASM_HARDWARE_MCASP_H
6 6
7 #include <mach/irqs.h> 7 #include <mach/irqs.h>
8 #include <mach/edma.h> 8 #include <mach/edma.h>
9 9
10 /* Bases of dm644x and dm355 register banks */ 10 /* Bases of dm644x and dm355 register banks */
11 #define DAVINCI_ASP0_BASE 0x01E02000 11 #define DAVINCI_ASP0_BASE 0x01E02000
12 #define DAVINCI_ASP1_BASE 0x01E04000 12 #define DAVINCI_ASP1_BASE 0x01E04000
13 13
14 /* Bases of dm365 register banks */ 14 /* Bases of dm365 register banks */
15 #define DAVINCI_DM365_ASP0_BASE 0x01D02000 15 #define DAVINCI_DM365_ASP0_BASE 0x01D02000
16 16
17 /* Bases of dm646x register banks */ 17 /* Bases of dm646x register banks */
18 #define DAVINCI_DM646X_MCASP0_REG_BASE 0x01D01000 18 #define DAVINCI_DM646X_MCASP0_REG_BASE 0x01D01000
19 #define DAVINCI_DM646X_MCASP1_REG_BASE 0x01D01800 19 #define DAVINCI_DM646X_MCASP1_REG_BASE 0x01D01800
20 20
21 /* Bases of da850/da830 McASP0 register banks */ 21 /* Bases of da850/da830 McASP0 register banks */
22 #define DAVINCI_DA8XX_MCASP0_REG_BASE 0x01D00000 22 #define DAVINCI_DA8XX_MCASP0_REG_BASE 0x01D00000
23 23
24 /* Bases of da830 McASP1 register banks */ 24 /* Bases of da830 McASP1 register banks */
25 #define DAVINCI_DA830_MCASP1_REG_BASE 0x01D04000 25 #define DAVINCI_DA830_MCASP1_REG_BASE 0x01D04000
26 26
27 /* EDMA channels of dm644x and dm355 */ 27 /* EDMA channels of dm644x and dm355 */
28 #define DAVINCI_DMA_ASP0_TX 2 28 #define DAVINCI_DMA_ASP0_TX 2
29 #define DAVINCI_DMA_ASP0_RX 3 29 #define DAVINCI_DMA_ASP0_RX 3
30 #define DAVINCI_DMA_ASP1_TX 8 30 #define DAVINCI_DMA_ASP1_TX 8
31 #define DAVINCI_DMA_ASP1_RX 9 31 #define DAVINCI_DMA_ASP1_RX 9
32 32
33 /* EDMA channels of dm646x */ 33 /* EDMA channels of dm646x */
34 #define DAVINCI_DM646X_DMA_MCASP0_AXEVT0 6 34 #define DAVINCI_DM646X_DMA_MCASP0_AXEVT0 6
35 #define DAVINCI_DM646X_DMA_MCASP0_AREVT0 9 35 #define DAVINCI_DM646X_DMA_MCASP0_AREVT0 9
36 #define DAVINCI_DM646X_DMA_MCASP1_AXEVT1 12 36 #define DAVINCI_DM646X_DMA_MCASP1_AXEVT1 12
37 37
38 /* EDMA channels of da850/da830 McASP0 */ 38 /* EDMA channels of da850/da830 McASP0 */
39 #define DAVINCI_DA8XX_DMA_MCASP0_AREVT 0 39 #define DAVINCI_DA8XX_DMA_MCASP0_AREVT 0
40 #define DAVINCI_DA8XX_DMA_MCASP0_AXEVT 1 40 #define DAVINCI_DA8XX_DMA_MCASP0_AXEVT 1
41 41
42 /* EDMA channels of da830 McASP1 */ 42 /* EDMA channels of da830 McASP1 */
43 #define DAVINCI_DA830_DMA_MCASP1_AREVT 2 43 #define DAVINCI_DA830_DMA_MCASP1_AREVT 2
44 #define DAVINCI_DA830_DMA_MCASP1_AXEVT 3 44 #define DAVINCI_DA830_DMA_MCASP1_AXEVT 3
45 45
46 /* Interrupts */ 46 /* Interrupts */
47 #define DAVINCI_ASP0_RX_INT IRQ_MBRINT 47 #define DAVINCI_ASP0_RX_INT IRQ_MBRINT
48 #define DAVINCI_ASP0_TX_INT IRQ_MBXINT 48 #define DAVINCI_ASP0_TX_INT IRQ_MBXINT
49 #define DAVINCI_ASP1_RX_INT IRQ_MBRINT 49 #define DAVINCI_ASP1_RX_INT IRQ_MBRINT
50 #define DAVINCI_ASP1_TX_INT IRQ_MBXINT 50 #define DAVINCI_ASP1_TX_INT IRQ_MBXINT
51 51
52 struct snd_platform_data { 52 struct snd_platform_data {
53 u32 tx_dma_offset; 53 u32 tx_dma_offset;
54 u32 rx_dma_offset; 54 u32 rx_dma_offset;
55 enum dma_event_q asp_chan_q; /* event queue number for ASP channel */ 55 enum dma_event_q asp_chan_q; /* event queue number for ASP channel */
56 enum dma_event_q ram_chan_q; /* event queue number for RAM channel */ 56 enum dma_event_q ram_chan_q; /* event queue number for RAM channel */
57 unsigned int codec_fmt; 57 unsigned int codec_fmt;
58 /* 58 /*
59 * Allowing this is more efficient and eliminates left and right swaps 59 * Allowing this is more efficient and eliminates left and right swaps
60 * caused by underruns, but will swap the left and right channels 60 * caused by underruns, but will swap the left and right channels
61 * when compared to previous behavior. 61 * when compared to previous behavior.
62 */ 62 */
63 unsigned enable_channel_combine:1; 63 unsigned enable_channel_combine:1;
64 unsigned sram_size_playback; 64 unsigned sram_size_playback;
65 unsigned sram_size_capture; 65 unsigned sram_size_capture;
66 66
67 /* 67 /*
68 * If McBSP peripheral gets the clock from an external pin, 68 * If McBSP peripheral gets the clock from an external pin,
69 * there are three chooses, that are MCBSP_CLKX, MCBSP_CLKR 69 * there are three chooses, that are MCBSP_CLKX, MCBSP_CLKR
70 * and MCBSP_CLKS. 70 * and MCBSP_CLKS.
71 * Depending on different hardware connections it is possible 71 * Depending on different hardware connections it is possible
72 * to use this setting to change the behaviour of McBSP 72 * to use this setting to change the behaviour of McBSP
73 * driver. The dm365_clk_input_pin enum is available for dm365 73 * driver. The dm365_clk_input_pin enum is available for dm365
74 */ 74 */
75 int clk_input_pin; 75 int clk_input_pin;
76 76
77 /* 77 /*
78 * This flag works when both clock and FS are outputs for the cpu 78 * This flag works when both clock and FS are outputs for the cpu
79 * and makes clock more accurate (FS is not symmetrical and the 79 * and makes clock more accurate (FS is not symmetrical and the
80 * clock is very fast. 80 * clock is very fast.
81 * The clock becoming faster is named 81 * The clock becoming faster is named
82 * i2s continuous serial clock (I2S_SCK) and it is an externally 82 * i2s continuous serial clock (I2S_SCK) and it is an externally
83 * visible bit clock. 83 * visible bit clock.
84 * 84 *
85 * first line : WordSelect 85 * first line : WordSelect
86 * second line : ContinuousSerialClock 86 * second line : ContinuousSerialClock
87 * third line: SerialData 87 * third line: SerialData
88 * 88 *
89 * SYMMETRICAL APPROACH: 89 * SYMMETRICAL APPROACH:
90 * _______________________ LEFT 90 * _______________________ LEFT
91 * _| RIGHT |______________________| 91 * _| RIGHT |______________________|
92 * _ _ _ _ _ _ _ _ 92 * _ _ _ _ _ _ _ _
93 * _| |_| |_ x16 _| |_| |_| |_| |_ x16 _| |_| |_ 93 * _| |_| |_ x16 _| |_| |_| |_| |_ x16 _| |_| |_
94 * _ _ _ _ _ _ _ _ 94 * _ _ _ _ _ _ _ _
95 * _/ \_/ \_ ... _/ \_/ \_/ \_/ \_ ... _/ \_/ \_ 95 * _/ \_/ \_ ... _/ \_/ \_/ \_/ \_ ... _/ \_/ \_
96 * \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ 96 * \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/
97 * 97 *
98 * ACCURATE CLOCK APPROACH: 98 * ACCURATE CLOCK APPROACH:
99 * ______________ LEFT 99 * ______________ LEFT
100 * _| RIGHT |_______________________________| 100 * _| RIGHT |_______________________________|
101 * _ _ _ _ _ _ _ _ _ 101 * _ _ _ _ _ _ _ _ _
102 * _| |_ x16 _| |_| |_ x16 _| |_| |_| |_| |_| |_| | 102 * _| |_ x16 _| |_| |_ x16 _| |_| |_| |_| |_| |_| |
103 * _ _ _ _ dummy cycles 103 * _ _ _ _ dummy cycles
104 * _/ \_ ... _/ \_/ \_ ... _/ \__________________ 104 * _/ \_ ... _/ \_/ \_ ... _/ \__________________
105 * \_/ \_/ \_/ \_/ 105 * \_/ \_/ \_/ \_/
106 * 106 *
107 */ 107 */
108 bool i2s_accurate_sck; 108 bool i2s_accurate_sck;
109 109
110 /* McASP specific fields */ 110 /* McASP specific fields */
111 int tdm_slots; 111 int tdm_slots;
112 u8 op_mode; 112 u8 op_mode;
113 u8 num_serializer; 113 u8 num_serializer;
114 u8 *serial_dir; 114 u8 *serial_dir;
115 u8 version; 115 u8 version;
116 u8 txnumevt; 116 u8 txnumevt;
117 u8 rxnumevt; 117 u8 rxnumevt;
118 }; 118 };
119 119
120 enum { 120 enum {
121 MCASP_VERSION_1 = 0, /* DM646x */ 121 MCASP_VERSION_1 = 0, /* DM646x */
122 MCASP_VERSION_2, /* DA8xx/OMAPL1x */ 122 MCASP_VERSION_2, /* DA8xx/OMAPL1x */
123 MCASP_VERSION_3, /* AM33xx */ 123 MCASP_VERSION_3, /* AM33xx */
124 }; 124 };
125 125
126 enum dm365_clk_input_pin { 126 enum dm365_clk_input_pin {
127 MCBSP_CLKR = 0, /* DM365 */ 127 MCBSP_CLKR = 0, /* DM365 */
128 MCBSP_CLKS, 128 MCBSP_CLKS,
129 }; 129 };
130 130
131 #define INACTIVE_MODE 0 131 #define INACTIVE_MODE 0
132 #define TX_MODE 1 132 #define TX_MODE 1
133 #define RX_MODE 2 133 #define RX_MODE 2
134 134
135 #define DAVINCI_MCASP_IIS_MODE 0 135 #define DAVINCI_MCASP_IIS_MODE 0
136 #define DAVINCI_MCASP_DIT_MODE 1 136 #define DAVINCI_MCASP_DIT_MODE 1
137 137
138 #if (defined(CONFIG_SOC_OMAPAM33XX) && defined(CONFIG_SND_AM33XX_SOC)) 138 #if (defined(CONFIG_SOC_OMAPAM33XX) && (defined(CONFIG_SND_AM33XX_SOC) \
139 || (defined(CONFIG_SND_AM33XX_SOC_MODULE))))
139 #define davinci_gen_pool omap_gen_pool 140 #define davinci_gen_pool omap_gen_pool
140 #endif 141 #endif
141 142
142 #endif /* __ASM_HARDWARE_MCASP_H */ 143 #endif /* __ASM_HARDWARE_MCASP_H */
143 144
arch/arm/mach-omap2/devices.c
Diff comments   View file @ 3feb24e
1 /* 1 /*
2 * linux/arch/arm/mach-omap2/devices.c 2 * linux/arch/arm/mach-omap2/devices.c
3 * 3 *
4 * OMAP2 platform device setup/initialization 4 * OMAP2 platform device setup/initialization
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or 8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version. 9 * (at your option) any later version.
10 */ 10 */
11 11
12 #include <linux/kernel.h> 12 #include <linux/kernel.h>
13 #include <linux/init.h> 13 #include <linux/init.h>
14 #include <linux/platform_device.h> 14 #include <linux/platform_device.h>
15 #include <linux/io.h> 15 #include <linux/io.h>
16 #include <linux/clk.h> 16 #include <linux/clk.h>
17 #include <linux/err.h> 17 #include <linux/err.h>
18 #include <linux/slab.h> 18 #include <linux/slab.h>
19 #include <linux/of.h> 19 #include <linux/of.h>
20 #include <linux/davinci_emac.h> 20 #include <linux/davinci_emac.h>
21 #include <linux/cpsw.h> 21 #include <linux/cpsw.h>
22 #include <linux/etherdevice.h> 22 #include <linux/etherdevice.h>
23 #include <linux/dma-mapping.h> 23 #include <linux/dma-mapping.h>
24 #include <linux/can/platform/d_can.h> 24 #include <linux/can/platform/d_can.h>
25 #include <linux/platform_data/uio_pruss.h> 25 #include <linux/platform_data/uio_pruss.h>
26 26
27 #include <mach/hardware.h> 27 #include <mach/hardware.h>
28 #include <mach/irqs.h> 28 #include <mach/irqs.h>
29 #include <mach/board-am335xevm.h> 29 #include <mach/board-am335xevm.h>
30 #include <asm/mach-types.h> 30 #include <asm/mach-types.h>
31 #include <asm/mach/map.h> 31 #include <asm/mach/map.h>
32 #include <asm/pmu.h> 32 #include <asm/pmu.h>
33 33
34 #ifdef CONFIG_OMAP3_EDMA 34 #ifdef CONFIG_OMAP3_EDMA
35 #include <mach/edma.h> 35 #include <mach/edma.h>
36 #endif 36 #endif
37 37
38 #include <asm/hardware/asp.h> 38 #include <asm/hardware/asp.h>
39 39
40 #include <plat/tc.h> 40 #include <plat/tc.h>
41 #include <plat/board.h> 41 #include <plat/board.h>
42 #include <plat/mcbsp.h> 42 #include <plat/mcbsp.h>
43 #include <mach/gpio.h> 43 #include <mach/gpio.h>
44 #include <plat/mmc.h> 44 #include <plat/mmc.h>
45 #include <plat/dma.h> 45 #include <plat/dma.h>
46 #include <plat/omap_hwmod.h> 46 #include <plat/omap_hwmod.h>
47 #include <plat/omap_device.h> 47 #include <plat/omap_device.h>
48 #include <plat/omap4-keypad.h> 48 #include <plat/omap4-keypad.h>
49 49
50 /* LCD controller similar DA8xx */ 50 /* LCD controller similar DA8xx */
51 #include <video/da8xx-fb.h> 51 #include <video/da8xx-fb.h>
52 52
53 #include "mux.h" 53 #include "mux.h"
54 #include "control.h" 54 #include "control.h"
55 #include "devices.h" 55 #include "devices.h"
56 56
57 #define L3_MODULES_MAX_LEN 12 57 #define L3_MODULES_MAX_LEN 12
58 #define L3_MODULES 3 58 #define L3_MODULES 3
59 59
60 static int __init omap3_l3_init(void) 60 static int __init omap3_l3_init(void)
61 { 61 {
62 int l; 62 int l;
63 struct omap_hwmod *oh; 63 struct omap_hwmod *oh;
64 struct platform_device *pdev; 64 struct platform_device *pdev;
65 char oh_name[L3_MODULES_MAX_LEN]; 65 char oh_name[L3_MODULES_MAX_LEN];
66 66
67 /* 67 /*
68 * To avoid code running on other OMAPs in 68 * To avoid code running on other OMAPs in
69 * multi-omap builds 69 * multi-omap builds
70 */ 70 */
71 if (!(cpu_is_omap34xx())) 71 if (!(cpu_is_omap34xx()))
72 return -ENODEV; 72 return -ENODEV;
73 73
74 l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main"); 74 l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main");
75 75
76 oh = omap_hwmod_lookup(oh_name); 76 oh = omap_hwmod_lookup(oh_name);
77 77
78 if (!oh) 78 if (!oh)
79 pr_err("could not look up %s\n", oh_name); 79 pr_err("could not look up %s\n", oh_name);
80 80
81 pdev = omap_device_build("omap_l3_smx", 0, oh, NULL, 0, 81 pdev = omap_device_build("omap_l3_smx", 0, oh, NULL, 0,
82 NULL, 0, 0); 82 NULL, 0, 0);
83 83
84 WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name); 84 WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
85 85
86 return IS_ERR(pdev) ? PTR_ERR(pdev) : 0; 86 return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
87 } 87 }
88 postcore_initcall(omap3_l3_init); 88 postcore_initcall(omap3_l3_init);
89 89
90 static int __init omap4_l3_init(void) 90 static int __init omap4_l3_init(void)
91 { 91 {
92 int l, i; 92 int l, i;
93 struct omap_hwmod *oh[3]; 93 struct omap_hwmod *oh[3];
94 struct platform_device *pdev; 94 struct platform_device *pdev;
95 char oh_name[L3_MODULES_MAX_LEN]; 95 char oh_name[L3_MODULES_MAX_LEN];
96 96
97 /* If dtb is there, the devices will be created dynamically */ 97 /* If dtb is there, the devices will be created dynamically */
98 if (of_have_populated_dt()) 98 if (of_have_populated_dt())
99 return -ENODEV; 99 return -ENODEV;
100 100
101 /* 101 /*
102 * To avoid code running on other OMAPs in 102 * To avoid code running on other OMAPs in
103 * multi-omap builds 103 * multi-omap builds
104 */ 104 */
105 if (!(cpu_is_omap44xx())) 105 if (!(cpu_is_omap44xx()))
106 return -ENODEV; 106 return -ENODEV;
107 107
108 for (i = 0; i < L3_MODULES; i++) { 108 for (i = 0; i < L3_MODULES; i++) {
109 l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main_%d", i+1); 109 l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main_%d", i+1);
110 110
111 oh[i] = omap_hwmod_lookup(oh_name); 111 oh[i] = omap_hwmod_lookup(oh_name);
112 if (!(oh[i])) 112 if (!(oh[i]))
113 pr_err("could not look up %s\n", oh_name); 113 pr_err("could not look up %s\n", oh_name);
114 } 114 }
115 115
116 pdev = omap_device_build_ss("omap_l3_noc", 0, oh, 3, NULL, 116 pdev = omap_device_build_ss("omap_l3_noc", 0, oh, 3, NULL,
117 0, NULL, 0, 0); 117 0, NULL, 0, 0);
118 118
119 WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name); 119 WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
120 120
121 return IS_ERR(pdev) ? PTR_ERR(pdev) : 0; 121 return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
122 } 122 }
123 postcore_initcall(omap4_l3_init); 123 postcore_initcall(omap4_l3_init);
124 124
125 #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE) 125 #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
126 126
127 static struct resource omap2cam_resources[] = { 127 static struct resource omap2cam_resources[] = {
128 { 128 {
129 .start = OMAP24XX_CAMERA_BASE, 129 .start = OMAP24XX_CAMERA_BASE,
130 .end = OMAP24XX_CAMERA_BASE + 0xfff, 130 .end = OMAP24XX_CAMERA_BASE + 0xfff,
131 .flags = IORESOURCE_MEM, 131 .flags = IORESOURCE_MEM,
132 }, 132 },
133 { 133 {
134 .start = INT_24XX_CAM_IRQ, 134 .start = INT_24XX_CAM_IRQ,
135 .flags = IORESOURCE_IRQ, 135 .flags = IORESOURCE_IRQ,
136 } 136 }
137 }; 137 };
138 138
139 static struct platform_device omap2cam_device = { 139 static struct platform_device omap2cam_device = {
140 .name = "omap24xxcam", 140 .name = "omap24xxcam",
141 .id = -1, 141 .id = -1,
142 .num_resources = ARRAY_SIZE(omap2cam_resources), 142 .num_resources = ARRAY_SIZE(omap2cam_resources),
143 .resource = omap2cam_resources, 143 .resource = omap2cam_resources,
144 }; 144 };
145 #endif 145 #endif
146 #define L4_PER_LCDC_PHYS 0x4830E000 146 #define L4_PER_LCDC_PHYS 0x4830E000
147 147
148 static struct resource am33xx_lcdc_resources[] = { 148 static struct resource am33xx_lcdc_resources[] = {
149 [0] = { /* registers */ 149 [0] = { /* registers */
150 .start = L4_PER_LCDC_PHYS, 150 .start = L4_PER_LCDC_PHYS,
151 .end = L4_PER_LCDC_PHYS + SZ_4K - 1, 151 .end = L4_PER_LCDC_PHYS + SZ_4K - 1,
152 .flags = IORESOURCE_MEM, 152 .flags = IORESOURCE_MEM,
153 }, 153 },
154 [1] = { /* interrupt */ 154 [1] = { /* interrupt */
155 .start = AM33XX_IRQ_LCD, 155 .start = AM33XX_IRQ_LCD,
156 .end = AM33XX_IRQ_LCD, 156 .end = AM33XX_IRQ_LCD,
157 .flags = IORESOURCE_IRQ, 157 .flags = IORESOURCE_IRQ,
158 }, 158 },
159 }; 159 };
160 160
161 static struct platform_device am33xx_lcdc_device = { 161 static struct platform_device am33xx_lcdc_device = {
162 .name = "da8xx_lcdc", 162 .name = "da8xx_lcdc",
163 .id = 0, 163 .id = 0,
164 .num_resources = ARRAY_SIZE(am33xx_lcdc_resources), 164 .num_resources = ARRAY_SIZE(am33xx_lcdc_resources),
165 .resource = am33xx_lcdc_resources, 165 .resource = am33xx_lcdc_resources,
166 }; 166 };
167 167
168 void __init am33xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata) 168 void __init am33xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata)
169 { 169 {
170 int ret; 170 int ret;
171 171
172 am33xx_lcdc_device.dev.platform_data = pdata; 172 am33xx_lcdc_device.dev.platform_data = pdata;
173 173
174 ret = platform_device_register(&am33xx_lcdc_device); 174 ret = platform_device_register(&am33xx_lcdc_device);
175 if (ret) 175 if (ret)
176 pr_warning("am33xx_register_lcdc: lcdc registration failed: %d\n", 176 pr_warning("am33xx_register_lcdc: lcdc registration failed: %d\n",
177 ret); 177 ret);
178 178
179 } 179 }
180 180
181 #if defined (CONFIG_SND_AM335X_SOC_EVM) 181 #if defined(CONFIG_SND_AM335X_SOC_EVM) || \
182 defined(CONFIG_SND_AM335X_SOC_EVM_MODULE)
182 static struct resource am335x_mcasp1_resource[] = { 183 static struct resource am335x_mcasp1_resource[] = {
183 { 184 {
184 .name = "mcasp1", 185 .name = "mcasp1",
185 .start = AM33XX_ASP1_BASE, 186 .start = AM33XX_ASP1_BASE,
186 .end = AM33XX_ASP1_BASE + (SZ_1K * 12) - 1, 187 .end = AM33XX_ASP1_BASE + (SZ_1K * 12) - 1,
187 .flags = IORESOURCE_MEM, 188 .flags = IORESOURCE_MEM,
188 }, 189 },
189 /* TX event */ 190 /* TX event */
190 { 191 {
191 .start = AM33XX_DMA_MCASP1_X, 192 .start = AM33XX_DMA_MCASP1_X,
192 .end = AM33XX_DMA_MCASP1_X, 193 .end = AM33XX_DMA_MCASP1_X,
193 .flags = IORESOURCE_DMA, 194 .flags = IORESOURCE_DMA,
194 }, 195 },
195 /* RX event */ 196 /* RX event */
196 { 197 {
197 .start = AM33XX_DMA_MCASP1_R, 198 .start = AM33XX_DMA_MCASP1_R,
198 .end = AM33XX_DMA_MCASP1_R, 199 .end = AM33XX_DMA_MCASP1_R,
199 .flags = IORESOURCE_DMA, 200 .flags = IORESOURCE_DMA,
200 }, 201 },
201 }; 202 };
202 203
203 static struct platform_device am335x_mcasp1_device = { 204 static struct platform_device am335x_mcasp1_device = {
204 .name = "davinci-mcasp", 205 .name = "davinci-mcasp",
205 .id = 1, 206 .id = 1,
206 .num_resources = ARRAY_SIZE(am335x_mcasp1_resource), 207 .num_resources = ARRAY_SIZE(am335x_mcasp1_resource),
207 .resource = am335x_mcasp1_resource, 208 .resource = am335x_mcasp1_resource,
208 }; 209 };
209 210
210 void __init am335x_register_mcasp1(struct snd_platform_data *pdata) 211 void __init am335x_register_mcasp1(struct snd_platform_data *pdata)
211 { 212 {
212 am335x_mcasp1_device.dev.platform_data = pdata; 213 am335x_mcasp1_device.dev.platform_data = pdata;
213 platform_device_register(&am335x_mcasp1_device); 214 platform_device_register(&am335x_mcasp1_device);
214 } 215 }
215 216
216 #else 217 #else
217 void __init am335x_register_mcasp1(struct snd_platform_data *pdata) {} 218 void __init am335x_register_mcasp1(struct snd_platform_data *pdata) {}
218 #endif 219 #endif
219 220
220 #if defined(CONFIG_SND_AM33XX_SOC) 221 #if (defined(CONFIG_SND_AM33XX_SOC) || (defined(CONFIG_SND_AM33XX_SOC_MODULE)))
221 struct platform_device am33xx_pcm_device = { 222 struct platform_device am33xx_pcm_device = {
222 .name = "davinci-pcm-audio", 223 .name = "davinci-pcm-audio",
223 .id = -1, 224 .id = -1,
224 }; 225 };
225 226
226 static void am33xx_init_pcm(void) 227 static void am33xx_init_pcm(void)
227 { 228 {
228 platform_device_register(&am33xx_pcm_device); 229 platform_device_register(&am33xx_pcm_device);
229 } 230 }
230 231
231 #else 232 #else
232 static inline void am33xx_init_pcm(void) {} 233 static inline void am33xx_init_pcm(void) {}
233 #endif 234 #endif
234 235
235 static struct resource omap3isp_resources[] = { 236 static struct resource omap3isp_resources[] = {
236 { 237 {
237 .start = OMAP3430_ISP_BASE, 238 .start = OMAP3430_ISP_BASE,
238 .end = OMAP3430_ISP_END, 239 .end = OMAP3430_ISP_END,
239 .flags = IORESOURCE_MEM, 240 .flags = IORESOURCE_MEM,
240 }, 241 },
241 { 242 {
242 .start = OMAP3430_ISP_CCP2_BASE, 243 .start = OMAP3430_ISP_CCP2_BASE,
243 .end = OMAP3430_ISP_CCP2_END, 244 .end = OMAP3430_ISP_CCP2_END,
244 .flags = IORESOURCE_MEM, 245 .flags = IORESOURCE_MEM,
245 }, 246 },
246 { 247 {
247 .start = OMAP3430_ISP_CCDC_BASE, 248 .start = OMAP3430_ISP_CCDC_BASE,
248 .end = OMAP3430_ISP_CCDC_END, 249 .end = OMAP3430_ISP_CCDC_END,
249 .flags = IORESOURCE_MEM, 250 .flags = IORESOURCE_MEM,
250 }, 251 },
251 { 252 {
252 .start = OMAP3430_ISP_HIST_BASE, 253 .start = OMAP3430_ISP_HIST_BASE,
253 .end = OMAP3430_ISP_HIST_END, 254 .end = OMAP3430_ISP_HIST_END,
254 .flags = IORESOURCE_MEM, 255 .flags = IORESOURCE_MEM,
255 }, 256 },
256 { 257 {
257 .start = OMAP3430_ISP_H3A_BASE, 258 .start = OMAP3430_ISP_H3A_BASE,
258 .end = OMAP3430_ISP_H3A_END, 259 .end = OMAP3430_ISP_H3A_END,
259 .flags = IORESOURCE_MEM, 260 .flags = IORESOURCE_MEM,
260 }, 261 },
261 { 262 {
262 .start = OMAP3430_ISP_PREV_BASE, 263 .start = OMAP3430_ISP_PREV_BASE,
263 .end = OMAP3430_ISP_PREV_END, 264 .end = OMAP3430_ISP_PREV_END,
264 .flags = IORESOURCE_MEM, 265 .flags = IORESOURCE_MEM,
265 }, 266 },
266 { 267 {
267 .start = OMAP3430_ISP_RESZ_BASE, 268 .start = OMAP3430_ISP_RESZ_BASE,
268 .end = OMAP3430_ISP_RESZ_END, 269 .end = OMAP3430_ISP_RESZ_END,
269 .flags = IORESOURCE_MEM, 270 .flags = IORESOURCE_MEM,
270 }, 271 },
271 { 272 {
272 .start = OMAP3430_ISP_SBL_BASE, 273 .start = OMAP3430_ISP_SBL_BASE,
273 .end = OMAP3430_ISP_SBL_END, 274 .end = OMAP3430_ISP_SBL_END,
274 .flags = IORESOURCE_MEM, 275 .flags = IORESOURCE_MEM,
275 }, 276 },
276 { 277 {
277 .start = OMAP3430_ISP_CSI2A_REGS1_BASE, 278 .start = OMAP3430_ISP_CSI2A_REGS1_BASE,
278 .end = OMAP3430_ISP_CSI2A_REGS1_END, 279 .end = OMAP3430_ISP_CSI2A_REGS1_END,
279 .flags = IORESOURCE_MEM, 280 .flags = IORESOURCE_MEM,
280 }, 281 },
281 { 282 {
282 .start = OMAP3430_ISP_CSIPHY2_BASE, 283 .start = OMAP3430_ISP_CSIPHY2_BASE,
283 .end = OMAP3430_ISP_CSIPHY2_END, 284 .end = OMAP3430_ISP_CSIPHY2_END,
284 .flags = IORESOURCE_MEM, 285 .flags = IORESOURCE_MEM,
285 }, 286 },
286 { 287 {
287 .start = OMAP3630_ISP_CSI2A_REGS2_BASE, 288 .start = OMAP3630_ISP_CSI2A_REGS2_BASE,
288 .end = OMAP3630_ISP_CSI2A_REGS2_END, 289 .end = OMAP3630_ISP_CSI2A_REGS2_END,
289 .flags = IORESOURCE_MEM, 290 .flags = IORESOURCE_MEM,
290 }, 291 },
291 { 292 {
292 .start = OMAP3630_ISP_CSI2C_REGS1_BASE, 293 .start = OMAP3630_ISP_CSI2C_REGS1_BASE,
293 .end = OMAP3630_ISP_CSI2C_REGS1_END, 294 .end = OMAP3630_ISP_CSI2C_REGS1_END,
294 .flags = IORESOURCE_MEM, 295 .flags = IORESOURCE_MEM,
295 }, 296 },
296 { 297 {
297 .start = OMAP3630_ISP_CSIPHY1_BASE, 298 .start = OMAP3630_ISP_CSIPHY1_BASE,
298 .end = OMAP3630_ISP_CSIPHY1_END, 299 .end = OMAP3630_ISP_CSIPHY1_END,
299 .flags = IORESOURCE_MEM, 300 .flags = IORESOURCE_MEM,
300 }, 301 },
301 { 302 {
302 .start = OMAP3630_ISP_CSI2C_REGS2_BASE, 303 .start = OMAP3630_ISP_CSI2C_REGS2_BASE,
303 .end = OMAP3630_ISP_CSI2C_REGS2_END, 304 .end = OMAP3630_ISP_CSI2C_REGS2_END,
304 .flags = IORESOURCE_MEM, 305 .flags = IORESOURCE_MEM,
305 }, 306 },
306 { 307 {
307 .start = INT_34XX_CAM_IRQ, 308 .start = INT_34XX_CAM_IRQ,
308 .flags = IORESOURCE_IRQ, 309 .flags = IORESOURCE_IRQ,
309 } 310 }
310 }; 311 };
311 312
312 static struct platform_device omap3isp_device = { 313 static struct platform_device omap3isp_device = {
313 .name = "omap3isp", 314 .name = "omap3isp",
314 .id = -1, 315 .id = -1,
315 .num_resources = ARRAY_SIZE(omap3isp_resources), 316 .num_resources = ARRAY_SIZE(omap3isp_resources),
316 .resource = omap3isp_resources, 317 .resource = omap3isp_resources,
317 }; 318 };
318 319
319 int omap3_init_camera(struct isp_platform_data *pdata) 320 int omap3_init_camera(struct isp_platform_data *pdata)
320 { 321 {
321 omap3isp_device.dev.platform_data = pdata; 322 omap3isp_device.dev.platform_data = pdata;
322 return platform_device_register(&omap3isp_device); 323 return platform_device_register(&omap3isp_device);
323 } 324 }
324 325
325 static inline void omap_init_camera(void) 326 static inline void omap_init_camera(void)
326 { 327 {
327 #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE) 328 #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
328 if (cpu_is_omap24xx()) 329 if (cpu_is_omap24xx())
329 platform_device_register(&omap2cam_device); 330 platform_device_register(&omap2cam_device);
330 #endif 331 #endif
331 } 332 }
332 333
333 int __init omap4_keyboard_init(struct omap4_keypad_platform_data 334 int __init omap4_keyboard_init(struct omap4_keypad_platform_data
334 *sdp4430_keypad_data, struct omap_board_data *bdata) 335 *sdp4430_keypad_data, struct omap_board_data *bdata)
335 { 336 {
336 struct platform_device *pdev; 337 struct platform_device *pdev;
337 struct omap_hwmod *oh; 338 struct omap_hwmod *oh;
338 struct omap4_keypad_platform_data *keypad_data; 339 struct omap4_keypad_platform_data *keypad_data;
339 unsigned int id = -1; 340 unsigned int id = -1;
340 char *oh_name = "kbd"; 341 char *oh_name = "kbd";
341 char *name = "omap4-keypad"; 342 char *name = "omap4-keypad";
342 343
343 oh = omap_hwmod_lookup(oh_name); 344 oh = omap_hwmod_lookup(oh_name);
344 if (!oh) { 345 if (!oh) {
345 pr_err("Could not look up %s\n", oh_name); 346 pr_err("Could not look up %s\n", oh_name);
346 return -ENODEV; 347 return -ENODEV;
347 } 348 }
348 349
349 keypad_data = sdp4430_keypad_data; 350 keypad_data = sdp4430_keypad_data;
350 351
351 pdev = omap_device_build(name, id, oh, keypad_data, 352 pdev = omap_device_build(name, id, oh, keypad_data,
352 sizeof(struct omap4_keypad_platform_data), NULL, 0, 0); 353 sizeof(struct omap4_keypad_platform_data), NULL, 0, 0);
353 354
354 if (IS_ERR(pdev)) { 355 if (IS_ERR(pdev)) {
355 WARN(1, "Can't build omap_device for %s:%s.\n", 356 WARN(1, "Can't build omap_device for %s:%s.\n",
356 name, oh->name); 357 name, oh->name);
357 return PTR_ERR(pdev); 358 return PTR_ERR(pdev);
358 } 359 }
359 oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt); 360 oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt);
360 361
361 return 0; 362 return 0;
362 } 363 }
363 364
364 #if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE) 365 #if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
365 static inline void omap_init_mbox(void) 366 static inline void omap_init_mbox(void)
366 { 367 {
367 struct omap_hwmod *oh; 368 struct omap_hwmod *oh;
368 struct platform_device *pdev; 369 struct platform_device *pdev;
369 370
370 oh = omap_hwmod_lookup("mailbox"); 371 oh = omap_hwmod_lookup("mailbox");
371 if (!oh) { 372 if (!oh) {
372 pr_err("%s: unable to find hwmod\n", __func__); 373 pr_err("%s: unable to find hwmod\n", __func__);
373 return; 374 return;
374 } 375 }
375 376
376 pdev = omap_device_build("omap-mailbox", -1, oh, NULL, 0, NULL, 0, 0); 377 pdev = omap_device_build("omap-mailbox", -1, oh, NULL, 0, NULL, 0, 0);
377 WARN(IS_ERR(pdev), "%s: could not build device, err %ld\n", 378 WARN(IS_ERR(pdev), "%s: could not build device, err %ld\n",
378 __func__, PTR_ERR(pdev)); 379 __func__, PTR_ERR(pdev));
379 } 380 }
380 #else 381 #else
381 static inline void omap_init_mbox(void) { } 382 static inline void omap_init_mbox(void) { }
382 #endif /* CONFIG_OMAP_MBOX_FWK */ 383 #endif /* CONFIG_OMAP_MBOX_FWK */
383 384
384 static inline void omap_init_sti(void) {} 385 static inline void omap_init_sti(void) {}
385 386
386 #if defined(CONFIG_SND_SOC) || defined(CONFIG_SND_SOC_MODULE) 387 #if defined(CONFIG_SND_SOC) || defined(CONFIG_SND_SOC_MODULE)
387 388
388 static struct platform_device omap_pcm = { 389 static struct platform_device omap_pcm = {
389 .name = "omap-pcm-audio", 390 .name = "omap-pcm-audio",
390 .id = -1, 391 .id = -1,
391 }; 392 };
392 393
393 /* 394 /*
394 * OMAP2420 has 2 McBSP ports 395 * OMAP2420 has 2 McBSP ports
395 * OMAP2430 has 5 McBSP ports 396 * OMAP2430 has 5 McBSP ports
396 * OMAP3 has 5 McBSP ports 397 * OMAP3 has 5 McBSP ports
397 * OMAP4 has 4 McBSP ports 398 * OMAP4 has 4 McBSP ports
398 */ 399 */
399 OMAP_MCBSP_PLATFORM_DEVICE(1); 400 OMAP_MCBSP_PLATFORM_DEVICE(1);
400 OMAP_MCBSP_PLATFORM_DEVICE(2); 401 OMAP_MCBSP_PLATFORM_DEVICE(2);
401 OMAP_MCBSP_PLATFORM_DEVICE(3); 402 OMAP_MCBSP_PLATFORM_DEVICE(3);
402 OMAP_MCBSP_PLATFORM_DEVICE(4); 403 OMAP_MCBSP_PLATFORM_DEVICE(4);
403 OMAP_MCBSP_PLATFORM_DEVICE(5); 404 OMAP_MCBSP_PLATFORM_DEVICE(5);
404 405
405 static void omap_init_audio(void) 406 static void omap_init_audio(void)
406 { 407 {
407 platform_device_register(&omap_mcbsp1); 408 platform_device_register(&omap_mcbsp1);
408 platform_device_register(&omap_mcbsp2); 409 platform_device_register(&omap_mcbsp2);
409 if (cpu_is_omap243x() || cpu_is_omap34xx() || cpu_is_omap44xx()) { 410 if (cpu_is_omap243x() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
410 platform_device_register(&omap_mcbsp3); 411 platform_device_register(&omap_mcbsp3);
411 platform_device_register(&omap_mcbsp4); 412 platform_device_register(&omap_mcbsp4);
412 } 413 }
413 if (cpu_is_omap243x() || cpu_is_omap34xx()) 414 if (cpu_is_omap243x() || cpu_is_omap34xx())
414 platform_device_register(&omap_mcbsp5); 415 platform_device_register(&omap_mcbsp5);
415 416
416 platform_device_register(&omap_pcm); 417 platform_device_register(&omap_pcm);
417 } 418 }
418 419
419 #else 420 #else
420 static inline void omap_init_audio(void) {} 421 static inline void omap_init_audio(void) {}
421 #endif 422 #endif
422 423
423 #if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE) 424 #if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
424 425
425 #include <plat/mcspi.h> 426 #include <plat/mcspi.h>
426 427
427 static int omap_mcspi_init(struct omap_hwmod *oh, void *unused) 428 static int omap_mcspi_init(struct omap_hwmod *oh, void *unused)
428 { 429 {
429 struct platform_device *pdev; 430 struct platform_device *pdev;
430 char *name = "omap2_mcspi"; 431 char *name = "omap2_mcspi";
431 struct omap2_mcspi_platform_config *pdata; 432 struct omap2_mcspi_platform_config *pdata;
432 static int spi_num; 433 static int spi_num;
433 struct omap2_mcspi_dev_attr *mcspi_attrib = oh->dev_attr; 434 struct omap2_mcspi_dev_attr *mcspi_attrib = oh->dev_attr;
434 435
435 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); 436 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
436 if (!pdata) { 437 if (!pdata) {
437 pr_err("Memory allocation for McSPI device failed\n"); 438 pr_err("Memory allocation for McSPI device failed\n");
438 return -ENOMEM; 439 return -ENOMEM;
439 } 440 }
440 441
441 pdata->num_cs = mcspi_attrib->num_chipselect; 442 pdata->num_cs = mcspi_attrib->num_chipselect;
442 switch (oh->class->rev) { 443 switch (oh->class->rev) {
443 case OMAP2_MCSPI_REV: 444 case OMAP2_MCSPI_REV:
444 case OMAP3_MCSPI_REV: 445 case OMAP3_MCSPI_REV:
445 pdata->regs_offset = 0; 446 pdata->regs_offset = 0;
446 break; 447 break;
447 case OMAP4_MCSPI_REV: 448 case OMAP4_MCSPI_REV:
448 pdata->regs_offset = OMAP4_MCSPI_REG_OFFSET; 449 pdata->regs_offset = OMAP4_MCSPI_REG_OFFSET;
449 break; 450 break;
450 default: 451 default:
451 pr_err("Invalid McSPI Revision value\n"); 452 pr_err("Invalid McSPI Revision value\n");
452 return -EINVAL; 453 return -EINVAL;
453 } 454 }
454 455
455 spi_num++; 456 spi_num++;
456 pdev = omap_device_build(name, spi_num, oh, pdata, 457 pdev = omap_device_build(name, spi_num, oh, pdata,
457 sizeof(*pdata), NULL, 0, 0); 458 sizeof(*pdata), NULL, 0, 0);
458 WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s\n", 459 WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s\n",
459 name, oh->name); 460 name, oh->name);
460 kfree(pdata); 461 kfree(pdata);
461 return 0; 462 return 0;
462 } 463 }
463 464
464 static void omap_init_mcspi(void) 465 static void omap_init_mcspi(void)
465 { 466 {
466 omap_hwmod_for_each_by_class("mcspi", omap_mcspi_init, NULL); 467 omap_hwmod_for_each_by_class("mcspi", omap_mcspi_init, NULL);
467 } 468 }
468 469
469 #else 470 #else
470 static inline void omap_init_mcspi(void) {} 471 static inline void omap_init_mcspi(void) {}
471 #endif 472 #endif
472 473
473 #ifdef CONFIG_SOC_OMAPAM33XX 474 #ifdef CONFIG_SOC_OMAPAM33XX
474 475
475 static int omap_elm_init(struct omap_hwmod *oh, void *unused) 476 static int omap_elm_init(struct omap_hwmod *oh, void *unused)
476 { 477 {
477 struct platform_device *pdev; 478 struct platform_device *pdev;
478 char *name = "omap2_elm"; 479 char *name = "omap2_elm";
479 static int elm_num; 480 static int elm_num;
480 481
481 482
482 elm_num++; 483 elm_num++;
483 pdev = omap_device_build(name, elm_num, oh, NULL, 484 pdev = omap_device_build(name, elm_num, oh, NULL,
484 0, NULL, 485 0, NULL,
485 0, 0); 486 0, 0);
486 return 0; 487 return 0;
487 } 488 }
488 489
489 static void omap_init_elm(void) 490 static void omap_init_elm(void)
490 { 491 {
491 492
492 omap_hwmod_for_each_by_class("elm", omap_elm_init, NULL); 493 omap_hwmod_for_each_by_class("elm", omap_elm_init, NULL);
493 } 494 }
494 495
495 #else 496 #else
496 static void omap_init_elm(void) {} 497 static void omap_init_elm(void) {}
497 #endif 498 #endif
498 499
499 500
500 static struct resource omap2_pmu_resource = { 501 static struct resource omap2_pmu_resource = {
501 .start = 3, 502 .start = 3,
502 .end = 3, 503 .end = 3,
503 .flags = IORESOURCE_IRQ, 504 .flags = IORESOURCE_IRQ,
504 }; 505 };
505 506
506 static struct resource omap3_pmu_resource = { 507 static struct resource omap3_pmu_resource = {
507 .start = INT_34XX_BENCH_MPU_EMUL, 508 .start = INT_34XX_BENCH_MPU_EMUL,
508 .end = INT_34XX_BENCH_MPU_EMUL, 509 .end = INT_34XX_BENCH_MPU_EMUL,
509 .flags = IORESOURCE_IRQ, 510 .flags = IORESOURCE_IRQ,
510 }; 511 };
511 512
512 static struct platform_device omap_pmu_device = { 513 static struct platform_device omap_pmu_device = {
513 .name = "arm-pmu", 514 .name = "arm-pmu",
514 .id = ARM_PMU_DEVICE_CPU, 515 .id = ARM_PMU_DEVICE_CPU,
515 .num_resources = 1, 516 .num_resources = 1,
516 }; 517 };
517 518
518 static void omap_init_pmu(void) 519 static void omap_init_pmu(void)
519 { 520 {
520 if (cpu_is_omap24xx()) 521 if (cpu_is_omap24xx())
521 omap_pmu_device.resource = &omap2_pmu_resource; 522 omap_pmu_device.resource = &omap2_pmu_resource;
522 else if (cpu_is_omap34xx()) 523 else if (cpu_is_omap34xx())
523 omap_pmu_device.resource = &omap3_pmu_resource; 524 omap_pmu_device.resource = &omap3_pmu_resource;
524 else 525 else
525 return; 526 return;
526 527
527 platform_device_register(&omap_pmu_device); 528 platform_device_register(&omap_pmu_device);
528 } 529 }
529 530
530 531
531 #if defined(CONFIG_CRYPTO_DEV_OMAP_SHAM) || defined(CONFIG_CRYPTO_DEV_OMAP_SHAM_MODULE) 532 #if defined(CONFIG_CRYPTO_DEV_OMAP_SHAM) || defined(CONFIG_CRYPTO_DEV_OMAP_SHAM_MODULE)
532 533
533 #ifdef CONFIG_ARCH_OMAP2 534 #ifdef CONFIG_ARCH_OMAP2
534 static struct resource omap2_sham_resources[] = { 535 static struct resource omap2_sham_resources[] = {
535 { 536 {
536 .start = OMAP24XX_SEC_SHA1MD5_BASE, 537 .start = OMAP24XX_SEC_SHA1MD5_BASE,
537 .end = OMAP24XX_SEC_SHA1MD5_BASE + 0x64, 538 .end = OMAP24XX_SEC_SHA1MD5_BASE + 0x64,
538 .flags = IORESOURCE_MEM, 539 .flags = IORESOURCE_MEM,
539 }, 540 },
540 { 541 {
541 .start = INT_24XX_SHA1MD5, 542 .start = INT_24XX_SHA1MD5,
542 .flags = IORESOURCE_IRQ, 543 .flags = IORESOURCE_IRQ,
543 } 544 }
544 }; 545 };
545 static int omap2_sham_resources_sz = ARRAY_SIZE(omap2_sham_resources); 546 static int omap2_sham_resources_sz = ARRAY_SIZE(omap2_sham_resources);
546 #else 547 #else
547 #define omap2_sham_resources NULL 548 #define omap2_sham_resources NULL
548 #define omap2_sham_resources_sz 0 549 #define omap2_sham_resources_sz 0
549 #endif 550 #endif
550 551
551 #ifdef CONFIG_ARCH_OMAP3 552 #ifdef CONFIG_ARCH_OMAP3
552 static struct resource omap3_sham_resources[] = { 553 static struct resource omap3_sham_resources[] = {
553 { 554 {
554 .start = OMAP34XX_SEC_SHA1MD5_BASE, 555 .start = OMAP34XX_SEC_SHA1MD5_BASE,
555 .end = OMAP34XX_SEC_SHA1MD5_BASE + 0x64, 556 .end = OMAP34XX_SEC_SHA1MD5_BASE + 0x64,
556 .flags = IORESOURCE_MEM, 557 .flags = IORESOURCE_MEM,
557 }, 558 },
558 { 559 {
559 .start = INT_34XX_SHA1MD52_IRQ, 560 .start = INT_34XX_SHA1MD52_IRQ,
560 .flags = IORESOURCE_IRQ, 561 .flags = IORESOURCE_IRQ,
561 }, 562 },
562 { 563 {
563 .start = OMAP34XX_DMA_SHA1MD5_RX, 564 .start = OMAP34XX_DMA_SHA1MD5_RX,
564 .flags = IORESOURCE_DMA, 565 .flags = IORESOURCE_DMA,
565 } 566 }
566 }; 567 };
567 static int omap3_sham_resources_sz = ARRAY_SIZE(omap3_sham_resources); 568 static int omap3_sham_resources_sz = ARRAY_SIZE(omap3_sham_resources);
568 #else 569 #else
569 #define omap3_sham_resources NULL 570 #define omap3_sham_resources NULL
570 #define omap3_sham_resources_sz 0 571 #define omap3_sham_resources_sz 0
571 #endif 572 #endif
572 573
573 static struct platform_device sham_device = { 574 static struct platform_device sham_device = {
574 .name = "omap-sham", 575 .name = "omap-sham",
575 .id = -1, 576 .id = -1,
576 }; 577 };
577 578
578 static void omap_init_sham(void) 579 static void omap_init_sham(void)
579 { 580 {
580 if (cpu_is_omap24xx()) { 581 if (cpu_is_omap24xx()) {
581 sham_device.resource = omap2_sham_resources; 582 sham_device.resource = omap2_sham_resources;
582 sham_device.num_resources = omap2_sham_resources_sz; 583 sham_device.num_resources = omap2_sham_resources_sz;
583 } else if (cpu_is_omap34xx()) { 584 } else if (cpu_is_omap34xx()) {
584 sham_device.resource = omap3_sham_resources; 585 sham_device.resource = omap3_sham_resources;
585 sham_device.num_resources = omap3_sham_resources_sz; 586 sham_device.num_resources = omap3_sham_resources_sz;
586 } else { 587 } else {
587 pr_err("%s: platform not supported\n", __func__); 588 pr_err("%s: platform not supported\n", __func__);
588 return; 589 return;
589 } 590 }
590 platform_device_register(&sham_device); 591 platform_device_register(&sham_device);
591 } 592 }
592 #else 593 #else
593 static inline void omap_init_sham(void) { } 594 static inline void omap_init_sham(void) { }
594 #endif 595 #endif
595 596
596 #if defined(CONFIG_CRYPTO_DEV_OMAP_AES) || defined(CONFIG_CRYPTO_DEV_OMAP_AES_MODULE) 597 #if defined(CONFIG_CRYPTO_DEV_OMAP_AES) || defined(CONFIG_CRYPTO_DEV_OMAP_AES_MODULE)
597 598
598 #ifdef CONFIG_ARCH_OMAP2 599 #ifdef CONFIG_ARCH_OMAP2
599 static struct resource omap2_aes_resources[] = { 600 static struct resource omap2_aes_resources[] = {
600 { 601 {
601 .start = OMAP24XX_SEC_AES_BASE, 602 .start = OMAP24XX_SEC_AES_BASE,
602 .end = OMAP24XX_SEC_AES_BASE + 0x4C, 603 .end = OMAP24XX_SEC_AES_BASE + 0x4C,
603 .flags = IORESOURCE_MEM, 604 .flags = IORESOURCE_MEM,
604 }, 605 },
605 { 606 {
606 .start = OMAP24XX_DMA_AES_TX, 607 .start = OMAP24XX_DMA_AES_TX,
607 .flags = IORESOURCE_DMA, 608 .flags = IORESOURCE_DMA,
608 }, 609 },
609 { 610 {
610 .start = OMAP24XX_DMA_AES_RX, 611 .start = OMAP24XX_DMA_AES_RX,
611 .flags = IORESOURCE_DMA, 612 .flags = IORESOURCE_DMA,
612 } 613 }
613 }; 614 };
614 static int omap2_aes_resources_sz = ARRAY_SIZE(omap2_aes_resources); 615 static int omap2_aes_resources_sz = ARRAY_SIZE(omap2_aes_resources);
615 #else 616 #else
616 #define omap2_aes_resources NULL 617 #define omap2_aes_resources NULL
617 #define omap2_aes_resources_sz 0 618 #define omap2_aes_resources_sz 0
618 #endif 619 #endif
619 620
620 #ifdef CONFIG_ARCH_OMAP3 621 #ifdef CONFIG_ARCH_OMAP3
621 static struct resource omap3_aes_resources[] = { 622 static struct resource omap3_aes_resources[] = {
622 { 623 {
623 .start = OMAP34XX_SEC_AES_BASE, 624 .start = OMAP34XX_SEC_AES_BASE,
624 .end = OMAP34XX_SEC_AES_BASE + 0x4C, 625 .end = OMAP34XX_SEC_AES_BASE + 0x4C,
625 .flags = IORESOURCE_MEM, 626 .flags = IORESOURCE_MEM,
626 }, 627 },
627 { 628 {
628 .start = OMAP34XX_DMA_AES2_TX, 629 .start = OMAP34XX_DMA_AES2_TX,
629 .flags = IORESOURCE_DMA, 630 .flags = IORESOURCE_DMA,
630 }, 631 },
631 { 632 {
632 .start = OMAP34XX_DMA_AES2_RX, 633 .start = OMAP34XX_DMA_AES2_RX,
633 .flags = IORESOURCE_DMA, 634 .flags = IORESOURCE_DMA,
634 } 635 }
635 }; 636 };
636 static int omap3_aes_resources_sz = ARRAY_SIZE(omap3_aes_resources); 637 static int omap3_aes_resources_sz = ARRAY_SIZE(omap3_aes_resources);
637 #else 638 #else
638 #define omap3_aes_resources NULL 639 #define omap3_aes_resources NULL
639 #define omap3_aes_resources_sz 0 640 #define omap3_aes_resources_sz 0
640 #endif 641 #endif
641 642
642 static struct platform_device aes_device = { 643 static struct platform_device aes_device = {
643 .name = "omap-aes", 644 .name = "omap-aes",
644 .id = -1, 645 .id = -1,
645 }; 646 };
646 647
647 static void omap_init_aes(void) 648 static void omap_init_aes(void)
648 { 649 {
649 if (cpu_is_omap24xx()) { 650 if (cpu_is_omap24xx()) {
650 aes_device.resource = omap2_aes_resources; 651 aes_device.resource = omap2_aes_resources;
651 aes_device.num_resources = omap2_aes_resources_sz; 652 aes_device.num_resources = omap2_aes_resources_sz;
652 } else if (cpu_is_omap34xx()) { 653 } else if (cpu_is_omap34xx()) {
653 aes_device.resource = omap3_aes_resources; 654 aes_device.resource = omap3_aes_resources;
654 aes_device.num_resources = omap3_aes_resources_sz; 655 aes_device.num_resources = omap3_aes_resources_sz;
655 } else { 656 } else {
656 pr_err("%s: platform not supported\n", __func__); 657 pr_err("%s: platform not supported\n", __func__);
657 return; 658 return;
658 } 659 }
659 platform_device_register(&aes_device); 660 platform_device_register(&aes_device);
660 } 661 }
661 662
662 #else 663 #else
663 static inline void omap_init_aes(void) { } 664 static inline void omap_init_aes(void) { }
664 #endif 665 #endif
665 666
666 /*-------------------------------------------------------------------------*/ 667 /*-------------------------------------------------------------------------*/
667 668
668 #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) 669 #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
669 670
670 static inline void omap242x_mmc_mux(struct omap_mmc_platform_data 671 static inline void omap242x_mmc_mux(struct omap_mmc_platform_data
671 *mmc_controller) 672 *mmc_controller)
672 { 673 {
673 if ((mmc_controller->slots[0].switch_pin > 0) && \ 674 if ((mmc_controller->slots[0].switch_pin > 0) && \
674 (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES)) 675 (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
675 omap_mux_init_gpio(mmc_controller->slots[0].switch_pin, 676 omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
676 OMAP_PIN_INPUT_PULLUP); 677 OMAP_PIN_INPUT_PULLUP);
677 if ((mmc_controller->slots[0].gpio_wp > 0) && \ 678 if ((mmc_controller->slots[0].gpio_wp > 0) && \
678 (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES)) 679 (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
679 omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp, 680 omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
680 OMAP_PIN_INPUT_PULLUP); 681 OMAP_PIN_INPUT_PULLUP);
681 682
682 omap_mux_init_signal("sdmmc_cmd", 0); 683 omap_mux_init_signal("sdmmc_cmd", 0);
683 omap_mux_init_signal("sdmmc_clki", 0); 684 omap_mux_init_signal("sdmmc_clki", 0);
684 omap_mux_init_signal("sdmmc_clko", 0); 685 omap_mux_init_signal("sdmmc_clko", 0);
685 omap_mux_init_signal("sdmmc_dat0", 0); 686 omap_mux_init_signal("sdmmc_dat0", 0);
686 omap_mux_init_signal("sdmmc_dat_dir0", 0); 687 omap_mux_init_signal("sdmmc_dat_dir0", 0);
687 omap_mux_init_signal("sdmmc_cmd_dir", 0); 688 omap_mux_init_signal("sdmmc_cmd_dir", 0);
688 if (mmc_controller->slots[0].caps & MMC_CAP_4_BIT_DATA) { 689 if (mmc_controller->slots[0].caps & MMC_CAP_4_BIT_DATA) {
689 omap_mux_init_signal("sdmmc_dat1", 0); 690 omap_mux_init_signal("sdmmc_dat1", 0);
690 omap_mux_init_signal("sdmmc_dat2", 0); 691 omap_mux_init_signal("sdmmc_dat2", 0);
691 omap_mux_init_signal("sdmmc_dat3", 0); 692 omap_mux_init_signal("sdmmc_dat3", 0);
692 omap_mux_init_signal("sdmmc_dat_dir1", 0); 693 omap_mux_init_signal("sdmmc_dat_dir1", 0);
693 omap_mux_init_signal("sdmmc_dat_dir2", 0); 694 omap_mux_init_signal("sdmmc_dat_dir2", 0);
694 omap_mux_init_signal("sdmmc_dat_dir3", 0); 695 omap_mux_init_signal("sdmmc_dat_dir3", 0);
695 } 696 }
696 697
697 /* 698 /*
698 * Use internal loop-back in MMC/SDIO Module Input Clock 699 * Use internal loop-back in MMC/SDIO Module Input Clock
699 * selection 700 * selection
700 */ 701 */
701 if (mmc_controller->slots[0].internal_clock) { 702 if (mmc_controller->slots[0].internal_clock) {
702 u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); 703 u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
703 v |= (1 << 24); 704 v |= (1 << 24);
704 omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0); 705 omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
705 } 706 }
706 } 707 }
707 708
708 void __init omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data) 709 void __init omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data)
709 { 710 {
710 char *name = "mmci-omap"; 711 char *name = "mmci-omap";
711 712
712 if (!mmc_data[0]) { 713 if (!mmc_data[0]) {
713 pr_err("%s fails: Incomplete platform data\n", __func__); 714 pr_err("%s fails: Incomplete platform data\n", __func__);
714 return; 715 return;
715 } 716 }
716 717
717 omap242x_mmc_mux(mmc_data[0]); 718 omap242x_mmc_mux(mmc_data[0]);
718 omap_mmc_add(name, 0, OMAP2_MMC1_BASE, OMAP2420_MMC_SIZE, 719 omap_mmc_add(name, 0, OMAP2_MMC1_BASE, OMAP2420_MMC_SIZE,
719 INT_24XX_MMC_IRQ, mmc_data[0]); 720 INT_24XX_MMC_IRQ, mmc_data[0]);
720 } 721 }
721 722
722 #endif 723 #endif
723 724
724 /*-------------------------------------------------------------------------*/ 725 /*-------------------------------------------------------------------------*/
725 726
726 #if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE) 727 #if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE)
727 #if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430) 728 #if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430)
728 #define OMAP_HDQ_BASE 0x480B2000 729 #define OMAP_HDQ_BASE 0x480B2000
729 #endif 730 #endif
730 static struct resource omap_hdq_resources[] = { 731 static struct resource omap_hdq_resources[] = {
731 { 732 {
732 .start = OMAP_HDQ_BASE, 733 .start = OMAP_HDQ_BASE,
733 .end = OMAP_HDQ_BASE + 0x1C, 734 .end = OMAP_HDQ_BASE + 0x1C,
734 .flags = IORESOURCE_MEM, 735 .flags = IORESOURCE_MEM,
735 }, 736 },
736 { 737 {
737 .start = INT_24XX_HDQ_IRQ, 738 .start = INT_24XX_HDQ_IRQ,
738 .flags = IORESOURCE_IRQ, 739 .flags = IORESOURCE_IRQ,
739 }, 740 },
740 }; 741 };
741 static struct platform_device omap_hdq_dev = { 742 static struct platform_device omap_hdq_dev = {
742 .name = "omap_hdq", 743 .name = "omap_hdq",
743 .id = 0, 744 .id = 0,
744 .dev = { 745 .dev = {
745 .platform_data = NULL, 746 .platform_data = NULL,
746 }, 747 },
747 .num_resources = ARRAY_SIZE(omap_hdq_resources), 748 .num_resources = ARRAY_SIZE(omap_hdq_resources),
748 .resource = omap_hdq_resources, 749 .resource = omap_hdq_resources,
749 }; 750 };
750 static inline void omap_hdq_init(void) 751 static inline void omap_hdq_init(void)
751 { 752 {
752 (void) platform_device_register(&omap_hdq_dev); 753 (void) platform_device_register(&omap_hdq_dev);
753 } 754 }
754 #else 755 #else
755 static inline void omap_hdq_init(void) {} 756 static inline void omap_hdq_init(void) {}
756 #endif 757 #endif
757 758
758 /*---------------------------------------------------------------------------*/ 759 /*---------------------------------------------------------------------------*/
759 760
760 #if defined(CONFIG_VIDEO_OMAP2_VOUT) || \ 761 #if defined(CONFIG_VIDEO_OMAP2_VOUT) || \
761 defined(CONFIG_VIDEO_OMAP2_VOUT_MODULE) 762 defined(CONFIG_VIDEO_OMAP2_VOUT_MODULE)
762 #if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE) 763 #if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
763 static struct resource omap_vout_resource[3 - CONFIG_FB_OMAP2_NUM_FBS] = { 764 static struct resource omap_vout_resource[3 - CONFIG_FB_OMAP2_NUM_FBS] = {
764 }; 765 };
765 #else 766 #else
766 static struct resource omap_vout_resource[2] = { 767 static struct resource omap_vout_resource[2] = {
767 }; 768 };
768 #endif 769 #endif
769 770
770 static struct platform_device omap_vout_device = { 771 static struct platform_device omap_vout_device = {
771 .name = "omap_vout", 772 .name = "omap_vout",
772 .num_resources = ARRAY_SIZE(omap_vout_resource), 773 .num_resources = ARRAY_SIZE(omap_vout_resource),
773 .resource = &omap_vout_resource[0], 774 .resource = &omap_vout_resource[0],
774 .id = -1, 775 .id = -1,
775 }; 776 };
776 static void omap_init_vout(void) 777 static void omap_init_vout(void)
777 { 778 {
778 if (platform_device_register(&omap_vout_device) < 0) 779 if (platform_device_register(&omap_vout_device) < 0)
779 printk(KERN_ERR "Unable to register OMAP-VOUT device\n"); 780 printk(KERN_ERR "Unable to register OMAP-VOUT device\n");
780 } 781 }
781 #else 782 #else
782 static inline void omap_init_vout(void) {} 783 static inline void omap_init_vout(void) {}
783 #endif 784 #endif
784 785
785 #if defined(CONFIG_SOC_OMAPAM33XX) && defined(CONFIG_OMAP3_EDMA) 786 #if defined(CONFIG_SOC_OMAPAM33XX) && defined(CONFIG_OMAP3_EDMA)
786 787
787 #define AM33XX_TPCC_BASE 0x49000000 788 #define AM33XX_TPCC_BASE 0x49000000
788 #define AM33XX_TPTC0_BASE 0x49800000 789 #define AM33XX_TPTC0_BASE 0x49800000
789 #define AM33XX_TPTC1_BASE 0x49900000 790 #define AM33XX_TPTC1_BASE 0x49900000
790 #define AM33XX_TPTC2_BASE 0x49a00000 791 #define AM33XX_TPTC2_BASE 0x49a00000
791 792
792 #define AM33XX_SCM_BASE_EDMA 0x00000f90 793 #define AM33XX_SCM_BASE_EDMA 0x00000f90
793 794
794 static struct resource am33xx_edma_resources[] = { 795 static struct resource am33xx_edma_resources[] = {
795 { 796 {
796 .name = "edma_cc0", 797 .name = "edma_cc0",
797 .start = AM33XX_TPCC_BASE, 798 .start = AM33XX_TPCC_BASE,
798 .end = AM33XX_TPCC_BASE + SZ_32K - 1, 799 .end = AM33XX_TPCC_BASE + SZ_32K - 1,
799 .flags = IORESOURCE_MEM, 800 .flags = IORESOURCE_MEM,
800 }, 801 },
801 { 802 {
802 .name = "edma_tc0", 803 .name = "edma_tc0",
803 .start = AM33XX_TPTC0_BASE, 804 .start = AM33XX_TPTC0_BASE,
804 .end = AM33XX_TPTC0_BASE + SZ_1K - 1, 805 .end = AM33XX_TPTC0_BASE + SZ_1K - 1,
805 .flags = IORESOURCE_MEM, 806 .flags = IORESOURCE_MEM,
806 }, 807 },
807 { 808 {
808 .name = "edma_tc1", 809 .name = "edma_tc1",
809 .start = AM33XX_TPTC1_BASE, 810 .start = AM33XX_TPTC1_BASE,
810 .end = AM33XX_TPTC1_BASE + SZ_1K - 1, 811 .end = AM33XX_TPTC1_BASE + SZ_1K - 1,
811 .flags = IORESOURCE_MEM, 812 .flags = IORESOURCE_MEM,
812 }, 813 },
813 { 814 {
814 .name = "edma_tc2", 815 .name = "edma_tc2",
815 .start = AM33XX_TPTC2_BASE, 816 .start = AM33XX_TPTC2_BASE,
816 .end = AM33XX_TPTC2_BASE + SZ_1K - 1, 817 .end = AM33XX_TPTC2_BASE + SZ_1K - 1,
817 .flags = IORESOURCE_MEM, 818 .flags = IORESOURCE_MEM,
818 }, 819 },
819 { 820 {
820 .name = "edma0", 821 .name = "edma0",
821 .start = AM33XX_IRQ_TPCC0_INT_PO0, 822 .start = AM33XX_IRQ_TPCC0_INT_PO0,
822 .flags = IORESOURCE_IRQ, 823 .flags = IORESOURCE_IRQ,
823 }, 824 },
824 { 825 {
825 .name = "edma0_err", 826 .name = "edma0_err",
826 .start = AM33XX_IRQ_TPCC0_ERRINT_PO, 827 .start = AM33XX_IRQ_TPCC0_ERRINT_PO,
827 .flags = IORESOURCE_IRQ, 828 .flags = IORESOURCE_IRQ,
828 }, 829 },
829 }; 830 };
830 831
831 static const s16 am33xx_dma_rsv_chans[][2] = { 832 static const s16 am33xx_dma_rsv_chans[][2] = {
832 /* (offset, number) */ 833 /* (offset, number) */
833 {0, 2}, 834 {0, 2},
834 {14, 2}, 835 {14, 2},
835 {26, 6}, 836 {26, 6},
836 {48, 4}, 837 {48, 4},
837 {56, 8}, 838 {56, 8},
838 {-1, -1} 839 {-1, -1}
839 }; 840 };
840 841
841 static const s16 am33xx_dma_rsv_slots[][2] = { 842 static const s16 am33xx_dma_rsv_slots[][2] = {
842 /* (offset, number) */ 843 /* (offset, number) */
843 {0, 2}, 844 {0, 2},
844 {14, 2}, 845 {14, 2},
845 {26, 6}, 846 {26, 6},
846 {48, 4}, 847 {48, 4},
847 {56, 8}, 848 {56, 8},
848 {64, 127}, 849 {64, 127},
849 {-1, -1} 850 {-1, -1}
850 }; 851 };
851 852
852 /* Three Transfer Controllers on AM33XX */ 853 /* Three Transfer Controllers on AM33XX */
853 static const s8 am33xx_queue_tc_mapping[][2] = { 854 static const s8 am33xx_queue_tc_mapping[][2] = {
854 /* {event queue no, TC no} */ 855 /* {event queue no, TC no} */
855 {0, 0}, 856 {0, 0},
856 {1, 1}, 857 {1, 1},
857 {2, 2}, 858 {2, 2},
858 {-1, -1} 859 {-1, -1}
859 }; 860 };
860 861
861 static const s8 am33xx_queue_priority_mapping[][2] = { 862 static const s8 am33xx_queue_priority_mapping[][2] = {
862 /* {event queue no, Priority} */ 863 /* {event queue no, Priority} */
863 {0, 0}, 864 {0, 0},
864 {1, 1}, 865 {1, 1},
865 {2, 2}, 866 {2, 2},
866 {-1, -1} 867 {-1, -1}
867 }; 868 };
868 869
869 static struct event_to_channel_map am33xx_xbar_event_mapping[] = { 870 static struct event_to_channel_map am33xx_xbar_event_mapping[] = {
870 /* {xbar event no, Channel} */ 871 /* {xbar event no, Channel} */
871 {1, 12}, /* SDTXEVT1 -> MMCHS2 */ 872 {1, 12}, /* SDTXEVT1 -> MMCHS2 */
872 {2, 13}, /* SDRXEVT1 -> MMCHS2 */ 873 {2, 13}, /* SDRXEVT1 -> MMCHS2 */
873 {3, -1}, 874 {3, -1},
874 {4, -1}, 875 {4, -1},
875 {5, -1}, 876 {5, -1},
876 {6, -1}, 877 {6, -1},
877 {7, -1}, 878 {7, -1},
878 {8, -1}, 879 {8, -1},
879 {9, -1}, 880 {9, -1},
880 {10, -1}, 881 {10, -1},
881 {11, -1}, 882 {11, -1},
882 {12, -1}, 883 {12, -1},
883 {13, -1}, 884 {13, -1},
884 {14, -1}, 885 {14, -1},
885 {15, -1}, 886 {15, -1},
886 {16, -1}, 887 {16, -1},
887 {17, -1}, 888 {17, -1},
888 {18, -1}, 889 {18, -1},
889 {19, -1}, 890 {19, -1},
890 {20, -1}, 891 {20, -1},
891 {21, -1}, 892 {21, -1},
892 {22, -1}, 893 {22, -1},
893 {23, -1}, 894 {23, -1},
894 {24, -1}, 895 {24, -1},
895 {25, -1}, 896 {25, -1},
896 {26, -1}, 897 {26, -1},
897 {27, -1}, 898 {27, -1},
898 {28, -1}, 899 {28, -1},
899 {29, -1}, 900 {29, -1},
900 {30, -1}, 901 {30, -1},
901 {31, -1}, 902 {31, -1},
902 {-1, -1} 903 {-1, -1}
903 }; 904 };
904 905
905 /** 906 /**
906 * map_xbar_event_to_channel - maps a crossbar event to a DMA channel 907 * map_xbar_event_to_channel - maps a crossbar event to a DMA channel
907 * according to the configuration provided 908 * according to the configuration provided
908 * @event: the event number for which mapping is required 909 * @event: the event number for which mapping is required
909 * @channel: channel being activated 910 * @channel: channel being activated
910 * @xbar_event_mapping: array that has the event to channel map 911 * @xbar_event_mapping: array that has the event to channel map
911 * 912 *
912 * Events that are routed by default are not mapped. Only events that 913 * Events that are routed by default are not mapped. Only events that
913 * are crossbar mapped are routed to available channels according to 914 * are crossbar mapped are routed to available channels according to
914 * the configuration provided 915 * the configuration provided
915 * 916 *
916 * Returns zero on success, else negative errno. 917 * Returns zero on success, else negative errno.
917 */ 918 */
918 int map_xbar_event_to_channel(unsigned int event, unsigned int *channel, 919 int map_xbar_event_to_channel(unsigned int event, unsigned int *channel,
919 struct event_to_channel_map *xbar_event_mapping) 920 struct event_to_channel_map *xbar_event_mapping)
920 { 921 {
921 unsigned int ctrl = 0; 922 unsigned int ctrl = 0;
922 unsigned int xbar_evt_no = 0; 923 unsigned int xbar_evt_no = 0;
923 unsigned int val = 0; 924 unsigned int val = 0;
924 unsigned int offset = 0; 925 unsigned int offset = 0;
925 unsigned int mask = 0; 926 unsigned int mask = 0;
926 927
927 ctrl = EDMA_CTLR(event); 928 ctrl = EDMA_CTLR(event);
928 xbar_evt_no = event - (edma_info[ctrl]->num_channels); 929 xbar_evt_no = event - (edma_info[ctrl]->num_channels);
929 930
930 if (event < edma_info[ctrl]->num_channels) { 931 if (event < edma_info[ctrl]->num_channels) {
931 *channel = event; 932 *channel = event;
932 } else if (event < edma_info[ctrl]->num_events) { 933 } else if (event < edma_info[ctrl]->num_events) {
933 *channel = xbar_event_mapping[xbar_evt_no].channel_no; 934 *channel = xbar_event_mapping[xbar_evt_no].channel_no;
934 /* confirm the range */ 935 /* confirm the range */
935 if (*channel < EDMA_MAX_DMACH) 936 if (*channel < EDMA_MAX_DMACH)
936 clear_bit(*channel, edma_info[ctrl]->edma_unused); 937 clear_bit(*channel, edma_info[ctrl]->edma_unused);
937 mask = (*channel)%4; 938 mask = (*channel)%4;
938 offset = (*channel)/4; 939 offset = (*channel)/4;
939 offset *= 4; 940 offset *= 4;
940 offset += mask; 941 offset += mask;
941 val = (unsigned int)__raw_readl(AM33XX_CTRL_REGADDR( 942 val = (unsigned int)__raw_readl(AM33XX_CTRL_REGADDR(
942 AM33XX_SCM_BASE_EDMA + offset)); 943 AM33XX_SCM_BASE_EDMA + offset));
943 val = val & (~(0xFF)); 944 val = val & (~(0xFF));
944 val = val | (xbar_event_mapping[xbar_evt_no].xbar_event_no); 945 val = val | (xbar_event_mapping[xbar_evt_no].xbar_event_no);
945 __raw_writel(val, 946 __raw_writel(val,
946 AM33XX_CTRL_REGADDR(AM33XX_SCM_BASE_EDMA + offset)); 947 AM33XX_CTRL_REGADDR(AM33XX_SCM_BASE_EDMA + offset));
947 return 0; 948 return 0;
948 } else { 949 } else {
949 return -EINVAL; 950 return -EINVAL;
950 } 951 }
951 952
952 return 0; 953 return 0;
953 } 954 }
954 955
955 static struct edma_soc_info am33xx_edma_info[] = { 956 static struct edma_soc_info am33xx_edma_info[] = {
956 { 957 {
957 .n_channel = 64, 958 .n_channel = 64,
958 .n_region = 4, 959 .n_region = 4,
959 .n_slot = 256, 960 .n_slot = 256,
960 .n_tc = 3, 961 .n_tc = 3,
961 .n_cc = 1, 962 .n_cc = 1,
962 .rsv_chans = am33xx_dma_rsv_chans, 963 .rsv_chans = am33xx_dma_rsv_chans,
963 .rsv_slots = am33xx_dma_rsv_slots, 964 .rsv_slots = am33xx_dma_rsv_slots,
964 .queue_tc_mapping = am33xx_queue_tc_mapping, 965 .queue_tc_mapping = am33xx_queue_tc_mapping,
965 .queue_priority_mapping = am33xx_queue_priority_mapping, 966 .queue_priority_mapping = am33xx_queue_priority_mapping,
966 .is_xbar = 1, 967 .is_xbar = 1,
967 .n_events = 95, 968 .n_events = 95,
968 .xbar_event_mapping = am33xx_xbar_event_mapping, 969 .xbar_event_mapping = am33xx_xbar_event_mapping,
969 .map_xbar_channel = map_xbar_event_to_channel, 970 .map_xbar_channel = map_xbar_event_to_channel,
970 }, 971 },
971 }; 972 };
972 973
973 static struct platform_device am33xx_edma_device = { 974 static struct platform_device am33xx_edma_device = {
974 .name = "edma", 975 .name = "edma",
975 .id = -1, 976 .id = -1,
976 .dev = { 977 .dev = {
977 .platform_data = am33xx_edma_info, 978 .platform_data = am33xx_edma_info,
978 }, 979 },
979 .num_resources = ARRAY_SIZE(am33xx_edma_resources), 980 .num_resources = ARRAY_SIZE(am33xx_edma_resources),
980 .resource = am33xx_edma_resources, 981 .resource = am33xx_edma_resources,
981 }; 982 };
982 983
983 int __init am33xx_register_edma(void) 984 int __init am33xx_register_edma(void)
984 { 985 {
985 struct platform_device *pdev; 986 struct platform_device *pdev;
986 static struct clk *edma_clk; 987 static struct clk *edma_clk;
987 988
988 if (cpu_is_am33xx()) 989 if (cpu_is_am33xx())
989 pdev = &am33xx_edma_device; 990 pdev = &am33xx_edma_device;
990 else { 991 else {
991 pr_err("%s: platform not supported\n", __func__); 992 pr_err("%s: platform not supported\n", __func__);
992 return -ENODEV; 993 return -ENODEV;
993 } 994 }
994 995
995 edma_clk = clk_get(NULL, "tpcc_ick"); 996 edma_clk = clk_get(NULL, "tpcc_ick");
996 if (IS_ERR(edma_clk)) { 997 if (IS_ERR(edma_clk)) {
997 printk(KERN_ERR "EDMA: Failed to get clock\n"); 998 printk(KERN_ERR "EDMA: Failed to get clock\n");
998 return -EBUSY; 999 return -EBUSY;
999 } 1000 }
1000 clk_enable(edma_clk); 1001 clk_enable(edma_clk);
1001 edma_clk = clk_get(NULL, "tptc0_ick"); 1002 edma_clk = clk_get(NULL, "tptc0_ick");
1002 if (IS_ERR(edma_clk)) { 1003 if (IS_ERR(edma_clk)) {
1003 printk(KERN_ERR "EDMA: Failed to get clock\n"); 1004 printk(KERN_ERR "EDMA: Failed to get clock\n");
1004 return -EBUSY; 1005 return -EBUSY;
1005 } 1006 }
1006 clk_enable(edma_clk); 1007 clk_enable(edma_clk);
1007 edma_clk = clk_get(NULL, "tptc1_ick"); 1008 edma_clk = clk_get(NULL, "tptc1_ick");
1008 if (IS_ERR(edma_clk)) { 1009 if (IS_ERR(edma_clk)) {
1009 printk(KERN_ERR "EDMA: Failed to get clock\n"); 1010 printk(KERN_ERR "EDMA: Failed to get clock\n");
1010 return -EBUSY; 1011 return -EBUSY;
1011 } 1012 }
1012 clk_enable(edma_clk); 1013 clk_enable(edma_clk);
1013 edma_clk = clk_get(NULL, "tptc2_ick"); 1014 edma_clk = clk_get(NULL, "tptc2_ick");
1014 if (IS_ERR(edma_clk)) { 1015 if (IS_ERR(edma_clk)) {
1015 printk(KERN_ERR "EDMA: Failed to get clock\n"); 1016 printk(KERN_ERR "EDMA: Failed to get clock\n");
1016 return -EBUSY; 1017 return -EBUSY;
1017 } 1018 }
1018 clk_enable(edma_clk); 1019 clk_enable(edma_clk);
1019 1020
1020 return platform_device_register(pdev); 1021 return platform_device_register(pdev);
1021 } 1022 }
1022 1023
1023 #else 1024 #else
1024 static inline void am33xx_register_edma(void) {} 1025 static inline void am33xx_register_edma(void) {}
1025 #endif 1026 #endif
1026 1027
1027 #if defined (CONFIG_SOC_OMAPAM33XX) 1028 #if defined (CONFIG_SOC_OMAPAM33XX)
1028 struct uio_pruss_pdata am335x_pruss_uio_pdata = { 1029 struct uio_pruss_pdata am335x_pruss_uio_pdata = {
1029 .pintc_base = 0x20000, 1030 .pintc_base = 0x20000,
1030 }; 1031 };
1031 1032
1032 static struct resource am335x_pruss_resources[] = { 1033 static struct resource am335x_pruss_resources[] = {
1033 { 1034 {
1034 .start = AM33XX_ICSS_BASE, 1035 .start = AM33XX_ICSS_BASE,
1035 .end = AM33XX_ICSS_BASE + AM33XX_ICSS_LEN, 1036 .end = AM33XX_ICSS_BASE + AM33XX_ICSS_LEN,
1036 .flags = IORESOURCE_MEM, 1037 .flags = IORESOURCE_MEM,
1037 }, 1038 },
1038 { 1039 {
1039 .start = AM33XX_IRQ_ICSS0_0, 1040 .start = AM33XX_IRQ_ICSS0_0,
1040 .end = AM33XX_IRQ_ICSS0_0, 1041 .end = AM33XX_IRQ_ICSS0_0,
1041 .flags = IORESOURCE_IRQ, 1042 .flags = IORESOURCE_IRQ,
1042 }, 1043 },
1043 { 1044 {
1044 .start = AM33XX_IRQ_ICSS0_1, 1045 .start = AM33XX_IRQ_ICSS0_1,
1045 .end = AM33XX_IRQ_ICSS0_1, 1046 .end = AM33XX_IRQ_ICSS0_1,
1046 .flags = IORESOURCE_IRQ, 1047 .flags = IORESOURCE_IRQ,
1047 }, 1048 },
1048 { 1049 {
1049 .start = AM33XX_IRQ_ICSS0_2, 1050 .start = AM33XX_IRQ_ICSS0_2,
1050 .end = AM33XX_IRQ_ICSS0_2, 1051 .end = AM33XX_IRQ_ICSS0_2,
1051 .flags = IORESOURCE_IRQ, 1052 .flags = IORESOURCE_IRQ,
1052 }, 1053 },
1053 { 1054 {
1054 .start = AM33XX_IRQ_ICSS0_3, 1055 .start = AM33XX_IRQ_ICSS0_3,
1055 .end = AM33XX_IRQ_ICSS0_3, 1056 .end = AM33XX_IRQ_ICSS0_3,
1056 .flags = IORESOURCE_IRQ, 1057 .flags = IORESOURCE_IRQ,
1057 }, 1058 },
1058 { 1059 {
1059 .start = AM33XX_IRQ_ICSS0_4, 1060 .start = AM33XX_IRQ_ICSS0_4,
1060 .end = AM33XX_IRQ_ICSS0_4, 1061 .end = AM33XX_IRQ_ICSS0_4,
1061 .flags = IORESOURCE_IRQ, 1062 .flags = IORESOURCE_IRQ,
1062 }, 1063 },
1063 { 1064 {
1064 .start = AM33XX_IRQ_ICSS0_5, 1065 .start = AM33XX_IRQ_ICSS0_5,
1065 .end = AM33XX_IRQ_ICSS0_5, 1066 .end = AM33XX_IRQ_ICSS0_5,
1066 .flags = IORESOURCE_IRQ, 1067 .flags = IORESOURCE_IRQ,
1067 }, 1068 },
1068 { 1069 {
1069 .start = AM33XX_IRQ_ICSS0_6, 1070 .start = AM33XX_IRQ_ICSS0_6,
1070 .end = AM33XX_IRQ_ICSS0_6, 1071 .end = AM33XX_IRQ_ICSS0_6,
1071 .flags = IORESOURCE_IRQ, 1072 .flags = IORESOURCE_IRQ,
1072 }, 1073 },
1073 { 1074 {
1074 .start = AM33XX_IRQ_ICSS0_7, 1075 .start = AM33XX_IRQ_ICSS0_7,
1075 .end = AM33XX_IRQ_ICSS0_7, 1076 .end = AM33XX_IRQ_ICSS0_7,
1076 .flags = IORESOURCE_IRQ, 1077 .flags = IORESOURCE_IRQ,
1077 }, 1078 },
1078 }; 1079 };
1079 1080
1080 static struct platform_device am335x_pruss_uio_dev = { 1081 static struct platform_device am335x_pruss_uio_dev = {
1081 .name = "pruss_uio", 1082 .name = "pruss_uio",
1082 .id = -1, 1083 .id = -1,
1083 .num_resources = ARRAY_SIZE(am335x_pruss_resources), 1084 .num_resources = ARRAY_SIZE(am335x_pruss_resources),
1084 .resource = am335x_pruss_resources, 1085 .resource = am335x_pruss_resources,
1085 .dev = { 1086 .dev = {
1086 .coherent_dma_mask = 0xffffffff, 1087 .coherent_dma_mask = 0xffffffff,
1087 } 1088 }
1088 }; 1089 };
1089 1090
1090 int __init am335x_register_pruss_uio(struct uio_pruss_pdata *config) 1091 int __init am335x_register_pruss_uio(struct uio_pruss_pdata *config)
1091 { 1092 {
1092 am335x_pruss_uio_dev.dev.platform_data = config; 1093 am335x_pruss_uio_dev.dev.platform_data = config;
1093 return platform_device_register(&am335x_pruss_uio_dev); 1094 return platform_device_register(&am335x_pruss_uio_dev);
1094 } 1095 }
1095 #endif 1096 #endif
1096 1097
1097 /*-------------------------------------------------------------------------*/ 1098 /*-------------------------------------------------------------------------*/
1098 1099
1099 static int __init omap2_init_devices(void) 1100 static int __init omap2_init_devices(void)
1100 { 1101 {
1101 /* 1102 /*
1102 * please keep these calls, and their implementations above, 1103 * please keep these calls, and their implementations above,
1103 * in alphabetical order so they're easier to sort through. 1104 * in alphabetical order so they're easier to sort through.
1104 */ 1105 */
1105 omap_init_audio(); 1106 omap_init_audio();
1106 omap_init_camera(); 1107 omap_init_camera();
1107 omap_init_mbox(); 1108 omap_init_mbox();
1108 omap_init_mcspi(); 1109 omap_init_mcspi();
1109 omap_init_elm(); 1110 omap_init_elm();
1110 omap_init_pmu(); 1111 omap_init_pmu();
1111 omap_hdq_init(); 1112 omap_hdq_init();
1112 omap_init_sti(); 1113 omap_init_sti();
1113 omap_init_sham(); 1114 omap_init_sham();
1114 omap_init_aes(); 1115 omap_init_aes();
1115 omap_init_vout(); 1116 omap_init_vout();
1116 am33xx_register_edma(); 1117 am33xx_register_edma();
1117 am33xx_init_pcm(); 1118 am33xx_init_pcm();
1118 #if defined (CONFIG_SOC_OMAPAM33XX) 1119 #if defined (CONFIG_SOC_OMAPAM33XX)
1119 am335x_register_pruss_uio(&am335x_pruss_uio_pdata); 1120 am335x_register_pruss_uio(&am335x_pruss_uio_pdata);
1120 #endif 1121 #endif
1121 return 0; 1122 return 0;
1122 } 1123 }
1123 arch_initcall(omap2_init_devices); 1124 arch_initcall(omap2_init_devices);
1124 1125
1125 #define AM33XX_EMAC_MDIO_FREQ (1000000) 1126 #define AM33XX_EMAC_MDIO_FREQ (1000000)
1126 1127
1127 static u64 am33xx_cpsw_dmamask = DMA_BIT_MASK(32); 1128 static u64 am33xx_cpsw_dmamask = DMA_BIT_MASK(32);
1128 /* TODO : Verify the offsets */ 1129 /* TODO : Verify the offsets */
1129 static struct cpsw_slave_data am33xx_cpsw_slaves[] = { 1130 static struct cpsw_slave_data am33xx_cpsw_slaves[] = {
1130 { 1131 {
1131 .slave_reg_ofs = 0x208, 1132 .slave_reg_ofs = 0x208,
1132 .sliver_reg_ofs = 0xd80, 1133 .sliver_reg_ofs = 0xd80,
1133 .phy_id = "0:00", 1134 .phy_id = "0:00",
1134 }, 1135 },
1135 { 1136 {
1136 .slave_reg_ofs = 0x308, 1137 .slave_reg_ofs = 0x308,
1137 .sliver_reg_ofs = 0xdc0, 1138 .sliver_reg_ofs = 0xdc0,
1138 .phy_id = "0:01", 1139 .phy_id = "0:01",
1139 }, 1140 },
1140 }; 1141 };
1141 1142
1142 static struct cpsw_platform_data am33xx_cpsw_pdata = { 1143 static struct cpsw_platform_data am33xx_cpsw_pdata = {
1143 .ss_reg_ofs = 0x1200, 1144 .ss_reg_ofs = 0x1200,
1144 .channels = 8, 1145 .channels = 8,
1145 .cpdma_reg_ofs = 0x800, 1146 .cpdma_reg_ofs = 0x800,
1146 .slaves = 2, 1147 .slaves = 2,
1147 .slave_data = am33xx_cpsw_slaves, 1148 .slave_data = am33xx_cpsw_slaves,
1148 .ale_reg_ofs = 0xd00, 1149 .ale_reg_ofs = 0xd00,
1149 .ale_entries = 1024, 1150 .ale_entries = 1024,
1150 .host_port_reg_ofs = 0x108, 1151 .host_port_reg_ofs = 0x108,
1151 .hw_stats_reg_ofs = 0x900, 1152 .hw_stats_reg_ofs = 0x900,
1152 .bd_ram_ofs = 0x2000, 1153 .bd_ram_ofs = 0x2000,
1153 .bd_ram_size = SZ_8K, 1154 .bd_ram_size = SZ_8K,
1154 .rx_descs = 64, 1155 .rx_descs = 64,
1155 .mac_control = BIT(5), /* MIIEN */ 1156 .mac_control = BIT(5), /* MIIEN */
1156 .gigabit_en = 1, 1157 .gigabit_en = 1,
1157 .host_port_num = 0, 1158 .host_port_num = 0,
1158 .no_bd_ram = false, 1159 .no_bd_ram = false,
1159 .version = CPSW_VERSION_2, 1160 .version = CPSW_VERSION_2,
1160 }; 1161 };
1161 1162
1162 static struct mdio_platform_data am33xx_cpsw_mdiopdata = { 1163 static struct mdio_platform_data am33xx_cpsw_mdiopdata = {
1163 .bus_freq = AM33XX_EMAC_MDIO_FREQ, 1164 .bus_freq = AM33XX_EMAC_MDIO_FREQ,
1164 }; 1165 };
1165 1166
1166 static struct resource am33xx_cpsw_mdioresources[] = { 1167 static struct resource am33xx_cpsw_mdioresources[] = {
1167 { 1168 {
1168 .start = AM33XX_CPSW_MDIO_BASE, 1169 .start = AM33XX_CPSW_MDIO_BASE,
1169 .end = AM33XX_CPSW_MDIO_BASE + SZ_256 - 1, 1170 .end = AM33XX_CPSW_MDIO_BASE + SZ_256 - 1,
1170 .flags = IORESOURCE_MEM, 1171 .flags = IORESOURCE_MEM,
1171 }, 1172 },
1172 }; 1173 };
1173 1174
1174 static struct platform_device am33xx_cpsw_mdiodevice = { 1175 static struct platform_device am33xx_cpsw_mdiodevice = {
1175 .name = "davinci_mdio", 1176 .name = "davinci_mdio",
1176 .id = 0, 1177 .id = 0,
1177 .num_resources = ARRAY_SIZE(am33xx_cpsw_mdioresources), 1178 .num_resources = ARRAY_SIZE(am33xx_cpsw_mdioresources),
1178 .resource = am33xx_cpsw_mdioresources, 1179 .resource = am33xx_cpsw_mdioresources,
1179 .dev.platform_data = &am33xx_cpsw_mdiopdata, 1180 .dev.platform_data = &am33xx_cpsw_mdiopdata,
1180 }; 1181 };
1181 1182
1182 static struct resource am33xx_cpsw_resources[] = { 1183 static struct resource am33xx_cpsw_resources[] = {
1183 { 1184 {
1184 .start = AM33XX_CPSW_BASE, 1185 .start = AM33XX_CPSW_BASE,
1185 .end = AM33XX_CPSW_BASE + SZ_2K - 1, 1186 .end = AM33XX_CPSW_BASE + SZ_2K - 1,
1186 .flags = IORESOURCE_MEM, 1187 .flags = IORESOURCE_MEM,
1187 }, 1188 },
1188 { 1189 {
1189 .start = AM33XX_CPSW_SS_BASE, 1190 .start = AM33XX_CPSW_SS_BASE,
1190 .end = AM33XX_CPSW_SS_BASE + SZ_256 - 1, 1191 .end = AM33XX_CPSW_SS_BASE + SZ_256 - 1,
1191 .flags = IORESOURCE_MEM, 1192 .flags = IORESOURCE_MEM,
1192 }, 1193 },
1193 { 1194 {
1194 .start = AM33XX_IRQ_CPSW_C0_RX, 1195 .start = AM33XX_IRQ_CPSW_C0_RX,
1195 .end = AM33XX_IRQ_CPSW_C0_RX, 1196 .end = AM33XX_IRQ_CPSW_C0_RX,
1196 .flags = IORESOURCE_IRQ, 1197 .flags = IORESOURCE_IRQ,
1197 }, 1198 },
1198 { 1199 {
1199 .start = AM33XX_IRQ_DMTIMER5, 1200 .start = AM33XX_IRQ_DMTIMER5,
1200 .end = AM33XX_IRQ_DMTIMER5, 1201 .end = AM33XX_IRQ_DMTIMER5,
1201 .flags = IORESOURCE_IRQ, 1202 .flags = IORESOURCE_IRQ,
1202 }, 1203 },
1203 { 1204 {
1204 .start = AM33XX_IRQ_DMTIMER6, 1205 .start = AM33XX_IRQ_DMTIMER6,
1205 .end = AM33XX_IRQ_DMTIMER6, 1206 .end = AM33XX_IRQ_DMTIMER6,
1206 .flags = IORESOURCE_IRQ, 1207 .flags = IORESOURCE_IRQ,
1207 }, 1208 },
1208 { 1209 {
1209 .start = AM33XX_IRQ_CPSW_C0, 1210 .start = AM33XX_IRQ_CPSW_C0,
1210 .end = AM33XX_IRQ_CPSW_C0, 1211 .end = AM33XX_IRQ_CPSW_C0,
1211 .flags = IORESOURCE_IRQ, 1212 .flags = IORESOURCE_IRQ,
1212 }, 1213 },
1213 }; 1214 };
1214 1215
1215 static struct platform_device am33xx_cpsw_device = { 1216 static struct platform_device am33xx_cpsw_device = {
1216 .name = "cpsw", 1217 .name = "cpsw",
1217 .id = 0, 1218 .id = 0,
1218 .num_resources = ARRAY_SIZE(am33xx_cpsw_resources), 1219 .num_resources = ARRAY_SIZE(am33xx_cpsw_resources),
1219 .resource = am33xx_cpsw_resources, 1220 .resource = am33xx_cpsw_resources,
1220 .dev = { 1221 .dev = {
1221 .platform_data = &am33xx_cpsw_pdata, 1222 .platform_data = &am33xx_cpsw_pdata,
1222 .dma_mask = &am33xx_cpsw_dmamask, 1223 .dma_mask = &am33xx_cpsw_dmamask,
1223 .coherent_dma_mask = DMA_BIT_MASK(32), 1224 .coherent_dma_mask = DMA_BIT_MASK(32),
1224 }, 1225 },
1225 }; 1226 };
1226 1227
1227 static unsigned char am33xx_macid0[ETH_ALEN]; 1228 static unsigned char am33xx_macid0[ETH_ALEN];
1228 static unsigned char am33xx_macid1[ETH_ALEN]; 1229 static unsigned char am33xx_macid1[ETH_ALEN];
1229 static unsigned int am33xx_evmid; 1230 static unsigned int am33xx_evmid;
1230 1231
1231 /* 1232 /*
1232 * am33xx_evmid_fillup - set up board evmid 1233 * am33xx_evmid_fillup - set up board evmid
1233 * @evmid - evm id which needs to be configured 1234 * @evmid - evm id which needs to be configured
1234 * 1235 *
1235 * This function is called to configure board evm id. 1236 * This function is called to configure board evm id.
1236 * IA Motor Control EVM needs special setting of MAC PHY Id. 1237 * IA Motor Control EVM needs special setting of MAC PHY Id.
1237 * This function is called when IA Motor Control EVM is detected 1238 * This function is called when IA Motor Control EVM is detected
1238 * during boot-up. 1239 * during boot-up.
1239 */ 1240 */
1240 void am33xx_evmid_fillup(unsigned int evmid) 1241 void am33xx_evmid_fillup(unsigned int evmid)
1241 { 1242 {
1242 am33xx_evmid = evmid; 1243 am33xx_evmid = evmid;
1243 return; 1244 return;
1244 } 1245 }
1245 1246
1246 /* 1247 /*
1247 * am33xx_cpsw_macidfillup - setup mac adrresses 1248 * am33xx_cpsw_macidfillup - setup mac adrresses
1248 * @eeprommacid0 - mac id 0 which needs to be configured 1249 * @eeprommacid0 - mac id 0 which needs to be configured
1249 * @eeprommacid1 - mac id 1 which needs to be configured 1250 * @eeprommacid1 - mac id 1 which needs to be configured
1250 * 1251 *
1251 * This function is called to configure mac addresses. 1252 * This function is called to configure mac addresses.
1252 * Mac addresses are read from eeprom and this function is called 1253 * Mac addresses are read from eeprom and this function is called
1253 * to store those mac adresses in am33xx_macid0 and am33xx_macid1. 1254 * to store those mac adresses in am33xx_macid0 and am33xx_macid1.
1254 * In case, mac address read from eFuse are invalid, mac addresses 1255 * In case, mac address read from eFuse are invalid, mac addresses
1255 * stored in these variable are used. 1256 * stored in these variable are used.
1256 */ 1257 */
1257 void am33xx_cpsw_macidfillup(char *eeprommacid0, char *eeprommacid1) 1258 void am33xx_cpsw_macidfillup(char *eeprommacid0, char *eeprommacid1)
1258 { 1259 {
1259 u32 i; 1260 u32 i;
1260 1261
1261 /* Fillup these mac addresses with the mac adresses from eeprom */ 1262 /* Fillup these mac addresses with the mac adresses from eeprom */
1262 for (i = 0; i < ETH_ALEN; i++) { 1263 for (i = 0; i < ETH_ALEN; i++) {
1263 am33xx_macid0[i] = eeprommacid0[i]; 1264 am33xx_macid0[i] = eeprommacid0[i];
1264 am33xx_macid1[i] = eeprommacid1[i]; 1265 am33xx_macid1[i] = eeprommacid1[i];
1265 } 1266 }
1266 1267
1267 return; 1268 return;
1268 } 1269 }
1269 1270
1270 void am33xx_cpsw_init(unsigned int gigen) 1271 void am33xx_cpsw_init(unsigned int gigen)
1271 { 1272 {
1272 u32 mac_lo, mac_hi; 1273 u32 mac_lo, mac_hi;
1273 u32 i; 1274 u32 i;
1274 1275
1275 mac_lo = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID0_LO); 1276 mac_lo = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID0_LO);
1276 mac_hi = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID0_HI); 1277 mac_hi = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID0_HI);
1277 am33xx_cpsw_slaves[0].mac_addr[0] = mac_hi & 0xFF; 1278 am33xx_cpsw_slaves[0].mac_addr[0] = mac_hi & 0xFF;
1278 am33xx_cpsw_slaves[0].mac_addr[1] = (mac_hi & 0xFF00) >> 8; 1279 am33xx_cpsw_slaves[0].mac_addr[1] = (mac_hi & 0xFF00) >> 8;
1279 am33xx_cpsw_slaves[0].mac_addr[2] = (mac_hi & 0xFF0000) >> 16; 1280 am33xx_cpsw_slaves[0].mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
1280 am33xx_cpsw_slaves[0].mac_addr[3] = (mac_hi & 0xFF000000) >> 24; 1281 am33xx_cpsw_slaves[0].mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
1281 am33xx_cpsw_slaves[0].mac_addr[4] = mac_lo & 0xFF; 1282 am33xx_cpsw_slaves[0].mac_addr[4] = mac_lo & 0xFF;
1282 am33xx_cpsw_slaves[0].mac_addr[5] = (mac_lo & 0xFF00) >> 8; 1283 am33xx_cpsw_slaves[0].mac_addr[5] = (mac_lo & 0xFF00) >> 8;
1283 1284
1284 /* Read MACID0 from eeprom if eFuse MACID is invalid */ 1285 /* Read MACID0 from eeprom if eFuse MACID is invalid */
1285 if (!is_valid_ether_addr(am33xx_cpsw_slaves[0].mac_addr)) { 1286 if (!is_valid_ether_addr(am33xx_cpsw_slaves[0].mac_addr)) {
1286 for (i = 0; i < ETH_ALEN; i++) 1287 for (i = 0; i < ETH_ALEN; i++)
1287 am33xx_cpsw_slaves[0].mac_addr[i] = am33xx_macid0[i]; 1288 am33xx_cpsw_slaves[0].mac_addr[i] = am33xx_macid0[i];
1288 } 1289 }
1289 1290
1290 mac_lo = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID1_LO); 1291 mac_lo = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID1_LO);
1291 mac_hi = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID1_HI); 1292 mac_hi = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID1_HI);
1292 am33xx_cpsw_slaves[1].mac_addr[0] = mac_hi & 0xFF; 1293 am33xx_cpsw_slaves[1].mac_addr[0] = mac_hi & 0xFF;
1293 am33xx_cpsw_slaves[1].mac_addr[1] = (mac_hi & 0xFF00) >> 8; 1294 am33xx_cpsw_slaves[1].mac_addr[1] = (mac_hi & 0xFF00) >> 8;
1294 am33xx_cpsw_slaves[1].mac_addr[2] = (mac_hi & 0xFF0000) >> 16; 1295 am33xx_cpsw_slaves[1].mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
1295 am33xx_cpsw_slaves[1].mac_addr[3] = (mac_hi & 0xFF000000) >> 24; 1296 am33xx_cpsw_slaves[1].mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
1296 am33xx_cpsw_slaves[1].mac_addr[4] = mac_lo & 0xFF; 1297 am33xx_cpsw_slaves[1].mac_addr[4] = mac_lo & 0xFF;
1297 am33xx_cpsw_slaves[1].mac_addr[5] = (mac_lo & 0xFF00) >> 8; 1298 am33xx_cpsw_slaves[1].mac_addr[5] = (mac_lo & 0xFF00) >> 8;
1298 1299
1299 /* Read MACID1 from eeprom if eFuse MACID is invalid */ 1300 /* Read MACID1 from eeprom if eFuse MACID is invalid */
1300 if (!is_valid_ether_addr(am33xx_cpsw_slaves[1].mac_addr)) { 1301 if (!is_valid_ether_addr(am33xx_cpsw_slaves[1].mac_addr)) {
1301 for (i = 0; i < ETH_ALEN; i++) 1302 for (i = 0; i < ETH_ALEN; i++)
1302 am33xx_cpsw_slaves[1].mac_addr[i] = am33xx_macid1[i]; 1303 am33xx_cpsw_slaves[1].mac_addr[i] = am33xx_macid1[i];
1303 } 1304 }
1304 1305
1305 if (am33xx_evmid == IND_AUT_MTR_EVM) { 1306 if (am33xx_evmid == IND_AUT_MTR_EVM) {
1306 am33xx_cpsw_slaves[0].phy_id = "0:1e"; 1307 am33xx_cpsw_slaves[0].phy_id = "0:1e";
1307 am33xx_cpsw_slaves[1].phy_id = "0:00"; 1308 am33xx_cpsw_slaves[1].phy_id = "0:00";
1308 } 1309 }
1309 1310
1310 am33xx_cpsw_pdata.gigabit_en = gigen; 1311 am33xx_cpsw_pdata.gigabit_en = gigen;
1311 1312
1312 memcpy(am33xx_cpsw_pdata.mac_addr, 1313 memcpy(am33xx_cpsw_pdata.mac_addr,
1313 am33xx_cpsw_slaves[0].mac_addr, ETH_ALEN); 1314 am33xx_cpsw_slaves[0].mac_addr, ETH_ALEN);
1314 platform_device_register(&am33xx_cpsw_mdiodevice); 1315 platform_device_register(&am33xx_cpsw_mdiodevice);
1315 platform_device_register(&am33xx_cpsw_device); 1316 platform_device_register(&am33xx_cpsw_device);
1316 clk_add_alias(NULL, dev_name(&am33xx_cpsw_mdiodevice.dev), 1317 clk_add_alias(NULL, dev_name(&am33xx_cpsw_mdiodevice.dev),
1317 NULL, &am33xx_cpsw_device.dev); 1318 NULL, &am33xx_cpsw_device.dev);
1318 } 1319 }
1319 1320
1320 #define AM33XX_D_CAN_RAM_BASE 0x1000 1321 #define AM33XX_D_CAN_RAM_BASE 0x1000
1321 #define AM33XX_D_CAN_NUM_MSG_OBJS 64 1322 #define AM33XX_D_CAN_NUM_MSG_OBJS 64
1322 #define AM33XX_D_CAN_VERSION 0x1 1323 #define AM33XX_D_CAN_VERSION 0x1
1323 #define AM33XX_CTL_DCAN_RAMINIT_OFFSET 0x644 1324 #define AM33XX_CTL_DCAN_RAMINIT_OFFSET 0x644
1324 #define AM33XX_D_CAN_RAMINIT_START(n) (0x1 << n) 1325 #define AM33XX_D_CAN_RAMINIT_START(n) (0x1 << n)
1325 1326
1326 static void d_can_hw_raminit(unsigned int instance) 1327 static void d_can_hw_raminit(unsigned int instance)
1327 { 1328 {
1328 u32 val; 1329 u32 val;
1329 1330
1330 /* Read the value */ 1331 /* Read the value */
1331 val = __raw_readl(AM33XX_CTRL_REGADDR(AM33XX_CTL_DCAN_RAMINIT_OFFSET)); 1332 val = __raw_readl(AM33XX_CTRL_REGADDR(AM33XX_CTL_DCAN_RAMINIT_OFFSET));
1332 1333
1333 /* Modify by setting "0" */ 1334 /* Modify by setting "0" */
1334 val &= ~AM33XX_D_CAN_RAMINIT_START(instance); 1335 val &= ~AM33XX_D_CAN_RAMINIT_START(instance);
1335 __raw_writel(val, AM33XX_CTRL_REGADDR(AM33XX_CTL_DCAN_RAMINIT_OFFSET)); 1336 __raw_writel(val, AM33XX_CTRL_REGADDR(AM33XX_CTL_DCAN_RAMINIT_OFFSET));
1336 1337
1337 /* Reset to one */ 1338 /* Reset to one */
1338 val |= AM33XX_D_CAN_RAMINIT_START(instance); 1339 val |= AM33XX_D_CAN_RAMINIT_START(instance);
1339 __raw_writel(val, AM33XX_CTRL_REGADDR(AM33XX_CTL_DCAN_RAMINIT_OFFSET)); 1340 __raw_writel(val, AM33XX_CTRL_REGADDR(AM33XX_CTL_DCAN_RAMINIT_OFFSET));
1340 1341
1341 /* Give some time delay for transition from 0 -> 1 */ 1342 /* Give some time delay for transition from 0 -> 1 */
1342 udelay(1); 1343 udelay(1);
1343 } 1344 }
1344 1345
1345 static struct d_can_platform_data am33xx_evm_d_can0_pdata = { 1346 static struct d_can_platform_data am33xx_evm_d_can0_pdata = {
1346 .d_can_offset = 0, 1347 .d_can_offset = 0,
1347 .d_can_ram_offset = AM33XX_D_CAN_RAM_BASE, 1348 .d_can_ram_offset = AM33XX_D_CAN_RAM_BASE,
1348 .num_of_msg_objs = AM33XX_D_CAN_NUM_MSG_OBJS, 1349 .num_of_msg_objs = AM33XX_D_CAN_NUM_MSG_OBJS,
1349 .dma_support = false, 1350 .dma_support = false,
1350 .test_mode_enable = false, 1351 .test_mode_enable = false,
1351 .parity_check = false, 1352 .parity_check = false,
1352 .fck_name = "dcan0_fck", 1353 .fck_name = "dcan0_fck",
1353 .ick_name = "dcan0_ick", 1354 .ick_name = "dcan0_ick",
1354 .version = AM33XX_D_CAN_VERSION, 1355 .version = AM33XX_D_CAN_VERSION,
1355 }; 1356 };
1356 1357
1357 static struct resource am33xx_d_can0_resources[] = { 1358 static struct resource am33xx_d_can0_resources[] = {
1358 { 1359 {
1359 .start = AM33XX_D_CAN0_BASE, 1360 .start = AM33XX_D_CAN0_BASE,
1360 .end = AM33XX_D_CAN0_BASE + 0x3FFF, 1361 .end = AM33XX_D_CAN0_BASE + 0x3FFF,
1361 .flags = IORESOURCE_MEM, 1362 .flags = IORESOURCE_MEM,
1362 }, 1363 },
1363 { 1364 {
1364 .name = "int0", 1365 .name = "int0",
1365 .start = AM33XX_IRQ_DCAN0_0, 1366 .start = AM33XX_IRQ_DCAN0_0,
1366 .end = AM33XX_IRQ_DCAN0_0, 1367 .end = AM33XX_IRQ_DCAN0_0,
1367 .flags = IORESOURCE_IRQ, 1368 .flags = IORESOURCE_IRQ,
1368 }, 1369 },
1369 { 1370 {
1370 .name = "int1", 1371 .name = "int1",
1371 .start = AM33XX_IRQ_DCAN0_1, 1372 .start = AM33XX_IRQ_DCAN0_1,
1372 .end = AM33XX_IRQ_DCAN0_1, 1373 .end = AM33XX_IRQ_DCAN0_1,
1373 .flags = IORESOURCE_IRQ, 1374 .flags = IORESOURCE_IRQ,
1374 }, 1375 },
1375 }; 1376 };
1376 1377
1377 static struct platform_device am33xx_d_can0_device = { 1378 static struct platform_device am33xx_d_can0_device = {
1378 .dev = { 1379 .dev = {
1379 .platform_data = &am33xx_evm_d_can0_pdata, 1380 .platform_data = &am33xx_evm_d_can0_pdata,
1380 }, 1381 },
1381 .name = "d_can", 1382 .name = "d_can",
1382 .id = -1, 1383 .id = -1,
1383 .num_resources = ARRAY_SIZE(am33xx_d_can0_resources), 1384 .num_resources = ARRAY_SIZE(am33xx_d_can0_resources),
1384 .resource = am33xx_d_can0_resources, 1385 .resource = am33xx_d_can0_resources,
1385 }; 1386 };
1386 1387
1387 static struct resource am33xx_d_can1_resources[] = { 1388 static struct resource am33xx_d_can1_resources[] = {
1388 { 1389 {
1389 .start = AM33XX_D_CAN1_BASE, 1390 .start = AM33XX_D_CAN1_BASE,
1390 .end = AM33XX_D_CAN1_BASE + 0x3FFF, 1391 .end = AM33XX_D_CAN1_BASE + 0x3FFF,
1391 .flags = IORESOURCE_MEM, 1392 .flags = IORESOURCE_MEM,
1392 }, 1393 },
1393 { 1394 {
1394 .name = "int0", 1395 .name = "int0",
1395 .start = AM33XX_IRQ_DCAN1_0, 1396 .start = AM33XX_IRQ_DCAN1_0,
1396 .end = AM33XX_IRQ_DCAN1_0, 1397 .end = AM33XX_IRQ_DCAN1_0,
1397 .flags = IORESOURCE_IRQ, 1398 .flags = IORESOURCE_IRQ,
1398 }, 1399 },
1399 { 1400 {
1400 .name = "int1", 1401 .name = "int1",
1401 .start = AM33XX_IRQ_DCAN1_1, 1402 .start = AM33XX_IRQ_DCAN1_1,
1402 .end = AM33XX_IRQ_DCAN1_1, 1403 .end = AM33XX_IRQ_DCAN1_1,
1403 .flags = IORESOURCE_IRQ, 1404 .flags = IORESOURCE_IRQ,
1404 }, 1405 },
1405 }; 1406 };
1406 1407
1407 static struct d_can_platform_data am33xx_evm_d_can1_pdata = { 1408 static struct d_can_platform_data am33xx_evm_d_can1_pdata = {
1408 .d_can_offset = 0, 1409 .d_can_offset = 0,
1409 .d_can_ram_offset = AM33XX_D_CAN_RAM_BASE, 1410 .d_can_ram_offset = AM33XX_D_CAN_RAM_BASE,
1410 .num_of_msg_objs = AM33XX_D_CAN_NUM_MSG_OBJS, 1411 .num_of_msg_objs = AM33XX_D_CAN_NUM_MSG_OBJS,
1411 .dma_support = false, 1412 .dma_support = false,
1412 .test_mode_enable = false, 1413 .test_mode_enable = false,
1413 .parity_check = false, 1414 .parity_check = false,
1414 .fck_name = "dcan1_fck", 1415 .fck_name = "dcan1_fck",
1415 .ick_name = "dcan1_ick", 1416 .ick_name = "dcan1_ick",
1416 .version = AM33XX_D_CAN_VERSION, 1417 .version = AM33XX_D_CAN_VERSION,
1417 }; 1418 };
1418 1419
1419 static struct platform_device am33xx_d_can1_device = { 1420 static struct platform_device am33xx_d_can1_device = {
1420 .dev = { 1421 .dev = {
1421 .platform_data = &am33xx_evm_d_can1_pdata, 1422 .platform_data = &am33xx_evm_d_can1_pdata,
1422 }, 1423 },
1423 .name = "d_can", 1424 .name = "d_can",
1424 .id = -1, 1425 .id = -1,
1425 .num_resources = ARRAY_SIZE(am33xx_d_can1_resources), 1426 .num_resources = ARRAY_SIZE(am33xx_d_can1_resources),
1426 .resource = am33xx_d_can1_resources, 1427 .resource = am33xx_d_can1_resources,
1427 }; 1428 };
1428 1429
1429 void am33xx_d_can_init(unsigned int instance) 1430 void am33xx_d_can_init(unsigned int instance)
1430 { 1431 {
1431 switch (instance) { 1432 switch (instance) {
1432 case 0: 1433 case 0:
1433 d_can_hw_raminit(instance); 1434 d_can_hw_raminit(instance);
1434 platform_device_register(&am33xx_d_can0_device); 1435 platform_device_register(&am33xx_d_can0_device);
1435 break; 1436 break;
1436 case 1: 1437 case 1:
1437 d_can_hw_raminit(instance); 1438 d_can_hw_raminit(instance);
1438 platform_device_register(&am33xx_d_can1_device); 1439 platform_device_register(&am33xx_d_can1_device);
1439 break; 1440 break;
1440 default: 1441 default:
1441 break; 1442 break;
1442 } 1443 }
1443 } 1444 }
1444 1445
1445 #if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE) 1446 #if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE)
1446 static int __init omap_init_wdt(void) 1447 static int __init omap_init_wdt(void)
1447 { 1448 {
1448 int id = -1; 1449 int id = -1;
1449 struct platform_device *pdev; 1450 struct platform_device *pdev;
1450 struct omap_hwmod *oh; 1451 struct omap_hwmod *oh;
1451 char *oh_name = "wd_timer2"; 1452 char *oh_name = "wd_timer2";
1452 char *dev_name = "omap_wdt"; 1453 char *dev_name = "omap_wdt";
1453 1454
1454 if (!cpu_class_is_omap2()) 1455 if (!cpu_class_is_omap2())
1455 return 0; 1456 return 0;
1456 1457
1457 oh = omap_hwmod_lookup(oh_name); 1458 oh = omap_hwmod_lookup(oh_name);
1458 if (!oh) { 1459 if (!oh) {
1459 pr_err("Could not look up wd_timer%d hwmod\n", id); 1460 pr_err("Could not look up wd_timer%d hwmod\n", id);
1460 return -EINVAL; 1461 return -EINVAL;
1461 } 1462 }
1462 1463
1463 pdev = omap_device_build(dev_name, id, oh, NULL, 0, NULL, 0, 0); 1464 pdev = omap_device_build(dev_name, id, oh, NULL, 0, NULL, 0, 0);
1464 WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s.\n", 1465 WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s.\n",
1465 dev_name, oh->name); 1466 dev_name, oh->name);
1466 return 0; 1467 return 0;
1467 } 1468 }
1468 subsys_initcall(omap_init_wdt); 1469 subsys_initcall(omap_init_wdt);
1469 #endif 1470 #endif
1470 1471
arch/arm/plat-omap/sram.c
Diff comments   View file @ 3feb24e
1 /* 1 /*
2 * linux/arch/arm/plat-omap/sram.c 2 * linux/arch/arm/plat-omap/sram.c
3 * 3 *
4 * OMAP SRAM detection and management 4 * OMAP SRAM detection and management
5 * 5 *
6 * Copyright (C) 2005 Nokia Corporation 6 * Copyright (C) 2005 Nokia Corporation
7 * Written by Tony Lindgren <tony@atomide.com> 7 * Written by Tony Lindgren <tony@atomide.com>
8 * 8 *
9 * Copyright (C) 2009 Texas Instruments 9 * Copyright (C) 2009 Texas Instruments
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> 10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
11 * 11 *
12 * This program is free software; you can redistribute it and/or modify 12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as 13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation. 14 * published by the Free Software Foundation.
15 */ 15 */
16 #undef DEBUG 16 #undef DEBUG
17 17
18 #include <linux/module.h> 18 #include <linux/module.h>
19 #include <linux/kernel.h> 19 #include <linux/kernel.h>
20 #include <linux/init.h> 20 #include <linux/init.h>
21 #include <linux/io.h> 21 #include <linux/io.h>
22 22
23 #include <asm/tlb.h> 23 #include <asm/tlb.h>
24 #include <asm/cacheflush.h> 24 #include <asm/cacheflush.h>
25 25
26 #include <asm/mach/map.h> 26 #include <asm/mach/map.h>
27 27
28 #include <plat/sram.h> 28 #include <plat/sram.h>
29 #include <plat/board.h> 29 #include <plat/board.h>
30 #include <plat/cpu.h> 30 #include <plat/cpu.h>
31 31
32 #include "sram.h" 32 #include "sram.h"
33 33
34 /* XXX These "sideways" includes are a sign that something is wrong */ 34 /* XXX These "sideways" includes are a sign that something is wrong */
35 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) 35 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
36 # include "../mach-omap2/prm2xxx_3xxx.h" 36 # include "../mach-omap2/prm2xxx_3xxx.h"
37 # include "../mach-omap2/sdrc.h" 37 # include "../mach-omap2/sdrc.h"
38 #endif 38 #endif
39 39
40 #define OMAP1_SRAM_PA 0x20000000 40 #define OMAP1_SRAM_PA 0x20000000
41 #define OMAP2_SRAM_PUB_PA (OMAP2_SRAM_PA + 0xf800) 41 #define OMAP2_SRAM_PUB_PA (OMAP2_SRAM_PA + 0xf800)
42 #define OMAP3_SRAM_PUB_PA (OMAP3_SRAM_PA + 0x8000) 42 #define OMAP3_SRAM_PUB_PA (OMAP3_SRAM_PA + 0x8000)
43 #define OMAP4_SRAM_PUB_PA (OMAP4_SRAM_PA + 0x4000) 43 #define OMAP4_SRAM_PUB_PA (OMAP4_SRAM_PA + 0x4000)
44 44
45 #if defined(CONFIG_ARCH_OMAP2PLUS) 45 #if defined(CONFIG_ARCH_OMAP2PLUS)
46 #define SRAM_BOOTLOADER_SZ 0x00 46 #define SRAM_BOOTLOADER_SZ 0x00
47 #else 47 #else
48 #define SRAM_BOOTLOADER_SZ 0x80 48 #define SRAM_BOOTLOADER_SZ 0x80
49 #endif 49 #endif
50 50
51 #define OMAP24XX_VA_REQINFOPERM0 OMAP2_L3_IO_ADDRESS(0x68005048) 51 #define OMAP24XX_VA_REQINFOPERM0 OMAP2_L3_IO_ADDRESS(0x68005048)
52 #define OMAP24XX_VA_READPERM0 OMAP2_L3_IO_ADDRESS(0x68005050) 52 #define OMAP24XX_VA_READPERM0 OMAP2_L3_IO_ADDRESS(0x68005050)
53 #define OMAP24XX_VA_WRITEPERM0 OMAP2_L3_IO_ADDRESS(0x68005058) 53 #define OMAP24XX_VA_WRITEPERM0 OMAP2_L3_IO_ADDRESS(0x68005058)
54 54
55 #define OMAP34XX_VA_REQINFOPERM0 OMAP2_L3_IO_ADDRESS(0x68012848) 55 #define OMAP34XX_VA_REQINFOPERM0 OMAP2_L3_IO_ADDRESS(0x68012848)
56 #define OMAP34XX_VA_READPERM0 OMAP2_L3_IO_ADDRESS(0x68012850) 56 #define OMAP34XX_VA_READPERM0 OMAP2_L3_IO_ADDRESS(0x68012850)
57 #define OMAP34XX_VA_WRITEPERM0 OMAP2_L3_IO_ADDRESS(0x68012858) 57 #define OMAP34XX_VA_WRITEPERM0 OMAP2_L3_IO_ADDRESS(0x68012858)
58 #define OMAP34XX_VA_ADDR_MATCH2 OMAP2_L3_IO_ADDRESS(0x68012880) 58 #define OMAP34XX_VA_ADDR_MATCH2 OMAP2_L3_IO_ADDRESS(0x68012880)
59 #define OMAP34XX_VA_SMS_RG_ATT0 OMAP2_L3_IO_ADDRESS(0x6C000048) 59 #define OMAP34XX_VA_SMS_RG_ATT0 OMAP2_L3_IO_ADDRESS(0x6C000048)
60 60
61 #define GP_DEVICE 0x300 61 #define GP_DEVICE 0x300
62 62
63 #define ROUND_DOWN(value,boundary) ((value) & (~((boundary)-1))) 63 #define ROUND_DOWN(value,boundary) ((value) & (~((boundary)-1)))
64 64
65 static unsigned long omap_sram_start; 65 static unsigned long omap_sram_start;
66 static void __iomem *omap_sram_base; 66 static void __iomem *omap_sram_base;
67 static unsigned long omap_sram_size; 67 static unsigned long omap_sram_size;
68 68
69 /* 69 /*
70 * Depending on the target RAMFS firewall setup, the public usable amount of 70 * Depending on the target RAMFS firewall setup, the public usable amount of
71 * SRAM varies. The default accessible size for all device types is 2k. A GP 71 * SRAM varies. The default accessible size for all device types is 2k. A GP
72 * device allows ARM11 but not other initiators for full size. This 72 * device allows ARM11 but not other initiators for full size. This
73 * functionality seems ok until some nice security API happens. 73 * functionality seems ok until some nice security API happens.
74 */ 74 */
75 static int is_sram_locked(void) 75 static int is_sram_locked(void)
76 { 76 {
77 if (OMAP2_DEVICE_TYPE_GP == omap_type()) { 77 if (OMAP2_DEVICE_TYPE_GP == omap_type()) {
78 /* RAMFW: R/W access to all initiators for all qualifier sets */ 78 /* RAMFW: R/W access to all initiators for all qualifier sets */
79 if (cpu_is_omap242x()) { 79 if (cpu_is_omap242x()) {
80 __raw_writel(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */ 80 __raw_writel(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
81 __raw_writel(0xCFDE, OMAP24XX_VA_READPERM0); /* all i-read */ 81 __raw_writel(0xCFDE, OMAP24XX_VA_READPERM0); /* all i-read */
82 __raw_writel(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */ 82 __raw_writel(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
83 } 83 }
84 if (cpu_is_omap34xx()) { 84 if (cpu_is_omap34xx()) {
85 __raw_writel(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */ 85 __raw_writel(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
86 __raw_writel(0xFFFF, OMAP34XX_VA_READPERM0); /* all i-read */ 86 __raw_writel(0xFFFF, OMAP34XX_VA_READPERM0); /* all i-read */
87 __raw_writel(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */ 87 __raw_writel(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
88 __raw_writel(0x0, OMAP34XX_VA_ADDR_MATCH2); 88 __raw_writel(0x0, OMAP34XX_VA_ADDR_MATCH2);
89 __raw_writel(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0); 89 __raw_writel(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0);
90 } 90 }
91 return 0; 91 return 0;
92 } else 92 } else
93 return 1; /* assume locked with no PPA or security driver */ 93 return 1; /* assume locked with no PPA or security driver */
94 } 94 }
95 95
96 struct gen_pool *omap_gen_pool; 96 struct gen_pool *omap_gen_pool;
97 EXPORT_SYMBOL_GPL(omap_gen_pool);
97 98
98 /* 99 /*
99 * The amount of SRAM depends on the core type. 100 * The amount of SRAM depends on the core type.
100 * Note that we cannot try to test for SRAM here because writes 101 * Note that we cannot try to test for SRAM here because writes
101 * to secure SRAM will hang the system. Also the SRAM is not 102 * to secure SRAM will hang the system. Also the SRAM is not
102 * yet mapped at this point. 103 * yet mapped at this point.
103 */ 104 */
104 static void __init omap_detect_sram(void) 105 static void __init omap_detect_sram(void)
105 { 106 {
106 if (cpu_class_is_omap2()) { 107 if (cpu_class_is_omap2()) {
107 if (is_sram_locked()) { 108 if (is_sram_locked()) {
108 if (cpu_is_omap34xx()) { 109 if (cpu_is_omap34xx()) {
109 omap_sram_start = OMAP3_SRAM_PUB_PA; 110 omap_sram_start = OMAP3_SRAM_PUB_PA;
110 if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) || 111 if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) ||
111 (omap_type() == OMAP2_DEVICE_TYPE_SEC)) { 112 (omap_type() == OMAP2_DEVICE_TYPE_SEC)) {
112 omap_sram_size = 0x7000; /* 28K */ 113 omap_sram_size = 0x7000; /* 28K */
113 } else { 114 } else {
114 omap_sram_size = 0x8000; /* 32K */ 115 omap_sram_size = 0x8000; /* 32K */
115 } 116 }
116 } else if (cpu_is_omap44xx()) { 117 } else if (cpu_is_omap44xx()) {
117 omap_sram_start = OMAP4_SRAM_PUB_PA; 118 omap_sram_start = OMAP4_SRAM_PUB_PA;
118 omap_sram_size = 0xa000; /* 40K */ 119 omap_sram_size = 0xa000; /* 40K */
119 } else { 120 } else {
120 omap_sram_start = OMAP2_SRAM_PUB_PA; 121 omap_sram_start = OMAP2_SRAM_PUB_PA;
121 omap_sram_size = 0x800; /* 2K */ 122 omap_sram_size = 0x800; /* 2K */
122 } 123 }
123 } else { 124 } else {
124 if (cpu_is_omap34xx()) { 125 if (cpu_is_omap34xx()) {
125 omap_sram_start = OMAP3_SRAM_PA; 126 omap_sram_start = OMAP3_SRAM_PA;
126 omap_sram_size = 0x10000; /* 64K */ 127 omap_sram_size = 0x10000; /* 64K */
127 } else if (cpu_is_omap44xx()) { 128 } else if (cpu_is_omap44xx()) {
128 omap_sram_start = OMAP4_SRAM_PA; 129 omap_sram_start = OMAP4_SRAM_PA;
129 omap_sram_size = 0xe000; /* 56K */ 130 omap_sram_size = 0xe000; /* 56K */
130 } else { 131 } else {
131 omap_sram_start = OMAP2_SRAM_PA; 132 omap_sram_start = OMAP2_SRAM_PA;
132 if (cpu_is_omap242x()) 133 if (cpu_is_omap242x())
133 omap_sram_size = 0xa0000; /* 640K */ 134 omap_sram_size = 0xa0000; /* 640K */
134 else if (cpu_is_omap243x()) 135 else if (cpu_is_omap243x())
135 omap_sram_size = 0x10000; /* 64K */ 136 omap_sram_size = 0x10000; /* 64K */
136 } 137 }
137 } 138 }
138 } else { 139 } else {
139 omap_sram_start = OMAP1_SRAM_PA; 140 omap_sram_start = OMAP1_SRAM_PA;
140 141
141 if (cpu_is_omap7xx()) 142 if (cpu_is_omap7xx())
142 omap_sram_size = 0x32000; /* 200K */ 143 omap_sram_size = 0x32000; /* 200K */
143 else if (cpu_is_omap15xx()) 144 else if (cpu_is_omap15xx())
144 omap_sram_size = 0x30000; /* 192K */ 145 omap_sram_size = 0x30000; /* 192K */
145 else if (cpu_is_omap1610() || cpu_is_omap1621() || 146 else if (cpu_is_omap1610() || cpu_is_omap1621() ||
146 cpu_is_omap1710()) 147 cpu_is_omap1710())
147 omap_sram_size = 0x4000; /* 16K */ 148 omap_sram_size = 0x4000; /* 16K */
148 else if (cpu_is_omap1611()) 149 else if (cpu_is_omap1611())
149 omap_sram_size = SZ_256K; 150 omap_sram_size = SZ_256K;
150 else { 151 else {
151 pr_err("Could not detect SRAM size\n"); 152 pr_err("Could not detect SRAM size\n");
152 omap_sram_size = 0x4000; 153 omap_sram_size = 0x4000;
153 } 154 }
154 } 155 }
155 { 156 {
156 /* The first SRAM_BOOTLOADER_SZ of SRAM are reserved */ 157 /* The first SRAM_BOOTLOADER_SZ of SRAM are reserved */
157 void *base = (void *)omap_sram_base + SRAM_BOOTLOADER_SZ; 158 void *base = (void *)omap_sram_base + SRAM_BOOTLOADER_SZ;
158 phys_addr_t phys = omap_sram_start + SRAM_BOOTLOADER_SZ; 159 phys_addr_t phys = omap_sram_start + SRAM_BOOTLOADER_SZ;
159 size_t len = omap_sram_size - SRAM_BOOTLOADER_SZ; 160 size_t len = omap_sram_size - SRAM_BOOTLOADER_SZ;
160 161
161 omap_gen_pool = gen_pool_create(ilog2(FNCPY_ALIGN), -1); 162 omap_gen_pool = gen_pool_create(ilog2(FNCPY_ALIGN), -1);
162 if (omap_gen_pool) 163 if (omap_gen_pool)
163 WARN_ON(gen_pool_add_virt(omap_gen_pool, 164 WARN_ON(gen_pool_add_virt(omap_gen_pool,
164 (unsigned long)base, phys, len, -1)); 165 (unsigned long)base, phys, len, -1));
165 WARN_ON(!omap_gen_pool); 166 WARN_ON(!omap_gen_pool);
166 } 167 }
167 } 168 }
168 169
169 /* 170 /*
170 * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early. 171 * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early.
171 */ 172 */
172 static void __init omap_map_sram(void) 173 static void __init omap_map_sram(void)
173 { 174 {
174 int cached = 1; 175 int cached = 1;
175 176
176 if (omap_sram_size == 0) 177 if (omap_sram_size == 0)
177 return; 178 return;
178 179
179 if (cpu_is_omap34xx()) { 180 if (cpu_is_omap34xx()) {
180 /* 181 /*
181 * SRAM must be marked as non-cached on OMAP3 since the 182 * SRAM must be marked as non-cached on OMAP3 since the
182 * CORE DPLL M2 divider change code (in SRAM) runs with the 183 * CORE DPLL M2 divider change code (in SRAM) runs with the
183 * SDRAM controller disabled, and if it is marked cached, 184 * SDRAM controller disabled, and if it is marked cached,
184 * the ARM may attempt to write cache lines back to SDRAM 185 * the ARM may attempt to write cache lines back to SDRAM
185 * which will cause the system to hang. 186 * which will cause the system to hang.
186 */ 187 */
187 cached = 0; 188 cached = 0;
188 } 189 }
189 190
190 omap_sram_start = ROUND_DOWN(omap_sram_start, PAGE_SIZE); 191 omap_sram_start = ROUND_DOWN(omap_sram_start, PAGE_SIZE);
191 omap_sram_base = __arm_ioremap_exec(omap_sram_start, omap_sram_size, 192 omap_sram_base = __arm_ioremap_exec(omap_sram_start, omap_sram_size,
192 cached); 193 cached);
193 if (!omap_sram_base) { 194 if (!omap_sram_base) {
194 pr_err("SRAM: Could not map\n"); 195 pr_err("SRAM: Could not map\n");
195 return; 196 return;
196 } 197 }
197 198
198 /* 199 /*
199 * Looks like we need to preserve some bootloader code at the 200 * Looks like we need to preserve some bootloader code at the
200 * beginning of SRAM for jumping to flash for reboot to work... 201 * beginning of SRAM for jumping to flash for reboot to work...
201 */ 202 */
202 memset((void *)omap_sram_base + SRAM_BOOTLOADER_SZ, 0, 203 memset((void *)omap_sram_base + SRAM_BOOTLOADER_SZ, 0,
203 omap_sram_size - SRAM_BOOTLOADER_SZ); 204 omap_sram_size - SRAM_BOOTLOADER_SZ);
204 } 205 }
205 206
206 #ifdef CONFIG_ARCH_OMAP1 207 #ifdef CONFIG_ARCH_OMAP1
207 208
208 static void (*_omap_sram_reprogram_clock)(u32 dpllctl, u32 ckctl); 209 static void (*_omap_sram_reprogram_clock)(u32 dpllctl, u32 ckctl);
209 210
210 void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl) 211 void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl)
211 { 212 {
212 BUG_ON(!_omap_sram_reprogram_clock); 213 BUG_ON(!_omap_sram_reprogram_clock);
213 _omap_sram_reprogram_clock(dpllctl, ckctl); 214 _omap_sram_reprogram_clock(dpllctl, ckctl);
214 } 215 }
215 216
216 static int __init omap1_sram_init(void) 217 static int __init omap1_sram_init(void)
217 { 218 {
218 _omap_sram_reprogram_clock = 219 _omap_sram_reprogram_clock =
219 omap_sram_push(omap1_sram_reprogram_clock, 220 omap_sram_push(omap1_sram_reprogram_clock,
220 omap1_sram_reprogram_clock_sz); 221 omap1_sram_reprogram_clock_sz);
221 222
222 return 0; 223 return 0;
223 } 224 }
224 225
225 #else 226 #else
226 #define omap1_sram_init() do {} while (0) 227 #define omap1_sram_init() do {} while (0)
227 #endif 228 #endif
228 229
229 #if defined(CONFIG_ARCH_OMAP2) 230 #if defined(CONFIG_ARCH_OMAP2)
230 231
231 static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl, 232 static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
232 u32 base_cs, u32 force_unlock); 233 u32 base_cs, u32 force_unlock);
233 234
234 void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl, 235 void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
235 u32 base_cs, u32 force_unlock) 236 u32 base_cs, u32 force_unlock)
236 { 237 {
237 BUG_ON(!_omap2_sram_ddr_init); 238 BUG_ON(!_omap2_sram_ddr_init);
238 _omap2_sram_ddr_init(slow_dll_ctrl, fast_dll_ctrl, 239 _omap2_sram_ddr_init(slow_dll_ctrl, fast_dll_ctrl,
239 base_cs, force_unlock); 240 base_cs, force_unlock);
240 } 241 }
241 242
242 static void (*_omap2_sram_reprogram_sdrc)(u32 perf_level, u32 dll_val, 243 static void (*_omap2_sram_reprogram_sdrc)(u32 perf_level, u32 dll_val,
243 u32 mem_type); 244 u32 mem_type);
244 245
245 void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type) 246 void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type)
246 { 247 {
247 BUG_ON(!_omap2_sram_reprogram_sdrc); 248 BUG_ON(!_omap2_sram_reprogram_sdrc);
248 _omap2_sram_reprogram_sdrc(perf_level, dll_val, mem_type); 249 _omap2_sram_reprogram_sdrc(perf_level, dll_val, mem_type);
249 } 250 }
250 251
251 static u32 (*_omap2_set_prcm)(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass); 252 static u32 (*_omap2_set_prcm)(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
252 253
253 u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass) 254 u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass)
254 { 255 {
255 BUG_ON(!_omap2_set_prcm); 256 BUG_ON(!_omap2_set_prcm);
256 return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass); 257 return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass);
257 } 258 }
258 #endif 259 #endif
259 260
260 #ifdef CONFIG_SOC_OMAP2420 261 #ifdef CONFIG_SOC_OMAP2420
261 static int __init omap242x_sram_init(void) 262 static int __init omap242x_sram_init(void)
262 { 263 {
263 _omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init, 264 _omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init,
264 omap242x_sram_ddr_init_sz); 265 omap242x_sram_ddr_init_sz);
265 266
266 _omap2_sram_reprogram_sdrc = omap_sram_push(omap242x_sram_reprogram_sdrc, 267 _omap2_sram_reprogram_sdrc = omap_sram_push(omap242x_sram_reprogram_sdrc,
267 omap242x_sram_reprogram_sdrc_sz); 268 omap242x_sram_reprogram_sdrc_sz);
268 269
269 _omap2_set_prcm = omap_sram_push(omap242x_sram_set_prcm, 270 _omap2_set_prcm = omap_sram_push(omap242x_sram_set_prcm,
270 omap242x_sram_set_prcm_sz); 271 omap242x_sram_set_prcm_sz);
271 272
272 return 0; 273 return 0;
273 } 274 }
274 #else 275 #else
275 static inline int omap242x_sram_init(void) 276 static inline int omap242x_sram_init(void)
276 { 277 {
277 return 0; 278 return 0;
278 } 279 }
279 #endif 280 #endif
280 281
281 #ifdef CONFIG_SOC_OMAP2430 282 #ifdef CONFIG_SOC_OMAP2430
282 static int __init omap243x_sram_init(void) 283 static int __init omap243x_sram_init(void)
283 { 284 {
284 _omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init, 285 _omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init,
285 omap243x_sram_ddr_init_sz); 286 omap243x_sram_ddr_init_sz);
286 287
287 _omap2_sram_reprogram_sdrc = omap_sram_push(omap243x_sram_reprogram_sdrc, 288 _omap2_sram_reprogram_sdrc = omap_sram_push(omap243x_sram_reprogram_sdrc,
288 omap243x_sram_reprogram_sdrc_sz); 289 omap243x_sram_reprogram_sdrc_sz);
289 290
290 _omap2_set_prcm = omap_sram_push(omap243x_sram_set_prcm, 291 _omap2_set_prcm = omap_sram_push(omap243x_sram_set_prcm,
291 omap243x_sram_set_prcm_sz); 292 omap243x_sram_set_prcm_sz);
292 293
293 return 0; 294 return 0;
294 } 295 }
295 #else 296 #else
296 static inline int omap243x_sram_init(void) 297 static inline int omap243x_sram_init(void)
297 { 298 {
298 return 0; 299 return 0;
299 } 300 }
300 #endif 301 #endif
301 302
302 #ifdef CONFIG_ARCH_OMAP3 303 #ifdef CONFIG_ARCH_OMAP3
303 304
304 static u32 (*_omap3_sram_configure_core_dpll)( 305 static u32 (*_omap3_sram_configure_core_dpll)(
305 u32 m2, u32 unlock_dll, u32 f, u32 inc, 306 u32 m2, u32 unlock_dll, u32 f, u32 inc,
306 u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0, 307 u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
307 u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0, 308 u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
308 u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1, 309 u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
309 u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1); 310 u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
310 311
311 u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc, 312 u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc,
312 u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0, 313 u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
313 u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0, 314 u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
314 u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1, 315 u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
315 u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1) 316 u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1)
316 { 317 {
317 BUG_ON(!_omap3_sram_configure_core_dpll); 318 BUG_ON(!_omap3_sram_configure_core_dpll);
318 return _omap3_sram_configure_core_dpll( 319 return _omap3_sram_configure_core_dpll(
319 m2, unlock_dll, f, inc, 320 m2, unlock_dll, f, inc,
320 sdrc_rfr_ctrl_0, sdrc_actim_ctrl_a_0, 321 sdrc_rfr_ctrl_0, sdrc_actim_ctrl_a_0,
321 sdrc_actim_ctrl_b_0, sdrc_mr_0, 322 sdrc_actim_ctrl_b_0, sdrc_mr_0,
322 sdrc_rfr_ctrl_1, sdrc_actim_ctrl_a_1, 323 sdrc_rfr_ctrl_1, sdrc_actim_ctrl_a_1,
323 sdrc_actim_ctrl_b_1, sdrc_mr_1); 324 sdrc_actim_ctrl_b_1, sdrc_mr_1);
324 } 325 }
325 326
326 #ifdef CONFIG_PM 327 #ifdef CONFIG_PM
327 void omap3_sram_restore_context(void) 328 void omap3_sram_restore_context(void)
328 { 329 {
329 _omap3_sram_configure_core_dpll = 330 _omap3_sram_configure_core_dpll =
330 omap_sram_push(omap3_sram_configure_core_dpll, 331 omap_sram_push(omap3_sram_configure_core_dpll,
331 omap3_sram_configure_core_dpll_sz); 332 omap3_sram_configure_core_dpll_sz);
332 omap_push_sram_idle(); 333 omap_push_sram_idle();
333 } 334 }
334 #endif /* CONFIG_PM */ 335 #endif /* CONFIG_PM */
335 336
336 #endif /* CONFIG_ARCH_OMAP3 */ 337 #endif /* CONFIG_ARCH_OMAP3 */
337 338
338 static inline int omap34xx_sram_init(void) 339 static inline int omap34xx_sram_init(void)
339 { 340 {
340 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) 341 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
341 omap3_sram_restore_context(); 342 omap3_sram_restore_context();
342 #endif 343 #endif
343 return 0; 344 return 0;
344 } 345 }
345 346
346 int __init omap_sram_init(void) 347 int __init omap_sram_init(void)
347 { 348 {
348 if (cpu_is_am33xx()) 349 if (cpu_is_am33xx())
349 return 0; 350 return 0;
350 351
351 omap_detect_sram(); 352 omap_detect_sram();
352 omap_map_sram(); 353 omap_map_sram();
353 354
354 if (!(cpu_class_is_omap2())) 355 if (!(cpu_class_is_omap2()))
355 omap1_sram_init(); 356 omap1_sram_init();
356 else if (cpu_is_omap242x()) 357 else if (cpu_is_omap242x())
357 omap242x_sram_init(); 358 omap242x_sram_init();
358 else if (cpu_is_omap2430()) 359 else if (cpu_is_omap2430())
359 omap243x_sram_init(); 360 omap243x_sram_init();
360 else if (cpu_is_omap34xx()) 361 else if (cpu_is_omap34xx())
361 omap34xx_sram_init(); 362 omap34xx_sram_init();
362 363
363 return 0; 364 return 0;
364 } 365 }
365 366