Commit 42650d8c9060a2658a79d4e30a5790b23d7753e0
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88ced03149
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powerpc: Fix some #ifndef __KERNEL__ that should be #ifdef
Grrr.... Signed-off-by: Paul Mackerras <paulus@samba.org>
Showing 3 changed files with 3 additions and 3 deletions Inline Diff
include/asm-powerpc/heathrow.h
| 1 | #ifndef _ASM_POWERPC_HEATHROW_H | 1 | #ifndef _ASM_POWERPC_HEATHROW_H |
| 2 | #define _ASM_POWERPC_HEATHROW_H | 2 | #define _ASM_POWERPC_HEATHROW_H |
| 3 | #ifndef __KERNEL__ | 3 | #ifdef __KERNEL__ |
| 4 | /* | 4 | /* |
| 5 | * heathrow.h: definitions for using the "Heathrow" I/O controller chip. | 5 | * heathrow.h: definitions for using the "Heathrow" I/O controller chip. |
| 6 | * | 6 | * |
| 7 | * Grabbed from Open Firmware definitions on a PowerBook G3 Series | 7 | * Grabbed from Open Firmware definitions on a PowerBook G3 Series |
| 8 | * | 8 | * |
| 9 | * Copyright (C) 1997 Paul Mackerras. | 9 | * Copyright (C) 1997 Paul Mackerras. |
| 10 | */ | 10 | */ |
| 11 | 11 | ||
| 12 | /* Front light color on Yikes/B&W G3. 32 bits */ | 12 | /* Front light color on Yikes/B&W G3. 32 bits */ |
| 13 | #define HEATHROW_FRONT_LIGHT 0x32 /* (set to 0 or 0xffffffff) */ | 13 | #define HEATHROW_FRONT_LIGHT 0x32 /* (set to 0 or 0xffffffff) */ |
| 14 | 14 | ||
| 15 | /* Brightness/contrast (gossamer iMac ?). 8 bits */ | 15 | /* Brightness/contrast (gossamer iMac ?). 8 bits */ |
| 16 | #define HEATHROW_BRIGHTNESS_CNTL 0x32 | 16 | #define HEATHROW_BRIGHTNESS_CNTL 0x32 |
| 17 | #define HEATHROW_CONTRAST_CNTL 0x33 | 17 | #define HEATHROW_CONTRAST_CNTL 0x33 |
| 18 | 18 | ||
| 19 | /* offset from ohare base for feature control register */ | 19 | /* offset from ohare base for feature control register */ |
| 20 | #define HEATHROW_MBCR 0x34 /* Media bay control */ | 20 | #define HEATHROW_MBCR 0x34 /* Media bay control */ |
| 21 | #define HEATHROW_FCR 0x38 /* Feature control */ | 21 | #define HEATHROW_FCR 0x38 /* Feature control */ |
| 22 | #define HEATHROW_AUX_CNTL_REG 0x3c /* Aux control */ | 22 | #define HEATHROW_AUX_CNTL_REG 0x3c /* Aux control */ |
| 23 | 23 | ||
| 24 | /* | 24 | /* |
| 25 | * Bits in feature control register. | 25 | * Bits in feature control register. |
| 26 | * Bits postfixed with a _N are in inverse logic | 26 | * Bits postfixed with a _N are in inverse logic |
| 27 | */ | 27 | */ |
| 28 | #define HRW_SCC_TRANS_EN_N 0x00000001 /* Also controls modem power */ | 28 | #define HRW_SCC_TRANS_EN_N 0x00000001 /* Also controls modem power */ |
| 29 | #define HRW_BAY_POWER_N 0x00000002 | 29 | #define HRW_BAY_POWER_N 0x00000002 |
| 30 | #define HRW_BAY_PCI_ENABLE 0x00000004 | 30 | #define HRW_BAY_PCI_ENABLE 0x00000004 |
| 31 | #define HRW_BAY_IDE_ENABLE 0x00000008 | 31 | #define HRW_BAY_IDE_ENABLE 0x00000008 |
| 32 | #define HRW_BAY_FLOPPY_ENABLE 0x00000010 | 32 | #define HRW_BAY_FLOPPY_ENABLE 0x00000010 |
| 33 | #define HRW_IDE0_ENABLE 0x00000020 | 33 | #define HRW_IDE0_ENABLE 0x00000020 |
| 34 | #define HRW_IDE0_RESET_N 0x00000040 | 34 | #define HRW_IDE0_RESET_N 0x00000040 |
| 35 | #define HRW_BAY_DEV_MASK 0x0000001c | 35 | #define HRW_BAY_DEV_MASK 0x0000001c |
| 36 | #define HRW_BAY_RESET_N 0x00000080 | 36 | #define HRW_BAY_RESET_N 0x00000080 |
| 37 | #define HRW_IOBUS_ENABLE 0x00000100 /* Internal IDE ? */ | 37 | #define HRW_IOBUS_ENABLE 0x00000100 /* Internal IDE ? */ |
| 38 | #define HRW_SCC_ENABLE 0x00000200 | 38 | #define HRW_SCC_ENABLE 0x00000200 |
| 39 | #define HRW_MESH_ENABLE 0x00000400 | 39 | #define HRW_MESH_ENABLE 0x00000400 |
| 40 | #define HRW_SWIM_ENABLE 0x00000800 | 40 | #define HRW_SWIM_ENABLE 0x00000800 |
| 41 | #define HRW_SOUND_POWER_N 0x00001000 | 41 | #define HRW_SOUND_POWER_N 0x00001000 |
| 42 | #define HRW_SOUND_CLK_ENABLE 0x00002000 | 42 | #define HRW_SOUND_CLK_ENABLE 0x00002000 |
| 43 | #define HRW_SCCA_IO 0x00004000 | 43 | #define HRW_SCCA_IO 0x00004000 |
| 44 | #define HRW_SCCB_IO 0x00008000 | 44 | #define HRW_SCCB_IO 0x00008000 |
| 45 | #define HRW_PORT_OR_DESK_VIA_N 0x00010000 /* This one is 0 on PowerBook */ | 45 | #define HRW_PORT_OR_DESK_VIA_N 0x00010000 /* This one is 0 on PowerBook */ |
| 46 | #define HRW_PWM_MON_ID_N 0x00020000 /* ??? (0) */ | 46 | #define HRW_PWM_MON_ID_N 0x00020000 /* ??? (0) */ |
| 47 | #define HRW_HOOK_MB_CNT_N 0x00040000 /* ??? (0) */ | 47 | #define HRW_HOOK_MB_CNT_N 0x00040000 /* ??? (0) */ |
| 48 | #define HRW_SWIM_CLONE_FLOPPY 0x00080000 /* ??? (0) */ | 48 | #define HRW_SWIM_CLONE_FLOPPY 0x00080000 /* ??? (0) */ |
| 49 | #define HRW_AUD_RUN22 0x00100000 /* ??? (1) */ | 49 | #define HRW_AUD_RUN22 0x00100000 /* ??? (1) */ |
| 50 | #define HRW_SCSI_LINK_MODE 0x00200000 /* Read ??? (1) */ | 50 | #define HRW_SCSI_LINK_MODE 0x00200000 /* Read ??? (1) */ |
| 51 | #define HRW_ARB_BYPASS 0x00400000 /* Disable internal PCI arbitrer */ | 51 | #define HRW_ARB_BYPASS 0x00400000 /* Disable internal PCI arbitrer */ |
| 52 | #define HRW_IDE1_RESET_N 0x00800000 /* Media bay */ | 52 | #define HRW_IDE1_RESET_N 0x00800000 /* Media bay */ |
| 53 | #define HRW_SLOW_SCC_PCLK 0x01000000 /* ??? (0) */ | 53 | #define HRW_SLOW_SCC_PCLK 0x01000000 /* ??? (0) */ |
| 54 | #define HRW_RESET_SCC 0x02000000 | 54 | #define HRW_RESET_SCC 0x02000000 |
| 55 | #define HRW_MFDC_CELL_ENABLE 0x04000000 /* ??? (0) */ | 55 | #define HRW_MFDC_CELL_ENABLE 0x04000000 /* ??? (0) */ |
| 56 | #define HRW_USE_MFDC 0x08000000 /* ??? (0) */ | 56 | #define HRW_USE_MFDC 0x08000000 /* ??? (0) */ |
| 57 | #define HRW_BMAC_IO_ENABLE 0x60000000 /* two bits, not documented in OF */ | 57 | #define HRW_BMAC_IO_ENABLE 0x60000000 /* two bits, not documented in OF */ |
| 58 | #define HRW_BMAC_RESET 0x80000000 /* not documented in OF */ | 58 | #define HRW_BMAC_RESET 0x80000000 /* not documented in OF */ |
| 59 | 59 | ||
| 60 | /* We OR those features at boot on desktop G3s */ | 60 | /* We OR those features at boot on desktop G3s */ |
| 61 | #define HRW_DEFAULTS (HRW_SCCA_IO | HRW_SCCB_IO | HRW_SCC_ENABLE) | 61 | #define HRW_DEFAULTS (HRW_SCCA_IO | HRW_SCCB_IO | HRW_SCC_ENABLE) |
| 62 | 62 | ||
| 63 | /* Looks like Heathrow has some sort of GPIOs as well... */ | 63 | /* Looks like Heathrow has some sort of GPIOs as well... */ |
| 64 | #define HRW_GPIO_MODEM_RESET 0x6d | 64 | #define HRW_GPIO_MODEM_RESET 0x6d |
| 65 | 65 | ||
| 66 | #endif /* __KERNEL__ */ | 66 | #endif /* __KERNEL__ */ |
| 67 | #endif /* _ASM_POWERPC_HEATHROW_H */ | 67 | #endif /* _ASM_POWERPC_HEATHROW_H */ |
| 68 | 68 |
include/asm-powerpc/ohare.h
| 1 | #ifndef _ASM_POWERPC_OHARE_H | 1 | #ifndef _ASM_POWERPC_OHARE_H |
| 2 | #define _ASM_POWERPC_OHARE_H | 2 | #define _ASM_POWERPC_OHARE_H |
| 3 | #ifndef __KERNEL__ | 3 | #ifdef __KERNEL__ |
| 4 | /* | 4 | /* |
| 5 | * ohare.h: definitions for using the "O'Hare" I/O controller chip. | 5 | * ohare.h: definitions for using the "O'Hare" I/O controller chip. |
| 6 | * | 6 | * |
| 7 | * Copyright (C) 1997 Paul Mackerras. | 7 | * Copyright (C) 1997 Paul Mackerras. |
| 8 | * | 8 | * |
| 9 | * BenH: Changed to match those of heathrow (but not all of them). Please | 9 | * BenH: Changed to match those of heathrow (but not all of them). Please |
| 10 | * check if I didn't break anything (especially the media bay). | 10 | * check if I didn't break anything (especially the media bay). |
| 11 | */ | 11 | */ |
| 12 | 12 | ||
| 13 | /* offset from ohare base for feature control register */ | 13 | /* offset from ohare base for feature control register */ |
| 14 | #define OHARE_MBCR 0x34 | 14 | #define OHARE_MBCR 0x34 |
| 15 | #define OHARE_FCR 0x38 | 15 | #define OHARE_FCR 0x38 |
| 16 | 16 | ||
| 17 | /* | 17 | /* |
| 18 | * Bits in feature control register. | 18 | * Bits in feature control register. |
| 19 | * These were mostly derived by experiment on a powerbook 3400 | 19 | * These were mostly derived by experiment on a powerbook 3400 |
| 20 | * and may differ for other machines. | 20 | * and may differ for other machines. |
| 21 | */ | 21 | */ |
| 22 | #define OH_SCC_RESET 1 | 22 | #define OH_SCC_RESET 1 |
| 23 | #define OH_BAY_POWER_N 2 /* a guess */ | 23 | #define OH_BAY_POWER_N 2 /* a guess */ |
| 24 | #define OH_BAY_PCI_ENABLE 4 /* a guess */ | 24 | #define OH_BAY_PCI_ENABLE 4 /* a guess */ |
| 25 | #define OH_BAY_IDE_ENABLE 8 | 25 | #define OH_BAY_IDE_ENABLE 8 |
| 26 | #define OH_BAY_FLOPPY_ENABLE 0x10 | 26 | #define OH_BAY_FLOPPY_ENABLE 0x10 |
| 27 | #define OH_IDE0_ENABLE 0x20 | 27 | #define OH_IDE0_ENABLE 0x20 |
| 28 | #define OH_IDE0_RESET_N 0x40 /* a guess */ | 28 | #define OH_IDE0_RESET_N 0x40 /* a guess */ |
| 29 | #define OH_BAY_DEV_MASK 0x1c | 29 | #define OH_BAY_DEV_MASK 0x1c |
| 30 | #define OH_BAY_RESET_N 0x80 | 30 | #define OH_BAY_RESET_N 0x80 |
| 31 | #define OH_IOBUS_ENABLE 0x100 /* IOBUS seems to be IDE */ | 31 | #define OH_IOBUS_ENABLE 0x100 /* IOBUS seems to be IDE */ |
| 32 | #define OH_SCC_ENABLE 0x200 | 32 | #define OH_SCC_ENABLE 0x200 |
| 33 | #define OH_MESH_ENABLE 0x400 | 33 | #define OH_MESH_ENABLE 0x400 |
| 34 | #define OH_FLOPPY_ENABLE 0x800 | 34 | #define OH_FLOPPY_ENABLE 0x800 |
| 35 | #define OH_SCCA_IO 0x4000 | 35 | #define OH_SCCA_IO 0x4000 |
| 36 | #define OH_SCCB_IO 0x8000 | 36 | #define OH_SCCB_IO 0x8000 |
| 37 | #define OH_VIA_ENABLE 0x10000 /* Is apparently wrong, to be verified */ | 37 | #define OH_VIA_ENABLE 0x10000 /* Is apparently wrong, to be verified */ |
| 38 | #define OH_IDE1_RESET_N 0x800000 | 38 | #define OH_IDE1_RESET_N 0x800000 |
| 39 | 39 | ||
| 40 | /* | 40 | /* |
| 41 | * Bits to set in the feature control register on PowerBooks. | 41 | * Bits to set in the feature control register on PowerBooks. |
| 42 | */ | 42 | */ |
| 43 | #define PBOOK_FEATURES (OH_IDE_ENABLE | OH_SCC_ENABLE | \ | 43 | #define PBOOK_FEATURES (OH_IDE_ENABLE | OH_SCC_ENABLE | \ |
| 44 | OH_MESH_ENABLE | OH_SCCA_IO | OH_SCCB_IO) | 44 | OH_MESH_ENABLE | OH_SCCA_IO | OH_SCCB_IO) |
| 45 | 45 | ||
| 46 | /* | 46 | /* |
| 47 | * A magic value to put into the feature control register of the | 47 | * A magic value to put into the feature control register of the |
| 48 | * "ohare" I/O controller on Starmaxes to enable the IDE CD interface. | 48 | * "ohare" I/O controller on Starmaxes to enable the IDE CD interface. |
| 49 | * Contributed by Harry Eaton. | 49 | * Contributed by Harry Eaton. |
| 50 | */ | 50 | */ |
| 51 | #define STARMAX_FEATURES 0xbeff7a | 51 | #define STARMAX_FEATURES 0xbeff7a |
| 52 | 52 | ||
| 53 | #endif /* __KERNEL__ */ | 53 | #endif /* __KERNEL__ */ |
| 54 | #endif /* _ASM_POWERPC_OHARE_H */ | 54 | #endif /* _ASM_POWERPC_OHARE_H */ |
| 55 | 55 |
include/asm-powerpc/seccomp.h
| 1 | #ifndef _ASM_POWERPC_SECCOMP_H | 1 | #ifndef _ASM_POWERPC_SECCOMP_H |
| 2 | #define _ASM_POWERPC_SECCOMP_H | 2 | #define _ASM_POWERPC_SECCOMP_H |
| 3 | 3 | ||
| 4 | #ifndef __KERNEL__ | 4 | #ifdef __KERNEL__ |
| 5 | #include <linux/thread_info.h> | 5 | #include <linux/thread_info.h> |
| 6 | #endif | 6 | #endif |
| 7 | 7 | ||
| 8 | #include <linux/unistd.h> | 8 | #include <linux/unistd.h> |
| 9 | 9 | ||
| 10 | #define __NR_seccomp_read __NR_read | 10 | #define __NR_seccomp_read __NR_read |
| 11 | #define __NR_seccomp_write __NR_write | 11 | #define __NR_seccomp_write __NR_write |
| 12 | #define __NR_seccomp_exit __NR_exit | 12 | #define __NR_seccomp_exit __NR_exit |
| 13 | #define __NR_seccomp_sigreturn __NR_rt_sigreturn | 13 | #define __NR_seccomp_sigreturn __NR_rt_sigreturn |
| 14 | 14 | ||
| 15 | #define __NR_seccomp_read_32 __NR_read | 15 | #define __NR_seccomp_read_32 __NR_read |
| 16 | #define __NR_seccomp_write_32 __NR_write | 16 | #define __NR_seccomp_write_32 __NR_write |
| 17 | #define __NR_seccomp_exit_32 __NR_exit | 17 | #define __NR_seccomp_exit_32 __NR_exit |
| 18 | #define __NR_seccomp_sigreturn_32 __NR_sigreturn | 18 | #define __NR_seccomp_sigreturn_32 __NR_sigreturn |
| 19 | 19 | ||
| 20 | #endif /* _ASM_POWERPC_SECCOMP_H */ | 20 | #endif /* _ASM_POWERPC_SECCOMP_H */ |
| 21 | 21 |