Eric Lee / linux-smarc-t335x-v3.2

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Commit 4f0cb8d978ab4b6e3b40147f619f48316d9d7f63

Authored by Ingo Molnar
Committed by Linus Torvalds
1 parent c9b02a2413
Exists in master and in 4 other branches v3.2_AM335xPSP_04.06.00.11, v3.2_NEWT335xPSP_04.06.00.11, v3.2_SBC_SMARTMEN, v3.2_SMARCT335xPSP_04.06.00.11

[PATCH] i386: fix incorrect TSS entry for LDT 

Noticed by Chuck Ebbert: the .ldt entry of the TSS was set up incorrectly.
It never mattered since this was a leftover from old times, so remove it.

Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Adrian Bunk <bunk@stusta.de>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

Showing 1 changed file with 0 additions and 1 deletions Inline Diff

include/asm-i386/processor.h
Diff comments   View file @ 4f0cb8d
1 /* 1 /*
2 * include/asm-i386/processor.h 2 * include/asm-i386/processor.h
3 * 3 *
4 * Copyright (C) 1994 Linus Torvalds 4 * Copyright (C) 1994 Linus Torvalds
5 */ 5 */
6 6
7 #ifndef __ASM_I386_PROCESSOR_H 7 #ifndef __ASM_I386_PROCESSOR_H
8 #define __ASM_I386_PROCESSOR_H 8 #define __ASM_I386_PROCESSOR_H
9 9
10 #include <asm/vm86.h> 10 #include <asm/vm86.h>
11 #include <asm/math_emu.h> 11 #include <asm/math_emu.h>
12 #include <asm/segment.h> 12 #include <asm/segment.h>
13 #include <asm/page.h> 13 #include <asm/page.h>
14 #include <asm/types.h> 14 #include <asm/types.h>
15 #include <asm/sigcontext.h> 15 #include <asm/sigcontext.h>
16 #include <asm/cpufeature.h> 16 #include <asm/cpufeature.h>
17 #include <asm/msr.h> 17 #include <asm/msr.h>
18 #include <asm/system.h> 18 #include <asm/system.h>
19 #include <linux/cache.h> 19 #include <linux/cache.h>
20 #include <linux/config.h> 20 #include <linux/config.h>
21 #include <linux/threads.h> 21 #include <linux/threads.h>
22 #include <asm/percpu.h> 22 #include <asm/percpu.h>
23 23
24 /* flag for disabling the tsc */ 24 /* flag for disabling the tsc */
25 extern int tsc_disable; 25 extern int tsc_disable;
26 26
27 struct desc_struct { 27 struct desc_struct {
28 unsigned long a,b; 28 unsigned long a,b;
29 }; 29 };
30 30
31 #define desc_empty(desc) \ 31 #define desc_empty(desc) \
32 (!((desc)->a | (desc)->b)) 32 (!((desc)->a | (desc)->b))
33 33
34 #define desc_equal(desc1, desc2) \ 34 #define desc_equal(desc1, desc2) \
35 (((desc1)->a == (desc2)->a) && ((desc1)->b == (desc2)->b)) 35 (((desc1)->a == (desc2)->a) && ((desc1)->b == (desc2)->b))
36 /* 36 /*
37 * Default implementation of macro that returns current 37 * Default implementation of macro that returns current
38 * instruction pointer ("program counter"). 38 * instruction pointer ("program counter").
39 */ 39 */
40 #define current_text_addr() ({ void *pc; __asm__("movl $1f,%0\n1:":"=g" (pc)); pc; }) 40 #define current_text_addr() ({ void *pc; __asm__("movl $1f,%0\n1:":"=g" (pc)); pc; })
41 41
42 /* 42 /*
43 * CPU type and hardware bug flags. Kept separately for each CPU. 43 * CPU type and hardware bug flags. Kept separately for each CPU.
44 * Members of this structure are referenced in head.S, so think twice 44 * Members of this structure are referenced in head.S, so think twice
45 * before touching them. [mj] 45 * before touching them. [mj]
46 */ 46 */
47 47
48 struct cpuinfo_x86 { 48 struct cpuinfo_x86 {
49 __u8 x86; /* CPU family */ 49 __u8 x86; /* CPU family */
50 __u8 x86_vendor; /* CPU vendor */ 50 __u8 x86_vendor; /* CPU vendor */
51 __u8 x86_model; 51 __u8 x86_model;
52 __u8 x86_mask; 52 __u8 x86_mask;
53 char wp_works_ok; /* It doesn't on 386's */ 53 char wp_works_ok; /* It doesn't on 386's */
54 char hlt_works_ok; /* Problems on some 486Dx4's and old 386's */ 54 char hlt_works_ok; /* Problems on some 486Dx4's and old 386's */
55 char hard_math; 55 char hard_math;
56 char rfu; 56 char rfu;
57 int cpuid_level; /* Maximum supported CPUID level, -1=no CPUID */ 57 int cpuid_level; /* Maximum supported CPUID level, -1=no CPUID */
58 unsigned long x86_capability[NCAPINTS]; 58 unsigned long x86_capability[NCAPINTS];
59 char x86_vendor_id[16]; 59 char x86_vendor_id[16];
60 char x86_model_id[64]; 60 char x86_model_id[64];
61 int x86_cache_size; /* in KB - valid for CPUS which support this 61 int x86_cache_size; /* in KB - valid for CPUS which support this
62 call */ 62 call */
63 int x86_cache_alignment; /* In bytes */ 63 int x86_cache_alignment; /* In bytes */
64 int fdiv_bug; 64 int fdiv_bug;
65 int f00f_bug; 65 int f00f_bug;
66 int coma_bug; 66 int coma_bug;
67 unsigned long loops_per_jiffy; 67 unsigned long loops_per_jiffy;
68 unsigned char x86_num_cores; 68 unsigned char x86_num_cores;
69 } __attribute__((__aligned__(SMP_CACHE_BYTES))); 69 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
70 70
71 #define X86_VENDOR_INTEL 0 71 #define X86_VENDOR_INTEL 0
72 #define X86_VENDOR_CYRIX 1 72 #define X86_VENDOR_CYRIX 1
73 #define X86_VENDOR_AMD 2 73 #define X86_VENDOR_AMD 2
74 #define X86_VENDOR_UMC 3 74 #define X86_VENDOR_UMC 3
75 #define X86_VENDOR_NEXGEN 4 75 #define X86_VENDOR_NEXGEN 4
76 #define X86_VENDOR_CENTAUR 5 76 #define X86_VENDOR_CENTAUR 5
77 #define X86_VENDOR_RISE 6 77 #define X86_VENDOR_RISE 6
78 #define X86_VENDOR_TRANSMETA 7 78 #define X86_VENDOR_TRANSMETA 7
79 #define X86_VENDOR_NSC 8 79 #define X86_VENDOR_NSC 8
80 #define X86_VENDOR_NUM 9 80 #define X86_VENDOR_NUM 9
81 #define X86_VENDOR_UNKNOWN 0xff 81 #define X86_VENDOR_UNKNOWN 0xff
82 82
83 /* 83 /*
84 * capabilities of CPUs 84 * capabilities of CPUs
85 */ 85 */
86 86
87 extern struct cpuinfo_x86 boot_cpu_data; 87 extern struct cpuinfo_x86 boot_cpu_data;
88 extern struct cpuinfo_x86 new_cpu_data; 88 extern struct cpuinfo_x86 new_cpu_data;
89 extern struct tss_struct doublefault_tss; 89 extern struct tss_struct doublefault_tss;
90 DECLARE_PER_CPU(struct tss_struct, init_tss); 90 DECLARE_PER_CPU(struct tss_struct, init_tss);
91 91
92 #ifdef CONFIG_SMP 92 #ifdef CONFIG_SMP
93 extern struct cpuinfo_x86 cpu_data[]; 93 extern struct cpuinfo_x86 cpu_data[];
94 #define current_cpu_data cpu_data[smp_processor_id()] 94 #define current_cpu_data cpu_data[smp_processor_id()]
95 #else 95 #else
96 #define cpu_data (&boot_cpu_data) 96 #define cpu_data (&boot_cpu_data)
97 #define current_cpu_data boot_cpu_data 97 #define current_cpu_data boot_cpu_data
98 #endif 98 #endif
99 99
100 extern int phys_proc_id[NR_CPUS]; 100 extern int phys_proc_id[NR_CPUS];
101 extern int cpu_core_id[NR_CPUS]; 101 extern int cpu_core_id[NR_CPUS];
102 extern char ignore_fpu_irq; 102 extern char ignore_fpu_irq;
103 103
104 extern void identify_cpu(struct cpuinfo_x86 *); 104 extern void identify_cpu(struct cpuinfo_x86 *);
105 extern void print_cpu_info(struct cpuinfo_x86 *); 105 extern void print_cpu_info(struct cpuinfo_x86 *);
106 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c); 106 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
107 107
108 #ifdef CONFIG_X86_HT 108 #ifdef CONFIG_X86_HT
109 extern void detect_ht(struct cpuinfo_x86 *c); 109 extern void detect_ht(struct cpuinfo_x86 *c);
110 #else 110 #else
111 static inline void detect_ht(struct cpuinfo_x86 *c) {} 111 static inline void detect_ht(struct cpuinfo_x86 *c) {}
112 #endif 112 #endif
113 113
114 /* 114 /*
115 * EFLAGS bits 115 * EFLAGS bits
116 */ 116 */
117 #define X86_EFLAGS_CF 0x00000001 /* Carry Flag */ 117 #define X86_EFLAGS_CF 0x00000001 /* Carry Flag */
118 #define X86_EFLAGS_PF 0x00000004 /* Parity Flag */ 118 #define X86_EFLAGS_PF 0x00000004 /* Parity Flag */
119 #define X86_EFLAGS_AF 0x00000010 /* Auxillary carry Flag */ 119 #define X86_EFLAGS_AF 0x00000010 /* Auxillary carry Flag */
120 #define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */ 120 #define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */
121 #define X86_EFLAGS_SF 0x00000080 /* Sign Flag */ 121 #define X86_EFLAGS_SF 0x00000080 /* Sign Flag */
122 #define X86_EFLAGS_TF 0x00000100 /* Trap Flag */ 122 #define X86_EFLAGS_TF 0x00000100 /* Trap Flag */
123 #define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */ 123 #define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */
124 #define X86_EFLAGS_DF 0x00000400 /* Direction Flag */ 124 #define X86_EFLAGS_DF 0x00000400 /* Direction Flag */
125 #define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */ 125 #define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */
126 #define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */ 126 #define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */
127 #define X86_EFLAGS_NT 0x00004000 /* Nested Task */ 127 #define X86_EFLAGS_NT 0x00004000 /* Nested Task */
128 #define X86_EFLAGS_RF 0x00010000 /* Resume Flag */ 128 #define X86_EFLAGS_RF 0x00010000 /* Resume Flag */
129 #define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */ 129 #define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */
130 #define X86_EFLAGS_AC 0x00040000 /* Alignment Check */ 130 #define X86_EFLAGS_AC 0x00040000 /* Alignment Check */
131 #define X86_EFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */ 131 #define X86_EFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */
132 #define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */ 132 #define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */
133 #define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */ 133 #define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */
134 134
135 /* 135 /*
136 * Generic CPUID function 136 * Generic CPUID function
137 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx 137 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
138 * resulting in stale register contents being returned. 138 * resulting in stale register contents being returned.
139 */ 139 */
140 static inline void cpuid(unsigned int op, unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx) 140 static inline void cpuid(unsigned int op, unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx)
141 { 141 {
142 __asm__("cpuid" 142 __asm__("cpuid"
143 : "=a" (*eax), 143 : "=a" (*eax),
144 "=b" (*ebx), 144 "=b" (*ebx),
145 "=c" (*ecx), 145 "=c" (*ecx),
146 "=d" (*edx) 146 "=d" (*edx)
147 : "0" (op), "c"(0)); 147 : "0" (op), "c"(0));
148 } 148 }
149 149
150 /* Some CPUID calls want 'count' to be placed in ecx */ 150 /* Some CPUID calls want 'count' to be placed in ecx */
151 static inline void cpuid_count(int op, int count, int *eax, int *ebx, int *ecx, 151 static inline void cpuid_count(int op, int count, int *eax, int *ebx, int *ecx,
152 int *edx) 152 int *edx)
153 { 153 {
154 __asm__("cpuid" 154 __asm__("cpuid"
155 : "=a" (*eax), 155 : "=a" (*eax),
156 "=b" (*ebx), 156 "=b" (*ebx),
157 "=c" (*ecx), 157 "=c" (*ecx),
158 "=d" (*edx) 158 "=d" (*edx)
159 : "0" (op), "c" (count)); 159 : "0" (op), "c" (count));
160 } 160 }
161 161
162 /* 162 /*
163 * CPUID functions returning a single datum 163 * CPUID functions returning a single datum
164 */ 164 */
165 static inline unsigned int cpuid_eax(unsigned int op) 165 static inline unsigned int cpuid_eax(unsigned int op)
166 { 166 {
167 unsigned int eax; 167 unsigned int eax;
168 168
169 __asm__("cpuid" 169 __asm__("cpuid"
170 : "=a" (eax) 170 : "=a" (eax)
171 : "0" (op) 171 : "0" (op)
172 : "bx", "cx", "dx"); 172 : "bx", "cx", "dx");
173 return eax; 173 return eax;
174 } 174 }
175 static inline unsigned int cpuid_ebx(unsigned int op) 175 static inline unsigned int cpuid_ebx(unsigned int op)
176 { 176 {
177 unsigned int eax, ebx; 177 unsigned int eax, ebx;
178 178
179 __asm__("cpuid" 179 __asm__("cpuid"
180 : "=a" (eax), "=b" (ebx) 180 : "=a" (eax), "=b" (ebx)
181 : "0" (op) 181 : "0" (op)
182 : "cx", "dx" ); 182 : "cx", "dx" );
183 return ebx; 183 return ebx;
184 } 184 }
185 static inline unsigned int cpuid_ecx(unsigned int op) 185 static inline unsigned int cpuid_ecx(unsigned int op)
186 { 186 {
187 unsigned int eax, ecx; 187 unsigned int eax, ecx;
188 188
189 __asm__("cpuid" 189 __asm__("cpuid"
190 : "=a" (eax), "=c" (ecx) 190 : "=a" (eax), "=c" (ecx)
191 : "0" (op) 191 : "0" (op)
192 : "bx", "dx" ); 192 : "bx", "dx" );
193 return ecx; 193 return ecx;
194 } 194 }
195 static inline unsigned int cpuid_edx(unsigned int op) 195 static inline unsigned int cpuid_edx(unsigned int op)
196 { 196 {
197 unsigned int eax, edx; 197 unsigned int eax, edx;
198 198
199 __asm__("cpuid" 199 __asm__("cpuid"
200 : "=a" (eax), "=d" (edx) 200 : "=a" (eax), "=d" (edx)
201 : "0" (op) 201 : "0" (op)
202 : "bx", "cx"); 202 : "bx", "cx");
203 return edx; 203 return edx;
204 } 204 }
205 205
206 #define load_cr3(pgdir) write_cr3(__pa(pgdir)) 206 #define load_cr3(pgdir) write_cr3(__pa(pgdir))
207 207
208 /* 208 /*
209 * Intel CPU features in CR4 209 * Intel CPU features in CR4
210 */ 210 */
211 #define X86_CR4_VME 0x0001 /* enable vm86 extensions */ 211 #define X86_CR4_VME 0x0001 /* enable vm86 extensions */
212 #define X86_CR4_PVI 0x0002 /* virtual interrupts flag enable */ 212 #define X86_CR4_PVI 0x0002 /* virtual interrupts flag enable */
213 #define X86_CR4_TSD 0x0004 /* disable time stamp at ipl 3 */ 213 #define X86_CR4_TSD 0x0004 /* disable time stamp at ipl 3 */
214 #define X86_CR4_DE 0x0008 /* enable debugging extensions */ 214 #define X86_CR4_DE 0x0008 /* enable debugging extensions */
215 #define X86_CR4_PSE 0x0010 /* enable page size extensions */ 215 #define X86_CR4_PSE 0x0010 /* enable page size extensions */
216 #define X86_CR4_PAE 0x0020 /* enable physical address extensions */ 216 #define X86_CR4_PAE 0x0020 /* enable physical address extensions */
217 #define X86_CR4_MCE 0x0040 /* Machine check enable */ 217 #define X86_CR4_MCE 0x0040 /* Machine check enable */
218 #define X86_CR4_PGE 0x0080 /* enable global pages */ 218 #define X86_CR4_PGE 0x0080 /* enable global pages */
219 #define X86_CR4_PCE 0x0100 /* enable performance counters at ipl 3 */ 219 #define X86_CR4_PCE 0x0100 /* enable performance counters at ipl 3 */
220 #define X86_CR4_OSFXSR 0x0200 /* enable fast FPU save and restore */ 220 #define X86_CR4_OSFXSR 0x0200 /* enable fast FPU save and restore */
221 #define X86_CR4_OSXMMEXCPT 0x0400 /* enable unmasked SSE exceptions */ 221 #define X86_CR4_OSXMMEXCPT 0x0400 /* enable unmasked SSE exceptions */
222 222
223 /* 223 /*
224 * Save the cr4 feature set we're using (ie 224 * Save the cr4 feature set we're using (ie
225 * Pentium 4MB enable and PPro Global page 225 * Pentium 4MB enable and PPro Global page
226 * enable), so that any CPU's that boot up 226 * enable), so that any CPU's that boot up
227 * after us can get the correct flags. 227 * after us can get the correct flags.
228 */ 228 */
229 extern unsigned long mmu_cr4_features; 229 extern unsigned long mmu_cr4_features;
230 230
231 static inline void set_in_cr4 (unsigned long mask) 231 static inline void set_in_cr4 (unsigned long mask)
232 { 232 {
233 unsigned cr4; 233 unsigned cr4;
234 mmu_cr4_features |= mask; 234 mmu_cr4_features |= mask;
235 cr4 = read_cr4(); 235 cr4 = read_cr4();
236 cr4 |= mask; 236 cr4 |= mask;
237 write_cr4(cr4); 237 write_cr4(cr4);
238 } 238 }
239 239
240 static inline void clear_in_cr4 (unsigned long mask) 240 static inline void clear_in_cr4 (unsigned long mask)
241 { 241 {
242 unsigned cr4; 242 unsigned cr4;
243 mmu_cr4_features &= ~mask; 243 mmu_cr4_features &= ~mask;
244 cr4 = read_cr4(); 244 cr4 = read_cr4();
245 cr4 &= ~mask; 245 cr4 &= ~mask;
246 write_cr4(cr4); 246 write_cr4(cr4);
247 } 247 }
248 248
249 /* 249 /*
250 * NSC/Cyrix CPU configuration register indexes 250 * NSC/Cyrix CPU configuration register indexes
251 */ 251 */
252 252
253 #define CX86_PCR0 0x20 253 #define CX86_PCR0 0x20
254 #define CX86_GCR 0xb8 254 #define CX86_GCR 0xb8
255 #define CX86_CCR0 0xc0 255 #define CX86_CCR0 0xc0
256 #define CX86_CCR1 0xc1 256 #define CX86_CCR1 0xc1
257 #define CX86_CCR2 0xc2 257 #define CX86_CCR2 0xc2
258 #define CX86_CCR3 0xc3 258 #define CX86_CCR3 0xc3
259 #define CX86_CCR4 0xe8 259 #define CX86_CCR4 0xe8
260 #define CX86_CCR5 0xe9 260 #define CX86_CCR5 0xe9
261 #define CX86_CCR6 0xea 261 #define CX86_CCR6 0xea
262 #define CX86_CCR7 0xeb 262 #define CX86_CCR7 0xeb
263 #define CX86_PCR1 0xf0 263 #define CX86_PCR1 0xf0
264 #define CX86_DIR0 0xfe 264 #define CX86_DIR0 0xfe
265 #define CX86_DIR1 0xff 265 #define CX86_DIR1 0xff
266 #define CX86_ARR_BASE 0xc4 266 #define CX86_ARR_BASE 0xc4
267 #define CX86_RCR_BASE 0xdc 267 #define CX86_RCR_BASE 0xdc
268 268
269 /* 269 /*
270 * NSC/Cyrix CPU indexed register access macros 270 * NSC/Cyrix CPU indexed register access macros
271 */ 271 */
272 272
273 #define getCx86(reg) ({ outb((reg), 0x22); inb(0x23); }) 273 #define getCx86(reg) ({ outb((reg), 0x22); inb(0x23); })
274 274
275 #define setCx86(reg, data) do { \ 275 #define setCx86(reg, data) do { \
276 outb((reg), 0x22); \ 276 outb((reg), 0x22); \
277 outb((data), 0x23); \ 277 outb((data), 0x23); \
278 } while (0) 278 } while (0)
279 279
280 static inline void serialize_cpu(void) 280 static inline void serialize_cpu(void)
281 { 281 {
282 __asm__ __volatile__ ("cpuid" : : : "ax", "bx", "cx", "dx"); 282 __asm__ __volatile__ ("cpuid" : : : "ax", "bx", "cx", "dx");
283 } 283 }
284 284
285 static inline void __monitor(const void *eax, unsigned long ecx, 285 static inline void __monitor(const void *eax, unsigned long ecx,
286 unsigned long edx) 286 unsigned long edx)
287 { 287 {
288 /* "monitor %eax,%ecx,%edx;" */ 288 /* "monitor %eax,%ecx,%edx;" */
289 asm volatile( 289 asm volatile(
290 ".byte 0x0f,0x01,0xc8;" 290 ".byte 0x0f,0x01,0xc8;"
291 : :"a" (eax), "c" (ecx), "d"(edx)); 291 : :"a" (eax), "c" (ecx), "d"(edx));
292 } 292 }
293 293
294 static inline void __mwait(unsigned long eax, unsigned long ecx) 294 static inline void __mwait(unsigned long eax, unsigned long ecx)
295 { 295 {
296 /* "mwait %eax,%ecx;" */ 296 /* "mwait %eax,%ecx;" */
297 asm volatile( 297 asm volatile(
298 ".byte 0x0f,0x01,0xc9;" 298 ".byte 0x0f,0x01,0xc9;"
299 : :"a" (eax), "c" (ecx)); 299 : :"a" (eax), "c" (ecx));
300 } 300 }
301 301
302 /* from system description table in BIOS. Mostly for MCA use, but 302 /* from system description table in BIOS. Mostly for MCA use, but
303 others may find it useful. */ 303 others may find it useful. */
304 extern unsigned int machine_id; 304 extern unsigned int machine_id;
305 extern unsigned int machine_submodel_id; 305 extern unsigned int machine_submodel_id;
306 extern unsigned int BIOS_revision; 306 extern unsigned int BIOS_revision;
307 extern unsigned int mca_pentium_flag; 307 extern unsigned int mca_pentium_flag;
308 308
309 /* Boot loader type from the setup header */ 309 /* Boot loader type from the setup header */
310 extern int bootloader_type; 310 extern int bootloader_type;
311 311
312 /* 312 /*
313 * User space process size: 3GB (default). 313 * User space process size: 3GB (default).
314 */ 314 */
315 #define TASK_SIZE (PAGE_OFFSET) 315 #define TASK_SIZE (PAGE_OFFSET)
316 316
317 /* This decides where the kernel will search for a free chunk of vm 317 /* This decides where the kernel will search for a free chunk of vm
318 * space during mmap's. 318 * space during mmap's.
319 */ 319 */
320 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3)) 320 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
321 321
322 #define HAVE_ARCH_PICK_MMAP_LAYOUT 322 #define HAVE_ARCH_PICK_MMAP_LAYOUT
323 323
324 /* 324 /*
325 * Size of io_bitmap. 325 * Size of io_bitmap.
326 */ 326 */
327 #define IO_BITMAP_BITS 65536 327 #define IO_BITMAP_BITS 65536
328 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8) 328 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
329 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long)) 329 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
330 #define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap) 330 #define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap)
331 #define INVALID_IO_BITMAP_OFFSET 0x8000 331 #define INVALID_IO_BITMAP_OFFSET 0x8000
332 #define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000 332 #define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
333 333
334 struct i387_fsave_struct { 334 struct i387_fsave_struct {
335 long cwd; 335 long cwd;
336 long swd; 336 long swd;
337 long twd; 337 long twd;
338 long fip; 338 long fip;
339 long fcs; 339 long fcs;
340 long foo; 340 long foo;
341 long fos; 341 long fos;
342 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */ 342 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
343 long status; /* software status information */ 343 long status; /* software status information */
344 }; 344 };
345 345
346 struct i387_fxsave_struct { 346 struct i387_fxsave_struct {
347 unsigned short cwd; 347 unsigned short cwd;
348 unsigned short swd; 348 unsigned short swd;
349 unsigned short twd; 349 unsigned short twd;
350 unsigned short fop; 350 unsigned short fop;
351 long fip; 351 long fip;
352 long fcs; 352 long fcs;
353 long foo; 353 long foo;
354 long fos; 354 long fos;
355 long mxcsr; 355 long mxcsr;
356 long mxcsr_mask; 356 long mxcsr_mask;
357 long st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */ 357 long st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
358 long xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */ 358 long xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
359 long padding[56]; 359 long padding[56];
360 } __attribute__ ((aligned (16))); 360 } __attribute__ ((aligned (16)));
361 361
362 struct i387_soft_struct { 362 struct i387_soft_struct {
363 long cwd; 363 long cwd;
364 long swd; 364 long swd;
365 long twd; 365 long twd;
366 long fip; 366 long fip;
367 long fcs; 367 long fcs;
368 long foo; 368 long foo;
369 long fos; 369 long fos;
370 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */ 370 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
371 unsigned char ftop, changed, lookahead, no_update, rm, alimit; 371 unsigned char ftop, changed, lookahead, no_update, rm, alimit;
372 struct info *info; 372 struct info *info;
373 unsigned long entry_eip; 373 unsigned long entry_eip;
374 }; 374 };
375 375
376 union i387_union { 376 union i387_union {
377 struct i387_fsave_struct fsave; 377 struct i387_fsave_struct fsave;
378 struct i387_fxsave_struct fxsave; 378 struct i387_fxsave_struct fxsave;
379 struct i387_soft_struct soft; 379 struct i387_soft_struct soft;
380 }; 380 };
381 381
382 typedef struct { 382 typedef struct {
383 unsigned long seg; 383 unsigned long seg;
384 } mm_segment_t; 384 } mm_segment_t;
385 385
386 struct thread_struct; 386 struct thread_struct;
387 387
388 struct tss_struct { 388 struct tss_struct {
389 unsigned short back_link,__blh; 389 unsigned short back_link,__blh;
390 unsigned long esp0; 390 unsigned long esp0;
391 unsigned short ss0,__ss0h; 391 unsigned short ss0,__ss0h;
392 unsigned long esp1; 392 unsigned long esp1;
393 unsigned short ss1,__ss1h; /* ss1 is used to cache MSR_IA32_SYSENTER_CS */ 393 unsigned short ss1,__ss1h; /* ss1 is used to cache MSR_IA32_SYSENTER_CS */
394 unsigned long esp2; 394 unsigned long esp2;
395 unsigned short ss2,__ss2h; 395 unsigned short ss2,__ss2h;
396 unsigned long __cr3; 396 unsigned long __cr3;
397 unsigned long eip; 397 unsigned long eip;
398 unsigned long eflags; 398 unsigned long eflags;
399 unsigned long eax,ecx,edx,ebx; 399 unsigned long eax,ecx,edx,ebx;
400 unsigned long esp; 400 unsigned long esp;
401 unsigned long ebp; 401 unsigned long ebp;
402 unsigned long esi; 402 unsigned long esi;
403 unsigned long edi; 403 unsigned long edi;
404 unsigned short es, __esh; 404 unsigned short es, __esh;
405 unsigned short cs, __csh; 405 unsigned short cs, __csh;
406 unsigned short ss, __ssh; 406 unsigned short ss, __ssh;
407 unsigned short ds, __dsh; 407 unsigned short ds, __dsh;
408 unsigned short fs, __fsh; 408 unsigned short fs, __fsh;
409 unsigned short gs, __gsh; 409 unsigned short gs, __gsh;
410 unsigned short ldt, __ldth; 410 unsigned short ldt, __ldth;
411 unsigned short trace, io_bitmap_base; 411 unsigned short trace, io_bitmap_base;
412 /* 412 /*
413 * The extra 1 is there because the CPU will access an 413 * The extra 1 is there because the CPU will access an
414 * additional byte beyond the end of the IO permission 414 * additional byte beyond the end of the IO permission
415 * bitmap. The extra byte must be all 1 bits, and must 415 * bitmap. The extra byte must be all 1 bits, and must
416 * be within the limit. 416 * be within the limit.
417 */ 417 */
418 unsigned long io_bitmap[IO_BITMAP_LONGS + 1]; 418 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
419 /* 419 /*
420 * Cache the current maximum and the last task that used the bitmap: 420 * Cache the current maximum and the last task that used the bitmap:
421 */ 421 */
422 unsigned long io_bitmap_max; 422 unsigned long io_bitmap_max;
423 struct thread_struct *io_bitmap_owner; 423 struct thread_struct *io_bitmap_owner;
424 /* 424 /*
425 * pads the TSS to be cacheline-aligned (size is 0x100) 425 * pads the TSS to be cacheline-aligned (size is 0x100)
426 */ 426 */
427 unsigned long __cacheline_filler[35]; 427 unsigned long __cacheline_filler[35];
428 /* 428 /*
429 * .. and then another 0x100 bytes for emergency kernel stack 429 * .. and then another 0x100 bytes for emergency kernel stack
430 */ 430 */
431 unsigned long stack[64]; 431 unsigned long stack[64];
432 } __attribute__((packed)); 432 } __attribute__((packed));
433 433
434 #define ARCH_MIN_TASKALIGN 16 434 #define ARCH_MIN_TASKALIGN 16
435 435
436 struct thread_struct { 436 struct thread_struct {
437 /* cached TLS descriptors. */ 437 /* cached TLS descriptors. */
438 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES]; 438 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
439 unsigned long esp0; 439 unsigned long esp0;
440 unsigned long sysenter_cs; 440 unsigned long sysenter_cs;
441 unsigned long eip; 441 unsigned long eip;
442 unsigned long esp; 442 unsigned long esp;
443 unsigned long fs; 443 unsigned long fs;
444 unsigned long gs; 444 unsigned long gs;
445 /* Hardware debugging registers */ 445 /* Hardware debugging registers */
446 unsigned long debugreg[8]; /* %%db0-7 debug registers */ 446 unsigned long debugreg[8]; /* %%db0-7 debug registers */
447 /* fault info */ 447 /* fault info */
448 unsigned long cr2, trap_no, error_code; 448 unsigned long cr2, trap_no, error_code;
449 /* floating point info */ 449 /* floating point info */
450 union i387_union i387; 450 union i387_union i387;
451 /* virtual 86 mode info */ 451 /* virtual 86 mode info */
452 struct vm86_struct __user * vm86_info; 452 struct vm86_struct __user * vm86_info;
453 unsigned long screen_bitmap; 453 unsigned long screen_bitmap;
454 unsigned long v86flags, v86mask, saved_esp0; 454 unsigned long v86flags, v86mask, saved_esp0;
455 unsigned int saved_fs, saved_gs; 455 unsigned int saved_fs, saved_gs;
456 /* IO permissions */ 456 /* IO permissions */
457 unsigned long *io_bitmap_ptr; 457 unsigned long *io_bitmap_ptr;
458 /* max allowed port in the bitmap, in bytes: */ 458 /* max allowed port in the bitmap, in bytes: */
459 unsigned long io_bitmap_max; 459 unsigned long io_bitmap_max;
460 }; 460 };
461 461
462 #define INIT_THREAD { \ 462 #define INIT_THREAD { \
463 .vm86_info = NULL, \ 463 .vm86_info = NULL, \
464 .sysenter_cs = __KERNEL_CS, \ 464 .sysenter_cs = __KERNEL_CS, \
465 .io_bitmap_ptr = NULL, \ 465 .io_bitmap_ptr = NULL, \
466 } 466 }
467 467
468 /* 468 /*
469 * Note that the .io_bitmap member must be extra-big. This is because 469 * Note that the .io_bitmap member must be extra-big. This is because
470 * the CPU will access an additional byte beyond the end of the IO 470 * the CPU will access an additional byte beyond the end of the IO
471 * permission bitmap. The extra byte must be all 1 bits, and must 471 * permission bitmap. The extra byte must be all 1 bits, and must
472 * be within the limit. 472 * be within the limit.
473 */ 473 */
474 #define INIT_TSS { \ 474 #define INIT_TSS { \
475 .esp0 = sizeof(init_stack) + (long)&init_stack, \ 475 .esp0 = sizeof(init_stack) + (long)&init_stack, \
476 .ss0 = __KERNEL_DS, \ 476 .ss0 = __KERNEL_DS, \
477 .ss1 = __KERNEL_CS, \ 477 .ss1 = __KERNEL_CS, \
478 .ldt = GDT_ENTRY_LDT, \
479 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \ 478 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
480 .io_bitmap = { [ 0 ... IO_BITMAP_LONGS] = ~0 }, \ 479 .io_bitmap = { [ 0 ... IO_BITMAP_LONGS] = ~0 }, \
481 } 480 }
482 481
483 static inline void load_esp0(struct tss_struct *tss, struct thread_struct *thread) 482 static inline void load_esp0(struct tss_struct *tss, struct thread_struct *thread)
484 { 483 {
485 tss->esp0 = thread->esp0; 484 tss->esp0 = thread->esp0;
486 /* This can only happen when SEP is enabled, no need to test "SEP"arately */ 485 /* This can only happen when SEP is enabled, no need to test "SEP"arately */
487 if (unlikely(tss->ss1 != thread->sysenter_cs)) { 486 if (unlikely(tss->ss1 != thread->sysenter_cs)) {
488 tss->ss1 = thread->sysenter_cs; 487 tss->ss1 = thread->sysenter_cs;
489 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0); 488 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
490 } 489 }
491 } 490 }
492 491
493 #define start_thread(regs, new_eip, new_esp) do { \ 492 #define start_thread(regs, new_eip, new_esp) do { \
494 __asm__("movl %0,%%fs ; movl %0,%%gs": :"r" (0)); \ 493 __asm__("movl %0,%%fs ; movl %0,%%gs": :"r" (0)); \
495 set_fs(USER_DS); \ 494 set_fs(USER_DS); \
496 regs->xds = __USER_DS; \ 495 regs->xds = __USER_DS; \
497 regs->xes = __USER_DS; \ 496 regs->xes = __USER_DS; \
498 regs->xss = __USER_DS; \ 497 regs->xss = __USER_DS; \
499 regs->xcs = __USER_CS; \ 498 regs->xcs = __USER_CS; \
500 regs->eip = new_eip; \ 499 regs->eip = new_eip; \
501 regs->esp = new_esp; \ 500 regs->esp = new_esp; \
502 } while (0) 501 } while (0)
503 502
504 /* 503 /*
505 * These special macros can be used to get or set a debugging register 504 * These special macros can be used to get or set a debugging register
506 */ 505 */
507 #define get_debugreg(var, register) \ 506 #define get_debugreg(var, register) \
508 __asm__("movl %%db" #register ", %0" \ 507 __asm__("movl %%db" #register ", %0" \
509 :"=r" (var)) 508 :"=r" (var))
510 #define set_debugreg(value, register) \ 509 #define set_debugreg(value, register) \
511 __asm__("movl %0,%%db" #register \ 510 __asm__("movl %0,%%db" #register \
512 : /* no output */ \ 511 : /* no output */ \
513 :"r" (value)) 512 :"r" (value))
514 513
515 514
516 /* Forward declaration, a strange C thing */ 515 /* Forward declaration, a strange C thing */
517 struct task_struct; 516 struct task_struct;
518 struct mm_struct; 517 struct mm_struct;
519 518
520 /* Free all resources held by a thread. */ 519 /* Free all resources held by a thread. */
521 extern void release_thread(struct task_struct *); 520 extern void release_thread(struct task_struct *);
522 521
523 /* Prepare to copy thread state - unlazy all lazy status */ 522 /* Prepare to copy thread state - unlazy all lazy status */
524 extern void prepare_to_copy(struct task_struct *tsk); 523 extern void prepare_to_copy(struct task_struct *tsk);
525 524
526 /* 525 /*
527 * create a kernel thread without removing it from tasklists 526 * create a kernel thread without removing it from tasklists
528 */ 527 */
529 extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags); 528 extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
530 529
531 extern unsigned long thread_saved_pc(struct task_struct *tsk); 530 extern unsigned long thread_saved_pc(struct task_struct *tsk);
532 void show_trace(struct task_struct *task, unsigned long *stack); 531 void show_trace(struct task_struct *task, unsigned long *stack);
533 532
534 unsigned long get_wchan(struct task_struct *p); 533 unsigned long get_wchan(struct task_struct *p);
535 534
536 #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long)) 535 #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
537 #define KSTK_TOP(info) \ 536 #define KSTK_TOP(info) \
538 ({ \ 537 ({ \
539 unsigned long *__ptr = (unsigned long *)(info); \ 538 unsigned long *__ptr = (unsigned long *)(info); \
540 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \ 539 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
541 }) 540 })
542 541
543 #define task_pt_regs(task) \ 542 #define task_pt_regs(task) \
544 ({ \ 543 ({ \
545 struct pt_regs *__regs__; \ 544 struct pt_regs *__regs__; \
546 __regs__ = (struct pt_regs *)KSTK_TOP((task)->thread_info); \ 545 __regs__ = (struct pt_regs *)KSTK_TOP((task)->thread_info); \
547 __regs__ - 1; \ 546 __regs__ - 1; \
548 }) 547 })
549 548
550 #define KSTK_EIP(task) (task_pt_regs(task)->eip) 549 #define KSTK_EIP(task) (task_pt_regs(task)->eip)
551 #define KSTK_ESP(task) (task_pt_regs(task)->esp) 550 #define KSTK_ESP(task) (task_pt_regs(task)->esp)
552 551
553 552
554 struct microcode_header { 553 struct microcode_header {
555 unsigned int hdrver; 554 unsigned int hdrver;
556 unsigned int rev; 555 unsigned int rev;
557 unsigned int date; 556 unsigned int date;
558 unsigned int sig; 557 unsigned int sig;
559 unsigned int cksum; 558 unsigned int cksum;
560 unsigned int ldrver; 559 unsigned int ldrver;
561 unsigned int pf; 560 unsigned int pf;
562 unsigned int datasize; 561 unsigned int datasize;
563 unsigned int totalsize; 562 unsigned int totalsize;
564 unsigned int reserved[3]; 563 unsigned int reserved[3];
565 }; 564 };
566 565
567 struct microcode { 566 struct microcode {
568 struct microcode_header hdr; 567 struct microcode_header hdr;
569 unsigned int bits[0]; 568 unsigned int bits[0];
570 }; 569 };
571 570
572 typedef struct microcode microcode_t; 571 typedef struct microcode microcode_t;
573 typedef struct microcode_header microcode_header_t; 572 typedef struct microcode_header microcode_header_t;
574 573
575 /* microcode format is extended from prescott processors */ 574 /* microcode format is extended from prescott processors */
576 struct extended_signature { 575 struct extended_signature {
577 unsigned int sig; 576 unsigned int sig;
578 unsigned int pf; 577 unsigned int pf;
579 unsigned int cksum; 578 unsigned int cksum;
580 }; 579 };
581 580
582 struct extended_sigtable { 581 struct extended_sigtable {
583 unsigned int count; 582 unsigned int count;
584 unsigned int cksum; 583 unsigned int cksum;
585 unsigned int reserved[3]; 584 unsigned int reserved[3];
586 struct extended_signature sigs[0]; 585 struct extended_signature sigs[0];
587 }; 586 };
588 /* '6' because it used to be for P6 only (but now covers Pentium 4 as well) */ 587 /* '6' because it used to be for P6 only (but now covers Pentium 4 as well) */
589 #define MICROCODE_IOCFREE _IO('6',0) 588 #define MICROCODE_IOCFREE _IO('6',0)
590 589
591 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */ 590 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
592 static inline void rep_nop(void) 591 static inline void rep_nop(void)
593 { 592 {
594 __asm__ __volatile__("rep;nop": : :"memory"); 593 __asm__ __volatile__("rep;nop": : :"memory");
595 } 594 }
596 595
597 #define cpu_relax() rep_nop() 596 #define cpu_relax() rep_nop()
598 597
599 /* generic versions from gas */ 598 /* generic versions from gas */
600 #define GENERIC_NOP1 ".byte 0x90\n" 599 #define GENERIC_NOP1 ".byte 0x90\n"
601 #define GENERIC_NOP2 ".byte 0x89,0xf6\n" 600 #define GENERIC_NOP2 ".byte 0x89,0xf6\n"
602 #define GENERIC_NOP3 ".byte 0x8d,0x76,0x00\n" 601 #define GENERIC_NOP3 ".byte 0x8d,0x76,0x00\n"
603 #define GENERIC_NOP4 ".byte 0x8d,0x74,0x26,0x00\n" 602 #define GENERIC_NOP4 ".byte 0x8d,0x74,0x26,0x00\n"
604 #define GENERIC_NOP5 GENERIC_NOP1 GENERIC_NOP4 603 #define GENERIC_NOP5 GENERIC_NOP1 GENERIC_NOP4
605 #define GENERIC_NOP6 ".byte 0x8d,0xb6,0x00,0x00,0x00,0x00\n" 604 #define GENERIC_NOP6 ".byte 0x8d,0xb6,0x00,0x00,0x00,0x00\n"
606 #define GENERIC_NOP7 ".byte 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00\n" 605 #define GENERIC_NOP7 ".byte 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00\n"
607 #define GENERIC_NOP8 GENERIC_NOP1 GENERIC_NOP7 606 #define GENERIC_NOP8 GENERIC_NOP1 GENERIC_NOP7
608 607
609 /* Opteron nops */ 608 /* Opteron nops */
610 #define K8_NOP1 GENERIC_NOP1 609 #define K8_NOP1 GENERIC_NOP1
611 #define K8_NOP2 ".byte 0x66,0x90\n" 610 #define K8_NOP2 ".byte 0x66,0x90\n"
612 #define K8_NOP3 ".byte 0x66,0x66,0x90\n" 611 #define K8_NOP3 ".byte 0x66,0x66,0x90\n"
613 #define K8_NOP4 ".byte 0x66,0x66,0x66,0x90\n" 612 #define K8_NOP4 ".byte 0x66,0x66,0x66,0x90\n"
614 #define K8_NOP5 K8_NOP3 K8_NOP2 613 #define K8_NOP5 K8_NOP3 K8_NOP2
615 #define K8_NOP6 K8_NOP3 K8_NOP3 614 #define K8_NOP6 K8_NOP3 K8_NOP3
616 #define K8_NOP7 K8_NOP4 K8_NOP3 615 #define K8_NOP7 K8_NOP4 K8_NOP3
617 #define K8_NOP8 K8_NOP4 K8_NOP4 616 #define K8_NOP8 K8_NOP4 K8_NOP4
618 617
619 /* K7 nops */ 618 /* K7 nops */
620 /* uses eax dependencies (arbitary choice) */ 619 /* uses eax dependencies (arbitary choice) */
621 #define K7_NOP1 GENERIC_NOP1 620 #define K7_NOP1 GENERIC_NOP1
622 #define K7_NOP2 ".byte 0x8b,0xc0\n" 621 #define K7_NOP2 ".byte 0x8b,0xc0\n"
623 #define K7_NOP3 ".byte 0x8d,0x04,0x20\n" 622 #define K7_NOP3 ".byte 0x8d,0x04,0x20\n"
624 #define K7_NOP4 ".byte 0x8d,0x44,0x20,0x00\n" 623 #define K7_NOP4 ".byte 0x8d,0x44,0x20,0x00\n"
625 #define K7_NOP5 K7_NOP4 ASM_NOP1 624 #define K7_NOP5 K7_NOP4 ASM_NOP1
626 #define K7_NOP6 ".byte 0x8d,0x80,0,0,0,0\n" 625 #define K7_NOP6 ".byte 0x8d,0x80,0,0,0,0\n"
627 #define K7_NOP7 ".byte 0x8D,0x04,0x05,0,0,0,0\n" 626 #define K7_NOP7 ".byte 0x8D,0x04,0x05,0,0,0,0\n"
628 #define K7_NOP8 K7_NOP7 ASM_NOP1 627 #define K7_NOP8 K7_NOP7 ASM_NOP1
629 628
630 #ifdef CONFIG_MK8 629 #ifdef CONFIG_MK8
631 #define ASM_NOP1 K8_NOP1 630 #define ASM_NOP1 K8_NOP1
632 #define ASM_NOP2 K8_NOP2 631 #define ASM_NOP2 K8_NOP2
633 #define ASM_NOP3 K8_NOP3 632 #define ASM_NOP3 K8_NOP3
634 #define ASM_NOP4 K8_NOP4 633 #define ASM_NOP4 K8_NOP4
635 #define ASM_NOP5 K8_NOP5 634 #define ASM_NOP5 K8_NOP5
636 #define ASM_NOP6 K8_NOP6 635 #define ASM_NOP6 K8_NOP6
637 #define ASM_NOP7 K8_NOP7 636 #define ASM_NOP7 K8_NOP7
638 #define ASM_NOP8 K8_NOP8 637 #define ASM_NOP8 K8_NOP8
639 #elif defined(CONFIG_MK7) 638 #elif defined(CONFIG_MK7)
640 #define ASM_NOP1 K7_NOP1 639 #define ASM_NOP1 K7_NOP1
641 #define ASM_NOP2 K7_NOP2 640 #define ASM_NOP2 K7_NOP2
642 #define ASM_NOP3 K7_NOP3 641 #define ASM_NOP3 K7_NOP3
643 #define ASM_NOP4 K7_NOP4 642 #define ASM_NOP4 K7_NOP4
644 #define ASM_NOP5 K7_NOP5 643 #define ASM_NOP5 K7_NOP5
645 #define ASM_NOP6 K7_NOP6 644 #define ASM_NOP6 K7_NOP6
646 #define ASM_NOP7 K7_NOP7 645 #define ASM_NOP7 K7_NOP7
647 #define ASM_NOP8 K7_NOP8 646 #define ASM_NOP8 K7_NOP8
648 #else 647 #else
649 #define ASM_NOP1 GENERIC_NOP1 648 #define ASM_NOP1 GENERIC_NOP1
650 #define ASM_NOP2 GENERIC_NOP2 649 #define ASM_NOP2 GENERIC_NOP2
651 #define ASM_NOP3 GENERIC_NOP3 650 #define ASM_NOP3 GENERIC_NOP3
652 #define ASM_NOP4 GENERIC_NOP4 651 #define ASM_NOP4 GENERIC_NOP4
653 #define ASM_NOP5 GENERIC_NOP5 652 #define ASM_NOP5 GENERIC_NOP5
654 #define ASM_NOP6 GENERIC_NOP6 653 #define ASM_NOP6 GENERIC_NOP6
655 #define ASM_NOP7 GENERIC_NOP7 654 #define ASM_NOP7 GENERIC_NOP7
656 #define ASM_NOP8 GENERIC_NOP8 655 #define ASM_NOP8 GENERIC_NOP8
657 #endif 656 #endif
658 657
659 #define ASM_NOP_MAX 8 658 #define ASM_NOP_MAX 8
660 659
661 /* Prefetch instructions for Pentium III and AMD Athlon */ 660 /* Prefetch instructions for Pentium III and AMD Athlon */
662 /* It's not worth to care about 3dnow! prefetches for the K6 661 /* It's not worth to care about 3dnow! prefetches for the K6
663 because they are microcoded there and very slow. 662 because they are microcoded there and very slow.
664 However we don't do prefetches for pre XP Athlons currently 663 However we don't do prefetches for pre XP Athlons currently
665 That should be fixed. */ 664 That should be fixed. */
666 #define ARCH_HAS_PREFETCH 665 #define ARCH_HAS_PREFETCH
667 extern inline void prefetch(const void *x) 666 extern inline void prefetch(const void *x)
668 { 667 {
669 alternative_input(ASM_NOP4, 668 alternative_input(ASM_NOP4,
670 "prefetchnta (%1)", 669 "prefetchnta (%1)",
671 X86_FEATURE_XMM, 670 X86_FEATURE_XMM,
672 "r" (x)); 671 "r" (x));
673 } 672 }
674 673
675 #define ARCH_HAS_PREFETCH 674 #define ARCH_HAS_PREFETCH
676 #define ARCH_HAS_PREFETCHW 675 #define ARCH_HAS_PREFETCHW
677 #define ARCH_HAS_SPINLOCK_PREFETCH 676 #define ARCH_HAS_SPINLOCK_PREFETCH
678 677
679 /* 3dnow! prefetch to get an exclusive cache line. Useful for 678 /* 3dnow! prefetch to get an exclusive cache line. Useful for
680 spinlocks to avoid one state transition in the cache coherency protocol. */ 679 spinlocks to avoid one state transition in the cache coherency protocol. */
681 extern inline void prefetchw(const void *x) 680 extern inline void prefetchw(const void *x)
682 { 681 {
683 alternative_input(ASM_NOP4, 682 alternative_input(ASM_NOP4,
684 "prefetchw (%1)", 683 "prefetchw (%1)",
685 X86_FEATURE_3DNOW, 684 X86_FEATURE_3DNOW,
686 "r" (x)); 685 "r" (x));
687 } 686 }
688 #define spin_lock_prefetch(x) prefetchw(x) 687 #define spin_lock_prefetch(x) prefetchw(x)
689 688
690 extern void select_idle_routine(const struct cpuinfo_x86 *c); 689 extern void select_idle_routine(const struct cpuinfo_x86 *c);
691 690
692 #define cache_line_size() (boot_cpu_data.x86_cache_alignment) 691 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
693 692
694 extern unsigned long boot_option_idle_override; 693 extern unsigned long boot_option_idle_override;
695 extern void enable_sep_cpu(void); 694 extern void enable_sep_cpu(void);
696 extern int sysenter_setup(void); 695 extern int sysenter_setup(void);
697 696
698 #ifdef CONFIG_MTRR 697 #ifdef CONFIG_MTRR
699 extern void mtrr_ap_init(void); 698 extern void mtrr_ap_init(void);
700 extern void mtrr_bp_init(void); 699 extern void mtrr_bp_init(void);
701 #else 700 #else
702 #define mtrr_ap_init() do {} while (0) 701 #define mtrr_ap_init() do {} while (0)
703 #define mtrr_bp_init() do {} while (0) 702 #define mtrr_bp_init() do {} while (0)
704 #endif 703 #endif
705 704
706 #endif /* __ASM_I386_PROCESSOR_H */ 705 #endif /* __ASM_I386_PROCESSOR_H */
707 706