Eric Lee / linux-smarc-t335x-v3.2

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Commit 57abae34c8ec0b6d86a66ea2d53589b2564a70d5

Authored by Vaibhav Bedia
1 parent 90c0ebd772
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arm:omap:am335x: Add cpuidle related board data 

Add board specific cpuidle hookup for AM335x EVM

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>

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arch/arm/mach-omap2/board-am335xevm.c
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1 /* 1 /*
2 * Code for AM335X EVM. 2 * Code for AM335X EVM.
3 * 3 *
4 * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/ 4 * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
5 * 5 *
6 * This program is free software; you can redistribute it and/or 6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as 7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2. 8 * published by the Free Software Foundation version 2.
9 * 9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty 11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details. 13 * GNU General Public License for more details.
14 */ 14 */
15 #include <linux/kernel.h> 15 #include <linux/kernel.h>
16 #include <linux/init.h> 16 #include <linux/init.h>
17 #include <linux/i2c.h> 17 #include <linux/i2c.h>
18 #include <linux/i2c/at24.h> 18 #include <linux/i2c/at24.h>
19 #include <linux/phy.h> 19 #include <linux/phy.h>
20 #include <linux/gpio.h> 20 #include <linux/gpio.h>
21 #include <linux/spi/spi.h> 21 #include <linux/spi/spi.h>
22 #include <linux/spi/flash.h> 22 #include <linux/spi/flash.h>
23 #ifdef CONFIG_KEYBOARD_GPIO 23 #ifdef CONFIG_KEYBOARD_GPIO
24 #include <linux/gpio_keys.h> 24 #include <linux/gpio_keys.h>
25 #endif 25 #endif
26 #ifdef CONFIG_KEYBOARD_MATRIX 26 #ifdef CONFIG_KEYBOARD_MATRIX
27 #include <linux/input.h> 27 #include <linux/input.h>
28 #include <linux/input/matrix_keypad.h> 28 #include <linux/input/matrix_keypad.h>
29 #endif 29 #endif
30 #include <linux/mtd/mtd.h> 30 #include <linux/mtd/mtd.h>
31 #include <linux/mtd/nand.h> 31 #include <linux/mtd/nand.h>
32 #include <linux/mtd/partitions.h> 32 #include <linux/mtd/partitions.h>
33 #include <linux/platform_device.h> 33 #include <linux/platform_device.h>
34 #include <linux/clk.h> 34 #include <linux/clk.h>
35 #include <linux/err.h> 35 #include <linux/err.h>
36 #include <linux/wl12xx.h> 36 #include <linux/wl12xx.h>
37 #include <linux/ethtool.h> 37 #include <linux/ethtool.h>
38 #include <linux/mfd/tps65910.h> 38 #include <linux/mfd/tps65910.h>
39 39
40 /* LCD controller is similar to DA850 */ 40 /* LCD controller is similar to DA850 */
41 #include <video/da8xx-fb.h> 41 #include <video/da8xx-fb.h>
42 42
43 #include <mach/hardware.h> 43 #include <mach/hardware.h>
44 #include <mach/board-am335xevm.h> 44 #include <mach/board-am335xevm.h>
45 45
46 #include <asm/mach-types.h> 46 #include <asm/mach-types.h>
47 #include <asm/mach/arch.h> 47 #include <asm/mach/arch.h>
48 #include <asm/mach/map.h> 48 #include <asm/mach/map.h>
49 #include <asm/hardware/asp.h> 49 #include <asm/hardware/asp.h>
50 50
51 #include <plat/irqs.h> 51 #include <plat/irqs.h>
52 #include <plat/board.h> 52 #include <plat/board.h>
53 #include <plat/common.h> 53 #include <plat/common.h>
54 #include <plat/lcdc.h> 54 #include <plat/lcdc.h>
55 #include <plat/usb.h> 55 #include <plat/usb.h>
56 #include <plat/mmc.h> 56 #include <plat/mmc.h>
57 57
58 #include "board-flash.h" 58 #include "board-flash.h"
59 #include "cpuidle33xx.h"
59 #include "mux.h" 60 #include "mux.h"
60 #include "devices.h" 61 #include "devices.h"
61 #include "hsmmc.h" 62 #include "hsmmc.h"
62 63
63 /* TLK PHY IDs */ 64 /* TLK PHY IDs */
64 #define TLK110_PHY_ID 0x2000A201 65 #define TLK110_PHY_ID 0x2000A201
65 #define TLK110_PHY_MASK 0xfffffff0 66 #define TLK110_PHY_MASK 0xfffffff0
66 67
67 /* BBB PHY IDs */ 68 /* BBB PHY IDs */
68 #define BBB_PHY_ID 0x7c0f1 69 #define BBB_PHY_ID 0x7c0f1
69 #define BBB_PHY_MASK 0xfffffffe 70 #define BBB_PHY_MASK 0xfffffffe
70 71
71 /* TLK110 PHY register offsets */ 72 /* TLK110 PHY register offsets */
72 #define TLK110_COARSEGAIN_REG 0x00A3 73 #define TLK110_COARSEGAIN_REG 0x00A3
73 #define TLK110_LPFHPF_REG 0x00AC 74 #define TLK110_LPFHPF_REG 0x00AC
74 #define TLK110_SPAREANALOG_REG 0x00B9 75 #define TLK110_SPAREANALOG_REG 0x00B9
75 #define TLK110_VRCR_REG 0x00D0 76 #define TLK110_VRCR_REG 0x00D0
76 #define TLK110_SETFFE_REG 0x0107 77 #define TLK110_SETFFE_REG 0x0107
77 #define TLK110_FTSP_REG 0x0154 78 #define TLK110_FTSP_REG 0x0154
78 #define TLK110_ALFATPIDL_REG 0x002A 79 #define TLK110_ALFATPIDL_REG 0x002A
79 #define TLK110_PSCOEF21_REG 0x0096 80 #define TLK110_PSCOEF21_REG 0x0096
80 #define TLK110_PSCOEF3_REG 0x0097 81 #define TLK110_PSCOEF3_REG 0x0097
81 #define TLK110_ALFAFACTOR1_REG 0x002C 82 #define TLK110_ALFAFACTOR1_REG 0x002C
82 #define TLK110_ALFAFACTOR2_REG 0x0023 83 #define TLK110_ALFAFACTOR2_REG 0x0023
83 #define TLK110_CFGPS_REG 0x0095 84 #define TLK110_CFGPS_REG 0x0095
84 #define TLK110_FTSPTXGAIN_REG 0x0150 85 #define TLK110_FTSPTXGAIN_REG 0x0150
85 #define TLK110_SWSCR3_REG 0x000B 86 #define TLK110_SWSCR3_REG 0x000B
86 #define TLK110_SCFALLBACK_REG 0x0040 87 #define TLK110_SCFALLBACK_REG 0x0040
87 #define TLK110_PHYRCR_REG 0x001F 88 #define TLK110_PHYRCR_REG 0x001F
88 89
89 /* TLK110 register writes values */ 90 /* TLK110 register writes values */
90 #define TLK110_COARSEGAIN_VAL 0x0000 91 #define TLK110_COARSEGAIN_VAL 0x0000
91 #define TLK110_LPFHPF_VAL 0x8000 92 #define TLK110_LPFHPF_VAL 0x8000
92 #define TLK110_SPANALOG_VAL 0x0000 93 #define TLK110_SPANALOG_VAL 0x0000
93 #define TLK110_VRCR_VAL 0x0008 94 #define TLK110_VRCR_VAL 0x0008
94 #define TLK110_SETFFE_VAL 0x0605 95 #define TLK110_SETFFE_VAL 0x0605
95 #define TLK110_FTSP_VAL 0x0255 96 #define TLK110_FTSP_VAL 0x0255
96 #define TLK110_ALFATPIDL_VAL 0x7998 97 #define TLK110_ALFATPIDL_VAL 0x7998
97 #define TLK110_PSCOEF21_VAL 0x3A20 98 #define TLK110_PSCOEF21_VAL 0x3A20
98 #define TLK110_PSCOEF3_VAL 0x003F 99 #define TLK110_PSCOEF3_VAL 0x003F
99 #define TLK110_ALFACTOR1_VAL 0xFF80 100 #define TLK110_ALFACTOR1_VAL 0xFF80
100 #define TLK110_ALFACTOR2_VAL 0x021C 101 #define TLK110_ALFACTOR2_VAL 0x021C
101 #define TLK110_CFGPS_VAL 0x0000 102 #define TLK110_CFGPS_VAL 0x0000
102 #define TLK110_FTSPTXGAIN_VAL 0x6A88 103 #define TLK110_FTSPTXGAIN_VAL 0x6A88
103 #define TLK110_SWSCR3_VAL 0x0000 104 #define TLK110_SWSCR3_VAL 0x0000
104 #define TLK110_SCFALLBACK_VAL 0xC11D 105 #define TLK110_SCFALLBACK_VAL 0xC11D
105 #define TLK110_PHYRCR_VAL 0x4000 106 #define TLK110_PHYRCR_VAL 0x4000
106 107
107 #ifdef CONFIG_TLK110_WORKAROUND 108 #ifdef CONFIG_TLK110_WORKAROUND
108 #define am335x_tlk110_phy_init()\ 109 #define am335x_tlk110_phy_init()\
109 do { \ 110 do { \
110 phy_register_fixup_for_uid(TLK110_PHY_ID,\ 111 phy_register_fixup_for_uid(TLK110_PHY_ID,\
111 TLK110_PHY_MASK,\ 112 TLK110_PHY_MASK,\
112 am335x_tlk110_phy_fixup);\ 113 am335x_tlk110_phy_fixup);\
113 } while (0); 114 } while (0);
114 #else 115 #else
115 #define am335x_tlk110_phy_init() do { } while (0); 116 #define am335x_tlk110_phy_init() do { } while (0);
116 #endif 117 #endif
117 118
118 /* Convert GPIO signal to GPIO pin number */ 119 /* Convert GPIO signal to GPIO pin number */
119 #define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio)) 120 #define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
120 121
121 static const struct display_panel disp_panel = { 122 static const struct display_panel disp_panel = {
122 WVGA, 123 WVGA,
123 32, 124 32,
124 32, 125 32,
125 COLOR_ACTIVE, 126 COLOR_ACTIVE,
126 }; 127 };
127 128
128 static struct lcd_ctrl_config lcd_cfg = { 129 static struct lcd_ctrl_config lcd_cfg = {
129 &disp_panel, 130 &disp_panel,
130 .ac_bias = 255, 131 .ac_bias = 255,
131 .ac_bias_intrpt = 0, 132 .ac_bias_intrpt = 0,
132 .dma_burst_sz = 16, 133 .dma_burst_sz = 16,
133 .bpp = 32, 134 .bpp = 32,
134 .fdd = 0x80, 135 .fdd = 0x80,
135 .tft_alt_mode = 0, 136 .tft_alt_mode = 0,
136 .stn_565_mode = 0, 137 .stn_565_mode = 0,
137 .mono_8bit_mode = 0, 138 .mono_8bit_mode = 0,
138 .invert_line_clock = 1, 139 .invert_line_clock = 1,
139 .invert_frm_clock = 1, 140 .invert_frm_clock = 1,
140 .sync_edge = 0, 141 .sync_edge = 0,
141 .sync_ctrl = 1, 142 .sync_ctrl = 1,
142 .raster_order = 0, 143 .raster_order = 0,
143 }; 144 };
144 145
145 struct da8xx_lcdc_platform_data TFC_S9700RTWV35TR_01B_pdata = { 146 struct da8xx_lcdc_platform_data TFC_S9700RTWV35TR_01B_pdata = {
146 .manu_name = "ThreeFive", 147 .manu_name = "ThreeFive",
147 .controller_data = &lcd_cfg, 148 .controller_data = &lcd_cfg,
148 .type = "TFC_S9700RTWV35TR_01B", 149 .type = "TFC_S9700RTWV35TR_01B",
149 }; 150 };
150 151
151 /* TSc controller */ 152 /* TSc controller */
152 #include <linux/input/ti_tscadc.h> 153 #include <linux/input/ti_tscadc.h>
153 #include <linux/lis3lv02d.h> 154 #include <linux/lis3lv02d.h>
154 155
155 static struct resource tsc_resources[] = { 156 static struct resource tsc_resources[] = {
156 [0] = { 157 [0] = {
157 .start = AM33XX_TSC_BASE, 158 .start = AM33XX_TSC_BASE,
158 .end = AM33XX_TSC_BASE + SZ_8K - 1, 159 .end = AM33XX_TSC_BASE + SZ_8K - 1,
159 .flags = IORESOURCE_MEM, 160 .flags = IORESOURCE_MEM,
160 }, 161 },
161 [1] = { 162 [1] = {
162 .start = AM33XX_IRQ_ADC_GEN, 163 .start = AM33XX_IRQ_ADC_GEN,
163 .end = AM33XX_IRQ_ADC_GEN, 164 .end = AM33XX_IRQ_ADC_GEN,
164 .flags = IORESOURCE_IRQ, 165 .flags = IORESOURCE_IRQ,
165 }, 166 },
166 }; 167 };
167 168
168 static struct tsc_data am335x_touchscreen_data = { 169 static struct tsc_data am335x_touchscreen_data = {
169 .wires = 4, 170 .wires = 4,
170 .x_plate_resistance = 200, 171 .x_plate_resistance = 200,
171 }; 172 };
172 173
173 static struct platform_device tsc_device = { 174 static struct platform_device tsc_device = {
174 .name = "tsc", 175 .name = "tsc",
175 .id = -1, 176 .id = -1,
176 .dev = { 177 .dev = {
177 .platform_data = &am335x_touchscreen_data, 178 .platform_data = &am335x_touchscreen_data,
178 }, 179 },
179 .num_resources = ARRAY_SIZE(tsc_resources), 180 .num_resources = ARRAY_SIZE(tsc_resources),
180 .resource = tsc_resources, 181 .resource = tsc_resources,
181 }; 182 };
182 183
183 static u8 am335x_iis_serializer_direction1[] = { 184 static u8 am335x_iis_serializer_direction1[] = {
184 INACTIVE_MODE, INACTIVE_MODE, TX_MODE, RX_MODE, 185 INACTIVE_MODE, INACTIVE_MODE, TX_MODE, RX_MODE,
185 INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, 186 INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
186 INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, 187 INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
187 INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, 188 INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
188 }; 189 };
189 190
190 static struct snd_platform_data am335x_evm_snd_data1 = { 191 static struct snd_platform_data am335x_evm_snd_data1 = {
191 .tx_dma_offset = 0x46400000, /* McASP1 */ 192 .tx_dma_offset = 0x46400000, /* McASP1 */
192 .rx_dma_offset = 0x46400000, 193 .rx_dma_offset = 0x46400000,
193 .op_mode = DAVINCI_MCASP_IIS_MODE, 194 .op_mode = DAVINCI_MCASP_IIS_MODE,
194 .num_serializer = ARRAY_SIZE(am335x_iis_serializer_direction1), 195 .num_serializer = ARRAY_SIZE(am335x_iis_serializer_direction1),
195 .tdm_slots = 2, 196 .tdm_slots = 2,
196 .serial_dir = am335x_iis_serializer_direction1, 197 .serial_dir = am335x_iis_serializer_direction1,
197 .asp_chan_q = EVENTQ_2, 198 .asp_chan_q = EVENTQ_2,
198 .version = MCASP_VERSION_3, 199 .version = MCASP_VERSION_3,
199 .txnumevt = 1, 200 .txnumevt = 1,
200 .rxnumevt = 1, 201 .rxnumevt = 1,
201 }; 202 };
202 203
203 static struct omap2_hsmmc_info am335x_mmc[] __initdata = { 204 static struct omap2_hsmmc_info am335x_mmc[] __initdata = {
204 { 205 {
205 .mmc = 1, 206 .mmc = 1,
206 .caps = MMC_CAP_4_BIT_DATA, 207 .caps = MMC_CAP_4_BIT_DATA,
207 .gpio_cd = GPIO_TO_PIN(0, 6), 208 .gpio_cd = GPIO_TO_PIN(0, 6),
208 .gpio_wp = GPIO_TO_PIN(3, 18), 209 .gpio_wp = GPIO_TO_PIN(3, 18),
209 .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, /* 3V3 */ 210 .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, /* 3V3 */
210 }, 211 },
211 { 212 {
212 .mmc = 0, /* will be set at runtime */ 213 .mmc = 0, /* will be set at runtime */
213 }, 214 },
214 { 215 {
215 .mmc = 0, /* will be set at runtime */ 216 .mmc = 0, /* will be set at runtime */
216 }, 217 },
217 {} /* Terminator */ 218 {} /* Terminator */
218 }; 219 };
219 220
220 221
221 #ifdef CONFIG_OMAP_MUX 222 #ifdef CONFIG_OMAP_MUX
222 static struct omap_board_mux board_mux[] __initdata = { 223 static struct omap_board_mux board_mux[] __initdata = {
223 AM33XX_MUX(I2C0_SDA, OMAP_MUX_MODE0 | AM33XX_SLEWCTRL_SLOW | 224 AM33XX_MUX(I2C0_SDA, OMAP_MUX_MODE0 | AM33XX_SLEWCTRL_SLOW |
224 AM33XX_INPUT_EN | AM33XX_PIN_OUTPUT), 225 AM33XX_INPUT_EN | AM33XX_PIN_OUTPUT),
225 AM33XX_MUX(I2C0_SCL, OMAP_MUX_MODE0 | AM33XX_SLEWCTRL_SLOW | 226 AM33XX_MUX(I2C0_SCL, OMAP_MUX_MODE0 | AM33XX_SLEWCTRL_SLOW |
226 AM33XX_INPUT_EN | AM33XX_PIN_OUTPUT), 227 AM33XX_INPUT_EN | AM33XX_PIN_OUTPUT),
227 { .reg_offset = OMAP_MUX_TERMINATOR }, 228 { .reg_offset = OMAP_MUX_TERMINATOR },
228 }; 229 };
229 #else 230 #else
230 #define board_mux NULL 231 #define board_mux NULL
231 #endif 232 #endif
232 233
233 /* module pin mux structure */ 234 /* module pin mux structure */
234 struct pinmux_config { 235 struct pinmux_config {
235 const char *string_name; /* signal name format */ 236 const char *string_name; /* signal name format */
236 int val; /* Options for the mux register value */ 237 int val; /* Options for the mux register value */
237 }; 238 };
238 239
239 struct evm_dev_cfg { 240 struct evm_dev_cfg {
240 void (*device_init)(int evm_id, int profile); 241 void (*device_init)(int evm_id, int profile);
241 242
242 /* 243 /*
243 * If the device is required on both baseboard & daughter board (ex i2c), 244 * If the device is required on both baseboard & daughter board (ex i2c),
244 * specify DEV_ON_BASEBOARD 245 * specify DEV_ON_BASEBOARD
245 */ 246 */
246 #define DEV_ON_BASEBOARD 0 247 #define DEV_ON_BASEBOARD 0
247 #define DEV_ON_DGHTR_BRD 1 248 #define DEV_ON_DGHTR_BRD 1
248 u32 device_on; 249 u32 device_on;
249 250
250 u32 profile; /* Profiles (0-7) in which the module is present */ 251 u32 profile; /* Profiles (0-7) in which the module is present */
251 }; 252 };
252 253
253 /* AM335X - CPLD Register Offsets */ 254 /* AM335X - CPLD Register Offsets */
254 #define CPLD_DEVICE_HDR 0x00 /* CPLD Header */ 255 #define CPLD_DEVICE_HDR 0x00 /* CPLD Header */
255 #define CPLD_DEVICE_ID 0x04 /* CPLD identification */ 256 #define CPLD_DEVICE_ID 0x04 /* CPLD identification */
256 #define CPLD_DEVICE_REV 0x0C /* Revision of the CPLD code */ 257 #define CPLD_DEVICE_REV 0x0C /* Revision of the CPLD code */
257 #define CPLD_CFG_REG 0x10 /* Configuration Register */ 258 #define CPLD_CFG_REG 0x10 /* Configuration Register */
258 259
259 static struct i2c_client *cpld_client; 260 static struct i2c_client *cpld_client;
260 261
261 static u32 am335x_evm_id; 262 static u32 am335x_evm_id;
262 263
263 static struct omap_board_config_kernel am335x_evm_config[] __initdata = { 264 static struct omap_board_config_kernel am335x_evm_config[] __initdata = {
264 }; 265 };
265 266
266 /* 267 /*
267 * EVM Config held in On-Board eeprom device. 268 * EVM Config held in On-Board eeprom device.
268 * 269 *
269 * Header Format 270 * Header Format
270 * 271 *
271 * Name Size Contents 272 * Name Size Contents
272 * (Bytes) 273 * (Bytes)
273 *------------------------------------------------------------- 274 *-------------------------------------------------------------
274 * Header 4 0xAA, 0x55, 0x33, 0xEE 275 * Header 4 0xAA, 0x55, 0x33, 0xEE
275 * 276 *
276 * Board Name 8 Name for board in ASCII. 277 * Board Name 8 Name for board in ASCII.
277 * example "A33515BB" = "AM335X 278 * example "A33515BB" = "AM335X
278 Low Cost EVM board" 279 Low Cost EVM board"
279 * 280 *
280 * Version 4 Hardware version code for board in 281 * Version 4 Hardware version code for board in
281 * in ASCII. "1.0A" = rev.01.0A 282 * in ASCII. "1.0A" = rev.01.0A
282 * 283 *
283 * Serial Number 12 Serial number of the board. This is a 12 284 * Serial Number 12 Serial number of the board. This is a 12
284 * character string which is WWYY4P16nnnn, where 285 * character string which is WWYY4P16nnnn, where
285 * WW = 2 digit week of the year of production 286 * WW = 2 digit week of the year of production
286 * YY = 2 digit year of production 287 * YY = 2 digit year of production
287 * nnnn = incrementing board number 288 * nnnn = incrementing board number
288 * 289 *
289 * Configuration option 32 Codes(TBD) to show the configuration 290 * Configuration option 32 Codes(TBD) to show the configuration
290 * setup on this board. 291 * setup on this board.
291 * 292 *
292 * Available 32720 Available space for other non-volatile 293 * Available 32720 Available space for other non-volatile
293 * data. 294 * data.
294 */ 295 */
295 struct am335x_evm_eeprom_config { 296 struct am335x_evm_eeprom_config {
296 u32 header; 297 u32 header;
297 u8 name[8]; 298 u8 name[8];
298 char version[4]; 299 char version[4];
299 u8 serial[12]; 300 u8 serial[12];
300 u8 opt[32]; 301 u8 opt[32];
301 }; 302 };
302 303
303 static struct am335x_evm_eeprom_config config; 304 static struct am335x_evm_eeprom_config config;
304 static bool daughter_brd_detected; 305 static bool daughter_brd_detected;
305 306
306 #define GP_EVM_REV_IS_1_0 0x1 307 #define GP_EVM_REV_IS_1_0 0x1
307 #define GP_EVM_REV_IS_1_1A 0x2 308 #define GP_EVM_REV_IS_1_1A 0x2
308 #define GP_EVM_REV_IS_UNKNOWN 0xFF 309 #define GP_EVM_REV_IS_UNKNOWN 0xFF
309 static unsigned int gp_evm_revision = GP_EVM_REV_IS_UNKNOWN; 310 static unsigned int gp_evm_revision = GP_EVM_REV_IS_UNKNOWN;
310 unsigned int gigabit_enable = 1; 311 unsigned int gigabit_enable = 1;
311 312
312 #define EEPROM_MAC_ADDRESS_OFFSET 60 /* 4+8+4+12+32 */ 313 #define EEPROM_MAC_ADDRESS_OFFSET 60 /* 4+8+4+12+32 */
313 #define EEPROM_NO_OF_MAC_ADDR 3 314 #define EEPROM_NO_OF_MAC_ADDR 3
314 static char am335x_mac_addr[EEPROM_NO_OF_MAC_ADDR][ETH_ALEN]; 315 static char am335x_mac_addr[EEPROM_NO_OF_MAC_ADDR][ETH_ALEN];
315 316
316 #define AM335X_EEPROM_HEADER 0xEE3355AA 317 #define AM335X_EEPROM_HEADER 0xEE3355AA
317 318
318 /* current profile if exists else PROFILE_0 on error */ 319 /* current profile if exists else PROFILE_0 on error */
319 static u32 am335x_get_profile_selection(void) 320 static u32 am335x_get_profile_selection(void)
320 { 321 {
321 int val = 0; 322 int val = 0;
322 323
323 if (!cpld_client) 324 if (!cpld_client)
324 /* error checking is not done in func's calling this routine. 325 /* error checking is not done in func's calling this routine.
325 so return profile 0 on error */ 326 so return profile 0 on error */
326 return 0; 327 return 0;
327 328
328 val = i2c_smbus_read_word_data(cpld_client, CPLD_CFG_REG); 329 val = i2c_smbus_read_word_data(cpld_client, CPLD_CFG_REG);
329 if (val < 0) 330 if (val < 0)
330 return 0; /* default to Profile 0 on Error */ 331 return 0; /* default to Profile 0 on Error */
331 else 332 else
332 return val & 0x7; 333 return val & 0x7;
333 } 334 }
334 335
335 /* Module pin mux for LCDC */ 336 /* Module pin mux for LCDC */
336 static struct pinmux_config lcdc_pin_mux[] = { 337 static struct pinmux_config lcdc_pin_mux[] = {
337 {"lcd_data0.lcd_data0", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT 338 {"lcd_data0.lcd_data0", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
338 | AM33XX_PULL_DISA}, 339 | AM33XX_PULL_DISA},
339 {"lcd_data1.lcd_data1", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT 340 {"lcd_data1.lcd_data1", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
340 | AM33XX_PULL_DISA}, 341 | AM33XX_PULL_DISA},
341 {"lcd_data2.lcd_data2", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT 342 {"lcd_data2.lcd_data2", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
342 | AM33XX_PULL_DISA}, 343 | AM33XX_PULL_DISA},
343 {"lcd_data3.lcd_data3", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT 344 {"lcd_data3.lcd_data3", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
344 | AM33XX_PULL_DISA}, 345 | AM33XX_PULL_DISA},
345 {"lcd_data4.lcd_data4", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT 346 {"lcd_data4.lcd_data4", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
346 | AM33XX_PULL_DISA}, 347 | AM33XX_PULL_DISA},
347 {"lcd_data5.lcd_data5", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT 348 {"lcd_data5.lcd_data5", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
348 | AM33XX_PULL_DISA}, 349 | AM33XX_PULL_DISA},
349 {"lcd_data6.lcd_data6", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT 350 {"lcd_data6.lcd_data6", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
350 | AM33XX_PULL_DISA}, 351 | AM33XX_PULL_DISA},
351 {"lcd_data7.lcd_data7", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT 352 {"lcd_data7.lcd_data7", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
352 | AM33XX_PULL_DISA}, 353 | AM33XX_PULL_DISA},
353 {"lcd_data8.lcd_data8", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT 354 {"lcd_data8.lcd_data8", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
354 | AM33XX_PULL_DISA}, 355 | AM33XX_PULL_DISA},
355 {"lcd_data9.lcd_data9", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT 356 {"lcd_data9.lcd_data9", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
356 | AM33XX_PULL_DISA}, 357 | AM33XX_PULL_DISA},
357 {"lcd_data10.lcd_data10", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT 358 {"lcd_data10.lcd_data10", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
358 | AM33XX_PULL_DISA}, 359 | AM33XX_PULL_DISA},
359 {"lcd_data11.lcd_data11", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT 360 {"lcd_data11.lcd_data11", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
360 | AM33XX_PULL_DISA}, 361 | AM33XX_PULL_DISA},
361 {"lcd_data12.lcd_data12", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT 362 {"lcd_data12.lcd_data12", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
362 | AM33XX_PULL_DISA}, 363 | AM33XX_PULL_DISA},
363 {"lcd_data13.lcd_data13", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT 364 {"lcd_data13.lcd_data13", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
364 | AM33XX_PULL_DISA}, 365 | AM33XX_PULL_DISA},
365 {"lcd_data14.lcd_data14", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT 366 {"lcd_data14.lcd_data14", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
366 | AM33XX_PULL_DISA}, 367 | AM33XX_PULL_DISA},
367 {"lcd_data15.lcd_data15", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT 368 {"lcd_data15.lcd_data15", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
368 | AM33XX_PULL_DISA}, 369 | AM33XX_PULL_DISA},
369 {"gpmc_ad8.lcd_data16", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT}, 370 {"gpmc_ad8.lcd_data16", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
370 {"gpmc_ad9.lcd_data17", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT}, 371 {"gpmc_ad9.lcd_data17", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
371 {"gpmc_ad10.lcd_data18", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT}, 372 {"gpmc_ad10.lcd_data18", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
372 {"gpmc_ad11.lcd_data19", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT}, 373 {"gpmc_ad11.lcd_data19", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
373 {"gpmc_ad12.lcd_data20", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT}, 374 {"gpmc_ad12.lcd_data20", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
374 {"gpmc_ad13.lcd_data21", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT}, 375 {"gpmc_ad13.lcd_data21", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
375 {"gpmc_ad14.lcd_data22", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT}, 376 {"gpmc_ad14.lcd_data22", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
376 {"gpmc_ad15.lcd_data23", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT}, 377 {"gpmc_ad15.lcd_data23", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
377 {"lcd_vsync.lcd_vsync", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, 378 {"lcd_vsync.lcd_vsync", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
378 {"lcd_hsync.lcd_hsync", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, 379 {"lcd_hsync.lcd_hsync", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
379 {"lcd_pclk.lcd_pclk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, 380 {"lcd_pclk.lcd_pclk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
380 {"lcd_ac_bias_en.lcd_ac_bias_en", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, 381 {"lcd_ac_bias_en.lcd_ac_bias_en", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
381 {NULL, 0}, 382 {NULL, 0},
382 }; 383 };
383 384
384 static struct pinmux_config tsc_pin_mux[] = { 385 static struct pinmux_config tsc_pin_mux[] = {
385 {"ain0.ain0", OMAP_MUX_MODE0 | AM33XX_INPUT_EN}, 386 {"ain0.ain0", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
386 {"ain1.ain1", OMAP_MUX_MODE0 | AM33XX_INPUT_EN}, 387 {"ain1.ain1", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
387 {"ain2.ain2", OMAP_MUX_MODE0 | AM33XX_INPUT_EN}, 388 {"ain2.ain2", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
388 {"ain3.ain3", OMAP_MUX_MODE0 | AM33XX_INPUT_EN}, 389 {"ain3.ain3", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
389 {"vrefp.vrefp", OMAP_MUX_MODE0 | AM33XX_INPUT_EN}, 390 {"vrefp.vrefp", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
390 {"vrefn.vrefn", OMAP_MUX_MODE0 | AM33XX_INPUT_EN}, 391 {"vrefn.vrefn", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
391 {NULL, 0}, 392 {NULL, 0},
392 }; 393 };
393 394
394 /* Pin mux for nand flash module */ 395 /* Pin mux for nand flash module */
395 static struct pinmux_config nand_pin_mux[] = { 396 static struct pinmux_config nand_pin_mux[] = {
396 {"gpmc_ad0.gpmc_ad0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 397 {"gpmc_ad0.gpmc_ad0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
397 {"gpmc_ad1.gpmc_ad1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 398 {"gpmc_ad1.gpmc_ad1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
398 {"gpmc_ad2.gpmc_ad2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 399 {"gpmc_ad2.gpmc_ad2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
399 {"gpmc_ad3.gpmc_ad3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 400 {"gpmc_ad3.gpmc_ad3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
400 {"gpmc_ad4.gpmc_ad4", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 401 {"gpmc_ad4.gpmc_ad4", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
401 {"gpmc_ad5.gpmc_ad5", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 402 {"gpmc_ad5.gpmc_ad5", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
402 {"gpmc_ad6.gpmc_ad6", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 403 {"gpmc_ad6.gpmc_ad6", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
403 {"gpmc_ad7.gpmc_ad7", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 404 {"gpmc_ad7.gpmc_ad7", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
404 {"gpmc_wait0.gpmc_wait0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 405 {"gpmc_wait0.gpmc_wait0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
405 {"gpmc_wpn.gpmc_wpn", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP}, 406 {"gpmc_wpn.gpmc_wpn", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
406 {"gpmc_csn0.gpmc_csn0", OMAP_MUX_MODE0 | AM33XX_PULL_DISA}, 407 {"gpmc_csn0.gpmc_csn0", OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
407 {"gpmc_advn_ale.gpmc_advn_ale", OMAP_MUX_MODE0 | AM33XX_PULL_DISA}, 408 {"gpmc_advn_ale.gpmc_advn_ale", OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
408 {"gpmc_oen_ren.gpmc_oen_ren", OMAP_MUX_MODE0 | AM33XX_PULL_DISA}, 409 {"gpmc_oen_ren.gpmc_oen_ren", OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
409 {"gpmc_wen.gpmc_wen", OMAP_MUX_MODE0 | AM33XX_PULL_DISA}, 410 {"gpmc_wen.gpmc_wen", OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
410 {"gpmc_ben0_cle.gpmc_ben0_cle", OMAP_MUX_MODE0 | AM33XX_PULL_DISA}, 411 {"gpmc_ben0_cle.gpmc_ben0_cle", OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
411 {NULL, 0}, 412 {NULL, 0},
412 }; 413 };
413 414
414 /* Module pin mux for SPI fash */ 415 /* Module pin mux for SPI fash */
415 static struct pinmux_config spi0_pin_mux[] = { 416 static struct pinmux_config spi0_pin_mux[] = {
416 {"spi0_sclk.spi0_sclk", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL 417 {"spi0_sclk.spi0_sclk", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL
417 | AM33XX_INPUT_EN}, 418 | AM33XX_INPUT_EN},
418 {"spi0_d0.spi0_d0", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL | AM33XX_PULL_UP 419 {"spi0_d0.spi0_d0", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL | AM33XX_PULL_UP
419 | AM33XX_INPUT_EN}, 420 | AM33XX_INPUT_EN},
420 {"spi0_d1.spi0_d1", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL 421 {"spi0_d1.spi0_d1", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL
421 | AM33XX_INPUT_EN}, 422 | AM33XX_INPUT_EN},
422 {"spi0_cs0.spi0_cs0", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL | AM33XX_PULL_UP 423 {"spi0_cs0.spi0_cs0", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL | AM33XX_PULL_UP
423 | AM33XX_INPUT_EN}, 424 | AM33XX_INPUT_EN},
424 {NULL, 0}, 425 {NULL, 0},
425 }; 426 };
426 427
427 /* Module pin mux for SPI flash */ 428 /* Module pin mux for SPI flash */
428 static struct pinmux_config spi1_pin_mux[] = { 429 static struct pinmux_config spi1_pin_mux[] = {
429 {"mcasp0_aclkx.spi1_sclk", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL 430 {"mcasp0_aclkx.spi1_sclk", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
430 | AM33XX_INPUT_EN}, 431 | AM33XX_INPUT_EN},
431 {"mcasp0_fsx.spi1_d0", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL 432 {"mcasp0_fsx.spi1_d0", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
432 | AM33XX_PULL_UP | AM33XX_INPUT_EN}, 433 | AM33XX_PULL_UP | AM33XX_INPUT_EN},
433 {"mcasp0_axr0.spi1_d1", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL 434 {"mcasp0_axr0.spi1_d1", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
434 | AM33XX_INPUT_EN}, 435 | AM33XX_INPUT_EN},
435 {"mcasp0_ahclkr.spi1_cs0", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL 436 {"mcasp0_ahclkr.spi1_cs0", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
436 | AM33XX_PULL_UP | AM33XX_INPUT_EN}, 437 | AM33XX_PULL_UP | AM33XX_INPUT_EN},
437 {NULL, 0}, 438 {NULL, 0},
438 }; 439 };
439 440
440 /* Module pin mux for rgmii1 */ 441 /* Module pin mux for rgmii1 */
441 static struct pinmux_config rgmii1_pin_mux[] = { 442 static struct pinmux_config rgmii1_pin_mux[] = {
442 {"mii1_txen.rgmii1_tctl", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, 443 {"mii1_txen.rgmii1_tctl", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
443 {"mii1_rxdv.rgmii1_rctl", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, 444 {"mii1_rxdv.rgmii1_rctl", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
444 {"mii1_txd3.rgmii1_td3", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, 445 {"mii1_txd3.rgmii1_td3", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
445 {"mii1_txd2.rgmii1_td2", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, 446 {"mii1_txd2.rgmii1_td2", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
446 {"mii1_txd1.rgmii1_td1", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, 447 {"mii1_txd1.rgmii1_td1", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
447 {"mii1_txd0.rgmii1_td0", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, 448 {"mii1_txd0.rgmii1_td0", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
448 {"mii1_txclk.rgmii1_tclk", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, 449 {"mii1_txclk.rgmii1_tclk", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
449 {"mii1_rxclk.rgmii1_rclk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, 450 {"mii1_rxclk.rgmii1_rclk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
450 {"mii1_rxd3.rgmii1_rd3", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, 451 {"mii1_rxd3.rgmii1_rd3", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
451 {"mii1_rxd2.rgmii1_rd2", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, 452 {"mii1_rxd2.rgmii1_rd2", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
452 {"mii1_rxd1.rgmii1_rd1", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, 453 {"mii1_rxd1.rgmii1_rd1", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
453 {"mii1_rxd0.rgmii1_rd0", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, 454 {"mii1_rxd0.rgmii1_rd0", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
454 {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 455 {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
455 {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP}, 456 {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
456 {NULL, 0}, 457 {NULL, 0},
457 }; 458 };
458 459
459 /* Module pin mux for rgmii2 */ 460 /* Module pin mux for rgmii2 */
460 static struct pinmux_config rgmii2_pin_mux[] = { 461 static struct pinmux_config rgmii2_pin_mux[] = {
461 {"gpmc_a0.rgmii2_tctl", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, 462 {"gpmc_a0.rgmii2_tctl", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
462 {"gpmc_a1.rgmii2_rctl", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, 463 {"gpmc_a1.rgmii2_rctl", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
463 {"gpmc_a2.rgmii2_td3", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, 464 {"gpmc_a2.rgmii2_td3", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
464 {"gpmc_a3.rgmii2_td2", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, 465 {"gpmc_a3.rgmii2_td2", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
465 {"gpmc_a4.rgmii2_td1", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, 466 {"gpmc_a4.rgmii2_td1", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
466 {"gpmc_a5.rgmii2_td0", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, 467 {"gpmc_a5.rgmii2_td0", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
467 {"gpmc_a6.rgmii2_tclk", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, 468 {"gpmc_a6.rgmii2_tclk", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
468 {"gpmc_a7.rgmii2_rclk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, 469 {"gpmc_a7.rgmii2_rclk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
469 {"gpmc_a8.rgmii2_rd3", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, 470 {"gpmc_a8.rgmii2_rd3", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
470 {"gpmc_a9.rgmii2_rd2", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, 471 {"gpmc_a9.rgmii2_rd2", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
471 {"gpmc_a10.rgmii2_rd1", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, 472 {"gpmc_a10.rgmii2_rd1", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
472 {"gpmc_a11.rgmii2_rd0", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, 473 {"gpmc_a11.rgmii2_rd0", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
473 {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 474 {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
474 {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP}, 475 {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
475 {NULL, 0}, 476 {NULL, 0},
476 }; 477 };
477 478
478 /* Module pin mux for mii1 */ 479 /* Module pin mux for mii1 */
479 static struct pinmux_config mii1_pin_mux[] = { 480 static struct pinmux_config mii1_pin_mux[] = {
480 {"mii1_rxerr.mii1_rxerr", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN}, 481 {"mii1_rxerr.mii1_rxerr", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
481 {"mii1_txen.mii1_txen", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, 482 {"mii1_txen.mii1_txen", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
482 {"mii1_rxdv.mii1_rxdv", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN}, 483 {"mii1_rxdv.mii1_rxdv", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
483 {"mii1_txd3.mii1_txd3", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, 484 {"mii1_txd3.mii1_txd3", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
484 {"mii1_txd2.mii1_txd2", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, 485 {"mii1_txd2.mii1_txd2", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
485 {"mii1_txd1.mii1_txd1", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, 486 {"mii1_txd1.mii1_txd1", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
486 {"mii1_txd0.mii1_txd0", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, 487 {"mii1_txd0.mii1_txd0", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
487 {"mii1_txclk.mii1_txclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN}, 488 {"mii1_txclk.mii1_txclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
488 {"mii1_rxclk.mii1_rxclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN}, 489 {"mii1_rxclk.mii1_rxclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
489 {"mii1_rxd3.mii1_rxd3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN}, 490 {"mii1_rxd3.mii1_rxd3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
490 {"mii1_rxd2.mii1_rxd2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN}, 491 {"mii1_rxd2.mii1_rxd2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
491 {"mii1_rxd1.mii1_rxd1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN}, 492 {"mii1_rxd1.mii1_rxd1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
492 {"mii1_rxd0.mii1_rxd0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN}, 493 {"mii1_rxd0.mii1_rxd0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
493 {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 494 {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
494 {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP}, 495 {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
495 {NULL, 0}, 496 {NULL, 0},
496 }; 497 };
497 498
498 /* Module pin mux for rmii1 */ 499 /* Module pin mux for rmii1 */
499 static struct pinmux_config rmii1_pin_mux[] = { 500 static struct pinmux_config rmii1_pin_mux[] = {
500 {"mii1_crs.rmii1_crs_dv", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN}, 501 {"mii1_crs.rmii1_crs_dv", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
501 {"mii1_rxerr.mii1_rxerr", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN}, 502 {"mii1_rxerr.mii1_rxerr", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
502 {"mii1_txen.mii1_txen", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT}, 503 {"mii1_txen.mii1_txen", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
503 {"mii1_txd1.mii1_txd1", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT}, 504 {"mii1_txd1.mii1_txd1", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
504 {"mii1_txd0.mii1_txd0", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT}, 505 {"mii1_txd0.mii1_txd0", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
505 {"mii1_rxd1.mii1_rxd1", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN}, 506 {"mii1_rxd1.mii1_rxd1", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
506 {"mii1_rxd0.mii1_rxd0", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN}, 507 {"mii1_rxd0.mii1_rxd0", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
507 {"rmii1_refclk.rmii1_refclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN}, 508 {"rmii1_refclk.rmii1_refclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
508 {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 509 {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
509 {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP}, 510 {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
510 {NULL, 0}, 511 {NULL, 0},
511 }; 512 };
512 513
513 static struct pinmux_config i2c1_pin_mux[] = { 514 static struct pinmux_config i2c1_pin_mux[] = {
514 {"spi0_d1.i2c1_sda", OMAP_MUX_MODE2 | AM33XX_SLEWCTRL_SLOW | 515 {"spi0_d1.i2c1_sda", OMAP_MUX_MODE2 | AM33XX_SLEWCTRL_SLOW |
515 AM33XX_PULL_ENBL | AM33XX_INPUT_EN}, 516 AM33XX_PULL_ENBL | AM33XX_INPUT_EN},
516 {"spi0_cs0.i2c1_scl", OMAP_MUX_MODE2 | AM33XX_SLEWCTRL_SLOW | 517 {"spi0_cs0.i2c1_scl", OMAP_MUX_MODE2 | AM33XX_SLEWCTRL_SLOW |
517 AM33XX_PULL_ENBL | AM33XX_INPUT_EN}, 518 AM33XX_PULL_ENBL | AM33XX_INPUT_EN},
518 {NULL, 0}, 519 {NULL, 0},
519 }; 520 };
520 521
521 /* Module pin mux for mcasp1 */ 522 /* Module pin mux for mcasp1 */
522 static struct pinmux_config mcasp1_pin_mux[] = { 523 static struct pinmux_config mcasp1_pin_mux[] = {
523 {"mii1_crs.mcasp1_aclkx", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN}, 524 {"mii1_crs.mcasp1_aclkx", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
524 {"mii1_rxerr.mcasp1_fsx", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN}, 525 {"mii1_rxerr.mcasp1_fsx", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
525 {"mii1_col.mcasp1_axr2", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN}, 526 {"mii1_col.mcasp1_axr2", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
526 {"rmii1_refclk.mcasp1_axr3", OMAP_MUX_MODE4 | 527 {"rmii1_refclk.mcasp1_axr3", OMAP_MUX_MODE4 |
527 AM33XX_PIN_INPUT_PULLDOWN}, 528 AM33XX_PIN_INPUT_PULLDOWN},
528 {NULL, 0}, 529 {NULL, 0},
529 }; 530 };
530 531
531 532
532 /* Module pin mux for mmc0 */ 533 /* Module pin mux for mmc0 */
533 static struct pinmux_config mmc0_pin_mux[] = { 534 static struct pinmux_config mmc0_pin_mux[] = {
534 {"mmc0_dat3.mmc0_dat3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 535 {"mmc0_dat3.mmc0_dat3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
535 {"mmc0_dat2.mmc0_dat2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 536 {"mmc0_dat2.mmc0_dat2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
536 {"mmc0_dat1.mmc0_dat1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 537 {"mmc0_dat1.mmc0_dat1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
537 {"mmc0_dat0.mmc0_dat0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 538 {"mmc0_dat0.mmc0_dat0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
538 {"mmc0_clk.mmc0_clk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 539 {"mmc0_clk.mmc0_clk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
539 {"mmc0_cmd.mmc0_cmd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 540 {"mmc0_cmd.mmc0_cmd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
540 {"mcasp0_aclkr.mmc0_sdwp", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP}, 541 {"mcasp0_aclkr.mmc0_sdwp", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
541 {"spi0_cs1.mmc0_sdcd", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP}, 542 {"spi0_cs1.mmc0_sdcd", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
542 {NULL, 0}, 543 {NULL, 0},
543 }; 544 };
544 545
545 static struct pinmux_config mmc0_no_cd_pin_mux[] = { 546 static struct pinmux_config mmc0_no_cd_pin_mux[] = {
546 {"mmc0_dat3.mmc0_dat3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 547 {"mmc0_dat3.mmc0_dat3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
547 {"mmc0_dat2.mmc0_dat2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 548 {"mmc0_dat2.mmc0_dat2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
548 {"mmc0_dat1.mmc0_dat1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 549 {"mmc0_dat1.mmc0_dat1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
549 {"mmc0_dat0.mmc0_dat0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 550 {"mmc0_dat0.mmc0_dat0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
550 {"mmc0_clk.mmc0_clk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 551 {"mmc0_clk.mmc0_clk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
551 {"mmc0_cmd.mmc0_cmd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 552 {"mmc0_cmd.mmc0_cmd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
552 {"mcasp0_aclkr.mmc0_sdwp", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN}, 553 {"mcasp0_aclkr.mmc0_sdwp", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
553 {NULL, 0}, 554 {NULL, 0},
554 }; 555 };
555 556
556 /* Module pin mux for mmc1 */ 557 /* Module pin mux for mmc1 */
557 static struct pinmux_config mmc1_pin_mux[] = { 558 static struct pinmux_config mmc1_pin_mux[] = {
558 {"gpmc_ad7.mmc1_dat7", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP}, 559 {"gpmc_ad7.mmc1_dat7", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
559 {"gpmc_ad6.mmc1_dat6", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP}, 560 {"gpmc_ad6.mmc1_dat6", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
560 {"gpmc_ad5.mmc1_dat5", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP}, 561 {"gpmc_ad5.mmc1_dat5", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
561 {"gpmc_ad4.mmc1_dat4", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP}, 562 {"gpmc_ad4.mmc1_dat4", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
562 {"gpmc_ad3.mmc1_dat3", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP}, 563 {"gpmc_ad3.mmc1_dat3", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
563 {"gpmc_ad2.mmc1_dat2", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP}, 564 {"gpmc_ad2.mmc1_dat2", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
564 {"gpmc_ad1.mmc1_dat1", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP}, 565 {"gpmc_ad1.mmc1_dat1", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
565 {"gpmc_ad0.mmc1_dat0", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP}, 566 {"gpmc_ad0.mmc1_dat0", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
566 {"gpmc_csn1.mmc1_clk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP}, 567 {"gpmc_csn1.mmc1_clk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
567 {"gpmc_csn2.mmc1_cmd", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP}, 568 {"gpmc_csn2.mmc1_cmd", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
568 {"gpmc_csn0.mmc1_sdwp", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP}, 569 {"gpmc_csn0.mmc1_sdwp", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
569 {"gpmc_advn_ale.mmc1_sdcd", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP}, 570 {"gpmc_advn_ale.mmc1_sdcd", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
570 {NULL, 0}, 571 {NULL, 0},
571 }; 572 };
572 573
573 /* Module pin mux for uart3 */ 574 /* Module pin mux for uart3 */
574 static struct pinmux_config uart3_pin_mux[] = { 575 static struct pinmux_config uart3_pin_mux[] = {
575 {"spi0_cs1.uart3_rxd", AM33XX_PIN_INPUT_PULLUP}, 576 {"spi0_cs1.uart3_rxd", AM33XX_PIN_INPUT_PULLUP},
576 {"ecap0_in_pwm0_out.uart3_txd", AM33XX_PULL_ENBL}, 577 {"ecap0_in_pwm0_out.uart3_txd", AM33XX_PULL_ENBL},
577 {NULL, 0}, 578 {NULL, 0},
578 }; 579 };
579 580
580 static struct pinmux_config d_can_gp_pin_mux[] = { 581 static struct pinmux_config d_can_gp_pin_mux[] = {
581 {"uart0_ctsn.d_can1_tx", OMAP_MUX_MODE2 | AM33XX_PULL_ENBL}, 582 {"uart0_ctsn.d_can1_tx", OMAP_MUX_MODE2 | AM33XX_PULL_ENBL},
582 {"uart0_rtsn.d_can1_rx", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP}, 583 {"uart0_rtsn.d_can1_rx", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
583 {NULL, 0}, 584 {NULL, 0},
584 }; 585 };
585 586
586 static struct pinmux_config d_can_ia_pin_mux[] = { 587 static struct pinmux_config d_can_ia_pin_mux[] = {
587 {"uart0_rxd.d_can0_tx", OMAP_MUX_MODE2 | AM33XX_PULL_ENBL}, 588 {"uart0_rxd.d_can0_tx", OMAP_MUX_MODE2 | AM33XX_PULL_ENBL},
588 {"uart0_txd.d_can0_rx", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP}, 589 {"uart0_txd.d_can0_rx", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
589 {NULL, 0}, 590 {NULL, 0},
590 }; 591 };
591 592
592 /* 593 /*
593 * @pin_mux - single module pin-mux structure which defines pin-mux 594 * @pin_mux - single module pin-mux structure which defines pin-mux
594 * details for all its pins. 595 * details for all its pins.
595 */ 596 */
596 static void setup_pin_mux(struct pinmux_config *pin_mux) 597 static void setup_pin_mux(struct pinmux_config *pin_mux)
597 { 598 {
598 int i; 599 int i;
599 600
600 for (i = 0; pin_mux->string_name != NULL; pin_mux++) 601 for (i = 0; pin_mux->string_name != NULL; pin_mux++)
601 omap_mux_init_signal(pin_mux->string_name, pin_mux->val); 602 omap_mux_init_signal(pin_mux->string_name, pin_mux->val);
602 603
603 } 604 }
604 605
605 /* Matrix GPIO Keypad Support for profile-0 only: TODO */ 606 /* Matrix GPIO Keypad Support for profile-0 only: TODO */
606 #ifdef CONFIG_KEYBOARD_MATRIX 607 #ifdef CONFIG_KEYBOARD_MATRIX
607 608
608 /* pinmux for keypad device */ 609 /* pinmux for keypad device */
609 static struct pinmux_config matrix_keypad_pin_mux[] = { 610 static struct pinmux_config matrix_keypad_pin_mux[] = {
610 {"gpmc_a5.gpio1_21", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT}, 611 {"gpmc_a5.gpio1_21", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
611 {"gpmc_a8.gpio1_24", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT}, 612 {"gpmc_a8.gpio1_24", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
612 {"gpmc_a9.gpio1_25", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT}, 613 {"gpmc_a9.gpio1_25", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
613 {"gpmc_a10.gpio1_26", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT}, 614 {"gpmc_a10.gpio1_26", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
614 {"gpmc_a11.gpio1_27", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT}, 615 {"gpmc_a11.gpio1_27", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
615 {NULL, 0}, 616 {NULL, 0},
616 }; 617 };
617 618
618 /* Keys mapping */ 619 /* Keys mapping */
619 static const uint32_t am335x_evm_matrix_keys[] = { 620 static const uint32_t am335x_evm_matrix_keys[] = {
620 KEY(0, 0, KEY_MENU), 621 KEY(0, 0, KEY_MENU),
621 KEY(1, 0, KEY_BACK), 622 KEY(1, 0, KEY_BACK),
622 KEY(2, 0, KEY_LEFT), 623 KEY(2, 0, KEY_LEFT),
623 624
624 KEY(0, 1, KEY_RIGHT), 625 KEY(0, 1, KEY_RIGHT),
625 KEY(1, 1, KEY_ENTER), 626 KEY(1, 1, KEY_ENTER),
626 KEY(2, 1, KEY_DOWN), 627 KEY(2, 1, KEY_DOWN),
627 }; 628 };
628 629
629 const struct matrix_keymap_data am335x_evm_keymap_data = { 630 const struct matrix_keymap_data am335x_evm_keymap_data = {
630 .keymap = am335x_evm_matrix_keys, 631 .keymap = am335x_evm_matrix_keys,
631 .keymap_size = ARRAY_SIZE(am335x_evm_matrix_keys), 632 .keymap_size = ARRAY_SIZE(am335x_evm_matrix_keys),
632 }; 633 };
633 634
634 static const unsigned int am335x_evm_keypad_row_gpios[] = { 635 static const unsigned int am335x_evm_keypad_row_gpios[] = {
635 GPIO_TO_PIN(1, 25), GPIO_TO_PIN(1, 26), GPIO_TO_PIN(1, 27) 636 GPIO_TO_PIN(1, 25), GPIO_TO_PIN(1, 26), GPIO_TO_PIN(1, 27)
636 }; 637 };
637 638
638 static const unsigned int am335x_evm_keypad_col_gpios[] = { 639 static const unsigned int am335x_evm_keypad_col_gpios[] = {
639 GPIO_TO_PIN(1, 21), GPIO_TO_PIN(1, 24) 640 GPIO_TO_PIN(1, 21), GPIO_TO_PIN(1, 24)
640 }; 641 };
641 642
642 static struct matrix_keypad_platform_data am335x_evm_keypad_platform_data = { 643 static struct matrix_keypad_platform_data am335x_evm_keypad_platform_data = {
643 .keymap_data = &am335x_evm_keymap_data, 644 .keymap_data = &am335x_evm_keymap_data,
644 .row_gpios = am335x_evm_keypad_row_gpios, 645 .row_gpios = am335x_evm_keypad_row_gpios,
645 .num_row_gpios = ARRAY_SIZE(am335x_evm_keypad_row_gpios), 646 .num_row_gpios = ARRAY_SIZE(am335x_evm_keypad_row_gpios),
646 .col_gpios = am335x_evm_keypad_col_gpios, 647 .col_gpios = am335x_evm_keypad_col_gpios,
647 .num_col_gpios = ARRAY_SIZE(am335x_evm_keypad_col_gpios), 648 .num_col_gpios = ARRAY_SIZE(am335x_evm_keypad_col_gpios),
648 .active_low = false, 649 .active_low = false,
649 .debounce_ms = 5, 650 .debounce_ms = 5,
650 .col_scan_delay_us = 2, 651 .col_scan_delay_us = 2,
651 }; 652 };
652 653
653 static struct platform_device am335x_evm_keyboard = { 654 static struct platform_device am335x_evm_keyboard = {
654 .name = "matrix-keypad", 655 .name = "matrix-keypad",
655 .id = -1, 656 .id = -1,
656 .dev = { 657 .dev = {
657 .platform_data = &am335x_evm_keypad_platform_data, 658 .platform_data = &am335x_evm_keypad_platform_data,
658 }, 659 },
659 }; 660 };
660 661
661 static void matrix_keypad_init(int evm_id, int profile) 662 static void matrix_keypad_init(int evm_id, int profile)
662 { 663 {
663 int err; 664 int err;
664 665
665 setup_pin_mux(matrix_keypad_pin_mux); 666 setup_pin_mux(matrix_keypad_pin_mux);
666 err = platform_device_register(&am335x_evm_keyboard); 667 err = platform_device_register(&am335x_evm_keyboard);
667 if (err) { 668 if (err) {
668 pr_err("failed to register matrix keypad (2x3) device\n"); 669 pr_err("failed to register matrix keypad (2x3) device\n");
669 } 670 }
670 } 671 }
671 #endif 672 #endif
672 673
673 674
674 #ifdef CONFIG_KEYBOARD_GPIO 675 #ifdef CONFIG_KEYBOARD_GPIO
675 /* pinmux for keypad device */ 676 /* pinmux for keypad device */
676 static struct pinmux_config volume_keys_pin_mux[] = { 677 static struct pinmux_config volume_keys_pin_mux[] = {
677 {"spi0_sclk.gpio0_2", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT}, 678 {"spi0_sclk.gpio0_2", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
678 {"spi0_d0.gpio0_3", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT}, 679 {"spi0_d0.gpio0_3", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
679 {NULL, 0}, 680 {NULL, 0},
680 }; 681 };
681 682
682 /* Configure GPIOs for Volume Keys */ 683 /* Configure GPIOs for Volume Keys */
683 static struct gpio_keys_button am335x_evm_volume_gpio_buttons[] = { 684 static struct gpio_keys_button am335x_evm_volume_gpio_buttons[] = {
684 { 685 {
685 .code = KEY_VOLUMEUP, 686 .code = KEY_VOLUMEUP,
686 .gpio = GPIO_TO_PIN(0, 2), 687 .gpio = GPIO_TO_PIN(0, 2),
687 .active_low = true, 688 .active_low = true,
688 .desc = "volume-up", 689 .desc = "volume-up",
689 .type = EV_KEY, 690 .type = EV_KEY,
690 .wakeup = 1, 691 .wakeup = 1,
691 }, 692 },
692 { 693 {
693 .code = KEY_VOLUMEDOWN, 694 .code = KEY_VOLUMEDOWN,
694 .gpio = GPIO_TO_PIN(0, 3), 695 .gpio = GPIO_TO_PIN(0, 3),
695 .active_low = true, 696 .active_low = true,
696 .desc = "volume-down", 697 .desc = "volume-down",
697 .type = EV_KEY, 698 .type = EV_KEY,
698 .wakeup = 1, 699 .wakeup = 1,
699 }, 700 },
700 }; 701 };
701 702
702 static struct gpio_keys_platform_data am335x_evm_volume_gpio_key_info = { 703 static struct gpio_keys_platform_data am335x_evm_volume_gpio_key_info = {
703 .buttons = am335x_evm_volume_gpio_buttons, 704 .buttons = am335x_evm_volume_gpio_buttons,
704 .nbuttons = ARRAY_SIZE(am335x_evm_volume_gpio_buttons), 705 .nbuttons = ARRAY_SIZE(am335x_evm_volume_gpio_buttons),
705 }; 706 };
706 707
707 static struct platform_device am335x_evm_volume_keys = { 708 static struct platform_device am335x_evm_volume_keys = {
708 .name = "gpio-keys", 709 .name = "gpio-keys",
709 .id = -1, 710 .id = -1,
710 .dev = { 711 .dev = {
711 .platform_data = &am335x_evm_volume_gpio_key_info, 712 .platform_data = &am335x_evm_volume_gpio_key_info,
712 }, 713 },
713 }; 714 };
714 715
715 static void volume_keys_init(int evm_id, int profile) 716 static void volume_keys_init(int evm_id, int profile)
716 { 717 {
717 int err; 718 int err;
718 719
719 setup_pin_mux(volume_keys_pin_mux); 720 setup_pin_mux(volume_keys_pin_mux);
720 err = platform_device_register(&am335x_evm_volume_keys); 721 err = platform_device_register(&am335x_evm_volume_keys);
721 if (err) 722 if (err)
722 pr_err("failed to register matrix keypad (2x3) device\n"); 723 pr_err("failed to register matrix keypad (2x3) device\n");
723 } 724 }
724 #endif 725 #endif
725 726
726 /* 727 /*
727 * @evm_id - evm id which needs to be configured 728 * @evm_id - evm id which needs to be configured
728 * @dev_cfg - single evm structure which includes 729 * @dev_cfg - single evm structure which includes
729 * all module inits, pin-mux defines 730 * all module inits, pin-mux defines
730 * @profile - if present, else PROFILE_NONE 731 * @profile - if present, else PROFILE_NONE
731 * @dghtr_brd_flg - Whether Daughter board is present or not 732 * @dghtr_brd_flg - Whether Daughter board is present or not
732 */ 733 */
733 static void _configure_device(int evm_id, struct evm_dev_cfg *dev_cfg, 734 static void _configure_device(int evm_id, struct evm_dev_cfg *dev_cfg,
734 int profile) 735 int profile)
735 { 736 {
736 int i; 737 int i;
737 738
738 /* 739 /*
739 * Only General Purpose & Industrial Auto Motro Control 740 * Only General Purpose & Industrial Auto Motro Control
740 * EVM has profiles. So check if this evm has profile. 741 * EVM has profiles. So check if this evm has profile.
741 * If not, ignore the profile comparison 742 * If not, ignore the profile comparison
742 */ 743 */
743 744
744 /* 745 /*
745 * If the device is on baseboard, directly configure it. Else (device on 746 * If the device is on baseboard, directly configure it. Else (device on
746 * Daughter board), check if the daughter card is detected. 747 * Daughter board), check if the daughter card is detected.
747 */ 748 */
748 if (profile == PROFILE_NONE) { 749 if (profile == PROFILE_NONE) {
749 for (i = 0; dev_cfg->device_init != NULL; dev_cfg++) { 750 for (i = 0; dev_cfg->device_init != NULL; dev_cfg++) {
750 if (dev_cfg->device_on == DEV_ON_BASEBOARD) 751 if (dev_cfg->device_on == DEV_ON_BASEBOARD)
751 dev_cfg->device_init(evm_id, profile); 752 dev_cfg->device_init(evm_id, profile);
752 else if (daughter_brd_detected == true) 753 else if (daughter_brd_detected == true)
753 dev_cfg->device_init(evm_id, profile); 754 dev_cfg->device_init(evm_id, profile);
754 } 755 }
755 } else { 756 } else {
756 for (i = 0; dev_cfg->device_init != NULL; dev_cfg++) { 757 for (i = 0; dev_cfg->device_init != NULL; dev_cfg++) {
757 if (dev_cfg->profile & profile) { 758 if (dev_cfg->profile & profile) {
758 if (dev_cfg->device_on == DEV_ON_BASEBOARD) 759 if (dev_cfg->device_on == DEV_ON_BASEBOARD)
759 dev_cfg->device_init(evm_id, profile); 760 dev_cfg->device_init(evm_id, profile);
760 else if (daughter_brd_detected == true) 761 else if (daughter_brd_detected == true)
761 dev_cfg->device_init(evm_id, profile); 762 dev_cfg->device_init(evm_id, profile);
762 } 763 }
763 } 764 }
764 } 765 }
765 } 766 }
766 767
767 #define AM335X_LCD_BL_PIN GPIO_TO_PIN(0, 7) 768 #define AM335X_LCD_BL_PIN GPIO_TO_PIN(0, 7)
768 769
769 /* pinmux for usb0 drvvbus */ 770 /* pinmux for usb0 drvvbus */
770 static struct pinmux_config usb0_pin_mux[] = { 771 static struct pinmux_config usb0_pin_mux[] = {
771 {"usb0_drvvbus.usb0_drvvbus", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, 772 {"usb0_drvvbus.usb0_drvvbus", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
772 {NULL, 0}, 773 {NULL, 0},
773 }; 774 };
774 775
775 /* pinmux for usb1 drvvbus */ 776 /* pinmux for usb1 drvvbus */
776 static struct pinmux_config usb1_pin_mux[] = { 777 static struct pinmux_config usb1_pin_mux[] = {
777 {"usb1_drvvbus.usb1_drvvbus", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, 778 {"usb1_drvvbus.usb1_drvvbus", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
778 {NULL, 0}, 779 {NULL, 0},
779 }; 780 };
780 781
781 /* pinmux for profibus */ 782 /* pinmux for profibus */
782 static struct pinmux_config profibus_pin_mux[] = { 783 static struct pinmux_config profibus_pin_mux[] = {
783 {"uart1_rxd.pr1_uart0_rxd_mux1", OMAP_MUX_MODE5 | AM33XX_PIN_INPUT}, 784 {"uart1_rxd.pr1_uart0_rxd_mux1", OMAP_MUX_MODE5 | AM33XX_PIN_INPUT},
784 {"uart1_txd.pr1_uart0_txd_mux1", OMAP_MUX_MODE5 | AM33XX_PIN_OUTPUT}, 785 {"uart1_txd.pr1_uart0_txd_mux1", OMAP_MUX_MODE5 | AM33XX_PIN_OUTPUT},
785 {"mcasp0_fsr.pr1_pru0_pru_r30_5", OMAP_MUX_MODE5 | AM33XX_PIN_OUTPUT}, 786 {"mcasp0_fsr.pr1_pru0_pru_r30_5", OMAP_MUX_MODE5 | AM33XX_PIN_OUTPUT},
786 {NULL, 0}, 787 {NULL, 0},
787 }; 788 };
788 789
789 /* Module pin mux for eCAP0 */ 790 /* Module pin mux for eCAP0 */
790 static struct pinmux_config ecap0_pin_mux[] = { 791 static struct pinmux_config ecap0_pin_mux[] = {
791 {"ecap0_in_pwm0_out.gpio0_7", AM33XX_PIN_OUTPUT}, 792 {"ecap0_in_pwm0_out.gpio0_7", AM33XX_PIN_OUTPUT},
792 {NULL, 0}, 793 {NULL, 0},
793 }; 794 };
794 795
795 #define AM335XEVM_WLAN_IRQ_GPIO GPIO_TO_PIN(3, 17) 796 #define AM335XEVM_WLAN_IRQ_GPIO GPIO_TO_PIN(3, 17)
796 797
797 struct wl12xx_platform_data am335xevm_wlan_data = { 798 struct wl12xx_platform_data am335xevm_wlan_data = {
798 .irq = OMAP_GPIO_IRQ(AM335XEVM_WLAN_IRQ_GPIO), 799 .irq = OMAP_GPIO_IRQ(AM335XEVM_WLAN_IRQ_GPIO),
799 .board_ref_clock = WL12XX_REFCLOCK_38_XTAL, /* 38.4Mhz */ 800 .board_ref_clock = WL12XX_REFCLOCK_38_XTAL, /* 38.4Mhz */
800 }; 801 };
801 802
802 /* Module pin mux for wlan and bluetooth */ 803 /* Module pin mux for wlan and bluetooth */
803 static struct pinmux_config mmc2_wl12xx_pin_mux[] = { 804 static struct pinmux_config mmc2_wl12xx_pin_mux[] = {
804 {"gpmc_a1.mmc2_dat0", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP}, 805 {"gpmc_a1.mmc2_dat0", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
805 {"gpmc_a2.mmc2_dat1", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP}, 806 {"gpmc_a2.mmc2_dat1", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
806 {"gpmc_a3.mmc2_dat2", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP}, 807 {"gpmc_a3.mmc2_dat2", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
807 {"gpmc_ben1.mmc2_dat3", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP}, 808 {"gpmc_ben1.mmc2_dat3", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
808 {"gpmc_csn3.mmc2_cmd", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP}, 809 {"gpmc_csn3.mmc2_cmd", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
809 {"gpmc_clk.mmc2_clk", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP}, 810 {"gpmc_clk.mmc2_clk", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
810 {NULL, 0}, 811 {NULL, 0},
811 }; 812 };
812 813
813 static struct pinmux_config uart1_wl12xx_pin_mux[] = { 814 static struct pinmux_config uart1_wl12xx_pin_mux[] = {
814 {"uart1_ctsn.uart1_ctsn", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, 815 {"uart1_ctsn.uart1_ctsn", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
815 {"uart1_rtsn.uart1_rtsn", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT}, 816 {"uart1_rtsn.uart1_rtsn", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT},
816 {"uart1_rxd.uart1_rxd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 817 {"uart1_rxd.uart1_rxd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
817 {"uart1_txd.uart1_txd", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL}, 818 {"uart1_txd.uart1_txd", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL},
818 {NULL, 0}, 819 {NULL, 0},
819 }; 820 };
820 821
821 static struct pinmux_config wl12xx_pin_mux_evm_rev1_1a[] = { 822 static struct pinmux_config wl12xx_pin_mux_evm_rev1_1a[] = {
822 {"gpmc_a0.gpio1_16", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT}, 823 {"gpmc_a0.gpio1_16", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
823 {"mcasp0_ahclkr.gpio3_17", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT}, 824 {"mcasp0_ahclkr.gpio3_17", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
824 {"mcasp0_ahclkx.gpio3_21", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT}, 825 {"mcasp0_ahclkx.gpio3_21", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
825 {NULL, 0}, 826 {NULL, 0},
826 }; 827 };
827 828
828 static struct pinmux_config wl12xx_pin_mux_evm_rev1_0[] = { 829 static struct pinmux_config wl12xx_pin_mux_evm_rev1_0[] = {
829 {"gpmc_csn1.gpio1_30", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT}, 830 {"gpmc_csn1.gpio1_30", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
830 {"mcasp0_ahclkr.gpio3_17", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT}, 831 {"mcasp0_ahclkr.gpio3_17", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
831 {"gpmc_csn2.gpio1_31", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT}, 832 {"gpmc_csn2.gpio1_31", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
832 {NULL, 0}, 833 {NULL, 0},
833 }; 834 };
834 835
835 static int backlight_enable = false; 836 static int backlight_enable = false;
836 837
837 static void enable_ecap0(int evm_id, int profile) 838 static void enable_ecap0(int evm_id, int profile)
838 { 839 {
839 backlight_enable = true; 840 backlight_enable = true;
840 } 841 }
841 842
842 static int __init ecap0_init(void) 843 static int __init ecap0_init(void)
843 { 844 {
844 int status = 0; 845 int status = 0;
845 846
846 if (backlight_enable) { 847 if (backlight_enable) {
847 setup_pin_mux(ecap0_pin_mux); 848 setup_pin_mux(ecap0_pin_mux);
848 849
849 status = gpio_request(AM335X_LCD_BL_PIN, "lcd bl\n"); 850 status = gpio_request(AM335X_LCD_BL_PIN, "lcd bl\n");
850 if (status < 0) 851 if (status < 0)
851 pr_warn("Failed to request gpio for LCD backlight\n"); 852 pr_warn("Failed to request gpio for LCD backlight\n");
852 853
853 gpio_direction_output(AM335X_LCD_BL_PIN, 1); 854 gpio_direction_output(AM335X_LCD_BL_PIN, 1);
854 } 855 }
855 return status; 856 return status;
856 } 857 }
857 late_initcall(ecap0_init); 858 late_initcall(ecap0_init);
858 859
859 static int __init conf_disp_pll(int rate) 860 static int __init conf_disp_pll(int rate)
860 { 861 {
861 struct clk *disp_pll; 862 struct clk *disp_pll;
862 int ret = -EINVAL; 863 int ret = -EINVAL;
863 864
864 disp_pll = clk_get(NULL, "dpll_disp_ck"); 865 disp_pll = clk_get(NULL, "dpll_disp_ck");
865 if (IS_ERR(disp_pll)) { 866 if (IS_ERR(disp_pll)) {
866 pr_err("Cannot clk_get disp_pll\n"); 867 pr_err("Cannot clk_get disp_pll\n");
867 goto out; 868 goto out;
868 } 869 }
869 870
870 ret = clk_set_rate(disp_pll, rate); 871 ret = clk_set_rate(disp_pll, rate);
871 clk_put(disp_pll); 872 clk_put(disp_pll);
872 out: 873 out:
873 return ret; 874 return ret;
874 } 875 }
875 876
876 static void lcdc_init(int evm_id, int profile) 877 static void lcdc_init(int evm_id, int profile)
877 { 878 {
878 879
879 setup_pin_mux(lcdc_pin_mux); 880 setup_pin_mux(lcdc_pin_mux);
880 881
881 if (conf_disp_pll(300000000)) { 882 if (conf_disp_pll(300000000)) {
882 pr_info("Failed configure display PLL, not attempting to" 883 pr_info("Failed configure display PLL, not attempting to"
883 "register LCDC\n"); 884 "register LCDC\n");
884 return; 885 return;
885 } 886 }
886 887
887 if (am33xx_register_lcdc(&TFC_S9700RTWV35TR_01B_pdata)) 888 if (am33xx_register_lcdc(&TFC_S9700RTWV35TR_01B_pdata))
888 pr_info("Failed to register LCDC device\n"); 889 pr_info("Failed to register LCDC device\n");
889 return; 890 return;
890 } 891 }
891 892
892 static void tsc_init(int evm_id, int profile) 893 static void tsc_init(int evm_id, int profile)
893 { 894 {
894 int err; 895 int err;
895 896
896 if (gp_evm_revision == GP_EVM_REV_IS_1_1A) { 897 if (gp_evm_revision == GP_EVM_REV_IS_1_1A) {
897 am335x_touchscreen_data.analog_input = 1; 898 am335x_touchscreen_data.analog_input = 1;
898 pr_info("TSC connected to beta GP EVM\n"); 899 pr_info("TSC connected to beta GP EVM\n");
899 } else { 900 } else {
900 am335x_touchscreen_data.analog_input = 0; 901 am335x_touchscreen_data.analog_input = 0;
901 pr_info("TSC connected to alpha GP EVM\n"); 902 pr_info("TSC connected to alpha GP EVM\n");
902 } 903 }
903 setup_pin_mux(tsc_pin_mux); 904 setup_pin_mux(tsc_pin_mux);
904 err = platform_device_register(&tsc_device); 905 err = platform_device_register(&tsc_device);
905 if (err) 906 if (err)
906 pr_err("failed to register touchscreen device\n"); 907 pr_err("failed to register touchscreen device\n");
907 } 908 }
908 909
909 static void rgmii1_init(int evm_id, int profile) 910 static void rgmii1_init(int evm_id, int profile)
910 { 911 {
911 setup_pin_mux(rgmii1_pin_mux); 912 setup_pin_mux(rgmii1_pin_mux);
912 return; 913 return;
913 } 914 }
914 915
915 static void rgmii2_init(int evm_id, int profile) 916 static void rgmii2_init(int evm_id, int profile)
916 { 917 {
917 setup_pin_mux(rgmii2_pin_mux); 918 setup_pin_mux(rgmii2_pin_mux);
918 return; 919 return;
919 } 920 }
920 921
921 static void mii1_init(int evm_id, int profile) 922 static void mii1_init(int evm_id, int profile)
922 { 923 {
923 setup_pin_mux(mii1_pin_mux); 924 setup_pin_mux(mii1_pin_mux);
924 return; 925 return;
925 } 926 }
926 927
927 static void rmii1_init(int evm_id, int profile) 928 static void rmii1_init(int evm_id, int profile)
928 { 929 {
929 setup_pin_mux(rmii1_pin_mux); 930 setup_pin_mux(rmii1_pin_mux);
930 return; 931 return;
931 } 932 }
932 933
933 static void usb0_init(int evm_id, int profile) 934 static void usb0_init(int evm_id, int profile)
934 { 935 {
935 setup_pin_mux(usb0_pin_mux); 936 setup_pin_mux(usb0_pin_mux);
936 return; 937 return;
937 } 938 }
938 939
939 static void usb1_init(int evm_id, int profile) 940 static void usb1_init(int evm_id, int profile)
940 { 941 {
941 setup_pin_mux(usb1_pin_mux); 942 setup_pin_mux(usb1_pin_mux);
942 return; 943 return;
943 } 944 }
944 945
945 /* setup uart3 */ 946 /* setup uart3 */
946 static void uart3_init(int evm_id, int profile) 947 static void uart3_init(int evm_id, int profile)
947 { 948 {
948 setup_pin_mux(uart3_pin_mux); 949 setup_pin_mux(uart3_pin_mux);
949 return; 950 return;
950 } 951 }
951 952
952 /* NAND partition information */ 953 /* NAND partition information */
953 static struct mtd_partition am335x_nand_partitions[] = { 954 static struct mtd_partition am335x_nand_partitions[] = {
954 /* All the partition sizes are listed in terms of NAND block size */ 955 /* All the partition sizes are listed in terms of NAND block size */
955 { 956 {
956 .name = "SPL", 957 .name = "SPL",
957 .offset = 0, /* Offset = 0x0 */ 958 .offset = 0, /* Offset = 0x0 */
958 .size = SZ_128K, 959 .size = SZ_128K,
959 }, 960 },
960 { 961 {
961 .name = "SPL.backup1", 962 .name = "SPL.backup1",
962 .offset = MTDPART_OFS_APPEND, /* Offset = 0x20000 */ 963 .offset = MTDPART_OFS_APPEND, /* Offset = 0x20000 */
963 .size = SZ_128K, 964 .size = SZ_128K,
964 }, 965 },
965 { 966 {
966 .name = "SPL.backup2", 967 .name = "SPL.backup2",
967 .offset = MTDPART_OFS_APPEND, /* Offset = 0x40000 */ 968 .offset = MTDPART_OFS_APPEND, /* Offset = 0x40000 */
968 .size = SZ_128K, 969 .size = SZ_128K,
969 }, 970 },
970 { 971 {
971 .name = "SPL.backup3", 972 .name = "SPL.backup3",
972 .offset = MTDPART_OFS_APPEND, /* Offset = 0x60000 */ 973 .offset = MTDPART_OFS_APPEND, /* Offset = 0x60000 */
973 .size = SZ_128K, 974 .size = SZ_128K,
974 }, 975 },
975 { 976 {
976 .name = "U-Boot", 977 .name = "U-Boot",
977 .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */ 978 .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */
978 .size = 15 * SZ_128K, 979 .size = 15 * SZ_128K,
979 }, 980 },
980 { 981 {
981 .name = "U-Boot Env", 982 .name = "U-Boot Env",
982 .offset = MTDPART_OFS_APPEND, /* Offset = 0x260000 */ 983 .offset = MTDPART_OFS_APPEND, /* Offset = 0x260000 */
983 .size = 1 * SZ_128K, 984 .size = 1 * SZ_128K,
984 }, 985 },
985 { 986 {
986 .name = "Kernel", 987 .name = "Kernel",
987 .offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */ 988 .offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */
988 .size = 40 * SZ_128K, 989 .size = 40 * SZ_128K,
989 }, 990 },
990 { 991 {
991 .name = "File System", 992 .name = "File System",
992 .offset = MTDPART_OFS_APPEND, /* Offset = 0x780000 */ 993 .offset = MTDPART_OFS_APPEND, /* Offset = 0x780000 */
993 .size = MTDPART_SIZ_FULL, 994 .size = MTDPART_SIZ_FULL,
994 }, 995 },
995 }; 996 };
996 997
997 /* SPI 0/1 Platform Data */ 998 /* SPI 0/1 Platform Data */
998 /* SPI flash information */ 999 /* SPI flash information */
999 static struct mtd_partition am335x_spi_partitions[] = { 1000 static struct mtd_partition am335x_spi_partitions[] = {
1000 /* All the partition sizes are listed in terms of erase size */ 1001 /* All the partition sizes are listed in terms of erase size */
1001 { 1002 {
1002 .name = "U-Boot-min", 1003 .name = "U-Boot-min",
1003 .offset = 0, 1004 .offset = 0,
1004 .size = SZ_128K, 1005 .size = SZ_128K,
1005 .mask_flags = MTD_WRITEABLE, /* force read-only */ 1006 .mask_flags = MTD_WRITEABLE, /* force read-only */
1006 }, 1007 },
1007 { 1008 {
1008 .name = "U-Boot", 1009 .name = "U-Boot",
1009 .offset = MTDPART_OFS_APPEND, 1010 .offset = MTDPART_OFS_APPEND,
1010 .size = 2 * SZ_128K, 1011 .size = 2 * SZ_128K,
1011 .mask_flags = MTD_WRITEABLE, /* force read-only */ 1012 .mask_flags = MTD_WRITEABLE, /* force read-only */
1012 }, 1013 },
1013 { 1014 {
1014 .name = "U-Boot Env", 1015 .name = "U-Boot Env",
1015 .offset = MTDPART_OFS_APPEND, 1016 .offset = MTDPART_OFS_APPEND,
1016 .size = 2 * SZ_4K, 1017 .size = 2 * SZ_4K,
1017 }, 1018 },
1018 { 1019 {
1019 .name = "Kernel", 1020 .name = "Kernel",
1020 .offset = MTDPART_OFS_APPEND, 1021 .offset = MTDPART_OFS_APPEND,
1021 .size = 28 * SZ_128K, 1022 .size = 28 * SZ_128K,
1022 }, 1023 },
1023 { 1024 {
1024 .name = "File System", 1025 .name = "File System",
1025 .offset = MTDPART_OFS_APPEND, 1026 .offset = MTDPART_OFS_APPEND,
1026 .size = MTDPART_SIZ_FULL, /* size ~= 1.1 MiB */ 1027 .size = MTDPART_SIZ_FULL, /* size ~= 1.1 MiB */
1027 } 1028 }
1028 }; 1029 };
1029 1030
1030 static const struct flash_platform_data am335x_spi_flash = { 1031 static const struct flash_platform_data am335x_spi_flash = {
1031 .type = "w25q64", 1032 .type = "w25q64",
1032 .name = "spi_flash", 1033 .name = "spi_flash",
1033 .parts = am335x_spi_partitions, 1034 .parts = am335x_spi_partitions,
1034 .nr_parts = ARRAY_SIZE(am335x_spi_partitions), 1035 .nr_parts = ARRAY_SIZE(am335x_spi_partitions),
1035 }; 1036 };
1036 1037
1037 /* 1038 /*
1038 * SPI Flash works at 80Mhz however SPI Controller works at 48MHz. 1039 * SPI Flash works at 80Mhz however SPI Controller works at 48MHz.
1039 * So setup Max speed to be less than that of Controller speed 1040 * So setup Max speed to be less than that of Controller speed
1040 */ 1041 */
1041 static struct spi_board_info am335x_spi0_slave_info[] = { 1042 static struct spi_board_info am335x_spi0_slave_info[] = {
1042 { 1043 {
1043 .modalias = "m25p80", 1044 .modalias = "m25p80",
1044 .platform_data = &am335x_spi_flash, 1045 .platform_data = &am335x_spi_flash,
1045 .irq = -1, 1046 .irq = -1,
1046 .max_speed_hz = 24000000, 1047 .max_speed_hz = 24000000,
1047 .bus_num = 1, 1048 .bus_num = 1,
1048 .chip_select = 0, 1049 .chip_select = 0,
1049 }, 1050 },
1050 }; 1051 };
1051 1052
1052 static struct spi_board_info am335x_spi1_slave_info[] = { 1053 static struct spi_board_info am335x_spi1_slave_info[] = {
1053 { 1054 {
1054 .modalias = "m25p80", 1055 .modalias = "m25p80",
1055 .platform_data = &am335x_spi_flash, 1056 .platform_data = &am335x_spi_flash,
1056 .irq = -1, 1057 .irq = -1,
1057 .max_speed_hz = 12000000, 1058 .max_speed_hz = 12000000,
1058 .bus_num = 2, 1059 .bus_num = 2,
1059 .chip_select = 0, 1060 .chip_select = 0,
1060 }, 1061 },
1061 }; 1062 };
1062 1063
1063 static void evm_nand_init(int evm_id, int profile) 1064 static void evm_nand_init(int evm_id, int profile)
1064 { 1065 {
1065 setup_pin_mux(nand_pin_mux); 1066 setup_pin_mux(nand_pin_mux);
1066 board_nand_init(am335x_nand_partitions, 1067 board_nand_init(am335x_nand_partitions,
1067 ARRAY_SIZE(am335x_nand_partitions), 0, 0); 1068 ARRAY_SIZE(am335x_nand_partitions), 0, 0);
1068 } 1069 }
1069 1070
1070 static struct lis3lv02d_platform_data lis331dlh_pdata = { 1071 static struct lis3lv02d_platform_data lis331dlh_pdata = {
1071 .click_flags = LIS3_CLICK_SINGLE_X | 1072 .click_flags = LIS3_CLICK_SINGLE_X |
1072 LIS3_CLICK_SINGLE_Y | 1073 LIS3_CLICK_SINGLE_Y |
1073 LIS3_CLICK_SINGLE_Z, 1074 LIS3_CLICK_SINGLE_Z,
1074 .wakeup_flags = LIS3_WAKEUP_X_LO | LIS3_WAKEUP_X_HI | 1075 .wakeup_flags = LIS3_WAKEUP_X_LO | LIS3_WAKEUP_X_HI |
1075 LIS3_WAKEUP_Y_LO | LIS3_WAKEUP_Y_HI | 1076 LIS3_WAKEUP_Y_LO | LIS3_WAKEUP_Y_HI |
1076 LIS3_WAKEUP_Z_LO | LIS3_WAKEUP_Z_HI, 1077 LIS3_WAKEUP_Z_LO | LIS3_WAKEUP_Z_HI,
1077 .irq_cfg = LIS3_IRQ1_CLICK | LIS3_IRQ2_CLICK, 1078 .irq_cfg = LIS3_IRQ1_CLICK | LIS3_IRQ2_CLICK,
1078 .wakeup_thresh = 10, 1079 .wakeup_thresh = 10,
1079 .click_thresh_x = 10, 1080 .click_thresh_x = 10,
1080 .click_thresh_y = 10, 1081 .click_thresh_y = 10,
1081 .click_thresh_z = 10, 1082 .click_thresh_z = 10,
1082 .g_range = 2, 1083 .g_range = 2,
1083 .st_min_limits[0] = 120, 1084 .st_min_limits[0] = 120,
1084 .st_min_limits[1] = 120, 1085 .st_min_limits[1] = 120,
1085 .st_min_limits[2] = 140, 1086 .st_min_limits[2] = 140,
1086 .st_max_limits[0] = 550, 1087 .st_max_limits[0] = 550,
1087 .st_max_limits[1] = 550, 1088 .st_max_limits[1] = 550,
1088 .st_max_limits[2] = 750, 1089 .st_max_limits[2] = 750,
1089 }; 1090 };
1090 1091
1091 static struct i2c_board_info am335x_i2c_boardinfo1[] = { 1092 static struct i2c_board_info am335x_i2c_boardinfo1[] = {
1092 { 1093 {
1093 I2C_BOARD_INFO("tlv320aic3x", 0x1b), 1094 I2C_BOARD_INFO("tlv320aic3x", 0x1b),
1094 }, 1095 },
1095 { 1096 {
1096 I2C_BOARD_INFO("lis331dlh", 0x18), 1097 I2C_BOARD_INFO("lis331dlh", 0x18),
1097 .platform_data = &lis331dlh_pdata, 1098 .platform_data = &lis331dlh_pdata,
1098 }, 1099 },
1099 { 1100 {
1100 I2C_BOARD_INFO("tsl2550", 0x39), 1101 I2C_BOARD_INFO("tsl2550", 0x39),
1101 }, 1102 },
1102 { 1103 {
1103 I2C_BOARD_INFO("tmp275", 0x48), 1104 I2C_BOARD_INFO("tmp275", 0x48),
1104 }, 1105 },
1105 }; 1106 };
1106 1107
1107 static void i2c1_init(int evm_id, int profile) 1108 static void i2c1_init(int evm_id, int profile)
1108 { 1109 {
1109 setup_pin_mux(i2c1_pin_mux); 1110 setup_pin_mux(i2c1_pin_mux);
1110 omap_register_i2c_bus(2, 100, am335x_i2c_boardinfo1, 1111 omap_register_i2c_bus(2, 100, am335x_i2c_boardinfo1,
1111 ARRAY_SIZE(am335x_i2c_boardinfo1)); 1112 ARRAY_SIZE(am335x_i2c_boardinfo1));
1112 return; 1113 return;
1113 } 1114 }
1114 1115
1115 /* Setup McASP 1 */ 1116 /* Setup McASP 1 */
1116 static void mcasp1_init(int evm_id, int profile) 1117 static void mcasp1_init(int evm_id, int profile)
1117 { 1118 {
1118 /* Configure McASP */ 1119 /* Configure McASP */
1119 setup_pin_mux(mcasp1_pin_mux); 1120 setup_pin_mux(mcasp1_pin_mux);
1120 am335x_register_mcasp1(&am335x_evm_snd_data1); 1121 am335x_register_mcasp1(&am335x_evm_snd_data1);
1121 return; 1122 return;
1122 } 1123 }
1123 1124
1124 static void mmc1_init(int evm_id, int profile) 1125 static void mmc1_init(int evm_id, int profile)
1125 { 1126 {
1126 setup_pin_mux(mmc1_pin_mux); 1127 setup_pin_mux(mmc1_pin_mux);
1127 1128
1128 am335x_mmc[1].mmc = 2; 1129 am335x_mmc[1].mmc = 2;
1129 am335x_mmc[1].caps = MMC_CAP_4_BIT_DATA; 1130 am335x_mmc[1].caps = MMC_CAP_4_BIT_DATA;
1130 am335x_mmc[1].gpio_cd = GPIO_TO_PIN(3, 15); 1131 am335x_mmc[1].gpio_cd = GPIO_TO_PIN(3, 15);
1131 am335x_mmc[1].gpio_wp = GPIO_TO_PIN(0, 14); 1132 am335x_mmc[1].gpio_wp = GPIO_TO_PIN(0, 14);
1132 am335x_mmc[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */ 1133 am335x_mmc[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */
1133 1134
1134 /* mmc will be initialized when mmc0_init is called */ 1135 /* mmc will be initialized when mmc0_init is called */
1135 return; 1136 return;
1136 } 1137 }
1137 1138
1138 static void mmc2_wl12xx_init(int evm_id, int profile) 1139 static void mmc2_wl12xx_init(int evm_id, int profile)
1139 { 1140 {
1140 setup_pin_mux(mmc2_wl12xx_pin_mux); 1141 setup_pin_mux(mmc2_wl12xx_pin_mux);
1141 1142
1142 am335x_mmc[1].mmc = 3; 1143 am335x_mmc[1].mmc = 3;
1143 am335x_mmc[1].name = "wl1271"; 1144 am335x_mmc[1].name = "wl1271";
1144 am335x_mmc[1].caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD 1145 am335x_mmc[1].caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD
1145 | MMC_PM_KEEP_POWER; 1146 | MMC_PM_KEEP_POWER;
1146 am335x_mmc[1].nonremovable = true; 1147 am335x_mmc[1].nonremovable = true;
1147 am335x_mmc[1].gpio_cd = -EINVAL; 1148 am335x_mmc[1].gpio_cd = -EINVAL;
1148 am335x_mmc[1].gpio_wp = -EINVAL; 1149 am335x_mmc[1].gpio_wp = -EINVAL;
1149 am335x_mmc[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */ 1150 am335x_mmc[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */
1150 1151
1151 /* mmc will be initialized when mmc0_init is called */ 1152 /* mmc will be initialized when mmc0_init is called */
1152 return; 1153 return;
1153 } 1154 }
1154 1155
1155 static void uart1_wl12xx_init(int evm_id, int profile) 1156 static void uart1_wl12xx_init(int evm_id, int profile)
1156 { 1157 {
1157 setup_pin_mux(uart1_wl12xx_pin_mux); 1158 setup_pin_mux(uart1_wl12xx_pin_mux);
1158 } 1159 }
1159 1160
1160 static void wl12xx_bluetooth_enable(void) 1161 static void wl12xx_bluetooth_enable(void)
1161 { 1162 {
1162 int status = gpio_request(am335xevm_wlan_data.bt_enable_gpio, 1163 int status = gpio_request(am335xevm_wlan_data.bt_enable_gpio,
1163 "bt_en\n"); 1164 "bt_en\n");
1164 if (status < 0) 1165 if (status < 0)
1165 pr_err("Failed to request gpio for bt_enable"); 1166 pr_err("Failed to request gpio for bt_enable");
1166 1167
1167 pr_info("Configure Bluetooth Enable pin...\n"); 1168 pr_info("Configure Bluetooth Enable pin...\n");
1168 gpio_direction_output(am335xevm_wlan_data.bt_enable_gpio, 0); 1169 gpio_direction_output(am335xevm_wlan_data.bt_enable_gpio, 0);
1169 } 1170 }
1170 1171
1171 static int wl12xx_set_power(struct device *dev, int slot, int on, int vdd) 1172 static int wl12xx_set_power(struct device *dev, int slot, int on, int vdd)
1172 { 1173 {
1173 if (on) { 1174 if (on) {
1174 gpio_set_value(am335xevm_wlan_data.wlan_enable_gpio, 1); 1175 gpio_set_value(am335xevm_wlan_data.wlan_enable_gpio, 1);
1175 mdelay(70); 1176 mdelay(70);
1176 } 1177 }
1177 else 1178 else
1178 gpio_set_value(am335xevm_wlan_data.wlan_enable_gpio, 0); 1179 gpio_set_value(am335xevm_wlan_data.wlan_enable_gpio, 0);
1179 1180
1180 return 0; 1181 return 0;
1181 } 1182 }
1182 1183
1183 static void wl12xx_init(int evm_id, int profile) 1184 static void wl12xx_init(int evm_id, int profile)
1184 { 1185 {
1185 struct device *dev; 1186 struct device *dev;
1186 struct omap_mmc_platform_data *pdata; 1187 struct omap_mmc_platform_data *pdata;
1187 int ret; 1188 int ret;
1188 1189
1189 /* Register WLAN and BT enable pins based on the evm board revision */ 1190 /* Register WLAN and BT enable pins based on the evm board revision */
1190 if (gp_evm_revision == GP_EVM_REV_IS_1_1A) { 1191 if (gp_evm_revision == GP_EVM_REV_IS_1_1A) {
1191 am335xevm_wlan_data.wlan_enable_gpio = GPIO_TO_PIN(1, 16); 1192 am335xevm_wlan_data.wlan_enable_gpio = GPIO_TO_PIN(1, 16);
1192 am335xevm_wlan_data.bt_enable_gpio = GPIO_TO_PIN(3, 21); 1193 am335xevm_wlan_data.bt_enable_gpio = GPIO_TO_PIN(3, 21);
1193 } 1194 }
1194 else { 1195 else {
1195 am335xevm_wlan_data.wlan_enable_gpio = GPIO_TO_PIN(1, 30); 1196 am335xevm_wlan_data.wlan_enable_gpio = GPIO_TO_PIN(1, 30);
1196 am335xevm_wlan_data.bt_enable_gpio = GPIO_TO_PIN(1, 31); 1197 am335xevm_wlan_data.bt_enable_gpio = GPIO_TO_PIN(1, 31);
1197 } 1198 }
1198 1199
1199 wl12xx_bluetooth_enable(); 1200 wl12xx_bluetooth_enable();
1200 1201
1201 if (wl12xx_set_platform_data(&am335xevm_wlan_data)) 1202 if (wl12xx_set_platform_data(&am335xevm_wlan_data))
1202 pr_err("error setting wl12xx data\n"); 1203 pr_err("error setting wl12xx data\n");
1203 1204
1204 dev = am335x_mmc[1].dev; 1205 dev = am335x_mmc[1].dev;
1205 if (!dev) { 1206 if (!dev) {
1206 pr_err("wl12xx mmc device initialization failed\n"); 1207 pr_err("wl12xx mmc device initialization failed\n");
1207 goto out; 1208 goto out;
1208 } 1209 }
1209 1210
1210 pdata = dev->platform_data; 1211 pdata = dev->platform_data;
1211 if (!pdata) { 1212 if (!pdata) {
1212 pr_err("Platfrom data of wl12xx device not set\n"); 1213 pr_err("Platfrom data of wl12xx device not set\n");
1213 goto out; 1214 goto out;
1214 } 1215 }
1215 1216
1216 ret = gpio_request_one(am335xevm_wlan_data.wlan_enable_gpio, 1217 ret = gpio_request_one(am335xevm_wlan_data.wlan_enable_gpio,
1217 GPIOF_OUT_INIT_LOW, "wlan_en"); 1218 GPIOF_OUT_INIT_LOW, "wlan_en");
1218 if (ret) { 1219 if (ret) {
1219 pr_err("Error requesting wlan enable gpio: %d\n", ret); 1220 pr_err("Error requesting wlan enable gpio: %d\n", ret);
1220 goto out; 1221 goto out;
1221 } 1222 }
1222 1223
1223 if (gp_evm_revision == GP_EVM_REV_IS_1_1A) 1224 if (gp_evm_revision == GP_EVM_REV_IS_1_1A)
1224 setup_pin_mux(wl12xx_pin_mux_evm_rev1_1a); 1225 setup_pin_mux(wl12xx_pin_mux_evm_rev1_1a);
1225 else 1226 else
1226 setup_pin_mux(wl12xx_pin_mux_evm_rev1_0); 1227 setup_pin_mux(wl12xx_pin_mux_evm_rev1_0);
1227 1228
1228 pdata->slots[0].set_power = wl12xx_set_power; 1229 pdata->slots[0].set_power = wl12xx_set_power;
1229 out: 1230 out:
1230 return; 1231 return;
1231 } 1232 }
1232 1233
1233 static void d_can_init(int evm_id, int profile) 1234 static void d_can_init(int evm_id, int profile)
1234 { 1235 {
1235 switch (evm_id) { 1236 switch (evm_id) {
1236 case IND_AUT_MTR_EVM: 1237 case IND_AUT_MTR_EVM:
1237 if ((profile == PROFILE_0) || (profile == PROFILE_1)) { 1238 if ((profile == PROFILE_0) || (profile == PROFILE_1)) {
1238 setup_pin_mux(d_can_ia_pin_mux); 1239 setup_pin_mux(d_can_ia_pin_mux);
1239 /* Instance Zero */ 1240 /* Instance Zero */
1240 am33xx_d_can_init(0); 1241 am33xx_d_can_init(0);
1241 } 1242 }
1242 break; 1243 break;
1243 case GEN_PURP_EVM: 1244 case GEN_PURP_EVM:
1244 if (profile == PROFILE_1) { 1245 if (profile == PROFILE_1) {
1245 setup_pin_mux(d_can_gp_pin_mux); 1246 setup_pin_mux(d_can_gp_pin_mux);
1246 /* Instance One */ 1247 /* Instance One */
1247 am33xx_d_can_init(1); 1248 am33xx_d_can_init(1);
1248 } 1249 }
1249 break; 1250 break;
1250 default: 1251 default:
1251 break; 1252 break;
1252 } 1253 }
1253 } 1254 }
1254 1255
1255 static void mmc0_init(int evm_id, int profile) 1256 static void mmc0_init(int evm_id, int profile)
1256 { 1257 {
1257 setup_pin_mux(mmc0_pin_mux); 1258 setup_pin_mux(mmc0_pin_mux);
1258 1259
1259 omap2_hsmmc_init(am335x_mmc); 1260 omap2_hsmmc_init(am335x_mmc);
1260 return; 1261 return;
1261 } 1262 }
1262 1263
1263 static void mmc0_no_cd_init(int evm_id, int profile) 1264 static void mmc0_no_cd_init(int evm_id, int profile)
1264 { 1265 {
1265 setup_pin_mux(mmc0_no_cd_pin_mux); 1266 setup_pin_mux(mmc0_no_cd_pin_mux);
1266 1267
1267 omap2_hsmmc_init(am335x_mmc); 1268 omap2_hsmmc_init(am335x_mmc);
1268 return; 1269 return;
1269 } 1270 }
1270 1271
1271 1272
1272 /* setup spi0 */ 1273 /* setup spi0 */
1273 static void spi0_init(int evm_id, int profile) 1274 static void spi0_init(int evm_id, int profile)
1274 { 1275 {
1275 setup_pin_mux(spi0_pin_mux); 1276 setup_pin_mux(spi0_pin_mux);
1276 spi_register_board_info(am335x_spi0_slave_info, 1277 spi_register_board_info(am335x_spi0_slave_info,
1277 ARRAY_SIZE(am335x_spi0_slave_info)); 1278 ARRAY_SIZE(am335x_spi0_slave_info));
1278 return; 1279 return;
1279 } 1280 }
1280 1281
1281 /* setup spi1 */ 1282 /* setup spi1 */
1282 static void spi1_init(int evm_id, int profile) 1283 static void spi1_init(int evm_id, int profile)
1283 { 1284 {
1284 setup_pin_mux(spi1_pin_mux); 1285 setup_pin_mux(spi1_pin_mux);
1285 spi_register_board_info(am335x_spi1_slave_info, 1286 spi_register_board_info(am335x_spi1_slave_info,
1286 ARRAY_SIZE(am335x_spi1_slave_info)); 1287 ARRAY_SIZE(am335x_spi1_slave_info));
1287 return; 1288 return;
1288 } 1289 }
1289 1290
1290 1291
1291 static int beaglebone_phy_fixup(struct phy_device *phydev) 1292 static int beaglebone_phy_fixup(struct phy_device *phydev)
1292 { 1293 {
1293 phydev->supported &= ~(SUPPORTED_100baseT_Half | 1294 phydev->supported &= ~(SUPPORTED_100baseT_Half |
1294 SUPPORTED_100baseT_Full); 1295 SUPPORTED_100baseT_Full);
1295 1296
1296 return 0; 1297 return 0;
1297 } 1298 }
1298 1299
1299 #ifdef CONFIG_TLK110_WORKAROUND 1300 #ifdef CONFIG_TLK110_WORKAROUND
1300 static int am335x_tlk110_phy_fixup(struct phy_device *phydev) 1301 static int am335x_tlk110_phy_fixup(struct phy_device *phydev)
1301 { 1302 {
1302 unsigned int val; 1303 unsigned int val;
1303 1304
1304 /* This is done as a workaround to support TLK110 rev1.0 phy */ 1305 /* This is done as a workaround to support TLK110 rev1.0 phy */
1305 val = phy_read(phydev, TLK110_COARSEGAIN_REG); 1306 val = phy_read(phydev, TLK110_COARSEGAIN_REG);
1306 phy_write(phydev, TLK110_COARSEGAIN_REG, (val | TLK110_COARSEGAIN_VAL)); 1307 phy_write(phydev, TLK110_COARSEGAIN_REG, (val | TLK110_COARSEGAIN_VAL));
1307 1308
1308 val = phy_read(phydev, TLK110_LPFHPF_REG); 1309 val = phy_read(phydev, TLK110_LPFHPF_REG);
1309 phy_write(phydev, TLK110_LPFHPF_REG, (val | TLK110_LPFHPF_VAL)); 1310 phy_write(phydev, TLK110_LPFHPF_REG, (val | TLK110_LPFHPF_VAL));
1310 1311
1311 val = phy_read(phydev, TLK110_SPAREANALOG_REG); 1312 val = phy_read(phydev, TLK110_SPAREANALOG_REG);
1312 phy_write(phydev, TLK110_SPAREANALOG_REG, (val | TLK110_SPANALOG_VAL)); 1313 phy_write(phydev, TLK110_SPAREANALOG_REG, (val | TLK110_SPANALOG_VAL));
1313 1314
1314 val = phy_read(phydev, TLK110_VRCR_REG); 1315 val = phy_read(phydev, TLK110_VRCR_REG);
1315 phy_write(phydev, TLK110_VRCR_REG, (val | TLK110_VRCR_VAL)); 1316 phy_write(phydev, TLK110_VRCR_REG, (val | TLK110_VRCR_VAL));
1316 1317
1317 val = phy_read(phydev, TLK110_SETFFE_REG); 1318 val = phy_read(phydev, TLK110_SETFFE_REG);
1318 phy_write(phydev, TLK110_SETFFE_REG, (val | TLK110_SETFFE_VAL)); 1319 phy_write(phydev, TLK110_SETFFE_REG, (val | TLK110_SETFFE_VAL));
1319 1320
1320 val = phy_read(phydev, TLK110_FTSP_REG); 1321 val = phy_read(phydev, TLK110_FTSP_REG);
1321 phy_write(phydev, TLK110_FTSP_REG, (val | TLK110_FTSP_VAL)); 1322 phy_write(phydev, TLK110_FTSP_REG, (val | TLK110_FTSP_VAL));
1322 1323
1323 val = phy_read(phydev, TLK110_ALFATPIDL_REG); 1324 val = phy_read(phydev, TLK110_ALFATPIDL_REG);
1324 phy_write(phydev, TLK110_ALFATPIDL_REG, (val | TLK110_ALFATPIDL_VAL)); 1325 phy_write(phydev, TLK110_ALFATPIDL_REG, (val | TLK110_ALFATPIDL_VAL));
1325 1326
1326 val = phy_read(phydev, TLK110_PSCOEF21_REG); 1327 val = phy_read(phydev, TLK110_PSCOEF21_REG);
1327 phy_write(phydev, TLK110_PSCOEF21_REG, (val | TLK110_PSCOEF21_VAL)); 1328 phy_write(phydev, TLK110_PSCOEF21_REG, (val | TLK110_PSCOEF21_VAL));
1328 1329
1329 val = phy_read(phydev, TLK110_PSCOEF3_REG); 1330 val = phy_read(phydev, TLK110_PSCOEF3_REG);
1330 phy_write(phydev, TLK110_PSCOEF3_REG, (val | TLK110_PSCOEF3_VAL)); 1331 phy_write(phydev, TLK110_PSCOEF3_REG, (val | TLK110_PSCOEF3_VAL));
1331 1332
1332 val = phy_read(phydev, TLK110_ALFAFACTOR1_REG); 1333 val = phy_read(phydev, TLK110_ALFAFACTOR1_REG);
1333 phy_write(phydev, TLK110_ALFAFACTOR1_REG, (val | TLK110_ALFACTOR1_VAL)); 1334 phy_write(phydev, TLK110_ALFAFACTOR1_REG, (val | TLK110_ALFACTOR1_VAL));
1334 1335
1335 val = phy_read(phydev, TLK110_ALFAFACTOR2_REG); 1336 val = phy_read(phydev, TLK110_ALFAFACTOR2_REG);
1336 phy_write(phydev, TLK110_ALFAFACTOR2_REG, (val | TLK110_ALFACTOR2_VAL)); 1337 phy_write(phydev, TLK110_ALFAFACTOR2_REG, (val | TLK110_ALFACTOR2_VAL));
1337 1338
1338 val = phy_read(phydev, TLK110_CFGPS_REG); 1339 val = phy_read(phydev, TLK110_CFGPS_REG);
1339 phy_write(phydev, TLK110_CFGPS_REG, (val | TLK110_CFGPS_VAL)); 1340 phy_write(phydev, TLK110_CFGPS_REG, (val | TLK110_CFGPS_VAL));
1340 1341
1341 val = phy_read(phydev, TLK110_FTSPTXGAIN_REG); 1342 val = phy_read(phydev, TLK110_FTSPTXGAIN_REG);
1342 phy_write(phydev, TLK110_FTSPTXGAIN_REG, (val | TLK110_FTSPTXGAIN_VAL)); 1343 phy_write(phydev, TLK110_FTSPTXGAIN_REG, (val | TLK110_FTSPTXGAIN_VAL));
1343 1344
1344 val = phy_read(phydev, TLK110_SWSCR3_REG); 1345 val = phy_read(phydev, TLK110_SWSCR3_REG);
1345 phy_write(phydev, TLK110_SWSCR3_REG, (val | TLK110_SWSCR3_VAL)); 1346 phy_write(phydev, TLK110_SWSCR3_REG, (val | TLK110_SWSCR3_VAL));
1346 1347
1347 val = phy_read(phydev, TLK110_SCFALLBACK_REG); 1348 val = phy_read(phydev, TLK110_SCFALLBACK_REG);
1348 phy_write(phydev, TLK110_SCFALLBACK_REG, (val | TLK110_SCFALLBACK_VAL)); 1349 phy_write(phydev, TLK110_SCFALLBACK_REG, (val | TLK110_SCFALLBACK_VAL));
1349 1350
1350 val = phy_read(phydev, TLK110_PHYRCR_REG); 1351 val = phy_read(phydev, TLK110_PHYRCR_REG);
1351 phy_write(phydev, TLK110_PHYRCR_REG, (val | TLK110_PHYRCR_VAL)); 1352 phy_write(phydev, TLK110_PHYRCR_REG, (val | TLK110_PHYRCR_VAL));
1352 1353
1353 return 0; 1354 return 0;
1354 } 1355 }
1355 #endif 1356 #endif
1356 1357
1357 static void profibus_init(int evm_id, int profile) 1358 static void profibus_init(int evm_id, int profile)
1358 { 1359 {
1359 setup_pin_mux(profibus_pin_mux); 1360 setup_pin_mux(profibus_pin_mux);
1360 return; 1361 return;
1361 } 1362 }
1362 1363
1363 /* Low-Cost EVM */ 1364 /* Low-Cost EVM */
1364 static struct evm_dev_cfg low_cost_evm_dev_cfg[] = { 1365 static struct evm_dev_cfg low_cost_evm_dev_cfg[] = {
1365 {rgmii1_init, DEV_ON_BASEBOARD, PROFILE_NONE}, 1366 {rgmii1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1366 {usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE}, 1367 {usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1367 {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE}, 1368 {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1368 {evm_nand_init, DEV_ON_BASEBOARD, PROFILE_NONE}, 1369 {evm_nand_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1369 {NULL, 0, 0}, 1370 {NULL, 0, 0},
1370 }; 1371 };
1371 1372
1372 /* General Purpose EVM */ 1373 /* General Purpose EVM */
1373 static struct evm_dev_cfg gen_purp_evm_dev_cfg[] = { 1374 static struct evm_dev_cfg gen_purp_evm_dev_cfg[] = {
1374 {enable_ecap0, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 | 1375 {enable_ecap0, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 |
1375 PROFILE_2 | PROFILE_7) }, 1376 PROFILE_2 | PROFILE_7) },
1376 {lcdc_init, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 | 1377 {lcdc_init, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 |
1377 PROFILE_2 | PROFILE_7) }, 1378 PROFILE_2 | PROFILE_7) },
1378 {tsc_init, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 | 1379 {tsc_init, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 |
1379 PROFILE_2 | PROFILE_7) }, 1380 PROFILE_2 | PROFILE_7) },
1380 {rgmii1_init, DEV_ON_BASEBOARD, PROFILE_ALL}, 1381 {rgmii1_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1381 {rgmii2_init, DEV_ON_DGHTR_BRD, (PROFILE_1 | PROFILE_2 | 1382 {rgmii2_init, DEV_ON_DGHTR_BRD, (PROFILE_1 | PROFILE_2 |
1382 PROFILE_4 | PROFILE_6) }, 1383 PROFILE_4 | PROFILE_6) },
1383 {usb0_init, DEV_ON_BASEBOARD, PROFILE_ALL}, 1384 {usb0_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1384 {usb1_init, DEV_ON_BASEBOARD, PROFILE_ALL}, 1385 {usb1_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1385 {evm_nand_init, DEV_ON_DGHTR_BRD, 1386 {evm_nand_init, DEV_ON_DGHTR_BRD,
1386 (PROFILE_ALL & ~PROFILE_2 & ~PROFILE_3)}, 1387 (PROFILE_ALL & ~PROFILE_2 & ~PROFILE_3)},
1387 {i2c1_init, DEV_ON_DGHTR_BRD, (PROFILE_ALL & ~PROFILE_2)}, 1388 {i2c1_init, DEV_ON_DGHTR_BRD, (PROFILE_ALL & ~PROFILE_2)},
1388 {mcasp1_init, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_3 | PROFILE_7) }, 1389 {mcasp1_init, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_3 | PROFILE_7) },
1389 {mmc1_init, DEV_ON_DGHTR_BRD, PROFILE_2}, 1390 {mmc1_init, DEV_ON_DGHTR_BRD, PROFILE_2},
1390 {mmc2_wl12xx_init, DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 | 1391 {mmc2_wl12xx_init, DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 |
1391 PROFILE_5)}, 1392 PROFILE_5)},
1392 {mmc0_init, DEV_ON_BASEBOARD, (PROFILE_ALL & ~PROFILE_5)}, 1393 {mmc0_init, DEV_ON_BASEBOARD, (PROFILE_ALL & ~PROFILE_5)},
1393 {mmc0_no_cd_init, DEV_ON_BASEBOARD, PROFILE_5}, 1394 {mmc0_no_cd_init, DEV_ON_BASEBOARD, PROFILE_5},
1394 {spi0_init, DEV_ON_DGHTR_BRD, PROFILE_2}, 1395 {spi0_init, DEV_ON_DGHTR_BRD, PROFILE_2},
1395 {uart1_wl12xx_init, DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 | 1396 {uart1_wl12xx_init, DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 |
1396 PROFILE_5)}, 1397 PROFILE_5)},
1397 {wl12xx_init, DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 | PROFILE_5)}, 1398 {wl12xx_init, DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 | PROFILE_5)},
1398 {d_can_init, DEV_ON_DGHTR_BRD, PROFILE_1}, 1399 {d_can_init, DEV_ON_DGHTR_BRD, PROFILE_1},
1399 #ifdef CONFIG_KEYBOARD_MATRIX 1400 #ifdef CONFIG_KEYBOARD_MATRIX
1400 {matrix_keypad_init, DEV_ON_DGHTR_BRD, PROFILE_0}, 1401 {matrix_keypad_init, DEV_ON_DGHTR_BRD, PROFILE_0},
1401 #endif 1402 #endif
1402 #ifdef CONFIG_KEYBOARD_GPIO 1403 #ifdef CONFIG_KEYBOARD_GPIO
1403 {volume_keys_init, DEV_ON_DGHTR_BRD, PROFILE_0}, 1404 {volume_keys_init, DEV_ON_DGHTR_BRD, PROFILE_0},
1404 #endif 1405 #endif
1405 {NULL, 0, 0}, 1406 {NULL, 0, 0},
1406 }; 1407 };
1407 1408
1408 /* Industrial Auto Motor Control EVM */ 1409 /* Industrial Auto Motor Control EVM */
1409 static struct evm_dev_cfg ind_auto_mtrl_evm_dev_cfg[] = { 1410 static struct evm_dev_cfg ind_auto_mtrl_evm_dev_cfg[] = {
1410 {mii1_init, DEV_ON_DGHTR_BRD, PROFILE_ALL}, 1411 {mii1_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
1411 {usb0_init, DEV_ON_BASEBOARD, PROFILE_ALL}, 1412 {usb0_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1412 {usb1_init, DEV_ON_BASEBOARD, PROFILE_ALL}, 1413 {usb1_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1413 {profibus_init, DEV_ON_DGHTR_BRD, PROFILE_ALL}, 1414 {profibus_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
1414 {evm_nand_init, DEV_ON_DGHTR_BRD, PROFILE_ALL}, 1415 {evm_nand_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
1415 {spi1_init, DEV_ON_DGHTR_BRD, PROFILE_ALL}, 1416 {spi1_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
1416 {uart3_init, DEV_ON_DGHTR_BRD, PROFILE_ALL}, 1417 {uart3_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
1417 {i2c1_init, DEV_ON_BASEBOARD, PROFILE_ALL}, 1418 {i2c1_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1418 {mmc0_no_cd_init, DEV_ON_BASEBOARD, PROFILE_ALL}, 1419 {mmc0_no_cd_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1419 {NULL, 0, 0}, 1420 {NULL, 0, 0},
1420 }; 1421 };
1421 1422
1422 /* IP-Phone EVM */ 1423 /* IP-Phone EVM */
1423 static struct evm_dev_cfg ip_phn_evm_dev_cfg[] = { 1424 static struct evm_dev_cfg ip_phn_evm_dev_cfg[] = {
1424 {enable_ecap0, DEV_ON_DGHTR_BRD, PROFILE_NONE}, 1425 {enable_ecap0, DEV_ON_DGHTR_BRD, PROFILE_NONE},
1425 {lcdc_init, DEV_ON_DGHTR_BRD, PROFILE_NONE}, 1426 {lcdc_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
1426 {tsc_init, DEV_ON_DGHTR_BRD, PROFILE_NONE}, 1427 {tsc_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
1427 {rgmii1_init, DEV_ON_BASEBOARD, PROFILE_NONE}, 1428 {rgmii1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1428 {rgmii2_init, DEV_ON_DGHTR_BRD, PROFILE_NONE}, 1429 {rgmii2_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
1429 {usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE}, 1430 {usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1430 {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE}, 1431 {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1431 {evm_nand_init, DEV_ON_DGHTR_BRD, PROFILE_NONE}, 1432 {evm_nand_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
1432 {i2c1_init, DEV_ON_BASEBOARD, PROFILE_NONE}, 1433 {i2c1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1433 {mcasp1_init, DEV_ON_DGHTR_BRD, PROFILE_NONE}, 1434 {mcasp1_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
1434 {mmc0_init, DEV_ON_BASEBOARD, PROFILE_NONE}, 1435 {mmc0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1435 {NULL, 0, 0}, 1436 {NULL, 0, 0},
1436 }; 1437 };
1437 1438
1438 /* Beaglebone < Rev A3 */ 1439 /* Beaglebone < Rev A3 */
1439 static struct evm_dev_cfg beaglebone_old_dev_cfg[] = { 1440 static struct evm_dev_cfg beaglebone_old_dev_cfg[] = {
1440 {rmii1_init, DEV_ON_BASEBOARD, PROFILE_NONE}, 1441 {rmii1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1441 {usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE}, 1442 {usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1442 {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE}, 1443 {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1443 {mmc0_init, DEV_ON_BASEBOARD, PROFILE_NONE}, 1444 {mmc0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1444 {NULL, 0, 0}, 1445 {NULL, 0, 0},
1445 }; 1446 };
1446 1447
1447 /* Beaglebone Rev A3 and after */ 1448 /* Beaglebone Rev A3 and after */
1448 static struct evm_dev_cfg beaglebone_dev_cfg[] = { 1449 static struct evm_dev_cfg beaglebone_dev_cfg[] = {
1449 {mii1_init, DEV_ON_BASEBOARD, PROFILE_NONE}, 1450 {mii1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1450 {usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE}, 1451 {usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1451 {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE}, 1452 {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1452 {mmc0_init, DEV_ON_BASEBOARD, PROFILE_NONE}, 1453 {mmc0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1453 {NULL, 0, 0}, 1454 {NULL, 0, 0},
1454 }; 1455 };
1455 1456
1456 static void setup_low_cost_evm(void) 1457 static void setup_low_cost_evm(void)
1457 { 1458 {
1458 pr_info("The board is a AM335x Low Cost EVM.\n"); 1459 pr_info("The board is a AM335x Low Cost EVM.\n");
1459 1460
1460 _configure_device(LOW_COST_EVM, low_cost_evm_dev_cfg, PROFILE_NONE); 1461 _configure_device(LOW_COST_EVM, low_cost_evm_dev_cfg, PROFILE_NONE);
1461 } 1462 }
1462 1463
1463 static void setup_general_purpose_evm(void) 1464 static void setup_general_purpose_evm(void)
1464 { 1465 {
1465 u32 prof_sel = am335x_get_profile_selection(); 1466 u32 prof_sel = am335x_get_profile_selection();
1466 pr_info("The board is general purpose EVM in profile %d\n", prof_sel); 1467 pr_info("The board is general purpose EVM in profile %d\n", prof_sel);
1467 1468
1468 if (!strncmp("1.1A", config.version, 4)) { 1469 if (!strncmp("1.1A", config.version, 4)) {
1469 gp_evm_revision = GP_EVM_REV_IS_1_1A; 1470 gp_evm_revision = GP_EVM_REV_IS_1_1A;
1470 } else if (!strncmp("1.0", config.version, 3)) { 1471 } else if (!strncmp("1.0", config.version, 3)) {
1471 gp_evm_revision = GP_EVM_REV_IS_1_0; 1472 gp_evm_revision = GP_EVM_REV_IS_1_0;
1472 } else { 1473 } else {
1473 pr_err("Found invalid GP EVM revision, falling back to Rev1.1A"); 1474 pr_err("Found invalid GP EVM revision, falling back to Rev1.1A");
1474 gp_evm_revision = GP_EVM_REV_IS_1_1A; 1475 gp_evm_revision = GP_EVM_REV_IS_1_1A;
1475 } 1476 }
1476 1477
1477 if (gp_evm_revision == GP_EVM_REV_IS_1_0) 1478 if (gp_evm_revision == GP_EVM_REV_IS_1_0)
1478 gigabit_enable = 0; 1479 gigabit_enable = 0;
1479 else if (gp_evm_revision == GP_EVM_REV_IS_1_1A) 1480 else if (gp_evm_revision == GP_EVM_REV_IS_1_1A)
1480 gigabit_enable = 1; 1481 gigabit_enable = 1;
1481 1482
1482 _configure_device(GEN_PURP_EVM, gen_purp_evm_dev_cfg, (1L << prof_sel)); 1483 _configure_device(GEN_PURP_EVM, gen_purp_evm_dev_cfg, (1L << prof_sel));
1483 } 1484 }
1484 1485
1485 static void setup_ind_auto_motor_ctrl_evm(void) 1486 static void setup_ind_auto_motor_ctrl_evm(void)
1486 { 1487 {
1487 u32 prof_sel = am335x_get_profile_selection(); 1488 u32 prof_sel = am335x_get_profile_selection();
1488 1489
1489 pr_info("The board is an industrial automation EVM in profile %d\n", 1490 pr_info("The board is an industrial automation EVM in profile %d\n",
1490 prof_sel); 1491 prof_sel);
1491 1492
1492 /* Only Profile 0 is supported */ 1493 /* Only Profile 0 is supported */
1493 if ((1L << prof_sel) != PROFILE_0) { 1494 if ((1L << prof_sel) != PROFILE_0) {
1494 pr_err("AM335X: Only Profile 0 is supported\n"); 1495 pr_err("AM335X: Only Profile 0 is supported\n");
1495 pr_err("Assuming profile 0 & continuing\n"); 1496 pr_err("Assuming profile 0 & continuing\n");
1496 prof_sel = PROFILE_0; 1497 prof_sel = PROFILE_0;
1497 } 1498 }
1498 1499
1499 _configure_device(IND_AUT_MTR_EVM, ind_auto_mtrl_evm_dev_cfg, 1500 _configure_device(IND_AUT_MTR_EVM, ind_auto_mtrl_evm_dev_cfg,
1500 PROFILE_0); 1501 PROFILE_0);
1501 1502
1502 /* Fillup global evmid */ 1503 /* Fillup global evmid */
1503 am33xx_evmid_fillup(IND_AUT_MTR_EVM); 1504 am33xx_evmid_fillup(IND_AUT_MTR_EVM);
1504 1505
1505 /* Initialize TLK110 PHY registers for phy version 1.0 */ 1506 /* Initialize TLK110 PHY registers for phy version 1.0 */
1506 am335x_tlk110_phy_init(); 1507 am335x_tlk110_phy_init();
1507 1508
1508 1509
1509 } 1510 }
1510 1511
1511 static void setup_ip_phone_evm(void) 1512 static void setup_ip_phone_evm(void)
1512 { 1513 {
1513 pr_info("The board is an IP phone EVM\n"); 1514 pr_info("The board is an IP phone EVM\n");
1514 1515
1515 _configure_device(IP_PHN_EVM, ip_phn_evm_dev_cfg, PROFILE_NONE); 1516 _configure_device(IP_PHN_EVM, ip_phn_evm_dev_cfg, PROFILE_NONE);
1516 } 1517 }
1517 1518
1518 /* BeagleBone < Rev A3 */ 1519 /* BeagleBone < Rev A3 */
1519 static void setup_beaglebone_old(void) 1520 static void setup_beaglebone_old(void)
1520 { 1521 {
1521 pr_info("The board is a AM335x Beaglebone < Rev A3.\n"); 1522 pr_info("The board is a AM335x Beaglebone < Rev A3.\n");
1522 1523
1523 /* Beagle Bone has Micro-SD slot which doesn't have Write Protect pin */ 1524 /* Beagle Bone has Micro-SD slot which doesn't have Write Protect pin */
1524 am335x_mmc[0].gpio_wp = -EINVAL; 1525 am335x_mmc[0].gpio_wp = -EINVAL;
1525 1526
1526 _configure_device(LOW_COST_EVM, beaglebone_old_dev_cfg, PROFILE_NONE); 1527 _configure_device(LOW_COST_EVM, beaglebone_old_dev_cfg, PROFILE_NONE);
1527 1528
1528 phy_register_fixup_for_uid(BBB_PHY_ID, BBB_PHY_MASK, 1529 phy_register_fixup_for_uid(BBB_PHY_ID, BBB_PHY_MASK,
1529 beaglebone_phy_fixup); 1530 beaglebone_phy_fixup);
1530 } 1531 }
1531 1532
1532 /* BeagleBone after Rev A3 */ 1533 /* BeagleBone after Rev A3 */
1533 static void setup_beaglebone(void) 1534 static void setup_beaglebone(void)
1534 { 1535 {
1535 pr_info("The board is a AM335x Beaglebone.\n"); 1536 pr_info("The board is a AM335x Beaglebone.\n");
1536 1537
1537 /* Beagle Bone has Micro-SD slot which doesn't have Write Protect pin */ 1538 /* Beagle Bone has Micro-SD slot which doesn't have Write Protect pin */
1538 am335x_mmc[0].gpio_wp = -EINVAL; 1539 am335x_mmc[0].gpio_wp = -EINVAL;
1539 1540
1540 _configure_device(LOW_COST_EVM, beaglebone_dev_cfg, PROFILE_NONE); 1541 _configure_device(LOW_COST_EVM, beaglebone_dev_cfg, PROFILE_NONE);
1541 } 1542 }
1542 1543
1543 1544
1544 static void am335x_setup_daughter_board(struct memory_accessor *m, void *c) 1545 static void am335x_setup_daughter_board(struct memory_accessor *m, void *c)
1545 { 1546 {
1546 u8 tmp; 1547 u8 tmp;
1547 int ret; 1548 int ret;
1548 1549
1549 /* 1550 /*
1550 * try reading a byte from the EEPROM to see if it is 1551 * try reading a byte from the EEPROM to see if it is
1551 * present. We could read a lot more, but that would 1552 * present. We could read a lot more, but that would
1552 * just slow the boot process and we have all the information 1553 * just slow the boot process and we have all the information
1553 * we need from the EEPROM on the base board anyway. 1554 * we need from the EEPROM on the base board anyway.
1554 */ 1555 */
1555 ret = m->read(m, &tmp, 0, sizeof(u8)); 1556 ret = m->read(m, &tmp, 0, sizeof(u8));
1556 if (ret == sizeof(u8)) { 1557 if (ret == sizeof(u8)) {
1557 pr_info("Detected a daughter card on AM335x EVM.."); 1558 pr_info("Detected a daughter card on AM335x EVM..");
1558 daughter_brd_detected = true; 1559 daughter_brd_detected = true;
1559 } else { 1560 } else {
1560 pr_info("No daughter card found\n"); 1561 pr_info("No daughter card found\n");
1561 daughter_brd_detected = false; 1562 daughter_brd_detected = false;
1562 } 1563 }
1563 } 1564 }
1564 1565
1565 static void am335x_evm_setup(struct memory_accessor *mem_acc, void *context) 1566 static void am335x_evm_setup(struct memory_accessor *mem_acc, void *context)
1566 { 1567 {
1567 int ret; 1568 int ret;
1568 char tmp[10]; 1569 char tmp[10];
1569 1570
1570 /* 1st get the MAC address from EEPROM */ 1571 /* 1st get the MAC address from EEPROM */
1571 ret = mem_acc->read(mem_acc, (char *)&am335x_mac_addr, 1572 ret = mem_acc->read(mem_acc, (char *)&am335x_mac_addr,
1572 EEPROM_MAC_ADDRESS_OFFSET, sizeof(am335x_mac_addr)); 1573 EEPROM_MAC_ADDRESS_OFFSET, sizeof(am335x_mac_addr));
1573 1574
1574 if (ret != sizeof(am335x_mac_addr)) { 1575 if (ret != sizeof(am335x_mac_addr)) {
1575 pr_warning("AM335X: EVM Config read fail: %d\n", ret); 1576 pr_warning("AM335X: EVM Config read fail: %d\n", ret);
1576 return; 1577 return;
1577 } 1578 }
1578 1579
1579 /* Fillup global mac id */ 1580 /* Fillup global mac id */
1580 am33xx_cpsw_macidfillup(&am335x_mac_addr[0][0], 1581 am33xx_cpsw_macidfillup(&am335x_mac_addr[0][0],
1581 &am335x_mac_addr[1][0]); 1582 &am335x_mac_addr[1][0]);
1582 1583
1583 /* get board specific data */ 1584 /* get board specific data */
1584 ret = mem_acc->read(mem_acc, (char *)&config, 0, sizeof(config)); 1585 ret = mem_acc->read(mem_acc, (char *)&config, 0, sizeof(config));
1585 if (ret != sizeof(config)) { 1586 if (ret != sizeof(config)) {
1586 pr_warning("AM335X EVM config read fail, read %d bytes\n", ret); 1587 pr_warning("AM335X EVM config read fail, read %d bytes\n", ret);
1587 return; 1588 return;
1588 } 1589 }
1589 1590
1590 if (config.header != AM335X_EEPROM_HEADER) { 1591 if (config.header != AM335X_EEPROM_HEADER) {
1591 pr_warning("AM335X: wrong header 0x%x, expected 0x%x\n", 1592 pr_warning("AM335X: wrong header 0x%x, expected 0x%x\n",
1592 config.header, AM335X_EEPROM_HEADER); 1593 config.header, AM335X_EEPROM_HEADER);
1593 goto out; 1594 goto out;
1594 } 1595 }
1595 1596
1596 if (strncmp("A335", config.name, 4)) { 1597 if (strncmp("A335", config.name, 4)) {
1597 pr_err("Board %s doesn't look like an AM335x board\n", 1598 pr_err("Board %s doesn't look like an AM335x board\n",
1598 config.name); 1599 config.name);
1599 goto out; 1600 goto out;
1600 } 1601 }
1601 1602
1602 snprintf(tmp, sizeof(config.name) + 1, "%s", config.name); 1603 snprintf(tmp, sizeof(config.name) + 1, "%s", config.name);
1603 pr_info("Board name: %s\n", tmp); 1604 pr_info("Board name: %s\n", tmp);
1604 snprintf(tmp, sizeof(config.version) + 1, "%s", config.version); 1605 snprintf(tmp, sizeof(config.version) + 1, "%s", config.version);
1605 pr_info("Board version: %s\n", tmp); 1606 pr_info("Board version: %s\n", tmp);
1606 1607
1607 if (!strncmp("A335BONE", config.name, 8)) { 1608 if (!strncmp("A335BONE", config.name, 8)) {
1608 daughter_brd_detected = false; 1609 daughter_brd_detected = false;
1609 if(!strncmp("00A1", config.version, 4) || 1610 if(!strncmp("00A1", config.version, 4) ||
1610 !strncmp("00A2", config.version, 4)) 1611 !strncmp("00A2", config.version, 4))
1611 setup_beaglebone_old(); 1612 setup_beaglebone_old();
1612 else 1613 else
1613 setup_beaglebone(); 1614 setup_beaglebone();
1614 } else { 1615 } else {
1615 /* only 6 characters of options string used for now */ 1616 /* only 6 characters of options string used for now */
1616 snprintf(tmp, 7, "%s", config.opt); 1617 snprintf(tmp, 7, "%s", config.opt);
1617 pr_info("SKU: %s\n", tmp); 1618 pr_info("SKU: %s\n", tmp);
1618 1619
1619 if (!strncmp("SKU#00", config.opt, 6)) 1620 if (!strncmp("SKU#00", config.opt, 6))
1620 setup_low_cost_evm(); 1621 setup_low_cost_evm();
1621 else if (!strncmp("SKU#01", config.opt, 6)) 1622 else if (!strncmp("SKU#01", config.opt, 6))
1622 setup_general_purpose_evm(); 1623 setup_general_purpose_evm();
1623 else if (!strncmp("SKU#02", config.opt, 6)) 1624 else if (!strncmp("SKU#02", config.opt, 6))
1624 setup_ind_auto_motor_ctrl_evm(); 1625 setup_ind_auto_motor_ctrl_evm();
1625 else if (!strncmp("SKU#03", config.opt, 6)) 1626 else if (!strncmp("SKU#03", config.opt, 6))
1626 setup_ip_phone_evm(); 1627 setup_ip_phone_evm();
1627 else 1628 else
1628 goto out; 1629 goto out;
1629 } 1630 }
1630 /* Initialize cpsw after board detection is completed as board 1631 /* Initialize cpsw after board detection is completed as board
1631 * information is required for configuring phy address and hence 1632 * information is required for configuring phy address and hence
1632 * should be call only after board detection 1633 * should be call only after board detection
1633 */ 1634 */
1634 am33xx_cpsw_init(gigabit_enable); 1635 am33xx_cpsw_init(gigabit_enable);
1635 1636
1636 return; 1637 return;
1637 out: 1638 out:
1638 /* 1639 /*
1639 * If the EEPROM hasn't been programed or an incorrect header 1640 * If the EEPROM hasn't been programed or an incorrect header
1640 * or board name are read, assume this is an old beaglebone board 1641 * or board name are read, assume this is an old beaglebone board
1641 * (< Rev A3) 1642 * (< Rev A3)
1642 */ 1643 */
1643 pr_err("Could not detect any board, falling back to: " 1644 pr_err("Could not detect any board, falling back to: "
1644 "Beaglebone (< Rev A3) with no daughter card connected\n"); 1645 "Beaglebone (< Rev A3) with no daughter card connected\n");
1645 daughter_brd_detected = false; 1646 daughter_brd_detected = false;
1646 setup_beaglebone_old(); 1647 setup_beaglebone_old();
1647 1648
1648 /* Initialize cpsw after board detection is completed as board 1649 /* Initialize cpsw after board detection is completed as board
1649 * information is required for configuring phy address and hence 1650 * information is required for configuring phy address and hence
1650 * should be call only after board detection 1651 * should be call only after board detection
1651 */ 1652 */
1652 1653
1653 am33xx_cpsw_init(gigabit_enable); 1654 am33xx_cpsw_init(gigabit_enable);
1654 } 1655 }
1655 1656
1656 static struct at24_platform_data am335x_daughter_board_eeprom_info = { 1657 static struct at24_platform_data am335x_daughter_board_eeprom_info = {
1657 .byte_len = (256*1024) / 8, 1658 .byte_len = (256*1024) / 8,
1658 .page_size = 64, 1659 .page_size = 64,
1659 .flags = AT24_FLAG_ADDR16, 1660 .flags = AT24_FLAG_ADDR16,
1660 .setup = am335x_setup_daughter_board, 1661 .setup = am335x_setup_daughter_board,
1661 .context = (void *)NULL, 1662 .context = (void *)NULL,
1662 }; 1663 };
1663 1664
1664 static struct at24_platform_data am335x_baseboard_eeprom_info = { 1665 static struct at24_platform_data am335x_baseboard_eeprom_info = {
1665 .byte_len = (256*1024) / 8, 1666 .byte_len = (256*1024) / 8,
1666 .page_size = 64, 1667 .page_size = 64,
1667 .flags = AT24_FLAG_ADDR16, 1668 .flags = AT24_FLAG_ADDR16,
1668 .setup = am335x_evm_setup, 1669 .setup = am335x_evm_setup,
1669 .context = (void *)NULL, 1670 .context = (void *)NULL,
1670 }; 1671 };
1671 1672
1672 static struct regulator_init_data am335x_dummy; 1673 static struct regulator_init_data am335x_dummy;
1673 1674
1674 static struct regulator_consumer_supply am335x_vdd1_supply[] = { 1675 static struct regulator_consumer_supply am335x_vdd1_supply[] = {
1675 REGULATOR_SUPPLY("mpu", "mpu.0"), 1676 REGULATOR_SUPPLY("mpu", "mpu.0"),
1676 }; 1677 };
1677 1678
1678 static struct regulator_init_data am335x_vdd1 = { 1679 static struct regulator_init_data am335x_vdd1 = {
1679 .constraints = { 1680 .constraints = {
1680 .min_uV = 600000, 1681 .min_uV = 600000,
1681 .max_uV = 1500000, 1682 .max_uV = 1500000,
1682 .valid_modes_mask = REGULATOR_MODE_NORMAL, 1683 .valid_modes_mask = REGULATOR_MODE_NORMAL,
1683 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, 1684 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
1684 .always_on = 1, 1685 .always_on = 1,
1685 }, 1686 },
1686 .num_consumer_supplies = ARRAY_SIZE(am335x_vdd1_supply), 1687 .num_consumer_supplies = ARRAY_SIZE(am335x_vdd1_supply),
1687 .consumer_supplies = am335x_vdd1_supply, 1688 .consumer_supplies = am335x_vdd1_supply,
1688 }; 1689 };
1689 1690
1690 static struct tps65910_board am335x_tps65910_info = { 1691 static struct tps65910_board am335x_tps65910_info = {
1691 .tps65910_pmic_init_data[TPS65910_REG_VRTC] = &am335x_dummy, 1692 .tps65910_pmic_init_data[TPS65910_REG_VRTC] = &am335x_dummy,
1692 .tps65910_pmic_init_data[TPS65910_REG_VIO] = &am335x_dummy, 1693 .tps65910_pmic_init_data[TPS65910_REG_VIO] = &am335x_dummy,
1693 .tps65910_pmic_init_data[TPS65910_REG_VDD1] = &am335x_vdd1, 1694 .tps65910_pmic_init_data[TPS65910_REG_VDD1] = &am335x_vdd1,
1694 .tps65910_pmic_init_data[TPS65910_REG_VDD2] = &am335x_dummy, 1695 .tps65910_pmic_init_data[TPS65910_REG_VDD2] = &am335x_dummy,
1695 .tps65910_pmic_init_data[TPS65910_REG_VDD3] = &am335x_dummy, 1696 .tps65910_pmic_init_data[TPS65910_REG_VDD3] = &am335x_dummy,
1696 .tps65910_pmic_init_data[TPS65910_REG_VDIG1] = &am335x_dummy, 1697 .tps65910_pmic_init_data[TPS65910_REG_VDIG1] = &am335x_dummy,
1697 .tps65910_pmic_init_data[TPS65910_REG_VDIG2] = &am335x_dummy, 1698 .tps65910_pmic_init_data[TPS65910_REG_VDIG2] = &am335x_dummy,
1698 .tps65910_pmic_init_data[TPS65910_REG_VPLL] = &am335x_dummy, 1699 .tps65910_pmic_init_data[TPS65910_REG_VPLL] = &am335x_dummy,
1699 .tps65910_pmic_init_data[TPS65910_REG_VDAC] = &am335x_dummy, 1700 .tps65910_pmic_init_data[TPS65910_REG_VDAC] = &am335x_dummy,
1700 .tps65910_pmic_init_data[TPS65910_REG_VAUX1] = &am335x_dummy, 1701 .tps65910_pmic_init_data[TPS65910_REG_VAUX1] = &am335x_dummy,
1701 .tps65910_pmic_init_data[TPS65910_REG_VAUX2] = &am335x_dummy, 1702 .tps65910_pmic_init_data[TPS65910_REG_VAUX2] = &am335x_dummy,
1702 .tps65910_pmic_init_data[TPS65910_REG_VAUX33] = &am335x_dummy, 1703 .tps65910_pmic_init_data[TPS65910_REG_VAUX33] = &am335x_dummy,
1703 .tps65910_pmic_init_data[TPS65910_REG_VMMC] = &am335x_dummy, 1704 .tps65910_pmic_init_data[TPS65910_REG_VMMC] = &am335x_dummy,
1704 }; 1705 };
1705 1706
1706 /* 1707 /*
1707 * Daughter board Detection. 1708 * Daughter board Detection.
1708 * Every board has a ID memory (EEPROM) on board. We probe these devices at 1709 * Every board has a ID memory (EEPROM) on board. We probe these devices at
1709 * machine init, starting from daughter board and ending with baseboard. 1710 * machine init, starting from daughter board and ending with baseboard.
1710 * Assumptions : 1711 * Assumptions :
1711 * 1. probe for i2c devices are called in the order they are included in 1712 * 1. probe for i2c devices are called in the order they are included in
1712 * the below struct. Daughter boards eeprom are probed 1st. Baseboard 1713 * the below struct. Daughter boards eeprom are probed 1st. Baseboard
1713 * eeprom probe is called last. 1714 * eeprom probe is called last.
1714 */ 1715 */
1715 static struct i2c_board_info __initdata am335x_i2c_boardinfo[] = { 1716 static struct i2c_board_info __initdata am335x_i2c_boardinfo[] = {
1716 { 1717 {
1717 /* Daughter Board EEPROM */ 1718 /* Daughter Board EEPROM */
1718 I2C_BOARD_INFO("24c256", DAUG_BOARD_I2C_ADDR), 1719 I2C_BOARD_INFO("24c256", DAUG_BOARD_I2C_ADDR),
1719 .platform_data = &am335x_daughter_board_eeprom_info, 1720 .platform_data = &am335x_daughter_board_eeprom_info,
1720 }, 1721 },
1721 { 1722 {
1722 /* Baseboard board EEPROM */ 1723 /* Baseboard board EEPROM */
1723 I2C_BOARD_INFO("24c256", BASEBOARD_I2C_ADDR), 1724 I2C_BOARD_INFO("24c256", BASEBOARD_I2C_ADDR),
1724 .platform_data = &am335x_baseboard_eeprom_info, 1725 .platform_data = &am335x_baseboard_eeprom_info,
1725 }, 1726 },
1726 { 1727 {
1727 I2C_BOARD_INFO("cpld_reg", 0x35), 1728 I2C_BOARD_INFO("cpld_reg", 0x35),
1728 }, 1729 },
1729 { 1730 {
1730 I2C_BOARD_INFO("tlc59108", 0x40), 1731 I2C_BOARD_INFO("tlc59108", 0x40),
1731 }, 1732 },
1732 { 1733 {
1733 I2C_BOARD_INFO("tps65910", TPS65910_I2C_ID1), 1734 I2C_BOARD_INFO("tps65910", TPS65910_I2C_ID1),
1734 .platform_data = &am335x_tps65910_info, 1735 .platform_data = &am335x_tps65910_info,
1735 }, 1736 },
1736 1737
1737 }; 1738 };
1738 1739
1739 static struct omap_musb_board_data musb_board_data = { 1740 static struct omap_musb_board_data musb_board_data = {
1740 .interface_type = MUSB_INTERFACE_ULPI, 1741 .interface_type = MUSB_INTERFACE_ULPI,
1741 .mode = MUSB_OTG, 1742 .mode = MUSB_OTG,
1742 .power = 500, 1743 .power = 500,
1743 .instances = 1, 1744 .instances = 1,
1744 }; 1745 };
1745 1746
1746 static int cpld_reg_probe(struct i2c_client *client, 1747 static int cpld_reg_probe(struct i2c_client *client,
1747 const struct i2c_device_id *id) 1748 const struct i2c_device_id *id)
1748 { 1749 {
1749 cpld_client = client; 1750 cpld_client = client;
1750 return 0; 1751 return 0;
1751 } 1752 }
1752 1753
1753 static int __devexit cpld_reg_remove(struct i2c_client *client) 1754 static int __devexit cpld_reg_remove(struct i2c_client *client)
1754 { 1755 {
1755 cpld_client = NULL; 1756 cpld_client = NULL;
1756 return 0; 1757 return 0;
1757 } 1758 }
1758 1759
1759 static const struct i2c_device_id cpld_reg_id[] = { 1760 static const struct i2c_device_id cpld_reg_id[] = {
1760 { "cpld_reg", 0 }, 1761 { "cpld_reg", 0 },
1761 { } 1762 { }
1762 }; 1763 };
1763 1764
1764 static struct i2c_driver cpld_reg_driver = { 1765 static struct i2c_driver cpld_reg_driver = {
1765 .driver = { 1766 .driver = {
1766 .name = "cpld_reg", 1767 .name = "cpld_reg",
1767 }, 1768 },
1768 .probe = cpld_reg_probe, 1769 .probe = cpld_reg_probe,
1769 .remove = cpld_reg_remove, 1770 .remove = cpld_reg_remove,
1770 .id_table = cpld_reg_id, 1771 .id_table = cpld_reg_id,
1771 }; 1772 };
1772 1773
1773 static void evm_init_cpld(void) 1774 static void evm_init_cpld(void)
1774 { 1775 {
1775 i2c_add_driver(&cpld_reg_driver); 1776 i2c_add_driver(&cpld_reg_driver);
1776 } 1777 }
1777 1778
1778 static void __init am335x_evm_i2c_init(void) 1779 static void __init am335x_evm_i2c_init(void)
1779 { 1780 {
1780 /* Initially assume Low Cost EVM Config */ 1781 /* Initially assume Low Cost EVM Config */
1781 am335x_evm_id = LOW_COST_EVM; 1782 am335x_evm_id = LOW_COST_EVM;
1782 1783
1783 evm_init_cpld(); 1784 evm_init_cpld();
1784 1785
1785 omap_register_i2c_bus(1, 100, am335x_i2c_boardinfo, 1786 omap_register_i2c_bus(1, 100, am335x_i2c_boardinfo,
1786 ARRAY_SIZE(am335x_i2c_boardinfo)); 1787 ARRAY_SIZE(am335x_i2c_boardinfo));
1787 } 1788 }
1788 1789
1789 static struct resource am335x_rtc_resources[] = { 1790 static struct resource am335x_rtc_resources[] = {
1790 { 1791 {
1791 .start = AM33XX_RTC_BASE, 1792 .start = AM33XX_RTC_BASE,
1792 .end = AM33XX_RTC_BASE + SZ_4K - 1, 1793 .end = AM33XX_RTC_BASE + SZ_4K - 1,
1793 .flags = IORESOURCE_MEM, 1794 .flags = IORESOURCE_MEM,
1794 }, 1795 },
1795 { /* timer irq */ 1796 { /* timer irq */
1796 .start = AM33XX_IRQ_RTC_TIMER, 1797 .start = AM33XX_IRQ_RTC_TIMER,
1797 .end = AM33XX_IRQ_RTC_TIMER, 1798 .end = AM33XX_IRQ_RTC_TIMER,
1798 .flags = IORESOURCE_IRQ, 1799 .flags = IORESOURCE_IRQ,
1799 }, 1800 },
1800 { /* alarm irq */ 1801 { /* alarm irq */
1801 .start = AM33XX_IRQ_RTC_ALARM, 1802 .start = AM33XX_IRQ_RTC_ALARM,
1802 .end = AM33XX_IRQ_RTC_ALARM, 1803 .end = AM33XX_IRQ_RTC_ALARM,
1803 .flags = IORESOURCE_IRQ, 1804 .flags = IORESOURCE_IRQ,
1804 }, 1805 },
1805 }; 1806 };
1806 1807
1807 static struct platform_device am335x_rtc_device = { 1808 static struct platform_device am335x_rtc_device = {
1808 .name = "omap_rtc", 1809 .name = "omap_rtc",
1809 .id = -1, 1810 .id = -1,
1810 .num_resources = ARRAY_SIZE(am335x_rtc_resources), 1811 .num_resources = ARRAY_SIZE(am335x_rtc_resources),
1811 .resource = am335x_rtc_resources, 1812 .resource = am335x_rtc_resources,
1812 }; 1813 };
1813 1814
1814 static int am335x_rtc_init(void) 1815 static int am335x_rtc_init(void)
1815 { 1816 {
1816 void __iomem *base; 1817 void __iomem *base;
1817 struct clk *clk; 1818 struct clk *clk;
1818 1819
1819 clk = clk_get(NULL, "rtc_fck"); 1820 clk = clk_get(NULL, "rtc_fck");
1820 if (IS_ERR(clk)) { 1821 if (IS_ERR(clk)) {
1821 pr_err("rtc : Failed to get RTC clock\n"); 1822 pr_err("rtc : Failed to get RTC clock\n");
1822 return -1; 1823 return -1;
1823 } 1824 }
1824 1825
1825 if (clk_enable(clk)) { 1826 if (clk_enable(clk)) {
1826 pr_err("rtc: Clock Enable Failed\n"); 1827 pr_err("rtc: Clock Enable Failed\n");
1827 return -1; 1828 return -1;
1828 } 1829 }
1829 1830
1830 base = ioremap(AM33XX_RTC_BASE, SZ_4K); 1831 base = ioremap(AM33XX_RTC_BASE, SZ_4K);
1831 1832
1832 if (WARN_ON(!base)) 1833 if (WARN_ON(!base))
1833 return -ENOMEM; 1834 return -ENOMEM;
1834 1835
1835 /* Unlock the rtc's registers */ 1836 /* Unlock the rtc's registers */
1836 __raw_writel(0x83e70b13, base + 0x6c); 1837 __raw_writel(0x83e70b13, base + 0x6c);
1837 __raw_writel(0x95a4f1e0, base + 0x70); 1838 __raw_writel(0x95a4f1e0, base + 0x70);
1838 1839
1839 /* 1840 /*
1840 * Enable the 32K OSc 1841 * Enable the 32K OSc
1841 * TODO: Need a better way to handle this 1842 * TODO: Need a better way to handle this
1842 * Since we want the clock to be running before mmc init 1843 * Since we want the clock to be running before mmc init
1843 * we need to do it before the rtc probe happens 1844 * we need to do it before the rtc probe happens
1844 */ 1845 */
1845 __raw_writel(0x48, base + 0x54); 1846 __raw_writel(0x48, base + 0x54);
1846 1847
1847 iounmap(base); 1848 iounmap(base);
1848 1849
1849 return platform_device_register(&am335x_rtc_device); 1850 return platform_device_register(&am335x_rtc_device);
1850 } 1851 }
1851 1852
1852 /* Enable clkout2 */ 1853 /* Enable clkout2 */
1853 static struct pinmux_config clkout2_pin_mux[] = { 1854 static struct pinmux_config clkout2_pin_mux[] = {
1854 {"xdma_event_intr1.clkout2", OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT}, 1855 {"xdma_event_intr1.clkout2", OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT},
1855 {NULL, 0}, 1856 {NULL, 0},
1856 }; 1857 };
1857 1858
1858 static void __init clkout2_enable(void) 1859 static void __init clkout2_enable(void)
1859 { 1860 {
1860 struct clk *ck_32; 1861 struct clk *ck_32;
1861 1862
1862 ck_32 = clk_get(NULL, "clkout2_ck"); 1863 ck_32 = clk_get(NULL, "clkout2_ck");
1863 if (IS_ERR(ck_32)) { 1864 if (IS_ERR(ck_32)) {
1864 pr_err("Cannot clk_get ck_32\n"); 1865 pr_err("Cannot clk_get ck_32\n");
1865 return; 1866 return;
1866 } 1867 }
1867 1868
1868 clk_enable(ck_32); 1869 clk_enable(ck_32);
1869 1870
1870 setup_pin_mux(clkout2_pin_mux); 1871 setup_pin_mux(clkout2_pin_mux);
1871 } 1872 }
1872 1873
1874 void __iomem * __init am33xx_get_mem_ctlr(void)
1875 {
1876 void __iomem *am33xx_emif_base;
1877
1878 am33xx_emif_base = ioremap(AM33XX_EMIF0_BASE, SZ_32K);
1879
1880 if (!am33xx_emif_base)
1881 pr_warning("%s: Unable to map DDR2 controller", __func__);
1882
1883 return am33xx_emif_base;
1884 }
1885
1886 static struct resource am33xx_cpuidle_resources[] = {
1887 {
1888 .start = AM33XX_EMIF0_BASE,
1889 .end = AM33XX_EMIF0_BASE + SZ_32K - 1,
1890 .flags = IORESOURCE_MEM,
1891 },
1892 };
1893
1894 /* AM33XX devices support DDR2 power down */
1895 static struct am33xx_cpuidle_config am33xx_cpuidle_pdata = {
1896 .ddr2_pdown = 1,
1897 };
1898
1899 static struct platform_device am33xx_cpuidle_device = {
1900 .name = "cpuidle-am33xx",
1901 .num_resources = ARRAY_SIZE(am33xx_cpuidle_resources),
1902 .resource = am33xx_cpuidle_resources,
1903 .dev = {
1904 .platform_data = &am33xx_cpuidle_pdata,
1905 },
1906 };
1907
1908 static void __init am33xx_cpuidle_init(void)
1909 {
1910 int ret;
1911
1912 am33xx_cpuidle_pdata.emif_base = am33xx_get_mem_ctlr();
1913
1914 ret = platform_device_register(&am33xx_cpuidle_device);
1915
1916 if (ret)
1917 pr_warning("AM33XX cpuidle registration failed\n");
1918
1919 }
1920
1873 static void __init am335x_evm_init(void) 1921 static void __init am335x_evm_init(void)
1874 { 1922 {
1923 am33xx_cpuidle_init();
1875 am33xx_mux_init(board_mux); 1924 am33xx_mux_init(board_mux);
1876 omap_serial_init(); 1925 omap_serial_init();
1877 am335x_rtc_init(); 1926 am335x_rtc_init();
1878 clkout2_enable(); 1927 clkout2_enable();
1879 am335x_evm_i2c_init(); 1928 am335x_evm_i2c_init();
1880 omap_sdrc_init(NULL, NULL); 1929 omap_sdrc_init(NULL, NULL);
1881 usb_musb_init(&musb_board_data); 1930 usb_musb_init(&musb_board_data);
1882 omap_board_config = am335x_evm_config; 1931 omap_board_config = am335x_evm_config;
1883 omap_board_config_size = ARRAY_SIZE(am335x_evm_config); 1932 omap_board_config_size = ARRAY_SIZE(am335x_evm_config);
1884 /* Create an alias for icss clock */ 1933 /* Create an alias for icss clock */
1885 if (clk_add_alias("pruss", NULL, "icss_uart_gclk", NULL)) 1934 if (clk_add_alias("pruss", NULL, "icss_uart_gclk", NULL))
1886 pr_err("failed to create an alias: icss_uart_gclk --> pruss\n"); 1935 pr_err("failed to create an alias: icss_uart_gclk --> pruss\n");
1887 /* Create an alias for gfx/sgx clock */ 1936 /* Create an alias for gfx/sgx clock */
1888 if (clk_add_alias("sgx_ck", NULL, "gfx_fclk", NULL)) 1937 if (clk_add_alias("sgx_ck", NULL, "gfx_fclk", NULL))
1889 pr_err("failed to create an alias: gfx_fclk --> sgx_ck\n"); 1938 pr_err("failed to create an alias: gfx_fclk --> sgx_ck\n");
1890 } 1939 }
1891 1940
1892 static void __init am335x_evm_map_io(void) 1941 static void __init am335x_evm_map_io(void)
1893 { 1942 {
1894 omap2_set_globals_am33xx(); 1943 omap2_set_globals_am33xx();
1895 omapam33xx_map_common_io(); 1944 omapam33xx_map_common_io();
1896 } 1945 }
1897 1946
1898 MACHINE_START(AM335XEVM, "am335xevm") 1947 MACHINE_START(AM335XEVM, "am335xevm")
1899 /* Maintainer: Texas Instruments */ 1948 /* Maintainer: Texas Instruments */
1900 .atag_offset = 0x100, 1949 .atag_offset = 0x100,
1901 .map_io = am335x_evm_map_io, 1950 .map_io = am335x_evm_map_io,
1902 .init_irq = ti816x_init_irq, 1951 .init_irq = ti816x_init_irq,
1903 .init_early = am335x_init_early, 1952 .init_early = am335x_init_early,
1904 .timer = &omap3_am33xx_timer, 1953 .timer = &omap3_am33xx_timer,
1905 .init_machine = am335x_evm_init, 1954 .init_machine = am335x_evm_init,
1906 MACHINE_END 1955 MACHINE_END
1907 1956
1908 MACHINE_START(AM335XIAEVM, "am335xiaevm") 1957 MACHINE_START(AM335XIAEVM, "am335xiaevm")
1909 /* Maintainer: Texas Instruments */ 1958 /* Maintainer: Texas Instruments */
1910 .atag_offset = 0x100, 1959 .atag_offset = 0x100,
1911 .map_io = am335x_evm_map_io, 1960 .map_io = am335x_evm_map_io,
1912 .init_irq = ti816x_init_irq, 1961 .init_irq = ti816x_init_irq,
1913 .init_early = am335x_init_early, 1962 .init_early = am335x_init_early,
1914 .timer = &omap3_am33xx_timer, 1963 .timer = &omap3_am33xx_timer,
1915 .init_machine = am335x_evm_init, 1964 .init_machine = am335x_evm_init,
1916 MACHINE_END 1965 MACHINE_END
1917 1966