Eric Lee / linux-smarc-t335x-v3.2

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Commit 69d279eaf8f23c7d7cfc0e879c629a92bfc3e3e0

Authored by hartleys
Committed by David S. Miller
1 parent bc7259a2ce
Exists in master and in 4 other branches v3.2_AM335xPSP_04.06.00.11, v3.2_NEWT335xPSP_04.06.00.11, v3.2_SBC_SMARTMEN, v3.2_SMARCT335xPSP_04.06.00.11

drivers/net/defxx.c: use %pMF to show MAC address 

Use the %pMF kernel extension to display the MAC address.

The address will still be displayed in the FDDI Canonical format.

Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com>
Cc: Maciej W. Rozycki <macro@linux-mips.org>
Cc: David S. Miller <davem@davemloft.net>
Signed-off-by: David S. Miller <davem@davemloft.net>

Showing 1 changed file with 2 additions and 5 deletions Inline Diff

1 /* 1 /*
2 * File Name: 2 * File Name:
3 * defxx.c 3 * defxx.c
4 * 4 *
5 * Copyright Information: 5 * Copyright Information:
6 * Copyright Digital Equipment Corporation 1996. 6 * Copyright Digital Equipment Corporation 1996.
7 * 7 *
8 * This software may be used and distributed according to the terms of 8 * This software may be used and distributed according to the terms of
9 * the GNU General Public License, incorporated herein by reference. 9 * the GNU General Public License, incorporated herein by reference.
10 * 10 *
11 * Abstract: 11 * Abstract:
12 * A Linux device driver supporting the Digital Equipment Corporation 12 * A Linux device driver supporting the Digital Equipment Corporation
13 * FDDI TURBOchannel, EISA and PCI controller families. Supported 13 * FDDI TURBOchannel, EISA and PCI controller families. Supported
14 * adapters include: 14 * adapters include:
15 * 15 *
16 * DEC FDDIcontroller/TURBOchannel (DEFTA) 16 * DEC FDDIcontroller/TURBOchannel (DEFTA)
17 * DEC FDDIcontroller/EISA (DEFEA) 17 * DEC FDDIcontroller/EISA (DEFEA)
18 * DEC FDDIcontroller/PCI (DEFPA) 18 * DEC FDDIcontroller/PCI (DEFPA)
19 * 19 *
20 * The original author: 20 * The original author:
21 * LVS Lawrence V. Stefani <lstefani@yahoo.com> 21 * LVS Lawrence V. Stefani <lstefani@yahoo.com>
22 * 22 *
23 * Maintainers: 23 * Maintainers:
24 * macro Maciej W. Rozycki <macro@linux-mips.org> 24 * macro Maciej W. Rozycki <macro@linux-mips.org>
25 * 25 *
26 * Credits: 26 * Credits:
27 * I'd like to thank Patricia Cross for helping me get started with 27 * I'd like to thank Patricia Cross for helping me get started with
28 * Linux, David Davies for a lot of help upgrading and configuring 28 * Linux, David Davies for a lot of help upgrading and configuring
29 * my development system and for answering many OS and driver 29 * my development system and for answering many OS and driver
30 * development questions, and Alan Cox for recommendations and 30 * development questions, and Alan Cox for recommendations and
31 * integration help on getting FDDI support into Linux. LVS 31 * integration help on getting FDDI support into Linux. LVS
32 * 32 *
33 * Driver Architecture: 33 * Driver Architecture:
34 * The driver architecture is largely based on previous driver work 34 * The driver architecture is largely based on previous driver work
35 * for other operating systems. The upper edge interface and 35 * for other operating systems. The upper edge interface and
36 * functions were largely taken from existing Linux device drivers 36 * functions were largely taken from existing Linux device drivers
37 * such as David Davies' DE4X5.C driver and Donald Becker's TULIP.C 37 * such as David Davies' DE4X5.C driver and Donald Becker's TULIP.C
38 * driver. 38 * driver.
39 * 39 *
40 * Adapter Probe - 40 * Adapter Probe -
41 * The driver scans for supported EISA adapters by reading the 41 * The driver scans for supported EISA adapters by reading the
42 * SLOT ID register for each EISA slot and making a match 42 * SLOT ID register for each EISA slot and making a match
43 * against the expected value. 43 * against the expected value.
44 * 44 *
45 * Bus-Specific Initialization - 45 * Bus-Specific Initialization -
46 * This driver currently supports both EISA and PCI controller 46 * This driver currently supports both EISA and PCI controller
47 * families. While the custom DMA chip and FDDI logic is similar 47 * families. While the custom DMA chip and FDDI logic is similar
48 * or identical, the bus logic is very different. After 48 * or identical, the bus logic is very different. After
49 * initialization, the only bus-specific differences is in how the 49 * initialization, the only bus-specific differences is in how the
50 * driver enables and disables interrupts. Other than that, the 50 * driver enables and disables interrupts. Other than that, the
51 * run-time critical code behaves the same on both families. 51 * run-time critical code behaves the same on both families.
52 * It's important to note that both adapter families are configured 52 * It's important to note that both adapter families are configured
53 * to I/O map, rather than memory map, the adapter registers. 53 * to I/O map, rather than memory map, the adapter registers.
54 * 54 *
55 * Driver Open/Close - 55 * Driver Open/Close -
56 * In the driver open routine, the driver ISR (interrupt service 56 * In the driver open routine, the driver ISR (interrupt service
57 * routine) is registered and the adapter is brought to an 57 * routine) is registered and the adapter is brought to an
58 * operational state. In the driver close routine, the opposite 58 * operational state. In the driver close routine, the opposite
59 * occurs; the driver ISR is deregistered and the adapter is 59 * occurs; the driver ISR is deregistered and the adapter is
60 * brought to a safe, but closed state. Users may use consecutive 60 * brought to a safe, but closed state. Users may use consecutive
61 * commands to bring the adapter up and down as in the following 61 * commands to bring the adapter up and down as in the following
62 * example: 62 * example:
63 * ifconfig fddi0 up 63 * ifconfig fddi0 up
64 * ifconfig fddi0 down 64 * ifconfig fddi0 down
65 * ifconfig fddi0 up 65 * ifconfig fddi0 up
66 * 66 *
67 * Driver Shutdown - 67 * Driver Shutdown -
68 * Apparently, there is no shutdown or halt routine support under 68 * Apparently, there is no shutdown or halt routine support under
69 * Linux. This routine would be called during "reboot" or 69 * Linux. This routine would be called during "reboot" or
70 * "shutdown" to allow the driver to place the adapter in a safe 70 * "shutdown" to allow the driver to place the adapter in a safe
71 * state before a warm reboot occurs. To be really safe, the user 71 * state before a warm reboot occurs. To be really safe, the user
72 * should close the adapter before shutdown (eg. ifconfig fddi0 down) 72 * should close the adapter before shutdown (eg. ifconfig fddi0 down)
73 * to ensure that the adapter DMA engine is taken off-line. However, 73 * to ensure that the adapter DMA engine is taken off-line. However,
74 * the current driver code anticipates this problem and always issues 74 * the current driver code anticipates this problem and always issues
75 * a soft reset of the adapter at the beginning of driver initialization. 75 * a soft reset of the adapter at the beginning of driver initialization.
76 * A future driver enhancement in this area may occur in 2.1.X where 76 * A future driver enhancement in this area may occur in 2.1.X where
77 * Alan indicated that a shutdown handler may be implemented. 77 * Alan indicated that a shutdown handler may be implemented.
78 * 78 *
79 * Interrupt Service Routine - 79 * Interrupt Service Routine -
80 * The driver supports shared interrupts, so the ISR is registered for 80 * The driver supports shared interrupts, so the ISR is registered for
81 * each board with the appropriate flag and the pointer to that board's 81 * each board with the appropriate flag and the pointer to that board's
82 * device structure. This provides the context during interrupt 82 * device structure. This provides the context during interrupt
83 * processing to support shared interrupts and multiple boards. 83 * processing to support shared interrupts and multiple boards.
84 * 84 *
85 * Interrupt enabling/disabling can occur at many levels. At the host 85 * Interrupt enabling/disabling can occur at many levels. At the host
86 * end, you can disable system interrupts, or disable interrupts at the 86 * end, you can disable system interrupts, or disable interrupts at the
87 * PIC (on Intel systems). Across the bus, both EISA and PCI adapters 87 * PIC (on Intel systems). Across the bus, both EISA and PCI adapters
88 * have a bus-logic chip interrupt enable/disable as well as a DMA 88 * have a bus-logic chip interrupt enable/disable as well as a DMA
89 * controller interrupt enable/disable. 89 * controller interrupt enable/disable.
90 * 90 *
91 * The driver currently enables and disables adapter interrupts at the 91 * The driver currently enables and disables adapter interrupts at the
92 * bus-logic chip and assumes that Linux will take care of clearing or 92 * bus-logic chip and assumes that Linux will take care of clearing or
93 * acknowledging any host-based interrupt chips. 93 * acknowledging any host-based interrupt chips.
94 * 94 *
95 * Control Functions - 95 * Control Functions -
96 * Control functions are those used to support functions such as adding 96 * Control functions are those used to support functions such as adding
97 * or deleting multicast addresses, enabling or disabling packet 97 * or deleting multicast addresses, enabling or disabling packet
98 * reception filters, or other custom/proprietary commands. Presently, 98 * reception filters, or other custom/proprietary commands. Presently,
99 * the driver supports the "get statistics", "set multicast list", and 99 * the driver supports the "get statistics", "set multicast list", and
100 * "set mac address" functions defined by Linux. A list of possible 100 * "set mac address" functions defined by Linux. A list of possible
101 * enhancements include: 101 * enhancements include:
102 * 102 *
103 * - Custom ioctl interface for executing port interface commands 103 * - Custom ioctl interface for executing port interface commands
104 * - Custom ioctl interface for adding unicast addresses to 104 * - Custom ioctl interface for adding unicast addresses to
105 * adapter CAM (to support bridge functions). 105 * adapter CAM (to support bridge functions).
106 * - Custom ioctl interface for supporting firmware upgrades. 106 * - Custom ioctl interface for supporting firmware upgrades.
107 * 107 *
108 * Hardware (port interface) Support Routines - 108 * Hardware (port interface) Support Routines -
109 * The driver function names that start with "dfx_hw_" represent 109 * The driver function names that start with "dfx_hw_" represent
110 * low-level port interface routines that are called frequently. They 110 * low-level port interface routines that are called frequently. They
111 * include issuing a DMA or port control command to the adapter, 111 * include issuing a DMA or port control command to the adapter,
112 * resetting the adapter, or reading the adapter state. Since the 112 * resetting the adapter, or reading the adapter state. Since the
113 * driver initialization and run-time code must make calls into the 113 * driver initialization and run-time code must make calls into the
114 * port interface, these routines were written to be as generic and 114 * port interface, these routines were written to be as generic and
115 * usable as possible. 115 * usable as possible.
116 * 116 *
117 * Receive Path - 117 * Receive Path -
118 * The adapter DMA engine supports a 256 entry receive descriptor block 118 * The adapter DMA engine supports a 256 entry receive descriptor block
119 * of which up to 255 entries can be used at any given time. The 119 * of which up to 255 entries can be used at any given time. The
120 * architecture is a standard producer, consumer, completion model in 120 * architecture is a standard producer, consumer, completion model in
121 * which the driver "produces" receive buffers to the adapter, the 121 * which the driver "produces" receive buffers to the adapter, the
122 * adapter "consumes" the receive buffers by DMAing incoming packet data, 122 * adapter "consumes" the receive buffers by DMAing incoming packet data,
123 * and the driver "completes" the receive buffers by servicing the 123 * and the driver "completes" the receive buffers by servicing the
124 * incoming packet, then "produces" a new buffer and starts the cycle 124 * incoming packet, then "produces" a new buffer and starts the cycle
125 * again. Receive buffers can be fragmented in up to 16 fragments 125 * again. Receive buffers can be fragmented in up to 16 fragments
126 * (descriptor entries). For simplicity, this driver posts 126 * (descriptor entries). For simplicity, this driver posts
127 * single-fragment receive buffers of 4608 bytes, then allocates a 127 * single-fragment receive buffers of 4608 bytes, then allocates a
128 * sk_buff, copies the data, then reposts the buffer. To reduce CPU 128 * sk_buff, copies the data, then reposts the buffer. To reduce CPU
129 * utilization, a better approach would be to pass up the receive 129 * utilization, a better approach would be to pass up the receive
130 * buffer (no extra copy) then allocate and post a replacement buffer. 130 * buffer (no extra copy) then allocate and post a replacement buffer.
131 * This is a performance enhancement that should be looked into at 131 * This is a performance enhancement that should be looked into at
132 * some point. 132 * some point.
133 * 133 *
134 * Transmit Path - 134 * Transmit Path -
135 * Like the receive path, the adapter DMA engine supports a 256 entry 135 * Like the receive path, the adapter DMA engine supports a 256 entry
136 * transmit descriptor block of which up to 255 entries can be used at 136 * transmit descriptor block of which up to 255 entries can be used at
137 * any given time. Transmit buffers can be fragmented in up to 255 137 * any given time. Transmit buffers can be fragmented in up to 255
138 * fragments (descriptor entries). This driver always posts one 138 * fragments (descriptor entries). This driver always posts one
139 * fragment per transmit packet request. 139 * fragment per transmit packet request.
140 * 140 *
141 * The fragment contains the entire packet from FC to end of data. 141 * The fragment contains the entire packet from FC to end of data.
142 * Before posting the buffer to the adapter, the driver sets a three-byte 142 * Before posting the buffer to the adapter, the driver sets a three-byte
143 * packet request header (PRH) which is required by the Motorola MAC chip 143 * packet request header (PRH) which is required by the Motorola MAC chip
144 * used on the adapters. The PRH tells the MAC the type of token to 144 * used on the adapters. The PRH tells the MAC the type of token to
145 * receive/send, whether or not to generate and append the CRC, whether 145 * receive/send, whether or not to generate and append the CRC, whether
146 * synchronous or asynchronous framing is used, etc. Since the PRH 146 * synchronous or asynchronous framing is used, etc. Since the PRH
147 * definition is not necessarily consistent across all FDDI chipsets, 147 * definition is not necessarily consistent across all FDDI chipsets,
148 * the driver, rather than the common FDDI packet handler routines, 148 * the driver, rather than the common FDDI packet handler routines,
149 * sets these bytes. 149 * sets these bytes.
150 * 150 *
151 * To reduce the amount of descriptor fetches needed per transmit request, 151 * To reduce the amount of descriptor fetches needed per transmit request,
152 * the driver takes advantage of the fact that there are at least three 152 * the driver takes advantage of the fact that there are at least three
153 * bytes available before the skb->data field on the outgoing transmit 153 * bytes available before the skb->data field on the outgoing transmit
154 * request. This is guaranteed by having fddi_setup() in net_init.c set 154 * request. This is guaranteed by having fddi_setup() in net_init.c set
155 * dev->hard_header_len to 24 bytes. 21 bytes accounts for the largest 155 * dev->hard_header_len to 24 bytes. 21 bytes accounts for the largest
156 * header in an 802.2 SNAP frame. The other 3 bytes are the extra "pad" 156 * header in an 802.2 SNAP frame. The other 3 bytes are the extra "pad"
157 * bytes which we'll use to store the PRH. 157 * bytes which we'll use to store the PRH.
158 * 158 *
159 * There's a subtle advantage to adding these pad bytes to the 159 * There's a subtle advantage to adding these pad bytes to the
160 * hard_header_len, it ensures that the data portion of the packet for 160 * hard_header_len, it ensures that the data portion of the packet for
161 * an 802.2 SNAP frame is longword aligned. Other FDDI driver 161 * an 802.2 SNAP frame is longword aligned. Other FDDI driver
162 * implementations may not need the extra padding and can start copying 162 * implementations may not need the extra padding and can start copying
163 * or DMAing directly from the FC byte which starts at skb->data. Should 163 * or DMAing directly from the FC byte which starts at skb->data. Should
164 * another driver implementation need ADDITIONAL padding, the net_init.c 164 * another driver implementation need ADDITIONAL padding, the net_init.c
165 * module should be updated and dev->hard_header_len should be increased. 165 * module should be updated and dev->hard_header_len should be increased.
166 * NOTE: To maintain the alignment on the data portion of the packet, 166 * NOTE: To maintain the alignment on the data portion of the packet,
167 * dev->hard_header_len should always be evenly divisible by 4 and at 167 * dev->hard_header_len should always be evenly divisible by 4 and at
168 * least 24 bytes in size. 168 * least 24 bytes in size.
169 * 169 *
170 * Modification History: 170 * Modification History:
171 * Date Name Description 171 * Date Name Description
172 * 16-Aug-96 LVS Created. 172 * 16-Aug-96 LVS Created.
173 * 20-Aug-96 LVS Updated dfx_probe so that version information 173 * 20-Aug-96 LVS Updated dfx_probe so that version information
174 * string is only displayed if 1 or more cards are 174 * string is only displayed if 1 or more cards are
175 * found. Changed dfx_rcv_queue_process to copy 175 * found. Changed dfx_rcv_queue_process to copy
176 * 3 NULL bytes before FC to ensure that data is 176 * 3 NULL bytes before FC to ensure that data is
177 * longword aligned in receive buffer. 177 * longword aligned in receive buffer.
178 * 09-Sep-96 LVS Updated dfx_ctl_set_multicast_list to enable 178 * 09-Sep-96 LVS Updated dfx_ctl_set_multicast_list to enable
179 * LLC group promiscuous mode if multicast list 179 * LLC group promiscuous mode if multicast list
180 * is too large. LLC individual/group promiscuous 180 * is too large. LLC individual/group promiscuous
181 * mode is now disabled if IFF_PROMISC flag not set. 181 * mode is now disabled if IFF_PROMISC flag not set.
182 * dfx_xmt_queue_pkt no longer checks for NULL skb 182 * dfx_xmt_queue_pkt no longer checks for NULL skb
183 * on Alan Cox recommendation. Added node address 183 * on Alan Cox recommendation. Added node address
184 * override support. 184 * override support.
185 * 12-Sep-96 LVS Reset current address to factory address during 185 * 12-Sep-96 LVS Reset current address to factory address during
186 * device open. Updated transmit path to post a 186 * device open. Updated transmit path to post a
187 * single fragment which includes PRH->end of data. 187 * single fragment which includes PRH->end of data.
188 * Mar 2000 AC Did various cleanups for 2.3.x 188 * Mar 2000 AC Did various cleanups for 2.3.x
189 * Jun 2000 jgarzik PCI and resource alloc cleanups 189 * Jun 2000 jgarzik PCI and resource alloc cleanups
190 * Jul 2000 tjeerd Much cleanup and some bug fixes 190 * Jul 2000 tjeerd Much cleanup and some bug fixes
191 * Sep 2000 tjeerd Fix leak on unload, cosmetic code cleanup 191 * Sep 2000 tjeerd Fix leak on unload, cosmetic code cleanup
192 * Feb 2001 Skb allocation fixes 192 * Feb 2001 Skb allocation fixes
193 * Feb 2001 davej PCI enable cleanups. 193 * Feb 2001 davej PCI enable cleanups.
194 * 04 Aug 2003 macro Converted to the DMA API. 194 * 04 Aug 2003 macro Converted to the DMA API.
195 * 14 Aug 2004 macro Fix device names reported. 195 * 14 Aug 2004 macro Fix device names reported.
196 * 14 Jun 2005 macro Use irqreturn_t. 196 * 14 Jun 2005 macro Use irqreturn_t.
197 * 23 Oct 2006 macro Big-endian host support. 197 * 23 Oct 2006 macro Big-endian host support.
198 * 14 Dec 2006 macro TURBOchannel support. 198 * 14 Dec 2006 macro TURBOchannel support.
199 */ 199 */
200 200
201 /* Include files */ 201 /* Include files */
202 #include <linux/bitops.h> 202 #include <linux/bitops.h>
203 #include <linux/compiler.h> 203 #include <linux/compiler.h>
204 #include <linux/delay.h> 204 #include <linux/delay.h>
205 #include <linux/dma-mapping.h> 205 #include <linux/dma-mapping.h>
206 #include <linux/eisa.h> 206 #include <linux/eisa.h>
207 #include <linux/errno.h> 207 #include <linux/errno.h>
208 #include <linux/fddidevice.h> 208 #include <linux/fddidevice.h>
209 #include <linux/init.h> 209 #include <linux/init.h>
210 #include <linux/interrupt.h> 210 #include <linux/interrupt.h>
211 #include <linux/ioport.h> 211 #include <linux/ioport.h>
212 #include <linux/kernel.h> 212 #include <linux/kernel.h>
213 #include <linux/module.h> 213 #include <linux/module.h>
214 #include <linux/netdevice.h> 214 #include <linux/netdevice.h>
215 #include <linux/pci.h> 215 #include <linux/pci.h>
216 #include <linux/skbuff.h> 216 #include <linux/skbuff.h>
217 #include <linux/slab.h> 217 #include <linux/slab.h>
218 #include <linux/string.h> 218 #include <linux/string.h>
219 #include <linux/tc.h> 219 #include <linux/tc.h>
220 220
221 #include <asm/byteorder.h> 221 #include <asm/byteorder.h>
222 #include <asm/io.h> 222 #include <asm/io.h>
223 223
224 #include "defxx.h" 224 #include "defxx.h"
225 225
226 /* Version information string should be updated prior to each new release! */ 226 /* Version information string should be updated prior to each new release! */
227 #define DRV_NAME "defxx" 227 #define DRV_NAME "defxx"
228 #define DRV_VERSION "v1.10" 228 #define DRV_VERSION "v1.10"
229 #define DRV_RELDATE "2006/12/14" 229 #define DRV_RELDATE "2006/12/14"
230 230
231 static char version[] __devinitdata = 231 static char version[] __devinitdata =
232 DRV_NAME ": " DRV_VERSION " " DRV_RELDATE 232 DRV_NAME ": " DRV_VERSION " " DRV_RELDATE
233 " Lawrence V. Stefani and others\n"; 233 " Lawrence V. Stefani and others\n";
234 234
235 #define DYNAMIC_BUFFERS 1 235 #define DYNAMIC_BUFFERS 1
236 236
237 #define SKBUFF_RX_COPYBREAK 200 237 #define SKBUFF_RX_COPYBREAK 200
238 /* 238 /*
239 * NEW_SKB_SIZE = PI_RCV_DATA_K_SIZE_MAX+128 to allow 128 byte 239 * NEW_SKB_SIZE = PI_RCV_DATA_K_SIZE_MAX+128 to allow 128 byte
240 * alignment for compatibility with old EISA boards. 240 * alignment for compatibility with old EISA boards.
241 */ 241 */
242 #define NEW_SKB_SIZE (PI_RCV_DATA_K_SIZE_MAX+128) 242 #define NEW_SKB_SIZE (PI_RCV_DATA_K_SIZE_MAX+128)
243 243
244 #ifdef CONFIG_PCI 244 #ifdef CONFIG_PCI
245 #define DFX_BUS_PCI(dev) (dev->bus == &pci_bus_type) 245 #define DFX_BUS_PCI(dev) (dev->bus == &pci_bus_type)
246 #else 246 #else
247 #define DFX_BUS_PCI(dev) 0 247 #define DFX_BUS_PCI(dev) 0
248 #endif 248 #endif
249 249
250 #ifdef CONFIG_EISA 250 #ifdef CONFIG_EISA
251 #define DFX_BUS_EISA(dev) (dev->bus == &eisa_bus_type) 251 #define DFX_BUS_EISA(dev) (dev->bus == &eisa_bus_type)
252 #else 252 #else
253 #define DFX_BUS_EISA(dev) 0 253 #define DFX_BUS_EISA(dev) 0
254 #endif 254 #endif
255 255
256 #ifdef CONFIG_TC 256 #ifdef CONFIG_TC
257 #define DFX_BUS_TC(dev) (dev->bus == &tc_bus_type) 257 #define DFX_BUS_TC(dev) (dev->bus == &tc_bus_type)
258 #else 258 #else
259 #define DFX_BUS_TC(dev) 0 259 #define DFX_BUS_TC(dev) 0
260 #endif 260 #endif
261 261
262 #ifdef CONFIG_DEFXX_MMIO 262 #ifdef CONFIG_DEFXX_MMIO
263 #define DFX_MMIO 1 263 #define DFX_MMIO 1
264 #else 264 #else
265 #define DFX_MMIO 0 265 #define DFX_MMIO 0
266 #endif 266 #endif
267 267
268 /* Define module-wide (static) routines */ 268 /* Define module-wide (static) routines */
269 269
270 static void dfx_bus_init(struct net_device *dev); 270 static void dfx_bus_init(struct net_device *dev);
271 static void dfx_bus_uninit(struct net_device *dev); 271 static void dfx_bus_uninit(struct net_device *dev);
272 static void dfx_bus_config_check(DFX_board_t *bp); 272 static void dfx_bus_config_check(DFX_board_t *bp);
273 273
274 static int dfx_driver_init(struct net_device *dev, 274 static int dfx_driver_init(struct net_device *dev,
275 const char *print_name, 275 const char *print_name,
276 resource_size_t bar_start); 276 resource_size_t bar_start);
277 static int dfx_adap_init(DFX_board_t *bp, int get_buffers); 277 static int dfx_adap_init(DFX_board_t *bp, int get_buffers);
278 278
279 static int dfx_open(struct net_device *dev); 279 static int dfx_open(struct net_device *dev);
280 static int dfx_close(struct net_device *dev); 280 static int dfx_close(struct net_device *dev);
281 281
282 static void dfx_int_pr_halt_id(DFX_board_t *bp); 282 static void dfx_int_pr_halt_id(DFX_board_t *bp);
283 static void dfx_int_type_0_process(DFX_board_t *bp); 283 static void dfx_int_type_0_process(DFX_board_t *bp);
284 static void dfx_int_common(struct net_device *dev); 284 static void dfx_int_common(struct net_device *dev);
285 static irqreturn_t dfx_interrupt(int irq, void *dev_id); 285 static irqreturn_t dfx_interrupt(int irq, void *dev_id);
286 286
287 static struct net_device_stats *dfx_ctl_get_stats(struct net_device *dev); 287 static struct net_device_stats *dfx_ctl_get_stats(struct net_device *dev);
288 static void dfx_ctl_set_multicast_list(struct net_device *dev); 288 static void dfx_ctl_set_multicast_list(struct net_device *dev);
289 static int dfx_ctl_set_mac_address(struct net_device *dev, void *addr); 289 static int dfx_ctl_set_mac_address(struct net_device *dev, void *addr);
290 static int dfx_ctl_update_cam(DFX_board_t *bp); 290 static int dfx_ctl_update_cam(DFX_board_t *bp);
291 static int dfx_ctl_update_filters(DFX_board_t *bp); 291 static int dfx_ctl_update_filters(DFX_board_t *bp);
292 292
293 static int dfx_hw_dma_cmd_req(DFX_board_t *bp); 293 static int dfx_hw_dma_cmd_req(DFX_board_t *bp);
294 static int dfx_hw_port_ctrl_req(DFX_board_t *bp, PI_UINT32 command, PI_UINT32 data_a, PI_UINT32 data_b, PI_UINT32 *host_data); 294 static int dfx_hw_port_ctrl_req(DFX_board_t *bp, PI_UINT32 command, PI_UINT32 data_a, PI_UINT32 data_b, PI_UINT32 *host_data);
295 static void dfx_hw_adap_reset(DFX_board_t *bp, PI_UINT32 type); 295 static void dfx_hw_adap_reset(DFX_board_t *bp, PI_UINT32 type);
296 static int dfx_hw_adap_state_rd(DFX_board_t *bp); 296 static int dfx_hw_adap_state_rd(DFX_board_t *bp);
297 static int dfx_hw_dma_uninit(DFX_board_t *bp, PI_UINT32 type); 297 static int dfx_hw_dma_uninit(DFX_board_t *bp, PI_UINT32 type);
298 298
299 static int dfx_rcv_init(DFX_board_t *bp, int get_buffers); 299 static int dfx_rcv_init(DFX_board_t *bp, int get_buffers);
300 static void dfx_rcv_queue_process(DFX_board_t *bp); 300 static void dfx_rcv_queue_process(DFX_board_t *bp);
301 static void dfx_rcv_flush(DFX_board_t *bp); 301 static void dfx_rcv_flush(DFX_board_t *bp);
302 302
303 static netdev_tx_t dfx_xmt_queue_pkt(struct sk_buff *skb, 303 static netdev_tx_t dfx_xmt_queue_pkt(struct sk_buff *skb,
304 struct net_device *dev); 304 struct net_device *dev);
305 static int dfx_xmt_done(DFX_board_t *bp); 305 static int dfx_xmt_done(DFX_board_t *bp);
306 static void dfx_xmt_flush(DFX_board_t *bp); 306 static void dfx_xmt_flush(DFX_board_t *bp);
307 307
308 /* Define module-wide (static) variables */ 308 /* Define module-wide (static) variables */
309 309
310 static struct pci_driver dfx_pci_driver; 310 static struct pci_driver dfx_pci_driver;
311 static struct eisa_driver dfx_eisa_driver; 311 static struct eisa_driver dfx_eisa_driver;
312 static struct tc_driver dfx_tc_driver; 312 static struct tc_driver dfx_tc_driver;
313 313
314 314
315 /* 315 /*
316 * ======================= 316 * =======================
317 * = dfx_port_write_long = 317 * = dfx_port_write_long =
318 * = dfx_port_read_long = 318 * = dfx_port_read_long =
319 * ======================= 319 * =======================
320 * 320 *
321 * Overview: 321 * Overview:
322 * Routines for reading and writing values from/to adapter 322 * Routines for reading and writing values from/to adapter
323 * 323 *
324 * Returns: 324 * Returns:
325 * None 325 * None
326 * 326 *
327 * Arguments: 327 * Arguments:
328 * bp - pointer to board information 328 * bp - pointer to board information
329 * offset - register offset from base I/O address 329 * offset - register offset from base I/O address
330 * data - for dfx_port_write_long, this is a value to write; 330 * data - for dfx_port_write_long, this is a value to write;
331 * for dfx_port_read_long, this is a pointer to store 331 * for dfx_port_read_long, this is a pointer to store
332 * the read value 332 * the read value
333 * 333 *
334 * Functional Description: 334 * Functional Description:
335 * These routines perform the correct operation to read or write 335 * These routines perform the correct operation to read or write
336 * the adapter register. 336 * the adapter register.
337 * 337 *
338 * EISA port block base addresses are based on the slot number in which the 338 * EISA port block base addresses are based on the slot number in which the
339 * controller is installed. For example, if the EISA controller is installed 339 * controller is installed. For example, if the EISA controller is installed
340 * in slot 4, the port block base address is 0x4000. If the controller is 340 * in slot 4, the port block base address is 0x4000. If the controller is
341 * installed in slot 2, the port block base address is 0x2000, and so on. 341 * installed in slot 2, the port block base address is 0x2000, and so on.
342 * This port block can be used to access PDQ, ESIC, and DEFEA on-board 342 * This port block can be used to access PDQ, ESIC, and DEFEA on-board
343 * registers using the register offsets defined in DEFXX.H. 343 * registers using the register offsets defined in DEFXX.H.
344 * 344 *
345 * PCI port block base addresses are assigned by the PCI BIOS or system 345 * PCI port block base addresses are assigned by the PCI BIOS or system
346 * firmware. There is one 128 byte port block which can be accessed. It 346 * firmware. There is one 128 byte port block which can be accessed. It
347 * allows for I/O mapping of both PDQ and PFI registers using the register 347 * allows for I/O mapping of both PDQ and PFI registers using the register
348 * offsets defined in DEFXX.H. 348 * offsets defined in DEFXX.H.
349 * 349 *
350 * Return Codes: 350 * Return Codes:
351 * None 351 * None
352 * 352 *
353 * Assumptions: 353 * Assumptions:
354 * bp->base is a valid base I/O address for this adapter. 354 * bp->base is a valid base I/O address for this adapter.
355 * offset is a valid register offset for this adapter. 355 * offset is a valid register offset for this adapter.
356 * 356 *
357 * Side Effects: 357 * Side Effects:
358 * Rather than produce macros for these functions, these routines 358 * Rather than produce macros for these functions, these routines
359 * are defined using "inline" to ensure that the compiler will 359 * are defined using "inline" to ensure that the compiler will
360 * generate inline code and not waste a procedure call and return. 360 * generate inline code and not waste a procedure call and return.
361 * This provides all the benefits of macros, but with the 361 * This provides all the benefits of macros, but with the
362 * advantage of strict data type checking. 362 * advantage of strict data type checking.
363 */ 363 */
364 364
365 static inline void dfx_writel(DFX_board_t *bp, int offset, u32 data) 365 static inline void dfx_writel(DFX_board_t *bp, int offset, u32 data)
366 { 366 {
367 writel(data, bp->base.mem + offset); 367 writel(data, bp->base.mem + offset);
368 mb(); 368 mb();
369 } 369 }
370 370
371 static inline void dfx_outl(DFX_board_t *bp, int offset, u32 data) 371 static inline void dfx_outl(DFX_board_t *bp, int offset, u32 data)
372 { 372 {
373 outl(data, bp->base.port + offset); 373 outl(data, bp->base.port + offset);
374 } 374 }
375 375
376 static void dfx_port_write_long(DFX_board_t *bp, int offset, u32 data) 376 static void dfx_port_write_long(DFX_board_t *bp, int offset, u32 data)
377 { 377 {
378 struct device __maybe_unused *bdev = bp->bus_dev; 378 struct device __maybe_unused *bdev = bp->bus_dev;
379 int dfx_bus_tc = DFX_BUS_TC(bdev); 379 int dfx_bus_tc = DFX_BUS_TC(bdev);
380 int dfx_use_mmio = DFX_MMIO || dfx_bus_tc; 380 int dfx_use_mmio = DFX_MMIO || dfx_bus_tc;
381 381
382 if (dfx_use_mmio) 382 if (dfx_use_mmio)
383 dfx_writel(bp, offset, data); 383 dfx_writel(bp, offset, data);
384 else 384 else
385 dfx_outl(bp, offset, data); 385 dfx_outl(bp, offset, data);
386 } 386 }
387 387
388 388
389 static inline void dfx_readl(DFX_board_t *bp, int offset, u32 *data) 389 static inline void dfx_readl(DFX_board_t *bp, int offset, u32 *data)
390 { 390 {
391 mb(); 391 mb();
392 *data = readl(bp->base.mem + offset); 392 *data = readl(bp->base.mem + offset);
393 } 393 }
394 394
395 static inline void dfx_inl(DFX_board_t *bp, int offset, u32 *data) 395 static inline void dfx_inl(DFX_board_t *bp, int offset, u32 *data)
396 { 396 {
397 *data = inl(bp->base.port + offset); 397 *data = inl(bp->base.port + offset);
398 } 398 }
399 399
400 static void dfx_port_read_long(DFX_board_t *bp, int offset, u32 *data) 400 static void dfx_port_read_long(DFX_board_t *bp, int offset, u32 *data)
401 { 401 {
402 struct device __maybe_unused *bdev = bp->bus_dev; 402 struct device __maybe_unused *bdev = bp->bus_dev;
403 int dfx_bus_tc = DFX_BUS_TC(bdev); 403 int dfx_bus_tc = DFX_BUS_TC(bdev);
404 int dfx_use_mmio = DFX_MMIO || dfx_bus_tc; 404 int dfx_use_mmio = DFX_MMIO || dfx_bus_tc;
405 405
406 if (dfx_use_mmio) 406 if (dfx_use_mmio)
407 dfx_readl(bp, offset, data); 407 dfx_readl(bp, offset, data);
408 else 408 else
409 dfx_inl(bp, offset, data); 409 dfx_inl(bp, offset, data);
410 } 410 }
411 411
412 412
413 /* 413 /*
414 * ================ 414 * ================
415 * = dfx_get_bars = 415 * = dfx_get_bars =
416 * ================ 416 * ================
417 * 417 *
418 * Overview: 418 * Overview:
419 * Retrieves the address range used to access control and status 419 * Retrieves the address range used to access control and status
420 * registers. 420 * registers.
421 * 421 *
422 * Returns: 422 * Returns:
423 * None 423 * None
424 * 424 *
425 * Arguments: 425 * Arguments:
426 * bdev - pointer to device information 426 * bdev - pointer to device information
427 * bar_start - pointer to store the start address 427 * bar_start - pointer to store the start address
428 * bar_len - pointer to store the length of the area 428 * bar_len - pointer to store the length of the area
429 * 429 *
430 * Assumptions: 430 * Assumptions:
431 * I am sure there are some. 431 * I am sure there are some.
432 * 432 *
433 * Side Effects: 433 * Side Effects:
434 * None 434 * None
435 */ 435 */
436 static void dfx_get_bars(struct device *bdev, 436 static void dfx_get_bars(struct device *bdev,
437 resource_size_t *bar_start, resource_size_t *bar_len) 437 resource_size_t *bar_start, resource_size_t *bar_len)
438 { 438 {
439 int dfx_bus_pci = DFX_BUS_PCI(bdev); 439 int dfx_bus_pci = DFX_BUS_PCI(bdev);
440 int dfx_bus_eisa = DFX_BUS_EISA(bdev); 440 int dfx_bus_eisa = DFX_BUS_EISA(bdev);
441 int dfx_bus_tc = DFX_BUS_TC(bdev); 441 int dfx_bus_tc = DFX_BUS_TC(bdev);
442 int dfx_use_mmio = DFX_MMIO || dfx_bus_tc; 442 int dfx_use_mmio = DFX_MMIO || dfx_bus_tc;
443 443
444 if (dfx_bus_pci) { 444 if (dfx_bus_pci) {
445 int num = dfx_use_mmio ? 0 : 1; 445 int num = dfx_use_mmio ? 0 : 1;
446 446
447 *bar_start = pci_resource_start(to_pci_dev(bdev), num); 447 *bar_start = pci_resource_start(to_pci_dev(bdev), num);
448 *bar_len = pci_resource_len(to_pci_dev(bdev), num); 448 *bar_len = pci_resource_len(to_pci_dev(bdev), num);
449 } 449 }
450 if (dfx_bus_eisa) { 450 if (dfx_bus_eisa) {
451 unsigned long base_addr = to_eisa_device(bdev)->base_addr; 451 unsigned long base_addr = to_eisa_device(bdev)->base_addr;
452 resource_size_t bar; 452 resource_size_t bar;
453 453
454 if (dfx_use_mmio) { 454 if (dfx_use_mmio) {
455 bar = inb(base_addr + PI_ESIC_K_MEM_ADD_CMP_2); 455 bar = inb(base_addr + PI_ESIC_K_MEM_ADD_CMP_2);
456 bar <<= 8; 456 bar <<= 8;
457 bar |= inb(base_addr + PI_ESIC_K_MEM_ADD_CMP_1); 457 bar |= inb(base_addr + PI_ESIC_K_MEM_ADD_CMP_1);
458 bar <<= 8; 458 bar <<= 8;
459 bar |= inb(base_addr + PI_ESIC_K_MEM_ADD_CMP_0); 459 bar |= inb(base_addr + PI_ESIC_K_MEM_ADD_CMP_0);
460 bar <<= 16; 460 bar <<= 16;
461 *bar_start = bar; 461 *bar_start = bar;
462 bar = inb(base_addr + PI_ESIC_K_MEM_ADD_MASK_2); 462 bar = inb(base_addr + PI_ESIC_K_MEM_ADD_MASK_2);
463 bar <<= 8; 463 bar <<= 8;
464 bar |= inb(base_addr + PI_ESIC_K_MEM_ADD_MASK_1); 464 bar |= inb(base_addr + PI_ESIC_K_MEM_ADD_MASK_1);
465 bar <<= 8; 465 bar <<= 8;
466 bar |= inb(base_addr + PI_ESIC_K_MEM_ADD_MASK_0); 466 bar |= inb(base_addr + PI_ESIC_K_MEM_ADD_MASK_0);
467 bar <<= 16; 467 bar <<= 16;
468 *bar_len = (bar | PI_MEM_ADD_MASK_M) + 1; 468 *bar_len = (bar | PI_MEM_ADD_MASK_M) + 1;
469 } else { 469 } else {
470 *bar_start = base_addr; 470 *bar_start = base_addr;
471 *bar_len = PI_ESIC_K_CSR_IO_LEN; 471 *bar_len = PI_ESIC_K_CSR_IO_LEN;
472 } 472 }
473 } 473 }
474 if (dfx_bus_tc) { 474 if (dfx_bus_tc) {
475 *bar_start = to_tc_dev(bdev)->resource.start + 475 *bar_start = to_tc_dev(bdev)->resource.start +
476 PI_TC_K_CSR_OFFSET; 476 PI_TC_K_CSR_OFFSET;
477 *bar_len = PI_TC_K_CSR_LEN; 477 *bar_len = PI_TC_K_CSR_LEN;
478 } 478 }
479 } 479 }
480 480
481 static const struct net_device_ops dfx_netdev_ops = { 481 static const struct net_device_ops dfx_netdev_ops = {
482 .ndo_open = dfx_open, 482 .ndo_open = dfx_open,
483 .ndo_stop = dfx_close, 483 .ndo_stop = dfx_close,
484 .ndo_start_xmit = dfx_xmt_queue_pkt, 484 .ndo_start_xmit = dfx_xmt_queue_pkt,
485 .ndo_get_stats = dfx_ctl_get_stats, 485 .ndo_get_stats = dfx_ctl_get_stats,
486 .ndo_set_multicast_list = dfx_ctl_set_multicast_list, 486 .ndo_set_multicast_list = dfx_ctl_set_multicast_list,
487 .ndo_set_mac_address = dfx_ctl_set_mac_address, 487 .ndo_set_mac_address = dfx_ctl_set_mac_address,
488 }; 488 };
489 489
490 /* 490 /*
491 * ================ 491 * ================
492 * = dfx_register = 492 * = dfx_register =
493 * ================ 493 * ================
494 * 494 *
495 * Overview: 495 * Overview:
496 * Initializes a supported FDDI controller 496 * Initializes a supported FDDI controller
497 * 497 *
498 * Returns: 498 * Returns:
499 * Condition code 499 * Condition code
500 * 500 *
501 * Arguments: 501 * Arguments:
502 * bdev - pointer to device information 502 * bdev - pointer to device information
503 * 503 *
504 * Functional Description: 504 * Functional Description:
505 * 505 *
506 * Return Codes: 506 * Return Codes:
507 * 0 - This device (fddi0, fddi1, etc) configured successfully 507 * 0 - This device (fddi0, fddi1, etc) configured successfully
508 * -EBUSY - Failed to get resources, or dfx_driver_init failed. 508 * -EBUSY - Failed to get resources, or dfx_driver_init failed.
509 * 509 *
510 * Assumptions: 510 * Assumptions:
511 * It compiles so it should work :-( (PCI cards do :-) 511 * It compiles so it should work :-( (PCI cards do :-)
512 * 512 *
513 * Side Effects: 513 * Side Effects:
514 * Device structures for FDDI adapters (fddi0, fddi1, etc) are 514 * Device structures for FDDI adapters (fddi0, fddi1, etc) are
515 * initialized and the board resources are read and stored in 515 * initialized and the board resources are read and stored in
516 * the device structure. 516 * the device structure.
517 */ 517 */
518 static int __devinit dfx_register(struct device *bdev) 518 static int __devinit dfx_register(struct device *bdev)
519 { 519 {
520 static int version_disp; 520 static int version_disp;
521 int dfx_bus_pci = DFX_BUS_PCI(bdev); 521 int dfx_bus_pci = DFX_BUS_PCI(bdev);
522 int dfx_bus_tc = DFX_BUS_TC(bdev); 522 int dfx_bus_tc = DFX_BUS_TC(bdev);
523 int dfx_use_mmio = DFX_MMIO || dfx_bus_tc; 523 int dfx_use_mmio = DFX_MMIO || dfx_bus_tc;
524 const char *print_name = dev_name(bdev); 524 const char *print_name = dev_name(bdev);
525 struct net_device *dev; 525 struct net_device *dev;
526 DFX_board_t *bp; /* board pointer */ 526 DFX_board_t *bp; /* board pointer */
527 resource_size_t bar_start = 0; /* pointer to port */ 527 resource_size_t bar_start = 0; /* pointer to port */
528 resource_size_t bar_len = 0; /* resource length */ 528 resource_size_t bar_len = 0; /* resource length */
529 int alloc_size; /* total buffer size used */ 529 int alloc_size; /* total buffer size used */
530 struct resource *region; 530 struct resource *region;
531 int err = 0; 531 int err = 0;
532 532
533 if (!version_disp) { /* display version info if adapter is found */ 533 if (!version_disp) { /* display version info if adapter is found */
534 version_disp = 1; /* set display flag to TRUE so that */ 534 version_disp = 1; /* set display flag to TRUE so that */
535 printk(version); /* we only display this string ONCE */ 535 printk(version); /* we only display this string ONCE */
536 } 536 }
537 537
538 dev = alloc_fddidev(sizeof(*bp)); 538 dev = alloc_fddidev(sizeof(*bp));
539 if (!dev) { 539 if (!dev) {
540 printk(KERN_ERR "%s: Unable to allocate fddidev, aborting\n", 540 printk(KERN_ERR "%s: Unable to allocate fddidev, aborting\n",
541 print_name); 541 print_name);
542 return -ENOMEM; 542 return -ENOMEM;
543 } 543 }
544 544
545 /* Enable PCI device. */ 545 /* Enable PCI device. */
546 if (dfx_bus_pci && pci_enable_device(to_pci_dev(bdev))) { 546 if (dfx_bus_pci && pci_enable_device(to_pci_dev(bdev))) {
547 printk(KERN_ERR "%s: Cannot enable PCI device, aborting\n", 547 printk(KERN_ERR "%s: Cannot enable PCI device, aborting\n",
548 print_name); 548 print_name);
549 goto err_out; 549 goto err_out;
550 } 550 }
551 551
552 SET_NETDEV_DEV(dev, bdev); 552 SET_NETDEV_DEV(dev, bdev);
553 553
554 bp = netdev_priv(dev); 554 bp = netdev_priv(dev);
555 bp->bus_dev = bdev; 555 bp->bus_dev = bdev;
556 dev_set_drvdata(bdev, dev); 556 dev_set_drvdata(bdev, dev);
557 557
558 dfx_get_bars(bdev, &bar_start, &bar_len); 558 dfx_get_bars(bdev, &bar_start, &bar_len);
559 559
560 if (dfx_use_mmio) 560 if (dfx_use_mmio)
561 region = request_mem_region(bar_start, bar_len, print_name); 561 region = request_mem_region(bar_start, bar_len, print_name);
562 else 562 else
563 region = request_region(bar_start, bar_len, print_name); 563 region = request_region(bar_start, bar_len, print_name);
564 if (!region) { 564 if (!region) {
565 printk(KERN_ERR "%s: Cannot reserve I/O resource " 565 printk(KERN_ERR "%s: Cannot reserve I/O resource "
566 "0x%lx @ 0x%lx, aborting\n", 566 "0x%lx @ 0x%lx, aborting\n",
567 print_name, (long)bar_len, (long)bar_start); 567 print_name, (long)bar_len, (long)bar_start);
568 err = -EBUSY; 568 err = -EBUSY;
569 goto err_out_disable; 569 goto err_out_disable;
570 } 570 }
571 571
572 /* Set up I/O base address. */ 572 /* Set up I/O base address. */
573 if (dfx_use_mmio) { 573 if (dfx_use_mmio) {
574 bp->base.mem = ioremap_nocache(bar_start, bar_len); 574 bp->base.mem = ioremap_nocache(bar_start, bar_len);
575 if (!bp->base.mem) { 575 if (!bp->base.mem) {
576 printk(KERN_ERR "%s: Cannot map MMIO\n", print_name); 576 printk(KERN_ERR "%s: Cannot map MMIO\n", print_name);
577 err = -ENOMEM; 577 err = -ENOMEM;
578 goto err_out_region; 578 goto err_out_region;
579 } 579 }
580 } else { 580 } else {
581 bp->base.port = bar_start; 581 bp->base.port = bar_start;
582 dev->base_addr = bar_start; 582 dev->base_addr = bar_start;
583 } 583 }
584 584
585 /* Initialize new device structure */ 585 /* Initialize new device structure */
586 dev->netdev_ops = &dfx_netdev_ops; 586 dev->netdev_ops = &dfx_netdev_ops;
587 587
588 if (dfx_bus_pci) 588 if (dfx_bus_pci)
589 pci_set_master(to_pci_dev(bdev)); 589 pci_set_master(to_pci_dev(bdev));
590 590
591 if (dfx_driver_init(dev, print_name, bar_start) != DFX_K_SUCCESS) { 591 if (dfx_driver_init(dev, print_name, bar_start) != DFX_K_SUCCESS) {
592 err = -ENODEV; 592 err = -ENODEV;
593 goto err_out_unmap; 593 goto err_out_unmap;
594 } 594 }
595 595
596 err = register_netdev(dev); 596 err = register_netdev(dev);
597 if (err) 597 if (err)
598 goto err_out_kfree; 598 goto err_out_kfree;
599 599
600 printk("%s: registered as %s\n", print_name, dev->name); 600 printk("%s: registered as %s\n", print_name, dev->name);
601 return 0; 601 return 0;
602 602
603 err_out_kfree: 603 err_out_kfree:
604 alloc_size = sizeof(PI_DESCR_BLOCK) + 604 alloc_size = sizeof(PI_DESCR_BLOCK) +
605 PI_CMD_REQ_K_SIZE_MAX + PI_CMD_RSP_K_SIZE_MAX + 605 PI_CMD_REQ_K_SIZE_MAX + PI_CMD_RSP_K_SIZE_MAX +
606 #ifndef DYNAMIC_BUFFERS 606 #ifndef DYNAMIC_BUFFERS
607 (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX) + 607 (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX) +
608 #endif 608 #endif
609 sizeof(PI_CONSUMER_BLOCK) + 609 sizeof(PI_CONSUMER_BLOCK) +
610 (PI_ALIGN_K_DESC_BLK - 1); 610 (PI_ALIGN_K_DESC_BLK - 1);
611 if (bp->kmalloced) 611 if (bp->kmalloced)
612 dma_free_coherent(bdev, alloc_size, 612 dma_free_coherent(bdev, alloc_size,
613 bp->kmalloced, bp->kmalloced_dma); 613 bp->kmalloced, bp->kmalloced_dma);
614 614
615 err_out_unmap: 615 err_out_unmap:
616 if (dfx_use_mmio) 616 if (dfx_use_mmio)
617 iounmap(bp->base.mem); 617 iounmap(bp->base.mem);
618 618
619 err_out_region: 619 err_out_region:
620 if (dfx_use_mmio) 620 if (dfx_use_mmio)
621 release_mem_region(bar_start, bar_len); 621 release_mem_region(bar_start, bar_len);
622 else 622 else
623 release_region(bar_start, bar_len); 623 release_region(bar_start, bar_len);
624 624
625 err_out_disable: 625 err_out_disable:
626 if (dfx_bus_pci) 626 if (dfx_bus_pci)
627 pci_disable_device(to_pci_dev(bdev)); 627 pci_disable_device(to_pci_dev(bdev));
628 628
629 err_out: 629 err_out:
630 free_netdev(dev); 630 free_netdev(dev);
631 return err; 631 return err;
632 } 632 }
633 633
634 634
635 /* 635 /*
636 * ================ 636 * ================
637 * = dfx_bus_init = 637 * = dfx_bus_init =
638 * ================ 638 * ================
639 * 639 *
640 * Overview: 640 * Overview:
641 * Initializes the bus-specific controller logic. 641 * Initializes the bus-specific controller logic.
642 * 642 *
643 * Returns: 643 * Returns:
644 * None 644 * None
645 * 645 *
646 * Arguments: 646 * Arguments:
647 * dev - pointer to device information 647 * dev - pointer to device information
648 * 648 *
649 * Functional Description: 649 * Functional Description:
650 * Determine and save adapter IRQ in device table, 650 * Determine and save adapter IRQ in device table,
651 * then perform bus-specific logic initialization. 651 * then perform bus-specific logic initialization.
652 * 652 *
653 * Return Codes: 653 * Return Codes:
654 * None 654 * None
655 * 655 *
656 * Assumptions: 656 * Assumptions:
657 * bp->base has already been set with the proper 657 * bp->base has already been set with the proper
658 * base I/O address for this device. 658 * base I/O address for this device.
659 * 659 *
660 * Side Effects: 660 * Side Effects:
661 * Interrupts are enabled at the adapter bus-specific logic. 661 * Interrupts are enabled at the adapter bus-specific logic.
662 * Note: Interrupts at the DMA engine (PDQ chip) are not 662 * Note: Interrupts at the DMA engine (PDQ chip) are not
663 * enabled yet. 663 * enabled yet.
664 */ 664 */
665 665
666 static void __devinit dfx_bus_init(struct net_device *dev) 666 static void __devinit dfx_bus_init(struct net_device *dev)
667 { 667 {
668 DFX_board_t *bp = netdev_priv(dev); 668 DFX_board_t *bp = netdev_priv(dev);
669 struct device *bdev = bp->bus_dev; 669 struct device *bdev = bp->bus_dev;
670 int dfx_bus_pci = DFX_BUS_PCI(bdev); 670 int dfx_bus_pci = DFX_BUS_PCI(bdev);
671 int dfx_bus_eisa = DFX_BUS_EISA(bdev); 671 int dfx_bus_eisa = DFX_BUS_EISA(bdev);
672 int dfx_bus_tc = DFX_BUS_TC(bdev); 672 int dfx_bus_tc = DFX_BUS_TC(bdev);
673 int dfx_use_mmio = DFX_MMIO || dfx_bus_tc; 673 int dfx_use_mmio = DFX_MMIO || dfx_bus_tc;
674 u8 val; 674 u8 val;
675 675
676 DBG_printk("In dfx_bus_init...\n"); 676 DBG_printk("In dfx_bus_init...\n");
677 677
678 /* Initialize a pointer back to the net_device struct */ 678 /* Initialize a pointer back to the net_device struct */
679 bp->dev = dev; 679 bp->dev = dev;
680 680
681 /* Initialize adapter based on bus type */ 681 /* Initialize adapter based on bus type */
682 682
683 if (dfx_bus_tc) 683 if (dfx_bus_tc)
684 dev->irq = to_tc_dev(bdev)->interrupt; 684 dev->irq = to_tc_dev(bdev)->interrupt;
685 if (dfx_bus_eisa) { 685 if (dfx_bus_eisa) {
686 unsigned long base_addr = to_eisa_device(bdev)->base_addr; 686 unsigned long base_addr = to_eisa_device(bdev)->base_addr;
687 687
688 /* Get the interrupt level from the ESIC chip. */ 688 /* Get the interrupt level from the ESIC chip. */
689 val = inb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0); 689 val = inb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0);
690 val &= PI_CONFIG_STAT_0_M_IRQ; 690 val &= PI_CONFIG_STAT_0_M_IRQ;
691 val >>= PI_CONFIG_STAT_0_V_IRQ; 691 val >>= PI_CONFIG_STAT_0_V_IRQ;
692 692
693 switch (val) { 693 switch (val) {
694 case PI_CONFIG_STAT_0_IRQ_K_9: 694 case PI_CONFIG_STAT_0_IRQ_K_9:
695 dev->irq = 9; 695 dev->irq = 9;
696 break; 696 break;
697 697
698 case PI_CONFIG_STAT_0_IRQ_K_10: 698 case PI_CONFIG_STAT_0_IRQ_K_10:
699 dev->irq = 10; 699 dev->irq = 10;
700 break; 700 break;
701 701
702 case PI_CONFIG_STAT_0_IRQ_K_11: 702 case PI_CONFIG_STAT_0_IRQ_K_11:
703 dev->irq = 11; 703 dev->irq = 11;
704 break; 704 break;
705 705
706 case PI_CONFIG_STAT_0_IRQ_K_15: 706 case PI_CONFIG_STAT_0_IRQ_K_15:
707 dev->irq = 15; 707 dev->irq = 15;
708 break; 708 break;
709 } 709 }
710 710
711 /* 711 /*
712 * Enable memory decoding (MEMCS0) and/or port decoding 712 * Enable memory decoding (MEMCS0) and/or port decoding
713 * (IOCS1/IOCS0) as appropriate in Function Control 713 * (IOCS1/IOCS0) as appropriate in Function Control
714 * Register. One of the port chip selects seems to be 714 * Register. One of the port chip selects seems to be
715 * used for the Burst Holdoff register, but this bit of 715 * used for the Burst Holdoff register, but this bit of
716 * documentation is missing and as yet it has not been 716 * documentation is missing and as yet it has not been
717 * determined which of the two. This is also the reason 717 * determined which of the two. This is also the reason
718 * the size of the decoded port range is twice as large 718 * the size of the decoded port range is twice as large
719 * as one required by the PDQ. 719 * as one required by the PDQ.
720 */ 720 */
721 721
722 /* Set the decode range of the board. */ 722 /* Set the decode range of the board. */
723 val = ((bp->base.port >> 12) << PI_IO_CMP_V_SLOT); 723 val = ((bp->base.port >> 12) << PI_IO_CMP_V_SLOT);
724 outb(base_addr + PI_ESIC_K_IO_ADD_CMP_0_1, val); 724 outb(base_addr + PI_ESIC_K_IO_ADD_CMP_0_1, val);
725 outb(base_addr + PI_ESIC_K_IO_ADD_CMP_0_0, 0); 725 outb(base_addr + PI_ESIC_K_IO_ADD_CMP_0_0, 0);
726 outb(base_addr + PI_ESIC_K_IO_ADD_CMP_1_1, val); 726 outb(base_addr + PI_ESIC_K_IO_ADD_CMP_1_1, val);
727 outb(base_addr + PI_ESIC_K_IO_ADD_CMP_1_0, 0); 727 outb(base_addr + PI_ESIC_K_IO_ADD_CMP_1_0, 0);
728 val = PI_ESIC_K_CSR_IO_LEN - 1; 728 val = PI_ESIC_K_CSR_IO_LEN - 1;
729 outb(base_addr + PI_ESIC_K_IO_ADD_MASK_0_1, (val >> 8) & 0xff); 729 outb(base_addr + PI_ESIC_K_IO_ADD_MASK_0_1, (val >> 8) & 0xff);
730 outb(base_addr + PI_ESIC_K_IO_ADD_MASK_0_0, val & 0xff); 730 outb(base_addr + PI_ESIC_K_IO_ADD_MASK_0_0, val & 0xff);
731 outb(base_addr + PI_ESIC_K_IO_ADD_MASK_1_1, (val >> 8) & 0xff); 731 outb(base_addr + PI_ESIC_K_IO_ADD_MASK_1_1, (val >> 8) & 0xff);
732 outb(base_addr + PI_ESIC_K_IO_ADD_MASK_1_0, val & 0xff); 732 outb(base_addr + PI_ESIC_K_IO_ADD_MASK_1_0, val & 0xff);
733 733
734 /* Enable the decoders. */ 734 /* Enable the decoders. */
735 val = PI_FUNCTION_CNTRL_M_IOCS1 | PI_FUNCTION_CNTRL_M_IOCS0; 735 val = PI_FUNCTION_CNTRL_M_IOCS1 | PI_FUNCTION_CNTRL_M_IOCS0;
736 if (dfx_use_mmio) 736 if (dfx_use_mmio)
737 val |= PI_FUNCTION_CNTRL_M_MEMCS0; 737 val |= PI_FUNCTION_CNTRL_M_MEMCS0;
738 outb(base_addr + PI_ESIC_K_FUNCTION_CNTRL, val); 738 outb(base_addr + PI_ESIC_K_FUNCTION_CNTRL, val);
739 739
740 /* 740 /*
741 * Enable access to the rest of the module 741 * Enable access to the rest of the module
742 * (including PDQ and packet memory). 742 * (including PDQ and packet memory).
743 */ 743 */
744 val = PI_SLOT_CNTRL_M_ENB; 744 val = PI_SLOT_CNTRL_M_ENB;
745 outb(base_addr + PI_ESIC_K_SLOT_CNTRL, val); 745 outb(base_addr + PI_ESIC_K_SLOT_CNTRL, val);
746 746
747 /* 747 /*
748 * Map PDQ registers into memory or port space. This is 748 * Map PDQ registers into memory or port space. This is
749 * done with a bit in the Burst Holdoff register. 749 * done with a bit in the Burst Holdoff register.
750 */ 750 */
751 val = inb(base_addr + PI_DEFEA_K_BURST_HOLDOFF); 751 val = inb(base_addr + PI_DEFEA_K_BURST_HOLDOFF);
752 if (dfx_use_mmio) 752 if (dfx_use_mmio)
753 val |= PI_BURST_HOLDOFF_V_MEM_MAP; 753 val |= PI_BURST_HOLDOFF_V_MEM_MAP;
754 else 754 else
755 val &= ~PI_BURST_HOLDOFF_V_MEM_MAP; 755 val &= ~PI_BURST_HOLDOFF_V_MEM_MAP;
756 outb(base_addr + PI_DEFEA_K_BURST_HOLDOFF, val); 756 outb(base_addr + PI_DEFEA_K_BURST_HOLDOFF, val);
757 757
758 /* Enable interrupts at EISA bus interface chip (ESIC) */ 758 /* Enable interrupts at EISA bus interface chip (ESIC) */
759 val = inb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0); 759 val = inb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0);
760 val |= PI_CONFIG_STAT_0_M_INT_ENB; 760 val |= PI_CONFIG_STAT_0_M_INT_ENB;
761 outb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0, val); 761 outb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0, val);
762 } 762 }
763 if (dfx_bus_pci) { 763 if (dfx_bus_pci) {
764 struct pci_dev *pdev = to_pci_dev(bdev); 764 struct pci_dev *pdev = to_pci_dev(bdev);
765 765
766 /* Get the interrupt level from the PCI Configuration Table */ 766 /* Get the interrupt level from the PCI Configuration Table */
767 767
768 dev->irq = pdev->irq; 768 dev->irq = pdev->irq;
769 769
770 /* Check Latency Timer and set if less than minimal */ 770 /* Check Latency Timer and set if less than minimal */
771 771
772 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &val); 772 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &val);
773 if (val < PFI_K_LAT_TIMER_MIN) { 773 if (val < PFI_K_LAT_TIMER_MIN) {
774 val = PFI_K_LAT_TIMER_DEF; 774 val = PFI_K_LAT_TIMER_DEF;
775 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, val); 775 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, val);
776 } 776 }
777 777
778 /* Enable interrupts at PCI bus interface chip (PFI) */ 778 /* Enable interrupts at PCI bus interface chip (PFI) */
779 val = PFI_MODE_M_PDQ_INT_ENB | PFI_MODE_M_DMA_ENB; 779 val = PFI_MODE_M_PDQ_INT_ENB | PFI_MODE_M_DMA_ENB;
780 dfx_port_write_long(bp, PFI_K_REG_MODE_CTRL, val); 780 dfx_port_write_long(bp, PFI_K_REG_MODE_CTRL, val);
781 } 781 }
782 } 782 }
783 783
784 /* 784 /*
785 * ================== 785 * ==================
786 * = dfx_bus_uninit = 786 * = dfx_bus_uninit =
787 * ================== 787 * ==================
788 * 788 *
789 * Overview: 789 * Overview:
790 * Uninitializes the bus-specific controller logic. 790 * Uninitializes the bus-specific controller logic.
791 * 791 *
792 * Returns: 792 * Returns:
793 * None 793 * None
794 * 794 *
795 * Arguments: 795 * Arguments:
796 * dev - pointer to device information 796 * dev - pointer to device information
797 * 797 *
798 * Functional Description: 798 * Functional Description:
799 * Perform bus-specific logic uninitialization. 799 * Perform bus-specific logic uninitialization.
800 * 800 *
801 * Return Codes: 801 * Return Codes:
802 * None 802 * None
803 * 803 *
804 * Assumptions: 804 * Assumptions:
805 * bp->base has already been set with the proper 805 * bp->base has already been set with the proper
806 * base I/O address for this device. 806 * base I/O address for this device.
807 * 807 *
808 * Side Effects: 808 * Side Effects:
809 * Interrupts are disabled at the adapter bus-specific logic. 809 * Interrupts are disabled at the adapter bus-specific logic.
810 */ 810 */
811 811
812 static void __devexit dfx_bus_uninit(struct net_device *dev) 812 static void __devexit dfx_bus_uninit(struct net_device *dev)
813 { 813 {
814 DFX_board_t *bp = netdev_priv(dev); 814 DFX_board_t *bp = netdev_priv(dev);
815 struct device *bdev = bp->bus_dev; 815 struct device *bdev = bp->bus_dev;
816 int dfx_bus_pci = DFX_BUS_PCI(bdev); 816 int dfx_bus_pci = DFX_BUS_PCI(bdev);
817 int dfx_bus_eisa = DFX_BUS_EISA(bdev); 817 int dfx_bus_eisa = DFX_BUS_EISA(bdev);
818 u8 val; 818 u8 val;
819 819
820 DBG_printk("In dfx_bus_uninit...\n"); 820 DBG_printk("In dfx_bus_uninit...\n");
821 821
822 /* Uninitialize adapter based on bus type */ 822 /* Uninitialize adapter based on bus type */
823 823
824 if (dfx_bus_eisa) { 824 if (dfx_bus_eisa) {
825 unsigned long base_addr = to_eisa_device(bdev)->base_addr; 825 unsigned long base_addr = to_eisa_device(bdev)->base_addr;
826 826
827 /* Disable interrupts at EISA bus interface chip (ESIC) */ 827 /* Disable interrupts at EISA bus interface chip (ESIC) */
828 val = inb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0); 828 val = inb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0);
829 val &= ~PI_CONFIG_STAT_0_M_INT_ENB; 829 val &= ~PI_CONFIG_STAT_0_M_INT_ENB;
830 outb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0, val); 830 outb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0, val);
831 } 831 }
832 if (dfx_bus_pci) { 832 if (dfx_bus_pci) {
833 /* Disable interrupts at PCI bus interface chip (PFI) */ 833 /* Disable interrupts at PCI bus interface chip (PFI) */
834 dfx_port_write_long(bp, PFI_K_REG_MODE_CTRL, 0); 834 dfx_port_write_long(bp, PFI_K_REG_MODE_CTRL, 0);
835 } 835 }
836 } 836 }
837 837
838 838
839 /* 839 /*
840 * ======================== 840 * ========================
841 * = dfx_bus_config_check = 841 * = dfx_bus_config_check =
842 * ======================== 842 * ========================
843 * 843 *
844 * Overview: 844 * Overview:
845 * Checks the configuration (burst size, full-duplex, etc.) If any parameters 845 * Checks the configuration (burst size, full-duplex, etc.) If any parameters
846 * are illegal, then this routine will set new defaults. 846 * are illegal, then this routine will set new defaults.
847 * 847 *
848 * Returns: 848 * Returns:
849 * None 849 * None
850 * 850 *
851 * Arguments: 851 * Arguments:
852 * bp - pointer to board information 852 * bp - pointer to board information
853 * 853 *
854 * Functional Description: 854 * Functional Description:
855 * For Revision 1 FDDI EISA, Revision 2 or later FDDI EISA with rev E or later 855 * For Revision 1 FDDI EISA, Revision 2 or later FDDI EISA with rev E or later
856 * PDQ, and all FDDI PCI controllers, all values are legal. 856 * PDQ, and all FDDI PCI controllers, all values are legal.
857 * 857 *
858 * Return Codes: 858 * Return Codes:
859 * None 859 * None
860 * 860 *
861 * Assumptions: 861 * Assumptions:
862 * dfx_adap_init has NOT been called yet so burst size and other items have 862 * dfx_adap_init has NOT been called yet so burst size and other items have
863 * not been set. 863 * not been set.
864 * 864 *
865 * Side Effects: 865 * Side Effects:
866 * None 866 * None
867 */ 867 */
868 868
869 static void __devinit dfx_bus_config_check(DFX_board_t *bp) 869 static void __devinit dfx_bus_config_check(DFX_board_t *bp)
870 { 870 {
871 struct device __maybe_unused *bdev = bp->bus_dev; 871 struct device __maybe_unused *bdev = bp->bus_dev;
872 int dfx_bus_eisa = DFX_BUS_EISA(bdev); 872 int dfx_bus_eisa = DFX_BUS_EISA(bdev);
873 int status; /* return code from adapter port control call */ 873 int status; /* return code from adapter port control call */
874 u32 host_data; /* LW data returned from port control call */ 874 u32 host_data; /* LW data returned from port control call */
875 875
876 DBG_printk("In dfx_bus_config_check...\n"); 876 DBG_printk("In dfx_bus_config_check...\n");
877 877
878 /* Configuration check only valid for EISA adapter */ 878 /* Configuration check only valid for EISA adapter */
879 879
880 if (dfx_bus_eisa) { 880 if (dfx_bus_eisa) {
881 /* 881 /*
882 * First check if revision 2 EISA controller. Rev. 1 cards used 882 * First check if revision 2 EISA controller. Rev. 1 cards used
883 * PDQ revision B, so no workaround needed in this case. Rev. 3 883 * PDQ revision B, so no workaround needed in this case. Rev. 3
884 * cards used PDQ revision E, so no workaround needed in this 884 * cards used PDQ revision E, so no workaround needed in this
885 * case, either. Only Rev. 2 cards used either Rev. D or E 885 * case, either. Only Rev. 2 cards used either Rev. D or E
886 * chips, so we must verify the chip revision on Rev. 2 cards. 886 * chips, so we must verify the chip revision on Rev. 2 cards.
887 */ 887 */
888 if (to_eisa_device(bdev)->id.driver_data == DEFEA_PROD_ID_2) { 888 if (to_eisa_device(bdev)->id.driver_data == DEFEA_PROD_ID_2) {
889 /* 889 /*
890 * Revision 2 FDDI EISA controller found, 890 * Revision 2 FDDI EISA controller found,
891 * so let's check PDQ revision of adapter. 891 * so let's check PDQ revision of adapter.
892 */ 892 */
893 status = dfx_hw_port_ctrl_req(bp, 893 status = dfx_hw_port_ctrl_req(bp,
894 PI_PCTRL_M_SUB_CMD, 894 PI_PCTRL_M_SUB_CMD,
895 PI_SUB_CMD_K_PDQ_REV_GET, 895 PI_SUB_CMD_K_PDQ_REV_GET,
896 0, 896 0,
897 &host_data); 897 &host_data);
898 if ((status != DFX_K_SUCCESS) || (host_data == 2)) 898 if ((status != DFX_K_SUCCESS) || (host_data == 2))
899 { 899 {
900 /* 900 /*
901 * Either we couldn't determine the PDQ revision, or 901 * Either we couldn't determine the PDQ revision, or
902 * we determined that it is at revision D. In either case, 902 * we determined that it is at revision D. In either case,
903 * we need to implement the workaround. 903 * we need to implement the workaround.
904 */ 904 */
905 905
906 /* Ensure that the burst size is set to 8 longwords or less */ 906 /* Ensure that the burst size is set to 8 longwords or less */
907 907
908 switch (bp->burst_size) 908 switch (bp->burst_size)
909 { 909 {
910 case PI_PDATA_B_DMA_BURST_SIZE_32: 910 case PI_PDATA_B_DMA_BURST_SIZE_32:
911 case PI_PDATA_B_DMA_BURST_SIZE_16: 911 case PI_PDATA_B_DMA_BURST_SIZE_16:
912 bp->burst_size = PI_PDATA_B_DMA_BURST_SIZE_8; 912 bp->burst_size = PI_PDATA_B_DMA_BURST_SIZE_8;
913 break; 913 break;
914 914
915 default: 915 default:
916 break; 916 break;
917 } 917 }
918 918
919 /* Ensure that full-duplex mode is not enabled */ 919 /* Ensure that full-duplex mode is not enabled */
920 920
921 bp->full_duplex_enb = PI_SNMP_K_FALSE; 921 bp->full_duplex_enb = PI_SNMP_K_FALSE;
922 } 922 }
923 } 923 }
924 } 924 }
925 } 925 }
926 926
927 927
928 /* 928 /*
929 * =================== 929 * ===================
930 * = dfx_driver_init = 930 * = dfx_driver_init =
931 * =================== 931 * ===================
932 * 932 *
933 * Overview: 933 * Overview:
934 * Initializes remaining adapter board structure information 934 * Initializes remaining adapter board structure information
935 * and makes sure adapter is in a safe state prior to dfx_open(). 935 * and makes sure adapter is in a safe state prior to dfx_open().
936 * 936 *
937 * Returns: 937 * Returns:
938 * Condition code 938 * Condition code
939 * 939 *
940 * Arguments: 940 * Arguments:
941 * dev - pointer to device information 941 * dev - pointer to device information
942 * print_name - printable device name 942 * print_name - printable device name
943 * 943 *
944 * Functional Description: 944 * Functional Description:
945 * This function allocates additional resources such as the host memory 945 * This function allocates additional resources such as the host memory
946 * blocks needed by the adapter (eg. descriptor and consumer blocks). 946 * blocks needed by the adapter (eg. descriptor and consumer blocks).
947 * Remaining bus initialization steps are also completed. The adapter 947 * Remaining bus initialization steps are also completed. The adapter
948 * is also reset so that it is in the DMA_UNAVAILABLE state. The OS 948 * is also reset so that it is in the DMA_UNAVAILABLE state. The OS
949 * must call dfx_open() to open the adapter and bring it on-line. 949 * must call dfx_open() to open the adapter and bring it on-line.
950 * 950 *
951 * Return Codes: 951 * Return Codes:
952 * DFX_K_SUCCESS - initialization succeeded 952 * DFX_K_SUCCESS - initialization succeeded
953 * DFX_K_FAILURE - initialization failed - could not allocate memory 953 * DFX_K_FAILURE - initialization failed - could not allocate memory
954 * or read adapter MAC address 954 * or read adapter MAC address
955 * 955 *
956 * Assumptions: 956 * Assumptions:
957 * Memory allocated from pci_alloc_consistent() call is physically 957 * Memory allocated from pci_alloc_consistent() call is physically
958 * contiguous, locked memory. 958 * contiguous, locked memory.
959 * 959 *
960 * Side Effects: 960 * Side Effects:
961 * Adapter is reset and should be in DMA_UNAVAILABLE state before 961 * Adapter is reset and should be in DMA_UNAVAILABLE state before
962 * returning from this routine. 962 * returning from this routine.
963 */ 963 */
964 964
965 static int __devinit dfx_driver_init(struct net_device *dev, 965 static int __devinit dfx_driver_init(struct net_device *dev,
966 const char *print_name, 966 const char *print_name,
967 resource_size_t bar_start) 967 resource_size_t bar_start)
968 { 968 {
969 DFX_board_t *bp = netdev_priv(dev); 969 DFX_board_t *bp = netdev_priv(dev);
970 struct device *bdev = bp->bus_dev; 970 struct device *bdev = bp->bus_dev;
971 int dfx_bus_pci = DFX_BUS_PCI(bdev); 971 int dfx_bus_pci = DFX_BUS_PCI(bdev);
972 int dfx_bus_eisa = DFX_BUS_EISA(bdev); 972 int dfx_bus_eisa = DFX_BUS_EISA(bdev);
973 int dfx_bus_tc = DFX_BUS_TC(bdev); 973 int dfx_bus_tc = DFX_BUS_TC(bdev);
974 int dfx_use_mmio = DFX_MMIO || dfx_bus_tc; 974 int dfx_use_mmio = DFX_MMIO || dfx_bus_tc;
975 int alloc_size; /* total buffer size needed */ 975 int alloc_size; /* total buffer size needed */
976 char *top_v, *curr_v; /* virtual addrs into memory block */ 976 char *top_v, *curr_v; /* virtual addrs into memory block */
977 dma_addr_t top_p, curr_p; /* physical addrs into memory block */ 977 dma_addr_t top_p, curr_p; /* physical addrs into memory block */
978 u32 data; /* host data register value */ 978 u32 data; /* host data register value */
979 __le32 le32; 979 __le32 le32;
980 char *board_name = NULL; 980 char *board_name = NULL;
981 981
982 DBG_printk("In dfx_driver_init...\n"); 982 DBG_printk("In dfx_driver_init...\n");
983 983
984 /* Initialize bus-specific hardware registers */ 984 /* Initialize bus-specific hardware registers */
985 985
986 dfx_bus_init(dev); 986 dfx_bus_init(dev);
987 987
988 /* 988 /*
989 * Initialize default values for configurable parameters 989 * Initialize default values for configurable parameters
990 * 990 *
991 * Note: All of these parameters are ones that a user may 991 * Note: All of these parameters are ones that a user may
992 * want to customize. It'd be nice to break these 992 * want to customize. It'd be nice to break these
993 * out into Space.c or someplace else that's more 993 * out into Space.c or someplace else that's more
994 * accessible/understandable than this file. 994 * accessible/understandable than this file.
995 */ 995 */
996 996
997 bp->full_duplex_enb = PI_SNMP_K_FALSE; 997 bp->full_duplex_enb = PI_SNMP_K_FALSE;
998 bp->req_ttrt = 8 * 12500; /* 8ms in 80 nanosec units */ 998 bp->req_ttrt = 8 * 12500; /* 8ms in 80 nanosec units */
999 bp->burst_size = PI_PDATA_B_DMA_BURST_SIZE_DEF; 999 bp->burst_size = PI_PDATA_B_DMA_BURST_SIZE_DEF;
1000 bp->rcv_bufs_to_post = RCV_BUFS_DEF; 1000 bp->rcv_bufs_to_post = RCV_BUFS_DEF;
1001 1001
1002 /* 1002 /*
1003 * Ensure that HW configuration is OK 1003 * Ensure that HW configuration is OK
1004 * 1004 *
1005 * Note: Depending on the hardware revision, we may need to modify 1005 * Note: Depending on the hardware revision, we may need to modify
1006 * some of the configurable parameters to workaround hardware 1006 * some of the configurable parameters to workaround hardware
1007 * limitations. We'll perform this configuration check AFTER 1007 * limitations. We'll perform this configuration check AFTER
1008 * setting the parameters to their default values. 1008 * setting the parameters to their default values.
1009 */ 1009 */
1010 1010
1011 dfx_bus_config_check(bp); 1011 dfx_bus_config_check(bp);
1012 1012
1013 /* Disable PDQ interrupts first */ 1013 /* Disable PDQ interrupts first */
1014 1014
1015 dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS); 1015 dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS);
1016 1016
1017 /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */ 1017 /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */
1018 1018
1019 (void) dfx_hw_dma_uninit(bp, PI_PDATA_A_RESET_M_SKIP_ST); 1019 (void) dfx_hw_dma_uninit(bp, PI_PDATA_A_RESET_M_SKIP_ST);
1020 1020
1021 /* Read the factory MAC address from the adapter then save it */ 1021 /* Read the factory MAC address from the adapter then save it */
1022 1022
1023 if (dfx_hw_port_ctrl_req(bp, PI_PCTRL_M_MLA, PI_PDATA_A_MLA_K_LO, 0, 1023 if (dfx_hw_port_ctrl_req(bp, PI_PCTRL_M_MLA, PI_PDATA_A_MLA_K_LO, 0,
1024 &data) != DFX_K_SUCCESS) { 1024 &data) != DFX_K_SUCCESS) {
1025 printk("%s: Could not read adapter factory MAC address!\n", 1025 printk("%s: Could not read adapter factory MAC address!\n",
1026 print_name); 1026 print_name);
1027 return(DFX_K_FAILURE); 1027 return(DFX_K_FAILURE);
1028 } 1028 }
1029 le32 = cpu_to_le32(data); 1029 le32 = cpu_to_le32(data);
1030 memcpy(&bp->factory_mac_addr[0], &le32, sizeof(u32)); 1030 memcpy(&bp->factory_mac_addr[0], &le32, sizeof(u32));
1031 1031
1032 if (dfx_hw_port_ctrl_req(bp, PI_PCTRL_M_MLA, PI_PDATA_A_MLA_K_HI, 0, 1032 if (dfx_hw_port_ctrl_req(bp, PI_PCTRL_M_MLA, PI_PDATA_A_MLA_K_HI, 0,
1033 &data) != DFX_K_SUCCESS) { 1033 &data) != DFX_K_SUCCESS) {
1034 printk("%s: Could not read adapter factory MAC address!\n", 1034 printk("%s: Could not read adapter factory MAC address!\n",
1035 print_name); 1035 print_name);
1036 return(DFX_K_FAILURE); 1036 return(DFX_K_FAILURE);
1037 } 1037 }
1038 le32 = cpu_to_le32(data); 1038 le32 = cpu_to_le32(data);
1039 memcpy(&bp->factory_mac_addr[4], &le32, sizeof(u16)); 1039 memcpy(&bp->factory_mac_addr[4], &le32, sizeof(u16));
1040 1040
1041 /* 1041 /*
1042 * Set current address to factory address 1042 * Set current address to factory address
1043 * 1043 *
1044 * Note: Node address override support is handled through 1044 * Note: Node address override support is handled through
1045 * dfx_ctl_set_mac_address. 1045 * dfx_ctl_set_mac_address.
1046 */ 1046 */
1047 1047
1048 memcpy(dev->dev_addr, bp->factory_mac_addr, FDDI_K_ALEN); 1048 memcpy(dev->dev_addr, bp->factory_mac_addr, FDDI_K_ALEN);
1049 if (dfx_bus_tc) 1049 if (dfx_bus_tc)
1050 board_name = "DEFTA"; 1050 board_name = "DEFTA";
1051 if (dfx_bus_eisa) 1051 if (dfx_bus_eisa)
1052 board_name = "DEFEA"; 1052 board_name = "DEFEA";
1053 if (dfx_bus_pci) 1053 if (dfx_bus_pci)
1054 board_name = "DEFPA"; 1054 board_name = "DEFPA";
1055 pr_info("%s: %s at %saddr = 0x%llx, IRQ = %d, " 1055 pr_info("%s: %s at %saddr = 0x%llx, IRQ = %d, Hardware addr = %pMF\n",
1056 "Hardware addr = %02X-%02X-%02X-%02X-%02X-%02X\n",
1057 print_name, board_name, dfx_use_mmio ? "" : "I/O ", 1056 print_name, board_name, dfx_use_mmio ? "" : "I/O ",
1058 (long long)bar_start, dev->irq, 1057 (long long)bar_start, dev->irq, dev->dev_addr);
1059 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
1060 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
1061 1058
1062 /* 1059 /*
1063 * Get memory for descriptor block, consumer block, and other buffers 1060 * Get memory for descriptor block, consumer block, and other buffers
1064 * that need to be DMA read or written to by the adapter. 1061 * that need to be DMA read or written to by the adapter.
1065 */ 1062 */
1066 1063
1067 alloc_size = sizeof(PI_DESCR_BLOCK) + 1064 alloc_size = sizeof(PI_DESCR_BLOCK) +
1068 PI_CMD_REQ_K_SIZE_MAX + 1065 PI_CMD_REQ_K_SIZE_MAX +
1069 PI_CMD_RSP_K_SIZE_MAX + 1066 PI_CMD_RSP_K_SIZE_MAX +
1070 #ifndef DYNAMIC_BUFFERS 1067 #ifndef DYNAMIC_BUFFERS
1071 (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX) + 1068 (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX) +
1072 #endif 1069 #endif
1073 sizeof(PI_CONSUMER_BLOCK) + 1070 sizeof(PI_CONSUMER_BLOCK) +
1074 (PI_ALIGN_K_DESC_BLK - 1); 1071 (PI_ALIGN_K_DESC_BLK - 1);
1075 bp->kmalloced = top_v = dma_alloc_coherent(bp->bus_dev, alloc_size, 1072 bp->kmalloced = top_v = dma_alloc_coherent(bp->bus_dev, alloc_size,
1076 &bp->kmalloced_dma, 1073 &bp->kmalloced_dma,
1077 GFP_ATOMIC); 1074 GFP_ATOMIC);
1078 if (top_v == NULL) { 1075 if (top_v == NULL) {
1079 printk("%s: Could not allocate memory for host buffers " 1076 printk("%s: Could not allocate memory for host buffers "
1080 "and structures!\n", print_name); 1077 "and structures!\n", print_name);
1081 return(DFX_K_FAILURE); 1078 return(DFX_K_FAILURE);
1082 } 1079 }
1083 memset(top_v, 0, alloc_size); /* zero out memory before continuing */ 1080 memset(top_v, 0, alloc_size); /* zero out memory before continuing */
1084 top_p = bp->kmalloced_dma; /* get physical address of buffer */ 1081 top_p = bp->kmalloced_dma; /* get physical address of buffer */
1085 1082
1086 /* 1083 /*
1087 * To guarantee the 8K alignment required for the descriptor block, 8K - 1 1084 * To guarantee the 8K alignment required for the descriptor block, 8K - 1
1088 * plus the amount of memory needed was allocated. The physical address 1085 * plus the amount of memory needed was allocated. The physical address
1089 * is now 8K aligned. By carving up the memory in a specific order, 1086 * is now 8K aligned. By carving up the memory in a specific order,
1090 * we'll guarantee the alignment requirements for all other structures. 1087 * we'll guarantee the alignment requirements for all other structures.
1091 * 1088 *
1092 * Note: If the assumptions change regarding the non-paged, non-cached, 1089 * Note: If the assumptions change regarding the non-paged, non-cached,
1093 * physically contiguous nature of the memory block or the address 1090 * physically contiguous nature of the memory block or the address
1094 * alignments, then we'll need to implement a different algorithm 1091 * alignments, then we'll need to implement a different algorithm
1095 * for allocating the needed memory. 1092 * for allocating the needed memory.
1096 */ 1093 */
1097 1094
1098 curr_p = ALIGN(top_p, PI_ALIGN_K_DESC_BLK); 1095 curr_p = ALIGN(top_p, PI_ALIGN_K_DESC_BLK);
1099 curr_v = top_v + (curr_p - top_p); 1096 curr_v = top_v + (curr_p - top_p);
1100 1097
1101 /* Reserve space for descriptor block */ 1098 /* Reserve space for descriptor block */
1102 1099
1103 bp->descr_block_virt = (PI_DESCR_BLOCK *) curr_v; 1100 bp->descr_block_virt = (PI_DESCR_BLOCK *) curr_v;
1104 bp->descr_block_phys = curr_p; 1101 bp->descr_block_phys = curr_p;
1105 curr_v += sizeof(PI_DESCR_BLOCK); 1102 curr_v += sizeof(PI_DESCR_BLOCK);
1106 curr_p += sizeof(PI_DESCR_BLOCK); 1103 curr_p += sizeof(PI_DESCR_BLOCK);
1107 1104
1108 /* Reserve space for command request buffer */ 1105 /* Reserve space for command request buffer */
1109 1106
1110 bp->cmd_req_virt = (PI_DMA_CMD_REQ *) curr_v; 1107 bp->cmd_req_virt = (PI_DMA_CMD_REQ *) curr_v;
1111 bp->cmd_req_phys = curr_p; 1108 bp->cmd_req_phys = curr_p;
1112 curr_v += PI_CMD_REQ_K_SIZE_MAX; 1109 curr_v += PI_CMD_REQ_K_SIZE_MAX;
1113 curr_p += PI_CMD_REQ_K_SIZE_MAX; 1110 curr_p += PI_CMD_REQ_K_SIZE_MAX;
1114 1111
1115 /* Reserve space for command response buffer */ 1112 /* Reserve space for command response buffer */
1116 1113
1117 bp->cmd_rsp_virt = (PI_DMA_CMD_RSP *) curr_v; 1114 bp->cmd_rsp_virt = (PI_DMA_CMD_RSP *) curr_v;
1118 bp->cmd_rsp_phys = curr_p; 1115 bp->cmd_rsp_phys = curr_p;
1119 curr_v += PI_CMD_RSP_K_SIZE_MAX; 1116 curr_v += PI_CMD_RSP_K_SIZE_MAX;
1120 curr_p += PI_CMD_RSP_K_SIZE_MAX; 1117 curr_p += PI_CMD_RSP_K_SIZE_MAX;
1121 1118
1122 /* Reserve space for the LLC host receive queue buffers */ 1119 /* Reserve space for the LLC host receive queue buffers */
1123 1120
1124 bp->rcv_block_virt = curr_v; 1121 bp->rcv_block_virt = curr_v;
1125 bp->rcv_block_phys = curr_p; 1122 bp->rcv_block_phys = curr_p;
1126 1123
1127 #ifndef DYNAMIC_BUFFERS 1124 #ifndef DYNAMIC_BUFFERS
1128 curr_v += (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX); 1125 curr_v += (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX);
1129 curr_p += (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX); 1126 curr_p += (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX);
1130 #endif 1127 #endif
1131 1128
1132 /* Reserve space for the consumer block */ 1129 /* Reserve space for the consumer block */
1133 1130
1134 bp->cons_block_virt = (PI_CONSUMER_BLOCK *) curr_v; 1131 bp->cons_block_virt = (PI_CONSUMER_BLOCK *) curr_v;
1135 bp->cons_block_phys = curr_p; 1132 bp->cons_block_phys = curr_p;
1136 1133
1137 /* Display virtual and physical addresses if debug driver */ 1134 /* Display virtual and physical addresses if debug driver */
1138 1135
1139 DBG_printk("%s: Descriptor block virt = %0lX, phys = %0X\n", 1136 DBG_printk("%s: Descriptor block virt = %0lX, phys = %0X\n",
1140 print_name, 1137 print_name,
1141 (long)bp->descr_block_virt, bp->descr_block_phys); 1138 (long)bp->descr_block_virt, bp->descr_block_phys);
1142 DBG_printk("%s: Command Request buffer virt = %0lX, phys = %0X\n", 1139 DBG_printk("%s: Command Request buffer virt = %0lX, phys = %0X\n",
1143 print_name, (long)bp->cmd_req_virt, bp->cmd_req_phys); 1140 print_name, (long)bp->cmd_req_virt, bp->cmd_req_phys);
1144 DBG_printk("%s: Command Response buffer virt = %0lX, phys = %0X\n", 1141 DBG_printk("%s: Command Response buffer virt = %0lX, phys = %0X\n",
1145 print_name, (long)bp->cmd_rsp_virt, bp->cmd_rsp_phys); 1142 print_name, (long)bp->cmd_rsp_virt, bp->cmd_rsp_phys);
1146 DBG_printk("%s: Receive buffer block virt = %0lX, phys = %0X\n", 1143 DBG_printk("%s: Receive buffer block virt = %0lX, phys = %0X\n",
1147 print_name, (long)bp->rcv_block_virt, bp->rcv_block_phys); 1144 print_name, (long)bp->rcv_block_virt, bp->rcv_block_phys);
1148 DBG_printk("%s: Consumer block virt = %0lX, phys = %0X\n", 1145 DBG_printk("%s: Consumer block virt = %0lX, phys = %0X\n",
1149 print_name, (long)bp->cons_block_virt, bp->cons_block_phys); 1146 print_name, (long)bp->cons_block_virt, bp->cons_block_phys);
1150 1147
1151 return(DFX_K_SUCCESS); 1148 return(DFX_K_SUCCESS);
1152 } 1149 }
1153 1150
1154 1151
1155 /* 1152 /*
1156 * ================= 1153 * =================
1157 * = dfx_adap_init = 1154 * = dfx_adap_init =
1158 * ================= 1155 * =================
1159 * 1156 *
1160 * Overview: 1157 * Overview:
1161 * Brings the adapter to the link avail/link unavailable state. 1158 * Brings the adapter to the link avail/link unavailable state.
1162 * 1159 *
1163 * Returns: 1160 * Returns:
1164 * Condition code 1161 * Condition code
1165 * 1162 *
1166 * Arguments: 1163 * Arguments:
1167 * bp - pointer to board information 1164 * bp - pointer to board information
1168 * get_buffers - non-zero if buffers to be allocated 1165 * get_buffers - non-zero if buffers to be allocated
1169 * 1166 *
1170 * Functional Description: 1167 * Functional Description:
1171 * Issues the low-level firmware/hardware calls necessary to bring 1168 * Issues the low-level firmware/hardware calls necessary to bring
1172 * the adapter up, or to properly reset and restore adapter during 1169 * the adapter up, or to properly reset and restore adapter during
1173 * run-time. 1170 * run-time.
1174 * 1171 *
1175 * Return Codes: 1172 * Return Codes:
1176 * DFX_K_SUCCESS - Adapter brought up successfully 1173 * DFX_K_SUCCESS - Adapter brought up successfully
1177 * DFX_K_FAILURE - Adapter initialization failed 1174 * DFX_K_FAILURE - Adapter initialization failed
1178 * 1175 *
1179 * Assumptions: 1176 * Assumptions:
1180 * bp->reset_type should be set to a valid reset type value before 1177 * bp->reset_type should be set to a valid reset type value before
1181 * calling this routine. 1178 * calling this routine.
1182 * 1179 *
1183 * Side Effects: 1180 * Side Effects:
1184 * Adapter should be in LINK_AVAILABLE or LINK_UNAVAILABLE state 1181 * Adapter should be in LINK_AVAILABLE or LINK_UNAVAILABLE state
1185 * upon a successful return of this routine. 1182 * upon a successful return of this routine.
1186 */ 1183 */
1187 1184
1188 static int dfx_adap_init(DFX_board_t *bp, int get_buffers) 1185 static int dfx_adap_init(DFX_board_t *bp, int get_buffers)
1189 { 1186 {
1190 DBG_printk("In dfx_adap_init...\n"); 1187 DBG_printk("In dfx_adap_init...\n");
1191 1188
1192 /* Disable PDQ interrupts first */ 1189 /* Disable PDQ interrupts first */
1193 1190
1194 dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS); 1191 dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS);
1195 1192
1196 /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */ 1193 /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */
1197 1194
1198 if (dfx_hw_dma_uninit(bp, bp->reset_type) != DFX_K_SUCCESS) 1195 if (dfx_hw_dma_uninit(bp, bp->reset_type) != DFX_K_SUCCESS)
1199 { 1196 {
1200 printk("%s: Could not uninitialize/reset adapter!\n", bp->dev->name); 1197 printk("%s: Could not uninitialize/reset adapter!\n", bp->dev->name);
1201 return(DFX_K_FAILURE); 1198 return(DFX_K_FAILURE);
1202 } 1199 }
1203 1200
1204 /* 1201 /*
1205 * When the PDQ is reset, some false Type 0 interrupts may be pending, 1202 * When the PDQ is reset, some false Type 0 interrupts may be pending,
1206 * so we'll acknowledge all Type 0 interrupts now before continuing. 1203 * so we'll acknowledge all Type 0 interrupts now before continuing.
1207 */ 1204 */
1208 1205
1209 dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_0_STATUS, PI_HOST_INT_K_ACK_ALL_TYPE_0); 1206 dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_0_STATUS, PI_HOST_INT_K_ACK_ALL_TYPE_0);
1210 1207
1211 /* 1208 /*
1212 * Clear Type 1 and Type 2 registers before going to DMA_AVAILABLE state 1209 * Clear Type 1 and Type 2 registers before going to DMA_AVAILABLE state
1213 * 1210 *
1214 * Note: We only need to clear host copies of these registers. The PDQ reset 1211 * Note: We only need to clear host copies of these registers. The PDQ reset
1215 * takes care of the on-board register values. 1212 * takes care of the on-board register values.
1216 */ 1213 */
1217 1214
1218 bp->cmd_req_reg.lword = 0; 1215 bp->cmd_req_reg.lword = 0;
1219 bp->cmd_rsp_reg.lword = 0; 1216 bp->cmd_rsp_reg.lword = 0;
1220 bp->rcv_xmt_reg.lword = 0; 1217 bp->rcv_xmt_reg.lword = 0;
1221 1218
1222 /* Clear consumer block before going to DMA_AVAILABLE state */ 1219 /* Clear consumer block before going to DMA_AVAILABLE state */
1223 1220
1224 memset(bp->cons_block_virt, 0, sizeof(PI_CONSUMER_BLOCK)); 1221 memset(bp->cons_block_virt, 0, sizeof(PI_CONSUMER_BLOCK));
1225 1222
1226 /* Initialize the DMA Burst Size */ 1223 /* Initialize the DMA Burst Size */
1227 1224
1228 if (dfx_hw_port_ctrl_req(bp, 1225 if (dfx_hw_port_ctrl_req(bp,
1229 PI_PCTRL_M_SUB_CMD, 1226 PI_PCTRL_M_SUB_CMD,
1230 PI_SUB_CMD_K_BURST_SIZE_SET, 1227 PI_SUB_CMD_K_BURST_SIZE_SET,
1231 bp->burst_size, 1228 bp->burst_size,
1232 NULL) != DFX_K_SUCCESS) 1229 NULL) != DFX_K_SUCCESS)
1233 { 1230 {
1234 printk("%s: Could not set adapter burst size!\n", bp->dev->name); 1231 printk("%s: Could not set adapter burst size!\n", bp->dev->name);
1235 return(DFX_K_FAILURE); 1232 return(DFX_K_FAILURE);
1236 } 1233 }
1237 1234
1238 /* 1235 /*
1239 * Set base address of Consumer Block 1236 * Set base address of Consumer Block
1240 * 1237 *
1241 * Assumption: 32-bit physical address of consumer block is 64 byte 1238 * Assumption: 32-bit physical address of consumer block is 64 byte
1242 * aligned. That is, bits 0-5 of the address must be zero. 1239 * aligned. That is, bits 0-5 of the address must be zero.
1243 */ 1240 */
1244 1241
1245 if (dfx_hw_port_ctrl_req(bp, 1242 if (dfx_hw_port_ctrl_req(bp,
1246 PI_PCTRL_M_CONS_BLOCK, 1243 PI_PCTRL_M_CONS_BLOCK,
1247 bp->cons_block_phys, 1244 bp->cons_block_phys,
1248 0, 1245 0,
1249 NULL) != DFX_K_SUCCESS) 1246 NULL) != DFX_K_SUCCESS)
1250 { 1247 {
1251 printk("%s: Could not set consumer block address!\n", bp->dev->name); 1248 printk("%s: Could not set consumer block address!\n", bp->dev->name);
1252 return(DFX_K_FAILURE); 1249 return(DFX_K_FAILURE);
1253 } 1250 }
1254 1251
1255 /* 1252 /*
1256 * Set the base address of Descriptor Block and bring adapter 1253 * Set the base address of Descriptor Block and bring adapter
1257 * to DMA_AVAILABLE state. 1254 * to DMA_AVAILABLE state.
1258 * 1255 *
1259 * Note: We also set the literal and data swapping requirements 1256 * Note: We also set the literal and data swapping requirements
1260 * in this command. 1257 * in this command.
1261 * 1258 *
1262 * Assumption: 32-bit physical address of descriptor block 1259 * Assumption: 32-bit physical address of descriptor block
1263 * is 8Kbyte aligned. 1260 * is 8Kbyte aligned.
1264 */ 1261 */
1265 if (dfx_hw_port_ctrl_req(bp, PI_PCTRL_M_INIT, 1262 if (dfx_hw_port_ctrl_req(bp, PI_PCTRL_M_INIT,
1266 (u32)(bp->descr_block_phys | 1263 (u32)(bp->descr_block_phys |
1267 PI_PDATA_A_INIT_M_BSWAP_INIT), 1264 PI_PDATA_A_INIT_M_BSWAP_INIT),
1268 0, NULL) != DFX_K_SUCCESS) { 1265 0, NULL) != DFX_K_SUCCESS) {
1269 printk("%s: Could not set descriptor block address!\n", 1266 printk("%s: Could not set descriptor block address!\n",
1270 bp->dev->name); 1267 bp->dev->name);
1271 return DFX_K_FAILURE; 1268 return DFX_K_FAILURE;
1272 } 1269 }
1273 1270
1274 /* Set transmit flush timeout value */ 1271 /* Set transmit flush timeout value */
1275 1272
1276 bp->cmd_req_virt->cmd_type = PI_CMD_K_CHARS_SET; 1273 bp->cmd_req_virt->cmd_type = PI_CMD_K_CHARS_SET;
1277 bp->cmd_req_virt->char_set.item[0].item_code = PI_ITEM_K_FLUSH_TIME; 1274 bp->cmd_req_virt->char_set.item[0].item_code = PI_ITEM_K_FLUSH_TIME;
1278 bp->cmd_req_virt->char_set.item[0].value = 3; /* 3 seconds */ 1275 bp->cmd_req_virt->char_set.item[0].value = 3; /* 3 seconds */
1279 bp->cmd_req_virt->char_set.item[0].item_index = 0; 1276 bp->cmd_req_virt->char_set.item[0].item_index = 0;
1280 bp->cmd_req_virt->char_set.item[1].item_code = PI_ITEM_K_EOL; 1277 bp->cmd_req_virt->char_set.item[1].item_code = PI_ITEM_K_EOL;
1281 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS) 1278 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS)
1282 { 1279 {
1283 printk("%s: DMA command request failed!\n", bp->dev->name); 1280 printk("%s: DMA command request failed!\n", bp->dev->name);
1284 return(DFX_K_FAILURE); 1281 return(DFX_K_FAILURE);
1285 } 1282 }
1286 1283
1287 /* Set the initial values for eFDXEnable and MACTReq MIB objects */ 1284 /* Set the initial values for eFDXEnable and MACTReq MIB objects */
1288 1285
1289 bp->cmd_req_virt->cmd_type = PI_CMD_K_SNMP_SET; 1286 bp->cmd_req_virt->cmd_type = PI_CMD_K_SNMP_SET;
1290 bp->cmd_req_virt->snmp_set.item[0].item_code = PI_ITEM_K_FDX_ENB_DIS; 1287 bp->cmd_req_virt->snmp_set.item[0].item_code = PI_ITEM_K_FDX_ENB_DIS;
1291 bp->cmd_req_virt->snmp_set.item[0].value = bp->full_duplex_enb; 1288 bp->cmd_req_virt->snmp_set.item[0].value = bp->full_duplex_enb;
1292 bp->cmd_req_virt->snmp_set.item[0].item_index = 0; 1289 bp->cmd_req_virt->snmp_set.item[0].item_index = 0;
1293 bp->cmd_req_virt->snmp_set.item[1].item_code = PI_ITEM_K_MAC_T_REQ; 1290 bp->cmd_req_virt->snmp_set.item[1].item_code = PI_ITEM_K_MAC_T_REQ;
1294 bp->cmd_req_virt->snmp_set.item[1].value = bp->req_ttrt; 1291 bp->cmd_req_virt->snmp_set.item[1].value = bp->req_ttrt;
1295 bp->cmd_req_virt->snmp_set.item[1].item_index = 0; 1292 bp->cmd_req_virt->snmp_set.item[1].item_index = 0;
1296 bp->cmd_req_virt->snmp_set.item[2].item_code = PI_ITEM_K_EOL; 1293 bp->cmd_req_virt->snmp_set.item[2].item_code = PI_ITEM_K_EOL;
1297 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS) 1294 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS)
1298 { 1295 {
1299 printk("%s: DMA command request failed!\n", bp->dev->name); 1296 printk("%s: DMA command request failed!\n", bp->dev->name);
1300 return(DFX_K_FAILURE); 1297 return(DFX_K_FAILURE);
1301 } 1298 }
1302 1299
1303 /* Initialize adapter CAM */ 1300 /* Initialize adapter CAM */
1304 1301
1305 if (dfx_ctl_update_cam(bp) != DFX_K_SUCCESS) 1302 if (dfx_ctl_update_cam(bp) != DFX_K_SUCCESS)
1306 { 1303 {
1307 printk("%s: Adapter CAM update failed!\n", bp->dev->name); 1304 printk("%s: Adapter CAM update failed!\n", bp->dev->name);
1308 return(DFX_K_FAILURE); 1305 return(DFX_K_FAILURE);
1309 } 1306 }
1310 1307
1311 /* Initialize adapter filters */ 1308 /* Initialize adapter filters */
1312 1309
1313 if (dfx_ctl_update_filters(bp) != DFX_K_SUCCESS) 1310 if (dfx_ctl_update_filters(bp) != DFX_K_SUCCESS)
1314 { 1311 {
1315 printk("%s: Adapter filters update failed!\n", bp->dev->name); 1312 printk("%s: Adapter filters update failed!\n", bp->dev->name);
1316 return(DFX_K_FAILURE); 1313 return(DFX_K_FAILURE);
1317 } 1314 }
1318 1315
1319 /* 1316 /*
1320 * Remove any existing dynamic buffers (i.e. if the adapter is being 1317 * Remove any existing dynamic buffers (i.e. if the adapter is being
1321 * reinitialized) 1318 * reinitialized)
1322 */ 1319 */
1323 1320
1324 if (get_buffers) 1321 if (get_buffers)
1325 dfx_rcv_flush(bp); 1322 dfx_rcv_flush(bp);
1326 1323
1327 /* Initialize receive descriptor block and produce buffers */ 1324 /* Initialize receive descriptor block and produce buffers */
1328 1325
1329 if (dfx_rcv_init(bp, get_buffers)) 1326 if (dfx_rcv_init(bp, get_buffers))
1330 { 1327 {
1331 printk("%s: Receive buffer allocation failed\n", bp->dev->name); 1328 printk("%s: Receive buffer allocation failed\n", bp->dev->name);
1332 if (get_buffers) 1329 if (get_buffers)
1333 dfx_rcv_flush(bp); 1330 dfx_rcv_flush(bp);
1334 return(DFX_K_FAILURE); 1331 return(DFX_K_FAILURE);
1335 } 1332 }
1336 1333
1337 /* Issue START command and bring adapter to LINK_(UN)AVAILABLE state */ 1334 /* Issue START command and bring adapter to LINK_(UN)AVAILABLE state */
1338 1335
1339 bp->cmd_req_virt->cmd_type = PI_CMD_K_START; 1336 bp->cmd_req_virt->cmd_type = PI_CMD_K_START;
1340 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS) 1337 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS)
1341 { 1338 {
1342 printk("%s: Start command failed\n", bp->dev->name); 1339 printk("%s: Start command failed\n", bp->dev->name);
1343 if (get_buffers) 1340 if (get_buffers)
1344 dfx_rcv_flush(bp); 1341 dfx_rcv_flush(bp);
1345 return(DFX_K_FAILURE); 1342 return(DFX_K_FAILURE);
1346 } 1343 }
1347 1344
1348 /* Initialization succeeded, reenable PDQ interrupts */ 1345 /* Initialization succeeded, reenable PDQ interrupts */
1349 1346
1350 dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_ENABLE_DEF_INTS); 1347 dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_ENABLE_DEF_INTS);
1351 return(DFX_K_SUCCESS); 1348 return(DFX_K_SUCCESS);
1352 } 1349 }
1353 1350
1354 1351
1355 /* 1352 /*
1356 * ============ 1353 * ============
1357 * = dfx_open = 1354 * = dfx_open =
1358 * ============ 1355 * ============
1359 * 1356 *
1360 * Overview: 1357 * Overview:
1361 * Opens the adapter 1358 * Opens the adapter
1362 * 1359 *
1363 * Returns: 1360 * Returns:
1364 * Condition code 1361 * Condition code
1365 * 1362 *
1366 * Arguments: 1363 * Arguments:
1367 * dev - pointer to device information 1364 * dev - pointer to device information
1368 * 1365 *
1369 * Functional Description: 1366 * Functional Description:
1370 * This function brings the adapter to an operational state. 1367 * This function brings the adapter to an operational state.
1371 * 1368 *
1372 * Return Codes: 1369 * Return Codes:
1373 * 0 - Adapter was successfully opened 1370 * 0 - Adapter was successfully opened
1374 * -EAGAIN - Could not register IRQ or adapter initialization failed 1371 * -EAGAIN - Could not register IRQ or adapter initialization failed
1375 * 1372 *
1376 * Assumptions: 1373 * Assumptions:
1377 * This routine should only be called for a device that was 1374 * This routine should only be called for a device that was
1378 * initialized successfully. 1375 * initialized successfully.
1379 * 1376 *
1380 * Side Effects: 1377 * Side Effects:
1381 * Adapter should be in LINK_AVAILABLE or LINK_UNAVAILABLE state 1378 * Adapter should be in LINK_AVAILABLE or LINK_UNAVAILABLE state
1382 * if the open is successful. 1379 * if the open is successful.
1383 */ 1380 */
1384 1381
1385 static int dfx_open(struct net_device *dev) 1382 static int dfx_open(struct net_device *dev)
1386 { 1383 {
1387 DFX_board_t *bp = netdev_priv(dev); 1384 DFX_board_t *bp = netdev_priv(dev);
1388 int ret; 1385 int ret;
1389 1386
1390 DBG_printk("In dfx_open...\n"); 1387 DBG_printk("In dfx_open...\n");
1391 1388
1392 /* Register IRQ - support shared interrupts by passing device ptr */ 1389 /* Register IRQ - support shared interrupts by passing device ptr */
1393 1390
1394 ret = request_irq(dev->irq, dfx_interrupt, IRQF_SHARED, dev->name, 1391 ret = request_irq(dev->irq, dfx_interrupt, IRQF_SHARED, dev->name,
1395 dev); 1392 dev);
1396 if (ret) { 1393 if (ret) {
1397 printk(KERN_ERR "%s: Requested IRQ %d is busy\n", dev->name, dev->irq); 1394 printk(KERN_ERR "%s: Requested IRQ %d is busy\n", dev->name, dev->irq);
1398 return ret; 1395 return ret;
1399 } 1396 }
1400 1397
1401 /* 1398 /*
1402 * Set current address to factory MAC address 1399 * Set current address to factory MAC address
1403 * 1400 *
1404 * Note: We've already done this step in dfx_driver_init. 1401 * Note: We've already done this step in dfx_driver_init.
1405 * However, it's possible that a user has set a node 1402 * However, it's possible that a user has set a node
1406 * address override, then closed and reopened the 1403 * address override, then closed and reopened the
1407 * adapter. Unless we reset the device address field 1404 * adapter. Unless we reset the device address field
1408 * now, we'll continue to use the existing modified 1405 * now, we'll continue to use the existing modified
1409 * address. 1406 * address.
1410 */ 1407 */
1411 1408
1412 memcpy(dev->dev_addr, bp->factory_mac_addr, FDDI_K_ALEN); 1409 memcpy(dev->dev_addr, bp->factory_mac_addr, FDDI_K_ALEN);
1413 1410
1414 /* Clear local unicast/multicast address tables and counts */ 1411 /* Clear local unicast/multicast address tables and counts */
1415 1412
1416 memset(bp->uc_table, 0, sizeof(bp->uc_table)); 1413 memset(bp->uc_table, 0, sizeof(bp->uc_table));
1417 memset(bp->mc_table, 0, sizeof(bp->mc_table)); 1414 memset(bp->mc_table, 0, sizeof(bp->mc_table));
1418 bp->uc_count = 0; 1415 bp->uc_count = 0;
1419 bp->mc_count = 0; 1416 bp->mc_count = 0;
1420 1417
1421 /* Disable promiscuous filter settings */ 1418 /* Disable promiscuous filter settings */
1422 1419
1423 bp->ind_group_prom = PI_FSTATE_K_BLOCK; 1420 bp->ind_group_prom = PI_FSTATE_K_BLOCK;
1424 bp->group_prom = PI_FSTATE_K_BLOCK; 1421 bp->group_prom = PI_FSTATE_K_BLOCK;
1425 1422
1426 spin_lock_init(&bp->lock); 1423 spin_lock_init(&bp->lock);
1427 1424
1428 /* Reset and initialize adapter */ 1425 /* Reset and initialize adapter */
1429 1426
1430 bp->reset_type = PI_PDATA_A_RESET_M_SKIP_ST; /* skip self-test */ 1427 bp->reset_type = PI_PDATA_A_RESET_M_SKIP_ST; /* skip self-test */
1431 if (dfx_adap_init(bp, 1) != DFX_K_SUCCESS) 1428 if (dfx_adap_init(bp, 1) != DFX_K_SUCCESS)
1432 { 1429 {
1433 printk(KERN_ERR "%s: Adapter open failed!\n", dev->name); 1430 printk(KERN_ERR "%s: Adapter open failed!\n", dev->name);
1434 free_irq(dev->irq, dev); 1431 free_irq(dev->irq, dev);
1435 return -EAGAIN; 1432 return -EAGAIN;
1436 } 1433 }
1437 1434
1438 /* Set device structure info */ 1435 /* Set device structure info */
1439 netif_start_queue(dev); 1436 netif_start_queue(dev);
1440 return(0); 1437 return(0);
1441 } 1438 }
1442 1439
1443 1440
1444 /* 1441 /*
1445 * ============= 1442 * =============
1446 * = dfx_close = 1443 * = dfx_close =
1447 * ============= 1444 * =============
1448 * 1445 *
1449 * Overview: 1446 * Overview:
1450 * Closes the device/module. 1447 * Closes the device/module.
1451 * 1448 *
1452 * Returns: 1449 * Returns:
1453 * Condition code 1450 * Condition code
1454 * 1451 *
1455 * Arguments: 1452 * Arguments:
1456 * dev - pointer to device information 1453 * dev - pointer to device information
1457 * 1454 *
1458 * Functional Description: 1455 * Functional Description:
1459 * This routine closes the adapter and brings it to a safe state. 1456 * This routine closes the adapter and brings it to a safe state.
1460 * The interrupt service routine is deregistered with the OS. 1457 * The interrupt service routine is deregistered with the OS.
1461 * The adapter can be opened again with another call to dfx_open(). 1458 * The adapter can be opened again with another call to dfx_open().
1462 * 1459 *
1463 * Return Codes: 1460 * Return Codes:
1464 * Always return 0. 1461 * Always return 0.
1465 * 1462 *
1466 * Assumptions: 1463 * Assumptions:
1467 * No further requests for this adapter are made after this routine is 1464 * No further requests for this adapter are made after this routine is
1468 * called. dfx_open() can be called to reset and reinitialize the 1465 * called. dfx_open() can be called to reset and reinitialize the
1469 * adapter. 1466 * adapter.
1470 * 1467 *
1471 * Side Effects: 1468 * Side Effects:
1472 * Adapter should be in DMA_UNAVAILABLE state upon completion of this 1469 * Adapter should be in DMA_UNAVAILABLE state upon completion of this
1473 * routine. 1470 * routine.
1474 */ 1471 */
1475 1472
1476 static int dfx_close(struct net_device *dev) 1473 static int dfx_close(struct net_device *dev)
1477 { 1474 {
1478 DFX_board_t *bp = netdev_priv(dev); 1475 DFX_board_t *bp = netdev_priv(dev);
1479 1476
1480 DBG_printk("In dfx_close...\n"); 1477 DBG_printk("In dfx_close...\n");
1481 1478
1482 /* Disable PDQ interrupts first */ 1479 /* Disable PDQ interrupts first */
1483 1480
1484 dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS); 1481 dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS);
1485 1482
1486 /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */ 1483 /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */
1487 1484
1488 (void) dfx_hw_dma_uninit(bp, PI_PDATA_A_RESET_M_SKIP_ST); 1485 (void) dfx_hw_dma_uninit(bp, PI_PDATA_A_RESET_M_SKIP_ST);
1489 1486
1490 /* 1487 /*
1491 * Flush any pending transmit buffers 1488 * Flush any pending transmit buffers
1492 * 1489 *
1493 * Note: It's important that we flush the transmit buffers 1490 * Note: It's important that we flush the transmit buffers
1494 * BEFORE we clear our copy of the Type 2 register. 1491 * BEFORE we clear our copy of the Type 2 register.
1495 * Otherwise, we'll have no idea how many buffers 1492 * Otherwise, we'll have no idea how many buffers
1496 * we need to free. 1493 * we need to free.
1497 */ 1494 */
1498 1495
1499 dfx_xmt_flush(bp); 1496 dfx_xmt_flush(bp);
1500 1497
1501 /* 1498 /*
1502 * Clear Type 1 and Type 2 registers after adapter reset 1499 * Clear Type 1 and Type 2 registers after adapter reset
1503 * 1500 *
1504 * Note: Even though we're closing the adapter, it's 1501 * Note: Even though we're closing the adapter, it's
1505 * possible that an interrupt will occur after 1502 * possible that an interrupt will occur after
1506 * dfx_close is called. Without some assurance to 1503 * dfx_close is called. Without some assurance to
1507 * the contrary we want to make sure that we don't 1504 * the contrary we want to make sure that we don't
1508 * process receive and transmit LLC frames and update 1505 * process receive and transmit LLC frames and update
1509 * the Type 2 register with bad information. 1506 * the Type 2 register with bad information.
1510 */ 1507 */
1511 1508
1512 bp->cmd_req_reg.lword = 0; 1509 bp->cmd_req_reg.lword = 0;
1513 bp->cmd_rsp_reg.lword = 0; 1510 bp->cmd_rsp_reg.lword = 0;
1514 bp->rcv_xmt_reg.lword = 0; 1511 bp->rcv_xmt_reg.lword = 0;
1515 1512
1516 /* Clear consumer block for the same reason given above */ 1513 /* Clear consumer block for the same reason given above */
1517 1514
1518 memset(bp->cons_block_virt, 0, sizeof(PI_CONSUMER_BLOCK)); 1515 memset(bp->cons_block_virt, 0, sizeof(PI_CONSUMER_BLOCK));
1519 1516
1520 /* Release all dynamically allocate skb in the receive ring. */ 1517 /* Release all dynamically allocate skb in the receive ring. */
1521 1518
1522 dfx_rcv_flush(bp); 1519 dfx_rcv_flush(bp);
1523 1520
1524 /* Clear device structure flags */ 1521 /* Clear device structure flags */
1525 1522
1526 netif_stop_queue(dev); 1523 netif_stop_queue(dev);
1527 1524
1528 /* Deregister (free) IRQ */ 1525 /* Deregister (free) IRQ */
1529 1526
1530 free_irq(dev->irq, dev); 1527 free_irq(dev->irq, dev);
1531 1528
1532 return(0); 1529 return(0);
1533 } 1530 }
1534 1531
1535 1532
1536 /* 1533 /*
1537 * ====================== 1534 * ======================
1538 * = dfx_int_pr_halt_id = 1535 * = dfx_int_pr_halt_id =
1539 * ====================== 1536 * ======================
1540 * 1537 *
1541 * Overview: 1538 * Overview:
1542 * Displays halt id's in string form. 1539 * Displays halt id's in string form.
1543 * 1540 *
1544 * Returns: 1541 * Returns:
1545 * None 1542 * None
1546 * 1543 *
1547 * Arguments: 1544 * Arguments:
1548 * bp - pointer to board information 1545 * bp - pointer to board information
1549 * 1546 *
1550 * Functional Description: 1547 * Functional Description:
1551 * Determine current halt id and display appropriate string. 1548 * Determine current halt id and display appropriate string.
1552 * 1549 *
1553 * Return Codes: 1550 * Return Codes:
1554 * None 1551 * None
1555 * 1552 *
1556 * Assumptions: 1553 * Assumptions:
1557 * None 1554 * None
1558 * 1555 *
1559 * Side Effects: 1556 * Side Effects:
1560 * None 1557 * None
1561 */ 1558 */
1562 1559
1563 static void dfx_int_pr_halt_id(DFX_board_t *bp) 1560 static void dfx_int_pr_halt_id(DFX_board_t *bp)
1564 { 1561 {
1565 PI_UINT32 port_status; /* PDQ port status register value */ 1562 PI_UINT32 port_status; /* PDQ port status register value */
1566 PI_UINT32 halt_id; /* PDQ port status halt ID */ 1563 PI_UINT32 halt_id; /* PDQ port status halt ID */
1567 1564
1568 /* Read the latest port status */ 1565 /* Read the latest port status */
1569 1566
1570 dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_STATUS, &port_status); 1567 dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_STATUS, &port_status);
1571 1568
1572 /* Display halt state transition information */ 1569 /* Display halt state transition information */
1573 1570
1574 halt_id = (port_status & PI_PSTATUS_M_HALT_ID) >> PI_PSTATUS_V_HALT_ID; 1571 halt_id = (port_status & PI_PSTATUS_M_HALT_ID) >> PI_PSTATUS_V_HALT_ID;
1575 switch (halt_id) 1572 switch (halt_id)
1576 { 1573 {
1577 case PI_HALT_ID_K_SELFTEST_TIMEOUT: 1574 case PI_HALT_ID_K_SELFTEST_TIMEOUT:
1578 printk("%s: Halt ID: Selftest Timeout\n", bp->dev->name); 1575 printk("%s: Halt ID: Selftest Timeout\n", bp->dev->name);
1579 break; 1576 break;
1580 1577
1581 case PI_HALT_ID_K_PARITY_ERROR: 1578 case PI_HALT_ID_K_PARITY_ERROR:
1582 printk("%s: Halt ID: Host Bus Parity Error\n", bp->dev->name); 1579 printk("%s: Halt ID: Host Bus Parity Error\n", bp->dev->name);
1583 break; 1580 break;
1584 1581
1585 case PI_HALT_ID_K_HOST_DIR_HALT: 1582 case PI_HALT_ID_K_HOST_DIR_HALT:
1586 printk("%s: Halt ID: Host-Directed Halt\n", bp->dev->name); 1583 printk("%s: Halt ID: Host-Directed Halt\n", bp->dev->name);
1587 break; 1584 break;
1588 1585
1589 case PI_HALT_ID_K_SW_FAULT: 1586 case PI_HALT_ID_K_SW_FAULT:
1590 printk("%s: Halt ID: Adapter Software Fault\n", bp->dev->name); 1587 printk("%s: Halt ID: Adapter Software Fault\n", bp->dev->name);
1591 break; 1588 break;
1592 1589
1593 case PI_HALT_ID_K_HW_FAULT: 1590 case PI_HALT_ID_K_HW_FAULT:
1594 printk("%s: Halt ID: Adapter Hardware Fault\n", bp->dev->name); 1591 printk("%s: Halt ID: Adapter Hardware Fault\n", bp->dev->name);
1595 break; 1592 break;
1596 1593
1597 case PI_HALT_ID_K_PC_TRACE: 1594 case PI_HALT_ID_K_PC_TRACE:
1598 printk("%s: Halt ID: FDDI Network PC Trace Path Test\n", bp->dev->name); 1595 printk("%s: Halt ID: FDDI Network PC Trace Path Test\n", bp->dev->name);
1599 break; 1596 break;
1600 1597
1601 case PI_HALT_ID_K_DMA_ERROR: 1598 case PI_HALT_ID_K_DMA_ERROR:
1602 printk("%s: Halt ID: Adapter DMA Error\n", bp->dev->name); 1599 printk("%s: Halt ID: Adapter DMA Error\n", bp->dev->name);
1603 break; 1600 break;
1604 1601
1605 case PI_HALT_ID_K_IMAGE_CRC_ERROR: 1602 case PI_HALT_ID_K_IMAGE_CRC_ERROR:
1606 printk("%s: Halt ID: Firmware Image CRC Error\n", bp->dev->name); 1603 printk("%s: Halt ID: Firmware Image CRC Error\n", bp->dev->name);
1607 break; 1604 break;
1608 1605
1609 case PI_HALT_ID_K_BUS_EXCEPTION: 1606 case PI_HALT_ID_K_BUS_EXCEPTION:
1610 printk("%s: Halt ID: 68000 Bus Exception\n", bp->dev->name); 1607 printk("%s: Halt ID: 68000 Bus Exception\n", bp->dev->name);
1611 break; 1608 break;
1612 1609
1613 default: 1610 default:
1614 printk("%s: Halt ID: Unknown (code = %X)\n", bp->dev->name, halt_id); 1611 printk("%s: Halt ID: Unknown (code = %X)\n", bp->dev->name, halt_id);
1615 break; 1612 break;
1616 } 1613 }
1617 } 1614 }
1618 1615
1619 1616
1620 /* 1617 /*
1621 * ========================== 1618 * ==========================
1622 * = dfx_int_type_0_process = 1619 * = dfx_int_type_0_process =
1623 * ========================== 1620 * ==========================
1624 * 1621 *
1625 * Overview: 1622 * Overview:
1626 * Processes Type 0 interrupts. 1623 * Processes Type 0 interrupts.
1627 * 1624 *
1628 * Returns: 1625 * Returns:
1629 * None 1626 * None
1630 * 1627 *
1631 * Arguments: 1628 * Arguments:
1632 * bp - pointer to board information 1629 * bp - pointer to board information
1633 * 1630 *
1634 * Functional Description: 1631 * Functional Description:
1635 * Processes all enabled Type 0 interrupts. If the reason for the interrupt 1632 * Processes all enabled Type 0 interrupts. If the reason for the interrupt
1636 * is a serious fault on the adapter, then an error message is displayed 1633 * is a serious fault on the adapter, then an error message is displayed
1637 * and the adapter is reset. 1634 * and the adapter is reset.
1638 * 1635 *
1639 * One tricky potential timing window is the rapid succession of "link avail" 1636 * One tricky potential timing window is the rapid succession of "link avail"
1640 * "link unavail" state change interrupts. The acknowledgement of the Type 0 1637 * "link unavail" state change interrupts. The acknowledgement of the Type 0
1641 * interrupt must be done before reading the state from the Port Status 1638 * interrupt must be done before reading the state from the Port Status
1642 * register. This is true because a state change could occur after reading 1639 * register. This is true because a state change could occur after reading
1643 * the data, but before acknowledging the interrupt. If this state change 1640 * the data, but before acknowledging the interrupt. If this state change
1644 * does happen, it would be lost because the driver is using the old state, 1641 * does happen, it would be lost because the driver is using the old state,
1645 * and it will never know about the new state because it subsequently 1642 * and it will never know about the new state because it subsequently
1646 * acknowledges the state change interrupt. 1643 * acknowledges the state change interrupt.
1647 * 1644 *
1648 * INCORRECT CORRECT 1645 * INCORRECT CORRECT
1649 * read type 0 int reasons read type 0 int reasons 1646 * read type 0 int reasons read type 0 int reasons
1650 * read adapter state ack type 0 interrupts 1647 * read adapter state ack type 0 interrupts
1651 * ack type 0 interrupts read adapter state 1648 * ack type 0 interrupts read adapter state
1652 * ... process interrupt ... ... process interrupt ... 1649 * ... process interrupt ... ... process interrupt ...
1653 * 1650 *
1654 * Return Codes: 1651 * Return Codes:
1655 * None 1652 * None
1656 * 1653 *
1657 * Assumptions: 1654 * Assumptions:
1658 * None 1655 * None
1659 * 1656 *
1660 * Side Effects: 1657 * Side Effects:
1661 * An adapter reset may occur if the adapter has any Type 0 error interrupts 1658 * An adapter reset may occur if the adapter has any Type 0 error interrupts
1662 * or if the port status indicates that the adapter is halted. The driver 1659 * or if the port status indicates that the adapter is halted. The driver
1663 * is responsible for reinitializing the adapter with the current CAM 1660 * is responsible for reinitializing the adapter with the current CAM
1664 * contents and adapter filter settings. 1661 * contents and adapter filter settings.
1665 */ 1662 */
1666 1663
1667 static void dfx_int_type_0_process(DFX_board_t *bp) 1664 static void dfx_int_type_0_process(DFX_board_t *bp)
1668 1665
1669 { 1666 {
1670 PI_UINT32 type_0_status; /* Host Interrupt Type 0 register */ 1667 PI_UINT32 type_0_status; /* Host Interrupt Type 0 register */
1671 PI_UINT32 state; /* current adap state (from port status) */ 1668 PI_UINT32 state; /* current adap state (from port status) */
1672 1669
1673 /* 1670 /*
1674 * Read host interrupt Type 0 register to determine which Type 0 1671 * Read host interrupt Type 0 register to determine which Type 0
1675 * interrupts are pending. Immediately write it back out to clear 1672 * interrupts are pending. Immediately write it back out to clear
1676 * those interrupts. 1673 * those interrupts.
1677 */ 1674 */
1678 1675
1679 dfx_port_read_long(bp, PI_PDQ_K_REG_TYPE_0_STATUS, &type_0_status); 1676 dfx_port_read_long(bp, PI_PDQ_K_REG_TYPE_0_STATUS, &type_0_status);
1680 dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_0_STATUS, type_0_status); 1677 dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_0_STATUS, type_0_status);
1681 1678
1682 /* Check for Type 0 error interrupts */ 1679 /* Check for Type 0 error interrupts */
1683 1680
1684 if (type_0_status & (PI_TYPE_0_STAT_M_NXM | 1681 if (type_0_status & (PI_TYPE_0_STAT_M_NXM |
1685 PI_TYPE_0_STAT_M_PM_PAR_ERR | 1682 PI_TYPE_0_STAT_M_PM_PAR_ERR |
1686 PI_TYPE_0_STAT_M_BUS_PAR_ERR)) 1683 PI_TYPE_0_STAT_M_BUS_PAR_ERR))
1687 { 1684 {
1688 /* Check for Non-Existent Memory error */ 1685 /* Check for Non-Existent Memory error */
1689 1686
1690 if (type_0_status & PI_TYPE_0_STAT_M_NXM) 1687 if (type_0_status & PI_TYPE_0_STAT_M_NXM)
1691 printk("%s: Non-Existent Memory Access Error\n", bp->dev->name); 1688 printk("%s: Non-Existent Memory Access Error\n", bp->dev->name);
1692 1689
1693 /* Check for Packet Memory Parity error */ 1690 /* Check for Packet Memory Parity error */
1694 1691
1695 if (type_0_status & PI_TYPE_0_STAT_M_PM_PAR_ERR) 1692 if (type_0_status & PI_TYPE_0_STAT_M_PM_PAR_ERR)
1696 printk("%s: Packet Memory Parity Error\n", bp->dev->name); 1693 printk("%s: Packet Memory Parity Error\n", bp->dev->name);
1697 1694
1698 /* Check for Host Bus Parity error */ 1695 /* Check for Host Bus Parity error */
1699 1696
1700 if (type_0_status & PI_TYPE_0_STAT_M_BUS_PAR_ERR) 1697 if (type_0_status & PI_TYPE_0_STAT_M_BUS_PAR_ERR)
1701 printk("%s: Host Bus Parity Error\n", bp->dev->name); 1698 printk("%s: Host Bus Parity Error\n", bp->dev->name);
1702 1699
1703 /* Reset adapter and bring it back on-line */ 1700 /* Reset adapter and bring it back on-line */
1704 1701
1705 bp->link_available = PI_K_FALSE; /* link is no longer available */ 1702 bp->link_available = PI_K_FALSE; /* link is no longer available */
1706 bp->reset_type = 0; /* rerun on-board diagnostics */ 1703 bp->reset_type = 0; /* rerun on-board diagnostics */
1707 printk("%s: Resetting adapter...\n", bp->dev->name); 1704 printk("%s: Resetting adapter...\n", bp->dev->name);
1708 if (dfx_adap_init(bp, 0) != DFX_K_SUCCESS) 1705 if (dfx_adap_init(bp, 0) != DFX_K_SUCCESS)
1709 { 1706 {
1710 printk("%s: Adapter reset failed! Disabling adapter interrupts.\n", bp->dev->name); 1707 printk("%s: Adapter reset failed! Disabling adapter interrupts.\n", bp->dev->name);
1711 dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS); 1708 dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS);
1712 return; 1709 return;
1713 } 1710 }
1714 printk("%s: Adapter reset successful!\n", bp->dev->name); 1711 printk("%s: Adapter reset successful!\n", bp->dev->name);
1715 return; 1712 return;
1716 } 1713 }
1717 1714
1718 /* Check for transmit flush interrupt */ 1715 /* Check for transmit flush interrupt */
1719 1716
1720 if (type_0_status & PI_TYPE_0_STAT_M_XMT_FLUSH) 1717 if (type_0_status & PI_TYPE_0_STAT_M_XMT_FLUSH)
1721 { 1718 {
1722 /* Flush any pending xmt's and acknowledge the flush interrupt */ 1719 /* Flush any pending xmt's and acknowledge the flush interrupt */
1723 1720
1724 bp->link_available = PI_K_FALSE; /* link is no longer available */ 1721 bp->link_available = PI_K_FALSE; /* link is no longer available */
1725 dfx_xmt_flush(bp); /* flush any outstanding packets */ 1722 dfx_xmt_flush(bp); /* flush any outstanding packets */
1726 (void) dfx_hw_port_ctrl_req(bp, 1723 (void) dfx_hw_port_ctrl_req(bp,
1727 PI_PCTRL_M_XMT_DATA_FLUSH_DONE, 1724 PI_PCTRL_M_XMT_DATA_FLUSH_DONE,
1728 0, 1725 0,
1729 0, 1726 0,
1730 NULL); 1727 NULL);
1731 } 1728 }
1732 1729
1733 /* Check for adapter state change */ 1730 /* Check for adapter state change */
1734 1731
1735 if (type_0_status & PI_TYPE_0_STAT_M_STATE_CHANGE) 1732 if (type_0_status & PI_TYPE_0_STAT_M_STATE_CHANGE)
1736 { 1733 {
1737 /* Get latest adapter state */ 1734 /* Get latest adapter state */
1738 1735
1739 state = dfx_hw_adap_state_rd(bp); /* get adapter state */ 1736 state = dfx_hw_adap_state_rd(bp); /* get adapter state */
1740 if (state == PI_STATE_K_HALTED) 1737 if (state == PI_STATE_K_HALTED)
1741 { 1738 {
1742 /* 1739 /*
1743 * Adapter has transitioned to HALTED state, try to reset 1740 * Adapter has transitioned to HALTED state, try to reset
1744 * adapter to bring it back on-line. If reset fails, 1741 * adapter to bring it back on-line. If reset fails,
1745 * leave the adapter in the broken state. 1742 * leave the adapter in the broken state.
1746 */ 1743 */
1747 1744
1748 printk("%s: Controller has transitioned to HALTED state!\n", bp->dev->name); 1745 printk("%s: Controller has transitioned to HALTED state!\n", bp->dev->name);
1749 dfx_int_pr_halt_id(bp); /* display halt id as string */ 1746 dfx_int_pr_halt_id(bp); /* display halt id as string */
1750 1747
1751 /* Reset adapter and bring it back on-line */ 1748 /* Reset adapter and bring it back on-line */
1752 1749
1753 bp->link_available = PI_K_FALSE; /* link is no longer available */ 1750 bp->link_available = PI_K_FALSE; /* link is no longer available */
1754 bp->reset_type = 0; /* rerun on-board diagnostics */ 1751 bp->reset_type = 0; /* rerun on-board diagnostics */
1755 printk("%s: Resetting adapter...\n", bp->dev->name); 1752 printk("%s: Resetting adapter...\n", bp->dev->name);
1756 if (dfx_adap_init(bp, 0) != DFX_K_SUCCESS) 1753 if (dfx_adap_init(bp, 0) != DFX_K_SUCCESS)
1757 { 1754 {
1758 printk("%s: Adapter reset failed! Disabling adapter interrupts.\n", bp->dev->name); 1755 printk("%s: Adapter reset failed! Disabling adapter interrupts.\n", bp->dev->name);
1759 dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS); 1756 dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS);
1760 return; 1757 return;
1761 } 1758 }
1762 printk("%s: Adapter reset successful!\n", bp->dev->name); 1759 printk("%s: Adapter reset successful!\n", bp->dev->name);
1763 } 1760 }
1764 else if (state == PI_STATE_K_LINK_AVAIL) 1761 else if (state == PI_STATE_K_LINK_AVAIL)
1765 { 1762 {
1766 bp->link_available = PI_K_TRUE; /* set link available flag */ 1763 bp->link_available = PI_K_TRUE; /* set link available flag */
1767 } 1764 }
1768 } 1765 }
1769 } 1766 }
1770 1767
1771 1768
1772 /* 1769 /*
1773 * ================== 1770 * ==================
1774 * = dfx_int_common = 1771 * = dfx_int_common =
1775 * ================== 1772 * ==================
1776 * 1773 *
1777 * Overview: 1774 * Overview:
1778 * Interrupt service routine (ISR) 1775 * Interrupt service routine (ISR)
1779 * 1776 *
1780 * Returns: 1777 * Returns:
1781 * None 1778 * None
1782 * 1779 *
1783 * Arguments: 1780 * Arguments:
1784 * bp - pointer to board information 1781 * bp - pointer to board information
1785 * 1782 *
1786 * Functional Description: 1783 * Functional Description:
1787 * This is the ISR which processes incoming adapter interrupts. 1784 * This is the ISR which processes incoming adapter interrupts.
1788 * 1785 *
1789 * Return Codes: 1786 * Return Codes:
1790 * None 1787 * None
1791 * 1788 *
1792 * Assumptions: 1789 * Assumptions:
1793 * This routine assumes PDQ interrupts have not been disabled. 1790 * This routine assumes PDQ interrupts have not been disabled.
1794 * When interrupts are disabled at the PDQ, the Port Status register 1791 * When interrupts are disabled at the PDQ, the Port Status register
1795 * is automatically cleared. This routine uses the Port Status 1792 * is automatically cleared. This routine uses the Port Status
1796 * register value to determine whether a Type 0 interrupt occurred, 1793 * register value to determine whether a Type 0 interrupt occurred,
1797 * so it's important that adapter interrupts are not normally 1794 * so it's important that adapter interrupts are not normally
1798 * enabled/disabled at the PDQ. 1795 * enabled/disabled at the PDQ.
1799 * 1796 *
1800 * It's vital that this routine is NOT reentered for the 1797 * It's vital that this routine is NOT reentered for the
1801 * same board and that the OS is not in another section of 1798 * same board and that the OS is not in another section of
1802 * code (eg. dfx_xmt_queue_pkt) for the same board on a 1799 * code (eg. dfx_xmt_queue_pkt) for the same board on a
1803 * different thread. 1800 * different thread.
1804 * 1801 *
1805 * Side Effects: 1802 * Side Effects:
1806 * Pending interrupts are serviced. Depending on the type of 1803 * Pending interrupts are serviced. Depending on the type of
1807 * interrupt, acknowledging and clearing the interrupt at the 1804 * interrupt, acknowledging and clearing the interrupt at the
1808 * PDQ involves writing a register to clear the interrupt bit 1805 * PDQ involves writing a register to clear the interrupt bit
1809 * or updating completion indices. 1806 * or updating completion indices.
1810 */ 1807 */
1811 1808
1812 static void dfx_int_common(struct net_device *dev) 1809 static void dfx_int_common(struct net_device *dev)
1813 { 1810 {
1814 DFX_board_t *bp = netdev_priv(dev); 1811 DFX_board_t *bp = netdev_priv(dev);
1815 PI_UINT32 port_status; /* Port Status register */ 1812 PI_UINT32 port_status; /* Port Status register */
1816 1813
1817 /* Process xmt interrupts - frequent case, so always call this routine */ 1814 /* Process xmt interrupts - frequent case, so always call this routine */
1818 1815
1819 if(dfx_xmt_done(bp)) /* free consumed xmt packets */ 1816 if(dfx_xmt_done(bp)) /* free consumed xmt packets */
1820 netif_wake_queue(dev); 1817 netif_wake_queue(dev);
1821 1818
1822 /* Process rcv interrupts - frequent case, so always call this routine */ 1819 /* Process rcv interrupts - frequent case, so always call this routine */
1823 1820
1824 dfx_rcv_queue_process(bp); /* service received LLC frames */ 1821 dfx_rcv_queue_process(bp); /* service received LLC frames */
1825 1822
1826 /* 1823 /*
1827 * Transmit and receive producer and completion indices are updated on the 1824 * Transmit and receive producer and completion indices are updated on the
1828 * adapter by writing to the Type 2 Producer register. Since the frequent 1825 * adapter by writing to the Type 2 Producer register. Since the frequent
1829 * case is that we'll be processing either LLC transmit or receive buffers, 1826 * case is that we'll be processing either LLC transmit or receive buffers,
1830 * we'll optimize I/O writes by doing a single register write here. 1827 * we'll optimize I/O writes by doing a single register write here.
1831 */ 1828 */
1832 1829
1833 dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_2_PROD, bp->rcv_xmt_reg.lword); 1830 dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_2_PROD, bp->rcv_xmt_reg.lword);
1834 1831
1835 /* Read PDQ Port Status register to find out which interrupts need processing */ 1832 /* Read PDQ Port Status register to find out which interrupts need processing */
1836 1833
1837 dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_STATUS, &port_status); 1834 dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_STATUS, &port_status);
1838 1835
1839 /* Process Type 0 interrupts (if any) - infrequent, so only call when needed */ 1836 /* Process Type 0 interrupts (if any) - infrequent, so only call when needed */
1840 1837
1841 if (port_status & PI_PSTATUS_M_TYPE_0_PENDING) 1838 if (port_status & PI_PSTATUS_M_TYPE_0_PENDING)
1842 dfx_int_type_0_process(bp); /* process Type 0 interrupts */ 1839 dfx_int_type_0_process(bp); /* process Type 0 interrupts */
1843 } 1840 }
1844 1841
1845 1842
1846 /* 1843 /*
1847 * ================= 1844 * =================
1848 * = dfx_interrupt = 1845 * = dfx_interrupt =
1849 * ================= 1846 * =================
1850 * 1847 *
1851 * Overview: 1848 * Overview:
1852 * Interrupt processing routine 1849 * Interrupt processing routine
1853 * 1850 *
1854 * Returns: 1851 * Returns:
1855 * Whether a valid interrupt was seen. 1852 * Whether a valid interrupt was seen.
1856 * 1853 *
1857 * Arguments: 1854 * Arguments:
1858 * irq - interrupt vector 1855 * irq - interrupt vector
1859 * dev_id - pointer to device information 1856 * dev_id - pointer to device information
1860 * 1857 *
1861 * Functional Description: 1858 * Functional Description:
1862 * This routine calls the interrupt processing routine for this adapter. It 1859 * This routine calls the interrupt processing routine for this adapter. It
1863 * disables and reenables adapter interrupts, as appropriate. We can support 1860 * disables and reenables adapter interrupts, as appropriate. We can support
1864 * shared interrupts since the incoming dev_id pointer provides our device 1861 * shared interrupts since the incoming dev_id pointer provides our device
1865 * structure context. 1862 * structure context.
1866 * 1863 *
1867 * Return Codes: 1864 * Return Codes:
1868 * IRQ_HANDLED - an IRQ was handled. 1865 * IRQ_HANDLED - an IRQ was handled.
1869 * IRQ_NONE - no IRQ was handled. 1866 * IRQ_NONE - no IRQ was handled.
1870 * 1867 *
1871 * Assumptions: 1868 * Assumptions:
1872 * The interrupt acknowledgement at the hardware level (eg. ACKing the PIC 1869 * The interrupt acknowledgement at the hardware level (eg. ACKing the PIC
1873 * on Intel-based systems) is done by the operating system outside this 1870 * on Intel-based systems) is done by the operating system outside this
1874 * routine. 1871 * routine.
1875 * 1872 *
1876 * System interrupts are enabled through this call. 1873 * System interrupts are enabled through this call.
1877 * 1874 *
1878 * Side Effects: 1875 * Side Effects:
1879 * Interrupts are disabled, then reenabled at the adapter. 1876 * Interrupts are disabled, then reenabled at the adapter.
1880 */ 1877 */
1881 1878
1882 static irqreturn_t dfx_interrupt(int irq, void *dev_id) 1879 static irqreturn_t dfx_interrupt(int irq, void *dev_id)
1883 { 1880 {
1884 struct net_device *dev = dev_id; 1881 struct net_device *dev = dev_id;
1885 DFX_board_t *bp = netdev_priv(dev); 1882 DFX_board_t *bp = netdev_priv(dev);
1886 struct device *bdev = bp->bus_dev; 1883 struct device *bdev = bp->bus_dev;
1887 int dfx_bus_pci = DFX_BUS_PCI(bdev); 1884 int dfx_bus_pci = DFX_BUS_PCI(bdev);
1888 int dfx_bus_eisa = DFX_BUS_EISA(bdev); 1885 int dfx_bus_eisa = DFX_BUS_EISA(bdev);
1889 int dfx_bus_tc = DFX_BUS_TC(bdev); 1886 int dfx_bus_tc = DFX_BUS_TC(bdev);
1890 1887
1891 /* Service adapter interrupts */ 1888 /* Service adapter interrupts */
1892 1889
1893 if (dfx_bus_pci) { 1890 if (dfx_bus_pci) {
1894 u32 status; 1891 u32 status;
1895 1892
1896 dfx_port_read_long(bp, PFI_K_REG_STATUS, &status); 1893 dfx_port_read_long(bp, PFI_K_REG_STATUS, &status);
1897 if (!(status & PFI_STATUS_M_PDQ_INT)) 1894 if (!(status & PFI_STATUS_M_PDQ_INT))
1898 return IRQ_NONE; 1895 return IRQ_NONE;
1899 1896
1900 spin_lock(&bp->lock); 1897 spin_lock(&bp->lock);
1901 1898
1902 /* Disable PDQ-PFI interrupts at PFI */ 1899 /* Disable PDQ-PFI interrupts at PFI */
1903 dfx_port_write_long(bp, PFI_K_REG_MODE_CTRL, 1900 dfx_port_write_long(bp, PFI_K_REG_MODE_CTRL,
1904 PFI_MODE_M_DMA_ENB); 1901 PFI_MODE_M_DMA_ENB);
1905 1902
1906 /* Call interrupt service routine for this adapter */ 1903 /* Call interrupt service routine for this adapter */
1907 dfx_int_common(dev); 1904 dfx_int_common(dev);
1908 1905
1909 /* Clear PDQ interrupt status bit and reenable interrupts */ 1906 /* Clear PDQ interrupt status bit and reenable interrupts */
1910 dfx_port_write_long(bp, PFI_K_REG_STATUS, 1907 dfx_port_write_long(bp, PFI_K_REG_STATUS,
1911 PFI_STATUS_M_PDQ_INT); 1908 PFI_STATUS_M_PDQ_INT);
1912 dfx_port_write_long(bp, PFI_K_REG_MODE_CTRL, 1909 dfx_port_write_long(bp, PFI_K_REG_MODE_CTRL,
1913 (PFI_MODE_M_PDQ_INT_ENB | 1910 (PFI_MODE_M_PDQ_INT_ENB |
1914 PFI_MODE_M_DMA_ENB)); 1911 PFI_MODE_M_DMA_ENB));
1915 1912
1916 spin_unlock(&bp->lock); 1913 spin_unlock(&bp->lock);
1917 } 1914 }
1918 if (dfx_bus_eisa) { 1915 if (dfx_bus_eisa) {
1919 unsigned long base_addr = to_eisa_device(bdev)->base_addr; 1916 unsigned long base_addr = to_eisa_device(bdev)->base_addr;
1920 u8 status; 1917 u8 status;
1921 1918
1922 status = inb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0); 1919 status = inb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0);
1923 if (!(status & PI_CONFIG_STAT_0_M_PEND)) 1920 if (!(status & PI_CONFIG_STAT_0_M_PEND))
1924 return IRQ_NONE; 1921 return IRQ_NONE;
1925 1922
1926 spin_lock(&bp->lock); 1923 spin_lock(&bp->lock);
1927 1924
1928 /* Disable interrupts at the ESIC */ 1925 /* Disable interrupts at the ESIC */
1929 status &= ~PI_CONFIG_STAT_0_M_INT_ENB; 1926 status &= ~PI_CONFIG_STAT_0_M_INT_ENB;
1930 outb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0, status); 1927 outb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0, status);
1931 1928
1932 /* Call interrupt service routine for this adapter */ 1929 /* Call interrupt service routine for this adapter */
1933 dfx_int_common(dev); 1930 dfx_int_common(dev);
1934 1931
1935 /* Reenable interrupts at the ESIC */ 1932 /* Reenable interrupts at the ESIC */
1936 status = inb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0); 1933 status = inb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0);
1937 status |= PI_CONFIG_STAT_0_M_INT_ENB; 1934 status |= PI_CONFIG_STAT_0_M_INT_ENB;
1938 outb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0, status); 1935 outb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0, status);
1939 1936
1940 spin_unlock(&bp->lock); 1937 spin_unlock(&bp->lock);
1941 } 1938 }
1942 if (dfx_bus_tc) { 1939 if (dfx_bus_tc) {
1943 u32 status; 1940 u32 status;
1944 1941
1945 dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_STATUS, &status); 1942 dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_STATUS, &status);
1946 if (!(status & (PI_PSTATUS_M_RCV_DATA_PENDING | 1943 if (!(status & (PI_PSTATUS_M_RCV_DATA_PENDING |
1947 PI_PSTATUS_M_XMT_DATA_PENDING | 1944 PI_PSTATUS_M_XMT_DATA_PENDING |
1948 PI_PSTATUS_M_SMT_HOST_PENDING | 1945 PI_PSTATUS_M_SMT_HOST_PENDING |
1949 PI_PSTATUS_M_UNSOL_PENDING | 1946 PI_PSTATUS_M_UNSOL_PENDING |
1950 PI_PSTATUS_M_CMD_RSP_PENDING | 1947 PI_PSTATUS_M_CMD_RSP_PENDING |
1951 PI_PSTATUS_M_CMD_REQ_PENDING | 1948 PI_PSTATUS_M_CMD_REQ_PENDING |
1952 PI_PSTATUS_M_TYPE_0_PENDING))) 1949 PI_PSTATUS_M_TYPE_0_PENDING)))
1953 return IRQ_NONE; 1950 return IRQ_NONE;
1954 1951
1955 spin_lock(&bp->lock); 1952 spin_lock(&bp->lock);
1956 1953
1957 /* Call interrupt service routine for this adapter */ 1954 /* Call interrupt service routine for this adapter */
1958 dfx_int_common(dev); 1955 dfx_int_common(dev);
1959 1956
1960 spin_unlock(&bp->lock); 1957 spin_unlock(&bp->lock);
1961 } 1958 }
1962 1959
1963 return IRQ_HANDLED; 1960 return IRQ_HANDLED;
1964 } 1961 }
1965 1962
1966 1963
1967 /* 1964 /*
1968 * ===================== 1965 * =====================
1969 * = dfx_ctl_get_stats = 1966 * = dfx_ctl_get_stats =
1970 * ===================== 1967 * =====================
1971 * 1968 *
1972 * Overview: 1969 * Overview:
1973 * Get statistics for FDDI adapter 1970 * Get statistics for FDDI adapter
1974 * 1971 *
1975 * Returns: 1972 * Returns:
1976 * Pointer to FDDI statistics structure 1973 * Pointer to FDDI statistics structure
1977 * 1974 *
1978 * Arguments: 1975 * Arguments:
1979 * dev - pointer to device information 1976 * dev - pointer to device information
1980 * 1977 *
1981 * Functional Description: 1978 * Functional Description:
1982 * Gets current MIB objects from adapter, then 1979 * Gets current MIB objects from adapter, then
1983 * returns FDDI statistics structure as defined 1980 * returns FDDI statistics structure as defined
1984 * in if_fddi.h. 1981 * in if_fddi.h.
1985 * 1982 *
1986 * Note: Since the FDDI statistics structure is 1983 * Note: Since the FDDI statistics structure is
1987 * still new and the device structure doesn't 1984 * still new and the device structure doesn't
1988 * have an FDDI-specific get statistics handler, 1985 * have an FDDI-specific get statistics handler,
1989 * we'll return the FDDI statistics structure as 1986 * we'll return the FDDI statistics structure as
1990 * a pointer to an Ethernet statistics structure. 1987 * a pointer to an Ethernet statistics structure.
1991 * That way, at least the first part of the statistics 1988 * That way, at least the first part of the statistics
1992 * structure can be decoded properly, and it allows 1989 * structure can be decoded properly, and it allows
1993 * "smart" applications to perform a second cast to 1990 * "smart" applications to perform a second cast to
1994 * decode the FDDI-specific statistics. 1991 * decode the FDDI-specific statistics.
1995 * 1992 *
1996 * We'll have to pay attention to this routine as the 1993 * We'll have to pay attention to this routine as the
1997 * device structure becomes more mature and LAN media 1994 * device structure becomes more mature and LAN media
1998 * independent. 1995 * independent.
1999 * 1996 *
2000 * Return Codes: 1997 * Return Codes:
2001 * None 1998 * None
2002 * 1999 *
2003 * Assumptions: 2000 * Assumptions:
2004 * None 2001 * None
2005 * 2002 *
2006 * Side Effects: 2003 * Side Effects:
2007 * None 2004 * None
2008 */ 2005 */
2009 2006
2010 static struct net_device_stats *dfx_ctl_get_stats(struct net_device *dev) 2007 static struct net_device_stats *dfx_ctl_get_stats(struct net_device *dev)
2011 { 2008 {
2012 DFX_board_t *bp = netdev_priv(dev); 2009 DFX_board_t *bp = netdev_priv(dev);
2013 2010
2014 /* Fill the bp->stats structure with driver-maintained counters */ 2011 /* Fill the bp->stats structure with driver-maintained counters */
2015 2012
2016 bp->stats.gen.rx_packets = bp->rcv_total_frames; 2013 bp->stats.gen.rx_packets = bp->rcv_total_frames;
2017 bp->stats.gen.tx_packets = bp->xmt_total_frames; 2014 bp->stats.gen.tx_packets = bp->xmt_total_frames;
2018 bp->stats.gen.rx_bytes = bp->rcv_total_bytes; 2015 bp->stats.gen.rx_bytes = bp->rcv_total_bytes;
2019 bp->stats.gen.tx_bytes = bp->xmt_total_bytes; 2016 bp->stats.gen.tx_bytes = bp->xmt_total_bytes;
2020 bp->stats.gen.rx_errors = bp->rcv_crc_errors + 2017 bp->stats.gen.rx_errors = bp->rcv_crc_errors +
2021 bp->rcv_frame_status_errors + 2018 bp->rcv_frame_status_errors +
2022 bp->rcv_length_errors; 2019 bp->rcv_length_errors;
2023 bp->stats.gen.tx_errors = bp->xmt_length_errors; 2020 bp->stats.gen.tx_errors = bp->xmt_length_errors;
2024 bp->stats.gen.rx_dropped = bp->rcv_discards; 2021 bp->stats.gen.rx_dropped = bp->rcv_discards;
2025 bp->stats.gen.tx_dropped = bp->xmt_discards; 2022 bp->stats.gen.tx_dropped = bp->xmt_discards;
2026 bp->stats.gen.multicast = bp->rcv_multicast_frames; 2023 bp->stats.gen.multicast = bp->rcv_multicast_frames;
2027 bp->stats.gen.collisions = 0; /* always zero (0) for FDDI */ 2024 bp->stats.gen.collisions = 0; /* always zero (0) for FDDI */
2028 2025
2029 /* Get FDDI SMT MIB objects */ 2026 /* Get FDDI SMT MIB objects */
2030 2027
2031 bp->cmd_req_virt->cmd_type = PI_CMD_K_SMT_MIB_GET; 2028 bp->cmd_req_virt->cmd_type = PI_CMD_K_SMT_MIB_GET;
2032 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS) 2029 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS)
2033 return((struct net_device_stats *) &bp->stats); 2030 return((struct net_device_stats *) &bp->stats);
2034 2031
2035 /* Fill the bp->stats structure with the SMT MIB object values */ 2032 /* Fill the bp->stats structure with the SMT MIB object values */
2036 2033
2037 memcpy(bp->stats.smt_station_id, &bp->cmd_rsp_virt->smt_mib_get.smt_station_id, sizeof(bp->cmd_rsp_virt->smt_mib_get.smt_station_id)); 2034 memcpy(bp->stats.smt_station_id, &bp->cmd_rsp_virt->smt_mib_get.smt_station_id, sizeof(bp->cmd_rsp_virt->smt_mib_get.smt_station_id));
2038 bp->stats.smt_op_version_id = bp->cmd_rsp_virt->smt_mib_get.smt_op_version_id; 2035 bp->stats.smt_op_version_id = bp->cmd_rsp_virt->smt_mib_get.smt_op_version_id;
2039 bp->stats.smt_hi_version_id = bp->cmd_rsp_virt->smt_mib_get.smt_hi_version_id; 2036 bp->stats.smt_hi_version_id = bp->cmd_rsp_virt->smt_mib_get.smt_hi_version_id;
2040 bp->stats.smt_lo_version_id = bp->cmd_rsp_virt->smt_mib_get.smt_lo_version_id; 2037 bp->stats.smt_lo_version_id = bp->cmd_rsp_virt->smt_mib_get.smt_lo_version_id;
2041 memcpy(bp->stats.smt_user_data, &bp->cmd_rsp_virt->smt_mib_get.smt_user_data, sizeof(bp->cmd_rsp_virt->smt_mib_get.smt_user_data)); 2038 memcpy(bp->stats.smt_user_data, &bp->cmd_rsp_virt->smt_mib_get.smt_user_data, sizeof(bp->cmd_rsp_virt->smt_mib_get.smt_user_data));
2042 bp->stats.smt_mib_version_id = bp->cmd_rsp_virt->smt_mib_get.smt_mib_version_id; 2039 bp->stats.smt_mib_version_id = bp->cmd_rsp_virt->smt_mib_get.smt_mib_version_id;
2043 bp->stats.smt_mac_cts = bp->cmd_rsp_virt->smt_mib_get.smt_mac_ct; 2040 bp->stats.smt_mac_cts = bp->cmd_rsp_virt->smt_mib_get.smt_mac_ct;
2044 bp->stats.smt_non_master_cts = bp->cmd_rsp_virt->smt_mib_get.smt_non_master_ct; 2041 bp->stats.smt_non_master_cts = bp->cmd_rsp_virt->smt_mib_get.smt_non_master_ct;
2045 bp->stats.smt_master_cts = bp->cmd_rsp_virt->smt_mib_get.smt_master_ct; 2042 bp->stats.smt_master_cts = bp->cmd_rsp_virt->smt_mib_get.smt_master_ct;
2046 bp->stats.smt_available_paths = bp->cmd_rsp_virt->smt_mib_get.smt_available_paths; 2043 bp->stats.smt_available_paths = bp->cmd_rsp_virt->smt_mib_get.smt_available_paths;
2047 bp->stats.smt_config_capabilities = bp->cmd_rsp_virt->smt_mib_get.smt_config_capabilities; 2044 bp->stats.smt_config_capabilities = bp->cmd_rsp_virt->smt_mib_get.smt_config_capabilities;
2048 bp->stats.smt_config_policy = bp->cmd_rsp_virt->smt_mib_get.smt_config_policy; 2045 bp->stats.smt_config_policy = bp->cmd_rsp_virt->smt_mib_get.smt_config_policy;
2049 bp->stats.smt_connection_policy = bp->cmd_rsp_virt->smt_mib_get.smt_connection_policy; 2046 bp->stats.smt_connection_policy = bp->cmd_rsp_virt->smt_mib_get.smt_connection_policy;
2050 bp->stats.smt_t_notify = bp->cmd_rsp_virt->smt_mib_get.smt_t_notify; 2047 bp->stats.smt_t_notify = bp->cmd_rsp_virt->smt_mib_get.smt_t_notify;
2051 bp->stats.smt_stat_rpt_policy = bp->cmd_rsp_virt->smt_mib_get.smt_stat_rpt_policy; 2048 bp->stats.smt_stat_rpt_policy = bp->cmd_rsp_virt->smt_mib_get.smt_stat_rpt_policy;
2052 bp->stats.smt_trace_max_expiration = bp->cmd_rsp_virt->smt_mib_get.smt_trace_max_expiration; 2049 bp->stats.smt_trace_max_expiration = bp->cmd_rsp_virt->smt_mib_get.smt_trace_max_expiration;
2053 bp->stats.smt_bypass_present = bp->cmd_rsp_virt->smt_mib_get.smt_bypass_present; 2050 bp->stats.smt_bypass_present = bp->cmd_rsp_virt->smt_mib_get.smt_bypass_present;
2054 bp->stats.smt_ecm_state = bp->cmd_rsp_virt->smt_mib_get.smt_ecm_state; 2051 bp->stats.smt_ecm_state = bp->cmd_rsp_virt->smt_mib_get.smt_ecm_state;
2055 bp->stats.smt_cf_state = bp->cmd_rsp_virt->smt_mib_get.smt_cf_state; 2052 bp->stats.smt_cf_state = bp->cmd_rsp_virt->smt_mib_get.smt_cf_state;
2056 bp->stats.smt_remote_disconnect_flag = bp->cmd_rsp_virt->smt_mib_get.smt_remote_disconnect_flag; 2053 bp->stats.smt_remote_disconnect_flag = bp->cmd_rsp_virt->smt_mib_get.smt_remote_disconnect_flag;
2057 bp->stats.smt_station_status = bp->cmd_rsp_virt->smt_mib_get.smt_station_status; 2054 bp->stats.smt_station_status = bp->cmd_rsp_virt->smt_mib_get.smt_station_status;
2058 bp->stats.smt_peer_wrap_flag = bp->cmd_rsp_virt->smt_mib_get.smt_peer_wrap_flag; 2055 bp->stats.smt_peer_wrap_flag = bp->cmd_rsp_virt->smt_mib_get.smt_peer_wrap_flag;
2059 bp->stats.smt_time_stamp = bp->cmd_rsp_virt->smt_mib_get.smt_msg_time_stamp.ls; 2056 bp->stats.smt_time_stamp = bp->cmd_rsp_virt->smt_mib_get.smt_msg_time_stamp.ls;
2060 bp->stats.smt_transition_time_stamp = bp->cmd_rsp_virt->smt_mib_get.smt_transition_time_stamp.ls; 2057 bp->stats.smt_transition_time_stamp = bp->cmd_rsp_virt->smt_mib_get.smt_transition_time_stamp.ls;
2061 bp->stats.mac_frame_status_functions = bp->cmd_rsp_virt->smt_mib_get.mac_frame_status_functions; 2058 bp->stats.mac_frame_status_functions = bp->cmd_rsp_virt->smt_mib_get.mac_frame_status_functions;
2062 bp->stats.mac_t_max_capability = bp->cmd_rsp_virt->smt_mib_get.mac_t_max_capability; 2059 bp->stats.mac_t_max_capability = bp->cmd_rsp_virt->smt_mib_get.mac_t_max_capability;
2063 bp->stats.mac_tvx_capability = bp->cmd_rsp_virt->smt_mib_get.mac_tvx_capability; 2060 bp->stats.mac_tvx_capability = bp->cmd_rsp_virt->smt_mib_get.mac_tvx_capability;
2064 bp->stats.mac_available_paths = bp->cmd_rsp_virt->smt_mib_get.mac_available_paths; 2061 bp->stats.mac_available_paths = bp->cmd_rsp_virt->smt_mib_get.mac_available_paths;
2065 bp->stats.mac_current_path = bp->cmd_rsp_virt->smt_mib_get.mac_current_path; 2062 bp->stats.mac_current_path = bp->cmd_rsp_virt->smt_mib_get.mac_current_path;
2066 memcpy(bp->stats.mac_upstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_upstream_nbr, FDDI_K_ALEN); 2063 memcpy(bp->stats.mac_upstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_upstream_nbr, FDDI_K_ALEN);
2067 memcpy(bp->stats.mac_downstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_downstream_nbr, FDDI_K_ALEN); 2064 memcpy(bp->stats.mac_downstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_downstream_nbr, FDDI_K_ALEN);
2068 memcpy(bp->stats.mac_old_upstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_old_upstream_nbr, FDDI_K_ALEN); 2065 memcpy(bp->stats.mac_old_upstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_old_upstream_nbr, FDDI_K_ALEN);
2069 memcpy(bp->stats.mac_old_downstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_old_downstream_nbr, FDDI_K_ALEN); 2066 memcpy(bp->stats.mac_old_downstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_old_downstream_nbr, FDDI_K_ALEN);
2070 bp->stats.mac_dup_address_test = bp->cmd_rsp_virt->smt_mib_get.mac_dup_address_test; 2067 bp->stats.mac_dup_address_test = bp->cmd_rsp_virt->smt_mib_get.mac_dup_address_test;
2071 bp->stats.mac_requested_paths = bp->cmd_rsp_virt->smt_mib_get.mac_requested_paths; 2068 bp->stats.mac_requested_paths = bp->cmd_rsp_virt->smt_mib_get.mac_requested_paths;
2072 bp->stats.mac_downstream_port_type = bp->cmd_rsp_virt->smt_mib_get.mac_downstream_port_type; 2069 bp->stats.mac_downstream_port_type = bp->cmd_rsp_virt->smt_mib_get.mac_downstream_port_type;
2073 memcpy(bp->stats.mac_smt_address, &bp->cmd_rsp_virt->smt_mib_get.mac_smt_address, FDDI_K_ALEN); 2070 memcpy(bp->stats.mac_smt_address, &bp->cmd_rsp_virt->smt_mib_get.mac_smt_address, FDDI_K_ALEN);
2074 bp->stats.mac_t_req = bp->cmd_rsp_virt->smt_mib_get.mac_t_req; 2071 bp->stats.mac_t_req = bp->cmd_rsp_virt->smt_mib_get.mac_t_req;
2075 bp->stats.mac_t_neg = bp->cmd_rsp_virt->smt_mib_get.mac_t_neg; 2072 bp->stats.mac_t_neg = bp->cmd_rsp_virt->smt_mib_get.mac_t_neg;
2076 bp->stats.mac_t_max = bp->cmd_rsp_virt->smt_mib_get.mac_t_max; 2073 bp->stats.mac_t_max = bp->cmd_rsp_virt->smt_mib_get.mac_t_max;
2077 bp->stats.mac_tvx_value = bp->cmd_rsp_virt->smt_mib_get.mac_tvx_value; 2074 bp->stats.mac_tvx_value = bp->cmd_rsp_virt->smt_mib_get.mac_tvx_value;
2078 bp->stats.mac_frame_error_threshold = bp->cmd_rsp_virt->smt_mib_get.mac_frame_error_threshold; 2075 bp->stats.mac_frame_error_threshold = bp->cmd_rsp_virt->smt_mib_get.mac_frame_error_threshold;
2079 bp->stats.mac_frame_error_ratio = bp->cmd_rsp_virt->smt_mib_get.mac_frame_error_ratio; 2076 bp->stats.mac_frame_error_ratio = bp->cmd_rsp_virt->smt_mib_get.mac_frame_error_ratio;
2080 bp->stats.mac_rmt_state = bp->cmd_rsp_virt->smt_mib_get.mac_rmt_state; 2077 bp->stats.mac_rmt_state = bp->cmd_rsp_virt->smt_mib_get.mac_rmt_state;
2081 bp->stats.mac_da_flag = bp->cmd_rsp_virt->smt_mib_get.mac_da_flag; 2078 bp->stats.mac_da_flag = bp->cmd_rsp_virt->smt_mib_get.mac_da_flag;
2082 bp->stats.mac_una_da_flag = bp->cmd_rsp_virt->smt_mib_get.mac_unda_flag; 2079 bp->stats.mac_una_da_flag = bp->cmd_rsp_virt->smt_mib_get.mac_unda_flag;
2083 bp->stats.mac_frame_error_flag = bp->cmd_rsp_virt->smt_mib_get.mac_frame_error_flag; 2080 bp->stats.mac_frame_error_flag = bp->cmd_rsp_virt->smt_mib_get.mac_frame_error_flag;
2084 bp->stats.mac_ma_unitdata_available = bp->cmd_rsp_virt->smt_mib_get.mac_ma_unitdata_available; 2081 bp->stats.mac_ma_unitdata_available = bp->cmd_rsp_virt->smt_mib_get.mac_ma_unitdata_available;
2085 bp->stats.mac_hardware_present = bp->cmd_rsp_virt->smt_mib_get.mac_hardware_present; 2082 bp->stats.mac_hardware_present = bp->cmd_rsp_virt->smt_mib_get.mac_hardware_present;
2086 bp->stats.mac_ma_unitdata_enable = bp->cmd_rsp_virt->smt_mib_get.mac_ma_unitdata_enable; 2083 bp->stats.mac_ma_unitdata_enable = bp->cmd_rsp_virt->smt_mib_get.mac_ma_unitdata_enable;
2087 bp->stats.path_tvx_lower_bound = bp->cmd_rsp_virt->smt_mib_get.path_tvx_lower_bound; 2084 bp->stats.path_tvx_lower_bound = bp->cmd_rsp_virt->smt_mib_get.path_tvx_lower_bound;
2088 bp->stats.path_t_max_lower_bound = bp->cmd_rsp_virt->smt_mib_get.path_t_max_lower_bound; 2085 bp->stats.path_t_max_lower_bound = bp->cmd_rsp_virt->smt_mib_get.path_t_max_lower_bound;
2089 bp->stats.path_max_t_req = bp->cmd_rsp_virt->smt_mib_get.path_max_t_req; 2086 bp->stats.path_max_t_req = bp->cmd_rsp_virt->smt_mib_get.path_max_t_req;
2090 memcpy(bp->stats.path_configuration, &bp->cmd_rsp_virt->smt_mib_get.path_configuration, sizeof(bp->cmd_rsp_virt->smt_mib_get.path_configuration)); 2087 memcpy(bp->stats.path_configuration, &bp->cmd_rsp_virt->smt_mib_get.path_configuration, sizeof(bp->cmd_rsp_virt->smt_mib_get.path_configuration));
2091 bp->stats.port_my_type[0] = bp->cmd_rsp_virt->smt_mib_get.port_my_type[0]; 2088 bp->stats.port_my_type[0] = bp->cmd_rsp_virt->smt_mib_get.port_my_type[0];
2092 bp->stats.port_my_type[1] = bp->cmd_rsp_virt->smt_mib_get.port_my_type[1]; 2089 bp->stats.port_my_type[1] = bp->cmd_rsp_virt->smt_mib_get.port_my_type[1];
2093 bp->stats.port_neighbor_type[0] = bp->cmd_rsp_virt->smt_mib_get.port_neighbor_type[0]; 2090 bp->stats.port_neighbor_type[0] = bp->cmd_rsp_virt->smt_mib_get.port_neighbor_type[0];
2094 bp->stats.port_neighbor_type[1] = bp->cmd_rsp_virt->smt_mib_get.port_neighbor_type[1]; 2091 bp->stats.port_neighbor_type[1] = bp->cmd_rsp_virt->smt_mib_get.port_neighbor_type[1];
2095 bp->stats.port_connection_policies[0] = bp->cmd_rsp_virt->smt_mib_get.port_connection_policies[0]; 2092 bp->stats.port_connection_policies[0] = bp->cmd_rsp_virt->smt_mib_get.port_connection_policies[0];
2096 bp->stats.port_connection_policies[1] = bp->cmd_rsp_virt->smt_mib_get.port_connection_policies[1]; 2093 bp->stats.port_connection_policies[1] = bp->cmd_rsp_virt->smt_mib_get.port_connection_policies[1];
2097 bp->stats.port_mac_indicated[0] = bp->cmd_rsp_virt->smt_mib_get.port_mac_indicated[0]; 2094 bp->stats.port_mac_indicated[0] = bp->cmd_rsp_virt->smt_mib_get.port_mac_indicated[0];
2098 bp->stats.port_mac_indicated[1] = bp->cmd_rsp_virt->smt_mib_get.port_mac_indicated[1]; 2095 bp->stats.port_mac_indicated[1] = bp->cmd_rsp_virt->smt_mib_get.port_mac_indicated[1];
2099 bp->stats.port_current_path[0] = bp->cmd_rsp_virt->smt_mib_get.port_current_path[0]; 2096 bp->stats.port_current_path[0] = bp->cmd_rsp_virt->smt_mib_get.port_current_path[0];
2100 bp->stats.port_current_path[1] = bp->cmd_rsp_virt->smt_mib_get.port_current_path[1]; 2097 bp->stats.port_current_path[1] = bp->cmd_rsp_virt->smt_mib_get.port_current_path[1];
2101 memcpy(&bp->stats.port_requested_paths[0*3], &bp->cmd_rsp_virt->smt_mib_get.port_requested_paths[0], 3); 2098 memcpy(&bp->stats.port_requested_paths[0*3], &bp->cmd_rsp_virt->smt_mib_get.port_requested_paths[0], 3);
2102 memcpy(&bp->stats.port_requested_paths[1*3], &bp->cmd_rsp_virt->smt_mib_get.port_requested_paths[1], 3); 2099 memcpy(&bp->stats.port_requested_paths[1*3], &bp->cmd_rsp_virt->smt_mib_get.port_requested_paths[1], 3);
2103 bp->stats.port_mac_placement[0] = bp->cmd_rsp_virt->smt_mib_get.port_mac_placement[0]; 2100 bp->stats.port_mac_placement[0] = bp->cmd_rsp_virt->smt_mib_get.port_mac_placement[0];
2104 bp->stats.port_mac_placement[1] = bp->cmd_rsp_virt->smt_mib_get.port_mac_placement[1]; 2101 bp->stats.port_mac_placement[1] = bp->cmd_rsp_virt->smt_mib_get.port_mac_placement[1];
2105 bp->stats.port_available_paths[0] = bp->cmd_rsp_virt->smt_mib_get.port_available_paths[0]; 2102 bp->stats.port_available_paths[0] = bp->cmd_rsp_virt->smt_mib_get.port_available_paths[0];
2106 bp->stats.port_available_paths[1] = bp->cmd_rsp_virt->smt_mib_get.port_available_paths[1]; 2103 bp->stats.port_available_paths[1] = bp->cmd_rsp_virt->smt_mib_get.port_available_paths[1];
2107 bp->stats.port_pmd_class[0] = bp->cmd_rsp_virt->smt_mib_get.port_pmd_class[0]; 2104 bp->stats.port_pmd_class[0] = bp->cmd_rsp_virt->smt_mib_get.port_pmd_class[0];
2108 bp->stats.port_pmd_class[1] = bp->cmd_rsp_virt->smt_mib_get.port_pmd_class[1]; 2105 bp->stats.port_pmd_class[1] = bp->cmd_rsp_virt->smt_mib_get.port_pmd_class[1];
2109 bp->stats.port_connection_capabilities[0] = bp->cmd_rsp_virt->smt_mib_get.port_connection_capabilities[0]; 2106 bp->stats.port_connection_capabilities[0] = bp->cmd_rsp_virt->smt_mib_get.port_connection_capabilities[0];
2110 bp->stats.port_connection_capabilities[1] = bp->cmd_rsp_virt->smt_mib_get.port_connection_capabilities[1]; 2107 bp->stats.port_connection_capabilities[1] = bp->cmd_rsp_virt->smt_mib_get.port_connection_capabilities[1];
2111 bp->stats.port_bs_flag[0] = bp->cmd_rsp_virt->smt_mib_get.port_bs_flag[0]; 2108 bp->stats.port_bs_flag[0] = bp->cmd_rsp_virt->smt_mib_get.port_bs_flag[0];
2112 bp->stats.port_bs_flag[1] = bp->cmd_rsp_virt->smt_mib_get.port_bs_flag[1]; 2109 bp->stats.port_bs_flag[1] = bp->cmd_rsp_virt->smt_mib_get.port_bs_flag[1];
2113 bp->stats.port_ler_estimate[0] = bp->cmd_rsp_virt->smt_mib_get.port_ler_estimate[0]; 2110 bp->stats.port_ler_estimate[0] = bp->cmd_rsp_virt->smt_mib_get.port_ler_estimate[0];
2114 bp->stats.port_ler_estimate[1] = bp->cmd_rsp_virt->smt_mib_get.port_ler_estimate[1]; 2111 bp->stats.port_ler_estimate[1] = bp->cmd_rsp_virt->smt_mib_get.port_ler_estimate[1];
2115 bp->stats.port_ler_cutoff[0] = bp->cmd_rsp_virt->smt_mib_get.port_ler_cutoff[0]; 2112 bp->stats.port_ler_cutoff[0] = bp->cmd_rsp_virt->smt_mib_get.port_ler_cutoff[0];
2116 bp->stats.port_ler_cutoff[1] = bp->cmd_rsp_virt->smt_mib_get.port_ler_cutoff[1]; 2113 bp->stats.port_ler_cutoff[1] = bp->cmd_rsp_virt->smt_mib_get.port_ler_cutoff[1];
2117 bp->stats.port_ler_alarm[0] = bp->cmd_rsp_virt->smt_mib_get.port_ler_alarm[0]; 2114 bp->stats.port_ler_alarm[0] = bp->cmd_rsp_virt->smt_mib_get.port_ler_alarm[0];
2118 bp->stats.port_ler_alarm[1] = bp->cmd_rsp_virt->smt_mib_get.port_ler_alarm[1]; 2115 bp->stats.port_ler_alarm[1] = bp->cmd_rsp_virt->smt_mib_get.port_ler_alarm[1];
2119 bp->stats.port_connect_state[0] = bp->cmd_rsp_virt->smt_mib_get.port_connect_state[0]; 2116 bp->stats.port_connect_state[0] = bp->cmd_rsp_virt->smt_mib_get.port_connect_state[0];
2120 bp->stats.port_connect_state[1] = bp->cmd_rsp_virt->smt_mib_get.port_connect_state[1]; 2117 bp->stats.port_connect_state[1] = bp->cmd_rsp_virt->smt_mib_get.port_connect_state[1];
2121 bp->stats.port_pcm_state[0] = bp->cmd_rsp_virt->smt_mib_get.port_pcm_state[0]; 2118 bp->stats.port_pcm_state[0] = bp->cmd_rsp_virt->smt_mib_get.port_pcm_state[0];
2122 bp->stats.port_pcm_state[1] = bp->cmd_rsp_virt->smt_mib_get.port_pcm_state[1]; 2119 bp->stats.port_pcm_state[1] = bp->cmd_rsp_virt->smt_mib_get.port_pcm_state[1];
2123 bp->stats.port_pc_withhold[0] = bp->cmd_rsp_virt->smt_mib_get.port_pc_withhold[0]; 2120 bp->stats.port_pc_withhold[0] = bp->cmd_rsp_virt->smt_mib_get.port_pc_withhold[0];
2124 bp->stats.port_pc_withhold[1] = bp->cmd_rsp_virt->smt_mib_get.port_pc_withhold[1]; 2121 bp->stats.port_pc_withhold[1] = bp->cmd_rsp_virt->smt_mib_get.port_pc_withhold[1];
2125 bp->stats.port_ler_flag[0] = bp->cmd_rsp_virt->smt_mib_get.port_ler_flag[0]; 2122 bp->stats.port_ler_flag[0] = bp->cmd_rsp_virt->smt_mib_get.port_ler_flag[0];
2126 bp->stats.port_ler_flag[1] = bp->cmd_rsp_virt->smt_mib_get.port_ler_flag[1]; 2123 bp->stats.port_ler_flag[1] = bp->cmd_rsp_virt->smt_mib_get.port_ler_flag[1];
2127 bp->stats.port_hardware_present[0] = bp->cmd_rsp_virt->smt_mib_get.port_hardware_present[0]; 2124 bp->stats.port_hardware_present[0] = bp->cmd_rsp_virt->smt_mib_get.port_hardware_present[0];
2128 bp->stats.port_hardware_present[1] = bp->cmd_rsp_virt->smt_mib_get.port_hardware_present[1]; 2125 bp->stats.port_hardware_present[1] = bp->cmd_rsp_virt->smt_mib_get.port_hardware_present[1];
2129 2126
2130 /* Get FDDI counters */ 2127 /* Get FDDI counters */
2131 2128
2132 bp->cmd_req_virt->cmd_type = PI_CMD_K_CNTRS_GET; 2129 bp->cmd_req_virt->cmd_type = PI_CMD_K_CNTRS_GET;
2133 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS) 2130 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS)
2134 return((struct net_device_stats *) &bp->stats); 2131 return((struct net_device_stats *) &bp->stats);
2135 2132
2136 /* Fill the bp->stats structure with the FDDI counter values */ 2133 /* Fill the bp->stats structure with the FDDI counter values */
2137 2134
2138 bp->stats.mac_frame_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.frame_cnt.ls; 2135 bp->stats.mac_frame_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.frame_cnt.ls;
2139 bp->stats.mac_copied_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.copied_cnt.ls; 2136 bp->stats.mac_copied_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.copied_cnt.ls;
2140 bp->stats.mac_transmit_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.transmit_cnt.ls; 2137 bp->stats.mac_transmit_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.transmit_cnt.ls;
2141 bp->stats.mac_error_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.error_cnt.ls; 2138 bp->stats.mac_error_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.error_cnt.ls;
2142 bp->stats.mac_lost_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.lost_cnt.ls; 2139 bp->stats.mac_lost_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.lost_cnt.ls;
2143 bp->stats.port_lct_fail_cts[0] = bp->cmd_rsp_virt->cntrs_get.cntrs.lct_rejects[0].ls; 2140 bp->stats.port_lct_fail_cts[0] = bp->cmd_rsp_virt->cntrs_get.cntrs.lct_rejects[0].ls;
2144 bp->stats.port_lct_fail_cts[1] = bp->cmd_rsp_virt->cntrs_get.cntrs.lct_rejects[1].ls; 2141 bp->stats.port_lct_fail_cts[1] = bp->cmd_rsp_virt->cntrs_get.cntrs.lct_rejects[1].ls;
2145 bp->stats.port_lem_reject_cts[0] = bp->cmd_rsp_virt->cntrs_get.cntrs.lem_rejects[0].ls; 2142 bp->stats.port_lem_reject_cts[0] = bp->cmd_rsp_virt->cntrs_get.cntrs.lem_rejects[0].ls;
2146 bp->stats.port_lem_reject_cts[1] = bp->cmd_rsp_virt->cntrs_get.cntrs.lem_rejects[1].ls; 2143 bp->stats.port_lem_reject_cts[1] = bp->cmd_rsp_virt->cntrs_get.cntrs.lem_rejects[1].ls;
2147 bp->stats.port_lem_cts[0] = bp->cmd_rsp_virt->cntrs_get.cntrs.link_errors[0].ls; 2144 bp->stats.port_lem_cts[0] = bp->cmd_rsp_virt->cntrs_get.cntrs.link_errors[0].ls;
2148 bp->stats.port_lem_cts[1] = bp->cmd_rsp_virt->cntrs_get.cntrs.link_errors[1].ls; 2145 bp->stats.port_lem_cts[1] = bp->cmd_rsp_virt->cntrs_get.cntrs.link_errors[1].ls;
2149 2146
2150 return((struct net_device_stats *) &bp->stats); 2147 return((struct net_device_stats *) &bp->stats);
2151 } 2148 }
2152 2149
2153 2150
2154 /* 2151 /*
2155 * ============================== 2152 * ==============================
2156 * = dfx_ctl_set_multicast_list = 2153 * = dfx_ctl_set_multicast_list =
2157 * ============================== 2154 * ==============================
2158 * 2155 *
2159 * Overview: 2156 * Overview:
2160 * Enable/Disable LLC frame promiscuous mode reception 2157 * Enable/Disable LLC frame promiscuous mode reception
2161 * on the adapter and/or update multicast address table. 2158 * on the adapter and/or update multicast address table.
2162 * 2159 *
2163 * Returns: 2160 * Returns:
2164 * None 2161 * None
2165 * 2162 *
2166 * Arguments: 2163 * Arguments:
2167 * dev - pointer to device information 2164 * dev - pointer to device information
2168 * 2165 *
2169 * Functional Description: 2166 * Functional Description:
2170 * This routine follows a fairly simple algorithm for setting the 2167 * This routine follows a fairly simple algorithm for setting the
2171 * adapter filters and CAM: 2168 * adapter filters and CAM:
2172 * 2169 *
2173 * if IFF_PROMISC flag is set 2170 * if IFF_PROMISC flag is set
2174 * enable LLC individual/group promiscuous mode 2171 * enable LLC individual/group promiscuous mode
2175 * else 2172 * else
2176 * disable LLC individual/group promiscuous mode 2173 * disable LLC individual/group promiscuous mode
2177 * if number of incoming multicast addresses > 2174 * if number of incoming multicast addresses >
2178 * (CAM max size - number of unicast addresses in CAM) 2175 * (CAM max size - number of unicast addresses in CAM)
2179 * enable LLC group promiscuous mode 2176 * enable LLC group promiscuous mode
2180 * set driver-maintained multicast address count to zero 2177 * set driver-maintained multicast address count to zero
2181 * else 2178 * else
2182 * disable LLC group promiscuous mode 2179 * disable LLC group promiscuous mode
2183 * set driver-maintained multicast address count to incoming count 2180 * set driver-maintained multicast address count to incoming count
2184 * update adapter CAM 2181 * update adapter CAM
2185 * update adapter filters 2182 * update adapter filters
2186 * 2183 *
2187 * Return Codes: 2184 * Return Codes:
2188 * None 2185 * None
2189 * 2186 *
2190 * Assumptions: 2187 * Assumptions:
2191 * Multicast addresses are presented in canonical (LSB) format. 2188 * Multicast addresses are presented in canonical (LSB) format.
2192 * 2189 *
2193 * Side Effects: 2190 * Side Effects:
2194 * On-board adapter CAM and filters are updated. 2191 * On-board adapter CAM and filters are updated.
2195 */ 2192 */
2196 2193
2197 static void dfx_ctl_set_multicast_list(struct net_device *dev) 2194 static void dfx_ctl_set_multicast_list(struct net_device *dev)
2198 { 2195 {
2199 DFX_board_t *bp = netdev_priv(dev); 2196 DFX_board_t *bp = netdev_priv(dev);
2200 int i; /* used as index in for loop */ 2197 int i; /* used as index in for loop */
2201 struct dev_mc_list *dmi; /* ptr to multicast addr entry */ 2198 struct dev_mc_list *dmi; /* ptr to multicast addr entry */
2202 2199
2203 /* Enable LLC frame promiscuous mode, if necessary */ 2200 /* Enable LLC frame promiscuous mode, if necessary */
2204 2201
2205 if (dev->flags & IFF_PROMISC) 2202 if (dev->flags & IFF_PROMISC)
2206 bp->ind_group_prom = PI_FSTATE_K_PASS; /* Enable LLC ind/group prom mode */ 2203 bp->ind_group_prom = PI_FSTATE_K_PASS; /* Enable LLC ind/group prom mode */
2207 2204
2208 /* Else, update multicast address table */ 2205 /* Else, update multicast address table */
2209 2206
2210 else 2207 else
2211 { 2208 {
2212 bp->ind_group_prom = PI_FSTATE_K_BLOCK; /* Disable LLC ind/group prom mode */ 2209 bp->ind_group_prom = PI_FSTATE_K_BLOCK; /* Disable LLC ind/group prom mode */
2213 /* 2210 /*
2214 * Check whether incoming multicast address count exceeds table size 2211 * Check whether incoming multicast address count exceeds table size
2215 * 2212 *
2216 * Note: The adapters utilize an on-board 64 entry CAM for 2213 * Note: The adapters utilize an on-board 64 entry CAM for
2217 * supporting perfect filtering of multicast packets 2214 * supporting perfect filtering of multicast packets
2218 * and bridge functions when adding unicast addresses. 2215 * and bridge functions when adding unicast addresses.
2219 * There is no hash function available. To support 2216 * There is no hash function available. To support
2220 * additional multicast addresses, the all multicast 2217 * additional multicast addresses, the all multicast
2221 * filter (LLC group promiscuous mode) must be enabled. 2218 * filter (LLC group promiscuous mode) must be enabled.
2222 * 2219 *
2223 * The firmware reserves two CAM entries for SMT-related 2220 * The firmware reserves two CAM entries for SMT-related
2224 * multicast addresses, which leaves 62 entries available. 2221 * multicast addresses, which leaves 62 entries available.
2225 * The following code ensures that we're not being asked 2222 * The following code ensures that we're not being asked
2226 * to add more than 62 addresses to the CAM. If we are, 2223 * to add more than 62 addresses to the CAM. If we are,
2227 * the driver will enable the all multicast filter. 2224 * the driver will enable the all multicast filter.
2228 * Should the number of multicast addresses drop below 2225 * Should the number of multicast addresses drop below
2229 * the high water mark, the filter will be disabled and 2226 * the high water mark, the filter will be disabled and
2230 * perfect filtering will be used. 2227 * perfect filtering will be used.
2231 */ 2228 */
2232 2229
2233 if (dev->mc_count > (PI_CMD_ADDR_FILTER_K_SIZE - bp->uc_count)) 2230 if (dev->mc_count > (PI_CMD_ADDR_FILTER_K_SIZE - bp->uc_count))
2234 { 2231 {
2235 bp->group_prom = PI_FSTATE_K_PASS; /* Enable LLC group prom mode */ 2232 bp->group_prom = PI_FSTATE_K_PASS; /* Enable LLC group prom mode */
2236 bp->mc_count = 0; /* Don't add mc addrs to CAM */ 2233 bp->mc_count = 0; /* Don't add mc addrs to CAM */
2237 } 2234 }
2238 else 2235 else
2239 { 2236 {
2240 bp->group_prom = PI_FSTATE_K_BLOCK; /* Disable LLC group prom mode */ 2237 bp->group_prom = PI_FSTATE_K_BLOCK; /* Disable LLC group prom mode */
2241 bp->mc_count = dev->mc_count; /* Add mc addrs to CAM */ 2238 bp->mc_count = dev->mc_count; /* Add mc addrs to CAM */
2242 } 2239 }
2243 2240
2244 /* Copy addresses to multicast address table, then update adapter CAM */ 2241 /* Copy addresses to multicast address table, then update adapter CAM */
2245 2242
2246 dmi = dev->mc_list; /* point to first multicast addr */ 2243 dmi = dev->mc_list; /* point to first multicast addr */
2247 for (i=0; i < bp->mc_count; i++) 2244 for (i=0; i < bp->mc_count; i++)
2248 { 2245 {
2249 memcpy(&bp->mc_table[i*FDDI_K_ALEN], dmi->dmi_addr, FDDI_K_ALEN); 2246 memcpy(&bp->mc_table[i*FDDI_K_ALEN], dmi->dmi_addr, FDDI_K_ALEN);
2250 dmi = dmi->next; /* point to next multicast addr */ 2247 dmi = dmi->next; /* point to next multicast addr */
2251 } 2248 }
2252 if (dfx_ctl_update_cam(bp) != DFX_K_SUCCESS) 2249 if (dfx_ctl_update_cam(bp) != DFX_K_SUCCESS)
2253 { 2250 {
2254 DBG_printk("%s: Could not update multicast address table!\n", dev->name); 2251 DBG_printk("%s: Could not update multicast address table!\n", dev->name);
2255 } 2252 }
2256 else 2253 else
2257 { 2254 {
2258 DBG_printk("%s: Multicast address table updated! Added %d addresses.\n", dev->name, bp->mc_count); 2255 DBG_printk("%s: Multicast address table updated! Added %d addresses.\n", dev->name, bp->mc_count);
2259 } 2256 }
2260 } 2257 }
2261 2258
2262 /* Update adapter filters */ 2259 /* Update adapter filters */
2263 2260
2264 if (dfx_ctl_update_filters(bp) != DFX_K_SUCCESS) 2261 if (dfx_ctl_update_filters(bp) != DFX_K_SUCCESS)
2265 { 2262 {
2266 DBG_printk("%s: Could not update adapter filters!\n", dev->name); 2263 DBG_printk("%s: Could not update adapter filters!\n", dev->name);
2267 } 2264 }
2268 else 2265 else
2269 { 2266 {
2270 DBG_printk("%s: Adapter filters updated!\n", dev->name); 2267 DBG_printk("%s: Adapter filters updated!\n", dev->name);
2271 } 2268 }
2272 } 2269 }
2273 2270
2274 2271
2275 /* 2272 /*
2276 * =========================== 2273 * ===========================
2277 * = dfx_ctl_set_mac_address = 2274 * = dfx_ctl_set_mac_address =
2278 * =========================== 2275 * ===========================
2279 * 2276 *
2280 * Overview: 2277 * Overview:
2281 * Add node address override (unicast address) to adapter 2278 * Add node address override (unicast address) to adapter
2282 * CAM and update dev_addr field in device table. 2279 * CAM and update dev_addr field in device table.
2283 * 2280 *
2284 * Returns: 2281 * Returns:
2285 * None 2282 * None
2286 * 2283 *
2287 * Arguments: 2284 * Arguments:
2288 * dev - pointer to device information 2285 * dev - pointer to device information
2289 * addr - pointer to sockaddr structure containing unicast address to add 2286 * addr - pointer to sockaddr structure containing unicast address to add
2290 * 2287 *
2291 * Functional Description: 2288 * Functional Description:
2292 * The adapter supports node address overrides by adding one or more 2289 * The adapter supports node address overrides by adding one or more
2293 * unicast addresses to the adapter CAM. This is similar to adding 2290 * unicast addresses to the adapter CAM. This is similar to adding
2294 * multicast addresses. In this routine we'll update the driver and 2291 * multicast addresses. In this routine we'll update the driver and
2295 * device structures with the new address, then update the adapter CAM 2292 * device structures with the new address, then update the adapter CAM
2296 * to ensure that the adapter will copy and strip frames destined and 2293 * to ensure that the adapter will copy and strip frames destined and
2297 * sourced by that address. 2294 * sourced by that address.
2298 * 2295 *
2299 * Return Codes: 2296 * Return Codes:
2300 * Always returns zero. 2297 * Always returns zero.
2301 * 2298 *
2302 * Assumptions: 2299 * Assumptions:
2303 * The address pointed to by addr->sa_data is a valid unicast 2300 * The address pointed to by addr->sa_data is a valid unicast
2304 * address and is presented in canonical (LSB) format. 2301 * address and is presented in canonical (LSB) format.
2305 * 2302 *
2306 * Side Effects: 2303 * Side Effects:
2307 * On-board adapter CAM is updated. On-board adapter filters 2304 * On-board adapter CAM is updated. On-board adapter filters
2308 * may be updated. 2305 * may be updated.
2309 */ 2306 */
2310 2307
2311 static int dfx_ctl_set_mac_address(struct net_device *dev, void *addr) 2308 static int dfx_ctl_set_mac_address(struct net_device *dev, void *addr)
2312 { 2309 {
2313 struct sockaddr *p_sockaddr = (struct sockaddr *)addr; 2310 struct sockaddr *p_sockaddr = (struct sockaddr *)addr;
2314 DFX_board_t *bp = netdev_priv(dev); 2311 DFX_board_t *bp = netdev_priv(dev);
2315 2312
2316 /* Copy unicast address to driver-maintained structs and update count */ 2313 /* Copy unicast address to driver-maintained structs and update count */
2317 2314
2318 memcpy(dev->dev_addr, p_sockaddr->sa_data, FDDI_K_ALEN); /* update device struct */ 2315 memcpy(dev->dev_addr, p_sockaddr->sa_data, FDDI_K_ALEN); /* update device struct */
2319 memcpy(&bp->uc_table[0], p_sockaddr->sa_data, FDDI_K_ALEN); /* update driver struct */ 2316 memcpy(&bp->uc_table[0], p_sockaddr->sa_data, FDDI_K_ALEN); /* update driver struct */
2320 bp->uc_count = 1; 2317 bp->uc_count = 1;
2321 2318
2322 /* 2319 /*
2323 * Verify we're not exceeding the CAM size by adding unicast address 2320 * Verify we're not exceeding the CAM size by adding unicast address
2324 * 2321 *
2325 * Note: It's possible that before entering this routine we've 2322 * Note: It's possible that before entering this routine we've
2326 * already filled the CAM with 62 multicast addresses. 2323 * already filled the CAM with 62 multicast addresses.
2327 * Since we need to place the node address override into 2324 * Since we need to place the node address override into
2328 * the CAM, we have to check to see that we're not 2325 * the CAM, we have to check to see that we're not
2329 * exceeding the CAM size. If we are, we have to enable 2326 * exceeding the CAM size. If we are, we have to enable
2330 * the LLC group (multicast) promiscuous mode filter as 2327 * the LLC group (multicast) promiscuous mode filter as
2331 * in dfx_ctl_set_multicast_list. 2328 * in dfx_ctl_set_multicast_list.
2332 */ 2329 */
2333 2330
2334 if ((bp->uc_count + bp->mc_count) > PI_CMD_ADDR_FILTER_K_SIZE) 2331 if ((bp->uc_count + bp->mc_count) > PI_CMD_ADDR_FILTER_K_SIZE)
2335 { 2332 {
2336 bp->group_prom = PI_FSTATE_K_PASS; /* Enable LLC group prom mode */ 2333 bp->group_prom = PI_FSTATE_K_PASS; /* Enable LLC group prom mode */
2337 bp->mc_count = 0; /* Don't add mc addrs to CAM */ 2334 bp->mc_count = 0; /* Don't add mc addrs to CAM */
2338 2335
2339 /* Update adapter filters */ 2336 /* Update adapter filters */
2340 2337
2341 if (dfx_ctl_update_filters(bp) != DFX_K_SUCCESS) 2338 if (dfx_ctl_update_filters(bp) != DFX_K_SUCCESS)
2342 { 2339 {
2343 DBG_printk("%s: Could not update adapter filters!\n", dev->name); 2340 DBG_printk("%s: Could not update adapter filters!\n", dev->name);
2344 } 2341 }
2345 else 2342 else
2346 { 2343 {
2347 DBG_printk("%s: Adapter filters updated!\n", dev->name); 2344 DBG_printk("%s: Adapter filters updated!\n", dev->name);
2348 } 2345 }
2349 } 2346 }
2350 2347
2351 /* Update adapter CAM with new unicast address */ 2348 /* Update adapter CAM with new unicast address */
2352 2349
2353 if (dfx_ctl_update_cam(bp) != DFX_K_SUCCESS) 2350 if (dfx_ctl_update_cam(bp) != DFX_K_SUCCESS)
2354 { 2351 {
2355 DBG_printk("%s: Could not set new MAC address!\n", dev->name); 2352 DBG_printk("%s: Could not set new MAC address!\n", dev->name);
2356 } 2353 }
2357 else 2354 else
2358 { 2355 {
2359 DBG_printk("%s: Adapter CAM updated with new MAC address\n", dev->name); 2356 DBG_printk("%s: Adapter CAM updated with new MAC address\n", dev->name);
2360 } 2357 }
2361 return(0); /* always return zero */ 2358 return(0); /* always return zero */
2362 } 2359 }
2363 2360
2364 2361
2365 /* 2362 /*
2366 * ====================== 2363 * ======================
2367 * = dfx_ctl_update_cam = 2364 * = dfx_ctl_update_cam =
2368 * ====================== 2365 * ======================
2369 * 2366 *
2370 * Overview: 2367 * Overview:
2371 * Procedure to update adapter CAM (Content Addressable Memory) 2368 * Procedure to update adapter CAM (Content Addressable Memory)
2372 * with desired unicast and multicast address entries. 2369 * with desired unicast and multicast address entries.
2373 * 2370 *
2374 * Returns: 2371 * Returns:
2375 * Condition code 2372 * Condition code
2376 * 2373 *
2377 * Arguments: 2374 * Arguments:
2378 * bp - pointer to board information 2375 * bp - pointer to board information
2379 * 2376 *
2380 * Functional Description: 2377 * Functional Description:
2381 * Updates adapter CAM with current contents of board structure 2378 * Updates adapter CAM with current contents of board structure
2382 * unicast and multicast address tables. Since there are only 62 2379 * unicast and multicast address tables. Since there are only 62
2383 * free entries in CAM, this routine ensures that the command 2380 * free entries in CAM, this routine ensures that the command
2384 * request buffer is not overrun. 2381 * request buffer is not overrun.
2385 * 2382 *
2386 * Return Codes: 2383 * Return Codes:
2387 * DFX_K_SUCCESS - Request succeeded 2384 * DFX_K_SUCCESS - Request succeeded
2388 * DFX_K_FAILURE - Request failed 2385 * DFX_K_FAILURE - Request failed
2389 * 2386 *
2390 * Assumptions: 2387 * Assumptions:
2391 * All addresses being added (unicast and multicast) are in canonical 2388 * All addresses being added (unicast and multicast) are in canonical
2392 * order. 2389 * order.
2393 * 2390 *
2394 * Side Effects: 2391 * Side Effects:
2395 * On-board adapter CAM is updated. 2392 * On-board adapter CAM is updated.
2396 */ 2393 */
2397 2394
2398 static int dfx_ctl_update_cam(DFX_board_t *bp) 2395 static int dfx_ctl_update_cam(DFX_board_t *bp)
2399 { 2396 {
2400 int i; /* used as index */ 2397 int i; /* used as index */
2401 PI_LAN_ADDR *p_addr; /* pointer to CAM entry */ 2398 PI_LAN_ADDR *p_addr; /* pointer to CAM entry */
2402 2399
2403 /* 2400 /*
2404 * Fill in command request information 2401 * Fill in command request information
2405 * 2402 *
2406 * Note: Even though both the unicast and multicast address 2403 * Note: Even though both the unicast and multicast address
2407 * table entries are stored as contiguous 6 byte entries, 2404 * table entries are stored as contiguous 6 byte entries,
2408 * the firmware address filter set command expects each 2405 * the firmware address filter set command expects each
2409 * entry to be two longwords (8 bytes total). We must be 2406 * entry to be two longwords (8 bytes total). We must be
2410 * careful to only copy the six bytes of each unicast and 2407 * careful to only copy the six bytes of each unicast and
2411 * multicast table entry into each command entry. This 2408 * multicast table entry into each command entry. This
2412 * is also why we must first clear the entire command 2409 * is also why we must first clear the entire command
2413 * request buffer. 2410 * request buffer.
2414 */ 2411 */
2415 2412
2416 memset(bp->cmd_req_virt, 0, PI_CMD_REQ_K_SIZE_MAX); /* first clear buffer */ 2413 memset(bp->cmd_req_virt, 0, PI_CMD_REQ_K_SIZE_MAX); /* first clear buffer */
2417 bp->cmd_req_virt->cmd_type = PI_CMD_K_ADDR_FILTER_SET; 2414 bp->cmd_req_virt->cmd_type = PI_CMD_K_ADDR_FILTER_SET;
2418 p_addr = &bp->cmd_req_virt->addr_filter_set.entry[0]; 2415 p_addr = &bp->cmd_req_virt->addr_filter_set.entry[0];
2419 2416
2420 /* Now add unicast addresses to command request buffer, if any */ 2417 /* Now add unicast addresses to command request buffer, if any */
2421 2418
2422 for (i=0; i < (int)bp->uc_count; i++) 2419 for (i=0; i < (int)bp->uc_count; i++)
2423 { 2420 {
2424 if (i < PI_CMD_ADDR_FILTER_K_SIZE) 2421 if (i < PI_CMD_ADDR_FILTER_K_SIZE)
2425 { 2422 {
2426 memcpy(p_addr, &bp->uc_table[i*FDDI_K_ALEN], FDDI_K_ALEN); 2423 memcpy(p_addr, &bp->uc_table[i*FDDI_K_ALEN], FDDI_K_ALEN);
2427 p_addr++; /* point to next command entry */ 2424 p_addr++; /* point to next command entry */
2428 } 2425 }
2429 } 2426 }
2430 2427
2431 /* Now add multicast addresses to command request buffer, if any */ 2428 /* Now add multicast addresses to command request buffer, if any */
2432 2429
2433 for (i=0; i < (int)bp->mc_count; i++) 2430 for (i=0; i < (int)bp->mc_count; i++)
2434 { 2431 {
2435 if ((i + bp->uc_count) < PI_CMD_ADDR_FILTER_K_SIZE) 2432 if ((i + bp->uc_count) < PI_CMD_ADDR_FILTER_K_SIZE)
2436 { 2433 {
2437 memcpy(p_addr, &bp->mc_table[i*FDDI_K_ALEN], FDDI_K_ALEN); 2434 memcpy(p_addr, &bp->mc_table[i*FDDI_K_ALEN], FDDI_K_ALEN);
2438 p_addr++; /* point to next command entry */ 2435 p_addr++; /* point to next command entry */
2439 } 2436 }
2440 } 2437 }
2441 2438
2442 /* Issue command to update adapter CAM, then return */ 2439 /* Issue command to update adapter CAM, then return */
2443 2440
2444 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS) 2441 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS)
2445 return(DFX_K_FAILURE); 2442 return(DFX_K_FAILURE);
2446 return(DFX_K_SUCCESS); 2443 return(DFX_K_SUCCESS);
2447 } 2444 }
2448 2445
2449 2446
2450 /* 2447 /*
2451 * ========================== 2448 * ==========================
2452 * = dfx_ctl_update_filters = 2449 * = dfx_ctl_update_filters =
2453 * ========================== 2450 * ==========================
2454 * 2451 *
2455 * Overview: 2452 * Overview:
2456 * Procedure to update adapter filters with desired 2453 * Procedure to update adapter filters with desired
2457 * filter settings. 2454 * filter settings.
2458 * 2455 *
2459 * Returns: 2456 * Returns:
2460 * Condition code 2457 * Condition code
2461 * 2458 *
2462 * Arguments: 2459 * Arguments:
2463 * bp - pointer to board information 2460 * bp - pointer to board information
2464 * 2461 *
2465 * Functional Description: 2462 * Functional Description:
2466 * Enables or disables filter using current filter settings. 2463 * Enables or disables filter using current filter settings.
2467 * 2464 *
2468 * Return Codes: 2465 * Return Codes:
2469 * DFX_K_SUCCESS - Request succeeded. 2466 * DFX_K_SUCCESS - Request succeeded.
2470 * DFX_K_FAILURE - Request failed. 2467 * DFX_K_FAILURE - Request failed.
2471 * 2468 *
2472 * Assumptions: 2469 * Assumptions:
2473 * We must always pass up packets destined to the broadcast 2470 * We must always pass up packets destined to the broadcast
2474 * address (FF-FF-FF-FF-FF-FF), so we'll always keep the 2471 * address (FF-FF-FF-FF-FF-FF), so we'll always keep the
2475 * broadcast filter enabled. 2472 * broadcast filter enabled.
2476 * 2473 *
2477 * Side Effects: 2474 * Side Effects:
2478 * On-board adapter filters are updated. 2475 * On-board adapter filters are updated.
2479 */ 2476 */
2480 2477
2481 static int dfx_ctl_update_filters(DFX_board_t *bp) 2478 static int dfx_ctl_update_filters(DFX_board_t *bp)
2482 { 2479 {
2483 int i = 0; /* used as index */ 2480 int i = 0; /* used as index */
2484 2481
2485 /* Fill in command request information */ 2482 /* Fill in command request information */
2486 2483
2487 bp->cmd_req_virt->cmd_type = PI_CMD_K_FILTERS_SET; 2484 bp->cmd_req_virt->cmd_type = PI_CMD_K_FILTERS_SET;
2488 2485
2489 /* Initialize Broadcast filter - * ALWAYS ENABLED * */ 2486 /* Initialize Broadcast filter - * ALWAYS ENABLED * */
2490 2487
2491 bp->cmd_req_virt->filter_set.item[i].item_code = PI_ITEM_K_BROADCAST; 2488 bp->cmd_req_virt->filter_set.item[i].item_code = PI_ITEM_K_BROADCAST;
2492 bp->cmd_req_virt->filter_set.item[i++].value = PI_FSTATE_K_PASS; 2489 bp->cmd_req_virt->filter_set.item[i++].value = PI_FSTATE_K_PASS;
2493 2490
2494 /* Initialize LLC Individual/Group Promiscuous filter */ 2491 /* Initialize LLC Individual/Group Promiscuous filter */
2495 2492
2496 bp->cmd_req_virt->filter_set.item[i].item_code = PI_ITEM_K_IND_GROUP_PROM; 2493 bp->cmd_req_virt->filter_set.item[i].item_code = PI_ITEM_K_IND_GROUP_PROM;
2497 bp->cmd_req_virt->filter_set.item[i++].value = bp->ind_group_prom; 2494 bp->cmd_req_virt->filter_set.item[i++].value = bp->ind_group_prom;
2498 2495
2499 /* Initialize LLC Group Promiscuous filter */ 2496 /* Initialize LLC Group Promiscuous filter */
2500 2497
2501 bp->cmd_req_virt->filter_set.item[i].item_code = PI_ITEM_K_GROUP_PROM; 2498 bp->cmd_req_virt->filter_set.item[i].item_code = PI_ITEM_K_GROUP_PROM;
2502 bp->cmd_req_virt->filter_set.item[i++].value = bp->group_prom; 2499 bp->cmd_req_virt->filter_set.item[i++].value = bp->group_prom;
2503 2500
2504 /* Terminate the item code list */ 2501 /* Terminate the item code list */
2505 2502
2506 bp->cmd_req_virt->filter_set.item[i].item_code = PI_ITEM_K_EOL; 2503 bp->cmd_req_virt->filter_set.item[i].item_code = PI_ITEM_K_EOL;
2507 2504
2508 /* Issue command to update adapter filters, then return */ 2505 /* Issue command to update adapter filters, then return */
2509 2506
2510 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS) 2507 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS)
2511 return(DFX_K_FAILURE); 2508 return(DFX_K_FAILURE);
2512 return(DFX_K_SUCCESS); 2509 return(DFX_K_SUCCESS);
2513 } 2510 }
2514 2511
2515 2512
2516 /* 2513 /*
2517 * ====================== 2514 * ======================
2518 * = dfx_hw_dma_cmd_req = 2515 * = dfx_hw_dma_cmd_req =
2519 * ====================== 2516 * ======================
2520 * 2517 *
2521 * Overview: 2518 * Overview:
2522 * Sends PDQ DMA command to adapter firmware 2519 * Sends PDQ DMA command to adapter firmware
2523 * 2520 *
2524 * Returns: 2521 * Returns:
2525 * Condition code 2522 * Condition code
2526 * 2523 *
2527 * Arguments: 2524 * Arguments:
2528 * bp - pointer to board information 2525 * bp - pointer to board information
2529 * 2526 *
2530 * Functional Description: 2527 * Functional Description:
2531 * The command request and response buffers are posted to the adapter in the manner 2528 * The command request and response buffers are posted to the adapter in the manner
2532 * described in the PDQ Port Specification: 2529 * described in the PDQ Port Specification:
2533 * 2530 *
2534 * 1. Command Response Buffer is posted to adapter. 2531 * 1. Command Response Buffer is posted to adapter.
2535 * 2. Command Request Buffer is posted to adapter. 2532 * 2. Command Request Buffer is posted to adapter.
2536 * 3. Command Request consumer index is polled until it indicates that request 2533 * 3. Command Request consumer index is polled until it indicates that request
2537 * buffer has been DMA'd to adapter. 2534 * buffer has been DMA'd to adapter.
2538 * 4. Command Response consumer index is polled until it indicates that response 2535 * 4. Command Response consumer index is polled until it indicates that response
2539 * buffer has been DMA'd from adapter. 2536 * buffer has been DMA'd from adapter.
2540 * 2537 *
2541 * This ordering ensures that a response buffer is already available for the firmware 2538 * This ordering ensures that a response buffer is already available for the firmware
2542 * to use once it's done processing the request buffer. 2539 * to use once it's done processing the request buffer.
2543 * 2540 *
2544 * Return Codes: 2541 * Return Codes:
2545 * DFX_K_SUCCESS - DMA command succeeded 2542 * DFX_K_SUCCESS - DMA command succeeded
2546 * DFX_K_OUTSTATE - Adapter is NOT in proper state 2543 * DFX_K_OUTSTATE - Adapter is NOT in proper state
2547 * DFX_K_HW_TIMEOUT - DMA command timed out 2544 * DFX_K_HW_TIMEOUT - DMA command timed out
2548 * 2545 *
2549 * Assumptions: 2546 * Assumptions:
2550 * Command request buffer has already been filled with desired DMA command. 2547 * Command request buffer has already been filled with desired DMA command.
2551 * 2548 *
2552 * Side Effects: 2549 * Side Effects:
2553 * None 2550 * None
2554 */ 2551 */
2555 2552
2556 static int dfx_hw_dma_cmd_req(DFX_board_t *bp) 2553 static int dfx_hw_dma_cmd_req(DFX_board_t *bp)
2557 { 2554 {
2558 int status; /* adapter status */ 2555 int status; /* adapter status */
2559 int timeout_cnt; /* used in for loops */ 2556 int timeout_cnt; /* used in for loops */
2560 2557
2561 /* Make sure the adapter is in a state that we can issue the DMA command in */ 2558 /* Make sure the adapter is in a state that we can issue the DMA command in */
2562 2559
2563 status = dfx_hw_adap_state_rd(bp); 2560 status = dfx_hw_adap_state_rd(bp);
2564 if ((status == PI_STATE_K_RESET) || 2561 if ((status == PI_STATE_K_RESET) ||
2565 (status == PI_STATE_K_HALTED) || 2562 (status == PI_STATE_K_HALTED) ||
2566 (status == PI_STATE_K_DMA_UNAVAIL) || 2563 (status == PI_STATE_K_DMA_UNAVAIL) ||
2567 (status == PI_STATE_K_UPGRADE)) 2564 (status == PI_STATE_K_UPGRADE))
2568 return(DFX_K_OUTSTATE); 2565 return(DFX_K_OUTSTATE);
2569 2566
2570 /* Put response buffer on the command response queue */ 2567 /* Put response buffer on the command response queue */
2571 2568
2572 bp->descr_block_virt->cmd_rsp[bp->cmd_rsp_reg.index.prod].long_0 = (u32) (PI_RCV_DESCR_M_SOP | 2569 bp->descr_block_virt->cmd_rsp[bp->cmd_rsp_reg.index.prod].long_0 = (u32) (PI_RCV_DESCR_M_SOP |
2573 ((PI_CMD_RSP_K_SIZE_MAX / PI_ALIGN_K_CMD_RSP_BUFF) << PI_RCV_DESCR_V_SEG_LEN)); 2570 ((PI_CMD_RSP_K_SIZE_MAX / PI_ALIGN_K_CMD_RSP_BUFF) << PI_RCV_DESCR_V_SEG_LEN));
2574 bp->descr_block_virt->cmd_rsp[bp->cmd_rsp_reg.index.prod].long_1 = bp->cmd_rsp_phys; 2571 bp->descr_block_virt->cmd_rsp[bp->cmd_rsp_reg.index.prod].long_1 = bp->cmd_rsp_phys;
2575 2572
2576 /* Bump (and wrap) the producer index and write out to register */ 2573 /* Bump (and wrap) the producer index and write out to register */
2577 2574
2578 bp->cmd_rsp_reg.index.prod += 1; 2575 bp->cmd_rsp_reg.index.prod += 1;
2579 bp->cmd_rsp_reg.index.prod &= PI_CMD_RSP_K_NUM_ENTRIES-1; 2576 bp->cmd_rsp_reg.index.prod &= PI_CMD_RSP_K_NUM_ENTRIES-1;
2580 dfx_port_write_long(bp, PI_PDQ_K_REG_CMD_RSP_PROD, bp->cmd_rsp_reg.lword); 2577 dfx_port_write_long(bp, PI_PDQ_K_REG_CMD_RSP_PROD, bp->cmd_rsp_reg.lword);
2581 2578
2582 /* Put request buffer on the command request queue */ 2579 /* Put request buffer on the command request queue */
2583 2580
2584 bp->descr_block_virt->cmd_req[bp->cmd_req_reg.index.prod].long_0 = (u32) (PI_XMT_DESCR_M_SOP | 2581 bp->descr_block_virt->cmd_req[bp->cmd_req_reg.index.prod].long_0 = (u32) (PI_XMT_DESCR_M_SOP |
2585 PI_XMT_DESCR_M_EOP | (PI_CMD_REQ_K_SIZE_MAX << PI_XMT_DESCR_V_SEG_LEN)); 2582 PI_XMT_DESCR_M_EOP | (PI_CMD_REQ_K_SIZE_MAX << PI_XMT_DESCR_V_SEG_LEN));
2586 bp->descr_block_virt->cmd_req[bp->cmd_req_reg.index.prod].long_1 = bp->cmd_req_phys; 2583 bp->descr_block_virt->cmd_req[bp->cmd_req_reg.index.prod].long_1 = bp->cmd_req_phys;
2587 2584
2588 /* Bump (and wrap) the producer index and write out to register */ 2585 /* Bump (and wrap) the producer index and write out to register */
2589 2586
2590 bp->cmd_req_reg.index.prod += 1; 2587 bp->cmd_req_reg.index.prod += 1;
2591 bp->cmd_req_reg.index.prod &= PI_CMD_REQ_K_NUM_ENTRIES-1; 2588 bp->cmd_req_reg.index.prod &= PI_CMD_REQ_K_NUM_ENTRIES-1;
2592 dfx_port_write_long(bp, PI_PDQ_K_REG_CMD_REQ_PROD, bp->cmd_req_reg.lword); 2589 dfx_port_write_long(bp, PI_PDQ_K_REG_CMD_REQ_PROD, bp->cmd_req_reg.lword);
2593 2590
2594 /* 2591 /*
2595 * Here we wait for the command request consumer index to be equal 2592 * Here we wait for the command request consumer index to be equal
2596 * to the producer, indicating that the adapter has DMAed the request. 2593 * to the producer, indicating that the adapter has DMAed the request.
2597 */ 2594 */
2598 2595
2599 for (timeout_cnt = 20000; timeout_cnt > 0; timeout_cnt--) 2596 for (timeout_cnt = 20000; timeout_cnt > 0; timeout_cnt--)
2600 { 2597 {
2601 if (bp->cmd_req_reg.index.prod == (u8)(bp->cons_block_virt->cmd_req)) 2598 if (bp->cmd_req_reg.index.prod == (u8)(bp->cons_block_virt->cmd_req))
2602 break; 2599 break;
2603 udelay(100); /* wait for 100 microseconds */ 2600 udelay(100); /* wait for 100 microseconds */
2604 } 2601 }
2605 if (timeout_cnt == 0) 2602 if (timeout_cnt == 0)
2606 return(DFX_K_HW_TIMEOUT); 2603 return(DFX_K_HW_TIMEOUT);
2607 2604
2608 /* Bump (and wrap) the completion index and write out to register */ 2605 /* Bump (and wrap) the completion index and write out to register */
2609 2606
2610 bp->cmd_req_reg.index.comp += 1; 2607 bp->cmd_req_reg.index.comp += 1;
2611 bp->cmd_req_reg.index.comp &= PI_CMD_REQ_K_NUM_ENTRIES-1; 2608 bp->cmd_req_reg.index.comp &= PI_CMD_REQ_K_NUM_ENTRIES-1;
2612 dfx_port_write_long(bp, PI_PDQ_K_REG_CMD_REQ_PROD, bp->cmd_req_reg.lword); 2609 dfx_port_write_long(bp, PI_PDQ_K_REG_CMD_REQ_PROD, bp->cmd_req_reg.lword);
2613 2610
2614 /* 2611 /*
2615 * Here we wait for the command response consumer index to be equal 2612 * Here we wait for the command response consumer index to be equal
2616 * to the producer, indicating that the adapter has DMAed the response. 2613 * to the producer, indicating that the adapter has DMAed the response.
2617 */ 2614 */
2618 2615
2619 for (timeout_cnt = 20000; timeout_cnt > 0; timeout_cnt--) 2616 for (timeout_cnt = 20000; timeout_cnt > 0; timeout_cnt--)
2620 { 2617 {
2621 if (bp->cmd_rsp_reg.index.prod == (u8)(bp->cons_block_virt->cmd_rsp)) 2618 if (bp->cmd_rsp_reg.index.prod == (u8)(bp->cons_block_virt->cmd_rsp))
2622 break; 2619 break;
2623 udelay(100); /* wait for 100 microseconds */ 2620 udelay(100); /* wait for 100 microseconds */
2624 } 2621 }
2625 if (timeout_cnt == 0) 2622 if (timeout_cnt == 0)
2626 return(DFX_K_HW_TIMEOUT); 2623 return(DFX_K_HW_TIMEOUT);
2627 2624
2628 /* Bump (and wrap) the completion index and write out to register */ 2625 /* Bump (and wrap) the completion index and write out to register */
2629 2626
2630 bp->cmd_rsp_reg.index.comp += 1; 2627 bp->cmd_rsp_reg.index.comp += 1;
2631 bp->cmd_rsp_reg.index.comp &= PI_CMD_RSP_K_NUM_ENTRIES-1; 2628 bp->cmd_rsp_reg.index.comp &= PI_CMD_RSP_K_NUM_ENTRIES-1;
2632 dfx_port_write_long(bp, PI_PDQ_K_REG_CMD_RSP_PROD, bp->cmd_rsp_reg.lword); 2629 dfx_port_write_long(bp, PI_PDQ_K_REG_CMD_RSP_PROD, bp->cmd_rsp_reg.lword);
2633 return(DFX_K_SUCCESS); 2630 return(DFX_K_SUCCESS);
2634 } 2631 }
2635 2632
2636 2633
2637 /* 2634 /*
2638 * ======================== 2635 * ========================
2639 * = dfx_hw_port_ctrl_req = 2636 * = dfx_hw_port_ctrl_req =
2640 * ======================== 2637 * ========================
2641 * 2638 *
2642 * Overview: 2639 * Overview:
2643 * Sends PDQ port control command to adapter firmware 2640 * Sends PDQ port control command to adapter firmware
2644 * 2641 *
2645 * Returns: 2642 * Returns:
2646 * Host data register value in host_data if ptr is not NULL 2643 * Host data register value in host_data if ptr is not NULL
2647 * 2644 *
2648 * Arguments: 2645 * Arguments:
2649 * bp - pointer to board information 2646 * bp - pointer to board information
2650 * command - port control command 2647 * command - port control command
2651 * data_a - port data A register value 2648 * data_a - port data A register value
2652 * data_b - port data B register value 2649 * data_b - port data B register value
2653 * host_data - ptr to host data register value 2650 * host_data - ptr to host data register value
2654 * 2651 *
2655 * Functional Description: 2652 * Functional Description:
2656 * Send generic port control command to adapter by writing 2653 * Send generic port control command to adapter by writing
2657 * to various PDQ port registers, then polling for completion. 2654 * to various PDQ port registers, then polling for completion.
2658 * 2655 *
2659 * Return Codes: 2656 * Return Codes:
2660 * DFX_K_SUCCESS - port control command succeeded 2657 * DFX_K_SUCCESS - port control command succeeded
2661 * DFX_K_HW_TIMEOUT - port control command timed out 2658 * DFX_K_HW_TIMEOUT - port control command timed out
2662 * 2659 *
2663 * Assumptions: 2660 * Assumptions:
2664 * None 2661 * None
2665 * 2662 *
2666 * Side Effects: 2663 * Side Effects:
2667 * None 2664 * None
2668 */ 2665 */
2669 2666
2670 static int dfx_hw_port_ctrl_req( 2667 static int dfx_hw_port_ctrl_req(
2671 DFX_board_t *bp, 2668 DFX_board_t *bp,
2672 PI_UINT32 command, 2669 PI_UINT32 command,
2673 PI_UINT32 data_a, 2670 PI_UINT32 data_a,
2674 PI_UINT32 data_b, 2671 PI_UINT32 data_b,
2675 PI_UINT32 *host_data 2672 PI_UINT32 *host_data
2676 ) 2673 )
2677 2674
2678 { 2675 {
2679 PI_UINT32 port_cmd; /* Port Control command register value */ 2676 PI_UINT32 port_cmd; /* Port Control command register value */
2680 int timeout_cnt; /* used in for loops */ 2677 int timeout_cnt; /* used in for loops */
2681 2678
2682 /* Set Command Error bit in command longword */ 2679 /* Set Command Error bit in command longword */
2683 2680
2684 port_cmd = (PI_UINT32) (command | PI_PCTRL_M_CMD_ERROR); 2681 port_cmd = (PI_UINT32) (command | PI_PCTRL_M_CMD_ERROR);
2685 2682
2686 /* Issue port command to the adapter */ 2683 /* Issue port command to the adapter */
2687 2684
2688 dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_DATA_A, data_a); 2685 dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_DATA_A, data_a);
2689 dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_DATA_B, data_b); 2686 dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_DATA_B, data_b);
2690 dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_CTRL, port_cmd); 2687 dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_CTRL, port_cmd);
2691 2688
2692 /* Now wait for command to complete */ 2689 /* Now wait for command to complete */
2693 2690
2694 if (command == PI_PCTRL_M_BLAST_FLASH) 2691 if (command == PI_PCTRL_M_BLAST_FLASH)
2695 timeout_cnt = 600000; /* set command timeout count to 60 seconds */ 2692 timeout_cnt = 600000; /* set command timeout count to 60 seconds */
2696 else 2693 else
2697 timeout_cnt = 20000; /* set command timeout count to 2 seconds */ 2694 timeout_cnt = 20000; /* set command timeout count to 2 seconds */
2698 2695
2699 for (; timeout_cnt > 0; timeout_cnt--) 2696 for (; timeout_cnt > 0; timeout_cnt--)
2700 { 2697 {
2701 dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_CTRL, &port_cmd); 2698 dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_CTRL, &port_cmd);
2702 if (!(port_cmd & PI_PCTRL_M_CMD_ERROR)) 2699 if (!(port_cmd & PI_PCTRL_M_CMD_ERROR))
2703 break; 2700 break;
2704 udelay(100); /* wait for 100 microseconds */ 2701 udelay(100); /* wait for 100 microseconds */
2705 } 2702 }
2706 if (timeout_cnt == 0) 2703 if (timeout_cnt == 0)
2707 return(DFX_K_HW_TIMEOUT); 2704 return(DFX_K_HW_TIMEOUT);
2708 2705
2709 /* 2706 /*
2710 * If the address of host_data is non-zero, assume caller has supplied a 2707 * If the address of host_data is non-zero, assume caller has supplied a
2711 * non NULL pointer, and return the contents of the HOST_DATA register in 2708 * non NULL pointer, and return the contents of the HOST_DATA register in
2712 * it. 2709 * it.
2713 */ 2710 */
2714 2711
2715 if (host_data != NULL) 2712 if (host_data != NULL)
2716 dfx_port_read_long(bp, PI_PDQ_K_REG_HOST_DATA, host_data); 2713 dfx_port_read_long(bp, PI_PDQ_K_REG_HOST_DATA, host_data);
2717 return(DFX_K_SUCCESS); 2714 return(DFX_K_SUCCESS);
2718 } 2715 }
2719 2716
2720 2717
2721 /* 2718 /*
2722 * ===================== 2719 * =====================
2723 * = dfx_hw_adap_reset = 2720 * = dfx_hw_adap_reset =
2724 * ===================== 2721 * =====================
2725 * 2722 *
2726 * Overview: 2723 * Overview:
2727 * Resets adapter 2724 * Resets adapter
2728 * 2725 *
2729 * Returns: 2726 * Returns:
2730 * None 2727 * None
2731 * 2728 *
2732 * Arguments: 2729 * Arguments:
2733 * bp - pointer to board information 2730 * bp - pointer to board information
2734 * type - type of reset to perform 2731 * type - type of reset to perform
2735 * 2732 *
2736 * Functional Description: 2733 * Functional Description:
2737 * Issue soft reset to adapter by writing to PDQ Port Reset 2734 * Issue soft reset to adapter by writing to PDQ Port Reset
2738 * register. Use incoming reset type to tell adapter what 2735 * register. Use incoming reset type to tell adapter what
2739 * kind of reset operation to perform. 2736 * kind of reset operation to perform.
2740 * 2737 *
2741 * Return Codes: 2738 * Return Codes:
2742 * None 2739 * None
2743 * 2740 *
2744 * Assumptions: 2741 * Assumptions:
2745 * This routine merely issues a soft reset to the adapter. 2742 * This routine merely issues a soft reset to the adapter.
2746 * It is expected that after this routine returns, the caller 2743 * It is expected that after this routine returns, the caller
2747 * will appropriately poll the Port Status register for the 2744 * will appropriately poll the Port Status register for the
2748 * adapter to enter the proper state. 2745 * adapter to enter the proper state.
2749 * 2746 *
2750 * Side Effects: 2747 * Side Effects:
2751 * Internal adapter registers are cleared. 2748 * Internal adapter registers are cleared.
2752 */ 2749 */
2753 2750
2754 static void dfx_hw_adap_reset( 2751 static void dfx_hw_adap_reset(
2755 DFX_board_t *bp, 2752 DFX_board_t *bp,
2756 PI_UINT32 type 2753 PI_UINT32 type
2757 ) 2754 )
2758 2755
2759 { 2756 {
2760 /* Set Reset type and assert reset */ 2757 /* Set Reset type and assert reset */
2761 2758
2762 dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_DATA_A, type); /* tell adapter type of reset */ 2759 dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_DATA_A, type); /* tell adapter type of reset */
2763 dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_RESET, PI_RESET_M_ASSERT_RESET); 2760 dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_RESET, PI_RESET_M_ASSERT_RESET);
2764 2761
2765 /* Wait for at least 1 Microsecond according to the spec. We wait 20 just to be safe */ 2762 /* Wait for at least 1 Microsecond according to the spec. We wait 20 just to be safe */
2766 2763
2767 udelay(20); 2764 udelay(20);
2768 2765
2769 /* Deassert reset */ 2766 /* Deassert reset */
2770 2767
2771 dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_RESET, 0); 2768 dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_RESET, 0);
2772 } 2769 }
2773 2770
2774 2771
2775 /* 2772 /*
2776 * ======================== 2773 * ========================
2777 * = dfx_hw_adap_state_rd = 2774 * = dfx_hw_adap_state_rd =
2778 * ======================== 2775 * ========================
2779 * 2776 *
2780 * Overview: 2777 * Overview:
2781 * Returns current adapter state 2778 * Returns current adapter state
2782 * 2779 *
2783 * Returns: 2780 * Returns:
2784 * Adapter state per PDQ Port Specification 2781 * Adapter state per PDQ Port Specification
2785 * 2782 *
2786 * Arguments: 2783 * Arguments:
2787 * bp - pointer to board information 2784 * bp - pointer to board information
2788 * 2785 *
2789 * Functional Description: 2786 * Functional Description:
2790 * Reads PDQ Port Status register and returns adapter state. 2787 * Reads PDQ Port Status register and returns adapter state.
2791 * 2788 *
2792 * Return Codes: 2789 * Return Codes:
2793 * None 2790 * None
2794 * 2791 *
2795 * Assumptions: 2792 * Assumptions:
2796 * None 2793 * None
2797 * 2794 *
2798 * Side Effects: 2795 * Side Effects:
2799 * None 2796 * None
2800 */ 2797 */
2801 2798
2802 static int dfx_hw_adap_state_rd(DFX_board_t *bp) 2799 static int dfx_hw_adap_state_rd(DFX_board_t *bp)
2803 { 2800 {
2804 PI_UINT32 port_status; /* Port Status register value */ 2801 PI_UINT32 port_status; /* Port Status register value */
2805 2802
2806 dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_STATUS, &port_status); 2803 dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_STATUS, &port_status);
2807 return((port_status & PI_PSTATUS_M_STATE) >> PI_PSTATUS_V_STATE); 2804 return((port_status & PI_PSTATUS_M_STATE) >> PI_PSTATUS_V_STATE);
2808 } 2805 }
2809 2806
2810 2807
2811 /* 2808 /*
2812 * ===================== 2809 * =====================
2813 * = dfx_hw_dma_uninit = 2810 * = dfx_hw_dma_uninit =
2814 * ===================== 2811 * =====================
2815 * 2812 *
2816 * Overview: 2813 * Overview:
2817 * Brings adapter to DMA_UNAVAILABLE state 2814 * Brings adapter to DMA_UNAVAILABLE state
2818 * 2815 *
2819 * Returns: 2816 * Returns:
2820 * Condition code 2817 * Condition code
2821 * 2818 *
2822 * Arguments: 2819 * Arguments:
2823 * bp - pointer to board information 2820 * bp - pointer to board information
2824 * type - type of reset to perform 2821 * type - type of reset to perform
2825 * 2822 *
2826 * Functional Description: 2823 * Functional Description:
2827 * Bring adapter to DMA_UNAVAILABLE state by performing the following: 2824 * Bring adapter to DMA_UNAVAILABLE state by performing the following:
2828 * 1. Set reset type bit in Port Data A Register then reset adapter. 2825 * 1. Set reset type bit in Port Data A Register then reset adapter.
2829 * 2. Check that adapter is in DMA_UNAVAILABLE state. 2826 * 2. Check that adapter is in DMA_UNAVAILABLE state.
2830 * 2827 *
2831 * Return Codes: 2828 * Return Codes:
2832 * DFX_K_SUCCESS - adapter is in DMA_UNAVAILABLE state 2829 * DFX_K_SUCCESS - adapter is in DMA_UNAVAILABLE state
2833 * DFX_K_HW_TIMEOUT - adapter did not reset properly 2830 * DFX_K_HW_TIMEOUT - adapter did not reset properly
2834 * 2831 *
2835 * Assumptions: 2832 * Assumptions:
2836 * None 2833 * None
2837 * 2834 *
2838 * Side Effects: 2835 * Side Effects:
2839 * Internal adapter registers are cleared. 2836 * Internal adapter registers are cleared.
2840 */ 2837 */
2841 2838
2842 static int dfx_hw_dma_uninit(DFX_board_t *bp, PI_UINT32 type) 2839 static int dfx_hw_dma_uninit(DFX_board_t *bp, PI_UINT32 type)
2843 { 2840 {
2844 int timeout_cnt; /* used in for loops */ 2841 int timeout_cnt; /* used in for loops */
2845 2842
2846 /* Set reset type bit and reset adapter */ 2843 /* Set reset type bit and reset adapter */
2847 2844
2848 dfx_hw_adap_reset(bp, type); 2845 dfx_hw_adap_reset(bp, type);
2849 2846
2850 /* Now wait for adapter to enter DMA_UNAVAILABLE state */ 2847 /* Now wait for adapter to enter DMA_UNAVAILABLE state */
2851 2848
2852 for (timeout_cnt = 100000; timeout_cnt > 0; timeout_cnt--) 2849 for (timeout_cnt = 100000; timeout_cnt > 0; timeout_cnt--)
2853 { 2850 {
2854 if (dfx_hw_adap_state_rd(bp) == PI_STATE_K_DMA_UNAVAIL) 2851 if (dfx_hw_adap_state_rd(bp) == PI_STATE_K_DMA_UNAVAIL)
2855 break; 2852 break;
2856 udelay(100); /* wait for 100 microseconds */ 2853 udelay(100); /* wait for 100 microseconds */
2857 } 2854 }
2858 if (timeout_cnt == 0) 2855 if (timeout_cnt == 0)
2859 return(DFX_K_HW_TIMEOUT); 2856 return(DFX_K_HW_TIMEOUT);
2860 return(DFX_K_SUCCESS); 2857 return(DFX_K_SUCCESS);
2861 } 2858 }
2862 2859
2863 /* 2860 /*
2864 * Align an sk_buff to a boundary power of 2 2861 * Align an sk_buff to a boundary power of 2
2865 * 2862 *
2866 */ 2863 */
2867 2864
2868 static void my_skb_align(struct sk_buff *skb, int n) 2865 static void my_skb_align(struct sk_buff *skb, int n)
2869 { 2866 {
2870 unsigned long x = (unsigned long)skb->data; 2867 unsigned long x = (unsigned long)skb->data;
2871 unsigned long v; 2868 unsigned long v;
2872 2869
2873 v = ALIGN(x, n); /* Where we want to be */ 2870 v = ALIGN(x, n); /* Where we want to be */
2874 2871
2875 skb_reserve(skb, v - x); 2872 skb_reserve(skb, v - x);
2876 } 2873 }
2877 2874
2878 2875
2879 /* 2876 /*
2880 * ================ 2877 * ================
2881 * = dfx_rcv_init = 2878 * = dfx_rcv_init =
2882 * ================ 2879 * ================
2883 * 2880 *
2884 * Overview: 2881 * Overview:
2885 * Produces buffers to adapter LLC Host receive descriptor block 2882 * Produces buffers to adapter LLC Host receive descriptor block
2886 * 2883 *
2887 * Returns: 2884 * Returns:
2888 * None 2885 * None
2889 * 2886 *
2890 * Arguments: 2887 * Arguments:
2891 * bp - pointer to board information 2888 * bp - pointer to board information
2892 * get_buffers - non-zero if buffers to be allocated 2889 * get_buffers - non-zero if buffers to be allocated
2893 * 2890 *
2894 * Functional Description: 2891 * Functional Description:
2895 * This routine can be called during dfx_adap_init() or during an adapter 2892 * This routine can be called during dfx_adap_init() or during an adapter
2896 * reset. It initializes the descriptor block and produces all allocated 2893 * reset. It initializes the descriptor block and produces all allocated
2897 * LLC Host queue receive buffers. 2894 * LLC Host queue receive buffers.
2898 * 2895 *
2899 * Return Codes: 2896 * Return Codes:
2900 * Return 0 on success or -ENOMEM if buffer allocation failed (when using 2897 * Return 0 on success or -ENOMEM if buffer allocation failed (when using
2901 * dynamic buffer allocation). If the buffer allocation failed, the 2898 * dynamic buffer allocation). If the buffer allocation failed, the
2902 * already allocated buffers will not be released and the caller should do 2899 * already allocated buffers will not be released and the caller should do
2903 * this. 2900 * this.
2904 * 2901 *
2905 * Assumptions: 2902 * Assumptions:
2906 * The PDQ has been reset and the adapter and driver maintained Type 2 2903 * The PDQ has been reset and the adapter and driver maintained Type 2
2907 * register indices are cleared. 2904 * register indices are cleared.
2908 * 2905 *
2909 * Side Effects: 2906 * Side Effects:
2910 * Receive buffers are posted to the adapter LLC queue and the adapter 2907 * Receive buffers are posted to the adapter LLC queue and the adapter
2911 * is notified. 2908 * is notified.
2912 */ 2909 */
2913 2910
2914 static int dfx_rcv_init(DFX_board_t *bp, int get_buffers) 2911 static int dfx_rcv_init(DFX_board_t *bp, int get_buffers)
2915 { 2912 {
2916 int i, j; /* used in for loop */ 2913 int i, j; /* used in for loop */
2917 2914
2918 /* 2915 /*
2919 * Since each receive buffer is a single fragment of same length, initialize 2916 * Since each receive buffer is a single fragment of same length, initialize
2920 * first longword in each receive descriptor for entire LLC Host descriptor 2917 * first longword in each receive descriptor for entire LLC Host descriptor
2921 * block. Also initialize second longword in each receive descriptor with 2918 * block. Also initialize second longword in each receive descriptor with
2922 * physical address of receive buffer. We'll always allocate receive 2919 * physical address of receive buffer. We'll always allocate receive
2923 * buffers in powers of 2 so that we can easily fill the 256 entry descriptor 2920 * buffers in powers of 2 so that we can easily fill the 256 entry descriptor
2924 * block and produce new receive buffers by simply updating the receive 2921 * block and produce new receive buffers by simply updating the receive
2925 * producer index. 2922 * producer index.
2926 * 2923 *
2927 * Assumptions: 2924 * Assumptions:
2928 * To support all shipping versions of PDQ, the receive buffer size 2925 * To support all shipping versions of PDQ, the receive buffer size
2929 * must be mod 128 in length and the physical address must be 128 byte 2926 * must be mod 128 in length and the physical address must be 128 byte
2930 * aligned. In other words, bits 0-6 of the length and address must 2927 * aligned. In other words, bits 0-6 of the length and address must
2931 * be zero for the following descriptor field entries to be correct on 2928 * be zero for the following descriptor field entries to be correct on
2932 * all PDQ-based boards. We guaranteed both requirements during 2929 * all PDQ-based boards. We guaranteed both requirements during
2933 * driver initialization when we allocated memory for the receive buffers. 2930 * driver initialization when we allocated memory for the receive buffers.
2934 */ 2931 */
2935 2932
2936 if (get_buffers) { 2933 if (get_buffers) {
2937 #ifdef DYNAMIC_BUFFERS 2934 #ifdef DYNAMIC_BUFFERS
2938 for (i = 0; i < (int)(bp->rcv_bufs_to_post); i++) 2935 for (i = 0; i < (int)(bp->rcv_bufs_to_post); i++)
2939 for (j = 0; (i + j) < (int)PI_RCV_DATA_K_NUM_ENTRIES; j += bp->rcv_bufs_to_post) 2936 for (j = 0; (i + j) < (int)PI_RCV_DATA_K_NUM_ENTRIES; j += bp->rcv_bufs_to_post)
2940 { 2937 {
2941 struct sk_buff *newskb = __netdev_alloc_skb(bp->dev, NEW_SKB_SIZE, GFP_NOIO); 2938 struct sk_buff *newskb = __netdev_alloc_skb(bp->dev, NEW_SKB_SIZE, GFP_NOIO);
2942 if (!newskb) 2939 if (!newskb)
2943 return -ENOMEM; 2940 return -ENOMEM;
2944 bp->descr_block_virt->rcv_data[i+j].long_0 = (u32) (PI_RCV_DESCR_M_SOP | 2941 bp->descr_block_virt->rcv_data[i+j].long_0 = (u32) (PI_RCV_DESCR_M_SOP |
2945 ((PI_RCV_DATA_K_SIZE_MAX / PI_ALIGN_K_RCV_DATA_BUFF) << PI_RCV_DESCR_V_SEG_LEN)); 2942 ((PI_RCV_DATA_K_SIZE_MAX / PI_ALIGN_K_RCV_DATA_BUFF) << PI_RCV_DESCR_V_SEG_LEN));
2946 /* 2943 /*
2947 * align to 128 bytes for compatibility with 2944 * align to 128 bytes for compatibility with
2948 * the old EISA boards. 2945 * the old EISA boards.
2949 */ 2946 */
2950 2947
2951 my_skb_align(newskb, 128); 2948 my_skb_align(newskb, 128);
2952 bp->descr_block_virt->rcv_data[i + j].long_1 = 2949 bp->descr_block_virt->rcv_data[i + j].long_1 =
2953 (u32)dma_map_single(bp->bus_dev, newskb->data, 2950 (u32)dma_map_single(bp->bus_dev, newskb->data,
2954 NEW_SKB_SIZE, 2951 NEW_SKB_SIZE,
2955 DMA_FROM_DEVICE); 2952 DMA_FROM_DEVICE);
2956 /* 2953 /*
2957 * p_rcv_buff_va is only used inside the 2954 * p_rcv_buff_va is only used inside the
2958 * kernel so we put the skb pointer here. 2955 * kernel so we put the skb pointer here.
2959 */ 2956 */
2960 bp->p_rcv_buff_va[i+j] = (char *) newskb; 2957 bp->p_rcv_buff_va[i+j] = (char *) newskb;
2961 } 2958 }
2962 #else 2959 #else
2963 for (i=0; i < (int)(bp->rcv_bufs_to_post); i++) 2960 for (i=0; i < (int)(bp->rcv_bufs_to_post); i++)
2964 for (j=0; (i + j) < (int)PI_RCV_DATA_K_NUM_ENTRIES; j += bp->rcv_bufs_to_post) 2961 for (j=0; (i + j) < (int)PI_RCV_DATA_K_NUM_ENTRIES; j += bp->rcv_bufs_to_post)
2965 { 2962 {
2966 bp->descr_block_virt->rcv_data[i+j].long_0 = (u32) (PI_RCV_DESCR_M_SOP | 2963 bp->descr_block_virt->rcv_data[i+j].long_0 = (u32) (PI_RCV_DESCR_M_SOP |
2967 ((PI_RCV_DATA_K_SIZE_MAX / PI_ALIGN_K_RCV_DATA_BUFF) << PI_RCV_DESCR_V_SEG_LEN)); 2964 ((PI_RCV_DATA_K_SIZE_MAX / PI_ALIGN_K_RCV_DATA_BUFF) << PI_RCV_DESCR_V_SEG_LEN));
2968 bp->descr_block_virt->rcv_data[i+j].long_1 = (u32) (bp->rcv_block_phys + (i * PI_RCV_DATA_K_SIZE_MAX)); 2965 bp->descr_block_virt->rcv_data[i+j].long_1 = (u32) (bp->rcv_block_phys + (i * PI_RCV_DATA_K_SIZE_MAX));
2969 bp->p_rcv_buff_va[i+j] = (char *) (bp->rcv_block_virt + (i * PI_RCV_DATA_K_SIZE_MAX)); 2966 bp->p_rcv_buff_va[i+j] = (char *) (bp->rcv_block_virt + (i * PI_RCV_DATA_K_SIZE_MAX));
2970 } 2967 }
2971 #endif 2968 #endif
2972 } 2969 }
2973 2970
2974 /* Update receive producer and Type 2 register */ 2971 /* Update receive producer and Type 2 register */
2975 2972
2976 bp->rcv_xmt_reg.index.rcv_prod = bp->rcv_bufs_to_post; 2973 bp->rcv_xmt_reg.index.rcv_prod = bp->rcv_bufs_to_post;
2977 dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_2_PROD, bp->rcv_xmt_reg.lword); 2974 dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_2_PROD, bp->rcv_xmt_reg.lword);
2978 return 0; 2975 return 0;
2979 } 2976 }
2980 2977
2981 2978
2982 /* 2979 /*
2983 * ========================= 2980 * =========================
2984 * = dfx_rcv_queue_process = 2981 * = dfx_rcv_queue_process =
2985 * ========================= 2982 * =========================
2986 * 2983 *
2987 * Overview: 2984 * Overview:
2988 * Process received LLC frames. 2985 * Process received LLC frames.
2989 * 2986 *
2990 * Returns: 2987 * Returns:
2991 * None 2988 * None
2992 * 2989 *
2993 * Arguments: 2990 * Arguments:
2994 * bp - pointer to board information 2991 * bp - pointer to board information
2995 * 2992 *
2996 * Functional Description: 2993 * Functional Description:
2997 * Received LLC frames are processed until there are no more consumed frames. 2994 * Received LLC frames are processed until there are no more consumed frames.
2998 * Once all frames are processed, the receive buffers are returned to the 2995 * Once all frames are processed, the receive buffers are returned to the
2999 * adapter. Note that this algorithm fixes the length of time that can be spent 2996 * adapter. Note that this algorithm fixes the length of time that can be spent
3000 * in this routine, because there are a fixed number of receive buffers to 2997 * in this routine, because there are a fixed number of receive buffers to
3001 * process and buffers are not produced until this routine exits and returns 2998 * process and buffers are not produced until this routine exits and returns
3002 * to the ISR. 2999 * to the ISR.
3003 * 3000 *
3004 * Return Codes: 3001 * Return Codes:
3005 * None 3002 * None
3006 * 3003 *
3007 * Assumptions: 3004 * Assumptions:
3008 * None 3005 * None
3009 * 3006 *
3010 * Side Effects: 3007 * Side Effects:
3011 * None 3008 * None
3012 */ 3009 */
3013 3010
3014 static void dfx_rcv_queue_process( 3011 static void dfx_rcv_queue_process(
3015 DFX_board_t *bp 3012 DFX_board_t *bp
3016 ) 3013 )
3017 3014
3018 { 3015 {
3019 PI_TYPE_2_CONSUMER *p_type_2_cons; /* ptr to rcv/xmt consumer block register */ 3016 PI_TYPE_2_CONSUMER *p_type_2_cons; /* ptr to rcv/xmt consumer block register */
3020 char *p_buff; /* ptr to start of packet receive buffer (FMC descriptor) */ 3017 char *p_buff; /* ptr to start of packet receive buffer (FMC descriptor) */
3021 u32 descr, pkt_len; /* FMC descriptor field and packet length */ 3018 u32 descr, pkt_len; /* FMC descriptor field and packet length */
3022 struct sk_buff *skb; /* pointer to a sk_buff to hold incoming packet data */ 3019 struct sk_buff *skb; /* pointer to a sk_buff to hold incoming packet data */
3023 3020
3024 /* Service all consumed LLC receive frames */ 3021 /* Service all consumed LLC receive frames */
3025 3022
3026 p_type_2_cons = (PI_TYPE_2_CONSUMER *)(&bp->cons_block_virt->xmt_rcv_data); 3023 p_type_2_cons = (PI_TYPE_2_CONSUMER *)(&bp->cons_block_virt->xmt_rcv_data);
3027 while (bp->rcv_xmt_reg.index.rcv_comp != p_type_2_cons->index.rcv_cons) 3024 while (bp->rcv_xmt_reg.index.rcv_comp != p_type_2_cons->index.rcv_cons)
3028 { 3025 {
3029 /* Process any errors */ 3026 /* Process any errors */
3030 3027
3031 int entry; 3028 int entry;
3032 3029
3033 entry = bp->rcv_xmt_reg.index.rcv_comp; 3030 entry = bp->rcv_xmt_reg.index.rcv_comp;
3034 #ifdef DYNAMIC_BUFFERS 3031 #ifdef DYNAMIC_BUFFERS
3035 p_buff = (char *) (((struct sk_buff *)bp->p_rcv_buff_va[entry])->data); 3032 p_buff = (char *) (((struct sk_buff *)bp->p_rcv_buff_va[entry])->data);
3036 #else 3033 #else
3037 p_buff = (char *) bp->p_rcv_buff_va[entry]; 3034 p_buff = (char *) bp->p_rcv_buff_va[entry];
3038 #endif 3035 #endif
3039 memcpy(&descr, p_buff + RCV_BUFF_K_DESCR, sizeof(u32)); 3036 memcpy(&descr, p_buff + RCV_BUFF_K_DESCR, sizeof(u32));
3040 3037
3041 if (descr & PI_FMC_DESCR_M_RCC_FLUSH) 3038 if (descr & PI_FMC_DESCR_M_RCC_FLUSH)
3042 { 3039 {
3043 if (descr & PI_FMC_DESCR_M_RCC_CRC) 3040 if (descr & PI_FMC_DESCR_M_RCC_CRC)
3044 bp->rcv_crc_errors++; 3041 bp->rcv_crc_errors++;
3045 else 3042 else
3046 bp->rcv_frame_status_errors++; 3043 bp->rcv_frame_status_errors++;
3047 } 3044 }
3048 else 3045 else
3049 { 3046 {
3050 int rx_in_place = 0; 3047 int rx_in_place = 0;
3051 3048
3052 /* The frame was received without errors - verify packet length */ 3049 /* The frame was received without errors - verify packet length */
3053 3050
3054 pkt_len = (u32)((descr & PI_FMC_DESCR_M_LEN) >> PI_FMC_DESCR_V_LEN); 3051 pkt_len = (u32)((descr & PI_FMC_DESCR_M_LEN) >> PI_FMC_DESCR_V_LEN);
3055 pkt_len -= 4; /* subtract 4 byte CRC */ 3052 pkt_len -= 4; /* subtract 4 byte CRC */
3056 if (!IN_RANGE(pkt_len, FDDI_K_LLC_ZLEN, FDDI_K_LLC_LEN)) 3053 if (!IN_RANGE(pkt_len, FDDI_K_LLC_ZLEN, FDDI_K_LLC_LEN))
3057 bp->rcv_length_errors++; 3054 bp->rcv_length_errors++;
3058 else{ 3055 else{
3059 #ifdef DYNAMIC_BUFFERS 3056 #ifdef DYNAMIC_BUFFERS
3060 if (pkt_len > SKBUFF_RX_COPYBREAK) { 3057 if (pkt_len > SKBUFF_RX_COPYBREAK) {
3061 struct sk_buff *newskb; 3058 struct sk_buff *newskb;
3062 3059
3063 newskb = dev_alloc_skb(NEW_SKB_SIZE); 3060 newskb = dev_alloc_skb(NEW_SKB_SIZE);
3064 if (newskb){ 3061 if (newskb){
3065 rx_in_place = 1; 3062 rx_in_place = 1;
3066 3063
3067 my_skb_align(newskb, 128); 3064 my_skb_align(newskb, 128);
3068 skb = (struct sk_buff *)bp->p_rcv_buff_va[entry]; 3065 skb = (struct sk_buff *)bp->p_rcv_buff_va[entry];
3069 dma_unmap_single(bp->bus_dev, 3066 dma_unmap_single(bp->bus_dev,
3070 bp->descr_block_virt->rcv_data[entry].long_1, 3067 bp->descr_block_virt->rcv_data[entry].long_1,
3071 NEW_SKB_SIZE, 3068 NEW_SKB_SIZE,
3072 DMA_FROM_DEVICE); 3069 DMA_FROM_DEVICE);
3073 skb_reserve(skb, RCV_BUFF_K_PADDING); 3070 skb_reserve(skb, RCV_BUFF_K_PADDING);
3074 bp->p_rcv_buff_va[entry] = (char *)newskb; 3071 bp->p_rcv_buff_va[entry] = (char *)newskb;
3075 bp->descr_block_virt->rcv_data[entry].long_1 = 3072 bp->descr_block_virt->rcv_data[entry].long_1 =
3076 (u32)dma_map_single(bp->bus_dev, 3073 (u32)dma_map_single(bp->bus_dev,
3077 newskb->data, 3074 newskb->data,
3078 NEW_SKB_SIZE, 3075 NEW_SKB_SIZE,
3079 DMA_FROM_DEVICE); 3076 DMA_FROM_DEVICE);
3080 } else 3077 } else
3081 skb = NULL; 3078 skb = NULL;
3082 } else 3079 } else
3083 #endif 3080 #endif
3084 skb = dev_alloc_skb(pkt_len+3); /* alloc new buffer to pass up, add room for PRH */ 3081 skb = dev_alloc_skb(pkt_len+3); /* alloc new buffer to pass up, add room for PRH */
3085 if (skb == NULL) 3082 if (skb == NULL)
3086 { 3083 {
3087 printk("%s: Could not allocate receive buffer. Dropping packet.\n", bp->dev->name); 3084 printk("%s: Could not allocate receive buffer. Dropping packet.\n", bp->dev->name);
3088 bp->rcv_discards++; 3085 bp->rcv_discards++;
3089 break; 3086 break;
3090 } 3087 }
3091 else { 3088 else {
3092 #ifndef DYNAMIC_BUFFERS 3089 #ifndef DYNAMIC_BUFFERS
3093 if (! rx_in_place) 3090 if (! rx_in_place)
3094 #endif 3091 #endif
3095 { 3092 {
3096 /* Receive buffer allocated, pass receive packet up */ 3093 /* Receive buffer allocated, pass receive packet up */
3097 3094
3098 skb_copy_to_linear_data(skb, 3095 skb_copy_to_linear_data(skb,
3099 p_buff + RCV_BUFF_K_PADDING, 3096 p_buff + RCV_BUFF_K_PADDING,
3100 pkt_len + 3); 3097 pkt_len + 3);
3101 } 3098 }
3102 3099
3103 skb_reserve(skb,3); /* adjust data field so that it points to FC byte */ 3100 skb_reserve(skb,3); /* adjust data field so that it points to FC byte */
3104 skb_put(skb, pkt_len); /* pass up packet length, NOT including CRC */ 3101 skb_put(skb, pkt_len); /* pass up packet length, NOT including CRC */
3105 skb->protocol = fddi_type_trans(skb, bp->dev); 3102 skb->protocol = fddi_type_trans(skb, bp->dev);
3106 bp->rcv_total_bytes += skb->len; 3103 bp->rcv_total_bytes += skb->len;
3107 netif_rx(skb); 3104 netif_rx(skb);
3108 3105
3109 /* Update the rcv counters */ 3106 /* Update the rcv counters */
3110 bp->rcv_total_frames++; 3107 bp->rcv_total_frames++;
3111 if (*(p_buff + RCV_BUFF_K_DA) & 0x01) 3108 if (*(p_buff + RCV_BUFF_K_DA) & 0x01)
3112 bp->rcv_multicast_frames++; 3109 bp->rcv_multicast_frames++;
3113 } 3110 }
3114 } 3111 }
3115 } 3112 }
3116 3113
3117 /* 3114 /*
3118 * Advance the producer (for recycling) and advance the completion 3115 * Advance the producer (for recycling) and advance the completion
3119 * (for servicing received frames). Note that it is okay to 3116 * (for servicing received frames). Note that it is okay to
3120 * advance the producer without checking that it passes the 3117 * advance the producer without checking that it passes the
3121 * completion index because they are both advanced at the same 3118 * completion index because they are both advanced at the same
3122 * rate. 3119 * rate.
3123 */ 3120 */
3124 3121
3125 bp->rcv_xmt_reg.index.rcv_prod += 1; 3122 bp->rcv_xmt_reg.index.rcv_prod += 1;
3126 bp->rcv_xmt_reg.index.rcv_comp += 1; 3123 bp->rcv_xmt_reg.index.rcv_comp += 1;
3127 } 3124 }
3128 } 3125 }
3129 3126
3130 3127
3131 /* 3128 /*
3132 * ===================== 3129 * =====================
3133 * = dfx_xmt_queue_pkt = 3130 * = dfx_xmt_queue_pkt =
3134 * ===================== 3131 * =====================
3135 * 3132 *
3136 * Overview: 3133 * Overview:
3137 * Queues packets for transmission 3134 * Queues packets for transmission
3138 * 3135 *
3139 * Returns: 3136 * Returns:
3140 * Condition code 3137 * Condition code
3141 * 3138 *
3142 * Arguments: 3139 * Arguments:
3143 * skb - pointer to sk_buff to queue for transmission 3140 * skb - pointer to sk_buff to queue for transmission
3144 * dev - pointer to device information 3141 * dev - pointer to device information
3145 * 3142 *
3146 * Functional Description: 3143 * Functional Description:
3147 * Here we assume that an incoming skb transmit request 3144 * Here we assume that an incoming skb transmit request
3148 * is contained in a single physically contiguous buffer 3145 * is contained in a single physically contiguous buffer
3149 * in which the virtual address of the start of packet 3146 * in which the virtual address of the start of packet
3150 * (skb->data) can be converted to a physical address 3147 * (skb->data) can be converted to a physical address
3151 * by using pci_map_single(). 3148 * by using pci_map_single().
3152 * 3149 *
3153 * Since the adapter architecture requires a three byte 3150 * Since the adapter architecture requires a three byte
3154 * packet request header to prepend the start of packet, 3151 * packet request header to prepend the start of packet,
3155 * we'll write the three byte field immediately prior to 3152 * we'll write the three byte field immediately prior to
3156 * the FC byte. This assumption is valid because we've 3153 * the FC byte. This assumption is valid because we've
3157 * ensured that dev->hard_header_len includes three pad 3154 * ensured that dev->hard_header_len includes three pad
3158 * bytes. By posting a single fragment to the adapter, 3155 * bytes. By posting a single fragment to the adapter,
3159 * we'll reduce the number of descriptor fetches and 3156 * we'll reduce the number of descriptor fetches and
3160 * bus traffic needed to send the request. 3157 * bus traffic needed to send the request.
3161 * 3158 *
3162 * Also, we can't free the skb until after it's been DMA'd 3159 * Also, we can't free the skb until after it's been DMA'd
3163 * out by the adapter, so we'll queue it in the driver and 3160 * out by the adapter, so we'll queue it in the driver and
3164 * return it in dfx_xmt_done. 3161 * return it in dfx_xmt_done.
3165 * 3162 *
3166 * Return Codes: 3163 * Return Codes:
3167 * 0 - driver queued packet, link is unavailable, or skbuff was bad 3164 * 0 - driver queued packet, link is unavailable, or skbuff was bad
3168 * 1 - caller should requeue the sk_buff for later transmission 3165 * 1 - caller should requeue the sk_buff for later transmission
3169 * 3166 *
3170 * Assumptions: 3167 * Assumptions:
3171 * First and foremost, we assume the incoming skb pointer 3168 * First and foremost, we assume the incoming skb pointer
3172 * is NOT NULL and is pointing to a valid sk_buff structure. 3169 * is NOT NULL and is pointing to a valid sk_buff structure.
3173 * 3170 *
3174 * The outgoing packet is complete, starting with the 3171 * The outgoing packet is complete, starting with the
3175 * frame control byte including the last byte of data, 3172 * frame control byte including the last byte of data,
3176 * but NOT including the 4 byte CRC. We'll let the 3173 * but NOT including the 4 byte CRC. We'll let the
3177 * adapter hardware generate and append the CRC. 3174 * adapter hardware generate and append the CRC.
3178 * 3175 *
3179 * The entire packet is stored in one physically 3176 * The entire packet is stored in one physically
3180 * contiguous buffer which is not cached and whose 3177 * contiguous buffer which is not cached and whose
3181 * 32-bit physical address can be determined. 3178 * 32-bit physical address can be determined.
3182 * 3179 *
3183 * It's vital that this routine is NOT reentered for the 3180 * It's vital that this routine is NOT reentered for the
3184 * same board and that the OS is not in another section of 3181 * same board and that the OS is not in another section of
3185 * code (eg. dfx_int_common) for the same board on a 3182 * code (eg. dfx_int_common) for the same board on a
3186 * different thread. 3183 * different thread.
3187 * 3184 *
3188 * Side Effects: 3185 * Side Effects:
3189 * None 3186 * None
3190 */ 3187 */
3191 3188
3192 static netdev_tx_t dfx_xmt_queue_pkt(struct sk_buff *skb, 3189 static netdev_tx_t dfx_xmt_queue_pkt(struct sk_buff *skb,
3193 struct net_device *dev) 3190 struct net_device *dev)
3194 { 3191 {
3195 DFX_board_t *bp = netdev_priv(dev); 3192 DFX_board_t *bp = netdev_priv(dev);
3196 u8 prod; /* local transmit producer index */ 3193 u8 prod; /* local transmit producer index */
3197 PI_XMT_DESCR *p_xmt_descr; /* ptr to transmit descriptor block entry */ 3194 PI_XMT_DESCR *p_xmt_descr; /* ptr to transmit descriptor block entry */
3198 XMT_DRIVER_DESCR *p_xmt_drv_descr; /* ptr to transmit driver descriptor */ 3195 XMT_DRIVER_DESCR *p_xmt_drv_descr; /* ptr to transmit driver descriptor */
3199 unsigned long flags; 3196 unsigned long flags;
3200 3197
3201 netif_stop_queue(dev); 3198 netif_stop_queue(dev);
3202 3199
3203 /* 3200 /*
3204 * Verify that incoming transmit request is OK 3201 * Verify that incoming transmit request is OK
3205 * 3202 *
3206 * Note: The packet size check is consistent with other 3203 * Note: The packet size check is consistent with other
3207 * Linux device drivers, although the correct packet 3204 * Linux device drivers, although the correct packet
3208 * size should be verified before calling the 3205 * size should be verified before calling the
3209 * transmit routine. 3206 * transmit routine.
3210 */ 3207 */
3211 3208
3212 if (!IN_RANGE(skb->len, FDDI_K_LLC_ZLEN, FDDI_K_LLC_LEN)) 3209 if (!IN_RANGE(skb->len, FDDI_K_LLC_ZLEN, FDDI_K_LLC_LEN))
3213 { 3210 {
3214 printk("%s: Invalid packet length - %u bytes\n", 3211 printk("%s: Invalid packet length - %u bytes\n",
3215 dev->name, skb->len); 3212 dev->name, skb->len);
3216 bp->xmt_length_errors++; /* bump error counter */ 3213 bp->xmt_length_errors++; /* bump error counter */
3217 netif_wake_queue(dev); 3214 netif_wake_queue(dev);
3218 dev_kfree_skb(skb); 3215 dev_kfree_skb(skb);
3219 return NETDEV_TX_OK; /* return "success" */ 3216 return NETDEV_TX_OK; /* return "success" */
3220 } 3217 }
3221 /* 3218 /*
3222 * See if adapter link is available, if not, free buffer 3219 * See if adapter link is available, if not, free buffer
3223 * 3220 *
3224 * Note: If the link isn't available, free buffer and return 0 3221 * Note: If the link isn't available, free buffer and return 0
3225 * rather than tell the upper layer to requeue the packet. 3222 * rather than tell the upper layer to requeue the packet.
3226 * The methodology here is that by the time the link 3223 * The methodology here is that by the time the link
3227 * becomes available, the packet to be sent will be 3224 * becomes available, the packet to be sent will be
3228 * fairly stale. By simply dropping the packet, the 3225 * fairly stale. By simply dropping the packet, the
3229 * higher layer protocols will eventually time out 3226 * higher layer protocols will eventually time out
3230 * waiting for response packets which it won't receive. 3227 * waiting for response packets which it won't receive.
3231 */ 3228 */
3232 3229
3233 if (bp->link_available == PI_K_FALSE) 3230 if (bp->link_available == PI_K_FALSE)
3234 { 3231 {
3235 if (dfx_hw_adap_state_rd(bp) == PI_STATE_K_LINK_AVAIL) /* is link really available? */ 3232 if (dfx_hw_adap_state_rd(bp) == PI_STATE_K_LINK_AVAIL) /* is link really available? */
3236 bp->link_available = PI_K_TRUE; /* if so, set flag and continue */ 3233 bp->link_available = PI_K_TRUE; /* if so, set flag and continue */
3237 else 3234 else
3238 { 3235 {
3239 bp->xmt_discards++; /* bump error counter */ 3236 bp->xmt_discards++; /* bump error counter */
3240 dev_kfree_skb(skb); /* free sk_buff now */ 3237 dev_kfree_skb(skb); /* free sk_buff now */
3241 netif_wake_queue(dev); 3238 netif_wake_queue(dev);
3242 return NETDEV_TX_OK; /* return "success" */ 3239 return NETDEV_TX_OK; /* return "success" */
3243 } 3240 }
3244 } 3241 }
3245 3242
3246 spin_lock_irqsave(&bp->lock, flags); 3243 spin_lock_irqsave(&bp->lock, flags);
3247 3244
3248 /* Get the current producer and the next free xmt data descriptor */ 3245 /* Get the current producer and the next free xmt data descriptor */
3249 3246
3250 prod = bp->rcv_xmt_reg.index.xmt_prod; 3247 prod = bp->rcv_xmt_reg.index.xmt_prod;
3251 p_xmt_descr = &(bp->descr_block_virt->xmt_data[prod]); 3248 p_xmt_descr = &(bp->descr_block_virt->xmt_data[prod]);
3252 3249
3253 /* 3250 /*
3254 * Get pointer to auxiliary queue entry to contain information 3251 * Get pointer to auxiliary queue entry to contain information
3255 * for this packet. 3252 * for this packet.
3256 * 3253 *
3257 * Note: The current xmt producer index will become the 3254 * Note: The current xmt producer index will become the
3258 * current xmt completion index when we complete this 3255 * current xmt completion index when we complete this
3259 * packet later on. So, we'll get the pointer to the 3256 * packet later on. So, we'll get the pointer to the
3260 * next auxiliary queue entry now before we bump the 3257 * next auxiliary queue entry now before we bump the
3261 * producer index. 3258 * producer index.
3262 */ 3259 */
3263 3260
3264 p_xmt_drv_descr = &(bp->xmt_drv_descr_blk[prod++]); /* also bump producer index */ 3261 p_xmt_drv_descr = &(bp->xmt_drv_descr_blk[prod++]); /* also bump producer index */
3265 3262
3266 /* Write the three PRH bytes immediately before the FC byte */ 3263 /* Write the three PRH bytes immediately before the FC byte */
3267 3264
3268 skb_push(skb,3); 3265 skb_push(skb,3);
3269 skb->data[0] = DFX_PRH0_BYTE; /* these byte values are defined */ 3266 skb->data[0] = DFX_PRH0_BYTE; /* these byte values are defined */
3270 skb->data[1] = DFX_PRH1_BYTE; /* in the Motorola FDDI MAC chip */ 3267 skb->data[1] = DFX_PRH1_BYTE; /* in the Motorola FDDI MAC chip */
3271 skb->data[2] = DFX_PRH2_BYTE; /* specification */ 3268 skb->data[2] = DFX_PRH2_BYTE; /* specification */
3272 3269
3273 /* 3270 /*
3274 * Write the descriptor with buffer info and bump producer 3271 * Write the descriptor with buffer info and bump producer
3275 * 3272 *
3276 * Note: Since we need to start DMA from the packet request 3273 * Note: Since we need to start DMA from the packet request
3277 * header, we'll add 3 bytes to the DMA buffer length, 3274 * header, we'll add 3 bytes to the DMA buffer length,
3278 * and we'll determine the physical address of the 3275 * and we'll determine the physical address of the
3279 * buffer from the PRH, not skb->data. 3276 * buffer from the PRH, not skb->data.
3280 * 3277 *
3281 * Assumptions: 3278 * Assumptions:
3282 * 1. Packet starts with the frame control (FC) byte 3279 * 1. Packet starts with the frame control (FC) byte
3283 * at skb->data. 3280 * at skb->data.
3284 * 2. The 4-byte CRC is not appended to the buffer or 3281 * 2. The 4-byte CRC is not appended to the buffer or
3285 * included in the length. 3282 * included in the length.
3286 * 3. Packet length (skb->len) is from FC to end of 3283 * 3. Packet length (skb->len) is from FC to end of
3287 * data, inclusive. 3284 * data, inclusive.
3288 * 4. The packet length does not exceed the maximum 3285 * 4. The packet length does not exceed the maximum
3289 * FDDI LLC frame length of 4491 bytes. 3286 * FDDI LLC frame length of 4491 bytes.
3290 * 5. The entire packet is contained in a physically 3287 * 5. The entire packet is contained in a physically
3291 * contiguous, non-cached, locked memory space 3288 * contiguous, non-cached, locked memory space
3292 * comprised of a single buffer pointed to by 3289 * comprised of a single buffer pointed to by
3293 * skb->data. 3290 * skb->data.
3294 * 6. The physical address of the start of packet 3291 * 6. The physical address of the start of packet
3295 * can be determined from the virtual address 3292 * can be determined from the virtual address
3296 * by using pci_map_single() and is only 32-bits 3293 * by using pci_map_single() and is only 32-bits
3297 * wide. 3294 * wide.
3298 */ 3295 */
3299 3296
3300 p_xmt_descr->long_0 = (u32) (PI_XMT_DESCR_M_SOP | PI_XMT_DESCR_M_EOP | ((skb->len) << PI_XMT_DESCR_V_SEG_LEN)); 3297 p_xmt_descr->long_0 = (u32) (PI_XMT_DESCR_M_SOP | PI_XMT_DESCR_M_EOP | ((skb->len) << PI_XMT_DESCR_V_SEG_LEN));
3301 p_xmt_descr->long_1 = (u32)dma_map_single(bp->bus_dev, skb->data, 3298 p_xmt_descr->long_1 = (u32)dma_map_single(bp->bus_dev, skb->data,
3302 skb->len, DMA_TO_DEVICE); 3299 skb->len, DMA_TO_DEVICE);
3303 3300
3304 /* 3301 /*
3305 * Verify that descriptor is actually available 3302 * Verify that descriptor is actually available
3306 * 3303 *
3307 * Note: If descriptor isn't available, return 1 which tells 3304 * Note: If descriptor isn't available, return 1 which tells
3308 * the upper layer to requeue the packet for later 3305 * the upper layer to requeue the packet for later
3309 * transmission. 3306 * transmission.
3310 * 3307 *
3311 * We need to ensure that the producer never reaches the 3308 * We need to ensure that the producer never reaches the
3312 * completion, except to indicate that the queue is empty. 3309 * completion, except to indicate that the queue is empty.
3313 */ 3310 */
3314 3311
3315 if (prod == bp->rcv_xmt_reg.index.xmt_comp) 3312 if (prod == bp->rcv_xmt_reg.index.xmt_comp)
3316 { 3313 {
3317 skb_pull(skb,3); 3314 skb_pull(skb,3);
3318 spin_unlock_irqrestore(&bp->lock, flags); 3315 spin_unlock_irqrestore(&bp->lock, flags);
3319 return NETDEV_TX_BUSY; /* requeue packet for later */ 3316 return NETDEV_TX_BUSY; /* requeue packet for later */
3320 } 3317 }
3321 3318
3322 /* 3319 /*
3323 * Save info for this packet for xmt done indication routine 3320 * Save info for this packet for xmt done indication routine
3324 * 3321 *
3325 * Normally, we'd save the producer index in the p_xmt_drv_descr 3322 * Normally, we'd save the producer index in the p_xmt_drv_descr
3326 * structure so that we'd have it handy when we complete this 3323 * structure so that we'd have it handy when we complete this
3327 * packet later (in dfx_xmt_done). However, since the current 3324 * packet later (in dfx_xmt_done). However, since the current
3328 * transmit architecture guarantees a single fragment for the 3325 * transmit architecture guarantees a single fragment for the
3329 * entire packet, we can simply bump the completion index by 3326 * entire packet, we can simply bump the completion index by
3330 * one (1) for each completed packet. 3327 * one (1) for each completed packet.
3331 * 3328 *
3332 * Note: If this assumption changes and we're presented with 3329 * Note: If this assumption changes and we're presented with
3333 * an inconsistent number of transmit fragments for packet 3330 * an inconsistent number of transmit fragments for packet
3334 * data, we'll need to modify this code to save the current 3331 * data, we'll need to modify this code to save the current
3335 * transmit producer index. 3332 * transmit producer index.
3336 */ 3333 */
3337 3334
3338 p_xmt_drv_descr->p_skb = skb; 3335 p_xmt_drv_descr->p_skb = skb;
3339 3336
3340 /* Update Type 2 register */ 3337 /* Update Type 2 register */
3341 3338
3342 bp->rcv_xmt_reg.index.xmt_prod = prod; 3339 bp->rcv_xmt_reg.index.xmt_prod = prod;
3343 dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_2_PROD, bp->rcv_xmt_reg.lword); 3340 dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_2_PROD, bp->rcv_xmt_reg.lword);
3344 spin_unlock_irqrestore(&bp->lock, flags); 3341 spin_unlock_irqrestore(&bp->lock, flags);
3345 netif_wake_queue(dev); 3342 netif_wake_queue(dev);
3346 return NETDEV_TX_OK; /* packet queued to adapter */ 3343 return NETDEV_TX_OK; /* packet queued to adapter */
3347 } 3344 }
3348 3345
3349 3346
3350 /* 3347 /*
3351 * ================ 3348 * ================
3352 * = dfx_xmt_done = 3349 * = dfx_xmt_done =
3353 * ================ 3350 * ================
3354 * 3351 *
3355 * Overview: 3352 * Overview:
3356 * Processes all frames that have been transmitted. 3353 * Processes all frames that have been transmitted.
3357 * 3354 *
3358 * Returns: 3355 * Returns:
3359 * None 3356 * None
3360 * 3357 *
3361 * Arguments: 3358 * Arguments:
3362 * bp - pointer to board information 3359 * bp - pointer to board information
3363 * 3360 *
3364 * Functional Description: 3361 * Functional Description:
3365 * For all consumed transmit descriptors that have not 3362 * For all consumed transmit descriptors that have not
3366 * yet been completed, we'll free the skb we were holding 3363 * yet been completed, we'll free the skb we were holding
3367 * onto using dev_kfree_skb and bump the appropriate 3364 * onto using dev_kfree_skb and bump the appropriate
3368 * counters. 3365 * counters.
3369 * 3366 *
3370 * Return Codes: 3367 * Return Codes:
3371 * None 3368 * None
3372 * 3369 *
3373 * Assumptions: 3370 * Assumptions:
3374 * The Type 2 register is not updated in this routine. It is 3371 * The Type 2 register is not updated in this routine. It is
3375 * assumed that it will be updated in the ISR when dfx_xmt_done 3372 * assumed that it will be updated in the ISR when dfx_xmt_done
3376 * returns. 3373 * returns.
3377 * 3374 *
3378 * Side Effects: 3375 * Side Effects:
3379 * None 3376 * None
3380 */ 3377 */
3381 3378
3382 static int dfx_xmt_done(DFX_board_t *bp) 3379 static int dfx_xmt_done(DFX_board_t *bp)
3383 { 3380 {
3384 XMT_DRIVER_DESCR *p_xmt_drv_descr; /* ptr to transmit driver descriptor */ 3381 XMT_DRIVER_DESCR *p_xmt_drv_descr; /* ptr to transmit driver descriptor */
3385 PI_TYPE_2_CONSUMER *p_type_2_cons; /* ptr to rcv/xmt consumer block register */ 3382 PI_TYPE_2_CONSUMER *p_type_2_cons; /* ptr to rcv/xmt consumer block register */
3386 u8 comp; /* local transmit completion index */ 3383 u8 comp; /* local transmit completion index */
3387 int freed = 0; /* buffers freed */ 3384 int freed = 0; /* buffers freed */
3388 3385
3389 /* Service all consumed transmit frames */ 3386 /* Service all consumed transmit frames */
3390 3387
3391 p_type_2_cons = (PI_TYPE_2_CONSUMER *)(&bp->cons_block_virt->xmt_rcv_data); 3388 p_type_2_cons = (PI_TYPE_2_CONSUMER *)(&bp->cons_block_virt->xmt_rcv_data);
3392 while (bp->rcv_xmt_reg.index.xmt_comp != p_type_2_cons->index.xmt_cons) 3389 while (bp->rcv_xmt_reg.index.xmt_comp != p_type_2_cons->index.xmt_cons)
3393 { 3390 {
3394 /* Get pointer to the transmit driver descriptor block information */ 3391 /* Get pointer to the transmit driver descriptor block information */
3395 3392
3396 p_xmt_drv_descr = &(bp->xmt_drv_descr_blk[bp->rcv_xmt_reg.index.xmt_comp]); 3393 p_xmt_drv_descr = &(bp->xmt_drv_descr_blk[bp->rcv_xmt_reg.index.xmt_comp]);
3397 3394
3398 /* Increment transmit counters */ 3395 /* Increment transmit counters */
3399 3396
3400 bp->xmt_total_frames++; 3397 bp->xmt_total_frames++;
3401 bp->xmt_total_bytes += p_xmt_drv_descr->p_skb->len; 3398 bp->xmt_total_bytes += p_xmt_drv_descr->p_skb->len;
3402 3399
3403 /* Return skb to operating system */ 3400 /* Return skb to operating system */
3404 comp = bp->rcv_xmt_reg.index.xmt_comp; 3401 comp = bp->rcv_xmt_reg.index.xmt_comp;
3405 dma_unmap_single(bp->bus_dev, 3402 dma_unmap_single(bp->bus_dev,
3406 bp->descr_block_virt->xmt_data[comp].long_1, 3403 bp->descr_block_virt->xmt_data[comp].long_1,
3407 p_xmt_drv_descr->p_skb->len, 3404 p_xmt_drv_descr->p_skb->len,
3408 DMA_TO_DEVICE); 3405 DMA_TO_DEVICE);
3409 dev_kfree_skb_irq(p_xmt_drv_descr->p_skb); 3406 dev_kfree_skb_irq(p_xmt_drv_descr->p_skb);
3410 3407
3411 /* 3408 /*
3412 * Move to start of next packet by updating completion index 3409 * Move to start of next packet by updating completion index
3413 * 3410 *
3414 * Here we assume that a transmit packet request is always 3411 * Here we assume that a transmit packet request is always
3415 * serviced by posting one fragment. We can therefore 3412 * serviced by posting one fragment. We can therefore
3416 * simplify the completion code by incrementing the 3413 * simplify the completion code by incrementing the
3417 * completion index by one. This code will need to be 3414 * completion index by one. This code will need to be
3418 * modified if this assumption changes. See comments 3415 * modified if this assumption changes. See comments
3419 * in dfx_xmt_queue_pkt for more details. 3416 * in dfx_xmt_queue_pkt for more details.
3420 */ 3417 */
3421 3418
3422 bp->rcv_xmt_reg.index.xmt_comp += 1; 3419 bp->rcv_xmt_reg.index.xmt_comp += 1;
3423 freed++; 3420 freed++;
3424 } 3421 }
3425 return freed; 3422 return freed;
3426 } 3423 }
3427 3424
3428 3425
3429 /* 3426 /*
3430 * ================= 3427 * =================
3431 * = dfx_rcv_flush = 3428 * = dfx_rcv_flush =
3432 * ================= 3429 * =================
3433 * 3430 *
3434 * Overview: 3431 * Overview:
3435 * Remove all skb's in the receive ring. 3432 * Remove all skb's in the receive ring.
3436 * 3433 *
3437 * Returns: 3434 * Returns:
3438 * None 3435 * None
3439 * 3436 *
3440 * Arguments: 3437 * Arguments:
3441 * bp - pointer to board information 3438 * bp - pointer to board information
3442 * 3439 *
3443 * Functional Description: 3440 * Functional Description:
3444 * Free's all the dynamically allocated skb's that are 3441 * Free's all the dynamically allocated skb's that are
3445 * currently attached to the device receive ring. This 3442 * currently attached to the device receive ring. This
3446 * function is typically only used when the device is 3443 * function is typically only used when the device is
3447 * initialized or reinitialized. 3444 * initialized or reinitialized.
3448 * 3445 *
3449 * Return Codes: 3446 * Return Codes:
3450 * None 3447 * None
3451 * 3448 *
3452 * Side Effects: 3449 * Side Effects:
3453 * None 3450 * None
3454 */ 3451 */
3455 #ifdef DYNAMIC_BUFFERS 3452 #ifdef DYNAMIC_BUFFERS
3456 static void dfx_rcv_flush( DFX_board_t *bp ) 3453 static void dfx_rcv_flush( DFX_board_t *bp )
3457 { 3454 {
3458 int i, j; 3455 int i, j;
3459 3456
3460 for (i = 0; i < (int)(bp->rcv_bufs_to_post); i++) 3457 for (i = 0; i < (int)(bp->rcv_bufs_to_post); i++)
3461 for (j = 0; (i + j) < (int)PI_RCV_DATA_K_NUM_ENTRIES; j += bp->rcv_bufs_to_post) 3458 for (j = 0; (i + j) < (int)PI_RCV_DATA_K_NUM_ENTRIES; j += bp->rcv_bufs_to_post)
3462 { 3459 {
3463 struct sk_buff *skb; 3460 struct sk_buff *skb;
3464 skb = (struct sk_buff *)bp->p_rcv_buff_va[i+j]; 3461 skb = (struct sk_buff *)bp->p_rcv_buff_va[i+j];
3465 if (skb) 3462 if (skb)
3466 dev_kfree_skb(skb); 3463 dev_kfree_skb(skb);
3467 bp->p_rcv_buff_va[i+j] = NULL; 3464 bp->p_rcv_buff_va[i+j] = NULL;
3468 } 3465 }
3469 3466
3470 } 3467 }
3471 #else 3468 #else
3472 static inline void dfx_rcv_flush( DFX_board_t *bp ) 3469 static inline void dfx_rcv_flush( DFX_board_t *bp )
3473 { 3470 {
3474 } 3471 }
3475 #endif /* DYNAMIC_BUFFERS */ 3472 #endif /* DYNAMIC_BUFFERS */
3476 3473
3477 /* 3474 /*
3478 * ================= 3475 * =================
3479 * = dfx_xmt_flush = 3476 * = dfx_xmt_flush =
3480 * ================= 3477 * =================
3481 * 3478 *
3482 * Overview: 3479 * Overview:
3483 * Processes all frames whether they've been transmitted 3480 * Processes all frames whether they've been transmitted
3484 * or not. 3481 * or not.
3485 * 3482 *
3486 * Returns: 3483 * Returns:
3487 * None 3484 * None
3488 * 3485 *
3489 * Arguments: 3486 * Arguments:
3490 * bp - pointer to board information 3487 * bp - pointer to board information
3491 * 3488 *
3492 * Functional Description: 3489 * Functional Description:
3493 * For all produced transmit descriptors that have not 3490 * For all produced transmit descriptors that have not
3494 * yet been completed, we'll free the skb we were holding 3491 * yet been completed, we'll free the skb we were holding
3495 * onto using dev_kfree_skb and bump the appropriate 3492 * onto using dev_kfree_skb and bump the appropriate
3496 * counters. Of course, it's possible that some of 3493 * counters. Of course, it's possible that some of
3497 * these transmit requests actually did go out, but we 3494 * these transmit requests actually did go out, but we
3498 * won't make that distinction here. Finally, we'll 3495 * won't make that distinction here. Finally, we'll
3499 * update the consumer index to match the producer. 3496 * update the consumer index to match the producer.
3500 * 3497 *
3501 * Return Codes: 3498 * Return Codes:
3502 * None 3499 * None
3503 * 3500 *
3504 * Assumptions: 3501 * Assumptions:
3505 * This routine does NOT update the Type 2 register. It 3502 * This routine does NOT update the Type 2 register. It
3506 * is assumed that this routine is being called during a 3503 * is assumed that this routine is being called during a
3507 * transmit flush interrupt, or a shutdown or close routine. 3504 * transmit flush interrupt, or a shutdown or close routine.
3508 * 3505 *
3509 * Side Effects: 3506 * Side Effects:
3510 * None 3507 * None
3511 */ 3508 */
3512 3509
3513 static void dfx_xmt_flush( DFX_board_t *bp ) 3510 static void dfx_xmt_flush( DFX_board_t *bp )
3514 { 3511 {
3515 u32 prod_cons; /* rcv/xmt consumer block longword */ 3512 u32 prod_cons; /* rcv/xmt consumer block longword */
3516 XMT_DRIVER_DESCR *p_xmt_drv_descr; /* ptr to transmit driver descriptor */ 3513 XMT_DRIVER_DESCR *p_xmt_drv_descr; /* ptr to transmit driver descriptor */
3517 u8 comp; /* local transmit completion index */ 3514 u8 comp; /* local transmit completion index */
3518 3515
3519 /* Flush all outstanding transmit frames */ 3516 /* Flush all outstanding transmit frames */
3520 3517
3521 while (bp->rcv_xmt_reg.index.xmt_comp != bp->rcv_xmt_reg.index.xmt_prod) 3518 while (bp->rcv_xmt_reg.index.xmt_comp != bp->rcv_xmt_reg.index.xmt_prod)
3522 { 3519 {
3523 /* Get pointer to the transmit driver descriptor block information */ 3520 /* Get pointer to the transmit driver descriptor block information */
3524 3521
3525 p_xmt_drv_descr = &(bp->xmt_drv_descr_blk[bp->rcv_xmt_reg.index.xmt_comp]); 3522 p_xmt_drv_descr = &(bp->xmt_drv_descr_blk[bp->rcv_xmt_reg.index.xmt_comp]);
3526 3523
3527 /* Return skb to operating system */ 3524 /* Return skb to operating system */
3528 comp = bp->rcv_xmt_reg.index.xmt_comp; 3525 comp = bp->rcv_xmt_reg.index.xmt_comp;
3529 dma_unmap_single(bp->bus_dev, 3526 dma_unmap_single(bp->bus_dev,
3530 bp->descr_block_virt->xmt_data[comp].long_1, 3527 bp->descr_block_virt->xmt_data[comp].long_1,
3531 p_xmt_drv_descr->p_skb->len, 3528 p_xmt_drv_descr->p_skb->len,
3532 DMA_TO_DEVICE); 3529 DMA_TO_DEVICE);
3533 dev_kfree_skb(p_xmt_drv_descr->p_skb); 3530 dev_kfree_skb(p_xmt_drv_descr->p_skb);
3534 3531
3535 /* Increment transmit error counter */ 3532 /* Increment transmit error counter */
3536 3533
3537 bp->xmt_discards++; 3534 bp->xmt_discards++;
3538 3535
3539 /* 3536 /*
3540 * Move to start of next packet by updating completion index 3537 * Move to start of next packet by updating completion index
3541 * 3538 *
3542 * Here we assume that a transmit packet request is always 3539 * Here we assume that a transmit packet request is always
3543 * serviced by posting one fragment. We can therefore 3540 * serviced by posting one fragment. We can therefore
3544 * simplify the completion code by incrementing the 3541 * simplify the completion code by incrementing the
3545 * completion index by one. This code will need to be 3542 * completion index by one. This code will need to be
3546 * modified if this assumption changes. See comments 3543 * modified if this assumption changes. See comments
3547 * in dfx_xmt_queue_pkt for more details. 3544 * in dfx_xmt_queue_pkt for more details.
3548 */ 3545 */
3549 3546
3550 bp->rcv_xmt_reg.index.xmt_comp += 1; 3547 bp->rcv_xmt_reg.index.xmt_comp += 1;
3551 } 3548 }
3552 3549
3553 /* Update the transmit consumer index in the consumer block */ 3550 /* Update the transmit consumer index in the consumer block */
3554 3551
3555 prod_cons = (u32)(bp->cons_block_virt->xmt_rcv_data & ~PI_CONS_M_XMT_INDEX); 3552 prod_cons = (u32)(bp->cons_block_virt->xmt_rcv_data & ~PI_CONS_M_XMT_INDEX);
3556 prod_cons |= (u32)(bp->rcv_xmt_reg.index.xmt_prod << PI_CONS_V_XMT_INDEX); 3553 prod_cons |= (u32)(bp->rcv_xmt_reg.index.xmt_prod << PI_CONS_V_XMT_INDEX);
3557 bp->cons_block_virt->xmt_rcv_data = prod_cons; 3554 bp->cons_block_virt->xmt_rcv_data = prod_cons;
3558 } 3555 }
3559 3556
3560 /* 3557 /*
3561 * ================== 3558 * ==================
3562 * = dfx_unregister = 3559 * = dfx_unregister =
3563 * ================== 3560 * ==================
3564 * 3561 *
3565 * Overview: 3562 * Overview:
3566 * Shuts down an FDDI controller 3563 * Shuts down an FDDI controller
3567 * 3564 *
3568 * Returns: 3565 * Returns:
3569 * Condition code 3566 * Condition code
3570 * 3567 *
3571 * Arguments: 3568 * Arguments:
3572 * bdev - pointer to device information 3569 * bdev - pointer to device information
3573 * 3570 *
3574 * Functional Description: 3571 * Functional Description:
3575 * 3572 *
3576 * Return Codes: 3573 * Return Codes:
3577 * None 3574 * None
3578 * 3575 *
3579 * Assumptions: 3576 * Assumptions:
3580 * It compiles so it should work :-( (PCI cards do :-) 3577 * It compiles so it should work :-( (PCI cards do :-)
3581 * 3578 *
3582 * Side Effects: 3579 * Side Effects:
3583 * Device structures for FDDI adapters (fddi0, fddi1, etc) are 3580 * Device structures for FDDI adapters (fddi0, fddi1, etc) are
3584 * freed. 3581 * freed.
3585 */ 3582 */
3586 static void __devexit dfx_unregister(struct device *bdev) 3583 static void __devexit dfx_unregister(struct device *bdev)
3587 { 3584 {
3588 struct net_device *dev = dev_get_drvdata(bdev); 3585 struct net_device *dev = dev_get_drvdata(bdev);
3589 DFX_board_t *bp = netdev_priv(dev); 3586 DFX_board_t *bp = netdev_priv(dev);
3590 int dfx_bus_pci = DFX_BUS_PCI(bdev); 3587 int dfx_bus_pci = DFX_BUS_PCI(bdev);
3591 int dfx_bus_tc = DFX_BUS_TC(bdev); 3588 int dfx_bus_tc = DFX_BUS_TC(bdev);
3592 int dfx_use_mmio = DFX_MMIO || dfx_bus_tc; 3589 int dfx_use_mmio = DFX_MMIO || dfx_bus_tc;
3593 resource_size_t bar_start = 0; /* pointer to port */ 3590 resource_size_t bar_start = 0; /* pointer to port */
3594 resource_size_t bar_len = 0; /* resource length */ 3591 resource_size_t bar_len = 0; /* resource length */
3595 int alloc_size; /* total buffer size used */ 3592 int alloc_size; /* total buffer size used */
3596 3593
3597 unregister_netdev(dev); 3594 unregister_netdev(dev);
3598 3595
3599 alloc_size = sizeof(PI_DESCR_BLOCK) + 3596 alloc_size = sizeof(PI_DESCR_BLOCK) +
3600 PI_CMD_REQ_K_SIZE_MAX + PI_CMD_RSP_K_SIZE_MAX + 3597 PI_CMD_REQ_K_SIZE_MAX + PI_CMD_RSP_K_SIZE_MAX +
3601 #ifndef DYNAMIC_BUFFERS 3598 #ifndef DYNAMIC_BUFFERS
3602 (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX) + 3599 (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX) +
3603 #endif 3600 #endif
3604 sizeof(PI_CONSUMER_BLOCK) + 3601 sizeof(PI_CONSUMER_BLOCK) +
3605 (PI_ALIGN_K_DESC_BLK - 1); 3602 (PI_ALIGN_K_DESC_BLK - 1);
3606 if (bp->kmalloced) 3603 if (bp->kmalloced)
3607 dma_free_coherent(bdev, alloc_size, 3604 dma_free_coherent(bdev, alloc_size,
3608 bp->kmalloced, bp->kmalloced_dma); 3605 bp->kmalloced, bp->kmalloced_dma);
3609 3606
3610 dfx_bus_uninit(dev); 3607 dfx_bus_uninit(dev);
3611 3608
3612 dfx_get_bars(bdev, &bar_start, &bar_len); 3609 dfx_get_bars(bdev, &bar_start, &bar_len);
3613 if (dfx_use_mmio) { 3610 if (dfx_use_mmio) {
3614 iounmap(bp->base.mem); 3611 iounmap(bp->base.mem);
3615 release_mem_region(bar_start, bar_len); 3612 release_mem_region(bar_start, bar_len);
3616 } else 3613 } else
3617 release_region(bar_start, bar_len); 3614 release_region(bar_start, bar_len);
3618 3615
3619 if (dfx_bus_pci) 3616 if (dfx_bus_pci)
3620 pci_disable_device(to_pci_dev(bdev)); 3617 pci_disable_device(to_pci_dev(bdev));
3621 3618
3622 free_netdev(dev); 3619 free_netdev(dev);
3623 } 3620 }
3624 3621
3625 3622
3626 static int __devinit __maybe_unused dfx_dev_register(struct device *); 3623 static int __devinit __maybe_unused dfx_dev_register(struct device *);
3627 static int __devexit __maybe_unused dfx_dev_unregister(struct device *); 3624 static int __devexit __maybe_unused dfx_dev_unregister(struct device *);
3628 3625
3629 #ifdef CONFIG_PCI 3626 #ifdef CONFIG_PCI
3630 static int __devinit dfx_pci_register(struct pci_dev *, 3627 static int __devinit dfx_pci_register(struct pci_dev *,
3631 const struct pci_device_id *); 3628 const struct pci_device_id *);
3632 static void __devexit dfx_pci_unregister(struct pci_dev *); 3629 static void __devexit dfx_pci_unregister(struct pci_dev *);
3633 3630
3634 static struct pci_device_id dfx_pci_table[] = { 3631 static struct pci_device_id dfx_pci_table[] = {
3635 { PCI_DEVICE(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_FDDI) }, 3632 { PCI_DEVICE(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_FDDI) },
3636 { } 3633 { }
3637 }; 3634 };
3638 MODULE_DEVICE_TABLE(pci, dfx_pci_table); 3635 MODULE_DEVICE_TABLE(pci, dfx_pci_table);
3639 3636
3640 static struct pci_driver dfx_pci_driver = { 3637 static struct pci_driver dfx_pci_driver = {
3641 .name = "defxx", 3638 .name = "defxx",
3642 .id_table = dfx_pci_table, 3639 .id_table = dfx_pci_table,
3643 .probe = dfx_pci_register, 3640 .probe = dfx_pci_register,
3644 .remove = __devexit_p(dfx_pci_unregister), 3641 .remove = __devexit_p(dfx_pci_unregister),
3645 }; 3642 };
3646 3643
3647 static __devinit int dfx_pci_register(struct pci_dev *pdev, 3644 static __devinit int dfx_pci_register(struct pci_dev *pdev,
3648 const struct pci_device_id *ent) 3645 const struct pci_device_id *ent)
3649 { 3646 {
3650 return dfx_register(&pdev->dev); 3647 return dfx_register(&pdev->dev);
3651 } 3648 }
3652 3649
3653 static void __devexit dfx_pci_unregister(struct pci_dev *pdev) 3650 static void __devexit dfx_pci_unregister(struct pci_dev *pdev)
3654 { 3651 {
3655 dfx_unregister(&pdev->dev); 3652 dfx_unregister(&pdev->dev);
3656 } 3653 }
3657 #endif /* CONFIG_PCI */ 3654 #endif /* CONFIG_PCI */
3658 3655
3659 #ifdef CONFIG_EISA 3656 #ifdef CONFIG_EISA
3660 static struct eisa_device_id dfx_eisa_table[] = { 3657 static struct eisa_device_id dfx_eisa_table[] = {
3661 { "DEC3001", DEFEA_PROD_ID_1 }, 3658 { "DEC3001", DEFEA_PROD_ID_1 },
3662 { "DEC3002", DEFEA_PROD_ID_2 }, 3659 { "DEC3002", DEFEA_PROD_ID_2 },
3663 { "DEC3003", DEFEA_PROD_ID_3 }, 3660 { "DEC3003", DEFEA_PROD_ID_3 },
3664 { "DEC3004", DEFEA_PROD_ID_4 }, 3661 { "DEC3004", DEFEA_PROD_ID_4 },
3665 { } 3662 { }
3666 }; 3663 };
3667 MODULE_DEVICE_TABLE(eisa, dfx_eisa_table); 3664 MODULE_DEVICE_TABLE(eisa, dfx_eisa_table);
3668 3665
3669 static struct eisa_driver dfx_eisa_driver = { 3666 static struct eisa_driver dfx_eisa_driver = {
3670 .id_table = dfx_eisa_table, 3667 .id_table = dfx_eisa_table,
3671 .driver = { 3668 .driver = {
3672 .name = "defxx", 3669 .name = "defxx",
3673 .bus = &eisa_bus_type, 3670 .bus = &eisa_bus_type,
3674 .probe = dfx_dev_register, 3671 .probe = dfx_dev_register,
3675 .remove = __devexit_p(dfx_dev_unregister), 3672 .remove = __devexit_p(dfx_dev_unregister),
3676 }, 3673 },
3677 }; 3674 };
3678 #endif /* CONFIG_EISA */ 3675 #endif /* CONFIG_EISA */
3679 3676
3680 #ifdef CONFIG_TC 3677 #ifdef CONFIG_TC
3681 static struct tc_device_id const dfx_tc_table[] = { 3678 static struct tc_device_id const dfx_tc_table[] = {
3682 { "DEC ", "PMAF-FA " }, 3679 { "DEC ", "PMAF-FA " },
3683 { "DEC ", "PMAF-FD " }, 3680 { "DEC ", "PMAF-FD " },
3684 { "DEC ", "PMAF-FS " }, 3681 { "DEC ", "PMAF-FS " },
3685 { "DEC ", "PMAF-FU " }, 3682 { "DEC ", "PMAF-FU " },
3686 { } 3683 { }
3687 }; 3684 };
3688 MODULE_DEVICE_TABLE(tc, dfx_tc_table); 3685 MODULE_DEVICE_TABLE(tc, dfx_tc_table);
3689 3686
3690 static struct tc_driver dfx_tc_driver = { 3687 static struct tc_driver dfx_tc_driver = {
3691 .id_table = dfx_tc_table, 3688 .id_table = dfx_tc_table,
3692 .driver = { 3689 .driver = {
3693 .name = "defxx", 3690 .name = "defxx",
3694 .bus = &tc_bus_type, 3691 .bus = &tc_bus_type,
3695 .probe = dfx_dev_register, 3692 .probe = dfx_dev_register,
3696 .remove = __devexit_p(dfx_dev_unregister), 3693 .remove = __devexit_p(dfx_dev_unregister),
3697 }, 3694 },
3698 }; 3695 };
3699 #endif /* CONFIG_TC */ 3696 #endif /* CONFIG_TC */
3700 3697
3701 static int __devinit __maybe_unused dfx_dev_register(struct device *dev) 3698 static int __devinit __maybe_unused dfx_dev_register(struct device *dev)
3702 { 3699 {
3703 int status; 3700 int status;
3704 3701
3705 status = dfx_register(dev); 3702 status = dfx_register(dev);
3706 if (!status) 3703 if (!status)
3707 get_device(dev); 3704 get_device(dev);
3708 return status; 3705 return status;
3709 } 3706 }
3710 3707
3711 static int __devexit __maybe_unused dfx_dev_unregister(struct device *dev) 3708 static int __devexit __maybe_unused dfx_dev_unregister(struct device *dev)
3712 { 3709 {
3713 put_device(dev); 3710 put_device(dev);
3714 dfx_unregister(dev); 3711 dfx_unregister(dev);
3715 return 0; 3712 return 0;
3716 } 3713 }
3717 3714
3718 3715
3719 static int __devinit dfx_init(void) 3716 static int __devinit dfx_init(void)
3720 { 3717 {
3721 int status; 3718 int status;
3722 3719
3723 status = pci_register_driver(&dfx_pci_driver); 3720 status = pci_register_driver(&dfx_pci_driver);
3724 if (!status) 3721 if (!status)
3725 status = eisa_driver_register(&dfx_eisa_driver); 3722 status = eisa_driver_register(&dfx_eisa_driver);
3726 if (!status) 3723 if (!status)
3727 status = tc_register_driver(&dfx_tc_driver); 3724 status = tc_register_driver(&dfx_tc_driver);
3728 return status; 3725 return status;
3729 } 3726 }
3730 3727
3731 static void __devexit dfx_cleanup(void) 3728 static void __devexit dfx_cleanup(void)
3732 { 3729 {
3733 tc_unregister_driver(&dfx_tc_driver); 3730 tc_unregister_driver(&dfx_tc_driver);
3734 eisa_driver_unregister(&dfx_eisa_driver); 3731 eisa_driver_unregister(&dfx_eisa_driver);
3735 pci_unregister_driver(&dfx_pci_driver); 3732 pci_unregister_driver(&dfx_pci_driver);
3736 } 3733 }
3737 3734
3738 module_init(dfx_init); 3735 module_init(dfx_init);
3739 module_exit(dfx_cleanup); 3736 module_exit(dfx_cleanup);
3740 MODULE_AUTHOR("Lawrence V. Stefani"); 3737 MODULE_AUTHOR("Lawrence V. Stefani");
3741 MODULE_DESCRIPTION("DEC FDDIcontroller TC/EISA/PCI (DEFTA/DEFEA/DEFPA) driver " 3738 MODULE_DESCRIPTION("DEC FDDIcontroller TC/EISA/PCI (DEFTA/DEFEA/DEFPA) driver "
3742 DRV_VERSION " " DRV_RELDATE); 3739 DRV_VERSION " " DRV_RELDATE);
3743 MODULE_LICENSE("GPL"); 3740 MODULE_LICENSE("GPL");
3744 3741