Eric Lee / linux-smarc-t335x-v3.2

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/*

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/*

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*

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*

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* This program is free software; you can redistribute it and/or modify

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* This program is free software; you can redistribute it and/or modify

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* it under the terms of the GNU General Public License as published by

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* it under the terms of the GNU General Public License as published by

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* the Free Software Foundation; either version 2 of the License, or

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* the Free Software Foundation; either version 2 of the License, or

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* (at your option) any later version.

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* (at your option) any later version.

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*

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*

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* This program is distributed in the hope that it will be useful,

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* This program is distributed in the hope that it will be useful,

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* but WITHOUT ANY WARRANTY; without even the implied warranty of

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* but WITHOUT ANY WARRANTY; without even the implied warranty of

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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

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* GNU General Public License for more details.

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* GNU General Public License for more details.

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*

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*

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* You should have received a copy of the GNU General Public License

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* You should have received a copy of the GNU General Public License

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* along with this program; if not, write to the Free Software

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* along with this program; if not, write to the Free Software

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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.

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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.

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*/

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*/

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#include <linux/init.h>

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#include <linux/init.h>

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#include <linux/module.h>

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#include <linux/module.h>

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#include <linux/device.h>

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#include <linux/device.h>

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#include <linux/ioport.h>

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#include <linux/ioport.h>

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#include <linux/errno.h>

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#include <linux/errno.h>

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#include <linux/interrupt.h>

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#include <linux/interrupt.h>

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#include <linux/platform_device.h>

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#include <linux/platform_device.h>

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#include <linux/dma-mapping.h>

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#include <linux/dma-mapping.h>

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#include <linux/spi/spi.h>

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#include <linux/spi/spi.h>

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#include <linux/workqueue.h>

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#include <linux/workqueue.h>

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#include <linux/errno.h>

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#include <linux/errno.h>

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#include <linux/delay.h>

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#include <linux/delay.h>

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#include <asm/io.h>

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#include <asm/io.h>

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#include <asm/irq.h>

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#include <asm/irq.h>

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#include <asm/hardware.h>

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#include <asm/hardware.h>

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#include <asm/delay.h>

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#include <asm/delay.h>

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#include <asm/dma.h>

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#include <asm/dma.h>

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#include <asm/arch/hardware.h>

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#include <asm/arch/hardware.h>

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#include <asm/arch/pxa-regs.h>

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#include <asm/arch/pxa-regs.h>

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#include <asm/arch/pxa2xx_spi.h>

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#include <asm/arch/pxa2xx_spi.h>

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MODULE_AUTHOR("Stephen Street");

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MODULE_AUTHOR("Stephen Street");

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MODULE_DESCRIPTION("PXA2xx SSP SPI Contoller");

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MODULE_DESCRIPTION("PXA2xx SSP SPI Contoller");

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MODULE_LICENSE("GPL");

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MODULE_LICENSE("GPL");

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#define MAX_BUSES 3

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#define MAX_BUSES 3

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#define DMA_INT_MASK (DCSR_ENDINTR | DCSR_STARTINTR | DCSR_BUSERR)

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#define DMA_INT_MASK (DCSR_ENDINTR | DCSR_STARTINTR | DCSR_BUSERR)

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#define RESET_DMA_CHANNEL (DCSR_NODESC | DMA_INT_MASK)

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#define RESET_DMA_CHANNEL (DCSR_NODESC | DMA_INT_MASK)

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#define IS_DMA_ALIGNED(x) (((u32)(x)&0x07)==0)

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#define IS_DMA_ALIGNED(x) (((u32)(x)&0x07)==0)

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/* for testing SSCR1 changes that require SSP restart, basically

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/* for testing SSCR1 changes that require SSP restart, basically

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* everything except the service and interrupt enables */

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* everything except the service and interrupt enables */

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#define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_EBCEI | SSCR1_SCFR \

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#define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_EBCEI | SSCR1_SCFR \

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| SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \

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| SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \

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| SSCR1_RWOT | SSCR1_TRAIL | SSCR1_PINTE \

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| SSCR1_RWOT | SSCR1_TRAIL | SSCR1_PINTE \

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| SSCR1_STRF | SSCR1_EFWR |SSCR1_RFT \

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| SSCR1_STRF | SSCR1_EFWR |SSCR1_RFT \

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| SSCR1_TFT | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)

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| SSCR1_TFT | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)

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#define DEFINE_SSP_REG(reg, off) \

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#define DEFINE_SSP_REG(reg, off) \

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static inline u32 read_##reg(void *p) { return __raw_readl(p + (off)); } \

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static inline u32 read_##reg(void *p) { return __raw_readl(p + (off)); } \

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static inline void write_##reg(u32 v, void *p) { __raw_writel(v, p + (off)); }

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static inline void write_##reg(u32 v, void *p) { __raw_writel(v, p + (off)); }

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DEFINE_SSP_REG(SSCR0, 0x00)

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DEFINE_SSP_REG(SSCR0, 0x00)

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DEFINE_SSP_REG(SSCR1, 0x04)

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DEFINE_SSP_REG(SSCR1, 0x04)

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DEFINE_SSP_REG(SSSR, 0x08)

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DEFINE_SSP_REG(SSSR, 0x08)

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DEFINE_SSP_REG(SSITR, 0x0c)

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DEFINE_SSP_REG(SSITR, 0x0c)

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DEFINE_SSP_REG(SSDR, 0x10)

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DEFINE_SSP_REG(SSDR, 0x10)

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DEFINE_SSP_REG(SSTO, 0x28)

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DEFINE_SSP_REG(SSTO, 0x28)

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DEFINE_SSP_REG(SSPSP, 0x2c)

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DEFINE_SSP_REG(SSPSP, 0x2c)

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#define START_STATE ((void*)0)

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#define START_STATE ((void*)0)

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#define RUNNING_STATE ((void*)1)

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#define RUNNING_STATE ((void*)1)

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#define DONE_STATE ((void*)2)

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#define DONE_STATE ((void*)2)

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#define ERROR_STATE ((void*)-1)

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#define ERROR_STATE ((void*)-1)

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#define QUEUE_RUNNING 0

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#define QUEUE_RUNNING 0

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#define QUEUE_STOPPED 1

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#define QUEUE_STOPPED 1

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struct driver_data {

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struct driver_data {

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/* Driver model hookup */

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/* Driver model hookup */

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struct platform_device *pdev;

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struct platform_device *pdev;

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/* SPI framework hookup */

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/* SPI framework hookup */

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enum pxa_ssp_type ssp_type;

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enum pxa_ssp_type ssp_type;

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struct spi_master *master;

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struct spi_master *master;

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/* PXA hookup */

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/* PXA hookup */

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struct pxa2xx_spi_master *master_info;

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struct pxa2xx_spi_master *master_info;

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/* DMA setup stuff */

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/* DMA setup stuff */

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int rx_channel;

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int rx_channel;

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int tx_channel;

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int tx_channel;

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u32 *null_dma_buf;

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u32 *null_dma_buf;

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/* SSP register addresses */

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/* SSP register addresses */

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void *ioaddr;

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void *ioaddr;

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u32 ssdr_physical;

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u32 ssdr_physical;

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/* SSP masks*/

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/* SSP masks*/

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u32 dma_cr1;

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u32 dma_cr1;

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u32 int_cr1;

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u32 int_cr1;

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u32 clear_sr;

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u32 clear_sr;

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u32 mask_sr;

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u32 mask_sr;

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/* Driver message queue */

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/* Driver message queue */

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struct workqueue_struct *workqueue;

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struct workqueue_struct *workqueue;

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struct work_struct pump_messages;

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struct work_struct pump_messages;

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spinlock_t lock;

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spinlock_t lock;

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struct list_head queue;

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struct list_head queue;

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int busy;

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int busy;

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int run;

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int run;

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/* Message Transfer pump */

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/* Message Transfer pump */

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struct tasklet_struct pump_transfers;

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struct tasklet_struct pump_transfers;

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/* Current message transfer state info */

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/* Current message transfer state info */

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struct spi_message* cur_msg;

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struct spi_message* cur_msg;

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struct spi_transfer* cur_transfer;

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struct spi_transfer* cur_transfer;

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struct chip_data *cur_chip;

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struct chip_data *cur_chip;

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size_t len;

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size_t len;

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void *tx;

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void *tx;

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void *tx_end;

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void *tx_end;

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void *rx;

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void *rx;

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void *rx_end;

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void *rx_end;

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int dma_mapped;

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int dma_mapped;

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dma_addr_t rx_dma;

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dma_addr_t rx_dma;

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dma_addr_t tx_dma;

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dma_addr_t tx_dma;

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size_t rx_map_len;

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size_t rx_map_len;

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size_t tx_map_len;

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size_t tx_map_len;

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u8 n_bytes;

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u8 n_bytes;

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u32 dma_width;

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u32 dma_width;

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int cs_change;

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int cs_change;

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int (*write)(struct driver_data *drv_data);

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int (*write)(struct driver_data *drv_data);

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int (*read)(struct driver_data *drv_data);

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int (*read)(struct driver_data *drv_data);

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irqreturn_t (*transfer_handler)(struct driver_data *drv_data);

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irqreturn_t (*transfer_handler)(struct driver_data *drv_data);

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void (*cs_control)(u32 command);

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void (*cs_control)(u32 command);

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};

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};

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struct chip_data {

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struct chip_data {

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u32 cr0;

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u32 cr0;

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u32 cr1;

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u32 cr1;

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u32 psp;

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u32 psp;

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u32 timeout;

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u32 timeout;

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u8 n_bytes;

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u8 n_bytes;

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u32 dma_width;

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u32 dma_width;

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u32 dma_burst_size;

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u32 dma_burst_size;

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u32 threshold;

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u32 threshold;

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u32 dma_threshold;

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u32 dma_threshold;

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u8 enable_dma;

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u8 enable_dma;

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u8 bits_per_word;

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u8 bits_per_word;

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u32 speed_hz;

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u32 speed_hz;

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int (*write)(struct driver_data *drv_data);

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int (*write)(struct driver_data *drv_data);

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int (*read)(struct driver_data *drv_data);

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int (*read)(struct driver_data *drv_data);

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void (*cs_control)(u32 command);

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void (*cs_control)(u32 command);

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};

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};

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static void pump_messages(struct work_struct *work);

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static void pump_messages(struct work_struct *work);

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static int flush(struct driver_data *drv_data)

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static int flush(struct driver_data *drv_data)

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{

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{

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unsigned long limit = loops_per_jiffy << 1;

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unsigned long limit = loops_per_jiffy << 1;

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void *reg = drv_data->ioaddr;

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void *reg = drv_data->ioaddr;

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do {

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do {

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while (read_SSSR(reg) & SSSR_RNE) {

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while (read_SSSR(reg) & SSSR_RNE) {

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read_SSDR(reg);

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read_SSDR(reg);

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}

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}

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} while ((read_SSSR(reg) & SSSR_BSY) && limit--);

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} while ((read_SSSR(reg) & SSSR_BSY) && limit--);

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write_SSSR(SSSR_ROR, reg);

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write_SSSR(SSSR_ROR, reg);

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return limit;

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return limit;

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}

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}

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static void null_cs_control(u32 command)

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static void null_cs_control(u32 command)

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{

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{

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}

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}

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static int null_writer(struct driver_data *drv_data)

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static int null_writer(struct driver_data *drv_data)

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{

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{

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void *reg = drv_data->ioaddr;

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void *reg = drv_data->ioaddr;

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u8 n_bytes = drv_data->n_bytes;

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u8 n_bytes = drv_data->n_bytes;

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if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00)

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if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00)

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|| (drv_data->tx == drv_data->tx_end))

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|| (drv_data->tx == drv_data->tx_end))

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return 0;

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return 0;

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write_SSDR(0, reg);

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write_SSDR(0, reg);

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drv_data->tx += n_bytes;

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drv_data->tx += n_bytes;

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return 1;

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return 1;

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}

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}

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static int null_reader(struct driver_data *drv_data)

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static int null_reader(struct driver_data *drv_data)

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{

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{

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void *reg = drv_data->ioaddr;

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void *reg = drv_data->ioaddr;

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u8 n_bytes = drv_data->n_bytes;

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u8 n_bytes = drv_data->n_bytes;

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while ((read_SSSR(reg) & SSSR_RNE)

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while ((read_SSSR(reg) & SSSR_RNE)

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&& (drv_data->rx < drv_data->rx_end)) {

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&& (drv_data->rx < drv_data->rx_end)) {

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read_SSDR(reg);

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read_SSDR(reg);

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drv_data->rx += n_bytes;

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drv_data->rx += n_bytes;

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}

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}

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return drv_data->rx == drv_data->rx_end;

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return drv_data->rx == drv_data->rx_end;

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}

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}

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static int u8_writer(struct driver_data *drv_data)

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static int u8_writer(struct driver_data *drv_data)

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{

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{

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void *reg = drv_data->ioaddr;

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void *reg = drv_data->ioaddr;

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if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00)

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if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00)

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|| (drv_data->tx == drv_data->tx_end))

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|| (drv_data->tx == drv_data->tx_end))

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return 0;

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return 0;

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write_SSDR(*(u8 *)(drv_data->tx), reg);

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write_SSDR(*(u8 *)(drv_data->tx), reg);

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++drv_data->tx;

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++drv_data->tx;

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return 1;

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return 1;

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}

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}

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static int u8_reader(struct driver_data *drv_data)

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static int u8_reader(struct driver_data *drv_data)

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{

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{

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void *reg = drv_data->ioaddr;

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void *reg = drv_data->ioaddr;

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while ((read_SSSR(reg) & SSSR_RNE)

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while ((read_SSSR(reg) & SSSR_RNE)

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&& (drv_data->rx < drv_data->rx_end)) {

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&& (drv_data->rx < drv_data->rx_end)) {

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*(u8 *)(drv_data->rx) = read_SSDR(reg);

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*(u8 *)(drv_data->rx) = read_SSDR(reg);

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++drv_data->rx;

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++drv_data->rx;

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}

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}

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return drv_data->rx == drv_data->rx_end;

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return drv_data->rx == drv_data->rx_end;

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}

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}

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static int u16_writer(struct driver_data *drv_data)

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static int u16_writer(struct driver_data *drv_data)

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{

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{

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void *reg = drv_data->ioaddr;

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void *reg = drv_data->ioaddr;

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if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00)

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if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00)

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|| (drv_data->tx == drv_data->tx_end))

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|| (drv_data->tx == drv_data->tx_end))

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return 0;

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return 0;

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write_SSDR(*(u16 *)(drv_data->tx), reg);

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write_SSDR(*(u16 *)(drv_data->tx), reg);

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drv_data->tx += 2;

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drv_data->tx += 2;

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return 1;

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return 1;

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}

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}

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static int u16_reader(struct driver_data *drv_data)

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static int u16_reader(struct driver_data *drv_data)

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{

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{

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void *reg = drv_data->ioaddr;

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void *reg = drv_data->ioaddr;

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while ((read_SSSR(reg) & SSSR_RNE)

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while ((read_SSSR(reg) & SSSR_RNE)

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&& (drv_data->rx < drv_data->rx_end)) {

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&& (drv_data->rx < drv_data->rx_end)) {

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*(u16 *)(drv_data->rx) = read_SSDR(reg);

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*(u16 *)(drv_data->rx) = read_SSDR(reg);

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drv_data->rx += 2;

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drv_data->rx += 2;

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}

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}

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return drv_data->rx == drv_data->rx_end;

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return drv_data->rx == drv_data->rx_end;

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}

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}

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static int u32_writer(struct driver_data *drv_data)

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static int u32_writer(struct driver_data *drv_data)

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{

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{

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void *reg = drv_data->ioaddr;

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void *reg = drv_data->ioaddr;

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if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00)

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if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00)

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|| (drv_data->tx == drv_data->tx_end))

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|| (drv_data->tx == drv_data->tx_end))

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return 0;

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return 0;

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write_SSDR(*(u32 *)(drv_data->tx), reg);

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write_SSDR(*(u32 *)(drv_data->tx), reg);

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drv_data->tx += 4;

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drv_data->tx += 4;

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return 1;

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return 1;

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}

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}

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static int u32_reader(struct driver_data *drv_data)

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static int u32_reader(struct driver_data *drv_data)

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{

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{

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void *reg = drv_data->ioaddr;

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void *reg = drv_data->ioaddr;

280

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while ((read_SSSR(reg) & SSSR_RNE)

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while ((read_SSSR(reg) & SSSR_RNE)

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&& (drv_data->rx < drv_data->rx_end)) {

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&& (drv_data->rx < drv_data->rx_end)) {

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*(u32 *)(drv_data->rx) = read_SSDR(reg);

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*(u32 *)(drv_data->rx) = read_SSDR(reg);

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drv_data->rx += 4;

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drv_data->rx += 4;

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}

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}

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return drv_data->rx == drv_data->rx_end;

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return drv_data->rx == drv_data->rx_end;

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}

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}

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static void *next_transfer(struct driver_data *drv_data)

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static void *next_transfer(struct driver_data *drv_data)

291

{

291

{

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struct spi_message *msg = drv_data->cur_msg;

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struct spi_message *msg = drv_data->cur_msg;

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struct spi_transfer *trans = drv_data->cur_transfer;

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struct spi_transfer *trans = drv_data->cur_transfer;

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/* Move to next transfer */

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/* Move to next transfer */

296

if (trans->transfer_list.next != &msg->transfers) {

296

if (trans->transfer_list.next != &msg->transfers) {

297

drv_data->cur_transfer =

297

drv_data->cur_transfer =

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list_entry(trans->transfer_list.next,

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list_entry(trans->transfer_list.next,

299

struct spi_transfer,

299

struct spi_transfer,

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transfer_list);

300

transfer_list);

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return RUNNING_STATE;

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return RUNNING_STATE;

302

} else

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} else

303

return DONE_STATE;

303

return DONE_STATE;

304

}

304

}

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static int map_dma_buffers(struct driver_data *drv_data)

306

static int map_dma_buffers(struct driver_data *drv_data)

307

{

307

{

308

struct spi_message *msg = drv_data->cur_msg;

308

struct spi_message *msg = drv_data->cur_msg;

309

struct device *dev = &msg->spi->dev;

309

struct device *dev = &msg->spi->dev;

310

311

if (!drv_data->cur_chip->enable_dma)

311

if (!drv_data->cur_chip->enable_dma)

312

return 0;

312

return 0;

313

314

if (msg->is_dma_mapped)

314

if (msg->is_dma_mapped)

315

return drv_data->rx_dma && drv_data->tx_dma;

315

return drv_data->rx_dma && drv_data->tx_dma;

316

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if (!IS_DMA_ALIGNED(drv_data->rx) || !IS_DMA_ALIGNED(drv_data->tx))

317

if (!IS_DMA_ALIGNED(drv_data->rx) || !IS_DMA_ALIGNED(drv_data->tx))

318

return 0;

318

return 0;

319

320

/* Modify setup if rx buffer is null */

320

/* Modify setup if rx buffer is null */

321

if (drv_data->rx == NULL) {

321

if (drv_data->rx == NULL) {

322

*drv_data->null_dma_buf = 0;

322

*drv_data->null_dma_buf = 0;

323

drv_data->rx = drv_data->null_dma_buf;

323

drv_data->rx = drv_data->null_dma_buf;

324

drv_data->rx_map_len = 4;

324

drv_data->rx_map_len = 4;

325

} else

325

} else

326

drv_data->rx_map_len = drv_data->len;

326

drv_data->rx_map_len = drv_data->len;

327

328

329

/* Modify setup if tx buffer is null */

329

/* Modify setup if tx buffer is null */

330

if (drv_data->tx == NULL) {

330

if (drv_data->tx == NULL) {

331

*drv_data->null_dma_buf = 0;

331

*drv_data->null_dma_buf = 0;

332

drv_data->tx = drv_data->null_dma_buf;

332

drv_data->tx = drv_data->null_dma_buf;

333

drv_data->tx_map_len = 4;

333

drv_data->tx_map_len = 4;

334

} else

334

} else

335

drv_data->tx_map_len = drv_data->len;

335

drv_data->tx_map_len = drv_data->len;

336

337

/* Stream map the rx buffer */

337

/* Stream map the rx buffer */

338

drv_data->rx_dma = dma_map_single(dev, drv_data->rx,

338

drv_data->rx_dma = dma_map_single(dev, drv_data->rx,

339

drv_data->rx_map_len,

339

drv_data->rx_map_len,

340

DMA_FROM_DEVICE);

340

DMA_FROM_DEVICE);

341

if (dma_mapping_error(drv_data->rx_dma))

341

if (dma_mapping_error(drv_data->rx_dma))

342

return 0;

342

return 0;

343

344

/* Stream map the tx buffer */

344

/* Stream map the tx buffer */

345

drv_data->tx_dma = dma_map_single(dev, drv_data->tx,

345

drv_data->tx_dma = dma_map_single(dev, drv_data->tx,

346

drv_data->tx_map_len,

346

drv_data->tx_map_len,

347

DMA_TO_DEVICE);

347

DMA_TO_DEVICE);

348

349

if (dma_mapping_error(drv_data->tx_dma)) {

349

if (dma_mapping_error(drv_data->tx_dma)) {

350

dma_unmap_single(dev, drv_data->rx_dma,

350

dma_unmap_single(dev, drv_data->rx_dma,

351

drv_data->rx_map_len, DMA_FROM_DEVICE);

351

drv_data->rx_map_len, DMA_FROM_DEVICE);

352

return 0;

352

return 0;

353

}

353

}

354

355

return 1;

355

return 1;

356

}

356

}

357

358

static void unmap_dma_buffers(struct driver_data *drv_data)

358

static void unmap_dma_buffers(struct driver_data *drv_data)

359

{

359

{

360

struct device *dev;

360

struct device *dev;

361

362

if (!drv_data->dma_mapped)

362

if (!drv_data->dma_mapped)

363

return;

363

return;

364

365

if (!drv_data->cur_msg->is_dma_mapped) {

365

if (!drv_data->cur_msg->is_dma_mapped) {

366

dev = &drv_data->cur_msg->spi->dev;

366

dev = &drv_data->cur_msg->spi->dev;

367

dma_unmap_single(dev, drv_data->rx_dma,

367

dma_unmap_single(dev, drv_data->rx_dma,

368

drv_data->rx_map_len, DMA_FROM_DEVICE);

368

drv_data->rx_map_len, DMA_FROM_DEVICE);

369

dma_unmap_single(dev, drv_data->tx_dma,

369

dma_unmap_single(dev, drv_data->tx_dma,

370

drv_data->tx_map_len, DMA_TO_DEVICE);

370

drv_data->tx_map_len, DMA_TO_DEVICE);

371

}

371

}

372

373

drv_data->dma_mapped = 0;

373

drv_data->dma_mapped = 0;

374

}

374

}

375

376

/* caller already set message->status; dma and pio irqs are blocked */

376

/* caller already set message->status; dma and pio irqs are blocked */

377

static void giveback(struct driver_data *drv_data)

377

static void giveback(struct driver_data *drv_data)

378

{

378

{

379

struct spi_transfer* last_transfer;

379

struct spi_transfer* last_transfer;

380

unsigned long flags;

380

unsigned long flags;

381

struct spi_message *msg;

381

struct spi_message *msg;

382

383

spin_lock_irqsave(&drv_data->lock, flags);

383

spin_lock_irqsave(&drv_data->lock, flags);

384

msg = drv_data->cur_msg;

384

msg = drv_data->cur_msg;

385

drv_data->cur_msg = NULL;

385

drv_data->cur_msg = NULL;

386

drv_data->cur_transfer = NULL;

386

drv_data->cur_transfer = NULL;

387

drv_data->cur_chip = NULL;

387

drv_data->cur_chip = NULL;

388

queue_work(drv_data->workqueue, &drv_data->pump_messages);

388

queue_work(drv_data->workqueue, &drv_data->pump_messages);

389

spin_unlock_irqrestore(&drv_data->lock, flags);

389

spin_unlock_irqrestore(&drv_data->lock, flags);

390

391

last_transfer = list_entry(msg->transfers.prev,

391

last_transfer = list_entry(msg->transfers.prev,

392

struct spi_transfer,

392

struct spi_transfer,

393

transfer_list);

393

transfer_list);

394

395

if (!last_transfer->cs_change)

395

if (!last_transfer->cs_change)

396

drv_data->cs_control(PXA2XX_CS_DEASSERT);

396

drv_data->cs_control(PXA2XX_CS_DEASSERT);

397

398

msg->state = NULL;

398

msg->state = NULL;

399

if (msg->complete)

399

if (msg->complete)

400

msg->complete(msg->context);

400

msg->complete(msg->context);

401

}

401

}

402

403

static int wait_ssp_rx_stall(void *ioaddr)

403

static int wait_ssp_rx_stall(void *ioaddr)

404

{

404

{

405

unsigned long limit = loops_per_jiffy << 1;

405

unsigned long limit = loops_per_jiffy << 1;

406

407

while ((read_SSSR(ioaddr) & SSSR_BSY) && limit--)

407

while ((read_SSSR(ioaddr) & SSSR_BSY) && limit--)

408

cpu_relax();

408

cpu_relax();

409

410

return limit;

410

return limit;

411

}

411

}

412

413

static int wait_dma_channel_stop(int channel)

413

static int wait_dma_channel_stop(int channel)

414

{

414

{

415

unsigned long limit = loops_per_jiffy << 1;

415

unsigned long limit = loops_per_jiffy << 1;

416

417

while (!(DCSR(channel) & DCSR_STOPSTATE) && limit--)

417

while (!(DCSR(channel) & DCSR_STOPSTATE) && limit--)

418

cpu_relax();

418

cpu_relax();

419

420

return limit;

420

return limit;

421

}

421

}

422

423

void dma_error_stop(struct driver_data *drv_data, const char *msg)

423

void dma_error_stop(struct driver_data *drv_data, const char *msg)

424

{

424

{

425

void *reg = drv_data->ioaddr;

425

void *reg = drv_data->ioaddr;

426

427

/* Stop and reset */

427

/* Stop and reset */

428

DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;

428

DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;

429

DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;

429

DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;

430

write_SSSR(drv_data->clear_sr, reg);

430

write_SSSR(drv_data->clear_sr, reg);

431

write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg);

431

write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg);

432

if (drv_data->ssp_type != PXA25x_SSP)

432

if (drv_data->ssp_type != PXA25x_SSP)

433

write_SSTO(0, reg);

433

write_SSTO(0, reg);

434

flush(drv_data);

434

flush(drv_data);

435

write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);

435

write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);

436

437

unmap_dma_buffers(drv_data);

437

unmap_dma_buffers(drv_data);

438

439

dev_err(&drv_data->pdev->dev, "%s\n", msg);

439

dev_err(&drv_data->pdev->dev, "%s\n", msg);

440

441

drv_data->cur_msg->state = ERROR_STATE;

441

drv_data->cur_msg->state = ERROR_STATE;

442

tasklet_schedule(&drv_data->pump_transfers);

442

tasklet_schedule(&drv_data->pump_transfers);

443

}

443

}

444

445

static void dma_transfer_complete(struct driver_data *drv_data)

445

static void dma_transfer_complete(struct driver_data *drv_data)

446

{

446

{

447

void *reg = drv_data->ioaddr;

447

void *reg = drv_data->ioaddr;

448

struct spi_message *msg = drv_data->cur_msg;

448

struct spi_message *msg = drv_data->cur_msg;

449

450

/* Clear and disable interrupts on SSP and DMA channels*/

450

/* Clear and disable interrupts on SSP and DMA channels*/

451

write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg);

451

write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg);

452

write_SSSR(drv_data->clear_sr, reg);

452

write_SSSR(drv_data->clear_sr, reg);

453

DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;

453

DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;

454

DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;

454

DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;

455

456

if (wait_dma_channel_stop(drv_data->rx_channel) == 0)

456

if (wait_dma_channel_stop(drv_data->rx_channel) == 0)

457

dev_err(&drv_data->pdev->dev,

457

dev_err(&drv_data->pdev->dev,

458

"dma_handler: dma rx channel stop failed\n");

458

"dma_handler: dma rx channel stop failed\n");

459

460

if (wait_ssp_rx_stall(drv_data->ioaddr) == 0)

460

if (wait_ssp_rx_stall(drv_data->ioaddr) == 0)

461

dev_err(&drv_data->pdev->dev,

461

dev_err(&drv_data->pdev->dev,

462

"dma_transfer: ssp rx stall failed\n");

462

"dma_transfer: ssp rx stall failed\n");

463

464

unmap_dma_buffers(drv_data);

464

unmap_dma_buffers(drv_data);

465

466

/* update the buffer pointer for the amount completed in dma */

466

/* update the buffer pointer for the amount completed in dma */

467

drv_data->rx += drv_data->len -

467

drv_data->rx += drv_data->len -

468

(DCMD(drv_data->rx_channel) & DCMD_LENGTH);

468

(DCMD(drv_data->rx_channel) & DCMD_LENGTH);

469

470

/* read trailing data from fifo, it does not matter how many

470

/* read trailing data from fifo, it does not matter how many

471

* bytes are in the fifo just read until buffer is full

471

* bytes are in the fifo just read until buffer is full

472

* or fifo is empty, which ever occurs first */

472

* or fifo is empty, which ever occurs first */

473

drv_data->read(drv_data);

473

drv_data->read(drv_data);

474

475

/* return count of what was actually read */

475

/* return count of what was actually read */

476

msg->actual_length += drv_data->len -

476

msg->actual_length += drv_data->len -

477

(drv_data->rx_end - drv_data->rx);

477

(drv_data->rx_end - drv_data->rx);

478

479

/* Release chip select if requested, transfer delays are

479

/* Release chip select if requested, transfer delays are

480

* handled in pump_transfers */

480

* handled in pump_transfers */

481

if (drv_data->cs_change)

481

if (drv_data->cs_change)

482

drv_data->cs_control(PXA2XX_CS_DEASSERT);

482

drv_data->cs_control(PXA2XX_CS_DEASSERT);

483

484

/* Move to next transfer */

484

/* Move to next transfer */

485

msg->state = next_transfer(drv_data);

485

msg->state = next_transfer(drv_data);

486

487

/* Schedule transfer tasklet */

487

/* Schedule transfer tasklet */

488

tasklet_schedule(&drv_data->pump_transfers);

488

tasklet_schedule(&drv_data->pump_transfers);

489

}

489

}

490

491

static void dma_handler(int channel, void *data)

491

static void dma_handler(int channel, void *data)

492

{

492

{

493

struct driver_data *drv_data = data;

493

struct driver_data *drv_data = data;

494

u32 irq_status = DCSR(channel) & DMA_INT_MASK;

494

u32 irq_status = DCSR(channel) & DMA_INT_MASK;

495

496

if (irq_status & DCSR_BUSERR) {

496

if (irq_status & DCSR_BUSERR) {

497

498

if (channel == drv_data->tx_channel)

498

if (channel == drv_data->tx_channel)

499

dma_error_stop(drv_data,

499

dma_error_stop(drv_data,

500

"dma_handler: "

500

"dma_handler: "

501

"bad bus address on tx channel");

501

"bad bus address on tx channel");

502

else

502

else

503

dma_error_stop(drv_data,

503

dma_error_stop(drv_data,

504

"dma_handler: "

504

"dma_handler: "

505

"bad bus address on rx channel");

505

"bad bus address on rx channel");

506

return;

506

return;

507

}

507

}

508

509

/* PXA255x_SSP has no timeout interrupt, wait for tailing bytes */

509

/* PXA255x_SSP has no timeout interrupt, wait for tailing bytes */

510

if ((channel == drv_data->tx_channel)

510

if ((channel == drv_data->tx_channel)

511

&& (irq_status & DCSR_ENDINTR)

511

&& (irq_status & DCSR_ENDINTR)

512

&& (drv_data->ssp_type == PXA25x_SSP)) {

512

&& (drv_data->ssp_type == PXA25x_SSP)) {

513

514

/* Wait for rx to stall */

514

/* Wait for rx to stall */

515

if (wait_ssp_rx_stall(drv_data->ioaddr) == 0)

515

if (wait_ssp_rx_stall(drv_data->ioaddr) == 0)

516

dev_err(&drv_data->pdev->dev,

516

dev_err(&drv_data->pdev->dev,

517

"dma_handler: ssp rx stall failed\n");

517

"dma_handler: ssp rx stall failed\n");

518

519

/* finish this transfer, start the next */

519

/* finish this transfer, start the next */

520

dma_transfer_complete(drv_data);

520

dma_transfer_complete(drv_data);

521

}

521

}

522

}

522

}

523

524

static irqreturn_t dma_transfer(struct driver_data *drv_data)

524

static irqreturn_t dma_transfer(struct driver_data *drv_data)

525

{

525

{

526

u32 irq_status;

526

u32 irq_status;

527

void *reg = drv_data->ioaddr;

527

void *reg = drv_data->ioaddr;

528

529

irq_status = read_SSSR(reg) & drv_data->mask_sr;

529

irq_status = read_SSSR(reg) & drv_data->mask_sr;

530

if (irq_status & SSSR_ROR) {

530

if (irq_status & SSSR_ROR) {

531

dma_error_stop(drv_data, "dma_transfer: fifo overrun");

531

dma_error_stop(drv_data, "dma_transfer: fifo overrun");

532

return IRQ_HANDLED;

532

return IRQ_HANDLED;

533

}

533

}

534

535

/* Check for false positive timeout */

535

/* Check for false positive timeout */

536

if ((irq_status & SSSR_TINT)

536

if ((irq_status & SSSR_TINT)

537

&& (DCSR(drv_data->tx_channel) & DCSR_RUN)) {

537

&& (DCSR(drv_data->tx_channel) & DCSR_RUN)) {

538

write_SSSR(SSSR_TINT, reg);

538

write_SSSR(SSSR_TINT, reg);

539

return IRQ_HANDLED;

539

return IRQ_HANDLED;

540

}

540

}

541

542

if (irq_status & SSSR_TINT || drv_data->rx == drv_data->rx_end) {

542

if (irq_status & SSSR_TINT || drv_data->rx == drv_data->rx_end) {

543

544

/* Clear and disable timeout interrupt, do the rest in

544

/* Clear and disable timeout interrupt, do the rest in

545

* dma_transfer_complete */

545

* dma_transfer_complete */

546

if (drv_data->ssp_type != PXA25x_SSP)

546

if (drv_data->ssp_type != PXA25x_SSP)

547

write_SSTO(0, reg);

547

write_SSTO(0, reg);

548

549

/* finish this transfer, start the next */

549

/* finish this transfer, start the next */

550

dma_transfer_complete(drv_data);

550

dma_transfer_complete(drv_data);

551

552

return IRQ_HANDLED;

552

return IRQ_HANDLED;

553

}

553

}

554

555

/* Opps problem detected */

555

/* Opps problem detected */

556

return IRQ_NONE;

556

return IRQ_NONE;

557

}

557

}

558

559

static void int_error_stop(struct driver_data *drv_data, const char* msg)

559

static void int_error_stop(struct driver_data *drv_data, const char* msg)

560

{

560

{

561

void *reg = drv_data->ioaddr;

561

void *reg = drv_data->ioaddr;

562

563

/* Stop and reset SSP */

563

/* Stop and reset SSP */

564

write_SSSR(drv_data->clear_sr, reg);

564

write_SSSR(drv_data->clear_sr, reg);

565

write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);

565

write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);

566

if (drv_data->ssp_type != PXA25x_SSP)

566

if (drv_data->ssp_type != PXA25x_SSP)

567

write_SSTO(0, reg);

567

write_SSTO(0, reg);

568

flush(drv_data);

568

flush(drv_data);

569

write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);

569

write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);

570

571

dev_err(&drv_data->pdev->dev, "%s\n", msg);

571

dev_err(&drv_data->pdev->dev, "%s\n", msg);

572

573

drv_data->cur_msg->state = ERROR_STATE;

573

drv_data->cur_msg->state = ERROR_STATE;

574

tasklet_schedule(&drv_data->pump_transfers);

574

tasklet_schedule(&drv_data->pump_transfers);

575

}

575

}

576

577

static void int_transfer_complete(struct driver_data *drv_data)

577

static void int_transfer_complete(struct driver_data *drv_data)

578

{

578

{

579

void *reg = drv_data->ioaddr;

579

void *reg = drv_data->ioaddr;

580

581

/* Stop SSP */

581

/* Stop SSP */

582

write_SSSR(drv_data->clear_sr, reg);

582

write_SSSR(drv_data->clear_sr, reg);

583

write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);

583

write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);

584

if (drv_data->ssp_type != PXA25x_SSP)

584

if (drv_data->ssp_type != PXA25x_SSP)

585

write_SSTO(0, reg);

585

write_SSTO(0, reg);

586

587

/* Update total byte transfered return count actual bytes read */

587

/* Update total byte transfered return count actual bytes read */

588

drv_data->cur_msg->actual_length += drv_data->len -

588

drv_data->cur_msg->actual_length += drv_data->len -

589

(drv_data->rx_end - drv_data->rx);

589

(drv_data->rx_end - drv_data->rx);

590

591

/* Release chip select if requested, transfer delays are

591

/* Release chip select if requested, transfer delays are

592

* handled in pump_transfers */

592

* handled in pump_transfers */

593

if (drv_data->cs_change)

593

if (drv_data->cs_change)

594

drv_data->cs_control(PXA2XX_CS_DEASSERT);

594

drv_data->cs_control(PXA2XX_CS_DEASSERT);

595

596

/* Move to next transfer */

596

/* Move to next transfer */

597

drv_data->cur_msg->state = next_transfer(drv_data);

597

drv_data->cur_msg->state = next_transfer(drv_data);

598

599

/* Schedule transfer tasklet */

599

/* Schedule transfer tasklet */

600

tasklet_schedule(&drv_data->pump_transfers);

600

tasklet_schedule(&drv_data->pump_transfers);

601

}

601

}

602

603

static irqreturn_t interrupt_transfer(struct driver_data *drv_data)

603

static irqreturn_t interrupt_transfer(struct driver_data *drv_data)

604

{

604

{

605

void *reg = drv_data->ioaddr;

605

void *reg = drv_data->ioaddr;

606

607

u32 irq_mask = (read_SSCR1(reg) & SSCR1_TIE) ?

607

u32 irq_mask = (read_SSCR1(reg) & SSCR1_TIE) ?

608

drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;

608

drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;

609

610

u32 irq_status = read_SSSR(reg) & irq_mask;

610

u32 irq_status = read_SSSR(reg) & irq_mask;

611

612

if (irq_status & SSSR_ROR) {

612

if (irq_status & SSSR_ROR) {

613

int_error_stop(drv_data, "interrupt_transfer: fifo overrun");

613

int_error_stop(drv_data, "interrupt_transfer: fifo overrun");

614

return IRQ_HANDLED;

614

return IRQ_HANDLED;

615

}

615

}

616

617

if (irq_status & SSSR_TINT) {

617

if (irq_status & SSSR_TINT) {

618

write_SSSR(SSSR_TINT, reg);

618

write_SSSR(SSSR_TINT, reg);

619

if (drv_data->read(drv_data)) {

619

if (drv_data->read(drv_data)) {

620

int_transfer_complete(drv_data);

620

int_transfer_complete(drv_data);

621

return IRQ_HANDLED;

621

return IRQ_HANDLED;

622

}

622

}

623

}

623

}

624

625

/* Drain rx fifo, Fill tx fifo and prevent overruns */

625

/* Drain rx fifo, Fill tx fifo and prevent overruns */

626

do {

626

do {

627

if (drv_data->read(drv_data)) {

627

if (drv_data->read(drv_data)) {

628

int_transfer_complete(drv_data);

628

int_transfer_complete(drv_data);

629

return IRQ_HANDLED;

629

return IRQ_HANDLED;

630

}

630

}

631

} while (drv_data->write(drv_data));

631

} while (drv_data->write(drv_data));

632

633

if (drv_data->read(drv_data)) {

633

if (drv_data->read(drv_data)) {

634

int_transfer_complete(drv_data);

634

int_transfer_complete(drv_data);

635

return IRQ_HANDLED;

635

return IRQ_HANDLED;

636

}

636

}

637

638

if (drv_data->tx == drv_data->tx_end) {

638

if (drv_data->tx == drv_data->tx_end) {

639

write_SSCR1(read_SSCR1(reg) & ~SSCR1_TIE, reg);

639

write_SSCR1(read_SSCR1(reg) & ~SSCR1_TIE, reg);

640

/* PXA25x_SSP has no timeout, read trailing bytes */

640

/* PXA25x_SSP has no timeout, read trailing bytes */

641

if (drv_data->ssp_type == PXA25x_SSP) {

641

if (drv_data->ssp_type == PXA25x_SSP) {

642

if (!wait_ssp_rx_stall(reg))

642

if (!wait_ssp_rx_stall(reg))

643

{

643

{

644

int_error_stop(drv_data, "interrupt_transfer: "

644

int_error_stop(drv_data, "interrupt_transfer: "

645

"rx stall failed");

645

"rx stall failed");

646

return IRQ_HANDLED;

646

return IRQ_HANDLED;

647

}

647

}

648

if (!drv_data->read(drv_data))

648

if (!drv_data->read(drv_data))

649

{

649

{

650

int_error_stop(drv_data,

650

int_error_stop(drv_data,

651

"interrupt_transfer: "

651

"interrupt_transfer: "

652

"trailing byte read failed");

652

"trailing byte read failed");

653

return IRQ_HANDLED;

653

return IRQ_HANDLED;

654

}

654

}

655

int_transfer_complete(drv_data);

655

int_transfer_complete(drv_data);

656

}

656

}

657

}

657

}

658

659

/* We did something */

659

/* We did something */

660

return IRQ_HANDLED;

660

return IRQ_HANDLED;

661

}

661

}

662

663

static irqreturn_t ssp_int(int irq, void *dev_id)

663

static irqreturn_t ssp_int(int irq, void *dev_id)

664

{

664

{

665

struct driver_data *drv_data = dev_id;

665

struct driver_data *drv_data = dev_id;

666

void *reg = drv_data->ioaddr;

666

void *reg = drv_data->ioaddr;

667

668

if (!drv_data->cur_msg) {

668

if (!drv_data->cur_msg) {

669

670

write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);

670

write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);

671

write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);

671

write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);

672

if (drv_data->ssp_type != PXA25x_SSP)

672

if (drv_data->ssp_type != PXA25x_SSP)

673

write_SSTO(0, reg);

673

write_SSTO(0, reg);

674

write_SSSR(drv_data->clear_sr, reg);

674

write_SSSR(drv_data->clear_sr, reg);

675

676

dev_err(&drv_data->pdev->dev, "bad message state "

676

dev_err(&drv_data->pdev->dev, "bad message state "

677

"in interrupt handler\n");

677

"in interrupt handler\n");

678

679

/* Never fail */

679

/* Never fail */

680

return IRQ_HANDLED;

680

return IRQ_HANDLED;

681

}

681

}

682

683

return drv_data->transfer_handler(drv_data);

683

return drv_data->transfer_handler(drv_data);

684

}

684

}

685

686

int set_dma_burst_and_threshold(struct chip_data *chip, struct spi_device *spi,

686

int set_dma_burst_and_threshold(struct chip_data *chip, struct spi_device *spi,

687

u8 bits_per_word, u32 *burst_code,

687

u8 bits_per_word, u32 *burst_code,

688

u32 *threshold)

688

u32 *threshold)

689

{

689

{

690

struct pxa2xx_spi_chip *chip_info =

690

struct pxa2xx_spi_chip *chip_info =

691

(struct pxa2xx_spi_chip *)spi->controller_data;

691

(struct pxa2xx_spi_chip *)spi->controller_data;

692

int bytes_per_word;

692

int bytes_per_word;

693

int burst_bytes;

693

int burst_bytes;

694

int thresh_words;

694

int thresh_words;

695

int req_burst_size;

695

int req_burst_size;

696

int retval = 0;

696

int retval = 0;

697

698

/* Set the threshold (in registers) to equal the same amount of data

698

/* Set the threshold (in registers) to equal the same amount of data

699

* as represented by burst size (in bytes). The computation below

699

* as represented by burst size (in bytes). The computation below

700

* is (burst_size rounded up to nearest 8 byte, word or long word)

700

* is (burst_size rounded up to nearest 8 byte, word or long word)

701

* divided by (bytes/register); the tx threshold is the inverse of

701

* divided by (bytes/register); the tx threshold is the inverse of

702

* the rx, so that there will always be enough data in the rx fifo

702

* the rx, so that there will always be enough data in the rx fifo

703

* to satisfy a burst, and there will always be enough space in the

703

* to satisfy a burst, and there will always be enough space in the

704

* tx fifo to accept a burst (a tx burst will overwrite the fifo if

704

* tx fifo to accept a burst (a tx burst will overwrite the fifo if

705

* there is not enough space), there must always remain enough empty

705

* there is not enough space), there must always remain enough empty

706

* space in the rx fifo for any data loaded to the tx fifo.

706

* space in the rx fifo for any data loaded to the tx fifo.

707

* Whenever burst_size (in bytes) equals bits/word, the fifo threshold

707

* Whenever burst_size (in bytes) equals bits/word, the fifo threshold

708

* will be 8, or half the fifo;

708

* will be 8, or half the fifo;

709

* The threshold can only be set to 2, 4 or 8, but not 16, because

709

* The threshold can only be set to 2, 4 or 8, but not 16, because

710

* to burst 16 to the tx fifo, the fifo would have to be empty;

710

* to burst 16 to the tx fifo, the fifo would have to be empty;

711

* however, the minimum fifo trigger level is 1, and the tx will

711

* however, the minimum fifo trigger level is 1, and the tx will

712

* request service when the fifo is at this level, with only 15 spaces.

712

* request service when the fifo is at this level, with only 15 spaces.

713

*/

713

*/

714

715

/* find bytes/word */

715

/* find bytes/word */

716

if (bits_per_word <= 8)

716

if (bits_per_word <= 8)

717

bytes_per_word = 1;

717

bytes_per_word = 1;

718

else if (bits_per_word <= 16)

718

else if (bits_per_word <= 16)

719

bytes_per_word = 2;

719

bytes_per_word = 2;

720

else

720

else

721

bytes_per_word = 4;

721

bytes_per_word = 4;

722

723

/* use struct pxa2xx_spi_chip->dma_burst_size if available */

723

/* use struct pxa2xx_spi_chip->dma_burst_size if available */

724

if (chip_info)

724

if (chip_info)

725

req_burst_size = chip_info->dma_burst_size;

725

req_burst_size = chip_info->dma_burst_size;

726

else {

726

else {

727

switch (chip->dma_burst_size) {

727

switch (chip->dma_burst_size) {

728

default:

728

default:

729

/* if the default burst size is not set,

729

/* if the default burst size is not set,

730

* do it now */

730

* do it now */

731

chip->dma_burst_size = DCMD_BURST8;

731

chip->dma_burst_size = DCMD_BURST8;

732

case DCMD_BURST8:

732

case DCMD_BURST8:

733

req_burst_size = 8;

733

req_burst_size = 8;

734

break;

734

break;

735

case DCMD_BURST16:

735

case DCMD_BURST16:

736

req_burst_size = 16;

736

req_burst_size = 16;

737

break;

737

break;

738

case DCMD_BURST32:

738

case DCMD_BURST32:

739

req_burst_size = 32;

739

req_burst_size = 32;

740

break;

740

break;

741

}

741

}

742

}

742

}

743

if (req_burst_size <= 8) {

743

if (req_burst_size <= 8) {

744

*burst_code = DCMD_BURST8;

744

*burst_code = DCMD_BURST8;

745

burst_bytes = 8;

745

burst_bytes = 8;

746

} else if (req_burst_size <= 16) {

746

} else if (req_burst_size <= 16) {

747

if (bytes_per_word == 1) {

747

if (bytes_per_word == 1) {

748

/* don't burst more than 1/2 the fifo */

748

/* don't burst more than 1/2 the fifo */

749

*burst_code = DCMD_BURST8;

749

*burst_code = DCMD_BURST8;

750

burst_bytes = 8;

750

burst_bytes = 8;

751

retval = 1;

751

retval = 1;

752

} else {

752

} else {

753

*burst_code = DCMD_BURST16;

753

*burst_code = DCMD_BURST16;

754

burst_bytes = 16;

754

burst_bytes = 16;

755

}

755

}

756

} else {

756

} else {

757

if (bytes_per_word == 1) {

757

if (bytes_per_word == 1) {

758

/* don't burst more than 1/2 the fifo */

758

/* don't burst more than 1/2 the fifo */

759

*burst_code = DCMD_BURST8;

759

*burst_code = DCMD_BURST8;

760

burst_bytes = 8;

760

burst_bytes = 8;

761

retval = 1;

761

retval = 1;

762

} else if (bytes_per_word == 2) {

762

} else if (bytes_per_word == 2) {

763

/* don't burst more than 1/2 the fifo */

763

/* don't burst more than 1/2 the fifo */

764

*burst_code = DCMD_BURST16;

764

*burst_code = DCMD_BURST16;

765

burst_bytes = 16;

765

burst_bytes = 16;

766

retval = 1;

766

retval = 1;

767

} else {

767

} else {

768

*burst_code = DCMD_BURST32;

768

*burst_code = DCMD_BURST32;

769

burst_bytes = 32;

769

burst_bytes = 32;

770

}

770

}

771

}

771

}

772

773

thresh_words = burst_bytes / bytes_per_word;

773

thresh_words = burst_bytes / bytes_per_word;

774

775

/* thresh_words will be between 2 and 8 */

775

/* thresh_words will be between 2 and 8 */

776

*threshold = (SSCR1_RxTresh(thresh_words) & SSCR1_RFT)

776

*threshold = (SSCR1_RxTresh(thresh_words) & SSCR1_RFT)

777

| (SSCR1_TxTresh(16-thresh_words) & SSCR1_TFT);

777

| (SSCR1_TxTresh(16-thresh_words) & SSCR1_TFT);

778

779

return retval;

779

return retval;

780

}

780

}

781

782

static void pump_transfers(unsigned long data)

782

static void pump_transfers(unsigned long data)

783

{

783

{

784

struct driver_data *drv_data = (struct driver_data *)data;

784

struct driver_data *drv_data = (struct driver_data *)data;

785

struct spi_message *message = NULL;

785

struct spi_message *message = NULL;

786

struct spi_transfer *transfer = NULL;

786

struct spi_transfer *transfer = NULL;

787

struct spi_transfer *previous = NULL;

787

struct spi_transfer *previous = NULL;

788

struct chip_data *chip = NULL;

788

struct chip_data *chip = NULL;

789

void *reg = drv_data->ioaddr;

789

void *reg = drv_data->ioaddr;

790

u32 clk_div = 0;

790

u32 clk_div = 0;

791

u8 bits = 0;

791

u8 bits = 0;

792

u32 speed = 0;

792

u32 speed = 0;

793

u32 cr0;

793

u32 cr0;

794

u32 cr1;

794

u32 cr1;

795

u32 dma_thresh = drv_data->cur_chip->dma_threshold;

795

u32 dma_thresh = drv_data->cur_chip->dma_threshold;

796

u32 dma_burst = drv_data->cur_chip->dma_burst_size;

796

u32 dma_burst = drv_data->cur_chip->dma_burst_size;

797

798

/* Get current state information */

798

/* Get current state information */

799

message = drv_data->cur_msg;

799

message = drv_data->cur_msg;

800

transfer = drv_data->cur_transfer;

800

transfer = drv_data->cur_transfer;

801

chip = drv_data->cur_chip;

801

chip = drv_data->cur_chip;

802

803

/* Handle for abort */

803

/* Handle for abort */

804

if (message->state == ERROR_STATE) {

804

if (message->state == ERROR_STATE) {

805

message->status = -EIO;

805

message->status = -EIO;

806

giveback(drv_data);

806

giveback(drv_data);

807

return;

807

return;

808

}

808

}

809

810

/* Handle end of message */

810

/* Handle end of message */

811

if (message->state == DONE_STATE) {

811

if (message->state == DONE_STATE) {

812

message->status = 0;

812

message->status = 0;

813

giveback(drv_data);

813

giveback(drv_data);

814

return;

814

return;

815

}

815

}

816

817

/* Delay if requested at end of transfer*/

817

/* Delay if requested at end of transfer*/

818

if (message->state == RUNNING_STATE) {

818

if (message->state == RUNNING_STATE) {

819

previous = list_entry(transfer->transfer_list.prev,

819

previous = list_entry(transfer->transfer_list.prev,

820

struct spi_transfer,

820

struct spi_transfer,

821

transfer_list);

821

transfer_list);

822

if (previous->delay_usecs)

822

if (previous->delay_usecs)

823

udelay(previous->delay_usecs);

823

udelay(previous->delay_usecs);

824

}

824

}

825

826

/* Check transfer length */

826

/* Check transfer length */

827

if (transfer->len > 8191)

827

if (transfer->len > 8191)

828

{

828

{

829

dev_warn(&drv_data->pdev->dev, "pump_transfers: transfer "

829

dev_warn(&drv_data->pdev->dev, "pump_transfers: transfer "

830

"length greater than 8191\n");

830

"length greater than 8191\n");

831

message->status = -EINVAL;

831

message->status = -EINVAL;

832

giveback(drv_data);

832

giveback(drv_data);

833

return;

833

return;

834

}

834

}

835

836

/* Setup the transfer state based on the type of transfer */

836

/* Setup the transfer state based on the type of transfer */

837

if (flush(drv_data) == 0) {

837

if (flush(drv_data) == 0) {

838

dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");

838

dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");

839

message->status = -EIO;

839

message->status = -EIO;

840

giveback(drv_data);

840

giveback(drv_data);

841

return;

841

return;

842

}

842

}

843

drv_data->n_bytes = chip->n_bytes;

843

drv_data->n_bytes = chip->n_bytes;

844

drv_data->dma_width = chip->dma_width;

844

drv_data->dma_width = chip->dma_width;

845

drv_data->cs_control = chip->cs_control;

845

drv_data->cs_control = chip->cs_control;

846

drv_data->tx = (void *)transfer->tx_buf;

846

drv_data->tx = (void *)transfer->tx_buf;

847

drv_data->tx_end = drv_data->tx + transfer->len;

847

drv_data->tx_end = drv_data->tx + transfer->len;

848

drv_data->rx = transfer->rx_buf;

848

drv_data->rx = transfer->rx_buf;

849

drv_data->rx_end = drv_data->rx + transfer->len;

849

drv_data->rx_end = drv_data->rx + transfer->len;

850

drv_data->rx_dma = transfer->rx_dma;

850

drv_data->rx_dma = transfer->rx_dma;

851

drv_data->tx_dma = transfer->tx_dma;

851

drv_data->tx_dma = transfer->tx_dma;

852

drv_data->len = transfer->len & DCMD_LENGTH;

852

drv_data->len = transfer->len & DCMD_LENGTH;

853

drv_data->write = drv_data->tx ? chip->write : null_writer;

853

drv_data->write = drv_data->tx ? chip->write : null_writer;

854

drv_data->read = drv_data->rx ? chip->read : null_reader;

854

drv_data->read = drv_data->rx ? chip->read : null_reader;

855

drv_data->cs_change = transfer->cs_change;

855

drv_data->cs_change = transfer->cs_change;

856

857

/* Change speed and bit per word on a per transfer */

857

/* Change speed and bit per word on a per transfer */

858

cr0 = chip->cr0;

858

cr0 = chip->cr0;

859

if (transfer->speed_hz || transfer->bits_per_word) {

859

if (transfer->speed_hz || transfer->bits_per_word) {

860

861

bits = chip->bits_per_word;

861

bits = chip->bits_per_word;

862

speed = chip->speed_hz;

862

speed = chip->speed_hz;

863

864

if (transfer->speed_hz)

864

if (transfer->speed_hz)

865

speed = transfer->speed_hz;

865

speed = transfer->speed_hz;

866

867

if (transfer->bits_per_word)

867

if (transfer->bits_per_word)

868

bits = transfer->bits_per_word;

868

bits = transfer->bits_per_word;

869

870

if (reg == SSP1_VIRT)

870

if (reg == SSP1_VIRT)

871

clk_div = SSP1_SerClkDiv(speed);

871

clk_div = SSP1_SerClkDiv(speed);

872

else if (reg == SSP2_VIRT)

872

else if (reg == SSP2_VIRT)

873

clk_div = SSP2_SerClkDiv(speed);

873

clk_div = SSP2_SerClkDiv(speed);

874

else if (reg == SSP3_VIRT)

874

else if (reg == SSP3_VIRT)

875

clk_div = SSP3_SerClkDiv(speed);

875

clk_div = SSP3_SerClkDiv(speed);

876

877

if (bits <= 8) {

877

if (bits <= 8) {

878

drv_data->n_bytes = 1;

878

drv_data->n_bytes = 1;

879

drv_data->dma_width = DCMD_WIDTH1;

879

drv_data->dma_width = DCMD_WIDTH1;

880

drv_data->read = drv_data->read != null_reader ?

880

drv_data->read = drv_data->read != null_reader ?

881

u8_reader : null_reader;

881

u8_reader : null_reader;

882

drv_data->write = drv_data->write != null_writer ?

882

drv_data->write = drv_data->write != null_writer ?

883

u8_writer : null_writer;

883

u8_writer : null_writer;

884

} else if (bits <= 16) {

884

} else if (bits <= 16) {

885

drv_data->n_bytes = 2;

885

drv_data->n_bytes = 2;

886

drv_data->dma_width = DCMD_WIDTH2;

886

drv_data->dma_width = DCMD_WIDTH2;

887

drv_data->read = drv_data->read != null_reader ?

887

drv_data->read = drv_data->read != null_reader ?

888

u16_reader : null_reader;

888

u16_reader : null_reader;

889

drv_data->write = drv_data->write != null_writer ?

889

drv_data->write = drv_data->write != null_writer ?

890

u16_writer : null_writer;

890

u16_writer : null_writer;

891

} else if (bits <= 32) {

891

} else if (bits <= 32) {

892

drv_data->n_bytes = 4;

892

drv_data->n_bytes = 4;

893

drv_data->dma_width = DCMD_WIDTH4;

893

drv_data->dma_width = DCMD_WIDTH4;

894

drv_data->read = drv_data->read != null_reader ?

894

drv_data->read = drv_data->read != null_reader ?

895

u32_reader : null_reader;

895

u32_reader : null_reader;

896

drv_data->write = drv_data->write != null_writer ?

896

drv_data->write = drv_data->write != null_writer ?

897

u32_writer : null_writer;

897

u32_writer : null_writer;

898

}

898

}

899

/* if bits/word is changed in dma mode, then must check the

899

/* if bits/word is changed in dma mode, then must check the

900

* thresholds and burst also */

900

* thresholds and burst also */

901

if (chip->enable_dma) {

901

if (chip->enable_dma) {

902

if (set_dma_burst_and_threshold(chip, message->spi,

902

if (set_dma_burst_and_threshold(chip, message->spi,

903

bits, &dma_burst,

903

bits, &dma_burst,

904

&dma_thresh))

904

&dma_thresh))

905

if (printk_ratelimit())

905

if (printk_ratelimit())

906

dev_warn(&message->spi->dev,

906

dev_warn(&message->spi->dev,

907

"pump_transfer: "

907

"pump_transfer: "

908

"DMA burst size reduced to "

908

"DMA burst size reduced to "

909

"match bits_per_word\n");

909

"match bits_per_word\n");

910

}

910

}

911

912

cr0 = clk_div

912

cr0 = clk_div

913

| SSCR0_Motorola

913

| SSCR0_Motorola

914

| SSCR0_DataSize(bits > 16 ? bits - 16 : bits)

914

| SSCR0_DataSize(bits > 16 ? bits - 16 : bits)

915

| SSCR0_SSE

915

| SSCR0_SSE

916

| (bits > 16 ? SSCR0_EDSS : 0);

916

| (bits > 16 ? SSCR0_EDSS : 0);

917

}

917

}

918

919

message->state = RUNNING_STATE;

919

message->state = RUNNING_STATE;

920

921

/* Try to map dma buffer and do a dma transfer if successful */

921

/* Try to map dma buffer and do a dma transfer if successful */

922

if ((drv_data->dma_mapped = map_dma_buffers(drv_data))) {

922

if ((drv_data->dma_mapped = map_dma_buffers(drv_data))) {

923

924

/* Ensure we have the correct interrupt handler */

924

/* Ensure we have the correct interrupt handler */

925

drv_data->transfer_handler = dma_transfer;

925

drv_data->transfer_handler = dma_transfer;

926

927

/* Setup rx DMA Channel */

927

/* Setup rx DMA Channel */

928

DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;

928

DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;

929

DSADR(drv_data->rx_channel) = drv_data->ssdr_physical;

929

DSADR(drv_data->rx_channel) = drv_data->ssdr_physical;

930

DTADR(drv_data->rx_channel) = drv_data->rx_dma;

930

DTADR(drv_data->rx_channel) = drv_data->rx_dma;

931

if (drv_data->rx == drv_data->null_dma_buf)

931

if (drv_data->rx == drv_data->null_dma_buf)

932

/* No target address increment */

932

/* No target address increment */

933

DCMD(drv_data->rx_channel) = DCMD_FLOWSRC

933

DCMD(drv_data->rx_channel) = DCMD_FLOWSRC

934

| drv_data->dma_width

934

| drv_data->dma_width

935

| dma_burst

935

| dma_burst

936

| drv_data->len;

936

| drv_data->len;

937

else

937

else

938

DCMD(drv_data->rx_channel) = DCMD_INCTRGADDR

938

DCMD(drv_data->rx_channel) = DCMD_INCTRGADDR

939

| DCMD_FLOWSRC

939

| DCMD_FLOWSRC

940

| drv_data->dma_width

940

| drv_data->dma_width

941

| dma_burst

941

| dma_burst

942

| drv_data->len;

942

| drv_data->len;

943

944

/* Setup tx DMA Channel */

944

/* Setup tx DMA Channel */

945

DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;

945

DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;

946

DSADR(drv_data->tx_channel) = drv_data->tx_dma;

946

DSADR(drv_data->tx_channel) = drv_data->tx_dma;

947

DTADR(drv_data->tx_channel) = drv_data->ssdr_physical;

947

DTADR(drv_data->tx_channel) = drv_data->ssdr_physical;

948

if (drv_data->tx == drv_data->null_dma_buf)

948

if (drv_data->tx == drv_data->null_dma_buf)

949

/* No source address increment */

949

/* No source address increment */

950

DCMD(drv_data->tx_channel) = DCMD_FLOWTRG

950

DCMD(drv_data->tx_channel) = DCMD_FLOWTRG

951

| drv_data->dma_width

951

| drv_data->dma_width

952

| dma_burst

952

| dma_burst

953

| drv_data->len;

953

| drv_data->len;

954

else

954

else

955

DCMD(drv_data->tx_channel) = DCMD_INCSRCADDR

955

DCMD(drv_data->tx_channel) = DCMD_INCSRCADDR

956

| DCMD_FLOWTRG

956

| DCMD_FLOWTRG

957

| drv_data->dma_width

957

| drv_data->dma_width

958

| dma_burst

958

| dma_burst

959

| drv_data->len;

959

| drv_data->len;

960

961

/* Enable dma end irqs on SSP to detect end of transfer */

961

/* Enable dma end irqs on SSP to detect end of transfer */

962

if (drv_data->ssp_type == PXA25x_SSP)

962

if (drv_data->ssp_type == PXA25x_SSP)

963

DCMD(drv_data->tx_channel) |= DCMD_ENDIRQEN;

963

DCMD(drv_data->tx_channel) |= DCMD_ENDIRQEN;

964

965

/* Fix me, need to handle cs polarity */

965

/* Fix me, need to handle cs polarity */

966

drv_data->cs_control(PXA2XX_CS_ASSERT);

966

drv_data->cs_control(PXA2XX_CS_ASSERT);

967

968

/* Clear status and start DMA engine */

968

/* Clear status and start DMA engine */

969

cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;

969

cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;

970

write_SSSR(drv_data->clear_sr, reg);

970

write_SSSR(drv_data->clear_sr, reg);

971

DCSR(drv_data->rx_channel) |= DCSR_RUN;

971

DCSR(drv_data->rx_channel) |= DCSR_RUN;

972

DCSR(drv_data->tx_channel) |= DCSR_RUN;

972

DCSR(drv_data->tx_channel) |= DCSR_RUN;

973

} else {

973

} else {

974

/* Ensure we have the correct interrupt handler */

974

/* Ensure we have the correct interrupt handler */

975

drv_data->transfer_handler = interrupt_transfer;

975

drv_data->transfer_handler = interrupt_transfer;

976

977

/* Fix me, need to handle cs polarity */

977

/* Fix me, need to handle cs polarity */

978

drv_data->cs_control(PXA2XX_CS_ASSERT);

978

drv_data->cs_control(PXA2XX_CS_ASSERT);

979

980

/* Clear status */

980

/* Clear status */

981

cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;

981

cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;

982

write_SSSR(drv_data->clear_sr, reg);

982

write_SSSR(drv_data->clear_sr, reg);

983

}

983

}

984

985

/* see if we need to reload the config registers */

985

/* see if we need to reload the config registers */

986

if ((read_SSCR0(reg) != cr0)

986

if ((read_SSCR0(reg) != cr0)

987

|| (read_SSCR1(reg) & SSCR1_CHANGE_MASK) !=

987

|| (read_SSCR1(reg) & SSCR1_CHANGE_MASK) !=

988

(cr1 & SSCR1_CHANGE_MASK)) {

988

(cr1 & SSCR1_CHANGE_MASK)) {

989

990

write_SSCR0(cr0 & ~SSCR0_SSE, reg);

990

write_SSCR0(cr0 & ~SSCR0_SSE, reg);

991

if (drv_data->ssp_type != PXA25x_SSP)

991

if (drv_data->ssp_type != PXA25x_SSP)

992

write_SSTO(chip->timeout, reg);

992

write_SSTO(chip->timeout, reg);

993

write_SSCR1(cr1, reg);

993

write_SSCR1(cr1, reg);

994

write_SSCR0(cr0, reg);

994

write_SSCR0(cr0, reg);

995

} else {

995

} else {

996

if (drv_data->ssp_type != PXA25x_SSP)

996

if (drv_data->ssp_type != PXA25x_SSP)

997

write_SSTO(chip->timeout, reg);

997

write_SSTO(chip->timeout, reg);

998

write_SSCR1(cr1, reg);

998

write_SSCR1(cr1, reg);

999

}

999

}

1000

}

1000

}

1001

1002

static void pump_messages(struct work_struct *work)

1002

static void pump_messages(struct work_struct *work)

1003

{

1003

{

1004

struct driver_data *drv_data =

1004

struct driver_data *drv_data =

1005

container_of(work, struct driver_data, pump_messages);

1005

container_of(work, struct driver_data, pump_messages);

1006

unsigned long flags;

1006

unsigned long flags;

1007

1008

/* Lock queue and check for queue work */

1008

/* Lock queue and check for queue work */

1009

spin_lock_irqsave(&drv_data->lock, flags);

1009

spin_lock_irqsave(&drv_data->lock, flags);

1010

if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) {

1010

if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) {

1011

drv_data->busy = 0;

1011

drv_data->busy = 0;

1012

spin_unlock_irqrestore(&drv_data->lock, flags);

1012

spin_unlock_irqrestore(&drv_data->lock, flags);

1013

return;

1013

return;

1014

}

1014

}

1015

1016

/* Make sure we are not already running a message */

1016

/* Make sure we are not already running a message */

1017

if (drv_data->cur_msg) {

1017

if (drv_data->cur_msg) {

1018

spin_unlock_irqrestore(&drv_data->lock, flags);

1018

spin_unlock_irqrestore(&drv_data->lock, flags);

1019

return;

1019

return;

1020

}

1020

}

1021

1022

/* Extract head of queue */

1022

/* Extract head of queue */

1023

drv_data->cur_msg = list_entry(drv_data->queue.next,

1023

drv_data->cur_msg = list_entry(drv_data->queue.next,

1024

struct spi_message, queue);

1024

struct spi_message, queue);

1025

list_del_init(&drv_data->cur_msg->queue);

1025

list_del_init(&drv_data->cur_msg->queue);

1026

1027

/* Initial message state*/

1027

/* Initial message state*/

1028

drv_data->cur_msg->state = START_STATE;

1028

drv_data->cur_msg->state = START_STATE;

1029

drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,

1029

drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,

1030

struct spi_transfer,

1030

struct spi_transfer,

1031

transfer_list);

1031

transfer_list);

1032

1033

/* prepare to setup the SSP, in pump_transfers, using the per

1033

/* prepare to setup the SSP, in pump_transfers, using the per

1034

* chip configuration */

1034

* chip configuration */

1035

drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);

1035

drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);

1036

1037

/* Mark as busy and launch transfers */

1037

/* Mark as busy and launch transfers */

1038

tasklet_schedule(&drv_data->pump_transfers);

1038

tasklet_schedule(&drv_data->pump_transfers);

1039

1040

drv_data->busy = 1;

1040

drv_data->busy = 1;

1041

spin_unlock_irqrestore(&drv_data->lock, flags);

1041

spin_unlock_irqrestore(&drv_data->lock, flags);

1042

}

1042

}

1043

1044

static int transfer(struct spi_device *spi, struct spi_message *msg)

1044

static int transfer(struct spi_device *spi, struct spi_message *msg)

1045

{

1045

{

1046

struct driver_data *drv_data = spi_master_get_devdata(spi->master);

1046

struct driver_data *drv_data = spi_master_get_devdata(spi->master);

1047

unsigned long flags;

1047

unsigned long flags;

1048

1049

spin_lock_irqsave(&drv_data->lock, flags);

1049

spin_lock_irqsave(&drv_data->lock, flags);

1050

1051

if (drv_data->run == QUEUE_STOPPED) {

1051

if (drv_data->run == QUEUE_STOPPED) {

1052

spin_unlock_irqrestore(&drv_data->lock, flags);

1052

spin_unlock_irqrestore(&drv_data->lock, flags);

1053

return -ESHUTDOWN;

1053

return -ESHUTDOWN;

1054

}

1054

}

1055

1056

msg->actual_length = 0;

1056

msg->actual_length = 0;

1057

msg->status = -EINPROGRESS;

1057

msg->status = -EINPROGRESS;

1058

msg->state = START_STATE;

1058

msg->state = START_STATE;

1059

1060

list_add_tail(&msg->queue, &drv_data->queue);

1060

list_add_tail(&msg->queue, &drv_data->queue);

1061

1062

if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)

1062

if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)

1063

queue_work(drv_data->workqueue, &drv_data->pump_messages);

1063

queue_work(drv_data->workqueue, &drv_data->pump_messages);

1064

1065

spin_unlock_irqrestore(&drv_data->lock, flags);

1065

spin_unlock_irqrestore(&drv_data->lock, flags);

1066

1067

return 0;

1067

return 0;

1068

}

1068

}

1069

1070

static int setup(struct spi_device *spi)

1070

static int setup(struct spi_device *spi)

1071

{

1071

{

1072

struct pxa2xx_spi_chip *chip_info = NULL;

1072

struct pxa2xx_spi_chip *chip_info = NULL;

1073

struct chip_data *chip;

1073

struct chip_data *chip;

1074

struct driver_data *drv_data = spi_master_get_devdata(spi->master);

1074

struct driver_data *drv_data = spi_master_get_devdata(spi->master);

1075

unsigned int clk_div;

1075

unsigned int clk_div;

1076

1077

if (!spi->bits_per_word)

1077

if (!spi->bits_per_word)

1078

spi->bits_per_word = 8;

1078

spi->bits_per_word = 8;

1079

1080

if (drv_data->ssp_type != PXA25x_SSP

1080

if (drv_data->ssp_type != PXA25x_SSP

1081

&& (spi->bits_per_word < 4 || spi->bits_per_word > 32)) {

1081

&& (spi->bits_per_word < 4 || spi->bits_per_word > 32)) {

1082

dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d "

1082

dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d "

1083

"b/w not 4-32 for type non-PXA25x_SSP\n",

1083

"b/w not 4-32 for type non-PXA25x_SSP\n",

1084

drv_data->ssp_type, spi->bits_per_word);

1084

drv_data->ssp_type, spi->bits_per_word);

1085

return -EINVAL;

1085

return -EINVAL;

1086

}

1086

}

1087

else if (drv_data->ssp_type == PXA25x_SSP

1087

else if (drv_data->ssp_type == PXA25x_SSP

1088

&& (spi->bits_per_word < 4

1088

&& (spi->bits_per_word < 4

1089

|| spi->bits_per_word > 16)) {

1089

|| spi->bits_per_word > 16)) {

1090

dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d "

1090

dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d "

1091

"b/w not 4-16 for type PXA25x_SSP\n",

1091

"b/w not 4-16 for type PXA25x_SSP\n",

1092

drv_data->ssp_type, spi->bits_per_word);

1092

drv_data->ssp_type, spi->bits_per_word);

1093

return -EINVAL;

1093

return -EINVAL;

1094

}

1094

}

1095

1096

/* Only alloc on first setup */

1096

/* Only alloc on first setup */

1097

chip = spi_get_ctldata(spi);

1097

chip = spi_get_ctldata(spi);

1098

if (!chip) {

1098

if (!chip) {

1099

chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);

1099

chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);

1100

if (!chip) {

1100

if (!chip) {

1101

dev_err(&spi->dev,

1101

dev_err(&spi->dev,

1102

"failed setup: can't allocate chip data\n");

1102

"failed setup: can't allocate chip data\n");

1103

return -ENOMEM;

1103

return -ENOMEM;

1104

}

1104

}

1105

1106

chip->cs_control = null_cs_control;

1106

chip->cs_control = null_cs_control;

1107

chip->enable_dma = 0;

1107

chip->enable_dma = 0;

1108

chip->timeout = 1000;

1108

chip->timeout = 1000;

1109

chip->threshold = SSCR1_RxTresh(1) | SSCR1_TxTresh(1);

1109

chip->threshold = SSCR1_RxTresh(1) | SSCR1_TxTresh(1);

1110

chip->dma_burst_size = drv_data->master_info->enable_dma ?

1110

chip->dma_burst_size = drv_data->master_info->enable_dma ?

1111

DCMD_BURST8 : 0;

1111

DCMD_BURST8 : 0;

1112

}

1112

}

1113

1114

/* protocol drivers may change the chip settings, so...

1114

/* protocol drivers may change the chip settings, so...

1115

* if chip_info exists, use it */

1115

* if chip_info exists, use it */

1116

chip_info = spi->controller_data;

1116

chip_info = spi->controller_data;

1117

1118

/* chip_info isn't always needed */

1118

/* chip_info isn't always needed */

1119

chip->cr1 = 0;

1119

chip->cr1 = 0;

1120

if (chip_info) {

1120

if (chip_info) {

1121

if (chip_info->cs_control)

1121

if (chip_info->cs_control)

1122

chip->cs_control = chip_info->cs_control;

1122

chip->cs_control = chip_info->cs_control;

1123

1124

chip->timeout = chip_info->timeout;

1124

chip->timeout = chip_info->timeout;

1125

1126

chip->threshold = (SSCR1_RxTresh(chip_info->rx_threshold) &

1126

chip->threshold = (SSCR1_RxTresh(chip_info->rx_threshold) &

1127

SSCR1_RFT) |

1127

SSCR1_RFT) |

1128

(SSCR1_TxTresh(chip_info->tx_threshold) &

1128

(SSCR1_TxTresh(chip_info->tx_threshold) &

1129

SSCR1_TFT);

1129

SSCR1_TFT);

1130

1131

chip->enable_dma = chip_info->dma_burst_size != 0

1131

chip->enable_dma = chip_info->dma_burst_size != 0

1132

&& drv_data->master_info->enable_dma;

1132

&& drv_data->master_info->enable_dma;

1133

chip->dma_threshold = 0;

1133

chip->dma_threshold = 0;

1134

1135

if (chip_info->enable_loopback)

1135

if (chip_info->enable_loopback)

1136

chip->cr1 = SSCR1_LBM;

1136

chip->cr1 = SSCR1_LBM;

1137

}

1137

}

1138

1139

/* set dma burst and threshold outside of chip_info path so that if

1139

/* set dma burst and threshold outside of chip_info path so that if

1140

* chip_info goes away after setting chip->enable_dma, the

1140

* chip_info goes away after setting chip->enable_dma, the

1141

* burst and threshold can still respond to changes in bits_per_word */

1141

* burst and threshold can still respond to changes in bits_per_word */

1142

if (chip->enable_dma) {

1142

if (chip->enable_dma) {

1143

/* set up legal burst and threshold for dma */

1143

/* set up legal burst and threshold for dma */

1144

if (set_dma_burst_and_threshold(chip, spi, spi->bits_per_word,

1144

if (set_dma_burst_and_threshold(chip, spi, spi->bits_per_word,

1145

&chip->dma_burst_size,

1145

&chip->dma_burst_size,

1146

&chip->dma_threshold)) {

1146

&chip->dma_threshold)) {

1147

dev_warn(&spi->dev, "in setup: DMA burst size reduced "

1147

dev_warn(&spi->dev, "in setup: DMA burst size reduced "

1148

"to match bits_per_word\n");

1148

"to match bits_per_word\n");

1149

}

1149

}

1150

}

1150

}

1151

1152

if (drv_data->ioaddr == SSP1_VIRT)

1152

if (drv_data->ioaddr == SSP1_VIRT)

1153

clk_div = SSP1_SerClkDiv(spi->max_speed_hz);

1153

clk_div = SSP1_SerClkDiv(spi->max_speed_hz);

1154

else if (drv_data->ioaddr == SSP2_VIRT)

1154

else if (drv_data->ioaddr == SSP2_VIRT)

1155

clk_div = SSP2_SerClkDiv(spi->max_speed_hz);

1155

clk_div = SSP2_SerClkDiv(spi->max_speed_hz);

1156

else if (drv_data->ioaddr == SSP3_VIRT)

1156

else if (drv_data->ioaddr == SSP3_VIRT)

1157

clk_div = SSP3_SerClkDiv(spi->max_speed_hz);

1157

clk_div = SSP3_SerClkDiv(spi->max_speed_hz);

1158

else

1158

else

1159

{

1159

{

1160

dev_err(&spi->dev, "failed setup: unknown IO address=0x%p\n",

1160

dev_err(&spi->dev, "failed setup: unknown IO address=0x%p\n",

1161

drv_data->ioaddr);

1161

drv_data->ioaddr);

1162

return -ENODEV;

1162

return -ENODEV;

1163

}

1163

}

1164

chip->speed_hz = spi->max_speed_hz;

1164

chip->speed_hz = spi->max_speed_hz;

1165

1166

chip->cr0 = clk_div

1166

chip->cr0 = clk_div

1167

| SSCR0_Motorola

1167

| SSCR0_Motorola

1168

| SSCR0_DataSize(spi->bits_per_word > 16 ?

1168

| SSCR0_DataSize(spi->bits_per_word > 16 ?

1169

spi->bits_per_word - 16 : spi->bits_per_word)

1169

spi->bits_per_word - 16 : spi->bits_per_word)

1170

| SSCR0_SSE

1170

| SSCR0_SSE

1171

| (spi->bits_per_word > 16 ? SSCR0_EDSS : 0);

1171

| (spi->bits_per_word > 16 ? SSCR0_EDSS : 0);

1172

chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) << 4)

1172

chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);

1173

| (((spi->mode & SPI_CPOL) != 0) << 3);

1173

chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)

1174

| (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);

1174

1175

/* NOTE: PXA25x_SSP _could_ use external clocking ... */

1176

/* NOTE: PXA25x_SSP _could_ use external clocking ... */

1176

if (drv_data->ssp_type != PXA25x_SSP)

1177

if (drv_data->ssp_type != PXA25x_SSP)

1177

dev_dbg(&spi->dev, "%d bits/word, %d Hz, mode %d\n",

1178

dev_dbg(&spi->dev, "%d bits/word, %d Hz, mode %d\n",

1178

spi->bits_per_word,

1179

spi->bits_per_word,

1179

(CLOCK_SPEED_HZ)

1180

(CLOCK_SPEED_HZ)

1180

/ (1 + ((chip->cr0 & SSCR0_SCR) >> 8)),

1181

/ (1 + ((chip->cr0 & SSCR0_SCR) >> 8)),

1181

spi->mode & 0x3);

1182

spi->mode & 0x3);

1182

else

1183

else

1183

dev_dbg(&spi->dev, "%d bits/word, %d Hz, mode %d\n",

1184

dev_dbg(&spi->dev, "%d bits/word, %d Hz, mode %d\n",

1184

spi->bits_per_word,

1185

spi->bits_per_word,

1185

(CLOCK_SPEED_HZ/2)

1186

(CLOCK_SPEED_HZ/2)

1186

/ (1 + ((chip->cr0 & SSCR0_SCR) >> 8)),

1187

/ (1 + ((chip->cr0 & SSCR0_SCR) >> 8)),

1187

spi->mode & 0x3);

1188

spi->mode & 0x3);

1188

1189

if (spi->bits_per_word <= 8) {

1190

if (spi->bits_per_word <= 8) {

1190

chip->n_bytes = 1;

1191

chip->n_bytes = 1;

1191

chip->dma_width = DCMD_WIDTH1;

1192

chip->dma_width = DCMD_WIDTH1;

1192

chip->read = u8_reader;

1193

chip->read = u8_reader;

1193

chip->write = u8_writer;

1194

chip->write = u8_writer;

1194

} else if (spi->bits_per_word <= 16) {

1195

} else if (spi->bits_per_word <= 16) {

1195

chip->n_bytes = 2;

1196

chip->n_bytes = 2;

1196

chip->dma_width = DCMD_WIDTH2;

1197

chip->dma_width = DCMD_WIDTH2;

1197

chip->read = u16_reader;

1198

chip->read = u16_reader;

1198

chip->write = u16_writer;

1199

chip->write = u16_writer;

1199

} else if (spi->bits_per_word <= 32) {

1200

} else if (spi->bits_per_word <= 32) {

1200

chip->cr0 |= SSCR0_EDSS;

1201

chip->cr0 |= SSCR0_EDSS;

1201

chip->n_bytes = 4;

1202

chip->n_bytes = 4;

1202

chip->dma_width = DCMD_WIDTH4;

1203

chip->dma_width = DCMD_WIDTH4;

1203

chip->read = u32_reader;

1204

chip->read = u32_reader;

1204

chip->write = u32_writer;

1205

chip->write = u32_writer;

1205

} else {

1206

} else {

1206

dev_err(&spi->dev, "invalid wordsize\n");

1207

dev_err(&spi->dev, "invalid wordsize\n");

1207

return -ENODEV;

1208

return -ENODEV;

1208

}

1209

}

1209

chip->bits_per_word = spi->bits_per_word;

1210

chip->bits_per_word = spi->bits_per_word;

1210

1211

spi_set_ctldata(spi, chip);

1212

spi_set_ctldata(spi, chip);

1212

1213

return 0;

1214

return 0;

1214

}

1215

}

1215

1216

static void cleanup(const struct spi_device *spi)

1217

static void cleanup(const struct spi_device *spi)

1217

{

1218

{

1218

struct chip_data *chip = spi_get_ctldata((struct spi_device *)spi);

1219

struct chip_data *chip = spi_get_ctldata((struct spi_device *)spi);

1219

1220

kfree(chip);

1221

kfree(chip);

1221

}

1222

}

1222

1223

static int init_queue(struct driver_data *drv_data)

1224

static int init_queue(struct driver_data *drv_data)

1224

{

1225

{

1225

INIT_LIST_HEAD(&drv_data->queue);

1226

INIT_LIST_HEAD(&drv_data->queue);

1226

spin_lock_init(&drv_data->lock);

1227

spin_lock_init(&drv_data->lock);

1227

1228

drv_data->run = QUEUE_STOPPED;

1229

drv_data->run = QUEUE_STOPPED;

1229

drv_data->busy = 0;

1230

drv_data->busy = 0;

1230

1231

tasklet_init(&drv_data->pump_transfers,

1232

tasklet_init(&drv_data->pump_transfers,

1232

pump_transfers, (unsigned long)drv_data);

1233

pump_transfers, (unsigned long)drv_data);

1233

1234

INIT_WORK(&drv_data->pump_messages, pump_messages);

1235

INIT_WORK(&drv_data->pump_messages, pump_messages);

1235

drv_data->workqueue = create_singlethread_workqueue(

1236

drv_data->workqueue = create_singlethread_workqueue(

1236

drv_data->master->cdev.dev->bus_id);

1237

drv_data->master->cdev.dev->bus_id);

1237

if (drv_data->workqueue == NULL)

1238

if (drv_data->workqueue == NULL)

1238

return -EBUSY;

1239

return -EBUSY;

1239

1240

return 0;

1241

return 0;

1241

}

1242

}

1242

1243

static int start_queue(struct driver_data *drv_data)

1244

static int start_queue(struct driver_data *drv_data)

1244

{

1245

{

1245

unsigned long flags;

1246

unsigned long flags;

1246

1247

spin_lock_irqsave(&drv_data->lock, flags);

1248

spin_lock_irqsave(&drv_data->lock, flags);

1248

1249

if (drv_data->run == QUEUE_RUNNING || drv_data->busy) {

1250

if (drv_data->run == QUEUE_RUNNING || drv_data->busy) {

1250

spin_unlock_irqrestore(&drv_data->lock, flags);

1251

spin_unlock_irqrestore(&drv_data->lock, flags);

1251

return -EBUSY;

1252

return -EBUSY;

1252

}

1253

}

1253

1254

drv_data->run = QUEUE_RUNNING;

1255

drv_data->run = QUEUE_RUNNING;

1255

drv_data->cur_msg = NULL;

1256

drv_data->cur_msg = NULL;

1256

drv_data->cur_transfer = NULL;

1257

drv_data->cur_transfer = NULL;

1257

drv_data->cur_chip = NULL;

1258

drv_data->cur_chip = NULL;

1258

spin_unlock_irqrestore(&drv_data->lock, flags);

1259

spin_unlock_irqrestore(&drv_data->lock, flags);

1259

1260

queue_work(drv_data->workqueue, &drv_data->pump_messages);

1261

queue_work(drv_data->workqueue, &drv_data->pump_messages);

1261

1262

return 0;

1263

return 0;

1263

}

1264

}

1264

1265

static int stop_queue(struct driver_data *drv_data)

1266

static int stop_queue(struct driver_data *drv_data)

1266

{

1267

{

1267

unsigned long flags;

1268

unsigned long flags;

1268

unsigned limit = 500;

1269

unsigned limit = 500;

1269

int status = 0;

1270

int status = 0;

1270

1271

spin_lock_irqsave(&drv_data->lock, flags);

1272

spin_lock_irqsave(&drv_data->lock, flags);

1272

1273

/* This is a bit lame, but is optimized for the common execution path.

1274

/* This is a bit lame, but is optimized for the common execution path.

1274

* A wait_queue on the drv_data->busy could be used, but then the common

1275

* A wait_queue on the drv_data->busy could be used, but then the common

1275

* execution path (pump_messages) would be required to call wake_up or

1276

* execution path (pump_messages) would be required to call wake_up or

1276

* friends on every SPI message. Do this instead */

1277

* friends on every SPI message. Do this instead */

1277

drv_data->run = QUEUE_STOPPED;

1278

drv_data->run = QUEUE_STOPPED;

1278

while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {

1279

while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {

1279

spin_unlock_irqrestore(&drv_data->lock, flags);

1280

spin_unlock_irqrestore(&drv_data->lock, flags);

1280

msleep(10);

1281

msleep(10);

1281

spin_lock_irqsave(&drv_data->lock, flags);

1282

spin_lock_irqsave(&drv_data->lock, flags);

1282

}

1283

}

1283

1284

if (!list_empty(&drv_data->queue) || drv_data->busy)

1285

if (!list_empty(&drv_data->queue) || drv_data->busy)

1285

status = -EBUSY;

1286

status = -EBUSY;

1286

1287

spin_unlock_irqrestore(&drv_data->lock, flags);

1288

spin_unlock_irqrestore(&drv_data->lock, flags);

1288

1289

return status;

1290

return status;

1290

}

1291

}

1291

1292

static int destroy_queue(struct driver_data *drv_data)

1293

static int destroy_queue(struct driver_data *drv_data)

1293

{

1294

{

1294

int status;

1295

int status;

1295

1296

status = stop_queue(drv_data);

1297

status = stop_queue(drv_data);

1297

/* we are unloading the module or failing to load (only two calls

1298

/* we are unloading the module or failing to load (only two calls

1298

* to this routine), and neither call can handle a return value.

1299

* to this routine), and neither call can handle a return value.

1299

* However, destroy_workqueue calls flush_workqueue, and that will

1300

* However, destroy_workqueue calls flush_workqueue, and that will

1300

* block until all work is done. If the reason that stop_queue

1301

* block until all work is done. If the reason that stop_queue

1301

* timed out is that the work will never finish, then it does no

1302

* timed out is that the work will never finish, then it does no

1302

* good to call destroy_workqueue, so return anyway. */

1303

* good to call destroy_workqueue, so return anyway. */

1303

if (status != 0)

1304

if (status != 0)

1304

return status;

1305

return status;

1305

1306

destroy_workqueue(drv_data->workqueue);

1307

destroy_workqueue(drv_data->workqueue);

1307

1308

return 0;

1309

return 0;

1309

}

1310

}

1310

1311

static int pxa2xx_spi_probe(struct platform_device *pdev)

1312

static int pxa2xx_spi_probe(struct platform_device *pdev)

1312

{

1313

{

1313

struct device *dev = &pdev->dev;

1314

struct device *dev = &pdev->dev;

1314

struct pxa2xx_spi_master *platform_info;

1315

struct pxa2xx_spi_master *platform_info;

1315

struct spi_master *master;

1316

struct spi_master *master;

1316

struct driver_data *drv_data = 0;

1317

struct driver_data *drv_data = 0;

1317

struct resource *memory_resource;

1318

struct resource *memory_resource;

1318

int irq;

1319

int irq;

1319

int status = 0;

1320

int status = 0;

1320

1321

platform_info = dev->platform_data;

1322

platform_info = dev->platform_data;

1322

1323

if (platform_info->ssp_type == SSP_UNDEFINED) {

1324

if (platform_info->ssp_type == SSP_UNDEFINED) {

1324

dev_err(&pdev->dev, "undefined SSP\n");

1325

dev_err(&pdev->dev, "undefined SSP\n");

1325

return -ENODEV;

1326

return -ENODEV;

1326

}

1327

}

1327

1328

/* Allocate master with space for drv_data and null dma buffer */

1329

/* Allocate master with space for drv_data and null dma buffer */

1329

master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);

1330

master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);

1330

if (!master) {

1331

if (!master) {

1331

dev_err(&pdev->dev, "can not alloc spi_master\n");

1332

dev_err(&pdev->dev, "can not alloc spi_master\n");

1332

return -ENOMEM;

1333

return -ENOMEM;

1333

}

1334

}

1334

drv_data = spi_master_get_devdata(master);

1335

drv_data = spi_master_get_devdata(master);

1335

drv_data->master = master;

1336

drv_data->master = master;

1336

drv_data->master_info = platform_info;

1337

drv_data->master_info = platform_info;

1337

drv_data->pdev = pdev;

1338

drv_data->pdev = pdev;

1338

1339

master->bus_num = pdev->id;

1340

master->bus_num = pdev->id;

1340

master->num_chipselect = platform_info->num_chipselect;

1341

master->num_chipselect = platform_info->num_chipselect;

1341

master->cleanup = cleanup;

1342

master->cleanup = cleanup;

1342

master->setup = setup;

1343

master->setup = setup;

1343

master->transfer = transfer;

1344

master->transfer = transfer;

1344

1345

drv_data->ssp_type = platform_info->ssp_type;

1346

drv_data->ssp_type = platform_info->ssp_type;

1346

drv_data->null_dma_buf = (u32 *)ALIGN((u32)(drv_data +

1347

drv_data->null_dma_buf = (u32 *)ALIGN((u32)(drv_data +

1347

sizeof(struct driver_data)), 8);

1348

sizeof(struct driver_data)), 8);

1348

1349

/* Setup register addresses */

1350

/* Setup register addresses */

1350

memory_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);

1351

memory_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);

1351

if (!memory_resource) {

1352

if (!memory_resource) {

1352

dev_err(&pdev->dev, "memory resources not defined\n");

1353

dev_err(&pdev->dev, "memory resources not defined\n");

1353

status = -ENODEV;

1354

status = -ENODEV;

1354

goto out_error_master_alloc;

1355

goto out_error_master_alloc;

1355

}

1356

}

1356

1357

drv_data->ioaddr = (void *)io_p2v((unsigned long)(memory_resource->start));

1358

drv_data->ioaddr = (void *)io_p2v((unsigned long)(memory_resource->start));

1358

drv_data->ssdr_physical = memory_resource->start + 0x00000010;

1359

drv_data->ssdr_physical = memory_resource->start + 0x00000010;

1359

if (platform_info->ssp_type == PXA25x_SSP) {

1360

if (platform_info->ssp_type == PXA25x_SSP) {

1360

drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;

1361

drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;

1361

drv_data->dma_cr1 = 0;

1362

drv_data->dma_cr1 = 0;

1362

drv_data->clear_sr = SSSR_ROR;

1363

drv_data->clear_sr = SSSR_ROR;

1363

drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;

1364

drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;

1364

} else {

1365

} else {

1365

drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;

1366

drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;

1366

drv_data->dma_cr1 = SSCR1_TSRE | SSCR1_RSRE | SSCR1_TINTE;

1367

drv_data->dma_cr1 = SSCR1_TSRE | SSCR1_RSRE | SSCR1_TINTE;

1367

drv_data->clear_sr = SSSR_ROR | SSSR_TINT;

1368

drv_data->clear_sr = SSSR_ROR | SSSR_TINT;

1368

drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR;

1369

drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR;

1369

}

1370

}

1370

1371

/* Attach to IRQ */

1372

/* Attach to IRQ */

1372

irq = platform_get_irq(pdev, 0);

1373

irq = platform_get_irq(pdev, 0);

1373

if (irq < 0) {

1374

if (irq < 0) {

1374

dev_err(&pdev->dev, "irq resource not defined\n");

1375

dev_err(&pdev->dev, "irq resource not defined\n");

1375

status = -ENODEV;

1376

status = -ENODEV;

1376

goto out_error_master_alloc;

1377

goto out_error_master_alloc;

1377

}

1378

}

1378

1379

status = request_irq(irq, ssp_int, 0, dev->bus_id, drv_data);

1380

status = request_irq(irq, ssp_int, 0, dev->bus_id, drv_data);

1380

if (status < 0) {

1381

if (status < 0) {

1381

dev_err(&pdev->dev, "can not get IRQ\n");

1382

dev_err(&pdev->dev, "can not get IRQ\n");

1382

goto out_error_master_alloc;

1383

goto out_error_master_alloc;

1383

}

1384

}

1384

1385

/* Setup DMA if requested */

1386

/* Setup DMA if requested */

1386

drv_data->tx_channel = -1;

1387

drv_data->tx_channel = -1;

1387

drv_data->rx_channel = -1;

1388

drv_data->rx_channel = -1;

1388

if (platform_info->enable_dma) {

1389

if (platform_info->enable_dma) {

1389

1390

/* Get two DMA channels (rx and tx) */

1391

/* Get two DMA channels (rx and tx) */

1391

drv_data->rx_channel = pxa_request_dma("pxa2xx_spi_ssp_rx",

1392

drv_data->rx_channel = pxa_request_dma("pxa2xx_spi_ssp_rx",

1392

DMA_PRIO_HIGH,

1393

DMA_PRIO_HIGH,

1393

dma_handler,

1394

dma_handler,

1394

drv_data);

1395

drv_data);

1395

if (drv_data->rx_channel < 0) {

1396

if (drv_data->rx_channel < 0) {

1396

dev_err(dev, "problem (%d) requesting rx channel\n",

1397

dev_err(dev, "problem (%d) requesting rx channel\n",

1397

drv_data->rx_channel);

1398

drv_data->rx_channel);

1398

status = -ENODEV;

1399

status = -ENODEV;

1399

goto out_error_irq_alloc;

1400

goto out_error_irq_alloc;

1400

}

1401

}

1401

drv_data->tx_channel = pxa_request_dma("pxa2xx_spi_ssp_tx",

1402

drv_data->tx_channel = pxa_request_dma("pxa2xx_spi_ssp_tx",

1402

DMA_PRIO_MEDIUM,

1403

DMA_PRIO_MEDIUM,

1403

dma_handler,

1404

dma_handler,

1404

drv_data);

1405

drv_data);

1405

if (drv_data->tx_channel < 0) {

1406

if (drv_data->tx_channel < 0) {

1406

dev_err(dev, "problem (%d) requesting tx channel\n",

1407

dev_err(dev, "problem (%d) requesting tx channel\n",

1407

drv_data->tx_channel);

1408

drv_data->tx_channel);

1408

status = -ENODEV;

1409

status = -ENODEV;

1409

goto out_error_dma_alloc;

1410

goto out_error_dma_alloc;

1410

}

1411

}

1411

1412

if (drv_data->ioaddr == SSP1_VIRT) {

1413

if (drv_data->ioaddr == SSP1_VIRT) {

1413

DRCMRRXSSDR = DRCMR_MAPVLD

1414

DRCMRRXSSDR = DRCMR_MAPVLD

1414

| drv_data->rx_channel;

1415

| drv_data->rx_channel;

1415

DRCMRTXSSDR = DRCMR_MAPVLD

1416

DRCMRTXSSDR = DRCMR_MAPVLD

1416

| drv_data->tx_channel;

1417

| drv_data->tx_channel;

1417

} else if (drv_data->ioaddr == SSP2_VIRT) {

1418

} else if (drv_data->ioaddr == SSP2_VIRT) {

1418

DRCMRRXSS2DR = DRCMR_MAPVLD

1419

DRCMRRXSS2DR = DRCMR_MAPVLD

1419

| drv_data->rx_channel;

1420

| drv_data->rx_channel;

1420

DRCMRTXSS2DR = DRCMR_MAPVLD

1421

DRCMRTXSS2DR = DRCMR_MAPVLD

1421

| drv_data->tx_channel;

1422

| drv_data->tx_channel;

1422

} else if (drv_data->ioaddr == SSP3_VIRT) {

1423

} else if (drv_data->ioaddr == SSP3_VIRT) {

1423

DRCMRRXSS3DR = DRCMR_MAPVLD

1424

DRCMRRXSS3DR = DRCMR_MAPVLD

1424

| drv_data->rx_channel;

1425

| drv_data->rx_channel;

1425

DRCMRTXSS3DR = DRCMR_MAPVLD

1426

DRCMRTXSS3DR = DRCMR_MAPVLD

1426

| drv_data->tx_channel;

1427

| drv_data->tx_channel;

1427

} else {

1428

} else {

1428

dev_err(dev, "bad SSP type\n");

1429

dev_err(dev, "bad SSP type\n");

1429

goto out_error_dma_alloc;

1430

goto out_error_dma_alloc;

1430

}

1431

}

1431

}

1432

}

1432

1433

/* Enable SOC clock */

1434

/* Enable SOC clock */

1434

pxa_set_cken(platform_info->clock_enable, 1);

1435

pxa_set_cken(platform_info->clock_enable, 1);

1435

1436

/* Load default SSP configuration */

1437

/* Load default SSP configuration */

1437

write_SSCR0(0, drv_data->ioaddr);

1438

write_SSCR0(0, drv_data->ioaddr);

1438

write_SSCR1(SSCR1_RxTresh(4) | SSCR1_TxTresh(12), drv_data->ioaddr);

1439

write_SSCR1(SSCR1_RxTresh(4) | SSCR1_TxTresh(12), drv_data->ioaddr);

1439

write_SSCR0(SSCR0_SerClkDiv(2)

1440

write_SSCR0(SSCR0_SerClkDiv(2)

1440

| SSCR0_Motorola

1441

| SSCR0_Motorola

1441

| SSCR0_DataSize(8),

1442

| SSCR0_DataSize(8),

1442

drv_data->ioaddr);

1443

drv_data->ioaddr);

1443

if (drv_data->ssp_type != PXA25x_SSP)

1444

if (drv_data->ssp_type != PXA25x_SSP)

1444

write_SSTO(0, drv_data->ioaddr);

1445

write_SSTO(0, drv_data->ioaddr);

1445

write_SSPSP(0, drv_data->ioaddr);

1446

write_SSPSP(0, drv_data->ioaddr);

1446

1447

/* Initial and start queue */

1448

/* Initial and start queue */

1448

status = init_queue(drv_data);

1449

status = init_queue(drv_data);

1449

if (status != 0) {

1450

if (status != 0) {

1450

dev_err(&pdev->dev, "problem initializing queue\n");

1451

dev_err(&pdev->dev, "problem initializing queue\n");

1451

goto out_error_clock_enabled;

1452

goto out_error_clock_enabled;

1452

}

1453

}

1453

status = start_queue(drv_data);

1454

status = start_queue(drv_data);

1454

if (status != 0) {

1455

if (status != 0) {

1455

dev_err(&pdev->dev, "problem starting queue\n");

1456

dev_err(&pdev->dev, "problem starting queue\n");

1456

goto out_error_clock_enabled;

1457

goto out_error_clock_enabled;

1457

}

1458

}

1458

1459

/* Register with the SPI framework */

1460

/* Register with the SPI framework */

1460

platform_set_drvdata(pdev, drv_data);

1461

platform_set_drvdata(pdev, drv_data);

1461

status = spi_register_master(master);

1462

status = spi_register_master(master);

1462

if (status != 0) {

1463

if (status != 0) {

1463

dev_err(&pdev->dev, "problem registering spi master\n");

1464

dev_err(&pdev->dev, "problem registering spi master\n");

1464

goto out_error_queue_alloc;

1465

goto out_error_queue_alloc;

1465

}

1466

}

1466

1467

return status;

1468

return status;

1468

1469

out_error_queue_alloc:

1470

out_error_queue_alloc:

1470

destroy_queue(drv_data);

1471

destroy_queue(drv_data);

1471

1472

out_error_clock_enabled:

1473

out_error_clock_enabled:

1473

pxa_set_cken(platform_info->clock_enable, 0);

1474

pxa_set_cken(platform_info->clock_enable, 0);

1474

1475

out_error_dma_alloc:

1476

out_error_dma_alloc:

1476

if (drv_data->tx_channel != -1)

1477

if (drv_data->tx_channel != -1)

1477

pxa_free_dma(drv_data->tx_channel);

1478

pxa_free_dma(drv_data->tx_channel);

1478

if (drv_data->rx_channel != -1)

1479

if (drv_data->rx_channel != -1)

1479

pxa_free_dma(drv_data->rx_channel);

1480

pxa_free_dma(drv_data->rx_channel);

1480

1481

out_error_irq_alloc:

1482

out_error_irq_alloc:

1482

free_irq(irq, drv_data);

1483

free_irq(irq, drv_data);

1483

1484

out_error_master_alloc:

1485

out_error_master_alloc:

1485

spi_master_put(master);

1486

spi_master_put(master);

1486

return status;

1487

return status;

1487

}

1488

}

1488

1489

static int pxa2xx_spi_remove(struct platform_device *pdev)

1490

static int pxa2xx_spi_remove(struct platform_device *pdev)

1490

{

1491

{

1491

struct driver_data *drv_data = platform_get_drvdata(pdev);

1492

struct driver_data *drv_data = platform_get_drvdata(pdev);

1492

int irq;

1493

int irq;

1493

int status = 0;

1494

int status = 0;

1494

1495

if (!drv_data)

1496

if (!drv_data)

1496

return 0;

1497

return 0;

1497

1498

/* Remove the queue */

1499

/* Remove the queue */

1499

status = destroy_queue(drv_data);

1500

status = destroy_queue(drv_data);

1500

if (status != 0)

1501

if (status != 0)

1501

/* the kernel does not check the return status of this

1502

/* the kernel does not check the return status of this

1502

* this routine (mod->exit, within the kernel). Therefore

1503

* this routine (mod->exit, within the kernel). Therefore

1503

* nothing is gained by returning from here, the module is

1504

* nothing is gained by returning from here, the module is

1504

* going away regardless, and we should not leave any more

1505

* going away regardless, and we should not leave any more

1505

* resources allocated than necessary. We cannot free the

1506

* resources allocated than necessary. We cannot free the

1506

* message memory in drv_data->queue, but we can release the

1507

* message memory in drv_data->queue, but we can release the

1507

* resources below. I think the kernel should honor -EBUSY

1508

* resources below. I think the kernel should honor -EBUSY

1508

* returns but... */

1509

* returns but... */

1509

dev_err(&pdev->dev, "pxa2xx_spi_remove: workqueue will not "

1510

dev_err(&pdev->dev, "pxa2xx_spi_remove: workqueue will not "

1510

"complete, message memory not freed\n");

1511

"complete, message memory not freed\n");

1511

1512

/* Disable the SSP at the peripheral and SOC level */

1513

/* Disable the SSP at the peripheral and SOC level */

1513

write_SSCR0(0, drv_data->ioaddr);

1514

write_SSCR0(0, drv_data->ioaddr);

1514

pxa_set_cken(drv_data->master_info->clock_enable, 0);

1515

pxa_set_cken(drv_data->master_info->clock_enable, 0);

1515

1516

/* Release DMA */

1517

/* Release DMA */

1517

if (drv_data->master_info->enable_dma) {

1518

if (drv_data->master_info->enable_dma) {

1518

if (drv_data->ioaddr == SSP1_VIRT) {

1519

if (drv_data->ioaddr == SSP1_VIRT) {

1519

DRCMRRXSSDR = 0;

1520

DRCMRRXSSDR = 0;

1520

DRCMRTXSSDR = 0;

1521

DRCMRTXSSDR = 0;

1521

} else if (drv_data->ioaddr == SSP2_VIRT) {

1522

} else if (drv_data->ioaddr == SSP2_VIRT) {

1522

DRCMRRXSS2DR = 0;

1523

DRCMRRXSS2DR = 0;

1523

DRCMRTXSS2DR = 0;

1524

DRCMRTXSS2DR = 0;

1524

} else if (drv_data->ioaddr == SSP3_VIRT) {

1525

} else if (drv_data->ioaddr == SSP3_VIRT) {

1525

DRCMRRXSS3DR = 0;

1526

DRCMRRXSS3DR = 0;

1526

DRCMRTXSS3DR = 0;

1527

DRCMRTXSS3DR = 0;

1527

}

1528

}

1528

pxa_free_dma(drv_data->tx_channel);

1529

pxa_free_dma(drv_data->tx_channel);

1529

pxa_free_dma(drv_data->rx_channel);

1530

pxa_free_dma(drv_data->rx_channel);

1530

}

1531

}

1531

1532

/* Release IRQ */

1533

/* Release IRQ */

1533

irq = platform_get_irq(pdev, 0);

1534

irq = platform_get_irq(pdev, 0);

1534

if (irq >= 0)

1535

if (irq >= 0)

1535

free_irq(irq, drv_data);

1536

free_irq(irq, drv_data);

1536

1537

/* Disconnect from the SPI framework */

1538

/* Disconnect from the SPI framework */

1538

spi_unregister_master(drv_data->master);

1539

spi_unregister_master(drv_data->master);

1539

1540

/* Prevent double remove */

1541

/* Prevent double remove */

1541

platform_set_drvdata(pdev, NULL);

1542

platform_set_drvdata(pdev, NULL);

1542

1543

return 0;

1544

return 0;

1544

}

1545

}

1545

1546

static void pxa2xx_spi_shutdown(struct platform_device *pdev)

1547

static void pxa2xx_spi_shutdown(struct platform_device *pdev)

1547

{

1548

{

1548

int status = 0;

1549

int status = 0;

1549

1550

if ((status = pxa2xx_spi_remove(pdev)) != 0)

1551

if ((status = pxa2xx_spi_remove(pdev)) != 0)

1551

dev_err(&pdev->dev, "shutdown failed with %d\n", status);

1552

dev_err(&pdev->dev, "shutdown failed with %d\n", status);

1552

}

1553

}

1553

1554

#ifdef CONFIG_PM

1555

#ifdef CONFIG_PM

1555

static int suspend_devices(struct device *dev, void *pm_message)

1556

static int suspend_devices(struct device *dev, void *pm_message)

1556

{

1557

{

1557

pm_message_t *state = pm_message;

1558

pm_message_t *state = pm_message;

1558

1559

if (dev->power.power_state.event != state->event) {

1560

if (dev->power.power_state.event != state->event) {

1560

dev_warn(dev, "pm state does not match request\n");

1561

dev_warn(dev, "pm state does not match request\n");

1561

return -1;

1562

return -1;

1562

}

1563

}

1563

1564

return 0;

1565

return 0;

1565

}

1566

}

1566

1567

static int pxa2xx_spi_suspend(struct platform_device *pdev, pm_message_t state)

1568

static int pxa2xx_spi_suspend(struct platform_device *pdev, pm_message_t state)

1568

{

1569

{

1569

struct driver_data *drv_data = platform_get_drvdata(pdev);

1570

struct driver_data *drv_data = platform_get_drvdata(pdev);

1570

int status = 0;

1571

int status = 0;

1571

1572

/* Check all childern for current power state */

1573

/* Check all childern for current power state */

1573

if (device_for_each_child(&pdev->dev, &state, suspend_devices) != 0) {

1574

if (device_for_each_child(&pdev->dev, &state, suspend_devices) != 0) {

1574

dev_warn(&pdev->dev, "suspend aborted\n");

1575

dev_warn(&pdev->dev, "suspend aborted\n");

1575

return -1;

1576

return -1;

1576

}

1577

}

1577

1578

status = stop_queue(drv_data);

1579

status = stop_queue(drv_data);

1579

if (status != 0)

1580

if (status != 0)

1580

return status;

1581

return status;

1581

write_SSCR0(0, drv_data->ioaddr);

1582

write_SSCR0(0, drv_data->ioaddr);

1582

pxa_set_cken(drv_data->master_info->clock_enable, 0);

1583

pxa_set_cken(drv_data->master_info->clock_enable, 0);

1583

1584

return 0;

1585

return 0;

1585

}

1586

}

1586

1587

static int pxa2xx_spi_resume(struct platform_device *pdev)

1588

static int pxa2xx_spi_resume(struct platform_device *pdev)

1588

{

1589

{

1589

struct driver_data *drv_data = platform_get_drvdata(pdev);

1590

struct driver_data *drv_data = platform_get_drvdata(pdev);

1590

int status = 0;

1591

int status = 0;

1591

1592

/* Enable the SSP clock */

1593

/* Enable the SSP clock */

1593

pxa_set_cken(drv_data->master_info->clock_enable, 1);

1594

pxa_set_cken(drv_data->master_info->clock_enable, 1);

1594

1595

/* Start the queue running */

1596

/* Start the queue running */

1596

status = start_queue(drv_data);

1597

status = start_queue(drv_data);

1597

if (status != 0) {

1598

if (status != 0) {

1598

dev_err(&pdev->dev, "problem starting queue (%d)\n", status);

1599

dev_err(&pdev->dev, "problem starting queue (%d)\n", status);

1599

return status;

1600

return status;

1600

}

1601

}

1601

1602

return 0;

1603

return 0;

1603

}

1604

}

1604

#else

1605

#else

1605

#define pxa2xx_spi_suspend NULL

1606

#define pxa2xx_spi_suspend NULL

1606

#define pxa2xx_spi_resume NULL

1607

#define pxa2xx_spi_resume NULL

1607

#endif /* CONFIG_PM */

1608

#endif /* CONFIG_PM */

1608

1609

static struct platform_driver driver = {

1610

static struct platform_driver driver = {

1610

.driver = {

1611

.driver = {

1611

.name = "pxa2xx-spi",

1612

.name = "pxa2xx-spi",

1612

.bus = &platform_bus_type,

1613

.bus = &platform_bus_type,

1613

.owner = THIS_MODULE,

1614

.owner = THIS_MODULE,

1614

},

1615

},

1615

.probe = pxa2xx_spi_probe,

1616

.probe = pxa2xx_spi_probe,

1616

.remove = __devexit_p(pxa2xx_spi_remove),

1617

.remove = __devexit_p(pxa2xx_spi_remove),

1617

.shutdown = pxa2xx_spi_shutdown,

1618

.shutdown = pxa2xx_spi_shutdown,

1618

.suspend = pxa2xx_spi_suspend,

1619

.suspend = pxa2xx_spi_suspend,

1619

.resume = pxa2xx_spi_resume,

1620

.resume = pxa2xx_spi_resume,

1620

};

1621

};

1621

1622

static int __init pxa2xx_spi_init(void)

1623

static int __init pxa2xx_spi_init(void)

1623

{

1624

{

1624

platform_driver_register(&driver);

1625

platform_driver_register(&driver);

1625

1626

return 0;

1627

return 0;

1627

}

1628

}

1628

module_init(pxa2xx_spi_init);

1629

module_init(pxa2xx_spi_init);

1629

1630

static void __exit pxa2xx_spi_exit(void)

1631

static void __exit pxa2xx_spi_exit(void)

1631

{

1632

{

1632

platform_driver_unregister(&driver);

1633

platform_driver_unregister(&driver);

1633

}

1634

}

1634

module_exit(pxa2xx_spi_exit);

1635

module_exit(pxa2xx_spi_exit);

1635

1636

GITLAB

Eric Lee / linux-smarc-t335x-v3.2

[PATCH] spi: fix error setting the spi mode in pxa2xx_spi.c

 /*
  * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
  * (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  */
 #include <linux/init.h>
 #include <linux/module.h>
 #include <linux/device.h>
 #include <linux/ioport.h>
 #include <linux/errno.h>
 #include <linux/interrupt.h>
 #include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
 #include <linux/spi/spi.h>
 #include <linux/workqueue.h>
 #include <linux/errno.h>
 #include <linux/delay.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/hardware.h>
 #include <asm/delay.h>
 #include <asm/dma.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/pxa-regs.h>
 #include <asm/arch/pxa2xx_spi.h>
 MODULE_AUTHOR("Stephen Street");
 MODULE_DESCRIPTION("PXA2xx SSP SPI Contoller");
 MODULE_LICENSE("GPL");
 #define MAX_BUSES 3
 #define DMA_INT_MASK (DCSR_ENDINTR | DCSR_STARTINTR | DCSR_BUSERR)
 #define RESET_DMA_CHANNEL (DCSR_NODESC | DMA_INT_MASK)
 #define IS_DMA_ALIGNED(x) (((u32)(x)&0x07)==0)
 /* for testing SSCR1 changes that require SSP restart, basically
  * everything except the service and interrupt enables */
 #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_EBCEI | SSCR1_SCFR \
 				| SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
 				| SSCR1_RWOT | SSCR1_TRAIL | SSCR1_PINTE \
 				| SSCR1_STRF | SSCR1_EFWR |SSCR1_RFT \
 				| SSCR1_TFT | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
 #define DEFINE_SSP_REG(reg, off) \
 static inline u32 read_##reg(void *p) { return __raw_readl(p + (off)); } \
 static inline void write_##reg(u32 v, void *p) { __raw_writel(v, p + (off)); }
 DEFINE_SSP_REG(SSCR0, 0x00)
 DEFINE_SSP_REG(SSCR1, 0x04)
 DEFINE_SSP_REG(SSSR, 0x08)
 DEFINE_SSP_REG(SSITR, 0x0c)
 DEFINE_SSP_REG(SSDR, 0x10)
 DEFINE_SSP_REG(SSTO, 0x28)
 DEFINE_SSP_REG(SSPSP, 0x2c)
 #define START_STATE ((void*)0)
 #define RUNNING_STATE ((void*)1)
 #define DONE_STATE ((void*)2)
 #define ERROR_STATE ((void*)-1)
 #define QUEUE_RUNNING 0
 #define QUEUE_STOPPED 1
 struct driver_data {
 	/* Driver model hookup */
 	struct platform_device *pdev;
 	/* SPI framework hookup */
 	enum pxa_ssp_type ssp_type;
 	struct spi_master *master;
 	/* PXA hookup */
 	struct pxa2xx_spi_master *master_info;
 	/* DMA setup stuff */
 	int rx_channel;
 	int tx_channel;
 	u32 *null_dma_buf;
 	/* SSP register addresses */
 	void *ioaddr;
 	u32 ssdr_physical;
 	/* SSP masks*/
 	u32 dma_cr1;
 	u32 int_cr1;
 	u32 clear_sr;
 	u32 mask_sr;
 	/* Driver message queue */
 	struct workqueue_struct	*workqueue;
 	struct work_struct pump_messages;
 	spinlock_t lock;
 	struct list_head queue;
 	int busy;
 	int run;
 	/* Message Transfer pump */
 	struct tasklet_struct pump_transfers;
 	/* Current message transfer state info */
 	struct spi_message* cur_msg;
 	struct spi_transfer* cur_transfer;
 	struct chip_data *cur_chip;
 	size_t len;
 	void *tx;
 	void *tx_end;
 	void *rx;
 	void *rx_end;
 	int dma_mapped;
 	dma_addr_t rx_dma;
 	dma_addr_t tx_dma;
 	size_t rx_map_len;
 	size_t tx_map_len;
 	u8 n_bytes;
 	u32 dma_width;
 	int cs_change;
 	int (*write)(struct driver_data *drv_data);
 	int (*read)(struct driver_data *drv_data);
 	irqreturn_t (*transfer_handler)(struct driver_data *drv_data);
 	void (*cs_control)(u32 command);
 };
 struct chip_data {
 	u32 cr0;
 	u32 cr1;
 	u32 psp;
 	u32 timeout;
 	u8 n_bytes;
 	u32 dma_width;
 	u32 dma_burst_size;
 	u32 threshold;
 	u32 dma_threshold;
 	u8 enable_dma;
 	u8 bits_per_word;
 	u32 speed_hz;
 	int (*write)(struct driver_data *drv_data);
 	int (*read)(struct driver_data *drv_data);
 	void (*cs_control)(u32 command);
 };
 static void pump_messages(struct work_struct *work);
 static int flush(struct driver_data *drv_data)
 {
 	unsigned long limit = loops_per_jiffy << 1;
 	void *reg = drv_data->ioaddr;
 	do {
 		while (read_SSSR(reg) & SSSR_RNE) {
 			read_SSDR(reg);
 		}
 	} while ((read_SSSR(reg) & SSSR_BSY) && limit--);
 	write_SSSR(SSSR_ROR, reg);
 	return limit;
 }
 static void null_cs_control(u32 command)
 {
 }
 static int null_writer(struct driver_data *drv_data)
 {
 	void *reg = drv_data->ioaddr;
 	u8 n_bytes = drv_data->n_bytes;
 	if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00)
 		|| (drv_data->tx == drv_data->tx_end))
 		return 0;
 	write_SSDR(0, reg);
 	drv_data->tx += n_bytes;
 	return 1;
 }
 static int null_reader(struct driver_data *drv_data)
 {
 	void *reg = drv_data->ioaddr;
 	u8 n_bytes = drv_data->n_bytes;
 	while ((read_SSSR(reg) & SSSR_RNE)
 		&& (drv_data->rx < drv_data->rx_end)) {
 		read_SSDR(reg);
 		drv_data->rx += n_bytes;
 	}
 	return drv_data->rx == drv_data->rx_end;
 }
 static int u8_writer(struct driver_data *drv_data)
 {
 	void *reg = drv_data->ioaddr;
 	if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00)
 		|| (drv_data->tx == drv_data->tx_end))
 		return 0;
 	write_SSDR(*(u8 *)(drv_data->tx), reg);
 	++drv_data->tx;
 	return 1;
 }
 static int u8_reader(struct driver_data *drv_data)
 {
 	void *reg = drv_data->ioaddr;
 	while ((read_SSSR(reg) & SSSR_RNE)
 		&& (drv_data->rx < drv_data->rx_end)) {
 		*(u8 *)(drv_data->rx) = read_SSDR(reg);
 		++drv_data->rx;
 	}
 	return drv_data->rx == drv_data->rx_end;
 }
 static int u16_writer(struct driver_data *drv_data)
 {
 	void *reg = drv_data->ioaddr;
 	if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00)
 		|| (drv_data->tx == drv_data->tx_end))
 		return 0;
 	write_SSDR(*(u16 *)(drv_data->tx), reg);
 	drv_data->tx += 2;
 	return 1;
 }
 static int u16_reader(struct driver_data *drv_data)
 {
 	void *reg = drv_data->ioaddr;
 	while ((read_SSSR(reg) & SSSR_RNE)
 		&& (drv_data->rx < drv_data->rx_end)) {
 		*(u16 *)(drv_data->rx) = read_SSDR(reg);
 		drv_data->rx += 2;
 	}
 	return drv_data->rx == drv_data->rx_end;
 }
 static int u32_writer(struct driver_data *drv_data)
 {
 	void *reg = drv_data->ioaddr;
 	if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00)
 		|| (drv_data->tx == drv_data->tx_end))
 		return 0;
 	write_SSDR(*(u32 *)(drv_data->tx), reg);
 	drv_data->tx += 4;
 	return 1;
 }
 static int u32_reader(struct driver_data *drv_data)
 {
 	void *reg = drv_data->ioaddr;
 	while ((read_SSSR(reg) & SSSR_RNE)
 		&& (drv_data->rx < drv_data->rx_end)) {
 		*(u32 *)(drv_data->rx) = read_SSDR(reg);
 		drv_data->rx += 4;
 	}
 	return drv_data->rx == drv_data->rx_end;
 }
 static void *next_transfer(struct driver_data *drv_data)
 {
 	struct spi_message *msg = drv_data->cur_msg;
 	struct spi_transfer *trans = drv_data->cur_transfer;
 	/* Move to next transfer */
 	if (trans->transfer_list.next != &msg->transfers) {
 		drv_data->cur_transfer =
 			list_entry(trans->transfer_list.next,
 					struct spi_transfer,
 					transfer_list);
 		return RUNNING_STATE;
 	} else
 		return DONE_STATE;
 }
 static int map_dma_buffers(struct driver_data *drv_data)
 {
 	struct spi_message *msg = drv_data->cur_msg;
 	struct device *dev = &msg->spi->dev;
 	if (!drv_data->cur_chip->enable_dma)
 		return 0;
 	if (msg->is_dma_mapped)
 		return  drv_data->rx_dma && drv_data->tx_dma;
 	if (!IS_DMA_ALIGNED(drv_data->rx) || !IS_DMA_ALIGNED(drv_data->tx))
 		return 0;
 	/* Modify setup if rx buffer is null */
 	if (drv_data->rx == NULL) {
 		*drv_data->null_dma_buf = 0;
 		drv_data->rx = drv_data->null_dma_buf;
 		drv_data->rx_map_len = 4;
 	} else
 		drv_data->rx_map_len = drv_data->len;
 	/* Modify setup if tx buffer is null */
 	if (drv_data->tx == NULL) {
 		*drv_data->null_dma_buf = 0;
 		drv_data->tx = drv_data->null_dma_buf;
 		drv_data->tx_map_len = 4;
 	} else
 		drv_data->tx_map_len = drv_data->len;
 	/* Stream map the rx buffer */
 	drv_data->rx_dma = dma_map_single(dev, drv_data->rx,
 						drv_data->rx_map_len,
 						DMA_FROM_DEVICE);
 	if (dma_mapping_error(drv_data->rx_dma))
 		return 0;
 	/* Stream map the tx buffer */
 	drv_data->tx_dma = dma_map_single(dev, drv_data->tx,
 						drv_data->tx_map_len,
 						DMA_TO_DEVICE);
 	if (dma_mapping_error(drv_data->tx_dma)) {
 		dma_unmap_single(dev, drv_data->rx_dma,
 					drv_data->rx_map_len, DMA_FROM_DEVICE);
 		return 0;
 	}
 	return 1;
 }
 static void unmap_dma_buffers(struct driver_data *drv_data)
 {
 	struct device *dev;
 	if (!drv_data->dma_mapped)
 		return;
 	if (!drv_data->cur_msg->is_dma_mapped) {
 		dev = &drv_data->cur_msg->spi->dev;
 		dma_unmap_single(dev, drv_data->rx_dma,
 					drv_data->rx_map_len, DMA_FROM_DEVICE);
 		dma_unmap_single(dev, drv_data->tx_dma,
 					drv_data->tx_map_len, DMA_TO_DEVICE);
 	}
 	drv_data->dma_mapped = 0;
 }
 /* caller already set message->status; dma and pio irqs are blocked */
 static void giveback(struct driver_data *drv_data)
 {
 	struct spi_transfer* last_transfer;
 	unsigned long flags;
 	struct spi_message *msg;
 	spin_lock_irqsave(&drv_data->lock, flags);
 	msg = drv_data->cur_msg;
 	drv_data->cur_msg = NULL;
 	drv_data->cur_transfer = NULL;
 	drv_data->cur_chip = NULL;
 	queue_work(drv_data->workqueue, &drv_data->pump_messages);
 	spin_unlock_irqrestore(&drv_data->lock, flags);
 	last_transfer = list_entry(msg->transfers.prev,
 					struct spi_transfer,
 					transfer_list);
 	if (!last_transfer->cs_change)
 		drv_data->cs_control(PXA2XX_CS_DEASSERT);
 	msg->state = NULL;
 	if (msg->complete)
 		msg->complete(msg->context);
 }
 static int wait_ssp_rx_stall(void *ioaddr)
 {
 	unsigned long limit = loops_per_jiffy << 1;
 	while ((read_SSSR(ioaddr) & SSSR_BSY) && limit--)
 		cpu_relax();
 	return limit;
 }
 static int wait_dma_channel_stop(int channel)
 {
 	unsigned long limit = loops_per_jiffy << 1;
 	while (!(DCSR(channel) & DCSR_STOPSTATE) && limit--)
 		cpu_relax();
 	return limit;
 }
 void dma_error_stop(struct driver_data *drv_data, const char *msg)
 {
 	void *reg = drv_data->ioaddr;
 	/* Stop and reset */
 	DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
 	DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
 	write_SSSR(drv_data->clear_sr, reg);
 	write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg);
 	if (drv_data->ssp_type != PXA25x_SSP)
 		write_SSTO(0, reg);
 	flush(drv_data);
 	write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
 	unmap_dma_buffers(drv_data);
 	dev_err(&drv_data->pdev->dev, "%s\n", msg);
 	drv_data->cur_msg->state = ERROR_STATE;
 	tasklet_schedule(&drv_data->pump_transfers);
 }
 static void dma_transfer_complete(struct driver_data *drv_data)
 {
 	void *reg = drv_data->ioaddr;
 	struct spi_message *msg = drv_data->cur_msg;
 	/* Clear and disable interrupts on SSP and DMA channels*/
 	write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg);
 	write_SSSR(drv_data->clear_sr, reg);
 	DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
 	DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
 	if (wait_dma_channel_stop(drv_data->rx_channel) == 0)
 		dev_err(&drv_data->pdev->dev,
 			"dma_handler: dma rx channel stop failed\n");
 	if (wait_ssp_rx_stall(drv_data->ioaddr) == 0)
 		dev_err(&drv_data->pdev->dev,
 			"dma_transfer: ssp rx stall failed\n");
 	unmap_dma_buffers(drv_data);
 	/* update the buffer pointer for the amount completed in dma */
 	drv_data->rx += drv_data->len -
 			(DCMD(drv_data->rx_channel) & DCMD_LENGTH);
 	/* read trailing data from fifo, it does not matter how many
 	 * bytes are in the fifo just read until buffer is full
 	 * or fifo is empty, which ever occurs first */
 	drv_data->read(drv_data);
 	/* return count of what was actually read */
 	msg->actual_length += drv_data->len -
 				(drv_data->rx_end - drv_data->rx);
 	/* Release chip select if requested, transfer delays are
 	 * handled in pump_transfers */
 	if (drv_data->cs_change)
 		drv_data->cs_control(PXA2XX_CS_DEASSERT);
 	/* Move to next transfer */
 	msg->state = next_transfer(drv_data);
 	/* Schedule transfer tasklet */
 	tasklet_schedule(&drv_data->pump_transfers);
 }
 static void dma_handler(int channel, void *data)
 {
 	struct driver_data *drv_data = data;
 	u32 irq_status = DCSR(channel) & DMA_INT_MASK;
 	if (irq_status & DCSR_BUSERR) {
 		if (channel == drv_data->tx_channel)
 			dma_error_stop(drv_data,
 					"dma_handler: "
 					"bad bus address on tx channel");
 		else
 			dma_error_stop(drv_data,
 					"dma_handler: "
 					"bad bus address on rx channel");
 		return;
 	}
 	/* PXA255x_SSP has no timeout interrupt, wait for tailing bytes */
 	if ((channel == drv_data->tx_channel)
 		&& (irq_status & DCSR_ENDINTR)
 		&& (drv_data->ssp_type == PXA25x_SSP)) {
 		/* Wait for rx to stall */
 		if (wait_ssp_rx_stall(drv_data->ioaddr) == 0)
 			dev_err(&drv_data->pdev->dev,
 				"dma_handler: ssp rx stall failed\n");
 		/* finish this transfer, start the next */
 		dma_transfer_complete(drv_data);
 	}
 }
 static irqreturn_t dma_transfer(struct driver_data *drv_data)
 {
 	u32 irq_status;
 	void *reg = drv_data->ioaddr;
 	irq_status = read_SSSR(reg) & drv_data->mask_sr;
 	if (irq_status & SSSR_ROR) {
 		dma_error_stop(drv_data, "dma_transfer: fifo overrun");
 		return IRQ_HANDLED;
 	}
 	/* Check for false positive timeout */
 	if ((irq_status & SSSR_TINT)
 		&& (DCSR(drv_data->tx_channel) & DCSR_RUN)) {
 		write_SSSR(SSSR_TINT, reg);
 		return IRQ_HANDLED;
 	}
 	if (irq_status & SSSR_TINT || drv_data->rx == drv_data->rx_end) {
 		/* Clear and disable timeout interrupt, do the rest in
 		 * dma_transfer_complete */
 		if (drv_data->ssp_type != PXA25x_SSP)
 			write_SSTO(0, reg);
 		/* finish this transfer, start the next */
 		dma_transfer_complete(drv_data);
 		return IRQ_HANDLED;
 	}
 	/* Opps problem detected */
 	return IRQ_NONE;
 }
 static void int_error_stop(struct driver_data *drv_data, const char* msg)
 {
 	void *reg = drv_data->ioaddr;
 	/* Stop and reset SSP */
 	write_SSSR(drv_data->clear_sr, reg);
 	write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
 	if (drv_data->ssp_type != PXA25x_SSP)
 		write_SSTO(0, reg);
 	flush(drv_data);
 	write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
 	dev_err(&drv_data->pdev->dev, "%s\n", msg);
 	drv_data->cur_msg->state = ERROR_STATE;
 	tasklet_schedule(&drv_data->pump_transfers);
 }
 static void int_transfer_complete(struct driver_data *drv_data)
 {
 	void *reg = drv_data->ioaddr;
 	/* Stop SSP */
 	write_SSSR(drv_data->clear_sr, reg);
 	write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
 	if (drv_data->ssp_type != PXA25x_SSP)
 		write_SSTO(0, reg);
 	/* Update total byte transfered return count actual bytes read */
 	drv_data->cur_msg->actual_length += drv_data->len -
 				(drv_data->rx_end - drv_data->rx);
 	/* Release chip select if requested, transfer delays are
 	 * handled in pump_transfers */
 	if (drv_data->cs_change)
 		drv_data->cs_control(PXA2XX_CS_DEASSERT);
 	/* Move to next transfer */
 	drv_data->cur_msg->state = next_transfer(drv_data);
 	/* Schedule transfer tasklet */
 	tasklet_schedule(&drv_data->pump_transfers);
 }
 static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
 {
 	void *reg = drv_data->ioaddr;
 	u32 irq_mask = (read_SSCR1(reg) & SSCR1_TIE) ?
 			drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
 	u32 irq_status = read_SSSR(reg) & irq_mask;
 	if (irq_status & SSSR_ROR) {
 		int_error_stop(drv_data, "interrupt_transfer: fifo overrun");
 		return IRQ_HANDLED;
 	}
 	if (irq_status & SSSR_TINT) {
 		write_SSSR(SSSR_TINT, reg);
 		if (drv_data->read(drv_data)) {
 			int_transfer_complete(drv_data);
 			return IRQ_HANDLED;
 		}
 	}
 	/* Drain rx fifo, Fill tx fifo and prevent overruns */
 	do {
 		if (drv_data->read(drv_data)) {
 			int_transfer_complete(drv_data);
 			return IRQ_HANDLED;
 		}
 	} while (drv_data->write(drv_data));
 	if (drv_data->read(drv_data)) {
 		int_transfer_complete(drv_data);
 		return IRQ_HANDLED;
 	}
 	if (drv_data->tx == drv_data->tx_end) {
 		write_SSCR1(read_SSCR1(reg) & ~SSCR1_TIE, reg);
 		/* PXA25x_SSP has no timeout, read trailing bytes */
 		if (drv_data->ssp_type == PXA25x_SSP) {
 			if (!wait_ssp_rx_stall(reg))
 			{
 				int_error_stop(drv_data, "interrupt_transfer: "
 						"rx stall failed");
 				return IRQ_HANDLED;
 			}
 			if (!drv_data->read(drv_data))
 			{
 				int_error_stop(drv_data,
 						"interrupt_transfer: "
 						"trailing byte read failed");
 				return IRQ_HANDLED;
 			}
 			int_transfer_complete(drv_data);
 		}
 	}
 	/* We did something */
 	return IRQ_HANDLED;
 }
 static irqreturn_t ssp_int(int irq, void *dev_id)
 {
 	struct driver_data *drv_data = dev_id;
 	void *reg = drv_data->ioaddr;
 	if (!drv_data->cur_msg) {
 		write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
 		write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
 		if (drv_data->ssp_type != PXA25x_SSP)
 			write_SSTO(0, reg);
 		write_SSSR(drv_data->clear_sr, reg);
 		dev_err(&drv_data->pdev->dev, "bad message state "
 			"in interrupt handler\n");
 		/* Never fail */
 		return IRQ_HANDLED;
 	}
 	return drv_data->transfer_handler(drv_data);
 }
 int set_dma_burst_and_threshold(struct chip_data *chip, struct spi_device *spi,
 				u8 bits_per_word, u32 *burst_code,
 				u32 *threshold)
 {
 	struct pxa2xx_spi_chip *chip_info =
 			(struct pxa2xx_spi_chip *)spi->controller_data;
 	int bytes_per_word;
 	int burst_bytes;
 	int thresh_words;
 	int req_burst_size;
 	int retval = 0;
 	/* Set the threshold (in registers) to equal the same amount of data
 	 * as represented by burst size (in bytes).  The computation below
 	 * is (burst_size rounded up to nearest 8 byte, word or long word)
 	 * divided by (bytes/register); the tx threshold is the inverse of
 	 * the rx, so that there will always be enough data in the rx fifo
 	 * to satisfy a burst, and there will always be enough space in the
 	 * tx fifo to accept a burst (a tx burst will overwrite the fifo if
 	 * there is not enough space), there must always remain enough empty
 	 * space in the rx fifo for any data loaded to the tx fifo.
 	 * Whenever burst_size (in bytes) equals bits/word, the fifo threshold
 	 * will be 8, or half the fifo;
 	 * The threshold can only be set to 2, 4 or 8, but not 16, because
 	 * to burst 16 to the tx fifo, the fifo would have to be empty;
 	 * however, the minimum fifo trigger level is 1, and the tx will
 	 * request service when the fifo is at this level, with only 15 spaces.
 	 */
 	/* find bytes/word */
 	if (bits_per_word <= 8)
 		bytes_per_word = 1;
 	else if (bits_per_word <= 16)
 		bytes_per_word = 2;
 	else
 		bytes_per_word = 4;
 	/* use struct pxa2xx_spi_chip->dma_burst_size if available */
 	if (chip_info)
 		req_burst_size = chip_info->dma_burst_size;
 	else {
 		switch (chip->dma_burst_size) {
 		default:
 			/* if the default burst size is not set,
 			 * do it now */
 			chip->dma_burst_size = DCMD_BURST8;
 		case DCMD_BURST8:
 			req_burst_size = 8;
 			break;
 		case DCMD_BURST16:
 			req_burst_size = 16;
 			break;
 		case DCMD_BURST32:
 			req_burst_size = 32;
 			break;
 		}
 	}
 	if (req_burst_size <= 8) {
 		*burst_code = DCMD_BURST8;
 		burst_bytes = 8;
 	} else if (req_burst_size <= 16) {
 		if (bytes_per_word == 1) {
 			/* don't burst more than 1/2 the fifo */
 			*burst_code = DCMD_BURST8;
 			burst_bytes = 8;
 			retval = 1;
 		} else {
 			*burst_code = DCMD_BURST16;
 			burst_bytes = 16;
 		}
 	} else {
 		if (bytes_per_word == 1) {
 			/* don't burst more than 1/2 the fifo */
 			*burst_code = DCMD_BURST8;
 			burst_bytes = 8;
 			retval = 1;
 		} else if (bytes_per_word == 2) {
 			/* don't burst more than 1/2 the fifo */
 			*burst_code = DCMD_BURST16;
 			burst_bytes = 16;
 			retval = 1;
 		} else {
 			*burst_code = DCMD_BURST32;
 			burst_bytes = 32;
 		}
 	}
 	thresh_words = burst_bytes / bytes_per_word;
 	/* thresh_words will be between 2 and 8 */
 	*threshold = (SSCR1_RxTresh(thresh_words) & SSCR1_RFT)
 			| (SSCR1_TxTresh(16-thresh_words) & SSCR1_TFT);
 	return retval;
 }
 static void pump_transfers(unsigned long data)
 {
 	struct driver_data *drv_data = (struct driver_data *)data;
 	struct spi_message *message = NULL;
 	struct spi_transfer *transfer = NULL;
 	struct spi_transfer *previous = NULL;
 	struct chip_data *chip = NULL;
 	void *reg = drv_data->ioaddr;
 	u32 clk_div = 0;
 	u8 bits = 0;
 	u32 speed = 0;
 	u32 cr0;
 	u32 cr1;
 	u32 dma_thresh = drv_data->cur_chip->dma_threshold;
 	u32 dma_burst = drv_data->cur_chip->dma_burst_size;
 	/* Get current state information */
 	message = drv_data->cur_msg;
 	transfer = drv_data->cur_transfer;
 	chip = drv_data->cur_chip;
 	/* Handle for abort */
 	if (message->state == ERROR_STATE) {
 		message->status = -EIO;
 		giveback(drv_data);
 		return;
 	}
 	/* Handle end of message */
 	if (message->state == DONE_STATE) {
 		message->status = 0;
 		giveback(drv_data);
 		return;
 	}
 	/* Delay if requested at end of transfer*/
 	if (message->state == RUNNING_STATE) {
 		previous = list_entry(transfer->transfer_list.prev,
 					struct spi_transfer,
 					transfer_list);
 		if (previous->delay_usecs)
 			udelay(previous->delay_usecs);
 	}
 	/* Check transfer length */
 	if (transfer->len > 8191)
 	{
 		dev_warn(&drv_data->pdev->dev, "pump_transfers: transfer "
 				"length greater than 8191\n");
 		message->status = -EINVAL;
 		giveback(drv_data);
 		return;
 	}
 	/* Setup the transfer state based on the type of transfer */
 	if (flush(drv_data) == 0) {
 		dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
 		message->status = -EIO;
 		giveback(drv_data);
 		return;
 	}
 	drv_data->n_bytes = chip->n_bytes;
 	drv_data->dma_width = chip->dma_width;
 	drv_data->cs_control = chip->cs_control;
 	drv_data->tx = (void *)transfer->tx_buf;
 	drv_data->tx_end = drv_data->tx + transfer->len;
 	drv_data->rx = transfer->rx_buf;
 	drv_data->rx_end = drv_data->rx + transfer->len;
 	drv_data->rx_dma = transfer->rx_dma;
 	drv_data->tx_dma = transfer->tx_dma;
 	drv_data->len = transfer->len & DCMD_LENGTH;
 	drv_data->write = drv_data->tx ? chip->write : null_writer;
 	drv_data->read = drv_data->rx ? chip->read : null_reader;
 	drv_data->cs_change = transfer->cs_change;
 	/* Change speed and bit per word on a per transfer */
 	cr0 = chip->cr0;
 	if (transfer->speed_hz || transfer->bits_per_word) {
 		bits = chip->bits_per_word;
 		speed = chip->speed_hz;
 		if (transfer->speed_hz)
 			speed = transfer->speed_hz;
 		if (transfer->bits_per_word)
 			bits = transfer->bits_per_word;
 		if (reg == SSP1_VIRT)
 			clk_div = SSP1_SerClkDiv(speed);
 		else if (reg == SSP2_VIRT)
 			clk_div = SSP2_SerClkDiv(speed);
 		else if (reg == SSP3_VIRT)
 			clk_div = SSP3_SerClkDiv(speed);
 		if (bits <= 8) {
 			drv_data->n_bytes = 1;
 			drv_data->dma_width = DCMD_WIDTH1;
 			drv_data->read = drv_data->read != null_reader ?
 						u8_reader : null_reader;
 			drv_data->write = drv_data->write != null_writer ?
 						u8_writer : null_writer;
 		} else if (bits <= 16) {
 			drv_data->n_bytes = 2;
 			drv_data->dma_width = DCMD_WIDTH2;
 			drv_data->read = drv_data->read != null_reader ?
 						u16_reader : null_reader;
 			drv_data->write = drv_data->write != null_writer ?
 						u16_writer : null_writer;
 		} else if (bits <= 32) {
 			drv_data->n_bytes = 4;
 			drv_data->dma_width = DCMD_WIDTH4;
 			drv_data->read = drv_data->read != null_reader ?
 						u32_reader : null_reader;
 			drv_data->write = drv_data->write != null_writer ?
 						u32_writer : null_writer;
 		}
 		/* if bits/word is changed in dma mode, then must check the
 		 * thresholds and burst also */
 		if (chip->enable_dma) {
 			if (set_dma_burst_and_threshold(chip, message->spi,
 							bits, &dma_burst,
 							&dma_thresh))
 				if (printk_ratelimit())
 					dev_warn(&message->spi->dev,
 						"pump_transfer: "
 						"DMA burst size reduced to "
 						"match bits_per_word\n");
 		}
 		cr0 = clk_div
 			| SSCR0_Motorola
 			| SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
 			| SSCR0_SSE
 			| (bits > 16 ? SSCR0_EDSS : 0);
 	}
 	message->state = RUNNING_STATE;
 	/* Try to map dma buffer and do a dma transfer if successful */
 	if ((drv_data->dma_mapped = map_dma_buffers(drv_data))) {
 		/* Ensure we have the correct interrupt handler */
 		drv_data->transfer_handler = dma_transfer;
 		/* Setup rx DMA Channel */
 		DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
 		DSADR(drv_data->rx_channel) = drv_data->ssdr_physical;
 		DTADR(drv_data->rx_channel) = drv_data->rx_dma;
 		if (drv_data->rx == drv_data->null_dma_buf)
 			/* No target address increment */
 			DCMD(drv_data->rx_channel) = DCMD_FLOWSRC
 							| drv_data->dma_width
 							| dma_burst
 							| drv_data->len;
 		else
 			DCMD(drv_data->rx_channel) = DCMD_INCTRGADDR
 							| DCMD_FLOWSRC
 							| drv_data->dma_width
 							| dma_burst
 							| drv_data->len;
 		/* Setup tx DMA Channel */
 		DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
 		DSADR(drv_data->tx_channel) = drv_data->tx_dma;
 		DTADR(drv_data->tx_channel) = drv_data->ssdr_physical;
 		if (drv_data->tx == drv_data->null_dma_buf)
 			/* No source address increment */
 			DCMD(drv_data->tx_channel) = DCMD_FLOWTRG
 							| drv_data->dma_width
 							| dma_burst
 							| drv_data->len;
 		else
 			DCMD(drv_data->tx_channel) = DCMD_INCSRCADDR
 							| DCMD_FLOWTRG
 							| drv_data->dma_width
 							| dma_burst
 							| drv_data->len;
 		/* Enable dma end irqs on SSP to detect end of transfer */
 		if (drv_data->ssp_type == PXA25x_SSP)
 			DCMD(drv_data->tx_channel) |= DCMD_ENDIRQEN;
 		/* Fix me, need to handle cs polarity */
 		drv_data->cs_control(PXA2XX_CS_ASSERT);
 		/* Clear status and start DMA engine */
 		cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
 		write_SSSR(drv_data->clear_sr, reg);
 		DCSR(drv_data->rx_channel) |= DCSR_RUN;
 		DCSR(drv_data->tx_channel) |= DCSR_RUN;
 	} else {
 		/* Ensure we have the correct interrupt handler	*/
 		drv_data->transfer_handler = interrupt_transfer;
 		/* Fix me, need to handle cs polarity */
 		drv_data->cs_control(PXA2XX_CS_ASSERT);
 		/* Clear status  */
 		cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
 		write_SSSR(drv_data->clear_sr, reg);
 	}
 	/* see if we need to reload the config registers */
 	if ((read_SSCR0(reg) != cr0)
 		|| (read_SSCR1(reg) & SSCR1_CHANGE_MASK) !=
 			(cr1 & SSCR1_CHANGE_MASK)) {
 		write_SSCR0(cr0 & ~SSCR0_SSE, reg);
 		if (drv_data->ssp_type != PXA25x_SSP)
 			write_SSTO(chip->timeout, reg);
 		write_SSCR1(cr1, reg);
 		write_SSCR0(cr0, reg);
 	} else {
 		if (drv_data->ssp_type != PXA25x_SSP)
 			write_SSTO(chip->timeout, reg);
 		write_SSCR1(cr1, reg);
 	}
 }
 static void pump_messages(struct work_struct *work)
 {
 	struct driver_data *drv_data =
 		container_of(work, struct driver_data, pump_messages);
 	unsigned long flags;
 	/* Lock queue and check for queue work */
 	spin_lock_irqsave(&drv_data->lock, flags);
 	if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) {
 		drv_data->busy = 0;
 		spin_unlock_irqrestore(&drv_data->lock, flags);
 		return;
 	}
 	/* Make sure we are not already running a message */
 	if (drv_data->cur_msg) {
 		spin_unlock_irqrestore(&drv_data->lock, flags);
 		return;
 	}
 	/* Extract head of queue */
 	drv_data->cur_msg = list_entry(drv_data->queue.next,
 					struct spi_message, queue);
 	list_del_init(&drv_data->cur_msg->queue);
 	/* Initial message state*/
 	drv_data->cur_msg->state = START_STATE;
 	drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
 						struct spi_transfer,
 						transfer_list);
 	/* prepare to setup the SSP, in pump_transfers, using the per
 	 * chip configuration */
 	drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
 	/* Mark as busy and launch transfers */
 	tasklet_schedule(&drv_data->pump_transfers);
 	drv_data->busy = 1;
 	spin_unlock_irqrestore(&drv_data->lock, flags);
 }
 static int transfer(struct spi_device *spi, struct spi_message *msg)
 {
 	struct driver_data *drv_data = spi_master_get_devdata(spi->master);
 	unsigned long flags;
 	spin_lock_irqsave(&drv_data->lock, flags);
 	if (drv_data->run == QUEUE_STOPPED) {
 		spin_unlock_irqrestore(&drv_data->lock, flags);
 		return -ESHUTDOWN;
 	}
 	msg->actual_length = 0;
 	msg->status = -EINPROGRESS;
 	msg->state = START_STATE;
 	list_add_tail(&msg->queue, &drv_data->queue);
 	if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)
 		queue_work(drv_data->workqueue, &drv_data->pump_messages);
 	spin_unlock_irqrestore(&drv_data->lock, flags);
 	return 0;
 }
 static int setup(struct spi_device *spi)
 {
 	struct pxa2xx_spi_chip *chip_info = NULL;
 	struct chip_data *chip;
 	struct driver_data *drv_data = spi_master_get_devdata(spi->master);
 	unsigned int clk_div;
 	if (!spi->bits_per_word)
 		spi->bits_per_word = 8;
 	if (drv_data->ssp_type != PXA25x_SSP
 		&& (spi->bits_per_word < 4 || spi->bits_per_word > 32)) {
 		dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d "
 				"b/w not 4-32 for type non-PXA25x_SSP\n",
 				drv_data->ssp_type, spi->bits_per_word);
 		return -EINVAL;
 	}
 	else if (drv_data->ssp_type == PXA25x_SSP
 			&& (spi->bits_per_word < 4
 				|| spi->bits_per_word > 16)) {
 		dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d "
 				"b/w not 4-16 for type PXA25x_SSP\n",
 				drv_data->ssp_type, spi->bits_per_word);
 		return -EINVAL;
 	}
 	/* Only alloc on first setup */
 	chip = spi_get_ctldata(spi);
 	if (!chip) {
 		chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
 		if (!chip) {
 			dev_err(&spi->dev,
 				"failed setup: can't allocate chip data\n");
 			return -ENOMEM;
 		}
 		chip->cs_control = null_cs_control;
 		chip->enable_dma = 0;
 		chip->timeout = 1000;
 		chip->threshold = SSCR1_RxTresh(1) | SSCR1_TxTresh(1);
 		chip->dma_burst_size = drv_data->master_info->enable_dma ?
 					DCMD_BURST8 : 0;
 	}
 	/* protocol drivers may change the chip settings, so...
 	 * if chip_info exists, use it */
 	chip_info = spi->controller_data;
 	/* chip_info isn't always needed */
 	chip->cr1 = 0;
 	if (chip_info) {
 		if (chip_info->cs_control)
 			chip->cs_control = chip_info->cs_control;
 		chip->timeout = chip_info->timeout;
 		chip->threshold = (SSCR1_RxTresh(chip_info->rx_threshold) &
 								SSCR1_RFT) |
 				(SSCR1_TxTresh(chip_info->tx_threshold) &
 								SSCR1_TFT);
 		chip->enable_dma = chip_info->dma_burst_size != 0
 					&& drv_data->master_info->enable_dma;
 		chip->dma_threshold = 0;
 		if (chip_info->enable_loopback)
 			chip->cr1 = SSCR1_LBM;
 	}
 	/* set dma burst and threshold outside of chip_info path so that if
 	 * chip_info goes away after setting chip->enable_dma, the
 	 * burst and threshold can still respond to changes in bits_per_word */
 	if (chip->enable_dma) {
 		/* set up legal burst and threshold for dma */
 		if (set_dma_burst_and_threshold(chip, spi, spi->bits_per_word,
 						&chip->dma_burst_size,
 						&chip->dma_threshold)) {
 			dev_warn(&spi->dev, "in setup: DMA burst size reduced "
 					"to match bits_per_word\n");
 		}
 	}
 	if (drv_data->ioaddr == SSP1_VIRT)
 		clk_div = SSP1_SerClkDiv(spi->max_speed_hz);
 	else if (drv_data->ioaddr == SSP2_VIRT)
 		clk_div = SSP2_SerClkDiv(spi->max_speed_hz);
 	else if (drv_data->ioaddr == SSP3_VIRT)
 		clk_div = SSP3_SerClkDiv(spi->max_speed_hz);
 	else
 	{
 		dev_err(&spi->dev, "failed setup: unknown IO address=0x%p\n",
 			drv_data->ioaddr);
 		return -ENODEV;
 	}
 	chip->speed_hz = spi->max_speed_hz;
 	chip->cr0 = clk_div
 			| SSCR0_Motorola
 			| SSCR0_DataSize(spi->bits_per_word > 16 ?
 				spi->bits_per_word - 16 : spi->bits_per_word)
 			| SSCR0_SSE
 			| (spi->bits_per_word > 16 ? SSCR0_EDSS : 0);
-	chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) << 4)
+	chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
-			| (((spi->mode & SPI_CPOL) != 0) << 3);
+	chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
+			| (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
 	/* NOTE:  PXA25x_SSP _could_ use external clocking ... */
 	if (drv_data->ssp_type != PXA25x_SSP)
 		dev_dbg(&spi->dev, "%d bits/word, %d Hz, mode %d\n",
 				spi->bits_per_word,
 				(CLOCK_SPEED_HZ)
 					/ (1 + ((chip->cr0 & SSCR0_SCR) >> 8)),
 				spi->mode & 0x3);
 	else
 		dev_dbg(&spi->dev, "%d bits/word, %d Hz, mode %d\n",
 				spi->bits_per_word,
 				(CLOCK_SPEED_HZ/2)
 					/ (1 + ((chip->cr0 & SSCR0_SCR) >> 8)),
 				spi->mode & 0x3);
 	if (spi->bits_per_word <= 8) {
 		chip->n_bytes = 1;
 		chip->dma_width = DCMD_WIDTH1;
 		chip->read = u8_reader;
 		chip->write = u8_writer;
 	} else if (spi->bits_per_word <= 16) {
 		chip->n_bytes = 2;
 		chip->dma_width = DCMD_WIDTH2;
 		chip->read = u16_reader;
 		chip->write = u16_writer;
 	} else if (spi->bits_per_word <= 32) {
 		chip->cr0 |= SSCR0_EDSS;
 		chip->n_bytes = 4;
 		chip->dma_width = DCMD_WIDTH4;
 		chip->read = u32_reader;
 		chip->write = u32_writer;
 	} else {
 		dev_err(&spi->dev, "invalid wordsize\n");
 		return -ENODEV;
 	}
 	chip->bits_per_word = spi->bits_per_word;
 	spi_set_ctldata(spi, chip);
 	return 0;
 }
 static void cleanup(const struct spi_device *spi)
 {
 	struct chip_data *chip = spi_get_ctldata((struct spi_device *)spi);
 	kfree(chip);
 }
 static int init_queue(struct driver_data *drv_data)
 {
 	INIT_LIST_HEAD(&drv_data->queue);
 	spin_lock_init(&drv_data->lock);
 	drv_data->run = QUEUE_STOPPED;
 	drv_data->busy = 0;
 	tasklet_init(&drv_data->pump_transfers,
 			pump_transfers,	(unsigned long)drv_data);
 	INIT_WORK(&drv_data->pump_messages, pump_messages);
 	drv_data->workqueue = create_singlethread_workqueue(
 					drv_data->master->cdev.dev->bus_id);
 	if (drv_data->workqueue == NULL)
 		return -EBUSY;
 	return 0;
 }
 static int start_queue(struct driver_data *drv_data)
 {
 	unsigned long flags;
 	spin_lock_irqsave(&drv_data->lock, flags);
 	if (drv_data->run == QUEUE_RUNNING || drv_data->busy) {
 		spin_unlock_irqrestore(&drv_data->lock, flags);
 		return -EBUSY;
 	}
 	drv_data->run = QUEUE_RUNNING;
 	drv_data->cur_msg = NULL;
 	drv_data->cur_transfer = NULL;
 	drv_data->cur_chip = NULL;
 	spin_unlock_irqrestore(&drv_data->lock, flags);
 	queue_work(drv_data->workqueue, &drv_data->pump_messages);
 	return 0;
 }
 static int stop_queue(struct driver_data *drv_data)
 {
 	unsigned long flags;
 	unsigned limit = 500;
 	int status = 0;
 	spin_lock_irqsave(&drv_data->lock, flags);
 	/* This is a bit lame, but is optimized for the common execution path.
 	 * A wait_queue on the drv_data->busy could be used, but then the common
 	 * execution path (pump_messages) would be required to call wake_up or
 	 * friends on every SPI message. Do this instead */
 	drv_data->run = QUEUE_STOPPED;
 	while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
 		spin_unlock_irqrestore(&drv_data->lock, flags);
 		msleep(10);
 		spin_lock_irqsave(&drv_data->lock, flags);
 	}
 	if (!list_empty(&drv_data->queue) || drv_data->busy)
 		status = -EBUSY;
 	spin_unlock_irqrestore(&drv_data->lock, flags);
 	return status;
 }
 static int destroy_queue(struct driver_data *drv_data)
 {
 	int status;
 	status = stop_queue(drv_data);
 	/* we are unloading the module or failing to load (only two calls
 	 * to this routine), and neither call can handle a return value.
 	 * However, destroy_workqueue calls flush_workqueue, and that will
 	 * block until all work is done.  If the reason that stop_queue
 	 * timed out is that the work will never finish, then it does no
 	 * good to call destroy_workqueue, so return anyway. */
 	if (status != 0)
 		return status;
 	destroy_workqueue(drv_data->workqueue);
 	return 0;
 }
 static int pxa2xx_spi_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
 	struct pxa2xx_spi_master *platform_info;
 	struct spi_master *master;
 	struct driver_data *drv_data = 0;
 	struct resource *memory_resource;
 	int irq;
 	int status = 0;
 	platform_info = dev->platform_data;
 	if (platform_info->ssp_type == SSP_UNDEFINED) {
 		dev_err(&pdev->dev, "undefined SSP\n");
 		return -ENODEV;
 	}
 	/* Allocate master with space for drv_data and null dma buffer */
 	master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
 	if (!master) {
 		dev_err(&pdev->dev, "can not alloc spi_master\n");
 		return -ENOMEM;
 	}
 	drv_data = spi_master_get_devdata(master);
 	drv_data->master = master;
 	drv_data->master_info = platform_info;
 	drv_data->pdev = pdev;
 	master->bus_num = pdev->id;
 	master->num_chipselect = platform_info->num_chipselect;
 	master->cleanup = cleanup;
 	master->setup = setup;
 	master->transfer = transfer;
 	drv_data->ssp_type = platform_info->ssp_type;
 	drv_data->null_dma_buf = (u32 *)ALIGN((u32)(drv_data +
 						sizeof(struct driver_data)), 8);
 	/* Setup register addresses */
 	memory_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (!memory_resource) {
 		dev_err(&pdev->dev, "memory resources not defined\n");
 		status = -ENODEV;
 		goto out_error_master_alloc;
 	}
 	drv_data->ioaddr = (void *)io_p2v((unsigned long)(memory_resource->start));
 	drv_data->ssdr_physical = memory_resource->start + 0x00000010;
 	if (platform_info->ssp_type == PXA25x_SSP) {
 		drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
 		drv_data->dma_cr1 = 0;
 		drv_data->clear_sr = SSSR_ROR;
 		drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
 	} else {
 		drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
 		drv_data->dma_cr1 = SSCR1_TSRE | SSCR1_RSRE | SSCR1_TINTE;
 		drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
 		drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR;
 	}
 	/* Attach to IRQ */
 	irq = platform_get_irq(pdev, 0);
 	if (irq < 0) {
 		dev_err(&pdev->dev, "irq resource not defined\n");
 		status = -ENODEV;
 		goto out_error_master_alloc;
 	}
 	status = request_irq(irq, ssp_int, 0, dev->bus_id, drv_data);
 	if (status < 0) {
 		dev_err(&pdev->dev, "can not get IRQ\n");
 		goto out_error_master_alloc;
 	}
 	/* Setup DMA if requested */
 	drv_data->tx_channel = -1;
 	drv_data->rx_channel = -1;
 	if (platform_info->enable_dma) {
 		/* Get two DMA channels	(rx and tx) */
 		drv_data->rx_channel = pxa_request_dma("pxa2xx_spi_ssp_rx",
 							DMA_PRIO_HIGH,
 							dma_handler,
 							drv_data);
 		if (drv_data->rx_channel < 0) {
 			dev_err(dev, "problem (%d) requesting rx channel\n",
 				drv_data->rx_channel);
 			status = -ENODEV;
 			goto out_error_irq_alloc;
 		}
 		drv_data->tx_channel = pxa_request_dma("pxa2xx_spi_ssp_tx",
 							DMA_PRIO_MEDIUM,
 							dma_handler,
 							drv_data);
 		if (drv_data->tx_channel < 0) {
 			dev_err(dev, "problem (%d) requesting tx channel\n",
 				drv_data->tx_channel);
 			status = -ENODEV;
 			goto out_error_dma_alloc;
 		}
 		if (drv_data->ioaddr == SSP1_VIRT) {
 				DRCMRRXSSDR = DRCMR_MAPVLD
 						| drv_data->rx_channel;
 				DRCMRTXSSDR = DRCMR_MAPVLD
 						| drv_data->tx_channel;
 		} else if (drv_data->ioaddr == SSP2_VIRT) {
 				DRCMRRXSS2DR = DRCMR_MAPVLD
 						| drv_data->rx_channel;
 				DRCMRTXSS2DR = DRCMR_MAPVLD
 						| drv_data->tx_channel;
 		} else if (drv_data->ioaddr == SSP3_VIRT) {
 				DRCMRRXSS3DR = DRCMR_MAPVLD
 						| drv_data->rx_channel;
 				DRCMRTXSS3DR = DRCMR_MAPVLD
 						| drv_data->tx_channel;
 		} else {
 			dev_err(dev, "bad SSP type\n");
 			goto out_error_dma_alloc;
 		}
 	}
 	/* Enable SOC clock */
 	pxa_set_cken(platform_info->clock_enable, 1);
 	/* Load default SSP configuration */
 	write_SSCR0(0, drv_data->ioaddr);
 	write_SSCR1(SSCR1_RxTresh(4) | SSCR1_TxTresh(12), drv_data->ioaddr);
 	write_SSCR0(SSCR0_SerClkDiv(2)
 			| SSCR0_Motorola
 			| SSCR0_DataSize(8),
 			drv_data->ioaddr);
 	if (drv_data->ssp_type != PXA25x_SSP)
 		write_SSTO(0, drv_data->ioaddr);
 	write_SSPSP(0, drv_data->ioaddr);
 	/* Initial and start queue */
 	status = init_queue(drv_data);
 	if (status != 0) {
 		dev_err(&pdev->dev, "problem initializing queue\n");
 		goto out_error_clock_enabled;
 	}
 	status = start_queue(drv_data);
 	if (status != 0) {
 		dev_err(&pdev->dev, "problem starting queue\n");
 		goto out_error_clock_enabled;
 	}
 	/* Register with the SPI framework */
 	platform_set_drvdata(pdev, drv_data);
 	status = spi_register_master(master);
 	if (status != 0) {
 		dev_err(&pdev->dev, "problem registering spi master\n");
 		goto out_error_queue_alloc;
 	}
 	return status;
 out_error_queue_alloc:
 	destroy_queue(drv_data);
 out_error_clock_enabled:
 	pxa_set_cken(platform_info->clock_enable, 0);
 out_error_dma_alloc:
 	if (drv_data->tx_channel != -1)
 		pxa_free_dma(drv_data->tx_channel);
 	if (drv_data->rx_channel != -1)
 		pxa_free_dma(drv_data->rx_channel);
 out_error_irq_alloc:
 	free_irq(irq, drv_data);
 out_error_master_alloc:
 	spi_master_put(master);
 	return status;
 }
 static int pxa2xx_spi_remove(struct platform_device *pdev)
 {
 	struct driver_data *drv_data = platform_get_drvdata(pdev);
 	int irq;
 	int status = 0;
 	if (!drv_data)
 		return 0;
 	/* Remove the queue */
 	status = destroy_queue(drv_data);
 	if (status != 0)
 		/* the kernel does not check the return status of this
 		 * this routine (mod->exit, within the kernel).  Therefore
 		 * nothing is gained by returning from here, the module is
 		 * going away regardless, and we should not leave any more
 		 * resources allocated than necessary.  We cannot free the
 		 * message memory in drv_data->queue, but we can release the
 		 * resources below.  I think the kernel should honor -EBUSY
 		 * returns but... */
 		dev_err(&pdev->dev, "pxa2xx_spi_remove: workqueue will not "
 			"complete, message memory not freed\n");
 	/* Disable the SSP at the peripheral and SOC level */
 	write_SSCR0(0, drv_data->ioaddr);
 	pxa_set_cken(drv_data->master_info->clock_enable, 0);
 	/* Release DMA */
 	if (drv_data->master_info->enable_dma) {
 		if (drv_data->ioaddr == SSP1_VIRT) {
 			DRCMRRXSSDR = 0;
 			DRCMRTXSSDR = 0;
 		} else if (drv_data->ioaddr == SSP2_VIRT) {
 			DRCMRRXSS2DR = 0;
 			DRCMRTXSS2DR = 0;
 		} else if (drv_data->ioaddr == SSP3_VIRT) {
 			DRCMRRXSS3DR = 0;
 			DRCMRTXSS3DR = 0;
 		}
 		pxa_free_dma(drv_data->tx_channel);
 		pxa_free_dma(drv_data->rx_channel);
 	}
 	/* Release IRQ */
 	irq = platform_get_irq(pdev, 0);
 	if (irq >= 0)
 		free_irq(irq, drv_data);
 	/* Disconnect from the SPI framework */
 	spi_unregister_master(drv_data->master);
 	/* Prevent double remove */
 	platform_set_drvdata(pdev, NULL);
 	return 0;
 }
 static void pxa2xx_spi_shutdown(struct platform_device *pdev)
 {
 	int status = 0;
 	if ((status = pxa2xx_spi_remove(pdev)) != 0)
 		dev_err(&pdev->dev, "shutdown failed with %d\n", status);
 }
 #ifdef CONFIG_PM
 static int suspend_devices(struct device *dev, void *pm_message)
 {
 	pm_message_t *state = pm_message;
 	if (dev->power.power_state.event != state->event) {
 		dev_warn(dev, "pm state does not match request\n");
 		return -1;
 	}
 	return 0;
 }
 static int pxa2xx_spi_suspend(struct platform_device *pdev, pm_message_t state)
 {
 	struct driver_data *drv_data = platform_get_drvdata(pdev);
 	int status = 0;
 	/* Check all childern for current power state */
 	if (device_for_each_child(&pdev->dev, &state, suspend_devices) != 0) {
 		dev_warn(&pdev->dev, "suspend aborted\n");
 		return -1;
 	}
 	status = stop_queue(drv_data);
 	if (status != 0)
 		return status;
 	write_SSCR0(0, drv_data->ioaddr);
 	pxa_set_cken(drv_data->master_info->clock_enable, 0);
 	return 0;
 }
 static int pxa2xx_spi_resume(struct platform_device *pdev)
 {
 	struct driver_data *drv_data = platform_get_drvdata(pdev);
 	int status = 0;
 	/* Enable the SSP clock */
 	pxa_set_cken(drv_data->master_info->clock_enable, 1);
 	/* Start the queue running */
 	status = start_queue(drv_data);
 	if (status != 0) {
 		dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
 		return status;
 	}
 	return 0;
 }
 #else
 #define pxa2xx_spi_suspend NULL
 #define pxa2xx_spi_resume NULL
 #endif /* CONFIG_PM */
 static struct platform_driver driver = {
 	.driver = {
 		.name = "pxa2xx-spi",
 		.bus = &platform_bus_type,
 		.owner = THIS_MODULE,
 	},
 	.probe = pxa2xx_spi_probe,
 	.remove = __devexit_p(pxa2xx_spi_remove),
 	.shutdown = pxa2xx_spi_shutdown,
 	.suspend = pxa2xx_spi_suspend,
 	.resume = pxa2xx_spi_resume,
 };
 static int __init pxa2xx_spi_init(void)
 {
 	platform_driver_register(&driver);
 	return 0;
 }
 module_init(pxa2xx_spi_init);
 static void __exit pxa2xx_spi_exit(void)
 {
 	platform_driver_unregister(&driver);
 }
 module_exit(pxa2xx_spi_exit);