Eric Lee / linux-smarc-t335x-v3.2

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/*

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/*

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* New driver for Marvell Yukon 2 chipset.

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* New driver for Marvell Yukon 2 chipset.

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* Based on earlier sk98lin, and skge driver.

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* Based on earlier sk98lin, and skge driver.

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*

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*

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* This driver intentionally does not support all the features

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* This driver intentionally does not support all the features

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* of the original driver such as link fail-over and link management because

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* of the original driver such as link fail-over and link management because

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* those should be done at higher levels.

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* those should be done at higher levels.

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*

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*

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*

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*

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* This program is free software; you can redistribute it and/or modify

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* This program is free software; you can redistribute it and/or modify

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* it under the terms of the GNU General Public License as published by

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* it under the terms of the GNU General Public License as published by

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* the Free Software Foundation; either version 2 of the License, or

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* the Free Software Foundation; either version 2 of the License, or

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* (at your option) any later version.

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* (at your option) any later version.

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*

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*

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* This program is distributed in the hope that it will be useful,

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* This program is distributed in the hope that it will be useful,

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* but WITHOUT ANY WARRANTY; without even the implied warranty of

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* but WITHOUT ANY WARRANTY; without even the implied warranty of

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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

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* GNU General Public License for more details.

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* GNU General Public License for more details.

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*

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*

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* You should have received a copy of the GNU General Public License

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* You should have received a copy of the GNU General Public License

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* along with this program; if not, write to the Free Software

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* along with this program; if not, write to the Free Software

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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.

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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.

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*/

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*/

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#include <linux/config.h>

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#include <linux/config.h>

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#include <linux/crc32.h>

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#include <linux/crc32.h>

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#include <linux/kernel.h>

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#include <linux/kernel.h>

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#include <linux/version.h>

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#include <linux/version.h>

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#include <linux/module.h>

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#include <linux/module.h>

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#include <linux/netdevice.h>

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#include <linux/netdevice.h>

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#include <linux/dma-mapping.h>

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#include <linux/dma-mapping.h>

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#include <linux/etherdevice.h>

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#include <linux/etherdevice.h>

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#include <linux/ethtool.h>

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#include <linux/ethtool.h>

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#include <linux/pci.h>

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#include <linux/pci.h>

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#include <linux/ip.h>

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#include <linux/ip.h>

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#include <linux/tcp.h>

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#include <linux/tcp.h>

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#include <linux/in.h>

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#include <linux/in.h>

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#include <linux/delay.h>

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#include <linux/delay.h>

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#include <linux/workqueue.h>

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#include <linux/workqueue.h>

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#include <linux/if_vlan.h>

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#include <linux/if_vlan.h>

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#include <linux/prefetch.h>

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#include <linux/prefetch.h>

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#include <linux/mii.h>

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#include <linux/mii.h>

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#include <asm/irq.h>

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#include <asm/irq.h>

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#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)

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#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)

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#define SKY2_VLAN_TAG_USED 1

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#define SKY2_VLAN_TAG_USED 1

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#endif

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#endif

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#include "sky2.h"

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#include "sky2.h"

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#define DRV_NAME "sky2"

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#define DRV_NAME "sky2"

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#define DRV_VERSION "0.15"

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#define DRV_VERSION "1.1"

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#define PFX DRV_NAME " "

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#define PFX DRV_NAME " "

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/*

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/*

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* The Yukon II chipset takes 64 bit command blocks (called list elements)

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* The Yukon II chipset takes 64 bit command blocks (called list elements)

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* that are organized into three (receive, transmit, status) different rings

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* that are organized into three (receive, transmit, status) different rings

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* similar to Tigon3. A transmit can require several elements;

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* similar to Tigon3. A transmit can require several elements;

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* a receive requires one (or two if using 64 bit dma).

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* a receive requires one (or two if using 64 bit dma).

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*/

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*/

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#define RX_LE_SIZE 512

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#define RX_LE_SIZE 512

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#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))

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#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))

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#define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)

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#define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)

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#define RX_DEF_PENDING RX_MAX_PENDING

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#define RX_DEF_PENDING RX_MAX_PENDING

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#define RX_SKB_ALIGN 8

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#define RX_SKB_ALIGN 8

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#define TX_RING_SIZE 512

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#define TX_RING_SIZE 512

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#define TX_DEF_PENDING (TX_RING_SIZE - 1)

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#define TX_DEF_PENDING (TX_RING_SIZE - 1)

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#define TX_MIN_PENDING 64

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#define TX_MIN_PENDING 64

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#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)

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#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)

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#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */

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#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */

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#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))

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#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))

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#define ETH_JUMBO_MTU 9000

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#define ETH_JUMBO_MTU 9000

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#define TX_WATCHDOG (5 * HZ)

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#define TX_WATCHDOG (5 * HZ)

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#define NAPI_WEIGHT 64

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#define NAPI_WEIGHT 64

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#define PHY_RETRIES 1000

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#define PHY_RETRIES 1000

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static const u32 default_msg =

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static const u32 default_msg =

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NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK

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NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK

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| NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR

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| NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR

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| NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;

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| NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;

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static int debug = -1; /* defaults above */

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static int debug = -1; /* defaults above */

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module_param(debug, int, 0);

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module_param(debug, int, 0);

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MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");

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MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");

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static int copybreak __read_mostly = 256;

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static int copybreak __read_mostly = 256;

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module_param(copybreak, int, 0);

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module_param(copybreak, int, 0);

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MODULE_PARM_DESC(copybreak, "Receive copy threshold");

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MODULE_PARM_DESC(copybreak, "Receive copy threshold");

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static int disable_msi = 0;

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static int disable_msi = 0;

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module_param(disable_msi, int, 0);

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module_param(disable_msi, int, 0);

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MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");

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MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");

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static const struct pci_device_id sky2_id_table[] = {

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static const struct pci_device_id sky2_id_table[] = {

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{ PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },

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{ PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },

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{ PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },

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{ PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },

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{ PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) },

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{ PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) },

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{ PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) },

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{ PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) },

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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },

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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },

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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },

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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },

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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },

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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },

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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },

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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },

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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },

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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },

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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },

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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },

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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },

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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },

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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },

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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },

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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },

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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },

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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },

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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },

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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },

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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },

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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },

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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },

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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },

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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },

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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },

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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },

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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },

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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },

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{ 0 }

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{ 0 }

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};

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};

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MODULE_DEVICE_TABLE(pci, sky2_id_table);

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MODULE_DEVICE_TABLE(pci, sky2_id_table);

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/* Avoid conditionals by using array */

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/* Avoid conditionals by using array */

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static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };

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static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };

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static const unsigned rxqaddr[] = { Q_R1, Q_R2 };

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static const unsigned rxqaddr[] = { Q_R1, Q_R2 };

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/* This driver supports yukon2 chipset only */

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/* This driver supports yukon2 chipset only */

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static const char *yukon2_name[] = {

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static const char *yukon2_name[] = {

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"XL", /* 0xb3 */

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"XL", /* 0xb3 */

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"EC Ultra", /* 0xb4 */

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"EC Ultra", /* 0xb4 */

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"UNKNOWN", /* 0xb5 */

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"UNKNOWN", /* 0xb5 */

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"EC", /* 0xb6 */

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"EC", /* 0xb6 */

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"FE", /* 0xb7 */

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"FE", /* 0xb7 */

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};

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};

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/* Access to external PHY */

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/* Access to external PHY */

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static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)

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static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)

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{

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{

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int i;

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int i;

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gma_write16(hw, port, GM_SMI_DATA, val);

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gma_write16(hw, port, GM_SMI_DATA, val);

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gma_write16(hw, port, GM_SMI_CTRL,

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gma_write16(hw, port, GM_SMI_CTRL,

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GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));

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GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));

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for (i = 0; i < PHY_RETRIES; i++) {

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for (i = 0; i < PHY_RETRIES; i++) {

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if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))

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if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))

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return 0;

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return 0;

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udelay(1);

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udelay(1);

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}

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}

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printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);

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printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);

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return -ETIMEDOUT;

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return -ETIMEDOUT;

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}

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}

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static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)

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static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)

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{

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{

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int i;

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int i;

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gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)

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gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)

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| GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);

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| GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);

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for (i = 0; i < PHY_RETRIES; i++) {

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for (i = 0; i < PHY_RETRIES; i++) {

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if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {

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if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {

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*val = gma_read16(hw, port, GM_SMI_DATA);

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*val = gma_read16(hw, port, GM_SMI_DATA);

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return 0;

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return 0;

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}

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}

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udelay(1);

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udelay(1);

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}

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}

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return -ETIMEDOUT;

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return -ETIMEDOUT;

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}

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}

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static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)

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static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)

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{

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{

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u16 v;

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u16 v;

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if (__gm_phy_read(hw, port, reg, &v) != 0)

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if (__gm_phy_read(hw, port, reg, &v) != 0)

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printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);

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printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);

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return v;

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return v;

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}

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}

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static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)

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static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)

185

{

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{

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u16 power_control;

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u16 power_control;

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u32 reg1;

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u32 reg1;

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int vaux;

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int vaux;

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int ret = 0;

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int ret = 0;

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pr_debug("sky2_set_power_state %d\n", state);

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pr_debug("sky2_set_power_state %d\n", state);

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sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);

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sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);

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power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_PMC);

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power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_PMC);

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vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) &&

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vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) &&

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(power_control & PCI_PM_CAP_PME_D3cold);

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(power_control & PCI_PM_CAP_PME_D3cold);

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198

power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_CTRL);

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power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_CTRL);

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200

power_control |= PCI_PM_CTRL_PME_STATUS;

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power_control |= PCI_PM_CTRL_PME_STATUS;

201

power_control &= ~(PCI_PM_CTRL_STATE_MASK);

201

power_control &= ~(PCI_PM_CTRL_STATE_MASK);

202

203

switch (state) {

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switch (state) {

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case PCI_D0:

204

case PCI_D0:

205

/* switch power to VCC (WA for VAUX problem) */

205

/* switch power to VCC (WA for VAUX problem) */

206

sky2_write8(hw, B0_POWER_CTRL,

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sky2_write8(hw, B0_POWER_CTRL,

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PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);

207

PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);

208

209

/* disable Core Clock Division, */

209

/* disable Core Clock Division, */

210

sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);

210

sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);

211

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if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)

212

if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)

213

/* enable bits are inverted */

213

/* enable bits are inverted */

214

sky2_write8(hw, B2_Y2_CLK_GATE,

214

sky2_write8(hw, B2_Y2_CLK_GATE,

215

Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |

215

Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |

216

Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |

216

Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |

217

Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);

217

Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);

218

else

218

else

219

sky2_write8(hw, B2_Y2_CLK_GATE, 0);

219

sky2_write8(hw, B2_Y2_CLK_GATE, 0);

220

221

/* Turn off phy power saving */

221

/* Turn off phy power saving */

222

reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);

222

reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);

223

reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);

223

reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);

224

225

/* looks like this XL is back asswards .. */

225

/* looks like this XL is back asswards .. */

226

if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) {

226

if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) {

227

reg1 |= PCI_Y2_PHY1_COMA;

227

reg1 |= PCI_Y2_PHY1_COMA;

228

if (hw->ports > 1)

228

if (hw->ports > 1)

229

reg1 |= PCI_Y2_PHY2_COMA;

229

reg1 |= PCI_Y2_PHY2_COMA;

230

}

230

}

231

232

if (hw->chip_id == CHIP_ID_YUKON_EC_U) {

232

if (hw->chip_id == CHIP_ID_YUKON_EC_U) {

233

sky2_pci_write32(hw, PCI_DEV_REG3, 0);

233

sky2_pci_write32(hw, PCI_DEV_REG3, 0);

234

reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);

234

reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);

235

reg1 &= P_ASPM_CONTROL_MSK;

235

reg1 &= P_ASPM_CONTROL_MSK;

236

sky2_pci_write32(hw, PCI_DEV_REG4, reg1);

236

sky2_pci_write32(hw, PCI_DEV_REG4, reg1);

237

sky2_pci_write32(hw, PCI_DEV_REG5, 0);

237

sky2_pci_write32(hw, PCI_DEV_REG5, 0);

238

}

238

}

239

240

sky2_pci_write32(hw, PCI_DEV_REG1, reg1);

240

sky2_pci_write32(hw, PCI_DEV_REG1, reg1);

241

242

break;

242

break;

243

244

case PCI_D3hot:

244

case PCI_D3hot:

245

case PCI_D3cold:

245

case PCI_D3cold:

246

/* Turn on phy power saving */

246

/* Turn on phy power saving */

247

reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);

247

reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);

248

if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)

248

if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)

249

reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);

249

reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);

250

else

250

else

251

reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);

251

reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);

252

sky2_pci_write32(hw, PCI_DEV_REG1, reg1);

252

sky2_pci_write32(hw, PCI_DEV_REG1, reg1);

253

254

if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)

254

if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)

255

sky2_write8(hw, B2_Y2_CLK_GATE, 0);

255

sky2_write8(hw, B2_Y2_CLK_GATE, 0);

256

else

256

else

257

/* enable bits are inverted */

257

/* enable bits are inverted */

258

sky2_write8(hw, B2_Y2_CLK_GATE,

258

sky2_write8(hw, B2_Y2_CLK_GATE,

259

Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |

259

Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |

260

Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |

260

Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |

261

Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);

261

Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);

262

263

/* switch power to VAUX */

263

/* switch power to VAUX */

264

if (vaux && state != PCI_D3cold)

264

if (vaux && state != PCI_D3cold)

265

sky2_write8(hw, B0_POWER_CTRL,

265

sky2_write8(hw, B0_POWER_CTRL,

266

(PC_VAUX_ENA | PC_VCC_ENA |

266

(PC_VAUX_ENA | PC_VCC_ENA |

267

PC_VAUX_ON | PC_VCC_OFF));

267

PC_VAUX_ON | PC_VCC_OFF));

268

break;

268

break;

269

default:

269

default:

270

printk(KERN_ERR PFX "Unknown power state %d\n", state);

270

printk(KERN_ERR PFX "Unknown power state %d\n", state);

271

ret = -1;

271

ret = -1;

272

}

272

}

273

274

sky2_pci_write16(hw, hw->pm_cap + PCI_PM_CTRL, power_control);

274

sky2_pci_write16(hw, hw->pm_cap + PCI_PM_CTRL, power_control);

275

sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);

275

sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);

276

return ret;

276

return ret;

277

}

277

}

278

279

static void sky2_phy_reset(struct sky2_hw *hw, unsigned port)

279

static void sky2_phy_reset(struct sky2_hw *hw, unsigned port)

280

{

280

{

281

u16 reg;

281

u16 reg;

282

283

/* disable all GMAC IRQ's */

283

/* disable all GMAC IRQ's */

284

sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);

284

sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);

285

/* disable PHY IRQs */

285

/* disable PHY IRQs */

286

gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);

286

gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);

287

288

gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */

288

gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */

289

gma_write16(hw, port, GM_MC_ADDR_H2, 0);

289

gma_write16(hw, port, GM_MC_ADDR_H2, 0);

290

gma_write16(hw, port, GM_MC_ADDR_H3, 0);

290

gma_write16(hw, port, GM_MC_ADDR_H3, 0);

291

gma_write16(hw, port, GM_MC_ADDR_H4, 0);

291

gma_write16(hw, port, GM_MC_ADDR_H4, 0);

292

293

reg = gma_read16(hw, port, GM_RX_CTRL);

293

reg = gma_read16(hw, port, GM_RX_CTRL);

294

reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;

294

reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;

295

gma_write16(hw, port, GM_RX_CTRL, reg);

295

gma_write16(hw, port, GM_RX_CTRL, reg);

296

}

296

}

297

298

static void sky2_phy_init(struct sky2_hw *hw, unsigned port)

298

static void sky2_phy_init(struct sky2_hw *hw, unsigned port)

299

{

299

{

300

struct sky2_port *sky2 = netdev_priv(hw->dev[port]);

300

struct sky2_port *sky2 = netdev_priv(hw->dev[port]);

301

u16 ctrl, ct1000, adv, pg, ledctrl, ledover;

301

u16 ctrl, ct1000, adv, pg, ledctrl, ledover;

302

303

if (sky2->autoneg == AUTONEG_ENABLE && hw->chip_id != CHIP_ID_YUKON_XL) {

303

if (sky2->autoneg == AUTONEG_ENABLE && hw->chip_id != CHIP_ID_YUKON_XL) {

304

u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);

304

u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);

305

306

ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |

306

ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |

307

PHY_M_EC_MAC_S_MSK);

307

PHY_M_EC_MAC_S_MSK);

308

ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);

308

ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);

309

310

if (hw->chip_id == CHIP_ID_YUKON_EC)

310

if (hw->chip_id == CHIP_ID_YUKON_EC)

311

ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;

311

ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;

312

else

312

else

313

ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);

313

ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);

314

315

gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);

315

gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);

316

}

316

}

317

318

ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);

318

ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);

319

if (hw->copper) {

319

if (hw->copper) {

320

if (hw->chip_id == CHIP_ID_YUKON_FE) {

320

if (hw->chip_id == CHIP_ID_YUKON_FE) {

321

/* enable automatic crossover */

321

/* enable automatic crossover */

322

ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;

322

ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;

323

} else {

323

} else {

324

/* disable energy detect */

324

/* disable energy detect */

325

ctrl &= ~PHY_M_PC_EN_DET_MSK;

325

ctrl &= ~PHY_M_PC_EN_DET_MSK;

326

327

/* enable automatic crossover */

327

/* enable automatic crossover */

328

ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);

328

ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);

329

330

if (sky2->autoneg == AUTONEG_ENABLE &&

330

if (sky2->autoneg == AUTONEG_ENABLE &&

331

hw->chip_id == CHIP_ID_YUKON_XL) {

331

hw->chip_id == CHIP_ID_YUKON_XL) {

332

ctrl &= ~PHY_M_PC_DSC_MSK;

332

ctrl &= ~PHY_M_PC_DSC_MSK;

333

ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;

333

ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;

334

}

334

}

335

}

335

}

336

gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);

336

gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);

337

} else {

337

} else {

338

/* workaround for deviation #4.88 (CRC errors) */

338

/* workaround for deviation #4.88 (CRC errors) */

339

/* disable Automatic Crossover */

339

/* disable Automatic Crossover */

340

341

ctrl &= ~PHY_M_PC_MDIX_MSK;

341

ctrl &= ~PHY_M_PC_MDIX_MSK;

342

gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);

342

gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);

343

344

if (hw->chip_id == CHIP_ID_YUKON_XL) {

344

if (hw->chip_id == CHIP_ID_YUKON_XL) {

345

/* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */

345

/* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */

346

gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);

346

gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);

347

ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);

347

ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);

348

ctrl &= ~PHY_M_MAC_MD_MSK;

348

ctrl &= ~PHY_M_MAC_MD_MSK;

349

ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);

349

ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);

350

gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);

350

gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);

351

352

/* select page 1 to access Fiber registers */

352

/* select page 1 to access Fiber registers */

353

gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);

353

gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);

354

}

354

}

355

}

355

}

356

357

ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);

357

ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);

358

if (sky2->autoneg == AUTONEG_DISABLE)

358

if (sky2->autoneg == AUTONEG_DISABLE)

359

ctrl &= ~PHY_CT_ANE;

359

ctrl &= ~PHY_CT_ANE;

360

else

360

else

361

ctrl |= PHY_CT_ANE;

361

ctrl |= PHY_CT_ANE;

362

363

ctrl |= PHY_CT_RESET;

363

ctrl |= PHY_CT_RESET;

364

gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);

364

gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);

365

366

ctrl = 0;

366

ctrl = 0;

367

ct1000 = 0;

367

ct1000 = 0;

368

adv = PHY_AN_CSMA;

368

adv = PHY_AN_CSMA;

369

370

if (sky2->autoneg == AUTONEG_ENABLE) {

370

if (sky2->autoneg == AUTONEG_ENABLE) {

371

if (hw->copper) {

371

if (hw->copper) {

372

if (sky2->advertising & ADVERTISED_1000baseT_Full)

372

if (sky2->advertising & ADVERTISED_1000baseT_Full)

373

ct1000 |= PHY_M_1000C_AFD;

373

ct1000 |= PHY_M_1000C_AFD;

374

if (sky2->advertising & ADVERTISED_1000baseT_Half)

374

if (sky2->advertising & ADVERTISED_1000baseT_Half)

375

ct1000 |= PHY_M_1000C_AHD;

375

ct1000 |= PHY_M_1000C_AHD;

376

if (sky2->advertising & ADVERTISED_100baseT_Full)

376

if (sky2->advertising & ADVERTISED_100baseT_Full)

377

adv |= PHY_M_AN_100_FD;

377

adv |= PHY_M_AN_100_FD;

378

if (sky2->advertising & ADVERTISED_100baseT_Half)

378

if (sky2->advertising & ADVERTISED_100baseT_Half)

379

adv |= PHY_M_AN_100_HD;

379

adv |= PHY_M_AN_100_HD;

380

if (sky2->advertising & ADVERTISED_10baseT_Full)

380

if (sky2->advertising & ADVERTISED_10baseT_Full)

381

adv |= PHY_M_AN_10_FD;

381

adv |= PHY_M_AN_10_FD;

382

if (sky2->advertising & ADVERTISED_10baseT_Half)

382

if (sky2->advertising & ADVERTISED_10baseT_Half)

383

adv |= PHY_M_AN_10_HD;

383

adv |= PHY_M_AN_10_HD;

384

} else /* special defines for FIBER (88E1011S only) */

384

} else /* special defines for FIBER (88E1011S only) */

385

adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;

385

adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;

386

387

/* Set Flow-control capabilities */

387

/* Set Flow-control capabilities */

388

if (sky2->tx_pause && sky2->rx_pause)

388

if (sky2->tx_pause && sky2->rx_pause)

389

adv |= PHY_AN_PAUSE_CAP; /* symmetric */

389

adv |= PHY_AN_PAUSE_CAP; /* symmetric */

390

else if (sky2->rx_pause && !sky2->tx_pause)

390

else if (sky2->rx_pause && !sky2->tx_pause)

391

adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;

391

adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;

392

else if (!sky2->rx_pause && sky2->tx_pause)

392

else if (!sky2->rx_pause && sky2->tx_pause)

393

adv |= PHY_AN_PAUSE_ASYM; /* local */

393

adv |= PHY_AN_PAUSE_ASYM; /* local */

394

395

/* Restart Auto-negotiation */

395

/* Restart Auto-negotiation */

396

ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;

396

ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;

397

} else {

397

} else {

398

/* forced speed/duplex settings */

398

/* forced speed/duplex settings */

399

ct1000 = PHY_M_1000C_MSE;

399

ct1000 = PHY_M_1000C_MSE;

400

401

if (sky2->duplex == DUPLEX_FULL)

401

if (sky2->duplex == DUPLEX_FULL)

402

ctrl |= PHY_CT_DUP_MD;

402

ctrl |= PHY_CT_DUP_MD;

403

404

switch (sky2->speed) {

404

switch (sky2->speed) {

405

case SPEED_1000:

405

case SPEED_1000:

406

ctrl |= PHY_CT_SP1000;

406

ctrl |= PHY_CT_SP1000;

407

break;

407

break;

408

case SPEED_100:

408

case SPEED_100:

409

ctrl |= PHY_CT_SP100;

409

ctrl |= PHY_CT_SP100;

410

break;

410

break;

411

}

411

}

412

413

ctrl |= PHY_CT_RESET;

413

ctrl |= PHY_CT_RESET;

414

}

414

}

415

416

if (hw->chip_id != CHIP_ID_YUKON_FE)

416

if (hw->chip_id != CHIP_ID_YUKON_FE)

417

gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);

417

gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);

418

419

gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);

419

gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);

420

gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);

420

gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);

421

422

/* Setup Phy LED's */

422

/* Setup Phy LED's */

423

ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);

423

ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);

424

ledover = 0;

424

ledover = 0;

425

426

switch (hw->chip_id) {

426

switch (hw->chip_id) {

427

case CHIP_ID_YUKON_FE:

427

case CHIP_ID_YUKON_FE:

428

/* on 88E3082 these bits are at 11..9 (shifted left) */

428

/* on 88E3082 these bits are at 11..9 (shifted left) */

429

ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;

429

ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;

430

431

ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);

431

ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);

432

433

/* delete ACT LED control bits */

433

/* delete ACT LED control bits */

434

ctrl &= ~PHY_M_FELP_LED1_MSK;

434

ctrl &= ~PHY_M_FELP_LED1_MSK;

435

/* change ACT LED control to blink mode */

435

/* change ACT LED control to blink mode */

436

ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);

436

ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);

437

gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);

437

gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);

438

break;

438

break;

439

440

case CHIP_ID_YUKON_XL:

440

case CHIP_ID_YUKON_XL:

441

pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);

441

pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);

442

443

/* select page 3 to access LED control register */

443

/* select page 3 to access LED control register */

444

gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);

444

gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);

445

446

/* set LED Function Control register */

446

/* set LED Function Control register */

447

gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */

447

gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */

448

PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */

448

PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */

449

PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */

449

PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */

450

PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */

450

PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */

451

452

/* set Polarity Control register */

452

/* set Polarity Control register */

453

gm_phy_write(hw, port, PHY_MARV_PHY_STAT,

453

gm_phy_write(hw, port, PHY_MARV_PHY_STAT,

454

(PHY_M_POLC_LS1_P_MIX(4) |

454

(PHY_M_POLC_LS1_P_MIX(4) |

455

PHY_M_POLC_IS0_P_MIX(4) |

455

PHY_M_POLC_IS0_P_MIX(4) |

456

PHY_M_POLC_LOS_CTRL(2) |

456

PHY_M_POLC_LOS_CTRL(2) |

457

PHY_M_POLC_INIT_CTRL(2) |

457

PHY_M_POLC_INIT_CTRL(2) |

458

PHY_M_POLC_STA1_CTRL(2) |

458

PHY_M_POLC_STA1_CTRL(2) |

459

PHY_M_POLC_STA0_CTRL(2)));

459

PHY_M_POLC_STA0_CTRL(2)));

460

461

/* restore page register */

461

/* restore page register */

462

gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);

462

gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);

463

break;

463

break;

464

465

default:

465

default:

466

/* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */

466

/* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */

467

ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;

467

ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;

468

/* turn off the Rx LED (LED_RX) */

468

/* turn off the Rx LED (LED_RX) */

469

ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);

469

ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);

470

}

470

}

471

472

if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {

472

if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {

473

/* apply fixes in PHY AFE */

473

/* apply fixes in PHY AFE */

474

gm_phy_write(hw, port, 22, 255);

474

gm_phy_write(hw, port, 22, 255);

475

/* increase differential signal amplitude in 10BASE-T */

475

/* increase differential signal amplitude in 10BASE-T */

476

gm_phy_write(hw, port, 24, 0xaa99);

476

gm_phy_write(hw, port, 24, 0xaa99);

477

gm_phy_write(hw, port, 23, 0x2011);

477

gm_phy_write(hw, port, 23, 0x2011);

478

479

/* fix for IEEE A/B Symmetry failure in 1000BASE-T */

479

/* fix for IEEE A/B Symmetry failure in 1000BASE-T */

480

gm_phy_write(hw, port, 24, 0xa204);

480

gm_phy_write(hw, port, 24, 0xa204);

481

gm_phy_write(hw, port, 23, 0x2002);

481

gm_phy_write(hw, port, 23, 0x2002);

482

483

/* set page register to 0 */

483

/* set page register to 0 */

484

gm_phy_write(hw, port, 22, 0);

484

gm_phy_write(hw, port, 22, 0);

485

} else {

485

} else {

486

gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);

486

gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);

487

488

if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {

488

if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {

489

/* turn on 100 Mbps LED (LED_LINK100) */

489

/* turn on 100 Mbps LED (LED_LINK100) */

490

ledover |= PHY_M_LED_MO_100(MO_LED_ON);

490

ledover |= PHY_M_LED_MO_100(MO_LED_ON);

491

}

491

}

492

493

if (ledover)

493

if (ledover)

494

gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);

494

gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);

495

496

}

496

}

497

/* Enable phy interrupt on auto-negotiation complete (or link up) */

497

/* Enable phy interrupt on auto-negotiation complete (or link up) */

498

if (sky2->autoneg == AUTONEG_ENABLE)

498

if (sky2->autoneg == AUTONEG_ENABLE)

499

gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);

499

gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);

500

else

500

else

501

gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);

501

gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);

502

}

502

}

503

504

/* Force a renegotiation */

504

/* Force a renegotiation */

505

static void sky2_phy_reinit(struct sky2_port *sky2)

505

static void sky2_phy_reinit(struct sky2_port *sky2)

506

{

506

{

507

spin_lock_bh(&sky2->phy_lock);

507

spin_lock_bh(&sky2->phy_lock);

508

sky2_phy_init(sky2->hw, sky2->port);

508

sky2_phy_init(sky2->hw, sky2->port);

509

spin_unlock_bh(&sky2->phy_lock);

509

spin_unlock_bh(&sky2->phy_lock);

510

}

510

}

511

512

static void sky2_mac_init(struct sky2_hw *hw, unsigned port)

512

static void sky2_mac_init(struct sky2_hw *hw, unsigned port)

513

{

513

{

514

struct sky2_port *sky2 = netdev_priv(hw->dev[port]);

514

struct sky2_port *sky2 = netdev_priv(hw->dev[port]);

515

u16 reg;

515

u16 reg;

516

int i;

516

int i;

517

const u8 *addr = hw->dev[port]->dev_addr;

517

const u8 *addr = hw->dev[port]->dev_addr;

518

519

sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);

519

sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);

520

sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);

520

sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);

521

522

sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);

522

sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);

523

524

if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {

524

if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {

525

/* WA DEV_472 -- looks like crossed wires on port 2 */

525

/* WA DEV_472 -- looks like crossed wires on port 2 */

526

/* clear GMAC 1 Control reset */

526

/* clear GMAC 1 Control reset */

527

sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);

527

sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);

528

do {

528

do {

529

sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);

529

sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);

530

sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);

530

sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);

531

} while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||

531

} while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||

532

gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||

532

gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||

533

gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);

533

gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);

534

}

534

}

535

536

if (sky2->autoneg == AUTONEG_DISABLE) {

536

if (sky2->autoneg == AUTONEG_DISABLE) {

537

reg = gma_read16(hw, port, GM_GP_CTRL);

537

reg = gma_read16(hw, port, GM_GP_CTRL);

538

reg |= GM_GPCR_AU_ALL_DIS;

538

reg |= GM_GPCR_AU_ALL_DIS;

539

gma_write16(hw, port, GM_GP_CTRL, reg);

539

gma_write16(hw, port, GM_GP_CTRL, reg);

540

gma_read16(hw, port, GM_GP_CTRL);

540

gma_read16(hw, port, GM_GP_CTRL);

541

542

switch (sky2->speed) {

542

switch (sky2->speed) {

543

case SPEED_1000:

543

case SPEED_1000:

544

reg &= ~GM_GPCR_SPEED_100;

544

reg &= ~GM_GPCR_SPEED_100;

545

reg |= GM_GPCR_SPEED_1000;

545

reg |= GM_GPCR_SPEED_1000;

546

break;

546

break;

547

case SPEED_100:

547

case SPEED_100:

548

reg &= ~GM_GPCR_SPEED_1000;

548

reg &= ~GM_GPCR_SPEED_1000;

549

reg |= GM_GPCR_SPEED_100;

549

reg |= GM_GPCR_SPEED_100;

550

break;

550

break;

551

case SPEED_10:

551

case SPEED_10:

552

reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);

552

reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);

553

break;

553

break;

554

}

554

}

555

556

if (sky2->duplex == DUPLEX_FULL)

556

if (sky2->duplex == DUPLEX_FULL)

557

reg |= GM_GPCR_DUP_FULL;

557

reg |= GM_GPCR_DUP_FULL;

558

} else

558

} else

559

reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;

559

reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;

560

561

if (!sky2->tx_pause && !sky2->rx_pause) {

561

if (!sky2->tx_pause && !sky2->rx_pause) {

562

sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);

562

sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);

563

reg |=

563

reg |=

564

GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;

564

GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;

565

} else if (sky2->tx_pause && !sky2->rx_pause) {

565

} else if (sky2->tx_pause && !sky2->rx_pause) {

566

/* disable Rx flow-control */

566

/* disable Rx flow-control */

567

reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;

567

reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;

568

}

568

}

569

570

gma_write16(hw, port, GM_GP_CTRL, reg);

570

gma_write16(hw, port, GM_GP_CTRL, reg);

571

572

sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));

572

sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));

573

574

spin_lock_bh(&sky2->phy_lock);

574

spin_lock_bh(&sky2->phy_lock);

575

sky2_phy_init(hw, port);

575

sky2_phy_init(hw, port);

576

spin_unlock_bh(&sky2->phy_lock);

576

spin_unlock_bh(&sky2->phy_lock);

577

578

/* MIB clear */

578

/* MIB clear */

579

reg = gma_read16(hw, port, GM_PHY_ADDR);

579

reg = gma_read16(hw, port, GM_PHY_ADDR);

580

gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);

580

gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);

581

582

for (i = 0; i < GM_MIB_CNT_SIZE; i++)

582

for (i = 0; i < GM_MIB_CNT_SIZE; i++)

583

gma_read16(hw, port, GM_MIB_CNT_BASE + 8 * i);

583

gma_read16(hw, port, GM_MIB_CNT_BASE + 8 * i);

584

gma_write16(hw, port, GM_PHY_ADDR, reg);

584

gma_write16(hw, port, GM_PHY_ADDR, reg);

585

586

/* transmit control */

586

/* transmit control */

587

gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));

587

gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));

588

589

/* receive control reg: unicast + multicast + no FCS */

589

/* receive control reg: unicast + multicast + no FCS */

590

gma_write16(hw, port, GM_RX_CTRL,

590

gma_write16(hw, port, GM_RX_CTRL,

591

GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);

591

GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);

592

593

/* transmit flow control */

593

/* transmit flow control */

594

gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);

594

gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);

595

596

/* transmit parameter */

596

/* transmit parameter */

597

gma_write16(hw, port, GM_TX_PARAM,

597

gma_write16(hw, port, GM_TX_PARAM,

598

TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |

598

TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |

599

TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |

599

TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |

600

TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |

600

TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |

601

TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));

601

TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));

602

603

/* serial mode register */

603

/* serial mode register */

604

reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |

604

reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |

605

GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);

605

GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);

606

607

if (hw->dev[port]->mtu > ETH_DATA_LEN)

607

if (hw->dev[port]->mtu > ETH_DATA_LEN)

608

reg |= GM_SMOD_JUMBO_ENA;

608

reg |= GM_SMOD_JUMBO_ENA;

609

610

gma_write16(hw, port, GM_SERIAL_MODE, reg);

610

gma_write16(hw, port, GM_SERIAL_MODE, reg);

611

612

/* virtual address for data */

612

/* virtual address for data */

613

gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);

613

gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);

614

615

/* physical address: used for pause frames */

615

/* physical address: used for pause frames */

616

gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);

616

gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);

617

618

/* ignore counter overflows */

618

/* ignore counter overflows */

619

gma_write16(hw, port, GM_TX_IRQ_MSK, 0);

619

gma_write16(hw, port, GM_TX_IRQ_MSK, 0);

620

gma_write16(hw, port, GM_RX_IRQ_MSK, 0);

620

gma_write16(hw, port, GM_RX_IRQ_MSK, 0);

621

gma_write16(hw, port, GM_TR_IRQ_MSK, 0);

621

gma_write16(hw, port, GM_TR_IRQ_MSK, 0);

622

623

/* Configure Rx MAC FIFO */

623

/* Configure Rx MAC FIFO */

624

sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);

624

sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);

625

sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),

625

sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),

626

GMF_OPER_ON | GMF_RX_F_FL_ON);

626

GMF_OPER_ON | GMF_RX_F_FL_ON);

627

628

/* Flush Rx MAC FIFO on any flow control or error */

628

/* Flush Rx MAC FIFO on any flow control or error */

629

sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);

629

sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);

630

631

/* Set threshold to 0xa (64 bytes)

631

/* Set threshold to 0xa (64 bytes)

632

* ASF disabled so no need to do WA dev #4.30

632

* ASF disabled so no need to do WA dev #4.30

633

*/

633

*/

634

sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);

634

sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);

635

636

/* Configure Tx MAC FIFO */

636

/* Configure Tx MAC FIFO */

637

sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);

637

sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);

638

sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);

638

sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);

639

640

if (hw->chip_id == CHIP_ID_YUKON_EC_U) {

640

if (hw->chip_id == CHIP_ID_YUKON_EC_U) {

641

sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);

641

sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);

642

sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);

642

sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);

643

if (hw->dev[port]->mtu > ETH_DATA_LEN) {

643

if (hw->dev[port]->mtu > ETH_DATA_LEN) {

644

/* set Tx GMAC FIFO Almost Empty Threshold */

644

/* set Tx GMAC FIFO Almost Empty Threshold */

645

sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);

645

sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);

646

/* Disable Store & Forward mode for TX */

646

/* Disable Store & Forward mode for TX */

647

sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);

647

sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);

648

}

648

}

649

}

649

}

650

651

}

651

}

652

653

/* Assign Ram Buffer allocation.

653

/* Assign Ram Buffer allocation.

654

* start and end are in units of 4k bytes

654

* start and end are in units of 4k bytes

655

* ram registers are in units of 64bit words

655

* ram registers are in units of 64bit words

656

*/

656

*/

657

static void sky2_ramset(struct sky2_hw *hw, u16 q, u8 startk, u8 endk)

657

static void sky2_ramset(struct sky2_hw *hw, u16 q, u8 startk, u8 endk)

658

{

658

{

659

u32 start, end;

659

u32 start, end;

660

661

start = startk * 4096/8;

661

start = startk * 4096/8;

662

end = (endk * 4096/8) - 1;

662

end = (endk * 4096/8) - 1;

663

664

sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);

664

sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);

665

sky2_write32(hw, RB_ADDR(q, RB_START), start);

665

sky2_write32(hw, RB_ADDR(q, RB_START), start);

666

sky2_write32(hw, RB_ADDR(q, RB_END), end);

666

sky2_write32(hw, RB_ADDR(q, RB_END), end);

667

sky2_write32(hw, RB_ADDR(q, RB_WP), start);

667

sky2_write32(hw, RB_ADDR(q, RB_WP), start);

668

sky2_write32(hw, RB_ADDR(q, RB_RP), start);

668

sky2_write32(hw, RB_ADDR(q, RB_RP), start);

669

670

if (q == Q_R1 || q == Q_R2) {

670

if (q == Q_R1 || q == Q_R2) {

671

u32 space = (endk - startk) * 4096/8;

671

u32 space = (endk - startk) * 4096/8;

672

u32 tp = space - space/4;

672

u32 tp = space - space/4;

673

674

/* On receive queue's set the thresholds

674

/* On receive queue's set the thresholds

675

* give receiver priority when > 3/4 full

675

* give receiver priority when > 3/4 full

676

* send pause when down to 2K

676

* send pause when down to 2K

677

*/

677

*/

678

sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);

678

sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);

679

sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);

679

sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);

680

681

tp = space - 2048/8;

681

tp = space - 2048/8;

682

sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);

682

sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);

683

sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);

683

sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);

684

} else {

684

} else {

685

/* Enable store & forward on Tx queue's because

685

/* Enable store & forward on Tx queue's because

686

* Tx FIFO is only 1K on Yukon

686

* Tx FIFO is only 1K on Yukon

687

*/

687

*/

688

sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);

688

sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);

689

}

689

}

690

691

sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);

691

sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);

692

sky2_read8(hw, RB_ADDR(q, RB_CTRL));

692

sky2_read8(hw, RB_ADDR(q, RB_CTRL));

693

}

693

}

694

695

/* Setup Bus Memory Interface */

695

/* Setup Bus Memory Interface */

696

static void sky2_qset(struct sky2_hw *hw, u16 q)

696

static void sky2_qset(struct sky2_hw *hw, u16 q)

697

{

697

{

698

sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);

698

sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);

699

sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);

699

sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);

700

sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);

700

sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);

701

sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);

701

sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);

702

}

702

}

703

704

/* Setup prefetch unit registers. This is the interface between

704

/* Setup prefetch unit registers. This is the interface between

705

* hardware and driver list elements

705

* hardware and driver list elements

706

*/

706

*/

707

static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,

707

static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,

708

u64 addr, u32 last)

708

u64 addr, u32 last)

709

{

709

{

710

sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);

710

sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);

711

sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);

711

sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);

712

sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);

712

sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);

713

sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);

713

sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);

714

sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);

714

sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);

715

sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);

715

sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);

716

717

sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));

717

sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));

718

}

718

}

719

720

static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)

720

static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)

721

{

721

{

722

struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;

722

struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;

723

724

sky2->tx_prod = (sky2->tx_prod + 1) % TX_RING_SIZE;

724

sky2->tx_prod = (sky2->tx_prod + 1) % TX_RING_SIZE;

725

return le;

725

return le;

726

}

726

}

727

728

/* Update chip's next pointer */

728

/* Update chip's next pointer */

729

static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)

729

static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)

730

{

730

{

731

wmb();

731

wmb();

732

sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);

732

sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);

733

mmiowb();

733

mmiowb();

734

}

734

}

735

736

737

static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)

737

static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)

738

{

738

{

739

struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;

739

struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;

740

sky2->rx_put = (sky2->rx_put + 1) % RX_LE_SIZE;

740

sky2->rx_put = (sky2->rx_put + 1) % RX_LE_SIZE;

741

return le;

741

return le;

742

}

742

}

743

744

/* Return high part of DMA address (could be 32 or 64 bit) */

744

/* Return high part of DMA address (could be 32 or 64 bit) */

745

static inline u32 high32(dma_addr_t a)

745

static inline u32 high32(dma_addr_t a)

746

{

746

{

747

return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;

747

return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;

748

}

748

}

749

750

/* Build description to hardware about buffer */

750

/* Build description to hardware about buffer */

751

static void sky2_rx_add(struct sky2_port *sky2, dma_addr_t map)

751

static void sky2_rx_add(struct sky2_port *sky2, dma_addr_t map)

752

{

752

{

753

struct sky2_rx_le *le;

753

struct sky2_rx_le *le;

754

u32 hi = high32(map);

754

u32 hi = high32(map);

755

u16 len = sky2->rx_bufsize;

755

u16 len = sky2->rx_bufsize;

756

757

if (sky2->rx_addr64 != hi) {

757

if (sky2->rx_addr64 != hi) {

758

le = sky2_next_rx(sky2);

758

le = sky2_next_rx(sky2);

759

le->addr = cpu_to_le32(hi);

759

le->addr = cpu_to_le32(hi);

760

le->ctrl = 0;

760

le->ctrl = 0;

761

le->opcode = OP_ADDR64 | HW_OWNER;

761

le->opcode = OP_ADDR64 | HW_OWNER;

762

sky2->rx_addr64 = high32(map + len);

762

sky2->rx_addr64 = high32(map + len);

763

}

763

}

764

765

le = sky2_next_rx(sky2);

765

le = sky2_next_rx(sky2);

766

le->addr = cpu_to_le32((u32) map);

766

le->addr = cpu_to_le32((u32) map);

767

le->length = cpu_to_le16(len);

767

le->length = cpu_to_le16(len);

768

le->ctrl = 0;

768

le->ctrl = 0;

769

le->opcode = OP_PACKET | HW_OWNER;

769

le->opcode = OP_PACKET | HW_OWNER;

770

}

770

}

771

772

773

/* Tell chip where to start receive checksum.

773

/* Tell chip where to start receive checksum.

774

* Actually has two checksums, but set both same to avoid possible byte

774

* Actually has two checksums, but set both same to avoid possible byte

775

* order problems.

775

* order problems.

776

*/

776

*/

777

static void rx_set_checksum(struct sky2_port *sky2)

777

static void rx_set_checksum(struct sky2_port *sky2)

778

{

778

{

779

struct sky2_rx_le *le;

779

struct sky2_rx_le *le;

780

781

le = sky2_next_rx(sky2);

781

le = sky2_next_rx(sky2);

782

le->addr = (ETH_HLEN << 16) | ETH_HLEN;

782

le->addr = (ETH_HLEN << 16) | ETH_HLEN;

783

le->ctrl = 0;

783

le->ctrl = 0;

784

le->opcode = OP_TCPSTART | HW_OWNER;

784

le->opcode = OP_TCPSTART | HW_OWNER;

785

786

sky2_write32(sky2->hw,

786

sky2_write32(sky2->hw,

787

Q_ADDR(rxqaddr[sky2->port], Q_CSR),

787

Q_ADDR(rxqaddr[sky2->port], Q_CSR),

788

sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);

788

sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);

789

790

}

790

}

791

792

/*

792

/*

793

* The RX Stop command will not work for Yukon-2 if the BMU does not

793

* The RX Stop command will not work for Yukon-2 if the BMU does not

794

* reach the end of packet and since we can't make sure that we have

794

* reach the end of packet and since we can't make sure that we have

795

* incoming data, we must reset the BMU while it is not doing a DMA

795

* incoming data, we must reset the BMU while it is not doing a DMA

796

* transfer. Since it is possible that the RX path is still active,

796

* transfer. Since it is possible that the RX path is still active,

797

* the RX RAM buffer will be stopped first, so any possible incoming

797

* the RX RAM buffer will be stopped first, so any possible incoming

798

* data will not trigger a DMA. After the RAM buffer is stopped, the

798

* data will not trigger a DMA. After the RAM buffer is stopped, the

799

* BMU is polled until any DMA in progress is ended and only then it

799

* BMU is polled until any DMA in progress is ended and only then it

800

* will be reset.

800

* will be reset.

801

*/

801

*/

802

static void sky2_rx_stop(struct sky2_port *sky2)

802

static void sky2_rx_stop(struct sky2_port *sky2)

803

{

803

{

804

struct sky2_hw *hw = sky2->hw;

804

struct sky2_hw *hw = sky2->hw;

805

unsigned rxq = rxqaddr[sky2->port];

805

unsigned rxq = rxqaddr[sky2->port];

806

int i;

806

int i;

807

808

/* disable the RAM Buffer receive queue */

808

/* disable the RAM Buffer receive queue */

809

sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);

809

sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);

810

811

for (i = 0; i < 0xffff; i++)

811

for (i = 0; i < 0xffff; i++)

812

if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))

812

if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))

813

== sky2_read8(hw, RB_ADDR(rxq, Q_RL)))

813

== sky2_read8(hw, RB_ADDR(rxq, Q_RL)))

814

goto stopped;

814

goto stopped;

815

816

printk(KERN_WARNING PFX "%s: receiver stop failed\n",

816

printk(KERN_WARNING PFX "%s: receiver stop failed\n",

817

sky2->netdev->name);

817

sky2->netdev->name);

818

stopped:

818

stopped:

819

sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);

819

sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);

820

821

/* reset the Rx prefetch unit */

821

/* reset the Rx prefetch unit */

822

sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);

822

sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);

823

}

823

}

824

825

/* Clean out receive buffer area, assumes receiver hardware stopped */

825

/* Clean out receive buffer area, assumes receiver hardware stopped */

826

static void sky2_rx_clean(struct sky2_port *sky2)

826

static void sky2_rx_clean(struct sky2_port *sky2)

827

{

827

{

828

unsigned i;

828

unsigned i;

829

830

memset(sky2->rx_le, 0, RX_LE_BYTES);

830

memset(sky2->rx_le, 0, RX_LE_BYTES);

831

for (i = 0; i < sky2->rx_pending; i++) {

831

for (i = 0; i < sky2->rx_pending; i++) {

832

struct ring_info *re = sky2->rx_ring + i;

832

struct ring_info *re = sky2->rx_ring + i;

833

834

if (re->skb) {

834

if (re->skb) {

835

pci_unmap_single(sky2->hw->pdev,

835

pci_unmap_single(sky2->hw->pdev,

836

re->mapaddr, sky2->rx_bufsize,

836

re->mapaddr, sky2->rx_bufsize,

837

PCI_DMA_FROMDEVICE);

837

PCI_DMA_FROMDEVICE);

838

kfree_skb(re->skb);

838

kfree_skb(re->skb);

839

re->skb = NULL;

839

re->skb = NULL;

840

}

840

}

841

}

841

}

842

}

842

}

843

844

/* Basic MII support */

844

/* Basic MII support */

845

static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)

845

static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)

846

{

846

{

847

struct mii_ioctl_data *data = if_mii(ifr);

847

struct mii_ioctl_data *data = if_mii(ifr);

848

struct sky2_port *sky2 = netdev_priv(dev);

848

struct sky2_port *sky2 = netdev_priv(dev);

849

struct sky2_hw *hw = sky2->hw;

849

struct sky2_hw *hw = sky2->hw;

850

int err = -EOPNOTSUPP;

850

int err = -EOPNOTSUPP;

851

852

if (!netif_running(dev))

852

if (!netif_running(dev))

853

return -ENODEV; /* Phy still in reset */

853

return -ENODEV; /* Phy still in reset */

854

855

switch (cmd) {

855

switch (cmd) {

856

case SIOCGMIIPHY:

856

case SIOCGMIIPHY:

857

data->phy_id = PHY_ADDR_MARV;

857

data->phy_id = PHY_ADDR_MARV;

858

859

/* fallthru */

859

/* fallthru */

860

case SIOCGMIIREG: {

860

case SIOCGMIIREG: {

861

u16 val = 0;

861

u16 val = 0;

862

863

spin_lock_bh(&sky2->phy_lock);

863

spin_lock_bh(&sky2->phy_lock);

864

err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);

864

err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);

865

spin_unlock_bh(&sky2->phy_lock);

865

spin_unlock_bh(&sky2->phy_lock);

866

867

data->val_out = val;

867

data->val_out = val;

868

break;

868

break;

869

}

869

}

870

871

case SIOCSMIIREG:

871

case SIOCSMIIREG:

872

if (!capable(CAP_NET_ADMIN))

872

if (!capable(CAP_NET_ADMIN))

873

return -EPERM;

873

return -EPERM;

874

875

spin_lock_bh(&sky2->phy_lock);

875

spin_lock_bh(&sky2->phy_lock);

876

err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,

876

err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,

877

data->val_in);

877

data->val_in);

878

spin_unlock_bh(&sky2->phy_lock);

878

spin_unlock_bh(&sky2->phy_lock);

879

break;

879

break;

880

}

880

}

881

return err;

881

return err;

882

}

882

}

883

884

#ifdef SKY2_VLAN_TAG_USED

884

#ifdef SKY2_VLAN_TAG_USED

885

static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)

885

static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)

886

{

886

{

887

struct sky2_port *sky2 = netdev_priv(dev);

887

struct sky2_port *sky2 = netdev_priv(dev);

888

struct sky2_hw *hw = sky2->hw;

888

struct sky2_hw *hw = sky2->hw;

889

u16 port = sky2->port;

889

u16 port = sky2->port;

890

891

spin_lock_bh(&sky2->tx_lock);

891

spin_lock_bh(&sky2->tx_lock);

892

893

sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);

893

sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);

894

sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);

894

sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);

895

sky2->vlgrp = grp;

895

sky2->vlgrp = grp;

896

897

spin_unlock_bh(&sky2->tx_lock);

897

spin_unlock_bh(&sky2->tx_lock);

898

}

898

}

899

900

static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)

900

static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)

901

{

901

{

902

struct sky2_port *sky2 = netdev_priv(dev);

902

struct sky2_port *sky2 = netdev_priv(dev);

903

struct sky2_hw *hw = sky2->hw;

903

struct sky2_hw *hw = sky2->hw;

904

u16 port = sky2->port;

904

u16 port = sky2->port;

905

906

spin_lock_bh(&sky2->tx_lock);

906

spin_lock_bh(&sky2->tx_lock);

907

908

sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);

908

sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);

909

sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);

909

sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);

910

if (sky2->vlgrp)

910

if (sky2->vlgrp)

911

sky2->vlgrp->vlan_devices[vid] = NULL;

911

sky2->vlgrp->vlan_devices[vid] = NULL;

912

913

spin_unlock_bh(&sky2->tx_lock);

913

spin_unlock_bh(&sky2->tx_lock);

914

}

914

}

915

#endif

915

#endif

916

917

/*

917

/*

918

* It appears the hardware has a bug in the FIFO logic that

918

* It appears the hardware has a bug in the FIFO logic that

919

* cause it to hang if the FIFO gets overrun and the receive buffer

919

* cause it to hang if the FIFO gets overrun and the receive buffer

920

* is not aligned. ALso alloc_skb() won't align properly if slab

920

* is not aligned. ALso alloc_skb() won't align properly if slab

921

* debugging is enabled.

921

* debugging is enabled.

922

*/

922

*/

923

static inline struct sk_buff *sky2_alloc_skb(unsigned int size, gfp_t gfp_mask)

923

static inline struct sk_buff *sky2_alloc_skb(unsigned int size, gfp_t gfp_mask)

924

{

924

{

925

struct sk_buff *skb;

925

struct sk_buff *skb;

926

927

skb = alloc_skb(size + RX_SKB_ALIGN, gfp_mask);

927

skb = alloc_skb(size + RX_SKB_ALIGN, gfp_mask);

928

if (likely(skb)) {

928

if (likely(skb)) {

929

unsigned long p = (unsigned long) skb->data;

929

unsigned long p = (unsigned long) skb->data;

930

skb_reserve(skb,

930

skb_reserve(skb,

931

((p + RX_SKB_ALIGN - 1) & ~(RX_SKB_ALIGN - 1)) - p);

931

((p + RX_SKB_ALIGN - 1) & ~(RX_SKB_ALIGN - 1)) - p);

932

}

932

}

933

934

return skb;

934

return skb;

935

}

935

}

936

937

/*

937

/*

938

* Allocate and setup receiver buffer pool.

938

* Allocate and setup receiver buffer pool.

939

* In case of 64 bit dma, there are 2X as many list elements

939

* In case of 64 bit dma, there are 2X as many list elements

940

* available as ring entries

940

* available as ring entries

941

* and need to reserve one list element so we don't wrap around.

941

* and need to reserve one list element so we don't wrap around.

942

*/

942

*/

943

static int sky2_rx_start(struct sky2_port *sky2)

943

static int sky2_rx_start(struct sky2_port *sky2)

944

{

944

{

945

struct sky2_hw *hw = sky2->hw;

945

struct sky2_hw *hw = sky2->hw;

946

unsigned rxq = rxqaddr[sky2->port];

946

unsigned rxq = rxqaddr[sky2->port];

947

int i;

947

int i;

948

949

sky2->rx_put = sky2->rx_next = 0;

949

sky2->rx_put = sky2->rx_next = 0;

950

sky2_qset(hw, rxq);

950

sky2_qset(hw, rxq);

951

952

if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {

952

if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {

953

/* MAC Rx RAM Read is controlled by hardware */

953

/* MAC Rx RAM Read is controlled by hardware */

954

sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);

954

sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);

955

}

955

}

956

957

sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);

957

sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);

958

959

rx_set_checksum(sky2);

959

rx_set_checksum(sky2);

960

for (i = 0; i < sky2->rx_pending; i++) {

960

for (i = 0; i < sky2->rx_pending; i++) {

961

struct ring_info *re = sky2->rx_ring + i;

961

struct ring_info *re = sky2->rx_ring + i;

962

963

re->skb = sky2_alloc_skb(sky2->rx_bufsize, GFP_KERNEL);

963

re->skb = sky2_alloc_skb(sky2->rx_bufsize, GFP_KERNEL);

964

if (!re->skb)

964

if (!re->skb)

965

goto nomem;

965

goto nomem;

966

967

re->mapaddr = pci_map_single(hw->pdev, re->skb->data,

967

re->mapaddr = pci_map_single(hw->pdev, re->skb->data,

968

sky2->rx_bufsize, PCI_DMA_FROMDEVICE);

968

sky2->rx_bufsize, PCI_DMA_FROMDEVICE);

969

sky2_rx_add(sky2, re->mapaddr);

969

sky2_rx_add(sky2, re->mapaddr);

970

}

970

}

971

972

/* Truncate oversize frames */

972

/* Truncate oversize frames */

973

sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), sky2->rx_bufsize - 8);

973

sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), sky2->rx_bufsize - 8);

974

sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);

974

sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);

975

976

/* Tell chip about available buffers */

976

/* Tell chip about available buffers */

977

sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);

977

sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);

978

return 0;

978

return 0;

979

nomem:

979

nomem:

980

sky2_rx_clean(sky2);

980

sky2_rx_clean(sky2);

981

return -ENOMEM;

981

return -ENOMEM;

982

}

982

}

983

984

/* Bring up network interface. */

984

/* Bring up network interface. */

985

static int sky2_up(struct net_device *dev)

985

static int sky2_up(struct net_device *dev)

986

{

986

{

987

struct sky2_port *sky2 = netdev_priv(dev);

987

struct sky2_port *sky2 = netdev_priv(dev);

988

struct sky2_hw *hw = sky2->hw;

988

struct sky2_hw *hw = sky2->hw;

989

unsigned port = sky2->port;

989

unsigned port = sky2->port;

990

u32 ramsize, rxspace, imask;

990

u32 ramsize, rxspace, imask;

991

int err = -ENOMEM;

991

int err = -ENOMEM;

992

993

if (netif_msg_ifup(sky2))

993

if (netif_msg_ifup(sky2))

994

printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);

994

printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);

995

996

/* must be power of 2 */

996

/* must be power of 2 */

997

sky2->tx_le = pci_alloc_consistent(hw->pdev,

997

sky2->tx_le = pci_alloc_consistent(hw->pdev,

998

TX_RING_SIZE *

998

TX_RING_SIZE *

999

sizeof(struct sky2_tx_le),

999

sizeof(struct sky2_tx_le),

1000

&sky2->tx_le_map);

1000

&sky2->tx_le_map);

1001

if (!sky2->tx_le)

1001

if (!sky2->tx_le)

1002

goto err_out;

1002

goto err_out;

1003

1004

sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),

1004

sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),

1005

GFP_KERNEL);

1005

GFP_KERNEL);

1006

if (!sky2->tx_ring)

1006

if (!sky2->tx_ring)

1007

goto err_out;

1007

goto err_out;

1008

sky2->tx_prod = sky2->tx_cons = 0;

1008

sky2->tx_prod = sky2->tx_cons = 0;

1009

1010

sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,

1010

sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,

1011

&sky2->rx_le_map);

1011

&sky2->rx_le_map);

1012

if (!sky2->rx_le)

1012

if (!sky2->rx_le)

1013

goto err_out;

1013

goto err_out;

1014

memset(sky2->rx_le, 0, RX_LE_BYTES);

1014

memset(sky2->rx_le, 0, RX_LE_BYTES);

1015

1016

sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct ring_info),

1016

sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct ring_info),

1017

GFP_KERNEL);

1017

GFP_KERNEL);

1018

if (!sky2->rx_ring)

1018

if (!sky2->rx_ring)

1019

goto err_out;

1019

goto err_out;

1020

1021

sky2_mac_init(hw, port);

1021

sky2_mac_init(hw, port);

1022

1023

/* Determine available ram buffer space (in 4K blocks).

1023

/* Determine available ram buffer space (in 4K blocks).

1024

* Note: not sure about the FE setting below yet

1024

* Note: not sure about the FE setting below yet

1025

*/

1025

*/

1026

if (hw->chip_id == CHIP_ID_YUKON_FE)

1026

if (hw->chip_id == CHIP_ID_YUKON_FE)

1027

ramsize = 4;

1027

ramsize = 4;

1028

else

1028

else

1029

ramsize = sky2_read8(hw, B2_E_0);

1029

ramsize = sky2_read8(hw, B2_E_0);

1030

1031

/* Give transmitter one third (rounded up) */

1031

/* Give transmitter one third (rounded up) */

1032

rxspace = ramsize - (ramsize + 2) / 3;

1032

rxspace = ramsize - (ramsize + 2) / 3;

1033

1034

sky2_ramset(hw, rxqaddr[port], 0, rxspace);

1034

sky2_ramset(hw, rxqaddr[port], 0, rxspace);

1035

sky2_ramset(hw, txqaddr[port], rxspace, ramsize);

1035

sky2_ramset(hw, txqaddr[port], rxspace, ramsize);

1036

1037

/* Make sure SyncQ is disabled */

1037

/* Make sure SyncQ is disabled */

1038

sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),

1038

sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),

1039

RB_RST_SET);

1039

RB_RST_SET);

1040

1041

sky2_qset(hw, txqaddr[port]);

1041

sky2_qset(hw, txqaddr[port]);

1042

1043

/* Set almost empty threshold */

1043

/* Set almost empty threshold */

1044

if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == 1)

1044

if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == 1)

1045

sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);

1045

sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);

1046

1047

sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,

1047

sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,

1048

TX_RING_SIZE - 1);

1048

TX_RING_SIZE - 1);

1049

1050

err = sky2_rx_start(sky2);

1050

err = sky2_rx_start(sky2);

1051

if (err)

1051

if (err)

1052

goto err_out;

1052

goto err_out;

1053

1054

/* Enable interrupts from phy/mac for port */

1054

/* Enable interrupts from phy/mac for port */

1055

imask = sky2_read32(hw, B0_IMSK);

1055

imask = sky2_read32(hw, B0_IMSK);

1056

imask |= (port == 0) ? Y2_IS_PORT_1 : Y2_IS_PORT_2;

1056

imask |= (port == 0) ? Y2_IS_PORT_1 : Y2_IS_PORT_2;

1057

sky2_write32(hw, B0_IMSK, imask);

1057

sky2_write32(hw, B0_IMSK, imask);

1058

1059

return 0;

1059

return 0;

1060

1061

err_out:

1061

err_out:

1062

if (sky2->rx_le) {

1062

if (sky2->rx_le) {

1063

pci_free_consistent(hw->pdev, RX_LE_BYTES,

1063

pci_free_consistent(hw->pdev, RX_LE_BYTES,

1064

sky2->rx_le, sky2->rx_le_map);

1064

sky2->rx_le, sky2->rx_le_map);

1065

sky2->rx_le = NULL;

1065

sky2->rx_le = NULL;

1066

}

1066

}

1067

if (sky2->tx_le) {

1067

if (sky2->tx_le) {

1068

pci_free_consistent(hw->pdev,

1068

pci_free_consistent(hw->pdev,

1069

TX_RING_SIZE * sizeof(struct sky2_tx_le),

1069

TX_RING_SIZE * sizeof(struct sky2_tx_le),

1070

sky2->tx_le, sky2->tx_le_map);

1070

sky2->tx_le, sky2->tx_le_map);

1071

sky2->tx_le = NULL;

1071

sky2->tx_le = NULL;

1072

}

1072

}

1073

kfree(sky2->tx_ring);

1073

kfree(sky2->tx_ring);

1074

kfree(sky2->rx_ring);

1074

kfree(sky2->rx_ring);

1075

1076

sky2->tx_ring = NULL;

1076

sky2->tx_ring = NULL;

1077

sky2->rx_ring = NULL;

1077

sky2->rx_ring = NULL;

1078

return err;

1078

return err;

1079

}

1079

}

1080

1081

/* Modular subtraction in ring */

1081

/* Modular subtraction in ring */

1082

static inline int tx_dist(unsigned tail, unsigned head)

1082

static inline int tx_dist(unsigned tail, unsigned head)

1083

{

1083

{

1084

return (head - tail) % TX_RING_SIZE;

1084

return (head - tail) % TX_RING_SIZE;

1085

}

1085

}

1086

1087

/* Number of list elements available for next tx */

1087

/* Number of list elements available for next tx */

1088

static inline int tx_avail(const struct sky2_port *sky2)

1088

static inline int tx_avail(const struct sky2_port *sky2)

1089

{

1089

{

1090

return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);

1090

return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);

1091

}

1091

}

1092

1093

/* Estimate of number of transmit list elements required */

1093

/* Estimate of number of transmit list elements required */

1094

static unsigned tx_le_req(const struct sk_buff *skb)

1094

static unsigned tx_le_req(const struct sk_buff *skb)

1095

{

1095

{

1096

unsigned count;

1096

unsigned count;

1097

1098

count = sizeof(dma_addr_t) / sizeof(u32);

1098

count = sizeof(dma_addr_t) / sizeof(u32);

1099

count += skb_shinfo(skb)->nr_frags * count;

1099

count += skb_shinfo(skb)->nr_frags * count;

1100

1101

if (skb_shinfo(skb)->tso_size)

1101

if (skb_shinfo(skb)->tso_size)

1102

++count;

1102

++count;

1103

1104

if (skb->ip_summed == CHECKSUM_HW)

1104

if (skb->ip_summed == CHECKSUM_HW)

1105

++count;

1105

++count;

1106

1107

return count;

1107

return count;

1108

}

1108

}

1109

1110

/*

1110

/*

1111

* Put one packet in ring for transmit.

1111

* Put one packet in ring for transmit.

1112

* A single packet can generate multiple list elements, and

1112

* A single packet can generate multiple list elements, and

1113

* the number of ring elements will probably be less than the number

1113

* the number of ring elements will probably be less than the number

1114

* of list elements used.

1114

* of list elements used.

1115

*

1115

*

1116

* No BH disabling for tx_lock here (like tg3)

1116

* No BH disabling for tx_lock here (like tg3)

1117

*/

1117

*/

1118

static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)

1118

static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)

1119

{

1119

{

1120

struct sky2_port *sky2 = netdev_priv(dev);

1120

struct sky2_port *sky2 = netdev_priv(dev);

1121

struct sky2_hw *hw = sky2->hw;

1121

struct sky2_hw *hw = sky2->hw;

1122

struct sky2_tx_le *le = NULL;

1122

struct sky2_tx_le *le = NULL;

1123

struct tx_ring_info *re;

1123

struct tx_ring_info *re;

1124

unsigned i, len;

1124

unsigned i, len;

1125

int avail;

1125

int avail;

1126

dma_addr_t mapping;

1126

dma_addr_t mapping;

1127

u32 addr64;

1127

u32 addr64;

1128

u16 mss;

1128

u16 mss;

1129

u8 ctrl;

1129

u8 ctrl;

1130

1131

/* No BH disabling for tx_lock here. We are running in BH disabled

1131

/* No BH disabling for tx_lock here. We are running in BH disabled

1132

* context and TX reclaim runs via poll inside of a software

1132

* context and TX reclaim runs via poll inside of a software

1133

* interrupt, and no related locks in IRQ processing.

1133

* interrupt, and no related locks in IRQ processing.

1134

*/

1134

*/

1135

if (!spin_trylock(&sky2->tx_lock))

1135

if (!spin_trylock(&sky2->tx_lock))

1136

return NETDEV_TX_LOCKED;

1136

return NETDEV_TX_LOCKED;

1137

1138

if (unlikely(tx_avail(sky2) < tx_le_req(skb))) {

1138

if (unlikely(tx_avail(sky2) < tx_le_req(skb))) {

1139

/* There is a known but harmless race with lockless tx

1139

/* There is a known but harmless race with lockless tx

1140

* and netif_stop_queue.

1140

* and netif_stop_queue.

1141

*/

1141

*/

1142

if (!netif_queue_stopped(dev)) {

1142

if (!netif_queue_stopped(dev)) {

1143

netif_stop_queue(dev);

1143

netif_stop_queue(dev);

1144

if (net_ratelimit())

1144

if (net_ratelimit())

1145

printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",

1145

printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",

1146

dev->name);

1146

dev->name);

1147

}

1147

}

1148

spin_unlock(&sky2->tx_lock);

1148

spin_unlock(&sky2->tx_lock);

1149

1150

return NETDEV_TX_BUSY;

1150

return NETDEV_TX_BUSY;

1151

}

1151

}

1152

1153

if (unlikely(netif_msg_tx_queued(sky2)))

1153

if (unlikely(netif_msg_tx_queued(sky2)))

1154

printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",

1154

printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",

1155

dev->name, sky2->tx_prod, skb->len);

1155

dev->name, sky2->tx_prod, skb->len);

1156

1157

len = skb_headlen(skb);

1157

len = skb_headlen(skb);

1158

mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);

1158

mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);

1159

addr64 = high32(mapping);

1159

addr64 = high32(mapping);

1160

1161

re = sky2->tx_ring + sky2->tx_prod;

1161

re = sky2->tx_ring + sky2->tx_prod;

1162

1163

/* Send high bits if changed or crosses boundary */

1163

/* Send high bits if changed or crosses boundary */

1164

if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {

1164

if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {

1165

le = get_tx_le(sky2);

1165

le = get_tx_le(sky2);

1166

le->tx.addr = cpu_to_le32(addr64);

1166

le->tx.addr = cpu_to_le32(addr64);

1167

le->ctrl = 0;

1167

le->ctrl = 0;

1168

le->opcode = OP_ADDR64 | HW_OWNER;

1168

le->opcode = OP_ADDR64 | HW_OWNER;

1169

sky2->tx_addr64 = high32(mapping + len);

1169

sky2->tx_addr64 = high32(mapping + len);

1170

}

1170

}

1171

1172

/* Check for TCP Segmentation Offload */

1172

/* Check for TCP Segmentation Offload */

1173

mss = skb_shinfo(skb)->tso_size;

1173

mss = skb_shinfo(skb)->tso_size;

1174

if (mss != 0) {

1174

if (mss != 0) {

1175

/* just drop the packet if non-linear expansion fails */

1175

/* just drop the packet if non-linear expansion fails */

1176

if (skb_header_cloned(skb) &&

1176

if (skb_header_cloned(skb) &&

1177

pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {

1177

pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {

1178

dev_kfree_skb_any(skb);

1178

dev_kfree_skb_any(skb);

1179

goto out_unlock;

1179

goto out_unlock;

1180

}

1180

}

1181

1182

mss += ((skb->h.th->doff - 5) * 4); /* TCP options */

1182

mss += ((skb->h.th->doff - 5) * 4); /* TCP options */

1183

mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);

1183

mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);

1184

mss += ETH_HLEN;

1184

mss += ETH_HLEN;

1185

}

1185

}

1186

1187

if (mss != sky2->tx_last_mss) {

1187

if (mss != sky2->tx_last_mss) {

1188

le = get_tx_le(sky2);

1188

le = get_tx_le(sky2);

1189

le->tx.tso.size = cpu_to_le16(mss);

1189

le->tx.tso.size = cpu_to_le16(mss);

1190

le->tx.tso.rsvd = 0;

1190

le->tx.tso.rsvd = 0;

1191

le->opcode = OP_LRGLEN | HW_OWNER;

1191

le->opcode = OP_LRGLEN | HW_OWNER;

1192

le->ctrl = 0;

1192

le->ctrl = 0;

1193

sky2->tx_last_mss = mss;

1193

sky2->tx_last_mss = mss;

1194

}

1194

}

1195

1196

ctrl = 0;

1196

ctrl = 0;

1197

#ifdef SKY2_VLAN_TAG_USED

1197

#ifdef SKY2_VLAN_TAG_USED

1198

/* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */

1198

/* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */

1199

if (sky2->vlgrp && vlan_tx_tag_present(skb)) {

1199

if (sky2->vlgrp && vlan_tx_tag_present(skb)) {

1200

if (!le) {

1200

if (!le) {

1201

le = get_tx_le(sky2);

1201

le = get_tx_le(sky2);

1202

le->tx.addr = 0;

1202

le->tx.addr = 0;

1203

le->opcode = OP_VLAN|HW_OWNER;

1203

le->opcode = OP_VLAN|HW_OWNER;

1204

le->ctrl = 0;

1204

le->ctrl = 0;

1205

} else

1205

} else

1206

le->opcode |= OP_VLAN;

1206

le->opcode |= OP_VLAN;

1207

le->length = cpu_to_be16(vlan_tx_tag_get(skb));

1207

le->length = cpu_to_be16(vlan_tx_tag_get(skb));

1208

ctrl |= INS_VLAN;

1208

ctrl |= INS_VLAN;

1209

}

1209

}

1210

#endif

1210

#endif

1211

1212

/* Handle TCP checksum offload */

1212

/* Handle TCP checksum offload */

1213

if (skb->ip_summed == CHECKSUM_HW) {

1213

if (skb->ip_summed == CHECKSUM_HW) {

1214

u16 hdr = skb->h.raw - skb->data;

1214

u16 hdr = skb->h.raw - skb->data;

1215

u16 offset = hdr + skb->csum;

1215

u16 offset = hdr + skb->csum;

1216

1217

ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;

1217

ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;

1218

if (skb->nh.iph->protocol == IPPROTO_UDP)

1218

if (skb->nh.iph->protocol == IPPROTO_UDP)

1219

ctrl |= UDPTCP;

1219

ctrl |= UDPTCP;

1220

1221

le = get_tx_le(sky2);

1221

le = get_tx_le(sky2);

1222

le->tx.csum.start = cpu_to_le16(hdr);

1222

le->tx.csum.start = cpu_to_le16(hdr);

1223

le->tx.csum.offset = cpu_to_le16(offset);

1223

le->tx.csum.offset = cpu_to_le16(offset);

1224

le->length = 0; /* initial checksum value */

1224

le->length = 0; /* initial checksum value */

1225

le->ctrl = 1; /* one packet */

1225

le->ctrl = 1; /* one packet */

1226

le->opcode = OP_TCPLISW | HW_OWNER;

1226

le->opcode = OP_TCPLISW | HW_OWNER;

1227

}

1227

}

1228

1229

le = get_tx_le(sky2);

1229

le = get_tx_le(sky2);

1230

le->tx.addr = cpu_to_le32((u32) mapping);

1230

le->tx.addr = cpu_to_le32((u32) mapping);

1231

le->length = cpu_to_le16(len);

1231

le->length = cpu_to_le16(len);

1232

le->ctrl = ctrl;

1232

le->ctrl = ctrl;

1233

le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);

1233

le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);

1234

1235

/* Record the transmit mapping info */

1235

/* Record the transmit mapping info */

1236

re->skb = skb;

1236

re->skb = skb;

1237

pci_unmap_addr_set(re, mapaddr, mapping);

1237

pci_unmap_addr_set(re, mapaddr, mapping);

1238

1239

for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {

1239

for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {

1240

skb_frag_t *frag = &skb_shinfo(skb)->frags[i];

1240

skb_frag_t *frag = &skb_shinfo(skb)->frags[i];

1241

struct tx_ring_info *fre;

1241

struct tx_ring_info *fre;

1242

1243

mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,

1243

mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,

1244

frag->size, PCI_DMA_TODEVICE);

1244

frag->size, PCI_DMA_TODEVICE);

1245

addr64 = high32(mapping);

1245

addr64 = high32(mapping);

1246

if (addr64 != sky2->tx_addr64) {

1246

if (addr64 != sky2->tx_addr64) {

1247

le = get_tx_le(sky2);

1247

le = get_tx_le(sky2);

1248

le->tx.addr = cpu_to_le32(addr64);

1248

le->tx.addr = cpu_to_le32(addr64);

1249

le->ctrl = 0;

1249

le->ctrl = 0;

1250

le->opcode = OP_ADDR64 | HW_OWNER;

1250

le->opcode = OP_ADDR64 | HW_OWNER;

1251

sky2->tx_addr64 = addr64;

1251

sky2->tx_addr64 = addr64;

1252

}

1252

}

1253

1254

le = get_tx_le(sky2);

1254

le = get_tx_le(sky2);

1255

le->tx.addr = cpu_to_le32((u32) mapping);

1255

le->tx.addr = cpu_to_le32((u32) mapping);

1256

le->length = cpu_to_le16(frag->size);

1256

le->length = cpu_to_le16(frag->size);

1257

le->ctrl = ctrl;

1257

le->ctrl = ctrl;

1258

le->opcode = OP_BUFFER | HW_OWNER;

1258

le->opcode = OP_BUFFER | HW_OWNER;

1259

1260

fre = sky2->tx_ring

1260

fre = sky2->tx_ring

1261

+ ((re - sky2->tx_ring) + i + 1) % TX_RING_SIZE;

1261

+ ((re - sky2->tx_ring) + i + 1) % TX_RING_SIZE;

1262

pci_unmap_addr_set(fre, mapaddr, mapping);

1262

pci_unmap_addr_set(fre, mapaddr, mapping);

1263

}

1263

}

1264

1265

re->idx = sky2->tx_prod;

1265

re->idx = sky2->tx_prod;

1266

le->ctrl |= EOP;

1266

le->ctrl |= EOP;

1267

1268

avail = tx_avail(sky2);

1268

avail = tx_avail(sky2);

1269

if (mss != 0 || avail < TX_MIN_PENDING) {

1269

if (mss != 0 || avail < TX_MIN_PENDING) {

1270

le->ctrl |= FRC_STAT;

1270

le->ctrl |= FRC_STAT;

1271

if (avail <= MAX_SKB_TX_LE)

1271

if (avail <= MAX_SKB_TX_LE)

1272

netif_stop_queue(dev);

1272

netif_stop_queue(dev);

1273

}

1273

}

1274

1275

sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);

1275

sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);

1276

1277

out_unlock:

1277

out_unlock:

1278

spin_unlock(&sky2->tx_lock);

1278

spin_unlock(&sky2->tx_lock);

1279

1280

dev->trans_start = jiffies;

1280

dev->trans_start = jiffies;

1281

return NETDEV_TX_OK;

1281

return NETDEV_TX_OK;

1282

}

1282

}

1283

1284

/*

1284

/*

1285

* Free ring elements from starting at tx_cons until "done"

1285

* Free ring elements from starting at tx_cons until "done"

1286

*

1286

*

1287

* NB: the hardware will tell us about partial completion of multi-part

1287

* NB: the hardware will tell us about partial completion of multi-part

1288

* buffers; these are deferred until completion.

1288

* buffers; these are deferred until completion.

1289

*/

1289

*/

1290

static void sky2_tx_complete(struct sky2_port *sky2, u16 done)

1290

static void sky2_tx_complete(struct sky2_port *sky2, u16 done)

1291

{

1291

{

1292

struct net_device *dev = sky2->netdev;

1292

struct net_device *dev = sky2->netdev;

1293

struct pci_dev *pdev = sky2->hw->pdev;

1293

struct pci_dev *pdev = sky2->hw->pdev;

1294

u16 nxt, put;

1294

u16 nxt, put;

1295

unsigned i;

1295

unsigned i;

1296

1297

BUG_ON(done >= TX_RING_SIZE);

1297

BUG_ON(done >= TX_RING_SIZE);

1298

1299

if (unlikely(netif_msg_tx_done(sky2)))

1299

if (unlikely(netif_msg_tx_done(sky2)))

1300

printk(KERN_DEBUG "%s: tx done, up to %u\n",

1300

printk(KERN_DEBUG "%s: tx done, up to %u\n",

1301

dev->name, done);

1301

dev->name, done);

1302

1303

for (put = sky2->tx_cons; put != done; put = nxt) {

1303

for (put = sky2->tx_cons; put != done; put = nxt) {

1304

struct tx_ring_info *re = sky2->tx_ring + put;

1304

struct tx_ring_info *re = sky2->tx_ring + put;

1305

struct sk_buff *skb = re->skb;

1305

struct sk_buff *skb = re->skb;

1306

1307

nxt = re->idx;

1307

nxt = re->idx;

1308

BUG_ON(nxt >= TX_RING_SIZE);

1308

BUG_ON(nxt >= TX_RING_SIZE);

1309

prefetch(sky2->tx_ring + nxt);

1309

prefetch(sky2->tx_ring + nxt);

1310

1311

/* Check for partial status */

1311

/* Check for partial status */

1312

if (tx_dist(put, done) < tx_dist(put, nxt))

1312

if (tx_dist(put, done) < tx_dist(put, nxt))

1313

break;

1313

break;

1314

1315

skb = re->skb;

1315

skb = re->skb;

1316

pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),

1316

pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),

1317

skb_headlen(skb), PCI_DMA_TODEVICE);

1317

skb_headlen(skb), PCI_DMA_TODEVICE);

1318

1319

for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {

1319

for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {

1320

struct tx_ring_info *fre;

1320

struct tx_ring_info *fre;

1321

fre = sky2->tx_ring + (put + i + 1) % TX_RING_SIZE;

1321

fre = sky2->tx_ring + (put + i + 1) % TX_RING_SIZE;

1322

pci_unmap_page(pdev, pci_unmap_addr(fre, mapaddr),

1322

pci_unmap_page(pdev, pci_unmap_addr(fre, mapaddr),

1323

skb_shinfo(skb)->frags[i].size,

1323

skb_shinfo(skb)->frags[i].size,

1324

PCI_DMA_TODEVICE);

1324

PCI_DMA_TODEVICE);

1325

}

1325

}

1326

1327

dev_kfree_skb_any(skb);

1327

dev_kfree_skb_any(skb);

1328

}

1328

}

1329

1330

sky2->tx_cons = put;

1330

sky2->tx_cons = put;

1331

if (tx_avail(sky2) > MAX_SKB_TX_LE)

1331

if (tx_avail(sky2) > MAX_SKB_TX_LE)

1332

netif_wake_queue(dev);

1332

netif_wake_queue(dev);

1333

}

1333

}

1334

1335

/* Cleanup all untransmitted buffers, assume transmitter not running */

1335

/* Cleanup all untransmitted buffers, assume transmitter not running */

1336

static void sky2_tx_clean(struct sky2_port *sky2)

1336

static void sky2_tx_clean(struct sky2_port *sky2)

1337

{

1337

{

1338

spin_lock_bh(&sky2->tx_lock);

1338

spin_lock_bh(&sky2->tx_lock);

1339

sky2_tx_complete(sky2, sky2->tx_prod);

1339

sky2_tx_complete(sky2, sky2->tx_prod);

1340

spin_unlock_bh(&sky2->tx_lock);

1340

spin_unlock_bh(&sky2->tx_lock);

1341

}

1341

}

1342

1343

/* Network shutdown */

1343

/* Network shutdown */

1344

static int sky2_down(struct net_device *dev)

1344

static int sky2_down(struct net_device *dev)

1345

{

1345

{

1346

struct sky2_port *sky2 = netdev_priv(dev);

1346

struct sky2_port *sky2 = netdev_priv(dev);

1347

struct sky2_hw *hw = sky2->hw;

1347

struct sky2_hw *hw = sky2->hw;

1348

unsigned port = sky2->port;

1348

unsigned port = sky2->port;

1349

u16 ctrl;

1349

u16 ctrl;

1350

u32 imask;

1350

u32 imask;

1351

1352

/* Never really got started! */

1352

/* Never really got started! */

1353

if (!sky2->tx_le)

1353

if (!sky2->tx_le)

1354

return 0;

1354

return 0;

1355

1356

if (netif_msg_ifdown(sky2))

1356

if (netif_msg_ifdown(sky2))

1357

printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);

1357

printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);

1358

1359

/* Stop more packets from being queued */

1359

/* Stop more packets from being queued */

1360

netif_stop_queue(dev);

1360

netif_stop_queue(dev);

1361

1362

sky2_phy_reset(hw, port);

1362

sky2_phy_reset(hw, port);

1363

1364

/* Stop transmitter */

1364

/* Stop transmitter */

1365

sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);

1365

sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);

1366

sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));

1366

sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));

1367

1368

sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),

1368

sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),

1369

RB_RST_SET | RB_DIS_OP_MD);

1369

RB_RST_SET | RB_DIS_OP_MD);

1370

1371

ctrl = gma_read16(hw, port, GM_GP_CTRL);

1371

ctrl = gma_read16(hw, port, GM_GP_CTRL);

1372

ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);

1372

ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);

1373

gma_write16(hw, port, GM_GP_CTRL, ctrl);

1373

gma_write16(hw, port, GM_GP_CTRL, ctrl);

1374

1375

sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);

1375

sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);

1376

1377

/* Workaround shared GMAC reset */

1377

/* Workaround shared GMAC reset */

1378

if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0

1378

if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0

1379

&& port == 0 && hw->dev[1] && netif_running(hw->dev[1])))

1379

&& port == 0 && hw->dev[1] && netif_running(hw->dev[1])))

1380

sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);

1380

sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);

1381

1382

/* Disable Force Sync bit and Enable Alloc bit */

1382

/* Disable Force Sync bit and Enable Alloc bit */

1383

sky2_write8(hw, SK_REG(port, TXA_CTRL),

1383

sky2_write8(hw, SK_REG(port, TXA_CTRL),

1384

TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);

1384

TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);

1385

1386

/* Stop Interval Timer and Limit Counter of Tx Arbiter */

1386

/* Stop Interval Timer and Limit Counter of Tx Arbiter */

1387

sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);

1387

sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);

1388

sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);

1388

sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);

1389

1390

/* Reset the PCI FIFO of the async Tx queue */

1390

/* Reset the PCI FIFO of the async Tx queue */

1391

sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),

1391

sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),

1392

BMU_RST_SET | BMU_FIFO_RST);

1392

BMU_RST_SET | BMU_FIFO_RST);

1393

1394

/* Reset the Tx prefetch units */

1394

/* Reset the Tx prefetch units */

1395

sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),

1395

sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),

1396

PREF_UNIT_RST_SET);

1396

PREF_UNIT_RST_SET);

1397

1398

sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);

1398

sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);

1399

1400

sky2_rx_stop(sky2);

1400

sky2_rx_stop(sky2);

1401

1402

sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);

1402

sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);

1403

sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);

1403

sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);

1404

1405

/* Disable port IRQ */

1405

/* Disable port IRQ */

1406

imask = sky2_read32(hw, B0_IMSK);

1406

imask = sky2_read32(hw, B0_IMSK);

1407

imask &= ~(sky2->port == 0) ? Y2_IS_PORT_1 : Y2_IS_PORT_2;

1407

imask &= ~(sky2->port == 0) ? Y2_IS_PORT_1 : Y2_IS_PORT_2;

1408

sky2_write32(hw, B0_IMSK, imask);

1408

sky2_write32(hw, B0_IMSK, imask);

1409

1410

/* turn off LED's */

1410

/* turn off LED's */

1411

sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);

1411

sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);

1412

1413

synchronize_irq(hw->pdev->irq);

1413

synchronize_irq(hw->pdev->irq);

1414

1415

sky2_tx_clean(sky2);

1415

sky2_tx_clean(sky2);

1416

sky2_rx_clean(sky2);

1416

sky2_rx_clean(sky2);

1417

1418

pci_free_consistent(hw->pdev, RX_LE_BYTES,

1418

pci_free_consistent(hw->pdev, RX_LE_BYTES,

1419

sky2->rx_le, sky2->rx_le_map);

1419

sky2->rx_le, sky2->rx_le_map);

1420

kfree(sky2->rx_ring);

1420

kfree(sky2->rx_ring);

1421

1422

pci_free_consistent(hw->pdev,

1422

pci_free_consistent(hw->pdev,

1423

TX_RING_SIZE * sizeof(struct sky2_tx_le),

1423

TX_RING_SIZE * sizeof(struct sky2_tx_le),

1424

sky2->tx_le, sky2->tx_le_map);

1424

sky2->tx_le, sky2->tx_le_map);

1425

kfree(sky2->tx_ring);

1425

kfree(sky2->tx_ring);

1426

1427

sky2->tx_le = NULL;

1427

sky2->tx_le = NULL;

1428

sky2->rx_le = NULL;

1428

sky2->rx_le = NULL;

1429

1430

sky2->rx_ring = NULL;

1430

sky2->rx_ring = NULL;

1431

sky2->tx_ring = NULL;

1431

sky2->tx_ring = NULL;

1432

1433

return 0;

1433

return 0;

1434

}

1434

}

1435

1436

static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)

1436

static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)

1437

{

1437

{

1438

if (!hw->copper)

1438

if (!hw->copper)

1439

return SPEED_1000;

1439

return SPEED_1000;

1440

1441

if (hw->chip_id == CHIP_ID_YUKON_FE)

1441

if (hw->chip_id == CHIP_ID_YUKON_FE)

1442

return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;

1442

return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;

1443

1444

switch (aux & PHY_M_PS_SPEED_MSK) {

1444

switch (aux & PHY_M_PS_SPEED_MSK) {

1445

case PHY_M_PS_SPEED_1000:

1445

case PHY_M_PS_SPEED_1000:

1446

return SPEED_1000;

1446

return SPEED_1000;

1447

case PHY_M_PS_SPEED_100:

1447

case PHY_M_PS_SPEED_100:

1448

return SPEED_100;

1448

return SPEED_100;

1449

default:

1449

default:

1450

return SPEED_10;

1450

return SPEED_10;

1451

}

1451

}

1452

}

1452

}

1453

1454

static void sky2_link_up(struct sky2_port *sky2)

1454

static void sky2_link_up(struct sky2_port *sky2)

1455

{

1455

{

1456

struct sky2_hw *hw = sky2->hw;

1456

struct sky2_hw *hw = sky2->hw;

1457

unsigned port = sky2->port;

1457

unsigned port = sky2->port;

1458

u16 reg;

1458

u16 reg;

1459

1460

/* Enable Transmit FIFO Underrun */

1460

/* Enable Transmit FIFO Underrun */

1461

sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);

1461

sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);

1462

1463

reg = gma_read16(hw, port, GM_GP_CTRL);

1463

reg = gma_read16(hw, port, GM_GP_CTRL);

1464

if (sky2->autoneg == AUTONEG_DISABLE) {

1464

if (sky2->autoneg == AUTONEG_DISABLE) {

1465

reg |= GM_GPCR_AU_ALL_DIS;

1465

reg |= GM_GPCR_AU_ALL_DIS;

1466

1467

/* Is write/read necessary? Copied from sky2_mac_init */

1467

/* Is write/read necessary? Copied from sky2_mac_init */

1468

gma_write16(hw, port, GM_GP_CTRL, reg);

1468

gma_write16(hw, port, GM_GP_CTRL, reg);

1469

gma_read16(hw, port, GM_GP_CTRL);

1469

gma_read16(hw, port, GM_GP_CTRL);

1470

1471

switch (sky2->speed) {

1471

switch (sky2->speed) {

1472

case SPEED_1000:

1472

case SPEED_1000:

1473

reg &= ~GM_GPCR_SPEED_100;

1473

reg &= ~GM_GPCR_SPEED_100;

1474

reg |= GM_GPCR_SPEED_1000;

1474

reg |= GM_GPCR_SPEED_1000;

1475

break;

1475

break;

1476

case SPEED_100:

1476

case SPEED_100:

1477

reg &= ~GM_GPCR_SPEED_1000;

1477

reg &= ~GM_GPCR_SPEED_1000;

1478

reg |= GM_GPCR_SPEED_100;

1478

reg |= GM_GPCR_SPEED_100;

1479

break;

1479

break;

1480

case SPEED_10:

1480

case SPEED_10:

1481

reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);

1481

reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);

1482

break;

1482

break;

1483

}

1483

}

1484

} else

1484

} else

1485

reg &= ~GM_GPCR_AU_ALL_DIS;

1485

reg &= ~GM_GPCR_AU_ALL_DIS;

1486

1487

if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE)

1487

if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE)

1488

reg |= GM_GPCR_DUP_FULL;

1488

reg |= GM_GPCR_DUP_FULL;

1489

1490

/* enable Rx/Tx */

1490

/* enable Rx/Tx */

1491

reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;

1491

reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;

1492

gma_write16(hw, port, GM_GP_CTRL, reg);

1492

gma_write16(hw, port, GM_GP_CTRL, reg);

1493

gma_read16(hw, port, GM_GP_CTRL);

1493

gma_read16(hw, port, GM_GP_CTRL);

1494

1495

gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);

1495

gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);

1496

1497

netif_carrier_on(sky2->netdev);

1497

netif_carrier_on(sky2->netdev);

1498

netif_wake_queue(sky2->netdev);

1498

netif_wake_queue(sky2->netdev);

1499

1500

/* Turn on link LED */

1500

/* Turn on link LED */

1501

sky2_write8(hw, SK_REG(port, LNK_LED_REG),

1501

sky2_write8(hw, SK_REG(port, LNK_LED_REG),

1502

LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);

1502

LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);

1503

1504

if (hw->chip_id == CHIP_ID_YUKON_XL) {

1504

if (hw->chip_id == CHIP_ID_YUKON_XL) {

1505

u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);

1505

u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);

1506

1507

gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);

1507

gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);

1508

gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */

1508

gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */

1509

PHY_M_LEDC_INIT_CTRL(sky2->speed ==

1509

PHY_M_LEDC_INIT_CTRL(sky2->speed ==

1510

SPEED_10 ? 7 : 0) |

1510

SPEED_10 ? 7 : 0) |

1511

PHY_M_LEDC_STA1_CTRL(sky2->speed ==

1511

PHY_M_LEDC_STA1_CTRL(sky2->speed ==

1512

SPEED_100 ? 7 : 0) |

1512

SPEED_100 ? 7 : 0) |

1513

PHY_M_LEDC_STA0_CTRL(sky2->speed ==

1513

PHY_M_LEDC_STA0_CTRL(sky2->speed ==

1514

SPEED_1000 ? 7 : 0));

1514

SPEED_1000 ? 7 : 0));

1515

gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);

1515

gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);

1516

}

1516

}

1517

1518

if (netif_msg_link(sky2))

1518

if (netif_msg_link(sky2))

1519

printk(KERN_INFO PFX

1519

printk(KERN_INFO PFX

1520

"%s: Link is up at %d Mbps, %s duplex, flow control %s\n",

1520

"%s: Link is up at %d Mbps, %s duplex, flow control %s\n",

1521

sky2->netdev->name, sky2->speed,

1521

sky2->netdev->name, sky2->speed,

1522

sky2->duplex == DUPLEX_FULL ? "full" : "half",

1522

sky2->duplex == DUPLEX_FULL ? "full" : "half",

1523

(sky2->tx_pause && sky2->rx_pause) ? "both" :

1523

(sky2->tx_pause && sky2->rx_pause) ? "both" :

1524

sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");

1524

sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");

1525

}

1525

}

1526

1527

static void sky2_link_down(struct sky2_port *sky2)

1527

static void sky2_link_down(struct sky2_port *sky2)

1528

{

1528

{

1529

struct sky2_hw *hw = sky2->hw;

1529

struct sky2_hw *hw = sky2->hw;

1530

unsigned port = sky2->port;

1530

unsigned port = sky2->port;

1531

u16 reg;

1531

u16 reg;

1532

1533

gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);

1533

gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);

1534

1535

reg = gma_read16(hw, port, GM_GP_CTRL);

1535

reg = gma_read16(hw, port, GM_GP_CTRL);

1536

reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);

1536

reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);

1537

gma_write16(hw, port, GM_GP_CTRL, reg);

1537

gma_write16(hw, port, GM_GP_CTRL, reg);

1538

gma_read16(hw, port, GM_GP_CTRL); /* PCI post */

1538

gma_read16(hw, port, GM_GP_CTRL); /* PCI post */

1539

1540

if (sky2->rx_pause && !sky2->tx_pause) {

1540

if (sky2->rx_pause && !sky2->tx_pause) {

1541

/* restore Asymmetric Pause bit */

1541

/* restore Asymmetric Pause bit */

1542

gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,

1542

gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,

1543

gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)

1543

gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)

1544

| PHY_M_AN_ASP);

1544

| PHY_M_AN_ASP);

1545

}

1545

}

1546

1547

netif_carrier_off(sky2->netdev);

1547

netif_carrier_off(sky2->netdev);

1548

netif_stop_queue(sky2->netdev);

1548

netif_stop_queue(sky2->netdev);

1549

1550

/* Turn on link LED */

1550

/* Turn on link LED */

1551

sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);

1551

sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);

1552

1553

if (netif_msg_link(sky2))

1553

if (netif_msg_link(sky2))

1554

printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);

1554

printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);

1555

sky2_phy_init(hw, port);

1555

sky2_phy_init(hw, port);

1556

}

1556

}

1557

1558

static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)

1558

static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)

1559

{

1559

{

1560

struct sky2_hw *hw = sky2->hw;

1560

struct sky2_hw *hw = sky2->hw;

1561

unsigned port = sky2->port;

1561

unsigned port = sky2->port;

1562

u16 lpa;

1562

u16 lpa;

1563

1564

lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);

1564

lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);

1565

1566

if (lpa & PHY_M_AN_RF) {

1566

if (lpa & PHY_M_AN_RF) {

1567

printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);

1567

printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);

1568

return -1;

1568

return -1;

1569

}

1569

}

1570

1571

if (hw->chip_id != CHIP_ID_YUKON_FE &&

1571

if (hw->chip_id != CHIP_ID_YUKON_FE &&

1572

gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {

1572

gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {

1573

printk(KERN_ERR PFX "%s: master/slave fault",

1573

printk(KERN_ERR PFX "%s: master/slave fault",

1574

sky2->netdev->name);

1574

sky2->netdev->name);

1575

return -1;

1575

return -1;

1576

}

1576

}

1577

1578

if (!(aux & PHY_M_PS_SPDUP_RES)) {

1578

if (!(aux & PHY_M_PS_SPDUP_RES)) {

1579

printk(KERN_ERR PFX "%s: speed/duplex mismatch",

1579

printk(KERN_ERR PFX "%s: speed/duplex mismatch",

1580

sky2->netdev->name);

1580

sky2->netdev->name);

1581

return -1;

1581

return -1;

1582

}

1582

}

1583

1584

sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;

1584

sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;

1585

1586

sky2->speed = sky2_phy_speed(hw, aux);

1586

sky2->speed = sky2_phy_speed(hw, aux);

1587

1588

/* Pause bits are offset (9..8) */

1588

/* Pause bits are offset (9..8) */

1589

if (hw->chip_id == CHIP_ID_YUKON_XL)

1589

if (hw->chip_id == CHIP_ID_YUKON_XL)

1590

aux >>= 6;

1590

aux >>= 6;

1591

1592

sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;

1592

sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;

1593

sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;

1593

sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;

1594

1595

if ((sky2->tx_pause || sky2->rx_pause)

1595

if ((sky2->tx_pause || sky2->rx_pause)

1596

&& !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF))

1596

&& !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF))

1597

sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);

1597

sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);

1598

else

1598

else

1599

sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);

1599

sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);

1600

1601

return 0;

1601

return 0;

1602

}

1602

}

1603

1604

/* Interrupt from PHY */

1604

/* Interrupt from PHY */

1605

static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)

1605

static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)

1606

{

1606

{

1607

struct net_device *dev = hw->dev[port];

1607

struct net_device *dev = hw->dev[port];

1608

struct sky2_port *sky2 = netdev_priv(dev);

1608

struct sky2_port *sky2 = netdev_priv(dev);

1609

u16 istatus, phystat;

1609

u16 istatus, phystat;

1610

1611

spin_lock(&sky2->phy_lock);

1611

spin_lock(&sky2->phy_lock);

1612

istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);

1612

istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);

1613

phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);

1613

phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);

1614

1615

if (!netif_running(dev))

1615

if (!netif_running(dev))

1616

goto out;

1616

goto out;

1617

1618

if (netif_msg_intr(sky2))

1618

if (netif_msg_intr(sky2))

1619

printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",

1619

printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",

1620

sky2->netdev->name, istatus, phystat);

1620

sky2->netdev->name, istatus, phystat);

1621

1622

if (istatus & PHY_M_IS_AN_COMPL) {

1622

if (istatus & PHY_M_IS_AN_COMPL) {

1623

if (sky2_autoneg_done(sky2, phystat) == 0)

1623

if (sky2_autoneg_done(sky2, phystat) == 0)

1624

sky2_link_up(sky2);

1624

sky2_link_up(sky2);

1625

goto out;

1625

goto out;

1626

}

1626

}

1627

1628

if (istatus & PHY_M_IS_LSP_CHANGE)

1628

if (istatus & PHY_M_IS_LSP_CHANGE)

1629

sky2->speed = sky2_phy_speed(hw, phystat);

1629

sky2->speed = sky2_phy_speed(hw, phystat);

1630

1631

if (istatus & PHY_M_IS_DUP_CHANGE)

1631

if (istatus & PHY_M_IS_DUP_CHANGE)

1632

sky2->duplex =

1632

sky2->duplex =

1633

(phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;

1633

(phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;

1634

1635

if (istatus & PHY_M_IS_LST_CHANGE) {

1635

if (istatus & PHY_M_IS_LST_CHANGE) {

1636

if (phystat & PHY_M_PS_LINK_UP)

1636

if (phystat & PHY_M_PS_LINK_UP)

1637

sky2_link_up(sky2);

1637

sky2_link_up(sky2);

1638

else

1638

else

1639

sky2_link_down(sky2);

1639

sky2_link_down(sky2);

1640

}

1640

}

1641

out:

1641

out:

1642

spin_unlock(&sky2->phy_lock);

1642

spin_unlock(&sky2->phy_lock);

1643

}

1643

}

1644

1645

1646

/* Transmit timeout is only called if we are running, carries is up

1646

/* Transmit timeout is only called if we are running, carries is up

1647

* and tx queue is full (stopped).

1647

* and tx queue is full (stopped).

1648

*/

1648

*/

1649

static void sky2_tx_timeout(struct net_device *dev)

1649

static void sky2_tx_timeout(struct net_device *dev)

1650

{

1650

{

1651

struct sky2_port *sky2 = netdev_priv(dev);

1651

struct sky2_port *sky2 = netdev_priv(dev);

1652

struct sky2_hw *hw = sky2->hw;

1652

struct sky2_hw *hw = sky2->hw;

1653

unsigned txq = txqaddr[sky2->port];

1653

unsigned txq = txqaddr[sky2->port];

1654

u16 report, done;

1654

u16 report, done;

1655

1656

if (netif_msg_timer(sky2))

1656

if (netif_msg_timer(sky2))

1657

printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);

1657

printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);

1658

1659

report = sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX);

1659

report = sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX);

1660

done = sky2_read16(hw, Q_ADDR(txq, Q_DONE));

1660

done = sky2_read16(hw, Q_ADDR(txq, Q_DONE));

1661

1662

printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",

1662

printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",

1663

dev->name,

1663

dev->name,

1664

sky2->tx_cons, sky2->tx_prod, report, done);

1664

sky2->tx_cons, sky2->tx_prod, report, done);

1665

1666

if (report != done) {

1666

if (report != done) {

1667

printk(KERN_INFO PFX "status burst pending (irq moderation?)\n");

1667

printk(KERN_INFO PFX "status burst pending (irq moderation?)\n");

1668

1669

sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);

1669

sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);

1670

sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);

1670

sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);

1671

} else if (report != sky2->tx_cons) {

1671

} else if (report != sky2->tx_cons) {

1672

printk(KERN_INFO PFX "status report lost?\n");

1672

printk(KERN_INFO PFX "status report lost?\n");

1673

1674

spin_lock_bh(&sky2->tx_lock);

1674

spin_lock_bh(&sky2->tx_lock);

1675

sky2_tx_complete(sky2, report);

1675

sky2_tx_complete(sky2, report);

1676

spin_unlock_bh(&sky2->tx_lock);

1676

spin_unlock_bh(&sky2->tx_lock);

1677

} else {

1677

} else {

1678

printk(KERN_INFO PFX "hardware hung? flushing\n");

1678

printk(KERN_INFO PFX "hardware hung? flushing\n");

1679

1680

sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP);

1680

sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP);

1681

sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);

1681

sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);

1682

1683

sky2_tx_clean(sky2);

1683

sky2_tx_clean(sky2);

1684

1685

sky2_qset(hw, txq);

1685

sky2_qset(hw, txq);

1686

sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1);

1686

sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1);

1687

}

1687

}

1688

}

1688

}

1689

1690

1691

#define roundup(x, y) ((((x)+((y)-1))/(y))*(y))

1691

#define roundup(x, y) ((((x)+((y)-1))/(y))*(y))

1692

/* Want receive buffer size to be multiple of 64 bits

1692

/* Want receive buffer size to be multiple of 64 bits

1693

* and incl room for vlan and truncation

1693

* and incl room for vlan and truncation

1694

*/

1694

*/

1695

static inline unsigned sky2_buf_size(int mtu)

1695

static inline unsigned sky2_buf_size(int mtu)

1696

{

1696

{

1697

return roundup(mtu + ETH_HLEN + VLAN_HLEN, 8) + 8;

1697

return roundup(mtu + ETH_HLEN + VLAN_HLEN, 8) + 8;

1698

}

1698

}

1699

1700

static int sky2_change_mtu(struct net_device *dev, int new_mtu)

1700

static int sky2_change_mtu(struct net_device *dev, int new_mtu)

1701

{

1701

{

1702

struct sky2_port *sky2 = netdev_priv(dev);

1702

struct sky2_port *sky2 = netdev_priv(dev);

1703

struct sky2_hw *hw = sky2->hw;

1703

struct sky2_hw *hw = sky2->hw;

1704

int err;

1704

int err;

1705

u16 ctl, mode;

1705

u16 ctl, mode;

1706

u32 imask;

1706

u32 imask;

1707

1708

if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)

1708

if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)

1709

return -EINVAL;

1709

return -EINVAL;

1710

1711

if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)

1711

if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)

1712

return -EINVAL;

1712

return -EINVAL;

1713

1714

if (!netif_running(dev)) {

1714

if (!netif_running(dev)) {

1715

dev->mtu = new_mtu;

1715

dev->mtu = new_mtu;

1716

return 0;

1716

return 0;

1717

}

1717

}

1718

1719

imask = sky2_read32(hw, B0_IMSK);

1719

imask = sky2_read32(hw, B0_IMSK);

1720

sky2_write32(hw, B0_IMSK, 0);

1720

sky2_write32(hw, B0_IMSK, 0);

1721

1722

dev->trans_start = jiffies; /* prevent tx timeout */

1722

dev->trans_start = jiffies; /* prevent tx timeout */

1723

netif_stop_queue(dev);

1723

netif_stop_queue(dev);

1724

netif_poll_disable(hw->dev[0]);

1724

netif_poll_disable(hw->dev[0]);

1725

1726

synchronize_irq(hw->pdev->irq);

1726

synchronize_irq(hw->pdev->irq);

1727

1728

ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);

1728

ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);

1729

gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);

1729

gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);

1730

sky2_rx_stop(sky2);

1730

sky2_rx_stop(sky2);

1731

sky2_rx_clean(sky2);

1731

sky2_rx_clean(sky2);

1732

1733

dev->mtu = new_mtu;

1733

dev->mtu = new_mtu;

1734

sky2->rx_bufsize = sky2_buf_size(new_mtu);

1734

sky2->rx_bufsize = sky2_buf_size(new_mtu);

1735

mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |

1735

mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |

1736

GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);

1736

GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);

1737

1738

if (dev->mtu > ETH_DATA_LEN)

1738

if (dev->mtu > ETH_DATA_LEN)

1739

mode |= GM_SMOD_JUMBO_ENA;

1739

mode |= GM_SMOD_JUMBO_ENA;

1740

1741

gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);

1741

gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);

1742

1743

sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);

1743

sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);

1744

1745

err = sky2_rx_start(sky2);

1745

err = sky2_rx_start(sky2);

1746

sky2_write32(hw, B0_IMSK, imask);

1746

sky2_write32(hw, B0_IMSK, imask);

1747

1748

if (err)

1748

if (err)

1749

dev_close(dev);

1749

dev_close(dev);

1750

else {

1750

else {

1751

gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);

1751

gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);

1752

1753

netif_poll_enable(hw->dev[0]);

1753

netif_poll_enable(hw->dev[0]);

1754

netif_wake_queue(dev);

1754

netif_wake_queue(dev);

1755

}

1755

}

1756

1757

return err;

1757

return err;

1758

}

1758

}

1759

1760

/*

1760

/*

1761

* Receive one packet.

1761

* Receive one packet.

1762

* For small packets or errors, just reuse existing skb.

1762

* For small packets or errors, just reuse existing skb.

1763

* For larger packets, get new buffer.

1763

* For larger packets, get new buffer.

1764

*/

1764

*/

1765

static struct sk_buff *sky2_receive(struct sky2_port *sky2,

1765

static struct sk_buff *sky2_receive(struct sky2_port *sky2,

1766

u16 length, u32 status)

1766

u16 length, u32 status)

1767

{

1767

{

1768

struct ring_info *re = sky2->rx_ring + sky2->rx_next;

1768

struct ring_info *re = sky2->rx_ring + sky2->rx_next;

1769

struct sk_buff *skb = NULL;

1769

struct sk_buff *skb = NULL;

1770

1771

if (unlikely(netif_msg_rx_status(sky2)))

1771

if (unlikely(netif_msg_rx_status(sky2)))

1772

printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",

1772

printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",

1773

sky2->netdev->name, sky2->rx_next, status, length);

1773

sky2->netdev->name, sky2->rx_next, status, length);

1774

1775

sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;

1775

sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;

1776

prefetch(sky2->rx_ring + sky2->rx_next);

1776

prefetch(sky2->rx_ring + sky2->rx_next);

1777

1778

if (status & GMR_FS_ANY_ERR)

1778

if (status & GMR_FS_ANY_ERR)

1779

goto error;

1779

goto error;

1780

1781

if (!(status & GMR_FS_RX_OK))

1781

if (!(status & GMR_FS_RX_OK))

1782

goto resubmit;

1782

goto resubmit;

1783

1784

if (length > sky2->netdev->mtu + ETH_HLEN)

1784

if (length > sky2->netdev->mtu + ETH_HLEN)

1785

goto oversize;

1785

goto oversize;

1786

1787

if (length < copybreak) {

1787

if (length < copybreak) {

1788

skb = alloc_skb(length + 2, GFP_ATOMIC);

1788

skb = alloc_skb(length + 2, GFP_ATOMIC);

1789

if (!skb)

1789

if (!skb)

1790

goto resubmit;

1790

goto resubmit;

1791

1792

skb_reserve(skb, 2);

1792

skb_reserve(skb, 2);

1793

pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr,

1793

pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr,

1794

length, PCI_DMA_FROMDEVICE);

1794

length, PCI_DMA_FROMDEVICE);

1795

memcpy(skb->data, re->skb->data, length);

1795

memcpy(skb->data, re->skb->data, length);

1796

skb->ip_summed = re->skb->ip_summed;

1796

skb->ip_summed = re->skb->ip_summed;

1797

skb->csum = re->skb->csum;

1797

skb->csum = re->skb->csum;

1798

pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr,

1798

pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr,

1799

length, PCI_DMA_FROMDEVICE);

1799

length, PCI_DMA_FROMDEVICE);

1800

} else {

1800

} else {

1801

struct sk_buff *nskb;

1801

struct sk_buff *nskb;

1802

1803

nskb = sky2_alloc_skb(sky2->rx_bufsize, GFP_ATOMIC);

1803

nskb = sky2_alloc_skb(sky2->rx_bufsize, GFP_ATOMIC);

1804

if (!nskb)

1804

if (!nskb)

1805

goto resubmit;

1805

goto resubmit;

1806

1807

skb = re->skb;

1807

skb = re->skb;

1808

re->skb = nskb;

1808

re->skb = nskb;

1809

pci_unmap_single(sky2->hw->pdev, re->mapaddr,

1809

pci_unmap_single(sky2->hw->pdev, re->mapaddr,

1810

sky2->rx_bufsize, PCI_DMA_FROMDEVICE);

1810

sky2->rx_bufsize, PCI_DMA_FROMDEVICE);

1811

prefetch(skb->data);

1811

prefetch(skb->data);

1812

1813

re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,

1813

re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,

1814

sky2->rx_bufsize, PCI_DMA_FROMDEVICE);

1814

sky2->rx_bufsize, PCI_DMA_FROMDEVICE);

1815

}

1815

}

1816

1817

skb_put(skb, length);

1817

skb_put(skb, length);

1818

resubmit:

1818

resubmit:

1819

re->skb->ip_summed = CHECKSUM_NONE;

1819

re->skb->ip_summed = CHECKSUM_NONE;

1820

sky2_rx_add(sky2, re->mapaddr);

1820

sky2_rx_add(sky2, re->mapaddr);

1821

1822

/* Tell receiver about new buffers. */

1822

/* Tell receiver about new buffers. */

1823

sky2_put_idx(sky2->hw, rxqaddr[sky2->port], sky2->rx_put);

1823

sky2_put_idx(sky2->hw, rxqaddr[sky2->port], sky2->rx_put);

1824

1825

return skb;

1825

return skb;

1826

1827

oversize:

1827

oversize:

1828

++sky2->net_stats.rx_over_errors;

1828

++sky2->net_stats.rx_over_errors;

1829

goto resubmit;

1829

goto resubmit;

1830

1831

error:

1831

error:

1832

++sky2->net_stats.rx_errors;

1832

++sky2->net_stats.rx_errors;

1833

1834

if (netif_msg_rx_err(sky2) && net_ratelimit())

1834

if (netif_msg_rx_err(sky2) && net_ratelimit())

1835

printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",

1835

printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",

1836

sky2->netdev->name, status, length);

1836

sky2->netdev->name, status, length);

1837

1838

if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))

1838

if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))

1839

sky2->net_stats.rx_length_errors++;

1839

sky2->net_stats.rx_length_errors++;

1840

if (status & GMR_FS_FRAGMENT)

1840

if (status & GMR_FS_FRAGMENT)

1841

sky2->net_stats.rx_frame_errors++;

1841

sky2->net_stats.rx_frame_errors++;

1842

if (status & GMR_FS_CRC_ERR)

1842

if (status & GMR_FS_CRC_ERR)

1843

sky2->net_stats.rx_crc_errors++;

1843

sky2->net_stats.rx_crc_errors++;

1844

if (status & GMR_FS_RX_FF_OV)

1844

if (status & GMR_FS_RX_FF_OV)

1845

sky2->net_stats.rx_fifo_errors++;

1845

sky2->net_stats.rx_fifo_errors++;

1846

1847

goto resubmit;

1847

goto resubmit;

1848

}

1848

}

1849

1850

/* Transmit complete */

1850

/* Transmit complete */

1851

static inline void sky2_tx_done(struct net_device *dev, u16 last)

1851

static inline void sky2_tx_done(struct net_device *dev, u16 last)

1852

{

1852

{

1853

struct sky2_port *sky2 = netdev_priv(dev);

1853

struct sky2_port *sky2 = netdev_priv(dev);

1854

1855

if (netif_running(dev)) {

1855

if (netif_running(dev)) {

1856

spin_lock(&sky2->tx_lock);

1856

spin_lock(&sky2->tx_lock);

1857

sky2_tx_complete(sky2, last);

1857

sky2_tx_complete(sky2, last);

1858

spin_unlock(&sky2->tx_lock);

1858

spin_unlock(&sky2->tx_lock);

1859

}

1859

}

1860

}

1860

}

1861

1862

/* Process status response ring */

1862

/* Process status response ring */

1863

static int sky2_status_intr(struct sky2_hw *hw, int to_do)

1863

static int sky2_status_intr(struct sky2_hw *hw, int to_do)

1864

{

1864

{

1865

int work_done = 0;

1865

int work_done = 0;

1866

1867

rmb();

1867

rmb();

1868

1869

for(;;) {

1869

for(;;) {

1870

struct sky2_status_le *le = hw->st_le + hw->st_idx;

1870

struct sky2_status_le *le = hw->st_le + hw->st_idx;

1871

struct net_device *dev;

1871

struct net_device *dev;

1872

struct sky2_port *sky2;

1872

struct sky2_port *sky2;

1873

struct sk_buff *skb;

1873

struct sk_buff *skb;

1874

u32 status;

1874

u32 status;

1875

u16 length;

1875

u16 length;

1876

u8 link, opcode;

1876

u8 link, opcode;

1877

1878

opcode = le->opcode;

1878

opcode = le->opcode;

1879

if (!opcode)

1879

if (!opcode)

1880

break;

1880

break;

1881

opcode &= ~HW_OWNER;

1881

opcode &= ~HW_OWNER;

1882

1883

hw->st_idx = (hw->st_idx + 1) % STATUS_RING_SIZE;

1883

hw->st_idx = (hw->st_idx + 1) % STATUS_RING_SIZE;

1884

le->opcode = 0;

1884

le->opcode = 0;

1885

1886

link = le->link;

1886

link = le->link;

1887

BUG_ON(link >= 2);

1887

BUG_ON(link >= 2);

1888

dev = hw->dev[link];

1888

dev = hw->dev[link];

1889

1890

sky2 = netdev_priv(dev);

1890

sky2 = netdev_priv(dev);

1891

length = le->length;

1891

length = le->length;

1892

status = le->status;

1892

status = le->status;

1893

1894

switch (opcode) {

1894

switch (opcode) {

1895

case OP_RXSTAT:

1895

case OP_RXSTAT:

1896

skb = sky2_receive(sky2, length, status);

1896

skb = sky2_receive(sky2, length, status);

1897

if (!skb)

1897

if (!skb)

1898

break;

1898

break;

1899

1900

skb->dev = dev;

1900

skb->dev = dev;

1901

skb->protocol = eth_type_trans(skb, dev);

1901

skb->protocol = eth_type_trans(skb, dev);

1902

dev->last_rx = jiffies;

1902

dev->last_rx = jiffies;

1903

1904

#ifdef SKY2_VLAN_TAG_USED

1904

#ifdef SKY2_VLAN_TAG_USED

1905

if (sky2->vlgrp && (status & GMR_FS_VLAN)) {

1905

if (sky2->vlgrp && (status & GMR_FS_VLAN)) {

1906

vlan_hwaccel_receive_skb(skb,

1906

vlan_hwaccel_receive_skb(skb,

1907

sky2->vlgrp,

1907

sky2->vlgrp,

1908

be16_to_cpu(sky2->rx_tag));

1908

be16_to_cpu(sky2->rx_tag));

1909

} else

1909

} else

1910

#endif

1910

#endif

1911

netif_receive_skb(skb);

1911

netif_receive_skb(skb);

1912

1913

if (++work_done >= to_do)

1913

if (++work_done >= to_do)

1914

goto exit_loop;

1914

goto exit_loop;

1915

break;

1915

break;

1916

1917

#ifdef SKY2_VLAN_TAG_USED

1917

#ifdef SKY2_VLAN_TAG_USED

1918

case OP_RXVLAN:

1918

case OP_RXVLAN:

1919

sky2->rx_tag = length;

1919

sky2->rx_tag = length;

1920

break;

1920

break;

1921

1922

case OP_RXCHKSVLAN:

1922

case OP_RXCHKSVLAN:

1923

sky2->rx_tag = length;

1923

sky2->rx_tag = length;

1924

/* fall through */

1924

/* fall through */

1925

#endif

1925

#endif

1926

case OP_RXCHKS:

1926

case OP_RXCHKS:

1927

skb = sky2->rx_ring[sky2->rx_next].skb;

1927

skb = sky2->rx_ring[sky2->rx_next].skb;

1928

skb->ip_summed = CHECKSUM_HW;

1928

skb->ip_summed = CHECKSUM_HW;

1929

skb->csum = le16_to_cpu(status);

1929

skb->csum = le16_to_cpu(status);

1930

break;

1930

break;

1931

1932

case OP_TXINDEXLE:

1932

case OP_TXINDEXLE:

1933

/* TX index reports status for both ports */

1933

/* TX index reports status for both ports */

1934

sky2_tx_done(hw->dev[0], status & 0xffff);

1934

sky2_tx_done(hw->dev[0], status & 0xffff);

1935

if (hw->dev[1])

1935

if (hw->dev[1])

1936

sky2_tx_done(hw->dev[1],

1936

sky2_tx_done(hw->dev[1],

1937

((status >> 24) & 0xff)

1937

((status >> 24) & 0xff)

1938

| (u16)(length & 0xf) << 8);

1938

| (u16)(length & 0xf) << 8);

1939

break;

1939

break;

1940

1941

default:

1941

default:

1942

if (net_ratelimit())

1942

if (net_ratelimit())

1943

printk(KERN_WARNING PFX

1943

printk(KERN_WARNING PFX

1944

"unknown status opcode 0x%x\n", opcode);

1944

"unknown status opcode 0x%x\n", opcode);

1945

break;

1945

break;

1946

}

1946

}

1947

}

1947

}

1948

1949

exit_loop:

1949

exit_loop:

1950

return work_done;

1950

return work_done;

1951

}

1951

}

1952

1953

static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)

1953

static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)

1954

{

1954

{

1955

struct net_device *dev = hw->dev[port];

1955

struct net_device *dev = hw->dev[port];

1956

1957

if (net_ratelimit())

1957

if (net_ratelimit())

1958

printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",

1958

printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",

1959

dev->name, status);

1959

dev->name, status);

1960

1961

if (status & Y2_IS_PAR_RD1) {

1961

if (status & Y2_IS_PAR_RD1) {

1962

if (net_ratelimit())

1962

if (net_ratelimit())

1963

printk(KERN_ERR PFX "%s: ram data read parity error\n",

1963

printk(KERN_ERR PFX "%s: ram data read parity error\n",

1964

dev->name);

1964

dev->name);

1965

/* Clear IRQ */

1965

/* Clear IRQ */

1966

sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);

1966

sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);

1967

}

1967

}

1968

1969

if (status & Y2_IS_PAR_WR1) {

1969

if (status & Y2_IS_PAR_WR1) {

1970

if (net_ratelimit())

1970

if (net_ratelimit())

1971

printk(KERN_ERR PFX "%s: ram data write parity error\n",

1971

printk(KERN_ERR PFX "%s: ram data write parity error\n",

1972

dev->name);

1972

dev->name);

1973

1974

sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);

1974

sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);

1975

}

1975

}

1976

1977

if (status & Y2_IS_PAR_MAC1) {

1977

if (status & Y2_IS_PAR_MAC1) {

1978

if (net_ratelimit())

1978

if (net_ratelimit())

1979

printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);

1979

printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);

1980

sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);

1980

sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);

1981

}

1981

}

1982

1983

if (status & Y2_IS_PAR_RX1) {

1983

if (status & Y2_IS_PAR_RX1) {

1984

if (net_ratelimit())

1984

if (net_ratelimit())

1985

printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);

1985

printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);

1986

sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);

1986

sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);

1987

}

1987

}

1988

1989

if (status & Y2_IS_TCP_TXA1) {

1989

if (status & Y2_IS_TCP_TXA1) {

1990

if (net_ratelimit())

1990

if (net_ratelimit())

1991

printk(KERN_ERR PFX "%s: TCP segmentation error\n",

1991

printk(KERN_ERR PFX "%s: TCP segmentation error\n",

1992

dev->name);

1992

dev->name);

1993

sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);

1993

sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);

1994

}

1994

}

1995

}

1995

}

1996

1997

static void sky2_hw_intr(struct sky2_hw *hw)

1997

static void sky2_hw_intr(struct sky2_hw *hw)

1998

{

1998

{

1999

u32 status = sky2_read32(hw, B0_HWE_ISRC);

1999

u32 status = sky2_read32(hw, B0_HWE_ISRC);

2000

2001

if (status & Y2_IS_TIST_OV)

2001

if (status & Y2_IS_TIST_OV)

2002

sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);

2002

sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);

2003

2004

if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {

2004

if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {

2005

u16 pci_err;

2005

u16 pci_err;

2006

2007

pci_err = sky2_pci_read16(hw, PCI_STATUS);

2007

pci_err = sky2_pci_read16(hw, PCI_STATUS);

2008

if (net_ratelimit())

2008

if (net_ratelimit())

2009

printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",

2009

printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",

2010

pci_name(hw->pdev), pci_err);

2010

pci_name(hw->pdev), pci_err);

2011

2012

sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);

2012

sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);

2013

sky2_pci_write16(hw, PCI_STATUS,

2013

sky2_pci_write16(hw, PCI_STATUS,

2014

pci_err | PCI_STATUS_ERROR_BITS);

2014

pci_err | PCI_STATUS_ERROR_BITS);

2015

sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);

2015

sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);

2016

}

2016

}

2017

2018

if (status & Y2_IS_PCI_EXP) {

2018

if (status & Y2_IS_PCI_EXP) {

2019

/* PCI-Express uncorrectable Error occurred */

2019

/* PCI-Express uncorrectable Error occurred */

2020

u32 pex_err;

2020

u32 pex_err;

2021

2022

pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);

2022

pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);

2023

2024

if (net_ratelimit())

2024

if (net_ratelimit())

2025

printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",

2025

printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",

2026

pci_name(hw->pdev), pex_err);

2026

pci_name(hw->pdev), pex_err);

2027

2028

/* clear the interrupt */

2028

/* clear the interrupt */

2029

sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);

2029

sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);

2030

sky2_pci_write32(hw, PEX_UNC_ERR_STAT,

2030

sky2_pci_write32(hw, PEX_UNC_ERR_STAT,

2031

0xffffffffUL);

2031

0xffffffffUL);

2032

sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);

2032

sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);

2033

2034

if (pex_err & PEX_FATAL_ERRORS) {

2034

if (pex_err & PEX_FATAL_ERRORS) {

2035

u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);

2035

u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);

2036

hwmsk &= ~Y2_IS_PCI_EXP;

2036

hwmsk &= ~Y2_IS_PCI_EXP;

2037

sky2_write32(hw, B0_HWE_IMSK, hwmsk);

2037

sky2_write32(hw, B0_HWE_IMSK, hwmsk);

2038

}

2038

}

2039

}

2039

}

2040

2041

if (status & Y2_HWE_L1_MASK)

2041

if (status & Y2_HWE_L1_MASK)

2042

sky2_hw_error(hw, 0, status);

2042

sky2_hw_error(hw, 0, status);

2043

status >>= 8;

2043

status >>= 8;

2044

if (status & Y2_HWE_L1_MASK)

2044

if (status & Y2_HWE_L1_MASK)

2045

sky2_hw_error(hw, 1, status);

2045

sky2_hw_error(hw, 1, status);

2046

}

2046

}

2047

2048

static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)

2048

static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)

2049

{

2049

{

2050

struct net_device *dev = hw->dev[port];

2050

struct net_device *dev = hw->dev[port];

2051

struct sky2_port *sky2 = netdev_priv(dev);

2051

struct sky2_port *sky2 = netdev_priv(dev);

2052

u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));

2052

u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));

2053

2054

if (netif_msg_intr(sky2))

2054

if (netif_msg_intr(sky2))

2055

printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",

2055

printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",

2056

dev->name, status);

2056

dev->name, status);

2057

2058

if (status & GM_IS_RX_FF_OR) {

2058

if (status & GM_IS_RX_FF_OR) {

2059

++sky2->net_stats.rx_fifo_errors;

2059

++sky2->net_stats.rx_fifo_errors;

2060

sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);

2060

sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);

2061

}

2061

}

2062

2063

if (status & GM_IS_TX_FF_UR) {

2063

if (status & GM_IS_TX_FF_UR) {

2064

++sky2->net_stats.tx_fifo_errors;

2064

++sky2->net_stats.tx_fifo_errors;

2065

sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);

2065

sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);

2066

}

2066

}

2067

}

2067

}

2068

2069

/* This should never happen it is a fatal situation */

2069

/* This should never happen it is a fatal situation */

2070

static void sky2_descriptor_error(struct sky2_hw *hw, unsigned port,

2070

static void sky2_descriptor_error(struct sky2_hw *hw, unsigned port,

2071

const char *rxtx, u32 mask)

2071

const char *rxtx, u32 mask)

2072

{

2072

{

2073

struct net_device *dev = hw->dev[port];

2073

struct net_device *dev = hw->dev[port];

2074

struct sky2_port *sky2 = netdev_priv(dev);

2074

struct sky2_port *sky2 = netdev_priv(dev);

2075

u32 imask;

2075

u32 imask;

2076

2077

printk(KERN_ERR PFX "%s: %s descriptor error (hardware problem)\n",

2077

printk(KERN_ERR PFX "%s: %s descriptor error (hardware problem)\n",

2078

dev ? dev->name : "<not registered>", rxtx);

2078

dev ? dev->name : "<not registered>", rxtx);

2079

2080

imask = sky2_read32(hw, B0_IMSK);

2080

imask = sky2_read32(hw, B0_IMSK);

2081

imask &= ~mask;

2081

imask &= ~mask;

2082

sky2_write32(hw, B0_IMSK, imask);

2082

sky2_write32(hw, B0_IMSK, imask);

2083

2084

if (dev) {

2084

if (dev) {

2085

spin_lock(&sky2->phy_lock);

2085

spin_lock(&sky2->phy_lock);

2086

sky2_link_down(sky2);

2086

sky2_link_down(sky2);

2087

spin_unlock(&sky2->phy_lock);

2087

spin_unlock(&sky2->phy_lock);

2088

}

2088

}

2089

}

2089

}

2090

2091

static int sky2_poll(struct net_device *dev0, int *budget)

2091

static int sky2_poll(struct net_device *dev0, int *budget)

2092

{

2092

{

2093

struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;

2093

struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;

2094

int work_limit = min(dev0->quota, *budget);

2094

int work_limit = min(dev0->quota, *budget);

2095

int work_done = 0;

2095

int work_done = 0;

2096

u32 status = sky2_read32(hw, B0_Y2_SP_EISR);

2096

u32 status = sky2_read32(hw, B0_Y2_SP_EISR);

2097

2098

if (unlikely(status & ~Y2_IS_STAT_BMU)) {

2098

if (unlikely(status & ~Y2_IS_STAT_BMU)) {

2099

if (status & Y2_IS_HW_ERR)

2099

if (status & Y2_IS_HW_ERR)

2100

sky2_hw_intr(hw);

2100

sky2_hw_intr(hw);

2101

2102

if (status & Y2_IS_IRQ_PHY1)

2102

if (status & Y2_IS_IRQ_PHY1)

2103

sky2_phy_intr(hw, 0);

2103

sky2_phy_intr(hw, 0);

2104

2105

if (status & Y2_IS_IRQ_PHY2)

2105

if (status & Y2_IS_IRQ_PHY2)

2106

sky2_phy_intr(hw, 1);

2106

sky2_phy_intr(hw, 1);

2107

2108

if (status & Y2_IS_IRQ_MAC1)

2108

if (status & Y2_IS_IRQ_MAC1)

2109

sky2_mac_intr(hw, 0);

2109

sky2_mac_intr(hw, 0);

2110

2111

if (status & Y2_IS_IRQ_MAC2)

2111

if (status & Y2_IS_IRQ_MAC2)

2112

sky2_mac_intr(hw, 1);

2112

sky2_mac_intr(hw, 1);

2113

2114

if (status & Y2_IS_CHK_RX1)

2114

if (status & Y2_IS_CHK_RX1)

2115

sky2_descriptor_error(hw, 0, "receive", Y2_IS_CHK_RX1);

2115

sky2_descriptor_error(hw, 0, "receive", Y2_IS_CHK_RX1);

2116

2117

if (status & Y2_IS_CHK_RX2)

2117

if (status & Y2_IS_CHK_RX2)

2118

sky2_descriptor_error(hw, 1, "receive", Y2_IS_CHK_RX2);

2118

sky2_descriptor_error(hw, 1, "receive", Y2_IS_CHK_RX2);

2119

2120

if (status & Y2_IS_CHK_TXA1)

2120

if (status & Y2_IS_CHK_TXA1)

2121

sky2_descriptor_error(hw, 0, "transmit", Y2_IS_CHK_TXA1);

2121

sky2_descriptor_error(hw, 0, "transmit", Y2_IS_CHK_TXA1);

2122

2123

if (status & Y2_IS_CHK_TXA2)

2123

if (status & Y2_IS_CHK_TXA2)

2124

sky2_descriptor_error(hw, 1, "transmit", Y2_IS_CHK_TXA2);

2124

sky2_descriptor_error(hw, 1, "transmit", Y2_IS_CHK_TXA2);

2125

}

2125

}

2126

2127

if (status & Y2_IS_STAT_BMU) {

2127

if (status & Y2_IS_STAT_BMU) {

2128

work_done = sky2_status_intr(hw, work_limit);

2128

work_done = sky2_status_intr(hw, work_limit);

2129

*budget -= work_done;

2129

*budget -= work_done;

2130

dev0->quota -= work_done;

2130

dev0->quota -= work_done;

2131

2132

if (work_done >= work_limit)

2132

if (work_done >= work_limit)

2133

return 1;

2133

return 1;

2134

2135

sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);

2135

sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);

2136

}

2136

}

2137

2138

netif_rx_complete(dev0);

2138

netif_rx_complete(dev0);

2139

2140

status = sky2_read32(hw, B0_Y2_SP_LISR);

2140

status = sky2_read32(hw, B0_Y2_SP_LISR);

2141

return 0;

2141

return 0;

2142

}

2142

}

2143

2144

static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)

2144

static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)

2145

{

2145

{

2146

struct sky2_hw *hw = dev_id;

2146

struct sky2_hw *hw = dev_id;

2147

struct net_device *dev0 = hw->dev[0];

2147

struct net_device *dev0 = hw->dev[0];

2148

u32 status;

2148

u32 status;

2149

2150

/* Reading this mask interrupts as side effect */

2150

/* Reading this mask interrupts as side effect */

2151

status = sky2_read32(hw, B0_Y2_SP_ISRC2);

2151

status = sky2_read32(hw, B0_Y2_SP_ISRC2);

2152

if (status == 0 || status == ~0)

2152

if (status == 0 || status == ~0)

2153

return IRQ_NONE;

2153

return IRQ_NONE;

2154

2155

prefetch(&hw->st_le[hw->st_idx]);

2155

prefetch(&hw->st_le[hw->st_idx]);

2156

if (likely(__netif_rx_schedule_prep(dev0)))

2156

if (likely(__netif_rx_schedule_prep(dev0)))

2157

__netif_rx_schedule(dev0);

2157

__netif_rx_schedule(dev0);

2158

else

2158

else

2159

printk(KERN_DEBUG PFX "irq race detected\n");

2159

printk(KERN_DEBUG PFX "irq race detected\n");

2160

2161

return IRQ_HANDLED;

2161

return IRQ_HANDLED;

2162

}

2162

}

2163

2164

#ifdef CONFIG_NET_POLL_CONTROLLER

2164

#ifdef CONFIG_NET_POLL_CONTROLLER

2165

static void sky2_netpoll(struct net_device *dev)

2165

static void sky2_netpoll(struct net_device *dev)

2166

{

2166

{

2167

struct sky2_port *sky2 = netdev_priv(dev);

2167

struct sky2_port *sky2 = netdev_priv(dev);

2168

2169

sky2_intr(sky2->hw->pdev->irq, sky2->hw, NULL);

2169

sky2_intr(sky2->hw->pdev->irq, sky2->hw, NULL);

2170

}

2170

}

2171

#endif

2171

#endif

2172

2173

/* Chip internal frequency for clock calculations */

2173

/* Chip internal frequency for clock calculations */

2174

static inline u32 sky2_mhz(const struct sky2_hw *hw)

2174

static inline u32 sky2_mhz(const struct sky2_hw *hw)

2175

{

2175

{

2176

switch (hw->chip_id) {

2176

switch (hw->chip_id) {

2177

case CHIP_ID_YUKON_EC:

2177

case CHIP_ID_YUKON_EC:

2178

case CHIP_ID_YUKON_EC_U:

2178

case CHIP_ID_YUKON_EC_U:

2179

return 125; /* 125 Mhz */

2179

return 125; /* 125 Mhz */

2180

case CHIP_ID_YUKON_FE:

2180

case CHIP_ID_YUKON_FE:

2181

return 100; /* 100 Mhz */

2181

return 100; /* 100 Mhz */

2182

default: /* YUKON_XL */

2182

default: /* YUKON_XL */

2183

return 156; /* 156 Mhz */

2183

return 156; /* 156 Mhz */

2184

}

2184

}

2185

}

2185

}

2186

2187

static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)

2187

static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)

2188

{

2188

{

2189

return sky2_mhz(hw) * us;

2189

return sky2_mhz(hw) * us;

2190

}

2190

}

2191

2192

static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)

2192

static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)

2193

{

2193

{

2194

return clk / sky2_mhz(hw);

2194

return clk / sky2_mhz(hw);

2195

}

2195

}

2196

2197

2198

static int sky2_reset(struct sky2_hw *hw)

2198

static int sky2_reset(struct sky2_hw *hw)

2199

{

2199

{

2200

u16 status;

2200

u16 status;

2201

u8 t8, pmd_type;

2201

u8 t8, pmd_type;

2202

int i;

2202

int i;

2203

2204

sky2_write8(hw, B0_CTST, CS_RST_CLR);

2204

sky2_write8(hw, B0_CTST, CS_RST_CLR);

2205

2206

hw->chip_id = sky2_read8(hw, B2_CHIP_ID);

2206

hw->chip_id = sky2_read8(hw, B2_CHIP_ID);

2207

if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {

2207

if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {

2208

printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",

2208

printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",

2209

pci_name(hw->pdev), hw->chip_id);

2209

pci_name(hw->pdev), hw->chip_id);

2210

return -EOPNOTSUPP;

2210

return -EOPNOTSUPP;

2211

}

2211

}

2212

2213

hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;

2213

hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;

2214

2215

/* This rev is really old, and requires untested workarounds */

2215

/* This rev is really old, and requires untested workarounds */

2216

if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {

2216

if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {

2217

printk(KERN_ERR PFX "%s: unsupported revision Yukon-%s (0x%x) rev %d\n",

2217

printk(KERN_ERR PFX "%s: unsupported revision Yukon-%s (0x%x) rev %d\n",

2218

pci_name(hw->pdev), yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],

2218

pci_name(hw->pdev), yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],

2219

hw->chip_id, hw->chip_rev);

2219

hw->chip_id, hw->chip_rev);

2220

return -EOPNOTSUPP;

2220

return -EOPNOTSUPP;

2221

}

2221

}

2222

2223

/* This chip is new and not tested yet */

2223

/* This chip is new and not tested yet */

2224

if (hw->chip_id == CHIP_ID_YUKON_EC_U) {

2224

if (hw->chip_id == CHIP_ID_YUKON_EC_U) {

2225

pr_info(PFX "%s: is a version of Yukon 2 chipset that has not been tested yet.\n",

2225

pr_info(PFX "%s: is a version of Yukon 2 chipset that has not been tested yet.\n",

2226

pci_name(hw->pdev));

2226

pci_name(hw->pdev));

2227

pr_info("Please report success/failure to maintainer <shemminger@osdl.org>\n");

2227

pr_info("Please report success/failure to maintainer <shemminger@osdl.org>\n");

2228

}

2228

}

2229

2230

/* disable ASF */

2230

/* disable ASF */

2231

if (hw->chip_id <= CHIP_ID_YUKON_EC) {

2231

if (hw->chip_id <= CHIP_ID_YUKON_EC) {

2232

sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);

2232

sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);

2233

sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);

2233

sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);

2234

}

2234

}

2235

2236

/* do a SW reset */

2236

/* do a SW reset */

2237

sky2_write8(hw, B0_CTST, CS_RST_SET);

2237

sky2_write8(hw, B0_CTST, CS_RST_SET);

2238

sky2_write8(hw, B0_CTST, CS_RST_CLR);

2238

sky2_write8(hw, B0_CTST, CS_RST_CLR);

2239

2240

/* clear PCI errors, if any */

2240

/* clear PCI errors, if any */

2241

status = sky2_pci_read16(hw, PCI_STATUS);

2241

status = sky2_pci_read16(hw, PCI_STATUS);

2242

2243

sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);

2243

sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);

2244

sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);

2244

sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);

2245

2246

2247

sky2_write8(hw, B0_CTST, CS_MRST_CLR);

2247

sky2_write8(hw, B0_CTST, CS_MRST_CLR);

2248

2249

/* clear any PEX errors */

2249

/* clear any PEX errors */

2250

if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))

2250

if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))

2251

sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);

2251

sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);

2252

2253

2254

pmd_type = sky2_read8(hw, B2_PMD_TYP);

2254

pmd_type = sky2_read8(hw, B2_PMD_TYP);

2255

hw->copper = !(pmd_type == 'L' || pmd_type == 'S');

2255

hw->copper = !(pmd_type == 'L' || pmd_type == 'S');

2256

2257

hw->ports = 1;

2257

hw->ports = 1;

2258

t8 = sky2_read8(hw, B2_Y2_HW_RES);

2258

t8 = sky2_read8(hw, B2_Y2_HW_RES);

2259

if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {

2259

if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {

2260

if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))

2260

if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))

2261

++hw->ports;

2261

++hw->ports;

2262

}

2262

}

2263

2264

sky2_set_power_state(hw, PCI_D0);

2264

sky2_set_power_state(hw, PCI_D0);

2265

2266

for (i = 0; i < hw->ports; i++) {

2266

for (i = 0; i < hw->ports; i++) {

2267

sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);

2267

sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);

2268

sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);

2268

sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);

2269

}

2269

}

2270

2271

sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);

2271

sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);

2272

2273

/* Clear I2C IRQ noise */

2273

/* Clear I2C IRQ noise */

2274

sky2_write32(hw, B2_I2C_IRQ, 1);

2274

sky2_write32(hw, B2_I2C_IRQ, 1);

2275

2276

/* turn off hardware timer (unused) */

2276

/* turn off hardware timer (unused) */

2277

sky2_write8(hw, B2_TI_CTRL, TIM_STOP);

2277

sky2_write8(hw, B2_TI_CTRL, TIM_STOP);

2278

sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);

2278

sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);

2279

2280

sky2_write8(hw, B0_Y2LED, LED_STAT_ON);

2280

sky2_write8(hw, B0_Y2LED, LED_STAT_ON);

2281

2282

/* Turn off descriptor polling */

2282

/* Turn off descriptor polling */

2283

sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);

2283

sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);

2284

2285

/* Turn off receive timestamp */

2285

/* Turn off receive timestamp */

2286

sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);

2286

sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);

2287

sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);

2287

sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);

2288

2289

/* enable the Tx Arbiters */

2289

/* enable the Tx Arbiters */

2290

for (i = 0; i < hw->ports; i++)

2290

for (i = 0; i < hw->ports; i++)

2291

sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);

2291

sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);

2292

2293

/* Initialize ram interface */

2293

/* Initialize ram interface */

2294

for (i = 0; i < hw->ports; i++) {

2294

for (i = 0; i < hw->ports; i++) {

2295

sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);

2295

sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);

2296

2297

sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);

2297

sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);

2298

sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);

2298

sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);

2299

sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);

2299

sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);

2300

sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);

2300

sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);

2301

sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);

2301

sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);

2302

sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);

2302

sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);

2303

sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);

2303

sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);

2304

sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);

2304

sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);

2305

sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);

2305

sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);

2306

sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);

2306

sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);

2307

sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);

2307

sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);

2308

sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);

2308

sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);

2309

}

2309

}

2310

2311

sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);

2311

sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);

2312

2313

for (i = 0; i < hw->ports; i++)

2313

for (i = 0; i < hw->ports; i++)

2314

sky2_phy_reset(hw, i);

2314

sky2_phy_reset(hw, i);

2315

2316

memset(hw->st_le, 0, STATUS_LE_BYTES);

2316

memset(hw->st_le, 0, STATUS_LE_BYTES);

2317

hw->st_idx = 0;

2317

hw->st_idx = 0;

2318

2319

sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);

2319

sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);

2320

sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);

2320

sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);

2321

2322

sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);

2322

sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);

2323

sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);

2323

sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);

2324

2325

/* Set the list last index */

2325

/* Set the list last index */

2326

sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);

2326

sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);

2327

2328

sky2_write16(hw, STAT_TX_IDX_TH, 10);

2328

sky2_write16(hw, STAT_TX_IDX_TH, 10);

2329

sky2_write8(hw, STAT_FIFO_WM, 16);

2329

sky2_write8(hw, STAT_FIFO_WM, 16);

2330

2331

/* set Status-FIFO ISR watermark */

2331

/* set Status-FIFO ISR watermark */

2332

if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)

2332

if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)

2333

sky2_write8(hw, STAT_FIFO_ISR_WM, 4);

2333

sky2_write8(hw, STAT_FIFO_ISR_WM, 4);

2334

else

2334

else

2335

sky2_write8(hw, STAT_FIFO_ISR_WM, 16);

2335

sky2_write8(hw, STAT_FIFO_ISR_WM, 16);

2336

2337

sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));

2337

sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));

2338

sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));

2338

sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));

2339

sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));

2339

sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));

2340

2341

/* enable status unit */

2341

/* enable status unit */

2342

sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);

2342

sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);

2343

2344

sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);

2344

sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);

2345

sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);

2345

sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);

2346

sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);

2346

sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);

2347

2348

return 0;

2348

return 0;

2349

}

2349

}

2350

2351

static u32 sky2_supported_modes(const struct sky2_hw *hw)

2351

static u32 sky2_supported_modes(const struct sky2_hw *hw)

2352

{

2352

{

2353

u32 modes;

2353

u32 modes;

2354

if (hw->copper) {

2354

if (hw->copper) {

2355

modes = SUPPORTED_10baseT_Half

2355

modes = SUPPORTED_10baseT_Half

2356

| SUPPORTED_10baseT_Full

2356

| SUPPORTED_10baseT_Full

2357

| SUPPORTED_100baseT_Half

2357

| SUPPORTED_100baseT_Half

2358

| SUPPORTED_100baseT_Full

2358

| SUPPORTED_100baseT_Full

2359

| SUPPORTED_Autoneg | SUPPORTED_TP;

2359

| SUPPORTED_Autoneg | SUPPORTED_TP;

2360

2361

if (hw->chip_id != CHIP_ID_YUKON_FE)

2361

if (hw->chip_id != CHIP_ID_YUKON_FE)

2362

modes |= SUPPORTED_1000baseT_Half

2362

modes |= SUPPORTED_1000baseT_Half

2363

| SUPPORTED_1000baseT_Full;

2363

| SUPPORTED_1000baseT_Full;

2364

} else

2364

} else

2365

modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE

2365

modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE

2366

| SUPPORTED_Autoneg;

2366

| SUPPORTED_Autoneg;

2367

return modes;

2367

return modes;

2368

}

2368

}

2369

2370

static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)

2370

static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)

2371

{

2371

{

2372

struct sky2_port *sky2 = netdev_priv(dev);

2372

struct sky2_port *sky2 = netdev_priv(dev);

2373

struct sky2_hw *hw = sky2->hw;

2373

struct sky2_hw *hw = sky2->hw;

2374

2375

ecmd->transceiver = XCVR_INTERNAL;

2375

ecmd->transceiver = XCVR_INTERNAL;

2376

ecmd->supported = sky2_supported_modes(hw);

2376

ecmd->supported = sky2_supported_modes(hw);

2377

ecmd->phy_address = PHY_ADDR_MARV;

2377

ecmd->phy_address = PHY_ADDR_MARV;

2378

if (hw->copper) {

2378

if (hw->copper) {

2379

ecmd->supported = SUPPORTED_10baseT_Half

2379

ecmd->supported = SUPPORTED_10baseT_Half

2380

| SUPPORTED_10baseT_Full

2380

| SUPPORTED_10baseT_Full

2381

| SUPPORTED_100baseT_Half

2381

| SUPPORTED_100baseT_Half

2382

| SUPPORTED_100baseT_Full

2382

| SUPPORTED_100baseT_Full

2383

| SUPPORTED_1000baseT_Half

2383

| SUPPORTED_1000baseT_Half

2384

| SUPPORTED_1000baseT_Full

2384

| SUPPORTED_1000baseT_Full

2385

| SUPPORTED_Autoneg | SUPPORTED_TP;

2385

| SUPPORTED_Autoneg | SUPPORTED_TP;

2386

ecmd->port = PORT_TP;

2386

ecmd->port = PORT_TP;

2387

} else

2387

} else

2388

ecmd->port = PORT_FIBRE;

2388

ecmd->port = PORT_FIBRE;

2389

2390

ecmd->advertising = sky2->advertising;

2390

ecmd->advertising = sky2->advertising;

2391

ecmd->autoneg = sky2->autoneg;

2391

ecmd->autoneg = sky2->autoneg;

2392

ecmd->speed = sky2->speed;

2392

ecmd->speed = sky2->speed;

2393

ecmd->duplex = sky2->duplex;

2393

ecmd->duplex = sky2->duplex;

2394

return 0;

2394

return 0;

2395

}

2395

}

2396

2397

static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)

2397

static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)

2398

{

2398

{

2399

struct sky2_port *sky2 = netdev_priv(dev);

2399

struct sky2_port *sky2 = netdev_priv(dev);

2400

const struct sky2_hw *hw = sky2->hw;

2400

const struct sky2_hw *hw = sky2->hw;

2401

u32 supported = sky2_supported_modes(hw);

2401

u32 supported = sky2_supported_modes(hw);

2402

2403

if (ecmd->autoneg == AUTONEG_ENABLE) {

2403

if (ecmd->autoneg == AUTONEG_ENABLE) {

2404

ecmd->advertising = supported;

2404

ecmd->advertising = supported;

2405

sky2->duplex = -1;

2405

sky2->duplex = -1;

2406

sky2->speed = -1;

2406

sky2->speed = -1;

2407

} else {

2407

} else {

2408

u32 setting;

2408

u32 setting;

2409

2410

switch (ecmd->speed) {

2410

switch (ecmd->speed) {

2411

case SPEED_1000:

2411

case SPEED_1000:

2412

if (ecmd->duplex == DUPLEX_FULL)

2412

if (ecmd->duplex == DUPLEX_FULL)

2413

setting = SUPPORTED_1000baseT_Full;

2413

setting = SUPPORTED_1000baseT_Full;

2414

else if (ecmd->duplex == DUPLEX_HALF)

2414

else if (ecmd->duplex == DUPLEX_HALF)

2415

setting = SUPPORTED_1000baseT_Half;

2415

setting = SUPPORTED_1000baseT_Half;

2416

else

2416

else

2417

return -EINVAL;

2417

return -EINVAL;

2418

break;

2418

break;

2419

case SPEED_100:

2419

case SPEED_100:

2420

if (ecmd->duplex == DUPLEX_FULL)

2420

if (ecmd->duplex == DUPLEX_FULL)

2421

setting = SUPPORTED_100baseT_Full;

2421

setting = SUPPORTED_100baseT_Full;

2422

else if (ecmd->duplex == DUPLEX_HALF)

2422

else if (ecmd->duplex == DUPLEX_HALF)

2423

setting = SUPPORTED_100baseT_Half;

2423

setting = SUPPORTED_100baseT_Half;

2424

else

2424

else

2425

return -EINVAL;

2425

return -EINVAL;

2426

break;

2426

break;

2427

2428

case SPEED_10:

2428

case SPEED_10:

2429

if (ecmd->duplex == DUPLEX_FULL)

2429

if (ecmd->duplex == DUPLEX_FULL)

2430

setting = SUPPORTED_10baseT_Full;

2430

setting = SUPPORTED_10baseT_Full;

2431

else if (ecmd->duplex == DUPLEX_HALF)

2431

else if (ecmd->duplex == DUPLEX_HALF)

2432

setting = SUPPORTED_10baseT_Half;

2432

setting = SUPPORTED_10baseT_Half;

2433

else

2433

else

2434

return -EINVAL;

2434

return -EINVAL;

2435

break;

2435

break;

2436

default:

2436

default:

2437

return -EINVAL;

2437

return -EINVAL;

2438

}

2438

}

2439

2440

if ((setting & supported) == 0)

2440

if ((setting & supported) == 0)

2441

return -EINVAL;

2441

return -EINVAL;

2442

2443

sky2->speed = ecmd->speed;

2443

sky2->speed = ecmd->speed;

2444

sky2->duplex = ecmd->duplex;

2444

sky2->duplex = ecmd->duplex;

2445

}

2445

}

2446

2447

sky2->autoneg = ecmd->autoneg;

2447

sky2->autoneg = ecmd->autoneg;

2448

sky2->advertising = ecmd->advertising;

2448

sky2->advertising = ecmd->advertising;

2449

2450

if (netif_running(dev))

2450

if (netif_running(dev))

2451

sky2_phy_reinit(sky2);

2451

sky2_phy_reinit(sky2);

2452

2453

return 0;

2453

return 0;

2454

}

2454

}

2455

2456

static void sky2_get_drvinfo(struct net_device *dev,

2456

static void sky2_get_drvinfo(struct net_device *dev,

2457

struct ethtool_drvinfo *info)

2457

struct ethtool_drvinfo *info)

2458

{

2458

{

2459

struct sky2_port *sky2 = netdev_priv(dev);

2459

struct sky2_port *sky2 = netdev_priv(dev);

2460

2461

strcpy(info->driver, DRV_NAME);

2461

strcpy(info->driver, DRV_NAME);

2462

strcpy(info->version, DRV_VERSION);

2462

strcpy(info->version, DRV_VERSION);

2463

strcpy(info->fw_version, "N/A");

2463

strcpy(info->fw_version, "N/A");

2464

strcpy(info->bus_info, pci_name(sky2->hw->pdev));

2464

strcpy(info->bus_info, pci_name(sky2->hw->pdev));

2465

}

2465

}

2466

2467

static const struct sky2_stat {

2467

static const struct sky2_stat {

2468

char name[ETH_GSTRING_LEN];

2468

char name[ETH_GSTRING_LEN];

2469

u16 offset;

2469

u16 offset;

2470

} sky2_stats[] = {

2470

} sky2_stats[] = {

2471

{ "tx_bytes", GM_TXO_OK_HI },

2471

{ "tx_bytes", GM_TXO_OK_HI },

2472

{ "rx_bytes", GM_RXO_OK_HI },

2472

{ "rx_bytes", GM_RXO_OK_HI },

2473

{ "tx_broadcast", GM_TXF_BC_OK },

2473

{ "tx_broadcast", GM_TXF_BC_OK },

2474

{ "rx_broadcast", GM_RXF_BC_OK },

2474

{ "rx_broadcast", GM_RXF_BC_OK },

2475

{ "tx_multicast", GM_TXF_MC_OK },

2475

{ "tx_multicast", GM_TXF_MC_OK },

2476

{ "rx_multicast", GM_RXF_MC_OK },

2476

{ "rx_multicast", GM_RXF_MC_OK },

2477

{ "tx_unicast", GM_TXF_UC_OK },

2477

{ "tx_unicast", GM_TXF_UC_OK },

2478

{ "rx_unicast", GM_RXF_UC_OK },

2478

{ "rx_unicast", GM_RXF_UC_OK },

2479

{ "tx_mac_pause", GM_TXF_MPAUSE },

2479

{ "tx_mac_pause", GM_TXF_MPAUSE },

2480

{ "rx_mac_pause", GM_RXF_MPAUSE },

2480

{ "rx_mac_pause", GM_RXF_MPAUSE },

2481

{ "collisions", GM_TXF_SNG_COL },

2481

{ "collisions", GM_TXF_SNG_COL },

2482

{ "late_collision",GM_TXF_LAT_COL },

2482

{ "late_collision",GM_TXF_LAT_COL },

2483

{ "aborted", GM_TXF_ABO_COL },

2483

{ "aborted", GM_TXF_ABO_COL },

2484

{ "multi_collisions", GM_TXF_MUL_COL },

2484

{ "multi_collisions", GM_TXF_MUL_COL },

2485

{ "fifo_underrun", GM_TXE_FIFO_UR },

2485

{ "fifo_underrun", GM_TXE_FIFO_UR },

2486

{ "fifo_overflow", GM_RXE_FIFO_OV },

2486

{ "fifo_overflow", GM_RXE_FIFO_OV },

2487

{ "rx_toolong", GM_RXF_LNG_ERR },

2487

{ "rx_toolong", GM_RXF_LNG_ERR },

2488

{ "rx_jabber", GM_RXF_JAB_PKT },

2488

{ "rx_jabber", GM_RXF_JAB_PKT },

2489

{ "rx_runt", GM_RXE_FRAG },

2489

{ "rx_runt", GM_RXE_FRAG },

2490

{ "rx_too_long", GM_RXF_LNG_ERR },

2490

{ "rx_too_long", GM_RXF_LNG_ERR },

2491

{ "rx_fcs_error", GM_RXF_FCS_ERR },

2491

{ "rx_fcs_error", GM_RXF_FCS_ERR },

2492

};

2492

};

2493

2494

static u32 sky2_get_rx_csum(struct net_device *dev)

2494

static u32 sky2_get_rx_csum(struct net_device *dev)

2495

{

2495

{

2496

struct sky2_port *sky2 = netdev_priv(dev);

2496

struct sky2_port *sky2 = netdev_priv(dev);

2497

2498

return sky2->rx_csum;

2498

return sky2->rx_csum;

2499

}

2499

}

2500

2501

static int sky2_set_rx_csum(struct net_device *dev, u32 data)

2501

static int sky2_set_rx_csum(struct net_device *dev, u32 data)

2502

{

2502

{

2503

struct sky2_port *sky2 = netdev_priv(dev);

2503

struct sky2_port *sky2 = netdev_priv(dev);

2504

2505

sky2->rx_csum = data;

2505

sky2->rx_csum = data;

2506

2507

sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),

2507

sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),

2508

data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);

2508

data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);

2509

2510

return 0;

2510

return 0;

2511

}

2511

}

2512

2513

static u32 sky2_get_msglevel(struct net_device *netdev)

2513

static u32 sky2_get_msglevel(struct net_device *netdev)

2514

{

2514

{

2515

struct sky2_port *sky2 = netdev_priv(netdev);

2515

struct sky2_port *sky2 = netdev_priv(netdev);

2516

return sky2->msg_enable;

2516

return sky2->msg_enable;

2517

}

2517

}

2518

2519

static int sky2_nway_reset(struct net_device *dev)

2519

static int sky2_nway_reset(struct net_device *dev)

2520

{

2520

{

2521

struct sky2_port *sky2 = netdev_priv(dev);

2521

struct sky2_port *sky2 = netdev_priv(dev);

2522

2523

if (sky2->autoneg != AUTONEG_ENABLE)

2523

if (sky2->autoneg != AUTONEG_ENABLE)

2524

return -EINVAL;

2524

return -EINVAL;

2525

2526

sky2_phy_reinit(sky2);

2526

sky2_phy_reinit(sky2);

2527

2528

return 0;

2528

return 0;

2529

}

2529

}

2530

2531

static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)

2531

static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)

2532

{

2532

{

2533

struct sky2_hw *hw = sky2->hw;

2533

struct sky2_hw *hw = sky2->hw;

2534

unsigned port = sky2->port;

2534

unsigned port = sky2->port;

2535

int i;

2535

int i;

2536

2537

data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32

2537

data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32

2538

| (u64) gma_read32(hw, port, GM_TXO_OK_LO);

2538

| (u64) gma_read32(hw, port, GM_TXO_OK_LO);

2539

data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32

2539

data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32

2540

| (u64) gma_read32(hw, port, GM_RXO_OK_LO);

2540

| (u64) gma_read32(hw, port, GM_RXO_OK_LO);

2541

2542

for (i = 2; i < count; i++)

2542

for (i = 2; i < count; i++)

2543

data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);

2543

data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);

2544

}

2544

}

2545

2546

static void sky2_set_msglevel(struct net_device *netdev, u32 value)

2546

static void sky2_set_msglevel(struct net_device *netdev, u32 value)

2547

{

2547

{

2548

struct sky2_port *sky2 = netdev_priv(netdev);

2548

struct sky2_port *sky2 = netdev_priv(netdev);

2549

sky2->msg_enable = value;

2549

sky2->msg_enable = value;

2550

}

2550

}

2551

2552

static int sky2_get_stats_count(struct net_device *dev)

2552

static int sky2_get_stats_count(struct net_device *dev)

2553

{

2553

{

2554

return ARRAY_SIZE(sky2_stats);

2554

return ARRAY_SIZE(sky2_stats);

2555

}

2555

}

2556

2557

static void sky2_get_ethtool_stats(struct net_device *dev,

2557

static void sky2_get_ethtool_stats(struct net_device *dev,

2558

struct ethtool_stats *stats, u64 * data)

2558

struct ethtool_stats *stats, u64 * data)

2559

{

2559

{

2560

struct sky2_port *sky2 = netdev_priv(dev);

2560

struct sky2_port *sky2 = netdev_priv(dev);

2561

2562

sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));

2562

sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));

2563

}

2563

}

2564

2565

static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)

2565

static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)

2566

{

2566

{

2567

int i;

2567

int i;

2568

2569

switch (stringset) {

2569

switch (stringset) {

2570

case ETH_SS_STATS:

2570

case ETH_SS_STATS:

2571

for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)

2571

for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)

2572

memcpy(data + i * ETH_GSTRING_LEN,

2572

memcpy(data + i * ETH_GSTRING_LEN,

2573

sky2_stats[i].name, ETH_GSTRING_LEN);

2573

sky2_stats[i].name, ETH_GSTRING_LEN);

2574

break;

2574

break;

2575

}

2575

}

2576

}

2576

}

2577

2578

/* Use hardware MIB variables for critical path statistics and

2578

/* Use hardware MIB variables for critical path statistics and

2579

* transmit feedback not reported at interrupt.

2579

* transmit feedback not reported at interrupt.

2580

* Other errors are accounted for in interrupt handler.

2580

* Other errors are accounted for in interrupt handler.

2581

*/

2581

*/

2582

static struct net_device_stats *sky2_get_stats(struct net_device *dev)

2582

static struct net_device_stats *sky2_get_stats(struct net_device *dev)

2583

{

2583

{

2584

struct sky2_port *sky2 = netdev_priv(dev);

2584

struct sky2_port *sky2 = netdev_priv(dev);

2585

u64 data[13];

2585

u64 data[13];

2586

2587

sky2_phy_stats(sky2, data, ARRAY_SIZE(data));

2587

sky2_phy_stats(sky2, data, ARRAY_SIZE(data));

2588

2589

sky2->net_stats.tx_bytes = data[0];

2589

sky2->net_stats.tx_bytes = data[0];

2590

sky2->net_stats.rx_bytes = data[1];

2590

sky2->net_stats.rx_bytes = data[1];

2591

sky2->net_stats.tx_packets = data[2] + data[4] + data[6];

2591

sky2->net_stats.tx_packets = data[2] + data[4] + data[6];

2592

sky2->net_stats.rx_packets = data[3] + data[5] + data[7];

2592

sky2->net_stats.rx_packets = data[3] + data[5] + data[7];

2593

sky2->net_stats.multicast = data[5] + data[7];

2593

sky2->net_stats.multicast = data[5] + data[7];

2594

sky2->net_stats.collisions = data[10];

2594

sky2->net_stats.collisions = data[10];

2595

sky2->net_stats.tx_aborted_errors = data[12];

2595

sky2->net_stats.tx_aborted_errors = data[12];

2596

2597

return &sky2->net_stats;

2597

return &sky2->net_stats;

2598

}

2598

}

2599

2600

static int sky2_set_mac_address(struct net_device *dev, void *p)

2600

static int sky2_set_mac_address(struct net_device *dev, void *p)

2601

{

2601

{

2602

struct sky2_port *sky2 = netdev_priv(dev);

2602

struct sky2_port *sky2 = netdev_priv(dev);

2603

struct sky2_hw *hw = sky2->hw;

2603

struct sky2_hw *hw = sky2->hw;

2604

unsigned port = sky2->port;

2604

unsigned port = sky2->port;

2605

const struct sockaddr *addr = p;

2605

const struct sockaddr *addr = p;

2606

2607

if (!is_valid_ether_addr(addr->sa_data))

2607

if (!is_valid_ether_addr(addr->sa_data))

2608

return -EADDRNOTAVAIL;

2608

return -EADDRNOTAVAIL;

2609

2610

memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);

2610

memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);

2611

memcpy_toio(hw->regs + B2_MAC_1 + port * 8,

2611

memcpy_toio(hw->regs + B2_MAC_1 + port * 8,

2612

dev->dev_addr, ETH_ALEN);

2612

dev->dev_addr, ETH_ALEN);

2613

memcpy_toio(hw->regs + B2_MAC_2 + port * 8,

2613

memcpy_toio(hw->regs + B2_MAC_2 + port * 8,

2614

dev->dev_addr, ETH_ALEN);

2614

dev->dev_addr, ETH_ALEN);

2615

2616

/* virtual address for data */

2616

/* virtual address for data */

2617

gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);

2617

gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);

2618

2619

/* physical address: used for pause frames */

2619

/* physical address: used for pause frames */

2620

gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);

2620

gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);

2621

2622

return 0;

2622

return 0;

2623

}

2623

}

2624

2625

static void sky2_set_multicast(struct net_device *dev)

2625

static void sky2_set_multicast(struct net_device *dev)

2626

{

2626

{

2627

struct sky2_port *sky2 = netdev_priv(dev);

2627

struct sky2_port *sky2 = netdev_priv(dev);

2628

struct sky2_hw *hw = sky2->hw;

2628

struct sky2_hw *hw = sky2->hw;

2629

unsigned port = sky2->port;

2629

unsigned port = sky2->port;

2630

struct dev_mc_list *list = dev->mc_list;

2630

struct dev_mc_list *list = dev->mc_list;

2631

u16 reg;

2631

u16 reg;

2632

u8 filter[8];

2632

u8 filter[8];

2633

2634

memset(filter, 0, sizeof(filter));

2634

memset(filter, 0, sizeof(filter));

2635

2636

reg = gma_read16(hw, port, GM_RX_CTRL);

2636

reg = gma_read16(hw, port, GM_RX_CTRL);

2637

reg |= GM_RXCR_UCF_ENA;

2637

reg |= GM_RXCR_UCF_ENA;

2638

2639

if (dev->flags & IFF_PROMISC) /* promiscuous */

2639

if (dev->flags & IFF_PROMISC) /* promiscuous */

2640

reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);

2640

reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);

2641

else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */

2641

else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */

2642

memset(filter, 0xff, sizeof(filter));

2642

memset(filter, 0xff, sizeof(filter));

2643

else if (dev->mc_count == 0) /* no multicast */

2643

else if (dev->mc_count == 0) /* no multicast */

2644

reg &= ~GM_RXCR_MCF_ENA;

2644

reg &= ~GM_RXCR_MCF_ENA;

2645

else {

2645

else {

2646

int i;

2646

int i;

2647

reg |= GM_RXCR_MCF_ENA;

2647

reg |= GM_RXCR_MCF_ENA;

2648

2649

for (i = 0; list && i < dev->mc_count; i++, list = list->next) {

2649

for (i = 0; list && i < dev->mc_count; i++, list = list->next) {

2650

u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;

2650

u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;

2651

filter[bit / 8] |= 1 << (bit % 8);

2651

filter[bit / 8] |= 1 << (bit % 8);

2652

}

2652

}

2653

}

2653

}

2654

2655

gma_write16(hw, port, GM_MC_ADDR_H1,

2655

gma_write16(hw, port, GM_MC_ADDR_H1,

2656

(u16) filter[0] | ((u16) filter[1] << 8));

2656

(u16) filter[0] | ((u16) filter[1] << 8));

2657

gma_write16(hw, port, GM_MC_ADDR_H2,

2657

gma_write16(hw, port, GM_MC_ADDR_H2,

2658

(u16) filter[2] | ((u16) filter[3] << 8));

2658

(u16) filter[2] | ((u16) filter[3] << 8));

2659

gma_write16(hw, port, GM_MC_ADDR_H3,

2659

gma_write16(hw, port, GM_MC_ADDR_H3,

2660

(u16) filter[4] | ((u16) filter[5] << 8));

2660

(u16) filter[4] | ((u16) filter[5] << 8));

2661

gma_write16(hw, port, GM_MC_ADDR_H4,

2661

gma_write16(hw, port, GM_MC_ADDR_H4,

2662

(u16) filter[6] | ((u16) filter[7] << 8));

2662

(u16) filter[6] | ((u16) filter[7] << 8));

2663

2664

gma_write16(hw, port, GM_RX_CTRL, reg);

2664

gma_write16(hw, port, GM_RX_CTRL, reg);

2665

}

2665

}

2666

2667

/* Can have one global because blinking is controlled by

2667

/* Can have one global because blinking is controlled by

2668

* ethtool and that is always under RTNL mutex

2668

* ethtool and that is always under RTNL mutex

2669

*/

2669

*/

2670

static void sky2_led(struct sky2_hw *hw, unsigned port, int on)

2670

static void sky2_led(struct sky2_hw *hw, unsigned port, int on)

2671

{

2671

{

2672

u16 pg;

2672

u16 pg;

2673

2674

switch (hw->chip_id) {

2674

switch (hw->chip_id) {

2675

case CHIP_ID_YUKON_XL:

2675

case CHIP_ID_YUKON_XL:

2676

pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);

2676

pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);

2677

gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);

2677

gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);

2678

gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,

2678

gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,

2679

on ? (PHY_M_LEDC_LOS_CTRL(1) |

2679

on ? (PHY_M_LEDC_LOS_CTRL(1) |

2680

PHY_M_LEDC_INIT_CTRL(7) |

2680

PHY_M_LEDC_INIT_CTRL(7) |

2681

PHY_M_LEDC_STA1_CTRL(7) |

2681

PHY_M_LEDC_STA1_CTRL(7) |

2682

PHY_M_LEDC_STA0_CTRL(7))

2682

PHY_M_LEDC_STA0_CTRL(7))

2683

: 0);

2683

: 0);

2684

2685

gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);

2685

gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);

2686

break;

2686

break;

2687

2688

default:

2688

default:

2689

gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);

2689

gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);

2690

gm_phy_write(hw, port, PHY_MARV_LED_OVER,

2690

gm_phy_write(hw, port, PHY_MARV_LED_OVER,

2691

on ? PHY_M_LED_MO_DUP(MO_LED_ON) |

2691

on ? PHY_M_LED_MO_DUP(MO_LED_ON) |

2692

PHY_M_LED_MO_10(MO_LED_ON) |

2692

PHY_M_LED_MO_10(MO_LED_ON) |

2693

PHY_M_LED_MO_100(MO_LED_ON) |

2693

PHY_M_LED_MO_100(MO_LED_ON) |

2694

PHY_M_LED_MO_1000(MO_LED_ON) |

2694

PHY_M_LED_MO_1000(MO_LED_ON) |

2695

PHY_M_LED_MO_RX(MO_LED_ON)

2695

PHY_M_LED_MO_RX(MO_LED_ON)

2696

: PHY_M_LED_MO_DUP(MO_LED_OFF) |

2696

: PHY_M_LED_MO_DUP(MO_LED_OFF) |

2697

PHY_M_LED_MO_10(MO_LED_OFF) |

2697

PHY_M_LED_MO_10(MO_LED_OFF) |

2698

PHY_M_LED_MO_100(MO_LED_OFF) |

2698

PHY_M_LED_MO_100(MO_LED_OFF) |

2699

PHY_M_LED_MO_1000(MO_LED_OFF) |

2699

PHY_M_LED_MO_1000(MO_LED_OFF) |

2700

PHY_M_LED_MO_RX(MO_LED_OFF));

2700

PHY_M_LED_MO_RX(MO_LED_OFF));

2701

2702

}

2702

}

2703

}

2703

}

2704

2705

/* blink LED's for finding board */

2705

/* blink LED's for finding board */

2706

static int sky2_phys_id(struct net_device *dev, u32 data)

2706

static int sky2_phys_id(struct net_device *dev, u32 data)

2707

{

2707

{

2708

struct sky2_port *sky2 = netdev_priv(dev);

2708

struct sky2_port *sky2 = netdev_priv(dev);

2709

struct sky2_hw *hw = sky2->hw;

2709

struct sky2_hw *hw = sky2->hw;

2710

unsigned port = sky2->port;

2710

unsigned port = sky2->port;

2711

u16 ledctrl, ledover = 0;

2711

u16 ledctrl, ledover = 0;

2712

long ms;

2712

long ms;

2713

int interrupted;

2713

int interrupted;

2714

int onoff = 1;

2714

int onoff = 1;

2715

2716

if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))

2716

if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))

2717

ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);

2717

ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);

2718

else

2718

else

2719

ms = data * 1000;

2719

ms = data * 1000;

2720

2721

/* save initial values */

2721

/* save initial values */

2722

spin_lock_bh(&sky2->phy_lock);

2722

spin_lock_bh(&sky2->phy_lock);

2723

if (hw->chip_id == CHIP_ID_YUKON_XL) {

2723

if (hw->chip_id == CHIP_ID_YUKON_XL) {

2724

u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);

2724

u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);

2725

gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);

2725

gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);

2726

ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);

2726

ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);

2727

gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);

2727

gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);

2728

} else {

2728

} else {

2729

ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);

2729

ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);

2730

ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);

2730

ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);

2731

}

2731

}

2732

2733

interrupted = 0;

2733

interrupted = 0;

2734

while (!interrupted && ms > 0) {

2734

while (!interrupted && ms > 0) {

2735

sky2_led(hw, port, onoff);

2735

sky2_led(hw, port, onoff);

2736

onoff = !onoff;

2736

onoff = !onoff;

2737

2738

spin_unlock_bh(&sky2->phy_lock);

2738

spin_unlock_bh(&sky2->phy_lock);

2739

interrupted = msleep_interruptible(250);

2739

interrupted = msleep_interruptible(250);

2740

spin_lock_bh(&sky2->phy_lock);

2740

spin_lock_bh(&sky2->phy_lock);

2741

2742

ms -= 250;

2742

ms -= 250;

2743

}

2743

}

2744

2745

/* resume regularly scheduled programming */

2745

/* resume regularly scheduled programming */

2746

if (hw->chip_id == CHIP_ID_YUKON_XL) {

2746

if (hw->chip_id == CHIP_ID_YUKON_XL) {

2747

u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);

2747

u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);

2748

gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);

2748

gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);

2749

gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);

2749

gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);

2750

gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);

2750

gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);

2751

} else {

2751

} else {

2752

gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);

2752

gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);

2753

gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);

2753

gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);

2754

}

2754

}

2755

spin_unlock_bh(&sky2->phy_lock);

2755

spin_unlock_bh(&sky2->phy_lock);

2756

2757

return 0;

2757

return 0;

2758

}

2758

}

2759

2760

static void sky2_get_pauseparam(struct net_device *dev,

2760

static void sky2_get_pauseparam(struct net_device *dev,

2761

struct ethtool_pauseparam *ecmd)

2761

struct ethtool_pauseparam *ecmd)

2762

{

2762

{

2763

struct sky2_port *sky2 = netdev_priv(dev);

2763

struct sky2_port *sky2 = netdev_priv(dev);

2764

2765

ecmd->tx_pause = sky2->tx_pause;

2765

ecmd->tx_pause = sky2->tx_pause;

2766

ecmd->rx_pause = sky2->rx_pause;

2766

ecmd->rx_pause = sky2->rx_pause;

2767

ecmd->autoneg = sky2->autoneg;

2767

ecmd->autoneg = sky2->autoneg;

2768

}

2768

}

2769

2770

static int sky2_set_pauseparam(struct net_device *dev,

2770

static int sky2_set_pauseparam(struct net_device *dev,

2771

struct ethtool_pauseparam *ecmd)

2771

struct ethtool_pauseparam *ecmd)

2772

{

2772

{

2773

struct sky2_port *sky2 = netdev_priv(dev);

2773

struct sky2_port *sky2 = netdev_priv(dev);

2774

int err = 0;

2774

int err = 0;

2775

2776

sky2->autoneg = ecmd->autoneg;

2776

sky2->autoneg = ecmd->autoneg;

2777

sky2->tx_pause = ecmd->tx_pause != 0;

2777

sky2->tx_pause = ecmd->tx_pause != 0;

2778

sky2->rx_pause = ecmd->rx_pause != 0;

2778

sky2->rx_pause = ecmd->rx_pause != 0;

2779

2780

sky2_phy_reinit(sky2);

2780

sky2_phy_reinit(sky2);

2781

2782

return err;

2782

return err;

2783

}

2783

}

2784

2785

static int sky2_get_coalesce(struct net_device *dev,

2785

static int sky2_get_coalesce(struct net_device *dev,

2786

struct ethtool_coalesce *ecmd)

2786

struct ethtool_coalesce *ecmd)

2787

{

2787

{

2788

struct sky2_port *sky2 = netdev_priv(dev);

2788

struct sky2_port *sky2 = netdev_priv(dev);

2789

struct sky2_hw *hw = sky2->hw;

2789

struct sky2_hw *hw = sky2->hw;

2790

2791

if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)

2791

if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)

2792

ecmd->tx_coalesce_usecs = 0;

2792

ecmd->tx_coalesce_usecs = 0;

2793

else {

2793

else {

2794

u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);

2794

u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);

2795

ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);

2795

ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);

2796

}

2796

}

2797

ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);

2797

ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);

2798

2799

if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)

2799

if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)

2800

ecmd->rx_coalesce_usecs = 0;

2800

ecmd->rx_coalesce_usecs = 0;

2801

else {

2801

else {

2802

u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);

2802

u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);

2803

ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);

2803

ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);

2804

}

2804

}

2805

ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);

2805

ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);

2806

2807

if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)

2807

if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)

2808

ecmd->rx_coalesce_usecs_irq = 0;

2808

ecmd->rx_coalesce_usecs_irq = 0;

2809

else {

2809

else {

2810

u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);

2810

u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);

2811

ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);

2811

ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);

2812

}

2812

}

2813

2814

ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);

2814

ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);

2815

2816

return 0;

2816

return 0;

2817

}

2817

}

2818

2819

/* Note: this affect both ports */

2819

/* Note: this affect both ports */

2820

static int sky2_set_coalesce(struct net_device *dev,

2820

static int sky2_set_coalesce(struct net_device *dev,

2821

struct ethtool_coalesce *ecmd)

2821

struct ethtool_coalesce *ecmd)

2822

{

2822

{

2823

struct sky2_port *sky2 = netdev_priv(dev);

2823

struct sky2_port *sky2 = netdev_priv(dev);

2824

struct sky2_hw *hw = sky2->hw;

2824

struct sky2_hw *hw = sky2->hw;

2825

const u32 tmax = sky2_clk2us(hw, 0x0ffffff);

2825

const u32 tmax = sky2_clk2us(hw, 0x0ffffff);

2826

2827

if (ecmd->tx_coalesce_usecs > tmax ||

2827

if (ecmd->tx_coalesce_usecs > tmax ||

2828

ecmd->rx_coalesce_usecs > tmax ||

2828

ecmd->rx_coalesce_usecs > tmax ||

2829

ecmd->rx_coalesce_usecs_irq > tmax)

2829

ecmd->rx_coalesce_usecs_irq > tmax)

2830

return -EINVAL;

2830

return -EINVAL;

2831

2832

if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)

2832

if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)

2833

return -EINVAL;

2833

return -EINVAL;

2834

if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)

2834

if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)

2835

return -EINVAL;

2835

return -EINVAL;

2836

if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)

2836

if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)

2837

return -EINVAL;

2837

return -EINVAL;

2838

2839

if (ecmd->tx_coalesce_usecs == 0)

2839

if (ecmd->tx_coalesce_usecs == 0)

2840

sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);

2840

sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);

2841

else {

2841

else {

2842

sky2_write32(hw, STAT_TX_TIMER_INI,

2842

sky2_write32(hw, STAT_TX_TIMER_INI,

2843

sky2_us2clk(hw, ecmd->tx_coalesce_usecs));

2843

sky2_us2clk(hw, ecmd->tx_coalesce_usecs));

2844

sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);

2844

sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);

2845

}

2845

}

2846

sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);

2846

sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);

2847

2848

if (ecmd->rx_coalesce_usecs == 0)

2848

if (ecmd->rx_coalesce_usecs == 0)

2849

sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);

2849

sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);

2850

else {

2850

else {

2851

sky2_write32(hw, STAT_LEV_TIMER_INI,

2851

sky2_write32(hw, STAT_LEV_TIMER_INI,

2852

sky2_us2clk(hw, ecmd->rx_coalesce_usecs));

2852

sky2_us2clk(hw, ecmd->rx_coalesce_usecs));

2853

sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);

2853

sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);

2854

}

2854

}

2855

sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);

2855

sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);

2856

2857

if (ecmd->rx_coalesce_usecs_irq == 0)

2857

if (ecmd->rx_coalesce_usecs_irq == 0)

2858

sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);

2858

sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);

2859

else {

2859

else {

2860

sky2_write32(hw, STAT_ISR_TIMER_INI,

2860

sky2_write32(hw, STAT_ISR_TIMER_INI,

2861

sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));

2861

sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));

2862

sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);

2862

sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);

2863

}

2863

}

2864

sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);

2864

sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);

2865

return 0;

2865

return 0;

2866

}

2866

}

2867

2868

static void sky2_get_ringparam(struct net_device *dev,

2868

static void sky2_get_ringparam(struct net_device *dev,

2869

struct ethtool_ringparam *ering)

2869

struct ethtool_ringparam *ering)

2870

{

2870

{

2871

struct sky2_port *sky2 = netdev_priv(dev);

2871

struct sky2_port *sky2 = netdev_priv(dev);

2872

2873

ering->rx_max_pending = RX_MAX_PENDING;

2873

ering->rx_max_pending = RX_MAX_PENDING;

2874

ering->rx_mini_max_pending = 0;

2874

ering->rx_mini_max_pending = 0;

2875

ering->rx_jumbo_max_pending = 0;

2875

ering->rx_jumbo_max_pending = 0;

2876

ering->tx_max_pending = TX_RING_SIZE - 1;

2876

ering->tx_max_pending = TX_RING_SIZE - 1;

2877

2878

ering->rx_pending = sky2->rx_pending;

2878

ering->rx_pending = sky2->rx_pending;

2879

ering->rx_mini_pending = 0;

2879

ering->rx_mini_pending = 0;

2880

ering->rx_jumbo_pending = 0;

2880

ering->rx_jumbo_pending = 0;

2881

ering->tx_pending = sky2->tx_pending;

2881

ering->tx_pending = sky2->tx_pending;

2882

}

2882

}

2883

2884

static int sky2_set_ringparam(struct net_device *dev,

2884

static int sky2_set_ringparam(struct net_device *dev,

2885

struct ethtool_ringparam *ering)

2885

struct ethtool_ringparam *ering)

2886

{

2886

{

2887

struct sky2_port *sky2 = netdev_priv(dev);

2887

struct sky2_port *sky2 = netdev_priv(dev);

2888

int err = 0;

2888

int err = 0;

2889

2890

if (ering->rx_pending > RX_MAX_PENDING ||

2890

if (ering->rx_pending > RX_MAX_PENDING ||

2891

ering->rx_pending < 8 ||

2891

ering->rx_pending < 8 ||

2892

ering->tx_pending < MAX_SKB_TX_LE ||

2892

ering->tx_pending < MAX_SKB_TX_LE ||

2893

ering->tx_pending > TX_RING_SIZE - 1)

2893

ering->tx_pending > TX_RING_SIZE - 1)

2894

return -EINVAL;

2894

return -EINVAL;

2895

2896

if (netif_running(dev))

2896

if (netif_running(dev))

2897

sky2_down(dev);

2897

sky2_down(dev);

2898

2899

sky2->rx_pending = ering->rx_pending;

2899

sky2->rx_pending = ering->rx_pending;

2900

sky2->tx_pending = ering->tx_pending;

2900

sky2->tx_pending = ering->tx_pending;

2901

2902

if (netif_running(dev)) {

2902

if (netif_running(dev)) {

2903

err = sky2_up(dev);

2903

err = sky2_up(dev);

2904

if (err)

2904

if (err)

2905

dev_close(dev);

2905

dev_close(dev);

2906

else

2906

else

2907

sky2_set_multicast(dev);

2907

sky2_set_multicast(dev);

2908

}

2908

}

2909

2910

return err;

2910

return err;

2911

}

2911

}

2912

2913

static int sky2_get_regs_len(struct net_device *dev)

2913

static int sky2_get_regs_len(struct net_device *dev)

2914

{

2914

{

2915

return 0x4000;

2915

return 0x4000;

2916

}

2916

}

2917

2918

/*

2918

/*

2919

* Returns copy of control register region

2919

* Returns copy of control register region

2920

* Note: access to the RAM address register set will cause timeouts.

2920

* Note: access to the RAM address register set will cause timeouts.

2921

*/

2921

*/

2922

static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,

2922

static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,

2923

void *p)

2923

void *p)

2924

{

2924

{

2925

const struct sky2_port *sky2 = netdev_priv(dev);

2925

const struct sky2_port *sky2 = netdev_priv(dev);

2926

const void __iomem *io = sky2->hw->regs;

2926

const void __iomem *io = sky2->hw->regs;

2927

2928

BUG_ON(regs->len < B3_RI_WTO_R1);

2928

BUG_ON(regs->len < B3_RI_WTO_R1);

2929

regs->version = 1;

2929

regs->version = 1;

2930

memset(p, 0, regs->len);

2930

memset(p, 0, regs->len);

2931

2932

memcpy_fromio(p, io, B3_RAM_ADDR);

2932

memcpy_fromio(p, io, B3_RAM_ADDR);

2933

2934

memcpy_fromio(p + B3_RI_WTO_R1,

2934

memcpy_fromio(p + B3_RI_WTO_R1,

2935

io + B3_RI_WTO_R1,

2935

io + B3_RI_WTO_R1,

2936

regs->len - B3_RI_WTO_R1);

2936

regs->len - B3_RI_WTO_R1);

2937

}

2937

}

2938

2939

static struct ethtool_ops sky2_ethtool_ops = {

2939

static struct ethtool_ops sky2_ethtool_ops = {

2940

.get_settings = sky2_get_settings,

2940

.get_settings = sky2_get_settings,

2941

.set_settings = sky2_set_settings,

2941

.set_settings = sky2_set_settings,

2942

.get_drvinfo = sky2_get_drvinfo,

2942

.get_drvinfo = sky2_get_drvinfo,

2943

.get_msglevel = sky2_get_msglevel,

2943

.get_msglevel = sky2_get_msglevel,

2944

.set_msglevel = sky2_set_msglevel,

2944

.set_msglevel = sky2_set_msglevel,

2945

.nway_reset = sky2_nway_reset,

2945

.nway_reset = sky2_nway_reset,

2946

.get_regs_len = sky2_get_regs_len,

2946

.get_regs_len = sky2_get_regs_len,

2947

.get_regs = sky2_get_regs,

2947

.get_regs = sky2_get_regs,

2948

.get_link = ethtool_op_get_link,

2948

.get_link = ethtool_op_get_link,

2949

.get_sg = ethtool_op_get_sg,

2949

.get_sg = ethtool_op_get_sg,

2950

.set_sg = ethtool_op_set_sg,

2950

.set_sg = ethtool_op_set_sg,

2951

.get_tx_csum = ethtool_op_get_tx_csum,

2951

.get_tx_csum = ethtool_op_get_tx_csum,

2952

.set_tx_csum = ethtool_op_set_tx_csum,

2952

.set_tx_csum = ethtool_op_set_tx_csum,

2953

.get_tso = ethtool_op_get_tso,

2953

.get_tso = ethtool_op_get_tso,

2954

.set_tso = ethtool_op_set_tso,

2954

.set_tso = ethtool_op_set_tso,

2955

.get_rx_csum = sky2_get_rx_csum,

2955

.get_rx_csum = sky2_get_rx_csum,

2956

.set_rx_csum = sky2_set_rx_csum,

2956

.set_rx_csum = sky2_set_rx_csum,

2957

.get_strings = sky2_get_strings,

2957

.get_strings = sky2_get_strings,

2958

.get_coalesce = sky2_get_coalesce,

2958

.get_coalesce = sky2_get_coalesce,

2959

.set_coalesce = sky2_set_coalesce,

2959

.set_coalesce = sky2_set_coalesce,

2960

.get_ringparam = sky2_get_ringparam,

2960

.get_ringparam = sky2_get_ringparam,

2961

.set_ringparam = sky2_set_ringparam,

2961

.set_ringparam = sky2_set_ringparam,

2962

.get_pauseparam = sky2_get_pauseparam,

2962

.get_pauseparam = sky2_get_pauseparam,

2963

.set_pauseparam = sky2_set_pauseparam,

2963

.set_pauseparam = sky2_set_pauseparam,

2964

.phys_id = sky2_phys_id,

2964

.phys_id = sky2_phys_id,

2965

.get_stats_count = sky2_get_stats_count,

2965

.get_stats_count = sky2_get_stats_count,

2966

.get_ethtool_stats = sky2_get_ethtool_stats,

2966

.get_ethtool_stats = sky2_get_ethtool_stats,

2967

.get_perm_addr = ethtool_op_get_perm_addr,

2967

.get_perm_addr = ethtool_op_get_perm_addr,

2968

};

2968

};

2969

2970

/* Initialize network device */

2970

/* Initialize network device */

2971

static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,

2971

static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,

2972

unsigned port, int highmem)

2972

unsigned port, int highmem)

2973

{

2973

{

2974

struct sky2_port *sky2;

2974

struct sky2_port *sky2;

2975

struct net_device *dev = alloc_etherdev(sizeof(*sky2));

2975

struct net_device *dev = alloc_etherdev(sizeof(*sky2));

2976

2977

if (!dev) {

2977

if (!dev) {

2978

printk(KERN_ERR "sky2 etherdev alloc failed");

2978

printk(KERN_ERR "sky2 etherdev alloc failed");

2979

return NULL;

2979

return NULL;

2980

}

2980

}

2981

2982

SET_MODULE_OWNER(dev);

2982

SET_MODULE_OWNER(dev);

2983

SET_NETDEV_DEV(dev, &hw->pdev->dev);

2983

SET_NETDEV_DEV(dev, &hw->pdev->dev);

2984

dev->irq = hw->pdev->irq;

2984

dev->irq = hw->pdev->irq;

2985

dev->open = sky2_up;

2985

dev->open = sky2_up;

2986

dev->stop = sky2_down;

2986

dev->stop = sky2_down;

2987

dev->do_ioctl = sky2_ioctl;

2987

dev->do_ioctl = sky2_ioctl;

2988

dev->hard_start_xmit = sky2_xmit_frame;

2988

dev->hard_start_xmit = sky2_xmit_frame;

2989

dev->get_stats = sky2_get_stats;

2989

dev->get_stats = sky2_get_stats;

2990

dev->set_multicast_list = sky2_set_multicast;

2990

dev->set_multicast_list = sky2_set_multicast;

2991

dev->set_mac_address = sky2_set_mac_address;

2991

dev->set_mac_address = sky2_set_mac_address;

2992

dev->change_mtu = sky2_change_mtu;

2992

dev->change_mtu = sky2_change_mtu;

2993

SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);

2993

SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);

2994

dev->tx_timeout = sky2_tx_timeout;

2994

dev->tx_timeout = sky2_tx_timeout;

2995

dev->watchdog_timeo = TX_WATCHDOG;

2995

dev->watchdog_timeo = TX_WATCHDOG;

2996

if (port == 0)

2996

if (port == 0)

2997

dev->poll = sky2_poll;

2997

dev->poll = sky2_poll;

2998

dev->weight = NAPI_WEIGHT;

2998

dev->weight = NAPI_WEIGHT;

2999

#ifdef CONFIG_NET_POLL_CONTROLLER

2999

#ifdef CONFIG_NET_POLL_CONTROLLER

3000

dev->poll_controller = sky2_netpoll;

3000

dev->poll_controller = sky2_netpoll;

3001

#endif

3001

#endif

3002

3003

sky2 = netdev_priv(dev);

3003

sky2 = netdev_priv(dev);

3004

sky2->netdev = dev;

3004

sky2->netdev = dev;

3005

sky2->hw = hw;

3005

sky2->hw = hw;

3006

sky2->msg_enable = netif_msg_init(debug, default_msg);

3006

sky2->msg_enable = netif_msg_init(debug, default_msg);

3007

3008

spin_lock_init(&sky2->tx_lock);

3008

spin_lock_init(&sky2->tx_lock);

3009

/* Auto speed and flow control */

3009

/* Auto speed and flow control */

3010

sky2->autoneg = AUTONEG_ENABLE;

3010

sky2->autoneg = AUTONEG_ENABLE;

3011

sky2->tx_pause = 1;

3011

sky2->tx_pause = 1;

3012

sky2->rx_pause = 1;

3012

sky2->rx_pause = 1;

3013

sky2->duplex = -1;

3013

sky2->duplex = -1;

3014

sky2->speed = -1;

3014

sky2->speed = -1;

3015

sky2->advertising = sky2_supported_modes(hw);

3015

sky2->advertising = sky2_supported_modes(hw);

3016

3017

/* Receive checksum disabled for Yukon XL

3017

/* Receive checksum disabled for Yukon XL

3018

* because of observed problems with incorrect

3018

* because of observed problems with incorrect

3019

* values when multiple packets are received in one interrupt

3019

* values when multiple packets are received in one interrupt

3020

*/

3020

*/

3021

sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);

3021

sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);

3022

3023

spin_lock_init(&sky2->phy_lock);

3023

spin_lock_init(&sky2->phy_lock);

3024

sky2->tx_pending = TX_DEF_PENDING;

3024

sky2->tx_pending = TX_DEF_PENDING;

3025

sky2->rx_pending = RX_DEF_PENDING;

3025

sky2->rx_pending = RX_DEF_PENDING;

3026

sky2->rx_bufsize = sky2_buf_size(ETH_DATA_LEN);

3026

sky2->rx_bufsize = sky2_buf_size(ETH_DATA_LEN);

3027

3028

hw->dev[port] = dev;

3028

hw->dev[port] = dev;

3029

3030

sky2->port = port;

3030

sky2->port = port;

3031

3032

dev->features |= NETIF_F_LLTX;

3032

dev->features |= NETIF_F_LLTX;

3033

if (hw->chip_id != CHIP_ID_YUKON_EC_U)

3033

if (hw->chip_id != CHIP_ID_YUKON_EC_U)

3034

dev->features |= NETIF_F_TSO;

3034

dev->features |= NETIF_F_TSO;

3035

if (highmem)

3035

if (highmem)

3036

dev->features |= NETIF_F_HIGHDMA;

3036

dev->features |= NETIF_F_HIGHDMA;

3037

dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;

3037

dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;

3038

3039

#ifdef SKY2_VLAN_TAG_USED

3039

#ifdef SKY2_VLAN_TAG_USED

3040

dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;

3040

dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;

3041

dev->vlan_rx_register = sky2_vlan_rx_register;

3041

dev->vlan_rx_register = sky2_vlan_rx_register;

3042

dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;

3042

dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;

3043

#endif

3043

#endif

3044

3045

/* read the mac address */

3045

/* read the mac address */

3046

memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);

3046

memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);

3047

memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);

3047

memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);

3048

3049

/* device is off until link detection */

3049

/* device is off until link detection */

3050

netif_carrier_off(dev);

3050

netif_carrier_off(dev);

3051

netif_stop_queue(dev);

3051

netif_stop_queue(dev);

3052

3053

return dev;

3053

return dev;

3054

}

3054

}

3055

3056

static void __devinit sky2_show_addr(struct net_device *dev)

3056

static void __devinit sky2_show_addr(struct net_device *dev)

3057

{

3057

{

3058

const struct sky2_port *sky2 = netdev_priv(dev);

3058

const struct sky2_port *sky2 = netdev_priv(dev);

3059

3060

if (netif_msg_probe(sky2))

3060

if (netif_msg_probe(sky2))

3061

printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",

3061

printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",

3062

dev->name,

3062

dev->name,

3063

dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],

3063

dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],

3064

dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);

3064

dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);

3065

}

3065

}

3066

3067

/* Handle software interrupt used during MSI test */

3067

/* Handle software interrupt used during MSI test */

3068

static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id,

3068

static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id,

3069

struct pt_regs *regs)

3069

struct pt_regs *regs)

3070

{

3070

{

3071

struct sky2_hw *hw = dev_id;

3071

struct sky2_hw *hw = dev_id;

3072

u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);

3072

u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);

3073

3074

if (status == 0)

3074

if (status == 0)

3075

return IRQ_NONE;

3075

return IRQ_NONE;

3076

3077

if (status & Y2_IS_IRQ_SW) {

3077

if (status & Y2_IS_IRQ_SW) {

3078

hw->msi_detected = 1;

3078

hw->msi_detected = 1;

3079

wake_up(&hw->msi_wait);

3079

wake_up(&hw->msi_wait);

3080

sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);

3080

sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);

3081

}

3081

}

3082

sky2_write32(hw, B0_Y2_SP_ICR, 2);

3082

sky2_write32(hw, B0_Y2_SP_ICR, 2);

3083

3084

return IRQ_HANDLED;

3084

return IRQ_HANDLED;

3085

}

3085

}

3086

3087

/* Test interrupt path by forcing a a software IRQ */

3087

/* Test interrupt path by forcing a a software IRQ */

3088

static int __devinit sky2_test_msi(struct sky2_hw *hw)

3088

static int __devinit sky2_test_msi(struct sky2_hw *hw)

3089

{

3089

{

3090

struct pci_dev *pdev = hw->pdev;

3090

struct pci_dev *pdev = hw->pdev;

3091

int err;

3091

int err;

3092

3093

sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);

3093

sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);

3094

3095

err = request_irq(pdev->irq, sky2_test_intr, SA_SHIRQ, DRV_NAME, hw);

3095

err = request_irq(pdev->irq, sky2_test_intr, SA_SHIRQ, DRV_NAME, hw);

3096

if (err) {

3096

if (err) {

3097

printk(KERN_ERR PFX "%s: cannot assign irq %d\n",

3097

printk(KERN_ERR PFX "%s: cannot assign irq %d\n",

3098

pci_name(pdev), pdev->irq);

3098

pci_name(pdev), pdev->irq);

3099

return err;

3099

return err;

3100

}

3100

}

3101

3102

init_waitqueue_head (&hw->msi_wait);

3102

init_waitqueue_head (&hw->msi_wait);

3103

3104

sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);

3104

sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);

3105

wmb();

3105

wmb();

3106

3107

wait_event_timeout(hw->msi_wait, hw->msi_detected, HZ/10);

3107

wait_event_timeout(hw->msi_wait, hw->msi_detected, HZ/10);

3108

3109

if (!hw->msi_detected) {

3109

if (!hw->msi_detected) {

3110

/* MSI test failed, go back to INTx mode */

3110

/* MSI test failed, go back to INTx mode */

3111

printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "

3111

printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "

3112

"switching to INTx mode. Please report this failure to "

3112

"switching to INTx mode. Please report this failure to "

3113

"the PCI maintainer and include system chipset information.\n",

3113

"the PCI maintainer and include system chipset information.\n",

3114

pci_name(pdev));

3114

pci_name(pdev));

3115

3116

err = -EOPNOTSUPP;

3116

err = -EOPNOTSUPP;

3117

sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);

3117

sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);

3118

}

3118

}

3119

3120

sky2_write32(hw, B0_IMSK, 0);

3120

sky2_write32(hw, B0_IMSK, 0);

3121

3122

free_irq(pdev->irq, hw);

3122

free_irq(pdev->irq, hw);

3123

3124

return err;

3124

return err;

3125

}

3125

}

3126

3127

static int __devinit sky2_probe(struct pci_dev *pdev,

3127

static int __devinit sky2_probe(struct pci_dev *pdev,

3128

const struct pci_device_id *ent)

3128

const struct pci_device_id *ent)

3129

{

3129

{

3130

struct net_device *dev, *dev1 = NULL;

3130

struct net_device *dev, *dev1 = NULL;

3131

struct sky2_hw *hw;

3131

struct sky2_hw *hw;

3132

int err, pm_cap, using_dac = 0;

3132

int err, pm_cap, using_dac = 0;

3133

3134

err = pci_enable_device(pdev);

3134

err = pci_enable_device(pdev);

3135

if (err) {

3135

if (err) {

3136

printk(KERN_ERR PFX "%s cannot enable PCI device\n",

3136

printk(KERN_ERR PFX "%s cannot enable PCI device\n",

3137

pci_name(pdev));

3137

pci_name(pdev));

3138

goto err_out;

3138

goto err_out;

3139

}

3139

}

3140

3141

err = pci_request_regions(pdev, DRV_NAME);

3141

err = pci_request_regions(pdev, DRV_NAME);

3142

if (err) {

3142

if (err) {

3143

printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",

3143

printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",

3144

pci_name(pdev));

3144

pci_name(pdev));

3145

goto err_out;

3145

goto err_out;

3146

}

3146

}

3147

3148

pci_set_master(pdev);

3148

pci_set_master(pdev);

3149

3150

/* Find power-management capability. */

3150

/* Find power-management capability. */

3151

pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);

3151

pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);

3152

if (pm_cap == 0) {

3152

if (pm_cap == 0) {

3153

printk(KERN_ERR PFX "Cannot find PowerManagement capability, "

3153

printk(KERN_ERR PFX "Cannot find PowerManagement capability, "

3154

"aborting.\n");

3154

"aborting.\n");

3155

err = -EIO;

3155

err = -EIO;

3156

goto err_out_free_regions;

3156

goto err_out_free_regions;

3157

}

3157

}

3158

3159

if (sizeof(dma_addr_t) > sizeof(u32) &&

3159

if (sizeof(dma_addr_t) > sizeof(u32) &&

3160

!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {

3160

!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {

3161

using_dac = 1;

3161

using_dac = 1;

3162

err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);

3162

err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);

3163

if (err < 0) {

3163

if (err < 0) {

3164

printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA "

3164

printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA "

3165

"for consistent allocations\n", pci_name(pdev));

3165

"for consistent allocations\n", pci_name(pdev));

3166

goto err_out_free_regions;

3166

goto err_out_free_regions;

3167

}

3167

}

3168

3169

} else {

3169

} else {

3170

err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);

3170

err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);

3171

if (err) {

3171

if (err) {

3172

printk(KERN_ERR PFX "%s no usable DMA configuration\n",

3172

printk(KERN_ERR PFX "%s no usable DMA configuration\n",

3173

pci_name(pdev));

3173

pci_name(pdev));

3174

goto err_out_free_regions;

3174

goto err_out_free_regions;

3175

}

3175

}

3176

}

3176

}

3177

3178

err = -ENOMEM;

3178

err = -ENOMEM;

3179

hw = kzalloc(sizeof(*hw), GFP_KERNEL);

3179

hw = kzalloc(sizeof(*hw), GFP_KERNEL);

3180

if (!hw) {

3180

if (!hw) {

3181

printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",

3181

printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",

3182

pci_name(pdev));

3182

pci_name(pdev));

3183

goto err_out_free_regions;

3183

goto err_out_free_regions;

3184

}

3184

}

3185

3186

hw->pdev = pdev;

3186

hw->pdev = pdev;

3187

3188

hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);

3188

hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);

3189

if (!hw->regs) {

3189

if (!hw->regs) {

3190

printk(KERN_ERR PFX "%s: cannot map device registers\n",

3190

printk(KERN_ERR PFX "%s: cannot map device registers\n",

3191

pci_name(pdev));

3191

pci_name(pdev));

3192

goto err_out_free_hw;

3192

goto err_out_free_hw;

3193

}

3193

}

3194

hw->pm_cap = pm_cap;

3194

hw->pm_cap = pm_cap;

3195

3196

#ifdef __BIG_ENDIAN

3196

#ifdef __BIG_ENDIAN

3197

/* byte swap descriptors in hardware */

3197

/* byte swap descriptors in hardware */

3198

{

3198

{

3199

u32 reg;

3199

u32 reg;

3200

3201

reg = sky2_pci_read32(hw, PCI_DEV_REG2);

3201

reg = sky2_pci_read32(hw, PCI_DEV_REG2);

3202

reg |= PCI_REV_DESC;

3202

reg |= PCI_REV_DESC;

3203

sky2_pci_write32(hw, PCI_DEV_REG2, reg);

3203

sky2_pci_write32(hw, PCI_DEV_REG2, reg);

3204

}

3204

}

3205

#endif

3205

#endif

3206

3207

/* ring for status responses */

3207

/* ring for status responses */

3208

hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,

3208

hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,

3209

&hw->st_dma);

3209

&hw->st_dma);

3210

if (!hw->st_le)

3210

if (!hw->st_le)

3211

goto err_out_iounmap;

3211

goto err_out_iounmap;

3212

3213

err = sky2_reset(hw);

3213

err = sky2_reset(hw);

3214

if (err)

3214

if (err)

3215

goto err_out_iounmap;

3215

goto err_out_iounmap;

3216

3217

printk(KERN_INFO PFX "v%s addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n",

3217

printk(KERN_INFO PFX "v%s addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n",

3218

DRV_VERSION, pci_resource_start(pdev, 0), pdev->irq,

3218

DRV_VERSION, pci_resource_start(pdev, 0), pdev->irq,

3219

yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],

3219

yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],

3220

hw->chip_id, hw->chip_rev);

3220

hw->chip_id, hw->chip_rev);

3221

3222

dev = sky2_init_netdev(hw, 0, using_dac);

3222

dev = sky2_init_netdev(hw, 0, using_dac);

3223

if (!dev)

3223

if (!dev)

3224

goto err_out_free_pci;

3224

goto err_out_free_pci;

3225

3226

err = register_netdev(dev);

3226

err = register_netdev(dev);

3227

if (err) {

3227

if (err) {

3228

printk(KERN_ERR PFX "%s: cannot register net device\n",

3228

printk(KERN_ERR PFX "%s: cannot register net device\n",

3229

pci_name(pdev));

3229

pci_name(pdev));

3230

goto err_out_free_netdev;

3230

goto err_out_free_netdev;

3231

}

3231

}

3232

3233

sky2_show_addr(dev);

3233

sky2_show_addr(dev);

3234

3235

if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {

3235

if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {

3236

if (register_netdev(dev1) == 0)

3236

if (register_netdev(dev1) == 0)

3237

sky2_show_addr(dev1);

3237

sky2_show_addr(dev1);

3238

else {

3238

else {

3239

/* Failure to register second port need not be fatal */

3239

/* Failure to register second port need not be fatal */

3240

printk(KERN_WARNING PFX

3240

printk(KERN_WARNING PFX

3241

"register of second port failed\n");

3241

"register of second port failed\n");

3242

hw->dev[1] = NULL;

3242

hw->dev[1] = NULL;

3243

free_netdev(dev1);

3243

free_netdev(dev1);

3244

}

3244

}

3245

}

3245

}

3246

3247

if (!disable_msi && pci_enable_msi(pdev) == 0) {

3247

if (!disable_msi && pci_enable_msi(pdev) == 0) {

3248

err = sky2_test_msi(hw);

3248

err = sky2_test_msi(hw);

3249

if (err == -EOPNOTSUPP)

3249

if (err == -EOPNOTSUPP)

3250

pci_disable_msi(pdev);

3250

pci_disable_msi(pdev);

3251

else if (err)

3251

else if (err)

3252

goto err_out_unregister;

3252

goto err_out_unregister;

3253

}

3253

}

3254

3255

err = request_irq(pdev->irq, sky2_intr, SA_SHIRQ, DRV_NAME, hw);

3255

err = request_irq(pdev->irq, sky2_intr, SA_SHIRQ, DRV_NAME, hw);

3256

if (err) {

3256

if (err) {

3257

printk(KERN_ERR PFX "%s: cannot assign irq %d\n",

3257

printk(KERN_ERR PFX "%s: cannot assign irq %d\n",

3258

pci_name(pdev), pdev->irq);

3258

pci_name(pdev), pdev->irq);

3259

goto err_out_unregister;

3259

goto err_out_unregister;

3260

}

3260

}

3261

3262

sky2_write32(hw, B0_IMSK, Y2_IS_BASE);

3262

sky2_write32(hw, B0_IMSK, Y2_IS_BASE);

3263

3264

pci_set_drvdata(pdev, hw);

3264

pci_set_drvdata(pdev, hw);

3265

3266

return 0;

3266

return 0;

3267

3268

err_out_unregister:

3268

err_out_unregister:

3269

pci_disable_msi(pdev);

3269

pci_disable_msi(pdev);

3270

if (dev1) {

3270

if (dev1) {

3271

unregister_netdev(dev1);

3271

unregister_netdev(dev1);

3272

free_netdev(dev1);

3272

free_netdev(dev1);

3273

}

3273

}

3274

unregister_netdev(dev);

3274

unregister_netdev(dev);

3275

err_out_free_netdev:

3275

err_out_free_netdev:

3276

free_netdev(dev);

3276

free_netdev(dev);

3277

err_out_free_pci:

3277

err_out_free_pci:

3278

sky2_write8(hw, B0_CTST, CS_RST_SET);

3278

sky2_write8(hw, B0_CTST, CS_RST_SET);

3279

pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);

3279

pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);

3280

err_out_iounmap:

3280

err_out_iounmap:

3281

iounmap(hw->regs);

3281

iounmap(hw->regs);

3282

err_out_free_hw:

3282

err_out_free_hw:

3283

kfree(hw);

3283

kfree(hw);

3284

err_out_free_regions:

3284

err_out_free_regions:

3285

pci_release_regions(pdev);

3285

pci_release_regions(pdev);

3286

pci_disable_device(pdev);

3286

pci_disable_device(pdev);

3287

err_out:

3287

err_out:

3288

return err;

3288

return err;

3289

}

3289

}

3290

3291

static void __devexit sky2_remove(struct pci_dev *pdev)

3291

static void __devexit sky2_remove(struct pci_dev *pdev)

3292

{

3292

{

3293

struct sky2_hw *hw = pci_get_drvdata(pdev);

3293

struct sky2_hw *hw = pci_get_drvdata(pdev);

3294

struct net_device *dev0, *dev1;

3294

struct net_device *dev0, *dev1;

3295

3296

if (!hw)

3296

if (!hw)

3297

return;

3297

return;

3298

3299

dev0 = hw->dev[0];

3299

dev0 = hw->dev[0];

3300

dev1 = hw->dev[1];

3300

dev1 = hw->dev[1];

3301

if (dev1)

3301

if (dev1)

3302

unregister_netdev(dev1);

3302

unregister_netdev(dev1);

3303

unregister_netdev(dev0);

3303

unregister_netdev(dev0);

3304

3305

sky2_write32(hw, B0_IMSK, 0);

3305

sky2_write32(hw, B0_IMSK, 0);

3306

sky2_set_power_state(hw, PCI_D3hot);

3306

sky2_set_power_state(hw, PCI_D3hot);

3307

sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);

3307

sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);

3308

sky2_write8(hw, B0_CTST, CS_RST_SET);

3308

sky2_write8(hw, B0_CTST, CS_RST_SET);

3309

sky2_read8(hw, B0_CTST);

3309

sky2_read8(hw, B0_CTST);

3310

3311

free_irq(pdev->irq, hw);

3311

free_irq(pdev->irq, hw);

3312

pci_disable_msi(pdev);

3312

pci_disable_msi(pdev);

3313

pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);

3313

pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);

3314

pci_release_regions(pdev);

3314

pci_release_regions(pdev);

3315

pci_disable_device(pdev);

3315

pci_disable_device(pdev);

3316

3317

if (dev1)

3317

if (dev1)

3318

free_netdev(dev1);

3318

free_netdev(dev1);

3319

free_netdev(dev0);

3319

free_netdev(dev0);

3320

iounmap(hw->regs);

3320

iounmap(hw->regs);

3321

kfree(hw);

3321

kfree(hw);

3322

3323

pci_set_drvdata(pdev, NULL);

3323

pci_set_drvdata(pdev, NULL);

3324

}

3324

}

3325

3326

#ifdef CONFIG_PM

3326

#ifdef CONFIG_PM

3327

static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)

3327

static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)

3328

{

3328

{

3329

struct sky2_hw *hw = pci_get_drvdata(pdev);

3329

struct sky2_hw *hw = pci_get_drvdata(pdev);

3330

int i;

3330

int i;

3331

3332

for (i = 0; i < 2; i++) {

3332

for (i = 0; i < 2; i++) {

3333

struct net_device *dev = hw->dev[i];

3333

struct net_device *dev = hw->dev[i];

3334

3335

if (dev) {

3335

if (dev) {

3336

if (!netif_running(dev))

3336

if (!netif_running(dev))

3337

continue;

3337

continue;

3338

3339

sky2_down(dev);

3339

sky2_down(dev);

3340

netif_device_detach(dev);

3340

netif_device_detach(dev);

3341

}

3341

}

3342

}

3342

}

3343

3344

return sky2_set_power_state(hw, pci_choose_state(pdev, state));

3344

return sky2_set_power_state(hw, pci_choose_state(pdev, state));

3345

}

3345

}

3346

3347

static int sky2_resume(struct pci_dev *pdev)

3347

static int sky2_resume(struct pci_dev *pdev)

3348

{

3348

{

3349

struct sky2_hw *hw = pci_get_drvdata(pdev);

3349

struct sky2_hw *hw = pci_get_drvdata(pdev);

3350

int i, err;

3350

int i, err;

3351

3352

pci_restore_state(pdev);

3352

pci_restore_state(pdev);

3353

pci_enable_wake(pdev, PCI_D0, 0);

3353

pci_enable_wake(pdev, PCI_D0, 0);

3354

err = sky2_set_power_state(hw, PCI_D0);

3354

err = sky2_set_power_state(hw, PCI_D0);

3355

if (err)

3355

if (err)

3356

goto out;

3356

goto out;

3357

3358

err = sky2_reset(hw);

3358

err = sky2_reset(hw);

3359

if (err)

3359

if (err)

3360

goto out;

3360

goto out;

3361

3362

for (i = 0; i < 2; i++) {

3362

for (i = 0; i < 2; i++) {

3363

struct net_device *dev = hw->dev[i];

3363

struct net_device *dev = hw->dev[i];

3364

if (dev && netif_running(dev)) {

3364

if (dev && netif_running(dev)) {

3365

netif_device_attach(dev);

3365

netif_device_attach(dev);

3366

err = sky2_up(dev);

3366

err = sky2_up(dev);

3367

if (err) {

3367

if (err) {

3368

printk(KERN_ERR PFX "%s: could not up: %d\n",

3368

printk(KERN_ERR PFX "%s: could not up: %d\n",

3369

dev->name, err);

3369

dev->name, err);

3370

dev_close(dev);

3370

dev_close(dev);

3371

break;

3371

break;

3372

}

3372

}

3373

}

3373

}

3374

}

3374

}

3375

out:

3375

out:

3376

return err;

3376

return err;

3377

}

3377

}

3378

#endif

3378

#endif

3379

3380

static struct pci_driver sky2_driver = {

3380

static struct pci_driver sky2_driver = {

3381

.name = DRV_NAME,

3381

.name = DRV_NAME,

3382

.id_table = sky2_id_table,

3382

.id_table = sky2_id_table,

3383

.probe = sky2_probe,

3383

.probe = sky2_probe,

3384

.remove = __devexit_p(sky2_remove),

3384

.remove = __devexit_p(sky2_remove),

3385

#ifdef CONFIG_PM

3385

#ifdef CONFIG_PM

3386

.suspend = sky2_suspend,

3386

.suspend = sky2_suspend,

3387

.resume = sky2_resume,

3387

.resume = sky2_resume,

3388

#endif

3388

#endif

3389

};

3389

};

3390

3391

static int __init sky2_init_module(void)

3391

static int __init sky2_init_module(void)

3392

{

3392

{

3393

return pci_register_driver(&sky2_driver);

3393

return pci_register_driver(&sky2_driver);

3394

}

3394

}

3395

3396

static void __exit sky2_cleanup_module(void)

3396

static void __exit sky2_cleanup_module(void)

3397

{

3397

{

3398

pci_unregister_driver(&sky2_driver);

3398

pci_unregister_driver(&sky2_driver);

3399

}

3399

}

3400

3401

module_init(sky2_init_module);

3401

module_init(sky2_init_module);

3402

module_exit(sky2_cleanup_module);

3402

module_exit(sky2_cleanup_module);

3403

3404

MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");

3404

MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");

3405

MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");

3405

MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");

3406

MODULE_LICENSE("GPL");

3406

MODULE_LICENSE("GPL");

3407

MODULE_VERSION(DRV_VERSION);

3407

MODULE_VERSION(DRV_VERSION);

3408

GITLAB

Eric Lee / linux-smarc-t335x-v3.2

[PATCH] sky2 version 1.1