Eric Lee / linux-smarc-t335x-v3.2

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/*

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/*

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* New driver for Marvell Yukon chipset and SysKonnect Gigabit

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* New driver for Marvell Yukon chipset and SysKonnect Gigabit

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* Ethernet adapters. Based on earlier sk98lin, e100 and

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* Ethernet adapters. Based on earlier sk98lin, e100 and

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* FreeBSD if_sk drivers.

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* FreeBSD if_sk drivers.

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*

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*

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* This driver intentionally does not support all the features

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* This driver intentionally does not support all the features

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* of the original driver such as link fail-over and link management because

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* of the original driver such as link fail-over and link management because

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* those should be done at higher levels.

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* those should be done at higher levels.

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*

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*

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*

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*

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* This program is free software; you can redistribute it and/or modify

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* This program is free software; you can redistribute it and/or modify

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* it under the terms of the GNU General Public License as published by

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* it under the terms of the GNU General Public License as published by

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* the Free Software Foundation; either version 2 of the License, or

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* the Free Software Foundation; either version 2 of the License, or

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* (at your option) any later version.

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* (at your option) any later version.

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*

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*

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* This program is distributed in the hope that it will be useful,

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* This program is distributed in the hope that it will be useful,

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* but WITHOUT ANY WARRANTY; without even the implied warranty of

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* but WITHOUT ANY WARRANTY; without even the implied warranty of

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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

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* GNU General Public License for more details.

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* GNU General Public License for more details.

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*

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*

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* You should have received a copy of the GNU General Public License

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* You should have received a copy of the GNU General Public License

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* along with this program; if not, write to the Free Software

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* along with this program; if not, write to the Free Software

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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.

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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.

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*/

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*/

26

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#include <linux/config.h>

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#include <linux/config.h>

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#include <linux/in.h>

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#include <linux/in.h>

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#include <linux/kernel.h>

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#include <linux/kernel.h>

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#include <linux/module.h>

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#include <linux/module.h>

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#include <linux/moduleparam.h>

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#include <linux/moduleparam.h>

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#include <linux/netdevice.h>

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#include <linux/netdevice.h>

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#include <linux/etherdevice.h>

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#include <linux/etherdevice.h>

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#include <linux/ethtool.h>

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#include <linux/ethtool.h>

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#include <linux/pci.h>

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#include <linux/pci.h>

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#include <linux/if_vlan.h>

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#include <linux/if_vlan.h>

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#include <linux/ip.h>

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#include <linux/ip.h>

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#include <linux/delay.h>

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#include <linux/delay.h>

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#include <linux/crc32.h>

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#include <linux/crc32.h>

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#include <linux/dma-mapping.h>

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#include <linux/dma-mapping.h>

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#include <linux/mii.h>

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#include <linux/mii.h>

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#include <asm/irq.h>

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#include <asm/irq.h>

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#include "skge.h"

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#include "skge.h"

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#define DRV_NAME "skge"

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#define DRV_NAME "skge"

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#define DRV_VERSION "1.3"

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#define DRV_VERSION "1.3"

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#define PFX DRV_NAME " "

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#define PFX DRV_NAME " "

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#define DEFAULT_TX_RING_SIZE 128

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#define DEFAULT_TX_RING_SIZE 128

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#define DEFAULT_RX_RING_SIZE 512

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#define DEFAULT_RX_RING_SIZE 512

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#define MAX_TX_RING_SIZE 1024

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#define MAX_TX_RING_SIZE 1024

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#define MAX_RX_RING_SIZE 4096

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#define MAX_RX_RING_SIZE 4096

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#define RX_COPY_THRESHOLD 128

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#define RX_COPY_THRESHOLD 128

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#define RX_BUF_SIZE 1536

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#define RX_BUF_SIZE 1536

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#define PHY_RETRIES 1000

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#define PHY_RETRIES 1000

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#define ETH_JUMBO_MTU 9000

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#define ETH_JUMBO_MTU 9000

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#define TX_WATCHDOG (5 * HZ)

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#define TX_WATCHDOG (5 * HZ)

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#define NAPI_WEIGHT 64

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#define NAPI_WEIGHT 64

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#define BLINK_MS 250

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#define BLINK_MS 250

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MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");

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MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");

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MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");

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MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");

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MODULE_LICENSE("GPL");

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MODULE_LICENSE("GPL");

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MODULE_VERSION(DRV_VERSION);

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MODULE_VERSION(DRV_VERSION);

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static const u32 default_msg

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static const u32 default_msg

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= NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK

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= NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK

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| NETIF_MSG_IFUP| NETIF_MSG_IFDOWN;

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| NETIF_MSG_IFUP| NETIF_MSG_IFDOWN;

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static int debug = -1; /* defaults above */

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static int debug = -1; /* defaults above */

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module_param(debug, int, 0);

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module_param(debug, int, 0);

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MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");

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MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");

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static const struct pci_device_id skge_id_table[] = {

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static const struct pci_device_id skge_id_table[] = {

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{ PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },

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{ PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },

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{ PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },

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{ PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },

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{ PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },

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{ PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },

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{ PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },

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{ PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },

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{ PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T), },

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{ PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T), },

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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },

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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },

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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */

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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */

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{ PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },

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{ PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },

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{ PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },

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{ PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },

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{ PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015, },

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{ PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015, },

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{ 0 }

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{ 0 }

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};

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};

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MODULE_DEVICE_TABLE(pci, skge_id_table);

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MODULE_DEVICE_TABLE(pci, skge_id_table);

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static int skge_up(struct net_device *dev);

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static int skge_up(struct net_device *dev);

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static int skge_down(struct net_device *dev);

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static int skge_down(struct net_device *dev);

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static void skge_phy_reset(struct skge_port *skge);

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static void skge_phy_reset(struct skge_port *skge);

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static void skge_tx_clean(struct skge_port *skge);

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static void skge_tx_clean(struct skge_port *skge);

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static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);

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static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);

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static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);

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static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);

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static void genesis_get_stats(struct skge_port *skge, u64 *data);

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static void genesis_get_stats(struct skge_port *skge, u64 *data);

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static void yukon_get_stats(struct skge_port *skge, u64 *data);

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static void yukon_get_stats(struct skge_port *skge, u64 *data);

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static void yukon_init(struct skge_hw *hw, int port);

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static void yukon_init(struct skge_hw *hw, int port);

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static void genesis_mac_init(struct skge_hw *hw, int port);

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static void genesis_mac_init(struct skge_hw *hw, int port);

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static void genesis_link_up(struct skge_port *skge);

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static void genesis_link_up(struct skge_port *skge);

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/* Avoid conditionals by using array */

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/* Avoid conditionals by using array */

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static const int txqaddr[] = { Q_XA1, Q_XA2 };

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static const int txqaddr[] = { Q_XA1, Q_XA2 };

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static const int rxqaddr[] = { Q_R1, Q_R2 };

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static const int rxqaddr[] = { Q_R1, Q_R2 };

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static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };

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static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };

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static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };

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static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };

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static int skge_get_regs_len(struct net_device *dev)

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static int skge_get_regs_len(struct net_device *dev)

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{

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{

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return 0x4000;

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return 0x4000;

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}

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}

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/*

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/*

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* Returns copy of whole control register region

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* Returns copy of whole control register region

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* Note: skip RAM address register because accessing it will

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* Note: skip RAM address register because accessing it will

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* cause bus hangs!

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* cause bus hangs!

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*/

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*/

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static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,

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static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,

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void *p)

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void *p)

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{

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{

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const struct skge_port *skge = netdev_priv(dev);

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const struct skge_port *skge = netdev_priv(dev);

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const void __iomem *io = skge->hw->regs;

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const void __iomem *io = skge->hw->regs;

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regs->version = 1;

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regs->version = 1;

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memset(p, 0, regs->len);

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memset(p, 0, regs->len);

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memcpy_fromio(p, io, B3_RAM_ADDR);

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memcpy_fromio(p, io, B3_RAM_ADDR);

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memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,

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memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,

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regs->len - B3_RI_WTO_R1);

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regs->len - B3_RI_WTO_R1);

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}

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}

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/* Wake on Lan only supported on Yukon chips with rev 1 or above */

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/* Wake on Lan only supported on Yukon chips with rev 1 or above */

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static int wol_supported(const struct skge_hw *hw)

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static int wol_supported(const struct skge_hw *hw)

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{

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{

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return !((hw->chip_id == CHIP_ID_GENESIS ||

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return !((hw->chip_id == CHIP_ID_GENESIS ||

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(hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)));

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(hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)));

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}

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}

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static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)

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static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)

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{

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{

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struct skge_port *skge = netdev_priv(dev);

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struct skge_port *skge = netdev_priv(dev);

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143

wol->supported = wol_supported(skge->hw) ? WAKE_MAGIC : 0;

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wol->supported = wol_supported(skge->hw) ? WAKE_MAGIC : 0;

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wol->wolopts = skge->wol ? WAKE_MAGIC : 0;

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wol->wolopts = skge->wol ? WAKE_MAGIC : 0;

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}

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}

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static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)

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static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)

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{

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{

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struct skge_port *skge = netdev_priv(dev);

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struct skge_port *skge = netdev_priv(dev);

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struct skge_hw *hw = skge->hw;

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struct skge_hw *hw = skge->hw;

151

152

if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)

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if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)

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return -EOPNOTSUPP;

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return -EOPNOTSUPP;

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155

if (wol->wolopts == WAKE_MAGIC && !wol_supported(hw))

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if (wol->wolopts == WAKE_MAGIC && !wol_supported(hw))

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return -EOPNOTSUPP;

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return -EOPNOTSUPP;

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158

skge->wol = wol->wolopts == WAKE_MAGIC;

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skge->wol = wol->wolopts == WAKE_MAGIC;

159

160

if (skge->wol) {

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if (skge->wol) {

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memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);

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memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);

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skge_write16(hw, WOL_CTRL_STAT,

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skge_write16(hw, WOL_CTRL_STAT,

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WOL_CTL_ENA_PME_ON_MAGIC_PKT |

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WOL_CTL_ENA_PME_ON_MAGIC_PKT |

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WOL_CTL_ENA_MAGIC_PKT_UNIT);

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WOL_CTL_ENA_MAGIC_PKT_UNIT);

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} else

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} else

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skge_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);

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skge_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);

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return 0;

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return 0;

170

}

170

}

171

172

/* Determine supported/advertised modes based on hardware.

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/* Determine supported/advertised modes based on hardware.

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* Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx

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* Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx

174

*/

174

*/

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static u32 skge_supported_modes(const struct skge_hw *hw)

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static u32 skge_supported_modes(const struct skge_hw *hw)

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{

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{

177

u32 supported;

177

u32 supported;

178

179

if (hw->copper) {

179

if (hw->copper) {

180

supported = SUPPORTED_10baseT_Half

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supported = SUPPORTED_10baseT_Half

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| SUPPORTED_10baseT_Full

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| SUPPORTED_10baseT_Full

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| SUPPORTED_100baseT_Half

182

| SUPPORTED_100baseT_Half

183

| SUPPORTED_100baseT_Full

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| SUPPORTED_100baseT_Full

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| SUPPORTED_1000baseT_Half

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| SUPPORTED_1000baseT_Half

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| SUPPORTED_1000baseT_Full

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| SUPPORTED_1000baseT_Full

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| SUPPORTED_Autoneg| SUPPORTED_TP;

186

| SUPPORTED_Autoneg| SUPPORTED_TP;

187

188

if (hw->chip_id == CHIP_ID_GENESIS)

188

if (hw->chip_id == CHIP_ID_GENESIS)

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supported &= ~(SUPPORTED_10baseT_Half

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supported &= ~(SUPPORTED_10baseT_Half

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| SUPPORTED_10baseT_Full

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| SUPPORTED_10baseT_Full

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| SUPPORTED_100baseT_Half

191

| SUPPORTED_100baseT_Half

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| SUPPORTED_100baseT_Full);

192

| SUPPORTED_100baseT_Full);

193

194

else if (hw->chip_id == CHIP_ID_YUKON)

194

else if (hw->chip_id == CHIP_ID_YUKON)

195

supported &= ~SUPPORTED_1000baseT_Half;

195

supported &= ~SUPPORTED_1000baseT_Half;

196

} else

196

} else

197

supported = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE

197

supported = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE

198

| SUPPORTED_Autoneg;

198

| SUPPORTED_Autoneg;

199

200

return supported;

200

return supported;

201

}

201

}

202

203

static int skge_get_settings(struct net_device *dev,

203

static int skge_get_settings(struct net_device *dev,

204

struct ethtool_cmd *ecmd)

204

struct ethtool_cmd *ecmd)

205

{

205

{

206

struct skge_port *skge = netdev_priv(dev);

206

struct skge_port *skge = netdev_priv(dev);

207

struct skge_hw *hw = skge->hw;

207

struct skge_hw *hw = skge->hw;

208

209

ecmd->transceiver = XCVR_INTERNAL;

209

ecmd->transceiver = XCVR_INTERNAL;

210

ecmd->supported = skge_supported_modes(hw);

210

ecmd->supported = skge_supported_modes(hw);

211

212

if (hw->copper) {

212

if (hw->copper) {

213

ecmd->port = PORT_TP;

213

ecmd->port = PORT_TP;

214

ecmd->phy_address = hw->phy_addr;

214

ecmd->phy_address = hw->phy_addr;

215

} else

215

} else

216

ecmd->port = PORT_FIBRE;

216

ecmd->port = PORT_FIBRE;

217

218

ecmd->advertising = skge->advertising;

218

ecmd->advertising = skge->advertising;

219

ecmd->autoneg = skge->autoneg;

219

ecmd->autoneg = skge->autoneg;

220

ecmd->speed = skge->speed;

220

ecmd->speed = skge->speed;

221

ecmd->duplex = skge->duplex;

221

ecmd->duplex = skge->duplex;

222

return 0;

222

return 0;

223

}

223

}

224

225

static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)

225

static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)

226

{

226

{

227

struct skge_port *skge = netdev_priv(dev);

227

struct skge_port *skge = netdev_priv(dev);

228

const struct skge_hw *hw = skge->hw;

228

const struct skge_hw *hw = skge->hw;

229

u32 supported = skge_supported_modes(hw);

229

u32 supported = skge_supported_modes(hw);

230

231

if (ecmd->autoneg == AUTONEG_ENABLE) {

231

if (ecmd->autoneg == AUTONEG_ENABLE) {

232

ecmd->advertising = supported;

232

ecmd->advertising = supported;

233

skge->duplex = -1;

233

skge->duplex = -1;

234

skge->speed = -1;

234

skge->speed = -1;

235

} else {

235

} else {

236

u32 setting;

236

u32 setting;

237

238

switch (ecmd->speed) {

238

switch (ecmd->speed) {

239

case SPEED_1000:

239

case SPEED_1000:

240

if (ecmd->duplex == DUPLEX_FULL)

240

if (ecmd->duplex == DUPLEX_FULL)

241

setting = SUPPORTED_1000baseT_Full;

241

setting = SUPPORTED_1000baseT_Full;

242

else if (ecmd->duplex == DUPLEX_HALF)

242

else if (ecmd->duplex == DUPLEX_HALF)

243

setting = SUPPORTED_1000baseT_Half;

243

setting = SUPPORTED_1000baseT_Half;

244

else

244

else

245

return -EINVAL;

245

return -EINVAL;

246

break;

246

break;

247

case SPEED_100:

247

case SPEED_100:

248

if (ecmd->duplex == DUPLEX_FULL)

248

if (ecmd->duplex == DUPLEX_FULL)

249

setting = SUPPORTED_100baseT_Full;

249

setting = SUPPORTED_100baseT_Full;

250

else if (ecmd->duplex == DUPLEX_HALF)

250

else if (ecmd->duplex == DUPLEX_HALF)

251

setting = SUPPORTED_100baseT_Half;

251

setting = SUPPORTED_100baseT_Half;

252

else

252

else

253

return -EINVAL;

253

return -EINVAL;

254

break;

254

break;

255

256

case SPEED_10:

256

case SPEED_10:

257

if (ecmd->duplex == DUPLEX_FULL)

257

if (ecmd->duplex == DUPLEX_FULL)

258

setting = SUPPORTED_10baseT_Full;

258

setting = SUPPORTED_10baseT_Full;

259

else if (ecmd->duplex == DUPLEX_HALF)

259

else if (ecmd->duplex == DUPLEX_HALF)

260

setting = SUPPORTED_10baseT_Half;

260

setting = SUPPORTED_10baseT_Half;

261

else

261

else

262

return -EINVAL;

262

return -EINVAL;

263

break;

263

break;

264

default:

264

default:

265

return -EINVAL;

265

return -EINVAL;

266

}

266

}

267

268

if ((setting & supported) == 0)

268

if ((setting & supported) == 0)

269

return -EINVAL;

269

return -EINVAL;

270

271

skge->speed = ecmd->speed;

271

skge->speed = ecmd->speed;

272

skge->duplex = ecmd->duplex;

272

skge->duplex = ecmd->duplex;

273

}

273

}

274

275

skge->autoneg = ecmd->autoneg;

275

skge->autoneg = ecmd->autoneg;

276

skge->advertising = ecmd->advertising;

276

skge->advertising = ecmd->advertising;

277

278

if (netif_running(dev))

278

if (netif_running(dev))

279

skge_phy_reset(skge);

279

skge_phy_reset(skge);

280

281

return (0);

281

return (0);

282

}

282

}

283

284

static void skge_get_drvinfo(struct net_device *dev,

284

static void skge_get_drvinfo(struct net_device *dev,

285

struct ethtool_drvinfo *info)

285

struct ethtool_drvinfo *info)

286

{

286

{

287

struct skge_port *skge = netdev_priv(dev);

287

struct skge_port *skge = netdev_priv(dev);

288

289

strcpy(info->driver, DRV_NAME);

289

strcpy(info->driver, DRV_NAME);

290

strcpy(info->version, DRV_VERSION);

290

strcpy(info->version, DRV_VERSION);

291

strcpy(info->fw_version, "N/A");

291

strcpy(info->fw_version, "N/A");

292

strcpy(info->bus_info, pci_name(skge->hw->pdev));

292

strcpy(info->bus_info, pci_name(skge->hw->pdev));

293

}

293

}

294

295

static const struct skge_stat {

295

static const struct skge_stat {

296

char name[ETH_GSTRING_LEN];

296

char name[ETH_GSTRING_LEN];

297

u16 xmac_offset;

297

u16 xmac_offset;

298

u16 gma_offset;

298

u16 gma_offset;

299

} skge_stats[] = {

299

} skge_stats[] = {

300

{ "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },

300

{ "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },

301

{ "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },

301

{ "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },

302

303

{ "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },

303

{ "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },

304

{ "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },

304

{ "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },

305

{ "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },

305

{ "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },

306

{ "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },

306

{ "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },

307

{ "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },

307

{ "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },

308

{ "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },

308

{ "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },

309

{ "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },

309

{ "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },

310

{ "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },

310

{ "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },

311

312

{ "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },

312

{ "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },

313

{ "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },

313

{ "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },

314

{ "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },

314

{ "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },

315

{ "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },

315

{ "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },

316

{ "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },

316

{ "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },

317

{ "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },

317

{ "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },

318

319

{ "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },

319

{ "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },

320

{ "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },

320

{ "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },

321

{ "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },

321

{ "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },

322

{ "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },

322

{ "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },

323

{ "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },

323

{ "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },

324

};

324

};

325

326

static int skge_get_stats_count(struct net_device *dev)

326

static int skge_get_stats_count(struct net_device *dev)

327

{

327

{

328

return ARRAY_SIZE(skge_stats);

328

return ARRAY_SIZE(skge_stats);

329

}

329

}

330

331

static void skge_get_ethtool_stats(struct net_device *dev,

331

static void skge_get_ethtool_stats(struct net_device *dev,

332

struct ethtool_stats *stats, u64 *data)

332

struct ethtool_stats *stats, u64 *data)

333

{

333

{

334

struct skge_port *skge = netdev_priv(dev);

334

struct skge_port *skge = netdev_priv(dev);

335

336

if (skge->hw->chip_id == CHIP_ID_GENESIS)

336

if (skge->hw->chip_id == CHIP_ID_GENESIS)

337

genesis_get_stats(skge, data);

337

genesis_get_stats(skge, data);

338

else

338

else

339

yukon_get_stats(skge, data);

339

yukon_get_stats(skge, data);

340

}

340

}

341

342

/* Use hardware MIB variables for critical path statistics and

342

/* Use hardware MIB variables for critical path statistics and

343

* transmit feedback not reported at interrupt.

343

* transmit feedback not reported at interrupt.

344

* Other errors are accounted for in interrupt handler.

344

* Other errors are accounted for in interrupt handler.

345

*/

345

*/

346

static struct net_device_stats *skge_get_stats(struct net_device *dev)

346

static struct net_device_stats *skge_get_stats(struct net_device *dev)

347

{

347

{

348

struct skge_port *skge = netdev_priv(dev);

348

struct skge_port *skge = netdev_priv(dev);

349

u64 data[ARRAY_SIZE(skge_stats)];

349

u64 data[ARRAY_SIZE(skge_stats)];

350

351

if (skge->hw->chip_id == CHIP_ID_GENESIS)

351

if (skge->hw->chip_id == CHIP_ID_GENESIS)

352

genesis_get_stats(skge, data);

352

genesis_get_stats(skge, data);

353

else

353

else

354

yukon_get_stats(skge, data);

354

yukon_get_stats(skge, data);

355

356

skge->net_stats.tx_bytes = data[0];

356

skge->net_stats.tx_bytes = data[0];

357

skge->net_stats.rx_bytes = data[1];

357

skge->net_stats.rx_bytes = data[1];

358

skge->net_stats.tx_packets = data[2] + data[4] + data[6];

358

skge->net_stats.tx_packets = data[2] + data[4] + data[6];

359

skge->net_stats.rx_packets = data[3] + data[5] + data[7];

359

skge->net_stats.rx_packets = data[3] + data[5] + data[7];

360

skge->net_stats.multicast = data[5] + data[7];

360

skge->net_stats.multicast = data[5] + data[7];

361

skge->net_stats.collisions = data[10];

361

skge->net_stats.collisions = data[10];

362

skge->net_stats.tx_aborted_errors = data[12];

362

skge->net_stats.tx_aborted_errors = data[12];

363

364

return &skge->net_stats;

364

return &skge->net_stats;

365

}

365

}

366

367

static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)

367

static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)

368

{

368

{

369

int i;

369

int i;

370

371

switch (stringset) {

371

switch (stringset) {

372

case ETH_SS_STATS:

372

case ETH_SS_STATS:

373

for (i = 0; i < ARRAY_SIZE(skge_stats); i++)

373

for (i = 0; i < ARRAY_SIZE(skge_stats); i++)

374

memcpy(data + i * ETH_GSTRING_LEN,

374

memcpy(data + i * ETH_GSTRING_LEN,

375

skge_stats[i].name, ETH_GSTRING_LEN);

375

skge_stats[i].name, ETH_GSTRING_LEN);

376

break;

376

break;

377

}

377

}

378

}

378

}

379

380

static void skge_get_ring_param(struct net_device *dev,

380

static void skge_get_ring_param(struct net_device *dev,

381

struct ethtool_ringparam *p)

381

struct ethtool_ringparam *p)

382

{

382

{

383

struct skge_port *skge = netdev_priv(dev);

383

struct skge_port *skge = netdev_priv(dev);

384

385

p->rx_max_pending = MAX_RX_RING_SIZE;

385

p->rx_max_pending = MAX_RX_RING_SIZE;

386

p->tx_max_pending = MAX_TX_RING_SIZE;

386

p->tx_max_pending = MAX_TX_RING_SIZE;

387

p->rx_mini_max_pending = 0;

387

p->rx_mini_max_pending = 0;

388

p->rx_jumbo_max_pending = 0;

388

p->rx_jumbo_max_pending = 0;

389

390

p->rx_pending = skge->rx_ring.count;

390

p->rx_pending = skge->rx_ring.count;

391

p->tx_pending = skge->tx_ring.count;

391

p->tx_pending = skge->tx_ring.count;

392

p->rx_mini_pending = 0;

392

p->rx_mini_pending = 0;

393

p->rx_jumbo_pending = 0;

393

p->rx_jumbo_pending = 0;

394

}

394

}

395

396

static int skge_set_ring_param(struct net_device *dev,

396

static int skge_set_ring_param(struct net_device *dev,

397

struct ethtool_ringparam *p)

397

struct ethtool_ringparam *p)

398

{

398

{

399

struct skge_port *skge = netdev_priv(dev);

399

struct skge_port *skge = netdev_priv(dev);

400

int err;

400

int err;

401

402

if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||

402

if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||

403

p->tx_pending == 0 || p->tx_pending > MAX_TX_RING_SIZE)

403

p->tx_pending == 0 || p->tx_pending > MAX_TX_RING_SIZE)

404

return -EINVAL;

404

return -EINVAL;

405

406

skge->rx_ring.count = p->rx_pending;

406

skge->rx_ring.count = p->rx_pending;

407

skge->tx_ring.count = p->tx_pending;

407

skge->tx_ring.count = p->tx_pending;

408

409

if (netif_running(dev)) {

409

if (netif_running(dev)) {

410

skge_down(dev);

410

skge_down(dev);

411

err = skge_up(dev);

411

err = skge_up(dev);

412

if (err)

412

if (err)

413

dev_close(dev);

413

dev_close(dev);

414

}

414

}

415

416

return 0;

416

return 0;

417

}

417

}

418

419

static u32 skge_get_msglevel(struct net_device *netdev)

419

static u32 skge_get_msglevel(struct net_device *netdev)

420

{

420

{

421

struct skge_port *skge = netdev_priv(netdev);

421

struct skge_port *skge = netdev_priv(netdev);

422

return skge->msg_enable;

422

return skge->msg_enable;

423

}

423

}

424

425

static void skge_set_msglevel(struct net_device *netdev, u32 value)

425

static void skge_set_msglevel(struct net_device *netdev, u32 value)

426

{

426

{

427

struct skge_port *skge = netdev_priv(netdev);

427

struct skge_port *skge = netdev_priv(netdev);

428

skge->msg_enable = value;

428

skge->msg_enable = value;

429

}

429

}

430

431

static int skge_nway_reset(struct net_device *dev)

431

static int skge_nway_reset(struct net_device *dev)

432

{

432

{

433

struct skge_port *skge = netdev_priv(dev);

433

struct skge_port *skge = netdev_priv(dev);

434

435

if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))

435

if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))

436

return -EINVAL;

436

return -EINVAL;

437

438

skge_phy_reset(skge);

438

skge_phy_reset(skge);

439

return 0;

439

return 0;

440

}

440

}

441

442

static int skge_set_sg(struct net_device *dev, u32 data)

442

static int skge_set_sg(struct net_device *dev, u32 data)

443

{

443

{

444

struct skge_port *skge = netdev_priv(dev);

444

struct skge_port *skge = netdev_priv(dev);

445

struct skge_hw *hw = skge->hw;

445

struct skge_hw *hw = skge->hw;

446

447

if (hw->chip_id == CHIP_ID_GENESIS && data)

447

if (hw->chip_id == CHIP_ID_GENESIS && data)

448

return -EOPNOTSUPP;

448

return -EOPNOTSUPP;

449

return ethtool_op_set_sg(dev, data);

449

return ethtool_op_set_sg(dev, data);

450

}

450

}

451

452

static int skge_set_tx_csum(struct net_device *dev, u32 data)

452

static int skge_set_tx_csum(struct net_device *dev, u32 data)

453

{

453

{

454

struct skge_port *skge = netdev_priv(dev);

454

struct skge_port *skge = netdev_priv(dev);

455

struct skge_hw *hw = skge->hw;

455

struct skge_hw *hw = skge->hw;

456

457

if (hw->chip_id == CHIP_ID_GENESIS && data)

457

if (hw->chip_id == CHIP_ID_GENESIS && data)

458

return -EOPNOTSUPP;

458

return -EOPNOTSUPP;

459

460

return ethtool_op_set_tx_csum(dev, data);

460

return ethtool_op_set_tx_csum(dev, data);

461

}

461

}

462

463

static u32 skge_get_rx_csum(struct net_device *dev)

463

static u32 skge_get_rx_csum(struct net_device *dev)

464

{

464

{

465

struct skge_port *skge = netdev_priv(dev);

465

struct skge_port *skge = netdev_priv(dev);

466

467

return skge->rx_csum;

467

return skge->rx_csum;

468

}

468

}

469

470

/* Only Yukon supports checksum offload. */

470

/* Only Yukon supports checksum offload. */

471

static int skge_set_rx_csum(struct net_device *dev, u32 data)

471

static int skge_set_rx_csum(struct net_device *dev, u32 data)

472

{

472

{

473

struct skge_port *skge = netdev_priv(dev);

473

struct skge_port *skge = netdev_priv(dev);

474

475

if (skge->hw->chip_id == CHIP_ID_GENESIS && data)

475

if (skge->hw->chip_id == CHIP_ID_GENESIS && data)

476

return -EOPNOTSUPP;

476

return -EOPNOTSUPP;

477

478

skge->rx_csum = data;

478

skge->rx_csum = data;

479

return 0;

479

return 0;

480

}

480

}

481

482

static void skge_get_pauseparam(struct net_device *dev,

482

static void skge_get_pauseparam(struct net_device *dev,

483

struct ethtool_pauseparam *ecmd)

483

struct ethtool_pauseparam *ecmd)

484

{

484

{

485

struct skge_port *skge = netdev_priv(dev);

485

struct skge_port *skge = netdev_priv(dev);

486

487

ecmd->tx_pause = (skge->flow_control == FLOW_MODE_LOC_SEND)

487

ecmd->tx_pause = (skge->flow_control == FLOW_MODE_LOC_SEND)

488

|| (skge->flow_control == FLOW_MODE_SYMMETRIC);

488

|| (skge->flow_control == FLOW_MODE_SYMMETRIC);

489

ecmd->rx_pause = (skge->flow_control == FLOW_MODE_REM_SEND)

489

ecmd->rx_pause = (skge->flow_control == FLOW_MODE_REM_SEND)

490

|| (skge->flow_control == FLOW_MODE_SYMMETRIC);

490

|| (skge->flow_control == FLOW_MODE_SYMMETRIC);

491

492

ecmd->autoneg = skge->autoneg;

492

ecmd->autoneg = skge->autoneg;

493

}

493

}

494

495

static int skge_set_pauseparam(struct net_device *dev,

495

static int skge_set_pauseparam(struct net_device *dev,

496

struct ethtool_pauseparam *ecmd)

496

struct ethtool_pauseparam *ecmd)

497

{

497

{

498

struct skge_port *skge = netdev_priv(dev);

498

struct skge_port *skge = netdev_priv(dev);

499

500

skge->autoneg = ecmd->autoneg;

500

skge->autoneg = ecmd->autoneg;

501

if (ecmd->rx_pause && ecmd->tx_pause)

501

if (ecmd->rx_pause && ecmd->tx_pause)

502

skge->flow_control = FLOW_MODE_SYMMETRIC;

502

skge->flow_control = FLOW_MODE_SYMMETRIC;

503

else if (ecmd->rx_pause && !ecmd->tx_pause)

503

else if (ecmd->rx_pause && !ecmd->tx_pause)

504

skge->flow_control = FLOW_MODE_REM_SEND;

504

skge->flow_control = FLOW_MODE_REM_SEND;

505

else if (!ecmd->rx_pause && ecmd->tx_pause)

505

else if (!ecmd->rx_pause && ecmd->tx_pause)

506

skge->flow_control = FLOW_MODE_LOC_SEND;

506

skge->flow_control = FLOW_MODE_LOC_SEND;

507

else

507

else

508

skge->flow_control = FLOW_MODE_NONE;

508

skge->flow_control = FLOW_MODE_NONE;

509

510

if (netif_running(dev))

510

if (netif_running(dev))

511

skge_phy_reset(skge);

511

skge_phy_reset(skge);

512

return 0;

512

return 0;

513

}

513

}

514

515

/* Chip internal frequency for clock calculations */

515

/* Chip internal frequency for clock calculations */

516

static inline u32 hwkhz(const struct skge_hw *hw)

516

static inline u32 hwkhz(const struct skge_hw *hw)

517

{

517

{

518

if (hw->chip_id == CHIP_ID_GENESIS)

518

if (hw->chip_id == CHIP_ID_GENESIS)

519

return 53215; /* or: 53.125 MHz */

519

return 53215; /* or: 53.125 MHz */

520

else

520

else

521

return 78215; /* or: 78.125 MHz */

521

return 78215; /* or: 78.125 MHz */

522

}

522

}

523

524

/* Chip HZ to microseconds */

524

/* Chip HZ to microseconds */

525

static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)

525

static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)

526

{

526

{

527

return (ticks * 1000) / hwkhz(hw);

527

return (ticks * 1000) / hwkhz(hw);

528

}

528

}

529

530

/* Microseconds to chip HZ */

530

/* Microseconds to chip HZ */

531

static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)

531

static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)

532

{

532

{

533

return hwkhz(hw) * usec / 1000;

533

return hwkhz(hw) * usec / 1000;

534

}

534

}

535

536

static int skge_get_coalesce(struct net_device *dev,

536

static int skge_get_coalesce(struct net_device *dev,

537

struct ethtool_coalesce *ecmd)

537

struct ethtool_coalesce *ecmd)

538

{

538

{

539

struct skge_port *skge = netdev_priv(dev);

539

struct skge_port *skge = netdev_priv(dev);

540

struct skge_hw *hw = skge->hw;

540

struct skge_hw *hw = skge->hw;

541

int port = skge->port;

541

int port = skge->port;

542

543

ecmd->rx_coalesce_usecs = 0;

543

ecmd->rx_coalesce_usecs = 0;

544

ecmd->tx_coalesce_usecs = 0;

544

ecmd->tx_coalesce_usecs = 0;

545

546

if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {

546

if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {

547

u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));

547

u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));

548

u32 msk = skge_read32(hw, B2_IRQM_MSK);

548

u32 msk = skge_read32(hw, B2_IRQM_MSK);

549

550

if (msk & rxirqmask[port])

550

if (msk & rxirqmask[port])

551

ecmd->rx_coalesce_usecs = delay;

551

ecmd->rx_coalesce_usecs = delay;

552

if (msk & txirqmask[port])

552

if (msk & txirqmask[port])

553

ecmd->tx_coalesce_usecs = delay;

553

ecmd->tx_coalesce_usecs = delay;

554

}

554

}

555

556

return 0;

556

return 0;

557

}

557

}

558

559

/* Note: interrupt timer is per board, but can turn on/off per port */

559

/* Note: interrupt timer is per board, but can turn on/off per port */

560

static int skge_set_coalesce(struct net_device *dev,

560

static int skge_set_coalesce(struct net_device *dev,

561

struct ethtool_coalesce *ecmd)

561

struct ethtool_coalesce *ecmd)

562

{

562

{

563

struct skge_port *skge = netdev_priv(dev);

563

struct skge_port *skge = netdev_priv(dev);

564

struct skge_hw *hw = skge->hw;

564

struct skge_hw *hw = skge->hw;

565

int port = skge->port;

565

int port = skge->port;

566

u32 msk = skge_read32(hw, B2_IRQM_MSK);

566

u32 msk = skge_read32(hw, B2_IRQM_MSK);

567

u32 delay = 25;

567

u32 delay = 25;

568

569

if (ecmd->rx_coalesce_usecs == 0)

569

if (ecmd->rx_coalesce_usecs == 0)

570

msk &= ~rxirqmask[port];

570

msk &= ~rxirqmask[port];

571

else if (ecmd->rx_coalesce_usecs < 25 ||

571

else if (ecmd->rx_coalesce_usecs < 25 ||

572

ecmd->rx_coalesce_usecs > 33333)

572

ecmd->rx_coalesce_usecs > 33333)

573

return -EINVAL;

573

return -EINVAL;

574

else {

574

else {

575

msk |= rxirqmask[port];

575

msk |= rxirqmask[port];

576

delay = ecmd->rx_coalesce_usecs;

576

delay = ecmd->rx_coalesce_usecs;

577

}

577

}

578

579

if (ecmd->tx_coalesce_usecs == 0)

579

if (ecmd->tx_coalesce_usecs == 0)

580

msk &= ~txirqmask[port];

580

msk &= ~txirqmask[port];

581

else if (ecmd->tx_coalesce_usecs < 25 ||

581

else if (ecmd->tx_coalesce_usecs < 25 ||

582

ecmd->tx_coalesce_usecs > 33333)

582

ecmd->tx_coalesce_usecs > 33333)

583

return -EINVAL;

583

return -EINVAL;

584

else {

584

else {

585

msk |= txirqmask[port];

585

msk |= txirqmask[port];

586

delay = min(delay, ecmd->rx_coalesce_usecs);

586

delay = min(delay, ecmd->rx_coalesce_usecs);

587

}

587

}

588

589

skge_write32(hw, B2_IRQM_MSK, msk);

589

skge_write32(hw, B2_IRQM_MSK, msk);

590

if (msk == 0)

590

if (msk == 0)

591

skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);

591

skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);

592

else {

592

else {

593

skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));

593

skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));

594

skge_write32(hw, B2_IRQM_CTRL, TIM_START);

594

skge_write32(hw, B2_IRQM_CTRL, TIM_START);

595

}

595

}

596

return 0;

596

return 0;

597

}

597

}

598

599

enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };

599

enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };

600

static void skge_led(struct skge_port *skge, enum led_mode mode)

600

static void skge_led(struct skge_port *skge, enum led_mode mode)

601

{

601

{

602

struct skge_hw *hw = skge->hw;

602

struct skge_hw *hw = skge->hw;

603

int port = skge->port;

603

int port = skge->port;

604

605

spin_lock_bh(&hw->phy_lock);

605

spin_lock_bh(&hw->phy_lock);

606

if (hw->chip_id == CHIP_ID_GENESIS) {

606

if (hw->chip_id == CHIP_ID_GENESIS) {

607

switch (mode) {

607

switch (mode) {

608

case LED_MODE_OFF:

608

case LED_MODE_OFF:

609

xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);

609

xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);

610

skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);

610

skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);

611

skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);

611

skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);

612

skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);

612

skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);

613

break;

613

break;

614

615

case LED_MODE_ON:

615

case LED_MODE_ON:

616

skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);

616

skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);

617

skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);

617

skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);

618

619

skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);

619

skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);

620

skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);

620

skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);

621

622

break;

622

break;

623

624

case LED_MODE_TST:

624

case LED_MODE_TST:

625

skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);

625

skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);

626

skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);

626

skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);

627

skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);

627

skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);

628

629

xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);

629

xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);

630

break;

630

break;

631

}

631

}

632

} else {

632

} else {

633

switch (mode) {

633

switch (mode) {

634

case LED_MODE_OFF:

634

case LED_MODE_OFF:

635

gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);

635

gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);

636

gm_phy_write(hw, port, PHY_MARV_LED_OVER,

636

gm_phy_write(hw, port, PHY_MARV_LED_OVER,

637

PHY_M_LED_MO_DUP(MO_LED_OFF) |

637

PHY_M_LED_MO_DUP(MO_LED_OFF) |

638

PHY_M_LED_MO_10(MO_LED_OFF) |

638

PHY_M_LED_MO_10(MO_LED_OFF) |

639

PHY_M_LED_MO_100(MO_LED_OFF) |

639

PHY_M_LED_MO_100(MO_LED_OFF) |

640

PHY_M_LED_MO_1000(MO_LED_OFF) |

640

PHY_M_LED_MO_1000(MO_LED_OFF) |

641

PHY_M_LED_MO_RX(MO_LED_OFF));

641

PHY_M_LED_MO_RX(MO_LED_OFF));

642

break;

642

break;

643

case LED_MODE_ON:

643

case LED_MODE_ON:

644

gm_phy_write(hw, port, PHY_MARV_LED_CTRL,

644

gm_phy_write(hw, port, PHY_MARV_LED_CTRL,

645

PHY_M_LED_PULS_DUR(PULS_170MS) |

645

PHY_M_LED_PULS_DUR(PULS_170MS) |

646

PHY_M_LED_BLINK_RT(BLINK_84MS) |

646

PHY_M_LED_BLINK_RT(BLINK_84MS) |

647

PHY_M_LEDC_TX_CTRL |

647

PHY_M_LEDC_TX_CTRL |

648

PHY_M_LEDC_DP_CTRL);

648

PHY_M_LEDC_DP_CTRL);

649

650

gm_phy_write(hw, port, PHY_MARV_LED_OVER,

650

gm_phy_write(hw, port, PHY_MARV_LED_OVER,

651

PHY_M_LED_MO_RX(MO_LED_OFF) |

651

PHY_M_LED_MO_RX(MO_LED_OFF) |

652

(skge->speed == SPEED_100 ?

652

(skge->speed == SPEED_100 ?

653

PHY_M_LED_MO_100(MO_LED_ON) : 0));

653

PHY_M_LED_MO_100(MO_LED_ON) : 0));

654

break;

654

break;

655

case LED_MODE_TST:

655

case LED_MODE_TST:

656

gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);

656

gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);

657

gm_phy_write(hw, port, PHY_MARV_LED_OVER,

657

gm_phy_write(hw, port, PHY_MARV_LED_OVER,

658

PHY_M_LED_MO_DUP(MO_LED_ON) |

658

PHY_M_LED_MO_DUP(MO_LED_ON) |

659

PHY_M_LED_MO_10(MO_LED_ON) |

659

PHY_M_LED_MO_10(MO_LED_ON) |

660

PHY_M_LED_MO_100(MO_LED_ON) |

660

PHY_M_LED_MO_100(MO_LED_ON) |

661

PHY_M_LED_MO_1000(MO_LED_ON) |

661

PHY_M_LED_MO_1000(MO_LED_ON) |

662

PHY_M_LED_MO_RX(MO_LED_ON));

662

PHY_M_LED_MO_RX(MO_LED_ON));

663

}

663

}

664

}

664

}

665

spin_unlock_bh(&hw->phy_lock);

665

spin_unlock_bh(&hw->phy_lock);

666

}

666

}

667

668

/* blink LED's for finding board */

668

/* blink LED's for finding board */

669

static int skge_phys_id(struct net_device *dev, u32 data)

669

static int skge_phys_id(struct net_device *dev, u32 data)

670

{

670

{

671

struct skge_port *skge = netdev_priv(dev);

671

struct skge_port *skge = netdev_priv(dev);

672

unsigned long ms;

672

unsigned long ms;

673

enum led_mode mode = LED_MODE_TST;

673

enum led_mode mode = LED_MODE_TST;

674

675

if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))

675

if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))

676

ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT / HZ) * 1000;

676

ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT / HZ) * 1000;

677

else

677

else

678

ms = data * 1000;

678

ms = data * 1000;

679

680

while (ms > 0) {

680

while (ms > 0) {

681

skge_led(skge, mode);

681

skge_led(skge, mode);

682

mode ^= LED_MODE_TST;

682

mode ^= LED_MODE_TST;

683

684

if (msleep_interruptible(BLINK_MS))

684

if (msleep_interruptible(BLINK_MS))

685

break;

685

break;

686

ms -= BLINK_MS;

686

ms -= BLINK_MS;

687

}

687

}

688

689

/* back to regular LED state */

689

/* back to regular LED state */

690

skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);

690

skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);

691

692

return 0;

692

return 0;

693

}

693

}

694

695

static struct ethtool_ops skge_ethtool_ops = {

695

static struct ethtool_ops skge_ethtool_ops = {

696

.get_settings = skge_get_settings,

696

.get_settings = skge_get_settings,

697

.set_settings = skge_set_settings,

697

.set_settings = skge_set_settings,

698

.get_drvinfo = skge_get_drvinfo,

698

.get_drvinfo = skge_get_drvinfo,

699

.get_regs_len = skge_get_regs_len,

699

.get_regs_len = skge_get_regs_len,

700

.get_regs = skge_get_regs,

700

.get_regs = skge_get_regs,

701

.get_wol = skge_get_wol,

701

.get_wol = skge_get_wol,

702

.set_wol = skge_set_wol,

702

.set_wol = skge_set_wol,

703

.get_msglevel = skge_get_msglevel,

703

.get_msglevel = skge_get_msglevel,

704

.set_msglevel = skge_set_msglevel,

704

.set_msglevel = skge_set_msglevel,

705

.nway_reset = skge_nway_reset,

705

.nway_reset = skge_nway_reset,

706

.get_link = ethtool_op_get_link,

706

.get_link = ethtool_op_get_link,

707

.get_ringparam = skge_get_ring_param,

707

.get_ringparam = skge_get_ring_param,

708

.set_ringparam = skge_set_ring_param,

708

.set_ringparam = skge_set_ring_param,

709

.get_pauseparam = skge_get_pauseparam,

709

.get_pauseparam = skge_get_pauseparam,

710

.set_pauseparam = skge_set_pauseparam,

710

.set_pauseparam = skge_set_pauseparam,

711

.get_coalesce = skge_get_coalesce,

711

.get_coalesce = skge_get_coalesce,

712

.set_coalesce = skge_set_coalesce,

712

.set_coalesce = skge_set_coalesce,

713

.get_sg = ethtool_op_get_sg,

713

.get_sg = ethtool_op_get_sg,

714

.set_sg = skge_set_sg,

714

.set_sg = skge_set_sg,

715

.get_tx_csum = ethtool_op_get_tx_csum,

715

.get_tx_csum = ethtool_op_get_tx_csum,

716

.set_tx_csum = skge_set_tx_csum,

716

.set_tx_csum = skge_set_tx_csum,

717

.get_rx_csum = skge_get_rx_csum,

717

.get_rx_csum = skge_get_rx_csum,

718

.set_rx_csum = skge_set_rx_csum,

718

.set_rx_csum = skge_set_rx_csum,

719

.get_strings = skge_get_strings,

719

.get_strings = skge_get_strings,

720

.phys_id = skge_phys_id,

720

.phys_id = skge_phys_id,

721

.get_stats_count = skge_get_stats_count,

721

.get_stats_count = skge_get_stats_count,

722

.get_ethtool_stats = skge_get_ethtool_stats,

722

.get_ethtool_stats = skge_get_ethtool_stats,

723

.get_perm_addr = ethtool_op_get_perm_addr,

723

.get_perm_addr = ethtool_op_get_perm_addr,

724

};

724

};

725

726

/*

726

/*

727

* Allocate ring elements and chain them together

727

* Allocate ring elements and chain them together

728

* One-to-one association of board descriptors with ring elements

728

* One-to-one association of board descriptors with ring elements

729

*/

729

*/

730

static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base)

730

static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base)

731

{

731

{

732

struct skge_tx_desc *d;

732

struct skge_tx_desc *d;

733

struct skge_element *e;

733

struct skge_element *e;

734

int i;

734

int i;

735

736

ring->start = kmalloc(sizeof(*e)*ring->count, GFP_KERNEL);

736

ring->start = kmalloc(sizeof(*e)*ring->count, GFP_KERNEL);

737

if (!ring->start)

737

if (!ring->start)

738

return -ENOMEM;

738

return -ENOMEM;

739

740

for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {

740

for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {

741

e->desc = d;

741

e->desc = d;

742

e->skb = NULL;

742

e->skb = NULL;

743

if (i == ring->count - 1) {

743

if (i == ring->count - 1) {

744

e->next = ring->start;

744

e->next = ring->start;

745

d->next_offset = base;

745

d->next_offset = base;

746

} else {

746

} else {

747

e->next = e + 1;

747

e->next = e + 1;

748

d->next_offset = base + (i+1) * sizeof(*d);

748

d->next_offset = base + (i+1) * sizeof(*d);

749

}

749

}

750

}

750

}

751

ring->to_use = ring->to_clean = ring->start;

751

ring->to_use = ring->to_clean = ring->start;

752

753

return 0;

753

return 0;

754

}

754

}

755

756

/* Allocate and setup a new buffer for receiving */

756

/* Allocate and setup a new buffer for receiving */

757

static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,

757

static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,

758

struct sk_buff *skb, unsigned int bufsize)

758

struct sk_buff *skb, unsigned int bufsize)

759

{

759

{

760

struct skge_rx_desc *rd = e->desc;

760

struct skge_rx_desc *rd = e->desc;

761

u64 map;

761

u64 map;

762

763

map = pci_map_single(skge->hw->pdev, skb->data, bufsize,

763

map = pci_map_single(skge->hw->pdev, skb->data, bufsize,

764

PCI_DMA_FROMDEVICE);

764

PCI_DMA_FROMDEVICE);

765

766

rd->dma_lo = map;

766

rd->dma_lo = map;

767

rd->dma_hi = map >> 32;

767

rd->dma_hi = map >> 32;

768

e->skb = skb;

768

e->skb = skb;

769

rd->csum1_start = ETH_HLEN;

769

rd->csum1_start = ETH_HLEN;

770

rd->csum2_start = ETH_HLEN;

770

rd->csum2_start = ETH_HLEN;

771

rd->csum1 = 0;

771

rd->csum1 = 0;

772

rd->csum2 = 0;

772

rd->csum2 = 0;

773

774

wmb();

774

wmb();

775

776

rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;

776

rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;

777

pci_unmap_addr_set(e, mapaddr, map);

777

pci_unmap_addr_set(e, mapaddr, map);

778

pci_unmap_len_set(e, maplen, bufsize);

778

pci_unmap_len_set(e, maplen, bufsize);

779

}

779

}

780

781

/* Resume receiving using existing skb,

781

/* Resume receiving using existing skb,

782

* Note: DMA address is not changed by chip.

782

* Note: DMA address is not changed by chip.

783

* MTU not changed while receiver active.

783

* MTU not changed while receiver active.

784

*/

784

*/

785

static void skge_rx_reuse(struct skge_element *e, unsigned int size)

785

static void skge_rx_reuse(struct skge_element *e, unsigned int size)

786

{

786

{

787

struct skge_rx_desc *rd = e->desc;

787

struct skge_rx_desc *rd = e->desc;

788

789

rd->csum2 = 0;

789

rd->csum2 = 0;

790

rd->csum2_start = ETH_HLEN;

790

rd->csum2_start = ETH_HLEN;

791

792

wmb();

792

wmb();

793

794

rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;

794

rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;

795

}

795

}

796

797

798

/* Free all buffers in receive ring, assumes receiver stopped */

798

/* Free all buffers in receive ring, assumes receiver stopped */

799

static void skge_rx_clean(struct skge_port *skge)

799

static void skge_rx_clean(struct skge_port *skge)

800

{

800

{

801

struct skge_hw *hw = skge->hw;

801

struct skge_hw *hw = skge->hw;

802

struct skge_ring *ring = &skge->rx_ring;

802

struct skge_ring *ring = &skge->rx_ring;

803

struct skge_element *e;

803

struct skge_element *e;

804

805

e = ring->start;

805

e = ring->start;

806

do {

806

do {

807

struct skge_rx_desc *rd = e->desc;

807

struct skge_rx_desc *rd = e->desc;

808

rd->control = 0;

808

rd->control = 0;

809

if (e->skb) {

809

if (e->skb) {

810

pci_unmap_single(hw->pdev,

810

pci_unmap_single(hw->pdev,

811

pci_unmap_addr(e, mapaddr),

811

pci_unmap_addr(e, mapaddr),

812

pci_unmap_len(e, maplen),

812

pci_unmap_len(e, maplen),

813

PCI_DMA_FROMDEVICE);

813

PCI_DMA_FROMDEVICE);

814

dev_kfree_skb(e->skb);

814

dev_kfree_skb(e->skb);

815

e->skb = NULL;

815

e->skb = NULL;

816

}

816

}

817

} while ((e = e->next) != ring->start);

817

} while ((e = e->next) != ring->start);

818

}

818

}

819

820

821

/* Allocate buffers for receive ring

821

/* Allocate buffers for receive ring

822

* For receive: to_clean is next received frame.

822

* For receive: to_clean is next received frame.

823

*/

823

*/

824

static int skge_rx_fill(struct skge_port *skge)

824

static int skge_rx_fill(struct skge_port *skge)

825

{

825

{

826

struct skge_ring *ring = &skge->rx_ring;

826

struct skge_ring *ring = &skge->rx_ring;

827

struct skge_element *e;

827

struct skge_element *e;

828

829

e = ring->start;

829

e = ring->start;

830

do {

830

do {

831

struct sk_buff *skb;

831

struct sk_buff *skb;

832

833

skb = dev_alloc_skb(skge->rx_buf_size + NET_IP_ALIGN);

833

skb = dev_alloc_skb(skge->rx_buf_size + NET_IP_ALIGN);

834

if (!skb)

834

if (!skb)

835

return -ENOMEM;

835

return -ENOMEM;

836

837

skb_reserve(skb, NET_IP_ALIGN);

837

skb_reserve(skb, NET_IP_ALIGN);

838

skge_rx_setup(skge, e, skb, skge->rx_buf_size);

838

skge_rx_setup(skge, e, skb, skge->rx_buf_size);

839

} while ( (e = e->next) != ring->start);

839

} while ( (e = e->next) != ring->start);

840

841

ring->to_clean = ring->start;

841

ring->to_clean = ring->start;

842

return 0;

842

return 0;

843

}

843

}

844

845

static void skge_link_up(struct skge_port *skge)

845

static void skge_link_up(struct skge_port *skge)

846

{

846

{

847

skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),

847

skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),

848

LED_BLK_OFF|LED_SYNC_OFF|LED_ON);

848

LED_BLK_OFF|LED_SYNC_OFF|LED_ON);

849

850

netif_carrier_on(skge->netdev);

850

netif_carrier_on(skge->netdev);

851

if (skge->tx_avail > MAX_SKB_FRAGS + 1)

851

if (skge->tx_avail > MAX_SKB_FRAGS + 1)

852

netif_wake_queue(skge->netdev);

852

netif_wake_queue(skge->netdev);

853

854

if (netif_msg_link(skge))

854

if (netif_msg_link(skge))

855

printk(KERN_INFO PFX

855

printk(KERN_INFO PFX

856

"%s: Link is up at %d Mbps, %s duplex, flow control %s\n",

856

"%s: Link is up at %d Mbps, %s duplex, flow control %s\n",

857

skge->netdev->name, skge->speed,

857

skge->netdev->name, skge->speed,

858

skge->duplex == DUPLEX_FULL ? "full" : "half",

858

skge->duplex == DUPLEX_FULL ? "full" : "half",

859

(skge->flow_control == FLOW_MODE_NONE) ? "none" :

859

(skge->flow_control == FLOW_MODE_NONE) ? "none" :

860

(skge->flow_control == FLOW_MODE_LOC_SEND) ? "tx only" :

860

(skge->flow_control == FLOW_MODE_LOC_SEND) ? "tx only" :

861

(skge->flow_control == FLOW_MODE_REM_SEND) ? "rx only" :

861

(skge->flow_control == FLOW_MODE_REM_SEND) ? "rx only" :

862

(skge->flow_control == FLOW_MODE_SYMMETRIC) ? "tx and rx" :

862

(skge->flow_control == FLOW_MODE_SYMMETRIC) ? "tx and rx" :

863

"unknown");

863

"unknown");

864

}

864

}

865

866

static void skge_link_down(struct skge_port *skge)

866

static void skge_link_down(struct skge_port *skge)

867

{

867

{

868

skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);

868

skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);

869

netif_carrier_off(skge->netdev);

869

netif_carrier_off(skge->netdev);

870

netif_stop_queue(skge->netdev);

870

netif_stop_queue(skge->netdev);

871

872

if (netif_msg_link(skge))

872

if (netif_msg_link(skge))

873

printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);

873

printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);

874

}

874

}

875

876

static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)

876

static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)

877

{

877

{

878

int i;

878

int i;

879

880

xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);

880

xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);

881

*val = xm_read16(hw, port, XM_PHY_DATA);

881

*val = xm_read16(hw, port, XM_PHY_DATA);

882

883

for (i = 0; i < PHY_RETRIES; i++) {

883

for (i = 0; i < PHY_RETRIES; i++) {

884

if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)

884

if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)

885

goto ready;

885

goto ready;

886

udelay(1);

886

udelay(1);

887

}

887

}

888

889

return -ETIMEDOUT;

889

return -ETIMEDOUT;

890

ready:

890

ready:

891

*val = xm_read16(hw, port, XM_PHY_DATA);

891

*val = xm_read16(hw, port, XM_PHY_DATA);

892

893

return 0;

893

return 0;

894

}

894

}

895

896

static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)

896

static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)

897

{

897

{

898

u16 v = 0;

898

u16 v = 0;

899

if (__xm_phy_read(hw, port, reg, &v))

899

if (__xm_phy_read(hw, port, reg, &v))

900

printk(KERN_WARNING PFX "%s: phy read timed out\n",

900

printk(KERN_WARNING PFX "%s: phy read timed out\n",

901

hw->dev[port]->name);

901

hw->dev[port]->name);

902

return v;

902

return v;

903

}

903

}

904

905

static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)

905

static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)

906

{

906

{

907

int i;

907

int i;

908

909

xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);

909

xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);

910

for (i = 0; i < PHY_RETRIES; i++) {

910

for (i = 0; i < PHY_RETRIES; i++) {

911

if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))

911

if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))

912

goto ready;

912

goto ready;

913

udelay(1);

913

udelay(1);

914

}

914

}

915

return -EIO;

915

return -EIO;

916

917

ready:

917

ready:

918

xm_write16(hw, port, XM_PHY_DATA, val);

918

xm_write16(hw, port, XM_PHY_DATA, val);

919

for (i = 0; i < PHY_RETRIES; i++) {

919

for (i = 0; i < PHY_RETRIES; i++) {

920

if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))

920

if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))

921

return 0;

921

return 0;

922

udelay(1);

922

udelay(1);

923

}

923

}

924

return -ETIMEDOUT;

924

return -ETIMEDOUT;

925

}

925

}

926

927

static void genesis_init(struct skge_hw *hw)

927

static void genesis_init(struct skge_hw *hw)

928

{

928

{

929

/* set blink source counter */

929

/* set blink source counter */

930

skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);

930

skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);

931

skge_write8(hw, B2_BSC_CTRL, BSC_START);

931

skge_write8(hw, B2_BSC_CTRL, BSC_START);

932

933

/* configure mac arbiter */

933

/* configure mac arbiter */

934

skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);

934

skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);

935

936

/* configure mac arbiter timeout values */

936

/* configure mac arbiter timeout values */

937

skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);

937

skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);

938

skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);

938

skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);

939

skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);

939

skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);

940

skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);

940

skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);

941

942

skge_write8(hw, B3_MA_RCINI_RX1, 0);

942

skge_write8(hw, B3_MA_RCINI_RX1, 0);

943

skge_write8(hw, B3_MA_RCINI_RX2, 0);

943

skge_write8(hw, B3_MA_RCINI_RX2, 0);

944

skge_write8(hw, B3_MA_RCINI_TX1, 0);

944

skge_write8(hw, B3_MA_RCINI_TX1, 0);

945

skge_write8(hw, B3_MA_RCINI_TX2, 0);

945

skge_write8(hw, B3_MA_RCINI_TX2, 0);

946

947

/* configure packet arbiter timeout */

947

/* configure packet arbiter timeout */

948

skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);

948

skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);

949

skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);

949

skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);

950

skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);

950

skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);

951

skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);

951

skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);

952

skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);

952

skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);

953

}

953

}

954

955

static void genesis_reset(struct skge_hw *hw, int port)

955

static void genesis_reset(struct skge_hw *hw, int port)

956

{

956

{

957

const u8 zero[8] = { 0 };

957

const u8 zero[8] = { 0 };

958

959

skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);

959

skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);

960

961

/* reset the statistics module */

961

/* reset the statistics module */

962

xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);

962

xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);

963

xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */

963

xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */

964

xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */

964

xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */

965

xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */

965

xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */

966

xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */

966

xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */

967

968

/* disable Broadcom PHY IRQ */

968

/* disable Broadcom PHY IRQ */

969

xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);

969

xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);

970

971

xm_outhash(hw, port, XM_HSM, zero);

971

xm_outhash(hw, port, XM_HSM, zero);

972

}

972

}

973

974

975

/* Convert mode to MII values */

975

/* Convert mode to MII values */

976

static const u16 phy_pause_map[] = {

976

static const u16 phy_pause_map[] = {

977

[FLOW_MODE_NONE] = 0,

977

[FLOW_MODE_NONE] = 0,

978

[FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,

978

[FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,

979

[FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,

979

[FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,

980

[FLOW_MODE_REM_SEND] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,

980

[FLOW_MODE_REM_SEND] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,

981

};

981

};

982

983

984

/* Check status of Broadcom phy link */

984

/* Check status of Broadcom phy link */

985

static void bcom_check_link(struct skge_hw *hw, int port)

985

static void bcom_check_link(struct skge_hw *hw, int port)

986

{

986

{

987

struct net_device *dev = hw->dev[port];

987

struct net_device *dev = hw->dev[port];

988

struct skge_port *skge = netdev_priv(dev);

988

struct skge_port *skge = netdev_priv(dev);

989

u16 status;

989

u16 status;

990

991

/* read twice because of latch */

991

/* read twice because of latch */

992

(void) xm_phy_read(hw, port, PHY_BCOM_STAT);

992

(void) xm_phy_read(hw, port, PHY_BCOM_STAT);

993

status = xm_phy_read(hw, port, PHY_BCOM_STAT);

993

status = xm_phy_read(hw, port, PHY_BCOM_STAT);

994

995

if ((status & PHY_ST_LSYNC) == 0) {

995

if ((status & PHY_ST_LSYNC) == 0) {

996

u16 cmd = xm_read16(hw, port, XM_MMU_CMD);

996

u16 cmd = xm_read16(hw, port, XM_MMU_CMD);

997

cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);

997

cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);

998

xm_write16(hw, port, XM_MMU_CMD, cmd);

998

xm_write16(hw, port, XM_MMU_CMD, cmd);

999

/* dummy read to ensure writing */

999

/* dummy read to ensure writing */

1000

(void) xm_read16(hw, port, XM_MMU_CMD);

1000

(void) xm_read16(hw, port, XM_MMU_CMD);

1001

1002

if (netif_carrier_ok(dev))

1002

if (netif_carrier_ok(dev))

1003

skge_link_down(skge);

1003

skge_link_down(skge);

1004

} else {

1004

} else {

1005

if (skge->autoneg == AUTONEG_ENABLE &&

1005

if (skge->autoneg == AUTONEG_ENABLE &&

1006

(status & PHY_ST_AN_OVER)) {

1006

(status & PHY_ST_AN_OVER)) {

1007

u16 lpa = xm_phy_read(hw, port, PHY_BCOM_AUNE_LP);

1007

u16 lpa = xm_phy_read(hw, port, PHY_BCOM_AUNE_LP);

1008

u16 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);

1008

u16 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);

1009

1010

if (lpa & PHY_B_AN_RF) {

1010

if (lpa & PHY_B_AN_RF) {

1011

printk(KERN_NOTICE PFX "%s: remote fault\n",

1011

printk(KERN_NOTICE PFX "%s: remote fault\n",

1012

dev->name);

1012

dev->name);

1013

return;

1013

return;

1014

}

1014

}

1015

1016

/* Check Duplex mismatch */

1016

/* Check Duplex mismatch */

1017

switch (aux & PHY_B_AS_AN_RES_MSK) {

1017

switch (aux & PHY_B_AS_AN_RES_MSK) {

1018

case PHY_B_RES_1000FD:

1018

case PHY_B_RES_1000FD:

1019

skge->duplex = DUPLEX_FULL;

1019

skge->duplex = DUPLEX_FULL;

1020

break;

1020

break;

1021

case PHY_B_RES_1000HD:

1021

case PHY_B_RES_1000HD:

1022

skge->duplex = DUPLEX_HALF;

1022

skge->duplex = DUPLEX_HALF;

1023

break;

1023

break;

1024

default:

1024

default:

1025

printk(KERN_NOTICE PFX "%s: duplex mismatch\n",

1025

printk(KERN_NOTICE PFX "%s: duplex mismatch\n",

1026

dev->name);

1026

dev->name);

1027

return;

1027

return;

1028

}

1028

}

1029

1030

1031

/* We are using IEEE 802.3z/D5.0 Table 37-4 */

1031

/* We are using IEEE 802.3z/D5.0 Table 37-4 */

1032

switch (aux & PHY_B_AS_PAUSE_MSK) {

1032

switch (aux & PHY_B_AS_PAUSE_MSK) {

1033

case PHY_B_AS_PAUSE_MSK:

1033

case PHY_B_AS_PAUSE_MSK:

1034

skge->flow_control = FLOW_MODE_SYMMETRIC;

1034

skge->flow_control = FLOW_MODE_SYMMETRIC;

1035

break;

1035

break;

1036

case PHY_B_AS_PRR:

1036

case PHY_B_AS_PRR:

1037

skge->flow_control = FLOW_MODE_REM_SEND;

1037

skge->flow_control = FLOW_MODE_REM_SEND;

1038

break;

1038

break;

1039

case PHY_B_AS_PRT:

1039

case PHY_B_AS_PRT:

1040

skge->flow_control = FLOW_MODE_LOC_SEND;

1040

skge->flow_control = FLOW_MODE_LOC_SEND;

1041

break;

1041

break;

1042

default:

1042

default:

1043

skge->flow_control = FLOW_MODE_NONE;

1043

skge->flow_control = FLOW_MODE_NONE;

1044

}

1044

}

1045

1046

skge->speed = SPEED_1000;

1046

skge->speed = SPEED_1000;

1047

}

1047

}

1048

1049

if (!netif_carrier_ok(dev))

1049

if (!netif_carrier_ok(dev))

1050

genesis_link_up(skge);

1050

genesis_link_up(skge);

1051

}

1051

}

1052

}

1052

}

1053

1054

/* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional

1054

/* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional

1055

* Phy on for 100 or 10Mbit operation

1055

* Phy on for 100 or 10Mbit operation

1056

*/

1056

*/

1057

static void bcom_phy_init(struct skge_port *skge, int jumbo)

1057

static void bcom_phy_init(struct skge_port *skge, int jumbo)

1058

{

1058

{

1059

struct skge_hw *hw = skge->hw;

1059

struct skge_hw *hw = skge->hw;

1060

int port = skge->port;

1060

int port = skge->port;

1061

int i;

1061

int i;

1062

u16 id1, r, ext, ctl;

1062

u16 id1, r, ext, ctl;

1063

1064

/* magic workaround patterns for Broadcom */

1064

/* magic workaround patterns for Broadcom */

1065

static const struct {

1065

static const struct {

1066

u16 reg;

1066

u16 reg;

1067

u16 val;

1067

u16 val;

1068

} A1hack[] = {

1068

} A1hack[] = {

1069

{ 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },

1069

{ 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },

1070

{ 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },

1070

{ 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },

1071

{ 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },

1071

{ 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },

1072

{ 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },

1072

{ 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },

1073

}, C0hack[] = {

1073

}, C0hack[] = {

1074

{ 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },

1074

{ 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },

1075

{ 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },

1075

{ 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },

1076

};

1076

};

1077

1078

/* read Id from external PHY (all have the same address) */

1078

/* read Id from external PHY (all have the same address) */

1079

id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);

1079

id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);

1080

1081

/* Optimize MDIO transfer by suppressing preamble. */

1081

/* Optimize MDIO transfer by suppressing preamble. */

1082

r = xm_read16(hw, port, XM_MMU_CMD);

1082

r = xm_read16(hw, port, XM_MMU_CMD);

1083

r |= XM_MMU_NO_PRE;

1083

r |= XM_MMU_NO_PRE;

1084

xm_write16(hw, port, XM_MMU_CMD,r);

1084

xm_write16(hw, port, XM_MMU_CMD,r);

1085

1086

switch (id1) {

1086

switch (id1) {

1087

case PHY_BCOM_ID1_C0:

1087

case PHY_BCOM_ID1_C0:

1088

/*

1088

/*

1089

* Workaround BCOM Errata for the C0 type.

1089

* Workaround BCOM Errata for the C0 type.

1090

* Write magic patterns to reserved registers.

1090

* Write magic patterns to reserved registers.

1091

*/

1091

*/

1092

for (i = 0; i < ARRAY_SIZE(C0hack); i++)

1092

for (i = 0; i < ARRAY_SIZE(C0hack); i++)

1093

xm_phy_write(hw, port,

1093

xm_phy_write(hw, port,

1094

C0hack[i].reg, C0hack[i].val);

1094

C0hack[i].reg, C0hack[i].val);

1095

1096

break;

1096

break;

1097

case PHY_BCOM_ID1_A1:

1097

case PHY_BCOM_ID1_A1:

1098

/*

1098

/*

1099

* Workaround BCOM Errata for the A1 type.

1099

* Workaround BCOM Errata for the A1 type.

1100

* Write magic patterns to reserved registers.

1100

* Write magic patterns to reserved registers.

1101

*/

1101

*/

1102

for (i = 0; i < ARRAY_SIZE(A1hack); i++)

1102

for (i = 0; i < ARRAY_SIZE(A1hack); i++)

1103

xm_phy_write(hw, port,

1103

xm_phy_write(hw, port,

1104

A1hack[i].reg, A1hack[i].val);

1104

A1hack[i].reg, A1hack[i].val);

1105

break;

1105

break;

1106

}

1106

}

1107

1108

/*

1108

/*

1109

* Workaround BCOM Errata (#10523) for all BCom PHYs.

1109

* Workaround BCOM Errata (#10523) for all BCom PHYs.

1110

* Disable Power Management after reset.

1110

* Disable Power Management after reset.

1111

*/

1111

*/

1112

r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);

1112

r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);

1113

r |= PHY_B_AC_DIS_PM;

1113

r |= PHY_B_AC_DIS_PM;

1114

xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);

1114

xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);

1115

1116

/* Dummy read */

1116

/* Dummy read */

1117

xm_read16(hw, port, XM_ISRC);

1117

xm_read16(hw, port, XM_ISRC);

1118

1119

ext = PHY_B_PEC_EN_LTR; /* enable tx led */

1119

ext = PHY_B_PEC_EN_LTR; /* enable tx led */

1120

ctl = PHY_CT_SP1000; /* always 1000mbit */

1120

ctl = PHY_CT_SP1000; /* always 1000mbit */

1121

1122

if (skge->autoneg == AUTONEG_ENABLE) {

1122

if (skge->autoneg == AUTONEG_ENABLE) {

1123

/*

1123

/*

1124

* Workaround BCOM Errata #1 for the C5 type.

1124

* Workaround BCOM Errata #1 for the C5 type.

1125

* 1000Base-T Link Acquisition Failure in Slave Mode

1125

* 1000Base-T Link Acquisition Failure in Slave Mode

1126

* Set Repeater/DTE bit 10 of the 1000Base-T Control Register

1126

* Set Repeater/DTE bit 10 of the 1000Base-T Control Register

1127

*/

1127

*/

1128

u16 adv = PHY_B_1000C_RD;

1128

u16 adv = PHY_B_1000C_RD;

1129

if (skge->advertising & ADVERTISED_1000baseT_Half)

1129

if (skge->advertising & ADVERTISED_1000baseT_Half)

1130

adv |= PHY_B_1000C_AHD;

1130

adv |= PHY_B_1000C_AHD;

1131

if (skge->advertising & ADVERTISED_1000baseT_Full)

1131

if (skge->advertising & ADVERTISED_1000baseT_Full)

1132

adv |= PHY_B_1000C_AFD;

1132

adv |= PHY_B_1000C_AFD;

1133

xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);

1133

xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);

1134

1135

ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;

1135

ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;

1136

} else {

1136

} else {

1137

if (skge->duplex == DUPLEX_FULL)

1137

if (skge->duplex == DUPLEX_FULL)

1138

ctl |= PHY_CT_DUP_MD;

1138

ctl |= PHY_CT_DUP_MD;

1139

/* Force to slave */

1139

/* Force to slave */

1140

xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);

1140

xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);

1141

}

1141

}

1142

1143

/* Set autonegotiation pause parameters */

1143

/* Set autonegotiation pause parameters */

1144

xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,

1144

xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,

1145

phy_pause_map[skge->flow_control] | PHY_AN_CSMA);

1145

phy_pause_map[skge->flow_control] | PHY_AN_CSMA);

1146

1147

/* Handle Jumbo frames */

1147

/* Handle Jumbo frames */

1148

if (jumbo) {

1148

if (jumbo) {

1149

xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,

1149

xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,

1150

PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);

1150

PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);

1151

1152

ext |= PHY_B_PEC_HIGH_LA;

1152

ext |= PHY_B_PEC_HIGH_LA;

1153

1154

}

1154

}

1155

1156

xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);

1156

xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);

1157

xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);

1157

xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);

1158

1159

/* Use link status change interrupt */

1159

/* Use link status change interrupt */

1160

xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);

1160

xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);

1161

1162

bcom_check_link(hw, port);

1162

bcom_check_link(hw, port);

1163

}

1163

}

1164

1165

static void genesis_mac_init(struct skge_hw *hw, int port)

1165

static void genesis_mac_init(struct skge_hw *hw, int port)

1166

{

1166

{

1167

struct net_device *dev = hw->dev[port];

1167

struct net_device *dev = hw->dev[port];

1168

struct skge_port *skge = netdev_priv(dev);

1168

struct skge_port *skge = netdev_priv(dev);

1169

int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;

1169

int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;

1170

int i;

1170

int i;

1171

u32 r;

1171

u32 r;

1172

const u8 zero[6] = { 0 };

1172

const u8 zero[6] = { 0 };

1173

1174

for (i = 0; i < 10; i++) {

1174

for (i = 0; i < 10; i++) {

1175

skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),

1175

skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),

1176

MFF_SET_MAC_RST);

1176

MFF_SET_MAC_RST);

1177

if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)

1177

if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)

1178

goto reset_ok;

1178

goto reset_ok;

1179

udelay(1);

1179

udelay(1);

1180

}

1180

}

1181

1182

printk(KERN_WARNING PFX "%s: genesis reset failed\n", dev->name);

1182

printk(KERN_WARNING PFX "%s: genesis reset failed\n", dev->name);

1183

1184

reset_ok:

1184

reset_ok:

1185

/* Unreset the XMAC. */

1185

/* Unreset the XMAC. */

1186

skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);

1186

skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);

1187

1188

/*

1188

/*

1189

* Perform additional initialization for external PHYs,

1189

* Perform additional initialization for external PHYs,

1190

* namely for the 1000baseTX cards that use the XMAC's

1190

* namely for the 1000baseTX cards that use the XMAC's

1191

* GMII mode.

1191

* GMII mode.

1192

*/

1192

*/

1193

/* Take external Phy out of reset */

1193

/* Take external Phy out of reset */

1194

r = skge_read32(hw, B2_GP_IO);

1194

r = skge_read32(hw, B2_GP_IO);

1195

if (port == 0)

1195

if (port == 0)

1196

r |= GP_DIR_0|GP_IO_0;

1196

r |= GP_DIR_0|GP_IO_0;

1197

else

1197

else

1198

r |= GP_DIR_2|GP_IO_2;

1198

r |= GP_DIR_2|GP_IO_2;

1199

1200

skge_write32(hw, B2_GP_IO, r);

1200

skge_write32(hw, B2_GP_IO, r);

1201

1202

1203

/* Enable GMII interface */

1203

/* Enable GMII interface */

1204

xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);

1204

xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);

1205

1206

bcom_phy_init(skge, jumbo);

1206

bcom_phy_init(skge, jumbo);

1207

1208

/* Set Station Address */

1208

/* Set Station Address */

1209

xm_outaddr(hw, port, XM_SA, dev->dev_addr);

1209

xm_outaddr(hw, port, XM_SA, dev->dev_addr);

1210

1211

/* We don't use match addresses so clear */

1211

/* We don't use match addresses so clear */

1212

for (i = 1; i < 16; i++)

1212

for (i = 1; i < 16; i++)

1213

xm_outaddr(hw, port, XM_EXM(i), zero);

1213

xm_outaddr(hw, port, XM_EXM(i), zero);

1214

1215

/* Clear MIB counters */

1215

/* Clear MIB counters */

1216

xm_write16(hw, port, XM_STAT_CMD,

1216

xm_write16(hw, port, XM_STAT_CMD,

1217

XM_SC_CLR_RXC | XM_SC_CLR_TXC);

1217

XM_SC_CLR_RXC | XM_SC_CLR_TXC);

1218

/* Clear two times according to Errata #3 */

1218

/* Clear two times according to Errata #3 */

1219

xm_write16(hw, port, XM_STAT_CMD,

1219

xm_write16(hw, port, XM_STAT_CMD,

1220

XM_SC_CLR_RXC | XM_SC_CLR_TXC);

1220

XM_SC_CLR_RXC | XM_SC_CLR_TXC);

1221

1222

/* configure Rx High Water Mark (XM_RX_HI_WM) */

1222

/* configure Rx High Water Mark (XM_RX_HI_WM) */

1223

xm_write16(hw, port, XM_RX_HI_WM, 1450);

1223

xm_write16(hw, port, XM_RX_HI_WM, 1450);

1224

1225

/* We don't need the FCS appended to the packet. */

1225

/* We don't need the FCS appended to the packet. */

1226

r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;

1226

r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;

1227

if (jumbo)

1227

if (jumbo)

1228

r |= XM_RX_BIG_PK_OK;

1228

r |= XM_RX_BIG_PK_OK;

1229

1230

if (skge->duplex == DUPLEX_HALF) {

1230

if (skge->duplex == DUPLEX_HALF) {

1231

/*

1231

/*

1232

* If in manual half duplex mode the other side might be in

1232

* If in manual half duplex mode the other side might be in

1233

* full duplex mode, so ignore if a carrier extension is not seen

1233

* full duplex mode, so ignore if a carrier extension is not seen

1234

* on frames received

1234

* on frames received

1235

*/

1235

*/

1236

r |= XM_RX_DIS_CEXT;

1236

r |= XM_RX_DIS_CEXT;

1237

}

1237

}

1238

xm_write16(hw, port, XM_RX_CMD, r);

1238

xm_write16(hw, port, XM_RX_CMD, r);

1239

1240

1241

/* We want short frames padded to 60 bytes. */

1241

/* We want short frames padded to 60 bytes. */

1242

xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);

1242

xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);

1243

1244

/*

1244

/*

1245

* Bump up the transmit threshold. This helps hold off transmit

1245

* Bump up the transmit threshold. This helps hold off transmit

1246

* underruns when we're blasting traffic from both ports at once.

1246

* underruns when we're blasting traffic from both ports at once.

1247

*/

1247

*/

1248

xm_write16(hw, port, XM_TX_THR, 512);

1248

xm_write16(hw, port, XM_TX_THR, 512);

1249

1250

/*

1250

/*

1251

* Enable the reception of all error frames. This is is

1251

* Enable the reception of all error frames. This is is

1252

* a necessary evil due to the design of the XMAC. The

1252

* a necessary evil due to the design of the XMAC. The

1253

* XMAC's receive FIFO is only 8K in size, however jumbo

1253

* XMAC's receive FIFO is only 8K in size, however jumbo

1254

* frames can be up to 9000 bytes in length. When bad

1254

* frames can be up to 9000 bytes in length. When bad

1255

* frame filtering is enabled, the XMAC's RX FIFO operates

1255

* frame filtering is enabled, the XMAC's RX FIFO operates

1256

* in 'store and forward' mode. For this to work, the

1256

* in 'store and forward' mode. For this to work, the

1257

* entire frame has to fit into the FIFO, but that means

1257

* entire frame has to fit into the FIFO, but that means

1258

* that jumbo frames larger than 8192 bytes will be

1258

* that jumbo frames larger than 8192 bytes will be

1259

* truncated. Disabling all bad frame filtering causes

1259

* truncated. Disabling all bad frame filtering causes

1260

* the RX FIFO to operate in streaming mode, in which

1260

* the RX FIFO to operate in streaming mode, in which

1261

* case the XMAC will start transferring frames out of the

1261

* case the XMAC will start transferring frames out of the

1262

* RX FIFO as soon as the FIFO threshold is reached.

1262

* RX FIFO as soon as the FIFO threshold is reached.

1263

*/

1263

*/

1264

xm_write32(hw, port, XM_MODE, XM_DEF_MODE);

1264

xm_write32(hw, port, XM_MODE, XM_DEF_MODE);

1265

1266

1267

/*

1267

/*

1268

* Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)

1268

* Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)

1269

* - Enable all bits excepting 'Octets Rx OK Low CntOv'

1269

* - Enable all bits excepting 'Octets Rx OK Low CntOv'

1270

* and 'Octets Rx OK Hi Cnt Ov'.

1270

* and 'Octets Rx OK Hi Cnt Ov'.

1271

*/

1271

*/

1272

xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);

1272

xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);

1273

1274

/*

1274

/*

1275

* Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)

1275

* Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)

1276

* - Enable all bits excepting 'Octets Tx OK Low CntOv'

1276

* - Enable all bits excepting 'Octets Tx OK Low CntOv'

1277

* and 'Octets Tx OK Hi Cnt Ov'.

1277

* and 'Octets Tx OK Hi Cnt Ov'.

1278

*/

1278

*/

1279

xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);

1279

xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);

1280

1281

/* Configure MAC arbiter */

1281

/* Configure MAC arbiter */

1282

skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);

1282

skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);

1283

1284

/* configure timeout values */

1284

/* configure timeout values */

1285

skge_write8(hw, B3_MA_TOINI_RX1, 72);

1285

skge_write8(hw, B3_MA_TOINI_RX1, 72);

1286

skge_write8(hw, B3_MA_TOINI_RX2, 72);

1286

skge_write8(hw, B3_MA_TOINI_RX2, 72);

1287

skge_write8(hw, B3_MA_TOINI_TX1, 72);

1287

skge_write8(hw, B3_MA_TOINI_TX1, 72);

1288

skge_write8(hw, B3_MA_TOINI_TX2, 72);

1288

skge_write8(hw, B3_MA_TOINI_TX2, 72);

1289

1290

skge_write8(hw, B3_MA_RCINI_RX1, 0);

1290

skge_write8(hw, B3_MA_RCINI_RX1, 0);

1291

skge_write8(hw, B3_MA_RCINI_RX2, 0);

1291

skge_write8(hw, B3_MA_RCINI_RX2, 0);

1292

skge_write8(hw, B3_MA_RCINI_TX1, 0);

1292

skge_write8(hw, B3_MA_RCINI_TX1, 0);

1293

skge_write8(hw, B3_MA_RCINI_TX2, 0);

1293

skge_write8(hw, B3_MA_RCINI_TX2, 0);

1294

1295

/* Configure Rx MAC FIFO */

1295

/* Configure Rx MAC FIFO */

1296

skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);

1296

skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);

1297

skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);

1297

skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);

1298

skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);

1298

skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);

1299

1300

/* Configure Tx MAC FIFO */

1300

/* Configure Tx MAC FIFO */

1301

skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);

1301

skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);

1302

skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);

1302

skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);

1303

skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);

1303

skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);

1304

1305

if (jumbo) {

1305

if (jumbo) {

1306

/* Enable frame flushing if jumbo frames used */

1306

/* Enable frame flushing if jumbo frames used */

1307

skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);

1307

skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);

1308

} else {

1308

} else {

1309

/* enable timeout timers if normal frames */

1309

/* enable timeout timers if normal frames */

1310

skge_write16(hw, B3_PA_CTRL,

1310

skge_write16(hw, B3_PA_CTRL,

1311

(port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);

1311

(port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);

1312

}

1312

}

1313

}

1313

}

1314

1315

static void genesis_stop(struct skge_port *skge)

1315

static void genesis_stop(struct skge_port *skge)

1316

{

1316

{

1317

struct skge_hw *hw = skge->hw;

1317

struct skge_hw *hw = skge->hw;

1318

int port = skge->port;

1318

int port = skge->port;

1319

u32 reg;

1319

u32 reg;

1320

1321

genesis_reset(hw, port);

1321

genesis_reset(hw, port);

1322

1323

/* Clear Tx packet arbiter timeout IRQ */

1323

/* Clear Tx packet arbiter timeout IRQ */

1324

skge_write16(hw, B3_PA_CTRL,

1324

skge_write16(hw, B3_PA_CTRL,

1325

port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);

1325

port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);

1326

1327

/*

1327

/*

1328

* If the transfer sticks at the MAC the STOP command will not

1328

* If the transfer sticks at the MAC the STOP command will not

1329

* terminate if we don't flush the XMAC's transmit FIFO !

1329

* terminate if we don't flush the XMAC's transmit FIFO !

1330

*/

1330

*/

1331

xm_write32(hw, port, XM_MODE,

1331

xm_write32(hw, port, XM_MODE,

1332

xm_read32(hw, port, XM_MODE)|XM_MD_FTF);

1332

xm_read32(hw, port, XM_MODE)|XM_MD_FTF);

1333

1334

1335

/* Reset the MAC */

1335

/* Reset the MAC */

1336

skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);

1336

skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);

1337

1338

/* For external PHYs there must be special handling */

1338

/* For external PHYs there must be special handling */

1339

reg = skge_read32(hw, B2_GP_IO);

1339

reg = skge_read32(hw, B2_GP_IO);

1340

if (port == 0) {

1340

if (port == 0) {

1341

reg |= GP_DIR_0;

1341

reg |= GP_DIR_0;

1342

reg &= ~GP_IO_0;

1342

reg &= ~GP_IO_0;

1343

} else {

1343

} else {

1344

reg |= GP_DIR_2;

1344

reg |= GP_DIR_2;

1345

reg &= ~GP_IO_2;

1345

reg &= ~GP_IO_2;

1346

}

1346

}

1347

skge_write32(hw, B2_GP_IO, reg);

1347

skge_write32(hw, B2_GP_IO, reg);

1348

skge_read32(hw, B2_GP_IO);

1348

skge_read32(hw, B2_GP_IO);

1349

1350

xm_write16(hw, port, XM_MMU_CMD,

1350

xm_write16(hw, port, XM_MMU_CMD,

1351

xm_read16(hw, port, XM_MMU_CMD)

1351

xm_read16(hw, port, XM_MMU_CMD)

1352

& ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));

1352

& ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));

1353

1354

xm_read16(hw, port, XM_MMU_CMD);

1354

xm_read16(hw, port, XM_MMU_CMD);

1355

}

1355

}

1356

1357

1358

static void genesis_get_stats(struct skge_port *skge, u64 *data)

1358

static void genesis_get_stats(struct skge_port *skge, u64 *data)

1359

{

1359

{

1360

struct skge_hw *hw = skge->hw;

1360

struct skge_hw *hw = skge->hw;

1361

int port = skge->port;

1361

int port = skge->port;

1362

int i;

1362

int i;

1363

unsigned long timeout = jiffies + HZ;

1363

unsigned long timeout = jiffies + HZ;

1364

1365

xm_write16(hw, port,

1365

xm_write16(hw, port,

1366

XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);

1366

XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);

1367

1368

/* wait for update to complete */

1368

/* wait for update to complete */

1369

while (xm_read16(hw, port, XM_STAT_CMD)

1369

while (xm_read16(hw, port, XM_STAT_CMD)

1370

& (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {

1370

& (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {

1371

if (time_after(jiffies, timeout))

1371

if (time_after(jiffies, timeout))

1372

break;

1372

break;

1373

udelay(10);

1373

udelay(10);

1374

}

1374

}

1375

1376

/* special case for 64 bit octet counter */

1376

/* special case for 64 bit octet counter */

1377

data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32

1377

data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32

1378

| xm_read32(hw, port, XM_TXO_OK_LO);

1378

| xm_read32(hw, port, XM_TXO_OK_LO);

1379

data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32

1379

data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32

1380

| xm_read32(hw, port, XM_RXO_OK_LO);

1380

| xm_read32(hw, port, XM_RXO_OK_LO);

1381

1382

for (i = 2; i < ARRAY_SIZE(skge_stats); i++)

1382

for (i = 2; i < ARRAY_SIZE(skge_stats); i++)

1383

data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);

1383

data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);

1384

}

1384

}

1385

1386

static void genesis_mac_intr(struct skge_hw *hw, int port)

1386

static void genesis_mac_intr(struct skge_hw *hw, int port)

1387

{

1387

{

1388

struct skge_port *skge = netdev_priv(hw->dev[port]);

1388

struct skge_port *skge = netdev_priv(hw->dev[port]);

1389

u16 status = xm_read16(hw, port, XM_ISRC);

1389

u16 status = xm_read16(hw, port, XM_ISRC);

1390

1391

if (netif_msg_intr(skge))

1391

if (netif_msg_intr(skge))

1392

printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",

1392

printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",

1393

skge->netdev->name, status);

1393

skge->netdev->name, status);

1394

1395

if (status & XM_IS_TXF_UR) {

1395

if (status & XM_IS_TXF_UR) {

1396

xm_write32(hw, port, XM_MODE, XM_MD_FTF);

1396

xm_write32(hw, port, XM_MODE, XM_MD_FTF);

1397

++skge->net_stats.tx_fifo_errors;

1397

++skge->net_stats.tx_fifo_errors;

1398

}

1398

}

1399

if (status & XM_IS_RXF_OV) {

1399

if (status & XM_IS_RXF_OV) {

1400

xm_write32(hw, port, XM_MODE, XM_MD_FRF);

1400

xm_write32(hw, port, XM_MODE, XM_MD_FRF);

1401

++skge->net_stats.rx_fifo_errors;

1401

++skge->net_stats.rx_fifo_errors;

1402

}

1402

}

1403

}

1403

}

1404

1405

static void genesis_link_up(struct skge_port *skge)

1405

static void genesis_link_up(struct skge_port *skge)

1406

{

1406

{

1407

struct skge_hw *hw = skge->hw;

1407

struct skge_hw *hw = skge->hw;

1408

int port = skge->port;

1408

int port = skge->port;

1409

u16 cmd;

1409

u16 cmd;

1410

u32 mode, msk;

1410

u32 mode, msk;

1411

1412

cmd = xm_read16(hw, port, XM_MMU_CMD);

1412

cmd = xm_read16(hw, port, XM_MMU_CMD);

1413

1414

/*

1414

/*

1415

* enabling pause frame reception is required for 1000BT

1415

* enabling pause frame reception is required for 1000BT

1416

* because the XMAC is not reset if the link is going down

1416

* because the XMAC is not reset if the link is going down

1417

*/

1417

*/

1418

if (skge->flow_control == FLOW_MODE_NONE ||

1418

if (skge->flow_control == FLOW_MODE_NONE ||

1419

skge->flow_control == FLOW_MODE_LOC_SEND)

1419

skge->flow_control == FLOW_MODE_LOC_SEND)

1420

/* Disable Pause Frame Reception */

1420

/* Disable Pause Frame Reception */

1421

cmd |= XM_MMU_IGN_PF;

1421

cmd |= XM_MMU_IGN_PF;

1422

else

1422

else

1423

/* Enable Pause Frame Reception */

1423

/* Enable Pause Frame Reception */

1424

cmd &= ~XM_MMU_IGN_PF;

1424

cmd &= ~XM_MMU_IGN_PF;

1425

1426

xm_write16(hw, port, XM_MMU_CMD, cmd);

1426

xm_write16(hw, port, XM_MMU_CMD, cmd);

1427

1428

mode = xm_read32(hw, port, XM_MODE);

1428

mode = xm_read32(hw, port, XM_MODE);

1429

if (skge->flow_control == FLOW_MODE_SYMMETRIC ||

1429

if (skge->flow_control == FLOW_MODE_SYMMETRIC ||

1430

skge->flow_control == FLOW_MODE_LOC_SEND) {

1430

skge->flow_control == FLOW_MODE_LOC_SEND) {

1431

/*

1431

/*

1432

* Configure Pause Frame Generation

1432

* Configure Pause Frame Generation

1433

* Use internal and external Pause Frame Generation.

1433

* Use internal and external Pause Frame Generation.

1434

* Sending pause frames is edge triggered.

1434

* Sending pause frames is edge triggered.

1435

* Send a Pause frame with the maximum pause time if

1435

* Send a Pause frame with the maximum pause time if

1436

* internal oder external FIFO full condition occurs.

1436

* internal oder external FIFO full condition occurs.

1437

* Send a zero pause time frame to re-start transmission.

1437

* Send a zero pause time frame to re-start transmission.

1438

*/

1438

*/

1439

/* XM_PAUSE_DA = '010000C28001' (default) */

1439

/* XM_PAUSE_DA = '010000C28001' (default) */

1440

/* XM_MAC_PTIME = 0xffff (maximum) */

1440

/* XM_MAC_PTIME = 0xffff (maximum) */

1441

/* remember this value is defined in big endian (!) */

1441

/* remember this value is defined in big endian (!) */

1442

xm_write16(hw, port, XM_MAC_PTIME, 0xffff);

1442

xm_write16(hw, port, XM_MAC_PTIME, 0xffff);

1443

1444

mode |= XM_PAUSE_MODE;

1444

mode |= XM_PAUSE_MODE;

1445

skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);

1445

skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);

1446

} else {

1446

} else {

1447

/*

1447

/*

1448

* disable pause frame generation is required for 1000BT

1448

* disable pause frame generation is required for 1000BT

1449

* because the XMAC is not reset if the link is going down

1449

* because the XMAC is not reset if the link is going down

1450

*/

1450

*/

1451

/* Disable Pause Mode in Mode Register */

1451

/* Disable Pause Mode in Mode Register */

1452

mode &= ~XM_PAUSE_MODE;

1452

mode &= ~XM_PAUSE_MODE;

1453

1454

skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);

1454

skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);

1455

}

1455

}

1456

1457

xm_write32(hw, port, XM_MODE, mode);

1457

xm_write32(hw, port, XM_MODE, mode);

1458

1459

msk = XM_DEF_MSK;

1459

msk = XM_DEF_MSK;

1460

/* disable GP0 interrupt bit for external Phy */

1460

/* disable GP0 interrupt bit for external Phy */

1461

msk |= XM_IS_INP_ASS;

1461

msk |= XM_IS_INP_ASS;

1462

1463

xm_write16(hw, port, XM_IMSK, msk);

1463

xm_write16(hw, port, XM_IMSK, msk);

1464

xm_read16(hw, port, XM_ISRC);

1464

xm_read16(hw, port, XM_ISRC);

1465

1466

/* get MMU Command Reg. */

1466

/* get MMU Command Reg. */

1467

cmd = xm_read16(hw, port, XM_MMU_CMD);

1467

cmd = xm_read16(hw, port, XM_MMU_CMD);

1468

if (skge->duplex == DUPLEX_FULL)

1468

if (skge->duplex == DUPLEX_FULL)

1469

cmd |= XM_MMU_GMII_FD;

1469

cmd |= XM_MMU_GMII_FD;

1470

1471

/*

1471

/*

1472

* Workaround BCOM Errata (#10523) for all BCom Phys

1472

* Workaround BCOM Errata (#10523) for all BCom Phys

1473

* Enable Power Management after link up

1473

* Enable Power Management after link up

1474

*/

1474

*/

1475

xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,

1475

xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,

1476

xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)

1476

xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)

1477

& ~PHY_B_AC_DIS_PM);

1477

& ~PHY_B_AC_DIS_PM);

1478

xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);

1478

xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);

1479

1480

/* enable Rx/Tx */

1480

/* enable Rx/Tx */

1481

xm_write16(hw, port, XM_MMU_CMD,

1481

xm_write16(hw, port, XM_MMU_CMD,

1482

cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);

1482

cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);

1483

skge_link_up(skge);

1483

skge_link_up(skge);

1484

}

1484

}

1485

1486

1487

static inline void bcom_phy_intr(struct skge_port *skge)

1487

static inline void bcom_phy_intr(struct skge_port *skge)

1488

{

1488

{

1489

struct skge_hw *hw = skge->hw;

1489

struct skge_hw *hw = skge->hw;

1490

int port = skge->port;

1490

int port = skge->port;

1491

u16 isrc;

1491

u16 isrc;

1492

1493

isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);

1493

isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);

1494

if (netif_msg_intr(skge))

1494

if (netif_msg_intr(skge))

1495

printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x\n",

1495

printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x\n",

1496

skge->netdev->name, isrc);

1496

skge->netdev->name, isrc);

1497

1498

if (isrc & PHY_B_IS_PSE)

1498

if (isrc & PHY_B_IS_PSE)

1499

printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n",

1499

printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n",

1500

hw->dev[port]->name);

1500

hw->dev[port]->name);

1501

1502

/* Workaround BCom Errata:

1502

/* Workaround BCom Errata:

1503

* enable and disable loopback mode if "NO HCD" occurs.

1503

* enable and disable loopback mode if "NO HCD" occurs.

1504

*/

1504

*/

1505

if (isrc & PHY_B_IS_NO_HDCL) {

1505

if (isrc & PHY_B_IS_NO_HDCL) {

1506

u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);

1506

u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);

1507

xm_phy_write(hw, port, PHY_BCOM_CTRL,

1507

xm_phy_write(hw, port, PHY_BCOM_CTRL,

1508

ctrl | PHY_CT_LOOP);

1508

ctrl | PHY_CT_LOOP);

1509

xm_phy_write(hw, port, PHY_BCOM_CTRL,

1509

xm_phy_write(hw, port, PHY_BCOM_CTRL,

1510

ctrl & ~PHY_CT_LOOP);

1510

ctrl & ~PHY_CT_LOOP);

1511

}

1511

}

1512

1513

if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))

1513

if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))

1514

bcom_check_link(hw, port);

1514

bcom_check_link(hw, port);

1515

1516

}

1516

}

1517

1518

static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)

1518

static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)

1519

{

1519

{

1520

int i;

1520

int i;

1521

1522

gma_write16(hw, port, GM_SMI_DATA, val);

1522

gma_write16(hw, port, GM_SMI_DATA, val);

1523

gma_write16(hw, port, GM_SMI_CTRL,

1523

gma_write16(hw, port, GM_SMI_CTRL,

1524

GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));

1524

GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));

1525

for (i = 0; i < PHY_RETRIES; i++) {

1525

for (i = 0; i < PHY_RETRIES; i++) {

1526

udelay(1);

1526

udelay(1);

1527

1528

if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))

1528

if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))

1529

return 0;

1529

return 0;

1530

}

1530

}

1531

1532

printk(KERN_WARNING PFX "%s: phy write timeout\n",

1532

printk(KERN_WARNING PFX "%s: phy write timeout\n",

1533

hw->dev[port]->name);

1533

hw->dev[port]->name);

1534

return -EIO;

1534

return -EIO;

1535

}

1535

}

1536

1537

static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)

1537

static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)

1538

{

1538

{

1539

int i;

1539

int i;

1540

1541

gma_write16(hw, port, GM_SMI_CTRL,

1541

gma_write16(hw, port, GM_SMI_CTRL,

1542

GM_SMI_CT_PHY_AD(hw->phy_addr)

1542

GM_SMI_CT_PHY_AD(hw->phy_addr)

1543

| GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);

1543

| GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);

1544

1545

for (i = 0; i < PHY_RETRIES; i++) {

1545

for (i = 0; i < PHY_RETRIES; i++) {

1546

udelay(1);

1546

udelay(1);

1547

if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)

1547

if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)

1548

goto ready;

1548

goto ready;

1549

}

1549

}

1550

1551

return -ETIMEDOUT;

1551

return -ETIMEDOUT;

1552

ready:

1552

ready:

1553

*val = gma_read16(hw, port, GM_SMI_DATA);

1553

*val = gma_read16(hw, port, GM_SMI_DATA);

1554

return 0;

1554

return 0;

1555

}

1555

}

1556

1557

static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)

1557

static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)

1558

{

1558

{

1559

u16 v = 0;

1559

u16 v = 0;

1560

if (__gm_phy_read(hw, port, reg, &v))

1560

if (__gm_phy_read(hw, port, reg, &v))

1561

printk(KERN_WARNING PFX "%s: phy read timeout\n",

1561

printk(KERN_WARNING PFX "%s: phy read timeout\n",

1562

hw->dev[port]->name);

1562

hw->dev[port]->name);

1563

return v;

1563

return v;

1564

}

1564

}

1565

1566

/* Marvell Phy Initialization */

1566

/* Marvell Phy Initialization */

1567

static void yukon_init(struct skge_hw *hw, int port)

1567

static void yukon_init(struct skge_hw *hw, int port)

1568

{

1568

{

1569

struct skge_port *skge = netdev_priv(hw->dev[port]);

1569

struct skge_port *skge = netdev_priv(hw->dev[port]);

1570

u16 ctrl, ct1000, adv;

1570

u16 ctrl, ct1000, adv;

1571

1572

if (skge->autoneg == AUTONEG_ENABLE) {

1572

if (skge->autoneg == AUTONEG_ENABLE) {

1573

u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);

1573

u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);

1574

1575

ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |

1575

ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |

1576

PHY_M_EC_MAC_S_MSK);

1576

PHY_M_EC_MAC_S_MSK);

1577

ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);

1577

ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);

1578

1579

ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);

1579

ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);

1580

1581

gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);

1581

gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);

1582

}

1582

}

1583

1584

ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);

1584

ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);

1585

if (skge->autoneg == AUTONEG_DISABLE)

1585

if (skge->autoneg == AUTONEG_DISABLE)

1586

ctrl &= ~PHY_CT_ANE;

1586

ctrl &= ~PHY_CT_ANE;

1587

1588

ctrl |= PHY_CT_RESET;

1588

ctrl |= PHY_CT_RESET;

1589

gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);

1589

gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);

1590

1591

ctrl = 0;

1591

ctrl = 0;

1592

ct1000 = 0;

1592

ct1000 = 0;

1593

adv = PHY_AN_CSMA;

1593

adv = PHY_AN_CSMA;

1594

1595

if (skge->autoneg == AUTONEG_ENABLE) {

1595

if (skge->autoneg == AUTONEG_ENABLE) {

1596

if (hw->copper) {

1596

if (hw->copper) {

1597

if (skge->advertising & ADVERTISED_1000baseT_Full)

1597

if (skge->advertising & ADVERTISED_1000baseT_Full)

1598

ct1000 |= PHY_M_1000C_AFD;

1598

ct1000 |= PHY_M_1000C_AFD;

1599

if (skge->advertising & ADVERTISED_1000baseT_Half)

1599

if (skge->advertising & ADVERTISED_1000baseT_Half)

1600

ct1000 |= PHY_M_1000C_AHD;

1600

ct1000 |= PHY_M_1000C_AHD;

1601

if (skge->advertising & ADVERTISED_100baseT_Full)

1601

if (skge->advertising & ADVERTISED_100baseT_Full)

1602

adv |= PHY_M_AN_100_FD;

1602

adv |= PHY_M_AN_100_FD;

1603

if (skge->advertising & ADVERTISED_100baseT_Half)

1603

if (skge->advertising & ADVERTISED_100baseT_Half)

1604

adv |= PHY_M_AN_100_HD;

1604

adv |= PHY_M_AN_100_HD;

1605

if (skge->advertising & ADVERTISED_10baseT_Full)

1605

if (skge->advertising & ADVERTISED_10baseT_Full)

1606

adv |= PHY_M_AN_10_FD;

1606

adv |= PHY_M_AN_10_FD;

1607

if (skge->advertising & ADVERTISED_10baseT_Half)

1607

if (skge->advertising & ADVERTISED_10baseT_Half)

1608

adv |= PHY_M_AN_10_HD;

1608

adv |= PHY_M_AN_10_HD;

1609

} else /* special defines for FIBER (88E1011S only) */

1609

} else /* special defines for FIBER (88E1011S only) */

1610

adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;

1610

adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;

1611

1612

/* Set Flow-control capabilities */

1612

/* Set Flow-control capabilities */

1613

adv |= phy_pause_map[skge->flow_control];

1613

adv |= phy_pause_map[skge->flow_control];

1614

1615

/* Restart Auto-negotiation */

1615

/* Restart Auto-negotiation */

1616

ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;

1616

ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;

1617

} else {

1617

} else {

1618

/* forced speed/duplex settings */

1618

/* forced speed/duplex settings */

1619

ct1000 = PHY_M_1000C_MSE;

1619

ct1000 = PHY_M_1000C_MSE;

1620

1621

if (skge->duplex == DUPLEX_FULL)

1621

if (skge->duplex == DUPLEX_FULL)

1622

ctrl |= PHY_CT_DUP_MD;

1622

ctrl |= PHY_CT_DUP_MD;

1623

1624

switch (skge->speed) {

1624

switch (skge->speed) {

1625

case SPEED_1000:

1625

case SPEED_1000:

1626

ctrl |= PHY_CT_SP1000;

1626

ctrl |= PHY_CT_SP1000;

1627

break;

1627

break;

1628

case SPEED_100:

1628

case SPEED_100:

1629

ctrl |= PHY_CT_SP100;

1629

ctrl |= PHY_CT_SP100;

1630

break;

1630

break;

1631

}

1631

}

1632

1633

ctrl |= PHY_CT_RESET;

1633

ctrl |= PHY_CT_RESET;

1634

}

1634

}

1635

1636

gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);

1636

gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);

1637

1638

gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);

1638

gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);

1639

gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);

1639

gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);

1640

1641

/* Enable phy interrupt on autonegotiation complete (or link up) */

1641

/* Enable phy interrupt on autonegotiation complete (or link up) */

1642

if (skge->autoneg == AUTONEG_ENABLE)

1642

if (skge->autoneg == AUTONEG_ENABLE)

1643

gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);

1643

gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);

1644

else

1644

else

1645

gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);

1645

gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);

1646

}

1646

}

1647

1648

static void yukon_reset(struct skge_hw *hw, int port)

1648

static void yukon_reset(struct skge_hw *hw, int port)

1649

{

1649

{

1650

gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */

1650

gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */

1651

gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */

1651

gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */

1652

gma_write16(hw, port, GM_MC_ADDR_H2, 0);

1652

gma_write16(hw, port, GM_MC_ADDR_H2, 0);

1653

gma_write16(hw, port, GM_MC_ADDR_H3, 0);

1653

gma_write16(hw, port, GM_MC_ADDR_H3, 0);

1654

gma_write16(hw, port, GM_MC_ADDR_H4, 0);

1654

gma_write16(hw, port, GM_MC_ADDR_H4, 0);

1655

1656

gma_write16(hw, port, GM_RX_CTRL,

1656

gma_write16(hw, port, GM_RX_CTRL,

1657

gma_read16(hw, port, GM_RX_CTRL)

1657

gma_read16(hw, port, GM_RX_CTRL)

1658

| GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);

1658

| GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);

1659

}

1659

}

1660

1661

/* Apparently, early versions of Yukon-Lite had wrong chip_id? */

1661

/* Apparently, early versions of Yukon-Lite had wrong chip_id? */

1662

static int is_yukon_lite_a0(struct skge_hw *hw)

1662

static int is_yukon_lite_a0(struct skge_hw *hw)

1663

{

1663

{

1664

u32 reg;

1664

u32 reg;

1665

int ret;

1665

int ret;

1666

1667

if (hw->chip_id != CHIP_ID_YUKON)

1667

if (hw->chip_id != CHIP_ID_YUKON)

1668

return 0;

1668

return 0;

1669

1670

reg = skge_read32(hw, B2_FAR);

1670

reg = skge_read32(hw, B2_FAR);

1671

skge_write8(hw, B2_FAR + 3, 0xff);

1671

skge_write8(hw, B2_FAR + 3, 0xff);

1672

ret = (skge_read8(hw, B2_FAR + 3) != 0);

1672

ret = (skge_read8(hw, B2_FAR + 3) != 0);

1673

skge_write32(hw, B2_FAR, reg);

1673

skge_write32(hw, B2_FAR, reg);

1674

return ret;

1674

return ret;

1675

}

1675

}

1676

1677

static void yukon_mac_init(struct skge_hw *hw, int port)

1677

static void yukon_mac_init(struct skge_hw *hw, int port)

1678

{

1678

{

1679

struct skge_port *skge = netdev_priv(hw->dev[port]);

1679

struct skge_port *skge = netdev_priv(hw->dev[port]);

1680

int i;

1680

int i;

1681

u32 reg;

1681

u32 reg;

1682

const u8 *addr = hw->dev[port]->dev_addr;

1682

const u8 *addr = hw->dev[port]->dev_addr;

1683

1684

/* WA code for COMA mode -- set PHY reset */

1684

/* WA code for COMA mode -- set PHY reset */

1685

if (hw->chip_id == CHIP_ID_YUKON_LITE &&

1685

if (hw->chip_id == CHIP_ID_YUKON_LITE &&

1686

hw->chip_rev >= CHIP_REV_YU_LITE_A3) {

1686

hw->chip_rev >= CHIP_REV_YU_LITE_A3) {

1687

reg = skge_read32(hw, B2_GP_IO);

1687

reg = skge_read32(hw, B2_GP_IO);

1688

reg |= GP_DIR_9 | GP_IO_9;

1688

reg |= GP_DIR_9 | GP_IO_9;

1689

skge_write32(hw, B2_GP_IO, reg);

1689

skge_write32(hw, B2_GP_IO, reg);

1690

}

1690

}

1691

1692

/* hard reset */

1692

/* hard reset */

1693

skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);

1693

skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);

1694

skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);

1694

skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);

1695

1696

/* WA code for COMA mode -- clear PHY reset */

1696

/* WA code for COMA mode -- clear PHY reset */

1697

if (hw->chip_id == CHIP_ID_YUKON_LITE &&

1697

if (hw->chip_id == CHIP_ID_YUKON_LITE &&

1698

hw->chip_rev >= CHIP_REV_YU_LITE_A3) {

1698

hw->chip_rev >= CHIP_REV_YU_LITE_A3) {

1699

reg = skge_read32(hw, B2_GP_IO);

1699

reg = skge_read32(hw, B2_GP_IO);

1700

reg |= GP_DIR_9;

1700

reg |= GP_DIR_9;

1701

reg &= ~GP_IO_9;

1701

reg &= ~GP_IO_9;

1702

skge_write32(hw, B2_GP_IO, reg);

1702

skge_write32(hw, B2_GP_IO, reg);

1703

}

1703

}

1704

1705

/* Set hardware config mode */

1705

/* Set hardware config mode */

1706

reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |

1706

reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |

1707

GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;

1707

GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;

1708

reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;

1708

reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;

1709

1710

/* Clear GMC reset */

1710

/* Clear GMC reset */

1711

skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);

1711

skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);

1712

skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);

1712

skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);

1713

skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);

1713

skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);

1714

1715

if (skge->autoneg == AUTONEG_DISABLE) {

1715

if (skge->autoneg == AUTONEG_DISABLE) {

1716

reg = GM_GPCR_AU_ALL_DIS;

1716

reg = GM_GPCR_AU_ALL_DIS;

1717

gma_write16(hw, port, GM_GP_CTRL,

1717

gma_write16(hw, port, GM_GP_CTRL,

1718

gma_read16(hw, port, GM_GP_CTRL) | reg);

1718

gma_read16(hw, port, GM_GP_CTRL) | reg);

1719

1720

switch (skge->speed) {

1720

switch (skge->speed) {

1721

case SPEED_1000:

1721

case SPEED_1000:

1722

reg &= ~GM_GPCR_SPEED_100;

1722

reg &= ~GM_GPCR_SPEED_100;

1723

reg |= GM_GPCR_SPEED_1000;

1723

reg |= GM_GPCR_SPEED_1000;

1724

break;

1724

break;

1725

case SPEED_100:

1725

case SPEED_100:

1726

reg &= ~GM_GPCR_SPEED_1000;

1726

reg &= ~GM_GPCR_SPEED_1000;

1727

reg |= GM_GPCR_SPEED_100;

1727

reg |= GM_GPCR_SPEED_100;

1728

break;

1728

break;

1729

case SPEED_10:

1729

case SPEED_10:

1730

reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);

1730

reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);

1731

break;

1731

break;

1732

}

1732

}

1733

1734

if (skge->duplex == DUPLEX_FULL)

1734

if (skge->duplex == DUPLEX_FULL)

1735

reg |= GM_GPCR_DUP_FULL;

1735

reg |= GM_GPCR_DUP_FULL;

1736

} else

1736

} else

1737

reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;

1737

reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;

1738

1739

switch (skge->flow_control) {

1739

switch (skge->flow_control) {

1740

case FLOW_MODE_NONE:

1740

case FLOW_MODE_NONE:

1741

skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);

1741

skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);

1742

reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;

1742

reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;

1743

break;

1743

break;

1744

case FLOW_MODE_LOC_SEND:

1744

case FLOW_MODE_LOC_SEND:

1745

/* disable Rx flow-control */

1745

/* disable Rx flow-control */

1746

reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;

1746

reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;

1747

}

1747

}

1748

1749

gma_write16(hw, port, GM_GP_CTRL, reg);

1749

gma_write16(hw, port, GM_GP_CTRL, reg);

1750

skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));

1750

skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));

1751

1752

yukon_init(hw, port);

1752

yukon_init(hw, port);

1753

1754

/* MIB clear */

1754

/* MIB clear */

1755

reg = gma_read16(hw, port, GM_PHY_ADDR);

1755

reg = gma_read16(hw, port, GM_PHY_ADDR);

1756

gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);

1756

gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);

1757

1758

for (i = 0; i < GM_MIB_CNT_SIZE; i++)

1758

for (i = 0; i < GM_MIB_CNT_SIZE; i++)

1759

gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);

1759

gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);

1760

gma_write16(hw, port, GM_PHY_ADDR, reg);

1760

gma_write16(hw, port, GM_PHY_ADDR, reg);

1761

1762

/* transmit control */

1762

/* transmit control */

1763

gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));

1763

gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));

1764

1765

/* receive control reg: unicast + multicast + no FCS */

1765

/* receive control reg: unicast + multicast + no FCS */

1766

gma_write16(hw, port, GM_RX_CTRL,

1766

gma_write16(hw, port, GM_RX_CTRL,

1767

GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);

1767

GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);

1768

1769

/* transmit flow control */

1769

/* transmit flow control */

1770

gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);

1770

gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);

1771

1772

/* transmit parameter */

1772

/* transmit parameter */

1773

gma_write16(hw, port, GM_TX_PARAM,

1773

gma_write16(hw, port, GM_TX_PARAM,

1774

TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |

1774

TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |

1775

TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |

1775

TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |

1776

TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));

1776

TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));

1777

1778

/* serial mode register */

1778

/* serial mode register */

1779

reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);

1779

reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);

1780

if (hw->dev[port]->mtu > 1500)

1780

if (hw->dev[port]->mtu > 1500)

1781

reg |= GM_SMOD_JUMBO_ENA;

1781

reg |= GM_SMOD_JUMBO_ENA;

1782

1783

gma_write16(hw, port, GM_SERIAL_MODE, reg);

1783

gma_write16(hw, port, GM_SERIAL_MODE, reg);

1784

1785

/* physical address: used for pause frames */

1785

/* physical address: used for pause frames */

1786

gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);

1786

gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);

1787

/* virtual address for data */

1787

/* virtual address for data */

1788

gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);

1788

gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);

1789

1790

/* enable interrupt mask for counter overflows */

1790

/* enable interrupt mask for counter overflows */

1791

gma_write16(hw, port, GM_TX_IRQ_MSK, 0);

1791

gma_write16(hw, port, GM_TX_IRQ_MSK, 0);

1792

gma_write16(hw, port, GM_RX_IRQ_MSK, 0);

1792

gma_write16(hw, port, GM_RX_IRQ_MSK, 0);

1793

gma_write16(hw, port, GM_TR_IRQ_MSK, 0);

1793

gma_write16(hw, port, GM_TR_IRQ_MSK, 0);

1794

1795

/* Initialize Mac Fifo */

1795

/* Initialize Mac Fifo */

1796

1797

/* Configure Rx MAC FIFO */

1797

/* Configure Rx MAC FIFO */

1798

skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);

1798

skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);

1799

reg = GMF_OPER_ON | GMF_RX_F_FL_ON;

1799

reg = GMF_OPER_ON | GMF_RX_F_FL_ON;

1800

1801

/* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */

1801

/* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */

1802

if (is_yukon_lite_a0(hw))

1802

if (is_yukon_lite_a0(hw))

1803

reg &= ~GMF_RX_F_FL_ON;

1803

reg &= ~GMF_RX_F_FL_ON;

1804

1805

skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);

1805

skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);

1806

skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);

1806

skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);

1807

/*

1807

/*

1808

* because Pause Packet Truncation in GMAC is not working

1808

* because Pause Packet Truncation in GMAC is not working

1809

* we have to increase the Flush Threshold to 64 bytes

1809

* we have to increase the Flush Threshold to 64 bytes

1810

* in order to flush pause packets in Rx FIFO on Yukon-1

1810

* in order to flush pause packets in Rx FIFO on Yukon-1

1811

*/

1811

*/

1812

skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);

1812

skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);

1813

1814

/* Configure Tx MAC FIFO */

1814

/* Configure Tx MAC FIFO */

1815

skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);

1815

skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);

1816

skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);

1816

skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);

1817

}

1817

}

1818

1819

/* Go into power down mode */

1819

/* Go into power down mode */

1820

static void yukon_suspend(struct skge_hw *hw, int port)

1820

static void yukon_suspend(struct skge_hw *hw, int port)

1821

{

1821

{

1822

u16 ctrl;

1822

u16 ctrl;

1823

1824

ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);

1824

ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);

1825

ctrl |= PHY_M_PC_POL_R_DIS;

1825

ctrl |= PHY_M_PC_POL_R_DIS;

1826

gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);

1826

gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);

1827

1828

ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);

1828

ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);

1829

ctrl |= PHY_CT_RESET;

1829

ctrl |= PHY_CT_RESET;

1830

gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);

1830

gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);

1831

1832

/* switch IEEE compatible power down mode on */

1832

/* switch IEEE compatible power down mode on */

1833

ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);

1833

ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);

1834

ctrl |= PHY_CT_PDOWN;

1834

ctrl |= PHY_CT_PDOWN;

1835

gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);

1835

gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);

1836

}

1836

}

1837

1838

static void yukon_stop(struct skge_port *skge)

1838

static void yukon_stop(struct skge_port *skge)

1839

{

1839

{

1840

struct skge_hw *hw = skge->hw;

1840

struct skge_hw *hw = skge->hw;

1841

int port = skge->port;

1841

int port = skge->port;

1842

1843

skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);

1843

skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);

1844

yukon_reset(hw, port);

1844

yukon_reset(hw, port);

1845

1846

gma_write16(hw, port, GM_GP_CTRL,

1846

gma_write16(hw, port, GM_GP_CTRL,

1847

gma_read16(hw, port, GM_GP_CTRL)

1847

gma_read16(hw, port, GM_GP_CTRL)

1848

& ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));

1848

& ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));

1849

gma_read16(hw, port, GM_GP_CTRL);

1849

gma_read16(hw, port, GM_GP_CTRL);

1850

1851

yukon_suspend(hw, port);

1851

yukon_suspend(hw, port);

1852

1853

/* set GPHY Control reset */

1853

/* set GPHY Control reset */

1854

skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);

1854

skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);

1855

skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);

1855

skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);

1856

}

1856

}

1857

1858

static void yukon_get_stats(struct skge_port *skge, u64 *data)

1858

static void yukon_get_stats(struct skge_port *skge, u64 *data)

1859

{

1859

{

1860

struct skge_hw *hw = skge->hw;

1860

struct skge_hw *hw = skge->hw;

1861

int port = skge->port;

1861

int port = skge->port;

1862

int i;

1862

int i;

1863

1864

data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32

1864

data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32

1865

| gma_read32(hw, port, GM_TXO_OK_LO);

1865

| gma_read32(hw, port, GM_TXO_OK_LO);

1866

data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32

1866

data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32

1867

| gma_read32(hw, port, GM_RXO_OK_LO);

1867

| gma_read32(hw, port, GM_RXO_OK_LO);

1868

1869

for (i = 2; i < ARRAY_SIZE(skge_stats); i++)

1869

for (i = 2; i < ARRAY_SIZE(skge_stats); i++)

1870

data[i] = gma_read32(hw, port,

1870

data[i] = gma_read32(hw, port,

1871

skge_stats[i].gma_offset);

1871

skge_stats[i].gma_offset);

1872

}

1872

}

1873

1874

static void yukon_mac_intr(struct skge_hw *hw, int port)

1874

static void yukon_mac_intr(struct skge_hw *hw, int port)

1875

{

1875

{

1876

struct net_device *dev = hw->dev[port];

1876

struct net_device *dev = hw->dev[port];

1877

struct skge_port *skge = netdev_priv(dev);

1877

struct skge_port *skge = netdev_priv(dev);

1878

u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));

1878

u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));

1879

1880

if (netif_msg_intr(skge))

1880

if (netif_msg_intr(skge))

1881

printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",

1881

printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",

1882

dev->name, status);

1882

dev->name, status);

1883

1884

if (status & GM_IS_RX_FF_OR) {

1884

if (status & GM_IS_RX_FF_OR) {

1885

++skge->net_stats.rx_fifo_errors;

1885

++skge->net_stats.rx_fifo_errors;

1886

skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);

1886

skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);

1887

}

1887

}

1888

1889

if (status & GM_IS_TX_FF_UR) {

1889

if (status & GM_IS_TX_FF_UR) {

1890

++skge->net_stats.tx_fifo_errors;

1890

++skge->net_stats.tx_fifo_errors;

1891

skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);

1891

skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);

1892

}

1892

}

1893

1894

}

1894

}

1895

1896

static u16 yukon_speed(const struct skge_hw *hw, u16 aux)

1896

static u16 yukon_speed(const struct skge_hw *hw, u16 aux)

1897

{

1897

{

1898

switch (aux & PHY_M_PS_SPEED_MSK) {

1898

switch (aux & PHY_M_PS_SPEED_MSK) {

1899

case PHY_M_PS_SPEED_1000:

1899

case PHY_M_PS_SPEED_1000:

1900

return SPEED_1000;

1900

return SPEED_1000;

1901

case PHY_M_PS_SPEED_100:

1901

case PHY_M_PS_SPEED_100:

1902

return SPEED_100;

1902

return SPEED_100;

1903

default:

1903

default:

1904

return SPEED_10;

1904

return SPEED_10;

1905

}

1905

}

1906

}

1906

}

1907

1908

static void yukon_link_up(struct skge_port *skge)

1908

static void yukon_link_up(struct skge_port *skge)

1909

{

1909

{

1910

struct skge_hw *hw = skge->hw;

1910

struct skge_hw *hw = skge->hw;

1911

int port = skge->port;

1911

int port = skge->port;

1912

u16 reg;

1912

u16 reg;

1913

1914

/* Enable Transmit FIFO Underrun */

1914

/* Enable Transmit FIFO Underrun */

1915

skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);

1915

skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);

1916

1917

reg = gma_read16(hw, port, GM_GP_CTRL);

1917

reg = gma_read16(hw, port, GM_GP_CTRL);

1918

if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)

1918

if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)

1919

reg |= GM_GPCR_DUP_FULL;

1919

reg |= GM_GPCR_DUP_FULL;

1920

1921

/* enable Rx/Tx */

1921

/* enable Rx/Tx */

1922

reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;

1922

reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;

1923

gma_write16(hw, port, GM_GP_CTRL, reg);

1923

gma_write16(hw, port, GM_GP_CTRL, reg);

1924

1925

gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);

1925

gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);

1926

skge_link_up(skge);

1926

skge_link_up(skge);

1927

}

1927

}

1928

1929

static void yukon_link_down(struct skge_port *skge)

1929

static void yukon_link_down(struct skge_port *skge)

1930

{

1930

{

1931

struct skge_hw *hw = skge->hw;

1931

struct skge_hw *hw = skge->hw;

1932

int port = skge->port;

1932

int port = skge->port;

1933

u16 ctrl;

1933

u16 ctrl;

1934

1935

gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);

1935

gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);

1936

1937

ctrl = gma_read16(hw, port, GM_GP_CTRL);

1937

ctrl = gma_read16(hw, port, GM_GP_CTRL);

1938

ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);

1938

ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);

1939

gma_write16(hw, port, GM_GP_CTRL, ctrl);

1939

gma_write16(hw, port, GM_GP_CTRL, ctrl);

1940

1941

if (skge->flow_control == FLOW_MODE_REM_SEND) {

1941

if (skge->flow_control == FLOW_MODE_REM_SEND) {

1942

/* restore Asymmetric Pause bit */

1942

/* restore Asymmetric Pause bit */

1943

gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,

1943

gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,

1944

gm_phy_read(hw, port,

1944

gm_phy_read(hw, port,

1945

PHY_MARV_AUNE_ADV)

1945

PHY_MARV_AUNE_ADV)

1946

| PHY_M_AN_ASP);

1946

| PHY_M_AN_ASP);

1947

1948

}

1948

}

1949

1950

yukon_reset(hw, port);

1950

yukon_reset(hw, port);

1951

skge_link_down(skge);

1951

skge_link_down(skge);

1952

1953

yukon_init(hw, port);

1953

yukon_init(hw, port);

1954

}

1954

}

1955

1956

static void yukon_phy_intr(struct skge_port *skge)

1956

static void yukon_phy_intr(struct skge_port *skge)

1957

{

1957

{

1958

struct skge_hw *hw = skge->hw;

1958

struct skge_hw *hw = skge->hw;

1959

int port = skge->port;

1959

int port = skge->port;

1960

const char *reason = NULL;

1960

const char *reason = NULL;

1961

u16 istatus, phystat;

1961

u16 istatus, phystat;

1962

1963

istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);

1963

istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);

1964

phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);

1964

phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);

1965

1966

if (netif_msg_intr(skge))

1966

if (netif_msg_intr(skge))

1967

printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x 0x%x\n",

1967

printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x 0x%x\n",

1968

skge->netdev->name, istatus, phystat);

1968

skge->netdev->name, istatus, phystat);

1969

1970

if (istatus & PHY_M_IS_AN_COMPL) {

1970

if (istatus & PHY_M_IS_AN_COMPL) {

1971

if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)

1971

if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)

1972

& PHY_M_AN_RF) {

1972

& PHY_M_AN_RF) {

1973

reason = "remote fault";

1973

reason = "remote fault";

1974

goto failed;

1974

goto failed;

1975

}

1975

}

1976

1977

if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {

1977

if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {

1978

reason = "master/slave fault";

1978

reason = "master/slave fault";

1979

goto failed;

1979

goto failed;

1980

}

1980

}

1981

1982

if (!(phystat & PHY_M_PS_SPDUP_RES)) {

1982

if (!(phystat & PHY_M_PS_SPDUP_RES)) {

1983

reason = "speed/duplex";

1983

reason = "speed/duplex";

1984

goto failed;

1984

goto failed;

1985

}

1985

}

1986

1987

skge->duplex = (phystat & PHY_M_PS_FULL_DUP)

1987

skge->duplex = (phystat & PHY_M_PS_FULL_DUP)

1988

? DUPLEX_FULL : DUPLEX_HALF;

1988

? DUPLEX_FULL : DUPLEX_HALF;

1989

skge->speed = yukon_speed(hw, phystat);

1989

skge->speed = yukon_speed(hw, phystat);

1990

1991

/* We are using IEEE 802.3z/D5.0 Table 37-4 */

1991

/* We are using IEEE 802.3z/D5.0 Table 37-4 */

1992

switch (phystat & PHY_M_PS_PAUSE_MSK) {

1992

switch (phystat & PHY_M_PS_PAUSE_MSK) {

1993

case PHY_M_PS_PAUSE_MSK:

1993

case PHY_M_PS_PAUSE_MSK:

1994

skge->flow_control = FLOW_MODE_SYMMETRIC;

1994

skge->flow_control = FLOW_MODE_SYMMETRIC;

1995

break;

1995

break;

1996

case PHY_M_PS_RX_P_EN:

1996

case PHY_M_PS_RX_P_EN:

1997

skge->flow_control = FLOW_MODE_REM_SEND;

1997

skge->flow_control = FLOW_MODE_REM_SEND;

1998

break;

1998

break;

1999

case PHY_M_PS_TX_P_EN:

1999

case PHY_M_PS_TX_P_EN:

2000

skge->flow_control = FLOW_MODE_LOC_SEND;

2000

skge->flow_control = FLOW_MODE_LOC_SEND;

2001

break;

2001

break;

2002

default:

2002

default:

2003

skge->flow_control = FLOW_MODE_NONE;

2003

skge->flow_control = FLOW_MODE_NONE;

2004

}

2004

}

2005

2006

if (skge->flow_control == FLOW_MODE_NONE ||

2006

if (skge->flow_control == FLOW_MODE_NONE ||

2007

(skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))

2007

(skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))

2008

skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);

2008

skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);

2009

else

2009

else

2010

skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);

2010

skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);

2011

yukon_link_up(skge);

2011

yukon_link_up(skge);

2012

return;

2012

return;

2013

}

2013

}

2014

2015

if (istatus & PHY_M_IS_LSP_CHANGE)

2015

if (istatus & PHY_M_IS_LSP_CHANGE)

2016

skge->speed = yukon_speed(hw, phystat);

2016

skge->speed = yukon_speed(hw, phystat);

2017

2018

if (istatus & PHY_M_IS_DUP_CHANGE)

2018

if (istatus & PHY_M_IS_DUP_CHANGE)

2019

skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;

2019

skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;

2020

if (istatus & PHY_M_IS_LST_CHANGE) {

2020

if (istatus & PHY_M_IS_LST_CHANGE) {

2021

if (phystat & PHY_M_PS_LINK_UP)

2021

if (phystat & PHY_M_PS_LINK_UP)

2022

yukon_link_up(skge);

2022

yukon_link_up(skge);

2023

else

2023

else

2024

yukon_link_down(skge);

2024

yukon_link_down(skge);

2025

}

2025

}

2026

return;

2026

return;

2027

failed:

2027

failed:

2028

printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n",

2028

printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n",

2029

skge->netdev->name, reason);

2029

skge->netdev->name, reason);

2030

2031

/* XXX restart autonegotiation? */

2031

/* XXX restart autonegotiation? */

2032

}

2032

}

2033

2034

static void skge_phy_reset(struct skge_port *skge)

2034

static void skge_phy_reset(struct skge_port *skge)

2035

{

2035

{

2036

struct skge_hw *hw = skge->hw;

2036

struct skge_hw *hw = skge->hw;

2037

int port = skge->port;

2037

int port = skge->port;

2038

2039

netif_stop_queue(skge->netdev);

2039

netif_stop_queue(skge->netdev);

2040

netif_carrier_off(skge->netdev);

2040

netif_carrier_off(skge->netdev);

2041

2042

spin_lock_bh(&hw->phy_lock);

2042

spin_lock_bh(&hw->phy_lock);

2043

if (hw->chip_id == CHIP_ID_GENESIS) {

2043

if (hw->chip_id == CHIP_ID_GENESIS) {

2044

genesis_reset(hw, port);

2044

genesis_reset(hw, port);

2045

genesis_mac_init(hw, port);

2045

genesis_mac_init(hw, port);

2046

} else {

2046

} else {

2047

yukon_reset(hw, port);

2047

yukon_reset(hw, port);

2048

yukon_init(hw, port);

2048

yukon_init(hw, port);

2049

}

2049

}

2050

spin_unlock_bh(&hw->phy_lock);

2050

spin_unlock_bh(&hw->phy_lock);

2051

}

2051

}

2052

2053

/* Basic MII support */

2053

/* Basic MII support */

2054

static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)

2054

static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)

2055

{

2055

{

2056

struct mii_ioctl_data *data = if_mii(ifr);

2056

struct mii_ioctl_data *data = if_mii(ifr);

2057

struct skge_port *skge = netdev_priv(dev);

2057

struct skge_port *skge = netdev_priv(dev);

2058

struct skge_hw *hw = skge->hw;

2058

struct skge_hw *hw = skge->hw;

2059

int err = -EOPNOTSUPP;

2059

int err = -EOPNOTSUPP;

2060

2061

if (!netif_running(dev))

2061

if (!netif_running(dev))

2062

return -ENODEV; /* Phy still in reset */

2062

return -ENODEV; /* Phy still in reset */

2063

2064

switch(cmd) {

2064

switch(cmd) {

2065

case SIOCGMIIPHY:

2065

case SIOCGMIIPHY:

2066

data->phy_id = hw->phy_addr;

2066

data->phy_id = hw->phy_addr;

2067

2068

/* fallthru */

2068

/* fallthru */

2069

case SIOCGMIIREG: {

2069

case SIOCGMIIREG: {

2070

u16 val = 0;

2070

u16 val = 0;

2071

spin_lock_bh(&hw->phy_lock);

2071

spin_lock_bh(&hw->phy_lock);

2072

if (hw->chip_id == CHIP_ID_GENESIS)

2072

if (hw->chip_id == CHIP_ID_GENESIS)

2073

err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);

2073

err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);

2074

else

2074

else

2075

err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);

2075

err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);

2076

spin_unlock_bh(&hw->phy_lock);

2076

spin_unlock_bh(&hw->phy_lock);

2077

data->val_out = val;

2077

data->val_out = val;

2078

break;

2078

break;

2079

}

2079

}

2080

2081

case SIOCSMIIREG:

2081

case SIOCSMIIREG:

2082

if (!capable(CAP_NET_ADMIN))

2082

if (!capable(CAP_NET_ADMIN))

2083

return -EPERM;

2083

return -EPERM;

2084

2085

spin_lock_bh(&hw->phy_lock);

2085

spin_lock_bh(&hw->phy_lock);

2086

if (hw->chip_id == CHIP_ID_GENESIS)

2086

if (hw->chip_id == CHIP_ID_GENESIS)

2087

err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,

2087

err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,

2088

data->val_in);

2088

data->val_in);

2089

else

2089

else

2090

err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,

2090

err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,

2091

data->val_in);

2091

data->val_in);

2092

spin_unlock_bh(&hw->phy_lock);

2092

spin_unlock_bh(&hw->phy_lock);

2093

break;

2093

break;

2094

}

2094

}

2095

return err;

2095

return err;

2096

}

2096

}

2097

2098

static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)

2098

static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)

2099

{

2099

{

2100

u32 end;

2100

u32 end;

2101

2102

start /= 8;

2102

start /= 8;

2103

len /= 8;

2103

len /= 8;

2104

end = start + len - 1;

2104

end = start + len - 1;

2105

2106

skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);

2106

skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);

2107

skge_write32(hw, RB_ADDR(q, RB_START), start);

2107

skge_write32(hw, RB_ADDR(q, RB_START), start);

2108

skge_write32(hw, RB_ADDR(q, RB_WP), start);

2108

skge_write32(hw, RB_ADDR(q, RB_WP), start);

2109

skge_write32(hw, RB_ADDR(q, RB_RP), start);

2109

skge_write32(hw, RB_ADDR(q, RB_RP), start);

2110

skge_write32(hw, RB_ADDR(q, RB_END), end);

2110

skge_write32(hw, RB_ADDR(q, RB_END), end);

2111

2112

if (q == Q_R1 || q == Q_R2) {

2112

if (q == Q_R1 || q == Q_R2) {

2113

/* Set thresholds on receive queue's */

2113

/* Set thresholds on receive queue's */

2114

skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),

2114

skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),

2115

start + (2*len)/3);

2115

start + (2*len)/3);

2116

skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),

2116

skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),

2117

start + (len/3));

2117

start + (len/3));

2118

} else {

2118

} else {

2119

/* Enable store & forward on Tx queue's because

2119

/* Enable store & forward on Tx queue's because

2120

* Tx FIFO is only 4K on Genesis and 1K on Yukon

2120

* Tx FIFO is only 4K on Genesis and 1K on Yukon

2121

*/

2121

*/

2122

skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);

2122

skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);

2123

}

2123

}

2124

2125

skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);

2125

skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);

2126

}

2126

}

2127

2128

/* Setup Bus Memory Interface */

2128

/* Setup Bus Memory Interface */

2129

static void skge_qset(struct skge_port *skge, u16 q,

2129

static void skge_qset(struct skge_port *skge, u16 q,

2130

const struct skge_element *e)

2130

const struct skge_element *e)

2131

{

2131

{

2132

struct skge_hw *hw = skge->hw;

2132

struct skge_hw *hw = skge->hw;

2133

u32 watermark = 0x600;

2133

u32 watermark = 0x600;

2134

u64 base = skge->dma + (e->desc - skge->mem);

2134

u64 base = skge->dma + (e->desc - skge->mem);

2135

2136

/* optimization to reduce window on 32bit/33mhz */

2136

/* optimization to reduce window on 32bit/33mhz */

2137

if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)

2137

if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)

2138

watermark /= 2;

2138

watermark /= 2;

2139

2140

skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);

2140

skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);

2141

skge_write32(hw, Q_ADDR(q, Q_F), watermark);

2141

skge_write32(hw, Q_ADDR(q, Q_F), watermark);

2142

skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));

2142

skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));

2143

skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);

2143

skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);

2144

}

2144

}

2145

2146

static int skge_up(struct net_device *dev)

2146

static int skge_up(struct net_device *dev)

2147

{

2147

{

2148

struct skge_port *skge = netdev_priv(dev);

2148

struct skge_port *skge = netdev_priv(dev);

2149

struct skge_hw *hw = skge->hw;

2149

struct skge_hw *hw = skge->hw;

2150

int port = skge->port;

2150

int port = skge->port;

2151

u32 chunk, ram_addr;

2151

u32 chunk, ram_addr;

2152

size_t rx_size, tx_size;

2152

size_t rx_size, tx_size;

2153

int err;

2153

int err;

2154

2155

if (netif_msg_ifup(skge))

2155

if (netif_msg_ifup(skge))

2156

printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);

2156

printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);

2157

2158

if (dev->mtu > RX_BUF_SIZE)

2158

if (dev->mtu > RX_BUF_SIZE)

2159

skge->rx_buf_size = dev->mtu + ETH_HLEN + NET_IP_ALIGN;

2159

skge->rx_buf_size = dev->mtu + ETH_HLEN + NET_IP_ALIGN;

2160

else

2160

else

2161

skge->rx_buf_size = RX_BUF_SIZE;

2161

skge->rx_buf_size = RX_BUF_SIZE;

2162

2163

2164

rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);

2164

rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);

2165

tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);

2165

tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);

2166

skge->mem_size = tx_size + rx_size;

2166

skge->mem_size = tx_size + rx_size;

2167

skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);

2167

skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);

2168

if (!skge->mem)

2168

if (!skge->mem)

2169

return -ENOMEM;

2169

return -ENOMEM;

2170

2171

BUG_ON(skge->dma & 7);

2171

BUG_ON(skge->dma & 7);

2172

2173

if ((u64)skge->dma >> 32 != ((u64) skge->dma + skge->mem_size) >> 32) {

2173

if ((u64)skge->dma >> 32 != ((u64) skge->dma + skge->mem_size) >> 32) {

2174

printk(KERN_ERR PFX "pci_alloc_consistent region crosses 4G boundary\n");

2174

printk(KERN_ERR PFX "pci_alloc_consistent region crosses 4G boundary\n");

2175

err = -EINVAL;

2175

err = -EINVAL;

2176

goto free_pci_mem;

2176

goto free_pci_mem;

2177

}

2177

}

2178

2179

memset(skge->mem, 0, skge->mem_size);

2179

memset(skge->mem, 0, skge->mem_size);

2180

2181

if ((err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma)))

2181

if ((err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma)))

2182

goto free_pci_mem;

2182

goto free_pci_mem;

2183

2184

err = skge_rx_fill(skge);

2184

err = skge_rx_fill(skge);

2185

if (err)

2185

if (err)

2186

goto free_rx_ring;

2186

goto free_rx_ring;

2187

2188

if ((err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,

2188

if ((err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,

2189

skge->dma + rx_size)))

2189

skge->dma + rx_size)))

2190

goto free_rx_ring;

2190

goto free_rx_ring;

2191

2192

skge->tx_avail = skge->tx_ring.count - 1;

2192

skge->tx_avail = skge->tx_ring.count - 1;

2193

2194

/* Initialize MAC */

2194

/* Initialize MAC */

2195

spin_lock_bh(&hw->phy_lock);

2195

spin_lock_bh(&hw->phy_lock);

2196

if (hw->chip_id == CHIP_ID_GENESIS)

2196

if (hw->chip_id == CHIP_ID_GENESIS)

2197

genesis_mac_init(hw, port);

2197

genesis_mac_init(hw, port);

2198

else

2198

else

2199

yukon_mac_init(hw, port);

2199

yukon_mac_init(hw, port);

2200

spin_unlock_bh(&hw->phy_lock);

2200

spin_unlock_bh(&hw->phy_lock);

2201

2202

/* Configure RAMbuffers */

2202

/* Configure RAMbuffers */

2203

chunk = hw->ram_size / ((hw->ports + 1)*2);

2203

chunk = hw->ram_size / ((hw->ports + 1)*2);

2204

ram_addr = hw->ram_offset + 2 * chunk * port;

2204

ram_addr = hw->ram_offset + 2 * chunk * port;

2205

2206

skge_ramset(hw, rxqaddr[port], ram_addr, chunk);

2206

skge_ramset(hw, rxqaddr[port], ram_addr, chunk);

2207

skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);

2207

skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);

2208

2209

BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);

2209

BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);

2210

skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);

2210

skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);

2211

skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);

2211

skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);

2212

2213

/* Start receiver BMU */

2213

/* Start receiver BMU */

2214

wmb();

2214

wmb();

2215

skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);

2215

skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);

2216

skge_led(skge, LED_MODE_ON);

2216

skge_led(skge, LED_MODE_ON);

2217

2218

return 0;

2218

return 0;

2219

2220

free_rx_ring:

2220

free_rx_ring:

2221

skge_rx_clean(skge);

2221

skge_rx_clean(skge);

2222

kfree(skge->rx_ring.start);

2222

kfree(skge->rx_ring.start);

2223

free_pci_mem:

2223

free_pci_mem:

2224

pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);

2224

pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);

2225

skge->mem = NULL;

2225

skge->mem = NULL;

2226

2227

return err;

2227

return err;

2228

}

2228

}

2229

2230

static int skge_down(struct net_device *dev)

2230

static int skge_down(struct net_device *dev)

2231

{

2231

{

2232

struct skge_port *skge = netdev_priv(dev);

2232

struct skge_port *skge = netdev_priv(dev);

2233

struct skge_hw *hw = skge->hw;

2233

struct skge_hw *hw = skge->hw;

2234

int port = skge->port;

2234

int port = skge->port;

2235

2236

if (skge->mem == NULL)

2236

if (skge->mem == NULL)

2237

return 0;

2237

return 0;

2238

2239

if (netif_msg_ifdown(skge))

2239

if (netif_msg_ifdown(skge))

2240

printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);

2240

printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);

2241

2242

netif_stop_queue(dev);

2242

netif_stop_queue(dev);

2243

2244

skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);

2244

skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);

2245

if (hw->chip_id == CHIP_ID_GENESIS)

2245

if (hw->chip_id == CHIP_ID_GENESIS)

2246

genesis_stop(skge);

2246

genesis_stop(skge);

2247

else

2247

else

2248

yukon_stop(skge);

2248

yukon_stop(skge);

2249

2250

/* Stop transmitter */

2250

/* Stop transmitter */

2251

skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);

2251

skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);

2252

skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),

2252

skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),

2253

RB_RST_SET|RB_DIS_OP_MD);

2253

RB_RST_SET|RB_DIS_OP_MD);

2254

2255

2256

/* Disable Force Sync bit and Enable Alloc bit */

2256

/* Disable Force Sync bit and Enable Alloc bit */

2257

skge_write8(hw, SK_REG(port, TXA_CTRL),

2257

skge_write8(hw, SK_REG(port, TXA_CTRL),

2258

TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);

2258

TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);

2259

2260

/* Stop Interval Timer and Limit Counter of Tx Arbiter */

2260

/* Stop Interval Timer and Limit Counter of Tx Arbiter */

2261

skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);

2261

skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);

2262

skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);

2262

skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);

2263

2264

/* Reset PCI FIFO */

2264

/* Reset PCI FIFO */

2265

skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);

2265

skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);

2266

skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);

2266

skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);

2267

2268

/* Reset the RAM Buffer async Tx queue */

2268

/* Reset the RAM Buffer async Tx queue */

2269

skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);

2269

skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);

2270

/* stop receiver */

2270

/* stop receiver */

2271

skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);

2271

skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);

2272

skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),

2272

skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),

2273

RB_RST_SET|RB_DIS_OP_MD);

2273

RB_RST_SET|RB_DIS_OP_MD);

2274

skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);

2274

skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);

2275

2276

if (hw->chip_id == CHIP_ID_GENESIS) {

2276

if (hw->chip_id == CHIP_ID_GENESIS) {

2277

skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);

2277

skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);

2278

skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);

2278

skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);

2279

} else {

2279

} else {

2280

skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);

2280

skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);

2281

skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);

2281

skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);

2282

}

2282

}

2283

2284

skge_led(skge, LED_MODE_OFF);

2284

skge_led(skge, LED_MODE_OFF);

2285

2286

skge_tx_clean(skge);

2286

skge_tx_clean(skge);

2287

skge_rx_clean(skge);

2287

skge_rx_clean(skge);

2288

2289

kfree(skge->rx_ring.start);

2289

kfree(skge->rx_ring.start);

2290

kfree(skge->tx_ring.start);

2290

kfree(skge->tx_ring.start);

2291

pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);

2291

pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);

2292

skge->mem = NULL;

2292

skge->mem = NULL;

2293

return 0;

2293

return 0;

2294

}

2294

}

2295

2296

static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)

2296

static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)

2297

{

2297

{

2298

struct skge_port *skge = netdev_priv(dev);

2298

struct skge_port *skge = netdev_priv(dev);

2299

struct skge_hw *hw = skge->hw;

2299

struct skge_hw *hw = skge->hw;

2300

struct skge_ring *ring = &skge->tx_ring;

2300

struct skge_ring *ring = &skge->tx_ring;

2301

struct skge_element *e;

2301

struct skge_element *e;

2302

struct skge_tx_desc *td;

2302

struct skge_tx_desc *td;

2303

int i;

2303

int i;

2304

u32 control, len;

2304

u32 control, len;

2305

u64 map;

2305

u64 map;

2306

2307

skb = skb_padto(skb, ETH_ZLEN);

2307

skb = skb_padto(skb, ETH_ZLEN);

2308

if (!skb)

2308

if (!skb)

2309

return NETDEV_TX_OK;

2309

return NETDEV_TX_OK;

2310

2311

if (!spin_trylock(&skge->tx_lock)) {

2311

if (!spin_trylock(&skge->tx_lock)) {

2312

/* Collision - tell upper layer to requeue */

2312

/* Collision - tell upper layer to requeue */

2313

return NETDEV_TX_LOCKED;

2313

return NETDEV_TX_LOCKED;

2314

}

2314

}

2315

2316

if (unlikely(skge->tx_avail < skb_shinfo(skb)->nr_frags +1)) {

2316

if (unlikely(skge->tx_avail < skb_shinfo(skb)->nr_frags +1)) {

2317

if (!netif_queue_stopped(dev)) {

2317

if (!netif_queue_stopped(dev)) {

2318

netif_stop_queue(dev);

2318

netif_stop_queue(dev);

2319

2320

printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",

2320

printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",

2321

dev->name);

2321

dev->name);

2322

}

2322

}

2323

spin_unlock(&skge->tx_lock);

2323

spin_unlock(&skge->tx_lock);

2324

return NETDEV_TX_BUSY;

2324

return NETDEV_TX_BUSY;

2325

}

2325

}

2326

2327

e = ring->to_use;

2327

e = ring->to_use;

2328

td = e->desc;

2328

td = e->desc;

2329

e->skb = skb;

2329

e->skb = skb;

2330

len = skb_headlen(skb);

2330

len = skb_headlen(skb);

2331

map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);

2331

map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);

2332

pci_unmap_addr_set(e, mapaddr, map);

2332

pci_unmap_addr_set(e, mapaddr, map);

2333

pci_unmap_len_set(e, maplen, len);

2333

pci_unmap_len_set(e, maplen, len);

2334

2335

td->dma_lo = map;

2335

td->dma_lo = map;

2336

td->dma_hi = map >> 32;

2336

td->dma_hi = map >> 32;

2337

2338

if (skb->ip_summed == CHECKSUM_HW) {

2338

if (skb->ip_summed == CHECKSUM_HW) {

2339

int offset = skb->h.raw - skb->data;

2339

int offset = skb->h.raw - skb->data;

2340

2341

/* This seems backwards, but it is what the sk98lin

2341

/* This seems backwards, but it is what the sk98lin

2342

* does. Looks like hardware is wrong?

2342

* does. Looks like hardware is wrong?

2343

*/

2343

*/

2344

if (skb->h.ipiph->protocol == IPPROTO_UDP

2344

if (skb->h.ipiph->protocol == IPPROTO_UDP

2345

&& hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)

2345

&& hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)

2346

control = BMU_TCP_CHECK;

2346

control = BMU_TCP_CHECK;

2347

else

2347

else

2348

control = BMU_UDP_CHECK;

2348

control = BMU_UDP_CHECK;

2349

2350

td->csum_offs = 0;

2350

td->csum_offs = 0;

2351

td->csum_start = offset;

2351

td->csum_start = offset;

2352

td->csum_write = offset + skb->csum;

2352

td->csum_write = offset + skb->csum;

2353

} else

2353

} else

2354

control = BMU_CHECK;

2354

control = BMU_CHECK;

2355

2356

if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */

2356

if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */

2357

control |= BMU_EOF| BMU_IRQ_EOF;

2357

control |= BMU_EOF| BMU_IRQ_EOF;

2358

else {

2358

else {

2359

struct skge_tx_desc *tf = td;

2359

struct skge_tx_desc *tf = td;

2360

2361

control |= BMU_STFWD;

2361

control |= BMU_STFWD;

2362

for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {

2362

for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {

2363

skb_frag_t *frag = &skb_shinfo(skb)->frags[i];

2363

skb_frag_t *frag = &skb_shinfo(skb)->frags[i];

2364

2365

map = pci_map_page(hw->pdev, frag->page, frag->page_offset,

2365

map = pci_map_page(hw->pdev, frag->page, frag->page_offset,

2366

frag->size, PCI_DMA_TODEVICE);

2366

frag->size, PCI_DMA_TODEVICE);

2367

2368

e = e->next;

2368

e = e->next;

2369

e->skb = NULL;

2369

e->skb = NULL;

2370

tf = e->desc;

2370

tf = e->desc;

2371

tf->dma_lo = map;

2371

tf->dma_lo = map;

2372

tf->dma_hi = (u64) map >> 32;

2372

tf->dma_hi = (u64) map >> 32;

2373

pci_unmap_addr_set(e, mapaddr, map);

2373

pci_unmap_addr_set(e, mapaddr, map);

2374

pci_unmap_len_set(e, maplen, frag->size);

2374

pci_unmap_len_set(e, maplen, frag->size);

2375

2376

tf->control = BMU_OWN | BMU_SW | control | frag->size;

2376

tf->control = BMU_OWN | BMU_SW | control | frag->size;

2377

}

2377

}

2378

tf->control |= BMU_EOF | BMU_IRQ_EOF;

2378

tf->control |= BMU_EOF | BMU_IRQ_EOF;

2379

}

2379

}

2380

/* Make sure all the descriptors written */

2380

/* Make sure all the descriptors written */

2381

wmb();

2381

wmb();

2382

td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;

2382

td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;

2383

wmb();

2383

wmb();

2384

2385

skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);

2385

skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);

2386

2387

if (netif_msg_tx_queued(skge))

2387

if (netif_msg_tx_queued(skge))

2388

printk(KERN_DEBUG "%s: tx queued, slot %td, len %d\n",

2388

printk(KERN_DEBUG "%s: tx queued, slot %td, len %d\n",

2389

dev->name, e - ring->start, skb->len);

2389

dev->name, e - ring->start, skb->len);

2390

2391

ring->to_use = e->next;

2391

ring->to_use = e->next;

2392

skge->tx_avail -= skb_shinfo(skb)->nr_frags + 1;

2392

skge->tx_avail -= skb_shinfo(skb)->nr_frags + 1;

2393

if (skge->tx_avail <= MAX_SKB_FRAGS + 1) {

2393

if (skge->tx_avail <= MAX_SKB_FRAGS + 1) {

2394

pr_debug("%s: transmit queue full\n", dev->name);

2394

pr_debug("%s: transmit queue full\n", dev->name);

2395

netif_stop_queue(dev);

2395

netif_stop_queue(dev);

2396

}

2396

}

2397

2398

dev->trans_start = jiffies;

2398

dev->trans_start = jiffies;

2399

spin_unlock(&skge->tx_lock);

2399

spin_unlock(&skge->tx_lock);

2400

2401

return NETDEV_TX_OK;

2401

return NETDEV_TX_OK;

2402

}

2402

}

2403

2404

static inline void skge_tx_free(struct skge_hw *hw, struct skge_element *e)

2404

static inline void skge_tx_free(struct skge_hw *hw, struct skge_element *e)

2405

{

2405

{

2406

/* This ring element can be skb or fragment */

2406

/* This ring element can be skb or fragment */

2407

if (e->skb) {

2407

if (e->skb) {

2408

pci_unmap_single(hw->pdev,

2408

pci_unmap_single(hw->pdev,

2409

pci_unmap_addr(e, mapaddr),

2409

pci_unmap_addr(e, mapaddr),

2410

pci_unmap_len(e, maplen),

2410

pci_unmap_len(e, maplen),

2411

PCI_DMA_TODEVICE);

2411

PCI_DMA_TODEVICE);

2412

dev_kfree_skb(e->skb);

2412

dev_kfree_skb(e->skb);

2413

e->skb = NULL;

2413

e->skb = NULL;

2414

} else {

2414

} else {

2415

pci_unmap_page(hw->pdev,

2415

pci_unmap_page(hw->pdev,

2416

pci_unmap_addr(e, mapaddr),

2416

pci_unmap_addr(e, mapaddr),

2417

pci_unmap_len(e, maplen),

2417

pci_unmap_len(e, maplen),

2418

PCI_DMA_TODEVICE);

2418

PCI_DMA_TODEVICE);

2419

}

2419

}

2420

}

2420

}

2421

2422

static void skge_tx_clean(struct skge_port *skge)

2422

static void skge_tx_clean(struct skge_port *skge)

2423

{

2423

{

2424

struct skge_ring *ring = &skge->tx_ring;

2424

struct skge_ring *ring = &skge->tx_ring;

2425

struct skge_element *e;

2425

struct skge_element *e;

2426

2427

spin_lock_bh(&skge->tx_lock);

2427

spin_lock_bh(&skge->tx_lock);

2428

for (e = ring->to_clean; e != ring->to_use; e = e->next) {

2428

for (e = ring->to_clean; e != ring->to_use; e = e->next) {

2429

++skge->tx_avail;

2429

++skge->tx_avail;

2430

skge_tx_free(skge->hw, e);

2430

skge_tx_free(skge->hw, e);

2431

}

2431

}

2432

ring->to_clean = e;

2432

ring->to_clean = e;

2433

spin_unlock_bh(&skge->tx_lock);

2433

spin_unlock_bh(&skge->tx_lock);

2434

}

2434

}

2435

2436

static void skge_tx_timeout(struct net_device *dev)

2436

static void skge_tx_timeout(struct net_device *dev)

2437

{

2437

{

2438

struct skge_port *skge = netdev_priv(dev);

2438

struct skge_port *skge = netdev_priv(dev);

2439

2440

if (netif_msg_timer(skge))

2440

if (netif_msg_timer(skge))

2441

printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name);

2441

printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name);

2442

2443

skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);

2443

skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);

2444

skge_tx_clean(skge);

2444

skge_tx_clean(skge);

2445

}

2445

}

2446

2447

static int skge_change_mtu(struct net_device *dev, int new_mtu)

2447

static int skge_change_mtu(struct net_device *dev, int new_mtu)

2448

{

2448

{

2449

int err;

2449

int err;

2450

2451

if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)

2451

if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)

2452

return -EINVAL;

2452

return -EINVAL;

2453

2454

if (!netif_running(dev)) {

2454

if (!netif_running(dev)) {

2455

dev->mtu = new_mtu;

2455

dev->mtu = new_mtu;

2456

return 0;

2456

return 0;

2457

}

2457

}

2458

2459

skge_down(dev);

2459

skge_down(dev);

2460

2461

dev->mtu = new_mtu;

2461

dev->mtu = new_mtu;

2462

2463

err = skge_up(dev);

2463

err = skge_up(dev);

2464

if (err)

2464

if (err)

2465

dev_close(dev);

2465

dev_close(dev);

2466

2467

return err;

2467

return err;

2468

}

2468

}

2469

2470

static void genesis_set_multicast(struct net_device *dev)

2470

static void genesis_set_multicast(struct net_device *dev)

2471

{

2471

{

2472

struct skge_port *skge = netdev_priv(dev);

2472

struct skge_port *skge = netdev_priv(dev);

2473

struct skge_hw *hw = skge->hw;

2473

struct skge_hw *hw = skge->hw;

2474

int port = skge->port;

2474

int port = skge->port;

2475

int i, count = dev->mc_count;

2475

int i, count = dev->mc_count;

2476

struct dev_mc_list *list = dev->mc_list;

2476

struct dev_mc_list *list = dev->mc_list;

2477

u32 mode;

2477

u32 mode;

2478

u8 filter[8];

2478

u8 filter[8];

2479

2480

mode = xm_read32(hw, port, XM_MODE);

2480

mode = xm_read32(hw, port, XM_MODE);

2481

mode |= XM_MD_ENA_HASH;

2481

mode |= XM_MD_ENA_HASH;

2482

if (dev->flags & IFF_PROMISC)

2482

if (dev->flags & IFF_PROMISC)

2483

mode |= XM_MD_ENA_PROM;

2483

mode |= XM_MD_ENA_PROM;

2484

else

2484

else

2485

mode &= ~XM_MD_ENA_PROM;

2485

mode &= ~XM_MD_ENA_PROM;

2486

2487

if (dev->flags & IFF_ALLMULTI)

2487

if (dev->flags & IFF_ALLMULTI)

2488

memset(filter, 0xff, sizeof(filter));

2488

memset(filter, 0xff, sizeof(filter));

2489

else {

2489

else {

2490

memset(filter, 0, sizeof(filter));

2490

memset(filter, 0, sizeof(filter));

2491

for (i = 0; list && i < count; i++, list = list->next) {

2491

for (i = 0; list && i < count; i++, list = list->next) {

2492

u32 crc, bit;

2492

u32 crc, bit;

2493

crc = ether_crc_le(ETH_ALEN, list->dmi_addr);

2493

crc = ether_crc_le(ETH_ALEN, list->dmi_addr);

2494

bit = ~crc & 0x3f;

2494

bit = ~crc & 0x3f;

2495

filter[bit/8] |= 1 << (bit%8);

2495

filter[bit/8] |= 1 << (bit%8);

2496

}

2496

}

2497

}

2497

}

2498

2499

xm_write32(hw, port, XM_MODE, mode);

2499

xm_write32(hw, port, XM_MODE, mode);

2500

xm_outhash(hw, port, XM_HSM, filter);

2500

xm_outhash(hw, port, XM_HSM, filter);

2501

}

2501

}

2502

2503

static void yukon_set_multicast(struct net_device *dev)

2503

static void yukon_set_multicast(struct net_device *dev)

2504

{

2504

{

2505

struct skge_port *skge = netdev_priv(dev);

2505

struct skge_port *skge = netdev_priv(dev);

2506

struct skge_hw *hw = skge->hw;

2506

struct skge_hw *hw = skge->hw;

2507

int port = skge->port;

2507

int port = skge->port;

2508

struct dev_mc_list *list = dev->mc_list;

2508

struct dev_mc_list *list = dev->mc_list;

2509

u16 reg;

2509

u16 reg;

2510

u8 filter[8];

2510

u8 filter[8];

2511

2512

memset(filter, 0, sizeof(filter));

2512

memset(filter, 0, sizeof(filter));

2513

2514

reg = gma_read16(hw, port, GM_RX_CTRL);

2514

reg = gma_read16(hw, port, GM_RX_CTRL);

2515

reg |= GM_RXCR_UCF_ENA;

2515

reg |= GM_RXCR_UCF_ENA;

2516

2517

if (dev->flags & IFF_PROMISC) /* promiscuous */

2517

if (dev->flags & IFF_PROMISC) /* promiscuous */

2518

reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);

2518

reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);

2519

else if (dev->flags & IFF_ALLMULTI) /* all multicast */

2519

else if (dev->flags & IFF_ALLMULTI) /* all multicast */

2520

memset(filter, 0xff, sizeof(filter));

2520

memset(filter, 0xff, sizeof(filter));

2521

else if (dev->mc_count == 0) /* no multicast */

2521

else if (dev->mc_count == 0) /* no multicast */

2522

reg &= ~GM_RXCR_MCF_ENA;

2522

reg &= ~GM_RXCR_MCF_ENA;

2523

else {

2523

else {

2524

int i;

2524

int i;

2525

reg |= GM_RXCR_MCF_ENA;

2525

reg |= GM_RXCR_MCF_ENA;

2526

2527

for (i = 0; list && i < dev->mc_count; i++, list = list->next) {

2527

for (i = 0; list && i < dev->mc_count; i++, list = list->next) {

2528

u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;

2528

u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;

2529

filter[bit/8] |= 1 << (bit%8);

2529

filter[bit/8] |= 1 << (bit%8);

2530

}

2530

}

2531

}

2531

}

2532

2533

2534

gma_write16(hw, port, GM_MC_ADDR_H1,

2534

gma_write16(hw, port, GM_MC_ADDR_H1,

2535

(u16)filter[0] | ((u16)filter[1] << 8));

2535

(u16)filter[0] | ((u16)filter[1] << 8));

2536

gma_write16(hw, port, GM_MC_ADDR_H2,

2536

gma_write16(hw, port, GM_MC_ADDR_H2,

2537

(u16)filter[2] | ((u16)filter[3] << 8));

2537

(u16)filter[2] | ((u16)filter[3] << 8));

2538

gma_write16(hw, port, GM_MC_ADDR_H3,

2538

gma_write16(hw, port, GM_MC_ADDR_H3,

2539

(u16)filter[4] | ((u16)filter[5] << 8));

2539

(u16)filter[4] | ((u16)filter[5] << 8));

2540

gma_write16(hw, port, GM_MC_ADDR_H4,

2540

gma_write16(hw, port, GM_MC_ADDR_H4,

2541

(u16)filter[6] | ((u16)filter[7] << 8));

2541

(u16)filter[6] | ((u16)filter[7] << 8));

2542

2543

gma_write16(hw, port, GM_RX_CTRL, reg);

2543

gma_write16(hw, port, GM_RX_CTRL, reg);

2544

}

2544

}

2545

2546

static inline u16 phy_length(const struct skge_hw *hw, u32 status)

2546

static inline u16 phy_length(const struct skge_hw *hw, u32 status)

2547

{

2547

{

2548

if (hw->chip_id == CHIP_ID_GENESIS)

2548

if (hw->chip_id == CHIP_ID_GENESIS)

2549

return status >> XMR_FS_LEN_SHIFT;

2549

return status >> XMR_FS_LEN_SHIFT;

2550

else

2550

else

2551

return status >> GMR_FS_LEN_SHIFT;

2551

return status >> GMR_FS_LEN_SHIFT;

2552

}

2552

}

2553

2554

static inline int bad_phy_status(const struct skge_hw *hw, u32 status)

2554

static inline int bad_phy_status(const struct skge_hw *hw, u32 status)

2555

{

2555

{

2556

if (hw->chip_id == CHIP_ID_GENESIS)

2556

if (hw->chip_id == CHIP_ID_GENESIS)

2557

return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;

2557

return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;

2558

else

2558

else

2559

return (status & GMR_FS_ANY_ERR) ||

2559

return (status & GMR_FS_ANY_ERR) ||

2560

(status & GMR_FS_RX_OK) == 0;

2560

(status & GMR_FS_RX_OK) == 0;

2561

}

2561

}

2562

2563

2564

/* Get receive buffer from descriptor.

2564

/* Get receive buffer from descriptor.

2565

* Handles copy of small buffers and reallocation failures

2565

* Handles copy of small buffers and reallocation failures

2566

*/

2566

*/

2567

static inline struct sk_buff *skge_rx_get(struct skge_port *skge,

2567

static inline struct sk_buff *skge_rx_get(struct skge_port *skge,

2568

struct skge_element *e,

2568

struct skge_element *e,

2569

u32 control, u32 status, u16 csum)

2569

u32 control, u32 status, u16 csum)

2570

{

2570

{

2571

struct sk_buff *skb;

2571

struct sk_buff *skb;

2572

u16 len = control & BMU_BBC;

2572

u16 len = control & BMU_BBC;

2573

2574

if (unlikely(netif_msg_rx_status(skge)))

2574

if (unlikely(netif_msg_rx_status(skge)))

2575

printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",

2575

printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",

2576

skge->netdev->name, e - skge->rx_ring.start,

2576

skge->netdev->name, e - skge->rx_ring.start,

2577

status, len);

2577

status, len);

2578

2579

if (len > skge->rx_buf_size)

2579

if (len > skge->rx_buf_size)

2580

goto error;

2580

goto error;

2581

2582

if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))

2582

if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))

2583

goto error;

2583

goto error;

2584

2585

if (bad_phy_status(skge->hw, status))

2585

if (bad_phy_status(skge->hw, status))

2586

goto error;

2586

goto error;

2587

2588

if (phy_length(skge->hw, status) != len)

2588

if (phy_length(skge->hw, status) != len)

2589

goto error;

2589

goto error;

2590

2591

if (len < RX_COPY_THRESHOLD) {

2591

if (len < RX_COPY_THRESHOLD) {

2592

skb = dev_alloc_skb(len + 2);

2592

skb = dev_alloc_skb(len + 2);

2593

if (!skb)

2593

if (!skb)

2594

goto resubmit;

2594

goto resubmit;

2595

2596

skb_reserve(skb, 2);

2596

skb_reserve(skb, 2);

2597

pci_dma_sync_single_for_cpu(skge->hw->pdev,

2597

pci_dma_sync_single_for_cpu(skge->hw->pdev,

2598

pci_unmap_addr(e, mapaddr),

2598

pci_unmap_addr(e, mapaddr),

2599

len, PCI_DMA_FROMDEVICE);

2599

len, PCI_DMA_FROMDEVICE);

2600

memcpy(skb->data, e->skb->data, len);

2600

memcpy(skb->data, e->skb->data, len);

2601

pci_dma_sync_single_for_device(skge->hw->pdev,

2601

pci_dma_sync_single_for_device(skge->hw->pdev,

2602

pci_unmap_addr(e, mapaddr),

2602

pci_unmap_addr(e, mapaddr),

2603

len, PCI_DMA_FROMDEVICE);

2603

len, PCI_DMA_FROMDEVICE);

2604

skge_rx_reuse(e, skge->rx_buf_size);

2604

skge_rx_reuse(e, skge->rx_buf_size);

2605

} else {

2605

} else {

2606

struct sk_buff *nskb;

2606

struct sk_buff *nskb;

2607

nskb = dev_alloc_skb(skge->rx_buf_size + NET_IP_ALIGN);

2607

nskb = dev_alloc_skb(skge->rx_buf_size + NET_IP_ALIGN);

2608

if (!nskb)

2608

if (!nskb)

2609

goto resubmit;

2609

goto resubmit;

2610

2611

pci_unmap_single(skge->hw->pdev,

2611

pci_unmap_single(skge->hw->pdev,

2612

pci_unmap_addr(e, mapaddr),

2612

pci_unmap_addr(e, mapaddr),

2613

pci_unmap_len(e, maplen),

2613

pci_unmap_len(e, maplen),

2614

PCI_DMA_FROMDEVICE);

2614

PCI_DMA_FROMDEVICE);

2615

skb = e->skb;

2615

skb = e->skb;

2616

prefetch(skb->data);

2616

prefetch(skb->data);

2617

skge_rx_setup(skge, e, nskb, skge->rx_buf_size);

2617

skge_rx_setup(skge, e, nskb, skge->rx_buf_size);

2618

}

2618

}

2619

2620

skb_put(skb, len);

2620

skb_put(skb, len);

2621

skb->dev = skge->netdev;

2621

skb->dev = skge->netdev;

2622

if (skge->rx_csum) {

2622

if (skge->rx_csum) {

2623

skb->csum = csum;

2623

skb->csum = csum;

2624

skb->ip_summed = CHECKSUM_HW;

2624

skb->ip_summed = CHECKSUM_HW;

2625

}

2625

}

2626

2627

skb->protocol = eth_type_trans(skb, skge->netdev);

2627

skb->protocol = eth_type_trans(skb, skge->netdev);

2628

2629

return skb;

2629

return skb;

2630

error:

2630

error:

2631

2632

if (netif_msg_rx_err(skge))

2632

if (netif_msg_rx_err(skge))

2633

printk(KERN_DEBUG PFX "%s: rx err, slot %td control 0x%x status 0x%x\n",

2633

printk(KERN_DEBUG PFX "%s: rx err, slot %td control 0x%x status 0x%x\n",

2634

skge->netdev->name, e - skge->rx_ring.start,

2634

skge->netdev->name, e - skge->rx_ring.start,

2635

control, status);

2635

control, status);

2636

2637

if (skge->hw->chip_id == CHIP_ID_GENESIS) {

2637

if (skge->hw->chip_id == CHIP_ID_GENESIS) {

2638

if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))

2638

if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))

2639

skge->net_stats.rx_length_errors++;

2639

skge->net_stats.rx_length_errors++;

2640

if (status & XMR_FS_FRA_ERR)

2640

if (status & XMR_FS_FRA_ERR)

2641

skge->net_stats.rx_frame_errors++;

2641

skge->net_stats.rx_frame_errors++;

2642

if (status & XMR_FS_FCS_ERR)

2642

if (status & XMR_FS_FCS_ERR)

2643

skge->net_stats.rx_crc_errors++;

2643

skge->net_stats.rx_crc_errors++;

2644

} else {

2644

} else {

2645

if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))

2645

if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))

2646

skge->net_stats.rx_length_errors++;

2646

skge->net_stats.rx_length_errors++;

2647

if (status & GMR_FS_FRAGMENT)

2647

if (status & GMR_FS_FRAGMENT)

2648

skge->net_stats.rx_frame_errors++;

2648

skge->net_stats.rx_frame_errors++;

2649

if (status & GMR_FS_CRC_ERR)

2649

if (status & GMR_FS_CRC_ERR)

2650

skge->net_stats.rx_crc_errors++;

2650

skge->net_stats.rx_crc_errors++;

2651

}

2651

}

2652

2653

resubmit:

2653

resubmit:

2654

skge_rx_reuse(e, skge->rx_buf_size);

2654

skge_rx_reuse(e, skge->rx_buf_size);

2655

return NULL;

2655

return NULL;

2656

}

2656

}

2657

2658

static void skge_tx_done(struct skge_port *skge)

2658

static void skge_tx_done(struct skge_port *skge)

2659

{

2659

{

2660

struct skge_ring *ring = &skge->tx_ring;

2660

struct skge_ring *ring = &skge->tx_ring;

2661

struct skge_element *e;

2661

struct skge_element *e;

2662

2663

spin_lock(&skge->tx_lock);

2663

spin_lock(&skge->tx_lock);

2664

for (e = ring->to_clean; prefetch(e->next), e != ring->to_use; e = e->next) {

2664

for (e = ring->to_clean; prefetch(e->next), e != ring->to_use; e = e->next) {

2665

struct skge_tx_desc *td = e->desc;

2665

struct skge_tx_desc *td = e->desc;

2666

u32 control;

2666

u32 control;

2667

2668

rmb();

2668

rmb();

2669

control = td->control;

2669

control = td->control;

2670

if (control & BMU_OWN)

2670

if (control & BMU_OWN)

2671

break;

2671

break;

2672

2673

if (unlikely(netif_msg_tx_done(skge)))

2673

if (unlikely(netif_msg_tx_done(skge)))

2674

printk(KERN_DEBUG PFX "%s: tx done slot %td status 0x%x\n",

2674

printk(KERN_DEBUG PFX "%s: tx done slot %td status 0x%x\n",

2675

skge->netdev->name, e - ring->start, td->status);

2675

skge->netdev->name, e - ring->start, td->status);

2676

2677

skge_tx_free(skge->hw, e);

2677

skge_tx_free(skge->hw, e);

2678

e->skb = NULL;

2678

e->skb = NULL;

2679

++skge->tx_avail;

2679

++skge->tx_avail;

2680

}

2680

}

2681

ring->to_clean = e;

2681

ring->to_clean = e;

2682

skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);

2682

skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);

2683

2684

if (skge->tx_avail > MAX_SKB_FRAGS + 1)

2684

if (skge->tx_avail > MAX_SKB_FRAGS + 1)

2685

netif_wake_queue(skge->netdev);

2685

netif_wake_queue(skge->netdev);

2686

2687

spin_unlock(&skge->tx_lock);

2687

spin_unlock(&skge->tx_lock);

2688

}

2688

}

2689

2690

static int skge_poll(struct net_device *dev, int *budget)

2690

static int skge_poll(struct net_device *dev, int *budget)

2691

{

2691

{

2692

struct skge_port *skge = netdev_priv(dev);

2692

struct skge_port *skge = netdev_priv(dev);

2693

struct skge_hw *hw = skge->hw;

2693

struct skge_hw *hw = skge->hw;

2694

struct skge_ring *ring = &skge->rx_ring;

2694

struct skge_ring *ring = &skge->rx_ring;

2695

struct skge_element *e;

2695

struct skge_element *e;

2696

int to_do = min(dev->quota, *budget);

2696

int to_do = min(dev->quota, *budget);

2697

int work_done = 0;

2697

int work_done = 0;

2698

2699

skge_tx_done(skge);

2699

skge_tx_done(skge);

2700

2701

for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) {

2701

for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) {

2702

struct skge_rx_desc *rd = e->desc;

2702

struct skge_rx_desc *rd = e->desc;

2703

struct sk_buff *skb;

2703

struct sk_buff *skb;

2704

u32 control;

2704

u32 control;

2705

2706

rmb();

2706

rmb();

2707

control = rd->control;

2707

control = rd->control;

2708

if (control & BMU_OWN)

2708

if (control & BMU_OWN)

2709

break;

2709

break;

2710

2711

skb = skge_rx_get(skge, e, control, rd->status,

2711

skb = skge_rx_get(skge, e, control, rd->status,

2712

le16_to_cpu(rd->csum2));

2712

le16_to_cpu(rd->csum2));

2713

if (likely(skb)) {

2713

if (likely(skb)) {

2714

dev->last_rx = jiffies;

2714

dev->last_rx = jiffies;

2715

netif_receive_skb(skb);

2715

netif_receive_skb(skb);

2716

2717

++work_done;

2717

++work_done;

2718

} else

2718

} else

2719

skge_rx_reuse(e, skge->rx_buf_size);

2719

skge_rx_reuse(e, skge->rx_buf_size);

2720

}

2720

}

2721

ring->to_clean = e;

2721

ring->to_clean = e;

2722

2723

/* restart receiver */

2723

/* restart receiver */

2724

wmb();

2724

wmb();

2725

skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);

2725

skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);

2726

2727

*budget -= work_done;

2727

*budget -= work_done;

2728

dev->quota -= work_done;

2728

dev->quota -= work_done;

2729

2730

if (work_done >= to_do)

2730

if (work_done >= to_do)

2731

return 1; /* not done */

2731

return 1; /* not done */

2732

2733

netif_rx_complete(dev);

2733

netif_rx_complete(dev);

2734

hw->intr_mask |= skge->port == 0 ? (IS_R1_F|IS_XA1_F) : (IS_R2_F|IS_XA2_F);

2734

hw->intr_mask |= skge->port == 0 ? (IS_R1_F|IS_XA1_F) : (IS_R2_F|IS_XA2_F);

2735

skge_write32(hw, B0_IMSK, hw->intr_mask);

2735

skge_write32(hw, B0_IMSK, hw->intr_mask);

2736

2737

return 0;

2737

return 0;

2738

}

2738

}

2739

2740

/* Parity errors seem to happen when Genesis is connected to a switch

2740

/* Parity errors seem to happen when Genesis is connected to a switch

2741

* with no other ports present. Heartbeat error??

2741

* with no other ports present. Heartbeat error??

2742

*/

2742

*/

2743

static void skge_mac_parity(struct skge_hw *hw, int port)

2743

static void skge_mac_parity(struct skge_hw *hw, int port)

2744

{

2744

{

2745

struct net_device *dev = hw->dev[port];

2745

struct net_device *dev = hw->dev[port];

2746

2747

if (dev) {

2747

if (dev) {

2748

struct skge_port *skge = netdev_priv(dev);

2748

struct skge_port *skge = netdev_priv(dev);

2749

++skge->net_stats.tx_heartbeat_errors;

2749

++skge->net_stats.tx_heartbeat_errors;

2750

}

2750

}

2751

2752

if (hw->chip_id == CHIP_ID_GENESIS)

2752

if (hw->chip_id == CHIP_ID_GENESIS)

2753

skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),

2753

skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),

2754

MFF_CLR_PERR);

2754

MFF_CLR_PERR);

2755

else

2755

else

2756

/* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */

2756

/* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */

2757

skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),

2757

skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),

2758

(hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)

2758

(hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)

2759

? GMF_CLI_TX_FC : GMF_CLI_TX_PE);

2759

? GMF_CLI_TX_FC : GMF_CLI_TX_PE);

2760

}

2760

}

2761

2762

static void skge_pci_clear(struct skge_hw *hw)

2762

static void skge_pci_clear(struct skge_hw *hw)

2763

{

2763

{

2764

u16 status;

2764

u16 status;

2765

2766

pci_read_config_word(hw->pdev, PCI_STATUS, &status);

2766

pci_read_config_word(hw->pdev, PCI_STATUS, &status);

2767

skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);

2767

skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);

2768

pci_write_config_word(hw->pdev, PCI_STATUS,

2768

pci_write_config_word(hw->pdev, PCI_STATUS,

2769

status | PCI_STATUS_ERROR_BITS);

2769

status | PCI_STATUS_ERROR_BITS);

2770

skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);

2770

skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);

2771

}

2771

}

2772

2773

static void skge_mac_intr(struct skge_hw *hw, int port)

2773

static void skge_mac_intr(struct skge_hw *hw, int port)

2774

{

2774

{

2775

if (hw->chip_id == CHIP_ID_GENESIS)

2775

if (hw->chip_id == CHIP_ID_GENESIS)

2776

genesis_mac_intr(hw, port);

2776

genesis_mac_intr(hw, port);

2777

else

2777

else

2778

yukon_mac_intr(hw, port);

2778

yukon_mac_intr(hw, port);

2779

}

2779

}

2780

2781

/* Handle device specific framing and timeout interrupts */

2781

/* Handle device specific framing and timeout interrupts */

2782

static void skge_error_irq(struct skge_hw *hw)

2782

static void skge_error_irq(struct skge_hw *hw)

2783

{

2783

{

2784

u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);

2784

u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);

2785

2786

if (hw->chip_id == CHIP_ID_GENESIS) {

2786

if (hw->chip_id == CHIP_ID_GENESIS) {

2787

/* clear xmac errors */

2787

/* clear xmac errors */

2788

if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))

2788

if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))

2789

skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);

2789

skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);

2790

if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))

2790

if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))

2791

skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);

2791

skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);

2792

} else {

2792

} else {

2793

/* Timestamp (unused) overflow */

2793

/* Timestamp (unused) overflow */

2794

if (hwstatus & IS_IRQ_TIST_OV)

2794

if (hwstatus & IS_IRQ_TIST_OV)

2795

skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);

2795

skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);

2796

}

2796

}

2797

2798

if (hwstatus & IS_RAM_RD_PAR) {

2798

if (hwstatus & IS_RAM_RD_PAR) {

2799

printk(KERN_ERR PFX "Ram read data parity error\n");

2799

printk(KERN_ERR PFX "Ram read data parity error\n");

2800

skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);

2800

skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);

2801

}

2801

}

2802

2803

if (hwstatus & IS_RAM_WR_PAR) {

2803

if (hwstatus & IS_RAM_WR_PAR) {

2804

printk(KERN_ERR PFX "Ram write data parity error\n");

2804

printk(KERN_ERR PFX "Ram write data parity error\n");

2805

skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);

2805

skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);

2806

}

2806

}

2807

2808

if (hwstatus & IS_M1_PAR_ERR)

2808

if (hwstatus & IS_M1_PAR_ERR)

2809

skge_mac_parity(hw, 0);

2809

skge_mac_parity(hw, 0);

2810

2811

if (hwstatus & IS_M2_PAR_ERR)

2811

if (hwstatus & IS_M2_PAR_ERR)

2812

skge_mac_parity(hw, 1);

2812

skge_mac_parity(hw, 1);

2813

2814

if (hwstatus & IS_R1_PAR_ERR)

2814

if (hwstatus & IS_R1_PAR_ERR)

2815

skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);

2815

skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);

2816

2817

if (hwstatus & IS_R2_PAR_ERR)

2817

if (hwstatus & IS_R2_PAR_ERR)

2818

skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);

2818

skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);

2819

2820

if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {

2820

if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {

2821

printk(KERN_ERR PFX "hardware error detected (status 0x%x)\n",

2821

printk(KERN_ERR PFX "hardware error detected (status 0x%x)\n",

2822

hwstatus);

2822

hwstatus);

2823

2824

skge_pci_clear(hw);

2824

skge_pci_clear(hw);

2825

2826

/* if error still set then just ignore it */

2826

/* if error still set then just ignore it */

2827

hwstatus = skge_read32(hw, B0_HWE_ISRC);

2827

hwstatus = skge_read32(hw, B0_HWE_ISRC);

2828

if (hwstatus & IS_IRQ_STAT) {

2828

if (hwstatus & IS_IRQ_STAT) {

2829

pr_debug("IRQ status %x: still set ignoring hardware errors\n",

2829

pr_debug("IRQ status %x: still set ignoring hardware errors\n",

2830

hwstatus);

2830

hwstatus);

2831

hw->intr_mask &= ~IS_HW_ERR;

2831

hw->intr_mask &= ~IS_HW_ERR;

2832

}

2832

}

2833

}

2833

}

2834

}

2834

}

2835

2836

/*

2836

/*

2837

* Interrupt from PHY are handled in tasklet (soft irq)

2837

* Interrupt from PHY are handled in tasklet (soft irq)

2838

* because accessing phy registers requires spin wait which might

2838

* because accessing phy registers requires spin wait which might

2839

* cause excess interrupt latency.

2839

* cause excess interrupt latency.

2840

*/

2840

*/

2841

static void skge_extirq(unsigned long data)

2841

static void skge_extirq(unsigned long data)

2842

{

2842

{

2843

struct skge_hw *hw = (struct skge_hw *) data;

2843

struct skge_hw *hw = (struct skge_hw *) data;

2844

int port;

2844

int port;

2845

2846

spin_lock(&hw->phy_lock);

2846

spin_lock(&hw->phy_lock);

2847

for (port = 0; port < hw->ports; port++) {

2847

for (port = 0; port < hw->ports; port++) {

2848

struct net_device *dev = hw->dev[port];

2848

struct net_device *dev = hw->dev[port];

2849

struct skge_port *skge = netdev_priv(dev);

2849

struct skge_port *skge = netdev_priv(dev);

2850

2851

if (netif_running(dev)) {

2851

if (netif_running(dev)) {

2852

if (hw->chip_id != CHIP_ID_GENESIS)

2852

if (hw->chip_id != CHIP_ID_GENESIS)

2853

yukon_phy_intr(skge);

2853

yukon_phy_intr(skge);

2854

else

2854

else

2855

bcom_phy_intr(skge);

2855

bcom_phy_intr(skge);

2856

}

2856

}

2857

}

2857

}

2858

spin_unlock(&hw->phy_lock);

2858

spin_unlock(&hw->phy_lock);

2859

2860

hw->intr_mask |= IS_EXT_REG;

2860

hw->intr_mask |= IS_EXT_REG;

2861

skge_write32(hw, B0_IMSK, hw->intr_mask);

2861

skge_write32(hw, B0_IMSK, hw->intr_mask);

2862

}

2862

}

2863

2864

static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)

2864

static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)

2865

{

2865

{

2866

struct skge_hw *hw = dev_id;

2866

struct skge_hw *hw = dev_id;

2867

u32 status;

2867

u32 status;

2868

2869

/* Reading this register masks IRQ */

2869

/* Reading this register masks IRQ */

2870

status = skge_read32(hw, B0_SP_ISRC);

2870

status = skge_read32(hw, B0_SP_ISRC);

2871

if (status == 0)

2871

if (status == 0)

2872

return IRQ_NONE;

2872

return IRQ_NONE;

2873

2874

if (status & IS_EXT_REG) {

2874

if (status & IS_EXT_REG) {

2875

hw->intr_mask &= ~IS_EXT_REG;

2875

hw->intr_mask &= ~IS_EXT_REG;

2876

tasklet_schedule(&hw->ext_tasklet);

2876

tasklet_schedule(&hw->ext_tasklet);

2877

}

2877

}

2878

2879

if (status & (IS_R1_F|IS_XA1_F)) {

2879

if (status & (IS_R1_F|IS_XA1_F)) {

2880

skge_write8(hw, Q_ADDR(Q_R1, Q_CSR), CSR_IRQ_CL_F);

2880

skge_write8(hw, Q_ADDR(Q_R1, Q_CSR), CSR_IRQ_CL_F);

2881

hw->intr_mask &= ~(IS_R1_F|IS_XA1_F);

2881

hw->intr_mask &= ~(IS_R1_F|IS_XA1_F);

2882

netif_rx_schedule(hw->dev[0]);

2882

netif_rx_schedule(hw->dev[0]);

2883

}

2883

}

2884

2885

if (status & (IS_R2_F|IS_XA2_F)) {

2885

if (status & (IS_R2_F|IS_XA2_F)) {

2886

skge_write8(hw, Q_ADDR(Q_R2, Q_CSR), CSR_IRQ_CL_F);

2886

skge_write8(hw, Q_ADDR(Q_R2, Q_CSR), CSR_IRQ_CL_F);

2887

hw->intr_mask &= ~(IS_R2_F|IS_XA2_F);

2887

hw->intr_mask &= ~(IS_R2_F|IS_XA2_F);

2888

netif_rx_schedule(hw->dev[1]);

2888

netif_rx_schedule(hw->dev[1]);

2889

}

2889

}

2890

2891

if (likely((status & hw->intr_mask) == 0))

2891

if (likely((status & hw->intr_mask) == 0))

2892

return IRQ_HANDLED;

2892

return IRQ_HANDLED;

2893

2894

if (status & IS_PA_TO_RX1) {

2894

if (status & IS_PA_TO_RX1) {

2895

struct skge_port *skge = netdev_priv(hw->dev[0]);

2895

struct skge_port *skge = netdev_priv(hw->dev[0]);

2896

++skge->net_stats.rx_over_errors;

2896

++skge->net_stats.rx_over_errors;

2897

skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);

2897

skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);

2898

}

2898

}

2899

2900

if (status & IS_PA_TO_RX2) {

2900

if (status & IS_PA_TO_RX2) {

2901

struct skge_port *skge = netdev_priv(hw->dev[1]);

2901

struct skge_port *skge = netdev_priv(hw->dev[1]);

2902

++skge->net_stats.rx_over_errors;

2902

++skge->net_stats.rx_over_errors;

2903

skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);

2903

skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);

2904

}

2904

}

2905

2906

if (status & IS_PA_TO_TX1)

2906

if (status & IS_PA_TO_TX1)

2907

skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);

2907

skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);

2908

2909

if (status & IS_PA_TO_TX2)

2909

if (status & IS_PA_TO_TX2)

2910

skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);

2910

skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);

2911

2912

if (status & IS_MAC1)

2912

if (status & IS_MAC1)

2913

skge_mac_intr(hw, 0);

2913

skge_mac_intr(hw, 0);

2914

2915

if (status & IS_MAC2)

2915

if (status & IS_MAC2)

2916

skge_mac_intr(hw, 1);

2916

skge_mac_intr(hw, 1);

2917

2918

if (status & IS_HW_ERR)

2918

if (status & IS_HW_ERR)

2919

skge_error_irq(hw);

2919

skge_error_irq(hw);

2920

2921

skge_write32(hw, B0_IMSK, hw->intr_mask);

2921

skge_write32(hw, B0_IMSK, hw->intr_mask);

2922

2923

return IRQ_HANDLED;

2923

return IRQ_HANDLED;

2924

}

2924

}

2925

2926

#ifdef CONFIG_NET_POLL_CONTROLLER

2926

#ifdef CONFIG_NET_POLL_CONTROLLER

2927

static void skge_netpoll(struct net_device *dev)

2927

static void skge_netpoll(struct net_device *dev)

2928

{

2928

{

2929

struct skge_port *skge = netdev_priv(dev);

2929

struct skge_port *skge = netdev_priv(dev);

2930

2931

disable_irq(dev->irq);

2931

disable_irq(dev->irq);

2932

skge_intr(dev->irq, skge->hw, NULL);

2932

skge_intr(dev->irq, skge->hw, NULL);

2933

enable_irq(dev->irq);

2933

enable_irq(dev->irq);

2934

}

2934

}

2935

#endif

2935

#endif

2936

2937

static int skge_set_mac_address(struct net_device *dev, void *p)

2937

static int skge_set_mac_address(struct net_device *dev, void *p)

2938

{

2938

{

2939

struct skge_port *skge = netdev_priv(dev);

2939

struct skge_port *skge = netdev_priv(dev);

2940

struct skge_hw *hw = skge->hw;

2940

struct skge_hw *hw = skge->hw;

2941

unsigned port = skge->port;

2941

unsigned port = skge->port;

2942

const struct sockaddr *addr = p;

2942

const struct sockaddr *addr = p;

2943

2944

if (!is_valid_ether_addr(addr->sa_data))

2944

if (!is_valid_ether_addr(addr->sa_data))

2945

return -EADDRNOTAVAIL;

2945

return -EADDRNOTAVAIL;

2946

2947

spin_lock_bh(&hw->phy_lock);

2947

spin_lock_bh(&hw->phy_lock);

2948

memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);

2948

memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);

2949

memcpy_toio(hw->regs + B2_MAC_1 + port*8,

2949

memcpy_toio(hw->regs + B2_MAC_1 + port*8,

2950

dev->dev_addr, ETH_ALEN);

2950

dev->dev_addr, ETH_ALEN);

2951

memcpy_toio(hw->regs + B2_MAC_2 + port*8,

2951

memcpy_toio(hw->regs + B2_MAC_2 + port*8,

2952

dev->dev_addr, ETH_ALEN);

2952

dev->dev_addr, ETH_ALEN);

2953

2954

if (hw->chip_id == CHIP_ID_GENESIS)

2954

if (hw->chip_id == CHIP_ID_GENESIS)

2955

xm_outaddr(hw, port, XM_SA, dev->dev_addr);

2955

xm_outaddr(hw, port, XM_SA, dev->dev_addr);

2956

else {

2956

else {

2957

gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);

2957

gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);

2958

gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);

2958

gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);

2959

}

2959

}

2960

spin_unlock_bh(&hw->phy_lock);

2960

spin_unlock_bh(&hw->phy_lock);

2961

2962

return 0;

2962

return 0;

2963

}

2963

}

2964

2965

static const struct {

2965

static const struct {

2966

u8 id;

2966

u8 id;

2967

const char *name;

2967

const char *name;

2968

} skge_chips[] = {

2968

} skge_chips[] = {

2969

{ CHIP_ID_GENESIS, "Genesis" },

2969

{ CHIP_ID_GENESIS, "Genesis" },

2970

{ CHIP_ID_YUKON, "Yukon" },

2970

{ CHIP_ID_YUKON, "Yukon" },

2971

{ CHIP_ID_YUKON_LITE, "Yukon-Lite"},

2971

{ CHIP_ID_YUKON_LITE, "Yukon-Lite"},

2972

{ CHIP_ID_YUKON_LP, "Yukon-LP"},

2972

{ CHIP_ID_YUKON_LP, "Yukon-LP"},

2973

};

2973

};

2974

2975

static const char *skge_board_name(const struct skge_hw *hw)

2975

static const char *skge_board_name(const struct skge_hw *hw)

2976

{

2976

{

2977

int i;

2977

int i;

2978

static char buf[16];

2978

static char buf[16];

2979

2980

for (i = 0; i < ARRAY_SIZE(skge_chips); i++)

2980

for (i = 0; i < ARRAY_SIZE(skge_chips); i++)

2981

if (skge_chips[i].id == hw->chip_id)

2981

if (skge_chips[i].id == hw->chip_id)

2982

return skge_chips[i].name;

2982

return skge_chips[i].name;

2983

2984

snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);

2984

snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);

2985

return buf;

2985

return buf;

2986

}

2986

}

2987

2988

2989

/*

2989

/*

2990

* Setup the board data structure, but don't bring up

2990

* Setup the board data structure, but don't bring up

2991

* the port(s)

2991

* the port(s)

2992

*/

2992

*/

2993

static int skge_reset(struct skge_hw *hw)

2993

static int skge_reset(struct skge_hw *hw)

2994

{

2994

{

2995

u32 reg;

2995

u32 reg;

2996

u16 ctst;

2996

u16 ctst;

2997

u8 t8, mac_cfg, pmd_type, phy_type;

2997

u8 t8, mac_cfg, pmd_type, phy_type;

2998

int i;

2998

int i;

2999

3000

ctst = skge_read16(hw, B0_CTST);

3000

ctst = skge_read16(hw, B0_CTST);

3001

3002

/* do a SW reset */

3002

/* do a SW reset */

3003

skge_write8(hw, B0_CTST, CS_RST_SET);

3003

skge_write8(hw, B0_CTST, CS_RST_SET);

3004

skge_write8(hw, B0_CTST, CS_RST_CLR);

3004

skge_write8(hw, B0_CTST, CS_RST_CLR);

3005

3006

/* clear PCI errors, if any */

3006

/* clear PCI errors, if any */

3007

skge_pci_clear(hw);

3007

skge_pci_clear(hw);

3008

3009

skge_write8(hw, B0_CTST, CS_MRST_CLR);

3009

skge_write8(hw, B0_CTST, CS_MRST_CLR);

3010

3011

/* restore CLK_RUN bits (for Yukon-Lite) */

3011

/* restore CLK_RUN bits (for Yukon-Lite) */

3012

skge_write16(hw, B0_CTST,

3012

skge_write16(hw, B0_CTST,

3013

ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));

3013

ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));

3014

3015

hw->chip_id = skge_read8(hw, B2_CHIP_ID);

3015

hw->chip_id = skge_read8(hw, B2_CHIP_ID);

3016

phy_type = skge_read8(hw, B2_E_1) & 0xf;

3016

phy_type = skge_read8(hw, B2_E_1) & 0xf;

3017

pmd_type = skge_read8(hw, B2_PMD_TYP);

3017

pmd_type = skge_read8(hw, B2_PMD_TYP);

3018

hw->copper = (pmd_type == 'T' || pmd_type == '1');

3018

hw->copper = (pmd_type == 'T' || pmd_type == '1');

3019

3020

switch (hw->chip_id) {

3020

switch (hw->chip_id) {

3021

case CHIP_ID_GENESIS:

3021

case CHIP_ID_GENESIS:

3022

switch (phy_type) {

3022

switch (phy_type) {

3023

case SK_PHY_BCOM:

3023

case SK_PHY_BCOM:

3024

hw->phy_addr = PHY_ADDR_BCOM;

3024

hw->phy_addr = PHY_ADDR_BCOM;

3025

break;

3025

break;

3026

default:

3026

default:

3027

printk(KERN_ERR PFX "%s: unsupported phy type 0x%x\n",

3027

printk(KERN_ERR PFX "%s: unsupported phy type 0x%x\n",

3028

pci_name(hw->pdev), phy_type);

3028

pci_name(hw->pdev), phy_type);

3029

return -EOPNOTSUPP;

3029

return -EOPNOTSUPP;

3030

}

3030

}

3031

break;

3031

break;

3032

3033

case CHIP_ID_YUKON:

3033

case CHIP_ID_YUKON:

3034

case CHIP_ID_YUKON_LITE:

3034

case CHIP_ID_YUKON_LITE:

3035

case CHIP_ID_YUKON_LP:

3035

case CHIP_ID_YUKON_LP:

3036

if (phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')

3036

if (phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')

3037

hw->copper = 1;

3037

hw->copper = 1;

3038

3039

hw->phy_addr = PHY_ADDR_MARV;

3039

hw->phy_addr = PHY_ADDR_MARV;

3040

break;

3040

break;

3041

3042

default:

3042

default:

3043

printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",

3043

printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",

3044

pci_name(hw->pdev), hw->chip_id);

3044

pci_name(hw->pdev), hw->chip_id);

3045

return -EOPNOTSUPP;

3045

return -EOPNOTSUPP;

3046

}

3046

}

3047

3048

mac_cfg = skge_read8(hw, B2_MAC_CFG);

3048

mac_cfg = skge_read8(hw, B2_MAC_CFG);

3049

hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;

3049

hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;

3050

hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;

3050

hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;

3051

3052

/* read the adapters RAM size */

3052

/* read the adapters RAM size */

3053

t8 = skge_read8(hw, B2_E_0);

3053

t8 = skge_read8(hw, B2_E_0);

3054

if (hw->chip_id == CHIP_ID_GENESIS) {

3054

if (hw->chip_id == CHIP_ID_GENESIS) {

3055

if (t8 == 3) {

3055

if (t8 == 3) {

3056

/* special case: 4 x 64k x 36, offset = 0x80000 */

3056

/* special case: 4 x 64k x 36, offset = 0x80000 */

3057

hw->ram_size = 0x100000;

3057

hw->ram_size = 0x100000;

3058

hw->ram_offset = 0x80000;

3058

hw->ram_offset = 0x80000;

3059

} else

3059

} else

3060

hw->ram_size = t8 * 512;

3060

hw->ram_size = t8 * 512;

3061

}

3061

}

3062

else if (t8 == 0)

3062

else if (t8 == 0)

3063

hw->ram_size = 0x20000;

3063

hw->ram_size = 0x20000;

3064

else

3064

else

3065

hw->ram_size = t8 * 4096;

3065

hw->ram_size = t8 * 4096;

3066

3067

hw->intr_mask = IS_HW_ERR | IS_EXT_REG | IS_PORT_1;

3067

hw->intr_mask = IS_HW_ERR | IS_EXT_REG | IS_PORT_1;

3068

if (hw->ports > 1)

3068

if (hw->ports > 1)

3069

hw->intr_mask |= IS_PORT_2;

3069

hw->intr_mask |= IS_PORT_2;

3070

3071

if (hw->chip_id == CHIP_ID_GENESIS)

3071

if (hw->chip_id == CHIP_ID_GENESIS)

3072

genesis_init(hw);

3072

genesis_init(hw);

3073

else {

3073

else {

3074

/* switch power to VCC (WA for VAUX problem) */

3074

/* switch power to VCC (WA for VAUX problem) */

3075

skge_write8(hw, B0_POWER_CTRL,

3075

skge_write8(hw, B0_POWER_CTRL,

3076

PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);

3076

PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);

3077

3078

/* avoid boards with stuck Hardware error bits */

3078

/* avoid boards with stuck Hardware error bits */

3079

if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&

3079

if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&

3080

(skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {

3080

(skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {

3081

printk(KERN_WARNING PFX "stuck hardware sensor bit\n");

3081

printk(KERN_WARNING PFX "stuck hardware sensor bit\n");

3082

hw->intr_mask &= ~IS_HW_ERR;

3082

hw->intr_mask &= ~IS_HW_ERR;

3083

}

3083

}

3084

3085

/* Clear PHY COMA */

3085

/* Clear PHY COMA */

3086

skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);

3086

skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);

3087

pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg);

3087

pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg);

3088

reg &= ~PCI_PHY_COMA;

3088

reg &= ~PCI_PHY_COMA;

3089

pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);

3089

pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);

3090

skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);

3090

skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);

3091

3092

3093

for (i = 0; i < hw->ports; i++) {

3093

for (i = 0; i < hw->ports; i++) {

3094

skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);

3094

skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);

3095

skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);

3095

skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);

3096

}

3096

}

3097

}

3097

}

3098

3099

/* turn off hardware timer (unused) */

3099

/* turn off hardware timer (unused) */

3100

skge_write8(hw, B2_TI_CTRL, TIM_STOP);

3100

skge_write8(hw, B2_TI_CTRL, TIM_STOP);

3101

skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);

3101

skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);

3102

skge_write8(hw, B0_LED, LED_STAT_ON);

3102

skge_write8(hw, B0_LED, LED_STAT_ON);

3103

3104

/* enable the Tx Arbiters */

3104

/* enable the Tx Arbiters */

3105

for (i = 0; i < hw->ports; i++)

3105

for (i = 0; i < hw->ports; i++)

3106

skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);

3106

skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);

3107

3108

/* Initialize ram interface */

3108

/* Initialize ram interface */

3109

skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);

3109

skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);

3110

3111

skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);

3111

skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);

3112

skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);

3112

skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);

3113

skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);

3113

skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);

3114

skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);

3114

skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);

3115

skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);

3115

skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);

3116

skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);

3116

skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);

3117

skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);

3117

skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);

3118

skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);

3118

skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);

3119

skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);

3119

skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);

3120

skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);

3120

skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);

3121

skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);

3121

skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);

3122

skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);

3122

skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);

3123

3124

skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);

3124

skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);

3125

3126

/* Set interrupt moderation for Transmit only

3126

/* Set interrupt moderation for Transmit only

3127

* Receive interrupts avoided by NAPI

3127

* Receive interrupts avoided by NAPI

3128

*/

3128

*/

3129

skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);

3129

skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);

3130

skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));

3130

skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));

3131

skge_write32(hw, B2_IRQM_CTRL, TIM_START);

3131

skge_write32(hw, B2_IRQM_CTRL, TIM_START);

3132

3133

skge_write32(hw, B0_IMSK, hw->intr_mask);

3133

skge_write32(hw, B0_IMSK, hw->intr_mask);

3134

3135

spin_lock_bh(&hw->phy_lock);

3135

spin_lock_bh(&hw->phy_lock);

3136

for (i = 0; i < hw->ports; i++) {

3136

for (i = 0; i < hw->ports; i++) {

3137

if (hw->chip_id == CHIP_ID_GENESIS)

3137

if (hw->chip_id == CHIP_ID_GENESIS)

3138

genesis_reset(hw, i);

3138

genesis_reset(hw, i);

3139

else

3139

else

3140

yukon_reset(hw, i);

3140

yukon_reset(hw, i);

3141

}

3141

}

3142

spin_unlock_bh(&hw->phy_lock);

3142

spin_unlock_bh(&hw->phy_lock);

3143

3144

return 0;

3144

return 0;

3145

}

3145

}

3146

3147

/* Initialize network device */

3147

/* Initialize network device */

3148

static struct net_device *skge_devinit(struct skge_hw *hw, int port,

3148

static struct net_device *skge_devinit(struct skge_hw *hw, int port,

3149

int highmem)

3149

int highmem)

3150

{

3150

{

3151

struct skge_port *skge;

3151

struct skge_port *skge;

3152

struct net_device *dev = alloc_etherdev(sizeof(*skge));

3152

struct net_device *dev = alloc_etherdev(sizeof(*skge));

3153

3154

if (!dev) {

3154

if (!dev) {

3155

printk(KERN_ERR "skge etherdev alloc failed");

3155

printk(KERN_ERR "skge etherdev alloc failed");

3156

return NULL;

3156

return NULL;

3157

}

3157

}

3158

3159

SET_MODULE_OWNER(dev);

3159

SET_MODULE_OWNER(dev);

3160

SET_NETDEV_DEV(dev, &hw->pdev->dev);

3160

SET_NETDEV_DEV(dev, &hw->pdev->dev);

3161

dev->open = skge_up;

3161

dev->open = skge_up;

3162

dev->stop = skge_down;

3162

dev->stop = skge_down;

3163

dev->do_ioctl = skge_ioctl;

3163

dev->do_ioctl = skge_ioctl;

3164

dev->hard_start_xmit = skge_xmit_frame;

3164

dev->hard_start_xmit = skge_xmit_frame;

3165

dev->get_stats = skge_get_stats;

3165

dev->get_stats = skge_get_stats;

3166

if (hw->chip_id == CHIP_ID_GENESIS)

3166

if (hw->chip_id == CHIP_ID_GENESIS)

3167

dev->set_multicast_list = genesis_set_multicast;

3167

dev->set_multicast_list = genesis_set_multicast;

3168

else

3168

else

3169

dev->set_multicast_list = yukon_set_multicast;

3169

dev->set_multicast_list = yukon_set_multicast;

3170

3171

dev->set_mac_address = skge_set_mac_address;

3171

dev->set_mac_address = skge_set_mac_address;

3172

dev->change_mtu = skge_change_mtu;

3172

dev->change_mtu = skge_change_mtu;

3173

SET_ETHTOOL_OPS(dev, &skge_ethtool_ops);

3173

SET_ETHTOOL_OPS(dev, &skge_ethtool_ops);

3174

dev->tx_timeout = skge_tx_timeout;

3174

dev->tx_timeout = skge_tx_timeout;

3175

dev->watchdog_timeo = TX_WATCHDOG;

3175

dev->watchdog_timeo = TX_WATCHDOG;

3176

dev->poll = skge_poll;

3176

dev->poll = skge_poll;

3177

dev->weight = NAPI_WEIGHT;

3177

dev->weight = NAPI_WEIGHT;

3178

#ifdef CONFIG_NET_POLL_CONTROLLER

3178

#ifdef CONFIG_NET_POLL_CONTROLLER

3179

dev->poll_controller = skge_netpoll;

3179

dev->poll_controller = skge_netpoll;

3180

#endif

3180

#endif

3181

dev->irq = hw->pdev->irq;

3181

dev->irq = hw->pdev->irq;

3182

dev->features = NETIF_F_LLTX;

3182

dev->features = NETIF_F_LLTX;

3183

if (highmem)

3183

if (highmem)

3184

dev->features |= NETIF_F_HIGHDMA;

3184

dev->features |= NETIF_F_HIGHDMA;

3185

3186

skge = netdev_priv(dev);

3186

skge = netdev_priv(dev);

3187

skge->netdev = dev;

3187

skge->netdev = dev;

3188

skge->hw = hw;

3188

skge->hw = hw;

3189

skge->msg_enable = netif_msg_init(debug, default_msg);

3189

skge->msg_enable = netif_msg_init(debug, default_msg);

3190

skge->tx_ring.count = DEFAULT_TX_RING_SIZE;

3190

skge->tx_ring.count = DEFAULT_TX_RING_SIZE;

3191

skge->rx_ring.count = DEFAULT_RX_RING_SIZE;

3191

skge->rx_ring.count = DEFAULT_RX_RING_SIZE;

3192

3193

/* Auto speed and flow control */

3193

/* Auto speed and flow control */

3194

skge->autoneg = AUTONEG_ENABLE;

3194

skge->autoneg = AUTONEG_ENABLE;

3195

skge->flow_control = FLOW_MODE_SYMMETRIC;

3195

skge->flow_control = FLOW_MODE_SYMMETRIC;

3196

skge->duplex = -1;

3196

skge->duplex = -1;

3197

skge->speed = -1;

3197

skge->speed = -1;

3198

skge->advertising = skge_supported_modes(hw);

3198

skge->advertising = skge_supported_modes(hw);

3199

3200

hw->dev[port] = dev;

3200

hw->dev[port] = dev;

3201

3202

skge->port = port;

3202

skge->port = port;

3203

3204

spin_lock_init(&skge->tx_lock);

3204

spin_lock_init(&skge->tx_lock);

3205

3206

if (hw->chip_id != CHIP_ID_GENESIS) {

3206

if (hw->chip_id != CHIP_ID_GENESIS) {

3207

dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;

3207

dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;

3208

skge->rx_csum = 1;

3208

skge->rx_csum = 1;

3209

}

3209

}

3210

3211

/* read the mac address */

3211

/* read the mac address */

3212

memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);

3212

memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);

3213

memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);

3213

memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);

3214

3215

/* device is off until link detection */

3215

/* device is off until link detection */

3216

netif_carrier_off(dev);

3216

netif_carrier_off(dev);

3217

netif_stop_queue(dev);

3217

netif_stop_queue(dev);

3218

3219

return dev;

3219

return dev;

3220

}

3220

}

3221

3222

static void __devinit skge_show_addr(struct net_device *dev)

3222

static void __devinit skge_show_addr(struct net_device *dev)

3223

{

3223

{

3224

const struct skge_port *skge = netdev_priv(dev);

3224

const struct skge_port *skge = netdev_priv(dev);

3225

3226

if (netif_msg_probe(skge))

3226

if (netif_msg_probe(skge))

3227

printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",

3227

printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",

3228

dev->name,

3228

dev->name,

3229

dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],

3229

dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],

3230

dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);

3230

dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);

3231

}

3231

}

3232

3233

static int __devinit skge_probe(struct pci_dev *pdev,

3233

static int __devinit skge_probe(struct pci_dev *pdev,

3234

const struct pci_device_id *ent)

3234

const struct pci_device_id *ent)

3235

{

3235

{

3236

struct net_device *dev, *dev1;

3236

struct net_device *dev, *dev1;

3237

struct skge_hw *hw;

3237

struct skge_hw *hw;

3238

int err, using_dac = 0;

3238

int err, using_dac = 0;

3239

3240

if ((err = pci_enable_device(pdev))) {

3240

if ((err = pci_enable_device(pdev))) {

3241

printk(KERN_ERR PFX "%s cannot enable PCI device\n",

3241

printk(KERN_ERR PFX "%s cannot enable PCI device\n",

3242

pci_name(pdev));

3242

pci_name(pdev));

3243

goto err_out;

3243

goto err_out;

3244

}

3244

}

3245

3246

if ((err = pci_request_regions(pdev, DRV_NAME))) {

3246

if ((err = pci_request_regions(pdev, DRV_NAME))) {

3247

printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",

3247

printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",

3248

pci_name(pdev));

3248

pci_name(pdev));

3249

goto err_out_disable_pdev;

3249

goto err_out_disable_pdev;

3250

}

3250

}

3251

3252

pci_set_master(pdev);

3252

pci_set_master(pdev);

3253

3254

if (sizeof(dma_addr_t) > sizeof(u32) &&

3254

if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {

3255

!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {

3256

using_dac = 1;

3255

using_dac = 1;

3257

err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);

3256

err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);

3258

if (err < 0) {

3257

} else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {

3259

printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA "

3258

using_dac = 0;

3260

"for consistent allocations\n", pci_name(pdev));

3259

err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);

3261

goto err_out_free_regions;

3260

}

3262

}

3261

3263

} else {

3262

if (err) {

3264

err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);

3263

printk(KERN_ERR PFX "%s no usable DMA configuration\n",

3265

if (err) {

3264

pci_name(pdev));

3266

printk(KERN_ERR PFX "%s no usable DMA configuration\n",

3265

goto err_out_free_regions;

3267

pci_name(pdev));

3268

goto err_out_free_regions;

3269

}

3270

}

3266

}

3271

3267

3272

#ifdef __BIG_ENDIAN

3268

#ifdef __BIG_ENDIAN

3273

/* byte swap descriptors in hardware */

3269

/* byte swap descriptors in hardware */

3274

{

3270

{

3275

u32 reg;

3271

u32 reg;

3276

3272

3277

pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);

3273

pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);

3278

reg |= PCI_REV_DESC;

3274

reg |= PCI_REV_DESC;

3279

pci_write_config_dword(pdev, PCI_DEV_REG2, reg);

3275

pci_write_config_dword(pdev, PCI_DEV_REG2, reg);

3280

}

3276

}

3281

#endif

3277

#endif

3282

3278

3283

err = -ENOMEM;

3279

err = -ENOMEM;

3284

hw = kzalloc(sizeof(*hw), GFP_KERNEL);

3280

hw = kzalloc(sizeof(*hw), GFP_KERNEL);

3285

if (!hw) {

3281

if (!hw) {

3286

printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",

3282

printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",

3287

pci_name(pdev));

3283

pci_name(pdev));

3288

goto err_out_free_regions;

3284

goto err_out_free_regions;

3289

}

3285

}

3290

3286

3291

hw->pdev = pdev;

3287

hw->pdev = pdev;

3292

spin_lock_init(&hw->phy_lock);

3288

spin_lock_init(&hw->phy_lock);

3293

tasklet_init(&hw->ext_tasklet, skge_extirq, (unsigned long) hw);

3289

tasklet_init(&hw->ext_tasklet, skge_extirq, (unsigned long) hw);

3294

3290

3295

hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);

3291

hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);

3296

if (!hw->regs) {

3292

if (!hw->regs) {

3297

printk(KERN_ERR PFX "%s: cannot map device registers\n",

3293

printk(KERN_ERR PFX "%s: cannot map device registers\n",

3298

pci_name(pdev));

3294

pci_name(pdev));

3299

goto err_out_free_hw;

3295

goto err_out_free_hw;

3300

}

3296

}

3301

3297

3302

if ((err = request_irq(pdev->irq, skge_intr, SA_SHIRQ, DRV_NAME, hw))) {

3298

if ((err = request_irq(pdev->irq, skge_intr, SA_SHIRQ, DRV_NAME, hw))) {

3303

printk(KERN_ERR PFX "%s: cannot assign irq %d\n",

3299

printk(KERN_ERR PFX "%s: cannot assign irq %d\n",

3304

pci_name(pdev), pdev->irq);

3300

pci_name(pdev), pdev->irq);

3305

goto err_out_iounmap;

3301

goto err_out_iounmap;

3306

}

3302

}

3307

pci_set_drvdata(pdev, hw);

3303

pci_set_drvdata(pdev, hw);

3308

3304

3309

err = skge_reset(hw);

3305

err = skge_reset(hw);

3310

if (err)

3306

if (err)

3311

goto err_out_free_irq;

3307

goto err_out_free_irq;

3312

3308

3313

printk(KERN_INFO PFX DRV_VERSION " addr 0x%lx irq %d chip %s rev %d\n",

3309

printk(KERN_INFO PFX DRV_VERSION " addr 0x%lx irq %d chip %s rev %d\n",

3314

pci_resource_start(pdev, 0), pdev->irq,

3310

pci_resource_start(pdev, 0), pdev->irq,

3315

skge_board_name(hw), hw->chip_rev);

3311

skge_board_name(hw), hw->chip_rev);

3316

3312

3317

if ((dev = skge_devinit(hw, 0, using_dac)) == NULL)

3313

if ((dev = skge_devinit(hw, 0, using_dac)) == NULL)

3318

goto err_out_led_off;

3314

goto err_out_led_off;

3319

3315

3320

if ((err = register_netdev(dev))) {

3316

if ((err = register_netdev(dev))) {

3321

printk(KERN_ERR PFX "%s: cannot register net device\n",

3317

printk(KERN_ERR PFX "%s: cannot register net device\n",

3322

pci_name(pdev));

3318

pci_name(pdev));

3323

goto err_out_free_netdev;

3319

goto err_out_free_netdev;

3324

}

3320

}

3325

3321

3326

skge_show_addr(dev);

3322

skge_show_addr(dev);

3327

3323

3328

if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {

3324

if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {

3329

if (register_netdev(dev1) == 0)

3325

if (register_netdev(dev1) == 0)

3330

skge_show_addr(dev1);

3326

skge_show_addr(dev1);

3331

else {

3327

else {

3332

/* Failure to register second port need not be fatal */

3328

/* Failure to register second port need not be fatal */

3333

printk(KERN_WARNING PFX "register of second port failed\n");

3329

printk(KERN_WARNING PFX "register of second port failed\n");

3334

hw->dev[1] = NULL;

3330

hw->dev[1] = NULL;

3335

free_netdev(dev1);

3331

free_netdev(dev1);

3336

}

3332

}

3337

}

3333

}

3338

3334

3339

return 0;

3335

return 0;

3340

3336

3341

err_out_free_netdev:

3337

err_out_free_netdev:

3342

free_netdev(dev);

3338

free_netdev(dev);

3343

err_out_led_off:

3339

err_out_led_off:

3344

skge_write16(hw, B0_LED, LED_STAT_OFF);

3340

skge_write16(hw, B0_LED, LED_STAT_OFF);

3345

err_out_free_irq:

3341

err_out_free_irq:

3346

free_irq(pdev->irq, hw);

3342

free_irq(pdev->irq, hw);

3347

err_out_iounmap:

3343

err_out_iounmap:

3348

iounmap(hw->regs);

3344

iounmap(hw->regs);

3349

err_out_free_hw:

3345

err_out_free_hw:

3350

kfree(hw);

3346

kfree(hw);

3351

err_out_free_regions:

3347

err_out_free_regions:

3352

pci_release_regions(pdev);

3348

pci_release_regions(pdev);

3353

err_out_disable_pdev:

3349

err_out_disable_pdev:

3354

pci_disable_device(pdev);

3350

pci_disable_device(pdev);

3355

pci_set_drvdata(pdev, NULL);

3351

pci_set_drvdata(pdev, NULL);

3356

err_out:

3352

err_out:

3357

return err;

3353

return err;

3358

}

3354

}

3359

3355

3360

static void __devexit skge_remove(struct pci_dev *pdev)

3356

static void __devexit skge_remove(struct pci_dev *pdev)

3361

{

3357

{

3362

struct skge_hw *hw = pci_get_drvdata(pdev);

3358

struct skge_hw *hw = pci_get_drvdata(pdev);

3363

struct net_device *dev0, *dev1;

3359

struct net_device *dev0, *dev1;

3364

3360

3365

if (!hw)

3361

if (!hw)

3366

return;

3362

return;

3367

3363

3368

if ((dev1 = hw->dev[1]))

3364

if ((dev1 = hw->dev[1]))

3369

unregister_netdev(dev1);

3365

unregister_netdev(dev1);

3370

dev0 = hw->dev[0];

3366

dev0 = hw->dev[0];

3371

unregister_netdev(dev0);

3367

unregister_netdev(dev0);

3372

3368

3373

skge_write32(hw, B0_IMSK, 0);

3369

skge_write32(hw, B0_IMSK, 0);

3374

skge_write16(hw, B0_LED, LED_STAT_OFF);

3370

skge_write16(hw, B0_LED, LED_STAT_OFF);

3375

skge_pci_clear(hw);

3371

skge_pci_clear(hw);

3376

skge_write8(hw, B0_CTST, CS_RST_SET);

3372

skge_write8(hw, B0_CTST, CS_RST_SET);

3377

3373

3378

tasklet_kill(&hw->ext_tasklet);

3374

tasklet_kill(&hw->ext_tasklet);

3379

3375

3380

free_irq(pdev->irq, hw);

3376

free_irq(pdev->irq, hw);

3381

pci_release_regions(pdev);

3377

pci_release_regions(pdev);

3382

pci_disable_device(pdev);

3378

pci_disable_device(pdev);

3383

if (dev1)

3379

if (dev1)

3384

free_netdev(dev1);

3380

free_netdev(dev1);

3385

free_netdev(dev0);

3381

free_netdev(dev0);

3386

3382

3387

iounmap(hw->regs);

3383

iounmap(hw->regs);

3388

kfree(hw);

3384

kfree(hw);

3389

pci_set_drvdata(pdev, NULL);

3385

pci_set_drvdata(pdev, NULL);

3390

}

3386

}

3391

3387

3392

#ifdef CONFIG_PM

3388

#ifdef CONFIG_PM

3393

static int skge_suspend(struct pci_dev *pdev, pm_message_t state)

3389

static int skge_suspend(struct pci_dev *pdev, pm_message_t state)

3394

{

3390

{

3395

struct skge_hw *hw = pci_get_drvdata(pdev);

3391

struct skge_hw *hw = pci_get_drvdata(pdev);

3396

int i, wol = 0;

3392

int i, wol = 0;

3397

3393

3398

for (i = 0; i < 2; i++) {

3394

for (i = 0; i < 2; i++) {

3399

struct net_device *dev = hw->dev[i];

3395

struct net_device *dev = hw->dev[i];

3400

3396

3401

if (dev) {

3397

if (dev) {

3402

struct skge_port *skge = netdev_priv(dev);

3398

struct skge_port *skge = netdev_priv(dev);

3403

if (netif_running(dev)) {

3399

if (netif_running(dev)) {

3404

netif_carrier_off(dev);

3400

netif_carrier_off(dev);

3405

if (skge->wol)

3401

if (skge->wol)

3406

netif_stop_queue(dev);

3402

netif_stop_queue(dev);

3407

else

3403

else

3408

skge_down(dev);

3404

skge_down(dev);

3409

}

3405

}

3410

netif_device_detach(dev);

3406

netif_device_detach(dev);

3411

wol |= skge->wol;

3407

wol |= skge->wol;

3412

}

3408

}

3413

}

3409

}

3414

3410

3415

pci_save_state(pdev);

3411

pci_save_state(pdev);

3416

pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);

3412

pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);

3417

pci_disable_device(pdev);

3413

pci_disable_device(pdev);

3418

pci_set_power_state(pdev, pci_choose_state(pdev, state));

3414

pci_set_power_state(pdev, pci_choose_state(pdev, state));

3419

3415

3420

return 0;

3416

return 0;

3421

}

3417

}

3422

3418

3423

static int skge_resume(struct pci_dev *pdev)

3419

static int skge_resume(struct pci_dev *pdev)

3424

{

3420

{

3425

struct skge_hw *hw = pci_get_drvdata(pdev);

3421

struct skge_hw *hw = pci_get_drvdata(pdev);

3426

int i;

3422

int i;

3427

3423

3428

pci_set_power_state(pdev, PCI_D0);

3424

pci_set_power_state(pdev, PCI_D0);

3429

pci_restore_state(pdev);

3425

pci_restore_state(pdev);

3430

pci_enable_wake(pdev, PCI_D0, 0);

3426

pci_enable_wake(pdev, PCI_D0, 0);

3431

3427

3432

skge_reset(hw);

3428

skge_reset(hw);

3433

3429

3434

for (i = 0; i < 2; i++) {

3430

for (i = 0; i < 2; i++) {

3435

struct net_device *dev = hw->dev[i];

3431

struct net_device *dev = hw->dev[i];

3436

if (dev) {

3432

if (dev) {

3437

netif_device_attach(dev);

3433

netif_device_attach(dev);

3438

if (netif_running(dev) && skge_up(dev))

3434

if (netif_running(dev) && skge_up(dev))

3439

dev_close(dev);

3435

dev_close(dev);

3440

}

3436

}

3441

}

3437

}

3442

return 0;

3438

return 0;

3443

}

3439

}

3444

#endif

3440

#endif

3445

3441

3446

static struct pci_driver skge_driver = {

3442

static struct pci_driver skge_driver = {

3447

.name = DRV_NAME,

3443

.name = DRV_NAME,

3448

.id_table = skge_id_table,

3444

.id_table = skge_id_table,

3449

.probe = skge_probe,

3445

.probe = skge_probe,

3450

.remove = __devexit_p(skge_remove),

3446

.remove = __devexit_p(skge_remove),

3451

#ifdef CONFIG_PM

3447

#ifdef CONFIG_PM

3452

.suspend = skge_suspend,

3448

.suspend = skge_suspend,

3453

.resume = skge_resume,

3449

.resume = skge_resume,

3454

#endif

3450

#endif

3455

};

3451

};

3456

3452

3457

static int __init skge_init_module(void)

3453

static int __init skge_init_module(void)

3458

{

3454

{

3459

return pci_module_init(&skge_driver);

3455

return pci_module_init(&skge_driver);

3460

}

3456

}

3461

3457

3462

static void __exit skge_cleanup_module(void)

3458

static void __exit skge_cleanup_module(void)

3463

{

3459

{

3464

pci_unregister_driver(&skge_driver);

3460

pci_unregister_driver(&skge_driver);

3465

}

3461

}

3466

3462

3467

module_init(skge_init_module);

3463

module_init(skge_init_module);

3468

module_exit(skge_cleanup_module);

3464

module_exit(skge_cleanup_module);

3469

3465

GITLAB

Eric Lee / linux-smarc-t335x-v3.2

[PATCH] skge: dma configuration cleanup