Eric Lee / linux-smarc-t335x-v3.2

Commit 94082f35882b7da6256c9609e17fa1047d9477c7

Authored by Hebbar, Gururaja 2011-12-16 18:21:58 +0800

Exists in master

arm:omap:am335x - Add support for UART 2

Support for UART 2 is added. UART 2 is tested for working in Profile 3
by passing kernel boot args from u-boot as setenv bootargs
'console=ttyO2,115200n8......'

Signed-off-by: Hebbar, Gururaja <gururaja.hebbar@ti.com>

Showing 3 changed files with 30 additions and 5 deletions Inline Diff

arch/arm/mach-omap2/board-am335xevm.c
arch/arm/mach-omap2/mux33xx.c
arch/arm/mach-omap2/omap_hwmod_33xx_data.c

arch/arm/mach-omap2/board-am335xevm.c

Diff comments View file @ 94082f3

 /*
  * Code for AM335X EVM.
  *
  * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation version 2.
  *
  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  * kind, whether express or implied; without even the implied warranty
  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  */
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/i2c.h>
 #include <linux/i2c/at24.h>
 #include <linux/phy.h>
 #include <linux/gpio.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/flash.h>
 #include <linux/input.h>
 #include <linux/gpio_keys.h>
 #include <linux/input/matrix_keypad.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/partitions.h>
 #include <linux/platform_device.h>
 #include <linux/clk.h>
 #include <linux/err.h>
 #include <linux/wl12xx.h>
 #include <linux/ethtool.h>
 #include <linux/mfd/tps65910.h>
 /* LCD controller is similar to DA850 */
 #include <video/da8xx-fb.h>
 #include <mach/hardware.h>
 #include <mach/board-am335xevm.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/hardware/asp.h>
 #include <plat/irqs.h>
 #include <plat/board.h>
 #include <plat/common.h>
 #include <plat/lcdc.h>
 #include <plat/usb.h>
 #include <plat/mmc.h>
 #include "board-flash.h"
 #include "cpuidle33xx.h"
 #include "mux.h"
 #include "devices.h"
 #include "hsmmc.h"
 /* TLK PHY IDs */
 #define TLK110_PHY_ID		0x2000A201
 #define TLK110_PHY_MASK		0xfffffff0
 /* BBB PHY IDs */
 #define BBB_PHY_ID		0x7c0f1
 #define BBB_PHY_MASK		0xfffffffe
 /* TLK110 PHY register offsets */
 #define TLK110_COARSEGAIN_REG	0x00A3
 #define TLK110_LPFHPF_REG	0x00AC
 #define TLK110_SPAREANALOG_REG	0x00B9
 #define TLK110_VRCR_REG		0x00D0
 #define TLK110_SETFFE_REG	0x0107
 #define TLK110_FTSP_REG		0x0154
 #define TLK110_ALFATPIDL_REG	0x002A
 #define TLK110_PSCOEF21_REG	0x0096
 #define TLK110_PSCOEF3_REG	0x0097
 #define TLK110_ALFAFACTOR1_REG	0x002C
 #define TLK110_ALFAFACTOR2_REG	0x0023
 #define TLK110_CFGPS_REG	0x0095
 #define TLK110_FTSPTXGAIN_REG	0x0150
 #define TLK110_SWSCR3_REG	0x000B
 #define TLK110_SCFALLBACK_REG	0x0040
 #define TLK110_PHYRCR_REG	0x001F
 /* TLK110 register writes values */
 #define TLK110_COARSEGAIN_VAL	0x0000
 #define TLK110_LPFHPF_VAL	0x8000
 #define TLK110_SPANALOG_VAL	0x0000
 #define TLK110_VRCR_VAL		0x0008
 #define TLK110_SETFFE_VAL	0x0605
 #define TLK110_FTSP_VAL		0x0255
 #define TLK110_ALFATPIDL_VAL	0x7998
 #define TLK110_PSCOEF21_VAL	0x3A20
 #define TLK110_PSCOEF3_VAL	0x003F
 #define TLK110_ALFACTOR1_VAL	0xFF80
 #define TLK110_ALFACTOR2_VAL	0x021C
 #define TLK110_CFGPS_VAL	0x0000
 #define TLK110_FTSPTXGAIN_VAL	0x6A88
 #define TLK110_SWSCR3_VAL	0x0000
 #define TLK110_SCFALLBACK_VAL	0xC11D
 #define TLK110_PHYRCR_VAL	0x4000
 #ifdef CONFIG_TLK110_WORKAROUND
 #define am335x_tlk110_phy_init()\
 	do {	\
 		phy_register_fixup_for_uid(TLK110_PHY_ID,\
 					TLK110_PHY_MASK,\
 					am335x_tlk110_phy_fixup);\
 	} while (0);
 #else
 #define am335x_tlk110_phy_init() do { } while (0);
 #endif
 /* Convert GPIO signal to GPIO pin number */
 #define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
 static const struct display_panel disp_panel = {
 	WVGA,
 	32,
 	32,
 	COLOR_ACTIVE,
 };
 static struct lcd_ctrl_config lcd_cfg = {
 	&disp_panel,
 	.ac_bias		= 255,
 	.ac_bias_intrpt		= 0,
 	.dma_burst_sz		= 16,
 	.bpp			= 32,
 	.fdd			= 0x80,
 	.tft_alt_mode		= 0,
 	.stn_565_mode		= 0,
 	.mono_8bit_mode		= 0,
 	.invert_line_clock	= 1,
 	.invert_frm_clock	= 1,
 	.sync_edge		= 0,
 	.sync_ctrl		= 1,
 	.raster_order		= 0,
 };
 struct da8xx_lcdc_platform_data TFC_S9700RTWV35TR_01B_pdata = {
 	.manu_name		= "ThreeFive",
 	.controller_data	= &lcd_cfg,
 	.type			= "TFC_S9700RTWV35TR_01B",
 };
 /* TSc controller */
 #include <linux/input/ti_tscadc.h>
 #include <linux/lis3lv02d.h>
 static struct resource tsc_resources[]  = {
 	[0] = {
 		.start  = AM33XX_TSC_BASE,
 		.end    = AM33XX_TSC_BASE + SZ_8K - 1,
 		.flags  = IORESOURCE_MEM,
 	},
 	[1] = {
 		.start  = AM33XX_IRQ_ADC_GEN,
 		.end    = AM33XX_IRQ_ADC_GEN,
 		.flags  = IORESOURCE_IRQ,
 	},
 };
 static struct tsc_data am335x_touchscreen_data  = {
 	.wires  = 4,
 	.x_plate_resistance = 200,
 };
 static struct platform_device tsc_device = {
 	.name   = "tsc",
 	.id     = -1,
 	.dev    = {
 			.platform_data  = &am335x_touchscreen_data,
 	},
 	.num_resources  = ARRAY_SIZE(tsc_resources),
 	.resource       = tsc_resources,
 };
 static u8 am335x_iis_serializer_direction1[] = {
 	INACTIVE_MODE,	INACTIVE_MODE,	TX_MODE,	RX_MODE,
 	INACTIVE_MODE,	INACTIVE_MODE,	INACTIVE_MODE,	INACTIVE_MODE,
 	INACTIVE_MODE,	INACTIVE_MODE,	INACTIVE_MODE,	INACTIVE_MODE,
 	INACTIVE_MODE,	INACTIVE_MODE,	INACTIVE_MODE,	INACTIVE_MODE,
 };
 static struct snd_platform_data am335x_evm_snd_data1 = {
 	.tx_dma_offset	= 0x46400000,	/* McASP1 */
 	.rx_dma_offset	= 0x46400000,
 	.op_mode	= DAVINCI_MCASP_IIS_MODE,
 	.num_serializer	= ARRAY_SIZE(am335x_iis_serializer_direction1),
 	.tdm_slots	= 2,
 	.serial_dir	= am335x_iis_serializer_direction1,
 	.asp_chan_q	= EVENTQ_2,
 	.version	= MCASP_VERSION_3,
 	.txnumevt	= 1,
 	.rxnumevt	= 1,
 };
 static struct omap2_hsmmc_info am335x_mmc[] __initdata = {
 	{
 		.mmc            = 1,
 		.caps           = MMC_CAP_4_BIT_DATA,
 		.gpio_cd        = GPIO_TO_PIN(0, 6),
 		.gpio_wp        = GPIO_TO_PIN(3, 18),
 		.ocr_mask       = MMC_VDD_32_33 | MMC_VDD_33_34, /* 3V3 */
 	},
 	{
 		.mmc            = 0,	/* will be set at runtime */
 	},
 	{
 		.mmc            = 0,	/* will be set at runtime */
 	},
 	{}      /* Terminator */
 };
 #ifdef CONFIG_OMAP_MUX
 static struct omap_board_mux board_mux[] __initdata = {
 	AM33XX_MUX(I2C0_SDA, OMAP_MUX_MODE0 | AM33XX_SLEWCTRL_SLOW |
 			AM33XX_INPUT_EN | AM33XX_PIN_OUTPUT),
 	AM33XX_MUX(I2C0_SCL, OMAP_MUX_MODE0 | AM33XX_SLEWCTRL_SLOW |
 			AM33XX_INPUT_EN | AM33XX_PIN_OUTPUT),
 	{ .reg_offset = OMAP_MUX_TERMINATOR },
 };
 #else
 #define	board_mux	NULL
 #endif
 /* module pin mux structure */
 struct pinmux_config {
 	const char *string_name; /* signal name format */
 	int val; /* Options for the mux register value */
 };
 struct evm_dev_cfg {
 	void (*device_init)(int evm_id, int profile);
 /*
 * If the device is required on both baseboard & daughter board (ex i2c),
 * specify DEV_ON_BASEBOARD
 */
 #define DEV_ON_BASEBOARD	0
 #define DEV_ON_DGHTR_BRD	1
 	u32 device_on;
 	u32 profile;	/* Profiles (0-7) in which the module is present */
 };
 /* AM335X - CPLD Register Offsets */
 #define	CPLD_DEVICE_HDR	0x00 /* CPLD Header */
 #define	CPLD_DEVICE_ID	0x04 /* CPLD identification */
 #define	CPLD_DEVICE_REV	0x0C /* Revision of the CPLD code */
 #define	CPLD_CFG_REG	0x10 /* Configuration Register */
 static struct i2c_client *cpld_client;
 static u32 am335x_evm_id;
 static struct omap_board_config_kernel am335x_evm_config[] __initdata = {
 };
 /*
 * EVM Config held in On-Board eeprom device.
 *
 * Header Format
 *
 *  Name			Size	Contents
 *			(Bytes)
 *-------------------------------------------------------------
 *  Header		4	0xAA, 0x55, 0x33, 0xEE
 *
 *  Board Name		8	Name for board in ASCII.
 *				example "A33515BB" = "AM335X
 				Low Cost EVM board"
 *
 *  Version		4	Hardware version code for board in
 *				in ASCII. "1.0A" = rev.01.0A
 *
 *  Serial Number	12	Serial number of the board. This is a 12
 *				character string which is WWYY4P16nnnn, where
 *				WW = 2 digit week of the year of production
 *				YY = 2 digit year of production
 *				nnnn = incrementing board number
 *
 *  Configuration option	32	Codes(TBD) to show the configuration
 *				setup on this board.
 *
 *  Available		32720	Available space for other non-volatile
 *				data.
 */
 struct am335x_evm_eeprom_config {
 	u32	header;
 	u8	name[8];
 	char	version[4];
 	u8	serial[12];
 	u8	opt[32];
 };
 static struct am335x_evm_eeprom_config config;
 static bool daughter_brd_detected;
 #define GP_EVM_REV_IS_1_0		0x1
 #define GP_EVM_REV_IS_1_1A		0x2
 #define GP_EVM_REV_IS_UNKNOWN		0xFF
 static unsigned int gp_evm_revision = GP_EVM_REV_IS_UNKNOWN;
 unsigned int gigabit_enable = 1;
 #define EEPROM_MAC_ADDRESS_OFFSET	60 /* 4+8+4+12+32 */
 #define EEPROM_NO_OF_MAC_ADDR		3
 static char am335x_mac_addr[EEPROM_NO_OF_MAC_ADDR][ETH_ALEN];
 #define AM335X_EEPROM_HEADER		0xEE3355AA
 /* current profile if exists else PROFILE_0 on error */
 static u32 am335x_get_profile_selection(void)
 {
 	int val = 0;
 	if (!cpld_client)
 		/* error checking is not done in func's calling this routine.
 		so return profile 0 on error */
 		return 0;
 	val = i2c_smbus_read_word_data(cpld_client, CPLD_CFG_REG);
 	if (val < 0)
 		return 0;	/* default to Profile 0 on Error */
 	else
 		return val & 0x7;
 }
 /* Module pin mux for LCDC */
 static struct pinmux_config lcdc_pin_mux[] = {
 	{"lcd_data0.lcd_data0",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
 						       | AM33XX_PULL_DISA},
 	{"lcd_data1.lcd_data1",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
 						       | AM33XX_PULL_DISA},
 	{"lcd_data2.lcd_data2",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
 						       | AM33XX_PULL_DISA},
 	{"lcd_data3.lcd_data3",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
 						       | AM33XX_PULL_DISA},
 	{"lcd_data4.lcd_data4",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
 						       | AM33XX_PULL_DISA},
 	{"lcd_data5.lcd_data5",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
 						       | AM33XX_PULL_DISA},
 	{"lcd_data6.lcd_data6",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
 						       | AM33XX_PULL_DISA},
 	{"lcd_data7.lcd_data7",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
 						       | AM33XX_PULL_DISA},
 	{"lcd_data8.lcd_data8",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
 						       | AM33XX_PULL_DISA},
 	{"lcd_data9.lcd_data9",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
 						       | AM33XX_PULL_DISA},
 	{"lcd_data10.lcd_data10",	OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
 						       | AM33XX_PULL_DISA},
 	{"lcd_data11.lcd_data11",	OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
 						       | AM33XX_PULL_DISA},
 	{"lcd_data12.lcd_data12",	OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
 						       | AM33XX_PULL_DISA},
 	{"lcd_data13.lcd_data13",	OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
 						       | AM33XX_PULL_DISA},
 	{"lcd_data14.lcd_data14",	OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
 						       | AM33XX_PULL_DISA},
 	{"lcd_data15.lcd_data15",	OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
 						       | AM33XX_PULL_DISA},
 	{"gpmc_ad8.lcd_data16",		OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
 	{"gpmc_ad9.lcd_data17",		OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
 	{"gpmc_ad10.lcd_data18",	OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
 	{"gpmc_ad11.lcd_data19",	OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
 	{"gpmc_ad12.lcd_data20",	OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
 	{"gpmc_ad13.lcd_data21",	OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
 	{"gpmc_ad14.lcd_data22",	OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
 	{"gpmc_ad15.lcd_data23",	OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
 	{"lcd_vsync.lcd_vsync",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
 	{"lcd_hsync.lcd_hsync",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
 	{"lcd_pclk.lcd_pclk",		OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
 	{"lcd_ac_bias_en.lcd_ac_bias_en", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
 	{NULL, 0},
 };
 static struct pinmux_config tsc_pin_mux[] = {
 	{"ain0.ain0",           OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
 	{"ain1.ain1",           OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
 	{"ain2.ain2",           OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
 	{"ain3.ain3",           OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
 	{"vrefp.vrefp",         OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
 	{"vrefn.vrefn",         OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
 	{NULL, 0},
 };
 /* Pin mux for nand flash module */
 static struct pinmux_config nand_pin_mux[] = {
 	{"gpmc_ad0.gpmc_ad0",	  OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 	{"gpmc_ad1.gpmc_ad1",	  OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 	{"gpmc_ad2.gpmc_ad2",	  OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 	{"gpmc_ad3.gpmc_ad3",	  OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 	{"gpmc_ad4.gpmc_ad4",	  OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 	{"gpmc_ad5.gpmc_ad5",	  OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 	{"gpmc_ad6.gpmc_ad6",	  OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 	{"gpmc_ad7.gpmc_ad7",	  OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 	{"gpmc_wait0.gpmc_wait0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 	{"gpmc_wpn.gpmc_wpn",	  OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
 	{"gpmc_csn0.gpmc_csn0",	  OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
 	{"gpmc_advn_ale.gpmc_advn_ale",  OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
 	{"gpmc_oen_ren.gpmc_oen_ren",	 OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
 	{"gpmc_wen.gpmc_wen",     OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
 	{"gpmc_ben0_cle.gpmc_ben0_cle",	 OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
 	{NULL, 0},
 };
 /* Module pin mux for SPI fash */
 static struct pinmux_config spi0_pin_mux[] = {
 	{"spi0_sclk.spi0_sclk", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL
 							| AM33XX_INPUT_EN},
 	{"spi0_d0.spi0_d0", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL | AM33XX_PULL_UP
 							| AM33XX_INPUT_EN},
 	{"spi0_d1.spi0_d1", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL
 							| AM33XX_INPUT_EN},
 	{"spi0_cs0.spi0_cs0", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL | AM33XX_PULL_UP
 							| AM33XX_INPUT_EN},
 	{NULL, 0},
 };
 /* Module pin mux for SPI flash */
 static struct pinmux_config spi1_pin_mux[] = {
 	{"mcasp0_aclkx.spi1_sclk", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
 		| AM33XX_INPUT_EN},
 	{"mcasp0_fsx.spi1_d0", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
 		| AM33XX_PULL_UP | AM33XX_INPUT_EN},
 	{"mcasp0_axr0.spi1_d1", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
 		| AM33XX_INPUT_EN},
 	{"mcasp0_ahclkr.spi1_cs0", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
 		| AM33XX_PULL_UP | AM33XX_INPUT_EN},
 	{NULL, 0},
 };
 /* Module pin mux for rgmii1 */
 static struct pinmux_config rgmii1_pin_mux[] = {
 	{"mii1_txen.rgmii1_tctl", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
 	{"mii1_rxdv.rgmii1_rctl", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
 	{"mii1_txd3.rgmii1_td3", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
 	{"mii1_txd2.rgmii1_td2", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
 	{"mii1_txd1.rgmii1_td1", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
 	{"mii1_txd0.rgmii1_td0", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
 	{"mii1_txclk.rgmii1_tclk", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
 	{"mii1_rxclk.rgmii1_rclk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
 	{"mii1_rxd3.rgmii1_rd3", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
 	{"mii1_rxd2.rgmii1_rd2", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
 	{"mii1_rxd1.rgmii1_rd1", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
 	{"mii1_rxd0.rgmii1_rd0", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
 	{"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 	{"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
 	{NULL, 0},
 };
 /* Module pin mux for rgmii2 */
 static struct pinmux_config rgmii2_pin_mux[] = {
 	{"gpmc_a0.rgmii2_tctl", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
 	{"gpmc_a1.rgmii2_rctl", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
 	{"gpmc_a2.rgmii2_td3", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
 	{"gpmc_a3.rgmii2_td2", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
 	{"gpmc_a4.rgmii2_td1", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
 	{"gpmc_a5.rgmii2_td0", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
 	{"gpmc_a6.rgmii2_tclk", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
 	{"gpmc_a7.rgmii2_rclk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
 	{"gpmc_a8.rgmii2_rd3", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
 	{"gpmc_a9.rgmii2_rd2", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
 	{"gpmc_a10.rgmii2_rd1", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
 	{"gpmc_a11.rgmii2_rd0", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
 	{"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 	{"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
 	{NULL, 0},
 };
 /* Module pin mux for mii1 */
 static struct pinmux_config mii1_pin_mux[] = {
 	{"mii1_rxerr.mii1_rxerr", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
 	{"mii1_txen.mii1_txen", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
 	{"mii1_rxdv.mii1_rxdv", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
 	{"mii1_txd3.mii1_txd3", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
 	{"mii1_txd2.mii1_txd2", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
 	{"mii1_txd1.mii1_txd1", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
 	{"mii1_txd0.mii1_txd0", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
 	{"mii1_txclk.mii1_txclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
 	{"mii1_rxclk.mii1_rxclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
 	{"mii1_rxd3.mii1_rxd3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
 	{"mii1_rxd2.mii1_rxd2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
 	{"mii1_rxd1.mii1_rxd1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
 	{"mii1_rxd0.mii1_rxd0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
 	{"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 	{"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
 	{NULL, 0},
 };
 /* Module pin mux for rmii1 */
 static struct pinmux_config rmii1_pin_mux[] = {
 	{"mii1_crs.rmii1_crs_dv", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
 	{"mii1_rxerr.mii1_rxerr", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
 	{"mii1_txen.mii1_txen", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
 	{"mii1_txd1.mii1_txd1", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
 	{"mii1_txd0.mii1_txd0", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
 	{"mii1_rxd1.mii1_rxd1", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
 	{"mii1_rxd0.mii1_rxd0", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
 	{"rmii1_refclk.rmii1_refclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
 	{"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 	{"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
 	{NULL, 0},
 };
 static struct pinmux_config i2c1_pin_mux[] = {
 	{"spi0_d1.i2c1_sda",    OMAP_MUX_MODE2 | AM33XX_SLEWCTRL_SLOW |
 					AM33XX_PULL_ENBL | AM33XX_INPUT_EN},
 	{"spi0_cs0.i2c1_scl",   OMAP_MUX_MODE2 | AM33XX_SLEWCTRL_SLOW |
 					AM33XX_PULL_ENBL | AM33XX_INPUT_EN},
 	{NULL, 0},
 };
 /* Module pin mux for mcasp1 */
 static struct pinmux_config mcasp1_pin_mux[] = {
 	{"mii1_crs.mcasp1_aclkx", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
 	{"mii1_rxerr.mcasp1_fsx", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
 	{"mii1_col.mcasp1_axr2", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
 	{"rmii1_refclk.mcasp1_axr3", OMAP_MUX_MODE4 |
 						AM33XX_PIN_INPUT_PULLDOWN},
 	{NULL, 0},
 };
 /* Module pin mux for mmc0 */
 static struct pinmux_config mmc0_pin_mux[] = {
 	{"mmc0_dat3.mmc0_dat3",	OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 	{"mmc0_dat2.mmc0_dat2",	OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 	{"mmc0_dat1.mmc0_dat1",	OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 	{"mmc0_dat0.mmc0_dat0",	OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 	{"mmc0_clk.mmc0_clk",	OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 	{"mmc0_cmd.mmc0_cmd",	OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 	{"mcasp0_aclkr.mmc0_sdwp", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
 	{"spi0_cs1.mmc0_sdcd",  OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
 	{NULL, 0},
 };
 static struct pinmux_config mmc0_no_cd_pin_mux[] = {
 	{"mmc0_dat3.mmc0_dat3",	OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 	{"mmc0_dat2.mmc0_dat2",	OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 	{"mmc0_dat1.mmc0_dat1",	OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 	{"mmc0_dat0.mmc0_dat0",	OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 	{"mmc0_clk.mmc0_clk",	OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 	{"mmc0_cmd.mmc0_cmd",	OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 	{"mcasp0_aclkr.mmc0_sdwp", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
 	{NULL, 0},
 };
 /* Module pin mux for mmc1 */
 static struct pinmux_config mmc1_pin_mux[] = {
 	{"gpmc_ad7.mmc1_dat7",	OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
 	{"gpmc_ad6.mmc1_dat6",	OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
 	{"gpmc_ad5.mmc1_dat5",	OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
 	{"gpmc_ad4.mmc1_dat4",	OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
 	{"gpmc_ad3.mmc1_dat3",	OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
 	{"gpmc_ad2.mmc1_dat2",	OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
 	{"gpmc_ad1.mmc1_dat1",	OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
 	{"gpmc_ad0.mmc1_dat0",	OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
 	{"gpmc_csn1.mmc1_clk",	OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
 	{"gpmc_csn2.mmc1_cmd",	OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
 	{"gpmc_csn0.mmc1_sdwp",	OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
 	{"gpmc_advn_ale.mmc1_sdcd", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
 	{NULL, 0},
 };
 /* Module pin mux for uart3 */
 static struct pinmux_config uart3_pin_mux[] = {
 	{"spi0_cs1.uart3_rxd", AM33XX_PIN_INPUT_PULLUP},
 	{"ecap0_in_pwm0_out.uart3_txd", AM33XX_PULL_ENBL},
 	{NULL, 0},
 };
 static struct pinmux_config d_can_gp_pin_mux[] = {
 	{"uart0_ctsn.d_can1_tx", OMAP_MUX_MODE2 | AM33XX_PULL_ENBL},
 	{"uart0_rtsn.d_can1_rx", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
 	{NULL, 0},
 };
 static struct pinmux_config d_can_ia_pin_mux[] = {
 	{"uart0_rxd.d_can0_tx", OMAP_MUX_MODE2 | AM33XX_PULL_ENBL},
 	{"uart0_txd.d_can0_rx", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
 	{NULL, 0},
 };
+/* Module pin mux for uart2 */
+static struct pinmux_config uart2_pin_mux[] = {
+	{"spi0_sclk.uart2_rxd", OMAP_MUX_MODE1 | AM33XX_SLEWCTRL_SLOW |
+						AM33XX_PIN_INPUT_PULLUP},
+	{"spi0_d0.uart2_txd", OMAP_MUX_MODE1 | AM33XX_PULL_UP |
+						AM33XX_PULL_DISA |
+						AM33XX_SLEWCTRL_SLOW},
+	{NULL, 0},
+};
 /*
 * @pin_mux - single module pin-mux structure which defines pin-mux
 *			details for all its pins.
 */
 static void setup_pin_mux(struct pinmux_config *pin_mux)
 {
 	int i;
 	for (i = 0; pin_mux->string_name != NULL; pin_mux++)
 		omap_mux_init_signal(pin_mux->string_name, pin_mux->val);
 }
 /* Matrix GPIO Keypad Support for profile-0 only: TODO */
 /* pinmux for keypad device */
 static struct pinmux_config matrix_keypad_pin_mux[] = {
 	{"gpmc_a5.gpio1_21",  OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
 	{"gpmc_a6.gpio1_22",  OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
 	{"gpmc_a9.gpio1_25",  OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
 	{"gpmc_a10.gpio1_26", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
 	{"gpmc_a11.gpio1_27", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
 	{NULL, 0},
 };
 /* Keys mapping */
 static const uint32_t am335x_evm_matrix_keys[] = {
 	KEY(0, 0, KEY_MENU),
 	KEY(1, 0, KEY_BACK),
 	KEY(2, 0, KEY_LEFT),
 	KEY(0, 1, KEY_RIGHT),
 	KEY(1, 1, KEY_ENTER),
 	KEY(2, 1, KEY_DOWN),
 };
 const struct matrix_keymap_data am335x_evm_keymap_data = {
 	.keymap      = am335x_evm_matrix_keys,
 	.keymap_size = ARRAY_SIZE(am335x_evm_matrix_keys),
 };
 static const unsigned int am335x_evm_keypad_row_gpios[] = {
 	GPIO_TO_PIN(1, 25), GPIO_TO_PIN(1, 26), GPIO_TO_PIN(1, 27)
 };
 static const unsigned int am335x_evm_keypad_col_gpios[] = {
 	GPIO_TO_PIN(1, 21), GPIO_TO_PIN(1, 22)
 };
 static struct matrix_keypad_platform_data am335x_evm_keypad_platform_data = {
 	.keymap_data       = &am335x_evm_keymap_data,
 	.row_gpios         = am335x_evm_keypad_row_gpios,
 	.num_row_gpios     = ARRAY_SIZE(am335x_evm_keypad_row_gpios),
 	.col_gpios         = am335x_evm_keypad_col_gpios,
 	.num_col_gpios     = ARRAY_SIZE(am335x_evm_keypad_col_gpios),
 	.active_low        = false,
 	.debounce_ms       = 5,
 	.col_scan_delay_us = 2,
 };
 static struct platform_device am335x_evm_keyboard = {
 	.name  = "matrix-keypad",
 	.id    = -1,
 	.dev   = {
 		.platform_data = &am335x_evm_keypad_platform_data,
 	},
 };
 static void matrix_keypad_init(int evm_id, int profile)
 {
 	int err;
 	setup_pin_mux(matrix_keypad_pin_mux);
 	err = platform_device_register(&am335x_evm_keyboard);
 	if (err) {
 		pr_err("failed to register matrix keypad (2x3) device\n");
 	}
 }
 /* pinmux for keypad device */
 static struct pinmux_config volume_keys_pin_mux[] = {
 	{"spi0_sclk.gpio0_2",  OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
 	{"spi0_d0.gpio0_3",    OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
 	{NULL, 0},
 };
 /* Configure GPIOs for Volume Keys */
 static struct gpio_keys_button am335x_evm_volume_gpio_buttons[] = {
 	{
 		.code                   = KEY_VOLUMEUP,
 		.gpio                   = GPIO_TO_PIN(0, 2),
 		.active_low             = true,
 		.desc                   = "volume-up",
 		.type                   = EV_KEY,
 		.wakeup                 = 1,
 	},
 	{
 		.code                   = KEY_VOLUMEDOWN,
 		.gpio                   = GPIO_TO_PIN(0, 3),
 		.active_low             = true,
 		.desc                   = "volume-down",
 		.type                   = EV_KEY,
 		.wakeup                 = 1,
 	},
 };
 static struct gpio_keys_platform_data am335x_evm_volume_gpio_key_info = {
 	.buttons        = am335x_evm_volume_gpio_buttons,
 	.nbuttons       = ARRAY_SIZE(am335x_evm_volume_gpio_buttons),
 };
 static struct platform_device am335x_evm_volume_keys = {
 	.name   = "gpio-keys",
 	.id     = -1,
 	.dev    = {
 		.platform_data  = &am335x_evm_volume_gpio_key_info,
 	},
 };
 static void volume_keys_init(int evm_id, int profile)
 {
 	int err;
 	setup_pin_mux(volume_keys_pin_mux);
 	err = platform_device_register(&am335x_evm_volume_keys);
 	if (err)
 		pr_err("failed to register matrix keypad (2x3) device\n");
 }
 /*
 * @evm_id - evm id which needs to be configured
 * @dev_cfg - single evm structure which includes
 *				all module inits, pin-mux defines
 * @profile - if present, else PROFILE_NONE
 * @dghtr_brd_flg - Whether Daughter board is present or not
 */
 static void _configure_device(int evm_id, struct evm_dev_cfg *dev_cfg,
 	int profile)
 {
 	int i;
 	/*
 	* Only General Purpose & Industrial Auto Motro Control
 	* EVM has profiles. So check if this evm has profile.
 	* If not, ignore the profile comparison
 	*/
 	/*
 	* If the device is on baseboard, directly configure it. Else (device on
 	* Daughter board), check if the daughter card is detected.
 	*/
 	if (profile == PROFILE_NONE) {
 		for (i = 0; dev_cfg->device_init != NULL; dev_cfg++) {
 			if (dev_cfg->device_on == DEV_ON_BASEBOARD)
 				dev_cfg->device_init(evm_id, profile);
 			else if (daughter_brd_detected == true)
 				dev_cfg->device_init(evm_id, profile);
 		}
 	} else {
 		for (i = 0; dev_cfg->device_init != NULL; dev_cfg++) {
 			if (dev_cfg->profile & profile) {
 				if (dev_cfg->device_on == DEV_ON_BASEBOARD)
 					dev_cfg->device_init(evm_id, profile);
 				else if (daughter_brd_detected == true)
 					dev_cfg->device_init(evm_id, profile);
 			}
 		}
 	}
 }
 #define AM335X_LCD_BL_PIN	GPIO_TO_PIN(0, 7)
 /* pinmux for usb0 drvvbus */
 static struct pinmux_config usb0_pin_mux[] = {
 	{"usb0_drvvbus.usb0_drvvbus",    OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
 	{NULL, 0},
 };
 /* pinmux for usb1 drvvbus */
 static struct pinmux_config usb1_pin_mux[] = {
 	{"usb1_drvvbus.usb1_drvvbus",    OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
 	{NULL, 0},
 };
 /* pinmux for profibus */
 static struct pinmux_config profibus_pin_mux[] = {
 	{"uart1_rxd.pr1_uart0_rxd_mux1", OMAP_MUX_MODE5 | AM33XX_PIN_INPUT},
 	{"uart1_txd.pr1_uart0_txd_mux1", OMAP_MUX_MODE5 | AM33XX_PIN_OUTPUT},
 	{"mcasp0_fsr.pr1_pru0_pru_r30_5", OMAP_MUX_MODE5 | AM33XX_PIN_OUTPUT},
 	{NULL, 0},
 };
 /* Module pin mux for eCAP0 */
 static struct pinmux_config ecap0_pin_mux[] = {
 	{"ecap0_in_pwm0_out.gpio0_7", AM33XX_PIN_OUTPUT},
 	{NULL, 0},
 };
 #define AM335XEVM_WLAN_IRQ_GPIO		GPIO_TO_PIN(3, 17)
 struct wl12xx_platform_data am335xevm_wlan_data = {
 	.irq = OMAP_GPIO_IRQ(AM335XEVM_WLAN_IRQ_GPIO),
 	.board_ref_clock = WL12XX_REFCLOCK_38_XTAL, /* 38.4Mhz */
 };
 /* Module pin mux for wlan and bluetooth */
 static struct pinmux_config mmc2_wl12xx_pin_mux[] = {
 	{"gpmc_a1.mmc2_dat0", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
 	{"gpmc_a2.mmc2_dat1", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
 	{"gpmc_a3.mmc2_dat2", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
 	{"gpmc_ben1.mmc2_dat3", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
 	{"gpmc_csn3.mmc2_cmd", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
 	{"gpmc_clk.mmc2_clk", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
 	{NULL, 0},
 };
 static struct pinmux_config uart1_wl12xx_pin_mux[] = {
 	{"uart1_ctsn.uart1_ctsn", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
 	{"uart1_rtsn.uart1_rtsn", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT},
 	{"uart1_rxd.uart1_rxd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 	{"uart1_txd.uart1_txd", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL},
 	{NULL, 0},
 };
 static struct pinmux_config wl12xx_pin_mux_evm_rev1_1a[] = {
 	{"gpmc_a0.gpio1_16", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
 	{"mcasp0_ahclkr.gpio3_17", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
 	{"mcasp0_ahclkx.gpio3_21", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
 	{NULL, 0},
  };
 static struct pinmux_config wl12xx_pin_mux_evm_rev1_0[] = {
 	{"gpmc_csn1.gpio1_30", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
 	{"mcasp0_ahclkr.gpio3_17", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
 	{"gpmc_csn2.gpio1_31", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
 	{NULL, 0},
  };
 static int backlight_enable = false;
 static void enable_ecap0(int evm_id, int profile)
 {
 	backlight_enable = true;
 }
 static int __init ecap0_init(void)
 {
 	int status = 0;
 	if (backlight_enable) {
 		setup_pin_mux(ecap0_pin_mux);
 		status = gpio_request(AM335X_LCD_BL_PIN, "lcd bl\n");
 		if (status < 0)
 			pr_warn("Failed to request gpio for LCD backlight\n");
 		gpio_direction_output(AM335X_LCD_BL_PIN, 1);
 	}
 	return status;
 }
 late_initcall(ecap0_init);
 static int __init conf_disp_pll(int rate)
 {
 	struct clk *disp_pll;
 	int ret = -EINVAL;
 	disp_pll = clk_get(NULL, "dpll_disp_ck");
 	if (IS_ERR(disp_pll)) {
 		pr_err("Cannot clk_get disp_pll\n");
 		goto out;
 	}
 	ret = clk_set_rate(disp_pll, rate);
 	clk_put(disp_pll);
 out:
 	return ret;
 }
 static void lcdc_init(int evm_id, int profile)
 {
 	setup_pin_mux(lcdc_pin_mux);
 	if (conf_disp_pll(300000000)) {
 		pr_info("Failed configure display PLL, not attempting to"
 				"register LCDC\n");
 		return;
 	}
 	if (am33xx_register_lcdc(&TFC_S9700RTWV35TR_01B_pdata))
 		pr_info("Failed to register LCDC device\n");
 	return;
 }
 static void tsc_init(int evm_id, int profile)
 {
 	int err;
 	if (gp_evm_revision == GP_EVM_REV_IS_1_1A) {
 		am335x_touchscreen_data.analog_input = 1;
 		pr_info("TSC connected to beta GP EVM\n");
 	} else {
 		am335x_touchscreen_data.analog_input = 0;
 		pr_info("TSC connected to alpha GP EVM\n");
 	}
 	setup_pin_mux(tsc_pin_mux);
 	err = platform_device_register(&tsc_device);
 	if (err)
 		pr_err("failed to register touchscreen device\n");
 }
 static void rgmii1_init(int evm_id, int profile)
 {
 	setup_pin_mux(rgmii1_pin_mux);
 	return;
 }
 static void rgmii2_init(int evm_id, int profile)
 {
 	setup_pin_mux(rgmii2_pin_mux);
 	return;
 }
 static void mii1_init(int evm_id, int profile)
 {
 	setup_pin_mux(mii1_pin_mux);
 	return;
 }
 static void rmii1_init(int evm_id, int profile)
 {
 	setup_pin_mux(rmii1_pin_mux);
 	return;
 }
 static void usb0_init(int evm_id, int profile)
 {
 	setup_pin_mux(usb0_pin_mux);
 	return;
 }
 static void usb1_init(int evm_id, int profile)
 {
 	setup_pin_mux(usb1_pin_mux);
 	return;
 }
 /* setup uart3 */
 static void uart3_init(int evm_id, int profile)
 {
 	setup_pin_mux(uart3_pin_mux);
 	return;
 }
+/* setup uart2 */
+static void uart2_init(int evm_id, int profile)
+{
+	setup_pin_mux(uart2_pin_mux);
+	return;
+}
 /* NAND partition information */
 static struct mtd_partition am335x_nand_partitions[] = {
 /* All the partition sizes are listed in terms of NAND block size */
 	{
 		.name           = "SPL",
 		.offset         = 0,			/* Offset = 0x0 */
 		.size           = SZ_128K,
 	},
 	{
 		.name           = "SPL.backup1",
 		.offset         = MTDPART_OFS_APPEND,	/* Offset = 0x20000 */
 		.size           = SZ_128K,
 	},
 	{
 		.name           = "SPL.backup2",
 		.offset         = MTDPART_OFS_APPEND,	/* Offset = 0x40000 */
 		.size           = SZ_128K,
 	},
 	{
 		.name           = "SPL.backup3",
 		.offset         = MTDPART_OFS_APPEND,	/* Offset = 0x60000 */
 		.size           = SZ_128K,
 	},
 	{
 		.name           = "U-Boot",
 		.offset         = MTDPART_OFS_APPEND,   /* Offset = 0x80000 */
 		.size           = 15 * SZ_128K,
 	},
 	{
 		.name           = "U-Boot Env",
 		.offset         = MTDPART_OFS_APPEND,   /* Offset = 0x260000 */
 		.size           = 1 * SZ_128K,
 	},
 	{
 		.name           = "Kernel",
 		.offset         = MTDPART_OFS_APPEND,   /* Offset = 0x280000 */
 		.size           = 40 * SZ_128K,
 	},
 	{
 		.name           = "File System",
 		.offset         = MTDPART_OFS_APPEND,   /* Offset = 0x780000 */
 		.size           = MTDPART_SIZ_FULL,
 	},
 };
 /* SPI 0/1 Platform Data */
 /* SPI flash information */
 static struct mtd_partition am335x_spi_partitions[] = {
 	/* All the partition sizes are listed in terms of erase size */
 	{
 		.name       = "U-Boot-min",
 		.offset     = 0,
 		.size       = SZ_128K,
 		.mask_flags = MTD_WRITEABLE,    /* force read-only */
 	},
 	{
 		.name       = "U-Boot",
 		.offset     = MTDPART_OFS_APPEND,
 		.size       = 2 * SZ_128K,
 		.mask_flags = MTD_WRITEABLE,    /* force read-only */
 	},
 	{
 		.name       = "U-Boot Env",
 		.offset     = MTDPART_OFS_APPEND,
 		.size       = 2 * SZ_4K,
 	},
 	{
 		.name       = "Kernel",
 		.offset     = MTDPART_OFS_APPEND,
 		.size       = 28 * SZ_128K,
 	},
 	{
 		.name       = "File System",
 		.offset     = MTDPART_OFS_APPEND,
 		.size       = MTDPART_SIZ_FULL,     /* size ~= 1.1 MiB */
 	}
 };
 static const struct flash_platform_data am335x_spi_flash = {
 	.type      = "w25q64",
 	.name      = "spi_flash",
 	.parts     = am335x_spi_partitions,
 	.nr_parts  = ARRAY_SIZE(am335x_spi_partitions),
 };
 /*
  * SPI Flash works at 80Mhz however SPI Controller works at 48MHz.
  * So setup Max speed to be less than that of Controller speed
  */
 static struct spi_board_info am335x_spi0_slave_info[] = {
 	{
 		.modalias      = "m25p80",
 		.platform_data = &am335x_spi_flash,
 		.irq           = -1,
 		.max_speed_hz  = 24000000,
 		.bus_num       = 1,
 		.chip_select   = 0,
 	},
 };
 static struct spi_board_info am335x_spi1_slave_info[] = {
 	{
 		.modalias      = "m25p80",
 		.platform_data = &am335x_spi_flash,
 		.irq           = -1,
 		.max_speed_hz  = 12000000,
 		.bus_num       = 2,
 		.chip_select   = 0,
 	},
 };
 static void evm_nand_init(int evm_id, int profile)
 {
 	setup_pin_mux(nand_pin_mux);
 	board_nand_init(am335x_nand_partitions,
 		ARRAY_SIZE(am335x_nand_partitions), 0, 0);
 }
 static struct lis3lv02d_platform_data lis331dlh_pdata = {
 	.click_flags = LIS3_CLICK_SINGLE_X |
 			LIS3_CLICK_SINGLE_Y |
 			LIS3_CLICK_SINGLE_Z,
 	.wakeup_flags = LIS3_WAKEUP_X_LO | LIS3_WAKEUP_X_HI |
 			LIS3_WAKEUP_Y_LO | LIS3_WAKEUP_Y_HI |
 			LIS3_WAKEUP_Z_LO | LIS3_WAKEUP_Z_HI,
 	.irq_cfg = LIS3_IRQ1_CLICK | LIS3_IRQ2_CLICK,
 	.wakeup_thresh	= 10,
 	.click_thresh_x = 10,
 	.click_thresh_y = 10,
 	.click_thresh_z = 10,
 	.g_range	= 2,
 	.st_min_limits[0] = 120,
 	.st_min_limits[1] = 120,
 	.st_min_limits[2] = 140,
 	.st_max_limits[0] = 550,
 	.st_max_limits[1] = 550,
 	.st_max_limits[2] = 750,
 };
 static struct i2c_board_info am335x_i2c_boardinfo1[] = {
 	{
 		I2C_BOARD_INFO("tlv320aic3x", 0x1b),
 	},
 	{
 		I2C_BOARD_INFO("lis331dlh", 0x18),
 		.platform_data = &lis331dlh_pdata,
 	},
 	{
 		I2C_BOARD_INFO("tsl2550", 0x39),
 	},
 	{
 		I2C_BOARD_INFO("tmp275", 0x48),
 	},
 };
 static void i2c1_init(int evm_id, int profile)
 {
 	setup_pin_mux(i2c1_pin_mux);
 	omap_register_i2c_bus(2, 100, am335x_i2c_boardinfo1,
 			ARRAY_SIZE(am335x_i2c_boardinfo1));
 	return;
 }
 /* Setup McASP 1 */
 static void mcasp1_init(int evm_id, int profile)
 {
 	/* Configure McASP */
 	setup_pin_mux(mcasp1_pin_mux);
 	am335x_register_mcasp1(&am335x_evm_snd_data1);
 	return;
 }
 static void mmc1_init(int evm_id, int profile)
 {
 	setup_pin_mux(mmc1_pin_mux);
 	am335x_mmc[1].mmc = 2;
 	am335x_mmc[1].caps = MMC_CAP_4_BIT_DATA;
 	am335x_mmc[1].gpio_cd = GPIO_TO_PIN(2, 2);
 	am335x_mmc[1].gpio_wp = GPIO_TO_PIN(1, 29);
 	am335x_mmc[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */
 	/* mmc will be initialized when mmc0_init is called */
 	return;
 }
 static void mmc2_wl12xx_init(int evm_id, int profile)
 {
 	setup_pin_mux(mmc2_wl12xx_pin_mux);
 	am335x_mmc[1].mmc = 3;
 	am335x_mmc[1].name = "wl1271";
 	am335x_mmc[1].caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD
 				| MMC_PM_KEEP_POWER;
 	am335x_mmc[1].nonremovable = true;
 	am335x_mmc[1].gpio_cd = -EINVAL;
 	am335x_mmc[1].gpio_wp = -EINVAL;
 	am335x_mmc[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */
 	/* mmc will be initialized when mmc0_init is called */
 	return;
 }
 static void uart1_wl12xx_init(int evm_id, int profile)
 {
 	setup_pin_mux(uart1_wl12xx_pin_mux);
 }
 static void wl12xx_bluetooth_enable(void)
 {
 	int status = gpio_request(am335xevm_wlan_data.bt_enable_gpio,
 		"bt_en\n");
 	if (status < 0)
 		pr_err("Failed to request gpio for bt_enable");
 	pr_info("Configure Bluetooth Enable pin...\n");
 	gpio_direction_output(am335xevm_wlan_data.bt_enable_gpio, 0);
 }
 static int wl12xx_set_power(struct device *dev, int slot, int on, int vdd)
 {
 	if (on) {
 		gpio_set_value(am335xevm_wlan_data.wlan_enable_gpio, 1);
 		mdelay(70);
 	}
 	else
 		gpio_set_value(am335xevm_wlan_data.wlan_enable_gpio, 0);
 	return 0;
 }
 static void wl12xx_init(int evm_id, int profile)
 {
 	struct device *dev;
 	struct omap_mmc_platform_data *pdata;
 	int ret;
 	/* Register WLAN and BT enable pins based on the evm board revision */
 	if (gp_evm_revision == GP_EVM_REV_IS_1_1A) {
 		am335xevm_wlan_data.wlan_enable_gpio = GPIO_TO_PIN(1, 16);
 		am335xevm_wlan_data.bt_enable_gpio = GPIO_TO_PIN(3, 21);
 	}
 	else {
 		am335xevm_wlan_data.wlan_enable_gpio = GPIO_TO_PIN(1, 30);
 		am335xevm_wlan_data.bt_enable_gpio = GPIO_TO_PIN(1, 31);
 	}
 	wl12xx_bluetooth_enable();
 	if (wl12xx_set_platform_data(&am335xevm_wlan_data))
 		pr_err("error setting wl12xx data\n");
 	dev = am335x_mmc[1].dev;
 	if (!dev) {
 		pr_err("wl12xx mmc device initialization failed\n");
 		goto out;
 	}
 	pdata = dev->platform_data;
 	if (!pdata) {
 		pr_err("Platfrom data of wl12xx device not set\n");
 		goto out;
 	}
 	ret = gpio_request_one(am335xevm_wlan_data.wlan_enable_gpio,
 		GPIOF_OUT_INIT_LOW, "wlan_en");
 	if (ret) {
 		pr_err("Error requesting wlan enable gpio: %d\n", ret);
 		goto out;
 	}
 	if (gp_evm_revision == GP_EVM_REV_IS_1_1A)
 		setup_pin_mux(wl12xx_pin_mux_evm_rev1_1a);
 	else
 		setup_pin_mux(wl12xx_pin_mux_evm_rev1_0);
 	pdata->slots[0].set_power = wl12xx_set_power;
 out:
 	return;
 }
 static void d_can_init(int evm_id, int profile)
 {
 	switch (evm_id) {
 	case IND_AUT_MTR_EVM:
 		if ((profile == PROFILE_0) || (profile == PROFILE_1)) {
 			setup_pin_mux(d_can_ia_pin_mux);
 			/* Instance Zero */
 			am33xx_d_can_init(0);
 		}
 		break;
 	case GEN_PURP_EVM:
 		if (profile == PROFILE_1) {
 			setup_pin_mux(d_can_gp_pin_mux);
 			/* Instance One */
 			am33xx_d_can_init(1);
 		}
 		break;
 	default:
 		break;
 	}
 }
 static void mmc0_init(int evm_id, int profile)
 {
 	setup_pin_mux(mmc0_pin_mux);
 	omap2_hsmmc_init(am335x_mmc);
 	return;
 }
 static void mmc0_no_cd_init(int evm_id, int profile)
 {
 	setup_pin_mux(mmc0_no_cd_pin_mux);
 	omap2_hsmmc_init(am335x_mmc);
 	return;
 }
 /* setup spi0 */
 static void spi0_init(int evm_id, int profile)
 {
 	setup_pin_mux(spi0_pin_mux);
 	spi_register_board_info(am335x_spi0_slave_info,
 			ARRAY_SIZE(am335x_spi0_slave_info));
 	return;
 }
 /* setup spi1 */
 static void spi1_init(int evm_id, int profile)
 {
 	setup_pin_mux(spi1_pin_mux);
 	spi_register_board_info(am335x_spi1_slave_info,
 			ARRAY_SIZE(am335x_spi1_slave_info));
 	return;
 }
 static int beaglebone_phy_fixup(struct phy_device *phydev)
 {
 	phydev->supported &= ~(SUPPORTED_100baseT_Half |
 				SUPPORTED_100baseT_Full);
 	return 0;
 }
 #ifdef CONFIG_TLK110_WORKAROUND
 static int am335x_tlk110_phy_fixup(struct phy_device *phydev)
 {
 	unsigned int val;
 	/* This is done as a workaround to support TLK110 rev1.0 phy */
 	val = phy_read(phydev, TLK110_COARSEGAIN_REG);
 	phy_write(phydev, TLK110_COARSEGAIN_REG, (val | TLK110_COARSEGAIN_VAL));
 	val = phy_read(phydev, TLK110_LPFHPF_REG);
 	phy_write(phydev, TLK110_LPFHPF_REG, (val | TLK110_LPFHPF_VAL));
 	val = phy_read(phydev, TLK110_SPAREANALOG_REG);
 	phy_write(phydev, TLK110_SPAREANALOG_REG, (val | TLK110_SPANALOG_VAL));
 	val = phy_read(phydev, TLK110_VRCR_REG);
 	phy_write(phydev, TLK110_VRCR_REG, (val | TLK110_VRCR_VAL));
 	val = phy_read(phydev, TLK110_SETFFE_REG);
 	phy_write(phydev, TLK110_SETFFE_REG, (val | TLK110_SETFFE_VAL));
 	val = phy_read(phydev, TLK110_FTSP_REG);
 	phy_write(phydev, TLK110_FTSP_REG, (val | TLK110_FTSP_VAL));
 	val = phy_read(phydev, TLK110_ALFATPIDL_REG);
 	phy_write(phydev, TLK110_ALFATPIDL_REG, (val | TLK110_ALFATPIDL_VAL));
 	val = phy_read(phydev, TLK110_PSCOEF21_REG);
 	phy_write(phydev, TLK110_PSCOEF21_REG, (val | TLK110_PSCOEF21_VAL));
 	val = phy_read(phydev, TLK110_PSCOEF3_REG);
 	phy_write(phydev, TLK110_PSCOEF3_REG, (val | TLK110_PSCOEF3_VAL));
 	val = phy_read(phydev, TLK110_ALFAFACTOR1_REG);
 	phy_write(phydev, TLK110_ALFAFACTOR1_REG, (val | TLK110_ALFACTOR1_VAL));
 	val = phy_read(phydev, TLK110_ALFAFACTOR2_REG);
 	phy_write(phydev, TLK110_ALFAFACTOR2_REG, (val | TLK110_ALFACTOR2_VAL));
 	val = phy_read(phydev, TLK110_CFGPS_REG);
 	phy_write(phydev, TLK110_CFGPS_REG, (val | TLK110_CFGPS_VAL));
 	val = phy_read(phydev, TLK110_FTSPTXGAIN_REG);
 	phy_write(phydev, TLK110_FTSPTXGAIN_REG, (val | TLK110_FTSPTXGAIN_VAL));
 	val = phy_read(phydev, TLK110_SWSCR3_REG);
 	phy_write(phydev, TLK110_SWSCR3_REG, (val | TLK110_SWSCR3_VAL));
 	val = phy_read(phydev, TLK110_SCFALLBACK_REG);
 	phy_write(phydev, TLK110_SCFALLBACK_REG, (val | TLK110_SCFALLBACK_VAL));
 	val = phy_read(phydev, TLK110_PHYRCR_REG);
 	phy_write(phydev, TLK110_PHYRCR_REG, (val | TLK110_PHYRCR_VAL));
 	return 0;
 }
 #endif
 static void profibus_init(int evm_id, int profile)
 {
 	setup_pin_mux(profibus_pin_mux);
 	return;
 }
 /* Low-Cost EVM */
 static struct evm_dev_cfg low_cost_evm_dev_cfg[] = {
 	{rgmii1_init,	DEV_ON_BASEBOARD, PROFILE_NONE},
 	{usb0_init,	DEV_ON_BASEBOARD, PROFILE_NONE},
 	{usb1_init,	DEV_ON_BASEBOARD, PROFILE_NONE},
 	{evm_nand_init, DEV_ON_BASEBOARD, PROFILE_NONE},
 	{NULL, 0, 0},
 };
 /* General Purpose EVM */
 static struct evm_dev_cfg gen_purp_evm_dev_cfg[] = {
 	{enable_ecap0,	DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 |
 						PROFILE_2 | PROFILE_7) },
 	{lcdc_init,	DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 |
 						PROFILE_2 | PROFILE_7) },
 	{tsc_init,	DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 |
 						PROFILE_2 | PROFILE_7) },
 	{rgmii1_init,	DEV_ON_BASEBOARD, PROFILE_ALL},
 	{rgmii2_init,	DEV_ON_DGHTR_BRD, (PROFILE_1 | PROFILE_2 |
 						PROFILE_4 | PROFILE_6) },
 	{usb0_init,	DEV_ON_BASEBOARD, PROFILE_ALL},
 	{usb1_init,	DEV_ON_BASEBOARD, PROFILE_ALL},
 	{evm_nand_init, DEV_ON_DGHTR_BRD,
 		(PROFILE_ALL & ~PROFILE_2 & ~PROFILE_3)},
 	{i2c1_init,	DEV_ON_DGHTR_BRD, (PROFILE_ALL & ~PROFILE_2)},
 	{mcasp1_init,	DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_3 | PROFILE_7) },
 	{mmc1_init,	DEV_ON_DGHTR_BRD, PROFILE_2},
 	{mmc2_wl12xx_init,	DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 |
 								PROFILE_5)},
 	{mmc0_init,	DEV_ON_BASEBOARD, (PROFILE_ALL & ~PROFILE_5)},
 	{mmc0_no_cd_init,	DEV_ON_BASEBOARD, PROFILE_5},
 	{spi0_init,	DEV_ON_DGHTR_BRD, PROFILE_2},
 	{uart1_wl12xx_init,	DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 |
 								PROFILE_5)},
 	{wl12xx_init,	DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 | PROFILE_5)},
 	{d_can_init,	DEV_ON_DGHTR_BRD, PROFILE_1},
 	{matrix_keypad_init, DEV_ON_DGHTR_BRD, PROFILE_0},
 	{volume_keys_init,  DEV_ON_DGHTR_BRD, PROFILE_0},
+	{uart2_init,	DEV_ON_DGHTR_BRD, PROFILE_3},
 	{NULL, 0, 0},
 };
 /* Industrial Auto Motor Control EVM */
 static struct evm_dev_cfg ind_auto_mtrl_evm_dev_cfg[] = {
 	{mii1_init,	DEV_ON_DGHTR_BRD, PROFILE_ALL},
 	{usb0_init,	DEV_ON_BASEBOARD, PROFILE_ALL},
 	{usb1_init,	DEV_ON_BASEBOARD, PROFILE_ALL},
 	{profibus_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
 	{evm_nand_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
 	{spi1_init,	DEV_ON_DGHTR_BRD, PROFILE_ALL},
 	{uart3_init,	DEV_ON_DGHTR_BRD, PROFILE_ALL},
 	{i2c1_init,	DEV_ON_BASEBOARD, PROFILE_ALL},
 	{mmc0_no_cd_init,	DEV_ON_BASEBOARD, PROFILE_ALL},
 	{NULL, 0, 0},
 };
 /* IP-Phone EVM */
 static struct evm_dev_cfg ip_phn_evm_dev_cfg[] = {
 	{enable_ecap0,	DEV_ON_DGHTR_BRD, PROFILE_NONE},
 	{lcdc_init,	DEV_ON_DGHTR_BRD, PROFILE_NONE},
 	{tsc_init,	DEV_ON_DGHTR_BRD, PROFILE_NONE},
 	{rgmii1_init,	DEV_ON_BASEBOARD, PROFILE_NONE},
 	{rgmii2_init,	DEV_ON_DGHTR_BRD, PROFILE_NONE},
 	{usb0_init,	DEV_ON_BASEBOARD, PROFILE_NONE},
 	{usb1_init,	DEV_ON_BASEBOARD, PROFILE_NONE},
 	{evm_nand_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
 	{i2c1_init,	DEV_ON_BASEBOARD, PROFILE_NONE},
 	{mcasp1_init,	DEV_ON_DGHTR_BRD, PROFILE_NONE},
 	{mmc0_init,	DEV_ON_BASEBOARD, PROFILE_NONE},
 	{NULL, 0, 0},
 };
 /* Beaglebone < Rev A3 */
 static struct evm_dev_cfg beaglebone_old_dev_cfg[] = {
 	{rmii1_init,	DEV_ON_BASEBOARD, PROFILE_NONE},
 	{usb0_init,	DEV_ON_BASEBOARD, PROFILE_NONE},
 	{usb1_init,	DEV_ON_BASEBOARD, PROFILE_NONE},
 	{mmc0_init,	DEV_ON_BASEBOARD, PROFILE_NONE},
 	{NULL, 0, 0},
 };
 /* Beaglebone Rev A3 and after */
 static struct evm_dev_cfg beaglebone_dev_cfg[] = {
 	{mii1_init,	DEV_ON_BASEBOARD, PROFILE_NONE},
 	{usb0_init,	DEV_ON_BASEBOARD, PROFILE_NONE},
 	{usb1_init,	DEV_ON_BASEBOARD, PROFILE_NONE},
 	{mmc0_init,	DEV_ON_BASEBOARD, PROFILE_NONE},
 	{NULL, 0, 0},
 };
 static void setup_low_cost_evm(void)
 {
 	pr_info("The board is a AM335x Low Cost EVM.\n");
 	_configure_device(LOW_COST_EVM, low_cost_evm_dev_cfg, PROFILE_NONE);
 }
 static void setup_general_purpose_evm(void)
 {
 	u32 prof_sel = am335x_get_profile_selection();
 	pr_info("The board is general purpose EVM in profile %d\n", prof_sel);
 	if (!strncmp("1.1A", config.version, 4)) {
 		gp_evm_revision = GP_EVM_REV_IS_1_1A;
 	} else if (!strncmp("1.0", config.version, 3)) {
 		gp_evm_revision = GP_EVM_REV_IS_1_0;
 	} else {
 		pr_err("Found invalid GP EVM revision, falling back to Rev1.1A");
 		gp_evm_revision = GP_EVM_REV_IS_1_1A;
 	}
 	if (gp_evm_revision == GP_EVM_REV_IS_1_0)
 		gigabit_enable = 0;
 	else if (gp_evm_revision == GP_EVM_REV_IS_1_1A)
 		gigabit_enable = 1;
 	_configure_device(GEN_PURP_EVM, gen_purp_evm_dev_cfg, (1L << prof_sel));
 }
 static void setup_ind_auto_motor_ctrl_evm(void)
 {
 	u32 prof_sel = am335x_get_profile_selection();
 	pr_info("The board is an industrial automation EVM in profile %d\n",
 		prof_sel);
 	/* Only Profile 0 is supported */
 	if ((1L << prof_sel) != PROFILE_0) {
 		pr_err("AM335X: Only Profile 0 is supported\n");
 		pr_err("Assuming profile 0 & continuing\n");
 		prof_sel = PROFILE_0;
 	}
 	_configure_device(IND_AUT_MTR_EVM, ind_auto_mtrl_evm_dev_cfg,
 		PROFILE_0);
 	/* Fillup global evmid */
 	am33xx_evmid_fillup(IND_AUT_MTR_EVM);
 	/* Initialize TLK110 PHY registers for phy version 1.0 */
 	am335x_tlk110_phy_init();
 }
 static void setup_ip_phone_evm(void)
 {
 	pr_info("The board is an IP phone EVM\n");
 	_configure_device(IP_PHN_EVM, ip_phn_evm_dev_cfg, PROFILE_NONE);
 }
 /* BeagleBone < Rev A3 */
 static void setup_beaglebone_old(void)
 {
 	pr_info("The board is a AM335x Beaglebone < Rev A3.\n");
 	/* Beagle Bone has Micro-SD slot which doesn't have Write Protect pin */
 	am335x_mmc[0].gpio_wp = -EINVAL;
 	_configure_device(LOW_COST_EVM, beaglebone_old_dev_cfg, PROFILE_NONE);
 	phy_register_fixup_for_uid(BBB_PHY_ID, BBB_PHY_MASK,
 					beaglebone_phy_fixup);
 }
 /* BeagleBone after Rev A3 */
 static void setup_beaglebone(void)
 {
 	pr_info("The board is a AM335x Beaglebone.\n");
 	/* Beagle Bone has Micro-SD slot which doesn't have Write Protect pin */
 	am335x_mmc[0].gpio_wp = -EINVAL;
 	_configure_device(LOW_COST_EVM, beaglebone_dev_cfg, PROFILE_NONE);
 }
 static void am335x_setup_daughter_board(struct memory_accessor *m, void *c)
 {
 	u8 tmp;
 	int ret;
 	/*
 	 * try reading a byte from the EEPROM to see if it is
 	 * present. We could read a lot more, but that would
 	 * just slow the boot process and we have all the information
 	 * we need from the EEPROM on the base board anyway.
 	 */
 	ret = m->read(m, &tmp, 0, sizeof(u8));
 	if (ret == sizeof(u8)) {
 		pr_info("Detected a daughter card on AM335x EVM..");
 		daughter_brd_detected = true;
 	} else {
 		pr_info("No daughter card found\n");
 		daughter_brd_detected = false;
 	}
 }
 static void am335x_evm_setup(struct memory_accessor *mem_acc, void *context)
 {
 	int ret;
 	char tmp[10];
 	/* 1st get the MAC address from EEPROM */
 	ret = mem_acc->read(mem_acc, (char *)&am335x_mac_addr,
 		EEPROM_MAC_ADDRESS_OFFSET, sizeof(am335x_mac_addr));
 	if (ret != sizeof(am335x_mac_addr)) {
 		pr_warning("AM335X: EVM Config read fail: %d\n", ret);
 		return;
 	}
 	/* Fillup global mac id */
 	am33xx_cpsw_macidfillup(&am335x_mac_addr[0][0],
 				&am335x_mac_addr[1][0]);
 	/* get board specific data */
 	ret = mem_acc->read(mem_acc, (char *)&config, 0, sizeof(config));
 	if (ret != sizeof(config)) {
 		pr_warning("AM335X EVM config read fail, read %d bytes\n", ret);
 		return;
 	}
 	if (config.header != AM335X_EEPROM_HEADER) {
 		pr_warning("AM335X: wrong header 0x%x, expected 0x%x\n",
 			config.header, AM335X_EEPROM_HEADER);
 		goto out;
 	}
 	if (strncmp("A335", config.name, 4)) {
 		pr_err("Board %s doesn't look like an AM335x board\n",
 			config.name);
 		goto out;
 	}
 	snprintf(tmp, sizeof(config.name) + 1, "%s", config.name);
 	pr_info("Board name: %s\n", tmp);
 	snprintf(tmp, sizeof(config.version) + 1, "%s", config.version);
 	pr_info("Board version: %s\n", tmp);
 	if (!strncmp("A335BONE", config.name, 8)) {
 		daughter_brd_detected = false;
 		if(!strncmp("00A1", config.version, 4) ||
 		   !strncmp("00A2", config.version, 4))
 			setup_beaglebone_old();
 		else
 			setup_beaglebone();
 	} else {
 		/* only 6 characters of options string used for now */
 		snprintf(tmp, 7, "%s", config.opt);
 		pr_info("SKU: %s\n", tmp);
 		if (!strncmp("SKU#00", config.opt, 6))
 			setup_low_cost_evm();
 		else if (!strncmp("SKU#01", config.opt, 6))
 			setup_general_purpose_evm();
 		else if (!strncmp("SKU#02", config.opt, 6))
 			setup_ind_auto_motor_ctrl_evm();
 		else if (!strncmp("SKU#03", config.opt, 6))
 			setup_ip_phone_evm();
 		else
 			goto out;
 	}
 	/* Initialize cpsw after board detection is completed as board
 	 * information is required for configuring phy address and hence
 	 * should be call only after board detection
 	 */
 	am33xx_cpsw_init(gigabit_enable);
 	return;
 out:
 	/*
 	 * If the EEPROM hasn't been programed or an incorrect header
 	 * or board name are read, assume this is an old beaglebone board
 	 * (< Rev A3)
 	 */
 	pr_err("Could not detect any board, falling back to: "
 		"Beaglebone (< Rev A3) with no daughter card connected\n");
 	daughter_brd_detected = false;
 	setup_beaglebone_old();
 	/* Initialize cpsw after board detection is completed as board
 	 * information is required for configuring phy address and hence
 	 * should be call only after board detection
 	 */
 	am33xx_cpsw_init(gigabit_enable);
 }
 static struct at24_platform_data am335x_daughter_board_eeprom_info = {
 	.byte_len       = (256*1024) / 8,
 	.page_size      = 64,
 	.flags          = AT24_FLAG_ADDR16,
 	.setup          = am335x_setup_daughter_board,
 	.context        = (void *)NULL,
 };
 static struct at24_platform_data am335x_baseboard_eeprom_info = {
 	.byte_len       = (256*1024) / 8,
 	.page_size      = 64,
 	.flags          = AT24_FLAG_ADDR16,
 	.setup          = am335x_evm_setup,
 	.context        = (void *)NULL,
 };
 static struct regulator_init_data am335x_dummy;
 static struct regulator_consumer_supply am335x_vdd1_supply[] = {
 	REGULATOR_SUPPLY("mpu", "mpu.0"),
 };
 static struct regulator_init_data am335x_vdd1 = {
 	.constraints = {
 		.min_uV			= 600000,
 		.max_uV			= 1500000,
 		.valid_modes_mask	= REGULATOR_MODE_NORMAL,
 		.valid_ops_mask		= REGULATOR_CHANGE_VOLTAGE,
 		.always_on		= 1,
 	},
 	.num_consumer_supplies	= ARRAY_SIZE(am335x_vdd1_supply),
 	.consumer_supplies	= am335x_vdd1_supply,
 };
 static struct tps65910_board am335x_tps65910_info = {
 	.tps65910_pmic_init_data[TPS65910_REG_VRTC]	= &am335x_dummy,
 	.tps65910_pmic_init_data[TPS65910_REG_VIO]	= &am335x_dummy,
 	.tps65910_pmic_init_data[TPS65910_REG_VDD1]	= &am335x_vdd1,
 	.tps65910_pmic_init_data[TPS65910_REG_VDD2]	= &am335x_dummy,
 	.tps65910_pmic_init_data[TPS65910_REG_VDD3]	= &am335x_dummy,
 	.tps65910_pmic_init_data[TPS65910_REG_VDIG1]	= &am335x_dummy,
 	.tps65910_pmic_init_data[TPS65910_REG_VDIG2]	= &am335x_dummy,
 	.tps65910_pmic_init_data[TPS65910_REG_VPLL]	= &am335x_dummy,
 	.tps65910_pmic_init_data[TPS65910_REG_VDAC]	= &am335x_dummy,
 	.tps65910_pmic_init_data[TPS65910_REG_VAUX1]	= &am335x_dummy,
 	.tps65910_pmic_init_data[TPS65910_REG_VAUX2]	= &am335x_dummy,
 	.tps65910_pmic_init_data[TPS65910_REG_VAUX33]	= &am335x_dummy,
 	.tps65910_pmic_init_data[TPS65910_REG_VMMC]	= &am335x_dummy,
 };
 /*
 * Daughter board Detection.
 * Every board has a ID memory (EEPROM) on board. We probe these devices at
 * machine init, starting from daughter board and ending with baseboard.
 * Assumptions :
 *	1. probe for i2c devices are called in the order they are included in
 *	   the below struct. Daughter boards eeprom are probed 1st. Baseboard
 *	   eeprom probe is called last.
 */
 static struct i2c_board_info __initdata am335x_i2c_boardinfo[] = {
 	{
 		/* Daughter Board EEPROM */
 		I2C_BOARD_INFO("24c256", DAUG_BOARD_I2C_ADDR),
 		.platform_data  = &am335x_daughter_board_eeprom_info,
 	},
 	{
 		/* Baseboard board EEPROM */
 		I2C_BOARD_INFO("24c256", BASEBOARD_I2C_ADDR),
 		.platform_data  = &am335x_baseboard_eeprom_info,
 	},
 	{
 		I2C_BOARD_INFO("cpld_reg", 0x35),
 	},
 	{
 		I2C_BOARD_INFO("tlc59108", 0x40),
 	},
 	{
 		I2C_BOARD_INFO("tps65910", TPS65910_I2C_ID1),
 		.platform_data  = &am335x_tps65910_info,
 	},
 };
 static struct omap_musb_board_data musb_board_data = {
 	.interface_type	= MUSB_INTERFACE_ULPI,
 	.mode           = MUSB_OTG,
 	.power		= 500,
 	.instances	= 1,
 };
 static int cpld_reg_probe(struct i2c_client *client,
 	    const struct i2c_device_id *id)
 {
 	cpld_client = client;
 	return 0;
 }
 static int __devexit cpld_reg_remove(struct i2c_client *client)
 {
 	cpld_client = NULL;
 	return 0;
 }
 static const struct i2c_device_id cpld_reg_id[] = {
 	{ "cpld_reg", 0 },
 	{ }
 };
 static struct i2c_driver cpld_reg_driver = {
 	.driver = {
 		.name	= "cpld_reg",
 	},
 	.probe		= cpld_reg_probe,
 	.remove		= cpld_reg_remove,
 	.id_table	= cpld_reg_id,
 };
 static void evm_init_cpld(void)
 {
 	i2c_add_driver(&cpld_reg_driver);
 }
 static void __init am335x_evm_i2c_init(void)
 {
 	/* Initially assume Low Cost EVM Config */
 	am335x_evm_id = LOW_COST_EVM;
 	evm_init_cpld();
 	omap_register_i2c_bus(1, 100, am335x_i2c_boardinfo,
 				ARRAY_SIZE(am335x_i2c_boardinfo));
 }
 static struct resource am335x_rtc_resources[] = {
 	{
 		.start		= AM33XX_RTC_BASE,
 		.end		= AM33XX_RTC_BASE + SZ_4K - 1,
 		.flags		= IORESOURCE_MEM,
 	},
 	{ /* timer irq */
 		.start		= AM33XX_IRQ_RTC_TIMER,
 		.end		= AM33XX_IRQ_RTC_TIMER,
 		.flags		= IORESOURCE_IRQ,
 	},
 	{ /* alarm irq */
 		.start		= AM33XX_IRQ_RTC_ALARM,
 		.end		= AM33XX_IRQ_RTC_ALARM,
 		.flags		= IORESOURCE_IRQ,
 	},
 };
 static struct platform_device am335x_rtc_device = {
 	.name           = "omap_rtc",
 	.id             = -1,
 	.num_resources	= ARRAY_SIZE(am335x_rtc_resources),
 	.resource	= am335x_rtc_resources,
 };
 static int am335x_rtc_init(void)
 {
 	void __iomem *base;
 	struct clk *clk;
 	clk = clk_get(NULL, "rtc_fck");
 	if (IS_ERR(clk)) {
 		pr_err("rtc : Failed to get RTC clock\n");
 		return -1;
 	}
 	if (clk_enable(clk)) {
 		pr_err("rtc: Clock Enable Failed\n");
 		return -1;
 	}
 	base = ioremap(AM33XX_RTC_BASE, SZ_4K);
 	if (WARN_ON(!base))
 		return -ENOMEM;
 	/* Unlock the rtc's registers */
 	__raw_writel(0x83e70b13, base + 0x6c);
 	__raw_writel(0x95a4f1e0, base + 0x70);
 	/*
 	 * Enable the 32K OSc
 	 * TODO: Need a better way to handle this
 	 * Since we want the clock to be running before mmc init
 	 * we need to do it before the rtc probe happens
 	 */
 	__raw_writel(0x48, base + 0x54);
 	iounmap(base);
 	return  platform_device_register(&am335x_rtc_device);
 }
 /* Enable clkout2 */
 static struct pinmux_config clkout2_pin_mux[] = {
 	{"xdma_event_intr1.clkout2", OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT},
 	{NULL, 0},
 };
 static void __init clkout2_enable(void)
 {
 	struct clk *ck_32;
 	ck_32 = clk_get(NULL, "clkout2_ck");
 	if (IS_ERR(ck_32)) {
 		pr_err("Cannot clk_get ck_32\n");
 		return;
 	}
 	clk_enable(ck_32);
 	setup_pin_mux(clkout2_pin_mux);
 }
 void __iomem * __init am33xx_get_mem_ctlr(void)
 {
 	void __iomem *am33xx_emif_base;
 	am33xx_emif_base = ioremap(AM33XX_EMIF0_BASE, SZ_32K);
 	if (!am33xx_emif_base)
 		pr_warning("%s: Unable to map DDR2 controller",	__func__);
 	return am33xx_emif_base;
 }
 static struct resource am33xx_cpuidle_resources[] = {
 	{
 		.start		= AM33XX_EMIF0_BASE,
 		.end		= AM33XX_EMIF0_BASE + SZ_32K - 1,
 		.flags		= IORESOURCE_MEM,
 	},
 };
 /* AM33XX devices support DDR2 power down */
 static struct am33xx_cpuidle_config am33xx_cpuidle_pdata = {
 	.ddr2_pdown	= 1,
 };
 static struct platform_device am33xx_cpuidle_device = {
 	.name			= "cpuidle-am33xx",
 	.num_resources		= ARRAY_SIZE(am33xx_cpuidle_resources),
 	.resource		= am33xx_cpuidle_resources,
 	.dev = {
 		.platform_data	= &am33xx_cpuidle_pdata,
 	},
 };
 static void __init am33xx_cpuidle_init(void)
 {
 	int ret;
 	am33xx_cpuidle_pdata.emif_base = am33xx_get_mem_ctlr();
 	ret = platform_device_register(&am33xx_cpuidle_device);
 	if (ret)
 		pr_warning("AM33XX cpuidle registration failed\n");
 }
 static void __init am335x_evm_init(void)
 {
 	am33xx_cpuidle_init();
 	am33xx_mux_init(board_mux);
 	omap_serial_init();
 	am335x_rtc_init();
 	clkout2_enable();
 	am335x_evm_i2c_init();
 	omap_sdrc_init(NULL, NULL);
 	usb_musb_init(&musb_board_data);
 	omap_board_config = am335x_evm_config;
 	omap_board_config_size = ARRAY_SIZE(am335x_evm_config);
 	/* Create an alias for icss clock */
 	if (clk_add_alias("pruss", NULL, "icss_uart_gclk", NULL))
 		pr_err("failed to create an alias: icss_uart_gclk --> pruss\n");
 	/* Create an alias for gfx/sgx clock */
 	if (clk_add_alias("sgx_ck", NULL, "gfx_fclk", NULL))
 		pr_err("failed to create an alias: gfx_fclk --> sgx_ck\n");
 }
 static void __init am335x_evm_map_io(void)
 {
 	omap2_set_globals_am33xx();
 	omapam33xx_map_common_io();
 }
 MACHINE_START(AM335XEVM, "am335xevm")
 	/* Maintainer: Texas Instruments */
 	.atag_offset	= 0x100,
 	.map_io		= am335x_evm_map_io,
 	.init_irq	= ti816x_init_irq,
 	.init_early	= am335x_init_early,
 	.timer		= &omap3_am33xx_timer,
 	.init_machine	= am335x_evm_init,
 MACHINE_END
 MACHINE_START(AM335XIAEVM, "am335xiaevm")
 	/* Maintainer: Texas Instruments */
 	.atag_offset	= 0x100,
 	.map_io		= am335x_evm_map_io,
 	.init_irq	= ti816x_init_irq,
 	.init_early	= am335x_init_early,
 	.timer		= &omap3_am33xx_timer,
 	.init_machine	= am335x_evm_init,
 MACHINE_END

arch/arm/mach-omap2/mux33xx.c

Diff comments View file @ 94082f3

1	/*	1	/*
2	* AM33XX mux data	2	* AM33XX mux data
3	*	3	*
4	* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/	4	* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
5	*	5	*
6	* Derived from: arch/arm/mach-omap2/mux34xx.c Original copyright follows:	6	* Derived from: arch/arm/mach-omap2/mux34xx.c Original copyright follows:
7	*	7	*
8	* Copyright (C) 2009 Nokia	8	* Copyright (C) 2009 Nokia
9	* Copyright (C) 2009 Texas Instruments	9	* Copyright (C) 2009 Texas Instruments
10	*	10	*
11	* This program is free software; you can redistribute it and/or modify	11	* This program is free software; you can redistribute it and/or modify
12	* it under the terms of the GNU General Public License version 2 as	12	* it under the terms of the GNU General Public License version 2 as
13	* published by the Free Software Foundation.	13	* published by the Free Software Foundation.
14	*/	14	*/
15		15
16	#include <linux/module.h>	16	#include <linux/module.h>
17	#include <linux/init.h>	17	#include <linux/init.h>
18		18
19	#include "mux.h"	19	#include "mux.h"
20		20
21	#ifdef CONFIG_OMAP_MUX	21	#ifdef CONFIG_OMAP_MUX
22		22
23	#define _AM33XX_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \	23	#define _AM33XX_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \
24	{ \	24	{ \
25	.reg_offset = (AM33XX_CONTROL_PADCONF_##M0##_OFFSET), \	25	.reg_offset = (AM33XX_CONTROL_PADCONF_##M0##_OFFSET), \
26	.gpio = (g), \	26	.gpio = (g), \
27	.muxnames = { m0, m1, m2, m3, m4, m5, m6, m7 }, \	27	.muxnames = { m0, m1, m2, m3, m4, m5, m6, m7 }, \
28	}	28	}
29		29
30	/* AM33XX pin mux super set */	30	/* AM33XX pin mux super set */
31	static struct omap_mux __initdata am33xx_muxmodes[] = {	31	static struct omap_mux __initdata am33xx_muxmodes[] = {
32	_AM33XX_MUXENTRY(GPMC_AD0, 0,	32	_AM33XX_MUXENTRY(GPMC_AD0, 0,
33	"gpmc_ad0", "mmc1_dat0", NULL, NULL,	33	"gpmc_ad0", "mmc1_dat0", NULL, NULL,
34	NULL, NULL, NULL, NULL),	34	NULL, NULL, NULL, NULL),
35	_AM33XX_MUXENTRY(GPMC_AD1, 0,	35	_AM33XX_MUXENTRY(GPMC_AD1, 0,
36	"gpmc_ad1", "mmc1_dat1", NULL, NULL,	36	"gpmc_ad1", "mmc1_dat1", NULL, NULL,
37	NULL, NULL, NULL, NULL),	37	NULL, NULL, NULL, NULL),
38	_AM33XX_MUXENTRY(GPMC_AD2, 0,	38	_AM33XX_MUXENTRY(GPMC_AD2, 0,
39	"gpmc_ad2", "mmc1_dat2", NULL, NULL,	39	"gpmc_ad2", "mmc1_dat2", NULL, NULL,
40	NULL, NULL, NULL, NULL),	40	NULL, NULL, NULL, NULL),
41	_AM33XX_MUXENTRY(GPMC_AD3, 0,	41	_AM33XX_MUXENTRY(GPMC_AD3, 0,
42	"gpmc_ad3", "mmc1_dat3", NULL, NULL,	42	"gpmc_ad3", "mmc1_dat3", NULL, NULL,
43	NULL, NULL, NULL, NULL),	43	NULL, NULL, NULL, NULL),
44	_AM33XX_MUXENTRY(GPMC_AD4, 0,	44	_AM33XX_MUXENTRY(GPMC_AD4, 0,
45	"gpmc_ad4", "mmc1_dat4", NULL, NULL,	45	"gpmc_ad4", "mmc1_dat4", NULL, NULL,
46	NULL, NULL, NULL, NULL),	46	NULL, NULL, NULL, NULL),
47	_AM33XX_MUXENTRY(GPMC_AD5, 0,	47	_AM33XX_MUXENTRY(GPMC_AD5, 0,
48	"gpmc_ad5", "mmc1_dat5", NULL, NULL,	48	"gpmc_ad5", "mmc1_dat5", NULL, NULL,
49	NULL, NULL, NULL, NULL),	49	NULL, NULL, NULL, NULL),
50	_AM33XX_MUXENTRY(GPMC_AD6, 0,	50	_AM33XX_MUXENTRY(GPMC_AD6, 0,
51	"gpmc_ad6", "mmc1_dat6", NULL, NULL,	51	"gpmc_ad6", "mmc1_dat6", NULL, NULL,
52	NULL, NULL, NULL, NULL),	52	NULL, NULL, NULL, NULL),
53	_AM33XX_MUXENTRY(GPMC_AD7, 0,	53	_AM33XX_MUXENTRY(GPMC_AD7, 0,
54	"gpmc_ad7", "mmc1_dat7", NULL, NULL,	54	"gpmc_ad7", "mmc1_dat7", NULL, NULL,
55	NULL, NULL, NULL, NULL),	55	NULL, NULL, NULL, NULL),
56	_AM33XX_MUXENTRY(GPMC_AD8, 0,	56	_AM33XX_MUXENTRY(GPMC_AD8, 0,
57	"gpmc_ad8", "lcd_data16", "mmc1_dat0", "mmc2_dat4",	57	"gpmc_ad8", "lcd_data16", "mmc1_dat0", "mmc2_dat4",
58	NULL, NULL, NULL, NULL),	58	NULL, NULL, NULL, NULL),
59	_AM33XX_MUXENTRY(GPMC_AD9, 0,	59	_AM33XX_MUXENTRY(GPMC_AD9, 0,
60	"gpmc_ad9", "lcd_data17", "mmc1_dat1", "mmc2_dat5",	60	"gpmc_ad9", "lcd_data17", "mmc1_dat1", "mmc2_dat5",
61	NULL, NULL, NULL, NULL),	61	NULL, NULL, NULL, NULL),
62	_AM33XX_MUXENTRY(GPMC_AD10, 0,	62	_AM33XX_MUXENTRY(GPMC_AD10, 0,
63	"gpmc_ad10", "lcd_data18", "mmc1_dat2", "mmc2_dat6",	63	"gpmc_ad10", "lcd_data18", "mmc1_dat2", "mmc2_dat6",
64	NULL, NULL, NULL, NULL),	64	NULL, NULL, NULL, NULL),
65	_AM33XX_MUXENTRY(GPMC_AD11, 0,	65	_AM33XX_MUXENTRY(GPMC_AD11, 0,
66	"gpmc_ad11", "lcd_data19", "mmc1_dat3", "mmc2_dat7",	66	"gpmc_ad11", "lcd_data19", "mmc1_dat3", "mmc2_dat7",
67	NULL, NULL, NULL, NULL),	67	NULL, NULL, NULL, NULL),
68	_AM33XX_MUXENTRY(GPMC_AD12, 0,	68	_AM33XX_MUXENTRY(GPMC_AD12, 0,
69	"gpmc_ad12", "lcd_data20", "mmc1_dat4", "mmc2_dat0",	69	"gpmc_ad12", "lcd_data20", "mmc1_dat4", "mmc2_dat0",
70	NULL, NULL, NULL, NULL),	70	NULL, NULL, NULL, NULL),
71	_AM33XX_MUXENTRY(GPMC_AD13, 0,	71	_AM33XX_MUXENTRY(GPMC_AD13, 0,
72	"gpmc_ad13", "lcd_data21", "mmc1_dat5", "mmc2_dat1",	72	"gpmc_ad13", "lcd_data21", "mmc1_dat5", "mmc2_dat1",
73	NULL, NULL, NULL, NULL),	73	NULL, NULL, NULL, NULL),
74	_AM33XX_MUXENTRY(GPMC_AD14, 0,	74	_AM33XX_MUXENTRY(GPMC_AD14, 0,
75	"gpmc_ad14", "lcd_data22", "mmc1_dat6", "mmc2_dat2",	75	"gpmc_ad14", "lcd_data22", "mmc1_dat6", "mmc2_dat2",
76	NULL, NULL, NULL, NULL),	76	NULL, NULL, NULL, NULL),
77	_AM33XX_MUXENTRY(GPMC_AD15, 0,	77	_AM33XX_MUXENTRY(GPMC_AD15, 0,
78	"gpmc_ad15", "lcd_data23", "mmc1_dat7", "mmc2_dat3",	78	"gpmc_ad15", "lcd_data23", "mmc1_dat7", "mmc2_dat3",
79	NULL, NULL, NULL, NULL),	79	NULL, NULL, NULL, NULL),
80	_AM33XX_MUXENTRY(GPMC_A0, 0,	80	_AM33XX_MUXENTRY(GPMC_A0, 0,
81	"gpmc_a0", "mii2_txen", "rgmii2_tctl", "rmii2_txen",	81	"gpmc_a0", "mii2_txen", "rgmii2_tctl", "rmii2_txen",
82	NULL, NULL, NULL, "gpio1_16"),	82	NULL, NULL, NULL, "gpio1_16"),
83	_AM33XX_MUXENTRY(GPMC_A1, 0,	83	_AM33XX_MUXENTRY(GPMC_A1, 0,
84	"gpmc_a1", "mii2_rxdv", "rgmii2_rctl", "mmc2_dat0",	84	"gpmc_a1", "mii2_rxdv", "rgmii2_rctl", "mmc2_dat0",
85	NULL, NULL, NULL, NULL),	85	NULL, NULL, NULL, NULL),
86	_AM33XX_MUXENTRY(GPMC_A2, 0,	86	_AM33XX_MUXENTRY(GPMC_A2, 0,
87	"gpmc_a2", "mii2_txd3", "rgmii2_td3", "mmc2_dat1",	87	"gpmc_a2", "mii2_txd3", "rgmii2_td3", "mmc2_dat1",
88	NULL, NULL, NULL, NULL),	88	NULL, NULL, NULL, NULL),
89	_AM33XX_MUXENTRY(GPMC_A3, 0,	89	_AM33XX_MUXENTRY(GPMC_A3, 0,
90	"gpmc_a3", "mii2_txd2", "rgmii2_td2", "mmc2_dat2",	90	"gpmc_a3", "mii2_txd2", "rgmii2_td2", "mmc2_dat2",
91	NULL, NULL, NULL, NULL),	91	NULL, NULL, NULL, NULL),
92	_AM33XX_MUXENTRY(GPMC_A4, 0,	92	_AM33XX_MUXENTRY(GPMC_A4, 0,
93	"gpmc_a4", "mii2_txd1", "rgmii2_td1", "rmii2_txd1",	93	"gpmc_a4", "mii2_txd1", "rgmii2_td1", "rmii2_txd1",
94	"gpmc_a20", NULL, NULL, NULL),	94	"gpmc_a20", NULL, NULL, NULL),
95	_AM33XX_MUXENTRY(GPMC_A5, 0,	95	_AM33XX_MUXENTRY(GPMC_A5, 0,
96	"gpmc_a5", "mii2_txd0", "rgmii2_td0", "rmii2_txd0",	96	"gpmc_a5", "mii2_txd0", "rgmii2_td0", "rmii2_txd0",
97	"gpmc_a21", NULL, NULL, "gpio1_21"),	97	"gpmc_a21", NULL, NULL, "gpio1_21"),
98	_AM33XX_MUXENTRY(GPMC_A6, 0,	98	_AM33XX_MUXENTRY(GPMC_A6, 0,
99	"gpmc_a6", "mii2_txclk", "rgmii2_tclk", "mmc2_dat4",	99	"gpmc_a6", "mii2_txclk", "rgmii2_tclk", "mmc2_dat4",
100	"gpmc_a22", NULL, NULL, "gpio1_22"),	100	"gpmc_a22", NULL, NULL, "gpio1_22"),
101	_AM33XX_MUXENTRY(GPMC_A7, 0,	101	_AM33XX_MUXENTRY(GPMC_A7, 0,
102	"gpmc_a7", "mii2_rxclk", "rgmii2_rclk", "mmc2_dat5",	102	"gpmc_a7", "mii2_rxclk", "rgmii2_rclk", "mmc2_dat5",
103	NULL, NULL, NULL, NULL),	103	NULL, NULL, NULL, NULL),
104	_AM33XX_MUXENTRY(GPMC_A8, 0,	104	_AM33XX_MUXENTRY(GPMC_A8, 0,
105	"gpmc_a8", "mii2_rxd3", "rgmii2_rd3", "mmc2_dat6",	105	"gpmc_a8", "mii2_rxd3", "rgmii2_rd3", "mmc2_dat6",
106	NULL, NULL, "mcasp0_aclkx", "gpio1_24"),	106	NULL, NULL, "mcasp0_aclkx", "gpio1_24"),
107	_AM33XX_MUXENTRY(GPMC_A9, 0,	107	_AM33XX_MUXENTRY(GPMC_A9, 0,
108	"gpmc_a9", "mii2_rxd2", "rgmii2_rd2", "mmc2_dat7",	108	"gpmc_a9", "mii2_rxd2", "rgmii2_rd2", "mmc2_dat7",
109	NULL, NULL, "mcasp0_fsx", "gpio1_25"),	109	NULL, NULL, "mcasp0_fsx", "gpio1_25"),
110	_AM33XX_MUXENTRY(GPMC_A10, 0,	110	_AM33XX_MUXENTRY(GPMC_A10, 0,
111	"gpmc_a10", "mii2_rxd1", "rgmii2_rd1", "rmii2_rxd1",	111	"gpmc_a10", "mii2_rxd1", "rgmii2_rd1", "rmii2_rxd1",
112	NULL, NULL, "mcasp0_axr0", "gpio1_26"),	112	NULL, NULL, "mcasp0_axr0", "gpio1_26"),
113	_AM33XX_MUXENTRY(GPMC_A11, 0,	113	_AM33XX_MUXENTRY(GPMC_A11, 0,
114	"gpmc_a11", "mii2_rxd0", "rgmii2_rd0", "rmii2_rxd0",	114	"gpmc_a11", "mii2_rxd0", "rgmii2_rd0", "rmii2_rxd0",
115	NULL, NULL, "mcasp0_axr1", "gpio1_27"),	115	NULL, NULL, "mcasp0_axr1", "gpio1_27"),
116	_AM33XX_MUXENTRY(GPMC_WAIT0, 0,	116	_AM33XX_MUXENTRY(GPMC_WAIT0, 0,
117	"gpmc_wait0", "mii2_crs", NULL, "rmii2_crs_dv",	117	"gpmc_wait0", "mii2_crs", NULL, "rmii2_crs_dv",
118	"mmc1_sdcd", NULL, NULL, NULL),	118	"mmc1_sdcd", NULL, NULL, NULL),
119	_AM33XX_MUXENTRY(GPMC_WPN, 0,	119	_AM33XX_MUXENTRY(GPMC_WPN, 0,
120	"gpmc_wpn", "mii2_rxerr", NULL, "rmii2_rxerr",	120	"gpmc_wpn", "mii2_rxerr", NULL, "rmii2_rxerr",
121	"mmc2_sdcd", NULL, NULL, NULL),	121	"mmc2_sdcd", NULL, NULL, NULL),
122	_AM33XX_MUXENTRY(GPMC_BEN1, 0,	122	_AM33XX_MUXENTRY(GPMC_BEN1, 0,
123	"gpmc_ben1", "mii2_col", NULL, "mmc2_dat3",	123	"gpmc_ben1", "mii2_col", NULL, "mmc2_dat3",
124	NULL, NULL, "mcasp0_aclkr", NULL),	124	NULL, NULL, "mcasp0_aclkr", NULL),
125	_AM33XX_MUXENTRY(GPMC_CSN0, 0,	125	_AM33XX_MUXENTRY(GPMC_CSN0, 0,
126	"gpmc_csn0", NULL, NULL, NULL,	126	"gpmc_csn0", NULL, NULL, NULL,
127	NULL, NULL, NULL, "mmc1_sdwp"),	127	NULL, NULL, NULL, "mmc1_sdwp"),
128	_AM33XX_MUXENTRY(GPMC_CSN1, 0,	128	_AM33XX_MUXENTRY(GPMC_CSN1, 0,
129	"gpmc_csn1", NULL, "mmc1_clk", NULL,	129	"gpmc_csn1", NULL, "mmc1_clk", NULL,
130	NULL, NULL, NULL, "gpio1_30"),	130	NULL, NULL, NULL, "gpio1_30"),
131	_AM33XX_MUXENTRY(GPMC_CSN2, 0,	131	_AM33XX_MUXENTRY(GPMC_CSN2, 0,
132	"gpmc_csn2", NULL, "mmc1_cmd", NULL,	132	"gpmc_csn2", NULL, "mmc1_cmd", NULL,
133	NULL, NULL, NULL, "gpio1_31"),	133	NULL, NULL, NULL, "gpio1_31"),
134	_AM33XX_MUXENTRY(GPMC_CSN3, 0,	134	_AM33XX_MUXENTRY(GPMC_CSN3, 0,
135	"gpmc_csn3", NULL, NULL, "mmc2_cmd",	135	"gpmc_csn3", NULL, NULL, "mmc2_cmd",
136	NULL, NULL, NULL, NULL),	136	NULL, NULL, NULL, NULL),
137	_AM33XX_MUXENTRY(GPMC_CLK, 0,	137	_AM33XX_MUXENTRY(GPMC_CLK, 0,
138	"gpmc_clk", NULL, NULL, "mmc2_clk",	138	"gpmc_clk", NULL, NULL, "mmc2_clk",
139	NULL, NULL, "mcasp0_fsr", NULL),	139	NULL, NULL, "mcasp0_fsr", NULL),
140	_AM33XX_MUXENTRY(GPMC_ADVN_ALE, 0,	140	_AM33XX_MUXENTRY(GPMC_ADVN_ALE, 0,
141	"gpmc_advn_ale", NULL, NULL, NULL,	141	"gpmc_advn_ale", NULL, NULL, NULL,
142	NULL, NULL, NULL, "mmc1_sdcd"),	142	NULL, NULL, NULL, "mmc1_sdcd"),
143	_AM33XX_MUXENTRY(GPMC_OEN_REN, 0,	143	_AM33XX_MUXENTRY(GPMC_OEN_REN, 0,
144	"gpmc_oen_ren", NULL, NULL, NULL,	144	"gpmc_oen_ren", NULL, NULL, NULL,
145	NULL, NULL, NULL, NULL),	145	NULL, NULL, NULL, NULL),
146	_AM33XX_MUXENTRY(GPMC_WEN, 0,	146	_AM33XX_MUXENTRY(GPMC_WEN, 0,
147	"gpmc_wen", NULL, NULL, NULL,	147	"gpmc_wen", NULL, NULL, NULL,
148	NULL, NULL, NULL, NULL),	148	NULL, NULL, NULL, NULL),
149	_AM33XX_MUXENTRY(GPMC_BEN0_CLE, 0,	149	_AM33XX_MUXENTRY(GPMC_BEN0_CLE, 0,
150	"gpmc_ben0_cle", NULL, NULL, NULL,	150	"gpmc_ben0_cle", NULL, NULL, NULL,
151	NULL, NULL, NULL, NULL),	151	NULL, NULL, NULL, NULL),
152	_AM33XX_MUXENTRY(LCD_DATA0, 0,	152	_AM33XX_MUXENTRY(LCD_DATA0, 0,
153	"lcd_data0", "gpmc_a0", NULL, NULL,	153	"lcd_data0", "gpmc_a0", NULL, NULL,
154	NULL, NULL, NULL, NULL),	154	NULL, NULL, NULL, NULL),
155	_AM33XX_MUXENTRY(LCD_DATA1, 0,	155	_AM33XX_MUXENTRY(LCD_DATA1, 0,
156	"lcd_data1", "gpmc_a1", NULL, NULL,	156	"lcd_data1", "gpmc_a1", NULL, NULL,
157	NULL, NULL, NULL, NULL),	157	NULL, NULL, NULL, NULL),
158	_AM33XX_MUXENTRY(LCD_DATA2, 0,	158	_AM33XX_MUXENTRY(LCD_DATA2, 0,
159	"lcd_data2", "gpmc_a2", NULL, NULL,	159	"lcd_data2", "gpmc_a2", NULL, NULL,
160	NULL, NULL, NULL, NULL),	160	NULL, NULL, NULL, NULL),
161	_AM33XX_MUXENTRY(LCD_DATA3, 0,	161	_AM33XX_MUXENTRY(LCD_DATA3, 0,
162	"lcd_data3", "gpmc_a3", NULL, NULL,	162	"lcd_data3", "gpmc_a3", NULL, NULL,
163	NULL, NULL, NULL, NULL),	163	NULL, NULL, NULL, NULL),
164	_AM33XX_MUXENTRY(LCD_DATA4, 0,	164	_AM33XX_MUXENTRY(LCD_DATA4, 0,
165	"lcd_data4", "gpmc_a4", NULL, NULL,	165	"lcd_data4", "gpmc_a4", NULL, NULL,
166	NULL, NULL, NULL, NULL),	166	NULL, NULL, NULL, NULL),
167	_AM33XX_MUXENTRY(LCD_DATA5, 0,	167	_AM33XX_MUXENTRY(LCD_DATA5, 0,
168	"lcd_data5", "gpmc_a5", NULL, NULL,	168	"lcd_data5", "gpmc_a5", NULL, NULL,
169	NULL, NULL, NULL, NULL),	169	NULL, NULL, NULL, NULL),
170	_AM33XX_MUXENTRY(LCD_DATA6, 0,	170	_AM33XX_MUXENTRY(LCD_DATA6, 0,
171	"lcd_data6", "gpmc_a6", NULL, NULL,	171	"lcd_data6", "gpmc_a6", NULL, NULL,
172	NULL, NULL, NULL, NULL),	172	NULL, NULL, NULL, NULL),
173	_AM33XX_MUXENTRY(LCD_DATA7, 0,	173	_AM33XX_MUXENTRY(LCD_DATA7, 0,
174	"lcd_data7", "gpmc_a7", NULL, NULL,	174	"lcd_data7", "gpmc_a7", NULL, NULL,
175	NULL, NULL, NULL, NULL),	175	NULL, NULL, NULL, NULL),
176	_AM33XX_MUXENTRY(LCD_DATA8, 0,	176	_AM33XX_MUXENTRY(LCD_DATA8, 0,
177	"lcd_data8", "gpmc_a12", NULL, "mcasp0_aclkx",	177	"lcd_data8", "gpmc_a12", NULL, "mcasp0_aclkx",
178	NULL, NULL, NULL, NULL),	178	NULL, NULL, "uart2_ctsn", NULL),
179	_AM33XX_MUXENTRY(LCD_DATA9, 0,	179	_AM33XX_MUXENTRY(LCD_DATA9, 0,
180	"lcd_data9", "gpmc_a13", NULL, "mcasp0_fsx",	180	"lcd_data9", "gpmc_a13", NULL, "mcasp0_fsx",
181	NULL, NULL, NULL, NULL),	181	NULL, NULL, "uart2_rtsn", NULL),
182	_AM33XX_MUXENTRY(LCD_DATA10, 0,	182	_AM33XX_MUXENTRY(LCD_DATA10, 0,
183	"lcd_data10", "gpmc_a14", NULL, "mcasp0_axr0",	183	"lcd_data10", "gpmc_a14", NULL, "mcasp0_axr0",
184	NULL, NULL, NULL, NULL),	184	NULL, NULL, NULL, NULL),
185	_AM33XX_MUXENTRY(LCD_DATA11, 0,	185	_AM33XX_MUXENTRY(LCD_DATA11, 0,
186	"lcd_data11", "gpmc_a15", NULL, "mcasp0_ahclkr",	186	"lcd_data11", "gpmc_a15", NULL, "mcasp0_ahclkr",
187	"mcasp0_axr2", NULL, NULL, NULL),	187	"mcasp0_axr2", NULL, NULL, NULL),
188	_AM33XX_MUXENTRY(LCD_DATA12, 0,	188	_AM33XX_MUXENTRY(LCD_DATA12, 0,
189	"lcd_data12", "gpmc_a16", NULL, "mcasp0_aclkr",	189	"lcd_data12", "gpmc_a16", NULL, "mcasp0_aclkr",
190	"mcasp0_axr2", NULL, NULL, NULL),	190	"mcasp0_axr2", NULL, NULL, NULL),
191	_AM33XX_MUXENTRY(LCD_DATA13, 0,	191	_AM33XX_MUXENTRY(LCD_DATA13, 0,
192	"lcd_data13", "gpmc_a17", NULL, "mcasp0_fsr",	192	"lcd_data13", "gpmc_a17", NULL, "mcasp0_fsr",
193	"mcasp0_axr3", NULL, NULL, NULL),	193	"mcasp0_axr3", NULL, NULL, NULL),
194	_AM33XX_MUXENTRY(LCD_DATA14, 0,	194	_AM33XX_MUXENTRY(LCD_DATA14, 0,
195	"lcd_data14", "gpmc_a18", NULL, "mcasp0_axr1",	195	"lcd_data14", "gpmc_a18", NULL, "mcasp0_axr1",
196	NULL, NULL, NULL, NULL),	196	NULL, NULL, NULL, NULL),
197	_AM33XX_MUXENTRY(LCD_DATA15, 0,	197	_AM33XX_MUXENTRY(LCD_DATA15, 0,
198	"lcd_data15", "gpmc_a19", NULL, "mcasp0_ahclkx",	198	"lcd_data15", "gpmc_a19", NULL, "mcasp0_ahclkx",
199	"mcasp0_axr3", NULL, NULL, NULL),	199	"mcasp0_axr3", NULL, NULL, NULL),
200	_AM33XX_MUXENTRY(LCD_VSYNC, 0,	200	_AM33XX_MUXENTRY(LCD_VSYNC, 0,
201	"lcd_vsync", NULL, NULL, NULL,	201	"lcd_vsync", NULL, NULL, NULL,
202	NULL, NULL, NULL, NULL),	202	NULL, NULL, NULL, NULL),
203	_AM33XX_MUXENTRY(LCD_HSYNC, 0,	203	_AM33XX_MUXENTRY(LCD_HSYNC, 0,
204	"lcd_hsync", NULL, NULL, NULL,	204	"lcd_hsync", NULL, NULL, NULL,
205	NULL, NULL, NULL, NULL),	205	NULL, NULL, NULL, NULL),
206	_AM33XX_MUXENTRY(LCD_PCLK, 0,	206	_AM33XX_MUXENTRY(LCD_PCLK, 0,
207	"lcd_pclk", NULL, NULL, NULL,	207	"lcd_pclk", NULL, NULL, NULL,
208	NULL, NULL, NULL, NULL),	208	NULL, NULL, NULL, NULL),
209	_AM33XX_MUXENTRY(LCD_AC_BIAS_EN, 0,	209	_AM33XX_MUXENTRY(LCD_AC_BIAS_EN, 0,
210	"lcd_ac_bias_en", NULL, NULL, NULL,	210	"lcd_ac_bias_en", NULL, NULL, NULL,
211	NULL, NULL, NULL, "gpio2_25"),	211	NULL, NULL, NULL, "gpio2_25"),
212	_AM33XX_MUXENTRY(GPMC_CLK, 0,	212	_AM33XX_MUXENTRY(GPMC_CLK, 0,
213	"gpmc_clk", "lcd_memory_clk_mux", NULL, NULL,	213	"gpmc_clk", "lcd_memory_clk_mux", NULL, NULL,
214	NULL, NULL, NULL, NULL),	214	NULL, NULL, NULL, NULL),
215	_AM33XX_MUXENTRY(MMC0_DAT3, 0,	215	_AM33XX_MUXENTRY(MMC0_DAT3, 0,
216	"mmc0_dat3", NULL, NULL, NULL,	216	"mmc0_dat3", NULL, NULL, NULL,
217	NULL, NULL, NULL, NULL),	217	NULL, NULL, NULL, NULL),
218	_AM33XX_MUXENTRY(MMC0_DAT2, 0,	218	_AM33XX_MUXENTRY(MMC0_DAT2, 0,
219	"mmc0_dat2", NULL, NULL, NULL,	219	"mmc0_dat2", NULL, NULL, NULL,
220	NULL, NULL, NULL, NULL),	220	NULL, NULL, NULL, NULL),
221	_AM33XX_MUXENTRY(MMC0_DAT1, 0,	221	_AM33XX_MUXENTRY(MMC0_DAT1, 0,
222	"mmc0_dat1", NULL, NULL, NULL,	222	"mmc0_dat1", NULL, NULL, NULL,
223	NULL, NULL, NULL, NULL),	223	NULL, NULL, NULL, NULL),
224	_AM33XX_MUXENTRY(MMC0_DAT0, 0,	224	_AM33XX_MUXENTRY(MMC0_DAT0, 0,
225	"mmc0_dat0", NULL, NULL, NULL,	225	"mmc0_dat0", NULL, NULL, NULL,
226	NULL, NULL, NULL, NULL),	226	NULL, NULL, NULL, NULL),
227	_AM33XX_MUXENTRY(MMC0_CLK, 0,	227	_AM33XX_MUXENTRY(MMC0_CLK, 0,
228	"mmc0_clk", NULL, NULL, NULL,	228	"mmc0_clk", NULL, NULL, NULL,
229	NULL, NULL, NULL, NULL),	229	NULL, NULL, NULL, NULL),
230	_AM33XX_MUXENTRY(MMC0_CMD, 0,	230	_AM33XX_MUXENTRY(MMC0_CMD, 0,
231	"mmc0_cmd", NULL, NULL, NULL,	231	"mmc0_cmd", NULL, NULL, NULL,
232	NULL, NULL, NULL, NULL),	232	NULL, NULL, NULL, NULL),
233	_AM33XX_MUXENTRY(MII1_COL, 0,	233	_AM33XX_MUXENTRY(MII1_COL, 0,
234	"mii1_col", "rmii2_refclk", "spi1_sclk", NULL,	234	"mii1_col", "rmii2_refclk", "spi1_sclk", NULL,
235	"mcasp1_axr2", "mmc2_dat3", "mcasp0_axr2", NULL),	235	"mcasp1_axr2", "mmc2_dat3", "mcasp0_axr2", NULL),
236	_AM33XX_MUXENTRY(MII1_CRS, 0,	236	_AM33XX_MUXENTRY(MII1_CRS, 0,
237	"mii1_crs", "rmii1_crs_dv", "spi1_d0", NULL,	237	"mii1_crs", "rmii1_crs_dv", "spi1_d0", NULL,
238	"mcasp1_aclkx", NULL, NULL, NULL),	238	"mcasp1_aclkx", NULL, NULL, NULL),
239	_AM33XX_MUXENTRY(MII1_RXERR, 0,	239	_AM33XX_MUXENTRY(MII1_RXERR, 0,
240	"mii1_rxerr", "rmii1_rxerr", "spi1_d1", NULL,	240	"mii1_rxerr", "rmii1_rxerr", "spi1_d1", NULL,
241	"mcasp1_fsx", NULL, NULL, NULL),	241	"mcasp1_fsx", NULL, NULL, NULL),
242	_AM33XX_MUXENTRY(MII1_TXEN, 0,	242	_AM33XX_MUXENTRY(MII1_TXEN, 0,
243	"mii1_txen", "rmii1_txen", "rgmii1_tctl", NULL,	243	"mii1_txen", "rmii1_txen", "rgmii1_tctl", NULL,
244	"mcasp1_axr0", NULL, "mmc2_cmd", NULL),	244	"mcasp1_axr0", NULL, "mmc2_cmd", NULL),
245	_AM33XX_MUXENTRY(MII1_RXDV, 0,	245	_AM33XX_MUXENTRY(MII1_RXDV, 0,
246	"mii1_rxdv", NULL, "rgmii1_rctl", NULL,	246	"mii1_rxdv", NULL, "rgmii1_rctl", NULL,
247	"mcasp1_aclx", "mmc2_dat0", "mcasp0_aclkr", NULL),	247	"mcasp1_aclx", "mmc2_dat0", "mcasp0_aclkr", NULL),
248	_AM33XX_MUXENTRY(MII1_TXD3, 0,	248	_AM33XX_MUXENTRY(MII1_TXD3, 0,
249	"mii1_txd3", NULL, "rgmii1_td3", NULL,	249	"mii1_txd3", NULL, "rgmii1_td3", NULL,
250	"mcasp1_fsx", "mmc2_dat1", "mcasp0_fsr", NULL),	250	"mcasp1_fsx", "mmc2_dat1", "mcasp0_fsr", NULL),
251	_AM33XX_MUXENTRY(MII1_TXD2, 0,	251	_AM33XX_MUXENTRY(MII1_TXD2, 0,
252	"mii1_txd2", NULL, "rgmii1_td2", NULL,	252	"mii1_txd2", NULL, "rgmii1_td2", NULL,
253	"mcasp1_axr0", "mmc2_dat2", "mcasp0_ahclkx", NULL),	253	"mcasp1_axr0", "mmc2_dat2", "mcasp0_ahclkx", NULL),
254	_AM33XX_MUXENTRY(MII1_TXD1, 0,	254	_AM33XX_MUXENTRY(MII1_TXD1, 0,
255	"mii1_txd1", "rmii1_txd1", "rgmii1_td1", "mcasp1_fsr",	255	"mii1_txd1", "rmii1_txd1", "rgmii1_td1", "mcasp1_fsr",
256	"mcasp1_axr1", NULL, "mmc1_cmd", NULL),	256	"mcasp1_axr1", NULL, "mmc1_cmd", NULL),
257	_AM33XX_MUXENTRY(MII1_TXD0, 0,	257	_AM33XX_MUXENTRY(MII1_TXD0, 0,
258	"mii1_txd0", "rmii1_txd0", "rgmii1_td0", "mcasp1_axr2",	258	"mii1_txd0", "rmii1_txd0", "rgmii1_td0", "mcasp1_axr2",
259	"mcasp1_aclkr", NULL, "mmc1_clk", NULL),	259	"mcasp1_aclkr", NULL, "mmc1_clk", NULL),
260	_AM33XX_MUXENTRY(MII1_TXCLK, 0,	260	_AM33XX_MUXENTRY(MII1_TXCLK, 0,
261	"mii1_txclk", NULL, "rgmii1_tclk", "mmc0_dat7",	261	"mii1_txclk", NULL, "rgmii1_tclk", "mmc0_dat7",
262	"mmc1_dat0", NULL, "mcasp0_aclkx", NULL),	262	"mmc1_dat0", NULL, "mcasp0_aclkx", NULL),
263	_AM33XX_MUXENTRY(MII1_RXCLK, 0,	263	_AM33XX_MUXENTRY(MII1_RXCLK, 0,
264	"mii1_rxclk", NULL, "rgmii1_rclk", "mmc0_dat6",	264	"mii1_rxclk", NULL, "rgmii1_rclk", "mmc0_dat6",
265	"mmc1_dat1", NULL, "mcasp0_fsx", NULL),	265	"mmc1_dat1", NULL, "mcasp0_fsx", NULL),
266	_AM33XX_MUXENTRY(MII1_RXD3, 0,	266	_AM33XX_MUXENTRY(MII1_RXD3, 0,
267	"mii1_rxd3", NULL, "rgmii1_rd3", "mmc0_dat5",	267	"mii1_rxd3", NULL, "rgmii1_rd3", "mmc0_dat5",
268	"mmc1_dat2", NULL, "mcasp0_axr0", NULL),	268	"mmc1_dat2", NULL, "mcasp0_axr0", NULL),
269	_AM33XX_MUXENTRY(MII1_RXD2, 0,	269	_AM33XX_MUXENTRY(MII1_RXD2, 0,
270	"mii1_rxd2", NULL, "rgmii1_rd2", "mmc0_dat4",	270	"mii1_rxd2", NULL, "rgmii1_rd2", "mmc0_dat4",
271	"mmc1_dat3", NULL, "mcasp0_axr1", NULL),	271	"mmc1_dat3", NULL, "mcasp0_axr1", NULL),
272	_AM33XX_MUXENTRY(MII1_RXD1, 0,	272	_AM33XX_MUXENTRY(MII1_RXD1, 0,
273	"mii1_rxd1", "rmii1_rxd1", "rgmii1_rd1", "mcasp1_axr3",	273	"mii1_rxd1", "rmii1_rxd1", "rgmii1_rd1", "mcasp1_axr3",
274	"mcasp1_fsr", NULL, "mmc2_clk", NULL),	274	"mcasp1_fsr", NULL, "mmc2_clk", NULL),
275	_AM33XX_MUXENTRY(MII1_RXD0, 0,	275	_AM33XX_MUXENTRY(MII1_RXD0, 0,
276	"mii1_rxd0", "rmii1_rxd0", "rgmii1_rd0", "mcasp1_ahclkx",	276	"mii1_rxd0", "rmii1_rxd0", "rgmii1_rd0", "mcasp1_ahclkx",
277	"mcasp1_ahclkr", "mcasp1_aclkr", "mcasp0_axr3", NULL),	277	"mcasp1_ahclkr", "mcasp1_aclkr", "mcasp0_axr3", NULL),
278	_AM33XX_MUXENTRY(MII1_REFCLK, 0,	278	_AM33XX_MUXENTRY(MII1_REFCLK, 0,
279	"rmii1_refclk", NULL, "spi1_cs0", NULL,	279	"rmii1_refclk", NULL, "spi1_cs0", NULL,
280	"mcasp1_axr3", "mmc0_pow", "mcasp1_ahclkx", NULL),	280	"mcasp1_axr3", "mmc0_pow", "mcasp1_ahclkx", NULL),
281	_AM33XX_MUXENTRY(MDIO_DATA, 0,	281	_AM33XX_MUXENTRY(MDIO_DATA, 0,
282	"mdio_data", NULL, NULL, NULL,	282	"mdio_data", NULL, NULL, NULL,
283	"mmc0_sdcd", "mmc1_cmd", "mmc2_cmd", NULL),	283	"mmc0_sdcd", "mmc1_cmd", "mmc2_cmd", NULL),
284	_AM33XX_MUXENTRY(MDIO_CLK, 0,	284	_AM33XX_MUXENTRY(MDIO_CLK, 0,
285	"mdio_clk", NULL, NULL, NULL,	285	"mdio_clk", NULL, NULL, NULL,
286	"mmc0_sdwp", "mmc1_clk", "mmc2_clk", NULL),	286	"mmc0_sdwp", "mmc1_clk", "mmc2_clk", NULL),
287	_AM33XX_MUXENTRY(SPI0_SCLK, 0,	287	_AM33XX_MUXENTRY(SPI0_SCLK, 0,
288	"spi0_sclk", NULL, NULL, NULL,	288	"spi0_sclk", "uart2_rxd", NULL, NULL,
289	NULL, NULL, NULL, "gpio0_2"),	289	NULL, NULL, NULL, "gpio0_2"),
290	_AM33XX_MUXENTRY(SPI0_D0, 0,	290	_AM33XX_MUXENTRY(SPI0_D0, 0,
291	"spi0_d0", NULL, NULL, NULL,	291	"spi0_d0", "uart2_txd", NULL, NULL,
292	NULL, NULL, NULL, "gpio0_3"),	292	NULL, NULL, NULL, "gpio0_3"),
293	_AM33XX_MUXENTRY(SPI0_D1, 0,	293	_AM33XX_MUXENTRY(SPI0_D1, 0,
294	"spi0_d1", "mmc1_sdwp", "i2c1_sda", NULL,	294	"spi0_d1", "mmc1_sdwp", "i2c1_sda", NULL,
295	NULL, NULL, NULL, NULL),	295	NULL, NULL, NULL, NULL),
296	_AM33XX_MUXENTRY(SPI0_CS0, 0,	296	_AM33XX_MUXENTRY(SPI0_CS0, 0,
297	"spi0_cs0", "mmc2_sdwp", "i2c1_scl", NULL,	297	"spi0_cs0", "mmc2_sdwp", "i2c1_scl", NULL,
298	NULL, NULL, NULL, NULL),	298	NULL, NULL, NULL, NULL),
299	_AM33XX_MUXENTRY(SPI0_CS1, 0,	299	_AM33XX_MUXENTRY(SPI0_CS1, 0,
300	"spi0_cs1", "uart3_rxd", NULL, "mmc0_pow",	300	"spi0_cs1", "uart3_rxd", NULL, "mmc0_pow",
301	NULL, "mmc0_sdcd", NULL, NULL),	301	NULL, "mmc0_sdcd", NULL, NULL),
302	_AM33XX_MUXENTRY(ECAP0_IN_PWM0_OUT, 0,	302	_AM33XX_MUXENTRY(ECAP0_IN_PWM0_OUT, 0,
303	"ecap0_in_pwm0_out", "uart3_txd", "spi1_cs1", NULL,	303	"ecap0_in_pwm0_out", "uart3_txd", "spi1_cs1", NULL,
304	"spi1_sclk", "mmc0_sdwp", NULL, "gpio0_7"),	304	"spi1_sclk", "mmc0_sdwp", NULL, "gpio0_7"),
305	_AM33XX_MUXENTRY(UART0_CTSN, 0,	305	_AM33XX_MUXENTRY(UART0_CTSN, 0,
306	"uart0_ctsn", NULL, "d_can1_tx", NULL,	306	"uart0_ctsn", NULL, "d_can1_tx", NULL,
307	"spi1_d0", NULL, NULL, NULL),	307	"spi1_d0", NULL, NULL, NULL),
308	_AM33XX_MUXENTRY(UART0_RTSN, 0,	308	_AM33XX_MUXENTRY(UART0_RTSN, 0,
309	"uart0_rtsn", NULL, "d_can1_rx", NULL,	309	"uart0_rtsn", NULL, "d_can1_rx", NULL,
310	"spi1_d1", "spi1_cs0", NULL, NULL),	310	"spi1_d1", "spi1_cs0", NULL, NULL),
311	_AM33XX_MUXENTRY(UART0_RXD, 0,	311	_AM33XX_MUXENTRY(UART0_RXD, 0,
312	"uart0_rxd", "spi1_cs0", "d_can0_tx", NULL,	312	"uart0_rxd", "spi1_cs0", "d_can0_tx", NULL,
313	NULL, NULL, NULL, NULL),	313	NULL, NULL, NULL, NULL),
314	_AM33XX_MUXENTRY(UART0_TXD, 0,	314	_AM33XX_MUXENTRY(UART0_TXD, 0,
315	"uart0_txd", "spi1_cs1", "d_can0_rx", NULL,	315	"uart0_txd", "spi1_cs1", "d_can0_rx", NULL,
316	NULL, NULL, NULL, NULL),	316	NULL, NULL, NULL, NULL),
317	_AM33XX_MUXENTRY(UART1_CTSN, 0,	317	_AM33XX_MUXENTRY(UART1_CTSN, 0,
318	"uart1_ctsn", NULL, NULL, NULL,	318	"uart1_ctsn", NULL, NULL, NULL,
319	"spi1_cs0", NULL, NULL, NULL),	319	"spi1_cs0", NULL, NULL, NULL),
320	_AM33XX_MUXENTRY(UART1_RTSN, 0,	320	_AM33XX_MUXENTRY(UART1_RTSN, 0,
321	"uart1_rtsn", NULL, NULL, NULL,	321	"uart1_rtsn", NULL, NULL, NULL,
322	"spi1_cs1", NULL, NULL, NULL),	322	"spi1_cs1", NULL, NULL, NULL),
323	_AM33XX_MUXENTRY(UART1_RXD, 0,	323	_AM33XX_MUXENTRY(UART1_RXD, 0,
324	"uart1_rxd", "mmc1_sdwp", NULL, NULL,	324	"uart1_rxd", "mmc1_sdwp", NULL, NULL,
325	NULL, "pr1_uart0_rxd_mux1", NULL, NULL),	325	NULL, "pr1_uart0_rxd_mux1", NULL, NULL),
326	_AM33XX_MUXENTRY(UART1_TXD, 0,	326	_AM33XX_MUXENTRY(UART1_TXD, 0,
327	"uart1_txd", "mmc2_sdwp", NULL, NULL,	327	"uart1_txd", "mmc2_sdwp", NULL, NULL,
328	NULL, "pr1_uart0_txd_mux1", NULL, NULL),	328	NULL, "pr1_uart0_txd_mux1", NULL, NULL),
329	_AM33XX_MUXENTRY(I2C0_SDA, 0,	329	_AM33XX_MUXENTRY(I2C0_SDA, 0,
330	"i2c0_sda", NULL, NULL, NULL,	330	"i2c0_sda", NULL, NULL, NULL,
331	NULL, NULL, NULL, NULL),	331	NULL, NULL, NULL, NULL),
332	_AM33XX_MUXENTRY(I2C0_SCL, 0,	332	_AM33XX_MUXENTRY(I2C0_SCL, 0,
333	"i2c0_scl", NULL, NULL, NULL,	333	"i2c0_scl", NULL, NULL, NULL,
334	NULL, NULL, NULL, NULL),	334	NULL, NULL, NULL, NULL),
335	_AM33XX_MUXENTRY(MCASP0_ACLKX, 0,	335	_AM33XX_MUXENTRY(MCASP0_ACLKX, 0,
336	"mcasp0_aclkx", NULL, NULL, "spi1_sclk",	336	"mcasp0_aclkx", NULL, NULL, "spi1_sclk",
337	"mmc0_sdcd", NULL, NULL, NULL),	337	"mmc0_sdcd", NULL, NULL, NULL),
338	_AM33XX_MUXENTRY(MCASP0_FSX, 0,	338	_AM33XX_MUXENTRY(MCASP0_FSX, 0,
339	"mcasp0_fsx", NULL, NULL, "spi1_d0",	339	"mcasp0_fsx", NULL, NULL, "spi1_d0",
340	"mmc1_sdcd", NULL, NULL, NULL),	340	"mmc1_sdcd", NULL, NULL, NULL),
341	_AM33XX_MUXENTRY(MCASP0_AXR0, 0,	341	_AM33XX_MUXENTRY(MCASP0_AXR0, 0,
342	"mcasp0_axr0", NULL, NULL, "spi1_d1",	342	"mcasp0_axr0", NULL, NULL, "spi1_d1",
343	"mmc2_sdcd", NULL, NULL, NULL),	343	"mmc2_sdcd", NULL, NULL, NULL),
344	_AM33XX_MUXENTRY(MCASP0_AHCLKR, 0,	344	_AM33XX_MUXENTRY(MCASP0_AHCLKR, 0,
345	"mcasp0_ahclkr", NULL, "mcasp0_axr2", "spi1_cs0",	345	"mcasp0_ahclkr", NULL, "mcasp0_axr2", "spi1_cs0",
346	NULL, NULL, NULL, "gpio3_17"),	346	NULL, NULL, NULL, "gpio3_17"),
347	_AM33XX_MUXENTRY(MCASP0_ACLKR, 0,	347	_AM33XX_MUXENTRY(MCASP0_ACLKR, 0,
348	"mcasp0_aclkr", NULL, "mcasp0_axr2", "mcasp1_aclkx",	348	"mcasp0_aclkr", NULL, "mcasp0_axr2", "mcasp1_aclkx",
349	"mmc0_sdwp", NULL, NULL, NULL),	349	"mmc0_sdwp", NULL, NULL, NULL),
350	_AM33XX_MUXENTRY(MCASP0_FSR, 0,	350	_AM33XX_MUXENTRY(MCASP0_FSR, 0,
351	"mcasp0_fsr", NULL, "mcasp0_axr3", "mcasp1_fsx",	351	"mcasp0_fsr", NULL, "mcasp0_axr3", "mcasp1_fsx",
352	NULL, "pr1_pru0_pru_r30_5", NULL, NULL),	352	NULL, "pr1_pru0_pru_r30_5", NULL, NULL),
353	_AM33XX_MUXENTRY(MCASP0_AXR1, 0,	353	_AM33XX_MUXENTRY(MCASP0_AXR1, 0,
354	"mcasp0_axr1", NULL, NULL, "mcasp1_axr0",	354	"mcasp0_axr1", NULL, NULL, "mcasp1_axr0",
355	NULL, NULL, NULL, NULL),	355	NULL, NULL, NULL, NULL),
356	_AM33XX_MUXENTRY(MCASP0_AHCLKX, 0,	356	_AM33XX_MUXENTRY(MCASP0_AHCLKX, 0,
357	"mcasp0_ahclkx", "mcasp0_axr3", NULL, "mcasp1_axr1",	357	"mcasp0_ahclkx", "mcasp0_axr3", NULL, "mcasp1_axr1",
358	NULL, NULL, NULL, "gpio3_21"),	358	NULL, NULL, NULL, "gpio3_21"),
359	_AM33XX_MUXENTRY(XDMA_EVENT_INTR0, 0,	359	_AM33XX_MUXENTRY(XDMA_EVENT_INTR0, 0,
360	"xdma_event_intr0", NULL, NULL, NULL,	360	"xdma_event_intr0", NULL, NULL, NULL,
361	"spi1_cs1", NULL, NULL, NULL),	361	"spi1_cs1", NULL, NULL, NULL),
362	_AM33XX_MUXENTRY(XDMA_EVENT_INTR1, 0,	362	_AM33XX_MUXENTRY(XDMA_EVENT_INTR1, 0,
363	"xdma_event_intr1", NULL, NULL, "clkout2",	363	"xdma_event_intr1", NULL, NULL, "clkout2",
364	NULL, NULL, NULL, NULL),	364	NULL, NULL, NULL, NULL),
365	_AM33XX_MUXENTRY(WARMRSTN, 0,	365	_AM33XX_MUXENTRY(WARMRSTN, 0,
366	NULL, NULL, NULL, NULL,	366	NULL, NULL, NULL, NULL,
367	NULL, NULL, NULL, NULL),	367	NULL, NULL, NULL, NULL),
368	_AM33XX_MUXENTRY(PWRONRSTN, 0,	368	_AM33XX_MUXENTRY(PWRONRSTN, 0,
369	NULL, NULL, NULL, NULL,	369	NULL, NULL, NULL, NULL,
370	NULL, NULL, NULL, NULL),	370	NULL, NULL, NULL, NULL),
371	_AM33XX_MUXENTRY(NMIN, 0,	371	_AM33XX_MUXENTRY(NMIN, 0,
372	NULL, NULL, NULL, NULL,	372	NULL, NULL, NULL, NULL,
373	NULL, NULL, NULL, NULL),	373	NULL, NULL, NULL, NULL),
374	_AM33XX_MUXENTRY(XTALIN, 0,	374	_AM33XX_MUXENTRY(XTALIN, 0,
375	NULL, NULL, NULL, NULL,	375	NULL, NULL, NULL, NULL,
376	NULL, NULL, NULL, NULL),	376	NULL, NULL, NULL, NULL),
377	_AM33XX_MUXENTRY(XTALOUT, 0,	377	_AM33XX_MUXENTRY(XTALOUT, 0,
378	NULL, NULL, NULL, NULL,	378	NULL, NULL, NULL, NULL,
379	NULL, NULL, NULL, NULL),	379	NULL, NULL, NULL, NULL),
380	_AM33XX_MUXENTRY(TMS, 0,	380	_AM33XX_MUXENTRY(TMS, 0,
381	NULL, NULL, NULL, NULL,	381	NULL, NULL, NULL, NULL,
382	NULL, NULL, NULL, NULL),	382	NULL, NULL, NULL, NULL),
383	_AM33XX_MUXENTRY(TDI, 0,	383	_AM33XX_MUXENTRY(TDI, 0,
384	NULL, NULL, NULL, NULL,	384	NULL, NULL, NULL, NULL,
385	NULL, NULL, NULL, NULL),	385	NULL, NULL, NULL, NULL),
386	_AM33XX_MUXENTRY(TDO, 0,	386	_AM33XX_MUXENTRY(TDO, 0,
387	NULL, NULL, NULL, NULL,	387	NULL, NULL, NULL, NULL,
388	NULL, NULL, NULL, NULL),	388	NULL, NULL, NULL, NULL),
389	_AM33XX_MUXENTRY(TCK, 0,	389	_AM33XX_MUXENTRY(TCK, 0,
390	NULL, NULL, NULL, NULL,	390	NULL, NULL, NULL, NULL,
391	NULL, NULL, NULL, NULL),	391	NULL, NULL, NULL, NULL),
392	_AM33XX_MUXENTRY(TRSTN, 0,	392	_AM33XX_MUXENTRY(TRSTN, 0,
393	NULL, NULL, NULL, NULL,	393	NULL, NULL, NULL, NULL,
394	NULL, NULL, NULL, NULL),	394	NULL, NULL, NULL, NULL),
395	_AM33XX_MUXENTRY(EMU0, 0,	395	_AM33XX_MUXENTRY(EMU0, 0,
396	NULL, NULL, NULL, NULL,	396	NULL, NULL, NULL, NULL,
397	NULL, NULL, NULL, NULL),	397	NULL, NULL, NULL, NULL),
398	_AM33XX_MUXENTRY(EMU1, 0,	398	_AM33XX_MUXENTRY(EMU1, 0,
399	NULL, NULL, NULL, NULL,	399	NULL, NULL, NULL, NULL,
400	NULL, NULL, NULL, NULL),	400	NULL, NULL, NULL, NULL),
401	_AM33XX_MUXENTRY(RTC_XTALIN, 0,	401	_AM33XX_MUXENTRY(RTC_XTALIN, 0,
402	NULL, NULL, NULL, NULL,	402	NULL, NULL, NULL, NULL,
403	NULL, NULL, NULL, NULL),	403	NULL, NULL, NULL, NULL),
404	_AM33XX_MUXENTRY(RTC_XTALOUT, 0,	404	_AM33XX_MUXENTRY(RTC_XTALOUT, 0,
405	NULL, NULL, NULL, NULL,	405	NULL, NULL, NULL, NULL,
406	NULL, NULL, NULL, NULL),	406	NULL, NULL, NULL, NULL),
407	_AM33XX_MUXENTRY(RTC_PWRONRSTN, 0,	407	_AM33XX_MUXENTRY(RTC_PWRONRSTN, 0,
408	NULL, NULL, NULL, NULL,	408	NULL, NULL, NULL, NULL,
409	NULL, NULL, NULL, NULL),	409	NULL, NULL, NULL, NULL),
410	_AM33XX_MUXENTRY(PMIC_POWER_EN, 0,	410	_AM33XX_MUXENTRY(PMIC_POWER_EN, 0,
411	NULL, NULL, NULL, NULL,	411	NULL, NULL, NULL, NULL,
412	NULL, NULL, NULL, NULL),	412	NULL, NULL, NULL, NULL),
413	_AM33XX_MUXENTRY(EXT_WAKEUP, 0,	413	_AM33XX_MUXENTRY(EXT_WAKEUP, 0,
414	NULL, NULL, NULL, NULL,	414	NULL, NULL, NULL, NULL,
415	NULL, NULL, NULL, NULL),	415	NULL, NULL, NULL, NULL),
416	_AM33XX_MUXENTRY(USB0_DRVVBUS, 0,	416	_AM33XX_MUXENTRY(USB0_DRVVBUS, 0,
417	"usb0_drvvbus", NULL, NULL, NULL,	417	"usb0_drvvbus", NULL, NULL, NULL,
418	NULL, NULL, NULL, NULL),	418	NULL, NULL, NULL, NULL),
419	_AM33XX_MUXENTRY(USB1_DRVVBUS, 0,	419	_AM33XX_MUXENTRY(USB1_DRVVBUS, 0,
420	"usb1_drvvbus", NULL, NULL, NULL,	420	"usb1_drvvbus", NULL, NULL, NULL,
421	NULL, NULL, NULL, NULL),	421	NULL, NULL, NULL, NULL),
422	_AM33XX_MUXENTRY(DDR_RESETN, 0,	422	_AM33XX_MUXENTRY(DDR_RESETN, 0,
423	NULL, NULL, NULL, NULL,	423	NULL, NULL, NULL, NULL,
424	NULL, NULL, NULL, NULL),	424	NULL, NULL, NULL, NULL),
425	_AM33XX_MUXENTRY(DDR_CSN0, 0,	425	_AM33XX_MUXENTRY(DDR_CSN0, 0,
426	NULL, NULL, NULL, NULL,	426	NULL, NULL, NULL, NULL,
427	NULL, NULL, NULL, NULL),	427	NULL, NULL, NULL, NULL),
428	_AM33XX_MUXENTRY(DDR_CKE, 0,	428	_AM33XX_MUXENTRY(DDR_CKE, 0,
429	NULL, NULL, NULL, NULL,	429	NULL, NULL, NULL, NULL,
430	NULL, NULL, NULL, NULL),	430	NULL, NULL, NULL, NULL),
431	_AM33XX_MUXENTRY(DDR_CK, 0,	431	_AM33XX_MUXENTRY(DDR_CK, 0,
432	NULL, NULL, NULL, NULL,	432	NULL, NULL, NULL, NULL,
433	NULL, NULL, NULL, NULL),	433	NULL, NULL, NULL, NULL),
434	_AM33XX_MUXENTRY(DDR_CKN, 0,	434	_AM33XX_MUXENTRY(DDR_CKN, 0,
435	NULL, NULL, NULL, NULL,	435	NULL, NULL, NULL, NULL,
436	NULL, NULL, NULL, NULL),	436	NULL, NULL, NULL, NULL),
437	_AM33XX_MUXENTRY(DDR_CASN, 0,	437	_AM33XX_MUXENTRY(DDR_CASN, 0,
438	NULL, NULL, NULL, NULL,	438	NULL, NULL, NULL, NULL,
439	NULL, NULL, NULL, NULL),	439	NULL, NULL, NULL, NULL),
440	_AM33XX_MUXENTRY(DDR_RASN, 0,	440	_AM33XX_MUXENTRY(DDR_RASN, 0,
441	NULL, NULL, NULL, NULL,	441	NULL, NULL, NULL, NULL,
442	NULL, NULL, NULL, NULL),	442	NULL, NULL, NULL, NULL),
443	_AM33XX_MUXENTRY(DDR_WEN, 0,	443	_AM33XX_MUXENTRY(DDR_WEN, 0,
444	NULL, NULL, NULL, NULL,	444	NULL, NULL, NULL, NULL,
445	NULL, NULL, NULL, NULL),	445	NULL, NULL, NULL, NULL),
446	_AM33XX_MUXENTRY(DDR_BA0, 0,	446	_AM33XX_MUXENTRY(DDR_BA0, 0,
447	NULL, NULL, NULL, NULL,	447	NULL, NULL, NULL, NULL,
448	NULL, NULL, NULL, NULL),	448	NULL, NULL, NULL, NULL),
449	_AM33XX_MUXENTRY(DDR_BA1, 0,	449	_AM33XX_MUXENTRY(DDR_BA1, 0,
450	NULL, NULL, NULL, NULL,	450	NULL, NULL, NULL, NULL,
451	NULL, NULL, NULL, NULL),	451	NULL, NULL, NULL, NULL),
452	_AM33XX_MUXENTRY(DDR_BA2, 0,	452	_AM33XX_MUXENTRY(DDR_BA2, 0,
453	NULL, NULL, NULL, NULL,	453	NULL, NULL, NULL, NULL,
454	NULL, NULL, NULL, NULL),	454	NULL, NULL, NULL, NULL),
455	_AM33XX_MUXENTRY(DDR_A0, 0,	455	_AM33XX_MUXENTRY(DDR_A0, 0,
456	NULL, NULL, NULL, NULL,	456	NULL, NULL, NULL, NULL,
457	NULL, NULL, NULL, NULL),	457	NULL, NULL, NULL, NULL),
458	_AM33XX_MUXENTRY(DDR_A1, 0,	458	_AM33XX_MUXENTRY(DDR_A1, 0,
459	NULL, NULL, NULL, NULL,	459	NULL, NULL, NULL, NULL,
460	NULL, NULL, NULL, NULL),	460	NULL, NULL, NULL, NULL),
461	_AM33XX_MUXENTRY(DDR_A2, 0,	461	_AM33XX_MUXENTRY(DDR_A2, 0,
462	NULL, NULL, NULL, NULL,	462	NULL, NULL, NULL, NULL,
463	NULL, NULL, NULL, NULL),	463	NULL, NULL, NULL, NULL),
464	_AM33XX_MUXENTRY(DDR_A3, 0,	464	_AM33XX_MUXENTRY(DDR_A3, 0,
465	NULL, NULL, NULL, NULL,	465	NULL, NULL, NULL, NULL,
466	NULL, NULL, NULL, NULL),	466	NULL, NULL, NULL, NULL),
467	_AM33XX_MUXENTRY(DDR_A4, 0,	467	_AM33XX_MUXENTRY(DDR_A4, 0,
468	NULL, NULL, NULL, NULL,	468	NULL, NULL, NULL, NULL,
469	NULL, NULL, NULL, NULL),	469	NULL, NULL, NULL, NULL),
470	_AM33XX_MUXENTRY(DDR_A5, 0,	470	_AM33XX_MUXENTRY(DDR_A5, 0,
471	NULL, NULL, NULL, NULL,	471	NULL, NULL, NULL, NULL,
472	NULL, NULL, NULL, NULL),	472	NULL, NULL, NULL, NULL),
473	_AM33XX_MUXENTRY(DDR_A6, 0,	473	_AM33XX_MUXENTRY(DDR_A6, 0,
474	NULL, NULL, NULL, NULL,	474	NULL, NULL, NULL, NULL,
475	NULL, NULL, NULL, NULL),	475	NULL, NULL, NULL, NULL),
476	_AM33XX_MUXENTRY(DDR_A7, 0,	476	_AM33XX_MUXENTRY(DDR_A7, 0,
477	NULL, NULL, NULL, NULL,	477	NULL, NULL, NULL, NULL,
478	NULL, NULL, NULL, NULL),	478	NULL, NULL, NULL, NULL),
479	_AM33XX_MUXENTRY(DDR_A8, 0,	479	_AM33XX_MUXENTRY(DDR_A8, 0,
480	NULL, NULL, NULL, NULL,	480	NULL, NULL, NULL, NULL,
481	NULL, NULL, NULL, NULL),	481	NULL, NULL, NULL, NULL),
482	_AM33XX_MUXENTRY(DDR_A9, 0,	482	_AM33XX_MUXENTRY(DDR_A9, 0,
483	NULL, NULL, NULL, NULL,	483	NULL, NULL, NULL, NULL,
484	NULL, NULL, NULL, NULL),	484	NULL, NULL, NULL, NULL),
485	_AM33XX_MUXENTRY(DDR_A10, 0,	485	_AM33XX_MUXENTRY(DDR_A10, 0,
486	NULL, NULL, NULL, NULL,	486	NULL, NULL, NULL, NULL,
487	NULL, NULL, NULL, NULL),	487	NULL, NULL, NULL, NULL),
488	_AM33XX_MUXENTRY(DDR_A11, 0,	488	_AM33XX_MUXENTRY(DDR_A11, 0,
489	NULL, NULL, NULL, NULL,	489	NULL, NULL, NULL, NULL,
490	NULL, NULL, NULL, NULL),	490	NULL, NULL, NULL, NULL),
491	_AM33XX_MUXENTRY(DDR_A12, 0,	491	_AM33XX_MUXENTRY(DDR_A12, 0,
492	NULL, NULL, NULL, NULL,	492	NULL, NULL, NULL, NULL,
493	NULL, NULL, NULL, NULL),	493	NULL, NULL, NULL, NULL),
494	_AM33XX_MUXENTRY(DDR_A13, 0,	494	_AM33XX_MUXENTRY(DDR_A13, 0,
495	NULL, NULL, NULL, NULL,	495	NULL, NULL, NULL, NULL,
496	NULL, NULL, NULL, NULL),	496	NULL, NULL, NULL, NULL),
497	_AM33XX_MUXENTRY(DDR_A14, 0,	497	_AM33XX_MUXENTRY(DDR_A14, 0,
498	NULL, NULL, NULL, NULL,	498	NULL, NULL, NULL, NULL,
499	NULL, NULL, NULL, NULL),	499	NULL, NULL, NULL, NULL),
500	_AM33XX_MUXENTRY(DDR_A15, 0,	500	_AM33XX_MUXENTRY(DDR_A15, 0,
501	NULL, NULL, NULL, NULL,	501	NULL, NULL, NULL, NULL,
502	NULL, NULL, NULL, NULL),	502	NULL, NULL, NULL, NULL),
503	_AM33XX_MUXENTRY(DDR_ODT, 0,	503	_AM33XX_MUXENTRY(DDR_ODT, 0,
504	NULL, NULL, NULL, NULL,	504	NULL, NULL, NULL, NULL,
505	NULL, NULL, NULL, NULL),	505	NULL, NULL, NULL, NULL),
506	_AM33XX_MUXENTRY(DDR_D0, 0,	506	_AM33XX_MUXENTRY(DDR_D0, 0,
507	NULL, NULL, NULL, NULL,	507	NULL, NULL, NULL, NULL,
508	NULL, NULL, NULL, NULL),	508	NULL, NULL, NULL, NULL),
509	_AM33XX_MUXENTRY(DDR_D1, 0,	509	_AM33XX_MUXENTRY(DDR_D1, 0,
510	NULL, NULL, NULL, NULL,	510	NULL, NULL, NULL, NULL,
511	NULL, NULL, NULL, NULL),	511	NULL, NULL, NULL, NULL),
512	_AM33XX_MUXENTRY(DDR_D2, 0,	512	_AM33XX_MUXENTRY(DDR_D2, 0,
513	NULL, NULL, NULL, NULL,	513	NULL, NULL, NULL, NULL,
514	NULL, NULL, NULL, NULL),	514	NULL, NULL, NULL, NULL),
515	_AM33XX_MUXENTRY(DDR_D3, 0,	515	_AM33XX_MUXENTRY(DDR_D3, 0,
516	NULL, NULL, NULL, NULL,	516	NULL, NULL, NULL, NULL,
517	NULL, NULL, NULL, NULL),	517	NULL, NULL, NULL, NULL),
518	_AM33XX_MUXENTRY(DDR_D4, 0,	518	_AM33XX_MUXENTRY(DDR_D4, 0,
519	NULL, NULL, NULL, NULL,	519	NULL, NULL, NULL, NULL,
520	NULL, NULL, NULL, NULL),	520	NULL, NULL, NULL, NULL),
521	_AM33XX_MUXENTRY(DDR_D5, 0,	521	_AM33XX_MUXENTRY(DDR_D5, 0,
522	NULL, NULL, NULL, NULL,	522	NULL, NULL, NULL, NULL,
523	NULL, NULL, NULL, NULL),	523	NULL, NULL, NULL, NULL),
524	_AM33XX_MUXENTRY(DDR_D6, 0,	524	_AM33XX_MUXENTRY(DDR_D6, 0,
525	NULL, NULL, NULL, NULL,	525	NULL, NULL, NULL, NULL,
526	NULL, NULL, NULL, NULL),	526	NULL, NULL, NULL, NULL),
527	_AM33XX_MUXENTRY(DDR_D7, 0,	527	_AM33XX_MUXENTRY(DDR_D7, 0,
528	NULL, NULL, NULL, NULL,	528	NULL, NULL, NULL, NULL,
529	NULL, NULL, NULL, NULL),	529	NULL, NULL, NULL, NULL),
530	_AM33XX_MUXENTRY(DDR_D8, 0,	530	_AM33XX_MUXENTRY(DDR_D8, 0,
531	NULL, NULL, NULL, NULL,	531	NULL, NULL, NULL, NULL,
532	NULL, NULL, NULL, NULL),	532	NULL, NULL, NULL, NULL),
533	_AM33XX_MUXENTRY(DDR_D9, 0,	533	_AM33XX_MUXENTRY(DDR_D9, 0,
534	NULL, NULL, NULL, NULL,	534	NULL, NULL, NULL, NULL,
535	NULL, NULL, NULL, NULL),	535	NULL, NULL, NULL, NULL),
536	_AM33XX_MUXENTRY(DDR_D10, 0,	536	_AM33XX_MUXENTRY(DDR_D10, 0,
537	NULL, NULL, NULL, NULL,	537	NULL, NULL, NULL, NULL,
538	NULL, NULL, NULL, NULL),	538	NULL, NULL, NULL, NULL),
539	_AM33XX_MUXENTRY(DDR_D11, 0,	539	_AM33XX_MUXENTRY(DDR_D11, 0,
540	NULL, NULL, NULL, NULL,	540	NULL, NULL, NULL, NULL,
541	NULL, NULL, NULL, NULL),	541	NULL, NULL, NULL, NULL),
542	_AM33XX_MUXENTRY(DDR_D12, 0,	542	_AM33XX_MUXENTRY(DDR_D12, 0,
543	NULL, NULL, NULL, NULL,	543	NULL, NULL, NULL, NULL,
544	NULL, NULL, NULL, NULL),	544	NULL, NULL, NULL, NULL),
545	_AM33XX_MUXENTRY(DDR_D13, 0,	545	_AM33XX_MUXENTRY(DDR_D13, 0,
546	NULL, NULL, NULL, NULL,	546	NULL, NULL, NULL, NULL,
547	NULL, NULL, NULL, NULL),	547	NULL, NULL, NULL, NULL),
548	_AM33XX_MUXENTRY(DDR_D14, 0,	548	_AM33XX_MUXENTRY(DDR_D14, 0,
549	NULL, NULL, NULL, NULL,	549	NULL, NULL, NULL, NULL,
550	NULL, NULL, NULL, NULL),	550	NULL, NULL, NULL, NULL),
551	_AM33XX_MUXENTRY(DDR_D15, 0,	551	_AM33XX_MUXENTRY(DDR_D15, 0,
552	NULL, NULL, NULL, NULL,	552	NULL, NULL, NULL, NULL,
553	NULL, NULL, NULL, NULL),	553	NULL, NULL, NULL, NULL),
554	_AM33XX_MUXENTRY(DDR_DQM0, 0,	554	_AM33XX_MUXENTRY(DDR_DQM0, 0,
555	NULL, NULL, NULL, NULL,	555	NULL, NULL, NULL, NULL,
556	NULL, NULL, NULL, NULL),	556	NULL, NULL, NULL, NULL),
557	_AM33XX_MUXENTRY(DDR_DQM1, 0,	557	_AM33XX_MUXENTRY(DDR_DQM1, 0,
558	NULL, NULL, NULL, NULL,	558	NULL, NULL, NULL, NULL,
559	NULL, NULL, NULL, NULL),	559	NULL, NULL, NULL, NULL),
560	_AM33XX_MUXENTRY(DDR_DQS0, 0,	560	_AM33XX_MUXENTRY(DDR_DQS0, 0,
561	NULL, NULL, NULL, NULL,	561	NULL, NULL, NULL, NULL,
562	NULL, NULL, NULL, NULL),	562	NULL, NULL, NULL, NULL),
563	_AM33XX_MUXENTRY(DDR_DQSN0, 0,	563	_AM33XX_MUXENTRY(DDR_DQSN0, 0,
564	NULL, NULL, NULL, NULL,	564	NULL, NULL, NULL, NULL,
565	NULL, NULL, NULL, NULL),	565	NULL, NULL, NULL, NULL),
566	_AM33XX_MUXENTRY(DDR_DQS1, 0,	566	_AM33XX_MUXENTRY(DDR_DQS1, 0,
567	NULL, NULL, NULL, NULL,	567	NULL, NULL, NULL, NULL,
568	NULL, NULL, NULL, NULL),	568	NULL, NULL, NULL, NULL),
569	_AM33XX_MUXENTRY(DDR_DQSN1, 0,	569	_AM33XX_MUXENTRY(DDR_DQSN1, 0,
570	NULL, NULL, NULL, NULL,	570	NULL, NULL, NULL, NULL,
571	NULL, NULL, NULL, NULL),	571	NULL, NULL, NULL, NULL),
572	_AM33XX_MUXENTRY(DDR_VREF, 0,	572	_AM33XX_MUXENTRY(DDR_VREF, 0,
573	NULL, NULL, NULL, NULL,	573	NULL, NULL, NULL, NULL,
574	NULL, NULL, NULL, NULL),	574	NULL, NULL, NULL, NULL),
575	_AM33XX_MUXENTRY(DDR_VTP, 0,	575	_AM33XX_MUXENTRY(DDR_VTP, 0,
576	NULL, NULL, NULL, NULL,	576	NULL, NULL, NULL, NULL,
577	NULL, NULL, NULL, NULL),	577	NULL, NULL, NULL, NULL),
578	_AM33XX_MUXENTRY(AIN0, 0,	578	_AM33XX_MUXENTRY(AIN0, 0,
579	"ain0", NULL, NULL, NULL,	579	"ain0", NULL, NULL, NULL,
580	NULL, NULL, NULL, NULL),	580	NULL, NULL, NULL, NULL),
581	_AM33XX_MUXENTRY(AIN1, 0,	581	_AM33XX_MUXENTRY(AIN1, 0,
582	"ain1", NULL, NULL, NULL,	582	"ain1", NULL, NULL, NULL,
583	NULL, NULL, NULL, NULL),	583	NULL, NULL, NULL, NULL),
584	_AM33XX_MUXENTRY(AIN2, 0,	584	_AM33XX_MUXENTRY(AIN2, 0,
585	"ain2", NULL, NULL, NULL,	585	"ain2", NULL, NULL, NULL,
586	NULL, NULL, NULL, NULL),	586	NULL, NULL, NULL, NULL),
587	_AM33XX_MUXENTRY(AIN3, 0,	587	_AM33XX_MUXENTRY(AIN3, 0,
588	"ain3", NULL, NULL, NULL,	588	"ain3", NULL, NULL, NULL,
589	NULL, NULL, NULL, NULL),	589	NULL, NULL, NULL, NULL),
590	_AM33XX_MUXENTRY(VREFP, 0,	590	_AM33XX_MUXENTRY(VREFP, 0,
591	"vrefp", NULL, NULL, NULL,	591	"vrefp", NULL, NULL, NULL,
592	NULL, NULL, NULL, NULL),	592	NULL, NULL, NULL, NULL),
593	_AM33XX_MUXENTRY(VREFN, 0,	593	_AM33XX_MUXENTRY(VREFN, 0,
594	"vrefn", NULL, NULL, NULL,	594	"vrefn", NULL, NULL, NULL,
595	NULL, NULL, NULL, NULL),	595	NULL, NULL, NULL, NULL),
596	{ .reg_offset = OMAP_MUX_TERMINATOR },	596	{ .reg_offset = OMAP_MUX_TERMINATOR },
597	};	597	};
598		598
599	int __init am33xx_mux_init(struct omap_board_mux *board_subset)	599	int __init am33xx_mux_init(struct omap_board_mux *board_subset)
600	{	600	{
601	return omap_mux_init("core", 0, AM33XX_CONTROL_PADCONF_MUX_PBASE,	601	return omap_mux_init("core", 0, AM33XX_CONTROL_PADCONF_MUX_PBASE,
602	AM33XX_CONTROL_PADCONF_MUX_SIZE, am33xx_muxmodes,	602	AM33XX_CONTROL_PADCONF_MUX_SIZE, am33xx_muxmodes,
603	NULL, board_subset, NULL);	603	NULL, board_subset, NULL);
604	}	604	}
605	#else	605	#else
606	int __init am33xx_mux_init(struct omap_board_mux *board_subset)	606	int __init am33xx_mux_init(struct omap_board_mux *board_subset)
607	{	607	{
608	return 0;	608	return 0;
609	}	609	}
610	#endif	610	#endif
611		611

arch/arm/mach-omap2/omap_hwmod_33xx_data.c

Diff comments View file @ 94082f3

 /*
  * Hardware modules present on the AM33XX chips
  *
  * Copyright (C) {2011} Texas Instruments Incorporated - http://www.ti.com/
  *
  * This file is automatically generated from the AM33XX hardware databases.
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation version 2.
  *
  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  * kind, whether express or implied; without even the implied warranty
  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  * GNU General Public License for more details.
  */
 #include <linux/io.h>
 #include <plat/omap_hwmod.h>
 #include <plat/cpu.h>
 #include <plat/gpio.h>
 #include <plat/dma.h>
 #include <plat/mmc.h>
 #include <plat/mcspi.h>
 #include "omap_hwmod_common_data.h"
 #include "control.h"
 #include "cm33xx.h"
 /* Backward references (IPs with Bus Master capability) */
 static struct omap_hwmod am33xx_mpu_hwmod;
 static struct omap_hwmod am33xx_l3slow_hwmod;
 static struct omap_hwmod am33xx_l4wkup_hwmod;
 static struct omap_hwmod am33xx_l4per_hwmod;
 static struct omap_hwmod am33xx_uart1_hwmod;
 static struct omap_hwmod am33xx_uart2_hwmod;
 static struct omap_hwmod am33xx_uart3_hwmod;
 static struct omap_hwmod am33xx_uart4_hwmod;
 static struct omap_hwmod am33xx_uart5_hwmod;
 static struct omap_hwmod am33xx_uart6_hwmod;
 static struct omap_hwmod am33xx_timer0_hwmod;
 static struct omap_hwmod am33xx_timer1_hwmod;
 static struct omap_hwmod am33xx_timer2_hwmod;
 static struct omap_hwmod am33xx_timer3_hwmod;
 static struct omap_hwmod am33xx_timer4_hwmod;
 static struct omap_hwmod am33xx_timer5_hwmod;
 static struct omap_hwmod am33xx_timer6_hwmod;
 static struct omap_hwmod am33xx_timer7_hwmod;
 static struct omap_hwmod am33xx_wd_timer1_hwmod;
 static struct omap_hwmod am33xx_cpgmac0_hwmod;
 static struct omap_hwmod am33xx_icss_hwmod;
 static struct omap_hwmod am33xx_ieee5000_hwmod;
 static struct omap_hwmod am33xx_tptc0_hwmod;
 static struct omap_hwmod am33xx_tptc1_hwmod;
 static struct omap_hwmod am33xx_tptc2_hwmod;
 static struct omap_hwmod am33xx_gpio0_hwmod;
 static struct omap_hwmod am33xx_gpio1_hwmod;
 static struct omap_hwmod am33xx_gpio2_hwmod;
 static struct omap_hwmod am33xx_gpio3_hwmod;
 static struct omap_hwmod am33xx_i2c1_hwmod;
 static struct omap_hwmod am33xx_i2c2_hwmod;
 static struct omap_hwmod am33xx_usbss_hwmod;
 static struct omap_hwmod am33xx_mmc0_hwmod;
 static struct omap_hwmod am33xx_mmc1_hwmod;
 static struct omap_hwmod am33xx_mmc2_hwmod;
 static struct omap_hwmod am33xx_spi0_hwmod;
 static struct omap_hwmod am33xx_spi1_hwmod;
 static struct omap_hwmod am33xx_elm_hwmod;
 /*
  * Interconnects hwmod structures
  * hwmods that compose the global AM33XX OCP interconnect
  */
 /* MPU -> L3_SLOW Peripheral interface */
 static struct omap_hwmod_ocp_if am33xx_mpu__l3_slow = {
 	.master 	= &am33xx_mpu_hwmod,
 	.slave		= &am33xx_l3slow_hwmod,
 	.user		= OCP_USER_MPU,
 };
 /* L3 SLOW -> L4_PER Peripheral interface */
 static struct omap_hwmod_ocp_if am33xx_l3_slow__l4_per = {
 	.master 	= &am33xx_l3slow_hwmod,
 	.slave		= &am33xx_l4per_hwmod,
 	.user		= OCP_USER_MPU,
 };
 /* L3 SLOW -> L4_WKUP Peripheral interface */
 static struct omap_hwmod_ocp_if am33xx_l3_slow__l4_wkup = {
 	.master 	= &am33xx_l3slow_hwmod,
 	.slave		= &am33xx_l4wkup_hwmod,
 	.user		= OCP_USER_MPU,
 };
 /* Master interfaces on the L4_WKUP interconnect */
 static struct omap_hwmod_ocp_if *am33xx_l3_slow_masters[] = {
 	&am33xx_l3_slow__l4_per,
 	&am33xx_l3_slow__l4_wkup,
 };
 /* Slave interfaces on the L3_SLOW interconnect */
 static struct omap_hwmod_ocp_if *am33xx_l3_slow_slaves[] = {
 	&am33xx_mpu__l3_slow,
 };
 static struct omap_hwmod am33xx_l3slow_hwmod = {
 	.name		= "l3_slow",
 	.class		= &l3_hwmod_class,
 	.clkdm_name	= "l3s_clkdm",
 	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
 	.masters	= am33xx_l3_slow_masters,
 	.masters_cnt	= ARRAY_SIZE(am33xx_l3_slow_masters),
 	.slaves		= am33xx_l3_slow_slaves,
 	.slaves_cnt	= ARRAY_SIZE(am33xx_l3_slow_slaves),
 };
 /* L4 PER -> GPIO2 */
 static struct omap_hwmod_addr_space am33xx_gpio1_addrs[] = {
 	{
 		.pa_start	= AM33XX_GPIO1_BASE,
 		.pa_end		= AM33XX_GPIO1_BASE + SZ_4K - 1,
 		.flags		= ADDR_TYPE_RT
 	},
 	{ }
 };
 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = {
 	.master		= &am33xx_l4per_hwmod,
 	.slave		= &am33xx_gpio1_hwmod,
 	.clk		= "l4ls_gclk",
 	.addr		= am33xx_gpio1_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 /* L4 PER -> GPIO3 */
 static struct omap_hwmod_addr_space am33xx_gpio2_addrs[] = {
 	{
 		.pa_start	= AM33XX_GPIO2_BASE,
 		.pa_end		= AM33XX_GPIO2_BASE + SZ_4K - 1,
 		.flags		= ADDR_TYPE_RT
 	},
 	{ }
 };
 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = {
 	.master		= &am33xx_l4per_hwmod,
 	.slave		= &am33xx_gpio2_hwmod,
 	.clk		= "l4ls_gclk",
 	.addr		= am33xx_gpio2_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 /* L4 PER -> GPIO4 */
 static struct omap_hwmod_addr_space am33xx_gpio3_addrs[] = {
 	{
 		.pa_start	= AM33XX_GPIO3_BASE,
 		.pa_end		= AM33XX_GPIO3_BASE + SZ_4K - 1,
 		.flags		= ADDR_TYPE_RT
 	},
 	{ }
 };
 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = {
 	.master		= &am33xx_l4per_hwmod,
 	.slave		= &am33xx_gpio3_hwmod,
 	.clk		= "l4ls_gclk",
 	.addr		= am33xx_gpio3_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 /* Master interfaces on the L4_PER interconnect */
 static struct omap_hwmod_ocp_if *am33xx_l4_per_masters[] = {
 	&am33xx_l4_per__gpio1,
 	&am33xx_l4_per__gpio2,
 	&am33xx_l4_per__gpio3,
 };
 /* Slave interfaces on the L4_PER interconnect */
 static struct omap_hwmod_ocp_if *am33xx_l4_per_slaves[] = {
 	&am33xx_l3_slow__l4_per,
 };
 static struct omap_hwmod am33xx_l4per_hwmod = {
 	.name		= "l4_per",
 	.class		= &l4_hwmod_class,
 	.clkdm_name	= "l4ls_clkdm",
 	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
 	.masters	= am33xx_l4_per_masters,
 	.masters_cnt	= ARRAY_SIZE(am33xx_l4_per_masters),
 	.slaves		= am33xx_l4_per_slaves,
 	.slaves_cnt	= ARRAY_SIZE(am33xx_l4_per_slaves),
 };
 /* L4 WKUP -> I2C1 */
 static struct omap_hwmod_addr_space am33xx_i2c1_addr_space[] = {
 	{
 		.pa_start	= AM33XX_I2C0_BASE,
 		.pa_end		= AM33XX_I2C0_BASE + SZ_4K - 1,
 		.flags		= ADDR_TYPE_RT
 	},
 	{ }
 };
 static struct omap_hwmod_ocp_if am33xx_l4_wkup_i2c1 = {
 	.master		= &am33xx_l4wkup_hwmod,
 	.slave		= &am33xx_i2c1_hwmod,
 	.addr		= am33xx_i2c1_addr_space,
 	.user		= OCP_USER_MPU,
 };
 /* L4 WKUP -> GPIO1 */
 static struct omap_hwmod_addr_space am33xx_gpio0_addrs[] = {
 	{
 		.pa_start	= AM33XX_GPIO0_BASE,
 		.pa_end		= AM33XX_GPIO0_BASE + SZ_4K - 1,
 		.flags		= ADDR_TYPE_RT
 	},
 	{ }
 };
 static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = {
 	.master		= &am33xx_l4wkup_hwmod,
 	.slave		= &am33xx_gpio0_hwmod,
 	.clk		= "l4ls_gclk",
 	.addr		= am33xx_gpio0_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 /* Master interfaces on the L4_WKUP interconnect */
 static struct omap_hwmod_ocp_if *am33xx_l4_wkup_masters[] = {
 	&am33xx_l4_wkup__gpio0,
 };
 /* Slave interfaces on the L4_WKUP interconnect */
 static struct omap_hwmod_ocp_if *am33xx_l4_wkup_slaves[] = {
 	&am33xx_l3_slow__l4_wkup,
 };
 static struct omap_hwmod am33xx_l4wkup_hwmod = {
 	.name		= "l4_wkup",
 	.class		= &l4_hwmod_class,
 	.clkdm_name	= "l4_wkup_clkdm",
 	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
 	.masters	= am33xx_l4_wkup_masters,
 	.masters_cnt	= ARRAY_SIZE(am33xx_l4_wkup_masters),
 	.slaves		= am33xx_l4_wkup_slaves,
 	.slaves_cnt	= ARRAY_SIZE(am33xx_l4_wkup_slaves),
 };
 /* 'adc_tsc' class */
 static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
 	.name		= "adc_tsc",
 };
 /* adc_tsc */
 static struct omap_hwmod_irq_info am33xx_adc_tsc_irqs[] = {
 	{ .irq = AM33XX_IRQ_TSC },
 	{ .irq = -1 }
 };
 static struct omap_hwmod am33xx_adc_tsc_hwmod = {
 	.name		= "adc_tsc",
 	.class		= &am33xx_adc_tsc_hwmod_class,
 	.mpu_irqs	= am33xx_adc_tsc_irqs,
 	.main_clk	= "adc_tsc_fck",
 	.clkdm_name	= "l4_wkup_clkdm",
 	.prcm		= {
 		.omap4	= {
 			.clkctrl_offs	= AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},
 };
 /* 'aes' class */
 static struct omap_hwmod_class am33xx_aes_hwmod_class = {
 	.name		= "aes",
 };
 /* aes0 */
 static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = {
 	{ .irq = AM33XX_IRQ_AESEIP36t0_S },
 	{ .irq = -1 }
 };
 static struct omap_hwmod am33xx_aes0_hwmod = {
 	.name		= "aes0",
 	.class		= &am33xx_aes_hwmod_class,
 	.mpu_irqs	= am33xx_aes0_irqs,
 	.main_clk	= "aes0_fck",
 	.clkdm_name	= "l3_clkdm",
 	.prcm		= {
 		.omap4	= {
 			.clkctrl_offs	= AM33XX_CM_PER_AES0_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},
 };
 /* 'cefuse' class */
 static struct omap_hwmod_class am33xx_cefuse_hwmod_class = {
 	.name		= "cefuse",
 };
 /* cefuse */
 static struct omap_hwmod am33xx_cefuse_hwmod = {
 	.name		= "cefuse",
 	.class		= &am33xx_cefuse_hwmod_class,
 	.main_clk	= "cefuse_fck",
 	.clkdm_name	= "l4_cefuse_clkdm",
 	.prcm		= {
 		.omap4	= {
 			.clkctrl_offs	= AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},
 };
 /* 'clkdiv32k' class */
 static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = {
 	.name		= "clkdiv32k",
 };
 /* clkdiv32k */
 static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
 	.name		= "clkdiv32k",
 	.class		= &am33xx_clkdiv32k_hwmod_class,
 	.main_clk	= "clkdiv32k_ick",
 	.clkdm_name	= "clk_24mhz_clkdm",
 	.prcm		= {
 		.omap4	= {
 			.clkctrl_offs	= AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},
 	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
 };
 /* 'control' class */
 static struct omap_hwmod_class am33xx_control_hwmod_class = {
 	.name		= "control",
 };
 /* control */
 static struct omap_hwmod_irq_info am33xx_control_irqs[] = {
 	{ .irq = AM33XX_IRQ_CONTROL_PLATFORM },
 	{ .irq = -1 }
 };
 static struct omap_hwmod am33xx_control_hwmod = {
 	.name		= "control",
 	.class		= &am33xx_control_hwmod_class,
 	.mpu_irqs	= am33xx_control_irqs,
 	.main_clk	= "control_fck",
 	.clkdm_name	= "l4_wkup_clkdm",
 	.prcm		= {
 		.omap4	= {
 			.clkctrl_offs	= AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},
 	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
 };
 /* 'cpgmac0' class */
 static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
 	.name		= "cpgmac0",
 };
 /* cpgmac0 */
 static struct omap_hwmod am33xx_cpgmac0_hwmod = {
 	.name		= "cpgmac0",
 	.class		= &am33xx_cpgmac0_hwmod_class,
 	.main_clk	= "cpgmac0_ick",
 	.clkdm_name	= "cpsw_125mhz_clkdm",
 	.prcm		= {
 		.omap4	= {
 			.clkctrl_offs	= AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},
 };
 /* 'dcan' class */
 static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
 	.name		= "dcan",
 };
 /* dcan0 */
 static struct omap_hwmod_irq_info am33xx_dcan0_irqs[] = {
 	{ .irq = AM33XX_IRQ_DCAN0_0 },
 	{ .irq = -1 }
 };
 static struct omap_hwmod am33xx_dcan0_hwmod = {
 	.name		= "dcan0",
 	.class		= &am33xx_dcan_hwmod_class,
 	.mpu_irqs	= am33xx_dcan0_irqs,
 	.main_clk	= "dcan0_fck",
 	.clkdm_name	= "l4ls_clkdm",
 	.prcm		= {
 		.omap4	= {
 			.clkctrl_offs	= AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},
 };
 /* dcan1 */
 static struct omap_hwmod_irq_info am33xx_dcan1_irqs[] = {
 	{ .irq = AM33XX_IRQ_DCAN1_0 },
 	{ .irq = -1 }
 };
 static struct omap_hwmod am33xx_dcan1_hwmod = {
 	.name		= "dcan1",
 	.class		= &am33xx_dcan_hwmod_class,
 	.mpu_irqs	= am33xx_dcan1_irqs,
 	.main_clk	= "dcan1_fck",
 	.clkdm_name	= "l4ls_clkdm",
 	.prcm		= {
 		.omap4	= {
 			.clkctrl_offs	= AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},
 };
 /* 'debugss' class */
 static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
 	.name		= "debugss",
 };
 /* debugss */
 static struct omap_hwmod am33xx_debugss_hwmod = {
 	.name		= "debugss",
 	.class		= &am33xx_debugss_hwmod_class,
 	.main_clk	= "debugss_ick",
 	.clkdm_name	= "l3_aon_clkdm",
 	.prcm		= {
 		.omap4	= {
 			.clkctrl_offs	= AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},
 #ifdef CONFIG_DEBUG_JTAG_ENABLE
 	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
 #endif
 };
 static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
 	.rev_offs	= 0x0000,
 	.sysc_offs	= 0x0010,
 	.syss_offs	= 0x0014,
 	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 				SYSC_HAS_SOFTRESET |
 				SYSS_HAS_RESET_STATUS),
 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 	.sysc_fields	= &omap_hwmod_sysc_type1,
 };
 /* 'elm' class */
 static struct omap_hwmod_class am33xx_elm_hwmod_class = {
 	.name   = "elm",
 	.sysc	= &am33xx_elm_sysc,
 };
 static struct omap_hwmod_irq_info am33xx_elm_irqs[] = {
 	{ .irq = AM33XX_IRQ_ELM },
 	{ .irq = -1 }
 };
 struct omap_hwmod_addr_space am33xx_elm_addr_space[] = {
 	{
 		.pa_start	= AM33XX_ELM_BASE,
 		.pa_end		= AM33XX_ELM_BASE + SZ_8K - 1,
 		.flags		= ADDR_TYPE_RT
 	},
 	{ }
 };
 struct omap_hwmod_ocp_if am33xx_l4_core__elm = {
 	.master		= &am33xx_l4per_hwmod,
 	.slave		= &am33xx_elm_hwmod,
 	.addr		= am33xx_elm_addr_space,
 	.user		= OCP_USER_MPU,
 };
 static struct omap_hwmod_ocp_if *am33xx_elm_slaves[] = {
 	&am33xx_l4_core__elm,
 };
 /* elm */
 static struct omap_hwmod am33xx_elm_hwmod = {
 	.name		= "elm",
 	.class		= &am33xx_elm_hwmod_class,
 	.mpu_irqs       = am33xx_elm_irqs,
 	.main_clk	= "elm_fck",
 	.clkdm_name	= "l4ls_clkdm",
 	.slaves		= am33xx_elm_slaves,
 	.slaves_cnt	= ARRAY_SIZE(am33xx_elm_slaves),
 	.prcm		= {
 		.omap4	= {
 			.clkctrl_offs	= AM33XX_CM_PER_ELM_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},
 };
 /* 'emif_fw' class */
 static struct omap_hwmod_class am33xx_emif_fw_hwmod_class = {
 	.name		= "emif_fw",
 };
 /* emif_fw */
 static struct omap_hwmod am33xx_emif_fw_hwmod = {
 	.name		= "emif_fw",
 	.class		= &am33xx_emif_fw_hwmod_class,
 	.main_clk	= "emif_fw_fck",
 	.clkdm_name	= "l4fw_clkdm",
 	.prcm		= {
 		.omap4	= {
 			.clkctrl_offs	= AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},
 	.flags		= HWMOD_INIT_NO_RESET | HWMOD_INIT_NO_IDLE,
 };
 /* 'epwmss' class */
 static struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
 	.name		= "epwmss",
 };
 /* epwmss0 */
 static struct omap_hwmod am33xx_epwmss0_hwmod = {
 	.name		= "epwmss0",
 	.class		= &am33xx_epwmss_hwmod_class,
 	.main_clk	= "epwmss0_fck",
 	.clkdm_name	= "l4ls_clkdm",
 	.prcm		= {
 		.omap4	= {
 			.clkctrl_offs	= AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},
 };
 /* epwmss1 */
 static struct omap_hwmod am33xx_epwmss1_hwmod = {
 	.name		= "epwmss1",
 	.class		= &am33xx_epwmss_hwmod_class,
 	.main_clk	= "epwmss1_fck",
 	.clkdm_name	= "l4ls_clkdm",
 	.prcm		= {
 		.omap4	= {
 			.clkctrl_offs	= AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},
 };
 /* epwmss2 */
 static struct omap_hwmod am33xx_epwmss2_hwmod = {
 	.name		= "epwmss2",
 	.class		= &am33xx_epwmss_hwmod_class,
 	.main_clk	= "epwmss2_fck",
 	.clkdm_name	= "l4ls_clkdm",
 	.prcm		= {
 		.omap4	= {
 			.clkctrl_offs	= AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},
 };
 static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
 	.rev_offs	= 0x0000,
 	.sysc_offs	= 0x0010,
 	.syss_offs	= 0x0114,
 	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
 			SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 			SYSS_HAS_RESET_STATUS),
 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 			SIDLE_SMART_WKUP),
 	.sysc_fields	= &omap_hwmod_sysc_type1,
 };
 /* 'gpio' class */
 static struct omap_hwmod_class am33xx_gpio_hwmod_class = {
 	.name		= "gpio",
 	.sysc		= &am33xx_gpio_sysc,
 	.rev		= 2,
 };
 /* gpio dev_attr */
 static struct omap_gpio_dev_attr gpio_dev_attr = {
 	.bank_width	= 32,
 	.dbck_flag	= true,
 };
 /* gpio0 */
 static struct omap_hwmod_irq_info am33xx_gpio0_irqs[] = {
 	{ .irq = AM33XX_IRQ_GPIO0_1 },
 	{ .irq = -1 }
 };
 /* gpio0 slave ports */
 static struct omap_hwmod_ocp_if *am33xx_gpio0_slaves[] = {
 	&am33xx_l4_wkup__gpio0,
 };
 static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
 	{ .role = "dbclk", .clk = "gpio0_dbclk" },
 };
 /* gpio0 */
 static struct omap_hwmod am33xx_gpio0_hwmod = {
 	.name		= "gpio1",
 	.class		= &am33xx_gpio_hwmod_class,
 	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 	.mpu_irqs	= am33xx_gpio0_irqs,
 	.main_clk	= "gpio0_ick",
 	.clkdm_name	= "l4_wkup_clkdm",
 	.prcm		= {
 		.omap4	= {
 			.clkctrl_offs	= AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},
 	.opt_clks	= gpio0_opt_clks,
 	.opt_clks_cnt	= ARRAY_SIZE(gpio0_opt_clks),
 	.dev_attr	= &gpio_dev_attr,
 	.slaves		= am33xx_gpio0_slaves,
 	.slaves_cnt	= ARRAY_SIZE(am33xx_gpio0_slaves),
 };
 /* gpio1 */
 static struct omap_hwmod_irq_info am33xx_gpio1_irqs[] = {
 	{ .irq = AM33XX_IRQ_GPIO1_1 },
 	{ .irq = -1 }
 };
 /* gpio1 slave ports */
 static struct omap_hwmod_ocp_if *am33xx_gpio1_slaves[] = {
 	&am33xx_l4_per__gpio1,
 };
 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
 	{ .role = "dbclk", .clk = "gpio1_dbclk" },
 };
 static struct omap_hwmod am33xx_gpio1_hwmod = {
 	.name		= "gpio2",
 	.class		= &am33xx_gpio_hwmod_class,
 	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 	.mpu_irqs	= am33xx_gpio1_irqs,
 	.main_clk	= "gpio1_ick",
 	.clkdm_name	= "l4ls_clkdm",
 	.prcm		= {
 		.omap4	= {
 			.clkctrl_offs	= AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},
 	.opt_clks	= gpio1_opt_clks,
 	.opt_clks_cnt	= ARRAY_SIZE(gpio1_opt_clks),
 	.dev_attr	= &gpio_dev_attr,
 	.slaves		= am33xx_gpio1_slaves,
 	.slaves_cnt	= ARRAY_SIZE(am33xx_gpio1_slaves),
 };
 /* gpio2 */
 static struct omap_hwmod_irq_info am33xx_gpio2_irqs[] = {
 	{ .irq = AM33XX_IRQ_GPIO2_1 },
 	{ .irq = -1 }
 };
 /* gpio2 slave ports */
 static struct omap_hwmod_ocp_if *am33xx_gpio2_slaves[] = {
 	&am33xx_l4_per__gpio2,
 };
 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
 	{ .role = "dbclk", .clk = "gpio2_dbclk" },
 };
 /* gpio2 */
 static struct omap_hwmod am33xx_gpio2_hwmod = {
 	.name		= "gpio3",
 	.class		= &am33xx_gpio_hwmod_class,
 	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 	.mpu_irqs	= am33xx_gpio2_irqs,
 	.main_clk	= "gpio2_ick",
 	.clkdm_name	= "l4ls_clkdm",
 	.prcm		= {
 		.omap4	= {
 			.clkctrl_offs	= AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},
 	.opt_clks	= gpio2_opt_clks,
 	.opt_clks_cnt	= ARRAY_SIZE(gpio2_opt_clks),
 	.dev_attr	= &gpio_dev_attr,
 	.slaves		= am33xx_gpio2_slaves,
 	.slaves_cnt	= ARRAY_SIZE(am33xx_gpio2_slaves),
 };
 /* gpio3 */
 static struct omap_hwmod_irq_info am33xx_gpio3_irqs[] = {
 	{ .irq = AM33XX_IRQ_GPIO3_1 },
 	{ .irq = -1 }
 };
 /* gpio3 slave ports */
 static struct omap_hwmod_ocp_if *am33xx_gpio3_slaves[] = {
 	&am33xx_l4_per__gpio3,
 };
 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
 	{ .role = "dbclk", .clk = "gpio3_dbclk" },
 };
 /* gpio3 */
 static struct omap_hwmod am33xx_gpio3_hwmod = {
 	.name		= "gpio4",
 	.class		= &am33xx_gpio_hwmod_class,
 	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 	.mpu_irqs	= am33xx_gpio3_irqs,
 	.main_clk	= "gpio3_ick",
 	.clkdm_name	= "l4ls_clkdm",
 	.prcm		= {
 		.omap4	= {
 			.clkctrl_offs	= AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},
 	.opt_clks	= gpio3_opt_clks,
 	.opt_clks_cnt	= ARRAY_SIZE(gpio3_opt_clks),
 	.dev_attr	= &gpio_dev_attr,
 	.slaves		= am33xx_gpio3_slaves,
 	.slaves_cnt	= ARRAY_SIZE(am33xx_gpio3_slaves),
 };
 /* 'gpmc' class */
 static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
 	.name		= "gpmc",
 };
 /* gpmc */
 static struct omap_hwmod am33xx_gpmc_hwmod = {
 	.name		= "gpmc",
 	.class		= &am33xx_gpmc_hwmod_class,
 	.main_clk	= "gpmc_fck",
 	.clkdm_name	= "l3s_clkdm",
 	.prcm		= {
 		.omap4	= {
 			.clkctrl_offs	= AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},
 };
 /* 'i2c' class */
 static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
 	.sysc_offs	= 0x0010,
 	.syss_offs	= 0x0090,
 	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 			SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 			SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 			SIDLE_SMART_WKUP),
 	.sysc_fields	= &omap_hwmod_sysc_type1,
 };
 static struct omap_i2c_dev_attr i2c_dev_attr = {
 	.flags		= OMAP_I2C_FLAG_BUS_SHIFT_NONE,
 };
 static struct omap_hwmod_class i2c_class = {
 	.name		= "i2c",
 	.sysc		= &am33xx_i2c_sysc,
 	.rev		= OMAP_I2C_IP_VERSION_2,
 	.reset		= &omap_i2c_reset,
 };
 /* I2C1 */
 static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
 	{ .irq = AM33XX_IRQ_MSHSI2COCP0 },
 	{ .irq = -1 }
 };
 static struct omap_hwmod_dma_info i2c1_edma_reqs[] = {
 	{ .name = "tx", .dma_req = 0, },
 	{ .name = "rx", .dma_req = 0, },
 	{ .dma_req = -1 }
 };
 static struct omap_hwmod_ocp_if *am33xx_i2c1_slaves[] = {
 	&am33xx_l4_wkup_i2c1,
 };
 static struct omap_hwmod am33xx_i2c1_hwmod = {
 	.name		= "i2c1",
 	.mpu_irqs	= i2c1_mpu_irqs,
 	.sdma_reqs	= i2c1_edma_reqs,
 	.main_clk	= "i2c1_fck",
 	.clkdm_name	= "l4_wkup_clkdm",
 	.prcm		= {
 		.omap4	= {
 			.clkctrl_offs	= AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},
 	.flags		= HWMOD_16BIT_REG,
 	.dev_attr	= &i2c_dev_attr,
 	.slaves		= am33xx_i2c1_slaves,
 	.slaves_cnt	= ARRAY_SIZE(am33xx_i2c1_slaves),
 	.class		= &i2c_class,
 };
 /* i2c2 */
 /* l4 per -> i2c2 */
 static struct omap_hwmod_addr_space am33xx_i2c2_addr_space[] = {
 	{
 		.pa_start	= AM33XX_I2C1_BASE,
 		.pa_end		= AM33XX_I2C1_BASE + SZ_4K - 1,
 		.flags		= ADDR_TYPE_RT
 	},
 	{ }
 };
 static struct omap_hwmod_ocp_if am335_l4_per_i2c2 = {
 	.master		= &am33xx_l4per_hwmod,
 	.slave		= &am33xx_i2c2_hwmod,
 	.addr		= am33xx_i2c2_addr_space,
 	.user		= OCP_USER_MPU,
 };
 static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
 	{ .irq = AM33XX_IRQ_MSHSI2COCP1 },
 	{ .irq = -1 }
 };
 static struct omap_hwmod_dma_info i2c2_edma_reqs[] = {
 	{ .name = "tx", .dma_req = 0, },
 	{ .name = "rx", .dma_req = 0, },
 	{ .dma_req = -1 }
 };
 static struct omap_hwmod_ocp_if *am33xx_i2c2_slaves[] = {
 	&am335_l4_per_i2c2,
 };
 static struct omap_hwmod am33xx_i2c2_hwmod = {
 	.name		= "i2c2",
 	.mpu_irqs	= i2c2_mpu_irqs,
 	.sdma_reqs	= i2c2_edma_reqs,
 	.main_clk	= "i2c2_fck",
 	.clkdm_name	= "l4ls_clkdm",
 	.prcm		= {
 		.omap4 = {
 			.clkctrl_offs	= AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},
 	.flags		= HWMOD_16BIT_REG,
 	.dev_attr	= &i2c_dev_attr,
 	.slaves		= am33xx_i2c2_slaves,
 	.slaves_cnt	= ARRAY_SIZE(am33xx_i2c2_slaves),
 	.class		= &i2c_class,
 };
 /* 'icss' class */
 static struct omap_hwmod_class am33xx_icss_hwmod_class = {
 	.name = "icss",
 };
 /* icss */
 static struct omap_hwmod am33xx_icss_hwmod = {
 	.name		= "icss",
 	.class		= &am33xx_icss_hwmod_class,
 	.main_clk	= "icss_uart_gclk",
 	.clkdm_name	= "icss_ocp_clkdm",
 	.prcm		= {
 		.omap4	= {
 			.clkctrl_offs	= AM33XX_CM_PER_ICSS_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},
 };
 /* 'ieee5000' class */
 static struct omap_hwmod_class am33xx_ieee5000_hwmod_class = {
 	.name		= "ieee5000",
 };
 /* ieee5000 */
 static struct omap_hwmod am33xx_ieee5000_hwmod = {
 	.name		= "ieee5000",
 	.class		= &am33xx_ieee5000_hwmod_class,
 	.main_clk	= "ieee5000_fck",
 	.clkdm_name	= "l3s_clkdm",
 	.prcm		= {
 		.omap4	= {
 			.clkctrl_offs	= AM33XX_CM_PER_IEEE5000_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},
 };
 /* 'l3' class */
 static struct omap_hwmod_class am33xx_l3_hwmod_class = {
 	.name		= "l3",
 };
 /* l4_hs */
 static struct omap_hwmod am33xx_l4_hs_hwmod = {
 	.name		= "l4_hs",
 	.class		= &am33xx_l3_hwmod_class,
 	.clkdm_name	= "l4hs_clkdm",
 	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
 	.prcm		= {
 		.omap4	= {
 			.clkctrl_offs	= AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},
 };
 /* l3_instr */
 static struct omap_hwmod am33xx_l3_instr_hwmod = {
 	.name		= "l3_instr",
 	.class		= &am33xx_l3_hwmod_class,
 	.clkdm_name	= "l3_clkdm",
 	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
 	.prcm		= {
 		.omap4	= {
 			.clkctrl_offs	= AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},
 };
 /* l3_main */
 static struct omap_hwmod am33xx_l3_main_hwmod = {
 	.name		= "l3_main",
 	.class		= &am33xx_l3_hwmod_class,
 	.clkdm_name	= "l3_clkdm",
 	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
 	.prcm		= {
 		.omap4	= {
 			.clkctrl_offs	= AM33XX_CM_PER_L3_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},
 };
 /* 'l4fw' class */
 static struct omap_hwmod_class am33xx_l4fw_hwmod_class = {
 	.name		= "l4fw",
 };
 /* l4fw */
 static struct omap_hwmod am33xx_l4fw_hwmod = {
 	.name		= "l4fw",
 	.class		= &am33xx_l4fw_hwmod_class,
 	.clkdm_name	= "l4fw_clkdm",
 	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
 	.prcm		= {
 		.omap4	= {
 			.clkctrl_offs	= AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},
 };
 /* 'l4ls' class */
 static struct omap_hwmod_class am33xx_l4ls_hwmod_class = {
 	.name		= "l4ls",
 };
 /* l4ls */
 static struct omap_hwmod am33xx_l4ls_hwmod = {
 	.name		= "l4ls",
 	.class		= &am33xx_l4ls_hwmod_class,
 	.main_clk	= "l4ls_gclk",
 	.clkdm_name	= "l4ls_clkdm",
 	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
 	.prcm		= {
 		.omap4	= {
 			.clkctrl_offs	= AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},
 };
 /* 'lcdc' class */
 static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
 	.name		= "lcdc",
 };
 /* lcdc */
 static struct omap_hwmod_irq_info am33xx_lcdc_irqs[] = {
 	{ .irq = AM33XX_IRQ_LCD },
 	{ .irq = -1 }
 };
 static struct omap_hwmod am33xx_lcdc_hwmod = {
 	.name		= "lcdc",
 	.class		= &am33xx_lcdc_hwmod_class,
 	.mpu_irqs	= am33xx_lcdc_irqs,
 	.main_clk	= "lcdc_fck",
 	.clkdm_name	= "lcdc_clkdm",
 	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
 	.prcm		= {
 		.omap4	= {
 			.clkctrl_offs	= AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},
 };
 /* 'mcasp' class */
 static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
 	.name		= "mcasp",
 };
 /* mcasp0 */
 static struct omap_hwmod_irq_info am33xx_mcasp0_irqs[] = {
 	{ .irq = 80 },
 	{ .irq = -1 }
 };
 static struct omap_hwmod am33xx_mcasp0_hwmod = {
 	.name		= "mcasp0",
 	.class		= &am33xx_mcasp_hwmod_class,
 	.mpu_irqs	= am33xx_mcasp0_irqs,
 	.main_clk	= "mcasp0_fck",
 	.clkdm_name	= "l3s_clkdm",
 	.prcm		= {
 		.omap4	= {
 			.clkctrl_offs	= AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},
 };
 /* 'mmc' class */
 static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = {
 	.rev_offs	= 0x1fc,
 	.sysc_offs	= 0x10,
 	.syss_offs	= 0x14,
 	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 			SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 			SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 	.sysc_fields	= &omap_hwmod_sysc_type1,
 };
 static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
 	.name		= "mmc",
 	.sysc		= &am33xx_mmc_sysc,
 };
 /* mmc0 */
 static struct omap_hwmod_irq_info am33xx_mmc0_irqs[] = {
 	{ .irq = AM33XX_IRQ_MMCHS0 },
 	{ .irq = -1 }
 };
 static struct omap_hwmod_dma_info am33xx_mmc0_edma_reqs[] = {
 	{ .name = "tx", .dma_req = AM33XX_DMA_MMCHS0_W, },
 	{ .name = "rx", .dma_req = AM33XX_DMA_MMCHS0_R, },
 	{ .dma_req = -1 }
 };
 static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = {
 	{
 		.pa_start	= AM33XX_MMC0_BASE,
 		.pa_end		= AM33XX_MMC0_BASE + SZ_4K - 1,
 		.flags		= ADDR_TYPE_RT
 	},
 	{ }
 };
 static struct omap_hwmod_ocp_if am33xx_l4ls__mmc0 = {
 	.master		= &am33xx_l4ls_hwmod,
 	.slave		= &am33xx_mmc0_hwmod,
 	.clk		= "mmc0_ick",
 	.addr		= am33xx_mmc0_addr_space,
 	.user		= OCP_USER_MPU,
 };
 static struct omap_hwmod_ocp_if *am33xx_mmc0_slaves[] = {
 	&am33xx_l4ls__mmc0,
 };
 static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = {
 	.flags		= OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
 };
 static struct omap_hwmod am33xx_mmc0_hwmod = {
 	.name		= "mmc1",
 	.class		= &am33xx_mmc_hwmod_class,
 	.mpu_irqs	= am33xx_mmc0_irqs,
 	.sdma_reqs	= am33xx_mmc0_edma_reqs,
 	.main_clk	= "mmc0_fck",
 	.clkdm_name	= "l4ls_clkdm",
 	.prcm		= {
 		.omap4	= {
 			.clkctrl_offs	= AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},
 	.dev_attr	= &am33xx_mmc0_dev_attr,
 	.slaves		= am33xx_mmc0_slaves,
 	.slaves_cnt	= ARRAY_SIZE(am33xx_mmc0_slaves),
 };
 /* mmc1 */
 static struct omap_hwmod_irq_info am33xx_mmc1_irqs[] = {
 	{ .irq = AM33XX_IRQ_MMCHS1 },
 	{ .irq = -1 }
 };
 static struct omap_hwmod_dma_info am33xx_mmc1_edma_reqs[] = {
 	{ .name = "tx", .dma_req = AM33XX_DMA_MMCHS1_W, },
 	{ .name = "rx", .dma_req = AM33XX_DMA_MMCHS1_R, },
 	{ .dma_req = -1 }
 };
 static struct omap_hwmod_addr_space am33xx_mmc1_addr_space[] = {
 	{
 		.pa_start	= AM33XX_MMC1_BASE,
 		.pa_end		= AM33XX_MMC1_BASE + SZ_4K - 1,
 		.flags		= ADDR_TYPE_RT
 	},
 	{ }
 };
 static struct omap_hwmod_ocp_if am33xx_l4ls__mmc1 = {
 	.master		= &am33xx_l4ls_hwmod,
 	.slave		= &am33xx_mmc1_hwmod,
 	.clk		= "mmc1_ick",
 	.addr		= am33xx_mmc1_addr_space,
 	.user		= OCP_USER_MPU,
 };
 static struct omap_hwmod_ocp_if *am33xx_mmc1_slaves[] = {
 	&am33xx_l4ls__mmc1,
 };
 static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = {
 	.flags		= OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
 };
 static struct omap_hwmod am33xx_mmc1_hwmod = {
 	.name		= "mmc2",
 	.class		= &am33xx_mmc_hwmod_class,
 	.mpu_irqs	= am33xx_mmc1_irqs,
 	.sdma_reqs	= am33xx_mmc1_edma_reqs,
 	.main_clk	= "mmc1_fck",
 	.clkdm_name	= "l4ls_clkdm",
 	.prcm		= {
 		.omap4	= {
 			.clkctrl_offs	= AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},
 	.dev_attr	= &am33xx_mmc1_dev_attr,
 	.slaves		= am33xx_mmc1_slaves,
 	.slaves_cnt	= ARRAY_SIZE(am33xx_mmc1_slaves),
 };
 /* mmc2 */
 static struct omap_hwmod_irq_info am33xx_mmc2_irqs[] = {
 	{ .irq = AM33XX_IRQ_MMCHS2 },
 	{ .irq = -1 }
 };
 static struct omap_hwmod_dma_info am33xx_mmc2_edma_reqs[] = {
 	{ .name = "tx", .dma_req = AM33XX_DMA_MMCHS2_W, },
 	{ .name = "rx", .dma_req = AM33XX_DMA_MMCHS2_R, },
 	{ .dma_req = -1 }
 };
 static struct omap_hwmod_addr_space am33xx_mmc2_addr_space[] = {
 	{
 		.pa_start	= AM33XX_MMC2_BASE,
 		.pa_end		= AM33XX_MMC2_BASE + SZ_64K - 1,
 		.flags		= ADDR_TYPE_RT
 	},
 	{ }
 };
 static struct omap_hwmod_ocp_if am33xx_l3_main__mmc2 = {
 	.master		= &am33xx_l3_main_hwmod,
 	.slave		= &am33xx_mmc2_hwmod,
 	.clk		= "mmc2_ick",
 	.addr		= am33xx_mmc2_addr_space,
 	.user		= OCP_USER_MPU,
 };
 static struct omap_hwmod_ocp_if *am33xx_mmc2_slaves[] = {
 	&am33xx_l3_main__mmc2,
 };
 static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = {
 	.flags		= OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
 };
 static struct omap_hwmod am33xx_mmc2_hwmod = {
 	.name		= "mmc3",
 	.class		= &am33xx_mmc_hwmod_class,
 	.mpu_irqs	= am33xx_mmc2_irqs,
 	.sdma_reqs	= am33xx_mmc2_edma_reqs,
 	.main_clk	= "mmc2_fck",
 	.clkdm_name	= "l3s_clkdm",
 	.prcm		= {
 		.omap4	= {
 			.clkctrl_offs	= AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},
 	.dev_attr	= &am33xx_mmc2_dev_attr,
 	.slaves		= am33xx_mmc2_slaves,
 	.slaves_cnt	= ARRAY_SIZE(am33xx_mmc2_slaves),
 };
 /* Master interfaces on the MPU interconnect */
 static struct omap_hwmod_ocp_if *am33xx_l3_mpu_masters[] = {
 	&am33xx_mpu__l3_slow,
 };
 /* mpu */
 static struct omap_hwmod am33xx_mpu_hwmod = {
 	.name		= "mpu",
 	.class		= &mpu_hwmod_class,
 	.masters	= am33xx_l3_mpu_masters,
 	.masters_cnt	= ARRAY_SIZE(am33xx_l3_mpu_masters),
 	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
 	.main_clk	= "mpu_fck",
 	.clkdm_name	= "mpu_clkdm",
 	.prcm		= {
 		.omap4	= {
 			.clkctrl_offs	= AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},
 };
 /* 'ocmcram' class */
 static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
 	.name = "ocmcram",
 };
 /* ocmcram */
 static struct omap_hwmod am33xx_ocmcram_hwmod = {
 	.name		= "ocmcram",
 	.class		= &am33xx_ocmcram_hwmod_class,
 	.main_clk	= "ocmcram_ick",
 	.clkdm_name	= "l3_clkdm",
 	.prcm		= {
 		.omap4	= {
 			.clkctrl_offs	= AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},
 };
 /* 'ocpwp' class */
 static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
 	.name		= "ocpwp",
 };
 /* ocpwp */
 static struct omap_hwmod am33xx_ocpwp_hwmod = {
 	.name		= "ocpwp",
 	.class		= &am33xx_ocpwp_hwmod_class,
 	.main_clk	= "ocpwp_fck",
 	.clkdm_name	= "l4ls_clkdm",
 	.prcm		= {
 		.omap4	= {
 			.clkctrl_offs	= AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},
 };
 /* 'rtc' class */
 static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
 	.name		= "rtc",
 };
 /* rtc */
 static struct omap_hwmod_irq_info am33xx_rtc_irqs[] = {
 	{ .irq = AM33XX_IRQ_RTC_TIMER },
 	{ .irq = -1 }
 };
 static struct omap_hwmod am33xx_rtc_hwmod = {
 	.name		= "rtc",
 	.class		= &am33xx_rtc_hwmod_class,
 	.mpu_irqs	= am33xx_rtc_irqs,
 	.main_clk	= "rtc_fck",
 	.clkdm_name	= "l4_rtc_clkdm",
 	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
 	.prcm		= {
 		.omap4	= {
 			.clkctrl_offs	= AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},
 };
 /* 'sha0' class */
 static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
 	.name		= "sha0",
 };
 /* sha0 */
 static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = {
 	{ .irq = AM33XX_IRQ_SHAEIP57t0_S },
 	{ .irq = -1 }
 };
 static struct omap_hwmod am33xx_sha0_hwmod = {
 	.name		= "sha0",
 	.class		= &am33xx_sha0_hwmod_class,
 	.mpu_irqs	= am33xx_sha0_irqs,
 	.main_clk	= "sha0_fck",
 	.clkdm_name	= "l3_clkdm",
 	.prcm		= {
 		.omap4	= {
 			.clkctrl_offs	= AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},
 };
 /* 'smartreflex' class */
 static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
 	.name		= "smartreflex",
 };
 /* smartreflex0 */
 static struct omap_hwmod_irq_info am33xx_smartreflex0_irqs[] = {
 	{ .irq = AM33XX_IRQ_SMARTREFLEX0 },
 	{ .irq = -1 }
 };
 static struct omap_hwmod am33xx_smartreflex0_hwmod = {
 	.name		= "smartreflex0",
 	.class		= &am33xx_smartreflex_hwmod_class,
 	.mpu_irqs	= am33xx_smartreflex0_irqs,
 	.main_clk	= "smartreflex0_fck",
 	.clkdm_name	= "l4_wkup_clkdm",
 	.prcm		= {
 		.omap4	= {
 			.clkctrl_offs	= AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},
 };
 /* smartreflex1 */
 static struct omap_hwmod_irq_info am33xx_smartreflex1_irqs[] = {
 	{ .irq = AM33XX_IRQ_SMARTREFLEX1 },
 	{ .irq = -1 }
 };
 static struct omap_hwmod am33xx_smartreflex1_hwmod = {
 	.name		= "smartreflex1",
 	.class		= &am33xx_smartreflex_hwmod_class,
 	.mpu_irqs	= am33xx_smartreflex1_irqs,
 	.main_clk	= "smartreflex1_fck",
 	.clkdm_name	= "l4_wkup_clkdm",
 	.prcm		= {
 		.omap4	= {
 			.clkctrl_offs	= AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},
 };
 /* 'spi' class */
 static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
 	.rev_offs	= 0x0000,
 	.sysc_offs	= 0x0110,
 	.syss_offs	= 0x0114,
 	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 			SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 			SYSS_HAS_RESET_STATUS),
 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 	.sysc_fields	= &omap_hwmod_sysc_type1,
 };
 static struct omap_hwmod_class am33xx_spi_hwmod_class = {
 	.name		= "mcspi",
 	.sysc		= &am33xx_mcspi_sysc,
 	.rev		= OMAP4_MCSPI_REV,
 };
 /* spi0 */
 static struct omap_hwmod_irq_info am33xx_spi0_irqs[] = {
 	{ .irq = AM33XX_IRQ_MCSPIOCP0 },
 	{ .irq = -1 }
 };
 struct omap_hwmod_dma_info am33xx_mcspi0_sdma_reqs[] = {
 	{ .name = "rx0", .dma_req = AM33XX_DMA_SPIOCP0_CH0R },
 	{ .name = "tx0", .dma_req = AM33XX_DMA_SPIOCP0_CH0W },
 	{ .name = "rx1", .dma_req = AM33XX_DMA_SPIOCP0_CH1R },
 	{ .name = "tx1", .dma_req = AM33XX_DMA_SPIOCP0_CH1W },
 	{ .dma_req = -1 }
 };
 struct omap_hwmod_addr_space am33xx_mcspi0_addr_space[] = {
 	{
 		.pa_start	= AM33XX_SPI0_BASE,
 		.pa_end		= AM33XX_SPI0_BASE + SZ_1K - 1,
 		.flags		= ADDR_TYPE_RT
 	},
 	{ }
 };
 struct omap_hwmod_ocp_if am33xx_l4_core__mcspi0 = {
 	.master		= &am33xx_l4per_hwmod,
 	.slave		= &am33xx_spi0_hwmod,
 	.clk		= "spi0_ick",
 	.addr		= am33xx_mcspi0_addr_space,
 	.user		= OCP_USER_MPU,
 };
 static struct omap_hwmod_ocp_if *am33xx_mcspi0_slaves[] = {
 	&am33xx_l4_core__mcspi0,
 };
 struct omap2_mcspi_dev_attr mcspi_attrib = {
 	.num_chipselect	= 2,
 };
 static struct omap_hwmod am33xx_spi0_hwmod = {
 	.name		= "spi0",
 	.class		= &am33xx_spi_hwmod_class,
 	.mpu_irqs	= am33xx_spi0_irqs,
 	.sdma_reqs	= am33xx_mcspi0_sdma_reqs,
 	.main_clk	= "spi0_fck",
 	.clkdm_name	= "l4ls_clkdm",
 	.prcm		= {
 		.omap4	= {
 			.clkctrl_offs	= AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},
 	.dev_attr	= &mcspi_attrib,
 	.slaves		= am33xx_mcspi0_slaves,
 	.slaves_cnt	= ARRAY_SIZE(am33xx_mcspi0_slaves),
 };
 /* spi1 */
 static struct omap_hwmod_irq_info am33xx_spi1_irqs[] = {
 	{ .irq = AM33XX_IRQ_SPI1 },
 	{ .irq = -1 }
 };
 struct omap_hwmod_dma_info am33xx_mcspi1_sdma_reqs[] = {
 	{ .name = "rx0", .dma_req = AM33XX_DMA_SPIOCP1_CH0R },
 	{ .name = "tx0", .dma_req = AM33XX_DMA_SPIOCP1_CH0W },
 	{ .name = "rx1", .dma_req = AM33XX_DMA_SPIOCP1_CH1R },
 	{ .name = "tx1", .dma_req = AM33XX_DMA_SPIOCP1_CH1W },
 	{ .dma_req = -1 }
 };
 struct omap_hwmod_addr_space am33xx_mcspi1_addr_space[] = {
 	{
 		.pa_start	= AM33XX_SPI1_BASE,
 		.pa_end		= AM33XX_SPI1_BASE + SZ_1K - 1,
 		.flags		= ADDR_TYPE_RT
 	},
 	{ }
 };
 struct omap_hwmod_ocp_if am33xx_l4_core__mcspi1 = {
 	.master		= &am33xx_l4per_hwmod,
 	.slave		= &am33xx_spi1_hwmod,
 	.clk		= "spi1_ick",
 	.addr		= am33xx_mcspi1_addr_space,
 	.user		= OCP_USER_MPU,
 };
 static struct omap_hwmod_ocp_if *am33xx_mcspi1_slaves[] = {
 	&am33xx_l4_core__mcspi1,
 };
 static struct omap_hwmod am33xx_spi1_hwmod = {
 	.name		= "spi1",
 	.class		= &am33xx_spi_hwmod_class,
 	.mpu_irqs	= am33xx_spi1_irqs,
 	.sdma_reqs	= am33xx_mcspi1_sdma_reqs,
 	.main_clk	= "spi1_fck",
 	.clkdm_name	= "l4ls_clkdm",
 	.prcm		= {
 		.omap4	= {
 			.clkctrl_offs	= AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},
 	.dev_attr	= &mcspi_attrib,
 	.slaves		= am33xx_mcspi1_slaves,
 	.slaves_cnt	= ARRAY_SIZE(am33xx_mcspi1_slaves),
 };
 /* 'spinlock' class */
 static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
 	.name		= "spinlock",
 };
 /* spinlock */
 static struct omap_hwmod am33xx_spinlock_hwmod = {
 	.name		= "spinlock",
 	.class		= &am33xx_spinlock_hwmod_class,
 	.main_clk	= "spinlock_fck",
 	.clkdm_name	= "l4ls_clkdm",
 	.prcm		= {
 		.omap4	= {
 			.clkctrl_offs	= AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},
 };
 /* 'timer 0 & 2-7' class */
 static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
 	.rev_offs	= 0x0000,
 	.sysc_offs	= 0x0010,
 	.syss_offs	= 0x0014,
 	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 			SIDLE_SMART_WKUP),
 	.sysc_fields	= &omap_hwmod_sysc_type2,
 };
 static struct omap_hwmod_class am33xx_timer_hwmod_class = {
 	.name		= "timer",
 	.sysc		= &am33xx_timer_sysc,
 };
 /* timer0 */
 /* l4 wkup -> timer0 interface */
 static struct omap_hwmod_addr_space am33xx_timer0_addr_space[] = {
 	{
 		.pa_start	= AM33XX_TIMER0_BASE,
 		.pa_end		= AM33XX_TIMER0_BASE + SZ_1K - 1,
 		.flags		= ADDR_TYPE_RT
 	},
 	{ }
 };
 static struct omap_hwmod_ocp_if am33xx_l4wkup__timer0 = {
 	.master		= &am33xx_l4wkup_hwmod,
 	.slave		= &am33xx_timer0_hwmod,
 	.clk		= "timer0_ick",
 	.addr		= am33xx_timer0_addr_space,
 	.user		= OCP_USER_MPU,
 };
 static struct omap_hwmod_ocp_if *am33xx_timer0_slaves[] = {
 	&am33xx_l4wkup__timer0,
 };
 static struct omap_hwmod_irq_info am33xx_timer0_irqs[] = {
 	{ .irq = AM33XX_IRQ_DMTIMER0 },
 	{ .irq = -1 }
 };
 static struct omap_hwmod am33xx_timer0_hwmod = {
 	.name		= "timer0",
 	.class		= &am33xx_timer_hwmod_class,
 	.mpu_irqs	= am33xx_timer0_irqs,
 	.main_clk	= "timer0_fck",
 	.clkdm_name	= "l4_wkup_clkdm",
 	.prcm		= {
 		.omap4	= {
 			.clkctrl_offs	= AM33XX_CM_WKUP_TIMER0_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},
 	.slaves		= am33xx_timer0_slaves,
 	.slaves_cnt	= ARRAY_SIZE(am33xx_timer0_slaves),
 };
 /* timer1 1ms */
 static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
 	.rev_offs	= 0x0000,
 	.sysc_offs	= 0x0010,
 	.syss_offs	= 0x0014,
 	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 			SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 			SYSS_HAS_RESET_STATUS),
 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 	.sysc_fields	= &omap_hwmod_sysc_type1,
 };
 static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
 	.name		= "timer",
 	.sysc		= &am33xx_timer1ms_sysc,
 };
 /* l4 wkup -> timer1 interface */
 static struct omap_hwmod_addr_space am33xx_timer1_addr_space[] = {
 	{
 		.pa_start	= AM33XX_TIMER1_BASE,
 		.pa_end		= AM33XX_TIMER1_BASE + SZ_1K - 1,
 		.flags		= ADDR_TYPE_RT
 	},
 	{ }
 };
 static struct omap_hwmod_ocp_if am33xx_l4wkup__timer1 = {
 	.master		= &am33xx_l4wkup_hwmod,
 	.slave		= &am33xx_timer1_hwmod,
 	.clk		= "timer1_ick",
 	.addr		= am33xx_timer1_addr_space,
 	.user		= OCP_USER_MPU,
 };
 static struct omap_hwmod_ocp_if *am33xx_timer1_slaves[] = {
 	&am33xx_l4wkup__timer1,
 };
 static struct omap_hwmod_irq_info am33xx_timer1_irqs[] = {
 	{ .irq = AM33XX_IRQ_DMTIMER1 },
 	{ .irq = -1 }
 };
 static struct omap_hwmod am33xx_timer1_hwmod = {
 	.name		= "timer1",
 	.class		= &am33xx_timer1ms_hwmod_class,
 	.mpu_irqs	= am33xx_timer1_irqs,
 	.main_clk	= "timer1_fck",
 	.clkdm_name	= "l4_wkup_clkdm",
 	.prcm		= {
 		.omap4	= {
 			.clkctrl_offs	= AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},
 	.slaves		= am33xx_timer1_slaves,
 	.slaves_cnt	= ARRAY_SIZE(am33xx_timer1_slaves),
 };
 /* timer2 */
 /* l4 per -> timer2 interface */
 static struct omap_hwmod_addr_space am33xx_timer2_addr_space[] = {
 	{
 		.pa_start	= AM33XX_TIMER2_BASE,
 		.pa_end		= AM33XX_TIMER2_BASE + SZ_1K - 1,
 		.flags		= ADDR_TYPE_RT
 	},
 	{ }
 };
 static struct omap_hwmod_ocp_if am33xx_l4per__timer2 = {
 	.master		= &am33xx_l4per_hwmod,
 	.slave		= &am33xx_timer2_hwmod,
 	.clk		= "timer2_ick",
 	.addr		= am33xx_timer2_addr_space,
 	.user		= OCP_USER_MPU,
 };
 static struct omap_hwmod_ocp_if *am33xx_timer2_slaves[] = {
 	&am33xx_l4per__timer2,
 };
 static struct omap_hwmod_irq_info am33xx_timer2_irqs[] = {
 	{ .irq = AM33XX_IRQ_DMTIMER2 },
 	{ .irq = -1 }
 };
 static struct omap_hwmod am33xx_timer2_hwmod = {
 	.name		= "timer2",
 	.class		= &am33xx_timer_hwmod_class,
 	.mpu_irqs	= am33xx_timer2_irqs,
 	.main_clk	= "timer2_fck",
 	.prcm		= {
 		.omap4	= {
 			.clkctrl_offs	= AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},
 	.slaves		= am33xx_timer2_slaves,
 	.slaves_cnt	= ARRAY_SIZE(am33xx_timer2_slaves),
 	.clkdm_name	= "l4ls_clkdm",
 };
 /* timer3 */
 /* l4 per -> timer3 interface */
 static struct omap_hwmod_addr_space am33xx_timer3_addr_space[] = {
 	{
 		.pa_start	= AM33XX_TIMER3_BASE,
 		.pa_end		= AM33XX_TIMER3_BASE + SZ_1K - 1,
 		.flags		= ADDR_TYPE_RT
 	},
 	{ }
 };
 static struct omap_hwmod_ocp_if am33xx_l4per__timer3 = {
 	.master		= &am33xx_l4per_hwmod,
 	.slave		= &am33xx_timer3_hwmod,
 	.clk		= "timer3_ick",
 	.addr		= am33xx_timer3_addr_space,
 	.user		= OCP_USER_MPU,
 };
 static struct omap_hwmod_ocp_if *am33xx_timer3_slaves[] = {
 	&am33xx_l4per__timer3,
 };
 static struct omap_hwmod_irq_info am33xx_timer3_irqs[] = {
 	{ .irq = AM33XX_IRQ_DMTIMER3 },
 	{ .irq = -1 }
 };
 static struct omap_hwmod am33xx_timer3_hwmod = {
 	.name		= "timer3",
 	.class		= &am33xx_timer_hwmod_class,
 	.mpu_irqs	= am33xx_timer3_irqs,
 	.main_clk	= "timer3_fck",
 	.clkdm_name	= "l4ls_clkdm",
 	.prcm		= {
 		.omap4	= {
 			.clkctrl_offs	= AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},
 	.slaves		= am33xx_timer3_slaves,
 	.slaves_cnt	= ARRAY_SIZE(am33xx_timer3_slaves),
 };
 /* timer4 */
 /* l4 per -> timer4 interface */
 static struct omap_hwmod_addr_space am33xx_timer4_addr_space[] = {
 	{
 		.pa_start	= AM33XX_TIMER4_BASE,
 		.pa_end		= AM33XX_TIMER4_BASE + SZ_1K - 1,
 		.flags		= ADDR_TYPE_RT
 	},
 	{ }
 };
 static struct omap_hwmod_ocp_if am33xx_l4per__timer4 = {
 	.master		= &am33xx_l4per_hwmod,
 	.slave		= &am33xx_timer4_hwmod,
 	.clk		= "timer4_ick",
 	.addr		= am33xx_timer4_addr_space,
 	.user		= OCP_USER_MPU,
 };
 static struct omap_hwmod_ocp_if *am33xx_timer4_slaves[] = {
 	&am33xx_l4per__timer4,
 };
 static struct omap_hwmod_irq_info am33xx_timer4_irqs[] = {
 	{ .irq = AM33XX_IRQ_DMTIMER4 },
 	{ .irq = -1 }
 };
 static struct omap_hwmod am33xx_timer4_hwmod = {
 	.name		= "timer4",
 	.class		= &am33xx_timer_hwmod_class,
 	.mpu_irqs	= am33xx_timer4_irqs,
 	.main_clk	= "timer4_fck",
 	.prcm		= {
 		.omap4	= {
 			.clkctrl_offs	= AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},
 	.slaves		= am33xx_timer4_slaves,
 	.slaves_cnt	= ARRAY_SIZE(am33xx_timer4_slaves),
 	.clkdm_name	= "l4ls_clkdm",
 };
 /* timer5 */
 /* l4 per -> timer5 interface */
 static struct omap_hwmod_addr_space am33xx_timer5_addr_space[] = {
 	{
 		.pa_start	= AM33XX_TIMER5_BASE,
 		.pa_end		= AM33XX_TIMER5_BASE + SZ_1K - 1,
 		.flags		= ADDR_TYPE_RT
 	},
 	{ }
 };
 static struct omap_hwmod_ocp_if am33xx_l4per__timer5 = {
 	.master		= &am33xx_l4per_hwmod,
 	.slave		= &am33xx_timer5_hwmod,
 	.clk		= "timer5_ick",
 	.addr		= am33xx_timer5_addr_space,
 	.user		= OCP_USER_MPU,
 };
 static struct omap_hwmod_ocp_if *am33xx_timer5_slaves[] = {
 	&am33xx_l4per__timer5,
 };
 static struct omap_hwmod_irq_info am33xx_timer5_irqs[] = {
 	{ .irq = AM33XX_IRQ_DMTIMER5 },
 	{ .irq = -1 }
 };
 static struct omap_hwmod am33xx_timer5_hwmod = {
 	.name		= "timer5",
 	.class		= &am33xx_timer_hwmod_class,
 	.mpu_irqs	= am33xx_timer5_irqs,
 	.main_clk	= "timer5_fck",
 	.prcm		= {
 		.omap4	= {
 			.clkctrl_offs	= AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},
 	.slaves		= am33xx_timer5_slaves,
 	.slaves_cnt	= ARRAY_SIZE(am33xx_timer5_slaves),
 	.clkdm_name	= "l4ls_clkdm",
 };
 /* timer6 */
 /* l4 per -> timer6 interface */
 static struct omap_hwmod_addr_space am33xx_timer6_addr_space[] = {
 	{
 		.pa_start	= AM33XX_TIMER6_BASE,
 		.pa_end		= AM33XX_TIMER6_BASE + SZ_1K - 1,
 		.flags		= ADDR_TYPE_RT
 	},
 	{ }
 };
 static struct omap_hwmod_ocp_if am33xx_l4per__timer6 = {
 	.master		= &am33xx_l4per_hwmod,
 	.slave		= &am33xx_timer6_hwmod,
 	.clk		= "timer6_ick",
 	.addr		= am33xx_timer6_addr_space,
 	.user		= OCP_USER_MPU,
 };
 static struct omap_hwmod_ocp_if *am33xx_timer6_slaves[] = {
 	&am33xx_l4per__timer6,
 };
 static struct omap_hwmod_irq_info am33xx_timer6_irqs[] = {
 	{ .irq = AM33XX_IRQ_DMTIMER6 },
 	{ .irq = -1 }
 };
 static struct omap_hwmod am33xx_timer6_hwmod = {
 	.name		= "timer6",
 	.class		= &am33xx_timer_hwmod_class,
 	.mpu_irqs	= am33xx_timer6_irqs,
 	.main_clk	= "timer6_fck",
 	.prcm		= {
 		.omap4	= {
 			.clkctrl_offs	= AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},
 	.slaves		= am33xx_timer6_slaves,
 	.slaves_cnt	= ARRAY_SIZE(am33xx_timer6_slaves),
 	.clkdm_name	= "l4ls_clkdm",
 };
 /* timer7 */
 /* l4 per -> timer7 interface */
 static struct omap_hwmod_addr_space am33xx_timer7_addr_space[] = {
 	{
 		.pa_start	= AM33XX_TIMER7_BASE,
 		.pa_end		= AM33XX_TIMER7_BASE + SZ_1K - 1,
 		.flags		= ADDR_TYPE_RT
 	},
 	{ }
 };
 static struct omap_hwmod_ocp_if am33xx_l4per__timer7 = {
 	.master		= &am33xx_l4per_hwmod,
 	.slave		= &am33xx_timer7_hwmod,
 	.clk		= "timer7_ick",
 	.addr		= am33xx_timer7_addr_space,
 	.user		= OCP_USER_MPU,
 };
 static struct omap_hwmod_ocp_if *am33xx_timer7_slaves[] = {
 	&am33xx_l4per__timer7,
 };
 static struct omap_hwmod_irq_info am33xx_timer7_irqs[] = {
 	{ .irq = AM33XX_IRQ_DMTIMER7 },
 	{ .irq = -1 }
 };
 static struct omap_hwmod am33xx_timer7_hwmod = {
 	.name		= "timer7",
 	.class		= &am33xx_timer_hwmod_class,
 	.mpu_irqs	= am33xx_timer7_irqs,
 	.main_clk	= "timer7_fck",
 	.prcm		= {
 		.omap4	= {
 			.clkctrl_offs	= AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},
 	.slaves		= am33xx_timer7_slaves,
 	.slaves_cnt	= ARRAY_SIZE(am33xx_timer7_slaves),
 	.clkdm_name	= "l4ls_clkdm",
 };
 /* 'tpcc' class */
 static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
 	.name		= "tpcc",
 };
 /* tpcc */
 static struct omap_hwmod_irq_info am33xx_tpcc_irqs[] = {
 	{ .irq = AM33XX_IRQ_TPCC0_INT_PO0 },
 	{ .irq = -1 },
 };
 static struct omap_hwmod am33xx_tpcc_hwmod = {
 	.name		= "tpcc",
 	.class		= &am33xx_tpcc_hwmod_class,
 	.mpu_irqs	= am33xx_tpcc_irqs,
 	.main_clk	= "tpcc_ick",
 	.clkdm_name	= "l3_clkdm",
 	.prcm		= {
 		.omap4	= {
 			.clkctrl_offs	= AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},
 };
 /* 'tptc' class */
 static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
 	.name		= "tptc",
 };
 /* tptc0 */
 static struct omap_hwmod_irq_info am33xx_tptc0_irqs[] = {
 	{ .irq = AM33XX_IRQ_TPTC0 },
 	{ .irq = -1 }
 };
 static struct omap_hwmod am33xx_tptc0_hwmod = {
 	.name		= "tptc0",
 	.class		= &am33xx_tptc_hwmod_class,
 	.mpu_irqs	= am33xx_tptc0_irqs,
 	.main_clk	= "tptc0_ick",
 	.clkdm_name	= "l3_clkdm",
 	.prcm		= {
 		.omap4	= {
 			.clkctrl_offs	= AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},
 };
 /* tptc1 */
 static struct omap_hwmod_irq_info am33xx_tptc1_irqs[] = {
 	{ .irq = AM33XX_IRQ_TPTC1 },
 	{ .irq = -1 }
 };
 static struct omap_hwmod am33xx_tptc1_hwmod = {
 	.name		= "tptc1",
 	.class		= &am33xx_tptc_hwmod_class,
 	.mpu_irqs	= am33xx_tptc1_irqs,
 	.main_clk	= "tptc1_ick",
 	.clkdm_name	= "l3_clkdm",
 	.prcm		= {
 		.omap4	= {
 			.clkctrl_offs	= AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},
 };
 /* tptc2 */
 static struct omap_hwmod_irq_info am33xx_tptc2_irqs[] = {
 	{ .irq = AM33XX_IRQ_TPTC2 },
 	{ .irq = -1 }
 };
 static struct omap_hwmod am33xx_tptc2_hwmod = {
 	.name		= "tptc2",
 	.class		= &am33xx_tptc_hwmod_class,
 	.mpu_irqs	= am33xx_tptc2_irqs,
 	.main_clk	= "tptc2_ick",
 	.clkdm_name	= "l3_clkdm",
 	.prcm		= {
 		.omap4	= {
 			.clkctrl_offs	= AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},
 };
 /* 'uart' class */
 static struct omap_hwmod_class_sysconfig uart_sysc = {
 	.rev_offs	= 0x50,
 	.sysc_offs	= 0x54,
 	.syss_offs	= 0x58,
 	.sysc_flags	= (SYSC_HAS_SIDLEMODE |
 			SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 			SYSC_HAS_AUTOIDLE),
 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 	.sysc_fields	= &omap_hwmod_sysc_type1,
 };
 static struct omap_hwmod_class uart_class = {
 	.name		= "uart",
 	.sysc		= &uart_sysc,
 };
 /* uart1 */
 static struct omap_hwmod_dma_info uart1_edma_reqs[] = {
 	{ .name = "tx",	.dma_req = 26, },
 	{ .name = "rx",	.dma_req = 27, },
 	{ .dma_req = -1 }
 };
 static struct omap_hwmod_addr_space am33xx_uart1_addr_space[] = {
 	{
 		.pa_start	= AM33XX_UART1_BASE,
 		.pa_end		= AM33XX_UART1_BASE + SZ_8K - 1,
 		.flags		= ADDR_TYPE_RT
 	},
 	{ }
 };
 static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
 	.master		= &am33xx_l4wkup_hwmod,
 	.slave		= &am33xx_uart1_hwmod,
 	.clk		= "uart1_ick",
 	.addr		= am33xx_uart1_addr_space,
 	.user		= OCP_USER_MPU,
 };
 static struct omap_hwmod_irq_info am33xx_uart1_irqs[] = {
 	{ .irq = AM33XX_IRQ_UART0 },
 	{ .irq = -1 }
 };
 static struct omap_hwmod_ocp_if *am33xx_uart1_slaves[] = {
 	&am33xx_l4_wkup__uart1,
 };
 static struct omap_hwmod am33xx_uart1_hwmod = {
 	.name		= "uart1",
 	.class		= &uart_class,
 	.mpu_irqs	= am33xx_uart1_irqs,
 	.sdma_reqs	= uart1_edma_reqs,
 	.main_clk	= "uart1_fck",
 	.clkdm_name	= "l4_wkup_clkdm",
 	.prcm		= {
 		.omap4	= {
 			.clkctrl_offs	= AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},
 	.slaves		= am33xx_uart1_slaves,
 	.slaves_cnt	= ARRAY_SIZE(am33xx_uart1_slaves),
 };
 /* uart2 */
 static struct omap_hwmod_addr_space am33xx_uart2_addr_space[] = {
 	{
 		.pa_start	= AM33XX_UART2_BASE,
 		.pa_end		= AM33XX_UART2_BASE + SZ_8K - 1,
 		.flags		= ADDR_TYPE_RT
 	},
 	{ }
 };
 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = {
 	.slave		= &am33xx_uart2_hwmod,
 	.clk		= "uart2_ick",
 	.addr		= am33xx_uart2_addr_space,
 	.user		= OCP_USER_MPU,
 };
 static struct omap_hwmod_irq_info am33xx_uart2_irqs[] = {
 	{ .irq = AM33XX_IRQ_UART1 },
 	{ .irq = -1 }
 };
 static struct omap_hwmod_ocp_if *am33xx_uart2_slaves[] = {
 	&am33xx_l4_ls__uart2,
 };
 static struct omap_hwmod am33xx_uart2_hwmod = {
 	.name		= "uart2",
 	.class		= &uart_class,
 	.mpu_irqs	= am33xx_uart2_irqs,
 	.main_clk	= "uart2_fck",
 	.clkdm_name	= "l4ls_clkdm",
 	.sdma_reqs	= uart1_edma_reqs,
 	.prcm		= {
 		.omap4	= {
 			.clkctrl_offs	= AM33XX_CM_PER_UART1_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},
 	.slaves		= am33xx_uart2_slaves,
 	.slaves_cnt	= ARRAY_SIZE(am33xx_uart2_slaves),
 };
 /* uart3 */
+static struct omap_hwmod_dma_info uart3_edma_reqs[] = {
+	{ .name = "tx",	.dma_req = 30, },
+	{ .name = "rx",	.dma_req = 31, },
+	{ .dma_req = -1 }
+};
 static struct omap_hwmod_addr_space am33xx_uart3_addr_space[] = {
 	{
 		.pa_start	= AM33XX_UART3_BASE,
 		.pa_end		= AM33XX_UART3_BASE + SZ_8K - 1,
 		.flags		= ADDR_TYPE_RT
 	},
 	{ }
 };
 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = {
 	.slave		= &am33xx_uart3_hwmod,
 	.clk		= "uart3_ick",
 	.addr		= am33xx_uart3_addr_space,
 	.user		= OCP_USER_MPU,
 };
 static struct omap_hwmod_irq_info am33xx_uart3_irqs[] = {
 	{ .irq = AM33XX_IRQ_UART2 },
 	{ .irq = -1 }
 };
 static struct omap_hwmod_ocp_if *am33xx_uart3_slaves[] = {
 	&am33xx_l4_ls__uart3,
 };
 static struct omap_hwmod am33xx_uart3_hwmod = {
 	.name		= "uart3",
 	.class		= &uart_class,
 	.mpu_irqs	= am33xx_uart3_irqs,
 	.main_clk	= "uart3_fck",
 	.clkdm_name	= "l4ls_clkdm",
-	.sdma_reqs	= uart1_edma_reqs,
+	.sdma_reqs	= uart3_edma_reqs,
 	.prcm		= {
 		.omap4	= {
 			.clkctrl_offs	= AM33XX_CM_PER_UART2_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},
 	.slaves		= am33xx_uart3_slaves,
 	.slaves_cnt	= ARRAY_SIZE(am33xx_uart3_slaves),
 };
 /* uart4 */
 static struct omap_hwmod_addr_space am33xx_uart4_addr_space[] = {
 	{
 		.pa_start	= AM33XX_UART4_BASE,
 		.pa_end		= AM33XX_UART4_BASE + SZ_8K - 1,
 		.flags		= ADDR_TYPE_RT
 	},
 	{ }
 };
 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = {
 	.slave		= &am33xx_uart4_hwmod,
 	.clk		= "uart4_ick",
 	.addr		= am33xx_uart4_addr_space,
 	.user		= OCP_USER_MPU,
 };
 static struct omap_hwmod_irq_info am33xx_uart4_irqs[] = {
 	{ .irq = AM33XX_IRQ_UART3 },
 	{ .irq = -1 }
 };
 static struct omap_hwmod_ocp_if *am33xx_uart4_slaves[] = {
 	&am33xx_l4_ls__uart4,
 };
 static struct omap_hwmod am33xx_uart4_hwmod = {
 	.name		= "uart4",
 	.class		= &uart_class,
 	.mpu_irqs	= am33xx_uart4_irqs,
 	.main_clk	= "uart4_fck",
 	.clkdm_name	= "l4ls_clkdm",
 	.sdma_reqs	= uart1_edma_reqs,
 	.prcm		= {
 		.omap4	= {
 			.clkctrl_offs	= AM33XX_CM_PER_UART3_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},
 	.slaves		= am33xx_uart4_slaves,
 	.slaves_cnt	= ARRAY_SIZE(am33xx_uart4_slaves),
 };
 /* uart5 */
 static struct omap_hwmod_addr_space am33xx_uart5_addr_space[] = {
 	{
 		.pa_start	= AM33XX_UART5_BASE,
 		.pa_end		= AM33XX_UART5_BASE + SZ_8K - 1,
 		.flags		= ADDR_TYPE_RT
 	},
 	{ }
 };
 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = {
 	.slave		= &am33xx_uart5_hwmod,
 	.clk		= "uart5_ick",
 	.addr		= am33xx_uart5_addr_space,
 	.user		= OCP_USER_MPU,
 };
 static struct omap_hwmod_irq_info am33xx_uart5_irqs[] = {
 	{ .irq = AM33XX_IRQ_UART4 },
 	{ .irq = -1 }
 };
 static struct omap_hwmod_ocp_if *am33xx_uart5_slaves[] = {
 	&am33xx_l4_ls__uart5,
 };
 static struct omap_hwmod am33xx_uart5_hwmod = {
 	.name		= "uart5",
 	.class		= &uart_class,
 	.mpu_irqs	= am33xx_uart5_irqs,
 	.main_clk	= "uart5_fck",
 	.clkdm_name	= "l4ls_clkdm",
 	.sdma_reqs	= uart1_edma_reqs,
 	.prcm		= {
 		.omap4	= {
 			.clkctrl_offs	= AM33XX_CM_PER_UART4_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},
 	.slaves		= am33xx_uart5_slaves,
 	.slaves_cnt	= ARRAY_SIZE(am33xx_uart5_slaves),
 };
 /* uart6 */
 static struct omap_hwmod_addr_space am33xx_uart6_addr_space[] = {
 	{
 		.pa_start	= AM33XX_UART6_BASE,
 		.pa_end		= AM33XX_UART6_BASE + SZ_8K - 1,
 		.flags		= ADDR_TYPE_RT
 	},
 	{ }
 };
 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = {
 	.slave		= &am33xx_uart6_hwmod,
 	.clk		= "uart6_ick",
 	.addr		= am33xx_uart6_addr_space,
 	.user		= OCP_USER_MPU,
 };
 static struct omap_hwmod_irq_info am33xx_uart6_irqs[] = {
 	{ .irq = AM33XX_IRQ_UART5 },
 	{ .irq = -1 }
 };
 static struct omap_hwmod_ocp_if *am33xx_uart6_slaves[] = {
 	&am33xx_l4_ls__uart6,
 };
 static struct omap_hwmod am33xx_uart6_hwmod = {
 	.name		= "uart6",
 	.class		= &uart_class,
 	.mpu_irqs	= am33xx_uart6_irqs,
 	.main_clk	= "uart6_fck",
 	.clkdm_name	= "l4ls_clkdm",
 	.sdma_reqs	= uart1_edma_reqs,
 	.prcm		= {
 		.omap4	= {
 			.clkctrl_offs	= AM33XX_CM_PER_UART5_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},
 	.slaves		= am33xx_uart6_slaves,
 	.slaves_cnt	= ARRAY_SIZE(am33xx_uart6_slaves),
 };
 /* 'wd_timer' class */
 static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
 	.name		= "wd_timer",
 };
 static struct omap_hwmod_addr_space am33xx_wd_timer1_addrs[] = {
 	{
 		.pa_start	= AM33XX_WDT1_BASE,
 		.pa_end		= AM33XX_WDT1_BASE + SZ_4K - 1,
 		.flags		= ADDR_TYPE_RT
 	},
 	{ }
 };
 /* l4_wkup -> wd_timer1 */
 static struct omap_hwmod_ocp_if am33xx_l4wkup__wd_timer1 = {
 	.master		= &am33xx_l4wkup_hwmod,
 	.slave		= &am33xx_wd_timer1_hwmod,
 	.addr		= am33xx_wd_timer1_addrs,
 	.user		= OCP_USER_MPU,
 };
 /* wd_timer1 slave ports */
 static struct omap_hwmod_ocp_if *am33xx_wd_timer1_slaves[] = {
 	&am33xx_l4wkup__wd_timer1,
 };
 /* wd_timer1 */
 /*
  * TODO: device.c file uses hardcoded name for watchdog
 	 timer driver "wd_timer2, so we are also using
 	 same name as of now...
  */
 static struct omap_hwmod am33xx_wd_timer1_hwmod = {
 	.name		= "wd_timer2",
 	.class		= &am33xx_wd_timer_hwmod_class,
 	.main_clk	= "wdt1_fck",
 	.clkdm_name	= "l4_wkup_clkdm",
 	.prcm		= {
 		.omap4	= {
 			.clkctrl_offs	= AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},
 	.slaves		= am33xx_wd_timer1_slaves,
 	.slaves_cnt	= ARRAY_SIZE(am33xx_wd_timer1_slaves),
 };
 /* 'wkup_m3' class */
 static struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
 	.name		= "wkup_m3",
 };
 /* wkup_m3 */
 static struct omap_hwmod am33xx_wkup_m3_hwmod = {
 	.name		= "wkup_m3",
 	.class		= &am33xx_wkup_m3_hwmod_class,
 	.clkdm_name	= "l4_wkup_aon_clkdm",
 	.main_clk	= "wkup_m3_fck",
 	.prcm		= {
 		.omap4	= {
 			.clkctrl_offs	= AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},
 };
 /* L3 SLOW -> USBSS interface */
 static struct omap_hwmod_addr_space am33xx_usbss_addr_space[] = {
 	{
 		.name		= "usbss",
 		.pa_start	= AM33XX_USBSS_BASE,
 		.pa_end		= AM33XX_USBSS_BASE + SZ_4K - 1,
 		.flags		= ADDR_TYPE_RT
 	},
 	{
 		.name		= "musb0",
 		.pa_start	= AM33XX_USB0_BASE,
 		.pa_end		= AM33XX_USB0_BASE + SZ_2K - 1,
 		.flags		= ADDR_TYPE_RT
 	},
 	{
 		.name		= "musb1",
 		.pa_start	= AM33XX_USB1_BASE,
 		.pa_end		= AM33XX_USB1_BASE + SZ_2K - 1,
 		.flags		= ADDR_TYPE_RT
 	},
 	{ }
 };
 static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = {
 	.rev_offs	= 0x0,
 	.sysc_offs	= 0x10,
 	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 	.sysc_fields	= &omap_hwmod_sysc_type2,
 };
 static struct omap_hwmod_class am33xx_usbotg_class = {
 	.name		= "usbotg",
 	.sysc		= &am33xx_usbhsotg_sysc,
 };
 static struct omap_hwmod_irq_info am33xx_usbss_mpu_irqs[] = {
 	{ .name = "usbss-irq", .irq = AM33XX_IRQ_USBSS, },
 	{ .name = "musb0-irq", .irq = AM33XX_IRQ_USB0, },
 	{ .name = "musb1-irq", .irq = AM33XX_IRQ_USB1, },
 	{ .irq = -1, },
 };
 static struct omap_hwmod_ocp_if am33xx_l3_slow__usbss = {
 	.master		= &am33xx_l3slow_hwmod,
 	.slave		= &am33xx_usbss_hwmod,
 	.addr		= am33xx_usbss_addr_space,
 	.user		= OCP_USER_MPU,
 	.flags		= OCPIF_SWSUP_IDLE,
 };
 static struct omap_hwmod_ocp_if *am33xx_usbss_slaves[] = {
 	&am33xx_l3_slow__usbss,
 };
 static struct omap_hwmod_opt_clk usbss_opt_clks[] = {
 	{ .role = "clkdcoldo", .clk = "usbotg_fck" },
 };
 static struct omap_hwmod am33xx_usbss_hwmod = {
 	.name		= "usb_otg_hs",
 	.mpu_irqs	= am33xx_usbss_mpu_irqs,
 	.main_clk	= "usbotg_ick",
 	.clkdm_name	= "l4ls_clkdm",
 	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 	.prcm		= {
 		.omap4	= {
 			.clkctrl_offs	= AM33XX_CM_PER_USB0_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},
 	.opt_clks	= usbss_opt_clks,
 	.opt_clks_cnt	= ARRAY_SIZE(usbss_opt_clks),
 	.slaves		= am33xx_usbss_slaves,
 	.slaves_cnt	= ARRAY_SIZE(am33xx_usbss_slaves),
 	.class		= &am33xx_usbotg_class,
 };
 /* sgx/gfx */
 /* Pseudo hwmod for reset control purpose only */
 static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
 	.name   = "gfx",
 };
 static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
 	{ .name = "gfx", .rst_shift = 0, .st_shift = 0 },
 };
 static struct omap_hwmod am33xx_gfx_hwmod = {
 	.name           = "gfx",
 	.class          = &am33xx_gfx_hwmod_class,
 	.clkdm_name     = "gfx_l3_clkdm",
 	.rst_lines      = am33xx_gfx_resets,
 	.rst_lines_cnt  = ARRAY_SIZE(am33xx_gfx_resets),
 };
 /* PRUSS/ICSS */
 /* Pseudo hwmod for reset control purpose only */
 static struct omap_hwmod_class am33xx_pruss_hwmod_class = {
 	.name   = "pruss",
 };
 static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
 	{ .name = "pruss", .rst_shift = 1, .st_shift = 1 },
 };
 static struct omap_hwmod am33xx_pruss_hwmod = {
 	.name           = "pruss",
 	.class          = &am33xx_pruss_hwmod_class,
 	.clkdm_name     = "icss_ocp_clkdm",
 	.rst_lines      = am33xx_pruss_resets,
 	.rst_lines_cnt  = ARRAY_SIZE(am33xx_pruss_resets),
 };
 static __initdata struct omap_hwmod *am33xx_hwmods[] = {
 	/* l3 class */
 	&am33xx_l3_instr_hwmod,
 	&am33xx_l3_main_hwmod,
 	/* l3s class */
 	&am33xx_l3slow_hwmod,
 	/* l4hs class */
 	&am33xx_l4_hs_hwmod,
 	/* l4fw class */
 	&am33xx_l4fw_hwmod,
 	/* l4ls class */
 	&am33xx_l4ls_hwmod,
 	/* l4per class */
 	&am33xx_l4per_hwmod,
 	/* l4wkup class */
 	&am33xx_l4wkup_hwmod,
 	/* clkdiv32k class */
 	&am33xx_clkdiv32k_hwmod,
 	/* mpu class */
 	&am33xx_mpu_hwmod,
 	/* adc_tsc class */
 	&am33xx_adc_tsc_hwmod,
 	/* aes class */
 	&am33xx_aes0_hwmod,
 	/* cefuse class */
 	&am33xx_cefuse_hwmod,
 	/* control class */
 	&am33xx_control_hwmod,
 	/* dcan class */
 	&am33xx_dcan0_hwmod,
 	&am33xx_dcan1_hwmod,
 	/* debugss class */
 	&am33xx_debugss_hwmod,
 	/* elm class */
 	&am33xx_elm_hwmod,
 	/* emif_fw class */
 	&am33xx_emif_fw_hwmod,
 	/* epwmss class */
 	&am33xx_epwmss0_hwmod,
 	&am33xx_epwmss1_hwmod,
 	&am33xx_epwmss2_hwmod,
 	/* gpio class */
 	&am33xx_gpio0_hwmod,
 	&am33xx_gpio1_hwmod,
 	&am33xx_gpio2_hwmod,
 	&am33xx_gpio3_hwmod,
 	/* gpmc class */
 	&am33xx_gpmc_hwmod,
 	/* i2c class */
 	&am33xx_i2c1_hwmod,
 	&am33xx_i2c2_hwmod,
 	/* icss class */
 	&am33xx_icss_hwmod,
 	/* ieee5000 class */
 	&am33xx_ieee5000_hwmod,
 	/* mcasp class */
 	&am33xx_mcasp0_hwmod,
 	/* mmc class */
 	&am33xx_mmc0_hwmod,
 	&am33xx_mmc1_hwmod,
 	&am33xx_mmc2_hwmod,
 	/* ocmcram class */
 	&am33xx_ocmcram_hwmod,
 	/* ocpwp class */
 	&am33xx_ocpwp_hwmod,
 	/* sha0 class */
 	&am33xx_sha0_hwmod,
 	/* smartreflex class */
 	&am33xx_smartreflex0_hwmod,
 	&am33xx_smartreflex1_hwmod,
 	/* spi class */
 	&am33xx_spi0_hwmod,
 	&am33xx_spi1_hwmod,
 	/* spinlock class */
 	&am33xx_spinlock_hwmod,
 	/* uart class */
 	&am33xx_uart1_hwmod,
 	&am33xx_uart2_hwmod,
 	&am33xx_uart3_hwmod,
 	&am33xx_uart4_hwmod,
 	&am33xx_uart5_hwmod,
 	&am33xx_uart6_hwmod,
 	/* timer class */
 	&am33xx_timer0_hwmod,
 	&am33xx_timer1_hwmod,
 	&am33xx_timer2_hwmod,
 	&am33xx_timer3_hwmod,
 	&am33xx_timer4_hwmod,
 	&am33xx_timer5_hwmod,
 	&am33xx_timer6_hwmod,
 	&am33xx_timer7_hwmod,
 	/* wkup_m3 class */
 	&am33xx_wkup_m3_hwmod,
 	/* wd_timer class */
 	&am33xx_wd_timer1_hwmod,
 	/* usbss hwmod */
 	&am33xx_usbss_hwmod,
 	/* cpgmac0 class */
 	&am33xx_cpgmac0_hwmod,
 	/* tptc class */
 	&am33xx_tptc0_hwmod,
 	&am33xx_tptc1_hwmod,
 	&am33xx_tptc2_hwmod,
 	/* tpcc class */
 	&am33xx_tpcc_hwmod,
 	/* LCDC class */
 	&am33xx_lcdc_hwmod,
 	/* gfx/sgx */
 	&am33xx_gfx_hwmod,
 	/* pruss/icss */
 	&am33xx_pruss_hwmod,
 	/* rtc */
 	&am33xx_rtc_hwmod,
 	NULL,
 };
 int __init am33xx_hwmod_init(void)
 {
 	return omap_hwmod_register(am33xx_hwmods);
 }