Eric Lee / linux-smarc-t335x-v3.2

Commit 950d0a10d12578a270f3dfa9fd76fe5c2deb343f

Authored by Linus Torvalds 2011-08-18 01:23:50 +0800

Exists in master and in 4 other branches

Merge branch 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel…

…/git/tip/linux-2.6-tip

* 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip:
  irq: Track the owner of irq descriptor
  irq: Always set IRQF_ONESHOT if no primary handler is specified
  genirq: Fix wrong bit operation

Showing 5 changed files Inline Diff

include/linux/irq.h
include/linux/irqdesc.h
kernel/irq/generic-chip.c
kernel/irq/irqdesc.c
kernel/irq/manage.c

include/linux/irq.h

Diff comments View file @ 950d0a1

 #ifndef _LINUX_IRQ_H
 #define _LINUX_IRQ_H
 /*
  * Please do not include this file in generic code.  There is currently
  * no requirement for any architecture to implement anything held
  * within this file.
  *
  * Thanks. --rmk
  */
 #include <linux/smp.h>
 #ifndef CONFIG_S390
 #include <linux/linkage.h>
 #include <linux/cache.h>
 #include <linux/spinlock.h>
 #include <linux/cpumask.h>
 #include <linux/gfp.h>
 #include <linux/irqreturn.h>
 #include <linux/irqnr.h>
 #include <linux/errno.h>
 #include <linux/topology.h>
 #include <linux/wait.h>
+#include <linux/module.h>
 #include <asm/irq.h>
 #include <asm/ptrace.h>
 #include <asm/irq_regs.h>
 struct seq_file;
 struct irq_desc;
 struct irq_data;
 typedef	void (*irq_flow_handler_t)(unsigned int irq,
 					    struct irq_desc *desc);
 typedef	void (*irq_preflow_handler_t)(struct irq_data *data);
 /*
  * IRQ line status.
  *
  * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h
  *
  * IRQ_TYPE_NONE		- default, unspecified type
  * IRQ_TYPE_EDGE_RISING		- rising edge triggered
  * IRQ_TYPE_EDGE_FALLING	- falling edge triggered
  * IRQ_TYPE_EDGE_BOTH		- rising and falling edge triggered
  * IRQ_TYPE_LEVEL_HIGH		- high level triggered
  * IRQ_TYPE_LEVEL_LOW		- low level triggered
  * IRQ_TYPE_LEVEL_MASK		- Mask to filter out the level bits
  * IRQ_TYPE_SENSE_MASK		- Mask for all the above bits
  * IRQ_TYPE_PROBE		- Special flag for probing in progress
  *
  * Bits which can be modified via irq_set/clear/modify_status_flags()
  * IRQ_LEVEL			- Interrupt is level type. Will be also
  *				  updated in the code when the above trigger
  *				  bits are modified via irq_set_irq_type()
  * IRQ_PER_CPU			- Mark an interrupt PER_CPU. Will protect
  *				  it from affinity setting
  * IRQ_NOPROBE			- Interrupt cannot be probed by autoprobing
  * IRQ_NOREQUEST		- Interrupt cannot be requested via
  *				  request_irq()
  * IRQ_NOTHREAD			- Interrupt cannot be threaded
  * IRQ_NOAUTOEN			- Interrupt is not automatically enabled in
  *				  request/setup_irq()
  * IRQ_NO_BALANCING		- Interrupt cannot be balanced (affinity set)
  * IRQ_MOVE_PCNTXT		- Interrupt can be migrated from process context
  * IRQ_NESTED_TRHEAD		- Interrupt nests into another thread
  */
 enum {
 	IRQ_TYPE_NONE		= 0x00000000,
 	IRQ_TYPE_EDGE_RISING	= 0x00000001,
 	IRQ_TYPE_EDGE_FALLING	= 0x00000002,
 	IRQ_TYPE_EDGE_BOTH	= (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING),
 	IRQ_TYPE_LEVEL_HIGH	= 0x00000004,
 	IRQ_TYPE_LEVEL_LOW	= 0x00000008,
 	IRQ_TYPE_LEVEL_MASK	= (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH),
 	IRQ_TYPE_SENSE_MASK	= 0x0000000f,
 	IRQ_TYPE_PROBE		= 0x00000010,
 	IRQ_LEVEL		= (1 <<  8),
 	IRQ_PER_CPU		= (1 <<  9),
 	IRQ_NOPROBE		= (1 << 10),
 	IRQ_NOREQUEST		= (1 << 11),
 	IRQ_NOAUTOEN		= (1 << 12),
 	IRQ_NO_BALANCING	= (1 << 13),
 	IRQ_MOVE_PCNTXT		= (1 << 14),
 	IRQ_NESTED_THREAD	= (1 << 15),
 	IRQ_NOTHREAD		= (1 << 16),
 };
 #define IRQF_MODIFY_MASK	\
 	(IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \
 	 IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \
 	 IRQ_PER_CPU | IRQ_NESTED_THREAD)
 #define IRQ_NO_BALANCING_MASK	(IRQ_PER_CPU | IRQ_NO_BALANCING)
 /*
  * Return value for chip->irq_set_affinity()
  *
  * IRQ_SET_MASK_OK	- OK, core updates irq_data.affinity
  * IRQ_SET_MASK_NOCPY	- OK, chip did update irq_data.affinity
  */
 enum {
 	IRQ_SET_MASK_OK = 0,
 	IRQ_SET_MASK_OK_NOCOPY,
 };
 struct msi_desc;
 struct irq_domain;
 /**
  * struct irq_data - per irq and irq chip data passed down to chip functions
  * @irq:		interrupt number
  * @hwirq:		hardware interrupt number, local to the interrupt domain
  * @node:		node index useful for balancing
  * @state_use_accessors: status information for irq chip functions.
  *			Use accessor functions to deal with it
  * @chip:		low level interrupt hardware access
  * @domain:		Interrupt translation domain; responsible for mapping
  *			between hwirq number and linux irq number.
  * @handler_data:	per-IRQ data for the irq_chip methods
  * @chip_data:		platform-specific per-chip private data for the chip
  *			methods, to allow shared chip implementations
  * @msi_desc:		MSI descriptor
  * @affinity:		IRQ affinity on SMP
  *
  * The fields here need to overlay the ones in irq_desc until we
  * cleaned up the direct references and switched everything over to
  * irq_data.
  */
 struct irq_data {
 	unsigned int		irq;
 	unsigned long		hwirq;
 	unsigned int		node;
 	unsigned int		state_use_accessors;
 	struct irq_chip		*chip;
 	struct irq_domain	*domain;
 	void			*handler_data;
 	void			*chip_data;
 	struct msi_desc		*msi_desc;
 #ifdef CONFIG_SMP
 	cpumask_var_t		affinity;
 #endif
 };
 /*
  * Bit masks for irq_data.state
  *
  * IRQD_TRIGGER_MASK		- Mask for the trigger type bits
  * IRQD_SETAFFINITY_PENDING	- Affinity setting is pending
  * IRQD_NO_BALANCING		- Balancing disabled for this IRQ
  * IRQD_PER_CPU			- Interrupt is per cpu
  * IRQD_AFFINITY_SET		- Interrupt affinity was set
  * IRQD_LEVEL			- Interrupt is level triggered
  * IRQD_WAKEUP_STATE		- Interrupt is configured for wakeup
  *				  from suspend
  * IRDQ_MOVE_PCNTXT		- Interrupt can be moved in process
  *				  context
  * IRQD_IRQ_DISABLED		- Disabled state of the interrupt
  * IRQD_IRQ_MASKED		- Masked state of the interrupt
  * IRQD_IRQ_INPROGRESS		- In progress state of the interrupt
  */
 enum {
 	IRQD_TRIGGER_MASK		= 0xf,
 	IRQD_SETAFFINITY_PENDING	= (1 <<  8),
 	IRQD_NO_BALANCING		= (1 << 10),
 	IRQD_PER_CPU			= (1 << 11),
 	IRQD_AFFINITY_SET		= (1 << 12),
 	IRQD_LEVEL			= (1 << 13),
 	IRQD_WAKEUP_STATE		= (1 << 14),
 	IRQD_MOVE_PCNTXT		= (1 << 15),
 	IRQD_IRQ_DISABLED		= (1 << 16),
 	IRQD_IRQ_MASKED			= (1 << 17),
 	IRQD_IRQ_INPROGRESS		= (1 << 18),
 };
 static inline bool irqd_is_setaffinity_pending(struct irq_data *d)
 {
 	return d->state_use_accessors & IRQD_SETAFFINITY_PENDING;
 }
 static inline bool irqd_is_per_cpu(struct irq_data *d)
 {
 	return d->state_use_accessors & IRQD_PER_CPU;
 }
 static inline bool irqd_can_balance(struct irq_data *d)
 {
 	return !(d->state_use_accessors & (IRQD_PER_CPU | IRQD_NO_BALANCING));
 }
 static inline bool irqd_affinity_was_set(struct irq_data *d)
 {
 	return d->state_use_accessors & IRQD_AFFINITY_SET;
 }
 static inline void irqd_mark_affinity_was_set(struct irq_data *d)
 {
 	d->state_use_accessors |= IRQD_AFFINITY_SET;
 }
 static inline u32 irqd_get_trigger_type(struct irq_data *d)
 {
 	return d->state_use_accessors & IRQD_TRIGGER_MASK;
 }
 /*
  * Must only be called inside irq_chip.irq_set_type() functions.
  */
 static inline void irqd_set_trigger_type(struct irq_data *d, u32 type)
 {
 	d->state_use_accessors &= ~IRQD_TRIGGER_MASK;
 	d->state_use_accessors |= type & IRQD_TRIGGER_MASK;
 }
 static inline bool irqd_is_level_type(struct irq_data *d)
 {
 	return d->state_use_accessors & IRQD_LEVEL;
 }
 static inline bool irqd_is_wakeup_set(struct irq_data *d)
 {
 	return d->state_use_accessors & IRQD_WAKEUP_STATE;
 }
 static inline bool irqd_can_move_in_process_context(struct irq_data *d)
 {
 	return d->state_use_accessors & IRQD_MOVE_PCNTXT;
 }
 static inline bool irqd_irq_disabled(struct irq_data *d)
 {
 	return d->state_use_accessors & IRQD_IRQ_DISABLED;
 }
 static inline bool irqd_irq_masked(struct irq_data *d)
 {
 	return d->state_use_accessors & IRQD_IRQ_MASKED;
 }
 static inline bool irqd_irq_inprogress(struct irq_data *d)
 {
 	return d->state_use_accessors & IRQD_IRQ_INPROGRESS;
 }
 /*
  * Functions for chained handlers which can be enabled/disabled by the
  * standard disable_irq/enable_irq calls. Must be called with
  * irq_desc->lock held.
  */
 static inline void irqd_set_chained_irq_inprogress(struct irq_data *d)
 {
 	d->state_use_accessors |= IRQD_IRQ_INPROGRESS;
 }
 static inline void irqd_clr_chained_irq_inprogress(struct irq_data *d)
 {
 	d->state_use_accessors &= ~IRQD_IRQ_INPROGRESS;
 }
 /**
  * struct irq_chip - hardware interrupt chip descriptor
  *
  * @name:		name for /proc/interrupts
  * @irq_startup:	start up the interrupt (defaults to ->enable if NULL)
  * @irq_shutdown:	shut down the interrupt (defaults to ->disable if NULL)
  * @irq_enable:		enable the interrupt (defaults to chip->unmask if NULL)
  * @irq_disable:	disable the interrupt
  * @irq_ack:		start of a new interrupt
  * @irq_mask:		mask an interrupt source
  * @irq_mask_ack:	ack and mask an interrupt source
  * @irq_unmask:		unmask an interrupt source
  * @irq_eoi:		end of interrupt
  * @irq_set_affinity:	set the CPU affinity on SMP machines
  * @irq_retrigger:	resend an IRQ to the CPU
  * @irq_set_type:	set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ
  * @irq_set_wake:	enable/disable power-management wake-on of an IRQ
  * @irq_bus_lock:	function to lock access to slow bus (i2c) chips
  * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips
  * @irq_cpu_online:	configure an interrupt source for a secondary CPU
  * @irq_cpu_offline:	un-configure an interrupt source for a secondary CPU
  * @irq_suspend:	function called from core code on suspend once per chip
  * @irq_resume:		function called from core code on resume once per chip
  * @irq_pm_shutdown:	function called from core code on shutdown once per chip
  * @irq_print_chip:	optional to print special chip info in show_interrupts
  * @flags:		chip specific flags
  *
  * @release:		release function solely used by UML
  */
 struct irq_chip {
 	const char	*name;
 	unsigned int	(*irq_startup)(struct irq_data *data);
 	void		(*irq_shutdown)(struct irq_data *data);
 	void		(*irq_enable)(struct irq_data *data);
 	void		(*irq_disable)(struct irq_data *data);
 	void		(*irq_ack)(struct irq_data *data);
 	void		(*irq_mask)(struct irq_data *data);
 	void		(*irq_mask_ack)(struct irq_data *data);
 	void		(*irq_unmask)(struct irq_data *data);
 	void		(*irq_eoi)(struct irq_data *data);
 	int		(*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force);
 	int		(*irq_retrigger)(struct irq_data *data);
 	int		(*irq_set_type)(struct irq_data *data, unsigned int flow_type);
 	int		(*irq_set_wake)(struct irq_data *data, unsigned int on);
 	void		(*irq_bus_lock)(struct irq_data *data);
 	void		(*irq_bus_sync_unlock)(struct irq_data *data);
 	void		(*irq_cpu_online)(struct irq_data *data);
 	void		(*irq_cpu_offline)(struct irq_data *data);
 	void		(*irq_suspend)(struct irq_data *data);
 	void		(*irq_resume)(struct irq_data *data);
 	void		(*irq_pm_shutdown)(struct irq_data *data);
 	void		(*irq_print_chip)(struct irq_data *data, struct seq_file *p);
 	unsigned long	flags;
 	/* Currently used only by UML, might disappear one day.*/
 #ifdef CONFIG_IRQ_RELEASE_METHOD
 	void		(*release)(unsigned int irq, void *dev_id);
 #endif
 };
 /*
  * irq_chip specific flags
  *
  * IRQCHIP_SET_TYPE_MASKED:	Mask before calling chip.irq_set_type()
  * IRQCHIP_EOI_IF_HANDLED:	Only issue irq_eoi() when irq was handled
  * IRQCHIP_MASK_ON_SUSPEND:	Mask non wake irqs in the suspend path
  * IRQCHIP_ONOFFLINE_ENABLED:	Only call irq_on/off_line callbacks
  *				when irq enabled
  */
 enum {
 	IRQCHIP_SET_TYPE_MASKED		= (1 <<  0),
 	IRQCHIP_EOI_IF_HANDLED		= (1 <<  1),
 	IRQCHIP_MASK_ON_SUSPEND		= (1 <<  2),
 	IRQCHIP_ONOFFLINE_ENABLED	= (1 <<  3),
 };
 /* This include will go away once we isolated irq_desc usage to core code */
 #include <linux/irqdesc.h>
 /*
  * Pick up the arch-dependent methods:
  */
 #include <asm/hw_irq.h>
 #ifndef NR_IRQS_LEGACY
 # define NR_IRQS_LEGACY 0
 #endif
 #ifndef ARCH_IRQ_INIT_FLAGS
 # define ARCH_IRQ_INIT_FLAGS	0
 #endif
 #define IRQ_DEFAULT_INIT_FLAGS	ARCH_IRQ_INIT_FLAGS
 struct irqaction;
 extern int setup_irq(unsigned int irq, struct irqaction *new);
 extern void remove_irq(unsigned int irq, struct irqaction *act);
 extern void irq_cpu_online(void);
 extern void irq_cpu_offline(void);
 extern int __irq_set_affinity_locked(struct irq_data *data,  const struct cpumask *cpumask);
 #ifdef CONFIG_GENERIC_HARDIRQS
 #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ)
 void irq_move_irq(struct irq_data *data);
 void irq_move_masked_irq(struct irq_data *data);
 #else
 static inline void irq_move_irq(struct irq_data *data) { }
 static inline void irq_move_masked_irq(struct irq_data *data) { }
 #endif
 extern int no_irq_affinity;
 /*
  * Built-in IRQ handlers for various IRQ types,
  * callable via desc->handle_irq()
  */
 extern void handle_level_irq(unsigned int irq, struct irq_desc *desc);
 extern void handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc);
 extern void handle_edge_irq(unsigned int irq, struct irq_desc *desc);
 extern void handle_edge_eoi_irq(unsigned int irq, struct irq_desc *desc);
 extern void handle_simple_irq(unsigned int irq, struct irq_desc *desc);
 extern void handle_percpu_irq(unsigned int irq, struct irq_desc *desc);
 extern void handle_bad_irq(unsigned int irq, struct irq_desc *desc);
 extern void handle_nested_irq(unsigned int irq);
 /* Handling of unhandled and spurious interrupts: */
 extern void note_interrupt(unsigned int irq, struct irq_desc *desc,
 			   irqreturn_t action_ret);
 /* Enable/disable irq debugging output: */
 extern int noirqdebug_setup(char *str);
 /* Checks whether the interrupt can be requested by request_irq(): */
 extern int can_request_irq(unsigned int irq, unsigned long irqflags);
 /* Dummy irq-chip implementations: */
 extern struct irq_chip no_irq_chip;
 extern struct irq_chip dummy_irq_chip;
 extern void
 irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip,
 			      irq_flow_handler_t handle, const char *name);
 static inline void irq_set_chip_and_handler(unsigned int irq, struct irq_chip *chip,
 					    irq_flow_handler_t handle)
 {
 	irq_set_chip_and_handler_name(irq, chip, handle, NULL);
 }
 extern void
 __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained,
 		  const char *name);
 static inline void
 irq_set_handler(unsigned int irq, irq_flow_handler_t handle)
 {
 	__irq_set_handler(irq, handle, 0, NULL);
 }
 /*
  * Set a highlevel chained flow handler for a given IRQ.
  * (a chained handler is automatically enabled and set to
  *  IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD)
  */
 static inline void
 irq_set_chained_handler(unsigned int irq, irq_flow_handler_t handle)
 {
 	__irq_set_handler(irq, handle, 1, NULL);
 }
 void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set);
 static inline void irq_set_status_flags(unsigned int irq, unsigned long set)
 {
 	irq_modify_status(irq, 0, set);
 }
 static inline void irq_clear_status_flags(unsigned int irq, unsigned long clr)
 {
 	irq_modify_status(irq, clr, 0);
 }
 static inline void irq_set_noprobe(unsigned int irq)
 {
 	irq_modify_status(irq, 0, IRQ_NOPROBE);
 }
 static inline void irq_set_probe(unsigned int irq)
 {
 	irq_modify_status(irq, IRQ_NOPROBE, 0);
 }
 static inline void irq_set_nothread(unsigned int irq)
 {
 	irq_modify_status(irq, 0, IRQ_NOTHREAD);
 }
 static inline void irq_set_thread(unsigned int irq)
 {
 	irq_modify_status(irq, IRQ_NOTHREAD, 0);
 }
 static inline void irq_set_nested_thread(unsigned int irq, bool nest)
 {
 	if (nest)
 		irq_set_status_flags(irq, IRQ_NESTED_THREAD);
 	else
 		irq_clear_status_flags(irq, IRQ_NESTED_THREAD);
 }
 /* Handle dynamic irq creation and destruction */
 extern unsigned int create_irq_nr(unsigned int irq_want, int node);
 extern int create_irq(void);
 extern void destroy_irq(unsigned int irq);
 /*
  * Dynamic irq helper functions. Obsolete. Use irq_alloc_desc* and
  * irq_free_desc instead.
  */
 extern void dynamic_irq_cleanup(unsigned int irq);
 static inline void dynamic_irq_init(unsigned int irq)
 {
 	dynamic_irq_cleanup(irq);
 }
 /* Set/get chip/data for an IRQ: */
 extern int irq_set_chip(unsigned int irq, struct irq_chip *chip);
 extern int irq_set_handler_data(unsigned int irq, void *data);
 extern int irq_set_chip_data(unsigned int irq, void *data);
 extern int irq_set_irq_type(unsigned int irq, unsigned int type);
 extern int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry);
 extern struct irq_data *irq_get_irq_data(unsigned int irq);
 static inline struct irq_chip *irq_get_chip(unsigned int irq)
 {
 	struct irq_data *d = irq_get_irq_data(irq);
 	return d ? d->chip : NULL;
 }
 static inline struct irq_chip *irq_data_get_irq_chip(struct irq_data *d)
 {
 	return d->chip;
 }
 static inline void *irq_get_chip_data(unsigned int irq)
 {
 	struct irq_data *d = irq_get_irq_data(irq);
 	return d ? d->chip_data : NULL;
 }
 static inline void *irq_data_get_irq_chip_data(struct irq_data *d)
 {
 	return d->chip_data;
 }
 static inline void *irq_get_handler_data(unsigned int irq)
 {
 	struct irq_data *d = irq_get_irq_data(irq);
 	return d ? d->handler_data : NULL;
 }
 static inline void *irq_data_get_irq_handler_data(struct irq_data *d)
 {
 	return d->handler_data;
 }
 static inline struct msi_desc *irq_get_msi_desc(unsigned int irq)
 {
 	struct irq_data *d = irq_get_irq_data(irq);
 	return d ? d->msi_desc : NULL;
 }
 static inline struct msi_desc *irq_data_get_msi(struct irq_data *d)
 {
 	return d->msi_desc;
 }
-int irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node);
+int __irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node,
+		struct module *owner);
+static inline int irq_alloc_descs(int irq, unsigned int from, unsigned int cnt,
+		int node)
+{
+	return __irq_alloc_descs(irq, from, cnt, node, THIS_MODULE);
+}
 void irq_free_descs(unsigned int irq, unsigned int cnt);
 int irq_reserve_irqs(unsigned int from, unsigned int cnt);
 static inline int irq_alloc_desc(int node)
 {
 	return irq_alloc_descs(-1, 0, 1, node);
 }
 static inline int irq_alloc_desc_at(unsigned int at, int node)
 {
 	return irq_alloc_descs(at, at, 1, node);
 }
 static inline int irq_alloc_desc_from(unsigned int from, int node)
 {
 	return irq_alloc_descs(-1, from, 1, node);
 }
 static inline void irq_free_desc(unsigned int irq)
 {
 	irq_free_descs(irq, 1);
 }
 static inline int irq_reserve_irq(unsigned int irq)
 {
 	return irq_reserve_irqs(irq, 1);
 }
 #ifndef irq_reg_writel
 # define irq_reg_writel(val, addr)	writel(val, addr)
 #endif
 #ifndef irq_reg_readl
 # define irq_reg_readl(addr)		readl(addr)
 #endif
 /**
  * struct irq_chip_regs - register offsets for struct irq_gci
  * @enable:	Enable register offset to reg_base
  * @disable:	Disable register offset to reg_base
  * @mask:	Mask register offset to reg_base
  * @ack:	Ack register offset to reg_base
  * @eoi:	Eoi register offset to reg_base
  * @type:	Type configuration register offset to reg_base
  * @polarity:	Polarity configuration register offset to reg_base
  */
 struct irq_chip_regs {
 	unsigned long		enable;
 	unsigned long		disable;
 	unsigned long		mask;
 	unsigned long		ack;
 	unsigned long		eoi;
 	unsigned long		type;
 	unsigned long		polarity;
 };
 /**
  * struct irq_chip_type - Generic interrupt chip instance for a flow type
  * @chip:		The real interrupt chip which provides the callbacks
  * @regs:		Register offsets for this chip
  * @handler:		Flow handler associated with this chip
  * @type:		Chip can handle these flow types
  *
  * A irq_generic_chip can have several instances of irq_chip_type when
  * it requires different functions and register offsets for different
  * flow types.
  */
 struct irq_chip_type {
 	struct irq_chip		chip;
 	struct irq_chip_regs	regs;
 	irq_flow_handler_t	handler;
 	u32			type;
 };
 /**
  * struct irq_chip_generic - Generic irq chip data structure
  * @lock:		Lock to protect register and cache data access
  * @reg_base:		Register base address (virtual)
  * @irq_base:		Interrupt base nr for this chip
  * @irq_cnt:		Number of interrupts handled by this chip
  * @mask_cache:		Cached mask register
  * @type_cache:		Cached type register
  * @polarity_cache:	Cached polarity register
  * @wake_enabled:	Interrupt can wakeup from suspend
  * @wake_active:	Interrupt is marked as an wakeup from suspend source
  * @num_ct:		Number of available irq_chip_type instances (usually 1)
  * @private:		Private data for non generic chip callbacks
  * @list:		List head for keeping track of instances
  * @chip_types:		Array of interrupt irq_chip_types
  *
  * Note, that irq_chip_generic can have multiple irq_chip_type
  * implementations which can be associated to a particular irq line of
  * an irq_chip_generic instance. That allows to share and protect
  * state in an irq_chip_generic instance when we need to implement
  * different flow mechanisms (level/edge) for it.
  */
 struct irq_chip_generic {
 	raw_spinlock_t		lock;
 	void __iomem		*reg_base;
 	unsigned int		irq_base;
 	unsigned int		irq_cnt;
 	u32			mask_cache;
 	u32			type_cache;
 	u32			polarity_cache;
 	u32			wake_enabled;
 	u32			wake_active;
 	unsigned int		num_ct;
 	void			*private;
 	struct list_head	list;
 	struct irq_chip_type	chip_types[0];
 };
 /**
  * enum irq_gc_flags - Initialization flags for generic irq chips
  * @IRQ_GC_INIT_MASK_CACHE:	Initialize the mask_cache by reading mask reg
  * @IRQ_GC_INIT_NESTED_LOCK:	Set the lock class of the irqs to nested for
  *				irq chips which need to call irq_set_wake() on
  *				the parent irq. Usually GPIO implementations
  */
 enum irq_gc_flags {
 	IRQ_GC_INIT_MASK_CACHE		= 1 << 0,
 	IRQ_GC_INIT_NESTED_LOCK		= 1 << 1,
 };
 /* Generic chip callback functions */
 void irq_gc_noop(struct irq_data *d);
 void irq_gc_mask_disable_reg(struct irq_data *d);
 void irq_gc_mask_set_bit(struct irq_data *d);
 void irq_gc_mask_clr_bit(struct irq_data *d);
 void irq_gc_unmask_enable_reg(struct irq_data *d);
 void irq_gc_ack_set_bit(struct irq_data *d);
 void irq_gc_ack_clr_bit(struct irq_data *d);
 void irq_gc_mask_disable_reg_and_ack(struct irq_data *d);
 void irq_gc_eoi(struct irq_data *d);
 int irq_gc_set_wake(struct irq_data *d, unsigned int on);
 /* Setup functions for irq_chip_generic */
 struct irq_chip_generic *
 irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base,
 		       void __iomem *reg_base, irq_flow_handler_t handler);
 void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk,
 			    enum irq_gc_flags flags, unsigned int clr,
 			    unsigned int set);
 int irq_setup_alt_chip(struct irq_data *d, unsigned int type);
 void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk,
 			     unsigned int clr, unsigned int set);
 static inline struct irq_chip_type *irq_data_get_chip_type(struct irq_data *d)
 {
 	return container_of(d->chip, struct irq_chip_type, chip);
 }
 #define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX)
 #ifdef CONFIG_SMP
 static inline void irq_gc_lock(struct irq_chip_generic *gc)
 {
 	raw_spin_lock(&gc->lock);
 }
 static inline void irq_gc_unlock(struct irq_chip_generic *gc)
 {
 	raw_spin_unlock(&gc->lock);
 }
 #else
 static inline void irq_gc_lock(struct irq_chip_generic *gc) { }
 static inline void irq_gc_unlock(struct irq_chip_generic *gc) { }
 #endif
 #endif /* CONFIG_GENERIC_HARDIRQS */
 #endif /* !CONFIG_S390 */
 #endif /* _LINUX_IRQ_H */

include/linux/irqdesc.h

Diff comments View file @ 950d0a1

 #ifndef _LINUX_IRQDESC_H
 #define _LINUX_IRQDESC_H
 /*
  * Core internal functions to deal with irq descriptors
  *
  * This include will move to kernel/irq once we cleaned up the tree.
  * For now it's included from <linux/irq.h>
  */
 struct irq_affinity_notify;
 struct proc_dir_entry;
 struct timer_rand_state;
 /**
  * struct irq_desc - interrupt descriptor
  * @irq_data:		per irq and chip data passed down to chip functions
  * @timer_rand_state:	pointer to timer rand state struct
  * @kstat_irqs:		irq stats per cpu
  * @handle_irq:		highlevel irq-events handler
  * @preflow_handler:	handler called before the flow handler (currently used by sparc)
  * @action:		the irq action chain
  * @status:		status information
  * @core_internal_state__do_not_mess_with_it: core internal status information
  * @depth:		disable-depth, for nested irq_disable() calls
  * @wake_depth:		enable depth, for multiple irq_set_irq_wake() callers
  * @irq_count:		stats field to detect stalled irqs
  * @last_unhandled:	aging timer for unhandled count
  * @irqs_unhandled:	stats field for spurious unhandled interrupts
  * @lock:		locking for SMP
  * @affinity_hint:	hint to user space for preferred irq affinity
  * @affinity_notify:	context for notification of affinity changes
  * @pending_mask:	pending rebalanced interrupts
  * @threads_oneshot:	bitfield to handle shared oneshot threads
  * @threads_active:	number of irqaction threads currently running
  * @wait_for_threads:	wait queue for sync_irq to wait for threaded handlers
  * @dir:		/proc/irq/ procfs entry
  * @name:		flow handler name for /proc/interrupts output
  */
 struct irq_desc {
 	struct irq_data		irq_data;
 	struct timer_rand_state *timer_rand_state;
 	unsigned int __percpu	*kstat_irqs;
 	irq_flow_handler_t	handle_irq;
 #ifdef CONFIG_IRQ_PREFLOW_FASTEOI
 	irq_preflow_handler_t	preflow_handler;
 #endif
 	struct irqaction	*action;	/* IRQ action list */
 	unsigned int		status_use_accessors;
 	unsigned int		core_internal_state__do_not_mess_with_it;
 	unsigned int		depth;		/* nested irq disables */
 	unsigned int		wake_depth;	/* nested wake enables */
 	unsigned int		irq_count;	/* For detecting broken IRQs */
 	unsigned long		last_unhandled;	/* Aging timer for unhandled count */
 	unsigned int		irqs_unhandled;
 	raw_spinlock_t		lock;
 #ifdef CONFIG_SMP
 	const struct cpumask	*affinity_hint;
 	struct irq_affinity_notify *affinity_notify;
 #ifdef CONFIG_GENERIC_PENDING_IRQ
 	cpumask_var_t		pending_mask;
 #endif
 #endif
 	unsigned long		threads_oneshot;
 	atomic_t		threads_active;
 	wait_queue_head_t       wait_for_threads;
 #ifdef CONFIG_PROC_FS
 	struct proc_dir_entry	*dir;
 #endif
+	struct module		*owner;
 	const char		*name;
 } ____cacheline_internodealigned_in_smp;
 #ifndef CONFIG_SPARSE_IRQ
 extern struct irq_desc irq_desc[NR_IRQS];
 #endif
 #ifdef CONFIG_GENERIC_HARDIRQS
 static inline struct irq_data *irq_desc_get_irq_data(struct irq_desc *desc)
 {
 	return &desc->irq_data;
 }
 static inline struct irq_chip *irq_desc_get_chip(struct irq_desc *desc)
 {
 	return desc->irq_data.chip;
 }
 static inline void *irq_desc_get_chip_data(struct irq_desc *desc)
 {
 	return desc->irq_data.chip_data;
 }
 static inline void *irq_desc_get_handler_data(struct irq_desc *desc)
 {
 	return desc->irq_data.handler_data;
 }
 static inline struct msi_desc *irq_desc_get_msi_desc(struct irq_desc *desc)
 {
 	return desc->irq_data.msi_desc;
 }
 /*
  * Architectures call this to let the generic IRQ layer
  * handle an interrupt. If the descriptor is attached to an
  * irqchip-style controller then we call the ->handle_irq() handler,
  * and it calls __do_IRQ() if it's attached to an irqtype-style controller.
  */
 static inline void generic_handle_irq_desc(unsigned int irq, struct irq_desc *desc)
 {
 	desc->handle_irq(irq, desc);
 }
 int generic_handle_irq(unsigned int irq);
 /* Test to see if a driver has successfully requested an irq */
 static inline int irq_has_action(unsigned int irq)
 {
 	struct irq_desc *desc = irq_to_desc(irq);
 	return desc->action != NULL;
 }
 /* caller has locked the irq_desc and both params are valid */
 static inline void __irq_set_handler_locked(unsigned int irq,
 					    irq_flow_handler_t handler)
 {
 	struct irq_desc *desc;
 	desc = irq_to_desc(irq);
 	desc->handle_irq = handler;
 }
 /* caller has locked the irq_desc and both params are valid */
 static inline void
 __irq_set_chip_handler_name_locked(unsigned int irq, struct irq_chip *chip,
 				   irq_flow_handler_t handler, const char *name)
 {
 	struct irq_desc *desc;
 	desc = irq_to_desc(irq);
 	irq_desc_get_irq_data(desc)->chip = chip;
 	desc->handle_irq = handler;
 	desc->name = name;
 }
 static inline int irq_balancing_disabled(unsigned int irq)
 {
 	struct irq_desc *desc;
 	desc = irq_to_desc(irq);
 	return desc->status_use_accessors & IRQ_NO_BALANCING_MASK;
 }
 static inline void
 irq_set_lockdep_class(unsigned int irq, struct lock_class_key *class)
 {
 	struct irq_desc *desc = irq_to_desc(irq);
 	if (desc)
 		lockdep_set_class(&desc->lock, class);
 }
 #ifdef CONFIG_IRQ_PREFLOW_FASTEOI
 static inline void
 __irq_set_preflow_handler(unsigned int irq, irq_preflow_handler_t handler)
 {
 	struct irq_desc *desc;
 	desc = irq_to_desc(irq);
 	desc->preflow_handler = handler;
 }
 #endif
 #endif
 #endif

kernel/irq/generic-chip.c

Diff comments View file @ 950d0a1

1	/*	1	/*
2	* Library implementing the most common irq chip callback functions	2	* Library implementing the most common irq chip callback functions
3	*	3	*
4	* Copyright (C) 2011, Thomas Gleixner	4	* Copyright (C) 2011, Thomas Gleixner
5	*/	5	*/
6	#include <linux/io.h>	6	#include <linux/io.h>
7	#include <linux/irq.h>	7	#include <linux/irq.h>
8	#include <linux/slab.h>	8	#include <linux/slab.h>
9	#include <linux/interrupt.h>	9	#include <linux/interrupt.h>
10	#include <linux/kernel_stat.h>	10	#include <linux/kernel_stat.h>
11	#include <linux/syscore_ops.h>	11	#include <linux/syscore_ops.h>
12		12
13	#include "internals.h"	13	#include "internals.h"
14		14
15	static LIST_HEAD(gc_list);	15	static LIST_HEAD(gc_list);
16	static DEFINE_RAW_SPINLOCK(gc_lock);	16	static DEFINE_RAW_SPINLOCK(gc_lock);
17		17
18	static inline struct irq_chip_regs cur_regs(struct irq_data d)	18	static inline struct irq_chip_regs cur_regs(struct irq_data d)
19	{	19	{
20	return &container_of(d->chip, struct irq_chip_type, chip)->regs;	20	return &container_of(d->chip, struct irq_chip_type, chip)->regs;
21	}	21	}
22		22
23	/**	23	/**
24	* irq_gc_noop - NOOP function	24	* irq_gc_noop - NOOP function
25	* @d: irq_data	25	* @d: irq_data
26	*/	26	*/
27	void irq_gc_noop(struct irq_data *d)	27	void irq_gc_noop(struct irq_data *d)
28	{	28	{
29	}	29	}
30		30
31	/**	31	/**
32	* irq_gc_mask_disable_reg - Mask chip via disable register	32	* irq_gc_mask_disable_reg - Mask chip via disable register
33	* @d: irq_data	33	* @d: irq_data
34	*	34	*
35	* Chip has separate enable/disable registers instead of a single mask	35	* Chip has separate enable/disable registers instead of a single mask
36	* register.	36	* register.
37	*/	37	*/
38	void irq_gc_mask_disable_reg(struct irq_data *d)	38	void irq_gc_mask_disable_reg(struct irq_data *d)
39	{	39	{
40	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);	40	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
41	u32 mask = 1 << (d->irq - gc->irq_base);	41	u32 mask = 1 << (d->irq - gc->irq_base);
42		42
43	irq_gc_lock(gc);	43	irq_gc_lock(gc);
44	irq_reg_writel(mask, gc->reg_base + cur_regs(d)->disable);	44	irq_reg_writel(mask, gc->reg_base + cur_regs(d)->disable);
45	gc->mask_cache &= ~mask;	45	gc->mask_cache &= ~mask;
46	irq_gc_unlock(gc);	46	irq_gc_unlock(gc);
47	}	47	}
48		48
49	/**	49	/**
50	* irq_gc_mask_set_mask_bit - Mask chip via setting bit in mask register	50	* irq_gc_mask_set_mask_bit - Mask chip via setting bit in mask register
51	* @d: irq_data	51	* @d: irq_data
52	*	52	*
53	* Chip has a single mask register. Values of this register are cached	53	* Chip has a single mask register. Values of this register are cached
54	* and protected by gc->lock	54	* and protected by gc->lock
55	*/	55	*/
56	void irq_gc_mask_set_bit(struct irq_data *d)	56	void irq_gc_mask_set_bit(struct irq_data *d)
57	{	57	{
58	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);	58	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
59	u32 mask = 1 << (d->irq - gc->irq_base);	59	u32 mask = 1 << (d->irq - gc->irq_base);
60		60
61	irq_gc_lock(gc);	61	irq_gc_lock(gc);
62	gc->mask_cache \|= mask;	62	gc->mask_cache \|= mask;
63	irq_reg_writel(gc->mask_cache, gc->reg_base + cur_regs(d)->mask);	63	irq_reg_writel(gc->mask_cache, gc->reg_base + cur_regs(d)->mask);
64	irq_gc_unlock(gc);	64	irq_gc_unlock(gc);
65	}	65	}
66		66
67	/**	67	/**
68	* irq_gc_mask_set_mask_bit - Mask chip via clearing bit in mask register	68	* irq_gc_mask_set_mask_bit - Mask chip via clearing bit in mask register
69	* @d: irq_data	69	* @d: irq_data
70	*	70	*
71	* Chip has a single mask register. Values of this register are cached	71	* Chip has a single mask register. Values of this register are cached
72	* and protected by gc->lock	72	* and protected by gc->lock
73	*/	73	*/
74	void irq_gc_mask_clr_bit(struct irq_data *d)	74	void irq_gc_mask_clr_bit(struct irq_data *d)
75	{	75	{
76	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);	76	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
77	u32 mask = 1 << (d->irq - gc->irq_base);	77	u32 mask = 1 << (d->irq - gc->irq_base);
78		78
79	irq_gc_lock(gc);	79	irq_gc_lock(gc);
80	gc->mask_cache &= ~mask;	80	gc->mask_cache &= ~mask;
81	irq_reg_writel(gc->mask_cache, gc->reg_base + cur_regs(d)->mask);	81	irq_reg_writel(gc->mask_cache, gc->reg_base + cur_regs(d)->mask);
82	irq_gc_unlock(gc);	82	irq_gc_unlock(gc);
83	}	83	}
84		84
85	/**	85	/**
86	* irq_gc_unmask_enable_reg - Unmask chip via enable register	86	* irq_gc_unmask_enable_reg - Unmask chip via enable register
87	* @d: irq_data	87	* @d: irq_data
88	*	88	*
89	* Chip has separate enable/disable registers instead of a single mask	89	* Chip has separate enable/disable registers instead of a single mask
90	* register.	90	* register.
91	*/	91	*/
92	void irq_gc_unmask_enable_reg(struct irq_data *d)	92	void irq_gc_unmask_enable_reg(struct irq_data *d)
93	{	93	{
94	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);	94	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
95	u32 mask = 1 << (d->irq - gc->irq_base);	95	u32 mask = 1 << (d->irq - gc->irq_base);
96		96
97	irq_gc_lock(gc);	97	irq_gc_lock(gc);
98	irq_reg_writel(mask, gc->reg_base + cur_regs(d)->enable);	98	irq_reg_writel(mask, gc->reg_base + cur_regs(d)->enable);
99	gc->mask_cache \|= mask;	99	gc->mask_cache \|= mask;
100	irq_gc_unlock(gc);	100	irq_gc_unlock(gc);
101	}	101	}
102		102
103	/**	103	/**
104	* irq_gc_ack_set_bit - Ack pending interrupt via setting bit	104	* irq_gc_ack_set_bit - Ack pending interrupt via setting bit
105	* @d: irq_data	105	* @d: irq_data
106	*/	106	*/
107	void irq_gc_ack_set_bit(struct irq_data *d)	107	void irq_gc_ack_set_bit(struct irq_data *d)
108	{	108	{
109	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);	109	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
110	u32 mask = 1 << (d->irq - gc->irq_base);	110	u32 mask = 1 << (d->irq - gc->irq_base);
111		111
112	irq_gc_lock(gc);	112	irq_gc_lock(gc);
113	irq_reg_writel(mask, gc->reg_base + cur_regs(d)->ack);	113	irq_reg_writel(mask, gc->reg_base + cur_regs(d)->ack);
114	irq_gc_unlock(gc);	114	irq_gc_unlock(gc);
115	}	115	}
116		116
117	/**	117	/**
118	* irq_gc_ack_clr_bit - Ack pending interrupt via clearing bit	118	* irq_gc_ack_clr_bit - Ack pending interrupt via clearing bit
119	* @d: irq_data	119	* @d: irq_data
120	*/	120	*/
121	void irq_gc_ack_clr_bit(struct irq_data *d)	121	void irq_gc_ack_clr_bit(struct irq_data *d)
122	{	122	{
123	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);	123	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
124	u32 mask = ~(1 << (d->irq - gc->irq_base));	124	u32 mask = ~(1 << (d->irq - gc->irq_base));
125		125
126	irq_gc_lock(gc);	126	irq_gc_lock(gc);
127	irq_reg_writel(mask, gc->reg_base + cur_regs(d)->ack);	127	irq_reg_writel(mask, gc->reg_base + cur_regs(d)->ack);
128	irq_gc_unlock(gc);	128	irq_gc_unlock(gc);
129	}	129	}
130		130
131	/**	131	/**
132	* irq_gc_mask_disable_reg_and_ack- Mask and ack pending interrupt	132	* irq_gc_mask_disable_reg_and_ack- Mask and ack pending interrupt
133	* @d: irq_data	133	* @d: irq_data
134	*/	134	*/
135	void irq_gc_mask_disable_reg_and_ack(struct irq_data *d)	135	void irq_gc_mask_disable_reg_and_ack(struct irq_data *d)
136	{	136	{
137	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);	137	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
138	u32 mask = 1 << (d->irq - gc->irq_base);	138	u32 mask = 1 << (d->irq - gc->irq_base);
139		139
140	irq_gc_lock(gc);	140	irq_gc_lock(gc);
141	irq_reg_writel(mask, gc->reg_base + cur_regs(d)->mask);	141	irq_reg_writel(mask, gc->reg_base + cur_regs(d)->mask);
142	irq_reg_writel(mask, gc->reg_base + cur_regs(d)->ack);	142	irq_reg_writel(mask, gc->reg_base + cur_regs(d)->ack);
143	irq_gc_unlock(gc);	143	irq_gc_unlock(gc);
144	}	144	}
145		145
146	/**	146	/**
147	* irq_gc_eoi - EOI interrupt	147	* irq_gc_eoi - EOI interrupt
148	* @d: irq_data	148	* @d: irq_data
149	*/	149	*/
150	void irq_gc_eoi(struct irq_data *d)	150	void irq_gc_eoi(struct irq_data *d)
151	{	151	{
152	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);	152	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
153	u32 mask = 1 << (d->irq - gc->irq_base);	153	u32 mask = 1 << (d->irq - gc->irq_base);
154		154
155	irq_gc_lock(gc);	155	irq_gc_lock(gc);
156	irq_reg_writel(mask, gc->reg_base + cur_regs(d)->eoi);	156	irq_reg_writel(mask, gc->reg_base + cur_regs(d)->eoi);
157	irq_gc_unlock(gc);	157	irq_gc_unlock(gc);
158	}	158	}
159		159
160	/**	160	/**
161	* irq_gc_set_wake - Set/clr wake bit for an interrupt	161	* irq_gc_set_wake - Set/clr wake bit for an interrupt
162	* @d: irq_data	162	* @d: irq_data
163	*	163	*
164	* For chips where the wake from suspend functionality is not	164	* For chips where the wake from suspend functionality is not
165	* configured in a separate register and the wakeup active state is	165	* configured in a separate register and the wakeup active state is
166	* just stored in a bitmask.	166	* just stored in a bitmask.
167	*/	167	*/
168	int irq_gc_set_wake(struct irq_data *d, unsigned int on)	168	int irq_gc_set_wake(struct irq_data *d, unsigned int on)
169	{	169	{
170	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);	170	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
171	u32 mask = 1 << (d->irq - gc->irq_base);	171	u32 mask = 1 << (d->irq - gc->irq_base);
172		172
173	if (!(mask & gc->wake_enabled))	173	if (!(mask & gc->wake_enabled))
174	return -EINVAL;	174	return -EINVAL;
175		175
176	irq_gc_lock(gc);	176	irq_gc_lock(gc);
177	if (on)	177	if (on)
178	gc->wake_active \|= mask;	178	gc->wake_active \|= mask;
179	else	179	else
180	gc->wake_active &= ~mask;	180	gc->wake_active &= ~mask;
181	irq_gc_unlock(gc);	181	irq_gc_unlock(gc);
182	return 0;	182	return 0;
183	}	183	}
184		184
185	/**	185	/**
186	* irq_alloc_generic_chip - Allocate a generic chip and initialize it	186	* irq_alloc_generic_chip - Allocate a generic chip and initialize it
187	* @name: Name of the irq chip	187	* @name: Name of the irq chip
188	* @num_ct: Number of irq_chip_type instances associated with this	188	* @num_ct: Number of irq_chip_type instances associated with this
189	* @irq_base: Interrupt base nr for this chip	189	* @irq_base: Interrupt base nr for this chip
190	* @reg_base: Register base address (virtual)	190	* @reg_base: Register base address (virtual)
191	* @handler: Default flow handler associated with this chip	191	* @handler: Default flow handler associated with this chip
192	*	192	*
193	* Returns an initialized irq_chip_generic structure. The chip defaults	193	* Returns an initialized irq_chip_generic structure. The chip defaults
194	* to the primary (index 0) irq_chip_type and @handler	194	* to the primary (index 0) irq_chip_type and @handler
195	*/	195	*/
196	struct irq_chip_generic *	196	struct irq_chip_generic *
197	irq_alloc_generic_chip(const char *name, int num_ct, unsigned int irq_base,	197	irq_alloc_generic_chip(const char *name, int num_ct, unsigned int irq_base,
198	void __iomem *reg_base, irq_flow_handler_t handler)	198	void __iomem *reg_base, irq_flow_handler_t handler)
199	{	199	{
200	struct irq_chip_generic *gc;	200	struct irq_chip_generic *gc;
201	unsigned long sz = sizeof(gc) + num_ct sizeof(struct irq_chip_type);	201	unsigned long sz = sizeof(gc) + num_ct sizeof(struct irq_chip_type);
202		202
203	gc = kzalloc(sz, GFP_KERNEL);	203	gc = kzalloc(sz, GFP_KERNEL);
204	if (gc) {	204	if (gc) {
205	raw_spin_lock_init(&gc->lock);	205	raw_spin_lock_init(&gc->lock);
206	gc->num_ct = num_ct;	206	gc->num_ct = num_ct;
207	gc->irq_base = irq_base;	207	gc->irq_base = irq_base;
208	gc->reg_base = reg_base;	208	gc->reg_base = reg_base;
209	gc->chip_types->chip.name = name;	209	gc->chip_types->chip.name = name;
210	gc->chip_types->handler = handler;	210	gc->chip_types->handler = handler;
211	}	211	}
212	return gc;	212	return gc;
213	}	213	}
214		214
215	/*	215	/*
216	* Separate lockdep class for interrupt chip which can nest irq_desc	216	* Separate lockdep class for interrupt chip which can nest irq_desc
217	* lock.	217	* lock.
218	*/	218	*/
219	static struct lock_class_key irq_nested_lock_class;	219	static struct lock_class_key irq_nested_lock_class;
220		220
221	/**	221	/**
222	* irq_setup_generic_chip - Setup a range of interrupts with a generic chip	222	* irq_setup_generic_chip - Setup a range of interrupts with a generic chip
223	* @gc: Generic irq chip holding all data	223	* @gc: Generic irq chip holding all data
224	* @msk: Bitmask holding the irqs to initialize relative to gc->irq_base	224	* @msk: Bitmask holding the irqs to initialize relative to gc->irq_base
225	* @flags: Flags for initialization	225	* @flags: Flags for initialization
226	* @clr: IRQ_* bits to clear	226	* @clr: IRQ_* bits to clear
227	* @set: IRQ_* bits to set	227	* @set: IRQ_* bits to set
228	*	228	*
229	* Set up max. 32 interrupts starting from gc->irq_base. Note, this	229	* Set up max. 32 interrupts starting from gc->irq_base. Note, this
230	* initializes all interrupts to the primary irq_chip_type and its	230	* initializes all interrupts to the primary irq_chip_type and its
231	* associated handler.	231	* associated handler.
232	*/	232	*/
233	void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk,	233	void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk,
234	enum irq_gc_flags flags, unsigned int clr,	234	enum irq_gc_flags flags, unsigned int clr,
235	unsigned int set)	235	unsigned int set)
236	{	236	{
237	struct irq_chip_type *ct = gc->chip_types;	237	struct irq_chip_type *ct = gc->chip_types;
238	unsigned int i;	238	unsigned int i;
239		239
240	raw_spin_lock(&gc_lock);	240	raw_spin_lock(&gc_lock);
241	list_add_tail(&gc->list, &gc_list);	241	list_add_tail(&gc->list, &gc_list);
242	raw_spin_unlock(&gc_lock);	242	raw_spin_unlock(&gc_lock);
243		243
244	/* Init mask cache ? */	244	/* Init mask cache ? */
245	if (flags & IRQ_GC_INIT_MASK_CACHE)	245	if (flags & IRQ_GC_INIT_MASK_CACHE)
246	gc->mask_cache = irq_reg_readl(gc->reg_base + ct->regs.mask);	246	gc->mask_cache = irq_reg_readl(gc->reg_base + ct->regs.mask);
247		247
248	for (i = gc->irq_base; msk; msk >>= 1, i++) {	248	for (i = gc->irq_base; msk; msk >>= 1, i++) {
249	if (!msk & 0x01)	249	if (!(msk & 0x01))
250	continue;	250	continue;
251		251
252	if (flags & IRQ_GC_INIT_NESTED_LOCK)	252	if (flags & IRQ_GC_INIT_NESTED_LOCK)
253	irq_set_lockdep_class(i, &irq_nested_lock_class);	253	irq_set_lockdep_class(i, &irq_nested_lock_class);
254		254
255	irq_set_chip_and_handler(i, &ct->chip, ct->handler);	255	irq_set_chip_and_handler(i, &ct->chip, ct->handler);
256	irq_set_chip_data(i, gc);	256	irq_set_chip_data(i, gc);
257	irq_modify_status(i, clr, set);	257	irq_modify_status(i, clr, set);
258	}	258	}
259	gc->irq_cnt = i - gc->irq_base;	259	gc->irq_cnt = i - gc->irq_base;
260	}	260	}
261		261
262	/**	262	/**
263	* irq_setup_alt_chip - Switch to alternative chip	263	* irq_setup_alt_chip - Switch to alternative chip
264	* @d: irq_data for this interrupt	264	* @d: irq_data for this interrupt
265	* @type Flow type to be initialized	265	* @type Flow type to be initialized
266	*	266	*
267	* Only to be called from chip->irq_set_type() callbacks.	267	* Only to be called from chip->irq_set_type() callbacks.
268	*/	268	*/
269	int irq_setup_alt_chip(struct irq_data *d, unsigned int type)	269	int irq_setup_alt_chip(struct irq_data *d, unsigned int type)
270	{	270	{
271	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);	271	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
272	struct irq_chip_type *ct = gc->chip_types;	272	struct irq_chip_type *ct = gc->chip_types;
273	unsigned int i;	273	unsigned int i;
274		274
275	for (i = 0; i < gc->num_ct; i++, ct++) {	275	for (i = 0; i < gc->num_ct; i++, ct++) {
276	if (ct->type & type) {	276	if (ct->type & type) {
277	d->chip = &ct->chip;	277	d->chip = &ct->chip;
278	irq_data_to_desc(d)->handle_irq = ct->handler;	278	irq_data_to_desc(d)->handle_irq = ct->handler;
279	return 0;	279	return 0;
280	}	280	}
281	}	281	}
282	return -EINVAL;	282	return -EINVAL;
283	}	283	}
284		284
285	/**	285	/**
286	* irq_remove_generic_chip - Remove a chip	286	* irq_remove_generic_chip - Remove a chip
287	* @gc: Generic irq chip holding all data	287	* @gc: Generic irq chip holding all data
288	* @msk: Bitmask holding the irqs to initialize relative to gc->irq_base	288	* @msk: Bitmask holding the irqs to initialize relative to gc->irq_base
289	* @clr: IRQ_* bits to clear	289	* @clr: IRQ_* bits to clear
290	* @set: IRQ_* bits to set	290	* @set: IRQ_* bits to set
291	*	291	*
292	* Remove up to 32 interrupts starting from gc->irq_base.	292	* Remove up to 32 interrupts starting from gc->irq_base.
293	*/	293	*/
294	void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk,	294	void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk,
295	unsigned int clr, unsigned int set)	295	unsigned int clr, unsigned int set)
296	{	296	{
297	unsigned int i = gc->irq_base;	297	unsigned int i = gc->irq_base;
298		298
299	raw_spin_lock(&gc_lock);	299	raw_spin_lock(&gc_lock);
300	list_del(&gc->list);	300	list_del(&gc->list);
301	raw_spin_unlock(&gc_lock);	301	raw_spin_unlock(&gc_lock);
302		302
303	for (; msk; msk >>= 1, i++) {	303	for (; msk; msk >>= 1, i++) {
304	if (!msk & 0x01)	304	if (!(msk & 0x01))
305	continue;	305	continue;
306		306
307	/* Remove handler first. That will mask the irq line */	307	/* Remove handler first. That will mask the irq line */
308	irq_set_handler(i, NULL);	308	irq_set_handler(i, NULL);
309	irq_set_chip(i, &no_irq_chip);	309	irq_set_chip(i, &no_irq_chip);
310	irq_set_chip_data(i, NULL);	310	irq_set_chip_data(i, NULL);
311	irq_modify_status(i, clr, set);	311	irq_modify_status(i, clr, set);
312	}	312	}
313	}	313	}
314		314
315	#ifdef CONFIG_PM	315	#ifdef CONFIG_PM
316	static int irq_gc_suspend(void)	316	static int irq_gc_suspend(void)
317	{	317	{
318	struct irq_chip_generic *gc;	318	struct irq_chip_generic *gc;
319		319
320	list_for_each_entry(gc, &gc_list, list) {	320	list_for_each_entry(gc, &gc_list, list) {
321	struct irq_chip_type *ct = gc->chip_types;	321	struct irq_chip_type *ct = gc->chip_types;
322		322
323	if (ct->chip.irq_suspend)	323	if (ct->chip.irq_suspend)
324	ct->chip.irq_suspend(irq_get_irq_data(gc->irq_base));	324	ct->chip.irq_suspend(irq_get_irq_data(gc->irq_base));
325	}	325	}
326	return 0;	326	return 0;
327	}	327	}
328		328
329	static void irq_gc_resume(void)	329	static void irq_gc_resume(void)
330	{	330	{
331	struct irq_chip_generic *gc;	331	struct irq_chip_generic *gc;
332		332
333	list_for_each_entry(gc, &gc_list, list) {	333	list_for_each_entry(gc, &gc_list, list) {
334	struct irq_chip_type *ct = gc->chip_types;	334	struct irq_chip_type *ct = gc->chip_types;
335		335
336	if (ct->chip.irq_resume)	336	if (ct->chip.irq_resume)
337	ct->chip.irq_resume(irq_get_irq_data(gc->irq_base));	337	ct->chip.irq_resume(irq_get_irq_data(gc->irq_base));
338	}	338	}
339	}	339	}
340	#else	340	#else
341	#define irq_gc_suspend NULL	341	#define irq_gc_suspend NULL
342	#define irq_gc_resume NULL	342	#define irq_gc_resume NULL
343	#endif	343	#endif
344		344
345	static void irq_gc_shutdown(void)	345	static void irq_gc_shutdown(void)
346	{	346	{
347	struct irq_chip_generic *gc;	347	struct irq_chip_generic *gc;
348		348
349	list_for_each_entry(gc, &gc_list, list) {	349	list_for_each_entry(gc, &gc_list, list) {
350	struct irq_chip_type *ct = gc->chip_types;	350	struct irq_chip_type *ct = gc->chip_types;
351		351
352	if (ct->chip.irq_pm_shutdown)	352	if (ct->chip.irq_pm_shutdown)
353	ct->chip.irq_pm_shutdown(irq_get_irq_data(gc->irq_base));	353	ct->chip.irq_pm_shutdown(irq_get_irq_data(gc->irq_base));
354	}	354	}
355	}	355	}
356		356
357	static struct syscore_ops irq_gc_syscore_ops = {	357	static struct syscore_ops irq_gc_syscore_ops = {
358	.suspend = irq_gc_suspend,	358	.suspend = irq_gc_suspend,
359	.resume = irq_gc_resume,	359	.resume = irq_gc_resume,
360	.shutdown = irq_gc_shutdown,	360	.shutdown = irq_gc_shutdown,
361	};	361	};
362		362
363	static int __init irq_gc_init_ops(void)	363	static int __init irq_gc_init_ops(void)
364	{	364	{
365	register_syscore_ops(&irq_gc_syscore_ops);	365	register_syscore_ops(&irq_gc_syscore_ops);
366	return 0;	366	return 0;
367	}	367	}
368	device_initcall(irq_gc_init_ops);	368	device_initcall(irq_gc_init_ops);
369		369

kernel/irq/irqdesc.c

Diff comments View file @ 950d0a1

 /*
  * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar
  * Copyright (C) 2005-2006, Thomas Gleixner, Russell King
  *
  * This file contains the interrupt descriptor management code
  *
  * Detailed information is available in Documentation/DocBook/genericirq
  *
  */
 #include <linux/irq.h>
 #include <linux/slab.h>
 #include <linux/module.h>
 #include <linux/interrupt.h>
 #include <linux/kernel_stat.h>
 #include <linux/radix-tree.h>
 #include <linux/bitmap.h>
 #include "internals.h"
 /*
  * lockdep: we want to handle all irq_desc locks as a single lock-class:
  */
 static struct lock_class_key irq_desc_lock_class;
 #if defined(CONFIG_SMP)
 static void __init init_irq_default_affinity(void)
 {
 	alloc_cpumask_var(&irq_default_affinity, GFP_NOWAIT);
 	cpumask_setall(irq_default_affinity);
 }
 #else
 static void __init init_irq_default_affinity(void)
 {
 }
 #endif
 #ifdef CONFIG_SMP
 static int alloc_masks(struct irq_desc *desc, gfp_t gfp, int node)
 {
 	if (!zalloc_cpumask_var_node(&desc->irq_data.affinity, gfp, node))
 		return -ENOMEM;
 #ifdef CONFIG_GENERIC_PENDING_IRQ
 	if (!zalloc_cpumask_var_node(&desc->pending_mask, gfp, node)) {
 		free_cpumask_var(desc->irq_data.affinity);
 		return -ENOMEM;
 	}
 #endif
 	return 0;
 }
 static void desc_smp_init(struct irq_desc *desc, int node)
 {
 	desc->irq_data.node = node;
 	cpumask_copy(desc->irq_data.affinity, irq_default_affinity);
 #ifdef CONFIG_GENERIC_PENDING_IRQ
 	cpumask_clear(desc->pending_mask);
 #endif
 }
 static inline int desc_node(struct irq_desc *desc)
 {
 	return desc->irq_data.node;
 }
 #else
 static inline int
 alloc_masks(struct irq_desc *desc, gfp_t gfp, int node) { return 0; }
 static inline void desc_smp_init(struct irq_desc *desc, int node) { }
 static inline int desc_node(struct irq_desc *desc) { return 0; }
 #endif
-static void desc_set_defaults(unsigned int irq, struct irq_desc *desc, int node)
+static void desc_set_defaults(unsigned int irq, struct irq_desc *desc, int node,
+		struct module *owner)
 {
 	int cpu;
 	desc->irq_data.irq = irq;
 	desc->irq_data.chip = &no_irq_chip;
 	desc->irq_data.chip_data = NULL;
 	desc->irq_data.handler_data = NULL;
 	desc->irq_data.msi_desc = NULL;
 	irq_settings_clr_and_set(desc, ~0, _IRQ_DEFAULT_INIT_FLAGS);
 	irqd_set(&desc->irq_data, IRQD_IRQ_DISABLED);
 	desc->handle_irq = handle_bad_irq;
 	desc->depth = 1;
 	desc->irq_count = 0;
 	desc->irqs_unhandled = 0;
 	desc->name = NULL;
+	desc->owner = owner;
 	for_each_possible_cpu(cpu)
 		*per_cpu_ptr(desc->kstat_irqs, cpu) = 0;
 	desc_smp_init(desc, node);
 }
 int nr_irqs = NR_IRQS;
 EXPORT_SYMBOL_GPL(nr_irqs);
 static DEFINE_MUTEX(sparse_irq_lock);
 static DECLARE_BITMAP(allocated_irqs, IRQ_BITMAP_BITS);
 #ifdef CONFIG_SPARSE_IRQ
 static RADIX_TREE(irq_desc_tree, GFP_KERNEL);
 static void irq_insert_desc(unsigned int irq, struct irq_desc *desc)
 {
 	radix_tree_insert(&irq_desc_tree, irq, desc);
 }
 struct irq_desc *irq_to_desc(unsigned int irq)
 {
 	return radix_tree_lookup(&irq_desc_tree, irq);
 }
 static void delete_irq_desc(unsigned int irq)
 {
 	radix_tree_delete(&irq_desc_tree, irq);
 }
 #ifdef CONFIG_SMP
 static void free_masks(struct irq_desc *desc)
 {
 #ifdef CONFIG_GENERIC_PENDING_IRQ
 	free_cpumask_var(desc->pending_mask);
 #endif
 	free_cpumask_var(desc->irq_data.affinity);
 }
 #else
 static inline void free_masks(struct irq_desc *desc) { }
 #endif
-static struct irq_desc *alloc_desc(int irq, int node)
+static struct irq_desc *alloc_desc(int irq, int node, struct module *owner)
 {
 	struct irq_desc *desc;
 	gfp_t gfp = GFP_KERNEL;
 	desc = kzalloc_node(sizeof(*desc), gfp, node);
 	if (!desc)
 		return NULL;
 	/* allocate based on nr_cpu_ids */
 	desc->kstat_irqs = alloc_percpu(unsigned int);
 	if (!desc->kstat_irqs)
 		goto err_desc;
 	if (alloc_masks(desc, gfp, node))
 		goto err_kstat;
 	raw_spin_lock_init(&desc->lock);
 	lockdep_set_class(&desc->lock, &irq_desc_lock_class);
-	desc_set_defaults(irq, desc, node);
+	desc_set_defaults(irq, desc, node, owner);
 	return desc;
 err_kstat:
 	free_percpu(desc->kstat_irqs);
 err_desc:
 	kfree(desc);
 	return NULL;
 }
 static void free_desc(unsigned int irq)
 {
 	struct irq_desc *desc = irq_to_desc(irq);
 	unregister_irq_proc(irq, desc);
 	mutex_lock(&sparse_irq_lock);
 	delete_irq_desc(irq);
 	mutex_unlock(&sparse_irq_lock);
 	free_masks(desc);
 	free_percpu(desc->kstat_irqs);
 	kfree(desc);
 }
-static int alloc_descs(unsigned int start, unsigned int cnt, int node)
+static int alloc_descs(unsigned int start, unsigned int cnt, int node,
+		       struct module *owner)
 {
 	struct irq_desc *desc;
 	int i;
 	for (i = 0; i < cnt; i++) {
-		desc = alloc_desc(start + i, node);
+		desc = alloc_desc(start + i, node, owner);
 		if (!desc)
 			goto err;
 		mutex_lock(&sparse_irq_lock);
 		irq_insert_desc(start + i, desc);
 		mutex_unlock(&sparse_irq_lock);
 	}
 	return start;
 err:
 	for (i--; i >= 0; i--)
 		free_desc(start + i);
 	mutex_lock(&sparse_irq_lock);
 	bitmap_clear(allocated_irqs, start, cnt);
 	mutex_unlock(&sparse_irq_lock);
 	return -ENOMEM;
 }
 static int irq_expand_nr_irqs(unsigned int nr)
 {
 	if (nr > IRQ_BITMAP_BITS)
 		return -ENOMEM;
 	nr_irqs = nr;
 	return 0;
 }
 int __init early_irq_init(void)
 {
 	int i, initcnt, node = first_online_node;
 	struct irq_desc *desc;
 	init_irq_default_affinity();
 	/* Let arch update nr_irqs and return the nr of preallocated irqs */
 	initcnt = arch_probe_nr_irqs();
 	printk(KERN_INFO "NR_IRQS:%d nr_irqs:%d %d\n", NR_IRQS, nr_irqs, initcnt);
 	if (WARN_ON(nr_irqs > IRQ_BITMAP_BITS))
 		nr_irqs = IRQ_BITMAP_BITS;
 	if (WARN_ON(initcnt > IRQ_BITMAP_BITS))
 		initcnt = IRQ_BITMAP_BITS;
 	if (initcnt > nr_irqs)
 		nr_irqs = initcnt;
 	for (i = 0; i < initcnt; i++) {
-		desc = alloc_desc(i, node);
+		desc = alloc_desc(i, node, NULL);
 		set_bit(i, allocated_irqs);
 		irq_insert_desc(i, desc);
 	}
 	return arch_early_irq_init();
 }
 #else /* !CONFIG_SPARSE_IRQ */
 struct irq_desc irq_desc[NR_IRQS] __cacheline_aligned_in_smp = {
 	[0 ... NR_IRQS-1] = {
 		.handle_irq	= handle_bad_irq,
 		.depth		= 1,
 		.lock		= __RAW_SPIN_LOCK_UNLOCKED(irq_desc->lock),
 	}
 };
 int __init early_irq_init(void)
 {
 	int count, i, node = first_online_node;
 	struct irq_desc *desc;
 	init_irq_default_affinity();
 	printk(KERN_INFO "NR_IRQS:%d\n", NR_IRQS);
 	desc = irq_desc;
 	count = ARRAY_SIZE(irq_desc);
 	for (i = 0; i < count; i++) {
 		desc[i].kstat_irqs = alloc_percpu(unsigned int);
 		alloc_masks(&desc[i], GFP_KERNEL, node);
 		raw_spin_lock_init(&desc[i].lock);
 		lockdep_set_class(&desc[i].lock, &irq_desc_lock_class);
-		desc_set_defaults(i, &desc[i], node);
+		desc_set_defaults(i, &desc[i], node, NULL);
 	}
 	return arch_early_irq_init();
 }
 struct irq_desc *irq_to_desc(unsigned int irq)
 {
 	return (irq < NR_IRQS) ? irq_desc + irq : NULL;
 }
 static void free_desc(unsigned int irq)
 {
 	dynamic_irq_cleanup(irq);
 }
-static inline int alloc_descs(unsigned int start, unsigned int cnt, int node)
+static inline int alloc_descs(unsigned int start, unsigned int cnt, int node,
+			      struct module *owner)
 {
+	u32 i;
+	for (i = 0; i < cnt; i++) {
+		struct irq_desc *desc = irq_to_desc(start + i);
+		desc->owner = owner;
+	}
 	return start;
 }
 static int irq_expand_nr_irqs(unsigned int nr)
 {
 	return -ENOMEM;
 }
 #endif /* !CONFIG_SPARSE_IRQ */
 /**
  * generic_handle_irq - Invoke the handler for a particular irq
  * @irq:	The irq number to handle
  *
  */
 int generic_handle_irq(unsigned int irq)
 {
 	struct irq_desc *desc = irq_to_desc(irq);
 	if (!desc)
 		return -EINVAL;
 	generic_handle_irq_desc(irq, desc);
 	return 0;
 }
 EXPORT_SYMBOL_GPL(generic_handle_irq);
 /* Dynamic interrupt handling */
 /**
  * irq_free_descs - free irq descriptors
  * @from:	Start of descriptor range
  * @cnt:	Number of consecutive irqs to free
  */
 void irq_free_descs(unsigned int from, unsigned int cnt)
 {
 	int i;
 	if (from >= nr_irqs || (from + cnt) > nr_irqs)
 		return;
 	for (i = 0; i < cnt; i++)
 		free_desc(from + i);
 	mutex_lock(&sparse_irq_lock);
 	bitmap_clear(allocated_irqs, from, cnt);
 	mutex_unlock(&sparse_irq_lock);
 }
 EXPORT_SYMBOL_GPL(irq_free_descs);
 /**
  * irq_alloc_descs - allocate and initialize a range of irq descriptors
  * @irq:	Allocate for specific irq number if irq >= 0
  * @from:	Start the search from this irq number
  * @cnt:	Number of consecutive irqs to allocate.
  * @node:	Preferred node on which the irq descriptor should be allocated
  *
  * Returns the first irq number or error code
  */
 int __ref
-irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node)
+__irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node,
+		  struct module *owner)
 {
 	int start, ret;
 	if (!cnt)
 		return -EINVAL;
 	if (irq >= 0) {
 		if (from > irq)
 			return -EINVAL;
 		from = irq;
 	}
 	mutex_lock(&sparse_irq_lock);
 	start = bitmap_find_next_zero_area(allocated_irqs, IRQ_BITMAP_BITS,
 					   from, cnt, 0);
 	ret = -EEXIST;
 	if (irq >=0 && start != irq)
 		goto err;
 	if (start + cnt > nr_irqs) {
 		ret = irq_expand_nr_irqs(start + cnt);
 		if (ret)
 			goto err;
 	}
 	bitmap_set(allocated_irqs, start, cnt);
 	mutex_unlock(&sparse_irq_lock);
-	return alloc_descs(start, cnt, node);
+	return alloc_descs(start, cnt, node, owner);
 err:
 	mutex_unlock(&sparse_irq_lock);
 	return ret;
 }
-EXPORT_SYMBOL_GPL(irq_alloc_descs);
+EXPORT_SYMBOL_GPL(__irq_alloc_descs);
 /**
  * irq_reserve_irqs - mark irqs allocated
  * @from:	mark from irq number
  * @cnt:	number of irqs to mark
  *
  * Returns 0 on success or an appropriate error code
  */
 int irq_reserve_irqs(unsigned int from, unsigned int cnt)
 {
 	unsigned int start;
 	int ret = 0;
 	if (!cnt || (from + cnt) > nr_irqs)
 		return -EINVAL;
 	mutex_lock(&sparse_irq_lock);
 	start = bitmap_find_next_zero_area(allocated_irqs, nr_irqs, from, cnt, 0);
 	if (start == from)
 		bitmap_set(allocated_irqs, start, cnt);
 	else
 		ret = -EEXIST;
 	mutex_unlock(&sparse_irq_lock);
 	return ret;
 }
 /**
  * irq_get_next_irq - get next allocated irq number
  * @offset:	where to start the search
  *
  * Returns next irq number after offset or nr_irqs if none is found.
  */
 unsigned int irq_get_next_irq(unsigned int offset)
 {
 	return find_next_bit(allocated_irqs, nr_irqs, offset);
 }
 struct irq_desc *
 __irq_get_desc_lock(unsigned int irq, unsigned long *flags, bool bus)
 {
 	struct irq_desc *desc = irq_to_desc(irq);
 	if (desc) {
 		if (bus)
 			chip_bus_lock(desc);
 		raw_spin_lock_irqsave(&desc->lock, *flags);
 	}
 	return desc;
 }
 void __irq_put_desc_unlock(struct irq_desc *desc, unsigned long flags, bool bus)
 {
 	raw_spin_unlock_irqrestore(&desc->lock, flags);
 	if (bus)
 		chip_bus_sync_unlock(desc);
 }
 /**
  * dynamic_irq_cleanup - cleanup a dynamically allocated irq
  * @irq:	irq number to initialize
  */
 void dynamic_irq_cleanup(unsigned int irq)
 {
 	struct irq_desc *desc = irq_to_desc(irq);
 	unsigned long flags;
 	raw_spin_lock_irqsave(&desc->lock, flags);
-	desc_set_defaults(irq, desc, desc_node(desc));
+	desc_set_defaults(irq, desc, desc_node(desc), NULL);
 	raw_spin_unlock_irqrestore(&desc->lock, flags);
 }
 unsigned int kstat_irqs_cpu(unsigned int irq, int cpu)
 {
 	struct irq_desc *desc = irq_to_desc(irq);
 	return desc && desc->kstat_irqs ?
 			*per_cpu_ptr(desc->kstat_irqs, cpu) : 0;
 }
 unsigned int kstat_irqs(unsigned int irq)
 {
 	struct irq_desc *desc = irq_to_desc(irq);
 	int cpu;
 	int sum = 0;
 	if (!desc || !desc->kstat_irqs)
 		return 0;
 	for_each_possible_cpu(cpu)
 		sum += *per_cpu_ptr(desc->kstat_irqs, cpu);
 	return sum;
 }

kernel/irq/manage.c

Diff comments View file @ 950d0a1

 /*
  * linux/kernel/irq/manage.c
  *
  * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar
  * Copyright (C) 2005-2006 Thomas Gleixner
  *
  * This file contains driver APIs to the irq subsystem.
  */
 #include <linux/irq.h>
 #include <linux/kthread.h>
 #include <linux/module.h>
 #include <linux/random.h>
 #include <linux/interrupt.h>
 #include <linux/slab.h>
 #include <linux/sched.h>
 #include "internals.h"
 #ifdef CONFIG_IRQ_FORCED_THREADING
 __read_mostly bool force_irqthreads;
 static int __init setup_forced_irqthreads(char *arg)
 {
 	force_irqthreads = true;
 	return 0;
 }
 early_param("threadirqs", setup_forced_irqthreads);
 #endif
 /**
  *	synchronize_irq - wait for pending IRQ handlers (on other CPUs)
  *	@irq: interrupt number to wait for
  *
  *	This function waits for any pending IRQ handlers for this interrupt
  *	to complete before returning. If you use this function while
  *	holding a resource the IRQ handler may need you will deadlock.
  *
  *	This function may be called - with care - from IRQ context.
  */
 void synchronize_irq(unsigned int irq)
 {
 	struct irq_desc *desc = irq_to_desc(irq);
 	bool inprogress;
 	if (!desc)
 		return;
 	do {
 		unsigned long flags;
 		/*
 		 * Wait until we're out of the critical section.  This might
 		 * give the wrong answer due to the lack of memory barriers.
 		 */
 		while (irqd_irq_inprogress(&desc->irq_data))
 			cpu_relax();
 		/* Ok, that indicated we're done: double-check carefully. */
 		raw_spin_lock_irqsave(&desc->lock, flags);
 		inprogress = irqd_irq_inprogress(&desc->irq_data);
 		raw_spin_unlock_irqrestore(&desc->lock, flags);
 		/* Oops, that failed? */
 	} while (inprogress);
 	/*
 	 * We made sure that no hardirq handler is running. Now verify
 	 * that no threaded handlers are active.
 	 */
 	wait_event(desc->wait_for_threads, !atomic_read(&desc->threads_active));
 }
 EXPORT_SYMBOL(synchronize_irq);
 #ifdef CONFIG_SMP
 cpumask_var_t irq_default_affinity;
 /**
  *	irq_can_set_affinity - Check if the affinity of a given irq can be set
  *	@irq:		Interrupt to check
  *
  */
 int irq_can_set_affinity(unsigned int irq)
 {
 	struct irq_desc *desc = irq_to_desc(irq);
 	if (!desc || !irqd_can_balance(&desc->irq_data) ||
 	    !desc->irq_data.chip || !desc->irq_data.chip->irq_set_affinity)
 		return 0;
 	return 1;
 }
 /**
  *	irq_set_thread_affinity - Notify irq threads to adjust affinity
  *	@desc:		irq descriptor which has affitnity changed
  *
  *	We just set IRQTF_AFFINITY and delegate the affinity setting
  *	to the interrupt thread itself. We can not call
  *	set_cpus_allowed_ptr() here as we hold desc->lock and this
  *	code can be called from hard interrupt context.
  */
 void irq_set_thread_affinity(struct irq_desc *desc)
 {
 	struct irqaction *action = desc->action;
 	while (action) {
 		if (action->thread)
 			set_bit(IRQTF_AFFINITY, &action->thread_flags);
 		action = action->next;
 	}
 }
 #ifdef CONFIG_GENERIC_PENDING_IRQ
 static inline bool irq_can_move_pcntxt(struct irq_data *data)
 {
 	return irqd_can_move_in_process_context(data);
 }
 static inline bool irq_move_pending(struct irq_data *data)
 {
 	return irqd_is_setaffinity_pending(data);
 }
 static inline void
 irq_copy_pending(struct irq_desc *desc, const struct cpumask *mask)
 {
 	cpumask_copy(desc->pending_mask, mask);
 }
 static inline void
 irq_get_pending(struct cpumask *mask, struct irq_desc *desc)
 {
 	cpumask_copy(mask, desc->pending_mask);
 }
 #else
 static inline bool irq_can_move_pcntxt(struct irq_data *data) { return true; }
 static inline bool irq_move_pending(struct irq_data *data) { return false; }
 static inline void
 irq_copy_pending(struct irq_desc *desc, const struct cpumask *mask) { }
 static inline void
 irq_get_pending(struct cpumask *mask, struct irq_desc *desc) { }
 #endif
 int __irq_set_affinity_locked(struct irq_data *data, const struct cpumask *mask)
 {
 	struct irq_chip *chip = irq_data_get_irq_chip(data);
 	struct irq_desc *desc = irq_data_to_desc(data);
 	int ret = 0;
 	if (!chip || !chip->irq_set_affinity)
 		return -EINVAL;
 	if (irq_can_move_pcntxt(data)) {
 		ret = chip->irq_set_affinity(data, mask, false);
 		switch (ret) {
 		case IRQ_SET_MASK_OK:
 			cpumask_copy(data->affinity, mask);
 		case IRQ_SET_MASK_OK_NOCOPY:
 			irq_set_thread_affinity(desc);
 			ret = 0;
 		}
 	} else {
 		irqd_set_move_pending(data);
 		irq_copy_pending(desc, mask);
 	}
 	if (desc->affinity_notify) {
 		kref_get(&desc->affinity_notify->kref);
 		schedule_work(&desc->affinity_notify->work);
 	}
 	irqd_set(data, IRQD_AFFINITY_SET);
 	return ret;
 }
 /**
  *	irq_set_affinity - Set the irq affinity of a given irq
  *	@irq:		Interrupt to set affinity
  *	@mask:		cpumask
  *
  */
 int irq_set_affinity(unsigned int irq, const struct cpumask *mask)
 {
 	struct irq_desc *desc = irq_to_desc(irq);
 	unsigned long flags;
 	int ret;
 	if (!desc)
 		return -EINVAL;
 	raw_spin_lock_irqsave(&desc->lock, flags);
 	ret =  __irq_set_affinity_locked(irq_desc_get_irq_data(desc), mask);
 	raw_spin_unlock_irqrestore(&desc->lock, flags);
 	return ret;
 }
 int irq_set_affinity_hint(unsigned int irq, const struct cpumask *m)
 {
 	unsigned long flags;
 	struct irq_desc *desc = irq_get_desc_lock(irq, &flags);
 	if (!desc)
 		return -EINVAL;
 	desc->affinity_hint = m;
 	irq_put_desc_unlock(desc, flags);
 	return 0;
 }
 EXPORT_SYMBOL_GPL(irq_set_affinity_hint);
 static void irq_affinity_notify(struct work_struct *work)
 {
 	struct irq_affinity_notify *notify =
 		container_of(work, struct irq_affinity_notify, work);
 	struct irq_desc *desc = irq_to_desc(notify->irq);
 	cpumask_var_t cpumask;
 	unsigned long flags;
 	if (!desc || !alloc_cpumask_var(&cpumask, GFP_KERNEL))
 		goto out;
 	raw_spin_lock_irqsave(&desc->lock, flags);
 	if (irq_move_pending(&desc->irq_data))
 		irq_get_pending(cpumask, desc);
 	else
 		cpumask_copy(cpumask, desc->irq_data.affinity);
 	raw_spin_unlock_irqrestore(&desc->lock, flags);
 	notify->notify(notify, cpumask);
 	free_cpumask_var(cpumask);
 out:
 	kref_put(&notify->kref, notify->release);
 }
 /**
  *	irq_set_affinity_notifier - control notification of IRQ affinity changes
  *	@irq:		Interrupt for which to enable/disable notification
  *	@notify:	Context for notification, or %NULL to disable
  *			notification.  Function pointers must be initialised;
  *			the other fields will be initialised by this function.
  *
  *	Must be called in process context.  Notification may only be enabled
  *	after the IRQ is allocated and must be disabled before the IRQ is
  *	freed using free_irq().
  */
 int
 irq_set_affinity_notifier(unsigned int irq, struct irq_affinity_notify *notify)
 {
 	struct irq_desc *desc = irq_to_desc(irq);
 	struct irq_affinity_notify *old_notify;
 	unsigned long flags;
 	/* The release function is promised process context */
 	might_sleep();
 	if (!desc)
 		return -EINVAL;
 	/* Complete initialisation of *notify */
 	if (notify) {
 		notify->irq = irq;
 		kref_init(&notify->kref);
 		INIT_WORK(&notify->work, irq_affinity_notify);
 	}
 	raw_spin_lock_irqsave(&desc->lock, flags);
 	old_notify = desc->affinity_notify;
 	desc->affinity_notify = notify;
 	raw_spin_unlock_irqrestore(&desc->lock, flags);
 	if (old_notify)
 		kref_put(&old_notify->kref, old_notify->release);
 	return 0;
 }
 EXPORT_SYMBOL_GPL(irq_set_affinity_notifier);
 #ifndef CONFIG_AUTO_IRQ_AFFINITY
 /*
  * Generic version of the affinity autoselector.
  */
 static int
 setup_affinity(unsigned int irq, struct irq_desc *desc, struct cpumask *mask)
 {
 	struct irq_chip *chip = irq_desc_get_chip(desc);
 	struct cpumask *set = irq_default_affinity;
 	int ret;
 	/* Excludes PER_CPU and NO_BALANCE interrupts */
 	if (!irq_can_set_affinity(irq))
 		return 0;
 	/*
 	 * Preserve an userspace affinity setup, but make sure that
 	 * one of the targets is online.
 	 */
 	if (irqd_has_set(&desc->irq_data, IRQD_AFFINITY_SET)) {
 		if (cpumask_intersects(desc->irq_data.affinity,
 				       cpu_online_mask))
 			set = desc->irq_data.affinity;
 		else
 			irqd_clear(&desc->irq_data, IRQD_AFFINITY_SET);
 	}
 	cpumask_and(mask, cpu_online_mask, set);
 	ret = chip->irq_set_affinity(&desc->irq_data, mask, false);
 	switch (ret) {
 	case IRQ_SET_MASK_OK:
 		cpumask_copy(desc->irq_data.affinity, mask);
 	case IRQ_SET_MASK_OK_NOCOPY:
 		irq_set_thread_affinity(desc);
 	}
 	return 0;
 }
 #else
 static inline int
 setup_affinity(unsigned int irq, struct irq_desc *d, struct cpumask *mask)
 {
 	return irq_select_affinity(irq);
 }
 #endif
 /*
  * Called when affinity is set via /proc/irq
  */
 int irq_select_affinity_usr(unsigned int irq, struct cpumask *mask)
 {
 	struct irq_desc *desc = irq_to_desc(irq);
 	unsigned long flags;
 	int ret;
 	raw_spin_lock_irqsave(&desc->lock, flags);
 	ret = setup_affinity(irq, desc, mask);
 	raw_spin_unlock_irqrestore(&desc->lock, flags);
 	return ret;
 }
 #else
 static inline int
 setup_affinity(unsigned int irq, struct irq_desc *desc, struct cpumask *mask)
 {
 	return 0;
 }
 #endif
 void __disable_irq(struct irq_desc *desc, unsigned int irq, bool suspend)
 {
 	if (suspend) {
 		if (!desc->action || (desc->action->flags & IRQF_NO_SUSPEND))
 			return;
 		desc->istate |= IRQS_SUSPENDED;
 	}
 	if (!desc->depth++)
 		irq_disable(desc);
 }
 static int __disable_irq_nosync(unsigned int irq)
 {
 	unsigned long flags;
 	struct irq_desc *desc = irq_get_desc_buslock(irq, &flags);
 	if (!desc)
 		return -EINVAL;
 	__disable_irq(desc, irq, false);
 	irq_put_desc_busunlock(desc, flags);
 	return 0;
 }
 /**
  *	disable_irq_nosync - disable an irq without waiting
  *	@irq: Interrupt to disable
  *
  *	Disable the selected interrupt line.  Disables and Enables are
  *	nested.
  *	Unlike disable_irq(), this function does not ensure existing
  *	instances of the IRQ handler have completed before returning.
  *
  *	This function may be called from IRQ context.
  */
 void disable_irq_nosync(unsigned int irq)
 {
 	__disable_irq_nosync(irq);
 }
 EXPORT_SYMBOL(disable_irq_nosync);
 /**
  *	disable_irq - disable an irq and wait for completion
  *	@irq: Interrupt to disable
  *
  *	Disable the selected interrupt line.  Enables and Disables are
  *	nested.
  *	This function waits for any pending IRQ handlers for this interrupt
  *	to complete before returning. If you use this function while
  *	holding a resource the IRQ handler may need you will deadlock.
  *
  *	This function may be called - with care - from IRQ context.
  */
 void disable_irq(unsigned int irq)
 {
 	if (!__disable_irq_nosync(irq))
 		synchronize_irq(irq);
 }
 EXPORT_SYMBOL(disable_irq);
 void __enable_irq(struct irq_desc *desc, unsigned int irq, bool resume)
 {
 	if (resume) {
 		if (!(desc->istate & IRQS_SUSPENDED)) {
 			if (!desc->action)
 				return;
 			if (!(desc->action->flags & IRQF_FORCE_RESUME))
 				return;
 			/* Pretend that it got disabled ! */
 			desc->depth++;
 		}
 		desc->istate &= ~IRQS_SUSPENDED;
 	}
 	switch (desc->depth) {
 	case 0:
  err_out:
 		WARN(1, KERN_WARNING "Unbalanced enable for IRQ %d\n", irq);
 		break;
 	case 1: {
 		if (desc->istate & IRQS_SUSPENDED)
 			goto err_out;
 		/* Prevent probing on this irq: */
 		irq_settings_set_noprobe(desc);
 		irq_enable(desc);
 		check_irq_resend(desc, irq);
 		/* fall-through */
 	}
 	default:
 		desc->depth--;
 	}
 }
 /**
  *	enable_irq - enable handling of an irq
  *	@irq: Interrupt to enable
  *
  *	Undoes the effect of one call to disable_irq().  If this
  *	matches the last disable, processing of interrupts on this
  *	IRQ line is re-enabled.
  *
  *	This function may be called from IRQ context only when
  *	desc->irq_data.chip->bus_lock and desc->chip->bus_sync_unlock are NULL !
  */
 void enable_irq(unsigned int irq)
 {
 	unsigned long flags;
 	struct irq_desc *desc = irq_get_desc_buslock(irq, &flags);
 	if (!desc)
 		return;
 	if (WARN(!desc->irq_data.chip,
 		 KERN_ERR "enable_irq before setup/request_irq: irq %u\n", irq))
 		goto out;
 	__enable_irq(desc, irq, false);
 out:
 	irq_put_desc_busunlock(desc, flags);
 }
 EXPORT_SYMBOL(enable_irq);
 static int set_irq_wake_real(unsigned int irq, unsigned int on)
 {
 	struct irq_desc *desc = irq_to_desc(irq);
 	int ret = -ENXIO;
 	if (desc->irq_data.chip->irq_set_wake)
 		ret = desc->irq_data.chip->irq_set_wake(&desc->irq_data, on);
 	return ret;
 }
 /**
  *	irq_set_irq_wake - control irq power management wakeup
  *	@irq:	interrupt to control
  *	@on:	enable/disable power management wakeup
  *
  *	Enable/disable power management wakeup mode, which is
  *	disabled by default.  Enables and disables must match,
  *	just as they match for non-wakeup mode support.
  *
  *	Wakeup mode lets this IRQ wake the system from sleep
  *	states like "suspend to RAM".
  */
 int irq_set_irq_wake(unsigned int irq, unsigned int on)
 {
 	unsigned long flags;
 	struct irq_desc *desc = irq_get_desc_buslock(irq, &flags);
 	int ret = 0;
 	if (!desc)
 		return -EINVAL;
 	/* wakeup-capable irqs can be shared between drivers that
 	 * don't need to have the same sleep mode behaviors.
 	 */
 	if (on) {
 		if (desc->wake_depth++ == 0) {
 			ret = set_irq_wake_real(irq, on);
 			if (ret)
 				desc->wake_depth = 0;
 			else
 				irqd_set(&desc->irq_data, IRQD_WAKEUP_STATE);
 		}
 	} else {
 		if (desc->wake_depth == 0) {
 			WARN(1, "Unbalanced IRQ %d wake disable\n", irq);
 		} else if (--desc->wake_depth == 0) {
 			ret = set_irq_wake_real(irq, on);
 			if (ret)
 				desc->wake_depth = 1;
 			else
 				irqd_clear(&desc->irq_data, IRQD_WAKEUP_STATE);
 		}
 	}
 	irq_put_desc_busunlock(desc, flags);
 	return ret;
 }
 EXPORT_SYMBOL(irq_set_irq_wake);
 /*
  * Internal function that tells the architecture code whether a
  * particular irq has been exclusively allocated or is available
  * for driver use.
  */
 int can_request_irq(unsigned int irq, unsigned long irqflags)
 {
 	unsigned long flags;
 	struct irq_desc *desc = irq_get_desc_lock(irq, &flags);
 	int canrequest = 0;
 	if (!desc)
 		return 0;
 	if (irq_settings_can_request(desc)) {
 		if (desc->action)
 			if (irqflags & desc->action->flags & IRQF_SHARED)
 				canrequest =1;
 	}
 	irq_put_desc_unlock(desc, flags);
 	return canrequest;
 }
 int __irq_set_trigger(struct irq_desc *desc, unsigned int irq,
 		      unsigned long flags)
 {
 	struct irq_chip *chip = desc->irq_data.chip;
 	int ret, unmask = 0;
 	if (!chip || !chip->irq_set_type) {
 		/*
 		 * IRQF_TRIGGER_* but the PIC does not support multiple
 		 * flow-types?
 		 */
 		pr_debug("No set_type function for IRQ %d (%s)\n", irq,
 				chip ? (chip->name ? : "unknown") : "unknown");
 		return 0;
 	}
 	flags &= IRQ_TYPE_SENSE_MASK;
 	if (chip->flags & IRQCHIP_SET_TYPE_MASKED) {
 		if (!irqd_irq_masked(&desc->irq_data))
 			mask_irq(desc);
 		if (!irqd_irq_disabled(&desc->irq_data))
 			unmask = 1;
 	}
 	/* caller masked out all except trigger mode flags */
 	ret = chip->irq_set_type(&desc->irq_data, flags);
 	switch (ret) {
 	case IRQ_SET_MASK_OK:
 		irqd_clear(&desc->irq_data, IRQD_TRIGGER_MASK);
 		irqd_set(&desc->irq_data, flags);
 	case IRQ_SET_MASK_OK_NOCOPY:
 		flags = irqd_get_trigger_type(&desc->irq_data);
 		irq_settings_set_trigger_mask(desc, flags);
 		irqd_clear(&desc->irq_data, IRQD_LEVEL);
 		irq_settings_clr_level(desc);
 		if (flags & IRQ_TYPE_LEVEL_MASK) {
 			irq_settings_set_level(desc);
 			irqd_set(&desc->irq_data, IRQD_LEVEL);
 		}
 		ret = 0;
 		break;
 	default:
 		pr_err("setting trigger mode %lu for irq %u failed (%pF)\n",
 		       flags, irq, chip->irq_set_type);
 	}
 	if (unmask)
 		unmask_irq(desc);
 	return ret;
 }
 /*
  * Default primary interrupt handler for threaded interrupts. Is
  * assigned as primary handler when request_threaded_irq is called
  * with handler == NULL. Useful for oneshot interrupts.
  */
 static irqreturn_t irq_default_primary_handler(int irq, void *dev_id)
 {
 	return IRQ_WAKE_THREAD;
 }
 /*
  * Primary handler for nested threaded interrupts. Should never be
  * called.
  */
 static irqreturn_t irq_nested_primary_handler(int irq, void *dev_id)
 {
 	WARN(1, "Primary handler called for nested irq %d\n", irq);
 	return IRQ_NONE;
 }
 static int irq_wait_for_interrupt(struct irqaction *action)
 {
 	while (!kthread_should_stop()) {
 		set_current_state(TASK_INTERRUPTIBLE);
 		if (test_and_clear_bit(IRQTF_RUNTHREAD,
 				       &action->thread_flags)) {
 			__set_current_state(TASK_RUNNING);
 			return 0;
 		}
 		schedule();
 	}
 	return -1;
 }
 /*
  * Oneshot interrupts keep the irq line masked until the threaded
  * handler finished. unmask if the interrupt has not been disabled and
  * is marked MASKED.
  */
 static void irq_finalize_oneshot(struct irq_desc *desc,
 				 struct irqaction *action, bool force)
 {
 	if (!(desc->istate & IRQS_ONESHOT))
 		return;
 again:
 	chip_bus_lock(desc);
 	raw_spin_lock_irq(&desc->lock);
 	/*
 	 * Implausible though it may be we need to protect us against
 	 * the following scenario:
 	 *
 	 * The thread is faster done than the hard interrupt handler
 	 * on the other CPU. If we unmask the irq line then the
 	 * interrupt can come in again and masks the line, leaves due
 	 * to IRQS_INPROGRESS and the irq line is masked forever.
 	 *
 	 * This also serializes the state of shared oneshot handlers
 	 * versus "desc->threads_onehsot |= action->thread_mask;" in
 	 * irq_wake_thread(). See the comment there which explains the
 	 * serialization.
 	 */
 	if (unlikely(irqd_irq_inprogress(&desc->irq_data))) {
 		raw_spin_unlock_irq(&desc->lock);
 		chip_bus_sync_unlock(desc);
 		cpu_relax();
 		goto again;
 	}
 	/*
 	 * Now check again, whether the thread should run. Otherwise
 	 * we would clear the threads_oneshot bit of this thread which
 	 * was just set.
 	 */
 	if (!force && test_bit(IRQTF_RUNTHREAD, &action->thread_flags))
 		goto out_unlock;
 	desc->threads_oneshot &= ~action->thread_mask;
 	if (!desc->threads_oneshot && !irqd_irq_disabled(&desc->irq_data) &&
 	    irqd_irq_masked(&desc->irq_data))
 		unmask_irq(desc);
 out_unlock:
 	raw_spin_unlock_irq(&desc->lock);
 	chip_bus_sync_unlock(desc);
 }
 #ifdef CONFIG_SMP
 /*
  * Check whether we need to chasnge the affinity of the interrupt thread.
  */
 static void
 irq_thread_check_affinity(struct irq_desc *desc, struct irqaction *action)
 {
 	cpumask_var_t mask;
 	if (!test_and_clear_bit(IRQTF_AFFINITY, &action->thread_flags))
 		return;
 	/*
 	 * In case we are out of memory we set IRQTF_AFFINITY again and
 	 * try again next time
 	 */
 	if (!alloc_cpumask_var(&mask, GFP_KERNEL)) {
 		set_bit(IRQTF_AFFINITY, &action->thread_flags);
 		return;
 	}
 	raw_spin_lock_irq(&desc->lock);
 	cpumask_copy(mask, desc->irq_data.affinity);
 	raw_spin_unlock_irq(&desc->lock);
 	set_cpus_allowed_ptr(current, mask);
 	free_cpumask_var(mask);
 }
 #else
 static inline void
 irq_thread_check_affinity(struct irq_desc *desc, struct irqaction *action) { }
 #endif
 /*
  * Interrupts which are not explicitely requested as threaded
  * interrupts rely on the implicit bh/preempt disable of the hard irq
  * context. So we need to disable bh here to avoid deadlocks and other
  * side effects.
  */
 static irqreturn_t
 irq_forced_thread_fn(struct irq_desc *desc, struct irqaction *action)
 {
 	irqreturn_t ret;
 	local_bh_disable();
 	ret = action->thread_fn(action->irq, action->dev_id);
 	irq_finalize_oneshot(desc, action, false);
 	local_bh_enable();
 	return ret;
 }
 /*
  * Interrupts explicitely requested as threaded interupts want to be
  * preemtible - many of them need to sleep and wait for slow busses to
  * complete.
  */
 static irqreturn_t irq_thread_fn(struct irq_desc *desc,
 		struct irqaction *action)
 {
 	irqreturn_t ret;
 	ret = action->thread_fn(action->irq, action->dev_id);
 	irq_finalize_oneshot(desc, action, false);
 	return ret;
 }
 /*
  * Interrupt handler thread
  */
 static int irq_thread(void *data)
 {
 	static const struct sched_param param = {
 		.sched_priority = MAX_USER_RT_PRIO/2,
 	};
 	struct irqaction *action = data;
 	struct irq_desc *desc = irq_to_desc(action->irq);
 	irqreturn_t (*handler_fn)(struct irq_desc *desc,
 			struct irqaction *action);
 	int wake;
 	if (force_irqthreads & test_bit(IRQTF_FORCED_THREAD,
 					&action->thread_flags))
 		handler_fn = irq_forced_thread_fn;
 	else
 		handler_fn = irq_thread_fn;
 	sched_setscheduler(current, SCHED_FIFO, &param);
 	current->irqaction = action;
 	while (!irq_wait_for_interrupt(action)) {
 		irq_thread_check_affinity(desc, action);
 		atomic_inc(&desc->threads_active);
 		raw_spin_lock_irq(&desc->lock);
 		if (unlikely(irqd_irq_disabled(&desc->irq_data))) {
 			/*
 			 * CHECKME: We might need a dedicated
 			 * IRQ_THREAD_PENDING flag here, which
 			 * retriggers the thread in check_irq_resend()
 			 * but AFAICT IRQS_PENDING should be fine as it
 			 * retriggers the interrupt itself --- tglx
 			 */
 			desc->istate |= IRQS_PENDING;
 			raw_spin_unlock_irq(&desc->lock);
 		} else {
 			irqreturn_t action_ret;
 			raw_spin_unlock_irq(&desc->lock);
 			action_ret = handler_fn(desc, action);
 			if (!noirqdebug)
 				note_interrupt(action->irq, desc, action_ret);
 		}
 		wake = atomic_dec_and_test(&desc->threads_active);
 		if (wake && waitqueue_active(&desc->wait_for_threads))
 			wake_up(&desc->wait_for_threads);
 	}
 	/* Prevent a stale desc->threads_oneshot */
 	irq_finalize_oneshot(desc, action, true);
 	/*
 	 * Clear irqaction. Otherwise exit_irq_thread() would make
 	 * fuzz about an active irq thread going into nirvana.
 	 */
 	current->irqaction = NULL;
 	return 0;
 }
 /*
  * Called from do_exit()
  */
 void exit_irq_thread(void)
 {
 	struct task_struct *tsk = current;
 	struct irq_desc *desc;
 	if (!tsk->irqaction)
 		return;
 	printk(KERN_ERR
 	       "exiting task \"%s\" (%d) is an active IRQ thread (irq %d)\n",
 	       tsk->comm ? tsk->comm : "", tsk->pid, tsk->irqaction->irq);
 	desc = irq_to_desc(tsk->irqaction->irq);
 	/*
 	 * Prevent a stale desc->threads_oneshot. Must be called
 	 * before setting the IRQTF_DIED flag.
 	 */
 	irq_finalize_oneshot(desc, tsk->irqaction, true);
 	/*
 	 * Set the THREAD DIED flag to prevent further wakeups of the
 	 * soon to be gone threaded handler.
 	 */
 	set_bit(IRQTF_DIED, &tsk->irqaction->flags);
 }
 static void irq_setup_forced_threading(struct irqaction *new)
 {
 	if (!force_irqthreads)
 		return;
 	if (new->flags & (IRQF_NO_THREAD | IRQF_PERCPU | IRQF_ONESHOT))
 		return;
 	new->flags |= IRQF_ONESHOT;
 	if (!new->thread_fn) {
 		set_bit(IRQTF_FORCED_THREAD, &new->thread_flags);
 		new->thread_fn = new->handler;
 		new->handler = irq_default_primary_handler;
 	}
 }
 /*
  * Internal function to register an irqaction - typically used to
  * allocate special interrupts that are part of the architecture.
  */
 static int
 __setup_irq(unsigned int irq, struct irq_desc *desc, struct irqaction *new)
 {
 	struct irqaction *old, **old_ptr;
 	const char *old_name = NULL;
 	unsigned long flags, thread_mask = 0;
 	int ret, nested, shared = 0;
 	cpumask_var_t mask;
 	if (!desc)
 		return -EINVAL;
 	if (desc->irq_data.chip == &no_irq_chip)
 		return -ENOSYS;
+	if (!try_module_get(desc->owner))
+		return -ENODEV;
 	/*
 	 * Some drivers like serial.c use request_irq() heavily,
 	 * so we have to be careful not to interfere with a
 	 * running system.
 	 */
 	if (new->flags & IRQF_SAMPLE_RANDOM) {
 		/*
 		 * This function might sleep, we want to call it first,
 		 * outside of the atomic block.
 		 * Yes, this might clear the entropy pool if the wrong
 		 * driver is attempted to be loaded, without actually
 		 * installing a new handler, but is this really a problem,
 		 * only the sysadmin is able to do this.
 		 */
 		rand_initialize_irq(irq);
 	}
 	/*
 	 * Check whether the interrupt nests into another interrupt
 	 * thread.
 	 */
 	nested = irq_settings_is_nested_thread(desc);
 	if (nested) {
-		if (!new->thread_fn)
+		if (!new->thread_fn) {
-			return -EINVAL;
+			ret = -EINVAL;
+			goto out_mput;
+		}
 		/*
 		 * Replace the primary handler which was provided from
 		 * the driver for non nested interrupt handling by the
 		 * dummy function which warns when called.
 		 */
 		new->handler = irq_nested_primary_handler;
 	} else {
 		if (irq_settings_can_thread(desc))
 			irq_setup_forced_threading(new);
 	}
 	/*
 	 * Create a handler thread when a thread function is supplied
 	 * and the interrupt does not nest into another interrupt
 	 * thread.
 	 */
 	if (new->thread_fn && !nested) {
 		struct task_struct *t;
 		t = kthread_create(irq_thread, new, "irq/%d-%s", irq,
 				   new->name);
-		if (IS_ERR(t))
+		if (IS_ERR(t)) {
-			return PTR_ERR(t);
+			ret = PTR_ERR(t);
+			goto out_mput;
+		}
 		/*
 		 * We keep the reference to the task struct even if
 		 * the thread dies to avoid that the interrupt code
 		 * references an already freed task_struct.
 		 */
 		get_task_struct(t);
 		new->thread = t;
 	}
 	if (!alloc_cpumask_var(&mask, GFP_KERNEL)) {
 		ret = -ENOMEM;
 		goto out_thread;
 	}
 	/*
 	 * The following block of code has to be executed atomically
 	 */
 	raw_spin_lock_irqsave(&desc->lock, flags);
 	old_ptr = &desc->action;
 	old = *old_ptr;
 	if (old) {
 		/*
 		 * Can't share interrupts unless both agree to and are
 		 * the same type (level, edge, polarity). So both flag
 		 * fields must have IRQF_SHARED set and the bits which
 		 * set the trigger type must match. Also all must
 		 * agree on ONESHOT.
 		 */
 		if (!((old->flags & new->flags) & IRQF_SHARED) ||
 		    ((old->flags ^ new->flags) & IRQF_TRIGGER_MASK) ||
 		    ((old->flags ^ new->flags) & IRQF_ONESHOT)) {
 			old_name = old->name;
 			goto mismatch;
 		}
 		/* All handlers must agree on per-cpuness */
 		if ((old->flags & IRQF_PERCPU) !=
 		    (new->flags & IRQF_PERCPU))
 			goto mismatch;
 		/* add new interrupt at end of irq queue */
 		do {
 			thread_mask |= old->thread_mask;
 			old_ptr = &old->next;
 			old = *old_ptr;
 		} while (old);
 		shared = 1;
 	}
 	/*
 	 * Setup the thread mask for this irqaction. Unlikely to have
 	 * 32 resp 64 irqs sharing one line, but who knows.
 	 */
 	if (new->flags & IRQF_ONESHOT && thread_mask == ~0UL) {
 		ret = -EBUSY;
 		goto out_mask;
 	}
 	new->thread_mask = 1 << ffz(thread_mask);
 	if (!shared) {
 		init_waitqueue_head(&desc->wait_for_threads);
 		/* Setup the type (level, edge polarity) if configured: */
 		if (new->flags & IRQF_TRIGGER_MASK) {
 			ret = __irq_set_trigger(desc, irq,
 					new->flags & IRQF_TRIGGER_MASK);
 			if (ret)
 				goto out_mask;
 		}
 		desc->istate &= ~(IRQS_AUTODETECT | IRQS_SPURIOUS_DISABLED | \
 				  IRQS_ONESHOT | IRQS_WAITING);
 		irqd_clear(&desc->irq_data, IRQD_IRQ_INPROGRESS);
 		if (new->flags & IRQF_PERCPU) {
 			irqd_set(&desc->irq_data, IRQD_PER_CPU);
 			irq_settings_set_per_cpu(desc);
 		}
 		if (new->flags & IRQF_ONESHOT)
 			desc->istate |= IRQS_ONESHOT;
 		if (irq_settings_can_autoenable(desc))
 			irq_startup(desc);
 		else
 			/* Undo nested disables: */
 			desc->depth = 1;
 		/* Exclude IRQ from balancing if requested */
 		if (new->flags & IRQF_NOBALANCING) {
 			irq_settings_set_no_balancing(desc);
 			irqd_set(&desc->irq_data, IRQD_NO_BALANCING);
 		}
 		/* Set default affinity mask once everything is setup */
 		setup_affinity(irq, desc, mask);
 	} else if (new->flags & IRQF_TRIGGER_MASK) {
 		unsigned int nmsk = new->flags & IRQF_TRIGGER_MASK;
 		unsigned int omsk = irq_settings_get_trigger_mask(desc);
 		if (nmsk != omsk)
 			/* hope the handler works with current  trigger mode */
 			pr_warning("IRQ %d uses trigger mode %u; requested %u\n",
 				   irq, nmsk, omsk);
 	}
 	new->irq = irq;
 	*old_ptr = new;
 	/* Reset broken irq detection when installing new handler */
 	desc->irq_count = 0;
 	desc->irqs_unhandled = 0;
 	/*
 	 * Check whether we disabled the irq via the spurious handler
 	 * before. Reenable it and give it another chance.
 	 */
 	if (shared && (desc->istate & IRQS_SPURIOUS_DISABLED)) {
 		desc->istate &= ~IRQS_SPURIOUS_DISABLED;
 		__enable_irq(desc, irq, false);
 	}
 	raw_spin_unlock_irqrestore(&desc->lock, flags);
 	/*
 	 * Strictly no need to wake it up, but hung_task complains
 	 * when no hard interrupt wakes the thread up.
 	 */
 	if (new->thread)
 		wake_up_process(new->thread);
 	register_irq_proc(irq, desc);
 	new->dir = NULL;
 	register_handler_proc(irq, new);
 	free_cpumask_var(mask);
 	return 0;
 mismatch:
 #ifdef CONFIG_DEBUG_SHIRQ
 	if (!(new->flags & IRQF_PROBE_SHARED)) {
 		printk(KERN_ERR "IRQ handler type mismatch for IRQ %d\n", irq);
 		if (old_name)
 			printk(KERN_ERR "current handler: %s\n", old_name);
 		dump_stack();
 	}
 #endif
 	ret = -EBUSY;
 out_mask:
 	raw_spin_unlock_irqrestore(&desc->lock, flags);
 	free_cpumask_var(mask);
 out_thread:
 	if (new->thread) {
 		struct task_struct *t = new->thread;
 		new->thread = NULL;
 		if (likely(!test_bit(IRQTF_DIED, &new->thread_flags)))
 			kthread_stop(t);
 		put_task_struct(t);
 	}
+out_mput:
+	module_put(desc->owner);
 	return ret;
 }
 /**
  *	setup_irq - setup an interrupt
  *	@irq: Interrupt line to setup
  *	@act: irqaction for the interrupt
  *
  * Used to statically setup interrupts in the early boot process.
  */
 int setup_irq(unsigned int irq, struct irqaction *act)
 {
 	int retval;
 	struct irq_desc *desc = irq_to_desc(irq);
 	chip_bus_lock(desc);
 	retval = __setup_irq(irq, desc, act);
 	chip_bus_sync_unlock(desc);
 	return retval;
 }
 EXPORT_SYMBOL_GPL(setup_irq);
  /*
  * Internal function to unregister an irqaction - used to free
  * regular and special interrupts that are part of the architecture.
  */
 static struct irqaction *__free_irq(unsigned int irq, void *dev_id)
 {
 	struct irq_desc *desc = irq_to_desc(irq);
 	struct irqaction *action, **action_ptr;
 	unsigned long flags;
 	WARN(in_interrupt(), "Trying to free IRQ %d from IRQ context!\n", irq);
 	if (!desc)
 		return NULL;
 	raw_spin_lock_irqsave(&desc->lock, flags);
 	/*
 	 * There can be multiple actions per IRQ descriptor, find the right
 	 * one based on the dev_id:
 	 */
 	action_ptr = &desc->action;
 	for (;;) {
 		action = *action_ptr;
 		if (!action) {
 			WARN(1, "Trying to free already-free IRQ %d\n", irq);
 			raw_spin_unlock_irqrestore(&desc->lock, flags);
 			return NULL;
 		}
 		if (action->dev_id == dev_id)
 			break;
 		action_ptr = &action->next;
 	}
 	/* Found it - now remove it from the list of entries: */
 	*action_ptr = action->next;
 	/* Currently used only by UML, might disappear one day: */
 #ifdef CONFIG_IRQ_RELEASE_METHOD
 	if (desc->irq_data.chip->release)
 		desc->irq_data.chip->release(irq, dev_id);
 #endif
 	/* If this was the last handler, shut down the IRQ line: */
 	if (!desc->action)
 		irq_shutdown(desc);
 #ifdef CONFIG_SMP
 	/* make sure affinity_hint is cleaned up */
 	if (WARN_ON_ONCE(desc->affinity_hint))
 		desc->affinity_hint = NULL;
 #endif
 	raw_spin_unlock_irqrestore(&desc->lock, flags);
 	unregister_handler_proc(irq, action);
 	/* Make sure it's not being used on another CPU: */
 	synchronize_irq(irq);
 #ifdef CONFIG_DEBUG_SHIRQ
 	/*
 	 * It's a shared IRQ -- the driver ought to be prepared for an IRQ
 	 * event to happen even now it's being freed, so let's make sure that
 	 * is so by doing an extra call to the handler ....
 	 *
 	 * ( We do this after actually deregistering it, to make sure that a
 	 *   'real' IRQ doesn't run in * parallel with our fake. )
 	 */
 	if (action->flags & IRQF_SHARED) {
 		local_irq_save(flags);
 		action->handler(irq, dev_id);
 		local_irq_restore(flags);
 	}
 #endif
 	if (action->thread) {
 		if (!test_bit(IRQTF_DIED, &action->thread_flags))
 			kthread_stop(action->thread);
 		put_task_struct(action->thread);
 	}
+	module_put(desc->owner);
 	return action;
 }
 /**
  *	remove_irq - free an interrupt
  *	@irq: Interrupt line to free
  *	@act: irqaction for the interrupt
  *
  * Used to remove interrupts statically setup by the early boot process.
  */
 void remove_irq(unsigned int irq, struct irqaction *act)
 {
 	__free_irq(irq, act->dev_id);
 }
 EXPORT_SYMBOL_GPL(remove_irq);
 /**
  *	free_irq - free an interrupt allocated with request_irq
  *	@irq: Interrupt line to free
  *	@dev_id: Device identity to free
  *
  *	Remove an interrupt handler. The handler is removed and if the
  *	interrupt line is no longer in use by any driver it is disabled.
  *	On a shared IRQ the caller must ensure the interrupt is disabled
  *	on the card it drives before calling this function. The function
  *	does not return until any executing interrupts for this IRQ
  *	have completed.
  *
  *	This function must not be called from interrupt context.
  */
 void free_irq(unsigned int irq, void *dev_id)
 {
 	struct irq_desc *desc = irq_to_desc(irq);
 	if (!desc)
 		return;
 #ifdef CONFIG_SMP
 	if (WARN_ON(desc->affinity_notify))
 		desc->affinity_notify = NULL;
 #endif
 	chip_bus_lock(desc);
 	kfree(__free_irq(irq, dev_id));
 	chip_bus_sync_unlock(desc);
 }
 EXPORT_SYMBOL(free_irq);
 /**
  *	request_threaded_irq - allocate an interrupt line
  *	@irq: Interrupt line to allocate
  *	@handler: Function to be called when the IRQ occurs.
  *		  Primary handler for threaded interrupts
  *		  If NULL and thread_fn != NULL the default
  *		  primary handler is installed
  *	@thread_fn: Function called from the irq handler thread
  *		    If NULL, no irq thread is created
  *	@irqflags: Interrupt type flags
  *	@devname: An ascii name for the claiming device
  *	@dev_id: A cookie passed back to the handler function
  *
  *	This call allocates interrupt resources and enables the
  *	interrupt line and IRQ handling. From the point this
  *	call is made your handler function may be invoked. Since
  *	your handler function must clear any interrupt the board
  *	raises, you must take care both to initialise your hardware
  *	and to set up the interrupt handler in the right order.
  *
  *	If you want to set up a threaded irq handler for your device
  *	then you need to supply @handler and @thread_fn. @handler ist
  *	still called in hard interrupt context and has to check
  *	whether the interrupt originates from the device. If yes it
  *	needs to disable the interrupt on the device and return
  *	IRQ_WAKE_THREAD which will wake up the handler thread and run
  *	@thread_fn. This split handler design is necessary to support
  *	shared interrupts.
  *
  *	Dev_id must be globally unique. Normally the address of the
  *	device data structure is used as the cookie. Since the handler
  *	receives this value it makes sense to use it.
  *
  *	If your interrupt is shared you must pass a non NULL dev_id
  *	as this is required when freeing the interrupt.
  *
  *	Flags:
  *
  *	IRQF_SHARED		Interrupt is shared
  *	IRQF_SAMPLE_RANDOM	The interrupt can be used for entropy
  *	IRQF_TRIGGER_*		Specify active edge(s) or level
  *
  */
 int request_threaded_irq(unsigned int irq, irq_handler_t handler,
 			 irq_handler_t thread_fn, unsigned long irqflags,
 			 const char *devname, void *dev_id)
 {
 	struct irqaction *action;
 	struct irq_desc *desc;
 	int retval;
 	/*
 	 * Sanity-check: shared interrupts must pass in a real dev-ID,
 	 * otherwise we'll have trouble later trying to figure out
 	 * which interrupt is which (messes up the interrupt freeing
 	 * logic etc).
 	 */
 	if ((irqflags & IRQF_SHARED) && !dev_id)
 		return -EINVAL;
 	desc = irq_to_desc(irq);
 	if (!desc)
 		return -EINVAL;
 	if (!irq_settings_can_request(desc))
 		return -EINVAL;
 	if (!handler) {
 		if (!thread_fn)
 			return -EINVAL;
 		handler = irq_default_primary_handler;
+		irqflags |= IRQF_ONESHOT;
 	}
 	action = kzalloc(sizeof(struct irqaction), GFP_KERNEL);
 	if (!action)
 		return -ENOMEM;
 	action->handler = handler;
 	action->thread_fn = thread_fn;
 	action->flags = irqflags;
 	action->name = devname;
 	action->dev_id = dev_id;
 	chip_bus_lock(desc);
 	retval = __setup_irq(irq, desc, action);
 	chip_bus_sync_unlock(desc);
 	if (retval)
 		kfree(action);
 #ifdef CONFIG_DEBUG_SHIRQ_FIXME
 	if (!retval && (irqflags & IRQF_SHARED)) {
 		/*
 		 * It's a shared IRQ -- the driver ought to be prepared for it
 		 * to happen immediately, so let's make sure....
 		 * We disable the irq to make sure that a 'real' IRQ doesn't
 		 * run in parallel with our fake.
 		 */
 		unsigned long flags;
 		disable_irq(irq);
 		local_irq_save(flags);
 		handler(irq, dev_id);
 		local_irq_restore(flags);
 		enable_irq(irq);
 	}
 #endif
 	return retval;
 }
 EXPORT_SYMBOL(request_threaded_irq);
 /**
  *	request_any_context_irq - allocate an interrupt line
  *	@irq: Interrupt line to allocate
  *	@handler: Function to be called when the IRQ occurs.
  *		  Threaded handler for threaded interrupts.
  *	@flags: Interrupt type flags
  *	@name: An ascii name for the claiming device
  *	@dev_id: A cookie passed back to the handler function
  *
  *	This call allocates interrupt resources and enables the
  *	interrupt line and IRQ handling. It selects either a
  *	hardirq or threaded handling method depending on the
  *	context.
  *
  *	On failure, it returns a negative value. On success,
  *	it returns either IRQC_IS_HARDIRQ or IRQC_IS_NESTED.
  */
 int request_any_context_irq(unsigned int irq, irq_handler_t handler,
 			    unsigned long flags, const char *name, void *dev_id)
 {
 	struct irq_desc *desc = irq_to_desc(irq);
 	int ret;
 	if (!desc)
 		return -EINVAL;
 	if (irq_settings_is_nested_thread(desc)) {
 		ret = request_threaded_irq(irq, NULL, handler,
 					   flags, name, dev_id);
 		return !ret ? IRQC_IS_NESTED : ret;
 	}
 	ret = request_irq(irq, handler, flags, name, dev_id);
 	return !ret ? IRQC_IS_HARDIRQ : ret;
 }
 EXPORT_SYMBOL_GPL(request_any_context_irq);