Commit 998350632344970f28fbbf83b7c669db8dd0ead6
1 parent
a36dd79796
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master
arm:omap:am335x: fix gpio number for mmc1 cd & wp
GPIO numbers were updated while moving from alpha to beta version of EVM. This patch corercts the GPIO numbers. MMC1_WP --> GPIO(1, 29) MMC1_CD --> GPIO(2, 2) Signed-off-by: Hebbar, Gururaja <gururaja.hebbar@ti.com>
Showing 1 changed file with 2 additions and 2 deletions Inline Diff
arch/arm/mach-omap2/board-am335xevm.c
1 | /* | 1 | /* |
2 | * Code for AM335X EVM. | 2 | * Code for AM335X EVM. |
3 | * | 3 | * |
4 | * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/ | 4 | * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/ |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or | 6 | * This program is free software; you can redistribute it and/or |
7 | * modify it under the terms of the GNU General Public License as | 7 | * modify it under the terms of the GNU General Public License as |
8 | * published by the Free Software Foundation version 2. | 8 | * published by the Free Software Foundation version 2. |
9 | * | 9 | * |
10 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | 10 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any |
11 | * kind, whether express or implied; without even the implied warranty | 11 | * kind, whether express or implied; without even the implied warranty |
12 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | 12 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
13 | * GNU General Public License for more details. | 13 | * GNU General Public License for more details. |
14 | */ | 14 | */ |
15 | #include <linux/kernel.h> | 15 | #include <linux/kernel.h> |
16 | #include <linux/init.h> | 16 | #include <linux/init.h> |
17 | #include <linux/i2c.h> | 17 | #include <linux/i2c.h> |
18 | #include <linux/i2c/at24.h> | 18 | #include <linux/i2c/at24.h> |
19 | #include <linux/phy.h> | 19 | #include <linux/phy.h> |
20 | #include <linux/gpio.h> | 20 | #include <linux/gpio.h> |
21 | #include <linux/spi/spi.h> | 21 | #include <linux/spi/spi.h> |
22 | #include <linux/spi/flash.h> | 22 | #include <linux/spi/flash.h> |
23 | #include <linux/input.h> | 23 | #include <linux/input.h> |
24 | #include <linux/gpio_keys.h> | 24 | #include <linux/gpio_keys.h> |
25 | #include <linux/input/matrix_keypad.h> | 25 | #include <linux/input/matrix_keypad.h> |
26 | #include <linux/mtd/mtd.h> | 26 | #include <linux/mtd/mtd.h> |
27 | #include <linux/mtd/nand.h> | 27 | #include <linux/mtd/nand.h> |
28 | #include <linux/mtd/partitions.h> | 28 | #include <linux/mtd/partitions.h> |
29 | #include <linux/platform_device.h> | 29 | #include <linux/platform_device.h> |
30 | #include <linux/clk.h> | 30 | #include <linux/clk.h> |
31 | #include <linux/err.h> | 31 | #include <linux/err.h> |
32 | #include <linux/wl12xx.h> | 32 | #include <linux/wl12xx.h> |
33 | #include <linux/ethtool.h> | 33 | #include <linux/ethtool.h> |
34 | #include <linux/mfd/tps65910.h> | 34 | #include <linux/mfd/tps65910.h> |
35 | 35 | ||
36 | /* LCD controller is similar to DA850 */ | 36 | /* LCD controller is similar to DA850 */ |
37 | #include <video/da8xx-fb.h> | 37 | #include <video/da8xx-fb.h> |
38 | 38 | ||
39 | #include <mach/hardware.h> | 39 | #include <mach/hardware.h> |
40 | #include <mach/board-am335xevm.h> | 40 | #include <mach/board-am335xevm.h> |
41 | 41 | ||
42 | #include <asm/mach-types.h> | 42 | #include <asm/mach-types.h> |
43 | #include <asm/mach/arch.h> | 43 | #include <asm/mach/arch.h> |
44 | #include <asm/mach/map.h> | 44 | #include <asm/mach/map.h> |
45 | #include <asm/hardware/asp.h> | 45 | #include <asm/hardware/asp.h> |
46 | 46 | ||
47 | #include <plat/irqs.h> | 47 | #include <plat/irqs.h> |
48 | #include <plat/board.h> | 48 | #include <plat/board.h> |
49 | #include <plat/common.h> | 49 | #include <plat/common.h> |
50 | #include <plat/lcdc.h> | 50 | #include <plat/lcdc.h> |
51 | #include <plat/usb.h> | 51 | #include <plat/usb.h> |
52 | #include <plat/mmc.h> | 52 | #include <plat/mmc.h> |
53 | 53 | ||
54 | #include "board-flash.h" | 54 | #include "board-flash.h" |
55 | #include "cpuidle33xx.h" | 55 | #include "cpuidle33xx.h" |
56 | #include "mux.h" | 56 | #include "mux.h" |
57 | #include "devices.h" | 57 | #include "devices.h" |
58 | #include "hsmmc.h" | 58 | #include "hsmmc.h" |
59 | 59 | ||
60 | /* TLK PHY IDs */ | 60 | /* TLK PHY IDs */ |
61 | #define TLK110_PHY_ID 0x2000A201 | 61 | #define TLK110_PHY_ID 0x2000A201 |
62 | #define TLK110_PHY_MASK 0xfffffff0 | 62 | #define TLK110_PHY_MASK 0xfffffff0 |
63 | 63 | ||
64 | /* BBB PHY IDs */ | 64 | /* BBB PHY IDs */ |
65 | #define BBB_PHY_ID 0x7c0f1 | 65 | #define BBB_PHY_ID 0x7c0f1 |
66 | #define BBB_PHY_MASK 0xfffffffe | 66 | #define BBB_PHY_MASK 0xfffffffe |
67 | 67 | ||
68 | /* TLK110 PHY register offsets */ | 68 | /* TLK110 PHY register offsets */ |
69 | #define TLK110_COARSEGAIN_REG 0x00A3 | 69 | #define TLK110_COARSEGAIN_REG 0x00A3 |
70 | #define TLK110_LPFHPF_REG 0x00AC | 70 | #define TLK110_LPFHPF_REG 0x00AC |
71 | #define TLK110_SPAREANALOG_REG 0x00B9 | 71 | #define TLK110_SPAREANALOG_REG 0x00B9 |
72 | #define TLK110_VRCR_REG 0x00D0 | 72 | #define TLK110_VRCR_REG 0x00D0 |
73 | #define TLK110_SETFFE_REG 0x0107 | 73 | #define TLK110_SETFFE_REG 0x0107 |
74 | #define TLK110_FTSP_REG 0x0154 | 74 | #define TLK110_FTSP_REG 0x0154 |
75 | #define TLK110_ALFATPIDL_REG 0x002A | 75 | #define TLK110_ALFATPIDL_REG 0x002A |
76 | #define TLK110_PSCOEF21_REG 0x0096 | 76 | #define TLK110_PSCOEF21_REG 0x0096 |
77 | #define TLK110_PSCOEF3_REG 0x0097 | 77 | #define TLK110_PSCOEF3_REG 0x0097 |
78 | #define TLK110_ALFAFACTOR1_REG 0x002C | 78 | #define TLK110_ALFAFACTOR1_REG 0x002C |
79 | #define TLK110_ALFAFACTOR2_REG 0x0023 | 79 | #define TLK110_ALFAFACTOR2_REG 0x0023 |
80 | #define TLK110_CFGPS_REG 0x0095 | 80 | #define TLK110_CFGPS_REG 0x0095 |
81 | #define TLK110_FTSPTXGAIN_REG 0x0150 | 81 | #define TLK110_FTSPTXGAIN_REG 0x0150 |
82 | #define TLK110_SWSCR3_REG 0x000B | 82 | #define TLK110_SWSCR3_REG 0x000B |
83 | #define TLK110_SCFALLBACK_REG 0x0040 | 83 | #define TLK110_SCFALLBACK_REG 0x0040 |
84 | #define TLK110_PHYRCR_REG 0x001F | 84 | #define TLK110_PHYRCR_REG 0x001F |
85 | 85 | ||
86 | /* TLK110 register writes values */ | 86 | /* TLK110 register writes values */ |
87 | #define TLK110_COARSEGAIN_VAL 0x0000 | 87 | #define TLK110_COARSEGAIN_VAL 0x0000 |
88 | #define TLK110_LPFHPF_VAL 0x8000 | 88 | #define TLK110_LPFHPF_VAL 0x8000 |
89 | #define TLK110_SPANALOG_VAL 0x0000 | 89 | #define TLK110_SPANALOG_VAL 0x0000 |
90 | #define TLK110_VRCR_VAL 0x0008 | 90 | #define TLK110_VRCR_VAL 0x0008 |
91 | #define TLK110_SETFFE_VAL 0x0605 | 91 | #define TLK110_SETFFE_VAL 0x0605 |
92 | #define TLK110_FTSP_VAL 0x0255 | 92 | #define TLK110_FTSP_VAL 0x0255 |
93 | #define TLK110_ALFATPIDL_VAL 0x7998 | 93 | #define TLK110_ALFATPIDL_VAL 0x7998 |
94 | #define TLK110_PSCOEF21_VAL 0x3A20 | 94 | #define TLK110_PSCOEF21_VAL 0x3A20 |
95 | #define TLK110_PSCOEF3_VAL 0x003F | 95 | #define TLK110_PSCOEF3_VAL 0x003F |
96 | #define TLK110_ALFACTOR1_VAL 0xFF80 | 96 | #define TLK110_ALFACTOR1_VAL 0xFF80 |
97 | #define TLK110_ALFACTOR2_VAL 0x021C | 97 | #define TLK110_ALFACTOR2_VAL 0x021C |
98 | #define TLK110_CFGPS_VAL 0x0000 | 98 | #define TLK110_CFGPS_VAL 0x0000 |
99 | #define TLK110_FTSPTXGAIN_VAL 0x6A88 | 99 | #define TLK110_FTSPTXGAIN_VAL 0x6A88 |
100 | #define TLK110_SWSCR3_VAL 0x0000 | 100 | #define TLK110_SWSCR3_VAL 0x0000 |
101 | #define TLK110_SCFALLBACK_VAL 0xC11D | 101 | #define TLK110_SCFALLBACK_VAL 0xC11D |
102 | #define TLK110_PHYRCR_VAL 0x4000 | 102 | #define TLK110_PHYRCR_VAL 0x4000 |
103 | 103 | ||
104 | #ifdef CONFIG_TLK110_WORKAROUND | 104 | #ifdef CONFIG_TLK110_WORKAROUND |
105 | #define am335x_tlk110_phy_init()\ | 105 | #define am335x_tlk110_phy_init()\ |
106 | do { \ | 106 | do { \ |
107 | phy_register_fixup_for_uid(TLK110_PHY_ID,\ | 107 | phy_register_fixup_for_uid(TLK110_PHY_ID,\ |
108 | TLK110_PHY_MASK,\ | 108 | TLK110_PHY_MASK,\ |
109 | am335x_tlk110_phy_fixup);\ | 109 | am335x_tlk110_phy_fixup);\ |
110 | } while (0); | 110 | } while (0); |
111 | #else | 111 | #else |
112 | #define am335x_tlk110_phy_init() do { } while (0); | 112 | #define am335x_tlk110_phy_init() do { } while (0); |
113 | #endif | 113 | #endif |
114 | 114 | ||
115 | /* Convert GPIO signal to GPIO pin number */ | 115 | /* Convert GPIO signal to GPIO pin number */ |
116 | #define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio)) | 116 | #define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio)) |
117 | 117 | ||
118 | static const struct display_panel disp_panel = { | 118 | static const struct display_panel disp_panel = { |
119 | WVGA, | 119 | WVGA, |
120 | 32, | 120 | 32, |
121 | 32, | 121 | 32, |
122 | COLOR_ACTIVE, | 122 | COLOR_ACTIVE, |
123 | }; | 123 | }; |
124 | 124 | ||
125 | static struct lcd_ctrl_config lcd_cfg = { | 125 | static struct lcd_ctrl_config lcd_cfg = { |
126 | &disp_panel, | 126 | &disp_panel, |
127 | .ac_bias = 255, | 127 | .ac_bias = 255, |
128 | .ac_bias_intrpt = 0, | 128 | .ac_bias_intrpt = 0, |
129 | .dma_burst_sz = 16, | 129 | .dma_burst_sz = 16, |
130 | .bpp = 32, | 130 | .bpp = 32, |
131 | .fdd = 0x80, | 131 | .fdd = 0x80, |
132 | .tft_alt_mode = 0, | 132 | .tft_alt_mode = 0, |
133 | .stn_565_mode = 0, | 133 | .stn_565_mode = 0, |
134 | .mono_8bit_mode = 0, | 134 | .mono_8bit_mode = 0, |
135 | .invert_line_clock = 1, | 135 | .invert_line_clock = 1, |
136 | .invert_frm_clock = 1, | 136 | .invert_frm_clock = 1, |
137 | .sync_edge = 0, | 137 | .sync_edge = 0, |
138 | .sync_ctrl = 1, | 138 | .sync_ctrl = 1, |
139 | .raster_order = 0, | 139 | .raster_order = 0, |
140 | }; | 140 | }; |
141 | 141 | ||
142 | struct da8xx_lcdc_platform_data TFC_S9700RTWV35TR_01B_pdata = { | 142 | struct da8xx_lcdc_platform_data TFC_S9700RTWV35TR_01B_pdata = { |
143 | .manu_name = "ThreeFive", | 143 | .manu_name = "ThreeFive", |
144 | .controller_data = &lcd_cfg, | 144 | .controller_data = &lcd_cfg, |
145 | .type = "TFC_S9700RTWV35TR_01B", | 145 | .type = "TFC_S9700RTWV35TR_01B", |
146 | }; | 146 | }; |
147 | 147 | ||
148 | /* TSc controller */ | 148 | /* TSc controller */ |
149 | #include <linux/input/ti_tscadc.h> | 149 | #include <linux/input/ti_tscadc.h> |
150 | #include <linux/lis3lv02d.h> | 150 | #include <linux/lis3lv02d.h> |
151 | 151 | ||
152 | static struct resource tsc_resources[] = { | 152 | static struct resource tsc_resources[] = { |
153 | [0] = { | 153 | [0] = { |
154 | .start = AM33XX_TSC_BASE, | 154 | .start = AM33XX_TSC_BASE, |
155 | .end = AM33XX_TSC_BASE + SZ_8K - 1, | 155 | .end = AM33XX_TSC_BASE + SZ_8K - 1, |
156 | .flags = IORESOURCE_MEM, | 156 | .flags = IORESOURCE_MEM, |
157 | }, | 157 | }, |
158 | [1] = { | 158 | [1] = { |
159 | .start = AM33XX_IRQ_ADC_GEN, | 159 | .start = AM33XX_IRQ_ADC_GEN, |
160 | .end = AM33XX_IRQ_ADC_GEN, | 160 | .end = AM33XX_IRQ_ADC_GEN, |
161 | .flags = IORESOURCE_IRQ, | 161 | .flags = IORESOURCE_IRQ, |
162 | }, | 162 | }, |
163 | }; | 163 | }; |
164 | 164 | ||
165 | static struct tsc_data am335x_touchscreen_data = { | 165 | static struct tsc_data am335x_touchscreen_data = { |
166 | .wires = 4, | 166 | .wires = 4, |
167 | .x_plate_resistance = 200, | 167 | .x_plate_resistance = 200, |
168 | }; | 168 | }; |
169 | 169 | ||
170 | static struct platform_device tsc_device = { | 170 | static struct platform_device tsc_device = { |
171 | .name = "tsc", | 171 | .name = "tsc", |
172 | .id = -1, | 172 | .id = -1, |
173 | .dev = { | 173 | .dev = { |
174 | .platform_data = &am335x_touchscreen_data, | 174 | .platform_data = &am335x_touchscreen_data, |
175 | }, | 175 | }, |
176 | .num_resources = ARRAY_SIZE(tsc_resources), | 176 | .num_resources = ARRAY_SIZE(tsc_resources), |
177 | .resource = tsc_resources, | 177 | .resource = tsc_resources, |
178 | }; | 178 | }; |
179 | 179 | ||
180 | static u8 am335x_iis_serializer_direction1[] = { | 180 | static u8 am335x_iis_serializer_direction1[] = { |
181 | INACTIVE_MODE, INACTIVE_MODE, TX_MODE, RX_MODE, | 181 | INACTIVE_MODE, INACTIVE_MODE, TX_MODE, RX_MODE, |
182 | INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, | 182 | INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, |
183 | INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, | 183 | INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, |
184 | INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, | 184 | INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, |
185 | }; | 185 | }; |
186 | 186 | ||
187 | static struct snd_platform_data am335x_evm_snd_data1 = { | 187 | static struct snd_platform_data am335x_evm_snd_data1 = { |
188 | .tx_dma_offset = 0x46400000, /* McASP1 */ | 188 | .tx_dma_offset = 0x46400000, /* McASP1 */ |
189 | .rx_dma_offset = 0x46400000, | 189 | .rx_dma_offset = 0x46400000, |
190 | .op_mode = DAVINCI_MCASP_IIS_MODE, | 190 | .op_mode = DAVINCI_MCASP_IIS_MODE, |
191 | .num_serializer = ARRAY_SIZE(am335x_iis_serializer_direction1), | 191 | .num_serializer = ARRAY_SIZE(am335x_iis_serializer_direction1), |
192 | .tdm_slots = 2, | 192 | .tdm_slots = 2, |
193 | .serial_dir = am335x_iis_serializer_direction1, | 193 | .serial_dir = am335x_iis_serializer_direction1, |
194 | .asp_chan_q = EVENTQ_2, | 194 | .asp_chan_q = EVENTQ_2, |
195 | .version = MCASP_VERSION_3, | 195 | .version = MCASP_VERSION_3, |
196 | .txnumevt = 1, | 196 | .txnumevt = 1, |
197 | .rxnumevt = 1, | 197 | .rxnumevt = 1, |
198 | }; | 198 | }; |
199 | 199 | ||
200 | static struct omap2_hsmmc_info am335x_mmc[] __initdata = { | 200 | static struct omap2_hsmmc_info am335x_mmc[] __initdata = { |
201 | { | 201 | { |
202 | .mmc = 1, | 202 | .mmc = 1, |
203 | .caps = MMC_CAP_4_BIT_DATA, | 203 | .caps = MMC_CAP_4_BIT_DATA, |
204 | .gpio_cd = GPIO_TO_PIN(0, 6), | 204 | .gpio_cd = GPIO_TO_PIN(0, 6), |
205 | .gpio_wp = GPIO_TO_PIN(3, 18), | 205 | .gpio_wp = GPIO_TO_PIN(3, 18), |
206 | .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, /* 3V3 */ | 206 | .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, /* 3V3 */ |
207 | }, | 207 | }, |
208 | { | 208 | { |
209 | .mmc = 0, /* will be set at runtime */ | 209 | .mmc = 0, /* will be set at runtime */ |
210 | }, | 210 | }, |
211 | { | 211 | { |
212 | .mmc = 0, /* will be set at runtime */ | 212 | .mmc = 0, /* will be set at runtime */ |
213 | }, | 213 | }, |
214 | {} /* Terminator */ | 214 | {} /* Terminator */ |
215 | }; | 215 | }; |
216 | 216 | ||
217 | 217 | ||
218 | #ifdef CONFIG_OMAP_MUX | 218 | #ifdef CONFIG_OMAP_MUX |
219 | static struct omap_board_mux board_mux[] __initdata = { | 219 | static struct omap_board_mux board_mux[] __initdata = { |
220 | AM33XX_MUX(I2C0_SDA, OMAP_MUX_MODE0 | AM33XX_SLEWCTRL_SLOW | | 220 | AM33XX_MUX(I2C0_SDA, OMAP_MUX_MODE0 | AM33XX_SLEWCTRL_SLOW | |
221 | AM33XX_INPUT_EN | AM33XX_PIN_OUTPUT), | 221 | AM33XX_INPUT_EN | AM33XX_PIN_OUTPUT), |
222 | AM33XX_MUX(I2C0_SCL, OMAP_MUX_MODE0 | AM33XX_SLEWCTRL_SLOW | | 222 | AM33XX_MUX(I2C0_SCL, OMAP_MUX_MODE0 | AM33XX_SLEWCTRL_SLOW | |
223 | AM33XX_INPUT_EN | AM33XX_PIN_OUTPUT), | 223 | AM33XX_INPUT_EN | AM33XX_PIN_OUTPUT), |
224 | { .reg_offset = OMAP_MUX_TERMINATOR }, | 224 | { .reg_offset = OMAP_MUX_TERMINATOR }, |
225 | }; | 225 | }; |
226 | #else | 226 | #else |
227 | #define board_mux NULL | 227 | #define board_mux NULL |
228 | #endif | 228 | #endif |
229 | 229 | ||
230 | /* module pin mux structure */ | 230 | /* module pin mux structure */ |
231 | struct pinmux_config { | 231 | struct pinmux_config { |
232 | const char *string_name; /* signal name format */ | 232 | const char *string_name; /* signal name format */ |
233 | int val; /* Options for the mux register value */ | 233 | int val; /* Options for the mux register value */ |
234 | }; | 234 | }; |
235 | 235 | ||
236 | struct evm_dev_cfg { | 236 | struct evm_dev_cfg { |
237 | void (*device_init)(int evm_id, int profile); | 237 | void (*device_init)(int evm_id, int profile); |
238 | 238 | ||
239 | /* | 239 | /* |
240 | * If the device is required on both baseboard & daughter board (ex i2c), | 240 | * If the device is required on both baseboard & daughter board (ex i2c), |
241 | * specify DEV_ON_BASEBOARD | 241 | * specify DEV_ON_BASEBOARD |
242 | */ | 242 | */ |
243 | #define DEV_ON_BASEBOARD 0 | 243 | #define DEV_ON_BASEBOARD 0 |
244 | #define DEV_ON_DGHTR_BRD 1 | 244 | #define DEV_ON_DGHTR_BRD 1 |
245 | u32 device_on; | 245 | u32 device_on; |
246 | 246 | ||
247 | u32 profile; /* Profiles (0-7) in which the module is present */ | 247 | u32 profile; /* Profiles (0-7) in which the module is present */ |
248 | }; | 248 | }; |
249 | 249 | ||
250 | /* AM335X - CPLD Register Offsets */ | 250 | /* AM335X - CPLD Register Offsets */ |
251 | #define CPLD_DEVICE_HDR 0x00 /* CPLD Header */ | 251 | #define CPLD_DEVICE_HDR 0x00 /* CPLD Header */ |
252 | #define CPLD_DEVICE_ID 0x04 /* CPLD identification */ | 252 | #define CPLD_DEVICE_ID 0x04 /* CPLD identification */ |
253 | #define CPLD_DEVICE_REV 0x0C /* Revision of the CPLD code */ | 253 | #define CPLD_DEVICE_REV 0x0C /* Revision of the CPLD code */ |
254 | #define CPLD_CFG_REG 0x10 /* Configuration Register */ | 254 | #define CPLD_CFG_REG 0x10 /* Configuration Register */ |
255 | 255 | ||
256 | static struct i2c_client *cpld_client; | 256 | static struct i2c_client *cpld_client; |
257 | 257 | ||
258 | static u32 am335x_evm_id; | 258 | static u32 am335x_evm_id; |
259 | 259 | ||
260 | static struct omap_board_config_kernel am335x_evm_config[] __initdata = { | 260 | static struct omap_board_config_kernel am335x_evm_config[] __initdata = { |
261 | }; | 261 | }; |
262 | 262 | ||
263 | /* | 263 | /* |
264 | * EVM Config held in On-Board eeprom device. | 264 | * EVM Config held in On-Board eeprom device. |
265 | * | 265 | * |
266 | * Header Format | 266 | * Header Format |
267 | * | 267 | * |
268 | * Name Size Contents | 268 | * Name Size Contents |
269 | * (Bytes) | 269 | * (Bytes) |
270 | *------------------------------------------------------------- | 270 | *------------------------------------------------------------- |
271 | * Header 4 0xAA, 0x55, 0x33, 0xEE | 271 | * Header 4 0xAA, 0x55, 0x33, 0xEE |
272 | * | 272 | * |
273 | * Board Name 8 Name for board in ASCII. | 273 | * Board Name 8 Name for board in ASCII. |
274 | * example "A33515BB" = "AM335X | 274 | * example "A33515BB" = "AM335X |
275 | Low Cost EVM board" | 275 | Low Cost EVM board" |
276 | * | 276 | * |
277 | * Version 4 Hardware version code for board in | 277 | * Version 4 Hardware version code for board in |
278 | * in ASCII. "1.0A" = rev.01.0A | 278 | * in ASCII. "1.0A" = rev.01.0A |
279 | * | 279 | * |
280 | * Serial Number 12 Serial number of the board. This is a 12 | 280 | * Serial Number 12 Serial number of the board. This is a 12 |
281 | * character string which is WWYY4P16nnnn, where | 281 | * character string which is WWYY4P16nnnn, where |
282 | * WW = 2 digit week of the year of production | 282 | * WW = 2 digit week of the year of production |
283 | * YY = 2 digit year of production | 283 | * YY = 2 digit year of production |
284 | * nnnn = incrementing board number | 284 | * nnnn = incrementing board number |
285 | * | 285 | * |
286 | * Configuration option 32 Codes(TBD) to show the configuration | 286 | * Configuration option 32 Codes(TBD) to show the configuration |
287 | * setup on this board. | 287 | * setup on this board. |
288 | * | 288 | * |
289 | * Available 32720 Available space for other non-volatile | 289 | * Available 32720 Available space for other non-volatile |
290 | * data. | 290 | * data. |
291 | */ | 291 | */ |
292 | struct am335x_evm_eeprom_config { | 292 | struct am335x_evm_eeprom_config { |
293 | u32 header; | 293 | u32 header; |
294 | u8 name[8]; | 294 | u8 name[8]; |
295 | char version[4]; | 295 | char version[4]; |
296 | u8 serial[12]; | 296 | u8 serial[12]; |
297 | u8 opt[32]; | 297 | u8 opt[32]; |
298 | }; | 298 | }; |
299 | 299 | ||
300 | static struct am335x_evm_eeprom_config config; | 300 | static struct am335x_evm_eeprom_config config; |
301 | static bool daughter_brd_detected; | 301 | static bool daughter_brd_detected; |
302 | 302 | ||
303 | #define GP_EVM_REV_IS_1_0 0x1 | 303 | #define GP_EVM_REV_IS_1_0 0x1 |
304 | #define GP_EVM_REV_IS_1_1A 0x2 | 304 | #define GP_EVM_REV_IS_1_1A 0x2 |
305 | #define GP_EVM_REV_IS_UNKNOWN 0xFF | 305 | #define GP_EVM_REV_IS_UNKNOWN 0xFF |
306 | static unsigned int gp_evm_revision = GP_EVM_REV_IS_UNKNOWN; | 306 | static unsigned int gp_evm_revision = GP_EVM_REV_IS_UNKNOWN; |
307 | unsigned int gigabit_enable = 1; | 307 | unsigned int gigabit_enable = 1; |
308 | 308 | ||
309 | #define EEPROM_MAC_ADDRESS_OFFSET 60 /* 4+8+4+12+32 */ | 309 | #define EEPROM_MAC_ADDRESS_OFFSET 60 /* 4+8+4+12+32 */ |
310 | #define EEPROM_NO_OF_MAC_ADDR 3 | 310 | #define EEPROM_NO_OF_MAC_ADDR 3 |
311 | static char am335x_mac_addr[EEPROM_NO_OF_MAC_ADDR][ETH_ALEN]; | 311 | static char am335x_mac_addr[EEPROM_NO_OF_MAC_ADDR][ETH_ALEN]; |
312 | 312 | ||
313 | #define AM335X_EEPROM_HEADER 0xEE3355AA | 313 | #define AM335X_EEPROM_HEADER 0xEE3355AA |
314 | 314 | ||
315 | /* current profile if exists else PROFILE_0 on error */ | 315 | /* current profile if exists else PROFILE_0 on error */ |
316 | static u32 am335x_get_profile_selection(void) | 316 | static u32 am335x_get_profile_selection(void) |
317 | { | 317 | { |
318 | int val = 0; | 318 | int val = 0; |
319 | 319 | ||
320 | if (!cpld_client) | 320 | if (!cpld_client) |
321 | /* error checking is not done in func's calling this routine. | 321 | /* error checking is not done in func's calling this routine. |
322 | so return profile 0 on error */ | 322 | so return profile 0 on error */ |
323 | return 0; | 323 | return 0; |
324 | 324 | ||
325 | val = i2c_smbus_read_word_data(cpld_client, CPLD_CFG_REG); | 325 | val = i2c_smbus_read_word_data(cpld_client, CPLD_CFG_REG); |
326 | if (val < 0) | 326 | if (val < 0) |
327 | return 0; /* default to Profile 0 on Error */ | 327 | return 0; /* default to Profile 0 on Error */ |
328 | else | 328 | else |
329 | return val & 0x7; | 329 | return val & 0x7; |
330 | } | 330 | } |
331 | 331 | ||
332 | /* Module pin mux for LCDC */ | 332 | /* Module pin mux for LCDC */ |
333 | static struct pinmux_config lcdc_pin_mux[] = { | 333 | static struct pinmux_config lcdc_pin_mux[] = { |
334 | {"lcd_data0.lcd_data0", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | 334 | {"lcd_data0.lcd_data0", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT |
335 | | AM33XX_PULL_DISA}, | 335 | | AM33XX_PULL_DISA}, |
336 | {"lcd_data1.lcd_data1", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | 336 | {"lcd_data1.lcd_data1", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT |
337 | | AM33XX_PULL_DISA}, | 337 | | AM33XX_PULL_DISA}, |
338 | {"lcd_data2.lcd_data2", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | 338 | {"lcd_data2.lcd_data2", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT |
339 | | AM33XX_PULL_DISA}, | 339 | | AM33XX_PULL_DISA}, |
340 | {"lcd_data3.lcd_data3", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | 340 | {"lcd_data3.lcd_data3", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT |
341 | | AM33XX_PULL_DISA}, | 341 | | AM33XX_PULL_DISA}, |
342 | {"lcd_data4.lcd_data4", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | 342 | {"lcd_data4.lcd_data4", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT |
343 | | AM33XX_PULL_DISA}, | 343 | | AM33XX_PULL_DISA}, |
344 | {"lcd_data5.lcd_data5", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | 344 | {"lcd_data5.lcd_data5", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT |
345 | | AM33XX_PULL_DISA}, | 345 | | AM33XX_PULL_DISA}, |
346 | {"lcd_data6.lcd_data6", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | 346 | {"lcd_data6.lcd_data6", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT |
347 | | AM33XX_PULL_DISA}, | 347 | | AM33XX_PULL_DISA}, |
348 | {"lcd_data7.lcd_data7", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | 348 | {"lcd_data7.lcd_data7", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT |
349 | | AM33XX_PULL_DISA}, | 349 | | AM33XX_PULL_DISA}, |
350 | {"lcd_data8.lcd_data8", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | 350 | {"lcd_data8.lcd_data8", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT |
351 | | AM33XX_PULL_DISA}, | 351 | | AM33XX_PULL_DISA}, |
352 | {"lcd_data9.lcd_data9", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | 352 | {"lcd_data9.lcd_data9", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT |
353 | | AM33XX_PULL_DISA}, | 353 | | AM33XX_PULL_DISA}, |
354 | {"lcd_data10.lcd_data10", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | 354 | {"lcd_data10.lcd_data10", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT |
355 | | AM33XX_PULL_DISA}, | 355 | | AM33XX_PULL_DISA}, |
356 | {"lcd_data11.lcd_data11", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | 356 | {"lcd_data11.lcd_data11", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT |
357 | | AM33XX_PULL_DISA}, | 357 | | AM33XX_PULL_DISA}, |
358 | {"lcd_data12.lcd_data12", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | 358 | {"lcd_data12.lcd_data12", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT |
359 | | AM33XX_PULL_DISA}, | 359 | | AM33XX_PULL_DISA}, |
360 | {"lcd_data13.lcd_data13", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | 360 | {"lcd_data13.lcd_data13", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT |
361 | | AM33XX_PULL_DISA}, | 361 | | AM33XX_PULL_DISA}, |
362 | {"lcd_data14.lcd_data14", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | 362 | {"lcd_data14.lcd_data14", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT |
363 | | AM33XX_PULL_DISA}, | 363 | | AM33XX_PULL_DISA}, |
364 | {"lcd_data15.lcd_data15", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | 364 | {"lcd_data15.lcd_data15", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT |
365 | | AM33XX_PULL_DISA}, | 365 | | AM33XX_PULL_DISA}, |
366 | {"gpmc_ad8.lcd_data16", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT}, | 366 | {"gpmc_ad8.lcd_data16", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT}, |
367 | {"gpmc_ad9.lcd_data17", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT}, | 367 | {"gpmc_ad9.lcd_data17", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT}, |
368 | {"gpmc_ad10.lcd_data18", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT}, | 368 | {"gpmc_ad10.lcd_data18", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT}, |
369 | {"gpmc_ad11.lcd_data19", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT}, | 369 | {"gpmc_ad11.lcd_data19", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT}, |
370 | {"gpmc_ad12.lcd_data20", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT}, | 370 | {"gpmc_ad12.lcd_data20", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT}, |
371 | {"gpmc_ad13.lcd_data21", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT}, | 371 | {"gpmc_ad13.lcd_data21", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT}, |
372 | {"gpmc_ad14.lcd_data22", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT}, | 372 | {"gpmc_ad14.lcd_data22", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT}, |
373 | {"gpmc_ad15.lcd_data23", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT}, | 373 | {"gpmc_ad15.lcd_data23", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT}, |
374 | {"lcd_vsync.lcd_vsync", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, | 374 | {"lcd_vsync.lcd_vsync", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, |
375 | {"lcd_hsync.lcd_hsync", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, | 375 | {"lcd_hsync.lcd_hsync", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, |
376 | {"lcd_pclk.lcd_pclk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, | 376 | {"lcd_pclk.lcd_pclk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, |
377 | {"lcd_ac_bias_en.lcd_ac_bias_en", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, | 377 | {"lcd_ac_bias_en.lcd_ac_bias_en", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, |
378 | {NULL, 0}, | 378 | {NULL, 0}, |
379 | }; | 379 | }; |
380 | 380 | ||
381 | static struct pinmux_config tsc_pin_mux[] = { | 381 | static struct pinmux_config tsc_pin_mux[] = { |
382 | {"ain0.ain0", OMAP_MUX_MODE0 | AM33XX_INPUT_EN}, | 382 | {"ain0.ain0", OMAP_MUX_MODE0 | AM33XX_INPUT_EN}, |
383 | {"ain1.ain1", OMAP_MUX_MODE0 | AM33XX_INPUT_EN}, | 383 | {"ain1.ain1", OMAP_MUX_MODE0 | AM33XX_INPUT_EN}, |
384 | {"ain2.ain2", OMAP_MUX_MODE0 | AM33XX_INPUT_EN}, | 384 | {"ain2.ain2", OMAP_MUX_MODE0 | AM33XX_INPUT_EN}, |
385 | {"ain3.ain3", OMAP_MUX_MODE0 | AM33XX_INPUT_EN}, | 385 | {"ain3.ain3", OMAP_MUX_MODE0 | AM33XX_INPUT_EN}, |
386 | {"vrefp.vrefp", OMAP_MUX_MODE0 | AM33XX_INPUT_EN}, | 386 | {"vrefp.vrefp", OMAP_MUX_MODE0 | AM33XX_INPUT_EN}, |
387 | {"vrefn.vrefn", OMAP_MUX_MODE0 | AM33XX_INPUT_EN}, | 387 | {"vrefn.vrefn", OMAP_MUX_MODE0 | AM33XX_INPUT_EN}, |
388 | {NULL, 0}, | 388 | {NULL, 0}, |
389 | }; | 389 | }; |
390 | 390 | ||
391 | /* Pin mux for nand flash module */ | 391 | /* Pin mux for nand flash module */ |
392 | static struct pinmux_config nand_pin_mux[] = { | 392 | static struct pinmux_config nand_pin_mux[] = { |
393 | {"gpmc_ad0.gpmc_ad0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, | 393 | {"gpmc_ad0.gpmc_ad0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, |
394 | {"gpmc_ad1.gpmc_ad1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, | 394 | {"gpmc_ad1.gpmc_ad1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, |
395 | {"gpmc_ad2.gpmc_ad2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, | 395 | {"gpmc_ad2.gpmc_ad2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, |
396 | {"gpmc_ad3.gpmc_ad3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, | 396 | {"gpmc_ad3.gpmc_ad3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, |
397 | {"gpmc_ad4.gpmc_ad4", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, | 397 | {"gpmc_ad4.gpmc_ad4", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, |
398 | {"gpmc_ad5.gpmc_ad5", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, | 398 | {"gpmc_ad5.gpmc_ad5", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, |
399 | {"gpmc_ad6.gpmc_ad6", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, | 399 | {"gpmc_ad6.gpmc_ad6", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, |
400 | {"gpmc_ad7.gpmc_ad7", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, | 400 | {"gpmc_ad7.gpmc_ad7", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, |
401 | {"gpmc_wait0.gpmc_wait0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, | 401 | {"gpmc_wait0.gpmc_wait0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, |
402 | {"gpmc_wpn.gpmc_wpn", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP}, | 402 | {"gpmc_wpn.gpmc_wpn", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP}, |
403 | {"gpmc_csn0.gpmc_csn0", OMAP_MUX_MODE0 | AM33XX_PULL_DISA}, | 403 | {"gpmc_csn0.gpmc_csn0", OMAP_MUX_MODE0 | AM33XX_PULL_DISA}, |
404 | {"gpmc_advn_ale.gpmc_advn_ale", OMAP_MUX_MODE0 | AM33XX_PULL_DISA}, | 404 | {"gpmc_advn_ale.gpmc_advn_ale", OMAP_MUX_MODE0 | AM33XX_PULL_DISA}, |
405 | {"gpmc_oen_ren.gpmc_oen_ren", OMAP_MUX_MODE0 | AM33XX_PULL_DISA}, | 405 | {"gpmc_oen_ren.gpmc_oen_ren", OMAP_MUX_MODE0 | AM33XX_PULL_DISA}, |
406 | {"gpmc_wen.gpmc_wen", OMAP_MUX_MODE0 | AM33XX_PULL_DISA}, | 406 | {"gpmc_wen.gpmc_wen", OMAP_MUX_MODE0 | AM33XX_PULL_DISA}, |
407 | {"gpmc_ben0_cle.gpmc_ben0_cle", OMAP_MUX_MODE0 | AM33XX_PULL_DISA}, | 407 | {"gpmc_ben0_cle.gpmc_ben0_cle", OMAP_MUX_MODE0 | AM33XX_PULL_DISA}, |
408 | {NULL, 0}, | 408 | {NULL, 0}, |
409 | }; | 409 | }; |
410 | 410 | ||
411 | /* Module pin mux for SPI fash */ | 411 | /* Module pin mux for SPI fash */ |
412 | static struct pinmux_config spi0_pin_mux[] = { | 412 | static struct pinmux_config spi0_pin_mux[] = { |
413 | {"spi0_sclk.spi0_sclk", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL | 413 | {"spi0_sclk.spi0_sclk", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL |
414 | | AM33XX_INPUT_EN}, | 414 | | AM33XX_INPUT_EN}, |
415 | {"spi0_d0.spi0_d0", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL | AM33XX_PULL_UP | 415 | {"spi0_d0.spi0_d0", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL | AM33XX_PULL_UP |
416 | | AM33XX_INPUT_EN}, | 416 | | AM33XX_INPUT_EN}, |
417 | {"spi0_d1.spi0_d1", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL | 417 | {"spi0_d1.spi0_d1", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL |
418 | | AM33XX_INPUT_EN}, | 418 | | AM33XX_INPUT_EN}, |
419 | {"spi0_cs0.spi0_cs0", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL | AM33XX_PULL_UP | 419 | {"spi0_cs0.spi0_cs0", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL | AM33XX_PULL_UP |
420 | | AM33XX_INPUT_EN}, | 420 | | AM33XX_INPUT_EN}, |
421 | {NULL, 0}, | 421 | {NULL, 0}, |
422 | }; | 422 | }; |
423 | 423 | ||
424 | /* Module pin mux for SPI flash */ | 424 | /* Module pin mux for SPI flash */ |
425 | static struct pinmux_config spi1_pin_mux[] = { | 425 | static struct pinmux_config spi1_pin_mux[] = { |
426 | {"mcasp0_aclkx.spi1_sclk", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL | 426 | {"mcasp0_aclkx.spi1_sclk", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL |
427 | | AM33XX_INPUT_EN}, | 427 | | AM33XX_INPUT_EN}, |
428 | {"mcasp0_fsx.spi1_d0", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL | 428 | {"mcasp0_fsx.spi1_d0", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL |
429 | | AM33XX_PULL_UP | AM33XX_INPUT_EN}, | 429 | | AM33XX_PULL_UP | AM33XX_INPUT_EN}, |
430 | {"mcasp0_axr0.spi1_d1", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL | 430 | {"mcasp0_axr0.spi1_d1", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL |
431 | | AM33XX_INPUT_EN}, | 431 | | AM33XX_INPUT_EN}, |
432 | {"mcasp0_ahclkr.spi1_cs0", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL | 432 | {"mcasp0_ahclkr.spi1_cs0", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL |
433 | | AM33XX_PULL_UP | AM33XX_INPUT_EN}, | 433 | | AM33XX_PULL_UP | AM33XX_INPUT_EN}, |
434 | {NULL, 0}, | 434 | {NULL, 0}, |
435 | }; | 435 | }; |
436 | 436 | ||
437 | /* Module pin mux for rgmii1 */ | 437 | /* Module pin mux for rgmii1 */ |
438 | static struct pinmux_config rgmii1_pin_mux[] = { | 438 | static struct pinmux_config rgmii1_pin_mux[] = { |
439 | {"mii1_txen.rgmii1_tctl", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, | 439 | {"mii1_txen.rgmii1_tctl", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, |
440 | {"mii1_rxdv.rgmii1_rctl", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, | 440 | {"mii1_rxdv.rgmii1_rctl", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, |
441 | {"mii1_txd3.rgmii1_td3", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, | 441 | {"mii1_txd3.rgmii1_td3", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, |
442 | {"mii1_txd2.rgmii1_td2", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, | 442 | {"mii1_txd2.rgmii1_td2", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, |
443 | {"mii1_txd1.rgmii1_td1", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, | 443 | {"mii1_txd1.rgmii1_td1", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, |
444 | {"mii1_txd0.rgmii1_td0", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, | 444 | {"mii1_txd0.rgmii1_td0", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, |
445 | {"mii1_txclk.rgmii1_tclk", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, | 445 | {"mii1_txclk.rgmii1_tclk", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, |
446 | {"mii1_rxclk.rgmii1_rclk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, | 446 | {"mii1_rxclk.rgmii1_rclk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, |
447 | {"mii1_rxd3.rgmii1_rd3", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, | 447 | {"mii1_rxd3.rgmii1_rd3", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, |
448 | {"mii1_rxd2.rgmii1_rd2", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, | 448 | {"mii1_rxd2.rgmii1_rd2", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, |
449 | {"mii1_rxd1.rgmii1_rd1", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, | 449 | {"mii1_rxd1.rgmii1_rd1", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, |
450 | {"mii1_rxd0.rgmii1_rd0", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, | 450 | {"mii1_rxd0.rgmii1_rd0", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, |
451 | {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, | 451 | {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, |
452 | {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP}, | 452 | {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP}, |
453 | {NULL, 0}, | 453 | {NULL, 0}, |
454 | }; | 454 | }; |
455 | 455 | ||
456 | /* Module pin mux for rgmii2 */ | 456 | /* Module pin mux for rgmii2 */ |
457 | static struct pinmux_config rgmii2_pin_mux[] = { | 457 | static struct pinmux_config rgmii2_pin_mux[] = { |
458 | {"gpmc_a0.rgmii2_tctl", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, | 458 | {"gpmc_a0.rgmii2_tctl", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, |
459 | {"gpmc_a1.rgmii2_rctl", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, | 459 | {"gpmc_a1.rgmii2_rctl", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, |
460 | {"gpmc_a2.rgmii2_td3", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, | 460 | {"gpmc_a2.rgmii2_td3", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, |
461 | {"gpmc_a3.rgmii2_td2", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, | 461 | {"gpmc_a3.rgmii2_td2", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, |
462 | {"gpmc_a4.rgmii2_td1", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, | 462 | {"gpmc_a4.rgmii2_td1", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, |
463 | {"gpmc_a5.rgmii2_td0", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, | 463 | {"gpmc_a5.rgmii2_td0", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, |
464 | {"gpmc_a6.rgmii2_tclk", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, | 464 | {"gpmc_a6.rgmii2_tclk", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, |
465 | {"gpmc_a7.rgmii2_rclk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, | 465 | {"gpmc_a7.rgmii2_rclk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, |
466 | {"gpmc_a8.rgmii2_rd3", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, | 466 | {"gpmc_a8.rgmii2_rd3", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, |
467 | {"gpmc_a9.rgmii2_rd2", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, | 467 | {"gpmc_a9.rgmii2_rd2", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, |
468 | {"gpmc_a10.rgmii2_rd1", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, | 468 | {"gpmc_a10.rgmii2_rd1", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, |
469 | {"gpmc_a11.rgmii2_rd0", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, | 469 | {"gpmc_a11.rgmii2_rd0", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, |
470 | {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, | 470 | {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, |
471 | {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP}, | 471 | {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP}, |
472 | {NULL, 0}, | 472 | {NULL, 0}, |
473 | }; | 473 | }; |
474 | 474 | ||
475 | /* Module pin mux for mii1 */ | 475 | /* Module pin mux for mii1 */ |
476 | static struct pinmux_config mii1_pin_mux[] = { | 476 | static struct pinmux_config mii1_pin_mux[] = { |
477 | {"mii1_rxerr.mii1_rxerr", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN}, | 477 | {"mii1_rxerr.mii1_rxerr", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN}, |
478 | {"mii1_txen.mii1_txen", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, | 478 | {"mii1_txen.mii1_txen", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, |
479 | {"mii1_rxdv.mii1_rxdv", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN}, | 479 | {"mii1_rxdv.mii1_rxdv", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN}, |
480 | {"mii1_txd3.mii1_txd3", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, | 480 | {"mii1_txd3.mii1_txd3", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, |
481 | {"mii1_txd2.mii1_txd2", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, | 481 | {"mii1_txd2.mii1_txd2", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, |
482 | {"mii1_txd1.mii1_txd1", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, | 482 | {"mii1_txd1.mii1_txd1", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, |
483 | {"mii1_txd0.mii1_txd0", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, | 483 | {"mii1_txd0.mii1_txd0", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, |
484 | {"mii1_txclk.mii1_txclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN}, | 484 | {"mii1_txclk.mii1_txclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN}, |
485 | {"mii1_rxclk.mii1_rxclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN}, | 485 | {"mii1_rxclk.mii1_rxclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN}, |
486 | {"mii1_rxd3.mii1_rxd3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN}, | 486 | {"mii1_rxd3.mii1_rxd3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN}, |
487 | {"mii1_rxd2.mii1_rxd2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN}, | 487 | {"mii1_rxd2.mii1_rxd2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN}, |
488 | {"mii1_rxd1.mii1_rxd1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN}, | 488 | {"mii1_rxd1.mii1_rxd1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN}, |
489 | {"mii1_rxd0.mii1_rxd0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN}, | 489 | {"mii1_rxd0.mii1_rxd0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN}, |
490 | {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, | 490 | {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, |
491 | {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP}, | 491 | {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP}, |
492 | {NULL, 0}, | 492 | {NULL, 0}, |
493 | }; | 493 | }; |
494 | 494 | ||
495 | /* Module pin mux for rmii1 */ | 495 | /* Module pin mux for rmii1 */ |
496 | static struct pinmux_config rmii1_pin_mux[] = { | 496 | static struct pinmux_config rmii1_pin_mux[] = { |
497 | {"mii1_crs.rmii1_crs_dv", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN}, | 497 | {"mii1_crs.rmii1_crs_dv", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN}, |
498 | {"mii1_rxerr.mii1_rxerr", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN}, | 498 | {"mii1_rxerr.mii1_rxerr", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN}, |
499 | {"mii1_txen.mii1_txen", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT}, | 499 | {"mii1_txen.mii1_txen", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT}, |
500 | {"mii1_txd1.mii1_txd1", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT}, | 500 | {"mii1_txd1.mii1_txd1", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT}, |
501 | {"mii1_txd0.mii1_txd0", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT}, | 501 | {"mii1_txd0.mii1_txd0", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT}, |
502 | {"mii1_rxd1.mii1_rxd1", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN}, | 502 | {"mii1_rxd1.mii1_rxd1", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN}, |
503 | {"mii1_rxd0.mii1_rxd0", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN}, | 503 | {"mii1_rxd0.mii1_rxd0", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN}, |
504 | {"rmii1_refclk.rmii1_refclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN}, | 504 | {"rmii1_refclk.rmii1_refclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN}, |
505 | {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, | 505 | {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, |
506 | {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP}, | 506 | {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP}, |
507 | {NULL, 0}, | 507 | {NULL, 0}, |
508 | }; | 508 | }; |
509 | 509 | ||
510 | static struct pinmux_config i2c1_pin_mux[] = { | 510 | static struct pinmux_config i2c1_pin_mux[] = { |
511 | {"spi0_d1.i2c1_sda", OMAP_MUX_MODE2 | AM33XX_SLEWCTRL_SLOW | | 511 | {"spi0_d1.i2c1_sda", OMAP_MUX_MODE2 | AM33XX_SLEWCTRL_SLOW | |
512 | AM33XX_PULL_ENBL | AM33XX_INPUT_EN}, | 512 | AM33XX_PULL_ENBL | AM33XX_INPUT_EN}, |
513 | {"spi0_cs0.i2c1_scl", OMAP_MUX_MODE2 | AM33XX_SLEWCTRL_SLOW | | 513 | {"spi0_cs0.i2c1_scl", OMAP_MUX_MODE2 | AM33XX_SLEWCTRL_SLOW | |
514 | AM33XX_PULL_ENBL | AM33XX_INPUT_EN}, | 514 | AM33XX_PULL_ENBL | AM33XX_INPUT_EN}, |
515 | {NULL, 0}, | 515 | {NULL, 0}, |
516 | }; | 516 | }; |
517 | 517 | ||
518 | /* Module pin mux for mcasp1 */ | 518 | /* Module pin mux for mcasp1 */ |
519 | static struct pinmux_config mcasp1_pin_mux[] = { | 519 | static struct pinmux_config mcasp1_pin_mux[] = { |
520 | {"mii1_crs.mcasp1_aclkx", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN}, | 520 | {"mii1_crs.mcasp1_aclkx", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN}, |
521 | {"mii1_rxerr.mcasp1_fsx", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN}, | 521 | {"mii1_rxerr.mcasp1_fsx", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN}, |
522 | {"mii1_col.mcasp1_axr2", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN}, | 522 | {"mii1_col.mcasp1_axr2", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN}, |
523 | {"rmii1_refclk.mcasp1_axr3", OMAP_MUX_MODE4 | | 523 | {"rmii1_refclk.mcasp1_axr3", OMAP_MUX_MODE4 | |
524 | AM33XX_PIN_INPUT_PULLDOWN}, | 524 | AM33XX_PIN_INPUT_PULLDOWN}, |
525 | {NULL, 0}, | 525 | {NULL, 0}, |
526 | }; | 526 | }; |
527 | 527 | ||
528 | 528 | ||
529 | /* Module pin mux for mmc0 */ | 529 | /* Module pin mux for mmc0 */ |
530 | static struct pinmux_config mmc0_pin_mux[] = { | 530 | static struct pinmux_config mmc0_pin_mux[] = { |
531 | {"mmc0_dat3.mmc0_dat3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, | 531 | {"mmc0_dat3.mmc0_dat3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, |
532 | {"mmc0_dat2.mmc0_dat2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, | 532 | {"mmc0_dat2.mmc0_dat2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, |
533 | {"mmc0_dat1.mmc0_dat1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, | 533 | {"mmc0_dat1.mmc0_dat1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, |
534 | {"mmc0_dat0.mmc0_dat0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, | 534 | {"mmc0_dat0.mmc0_dat0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, |
535 | {"mmc0_clk.mmc0_clk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, | 535 | {"mmc0_clk.mmc0_clk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, |
536 | {"mmc0_cmd.mmc0_cmd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, | 536 | {"mmc0_cmd.mmc0_cmd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, |
537 | {"mcasp0_aclkr.mmc0_sdwp", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP}, | 537 | {"mcasp0_aclkr.mmc0_sdwp", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP}, |
538 | {"spi0_cs1.mmc0_sdcd", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP}, | 538 | {"spi0_cs1.mmc0_sdcd", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP}, |
539 | {NULL, 0}, | 539 | {NULL, 0}, |
540 | }; | 540 | }; |
541 | 541 | ||
542 | static struct pinmux_config mmc0_no_cd_pin_mux[] = { | 542 | static struct pinmux_config mmc0_no_cd_pin_mux[] = { |
543 | {"mmc0_dat3.mmc0_dat3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, | 543 | {"mmc0_dat3.mmc0_dat3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, |
544 | {"mmc0_dat2.mmc0_dat2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, | 544 | {"mmc0_dat2.mmc0_dat2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, |
545 | {"mmc0_dat1.mmc0_dat1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, | 545 | {"mmc0_dat1.mmc0_dat1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, |
546 | {"mmc0_dat0.mmc0_dat0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, | 546 | {"mmc0_dat0.mmc0_dat0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, |
547 | {"mmc0_clk.mmc0_clk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, | 547 | {"mmc0_clk.mmc0_clk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, |
548 | {"mmc0_cmd.mmc0_cmd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, | 548 | {"mmc0_cmd.mmc0_cmd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, |
549 | {"mcasp0_aclkr.mmc0_sdwp", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN}, | 549 | {"mcasp0_aclkr.mmc0_sdwp", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN}, |
550 | {NULL, 0}, | 550 | {NULL, 0}, |
551 | }; | 551 | }; |
552 | 552 | ||
553 | /* Module pin mux for mmc1 */ | 553 | /* Module pin mux for mmc1 */ |
554 | static struct pinmux_config mmc1_pin_mux[] = { | 554 | static struct pinmux_config mmc1_pin_mux[] = { |
555 | {"gpmc_ad7.mmc1_dat7", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP}, | 555 | {"gpmc_ad7.mmc1_dat7", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP}, |
556 | {"gpmc_ad6.mmc1_dat6", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP}, | 556 | {"gpmc_ad6.mmc1_dat6", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP}, |
557 | {"gpmc_ad5.mmc1_dat5", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP}, | 557 | {"gpmc_ad5.mmc1_dat5", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP}, |
558 | {"gpmc_ad4.mmc1_dat4", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP}, | 558 | {"gpmc_ad4.mmc1_dat4", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP}, |
559 | {"gpmc_ad3.mmc1_dat3", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP}, | 559 | {"gpmc_ad3.mmc1_dat3", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP}, |
560 | {"gpmc_ad2.mmc1_dat2", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP}, | 560 | {"gpmc_ad2.mmc1_dat2", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP}, |
561 | {"gpmc_ad1.mmc1_dat1", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP}, | 561 | {"gpmc_ad1.mmc1_dat1", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP}, |
562 | {"gpmc_ad0.mmc1_dat0", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP}, | 562 | {"gpmc_ad0.mmc1_dat0", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP}, |
563 | {"gpmc_csn1.mmc1_clk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP}, | 563 | {"gpmc_csn1.mmc1_clk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP}, |
564 | {"gpmc_csn2.mmc1_cmd", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP}, | 564 | {"gpmc_csn2.mmc1_cmd", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP}, |
565 | {"gpmc_csn0.mmc1_sdwp", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP}, | 565 | {"gpmc_csn0.mmc1_sdwp", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP}, |
566 | {"gpmc_advn_ale.mmc1_sdcd", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP}, | 566 | {"gpmc_advn_ale.mmc1_sdcd", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP}, |
567 | {NULL, 0}, | 567 | {NULL, 0}, |
568 | }; | 568 | }; |
569 | 569 | ||
570 | /* Module pin mux for uart3 */ | 570 | /* Module pin mux for uart3 */ |
571 | static struct pinmux_config uart3_pin_mux[] = { | 571 | static struct pinmux_config uart3_pin_mux[] = { |
572 | {"spi0_cs1.uart3_rxd", AM33XX_PIN_INPUT_PULLUP}, | 572 | {"spi0_cs1.uart3_rxd", AM33XX_PIN_INPUT_PULLUP}, |
573 | {"ecap0_in_pwm0_out.uart3_txd", AM33XX_PULL_ENBL}, | 573 | {"ecap0_in_pwm0_out.uart3_txd", AM33XX_PULL_ENBL}, |
574 | {NULL, 0}, | 574 | {NULL, 0}, |
575 | }; | 575 | }; |
576 | 576 | ||
577 | static struct pinmux_config d_can_gp_pin_mux[] = { | 577 | static struct pinmux_config d_can_gp_pin_mux[] = { |
578 | {"uart0_ctsn.d_can1_tx", OMAP_MUX_MODE2 | AM33XX_PULL_ENBL}, | 578 | {"uart0_ctsn.d_can1_tx", OMAP_MUX_MODE2 | AM33XX_PULL_ENBL}, |
579 | {"uart0_rtsn.d_can1_rx", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP}, | 579 | {"uart0_rtsn.d_can1_rx", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP}, |
580 | {NULL, 0}, | 580 | {NULL, 0}, |
581 | }; | 581 | }; |
582 | 582 | ||
583 | static struct pinmux_config d_can_ia_pin_mux[] = { | 583 | static struct pinmux_config d_can_ia_pin_mux[] = { |
584 | {"uart0_rxd.d_can0_tx", OMAP_MUX_MODE2 | AM33XX_PULL_ENBL}, | 584 | {"uart0_rxd.d_can0_tx", OMAP_MUX_MODE2 | AM33XX_PULL_ENBL}, |
585 | {"uart0_txd.d_can0_rx", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP}, | 585 | {"uart0_txd.d_can0_rx", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP}, |
586 | {NULL, 0}, | 586 | {NULL, 0}, |
587 | }; | 587 | }; |
588 | 588 | ||
589 | /* | 589 | /* |
590 | * @pin_mux - single module pin-mux structure which defines pin-mux | 590 | * @pin_mux - single module pin-mux structure which defines pin-mux |
591 | * details for all its pins. | 591 | * details for all its pins. |
592 | */ | 592 | */ |
593 | static void setup_pin_mux(struct pinmux_config *pin_mux) | 593 | static void setup_pin_mux(struct pinmux_config *pin_mux) |
594 | { | 594 | { |
595 | int i; | 595 | int i; |
596 | 596 | ||
597 | for (i = 0; pin_mux->string_name != NULL; pin_mux++) | 597 | for (i = 0; pin_mux->string_name != NULL; pin_mux++) |
598 | omap_mux_init_signal(pin_mux->string_name, pin_mux->val); | 598 | omap_mux_init_signal(pin_mux->string_name, pin_mux->val); |
599 | 599 | ||
600 | } | 600 | } |
601 | 601 | ||
602 | /* Matrix GPIO Keypad Support for profile-0 only: TODO */ | 602 | /* Matrix GPIO Keypad Support for profile-0 only: TODO */ |
603 | #ifdef CONFIG_KEYBOARD_MATRIX | 603 | #ifdef CONFIG_KEYBOARD_MATRIX |
604 | 604 | ||
605 | /* pinmux for keypad device */ | 605 | /* pinmux for keypad device */ |
606 | static struct pinmux_config matrix_keypad_pin_mux[] = { | 606 | static struct pinmux_config matrix_keypad_pin_mux[] = { |
607 | {"gpmc_a5.gpio1_21", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT}, | 607 | {"gpmc_a5.gpio1_21", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT}, |
608 | {"gpmc_a8.gpio1_22", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT}, | 608 | {"gpmc_a8.gpio1_22", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT}, |
609 | {"gpmc_a9.gpio1_25", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT}, | 609 | {"gpmc_a9.gpio1_25", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT}, |
610 | {"gpmc_a10.gpio1_26", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT}, | 610 | {"gpmc_a10.gpio1_26", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT}, |
611 | {"gpmc_a11.gpio1_27", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT}, | 611 | {"gpmc_a11.gpio1_27", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT}, |
612 | {NULL, 0}, | 612 | {NULL, 0}, |
613 | }; | 613 | }; |
614 | 614 | ||
615 | /* Keys mapping */ | 615 | /* Keys mapping */ |
616 | static const uint32_t am335x_evm_matrix_keys[] = { | 616 | static const uint32_t am335x_evm_matrix_keys[] = { |
617 | KEY(0, 0, KEY_MENU), | 617 | KEY(0, 0, KEY_MENU), |
618 | KEY(1, 0, KEY_BACK), | 618 | KEY(1, 0, KEY_BACK), |
619 | KEY(2, 0, KEY_LEFT), | 619 | KEY(2, 0, KEY_LEFT), |
620 | 620 | ||
621 | KEY(0, 1, KEY_RIGHT), | 621 | KEY(0, 1, KEY_RIGHT), |
622 | KEY(1, 1, KEY_ENTER), | 622 | KEY(1, 1, KEY_ENTER), |
623 | KEY(2, 1, KEY_DOWN), | 623 | KEY(2, 1, KEY_DOWN), |
624 | }; | 624 | }; |
625 | 625 | ||
626 | const struct matrix_keymap_data am335x_evm_keymap_data = { | 626 | const struct matrix_keymap_data am335x_evm_keymap_data = { |
627 | .keymap = am335x_evm_matrix_keys, | 627 | .keymap = am335x_evm_matrix_keys, |
628 | .keymap_size = ARRAY_SIZE(am335x_evm_matrix_keys), | 628 | .keymap_size = ARRAY_SIZE(am335x_evm_matrix_keys), |
629 | }; | 629 | }; |
630 | 630 | ||
631 | static const unsigned int am335x_evm_keypad_row_gpios[] = { | 631 | static const unsigned int am335x_evm_keypad_row_gpios[] = { |
632 | GPIO_TO_PIN(1, 25), GPIO_TO_PIN(1, 26), GPIO_TO_PIN(1, 27) | 632 | GPIO_TO_PIN(1, 25), GPIO_TO_PIN(1, 26), GPIO_TO_PIN(1, 27) |
633 | }; | 633 | }; |
634 | 634 | ||
635 | static const unsigned int am335x_evm_keypad_col_gpios[] = { | 635 | static const unsigned int am335x_evm_keypad_col_gpios[] = { |
636 | GPIO_TO_PIN(1, 21), GPIO_TO_PIN(1, 22) | 636 | GPIO_TO_PIN(1, 21), GPIO_TO_PIN(1, 22) |
637 | }; | 637 | }; |
638 | 638 | ||
639 | static struct matrix_keypad_platform_data am335x_evm_keypad_platform_data = { | 639 | static struct matrix_keypad_platform_data am335x_evm_keypad_platform_data = { |
640 | .keymap_data = &am335x_evm_keymap_data, | 640 | .keymap_data = &am335x_evm_keymap_data, |
641 | .row_gpios = am335x_evm_keypad_row_gpios, | 641 | .row_gpios = am335x_evm_keypad_row_gpios, |
642 | .num_row_gpios = ARRAY_SIZE(am335x_evm_keypad_row_gpios), | 642 | .num_row_gpios = ARRAY_SIZE(am335x_evm_keypad_row_gpios), |
643 | .col_gpios = am335x_evm_keypad_col_gpios, | 643 | .col_gpios = am335x_evm_keypad_col_gpios, |
644 | .num_col_gpios = ARRAY_SIZE(am335x_evm_keypad_col_gpios), | 644 | .num_col_gpios = ARRAY_SIZE(am335x_evm_keypad_col_gpios), |
645 | .active_low = false, | 645 | .active_low = false, |
646 | .debounce_ms = 5, | 646 | .debounce_ms = 5, |
647 | .col_scan_delay_us = 2, | 647 | .col_scan_delay_us = 2, |
648 | }; | 648 | }; |
649 | 649 | ||
650 | static struct platform_device am335x_evm_keyboard = { | 650 | static struct platform_device am335x_evm_keyboard = { |
651 | .name = "matrix-keypad", | 651 | .name = "matrix-keypad", |
652 | .id = -1, | 652 | .id = -1, |
653 | .dev = { | 653 | .dev = { |
654 | .platform_data = &am335x_evm_keypad_platform_data, | 654 | .platform_data = &am335x_evm_keypad_platform_data, |
655 | }, | 655 | }, |
656 | }; | 656 | }; |
657 | 657 | ||
658 | static void matrix_keypad_init(int evm_id, int profile) | 658 | static void matrix_keypad_init(int evm_id, int profile) |
659 | { | 659 | { |
660 | int err; | 660 | int err; |
661 | 661 | ||
662 | setup_pin_mux(matrix_keypad_pin_mux); | 662 | setup_pin_mux(matrix_keypad_pin_mux); |
663 | err = platform_device_register(&am335x_evm_keyboard); | 663 | err = platform_device_register(&am335x_evm_keyboard); |
664 | if (err) { | 664 | if (err) { |
665 | pr_err("failed to register matrix keypad (2x3) device\n"); | 665 | pr_err("failed to register matrix keypad (2x3) device\n"); |
666 | } | 666 | } |
667 | } | 667 | } |
668 | #endif | 668 | #endif |
669 | 669 | ||
670 | 670 | ||
671 | #ifdef CONFIG_KEYBOARD_GPIO | 671 | #ifdef CONFIG_KEYBOARD_GPIO |
672 | /* pinmux for keypad device */ | 672 | /* pinmux for keypad device */ |
673 | static struct pinmux_config volume_keys_pin_mux[] = { | 673 | static struct pinmux_config volume_keys_pin_mux[] = { |
674 | {"spi0_sclk.gpio0_2", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT}, | 674 | {"spi0_sclk.gpio0_2", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT}, |
675 | {"spi0_d0.gpio0_3", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT}, | 675 | {"spi0_d0.gpio0_3", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT}, |
676 | {NULL, 0}, | 676 | {NULL, 0}, |
677 | }; | 677 | }; |
678 | 678 | ||
679 | /* Configure GPIOs for Volume Keys */ | 679 | /* Configure GPIOs for Volume Keys */ |
680 | static struct gpio_keys_button am335x_evm_volume_gpio_buttons[] = { | 680 | static struct gpio_keys_button am335x_evm_volume_gpio_buttons[] = { |
681 | { | 681 | { |
682 | .code = KEY_VOLUMEUP, | 682 | .code = KEY_VOLUMEUP, |
683 | .gpio = GPIO_TO_PIN(0, 2), | 683 | .gpio = GPIO_TO_PIN(0, 2), |
684 | .active_low = true, | 684 | .active_low = true, |
685 | .desc = "volume-up", | 685 | .desc = "volume-up", |
686 | .type = EV_KEY, | 686 | .type = EV_KEY, |
687 | .wakeup = 1, | 687 | .wakeup = 1, |
688 | }, | 688 | }, |
689 | { | 689 | { |
690 | .code = KEY_VOLUMEDOWN, | 690 | .code = KEY_VOLUMEDOWN, |
691 | .gpio = GPIO_TO_PIN(0, 3), | 691 | .gpio = GPIO_TO_PIN(0, 3), |
692 | .active_low = true, | 692 | .active_low = true, |
693 | .desc = "volume-down", | 693 | .desc = "volume-down", |
694 | .type = EV_KEY, | 694 | .type = EV_KEY, |
695 | .wakeup = 1, | 695 | .wakeup = 1, |
696 | }, | 696 | }, |
697 | }; | 697 | }; |
698 | 698 | ||
699 | static struct gpio_keys_platform_data am335x_evm_volume_gpio_key_info = { | 699 | static struct gpio_keys_platform_data am335x_evm_volume_gpio_key_info = { |
700 | .buttons = am335x_evm_volume_gpio_buttons, | 700 | .buttons = am335x_evm_volume_gpio_buttons, |
701 | .nbuttons = ARRAY_SIZE(am335x_evm_volume_gpio_buttons), | 701 | .nbuttons = ARRAY_SIZE(am335x_evm_volume_gpio_buttons), |
702 | }; | 702 | }; |
703 | 703 | ||
704 | static struct platform_device am335x_evm_volume_keys = { | 704 | static struct platform_device am335x_evm_volume_keys = { |
705 | .name = "gpio-keys", | 705 | .name = "gpio-keys", |
706 | .id = -1, | 706 | .id = -1, |
707 | .dev = { | 707 | .dev = { |
708 | .platform_data = &am335x_evm_volume_gpio_key_info, | 708 | .platform_data = &am335x_evm_volume_gpio_key_info, |
709 | }, | 709 | }, |
710 | }; | 710 | }; |
711 | 711 | ||
712 | static void volume_keys_init(int evm_id, int profile) | 712 | static void volume_keys_init(int evm_id, int profile) |
713 | { | 713 | { |
714 | int err; | 714 | int err; |
715 | 715 | ||
716 | setup_pin_mux(volume_keys_pin_mux); | 716 | setup_pin_mux(volume_keys_pin_mux); |
717 | err = platform_device_register(&am335x_evm_volume_keys); | 717 | err = platform_device_register(&am335x_evm_volume_keys); |
718 | if (err) | 718 | if (err) |
719 | pr_err("failed to register matrix keypad (2x3) device\n"); | 719 | pr_err("failed to register matrix keypad (2x3) device\n"); |
720 | } | 720 | } |
721 | #endif | 721 | #endif |
722 | 722 | ||
723 | /* | 723 | /* |
724 | * @evm_id - evm id which needs to be configured | 724 | * @evm_id - evm id which needs to be configured |
725 | * @dev_cfg - single evm structure which includes | 725 | * @dev_cfg - single evm structure which includes |
726 | * all module inits, pin-mux defines | 726 | * all module inits, pin-mux defines |
727 | * @profile - if present, else PROFILE_NONE | 727 | * @profile - if present, else PROFILE_NONE |
728 | * @dghtr_brd_flg - Whether Daughter board is present or not | 728 | * @dghtr_brd_flg - Whether Daughter board is present or not |
729 | */ | 729 | */ |
730 | static void _configure_device(int evm_id, struct evm_dev_cfg *dev_cfg, | 730 | static void _configure_device(int evm_id, struct evm_dev_cfg *dev_cfg, |
731 | int profile) | 731 | int profile) |
732 | { | 732 | { |
733 | int i; | 733 | int i; |
734 | 734 | ||
735 | /* | 735 | /* |
736 | * Only General Purpose & Industrial Auto Motro Control | 736 | * Only General Purpose & Industrial Auto Motro Control |
737 | * EVM has profiles. So check if this evm has profile. | 737 | * EVM has profiles. So check if this evm has profile. |
738 | * If not, ignore the profile comparison | 738 | * If not, ignore the profile comparison |
739 | */ | 739 | */ |
740 | 740 | ||
741 | /* | 741 | /* |
742 | * If the device is on baseboard, directly configure it. Else (device on | 742 | * If the device is on baseboard, directly configure it. Else (device on |
743 | * Daughter board), check if the daughter card is detected. | 743 | * Daughter board), check if the daughter card is detected. |
744 | */ | 744 | */ |
745 | if (profile == PROFILE_NONE) { | 745 | if (profile == PROFILE_NONE) { |
746 | for (i = 0; dev_cfg->device_init != NULL; dev_cfg++) { | 746 | for (i = 0; dev_cfg->device_init != NULL; dev_cfg++) { |
747 | if (dev_cfg->device_on == DEV_ON_BASEBOARD) | 747 | if (dev_cfg->device_on == DEV_ON_BASEBOARD) |
748 | dev_cfg->device_init(evm_id, profile); | 748 | dev_cfg->device_init(evm_id, profile); |
749 | else if (daughter_brd_detected == true) | 749 | else if (daughter_brd_detected == true) |
750 | dev_cfg->device_init(evm_id, profile); | 750 | dev_cfg->device_init(evm_id, profile); |
751 | } | 751 | } |
752 | } else { | 752 | } else { |
753 | for (i = 0; dev_cfg->device_init != NULL; dev_cfg++) { | 753 | for (i = 0; dev_cfg->device_init != NULL; dev_cfg++) { |
754 | if (dev_cfg->profile & profile) { | 754 | if (dev_cfg->profile & profile) { |
755 | if (dev_cfg->device_on == DEV_ON_BASEBOARD) | 755 | if (dev_cfg->device_on == DEV_ON_BASEBOARD) |
756 | dev_cfg->device_init(evm_id, profile); | 756 | dev_cfg->device_init(evm_id, profile); |
757 | else if (daughter_brd_detected == true) | 757 | else if (daughter_brd_detected == true) |
758 | dev_cfg->device_init(evm_id, profile); | 758 | dev_cfg->device_init(evm_id, profile); |
759 | } | 759 | } |
760 | } | 760 | } |
761 | } | 761 | } |
762 | } | 762 | } |
763 | 763 | ||
764 | #define AM335X_LCD_BL_PIN GPIO_TO_PIN(0, 7) | 764 | #define AM335X_LCD_BL_PIN GPIO_TO_PIN(0, 7) |
765 | 765 | ||
766 | /* pinmux for usb0 drvvbus */ | 766 | /* pinmux for usb0 drvvbus */ |
767 | static struct pinmux_config usb0_pin_mux[] = { | 767 | static struct pinmux_config usb0_pin_mux[] = { |
768 | {"usb0_drvvbus.usb0_drvvbus", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, | 768 | {"usb0_drvvbus.usb0_drvvbus", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, |
769 | {NULL, 0}, | 769 | {NULL, 0}, |
770 | }; | 770 | }; |
771 | 771 | ||
772 | /* pinmux for usb1 drvvbus */ | 772 | /* pinmux for usb1 drvvbus */ |
773 | static struct pinmux_config usb1_pin_mux[] = { | 773 | static struct pinmux_config usb1_pin_mux[] = { |
774 | {"usb1_drvvbus.usb1_drvvbus", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, | 774 | {"usb1_drvvbus.usb1_drvvbus", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, |
775 | {NULL, 0}, | 775 | {NULL, 0}, |
776 | }; | 776 | }; |
777 | 777 | ||
778 | /* pinmux for profibus */ | 778 | /* pinmux for profibus */ |
779 | static struct pinmux_config profibus_pin_mux[] = { | 779 | static struct pinmux_config profibus_pin_mux[] = { |
780 | {"uart1_rxd.pr1_uart0_rxd_mux1", OMAP_MUX_MODE5 | AM33XX_PIN_INPUT}, | 780 | {"uart1_rxd.pr1_uart0_rxd_mux1", OMAP_MUX_MODE5 | AM33XX_PIN_INPUT}, |
781 | {"uart1_txd.pr1_uart0_txd_mux1", OMAP_MUX_MODE5 | AM33XX_PIN_OUTPUT}, | 781 | {"uart1_txd.pr1_uart0_txd_mux1", OMAP_MUX_MODE5 | AM33XX_PIN_OUTPUT}, |
782 | {"mcasp0_fsr.pr1_pru0_pru_r30_5", OMAP_MUX_MODE5 | AM33XX_PIN_OUTPUT}, | 782 | {"mcasp0_fsr.pr1_pru0_pru_r30_5", OMAP_MUX_MODE5 | AM33XX_PIN_OUTPUT}, |
783 | {NULL, 0}, | 783 | {NULL, 0}, |
784 | }; | 784 | }; |
785 | 785 | ||
786 | /* Module pin mux for eCAP0 */ | 786 | /* Module pin mux for eCAP0 */ |
787 | static struct pinmux_config ecap0_pin_mux[] = { | 787 | static struct pinmux_config ecap0_pin_mux[] = { |
788 | {"ecap0_in_pwm0_out.gpio0_7", AM33XX_PIN_OUTPUT}, | 788 | {"ecap0_in_pwm0_out.gpio0_7", AM33XX_PIN_OUTPUT}, |
789 | {NULL, 0}, | 789 | {NULL, 0}, |
790 | }; | 790 | }; |
791 | 791 | ||
792 | #define AM335XEVM_WLAN_IRQ_GPIO GPIO_TO_PIN(3, 17) | 792 | #define AM335XEVM_WLAN_IRQ_GPIO GPIO_TO_PIN(3, 17) |
793 | 793 | ||
794 | struct wl12xx_platform_data am335xevm_wlan_data = { | 794 | struct wl12xx_platform_data am335xevm_wlan_data = { |
795 | .irq = OMAP_GPIO_IRQ(AM335XEVM_WLAN_IRQ_GPIO), | 795 | .irq = OMAP_GPIO_IRQ(AM335XEVM_WLAN_IRQ_GPIO), |
796 | .board_ref_clock = WL12XX_REFCLOCK_38_XTAL, /* 38.4Mhz */ | 796 | .board_ref_clock = WL12XX_REFCLOCK_38_XTAL, /* 38.4Mhz */ |
797 | }; | 797 | }; |
798 | 798 | ||
799 | /* Module pin mux for wlan and bluetooth */ | 799 | /* Module pin mux for wlan and bluetooth */ |
800 | static struct pinmux_config mmc2_wl12xx_pin_mux[] = { | 800 | static struct pinmux_config mmc2_wl12xx_pin_mux[] = { |
801 | {"gpmc_a1.mmc2_dat0", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP}, | 801 | {"gpmc_a1.mmc2_dat0", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP}, |
802 | {"gpmc_a2.mmc2_dat1", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP}, | 802 | {"gpmc_a2.mmc2_dat1", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP}, |
803 | {"gpmc_a3.mmc2_dat2", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP}, | 803 | {"gpmc_a3.mmc2_dat2", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP}, |
804 | {"gpmc_ben1.mmc2_dat3", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP}, | 804 | {"gpmc_ben1.mmc2_dat3", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP}, |
805 | {"gpmc_csn3.mmc2_cmd", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP}, | 805 | {"gpmc_csn3.mmc2_cmd", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP}, |
806 | {"gpmc_clk.mmc2_clk", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP}, | 806 | {"gpmc_clk.mmc2_clk", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP}, |
807 | {NULL, 0}, | 807 | {NULL, 0}, |
808 | }; | 808 | }; |
809 | 809 | ||
810 | static struct pinmux_config uart1_wl12xx_pin_mux[] = { | 810 | static struct pinmux_config uart1_wl12xx_pin_mux[] = { |
811 | {"uart1_ctsn.uart1_ctsn", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, | 811 | {"uart1_ctsn.uart1_ctsn", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, |
812 | {"uart1_rtsn.uart1_rtsn", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT}, | 812 | {"uart1_rtsn.uart1_rtsn", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT}, |
813 | {"uart1_rxd.uart1_rxd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, | 813 | {"uart1_rxd.uart1_rxd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, |
814 | {"uart1_txd.uart1_txd", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL}, | 814 | {"uart1_txd.uart1_txd", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL}, |
815 | {NULL, 0}, | 815 | {NULL, 0}, |
816 | }; | 816 | }; |
817 | 817 | ||
818 | static struct pinmux_config wl12xx_pin_mux_evm_rev1_1a[] = { | 818 | static struct pinmux_config wl12xx_pin_mux_evm_rev1_1a[] = { |
819 | {"gpmc_a0.gpio1_16", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT}, | 819 | {"gpmc_a0.gpio1_16", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT}, |
820 | {"mcasp0_ahclkr.gpio3_17", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT}, | 820 | {"mcasp0_ahclkr.gpio3_17", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT}, |
821 | {"mcasp0_ahclkx.gpio3_21", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT}, | 821 | {"mcasp0_ahclkx.gpio3_21", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT}, |
822 | {NULL, 0}, | 822 | {NULL, 0}, |
823 | }; | 823 | }; |
824 | 824 | ||
825 | static struct pinmux_config wl12xx_pin_mux_evm_rev1_0[] = { | 825 | static struct pinmux_config wl12xx_pin_mux_evm_rev1_0[] = { |
826 | {"gpmc_csn1.gpio1_30", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT}, | 826 | {"gpmc_csn1.gpio1_30", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT}, |
827 | {"mcasp0_ahclkr.gpio3_17", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT}, | 827 | {"mcasp0_ahclkr.gpio3_17", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT}, |
828 | {"gpmc_csn2.gpio1_31", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT}, | 828 | {"gpmc_csn2.gpio1_31", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT}, |
829 | {NULL, 0}, | 829 | {NULL, 0}, |
830 | }; | 830 | }; |
831 | 831 | ||
832 | static int backlight_enable = false; | 832 | static int backlight_enable = false; |
833 | 833 | ||
834 | static void enable_ecap0(int evm_id, int profile) | 834 | static void enable_ecap0(int evm_id, int profile) |
835 | { | 835 | { |
836 | backlight_enable = true; | 836 | backlight_enable = true; |
837 | } | 837 | } |
838 | 838 | ||
839 | static int __init ecap0_init(void) | 839 | static int __init ecap0_init(void) |
840 | { | 840 | { |
841 | int status = 0; | 841 | int status = 0; |
842 | 842 | ||
843 | if (backlight_enable) { | 843 | if (backlight_enable) { |
844 | setup_pin_mux(ecap0_pin_mux); | 844 | setup_pin_mux(ecap0_pin_mux); |
845 | 845 | ||
846 | status = gpio_request(AM335X_LCD_BL_PIN, "lcd bl\n"); | 846 | status = gpio_request(AM335X_LCD_BL_PIN, "lcd bl\n"); |
847 | if (status < 0) | 847 | if (status < 0) |
848 | pr_warn("Failed to request gpio for LCD backlight\n"); | 848 | pr_warn("Failed to request gpio for LCD backlight\n"); |
849 | 849 | ||
850 | gpio_direction_output(AM335X_LCD_BL_PIN, 1); | 850 | gpio_direction_output(AM335X_LCD_BL_PIN, 1); |
851 | } | 851 | } |
852 | return status; | 852 | return status; |
853 | } | 853 | } |
854 | late_initcall(ecap0_init); | 854 | late_initcall(ecap0_init); |
855 | 855 | ||
856 | static int __init conf_disp_pll(int rate) | 856 | static int __init conf_disp_pll(int rate) |
857 | { | 857 | { |
858 | struct clk *disp_pll; | 858 | struct clk *disp_pll; |
859 | int ret = -EINVAL; | 859 | int ret = -EINVAL; |
860 | 860 | ||
861 | disp_pll = clk_get(NULL, "dpll_disp_ck"); | 861 | disp_pll = clk_get(NULL, "dpll_disp_ck"); |
862 | if (IS_ERR(disp_pll)) { | 862 | if (IS_ERR(disp_pll)) { |
863 | pr_err("Cannot clk_get disp_pll\n"); | 863 | pr_err("Cannot clk_get disp_pll\n"); |
864 | goto out; | 864 | goto out; |
865 | } | 865 | } |
866 | 866 | ||
867 | ret = clk_set_rate(disp_pll, rate); | 867 | ret = clk_set_rate(disp_pll, rate); |
868 | clk_put(disp_pll); | 868 | clk_put(disp_pll); |
869 | out: | 869 | out: |
870 | return ret; | 870 | return ret; |
871 | } | 871 | } |
872 | 872 | ||
873 | static void lcdc_init(int evm_id, int profile) | 873 | static void lcdc_init(int evm_id, int profile) |
874 | { | 874 | { |
875 | 875 | ||
876 | setup_pin_mux(lcdc_pin_mux); | 876 | setup_pin_mux(lcdc_pin_mux); |
877 | 877 | ||
878 | if (conf_disp_pll(300000000)) { | 878 | if (conf_disp_pll(300000000)) { |
879 | pr_info("Failed configure display PLL, not attempting to" | 879 | pr_info("Failed configure display PLL, not attempting to" |
880 | "register LCDC\n"); | 880 | "register LCDC\n"); |
881 | return; | 881 | return; |
882 | } | 882 | } |
883 | 883 | ||
884 | if (am33xx_register_lcdc(&TFC_S9700RTWV35TR_01B_pdata)) | 884 | if (am33xx_register_lcdc(&TFC_S9700RTWV35TR_01B_pdata)) |
885 | pr_info("Failed to register LCDC device\n"); | 885 | pr_info("Failed to register LCDC device\n"); |
886 | return; | 886 | return; |
887 | } | 887 | } |
888 | 888 | ||
889 | static void tsc_init(int evm_id, int profile) | 889 | static void tsc_init(int evm_id, int profile) |
890 | { | 890 | { |
891 | int err; | 891 | int err; |
892 | 892 | ||
893 | if (gp_evm_revision == GP_EVM_REV_IS_1_1A) { | 893 | if (gp_evm_revision == GP_EVM_REV_IS_1_1A) { |
894 | am335x_touchscreen_data.analog_input = 1; | 894 | am335x_touchscreen_data.analog_input = 1; |
895 | pr_info("TSC connected to beta GP EVM\n"); | 895 | pr_info("TSC connected to beta GP EVM\n"); |
896 | } else { | 896 | } else { |
897 | am335x_touchscreen_data.analog_input = 0; | 897 | am335x_touchscreen_data.analog_input = 0; |
898 | pr_info("TSC connected to alpha GP EVM\n"); | 898 | pr_info("TSC connected to alpha GP EVM\n"); |
899 | } | 899 | } |
900 | setup_pin_mux(tsc_pin_mux); | 900 | setup_pin_mux(tsc_pin_mux); |
901 | err = platform_device_register(&tsc_device); | 901 | err = platform_device_register(&tsc_device); |
902 | if (err) | 902 | if (err) |
903 | pr_err("failed to register touchscreen device\n"); | 903 | pr_err("failed to register touchscreen device\n"); |
904 | } | 904 | } |
905 | 905 | ||
906 | static void rgmii1_init(int evm_id, int profile) | 906 | static void rgmii1_init(int evm_id, int profile) |
907 | { | 907 | { |
908 | setup_pin_mux(rgmii1_pin_mux); | 908 | setup_pin_mux(rgmii1_pin_mux); |
909 | return; | 909 | return; |
910 | } | 910 | } |
911 | 911 | ||
912 | static void rgmii2_init(int evm_id, int profile) | 912 | static void rgmii2_init(int evm_id, int profile) |
913 | { | 913 | { |
914 | setup_pin_mux(rgmii2_pin_mux); | 914 | setup_pin_mux(rgmii2_pin_mux); |
915 | return; | 915 | return; |
916 | } | 916 | } |
917 | 917 | ||
918 | static void mii1_init(int evm_id, int profile) | 918 | static void mii1_init(int evm_id, int profile) |
919 | { | 919 | { |
920 | setup_pin_mux(mii1_pin_mux); | 920 | setup_pin_mux(mii1_pin_mux); |
921 | return; | 921 | return; |
922 | } | 922 | } |
923 | 923 | ||
924 | static void rmii1_init(int evm_id, int profile) | 924 | static void rmii1_init(int evm_id, int profile) |
925 | { | 925 | { |
926 | setup_pin_mux(rmii1_pin_mux); | 926 | setup_pin_mux(rmii1_pin_mux); |
927 | return; | 927 | return; |
928 | } | 928 | } |
929 | 929 | ||
930 | static void usb0_init(int evm_id, int profile) | 930 | static void usb0_init(int evm_id, int profile) |
931 | { | 931 | { |
932 | setup_pin_mux(usb0_pin_mux); | 932 | setup_pin_mux(usb0_pin_mux); |
933 | return; | 933 | return; |
934 | } | 934 | } |
935 | 935 | ||
936 | static void usb1_init(int evm_id, int profile) | 936 | static void usb1_init(int evm_id, int profile) |
937 | { | 937 | { |
938 | setup_pin_mux(usb1_pin_mux); | 938 | setup_pin_mux(usb1_pin_mux); |
939 | return; | 939 | return; |
940 | } | 940 | } |
941 | 941 | ||
942 | /* setup uart3 */ | 942 | /* setup uart3 */ |
943 | static void uart3_init(int evm_id, int profile) | 943 | static void uart3_init(int evm_id, int profile) |
944 | { | 944 | { |
945 | setup_pin_mux(uart3_pin_mux); | 945 | setup_pin_mux(uart3_pin_mux); |
946 | return; | 946 | return; |
947 | } | 947 | } |
948 | 948 | ||
949 | /* NAND partition information */ | 949 | /* NAND partition information */ |
950 | static struct mtd_partition am335x_nand_partitions[] = { | 950 | static struct mtd_partition am335x_nand_partitions[] = { |
951 | /* All the partition sizes are listed in terms of NAND block size */ | 951 | /* All the partition sizes are listed in terms of NAND block size */ |
952 | { | 952 | { |
953 | .name = "SPL", | 953 | .name = "SPL", |
954 | .offset = 0, /* Offset = 0x0 */ | 954 | .offset = 0, /* Offset = 0x0 */ |
955 | .size = SZ_128K, | 955 | .size = SZ_128K, |
956 | }, | 956 | }, |
957 | { | 957 | { |
958 | .name = "SPL.backup1", | 958 | .name = "SPL.backup1", |
959 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x20000 */ | 959 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x20000 */ |
960 | .size = SZ_128K, | 960 | .size = SZ_128K, |
961 | }, | 961 | }, |
962 | { | 962 | { |
963 | .name = "SPL.backup2", | 963 | .name = "SPL.backup2", |
964 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x40000 */ | 964 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x40000 */ |
965 | .size = SZ_128K, | 965 | .size = SZ_128K, |
966 | }, | 966 | }, |
967 | { | 967 | { |
968 | .name = "SPL.backup3", | 968 | .name = "SPL.backup3", |
969 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x60000 */ | 969 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x60000 */ |
970 | .size = SZ_128K, | 970 | .size = SZ_128K, |
971 | }, | 971 | }, |
972 | { | 972 | { |
973 | .name = "U-Boot", | 973 | .name = "U-Boot", |
974 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */ | 974 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */ |
975 | .size = 15 * SZ_128K, | 975 | .size = 15 * SZ_128K, |
976 | }, | 976 | }, |
977 | { | 977 | { |
978 | .name = "U-Boot Env", | 978 | .name = "U-Boot Env", |
979 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x260000 */ | 979 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x260000 */ |
980 | .size = 1 * SZ_128K, | 980 | .size = 1 * SZ_128K, |
981 | }, | 981 | }, |
982 | { | 982 | { |
983 | .name = "Kernel", | 983 | .name = "Kernel", |
984 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */ | 984 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */ |
985 | .size = 40 * SZ_128K, | 985 | .size = 40 * SZ_128K, |
986 | }, | 986 | }, |
987 | { | 987 | { |
988 | .name = "File System", | 988 | .name = "File System", |
989 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x780000 */ | 989 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x780000 */ |
990 | .size = MTDPART_SIZ_FULL, | 990 | .size = MTDPART_SIZ_FULL, |
991 | }, | 991 | }, |
992 | }; | 992 | }; |
993 | 993 | ||
994 | /* SPI 0/1 Platform Data */ | 994 | /* SPI 0/1 Platform Data */ |
995 | /* SPI flash information */ | 995 | /* SPI flash information */ |
996 | static struct mtd_partition am335x_spi_partitions[] = { | 996 | static struct mtd_partition am335x_spi_partitions[] = { |
997 | /* All the partition sizes are listed in terms of erase size */ | 997 | /* All the partition sizes are listed in terms of erase size */ |
998 | { | 998 | { |
999 | .name = "U-Boot-min", | 999 | .name = "U-Boot-min", |
1000 | .offset = 0, | 1000 | .offset = 0, |
1001 | .size = SZ_128K, | 1001 | .size = SZ_128K, |
1002 | .mask_flags = MTD_WRITEABLE, /* force read-only */ | 1002 | .mask_flags = MTD_WRITEABLE, /* force read-only */ |
1003 | }, | 1003 | }, |
1004 | { | 1004 | { |
1005 | .name = "U-Boot", | 1005 | .name = "U-Boot", |
1006 | .offset = MTDPART_OFS_APPEND, | 1006 | .offset = MTDPART_OFS_APPEND, |
1007 | .size = 2 * SZ_128K, | 1007 | .size = 2 * SZ_128K, |
1008 | .mask_flags = MTD_WRITEABLE, /* force read-only */ | 1008 | .mask_flags = MTD_WRITEABLE, /* force read-only */ |
1009 | }, | 1009 | }, |
1010 | { | 1010 | { |
1011 | .name = "U-Boot Env", | 1011 | .name = "U-Boot Env", |
1012 | .offset = MTDPART_OFS_APPEND, | 1012 | .offset = MTDPART_OFS_APPEND, |
1013 | .size = 2 * SZ_4K, | 1013 | .size = 2 * SZ_4K, |
1014 | }, | 1014 | }, |
1015 | { | 1015 | { |
1016 | .name = "Kernel", | 1016 | .name = "Kernel", |
1017 | .offset = MTDPART_OFS_APPEND, | 1017 | .offset = MTDPART_OFS_APPEND, |
1018 | .size = 28 * SZ_128K, | 1018 | .size = 28 * SZ_128K, |
1019 | }, | 1019 | }, |
1020 | { | 1020 | { |
1021 | .name = "File System", | 1021 | .name = "File System", |
1022 | .offset = MTDPART_OFS_APPEND, | 1022 | .offset = MTDPART_OFS_APPEND, |
1023 | .size = MTDPART_SIZ_FULL, /* size ~= 1.1 MiB */ | 1023 | .size = MTDPART_SIZ_FULL, /* size ~= 1.1 MiB */ |
1024 | } | 1024 | } |
1025 | }; | 1025 | }; |
1026 | 1026 | ||
1027 | static const struct flash_platform_data am335x_spi_flash = { | 1027 | static const struct flash_platform_data am335x_spi_flash = { |
1028 | .type = "w25q64", | 1028 | .type = "w25q64", |
1029 | .name = "spi_flash", | 1029 | .name = "spi_flash", |
1030 | .parts = am335x_spi_partitions, | 1030 | .parts = am335x_spi_partitions, |
1031 | .nr_parts = ARRAY_SIZE(am335x_spi_partitions), | 1031 | .nr_parts = ARRAY_SIZE(am335x_spi_partitions), |
1032 | }; | 1032 | }; |
1033 | 1033 | ||
1034 | /* | 1034 | /* |
1035 | * SPI Flash works at 80Mhz however SPI Controller works at 48MHz. | 1035 | * SPI Flash works at 80Mhz however SPI Controller works at 48MHz. |
1036 | * So setup Max speed to be less than that of Controller speed | 1036 | * So setup Max speed to be less than that of Controller speed |
1037 | */ | 1037 | */ |
1038 | static struct spi_board_info am335x_spi0_slave_info[] = { | 1038 | static struct spi_board_info am335x_spi0_slave_info[] = { |
1039 | { | 1039 | { |
1040 | .modalias = "m25p80", | 1040 | .modalias = "m25p80", |
1041 | .platform_data = &am335x_spi_flash, | 1041 | .platform_data = &am335x_spi_flash, |
1042 | .irq = -1, | 1042 | .irq = -1, |
1043 | .max_speed_hz = 24000000, | 1043 | .max_speed_hz = 24000000, |
1044 | .bus_num = 1, | 1044 | .bus_num = 1, |
1045 | .chip_select = 0, | 1045 | .chip_select = 0, |
1046 | }, | 1046 | }, |
1047 | }; | 1047 | }; |
1048 | 1048 | ||
1049 | static struct spi_board_info am335x_spi1_slave_info[] = { | 1049 | static struct spi_board_info am335x_spi1_slave_info[] = { |
1050 | { | 1050 | { |
1051 | .modalias = "m25p80", | 1051 | .modalias = "m25p80", |
1052 | .platform_data = &am335x_spi_flash, | 1052 | .platform_data = &am335x_spi_flash, |
1053 | .irq = -1, | 1053 | .irq = -1, |
1054 | .max_speed_hz = 12000000, | 1054 | .max_speed_hz = 12000000, |
1055 | .bus_num = 2, | 1055 | .bus_num = 2, |
1056 | .chip_select = 0, | 1056 | .chip_select = 0, |
1057 | }, | 1057 | }, |
1058 | }; | 1058 | }; |
1059 | 1059 | ||
1060 | static void evm_nand_init(int evm_id, int profile) | 1060 | static void evm_nand_init(int evm_id, int profile) |
1061 | { | 1061 | { |
1062 | setup_pin_mux(nand_pin_mux); | 1062 | setup_pin_mux(nand_pin_mux); |
1063 | board_nand_init(am335x_nand_partitions, | 1063 | board_nand_init(am335x_nand_partitions, |
1064 | ARRAY_SIZE(am335x_nand_partitions), 0, 0); | 1064 | ARRAY_SIZE(am335x_nand_partitions), 0, 0); |
1065 | } | 1065 | } |
1066 | 1066 | ||
1067 | static struct lis3lv02d_platform_data lis331dlh_pdata = { | 1067 | static struct lis3lv02d_platform_data lis331dlh_pdata = { |
1068 | .click_flags = LIS3_CLICK_SINGLE_X | | 1068 | .click_flags = LIS3_CLICK_SINGLE_X | |
1069 | LIS3_CLICK_SINGLE_Y | | 1069 | LIS3_CLICK_SINGLE_Y | |
1070 | LIS3_CLICK_SINGLE_Z, | 1070 | LIS3_CLICK_SINGLE_Z, |
1071 | .wakeup_flags = LIS3_WAKEUP_X_LO | LIS3_WAKEUP_X_HI | | 1071 | .wakeup_flags = LIS3_WAKEUP_X_LO | LIS3_WAKEUP_X_HI | |
1072 | LIS3_WAKEUP_Y_LO | LIS3_WAKEUP_Y_HI | | 1072 | LIS3_WAKEUP_Y_LO | LIS3_WAKEUP_Y_HI | |
1073 | LIS3_WAKEUP_Z_LO | LIS3_WAKEUP_Z_HI, | 1073 | LIS3_WAKEUP_Z_LO | LIS3_WAKEUP_Z_HI, |
1074 | .irq_cfg = LIS3_IRQ1_CLICK | LIS3_IRQ2_CLICK, | 1074 | .irq_cfg = LIS3_IRQ1_CLICK | LIS3_IRQ2_CLICK, |
1075 | .wakeup_thresh = 10, | 1075 | .wakeup_thresh = 10, |
1076 | .click_thresh_x = 10, | 1076 | .click_thresh_x = 10, |
1077 | .click_thresh_y = 10, | 1077 | .click_thresh_y = 10, |
1078 | .click_thresh_z = 10, | 1078 | .click_thresh_z = 10, |
1079 | .g_range = 2, | 1079 | .g_range = 2, |
1080 | .st_min_limits[0] = 120, | 1080 | .st_min_limits[0] = 120, |
1081 | .st_min_limits[1] = 120, | 1081 | .st_min_limits[1] = 120, |
1082 | .st_min_limits[2] = 140, | 1082 | .st_min_limits[2] = 140, |
1083 | .st_max_limits[0] = 550, | 1083 | .st_max_limits[0] = 550, |
1084 | .st_max_limits[1] = 550, | 1084 | .st_max_limits[1] = 550, |
1085 | .st_max_limits[2] = 750, | 1085 | .st_max_limits[2] = 750, |
1086 | }; | 1086 | }; |
1087 | 1087 | ||
1088 | static struct i2c_board_info am335x_i2c_boardinfo1[] = { | 1088 | static struct i2c_board_info am335x_i2c_boardinfo1[] = { |
1089 | { | 1089 | { |
1090 | I2C_BOARD_INFO("tlv320aic3x", 0x1b), | 1090 | I2C_BOARD_INFO("tlv320aic3x", 0x1b), |
1091 | }, | 1091 | }, |
1092 | { | 1092 | { |
1093 | I2C_BOARD_INFO("lis331dlh", 0x18), | 1093 | I2C_BOARD_INFO("lis331dlh", 0x18), |
1094 | .platform_data = &lis331dlh_pdata, | 1094 | .platform_data = &lis331dlh_pdata, |
1095 | }, | 1095 | }, |
1096 | { | 1096 | { |
1097 | I2C_BOARD_INFO("tsl2550", 0x39), | 1097 | I2C_BOARD_INFO("tsl2550", 0x39), |
1098 | }, | 1098 | }, |
1099 | { | 1099 | { |
1100 | I2C_BOARD_INFO("tmp275", 0x48), | 1100 | I2C_BOARD_INFO("tmp275", 0x48), |
1101 | }, | 1101 | }, |
1102 | }; | 1102 | }; |
1103 | 1103 | ||
1104 | static void i2c1_init(int evm_id, int profile) | 1104 | static void i2c1_init(int evm_id, int profile) |
1105 | { | 1105 | { |
1106 | setup_pin_mux(i2c1_pin_mux); | 1106 | setup_pin_mux(i2c1_pin_mux); |
1107 | omap_register_i2c_bus(2, 100, am335x_i2c_boardinfo1, | 1107 | omap_register_i2c_bus(2, 100, am335x_i2c_boardinfo1, |
1108 | ARRAY_SIZE(am335x_i2c_boardinfo1)); | 1108 | ARRAY_SIZE(am335x_i2c_boardinfo1)); |
1109 | return; | 1109 | return; |
1110 | } | 1110 | } |
1111 | 1111 | ||
1112 | /* Setup McASP 1 */ | 1112 | /* Setup McASP 1 */ |
1113 | static void mcasp1_init(int evm_id, int profile) | 1113 | static void mcasp1_init(int evm_id, int profile) |
1114 | { | 1114 | { |
1115 | /* Configure McASP */ | 1115 | /* Configure McASP */ |
1116 | setup_pin_mux(mcasp1_pin_mux); | 1116 | setup_pin_mux(mcasp1_pin_mux); |
1117 | am335x_register_mcasp1(&am335x_evm_snd_data1); | 1117 | am335x_register_mcasp1(&am335x_evm_snd_data1); |
1118 | return; | 1118 | return; |
1119 | } | 1119 | } |
1120 | 1120 | ||
1121 | static void mmc1_init(int evm_id, int profile) | 1121 | static void mmc1_init(int evm_id, int profile) |
1122 | { | 1122 | { |
1123 | setup_pin_mux(mmc1_pin_mux); | 1123 | setup_pin_mux(mmc1_pin_mux); |
1124 | 1124 | ||
1125 | am335x_mmc[1].mmc = 2; | 1125 | am335x_mmc[1].mmc = 2; |
1126 | am335x_mmc[1].caps = MMC_CAP_4_BIT_DATA; | 1126 | am335x_mmc[1].caps = MMC_CAP_4_BIT_DATA; |
1127 | am335x_mmc[1].gpio_cd = GPIO_TO_PIN(3, 15); | 1127 | am335x_mmc[1].gpio_cd = GPIO_TO_PIN(2, 2); |
1128 | am335x_mmc[1].gpio_wp = GPIO_TO_PIN(0, 14); | 1128 | am335x_mmc[1].gpio_wp = GPIO_TO_PIN(1, 29); |
1129 | am335x_mmc[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */ | 1129 | am335x_mmc[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */ |
1130 | 1130 | ||
1131 | /* mmc will be initialized when mmc0_init is called */ | 1131 | /* mmc will be initialized when mmc0_init is called */ |
1132 | return; | 1132 | return; |
1133 | } | 1133 | } |
1134 | 1134 | ||
1135 | static void mmc2_wl12xx_init(int evm_id, int profile) | 1135 | static void mmc2_wl12xx_init(int evm_id, int profile) |
1136 | { | 1136 | { |
1137 | setup_pin_mux(mmc2_wl12xx_pin_mux); | 1137 | setup_pin_mux(mmc2_wl12xx_pin_mux); |
1138 | 1138 | ||
1139 | am335x_mmc[1].mmc = 3; | 1139 | am335x_mmc[1].mmc = 3; |
1140 | am335x_mmc[1].name = "wl1271"; | 1140 | am335x_mmc[1].name = "wl1271"; |
1141 | am335x_mmc[1].caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD | 1141 | am335x_mmc[1].caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD |
1142 | | MMC_PM_KEEP_POWER; | 1142 | | MMC_PM_KEEP_POWER; |
1143 | am335x_mmc[1].nonremovable = true; | 1143 | am335x_mmc[1].nonremovable = true; |
1144 | am335x_mmc[1].gpio_cd = -EINVAL; | 1144 | am335x_mmc[1].gpio_cd = -EINVAL; |
1145 | am335x_mmc[1].gpio_wp = -EINVAL; | 1145 | am335x_mmc[1].gpio_wp = -EINVAL; |
1146 | am335x_mmc[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */ | 1146 | am335x_mmc[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */ |
1147 | 1147 | ||
1148 | /* mmc will be initialized when mmc0_init is called */ | 1148 | /* mmc will be initialized when mmc0_init is called */ |
1149 | return; | 1149 | return; |
1150 | } | 1150 | } |
1151 | 1151 | ||
1152 | static void uart1_wl12xx_init(int evm_id, int profile) | 1152 | static void uart1_wl12xx_init(int evm_id, int profile) |
1153 | { | 1153 | { |
1154 | setup_pin_mux(uart1_wl12xx_pin_mux); | 1154 | setup_pin_mux(uart1_wl12xx_pin_mux); |
1155 | } | 1155 | } |
1156 | 1156 | ||
1157 | static void wl12xx_bluetooth_enable(void) | 1157 | static void wl12xx_bluetooth_enable(void) |
1158 | { | 1158 | { |
1159 | int status = gpio_request(am335xevm_wlan_data.bt_enable_gpio, | 1159 | int status = gpio_request(am335xevm_wlan_data.bt_enable_gpio, |
1160 | "bt_en\n"); | 1160 | "bt_en\n"); |
1161 | if (status < 0) | 1161 | if (status < 0) |
1162 | pr_err("Failed to request gpio for bt_enable"); | 1162 | pr_err("Failed to request gpio for bt_enable"); |
1163 | 1163 | ||
1164 | pr_info("Configure Bluetooth Enable pin...\n"); | 1164 | pr_info("Configure Bluetooth Enable pin...\n"); |
1165 | gpio_direction_output(am335xevm_wlan_data.bt_enable_gpio, 0); | 1165 | gpio_direction_output(am335xevm_wlan_data.bt_enable_gpio, 0); |
1166 | } | 1166 | } |
1167 | 1167 | ||
1168 | static int wl12xx_set_power(struct device *dev, int slot, int on, int vdd) | 1168 | static int wl12xx_set_power(struct device *dev, int slot, int on, int vdd) |
1169 | { | 1169 | { |
1170 | if (on) { | 1170 | if (on) { |
1171 | gpio_set_value(am335xevm_wlan_data.wlan_enable_gpio, 1); | 1171 | gpio_set_value(am335xevm_wlan_data.wlan_enable_gpio, 1); |
1172 | mdelay(70); | 1172 | mdelay(70); |
1173 | } | 1173 | } |
1174 | else | 1174 | else |
1175 | gpio_set_value(am335xevm_wlan_data.wlan_enable_gpio, 0); | 1175 | gpio_set_value(am335xevm_wlan_data.wlan_enable_gpio, 0); |
1176 | 1176 | ||
1177 | return 0; | 1177 | return 0; |
1178 | } | 1178 | } |
1179 | 1179 | ||
1180 | static void wl12xx_init(int evm_id, int profile) | 1180 | static void wl12xx_init(int evm_id, int profile) |
1181 | { | 1181 | { |
1182 | struct device *dev; | 1182 | struct device *dev; |
1183 | struct omap_mmc_platform_data *pdata; | 1183 | struct omap_mmc_platform_data *pdata; |
1184 | int ret; | 1184 | int ret; |
1185 | 1185 | ||
1186 | /* Register WLAN and BT enable pins based on the evm board revision */ | 1186 | /* Register WLAN and BT enable pins based on the evm board revision */ |
1187 | if (gp_evm_revision == GP_EVM_REV_IS_1_1A) { | 1187 | if (gp_evm_revision == GP_EVM_REV_IS_1_1A) { |
1188 | am335xevm_wlan_data.wlan_enable_gpio = GPIO_TO_PIN(1, 16); | 1188 | am335xevm_wlan_data.wlan_enable_gpio = GPIO_TO_PIN(1, 16); |
1189 | am335xevm_wlan_data.bt_enable_gpio = GPIO_TO_PIN(3, 21); | 1189 | am335xevm_wlan_data.bt_enable_gpio = GPIO_TO_PIN(3, 21); |
1190 | } | 1190 | } |
1191 | else { | 1191 | else { |
1192 | am335xevm_wlan_data.wlan_enable_gpio = GPIO_TO_PIN(1, 30); | 1192 | am335xevm_wlan_data.wlan_enable_gpio = GPIO_TO_PIN(1, 30); |
1193 | am335xevm_wlan_data.bt_enable_gpio = GPIO_TO_PIN(1, 31); | 1193 | am335xevm_wlan_data.bt_enable_gpio = GPIO_TO_PIN(1, 31); |
1194 | } | 1194 | } |
1195 | 1195 | ||
1196 | wl12xx_bluetooth_enable(); | 1196 | wl12xx_bluetooth_enable(); |
1197 | 1197 | ||
1198 | if (wl12xx_set_platform_data(&am335xevm_wlan_data)) | 1198 | if (wl12xx_set_platform_data(&am335xevm_wlan_data)) |
1199 | pr_err("error setting wl12xx data\n"); | 1199 | pr_err("error setting wl12xx data\n"); |
1200 | 1200 | ||
1201 | dev = am335x_mmc[1].dev; | 1201 | dev = am335x_mmc[1].dev; |
1202 | if (!dev) { | 1202 | if (!dev) { |
1203 | pr_err("wl12xx mmc device initialization failed\n"); | 1203 | pr_err("wl12xx mmc device initialization failed\n"); |
1204 | goto out; | 1204 | goto out; |
1205 | } | 1205 | } |
1206 | 1206 | ||
1207 | pdata = dev->platform_data; | 1207 | pdata = dev->platform_data; |
1208 | if (!pdata) { | 1208 | if (!pdata) { |
1209 | pr_err("Platfrom data of wl12xx device not set\n"); | 1209 | pr_err("Platfrom data of wl12xx device not set\n"); |
1210 | goto out; | 1210 | goto out; |
1211 | } | 1211 | } |
1212 | 1212 | ||
1213 | ret = gpio_request_one(am335xevm_wlan_data.wlan_enable_gpio, | 1213 | ret = gpio_request_one(am335xevm_wlan_data.wlan_enable_gpio, |
1214 | GPIOF_OUT_INIT_LOW, "wlan_en"); | 1214 | GPIOF_OUT_INIT_LOW, "wlan_en"); |
1215 | if (ret) { | 1215 | if (ret) { |
1216 | pr_err("Error requesting wlan enable gpio: %d\n", ret); | 1216 | pr_err("Error requesting wlan enable gpio: %d\n", ret); |
1217 | goto out; | 1217 | goto out; |
1218 | } | 1218 | } |
1219 | 1219 | ||
1220 | if (gp_evm_revision == GP_EVM_REV_IS_1_1A) | 1220 | if (gp_evm_revision == GP_EVM_REV_IS_1_1A) |
1221 | setup_pin_mux(wl12xx_pin_mux_evm_rev1_1a); | 1221 | setup_pin_mux(wl12xx_pin_mux_evm_rev1_1a); |
1222 | else | 1222 | else |
1223 | setup_pin_mux(wl12xx_pin_mux_evm_rev1_0); | 1223 | setup_pin_mux(wl12xx_pin_mux_evm_rev1_0); |
1224 | 1224 | ||
1225 | pdata->slots[0].set_power = wl12xx_set_power; | 1225 | pdata->slots[0].set_power = wl12xx_set_power; |
1226 | out: | 1226 | out: |
1227 | return; | 1227 | return; |
1228 | } | 1228 | } |
1229 | 1229 | ||
1230 | static void d_can_init(int evm_id, int profile) | 1230 | static void d_can_init(int evm_id, int profile) |
1231 | { | 1231 | { |
1232 | switch (evm_id) { | 1232 | switch (evm_id) { |
1233 | case IND_AUT_MTR_EVM: | 1233 | case IND_AUT_MTR_EVM: |
1234 | if ((profile == PROFILE_0) || (profile == PROFILE_1)) { | 1234 | if ((profile == PROFILE_0) || (profile == PROFILE_1)) { |
1235 | setup_pin_mux(d_can_ia_pin_mux); | 1235 | setup_pin_mux(d_can_ia_pin_mux); |
1236 | /* Instance Zero */ | 1236 | /* Instance Zero */ |
1237 | am33xx_d_can_init(0); | 1237 | am33xx_d_can_init(0); |
1238 | } | 1238 | } |
1239 | break; | 1239 | break; |
1240 | case GEN_PURP_EVM: | 1240 | case GEN_PURP_EVM: |
1241 | if (profile == PROFILE_1) { | 1241 | if (profile == PROFILE_1) { |
1242 | setup_pin_mux(d_can_gp_pin_mux); | 1242 | setup_pin_mux(d_can_gp_pin_mux); |
1243 | /* Instance One */ | 1243 | /* Instance One */ |
1244 | am33xx_d_can_init(1); | 1244 | am33xx_d_can_init(1); |
1245 | } | 1245 | } |
1246 | break; | 1246 | break; |
1247 | default: | 1247 | default: |
1248 | break; | 1248 | break; |
1249 | } | 1249 | } |
1250 | } | 1250 | } |
1251 | 1251 | ||
1252 | static void mmc0_init(int evm_id, int profile) | 1252 | static void mmc0_init(int evm_id, int profile) |
1253 | { | 1253 | { |
1254 | setup_pin_mux(mmc0_pin_mux); | 1254 | setup_pin_mux(mmc0_pin_mux); |
1255 | 1255 | ||
1256 | omap2_hsmmc_init(am335x_mmc); | 1256 | omap2_hsmmc_init(am335x_mmc); |
1257 | return; | 1257 | return; |
1258 | } | 1258 | } |
1259 | 1259 | ||
1260 | static void mmc0_no_cd_init(int evm_id, int profile) | 1260 | static void mmc0_no_cd_init(int evm_id, int profile) |
1261 | { | 1261 | { |
1262 | setup_pin_mux(mmc0_no_cd_pin_mux); | 1262 | setup_pin_mux(mmc0_no_cd_pin_mux); |
1263 | 1263 | ||
1264 | omap2_hsmmc_init(am335x_mmc); | 1264 | omap2_hsmmc_init(am335x_mmc); |
1265 | return; | 1265 | return; |
1266 | } | 1266 | } |
1267 | 1267 | ||
1268 | 1268 | ||
1269 | /* setup spi0 */ | 1269 | /* setup spi0 */ |
1270 | static void spi0_init(int evm_id, int profile) | 1270 | static void spi0_init(int evm_id, int profile) |
1271 | { | 1271 | { |
1272 | setup_pin_mux(spi0_pin_mux); | 1272 | setup_pin_mux(spi0_pin_mux); |
1273 | spi_register_board_info(am335x_spi0_slave_info, | 1273 | spi_register_board_info(am335x_spi0_slave_info, |
1274 | ARRAY_SIZE(am335x_spi0_slave_info)); | 1274 | ARRAY_SIZE(am335x_spi0_slave_info)); |
1275 | return; | 1275 | return; |
1276 | } | 1276 | } |
1277 | 1277 | ||
1278 | /* setup spi1 */ | 1278 | /* setup spi1 */ |
1279 | static void spi1_init(int evm_id, int profile) | 1279 | static void spi1_init(int evm_id, int profile) |
1280 | { | 1280 | { |
1281 | setup_pin_mux(spi1_pin_mux); | 1281 | setup_pin_mux(spi1_pin_mux); |
1282 | spi_register_board_info(am335x_spi1_slave_info, | 1282 | spi_register_board_info(am335x_spi1_slave_info, |
1283 | ARRAY_SIZE(am335x_spi1_slave_info)); | 1283 | ARRAY_SIZE(am335x_spi1_slave_info)); |
1284 | return; | 1284 | return; |
1285 | } | 1285 | } |
1286 | 1286 | ||
1287 | 1287 | ||
1288 | static int beaglebone_phy_fixup(struct phy_device *phydev) | 1288 | static int beaglebone_phy_fixup(struct phy_device *phydev) |
1289 | { | 1289 | { |
1290 | phydev->supported &= ~(SUPPORTED_100baseT_Half | | 1290 | phydev->supported &= ~(SUPPORTED_100baseT_Half | |
1291 | SUPPORTED_100baseT_Full); | 1291 | SUPPORTED_100baseT_Full); |
1292 | 1292 | ||
1293 | return 0; | 1293 | return 0; |
1294 | } | 1294 | } |
1295 | 1295 | ||
1296 | #ifdef CONFIG_TLK110_WORKAROUND | 1296 | #ifdef CONFIG_TLK110_WORKAROUND |
1297 | static int am335x_tlk110_phy_fixup(struct phy_device *phydev) | 1297 | static int am335x_tlk110_phy_fixup(struct phy_device *phydev) |
1298 | { | 1298 | { |
1299 | unsigned int val; | 1299 | unsigned int val; |
1300 | 1300 | ||
1301 | /* This is done as a workaround to support TLK110 rev1.0 phy */ | 1301 | /* This is done as a workaround to support TLK110 rev1.0 phy */ |
1302 | val = phy_read(phydev, TLK110_COARSEGAIN_REG); | 1302 | val = phy_read(phydev, TLK110_COARSEGAIN_REG); |
1303 | phy_write(phydev, TLK110_COARSEGAIN_REG, (val | TLK110_COARSEGAIN_VAL)); | 1303 | phy_write(phydev, TLK110_COARSEGAIN_REG, (val | TLK110_COARSEGAIN_VAL)); |
1304 | 1304 | ||
1305 | val = phy_read(phydev, TLK110_LPFHPF_REG); | 1305 | val = phy_read(phydev, TLK110_LPFHPF_REG); |
1306 | phy_write(phydev, TLK110_LPFHPF_REG, (val | TLK110_LPFHPF_VAL)); | 1306 | phy_write(phydev, TLK110_LPFHPF_REG, (val | TLK110_LPFHPF_VAL)); |
1307 | 1307 | ||
1308 | val = phy_read(phydev, TLK110_SPAREANALOG_REG); | 1308 | val = phy_read(phydev, TLK110_SPAREANALOG_REG); |
1309 | phy_write(phydev, TLK110_SPAREANALOG_REG, (val | TLK110_SPANALOG_VAL)); | 1309 | phy_write(phydev, TLK110_SPAREANALOG_REG, (val | TLK110_SPANALOG_VAL)); |
1310 | 1310 | ||
1311 | val = phy_read(phydev, TLK110_VRCR_REG); | 1311 | val = phy_read(phydev, TLK110_VRCR_REG); |
1312 | phy_write(phydev, TLK110_VRCR_REG, (val | TLK110_VRCR_VAL)); | 1312 | phy_write(phydev, TLK110_VRCR_REG, (val | TLK110_VRCR_VAL)); |
1313 | 1313 | ||
1314 | val = phy_read(phydev, TLK110_SETFFE_REG); | 1314 | val = phy_read(phydev, TLK110_SETFFE_REG); |
1315 | phy_write(phydev, TLK110_SETFFE_REG, (val | TLK110_SETFFE_VAL)); | 1315 | phy_write(phydev, TLK110_SETFFE_REG, (val | TLK110_SETFFE_VAL)); |
1316 | 1316 | ||
1317 | val = phy_read(phydev, TLK110_FTSP_REG); | 1317 | val = phy_read(phydev, TLK110_FTSP_REG); |
1318 | phy_write(phydev, TLK110_FTSP_REG, (val | TLK110_FTSP_VAL)); | 1318 | phy_write(phydev, TLK110_FTSP_REG, (val | TLK110_FTSP_VAL)); |
1319 | 1319 | ||
1320 | val = phy_read(phydev, TLK110_ALFATPIDL_REG); | 1320 | val = phy_read(phydev, TLK110_ALFATPIDL_REG); |
1321 | phy_write(phydev, TLK110_ALFATPIDL_REG, (val | TLK110_ALFATPIDL_VAL)); | 1321 | phy_write(phydev, TLK110_ALFATPIDL_REG, (val | TLK110_ALFATPIDL_VAL)); |
1322 | 1322 | ||
1323 | val = phy_read(phydev, TLK110_PSCOEF21_REG); | 1323 | val = phy_read(phydev, TLK110_PSCOEF21_REG); |
1324 | phy_write(phydev, TLK110_PSCOEF21_REG, (val | TLK110_PSCOEF21_VAL)); | 1324 | phy_write(phydev, TLK110_PSCOEF21_REG, (val | TLK110_PSCOEF21_VAL)); |
1325 | 1325 | ||
1326 | val = phy_read(phydev, TLK110_PSCOEF3_REG); | 1326 | val = phy_read(phydev, TLK110_PSCOEF3_REG); |
1327 | phy_write(phydev, TLK110_PSCOEF3_REG, (val | TLK110_PSCOEF3_VAL)); | 1327 | phy_write(phydev, TLK110_PSCOEF3_REG, (val | TLK110_PSCOEF3_VAL)); |
1328 | 1328 | ||
1329 | val = phy_read(phydev, TLK110_ALFAFACTOR1_REG); | 1329 | val = phy_read(phydev, TLK110_ALFAFACTOR1_REG); |
1330 | phy_write(phydev, TLK110_ALFAFACTOR1_REG, (val | TLK110_ALFACTOR1_VAL)); | 1330 | phy_write(phydev, TLK110_ALFAFACTOR1_REG, (val | TLK110_ALFACTOR1_VAL)); |
1331 | 1331 | ||
1332 | val = phy_read(phydev, TLK110_ALFAFACTOR2_REG); | 1332 | val = phy_read(phydev, TLK110_ALFAFACTOR2_REG); |
1333 | phy_write(phydev, TLK110_ALFAFACTOR2_REG, (val | TLK110_ALFACTOR2_VAL)); | 1333 | phy_write(phydev, TLK110_ALFAFACTOR2_REG, (val | TLK110_ALFACTOR2_VAL)); |
1334 | 1334 | ||
1335 | val = phy_read(phydev, TLK110_CFGPS_REG); | 1335 | val = phy_read(phydev, TLK110_CFGPS_REG); |
1336 | phy_write(phydev, TLK110_CFGPS_REG, (val | TLK110_CFGPS_VAL)); | 1336 | phy_write(phydev, TLK110_CFGPS_REG, (val | TLK110_CFGPS_VAL)); |
1337 | 1337 | ||
1338 | val = phy_read(phydev, TLK110_FTSPTXGAIN_REG); | 1338 | val = phy_read(phydev, TLK110_FTSPTXGAIN_REG); |
1339 | phy_write(phydev, TLK110_FTSPTXGAIN_REG, (val | TLK110_FTSPTXGAIN_VAL)); | 1339 | phy_write(phydev, TLK110_FTSPTXGAIN_REG, (val | TLK110_FTSPTXGAIN_VAL)); |
1340 | 1340 | ||
1341 | val = phy_read(phydev, TLK110_SWSCR3_REG); | 1341 | val = phy_read(phydev, TLK110_SWSCR3_REG); |
1342 | phy_write(phydev, TLK110_SWSCR3_REG, (val | TLK110_SWSCR3_VAL)); | 1342 | phy_write(phydev, TLK110_SWSCR3_REG, (val | TLK110_SWSCR3_VAL)); |
1343 | 1343 | ||
1344 | val = phy_read(phydev, TLK110_SCFALLBACK_REG); | 1344 | val = phy_read(phydev, TLK110_SCFALLBACK_REG); |
1345 | phy_write(phydev, TLK110_SCFALLBACK_REG, (val | TLK110_SCFALLBACK_VAL)); | 1345 | phy_write(phydev, TLK110_SCFALLBACK_REG, (val | TLK110_SCFALLBACK_VAL)); |
1346 | 1346 | ||
1347 | val = phy_read(phydev, TLK110_PHYRCR_REG); | 1347 | val = phy_read(phydev, TLK110_PHYRCR_REG); |
1348 | phy_write(phydev, TLK110_PHYRCR_REG, (val | TLK110_PHYRCR_VAL)); | 1348 | phy_write(phydev, TLK110_PHYRCR_REG, (val | TLK110_PHYRCR_VAL)); |
1349 | 1349 | ||
1350 | return 0; | 1350 | return 0; |
1351 | } | 1351 | } |
1352 | #endif | 1352 | #endif |
1353 | 1353 | ||
1354 | static void profibus_init(int evm_id, int profile) | 1354 | static void profibus_init(int evm_id, int profile) |
1355 | { | 1355 | { |
1356 | setup_pin_mux(profibus_pin_mux); | 1356 | setup_pin_mux(profibus_pin_mux); |
1357 | return; | 1357 | return; |
1358 | } | 1358 | } |
1359 | 1359 | ||
1360 | /* Low-Cost EVM */ | 1360 | /* Low-Cost EVM */ |
1361 | static struct evm_dev_cfg low_cost_evm_dev_cfg[] = { | 1361 | static struct evm_dev_cfg low_cost_evm_dev_cfg[] = { |
1362 | {rgmii1_init, DEV_ON_BASEBOARD, PROFILE_NONE}, | 1362 | {rgmii1_init, DEV_ON_BASEBOARD, PROFILE_NONE}, |
1363 | {usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE}, | 1363 | {usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE}, |
1364 | {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE}, | 1364 | {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE}, |
1365 | {evm_nand_init, DEV_ON_BASEBOARD, PROFILE_NONE}, | 1365 | {evm_nand_init, DEV_ON_BASEBOARD, PROFILE_NONE}, |
1366 | {NULL, 0, 0}, | 1366 | {NULL, 0, 0}, |
1367 | }; | 1367 | }; |
1368 | 1368 | ||
1369 | /* General Purpose EVM */ | 1369 | /* General Purpose EVM */ |
1370 | static struct evm_dev_cfg gen_purp_evm_dev_cfg[] = { | 1370 | static struct evm_dev_cfg gen_purp_evm_dev_cfg[] = { |
1371 | {enable_ecap0, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 | | 1371 | {enable_ecap0, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 | |
1372 | PROFILE_2 | PROFILE_7) }, | 1372 | PROFILE_2 | PROFILE_7) }, |
1373 | {lcdc_init, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 | | 1373 | {lcdc_init, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 | |
1374 | PROFILE_2 | PROFILE_7) }, | 1374 | PROFILE_2 | PROFILE_7) }, |
1375 | {tsc_init, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 | | 1375 | {tsc_init, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 | |
1376 | PROFILE_2 | PROFILE_7) }, | 1376 | PROFILE_2 | PROFILE_7) }, |
1377 | {rgmii1_init, DEV_ON_BASEBOARD, PROFILE_ALL}, | 1377 | {rgmii1_init, DEV_ON_BASEBOARD, PROFILE_ALL}, |
1378 | {rgmii2_init, DEV_ON_DGHTR_BRD, (PROFILE_1 | PROFILE_2 | | 1378 | {rgmii2_init, DEV_ON_DGHTR_BRD, (PROFILE_1 | PROFILE_2 | |
1379 | PROFILE_4 | PROFILE_6) }, | 1379 | PROFILE_4 | PROFILE_6) }, |
1380 | {usb0_init, DEV_ON_BASEBOARD, PROFILE_ALL}, | 1380 | {usb0_init, DEV_ON_BASEBOARD, PROFILE_ALL}, |
1381 | {usb1_init, DEV_ON_BASEBOARD, PROFILE_ALL}, | 1381 | {usb1_init, DEV_ON_BASEBOARD, PROFILE_ALL}, |
1382 | {evm_nand_init, DEV_ON_DGHTR_BRD, | 1382 | {evm_nand_init, DEV_ON_DGHTR_BRD, |
1383 | (PROFILE_ALL & ~PROFILE_2 & ~PROFILE_3)}, | 1383 | (PROFILE_ALL & ~PROFILE_2 & ~PROFILE_3)}, |
1384 | {i2c1_init, DEV_ON_DGHTR_BRD, (PROFILE_ALL & ~PROFILE_2)}, | 1384 | {i2c1_init, DEV_ON_DGHTR_BRD, (PROFILE_ALL & ~PROFILE_2)}, |
1385 | {mcasp1_init, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_3 | PROFILE_7) }, | 1385 | {mcasp1_init, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_3 | PROFILE_7) }, |
1386 | {mmc1_init, DEV_ON_DGHTR_BRD, PROFILE_2}, | 1386 | {mmc1_init, DEV_ON_DGHTR_BRD, PROFILE_2}, |
1387 | {mmc2_wl12xx_init, DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 | | 1387 | {mmc2_wl12xx_init, DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 | |
1388 | PROFILE_5)}, | 1388 | PROFILE_5)}, |
1389 | {mmc0_init, DEV_ON_BASEBOARD, (PROFILE_ALL & ~PROFILE_5)}, | 1389 | {mmc0_init, DEV_ON_BASEBOARD, (PROFILE_ALL & ~PROFILE_5)}, |
1390 | {mmc0_no_cd_init, DEV_ON_BASEBOARD, PROFILE_5}, | 1390 | {mmc0_no_cd_init, DEV_ON_BASEBOARD, PROFILE_5}, |
1391 | {spi0_init, DEV_ON_DGHTR_BRD, PROFILE_2}, | 1391 | {spi0_init, DEV_ON_DGHTR_BRD, PROFILE_2}, |
1392 | {uart1_wl12xx_init, DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 | | 1392 | {uart1_wl12xx_init, DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 | |
1393 | PROFILE_5)}, | 1393 | PROFILE_5)}, |
1394 | {wl12xx_init, DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 | PROFILE_5)}, | 1394 | {wl12xx_init, DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 | PROFILE_5)}, |
1395 | {d_can_init, DEV_ON_DGHTR_BRD, PROFILE_1}, | 1395 | {d_can_init, DEV_ON_DGHTR_BRD, PROFILE_1}, |
1396 | #ifdef CONFIG_KEYBOARD_MATRIX | 1396 | #ifdef CONFIG_KEYBOARD_MATRIX |
1397 | {matrix_keypad_init, DEV_ON_DGHTR_BRD, PROFILE_0}, | 1397 | {matrix_keypad_init, DEV_ON_DGHTR_BRD, PROFILE_0}, |
1398 | #endif | 1398 | #endif |
1399 | #ifdef CONFIG_KEYBOARD_GPIO | 1399 | #ifdef CONFIG_KEYBOARD_GPIO |
1400 | {volume_keys_init, DEV_ON_DGHTR_BRD, PROFILE_0}, | 1400 | {volume_keys_init, DEV_ON_DGHTR_BRD, PROFILE_0}, |
1401 | #endif | 1401 | #endif |
1402 | {NULL, 0, 0}, | 1402 | {NULL, 0, 0}, |
1403 | }; | 1403 | }; |
1404 | 1404 | ||
1405 | /* Industrial Auto Motor Control EVM */ | 1405 | /* Industrial Auto Motor Control EVM */ |
1406 | static struct evm_dev_cfg ind_auto_mtrl_evm_dev_cfg[] = { | 1406 | static struct evm_dev_cfg ind_auto_mtrl_evm_dev_cfg[] = { |
1407 | {mii1_init, DEV_ON_DGHTR_BRD, PROFILE_ALL}, | 1407 | {mii1_init, DEV_ON_DGHTR_BRD, PROFILE_ALL}, |
1408 | {usb0_init, DEV_ON_BASEBOARD, PROFILE_ALL}, | 1408 | {usb0_init, DEV_ON_BASEBOARD, PROFILE_ALL}, |
1409 | {usb1_init, DEV_ON_BASEBOARD, PROFILE_ALL}, | 1409 | {usb1_init, DEV_ON_BASEBOARD, PROFILE_ALL}, |
1410 | {profibus_init, DEV_ON_DGHTR_BRD, PROFILE_ALL}, | 1410 | {profibus_init, DEV_ON_DGHTR_BRD, PROFILE_ALL}, |
1411 | {evm_nand_init, DEV_ON_DGHTR_BRD, PROFILE_ALL}, | 1411 | {evm_nand_init, DEV_ON_DGHTR_BRD, PROFILE_ALL}, |
1412 | {spi1_init, DEV_ON_DGHTR_BRD, PROFILE_ALL}, | 1412 | {spi1_init, DEV_ON_DGHTR_BRD, PROFILE_ALL}, |
1413 | {uart3_init, DEV_ON_DGHTR_BRD, PROFILE_ALL}, | 1413 | {uart3_init, DEV_ON_DGHTR_BRD, PROFILE_ALL}, |
1414 | {i2c1_init, DEV_ON_BASEBOARD, PROFILE_ALL}, | 1414 | {i2c1_init, DEV_ON_BASEBOARD, PROFILE_ALL}, |
1415 | {mmc0_no_cd_init, DEV_ON_BASEBOARD, PROFILE_ALL}, | 1415 | {mmc0_no_cd_init, DEV_ON_BASEBOARD, PROFILE_ALL}, |
1416 | {NULL, 0, 0}, | 1416 | {NULL, 0, 0}, |
1417 | }; | 1417 | }; |
1418 | 1418 | ||
1419 | /* IP-Phone EVM */ | 1419 | /* IP-Phone EVM */ |
1420 | static struct evm_dev_cfg ip_phn_evm_dev_cfg[] = { | 1420 | static struct evm_dev_cfg ip_phn_evm_dev_cfg[] = { |
1421 | {enable_ecap0, DEV_ON_DGHTR_BRD, PROFILE_NONE}, | 1421 | {enable_ecap0, DEV_ON_DGHTR_BRD, PROFILE_NONE}, |
1422 | {lcdc_init, DEV_ON_DGHTR_BRD, PROFILE_NONE}, | 1422 | {lcdc_init, DEV_ON_DGHTR_BRD, PROFILE_NONE}, |
1423 | {tsc_init, DEV_ON_DGHTR_BRD, PROFILE_NONE}, | 1423 | {tsc_init, DEV_ON_DGHTR_BRD, PROFILE_NONE}, |
1424 | {rgmii1_init, DEV_ON_BASEBOARD, PROFILE_NONE}, | 1424 | {rgmii1_init, DEV_ON_BASEBOARD, PROFILE_NONE}, |
1425 | {rgmii2_init, DEV_ON_DGHTR_BRD, PROFILE_NONE}, | 1425 | {rgmii2_init, DEV_ON_DGHTR_BRD, PROFILE_NONE}, |
1426 | {usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE}, | 1426 | {usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE}, |
1427 | {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE}, | 1427 | {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE}, |
1428 | {evm_nand_init, DEV_ON_DGHTR_BRD, PROFILE_NONE}, | 1428 | {evm_nand_init, DEV_ON_DGHTR_BRD, PROFILE_NONE}, |
1429 | {i2c1_init, DEV_ON_BASEBOARD, PROFILE_NONE}, | 1429 | {i2c1_init, DEV_ON_BASEBOARD, PROFILE_NONE}, |
1430 | {mcasp1_init, DEV_ON_DGHTR_BRD, PROFILE_NONE}, | 1430 | {mcasp1_init, DEV_ON_DGHTR_BRD, PROFILE_NONE}, |
1431 | {mmc0_init, DEV_ON_BASEBOARD, PROFILE_NONE}, | 1431 | {mmc0_init, DEV_ON_BASEBOARD, PROFILE_NONE}, |
1432 | {NULL, 0, 0}, | 1432 | {NULL, 0, 0}, |
1433 | }; | 1433 | }; |
1434 | 1434 | ||
1435 | /* Beaglebone < Rev A3 */ | 1435 | /* Beaglebone < Rev A3 */ |
1436 | static struct evm_dev_cfg beaglebone_old_dev_cfg[] = { | 1436 | static struct evm_dev_cfg beaglebone_old_dev_cfg[] = { |
1437 | {rmii1_init, DEV_ON_BASEBOARD, PROFILE_NONE}, | 1437 | {rmii1_init, DEV_ON_BASEBOARD, PROFILE_NONE}, |
1438 | {usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE}, | 1438 | {usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE}, |
1439 | {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE}, | 1439 | {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE}, |
1440 | {mmc0_init, DEV_ON_BASEBOARD, PROFILE_NONE}, | 1440 | {mmc0_init, DEV_ON_BASEBOARD, PROFILE_NONE}, |
1441 | {NULL, 0, 0}, | 1441 | {NULL, 0, 0}, |
1442 | }; | 1442 | }; |
1443 | 1443 | ||
1444 | /* Beaglebone Rev A3 and after */ | 1444 | /* Beaglebone Rev A3 and after */ |
1445 | static struct evm_dev_cfg beaglebone_dev_cfg[] = { | 1445 | static struct evm_dev_cfg beaglebone_dev_cfg[] = { |
1446 | {mii1_init, DEV_ON_BASEBOARD, PROFILE_NONE}, | 1446 | {mii1_init, DEV_ON_BASEBOARD, PROFILE_NONE}, |
1447 | {usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE}, | 1447 | {usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE}, |
1448 | {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE}, | 1448 | {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE}, |
1449 | {mmc0_init, DEV_ON_BASEBOARD, PROFILE_NONE}, | 1449 | {mmc0_init, DEV_ON_BASEBOARD, PROFILE_NONE}, |
1450 | {NULL, 0, 0}, | 1450 | {NULL, 0, 0}, |
1451 | }; | 1451 | }; |
1452 | 1452 | ||
1453 | static void setup_low_cost_evm(void) | 1453 | static void setup_low_cost_evm(void) |
1454 | { | 1454 | { |
1455 | pr_info("The board is a AM335x Low Cost EVM.\n"); | 1455 | pr_info("The board is a AM335x Low Cost EVM.\n"); |
1456 | 1456 | ||
1457 | _configure_device(LOW_COST_EVM, low_cost_evm_dev_cfg, PROFILE_NONE); | 1457 | _configure_device(LOW_COST_EVM, low_cost_evm_dev_cfg, PROFILE_NONE); |
1458 | } | 1458 | } |
1459 | 1459 | ||
1460 | static void setup_general_purpose_evm(void) | 1460 | static void setup_general_purpose_evm(void) |
1461 | { | 1461 | { |
1462 | u32 prof_sel = am335x_get_profile_selection(); | 1462 | u32 prof_sel = am335x_get_profile_selection(); |
1463 | pr_info("The board is general purpose EVM in profile %d\n", prof_sel); | 1463 | pr_info("The board is general purpose EVM in profile %d\n", prof_sel); |
1464 | 1464 | ||
1465 | if (!strncmp("1.1A", config.version, 4)) { | 1465 | if (!strncmp("1.1A", config.version, 4)) { |
1466 | gp_evm_revision = GP_EVM_REV_IS_1_1A; | 1466 | gp_evm_revision = GP_EVM_REV_IS_1_1A; |
1467 | } else if (!strncmp("1.0", config.version, 3)) { | 1467 | } else if (!strncmp("1.0", config.version, 3)) { |
1468 | gp_evm_revision = GP_EVM_REV_IS_1_0; | 1468 | gp_evm_revision = GP_EVM_REV_IS_1_0; |
1469 | } else { | 1469 | } else { |
1470 | pr_err("Found invalid GP EVM revision, falling back to Rev1.1A"); | 1470 | pr_err("Found invalid GP EVM revision, falling back to Rev1.1A"); |
1471 | gp_evm_revision = GP_EVM_REV_IS_1_1A; | 1471 | gp_evm_revision = GP_EVM_REV_IS_1_1A; |
1472 | } | 1472 | } |
1473 | 1473 | ||
1474 | if (gp_evm_revision == GP_EVM_REV_IS_1_0) | 1474 | if (gp_evm_revision == GP_EVM_REV_IS_1_0) |
1475 | gigabit_enable = 0; | 1475 | gigabit_enable = 0; |
1476 | else if (gp_evm_revision == GP_EVM_REV_IS_1_1A) | 1476 | else if (gp_evm_revision == GP_EVM_REV_IS_1_1A) |
1477 | gigabit_enable = 1; | 1477 | gigabit_enable = 1; |
1478 | 1478 | ||
1479 | _configure_device(GEN_PURP_EVM, gen_purp_evm_dev_cfg, (1L << prof_sel)); | 1479 | _configure_device(GEN_PURP_EVM, gen_purp_evm_dev_cfg, (1L << prof_sel)); |
1480 | } | 1480 | } |
1481 | 1481 | ||
1482 | static void setup_ind_auto_motor_ctrl_evm(void) | 1482 | static void setup_ind_auto_motor_ctrl_evm(void) |
1483 | { | 1483 | { |
1484 | u32 prof_sel = am335x_get_profile_selection(); | 1484 | u32 prof_sel = am335x_get_profile_selection(); |
1485 | 1485 | ||
1486 | pr_info("The board is an industrial automation EVM in profile %d\n", | 1486 | pr_info("The board is an industrial automation EVM in profile %d\n", |
1487 | prof_sel); | 1487 | prof_sel); |
1488 | 1488 | ||
1489 | /* Only Profile 0 is supported */ | 1489 | /* Only Profile 0 is supported */ |
1490 | if ((1L << prof_sel) != PROFILE_0) { | 1490 | if ((1L << prof_sel) != PROFILE_0) { |
1491 | pr_err("AM335X: Only Profile 0 is supported\n"); | 1491 | pr_err("AM335X: Only Profile 0 is supported\n"); |
1492 | pr_err("Assuming profile 0 & continuing\n"); | 1492 | pr_err("Assuming profile 0 & continuing\n"); |
1493 | prof_sel = PROFILE_0; | 1493 | prof_sel = PROFILE_0; |
1494 | } | 1494 | } |
1495 | 1495 | ||
1496 | _configure_device(IND_AUT_MTR_EVM, ind_auto_mtrl_evm_dev_cfg, | 1496 | _configure_device(IND_AUT_MTR_EVM, ind_auto_mtrl_evm_dev_cfg, |
1497 | PROFILE_0); | 1497 | PROFILE_0); |
1498 | 1498 | ||
1499 | /* Fillup global evmid */ | 1499 | /* Fillup global evmid */ |
1500 | am33xx_evmid_fillup(IND_AUT_MTR_EVM); | 1500 | am33xx_evmid_fillup(IND_AUT_MTR_EVM); |
1501 | 1501 | ||
1502 | /* Initialize TLK110 PHY registers for phy version 1.0 */ | 1502 | /* Initialize TLK110 PHY registers for phy version 1.0 */ |
1503 | am335x_tlk110_phy_init(); | 1503 | am335x_tlk110_phy_init(); |
1504 | 1504 | ||
1505 | 1505 | ||
1506 | } | 1506 | } |
1507 | 1507 | ||
1508 | static void setup_ip_phone_evm(void) | 1508 | static void setup_ip_phone_evm(void) |
1509 | { | 1509 | { |
1510 | pr_info("The board is an IP phone EVM\n"); | 1510 | pr_info("The board is an IP phone EVM\n"); |
1511 | 1511 | ||
1512 | _configure_device(IP_PHN_EVM, ip_phn_evm_dev_cfg, PROFILE_NONE); | 1512 | _configure_device(IP_PHN_EVM, ip_phn_evm_dev_cfg, PROFILE_NONE); |
1513 | } | 1513 | } |
1514 | 1514 | ||
1515 | /* BeagleBone < Rev A3 */ | 1515 | /* BeagleBone < Rev A3 */ |
1516 | static void setup_beaglebone_old(void) | 1516 | static void setup_beaglebone_old(void) |
1517 | { | 1517 | { |
1518 | pr_info("The board is a AM335x Beaglebone < Rev A3.\n"); | 1518 | pr_info("The board is a AM335x Beaglebone < Rev A3.\n"); |
1519 | 1519 | ||
1520 | /* Beagle Bone has Micro-SD slot which doesn't have Write Protect pin */ | 1520 | /* Beagle Bone has Micro-SD slot which doesn't have Write Protect pin */ |
1521 | am335x_mmc[0].gpio_wp = -EINVAL; | 1521 | am335x_mmc[0].gpio_wp = -EINVAL; |
1522 | 1522 | ||
1523 | _configure_device(LOW_COST_EVM, beaglebone_old_dev_cfg, PROFILE_NONE); | 1523 | _configure_device(LOW_COST_EVM, beaglebone_old_dev_cfg, PROFILE_NONE); |
1524 | 1524 | ||
1525 | phy_register_fixup_for_uid(BBB_PHY_ID, BBB_PHY_MASK, | 1525 | phy_register_fixup_for_uid(BBB_PHY_ID, BBB_PHY_MASK, |
1526 | beaglebone_phy_fixup); | 1526 | beaglebone_phy_fixup); |
1527 | } | 1527 | } |
1528 | 1528 | ||
1529 | /* BeagleBone after Rev A3 */ | 1529 | /* BeagleBone after Rev A3 */ |
1530 | static void setup_beaglebone(void) | 1530 | static void setup_beaglebone(void) |
1531 | { | 1531 | { |
1532 | pr_info("The board is a AM335x Beaglebone.\n"); | 1532 | pr_info("The board is a AM335x Beaglebone.\n"); |
1533 | 1533 | ||
1534 | /* Beagle Bone has Micro-SD slot which doesn't have Write Protect pin */ | 1534 | /* Beagle Bone has Micro-SD slot which doesn't have Write Protect pin */ |
1535 | am335x_mmc[0].gpio_wp = -EINVAL; | 1535 | am335x_mmc[0].gpio_wp = -EINVAL; |
1536 | 1536 | ||
1537 | _configure_device(LOW_COST_EVM, beaglebone_dev_cfg, PROFILE_NONE); | 1537 | _configure_device(LOW_COST_EVM, beaglebone_dev_cfg, PROFILE_NONE); |
1538 | } | 1538 | } |
1539 | 1539 | ||
1540 | 1540 | ||
1541 | static void am335x_setup_daughter_board(struct memory_accessor *m, void *c) | 1541 | static void am335x_setup_daughter_board(struct memory_accessor *m, void *c) |
1542 | { | 1542 | { |
1543 | u8 tmp; | 1543 | u8 tmp; |
1544 | int ret; | 1544 | int ret; |
1545 | 1545 | ||
1546 | /* | 1546 | /* |
1547 | * try reading a byte from the EEPROM to see if it is | 1547 | * try reading a byte from the EEPROM to see if it is |
1548 | * present. We could read a lot more, but that would | 1548 | * present. We could read a lot more, but that would |
1549 | * just slow the boot process and we have all the information | 1549 | * just slow the boot process and we have all the information |
1550 | * we need from the EEPROM on the base board anyway. | 1550 | * we need from the EEPROM on the base board anyway. |
1551 | */ | 1551 | */ |
1552 | ret = m->read(m, &tmp, 0, sizeof(u8)); | 1552 | ret = m->read(m, &tmp, 0, sizeof(u8)); |
1553 | if (ret == sizeof(u8)) { | 1553 | if (ret == sizeof(u8)) { |
1554 | pr_info("Detected a daughter card on AM335x EVM.."); | 1554 | pr_info("Detected a daughter card on AM335x EVM.."); |
1555 | daughter_brd_detected = true; | 1555 | daughter_brd_detected = true; |
1556 | } else { | 1556 | } else { |
1557 | pr_info("No daughter card found\n"); | 1557 | pr_info("No daughter card found\n"); |
1558 | daughter_brd_detected = false; | 1558 | daughter_brd_detected = false; |
1559 | } | 1559 | } |
1560 | } | 1560 | } |
1561 | 1561 | ||
1562 | static void am335x_evm_setup(struct memory_accessor *mem_acc, void *context) | 1562 | static void am335x_evm_setup(struct memory_accessor *mem_acc, void *context) |
1563 | { | 1563 | { |
1564 | int ret; | 1564 | int ret; |
1565 | char tmp[10]; | 1565 | char tmp[10]; |
1566 | 1566 | ||
1567 | /* 1st get the MAC address from EEPROM */ | 1567 | /* 1st get the MAC address from EEPROM */ |
1568 | ret = mem_acc->read(mem_acc, (char *)&am335x_mac_addr, | 1568 | ret = mem_acc->read(mem_acc, (char *)&am335x_mac_addr, |
1569 | EEPROM_MAC_ADDRESS_OFFSET, sizeof(am335x_mac_addr)); | 1569 | EEPROM_MAC_ADDRESS_OFFSET, sizeof(am335x_mac_addr)); |
1570 | 1570 | ||
1571 | if (ret != sizeof(am335x_mac_addr)) { | 1571 | if (ret != sizeof(am335x_mac_addr)) { |
1572 | pr_warning("AM335X: EVM Config read fail: %d\n", ret); | 1572 | pr_warning("AM335X: EVM Config read fail: %d\n", ret); |
1573 | return; | 1573 | return; |
1574 | } | 1574 | } |
1575 | 1575 | ||
1576 | /* Fillup global mac id */ | 1576 | /* Fillup global mac id */ |
1577 | am33xx_cpsw_macidfillup(&am335x_mac_addr[0][0], | 1577 | am33xx_cpsw_macidfillup(&am335x_mac_addr[0][0], |
1578 | &am335x_mac_addr[1][0]); | 1578 | &am335x_mac_addr[1][0]); |
1579 | 1579 | ||
1580 | /* get board specific data */ | 1580 | /* get board specific data */ |
1581 | ret = mem_acc->read(mem_acc, (char *)&config, 0, sizeof(config)); | 1581 | ret = mem_acc->read(mem_acc, (char *)&config, 0, sizeof(config)); |
1582 | if (ret != sizeof(config)) { | 1582 | if (ret != sizeof(config)) { |
1583 | pr_warning("AM335X EVM config read fail, read %d bytes\n", ret); | 1583 | pr_warning("AM335X EVM config read fail, read %d bytes\n", ret); |
1584 | return; | 1584 | return; |
1585 | } | 1585 | } |
1586 | 1586 | ||
1587 | if (config.header != AM335X_EEPROM_HEADER) { | 1587 | if (config.header != AM335X_EEPROM_HEADER) { |
1588 | pr_warning("AM335X: wrong header 0x%x, expected 0x%x\n", | 1588 | pr_warning("AM335X: wrong header 0x%x, expected 0x%x\n", |
1589 | config.header, AM335X_EEPROM_HEADER); | 1589 | config.header, AM335X_EEPROM_HEADER); |
1590 | goto out; | 1590 | goto out; |
1591 | } | 1591 | } |
1592 | 1592 | ||
1593 | if (strncmp("A335", config.name, 4)) { | 1593 | if (strncmp("A335", config.name, 4)) { |
1594 | pr_err("Board %s doesn't look like an AM335x board\n", | 1594 | pr_err("Board %s doesn't look like an AM335x board\n", |
1595 | config.name); | 1595 | config.name); |
1596 | goto out; | 1596 | goto out; |
1597 | } | 1597 | } |
1598 | 1598 | ||
1599 | snprintf(tmp, sizeof(config.name) + 1, "%s", config.name); | 1599 | snprintf(tmp, sizeof(config.name) + 1, "%s", config.name); |
1600 | pr_info("Board name: %s\n", tmp); | 1600 | pr_info("Board name: %s\n", tmp); |
1601 | snprintf(tmp, sizeof(config.version) + 1, "%s", config.version); | 1601 | snprintf(tmp, sizeof(config.version) + 1, "%s", config.version); |
1602 | pr_info("Board version: %s\n", tmp); | 1602 | pr_info("Board version: %s\n", tmp); |
1603 | 1603 | ||
1604 | if (!strncmp("A335BONE", config.name, 8)) { | 1604 | if (!strncmp("A335BONE", config.name, 8)) { |
1605 | daughter_brd_detected = false; | 1605 | daughter_brd_detected = false; |
1606 | if(!strncmp("00A1", config.version, 4) || | 1606 | if(!strncmp("00A1", config.version, 4) || |
1607 | !strncmp("00A2", config.version, 4)) | 1607 | !strncmp("00A2", config.version, 4)) |
1608 | setup_beaglebone_old(); | 1608 | setup_beaglebone_old(); |
1609 | else | 1609 | else |
1610 | setup_beaglebone(); | 1610 | setup_beaglebone(); |
1611 | } else { | 1611 | } else { |
1612 | /* only 6 characters of options string used for now */ | 1612 | /* only 6 characters of options string used for now */ |
1613 | snprintf(tmp, 7, "%s", config.opt); | 1613 | snprintf(tmp, 7, "%s", config.opt); |
1614 | pr_info("SKU: %s\n", tmp); | 1614 | pr_info("SKU: %s\n", tmp); |
1615 | 1615 | ||
1616 | if (!strncmp("SKU#00", config.opt, 6)) | 1616 | if (!strncmp("SKU#00", config.opt, 6)) |
1617 | setup_low_cost_evm(); | 1617 | setup_low_cost_evm(); |
1618 | else if (!strncmp("SKU#01", config.opt, 6)) | 1618 | else if (!strncmp("SKU#01", config.opt, 6)) |
1619 | setup_general_purpose_evm(); | 1619 | setup_general_purpose_evm(); |
1620 | else if (!strncmp("SKU#02", config.opt, 6)) | 1620 | else if (!strncmp("SKU#02", config.opt, 6)) |
1621 | setup_ind_auto_motor_ctrl_evm(); | 1621 | setup_ind_auto_motor_ctrl_evm(); |
1622 | else if (!strncmp("SKU#03", config.opt, 6)) | 1622 | else if (!strncmp("SKU#03", config.opt, 6)) |
1623 | setup_ip_phone_evm(); | 1623 | setup_ip_phone_evm(); |
1624 | else | 1624 | else |
1625 | goto out; | 1625 | goto out; |
1626 | } | 1626 | } |
1627 | /* Initialize cpsw after board detection is completed as board | 1627 | /* Initialize cpsw after board detection is completed as board |
1628 | * information is required for configuring phy address and hence | 1628 | * information is required for configuring phy address and hence |
1629 | * should be call only after board detection | 1629 | * should be call only after board detection |
1630 | */ | 1630 | */ |
1631 | am33xx_cpsw_init(gigabit_enable); | 1631 | am33xx_cpsw_init(gigabit_enable); |
1632 | 1632 | ||
1633 | return; | 1633 | return; |
1634 | out: | 1634 | out: |
1635 | /* | 1635 | /* |
1636 | * If the EEPROM hasn't been programed or an incorrect header | 1636 | * If the EEPROM hasn't been programed or an incorrect header |
1637 | * or board name are read, assume this is an old beaglebone board | 1637 | * or board name are read, assume this is an old beaglebone board |
1638 | * (< Rev A3) | 1638 | * (< Rev A3) |
1639 | */ | 1639 | */ |
1640 | pr_err("Could not detect any board, falling back to: " | 1640 | pr_err("Could not detect any board, falling back to: " |
1641 | "Beaglebone (< Rev A3) with no daughter card connected\n"); | 1641 | "Beaglebone (< Rev A3) with no daughter card connected\n"); |
1642 | daughter_brd_detected = false; | 1642 | daughter_brd_detected = false; |
1643 | setup_beaglebone_old(); | 1643 | setup_beaglebone_old(); |
1644 | 1644 | ||
1645 | /* Initialize cpsw after board detection is completed as board | 1645 | /* Initialize cpsw after board detection is completed as board |
1646 | * information is required for configuring phy address and hence | 1646 | * information is required for configuring phy address and hence |
1647 | * should be call only after board detection | 1647 | * should be call only after board detection |
1648 | */ | 1648 | */ |
1649 | 1649 | ||
1650 | am33xx_cpsw_init(gigabit_enable); | 1650 | am33xx_cpsw_init(gigabit_enable); |
1651 | } | 1651 | } |
1652 | 1652 | ||
1653 | static struct at24_platform_data am335x_daughter_board_eeprom_info = { | 1653 | static struct at24_platform_data am335x_daughter_board_eeprom_info = { |
1654 | .byte_len = (256*1024) / 8, | 1654 | .byte_len = (256*1024) / 8, |
1655 | .page_size = 64, | 1655 | .page_size = 64, |
1656 | .flags = AT24_FLAG_ADDR16, | 1656 | .flags = AT24_FLAG_ADDR16, |
1657 | .setup = am335x_setup_daughter_board, | 1657 | .setup = am335x_setup_daughter_board, |
1658 | .context = (void *)NULL, | 1658 | .context = (void *)NULL, |
1659 | }; | 1659 | }; |
1660 | 1660 | ||
1661 | static struct at24_platform_data am335x_baseboard_eeprom_info = { | 1661 | static struct at24_platform_data am335x_baseboard_eeprom_info = { |
1662 | .byte_len = (256*1024) / 8, | 1662 | .byte_len = (256*1024) / 8, |
1663 | .page_size = 64, | 1663 | .page_size = 64, |
1664 | .flags = AT24_FLAG_ADDR16, | 1664 | .flags = AT24_FLAG_ADDR16, |
1665 | .setup = am335x_evm_setup, | 1665 | .setup = am335x_evm_setup, |
1666 | .context = (void *)NULL, | 1666 | .context = (void *)NULL, |
1667 | }; | 1667 | }; |
1668 | 1668 | ||
1669 | static struct regulator_init_data am335x_dummy; | 1669 | static struct regulator_init_data am335x_dummy; |
1670 | 1670 | ||
1671 | static struct regulator_consumer_supply am335x_vdd1_supply[] = { | 1671 | static struct regulator_consumer_supply am335x_vdd1_supply[] = { |
1672 | REGULATOR_SUPPLY("mpu", "mpu.0"), | 1672 | REGULATOR_SUPPLY("mpu", "mpu.0"), |
1673 | }; | 1673 | }; |
1674 | 1674 | ||
1675 | static struct regulator_init_data am335x_vdd1 = { | 1675 | static struct regulator_init_data am335x_vdd1 = { |
1676 | .constraints = { | 1676 | .constraints = { |
1677 | .min_uV = 600000, | 1677 | .min_uV = 600000, |
1678 | .max_uV = 1500000, | 1678 | .max_uV = 1500000, |
1679 | .valid_modes_mask = REGULATOR_MODE_NORMAL, | 1679 | .valid_modes_mask = REGULATOR_MODE_NORMAL, |
1680 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, | 1680 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, |
1681 | .always_on = 1, | 1681 | .always_on = 1, |
1682 | }, | 1682 | }, |
1683 | .num_consumer_supplies = ARRAY_SIZE(am335x_vdd1_supply), | 1683 | .num_consumer_supplies = ARRAY_SIZE(am335x_vdd1_supply), |
1684 | .consumer_supplies = am335x_vdd1_supply, | 1684 | .consumer_supplies = am335x_vdd1_supply, |
1685 | }; | 1685 | }; |
1686 | 1686 | ||
1687 | static struct tps65910_board am335x_tps65910_info = { | 1687 | static struct tps65910_board am335x_tps65910_info = { |
1688 | .tps65910_pmic_init_data[TPS65910_REG_VRTC] = &am335x_dummy, | 1688 | .tps65910_pmic_init_data[TPS65910_REG_VRTC] = &am335x_dummy, |
1689 | .tps65910_pmic_init_data[TPS65910_REG_VIO] = &am335x_dummy, | 1689 | .tps65910_pmic_init_data[TPS65910_REG_VIO] = &am335x_dummy, |
1690 | .tps65910_pmic_init_data[TPS65910_REG_VDD1] = &am335x_vdd1, | 1690 | .tps65910_pmic_init_data[TPS65910_REG_VDD1] = &am335x_vdd1, |
1691 | .tps65910_pmic_init_data[TPS65910_REG_VDD2] = &am335x_dummy, | 1691 | .tps65910_pmic_init_data[TPS65910_REG_VDD2] = &am335x_dummy, |
1692 | .tps65910_pmic_init_data[TPS65910_REG_VDD3] = &am335x_dummy, | 1692 | .tps65910_pmic_init_data[TPS65910_REG_VDD3] = &am335x_dummy, |
1693 | .tps65910_pmic_init_data[TPS65910_REG_VDIG1] = &am335x_dummy, | 1693 | .tps65910_pmic_init_data[TPS65910_REG_VDIG1] = &am335x_dummy, |
1694 | .tps65910_pmic_init_data[TPS65910_REG_VDIG2] = &am335x_dummy, | 1694 | .tps65910_pmic_init_data[TPS65910_REG_VDIG2] = &am335x_dummy, |
1695 | .tps65910_pmic_init_data[TPS65910_REG_VPLL] = &am335x_dummy, | 1695 | .tps65910_pmic_init_data[TPS65910_REG_VPLL] = &am335x_dummy, |
1696 | .tps65910_pmic_init_data[TPS65910_REG_VDAC] = &am335x_dummy, | 1696 | .tps65910_pmic_init_data[TPS65910_REG_VDAC] = &am335x_dummy, |
1697 | .tps65910_pmic_init_data[TPS65910_REG_VAUX1] = &am335x_dummy, | 1697 | .tps65910_pmic_init_data[TPS65910_REG_VAUX1] = &am335x_dummy, |
1698 | .tps65910_pmic_init_data[TPS65910_REG_VAUX2] = &am335x_dummy, | 1698 | .tps65910_pmic_init_data[TPS65910_REG_VAUX2] = &am335x_dummy, |
1699 | .tps65910_pmic_init_data[TPS65910_REG_VAUX33] = &am335x_dummy, | 1699 | .tps65910_pmic_init_data[TPS65910_REG_VAUX33] = &am335x_dummy, |
1700 | .tps65910_pmic_init_data[TPS65910_REG_VMMC] = &am335x_dummy, | 1700 | .tps65910_pmic_init_data[TPS65910_REG_VMMC] = &am335x_dummy, |
1701 | }; | 1701 | }; |
1702 | 1702 | ||
1703 | /* | 1703 | /* |
1704 | * Daughter board Detection. | 1704 | * Daughter board Detection. |
1705 | * Every board has a ID memory (EEPROM) on board. We probe these devices at | 1705 | * Every board has a ID memory (EEPROM) on board. We probe these devices at |
1706 | * machine init, starting from daughter board and ending with baseboard. | 1706 | * machine init, starting from daughter board and ending with baseboard. |
1707 | * Assumptions : | 1707 | * Assumptions : |
1708 | * 1. probe for i2c devices are called in the order they are included in | 1708 | * 1. probe for i2c devices are called in the order they are included in |
1709 | * the below struct. Daughter boards eeprom are probed 1st. Baseboard | 1709 | * the below struct. Daughter boards eeprom are probed 1st. Baseboard |
1710 | * eeprom probe is called last. | 1710 | * eeprom probe is called last. |
1711 | */ | 1711 | */ |
1712 | static struct i2c_board_info __initdata am335x_i2c_boardinfo[] = { | 1712 | static struct i2c_board_info __initdata am335x_i2c_boardinfo[] = { |
1713 | { | 1713 | { |
1714 | /* Daughter Board EEPROM */ | 1714 | /* Daughter Board EEPROM */ |
1715 | I2C_BOARD_INFO("24c256", DAUG_BOARD_I2C_ADDR), | 1715 | I2C_BOARD_INFO("24c256", DAUG_BOARD_I2C_ADDR), |
1716 | .platform_data = &am335x_daughter_board_eeprom_info, | 1716 | .platform_data = &am335x_daughter_board_eeprom_info, |
1717 | }, | 1717 | }, |
1718 | { | 1718 | { |
1719 | /* Baseboard board EEPROM */ | 1719 | /* Baseboard board EEPROM */ |
1720 | I2C_BOARD_INFO("24c256", BASEBOARD_I2C_ADDR), | 1720 | I2C_BOARD_INFO("24c256", BASEBOARD_I2C_ADDR), |
1721 | .platform_data = &am335x_baseboard_eeprom_info, | 1721 | .platform_data = &am335x_baseboard_eeprom_info, |
1722 | }, | 1722 | }, |
1723 | { | 1723 | { |
1724 | I2C_BOARD_INFO("cpld_reg", 0x35), | 1724 | I2C_BOARD_INFO("cpld_reg", 0x35), |
1725 | }, | 1725 | }, |
1726 | { | 1726 | { |
1727 | I2C_BOARD_INFO("tlc59108", 0x40), | 1727 | I2C_BOARD_INFO("tlc59108", 0x40), |
1728 | }, | 1728 | }, |
1729 | { | 1729 | { |
1730 | I2C_BOARD_INFO("tps65910", TPS65910_I2C_ID1), | 1730 | I2C_BOARD_INFO("tps65910", TPS65910_I2C_ID1), |
1731 | .platform_data = &am335x_tps65910_info, | 1731 | .platform_data = &am335x_tps65910_info, |
1732 | }, | 1732 | }, |
1733 | 1733 | ||
1734 | }; | 1734 | }; |
1735 | 1735 | ||
1736 | static struct omap_musb_board_data musb_board_data = { | 1736 | static struct omap_musb_board_data musb_board_data = { |
1737 | .interface_type = MUSB_INTERFACE_ULPI, | 1737 | .interface_type = MUSB_INTERFACE_ULPI, |
1738 | .mode = MUSB_OTG, | 1738 | .mode = MUSB_OTG, |
1739 | .power = 500, | 1739 | .power = 500, |
1740 | .instances = 1, | 1740 | .instances = 1, |
1741 | }; | 1741 | }; |
1742 | 1742 | ||
1743 | static int cpld_reg_probe(struct i2c_client *client, | 1743 | static int cpld_reg_probe(struct i2c_client *client, |
1744 | const struct i2c_device_id *id) | 1744 | const struct i2c_device_id *id) |
1745 | { | 1745 | { |
1746 | cpld_client = client; | 1746 | cpld_client = client; |
1747 | return 0; | 1747 | return 0; |
1748 | } | 1748 | } |
1749 | 1749 | ||
1750 | static int __devexit cpld_reg_remove(struct i2c_client *client) | 1750 | static int __devexit cpld_reg_remove(struct i2c_client *client) |
1751 | { | 1751 | { |
1752 | cpld_client = NULL; | 1752 | cpld_client = NULL; |
1753 | return 0; | 1753 | return 0; |
1754 | } | 1754 | } |
1755 | 1755 | ||
1756 | static const struct i2c_device_id cpld_reg_id[] = { | 1756 | static const struct i2c_device_id cpld_reg_id[] = { |
1757 | { "cpld_reg", 0 }, | 1757 | { "cpld_reg", 0 }, |
1758 | { } | 1758 | { } |
1759 | }; | 1759 | }; |
1760 | 1760 | ||
1761 | static struct i2c_driver cpld_reg_driver = { | 1761 | static struct i2c_driver cpld_reg_driver = { |
1762 | .driver = { | 1762 | .driver = { |
1763 | .name = "cpld_reg", | 1763 | .name = "cpld_reg", |
1764 | }, | 1764 | }, |
1765 | .probe = cpld_reg_probe, | 1765 | .probe = cpld_reg_probe, |
1766 | .remove = cpld_reg_remove, | 1766 | .remove = cpld_reg_remove, |
1767 | .id_table = cpld_reg_id, | 1767 | .id_table = cpld_reg_id, |
1768 | }; | 1768 | }; |
1769 | 1769 | ||
1770 | static void evm_init_cpld(void) | 1770 | static void evm_init_cpld(void) |
1771 | { | 1771 | { |
1772 | i2c_add_driver(&cpld_reg_driver); | 1772 | i2c_add_driver(&cpld_reg_driver); |
1773 | } | 1773 | } |
1774 | 1774 | ||
1775 | static void __init am335x_evm_i2c_init(void) | 1775 | static void __init am335x_evm_i2c_init(void) |
1776 | { | 1776 | { |
1777 | /* Initially assume Low Cost EVM Config */ | 1777 | /* Initially assume Low Cost EVM Config */ |
1778 | am335x_evm_id = LOW_COST_EVM; | 1778 | am335x_evm_id = LOW_COST_EVM; |
1779 | 1779 | ||
1780 | evm_init_cpld(); | 1780 | evm_init_cpld(); |
1781 | 1781 | ||
1782 | omap_register_i2c_bus(1, 100, am335x_i2c_boardinfo, | 1782 | omap_register_i2c_bus(1, 100, am335x_i2c_boardinfo, |
1783 | ARRAY_SIZE(am335x_i2c_boardinfo)); | 1783 | ARRAY_SIZE(am335x_i2c_boardinfo)); |
1784 | } | 1784 | } |
1785 | 1785 | ||
1786 | static struct resource am335x_rtc_resources[] = { | 1786 | static struct resource am335x_rtc_resources[] = { |
1787 | { | 1787 | { |
1788 | .start = AM33XX_RTC_BASE, | 1788 | .start = AM33XX_RTC_BASE, |
1789 | .end = AM33XX_RTC_BASE + SZ_4K - 1, | 1789 | .end = AM33XX_RTC_BASE + SZ_4K - 1, |
1790 | .flags = IORESOURCE_MEM, | 1790 | .flags = IORESOURCE_MEM, |
1791 | }, | 1791 | }, |
1792 | { /* timer irq */ | 1792 | { /* timer irq */ |
1793 | .start = AM33XX_IRQ_RTC_TIMER, | 1793 | .start = AM33XX_IRQ_RTC_TIMER, |
1794 | .end = AM33XX_IRQ_RTC_TIMER, | 1794 | .end = AM33XX_IRQ_RTC_TIMER, |
1795 | .flags = IORESOURCE_IRQ, | 1795 | .flags = IORESOURCE_IRQ, |
1796 | }, | 1796 | }, |
1797 | { /* alarm irq */ | 1797 | { /* alarm irq */ |
1798 | .start = AM33XX_IRQ_RTC_ALARM, | 1798 | .start = AM33XX_IRQ_RTC_ALARM, |
1799 | .end = AM33XX_IRQ_RTC_ALARM, | 1799 | .end = AM33XX_IRQ_RTC_ALARM, |
1800 | .flags = IORESOURCE_IRQ, | 1800 | .flags = IORESOURCE_IRQ, |
1801 | }, | 1801 | }, |
1802 | }; | 1802 | }; |
1803 | 1803 | ||
1804 | static struct platform_device am335x_rtc_device = { | 1804 | static struct platform_device am335x_rtc_device = { |
1805 | .name = "omap_rtc", | 1805 | .name = "omap_rtc", |
1806 | .id = -1, | 1806 | .id = -1, |
1807 | .num_resources = ARRAY_SIZE(am335x_rtc_resources), | 1807 | .num_resources = ARRAY_SIZE(am335x_rtc_resources), |
1808 | .resource = am335x_rtc_resources, | 1808 | .resource = am335x_rtc_resources, |
1809 | }; | 1809 | }; |
1810 | 1810 | ||
1811 | static int am335x_rtc_init(void) | 1811 | static int am335x_rtc_init(void) |
1812 | { | 1812 | { |
1813 | void __iomem *base; | 1813 | void __iomem *base; |
1814 | struct clk *clk; | 1814 | struct clk *clk; |
1815 | 1815 | ||
1816 | clk = clk_get(NULL, "rtc_fck"); | 1816 | clk = clk_get(NULL, "rtc_fck"); |
1817 | if (IS_ERR(clk)) { | 1817 | if (IS_ERR(clk)) { |
1818 | pr_err("rtc : Failed to get RTC clock\n"); | 1818 | pr_err("rtc : Failed to get RTC clock\n"); |
1819 | return -1; | 1819 | return -1; |
1820 | } | 1820 | } |
1821 | 1821 | ||
1822 | if (clk_enable(clk)) { | 1822 | if (clk_enable(clk)) { |
1823 | pr_err("rtc: Clock Enable Failed\n"); | 1823 | pr_err("rtc: Clock Enable Failed\n"); |
1824 | return -1; | 1824 | return -1; |
1825 | } | 1825 | } |
1826 | 1826 | ||
1827 | base = ioremap(AM33XX_RTC_BASE, SZ_4K); | 1827 | base = ioremap(AM33XX_RTC_BASE, SZ_4K); |
1828 | 1828 | ||
1829 | if (WARN_ON(!base)) | 1829 | if (WARN_ON(!base)) |
1830 | return -ENOMEM; | 1830 | return -ENOMEM; |
1831 | 1831 | ||
1832 | /* Unlock the rtc's registers */ | 1832 | /* Unlock the rtc's registers */ |
1833 | __raw_writel(0x83e70b13, base + 0x6c); | 1833 | __raw_writel(0x83e70b13, base + 0x6c); |
1834 | __raw_writel(0x95a4f1e0, base + 0x70); | 1834 | __raw_writel(0x95a4f1e0, base + 0x70); |
1835 | 1835 | ||
1836 | /* | 1836 | /* |
1837 | * Enable the 32K OSc | 1837 | * Enable the 32K OSc |
1838 | * TODO: Need a better way to handle this | 1838 | * TODO: Need a better way to handle this |
1839 | * Since we want the clock to be running before mmc init | 1839 | * Since we want the clock to be running before mmc init |
1840 | * we need to do it before the rtc probe happens | 1840 | * we need to do it before the rtc probe happens |
1841 | */ | 1841 | */ |
1842 | __raw_writel(0x48, base + 0x54); | 1842 | __raw_writel(0x48, base + 0x54); |
1843 | 1843 | ||
1844 | iounmap(base); | 1844 | iounmap(base); |
1845 | 1845 | ||
1846 | return platform_device_register(&am335x_rtc_device); | 1846 | return platform_device_register(&am335x_rtc_device); |
1847 | } | 1847 | } |
1848 | 1848 | ||
1849 | /* Enable clkout2 */ | 1849 | /* Enable clkout2 */ |
1850 | static struct pinmux_config clkout2_pin_mux[] = { | 1850 | static struct pinmux_config clkout2_pin_mux[] = { |
1851 | {"xdma_event_intr1.clkout2", OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT}, | 1851 | {"xdma_event_intr1.clkout2", OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT}, |
1852 | {NULL, 0}, | 1852 | {NULL, 0}, |
1853 | }; | 1853 | }; |
1854 | 1854 | ||
1855 | static void __init clkout2_enable(void) | 1855 | static void __init clkout2_enable(void) |
1856 | { | 1856 | { |
1857 | struct clk *ck_32; | 1857 | struct clk *ck_32; |
1858 | 1858 | ||
1859 | ck_32 = clk_get(NULL, "clkout2_ck"); | 1859 | ck_32 = clk_get(NULL, "clkout2_ck"); |
1860 | if (IS_ERR(ck_32)) { | 1860 | if (IS_ERR(ck_32)) { |
1861 | pr_err("Cannot clk_get ck_32\n"); | 1861 | pr_err("Cannot clk_get ck_32\n"); |
1862 | return; | 1862 | return; |
1863 | } | 1863 | } |
1864 | 1864 | ||
1865 | clk_enable(ck_32); | 1865 | clk_enable(ck_32); |
1866 | 1866 | ||
1867 | setup_pin_mux(clkout2_pin_mux); | 1867 | setup_pin_mux(clkout2_pin_mux); |
1868 | } | 1868 | } |
1869 | 1869 | ||
1870 | void __iomem * __init am33xx_get_mem_ctlr(void) | 1870 | void __iomem * __init am33xx_get_mem_ctlr(void) |
1871 | { | 1871 | { |
1872 | void __iomem *am33xx_emif_base; | 1872 | void __iomem *am33xx_emif_base; |
1873 | 1873 | ||
1874 | am33xx_emif_base = ioremap(AM33XX_EMIF0_BASE, SZ_32K); | 1874 | am33xx_emif_base = ioremap(AM33XX_EMIF0_BASE, SZ_32K); |
1875 | 1875 | ||
1876 | if (!am33xx_emif_base) | 1876 | if (!am33xx_emif_base) |
1877 | pr_warning("%s: Unable to map DDR2 controller", __func__); | 1877 | pr_warning("%s: Unable to map DDR2 controller", __func__); |
1878 | 1878 | ||
1879 | return am33xx_emif_base; | 1879 | return am33xx_emif_base; |
1880 | } | 1880 | } |
1881 | 1881 | ||
1882 | static struct resource am33xx_cpuidle_resources[] = { | 1882 | static struct resource am33xx_cpuidle_resources[] = { |
1883 | { | 1883 | { |
1884 | .start = AM33XX_EMIF0_BASE, | 1884 | .start = AM33XX_EMIF0_BASE, |
1885 | .end = AM33XX_EMIF0_BASE + SZ_32K - 1, | 1885 | .end = AM33XX_EMIF0_BASE + SZ_32K - 1, |
1886 | .flags = IORESOURCE_MEM, | 1886 | .flags = IORESOURCE_MEM, |
1887 | }, | 1887 | }, |
1888 | }; | 1888 | }; |
1889 | 1889 | ||
1890 | /* AM33XX devices support DDR2 power down */ | 1890 | /* AM33XX devices support DDR2 power down */ |
1891 | static struct am33xx_cpuidle_config am33xx_cpuidle_pdata = { | 1891 | static struct am33xx_cpuidle_config am33xx_cpuidle_pdata = { |
1892 | .ddr2_pdown = 1, | 1892 | .ddr2_pdown = 1, |
1893 | }; | 1893 | }; |
1894 | 1894 | ||
1895 | static struct platform_device am33xx_cpuidle_device = { | 1895 | static struct platform_device am33xx_cpuidle_device = { |
1896 | .name = "cpuidle-am33xx", | 1896 | .name = "cpuidle-am33xx", |
1897 | .num_resources = ARRAY_SIZE(am33xx_cpuidle_resources), | 1897 | .num_resources = ARRAY_SIZE(am33xx_cpuidle_resources), |
1898 | .resource = am33xx_cpuidle_resources, | 1898 | .resource = am33xx_cpuidle_resources, |
1899 | .dev = { | 1899 | .dev = { |
1900 | .platform_data = &am33xx_cpuidle_pdata, | 1900 | .platform_data = &am33xx_cpuidle_pdata, |
1901 | }, | 1901 | }, |
1902 | }; | 1902 | }; |
1903 | 1903 | ||
1904 | static void __init am33xx_cpuidle_init(void) | 1904 | static void __init am33xx_cpuidle_init(void) |
1905 | { | 1905 | { |
1906 | int ret; | 1906 | int ret; |
1907 | 1907 | ||
1908 | am33xx_cpuidle_pdata.emif_base = am33xx_get_mem_ctlr(); | 1908 | am33xx_cpuidle_pdata.emif_base = am33xx_get_mem_ctlr(); |
1909 | 1909 | ||
1910 | ret = platform_device_register(&am33xx_cpuidle_device); | 1910 | ret = platform_device_register(&am33xx_cpuidle_device); |
1911 | 1911 | ||
1912 | if (ret) | 1912 | if (ret) |
1913 | pr_warning("AM33XX cpuidle registration failed\n"); | 1913 | pr_warning("AM33XX cpuidle registration failed\n"); |
1914 | 1914 | ||
1915 | } | 1915 | } |
1916 | 1916 | ||
1917 | static void __init am335x_evm_init(void) | 1917 | static void __init am335x_evm_init(void) |
1918 | { | 1918 | { |
1919 | am33xx_cpuidle_init(); | 1919 | am33xx_cpuidle_init(); |
1920 | am33xx_mux_init(board_mux); | 1920 | am33xx_mux_init(board_mux); |
1921 | omap_serial_init(); | 1921 | omap_serial_init(); |
1922 | am335x_rtc_init(); | 1922 | am335x_rtc_init(); |
1923 | clkout2_enable(); | 1923 | clkout2_enable(); |
1924 | am335x_evm_i2c_init(); | 1924 | am335x_evm_i2c_init(); |
1925 | omap_sdrc_init(NULL, NULL); | 1925 | omap_sdrc_init(NULL, NULL); |
1926 | usb_musb_init(&musb_board_data); | 1926 | usb_musb_init(&musb_board_data); |
1927 | omap_board_config = am335x_evm_config; | 1927 | omap_board_config = am335x_evm_config; |
1928 | omap_board_config_size = ARRAY_SIZE(am335x_evm_config); | 1928 | omap_board_config_size = ARRAY_SIZE(am335x_evm_config); |
1929 | /* Create an alias for icss clock */ | 1929 | /* Create an alias for icss clock */ |
1930 | if (clk_add_alias("pruss", NULL, "icss_uart_gclk", NULL)) | 1930 | if (clk_add_alias("pruss", NULL, "icss_uart_gclk", NULL)) |
1931 | pr_err("failed to create an alias: icss_uart_gclk --> pruss\n"); | 1931 | pr_err("failed to create an alias: icss_uart_gclk --> pruss\n"); |
1932 | /* Create an alias for gfx/sgx clock */ | 1932 | /* Create an alias for gfx/sgx clock */ |
1933 | if (clk_add_alias("sgx_ck", NULL, "gfx_fclk", NULL)) | 1933 | if (clk_add_alias("sgx_ck", NULL, "gfx_fclk", NULL)) |
1934 | pr_err("failed to create an alias: gfx_fclk --> sgx_ck\n"); | 1934 | pr_err("failed to create an alias: gfx_fclk --> sgx_ck\n"); |
1935 | } | 1935 | } |
1936 | 1936 | ||
1937 | static void __init am335x_evm_map_io(void) | 1937 | static void __init am335x_evm_map_io(void) |
1938 | { | 1938 | { |
1939 | omap2_set_globals_am33xx(); | 1939 | omap2_set_globals_am33xx(); |
1940 | omapam33xx_map_common_io(); | 1940 | omapam33xx_map_common_io(); |
1941 | } | 1941 | } |
1942 | 1942 | ||
1943 | MACHINE_START(AM335XEVM, "am335xevm") | 1943 | MACHINE_START(AM335XEVM, "am335xevm") |
1944 | /* Maintainer: Texas Instruments */ | 1944 | /* Maintainer: Texas Instruments */ |
1945 | .atag_offset = 0x100, | 1945 | .atag_offset = 0x100, |
1946 | .map_io = am335x_evm_map_io, | 1946 | .map_io = am335x_evm_map_io, |
1947 | .init_irq = ti816x_init_irq, | 1947 | .init_irq = ti816x_init_irq, |
1948 | .init_early = am335x_init_early, | 1948 | .init_early = am335x_init_early, |
1949 | .timer = &omap3_am33xx_timer, | 1949 | .timer = &omap3_am33xx_timer, |
1950 | .init_machine = am335x_evm_init, | 1950 | .init_machine = am335x_evm_init, |
1951 | MACHINE_END | 1951 | MACHINE_END |
1952 | 1952 | ||
1953 | MACHINE_START(AM335XIAEVM, "am335xiaevm") | 1953 | MACHINE_START(AM335XIAEVM, "am335xiaevm") |
1954 | /* Maintainer: Texas Instruments */ | 1954 | /* Maintainer: Texas Instruments */ |
1955 | .atag_offset = 0x100, | 1955 | .atag_offset = 0x100, |
1956 | .map_io = am335x_evm_map_io, | 1956 | .map_io = am335x_evm_map_io, |
1957 | .init_irq = ti816x_init_irq, | 1957 | .init_irq = ti816x_init_irq, |
1958 | .init_early = am335x_init_early, | 1958 | .init_early = am335x_init_early, |
1959 | .timer = &omap3_am33xx_timer, | 1959 | .timer = &omap3_am33xx_timer, |
1960 | .init_machine = am335x_evm_init, | 1960 | .init_machine = am335x_evm_init, |
1961 | MACHINE_END | 1961 | MACHINE_END |
1962 | 1962 |