Eric Lee / linux-smarc-t335x-v3.2

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Commit af4ec5a39fb6762f33bdaf7b1b9975bbd5bc2108

Authored by Vaibhav Bedia
Committed by Afzal Mohammed
1 parent 7b4dfa0454
Exists in master

OMAP: clock: am33xx specific API handling 

Jitter correction for AM33XX is not present.
Handle revelant clock API's properly.

Signed-off-by: Afzal Mohammed <afzal@ti.com>

Showing 1 changed file with 6 additions and 5 deletions Inline Diff

arch/arm/mach-omap2/dpll3xxx.c
Diff comments   View file @ af4ec5a
1 /* 1 /*
2 * OMAP3/4 - specific DPLL control functions 2 * OMAP3/4 - specific DPLL control functions
3 * 3 *
4 * Copyright (C) 2009-2010 Texas Instruments, Inc. 4 * Copyright (C) 2009-2010 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation 5 * Copyright (C) 2009-2010 Nokia Corporation
6 * 6 *
7 * Written by Paul Walmsley 7 * Written by Paul Walmsley
8 * Testing and integration fixes by Jouni Högander 8 * Testing and integration fixes by Jouni Högander
9 * 9 *
10 * 36xx support added by Vishwanath BS, Richard Woodruff, and Nishanth 10 * 36xx support added by Vishwanath BS, Richard Woodruff, and Nishanth
11 * Menon 11 * Menon
12 * 12 *
13 * Parts of this code are based on code written by 13 * Parts of this code are based on code written by
14 * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu 14 * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
15 * 15 *
16 * This program is free software; you can redistribute it and/or modify 16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as 17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation. 18 * published by the Free Software Foundation.
19 */ 19 */
20 20
21 #include <linux/kernel.h> 21 #include <linux/kernel.h>
22 #include <linux/device.h> 22 #include <linux/device.h>
23 #include <linux/list.h> 23 #include <linux/list.h>
24 #include <linux/errno.h> 24 #include <linux/errno.h>
25 #include <linux/delay.h> 25 #include <linux/delay.h>
26 #include <linux/clk.h> 26 #include <linux/clk.h>
27 #include <linux/io.h> 27 #include <linux/io.h>
28 #include <linux/bitops.h> 28 #include <linux/bitops.h>
29 #include <linux/clkdev.h> 29 #include <linux/clkdev.h>
30 30
31 #include <plat/cpu.h> 31 #include <plat/cpu.h>
32 #include <plat/clock.h> 32 #include <plat/clock.h>
33 33
34 #include "clock.h" 34 #include "clock.h"
35 #include "cm2xxx_3xxx.h" 35 #include "cm2xxx_3xxx.h"
36 #include "cm-regbits-34xx.h" 36 #include "cm-regbits-34xx.h"
37 37
38 /* CM_AUTOIDLE_PLL*.AUTO_* bit values */ 38 /* CM_AUTOIDLE_PLL*.AUTO_* bit values */
39 #define DPLL_AUTOIDLE_DISABLE 0x0 39 #define DPLL_AUTOIDLE_DISABLE 0x0
40 #define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1 40 #define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1
41 41
42 #define MAX_DPLL_WAIT_TRIES 1000000 42 #define MAX_DPLL_WAIT_TRIES 1000000
43 43
44 /* Private functions */ 44 /* Private functions */
45 45
46 /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */ 46 /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
47 static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits) 47 static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits)
48 { 48 {
49 const struct dpll_data *dd; 49 const struct dpll_data *dd;
50 u32 v; 50 u32 v;
51 51
52 dd = clk->dpll_data; 52 dd = clk->dpll_data;
53 53
54 v = __raw_readl(dd->control_reg); 54 v = __raw_readl(dd->control_reg);
55 v &= ~dd->enable_mask; 55 v &= ~dd->enable_mask;
56 v |= clken_bits << __ffs(dd->enable_mask); 56 v |= clken_bits << __ffs(dd->enable_mask);
57 __raw_writel(v, dd->control_reg); 57 __raw_writel(v, dd->control_reg);
58 } 58 }
59 59
60 /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */ 60 /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
61 static int _omap3_wait_dpll_status(struct clk *clk, u8 state) 61 static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
62 { 62 {
63 const struct dpll_data *dd; 63 const struct dpll_data *dd;
64 int i = 0; 64 int i = 0;
65 int ret = -EINVAL; 65 int ret = -EINVAL;
66 66
67 dd = clk->dpll_data; 67 dd = clk->dpll_data;
68 68
69 state <<= __ffs(dd->idlest_mask); 69 state <<= __ffs(dd->idlest_mask);
70 70
71 while (((__raw_readl(dd->idlest_reg) & dd->idlest_mask) != state) && 71 while (((__raw_readl(dd->idlest_reg) & dd->idlest_mask) != state) &&
72 i < MAX_DPLL_WAIT_TRIES) { 72 i < MAX_DPLL_WAIT_TRIES) {
73 i++; 73 i++;
74 udelay(1); 74 udelay(1);
75 } 75 }
76 76
77 if (i == MAX_DPLL_WAIT_TRIES) { 77 if (i == MAX_DPLL_WAIT_TRIES) {
78 printk(KERN_ERR "clock: %s failed transition to '%s'\n", 78 printk(KERN_ERR "clock: %s failed transition to '%s'\n",
79 clk->name, (state) ? "locked" : "bypassed"); 79 clk->name, (state) ? "locked" : "bypassed");
80 } else { 80 } else {
81 pr_debug("clock: %s transition to '%s' in %d loops\n", 81 pr_debug("clock: %s transition to '%s' in %d loops\n",
82 clk->name, (state) ? "locked" : "bypassed", i); 82 clk->name, (state) ? "locked" : "bypassed", i);
83 83
84 ret = 0; 84 ret = 0;
85 } 85 }
86 86
87 return ret; 87 return ret;
88 } 88 }
89 89
90 /* From 3430 TRM ES2 4.7.6.2 */ 90 /* From 3430 TRM ES2 4.7.6.2 */
91 static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n) 91 static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n)
92 { 92 {
93 unsigned long fint; 93 unsigned long fint;
94 u16 f = 0; 94 u16 f = 0;
95 95
96 fint = clk->dpll_data->clk_ref->rate / n; 96 fint = clk->dpll_data->clk_ref->rate / n;
97 97
98 pr_debug("clock: fint is %lu\n", fint); 98 pr_debug("clock: fint is %lu\n", fint);
99 99
100 if (fint >= 750000 && fint <= 1000000) 100 if (fint >= 750000 && fint <= 1000000)
101 f = 0x3; 101 f = 0x3;
102 else if (fint > 1000000 && fint <= 1250000) 102 else if (fint > 1000000 && fint <= 1250000)
103 f = 0x4; 103 f = 0x4;
104 else if (fint > 1250000 && fint <= 1500000) 104 else if (fint > 1250000 && fint <= 1500000)
105 f = 0x5; 105 f = 0x5;
106 else if (fint > 1500000 && fint <= 1750000) 106 else if (fint > 1500000 && fint <= 1750000)
107 f = 0x6; 107 f = 0x6;
108 else if (fint > 1750000 && fint <= 2100000) 108 else if (fint > 1750000 && fint <= 2100000)
109 f = 0x7; 109 f = 0x7;
110 else if (fint > 7500000 && fint <= 10000000) 110 else if (fint > 7500000 && fint <= 10000000)
111 f = 0xB; 111 f = 0xB;
112 else if (fint > 10000000 && fint <= 12500000) 112 else if (fint > 10000000 && fint <= 12500000)
113 f = 0xC; 113 f = 0xC;
114 else if (fint > 12500000 && fint <= 15000000) 114 else if (fint > 12500000 && fint <= 15000000)
115 f = 0xD; 115 f = 0xD;
116 else if (fint > 15000000 && fint <= 17500000) 116 else if (fint > 15000000 && fint <= 17500000)
117 f = 0xE; 117 f = 0xE;
118 else if (fint > 17500000 && fint <= 21000000) 118 else if (fint > 17500000 && fint <= 21000000)
119 f = 0xF; 119 f = 0xF;
120 else 120 else
121 pr_debug("clock: unknown freqsel setting for %d\n", n); 121 pr_debug("clock: unknown freqsel setting for %d\n", n);
122 122
123 return f; 123 return f;
124 } 124 }
125 125
126 /* 126 /*
127 * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness 127 * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
128 * @clk: pointer to a DPLL struct clk 128 * @clk: pointer to a DPLL struct clk
129 * 129 *
130 * Instructs a non-CORE DPLL to lock. Waits for the DPLL to report 130 * Instructs a non-CORE DPLL to lock. Waits for the DPLL to report
131 * readiness before returning. Will save and restore the DPLL's 131 * readiness before returning. Will save and restore the DPLL's
132 * autoidle state across the enable, per the CDP code. If the DPLL 132 * autoidle state across the enable, per the CDP code. If the DPLL
133 * locked successfully, return 0; if the DPLL did not lock in the time 133 * locked successfully, return 0; if the DPLL did not lock in the time
134 * allotted, or DPLL3 was passed in, return -EINVAL. 134 * allotted, or DPLL3 was passed in, return -EINVAL.
135 */ 135 */
136 static int _omap3_noncore_dpll_lock(struct clk *clk) 136 static int _omap3_noncore_dpll_lock(struct clk *clk)
137 { 137 {
138 u8 ai; 138 u8 ai;
139 int r; 139 int r;
140 140
141 pr_debug("clock: locking DPLL %s\n", clk->name); 141 pr_debug("clock: locking DPLL %s\n", clk->name);
142 142
143 ai = omap3_dpll_autoidle_read(clk); 143 ai = omap3_dpll_autoidle_read(clk);
144 144
145 omap3_dpll_deny_idle(clk); 145 omap3_dpll_deny_idle(clk);
146 146
147 _omap3_dpll_write_clken(clk, DPLL_LOCKED); 147 _omap3_dpll_write_clken(clk, DPLL_LOCKED);
148 148
149 r = _omap3_wait_dpll_status(clk, 1); 149 r = _omap3_wait_dpll_status(clk, 1);
150 150
151 if (ai) 151 if (ai)
152 omap3_dpll_allow_idle(clk); 152 omap3_dpll_allow_idle(clk);
153 153
154 return r; 154 return r;
155 } 155 }
156 156
157 /* 157 /*
158 * _omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness 158 * _omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness
159 * @clk: pointer to a DPLL struct clk 159 * @clk: pointer to a DPLL struct clk
160 * 160 *
161 * Instructs a non-CORE DPLL to enter low-power bypass mode. In 161 * Instructs a non-CORE DPLL to enter low-power bypass mode. In
162 * bypass mode, the DPLL's rate is set equal to its parent clock's 162 * bypass mode, the DPLL's rate is set equal to its parent clock's
163 * rate. Waits for the DPLL to report readiness before returning. 163 * rate. Waits for the DPLL to report readiness before returning.
164 * Will save and restore the DPLL's autoidle state across the enable, 164 * Will save and restore the DPLL's autoidle state across the enable,
165 * per the CDP code. If the DPLL entered bypass mode successfully, 165 * per the CDP code. If the DPLL entered bypass mode successfully,
166 * return 0; if the DPLL did not enter bypass in the time allotted, or 166 * return 0; if the DPLL did not enter bypass in the time allotted, or
167 * DPLL3 was passed in, or the DPLL does not support low-power bypass, 167 * DPLL3 was passed in, or the DPLL does not support low-power bypass,
168 * return -EINVAL. 168 * return -EINVAL.
169 */ 169 */
170 static int _omap3_noncore_dpll_bypass(struct clk *clk) 170 static int _omap3_noncore_dpll_bypass(struct clk *clk)
171 { 171 {
172 int r; 172 int r;
173 u8 ai; 173 u8 ai;
174 174
175 if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) 175 if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS)))
176 return -EINVAL; 176 return -EINVAL;
177 177
178 pr_debug("clock: configuring DPLL %s for low-power bypass\n", 178 pr_debug("clock: configuring DPLL %s for low-power bypass\n",
179 clk->name); 179 clk->name);
180 180
181 ai = omap3_dpll_autoidle_read(clk); 181 ai = omap3_dpll_autoidle_read(clk);
182 182
183 _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_BYPASS); 183 _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_BYPASS);
184 184
185 r = _omap3_wait_dpll_status(clk, 0); 185 r = _omap3_wait_dpll_status(clk, 0);
186 186
187 if (ai) 187 if (ai)
188 omap3_dpll_allow_idle(clk); 188 omap3_dpll_allow_idle(clk);
189 else 189 else
190 omap3_dpll_deny_idle(clk); 190 omap3_dpll_deny_idle(clk);
191 191
192 return r; 192 return r;
193 } 193 }
194 194
195 /* 195 /*
196 * _omap3_noncore_dpll_stop - instruct a DPLL to stop 196 * _omap3_noncore_dpll_stop - instruct a DPLL to stop
197 * @clk: pointer to a DPLL struct clk 197 * @clk: pointer to a DPLL struct clk
198 * 198 *
199 * Instructs a non-CORE DPLL to enter low-power stop. Will save and 199 * Instructs a non-CORE DPLL to enter low-power stop. Will save and
200 * restore the DPLL's autoidle state across the stop, per the CDP 200 * restore the DPLL's autoidle state across the stop, per the CDP
201 * code. If DPLL3 was passed in, or the DPLL does not support 201 * code. If DPLL3 was passed in, or the DPLL does not support
202 * low-power stop, return -EINVAL; otherwise, return 0. 202 * low-power stop, return -EINVAL; otherwise, return 0.
203 */ 203 */
204 static int _omap3_noncore_dpll_stop(struct clk *clk) 204 static int _omap3_noncore_dpll_stop(struct clk *clk)
205 { 205 {
206 u8 ai; 206 u8 ai;
207 207
208 if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP))) 208 if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP)))
209 return -EINVAL; 209 return -EINVAL;
210 210
211 pr_debug("clock: stopping DPLL %s\n", clk->name); 211 pr_debug("clock: stopping DPLL %s\n", clk->name);
212 212
213 ai = omap3_dpll_autoidle_read(clk); 213 ai = omap3_dpll_autoidle_read(clk);
214 214
215 _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_STOP); 215 _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_STOP);
216 216
217 if (ai) 217 if (ai)
218 omap3_dpll_allow_idle(clk); 218 omap3_dpll_allow_idle(clk);
219 else 219 else
220 omap3_dpll_deny_idle(clk); 220 omap3_dpll_deny_idle(clk);
221 221
222 return 0; 222 return 0;
223 } 223 }
224 224
225 /** 225 /**
226 * _lookup_dco - Lookup DCO used by j-type DPLL 226 * _lookup_dco - Lookup DCO used by j-type DPLL
227 * @clk: pointer to a DPLL struct clk 227 * @clk: pointer to a DPLL struct clk
228 * @dco: digital control oscillator selector 228 * @dco: digital control oscillator selector
229 * @m: DPLL multiplier to set 229 * @m: DPLL multiplier to set
230 * @n: DPLL divider to set 230 * @n: DPLL divider to set
231 * 231 *
232 * See 36xx TRM section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)" 232 * See 36xx TRM section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)"
233 * 233 *
234 * XXX This code is not needed for 3430/AM35xx; can it be optimized 234 * XXX This code is not needed for 3430/AM35xx; can it be optimized
235 * out in non-multi-OMAP builds for those chips? 235 * out in non-multi-OMAP builds for those chips?
236 */ 236 */
237 static void _lookup_dco(struct clk *clk, u8 *dco, u16 m, u8 n) 237 static void _lookup_dco(struct clk *clk, u8 *dco, u16 m, u8 n)
238 { 238 {
239 unsigned long fint, clkinp; /* watch out for overflow */ 239 unsigned long fint, clkinp; /* watch out for overflow */
240 240
241 clkinp = clk->parent->rate; 241 clkinp = clk->parent->rate;
242 fint = (clkinp / n) * m; 242 fint = (clkinp / n) * m;
243 243
244 if (fint < 1000000000) 244 if (fint < 1000000000)
245 *dco = 2; 245 *dco = 2;
246 else 246 else
247 *dco = 4; 247 *dco = 4;
248 } 248 }
249 249
250 /** 250 /**
251 * _lookup_sddiv - Calculate sigma delta divider for j-type DPLL 251 * _lookup_sddiv - Calculate sigma delta divider for j-type DPLL
252 * @clk: pointer to a DPLL struct clk 252 * @clk: pointer to a DPLL struct clk
253 * @sd_div: target sigma-delta divider 253 * @sd_div: target sigma-delta divider
254 * @m: DPLL multiplier to set 254 * @m: DPLL multiplier to set
255 * @n: DPLL divider to set 255 * @n: DPLL divider to set
256 * 256 *
257 * See 36xx TRM section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)" 257 * See 36xx TRM section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)"
258 * 258 *
259 * XXX This code is not needed for 3430/AM35xx; can it be optimized 259 * XXX This code is not needed for 3430/AM35xx; can it be optimized
260 * out in non-multi-OMAP builds for those chips? 260 * out in non-multi-OMAP builds for those chips?
261 */ 261 */
262 static void _lookup_sddiv(struct clk *clk, u8 *sd_div, u16 m, u8 n) 262 static void _lookup_sddiv(struct clk *clk, u8 *sd_div, u16 m, u8 n)
263 { 263 {
264 unsigned long clkinp, sd; /* watch out for overflow */ 264 unsigned long clkinp, sd; /* watch out for overflow */
265 int mod1, mod2; 265 int mod1, mod2;
266 266
267 clkinp = clk->parent->rate; 267 clkinp = clk->parent->rate;
268 268
269 /* 269 /*
270 * target sigma-delta to near 250MHz 270 * target sigma-delta to near 250MHz
271 * sd = ceil[(m/(n+1)) * (clkinp_MHz / 250)] 271 * sd = ceil[(m/(n+1)) * (clkinp_MHz / 250)]
272 */ 272 */
273 clkinp /= 100000; /* shift from MHz to 10*Hz for 38.4 and 19.2 */ 273 clkinp /= 100000; /* shift from MHz to 10*Hz for 38.4 and 19.2 */
274 mod1 = (clkinp * m) % (250 * n); 274 mod1 = (clkinp * m) % (250 * n);
275 sd = (clkinp * m) / (250 * n); 275 sd = (clkinp * m) / (250 * n);
276 mod2 = sd % 10; 276 mod2 = sd % 10;
277 sd /= 10; 277 sd /= 10;
278 278
279 if (mod1 || mod2) 279 if (mod1 || mod2)
280 sd++; 280 sd++;
281 *sd_div = sd; 281 *sd_div = sd;
282 } 282 }
283 283
284 /* 284 /*
285 * _omap3_noncore_dpll_program - set non-core DPLL M,N values directly 285 * _omap3_noncore_dpll_program - set non-core DPLL M,N values directly
286 * @clk: struct clk * of DPLL to set 286 * @clk: struct clk * of DPLL to set
287 * @m: DPLL multiplier to set 287 * @m: DPLL multiplier to set
288 * @n: DPLL divider to set 288 * @n: DPLL divider to set
289 * @freqsel: FREQSEL value to set 289 * @freqsel: FREQSEL value to set
290 * 290 *
291 * Program the DPLL with the supplied M, N values, and wait for the DPLL to 291 * Program the DPLL with the supplied M, N values, and wait for the DPLL to
292 * lock.. Returns -EINVAL upon error, or 0 upon success. 292 * lock.. Returns -EINVAL upon error, or 0 upon success.
293 */ 293 */
294 static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel) 294 static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
295 { 295 {
296 struct dpll_data *dd = clk->dpll_data; 296 struct dpll_data *dd = clk->dpll_data;
297 u8 dco, sd_div; 297 u8 dco, sd_div;
298 u32 v; 298 u32 v;
299 299
300 /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */ 300 /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
301 _omap3_noncore_dpll_bypass(clk); 301 _omap3_noncore_dpll_bypass(clk);
302 302
303 /* 303 /*
304 * Set jitter correction. No jitter correction for OMAP4 and 3630 304 * Set jitter correction. No jitter correction for OMAP4, 3630
305 * since freqsel field is no longer present 305 * and AM33XX since freqsel field is no longer present
306 */ 306 */
307 if (!cpu_is_omap44xx() && !cpu_is_omap3630()) { 307 if (!cpu_is_omap44xx() && !cpu_is_omap3630() && !cpu_is_am33xx()) {
308 v = __raw_readl(dd->control_reg); 308 v = __raw_readl(dd->control_reg);
309 v &= ~dd->freqsel_mask; 309 v &= ~dd->freqsel_mask;
310 v |= freqsel << __ffs(dd->freqsel_mask); 310 v |= freqsel << __ffs(dd->freqsel_mask);
311 __raw_writel(v, dd->control_reg); 311 __raw_writel(v, dd->control_reg);
312 } 312 }
313 313
314 /* Set DPLL multiplier, divider */ 314 /* Set DPLL multiplier, divider */
315 v = __raw_readl(dd->mult_div1_reg); 315 v = __raw_readl(dd->mult_div1_reg);
316 v &= ~(dd->mult_mask | dd->div1_mask); 316 v &= ~(dd->mult_mask | dd->div1_mask);
317 v |= m << __ffs(dd->mult_mask); 317 v |= m << __ffs(dd->mult_mask);
318 v |= (n - 1) << __ffs(dd->div1_mask); 318 v |= (n - 1) << __ffs(dd->div1_mask);
319 319
320 /* Configure dco and sd_div for dplls that have these fields */ 320 /* Configure dco and sd_div for dplls that have these fields */
321 if (dd->dco_mask) { 321 if (dd->dco_mask) {
322 _lookup_dco(clk, &dco, m, n); 322 _lookup_dco(clk, &dco, m, n);
323 v &= ~(dd->dco_mask); 323 v &= ~(dd->dco_mask);
324 v |= dco << __ffs(dd->dco_mask); 324 v |= dco << __ffs(dd->dco_mask);
325 } 325 }
326 if (dd->sddiv_mask) { 326 if (dd->sddiv_mask) {
327 _lookup_sddiv(clk, &sd_div, m, n); 327 _lookup_sddiv(clk, &sd_div, m, n);
328 v &= ~(dd->sddiv_mask); 328 v &= ~(dd->sddiv_mask);
329 v |= sd_div << __ffs(dd->sddiv_mask); 329 v |= sd_div << __ffs(dd->sddiv_mask);
330 } 330 }
331 331
332 __raw_writel(v, dd->mult_div1_reg); 332 __raw_writel(v, dd->mult_div1_reg);
333 333
334 /* We let the clock framework set the other output dividers later */ 334 /* We let the clock framework set the other output dividers later */
335 335
336 /* REVISIT: Set ramp-up delay? */ 336 /* REVISIT: Set ramp-up delay? */
337 337
338 _omap3_noncore_dpll_lock(clk); 338 _omap3_noncore_dpll_lock(clk);
339 339
340 return 0; 340 return 0;
341 } 341 }
342 342
343 /* Public functions */ 343 /* Public functions */
344 344
345 /** 345 /**
346 * omap3_dpll_recalc - recalculate DPLL rate 346 * omap3_dpll_recalc - recalculate DPLL rate
347 * @clk: DPLL struct clk 347 * @clk: DPLL struct clk
348 * 348 *
349 * Recalculate and propagate the DPLL rate. 349 * Recalculate and propagate the DPLL rate.
350 */ 350 */
351 unsigned long omap3_dpll_recalc(struct clk *clk) 351 unsigned long omap3_dpll_recalc(struct clk *clk)
352 { 352 {
353 return omap2_get_dpll_rate(clk); 353 return omap2_get_dpll_rate(clk);
354 } 354 }
355 355
356 /* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */ 356 /* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */
357 357
358 /** 358 /**
359 * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode 359 * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
360 * @clk: pointer to a DPLL struct clk 360 * @clk: pointer to a DPLL struct clk
361 * 361 *
362 * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock. 362 * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
363 * The choice of modes depends on the DPLL's programmed rate: if it is 363 * The choice of modes depends on the DPLL's programmed rate: if it is
364 * the same as the DPLL's parent clock, it will enter bypass; 364 * the same as the DPLL's parent clock, it will enter bypass;
365 * otherwise, it will enter lock. This code will wait for the DPLL to 365 * otherwise, it will enter lock. This code will wait for the DPLL to
366 * indicate readiness before returning, unless the DPLL takes too long 366 * indicate readiness before returning, unless the DPLL takes too long
367 * to enter the target state. Intended to be used as the struct clk's 367 * to enter the target state. Intended to be used as the struct clk's
368 * enable function. If DPLL3 was passed in, or the DPLL does not 368 * enable function. If DPLL3 was passed in, or the DPLL does not
369 * support low-power stop, or if the DPLL took too long to enter 369 * support low-power stop, or if the DPLL took too long to enter
370 * bypass or lock, return -EINVAL; otherwise, return 0. 370 * bypass or lock, return -EINVAL; otherwise, return 0.
371 */ 371 */
372 int omap3_noncore_dpll_enable(struct clk *clk) 372 int omap3_noncore_dpll_enable(struct clk *clk)
373 { 373 {
374 int r; 374 int r;
375 struct dpll_data *dd; 375 struct dpll_data *dd;
376 376
377 dd = clk->dpll_data; 377 dd = clk->dpll_data;
378 if (!dd) 378 if (!dd)
379 return -EINVAL; 379 return -EINVAL;
380 380
381 if (clk->rate == dd->clk_bypass->rate) { 381 if (clk->rate == dd->clk_bypass->rate) {
382 WARN_ON(clk->parent != dd->clk_bypass); 382 WARN_ON(clk->parent != dd->clk_bypass);
383 r = _omap3_noncore_dpll_bypass(clk); 383 r = _omap3_noncore_dpll_bypass(clk);
384 } else { 384 } else {
385 WARN_ON(clk->parent != dd->clk_ref); 385 WARN_ON(clk->parent != dd->clk_ref);
386 r = _omap3_noncore_dpll_lock(clk); 386 r = _omap3_noncore_dpll_lock(clk);
387 } 387 }
388 /* 388 /*
389 *FIXME: this is dubious - if clk->rate has changed, what about 389 *FIXME: this is dubious - if clk->rate has changed, what about
390 * propagating? 390 * propagating?
391 */ 391 */
392 if (!r) 392 if (!r)
393 clk->rate = omap2_get_dpll_rate(clk); 393 clk->rate = omap2_get_dpll_rate(clk);
394 394
395 return r; 395 return r;
396 } 396 }
397 397
398 /** 398 /**
399 * omap3_noncore_dpll_disable - instruct a DPLL to enter low-power stop 399 * omap3_noncore_dpll_disable - instruct a DPLL to enter low-power stop
400 * @clk: pointer to a DPLL struct clk 400 * @clk: pointer to a DPLL struct clk
401 * 401 *
402 * Instructs a non-CORE DPLL to enter low-power stop. This function is 402 * Instructs a non-CORE DPLL to enter low-power stop. This function is
403 * intended for use in struct clkops. No return value. 403 * intended for use in struct clkops. No return value.
404 */ 404 */
405 void omap3_noncore_dpll_disable(struct clk *clk) 405 void omap3_noncore_dpll_disable(struct clk *clk)
406 { 406 {
407 _omap3_noncore_dpll_stop(clk); 407 _omap3_noncore_dpll_stop(clk);
408 } 408 }
409 409
410 410
411 /* Non-CORE DPLL rate set code */ 411 /* Non-CORE DPLL rate set code */
412 412
413 /** 413 /**
414 * omap3_noncore_dpll_set_rate - set non-core DPLL rate 414 * omap3_noncore_dpll_set_rate - set non-core DPLL rate
415 * @clk: struct clk * of DPLL to set 415 * @clk: struct clk * of DPLL to set
416 * @rate: rounded target rate 416 * @rate: rounded target rate
417 * 417 *
418 * Set the DPLL CLKOUT to the target rate. If the DPLL can enter 418 * Set the DPLL CLKOUT to the target rate. If the DPLL can enter
419 * low-power bypass, and the target rate is the bypass source clock 419 * low-power bypass, and the target rate is the bypass source clock
420 * rate, then configure the DPLL for bypass. Otherwise, round the 420 * rate, then configure the DPLL for bypass. Otherwise, round the
421 * target rate if it hasn't been done already, then program and lock 421 * target rate if it hasn't been done already, then program and lock
422 * the DPLL. Returns -EINVAL upon error, or 0 upon success. 422 * the DPLL. Returns -EINVAL upon error, or 0 upon success.
423 */ 423 */
424 int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) 424 int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
425 { 425 {
426 struct clk *new_parent = NULL; 426 struct clk *new_parent = NULL;
427 u16 freqsel = 0; 427 u16 freqsel = 0;
428 struct dpll_data *dd; 428 struct dpll_data *dd;
429 int ret; 429 int ret;
430 430
431 if (!clk || !rate) 431 if (!clk || !rate)
432 return -EINVAL; 432 return -EINVAL;
433 433
434 dd = clk->dpll_data; 434 dd = clk->dpll_data;
435 if (!dd) 435 if (!dd)
436 return -EINVAL; 436 return -EINVAL;
437 437
438 if (rate == omap2_get_dpll_rate(clk)) 438 if (rate == omap2_get_dpll_rate(clk))
439 return 0; 439 return 0;
440 440
441 /* 441 /*
442 * Ensure both the bypass and ref clocks are enabled prior to 442 * Ensure both the bypass and ref clocks are enabled prior to
443 * doing anything; we need the bypass clock running to reprogram 443 * doing anything; we need the bypass clock running to reprogram
444 * the DPLL. 444 * the DPLL.
445 */ 445 */
446 omap2_clk_enable(dd->clk_bypass); 446 omap2_clk_enable(dd->clk_bypass);
447 omap2_clk_enable(dd->clk_ref); 447 omap2_clk_enable(dd->clk_ref);
448 448
449 if (dd->clk_bypass->rate == rate && 449 if (dd->clk_bypass->rate == rate &&
450 (clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) { 450 (clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
451 pr_debug("clock: %s: set rate: entering bypass.\n", clk->name); 451 pr_debug("clock: %s: set rate: entering bypass.\n", clk->name);
452 452
453 ret = _omap3_noncore_dpll_bypass(clk); 453 ret = _omap3_noncore_dpll_bypass(clk);
454 if (!ret) 454 if (!ret)
455 new_parent = dd->clk_bypass; 455 new_parent = dd->clk_bypass;
456 } else { 456 } else {
457 if (dd->last_rounded_rate != rate) 457 if (dd->last_rounded_rate != rate)
458 omap2_dpll_round_rate(clk, rate); 458 omap2_dpll_round_rate(clk, rate);
459 459
460 if (dd->last_rounded_rate == 0) 460 if (dd->last_rounded_rate == 0)
461 return -EINVAL; 461 return -EINVAL;
462 462
463 /* No freqsel on OMAP4 and OMAP3630 */ 463 /* No freqsel on OMAP4, OMAP3630 and AM33XX */
464 if (!cpu_is_omap44xx() && !cpu_is_omap3630()) { 464 if (!cpu_is_omap44xx() && !cpu_is_omap3630() &&
465 !cpu_is_am33xx()) {
465 freqsel = _omap3_dpll_compute_freqsel(clk, 466 freqsel = _omap3_dpll_compute_freqsel(clk,
466 dd->last_rounded_n); 467 dd->last_rounded_n);
467 if (!freqsel) 468 if (!freqsel)
468 WARN_ON(1); 469 WARN_ON(1);
469 } 470 }
470 471
471 pr_debug("clock: %s: set rate: locking rate to %lu.\n", 472 pr_debug("clock: %s: set rate: locking rate to %lu.\n",
472 clk->name, rate); 473 clk->name, rate);
473 474
474 ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m, 475 ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m,
475 dd->last_rounded_n, freqsel); 476 dd->last_rounded_n, freqsel);
476 if (!ret) 477 if (!ret)
477 new_parent = dd->clk_ref; 478 new_parent = dd->clk_ref;
478 } 479 }
479 if (!ret) { 480 if (!ret) {
480 /* 481 /*
481 * Switch the parent clock in the hierarchy, and make sure 482 * Switch the parent clock in the hierarchy, and make sure
482 * that the new parent's usecount is correct. Note: we 483 * that the new parent's usecount is correct. Note: we
483 * enable the new parent before disabling the old to avoid 484 * enable the new parent before disabling the old to avoid
484 * any unnecessary hardware disable->enable transitions. 485 * any unnecessary hardware disable->enable transitions.
485 */ 486 */
486 if (clk->usecount) { 487 if (clk->usecount) {
487 omap2_clk_enable(new_parent); 488 omap2_clk_enable(new_parent);
488 omap2_clk_disable(clk->parent); 489 omap2_clk_disable(clk->parent);
489 } 490 }
490 clk_reparent(clk, new_parent); 491 clk_reparent(clk, new_parent);
491 clk->rate = rate; 492 clk->rate = rate;
492 } 493 }
493 omap2_clk_disable(dd->clk_ref); 494 omap2_clk_disable(dd->clk_ref);
494 omap2_clk_disable(dd->clk_bypass); 495 omap2_clk_disable(dd->clk_bypass);
495 496
496 return 0; 497 return 0;
497 } 498 }
498 499
499 /* DPLL autoidle read/set code */ 500 /* DPLL autoidle read/set code */
500 501
501 /** 502 /**
502 * omap3_dpll_autoidle_read - read a DPLL's autoidle bits 503 * omap3_dpll_autoidle_read - read a DPLL's autoidle bits
503 * @clk: struct clk * of the DPLL to read 504 * @clk: struct clk * of the DPLL to read
504 * 505 *
505 * Return the DPLL's autoidle bits, shifted down to bit 0. Returns 506 * Return the DPLL's autoidle bits, shifted down to bit 0. Returns
506 * -EINVAL if passed a null pointer or if the struct clk does not 507 * -EINVAL if passed a null pointer or if the struct clk does not
507 * appear to refer to a DPLL. 508 * appear to refer to a DPLL.
508 */ 509 */
509 u32 omap3_dpll_autoidle_read(struct clk *clk) 510 u32 omap3_dpll_autoidle_read(struct clk *clk)
510 { 511 {
511 const struct dpll_data *dd; 512 const struct dpll_data *dd;
512 u32 v; 513 u32 v;
513 514
514 if (!clk || !clk->dpll_data) 515 if (!clk || !clk->dpll_data)
515 return -EINVAL; 516 return -EINVAL;
516 517
517 dd = clk->dpll_data; 518 dd = clk->dpll_data;
518 519
519 v = __raw_readl(dd->autoidle_reg); 520 v = __raw_readl(dd->autoidle_reg);
520 v &= dd->autoidle_mask; 521 v &= dd->autoidle_mask;
521 v >>= __ffs(dd->autoidle_mask); 522 v >>= __ffs(dd->autoidle_mask);
522 523
523 return v; 524 return v;
524 } 525 }
525 526
526 /** 527 /**
527 * omap3_dpll_allow_idle - enable DPLL autoidle bits 528 * omap3_dpll_allow_idle - enable DPLL autoidle bits
528 * @clk: struct clk * of the DPLL to operate on 529 * @clk: struct clk * of the DPLL to operate on
529 * 530 *
530 * Enable DPLL automatic idle control. This automatic idle mode 531 * Enable DPLL automatic idle control. This automatic idle mode
531 * switching takes effect only when the DPLL is locked, at least on 532 * switching takes effect only when the DPLL is locked, at least on
532 * OMAP3430. The DPLL will enter low-power stop when its downstream 533 * OMAP3430. The DPLL will enter low-power stop when its downstream
533 * clocks are gated. No return value. 534 * clocks are gated. No return value.
534 */ 535 */
535 void omap3_dpll_allow_idle(struct clk *clk) 536 void omap3_dpll_allow_idle(struct clk *clk)
536 { 537 {
537 const struct dpll_data *dd; 538 const struct dpll_data *dd;
538 u32 v; 539 u32 v;
539 540
540 if (!clk || !clk->dpll_data) 541 if (!clk || !clk->dpll_data)
541 return; 542 return;
542 543
543 dd = clk->dpll_data; 544 dd = clk->dpll_data;
544 545
545 /* 546 /*
546 * REVISIT: CORE DPLL can optionally enter low-power bypass 547 * REVISIT: CORE DPLL can optionally enter low-power bypass
547 * by writing 0x5 instead of 0x1. Add some mechanism to 548 * by writing 0x5 instead of 0x1. Add some mechanism to
548 * optionally enter this mode. 549 * optionally enter this mode.
549 */ 550 */
550 v = __raw_readl(dd->autoidle_reg); 551 v = __raw_readl(dd->autoidle_reg);
551 v &= ~dd->autoidle_mask; 552 v &= ~dd->autoidle_mask;
552 v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask); 553 v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
553 __raw_writel(v, dd->autoidle_reg); 554 __raw_writel(v, dd->autoidle_reg);
554 } 555 }
555 556
556 /** 557 /**
557 * omap3_dpll_deny_idle - prevent DPLL from automatically idling 558 * omap3_dpll_deny_idle - prevent DPLL from automatically idling
558 * @clk: struct clk * of the DPLL to operate on 559 * @clk: struct clk * of the DPLL to operate on
559 * 560 *
560 * Disable DPLL automatic idle control. No return value. 561 * Disable DPLL automatic idle control. No return value.
561 */ 562 */
562 void omap3_dpll_deny_idle(struct clk *clk) 563 void omap3_dpll_deny_idle(struct clk *clk)
563 { 564 {
564 const struct dpll_data *dd; 565 const struct dpll_data *dd;
565 u32 v; 566 u32 v;
566 567
567 if (!clk || !clk->dpll_data) 568 if (!clk || !clk->dpll_data)
568 return; 569 return;
569 570
570 dd = clk->dpll_data; 571 dd = clk->dpll_data;
571 572
572 v = __raw_readl(dd->autoidle_reg); 573 v = __raw_readl(dd->autoidle_reg);
573 v &= ~dd->autoidle_mask; 574 v &= ~dd->autoidle_mask;
574 v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask); 575 v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
575 __raw_writel(v, dd->autoidle_reg); 576 __raw_writel(v, dd->autoidle_reg);
576 577
577 } 578 }
578 579
579 /* Clock control for DPLL outputs */ 580 /* Clock control for DPLL outputs */
580 581
581 /** 582 /**
582 * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate 583 * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate
583 * @clk: DPLL output struct clk 584 * @clk: DPLL output struct clk
584 * 585 *
585 * Using parent clock DPLL data, look up DPLL state. If locked, set our 586 * Using parent clock DPLL data, look up DPLL state. If locked, set our
586 * rate to the dpll_clk * 2; otherwise, just use dpll_clk. 587 * rate to the dpll_clk * 2; otherwise, just use dpll_clk.
587 */ 588 */
588 unsigned long omap3_clkoutx2_recalc(struct clk *clk) 589 unsigned long omap3_clkoutx2_recalc(struct clk *clk)
589 { 590 {
590 const struct dpll_data *dd; 591 const struct dpll_data *dd;
591 unsigned long rate; 592 unsigned long rate;
592 u32 v; 593 u32 v;
593 struct clk *pclk; 594 struct clk *pclk;
594 595
595 /* Walk up the parents of clk, looking for a DPLL */ 596 /* Walk up the parents of clk, looking for a DPLL */
596 pclk = clk->parent; 597 pclk = clk->parent;
597 while (pclk && !pclk->dpll_data) 598 while (pclk && !pclk->dpll_data)
598 pclk = pclk->parent; 599 pclk = pclk->parent;
599 600
600 /* clk does not have a DPLL as a parent? */ 601 /* clk does not have a DPLL as a parent? */
601 WARN_ON(!pclk); 602 WARN_ON(!pclk);
602 603
603 dd = pclk->dpll_data; 604 dd = pclk->dpll_data;
604 605
605 WARN_ON(!dd->enable_mask); 606 WARN_ON(!dd->enable_mask);
606 607
607 v = __raw_readl(dd->control_reg) & dd->enable_mask; 608 v = __raw_readl(dd->control_reg) & dd->enable_mask;
608 v >>= __ffs(dd->enable_mask); 609 v >>= __ffs(dd->enable_mask);
609 if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE)) 610 if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE))
610 rate = clk->parent->rate; 611 rate = clk->parent->rate;
611 else 612 else
612 rate = clk->parent->rate * 2; 613 rate = clk->parent->rate * 2;
613 return rate; 614 return rate;
614 } 615 }
615 616