Eric Lee / linux-smarc-t335x-v3.2

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Commit c55c452a6881b2560e8490ee346a87eb9e092075

Authored by Goutam Kumar
Committed by Hebbar, Gururaja
1 parent 0088903287
Exists in master

arm:omap:am335x: fix incorrect #ifdef usage 

Remove incorrect #ifdef added from a prev commit.

while we are here, also move <linux/input.h> upwards before any input
or key related macros are used.

Signed-off-by: Goutam Kumar <goutam.kumar@ti.com>
Signed-off-by: Hebbar, Gururaja <gururaja.hebbar@ti.com>

Showing 1 changed file with 1 additions and 5 deletions Inline Diff

arch/arm/mach-omap2/board-am335xevm.c
Diff comments   View file @ c55c452
1 /* 1 /*
2 * Code for AM335X EVM. 2 * Code for AM335X EVM.
3 * 3 *
4 * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/ 4 * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
5 * 5 *
6 * This program is free software; you can redistribute it and/or 6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as 7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2. 8 * published by the Free Software Foundation version 2.
9 * 9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty 11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details. 13 * GNU General Public License for more details.
14 */ 14 */
15 #include <linux/kernel.h> 15 #include <linux/kernel.h>
16 #include <linux/init.h> 16 #include <linux/init.h>
17 #include <linux/i2c.h> 17 #include <linux/i2c.h>
18 #include <linux/i2c/at24.h> 18 #include <linux/i2c/at24.h>
19 #include <linux/phy.h> 19 #include <linux/phy.h>
20 #include <linux/gpio.h> 20 #include <linux/gpio.h>
21 #include <linux/spi/spi.h> 21 #include <linux/spi/spi.h>
22 #include <linux/spi/flash.h> 22 #include <linux/spi/flash.h>
23 #ifdef CONFIG_KEYBOARD_GPIO
24 #include <linux/gpio_keys.h>
25 #endif
26 #ifdef CONFIG_KEYBOARD_MATRIX
27 #include <linux/input.h> 23 #include <linux/input.h>
24 #include <linux/gpio_keys.h>
28 #include <linux/input/matrix_keypad.h> 25 #include <linux/input/matrix_keypad.h>
29 #endif
30 #include <linux/mtd/mtd.h> 26 #include <linux/mtd/mtd.h>
31 #include <linux/mtd/nand.h> 27 #include <linux/mtd/nand.h>
32 #include <linux/mtd/partitions.h> 28 #include <linux/mtd/partitions.h>
33 #include <linux/platform_device.h> 29 #include <linux/platform_device.h>
34 #include <linux/clk.h> 30 #include <linux/clk.h>
35 #include <linux/err.h> 31 #include <linux/err.h>
36 #include <linux/wl12xx.h> 32 #include <linux/wl12xx.h>
37 #include <linux/ethtool.h> 33 #include <linux/ethtool.h>
38 #include <linux/mfd/tps65910.h> 34 #include <linux/mfd/tps65910.h>
39 35
40 /* LCD controller is similar to DA850 */ 36 /* LCD controller is similar to DA850 */
41 #include <video/da8xx-fb.h> 37 #include <video/da8xx-fb.h>
42 38
43 #include <mach/hardware.h> 39 #include <mach/hardware.h>
44 #include <mach/board-am335xevm.h> 40 #include <mach/board-am335xevm.h>
45 41
46 #include <asm/mach-types.h> 42 #include <asm/mach-types.h>
47 #include <asm/mach/arch.h> 43 #include <asm/mach/arch.h>
48 #include <asm/mach/map.h> 44 #include <asm/mach/map.h>
49 #include <asm/hardware/asp.h> 45 #include <asm/hardware/asp.h>
50 46
51 #include <plat/irqs.h> 47 #include <plat/irqs.h>
52 #include <plat/board.h> 48 #include <plat/board.h>
53 #include <plat/common.h> 49 #include <plat/common.h>
54 #include <plat/lcdc.h> 50 #include <plat/lcdc.h>
55 #include <plat/usb.h> 51 #include <plat/usb.h>
56 #include <plat/mmc.h> 52 #include <plat/mmc.h>
57 53
58 #include "board-flash.h" 54 #include "board-flash.h"
59 #include "cpuidle33xx.h" 55 #include "cpuidle33xx.h"
60 #include "mux.h" 56 #include "mux.h"
61 #include "devices.h" 57 #include "devices.h"
62 #include "hsmmc.h" 58 #include "hsmmc.h"
63 59
64 /* TLK PHY IDs */ 60 /* TLK PHY IDs */
65 #define TLK110_PHY_ID 0x2000A201 61 #define TLK110_PHY_ID 0x2000A201
66 #define TLK110_PHY_MASK 0xfffffff0 62 #define TLK110_PHY_MASK 0xfffffff0
67 63
68 /* BBB PHY IDs */ 64 /* BBB PHY IDs */
69 #define BBB_PHY_ID 0x7c0f1 65 #define BBB_PHY_ID 0x7c0f1
70 #define BBB_PHY_MASK 0xfffffffe 66 #define BBB_PHY_MASK 0xfffffffe
71 67
72 /* TLK110 PHY register offsets */ 68 /* TLK110 PHY register offsets */
73 #define TLK110_COARSEGAIN_REG 0x00A3 69 #define TLK110_COARSEGAIN_REG 0x00A3
74 #define TLK110_LPFHPF_REG 0x00AC 70 #define TLK110_LPFHPF_REG 0x00AC
75 #define TLK110_SPAREANALOG_REG 0x00B9 71 #define TLK110_SPAREANALOG_REG 0x00B9
76 #define TLK110_VRCR_REG 0x00D0 72 #define TLK110_VRCR_REG 0x00D0
77 #define TLK110_SETFFE_REG 0x0107 73 #define TLK110_SETFFE_REG 0x0107
78 #define TLK110_FTSP_REG 0x0154 74 #define TLK110_FTSP_REG 0x0154
79 #define TLK110_ALFATPIDL_REG 0x002A 75 #define TLK110_ALFATPIDL_REG 0x002A
80 #define TLK110_PSCOEF21_REG 0x0096 76 #define TLK110_PSCOEF21_REG 0x0096
81 #define TLK110_PSCOEF3_REG 0x0097 77 #define TLK110_PSCOEF3_REG 0x0097
82 #define TLK110_ALFAFACTOR1_REG 0x002C 78 #define TLK110_ALFAFACTOR1_REG 0x002C
83 #define TLK110_ALFAFACTOR2_REG 0x0023 79 #define TLK110_ALFAFACTOR2_REG 0x0023
84 #define TLK110_CFGPS_REG 0x0095 80 #define TLK110_CFGPS_REG 0x0095
85 #define TLK110_FTSPTXGAIN_REG 0x0150 81 #define TLK110_FTSPTXGAIN_REG 0x0150
86 #define TLK110_SWSCR3_REG 0x000B 82 #define TLK110_SWSCR3_REG 0x000B
87 #define TLK110_SCFALLBACK_REG 0x0040 83 #define TLK110_SCFALLBACK_REG 0x0040
88 #define TLK110_PHYRCR_REG 0x001F 84 #define TLK110_PHYRCR_REG 0x001F
89 85
90 /* TLK110 register writes values */ 86 /* TLK110 register writes values */
91 #define TLK110_COARSEGAIN_VAL 0x0000 87 #define TLK110_COARSEGAIN_VAL 0x0000
92 #define TLK110_LPFHPF_VAL 0x8000 88 #define TLK110_LPFHPF_VAL 0x8000
93 #define TLK110_SPANALOG_VAL 0x0000 89 #define TLK110_SPANALOG_VAL 0x0000
94 #define TLK110_VRCR_VAL 0x0008 90 #define TLK110_VRCR_VAL 0x0008
95 #define TLK110_SETFFE_VAL 0x0605 91 #define TLK110_SETFFE_VAL 0x0605
96 #define TLK110_FTSP_VAL 0x0255 92 #define TLK110_FTSP_VAL 0x0255
97 #define TLK110_ALFATPIDL_VAL 0x7998 93 #define TLK110_ALFATPIDL_VAL 0x7998
98 #define TLK110_PSCOEF21_VAL 0x3A20 94 #define TLK110_PSCOEF21_VAL 0x3A20
99 #define TLK110_PSCOEF3_VAL 0x003F 95 #define TLK110_PSCOEF3_VAL 0x003F
100 #define TLK110_ALFACTOR1_VAL 0xFF80 96 #define TLK110_ALFACTOR1_VAL 0xFF80
101 #define TLK110_ALFACTOR2_VAL 0x021C 97 #define TLK110_ALFACTOR2_VAL 0x021C
102 #define TLK110_CFGPS_VAL 0x0000 98 #define TLK110_CFGPS_VAL 0x0000
103 #define TLK110_FTSPTXGAIN_VAL 0x6A88 99 #define TLK110_FTSPTXGAIN_VAL 0x6A88
104 #define TLK110_SWSCR3_VAL 0x0000 100 #define TLK110_SWSCR3_VAL 0x0000
105 #define TLK110_SCFALLBACK_VAL 0xC11D 101 #define TLK110_SCFALLBACK_VAL 0xC11D
106 #define TLK110_PHYRCR_VAL 0x4000 102 #define TLK110_PHYRCR_VAL 0x4000
107 103
108 #ifdef CONFIG_TLK110_WORKAROUND 104 #ifdef CONFIG_TLK110_WORKAROUND
109 #define am335x_tlk110_phy_init()\ 105 #define am335x_tlk110_phy_init()\
110 do { \ 106 do { \
111 phy_register_fixup_for_uid(TLK110_PHY_ID,\ 107 phy_register_fixup_for_uid(TLK110_PHY_ID,\
112 TLK110_PHY_MASK,\ 108 TLK110_PHY_MASK,\
113 am335x_tlk110_phy_fixup);\ 109 am335x_tlk110_phy_fixup);\
114 } while (0); 110 } while (0);
115 #else 111 #else
116 #define am335x_tlk110_phy_init() do { } while (0); 112 #define am335x_tlk110_phy_init() do { } while (0);
117 #endif 113 #endif
118 114
119 /* Convert GPIO signal to GPIO pin number */ 115 /* Convert GPIO signal to GPIO pin number */
120 #define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio)) 116 #define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
121 117
122 static const struct display_panel disp_panel = { 118 static const struct display_panel disp_panel = {
123 WVGA, 119 WVGA,
124 32, 120 32,
125 32, 121 32,
126 COLOR_ACTIVE, 122 COLOR_ACTIVE,
127 }; 123 };
128 124
129 static struct lcd_ctrl_config lcd_cfg = { 125 static struct lcd_ctrl_config lcd_cfg = {
130 &disp_panel, 126 &disp_panel,
131 .ac_bias = 255, 127 .ac_bias = 255,
132 .ac_bias_intrpt = 0, 128 .ac_bias_intrpt = 0,
133 .dma_burst_sz = 16, 129 .dma_burst_sz = 16,
134 .bpp = 32, 130 .bpp = 32,
135 .fdd = 0x80, 131 .fdd = 0x80,
136 .tft_alt_mode = 0, 132 .tft_alt_mode = 0,
137 .stn_565_mode = 0, 133 .stn_565_mode = 0,
138 .mono_8bit_mode = 0, 134 .mono_8bit_mode = 0,
139 .invert_line_clock = 1, 135 .invert_line_clock = 1,
140 .invert_frm_clock = 1, 136 .invert_frm_clock = 1,
141 .sync_edge = 0, 137 .sync_edge = 0,
142 .sync_ctrl = 1, 138 .sync_ctrl = 1,
143 .raster_order = 0, 139 .raster_order = 0,
144 }; 140 };
145 141
146 struct da8xx_lcdc_platform_data TFC_S9700RTWV35TR_01B_pdata = { 142 struct da8xx_lcdc_platform_data TFC_S9700RTWV35TR_01B_pdata = {
147 .manu_name = "ThreeFive", 143 .manu_name = "ThreeFive",
148 .controller_data = &lcd_cfg, 144 .controller_data = &lcd_cfg,
149 .type = "TFC_S9700RTWV35TR_01B", 145 .type = "TFC_S9700RTWV35TR_01B",
150 }; 146 };
151 147
152 /* TSc controller */ 148 /* TSc controller */
153 #include <linux/input/ti_tscadc.h> 149 #include <linux/input/ti_tscadc.h>
154 #include <linux/lis3lv02d.h> 150 #include <linux/lis3lv02d.h>
155 151
156 static struct resource tsc_resources[] = { 152 static struct resource tsc_resources[] = {
157 [0] = { 153 [0] = {
158 .start = AM33XX_TSC_BASE, 154 .start = AM33XX_TSC_BASE,
159 .end = AM33XX_TSC_BASE + SZ_8K - 1, 155 .end = AM33XX_TSC_BASE + SZ_8K - 1,
160 .flags = IORESOURCE_MEM, 156 .flags = IORESOURCE_MEM,
161 }, 157 },
162 [1] = { 158 [1] = {
163 .start = AM33XX_IRQ_ADC_GEN, 159 .start = AM33XX_IRQ_ADC_GEN,
164 .end = AM33XX_IRQ_ADC_GEN, 160 .end = AM33XX_IRQ_ADC_GEN,
165 .flags = IORESOURCE_IRQ, 161 .flags = IORESOURCE_IRQ,
166 }, 162 },
167 }; 163 };
168 164
169 static struct tsc_data am335x_touchscreen_data = { 165 static struct tsc_data am335x_touchscreen_data = {
170 .wires = 4, 166 .wires = 4,
171 .x_plate_resistance = 200, 167 .x_plate_resistance = 200,
172 }; 168 };
173 169
174 static struct platform_device tsc_device = { 170 static struct platform_device tsc_device = {
175 .name = "tsc", 171 .name = "tsc",
176 .id = -1, 172 .id = -1,
177 .dev = { 173 .dev = {
178 .platform_data = &am335x_touchscreen_data, 174 .platform_data = &am335x_touchscreen_data,
179 }, 175 },
180 .num_resources = ARRAY_SIZE(tsc_resources), 176 .num_resources = ARRAY_SIZE(tsc_resources),
181 .resource = tsc_resources, 177 .resource = tsc_resources,
182 }; 178 };
183 179
184 static u8 am335x_iis_serializer_direction1[] = { 180 static u8 am335x_iis_serializer_direction1[] = {
185 INACTIVE_MODE, INACTIVE_MODE, TX_MODE, RX_MODE, 181 INACTIVE_MODE, INACTIVE_MODE, TX_MODE, RX_MODE,
186 INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, 182 INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
187 INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, 183 INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
188 INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, 184 INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
189 }; 185 };
190 186
191 static struct snd_platform_data am335x_evm_snd_data1 = { 187 static struct snd_platform_data am335x_evm_snd_data1 = {
192 .tx_dma_offset = 0x46400000, /* McASP1 */ 188 .tx_dma_offset = 0x46400000, /* McASP1 */
193 .rx_dma_offset = 0x46400000, 189 .rx_dma_offset = 0x46400000,
194 .op_mode = DAVINCI_MCASP_IIS_MODE, 190 .op_mode = DAVINCI_MCASP_IIS_MODE,
195 .num_serializer = ARRAY_SIZE(am335x_iis_serializer_direction1), 191 .num_serializer = ARRAY_SIZE(am335x_iis_serializer_direction1),
196 .tdm_slots = 2, 192 .tdm_slots = 2,
197 .serial_dir = am335x_iis_serializer_direction1, 193 .serial_dir = am335x_iis_serializer_direction1,
198 .asp_chan_q = EVENTQ_2, 194 .asp_chan_q = EVENTQ_2,
199 .version = MCASP_VERSION_3, 195 .version = MCASP_VERSION_3,
200 .txnumevt = 1, 196 .txnumevt = 1,
201 .rxnumevt = 1, 197 .rxnumevt = 1,
202 }; 198 };
203 199
204 static struct omap2_hsmmc_info am335x_mmc[] __initdata = { 200 static struct omap2_hsmmc_info am335x_mmc[] __initdata = {
205 { 201 {
206 .mmc = 1, 202 .mmc = 1,
207 .caps = MMC_CAP_4_BIT_DATA, 203 .caps = MMC_CAP_4_BIT_DATA,
208 .gpio_cd = GPIO_TO_PIN(0, 6), 204 .gpio_cd = GPIO_TO_PIN(0, 6),
209 .gpio_wp = GPIO_TO_PIN(3, 18), 205 .gpio_wp = GPIO_TO_PIN(3, 18),
210 .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, /* 3V3 */ 206 .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, /* 3V3 */
211 }, 207 },
212 { 208 {
213 .mmc = 0, /* will be set at runtime */ 209 .mmc = 0, /* will be set at runtime */
214 }, 210 },
215 { 211 {
216 .mmc = 0, /* will be set at runtime */ 212 .mmc = 0, /* will be set at runtime */
217 }, 213 },
218 {} /* Terminator */ 214 {} /* Terminator */
219 }; 215 };
220 216
221 217
222 #ifdef CONFIG_OMAP_MUX 218 #ifdef CONFIG_OMAP_MUX
223 static struct omap_board_mux board_mux[] __initdata = { 219 static struct omap_board_mux board_mux[] __initdata = {
224 AM33XX_MUX(I2C0_SDA, OMAP_MUX_MODE0 | AM33XX_SLEWCTRL_SLOW | 220 AM33XX_MUX(I2C0_SDA, OMAP_MUX_MODE0 | AM33XX_SLEWCTRL_SLOW |
225 AM33XX_INPUT_EN | AM33XX_PIN_OUTPUT), 221 AM33XX_INPUT_EN | AM33XX_PIN_OUTPUT),
226 AM33XX_MUX(I2C0_SCL, OMAP_MUX_MODE0 | AM33XX_SLEWCTRL_SLOW | 222 AM33XX_MUX(I2C0_SCL, OMAP_MUX_MODE0 | AM33XX_SLEWCTRL_SLOW |
227 AM33XX_INPUT_EN | AM33XX_PIN_OUTPUT), 223 AM33XX_INPUT_EN | AM33XX_PIN_OUTPUT),
228 { .reg_offset = OMAP_MUX_TERMINATOR }, 224 { .reg_offset = OMAP_MUX_TERMINATOR },
229 }; 225 };
230 #else 226 #else
231 #define board_mux NULL 227 #define board_mux NULL
232 #endif 228 #endif
233 229
234 /* module pin mux structure */ 230 /* module pin mux structure */
235 struct pinmux_config { 231 struct pinmux_config {
236 const char *string_name; /* signal name format */ 232 const char *string_name; /* signal name format */
237 int val; /* Options for the mux register value */ 233 int val; /* Options for the mux register value */
238 }; 234 };
239 235
240 struct evm_dev_cfg { 236 struct evm_dev_cfg {
241 void (*device_init)(int evm_id, int profile); 237 void (*device_init)(int evm_id, int profile);
242 238
243 /* 239 /*
244 * If the device is required on both baseboard & daughter board (ex i2c), 240 * If the device is required on both baseboard & daughter board (ex i2c),
245 * specify DEV_ON_BASEBOARD 241 * specify DEV_ON_BASEBOARD
246 */ 242 */
247 #define DEV_ON_BASEBOARD 0 243 #define DEV_ON_BASEBOARD 0
248 #define DEV_ON_DGHTR_BRD 1 244 #define DEV_ON_DGHTR_BRD 1
249 u32 device_on; 245 u32 device_on;
250 246
251 u32 profile; /* Profiles (0-7) in which the module is present */ 247 u32 profile; /* Profiles (0-7) in which the module is present */
252 }; 248 };
253 249
254 /* AM335X - CPLD Register Offsets */ 250 /* AM335X - CPLD Register Offsets */
255 #define CPLD_DEVICE_HDR 0x00 /* CPLD Header */ 251 #define CPLD_DEVICE_HDR 0x00 /* CPLD Header */
256 #define CPLD_DEVICE_ID 0x04 /* CPLD identification */ 252 #define CPLD_DEVICE_ID 0x04 /* CPLD identification */
257 #define CPLD_DEVICE_REV 0x0C /* Revision of the CPLD code */ 253 #define CPLD_DEVICE_REV 0x0C /* Revision of the CPLD code */
258 #define CPLD_CFG_REG 0x10 /* Configuration Register */ 254 #define CPLD_CFG_REG 0x10 /* Configuration Register */
259 255
260 static struct i2c_client *cpld_client; 256 static struct i2c_client *cpld_client;
261 257
262 static u32 am335x_evm_id; 258 static u32 am335x_evm_id;
263 259
264 static struct omap_board_config_kernel am335x_evm_config[] __initdata = { 260 static struct omap_board_config_kernel am335x_evm_config[] __initdata = {
265 }; 261 };
266 262
267 /* 263 /*
268 * EVM Config held in On-Board eeprom device. 264 * EVM Config held in On-Board eeprom device.
269 * 265 *
270 * Header Format 266 * Header Format
271 * 267 *
272 * Name Size Contents 268 * Name Size Contents
273 * (Bytes) 269 * (Bytes)
274 *------------------------------------------------------------- 270 *-------------------------------------------------------------
275 * Header 4 0xAA, 0x55, 0x33, 0xEE 271 * Header 4 0xAA, 0x55, 0x33, 0xEE
276 * 272 *
277 * Board Name 8 Name for board in ASCII. 273 * Board Name 8 Name for board in ASCII.
278 * example "A33515BB" = "AM335X 274 * example "A33515BB" = "AM335X
279 Low Cost EVM board" 275 Low Cost EVM board"
280 * 276 *
281 * Version 4 Hardware version code for board in 277 * Version 4 Hardware version code for board in
282 * in ASCII. "1.0A" = rev.01.0A 278 * in ASCII. "1.0A" = rev.01.0A
283 * 279 *
284 * Serial Number 12 Serial number of the board. This is a 12 280 * Serial Number 12 Serial number of the board. This is a 12
285 * character string which is WWYY4P16nnnn, where 281 * character string which is WWYY4P16nnnn, where
286 * WW = 2 digit week of the year of production 282 * WW = 2 digit week of the year of production
287 * YY = 2 digit year of production 283 * YY = 2 digit year of production
288 * nnnn = incrementing board number 284 * nnnn = incrementing board number
289 * 285 *
290 * Configuration option 32 Codes(TBD) to show the configuration 286 * Configuration option 32 Codes(TBD) to show the configuration
291 * setup on this board. 287 * setup on this board.
292 * 288 *
293 * Available 32720 Available space for other non-volatile 289 * Available 32720 Available space for other non-volatile
294 * data. 290 * data.
295 */ 291 */
296 struct am335x_evm_eeprom_config { 292 struct am335x_evm_eeprom_config {
297 u32 header; 293 u32 header;
298 u8 name[8]; 294 u8 name[8];
299 char version[4]; 295 char version[4];
300 u8 serial[12]; 296 u8 serial[12];
301 u8 opt[32]; 297 u8 opt[32];
302 }; 298 };
303 299
304 static struct am335x_evm_eeprom_config config; 300 static struct am335x_evm_eeprom_config config;
305 static bool daughter_brd_detected; 301 static bool daughter_brd_detected;
306 302
307 #define GP_EVM_REV_IS_1_0 0x1 303 #define GP_EVM_REV_IS_1_0 0x1
308 #define GP_EVM_REV_IS_1_1A 0x2 304 #define GP_EVM_REV_IS_1_1A 0x2
309 #define GP_EVM_REV_IS_UNKNOWN 0xFF 305 #define GP_EVM_REV_IS_UNKNOWN 0xFF
310 static unsigned int gp_evm_revision = GP_EVM_REV_IS_UNKNOWN; 306 static unsigned int gp_evm_revision = GP_EVM_REV_IS_UNKNOWN;
311 unsigned int gigabit_enable = 1; 307 unsigned int gigabit_enable = 1;
312 308
313 #define EEPROM_MAC_ADDRESS_OFFSET 60 /* 4+8+4+12+32 */ 309 #define EEPROM_MAC_ADDRESS_OFFSET 60 /* 4+8+4+12+32 */
314 #define EEPROM_NO_OF_MAC_ADDR 3 310 #define EEPROM_NO_OF_MAC_ADDR 3
315 static char am335x_mac_addr[EEPROM_NO_OF_MAC_ADDR][ETH_ALEN]; 311 static char am335x_mac_addr[EEPROM_NO_OF_MAC_ADDR][ETH_ALEN];
316 312
317 #define AM335X_EEPROM_HEADER 0xEE3355AA 313 #define AM335X_EEPROM_HEADER 0xEE3355AA
318 314
319 /* current profile if exists else PROFILE_0 on error */ 315 /* current profile if exists else PROFILE_0 on error */
320 static u32 am335x_get_profile_selection(void) 316 static u32 am335x_get_profile_selection(void)
321 { 317 {
322 int val = 0; 318 int val = 0;
323 319
324 if (!cpld_client) 320 if (!cpld_client)
325 /* error checking is not done in func's calling this routine. 321 /* error checking is not done in func's calling this routine.
326 so return profile 0 on error */ 322 so return profile 0 on error */
327 return 0; 323 return 0;
328 324
329 val = i2c_smbus_read_word_data(cpld_client, CPLD_CFG_REG); 325 val = i2c_smbus_read_word_data(cpld_client, CPLD_CFG_REG);
330 if (val < 0) 326 if (val < 0)
331 return 0; /* default to Profile 0 on Error */ 327 return 0; /* default to Profile 0 on Error */
332 else 328 else
333 return val & 0x7; 329 return val & 0x7;
334 } 330 }
335 331
336 /* Module pin mux for LCDC */ 332 /* Module pin mux for LCDC */
337 static struct pinmux_config lcdc_pin_mux[] = { 333 static struct pinmux_config lcdc_pin_mux[] = {
338 {"lcd_data0.lcd_data0", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT 334 {"lcd_data0.lcd_data0", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
339 | AM33XX_PULL_DISA}, 335 | AM33XX_PULL_DISA},
340 {"lcd_data1.lcd_data1", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT 336 {"lcd_data1.lcd_data1", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
341 | AM33XX_PULL_DISA}, 337 | AM33XX_PULL_DISA},
342 {"lcd_data2.lcd_data2", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT 338 {"lcd_data2.lcd_data2", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
343 | AM33XX_PULL_DISA}, 339 | AM33XX_PULL_DISA},
344 {"lcd_data3.lcd_data3", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT 340 {"lcd_data3.lcd_data3", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
345 | AM33XX_PULL_DISA}, 341 | AM33XX_PULL_DISA},
346 {"lcd_data4.lcd_data4", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT 342 {"lcd_data4.lcd_data4", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
347 | AM33XX_PULL_DISA}, 343 | AM33XX_PULL_DISA},
348 {"lcd_data5.lcd_data5", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT 344 {"lcd_data5.lcd_data5", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
349 | AM33XX_PULL_DISA}, 345 | AM33XX_PULL_DISA},
350 {"lcd_data6.lcd_data6", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT 346 {"lcd_data6.lcd_data6", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
351 | AM33XX_PULL_DISA}, 347 | AM33XX_PULL_DISA},
352 {"lcd_data7.lcd_data7", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT 348 {"lcd_data7.lcd_data7", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
353 | AM33XX_PULL_DISA}, 349 | AM33XX_PULL_DISA},
354 {"lcd_data8.lcd_data8", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT 350 {"lcd_data8.lcd_data8", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
355 | AM33XX_PULL_DISA}, 351 | AM33XX_PULL_DISA},
356 {"lcd_data9.lcd_data9", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT 352 {"lcd_data9.lcd_data9", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
357 | AM33XX_PULL_DISA}, 353 | AM33XX_PULL_DISA},
358 {"lcd_data10.lcd_data10", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT 354 {"lcd_data10.lcd_data10", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
359 | AM33XX_PULL_DISA}, 355 | AM33XX_PULL_DISA},
360 {"lcd_data11.lcd_data11", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT 356 {"lcd_data11.lcd_data11", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
361 | AM33XX_PULL_DISA}, 357 | AM33XX_PULL_DISA},
362 {"lcd_data12.lcd_data12", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT 358 {"lcd_data12.lcd_data12", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
363 | AM33XX_PULL_DISA}, 359 | AM33XX_PULL_DISA},
364 {"lcd_data13.lcd_data13", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT 360 {"lcd_data13.lcd_data13", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
365 | AM33XX_PULL_DISA}, 361 | AM33XX_PULL_DISA},
366 {"lcd_data14.lcd_data14", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT 362 {"lcd_data14.lcd_data14", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
367 | AM33XX_PULL_DISA}, 363 | AM33XX_PULL_DISA},
368 {"lcd_data15.lcd_data15", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT 364 {"lcd_data15.lcd_data15", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
369 | AM33XX_PULL_DISA}, 365 | AM33XX_PULL_DISA},
370 {"gpmc_ad8.lcd_data16", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT}, 366 {"gpmc_ad8.lcd_data16", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
371 {"gpmc_ad9.lcd_data17", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT}, 367 {"gpmc_ad9.lcd_data17", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
372 {"gpmc_ad10.lcd_data18", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT}, 368 {"gpmc_ad10.lcd_data18", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
373 {"gpmc_ad11.lcd_data19", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT}, 369 {"gpmc_ad11.lcd_data19", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
374 {"gpmc_ad12.lcd_data20", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT}, 370 {"gpmc_ad12.lcd_data20", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
375 {"gpmc_ad13.lcd_data21", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT}, 371 {"gpmc_ad13.lcd_data21", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
376 {"gpmc_ad14.lcd_data22", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT}, 372 {"gpmc_ad14.lcd_data22", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
377 {"gpmc_ad15.lcd_data23", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT}, 373 {"gpmc_ad15.lcd_data23", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
378 {"lcd_vsync.lcd_vsync", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, 374 {"lcd_vsync.lcd_vsync", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
379 {"lcd_hsync.lcd_hsync", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, 375 {"lcd_hsync.lcd_hsync", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
380 {"lcd_pclk.lcd_pclk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, 376 {"lcd_pclk.lcd_pclk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
381 {"lcd_ac_bias_en.lcd_ac_bias_en", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, 377 {"lcd_ac_bias_en.lcd_ac_bias_en", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
382 {NULL, 0}, 378 {NULL, 0},
383 }; 379 };
384 380
385 static struct pinmux_config tsc_pin_mux[] = { 381 static struct pinmux_config tsc_pin_mux[] = {
386 {"ain0.ain0", OMAP_MUX_MODE0 | AM33XX_INPUT_EN}, 382 {"ain0.ain0", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
387 {"ain1.ain1", OMAP_MUX_MODE0 | AM33XX_INPUT_EN}, 383 {"ain1.ain1", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
388 {"ain2.ain2", OMAP_MUX_MODE0 | AM33XX_INPUT_EN}, 384 {"ain2.ain2", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
389 {"ain3.ain3", OMAP_MUX_MODE0 | AM33XX_INPUT_EN}, 385 {"ain3.ain3", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
390 {"vrefp.vrefp", OMAP_MUX_MODE0 | AM33XX_INPUT_EN}, 386 {"vrefp.vrefp", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
391 {"vrefn.vrefn", OMAP_MUX_MODE0 | AM33XX_INPUT_EN}, 387 {"vrefn.vrefn", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
392 {NULL, 0}, 388 {NULL, 0},
393 }; 389 };
394 390
395 /* Pin mux for nand flash module */ 391 /* Pin mux for nand flash module */
396 static struct pinmux_config nand_pin_mux[] = { 392 static struct pinmux_config nand_pin_mux[] = {
397 {"gpmc_ad0.gpmc_ad0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 393 {"gpmc_ad0.gpmc_ad0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
398 {"gpmc_ad1.gpmc_ad1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 394 {"gpmc_ad1.gpmc_ad1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
399 {"gpmc_ad2.gpmc_ad2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 395 {"gpmc_ad2.gpmc_ad2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
400 {"gpmc_ad3.gpmc_ad3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 396 {"gpmc_ad3.gpmc_ad3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
401 {"gpmc_ad4.gpmc_ad4", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 397 {"gpmc_ad4.gpmc_ad4", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
402 {"gpmc_ad5.gpmc_ad5", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 398 {"gpmc_ad5.gpmc_ad5", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
403 {"gpmc_ad6.gpmc_ad6", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 399 {"gpmc_ad6.gpmc_ad6", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
404 {"gpmc_ad7.gpmc_ad7", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 400 {"gpmc_ad7.gpmc_ad7", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
405 {"gpmc_wait0.gpmc_wait0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 401 {"gpmc_wait0.gpmc_wait0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
406 {"gpmc_wpn.gpmc_wpn", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP}, 402 {"gpmc_wpn.gpmc_wpn", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
407 {"gpmc_csn0.gpmc_csn0", OMAP_MUX_MODE0 | AM33XX_PULL_DISA}, 403 {"gpmc_csn0.gpmc_csn0", OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
408 {"gpmc_advn_ale.gpmc_advn_ale", OMAP_MUX_MODE0 | AM33XX_PULL_DISA}, 404 {"gpmc_advn_ale.gpmc_advn_ale", OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
409 {"gpmc_oen_ren.gpmc_oen_ren", OMAP_MUX_MODE0 | AM33XX_PULL_DISA}, 405 {"gpmc_oen_ren.gpmc_oen_ren", OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
410 {"gpmc_wen.gpmc_wen", OMAP_MUX_MODE0 | AM33XX_PULL_DISA}, 406 {"gpmc_wen.gpmc_wen", OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
411 {"gpmc_ben0_cle.gpmc_ben0_cle", OMAP_MUX_MODE0 | AM33XX_PULL_DISA}, 407 {"gpmc_ben0_cle.gpmc_ben0_cle", OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
412 {NULL, 0}, 408 {NULL, 0},
413 }; 409 };
414 410
415 /* Module pin mux for SPI fash */ 411 /* Module pin mux for SPI fash */
416 static struct pinmux_config spi0_pin_mux[] = { 412 static struct pinmux_config spi0_pin_mux[] = {
417 {"spi0_sclk.spi0_sclk", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL 413 {"spi0_sclk.spi0_sclk", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL
418 | AM33XX_INPUT_EN}, 414 | AM33XX_INPUT_EN},
419 {"spi0_d0.spi0_d0", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL | AM33XX_PULL_UP 415 {"spi0_d0.spi0_d0", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL | AM33XX_PULL_UP
420 | AM33XX_INPUT_EN}, 416 | AM33XX_INPUT_EN},
421 {"spi0_d1.spi0_d1", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL 417 {"spi0_d1.spi0_d1", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL
422 | AM33XX_INPUT_EN}, 418 | AM33XX_INPUT_EN},
423 {"spi0_cs0.spi0_cs0", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL | AM33XX_PULL_UP 419 {"spi0_cs0.spi0_cs0", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL | AM33XX_PULL_UP
424 | AM33XX_INPUT_EN}, 420 | AM33XX_INPUT_EN},
425 {NULL, 0}, 421 {NULL, 0},
426 }; 422 };
427 423
428 /* Module pin mux for SPI flash */ 424 /* Module pin mux for SPI flash */
429 static struct pinmux_config spi1_pin_mux[] = { 425 static struct pinmux_config spi1_pin_mux[] = {
430 {"mcasp0_aclkx.spi1_sclk", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL 426 {"mcasp0_aclkx.spi1_sclk", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
431 | AM33XX_INPUT_EN}, 427 | AM33XX_INPUT_EN},
432 {"mcasp0_fsx.spi1_d0", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL 428 {"mcasp0_fsx.spi1_d0", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
433 | AM33XX_PULL_UP | AM33XX_INPUT_EN}, 429 | AM33XX_PULL_UP | AM33XX_INPUT_EN},
434 {"mcasp0_axr0.spi1_d1", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL 430 {"mcasp0_axr0.spi1_d1", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
435 | AM33XX_INPUT_EN}, 431 | AM33XX_INPUT_EN},
436 {"mcasp0_ahclkr.spi1_cs0", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL 432 {"mcasp0_ahclkr.spi1_cs0", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
437 | AM33XX_PULL_UP | AM33XX_INPUT_EN}, 433 | AM33XX_PULL_UP | AM33XX_INPUT_EN},
438 {NULL, 0}, 434 {NULL, 0},
439 }; 435 };
440 436
441 /* Module pin mux for rgmii1 */ 437 /* Module pin mux for rgmii1 */
442 static struct pinmux_config rgmii1_pin_mux[] = { 438 static struct pinmux_config rgmii1_pin_mux[] = {
443 {"mii1_txen.rgmii1_tctl", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, 439 {"mii1_txen.rgmii1_tctl", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
444 {"mii1_rxdv.rgmii1_rctl", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, 440 {"mii1_rxdv.rgmii1_rctl", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
445 {"mii1_txd3.rgmii1_td3", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, 441 {"mii1_txd3.rgmii1_td3", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
446 {"mii1_txd2.rgmii1_td2", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, 442 {"mii1_txd2.rgmii1_td2", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
447 {"mii1_txd1.rgmii1_td1", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, 443 {"mii1_txd1.rgmii1_td1", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
448 {"mii1_txd0.rgmii1_td0", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, 444 {"mii1_txd0.rgmii1_td0", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
449 {"mii1_txclk.rgmii1_tclk", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, 445 {"mii1_txclk.rgmii1_tclk", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
450 {"mii1_rxclk.rgmii1_rclk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, 446 {"mii1_rxclk.rgmii1_rclk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
451 {"mii1_rxd3.rgmii1_rd3", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, 447 {"mii1_rxd3.rgmii1_rd3", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
452 {"mii1_rxd2.rgmii1_rd2", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, 448 {"mii1_rxd2.rgmii1_rd2", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
453 {"mii1_rxd1.rgmii1_rd1", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, 449 {"mii1_rxd1.rgmii1_rd1", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
454 {"mii1_rxd0.rgmii1_rd0", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, 450 {"mii1_rxd0.rgmii1_rd0", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
455 {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 451 {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
456 {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP}, 452 {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
457 {NULL, 0}, 453 {NULL, 0},
458 }; 454 };
459 455
460 /* Module pin mux for rgmii2 */ 456 /* Module pin mux for rgmii2 */
461 static struct pinmux_config rgmii2_pin_mux[] = { 457 static struct pinmux_config rgmii2_pin_mux[] = {
462 {"gpmc_a0.rgmii2_tctl", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, 458 {"gpmc_a0.rgmii2_tctl", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
463 {"gpmc_a1.rgmii2_rctl", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, 459 {"gpmc_a1.rgmii2_rctl", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
464 {"gpmc_a2.rgmii2_td3", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, 460 {"gpmc_a2.rgmii2_td3", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
465 {"gpmc_a3.rgmii2_td2", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, 461 {"gpmc_a3.rgmii2_td2", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
466 {"gpmc_a4.rgmii2_td1", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, 462 {"gpmc_a4.rgmii2_td1", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
467 {"gpmc_a5.rgmii2_td0", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, 463 {"gpmc_a5.rgmii2_td0", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
468 {"gpmc_a6.rgmii2_tclk", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, 464 {"gpmc_a6.rgmii2_tclk", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
469 {"gpmc_a7.rgmii2_rclk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, 465 {"gpmc_a7.rgmii2_rclk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
470 {"gpmc_a8.rgmii2_rd3", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, 466 {"gpmc_a8.rgmii2_rd3", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
471 {"gpmc_a9.rgmii2_rd2", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, 467 {"gpmc_a9.rgmii2_rd2", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
472 {"gpmc_a10.rgmii2_rd1", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, 468 {"gpmc_a10.rgmii2_rd1", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
473 {"gpmc_a11.rgmii2_rd0", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, 469 {"gpmc_a11.rgmii2_rd0", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
474 {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 470 {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
475 {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP}, 471 {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
476 {NULL, 0}, 472 {NULL, 0},
477 }; 473 };
478 474
479 /* Module pin mux for mii1 */ 475 /* Module pin mux for mii1 */
480 static struct pinmux_config mii1_pin_mux[] = { 476 static struct pinmux_config mii1_pin_mux[] = {
481 {"mii1_rxerr.mii1_rxerr", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN}, 477 {"mii1_rxerr.mii1_rxerr", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
482 {"mii1_txen.mii1_txen", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, 478 {"mii1_txen.mii1_txen", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
483 {"mii1_rxdv.mii1_rxdv", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN}, 479 {"mii1_rxdv.mii1_rxdv", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
484 {"mii1_txd3.mii1_txd3", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, 480 {"mii1_txd3.mii1_txd3", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
485 {"mii1_txd2.mii1_txd2", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, 481 {"mii1_txd2.mii1_txd2", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
486 {"mii1_txd1.mii1_txd1", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, 482 {"mii1_txd1.mii1_txd1", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
487 {"mii1_txd0.mii1_txd0", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, 483 {"mii1_txd0.mii1_txd0", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
488 {"mii1_txclk.mii1_txclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN}, 484 {"mii1_txclk.mii1_txclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
489 {"mii1_rxclk.mii1_rxclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN}, 485 {"mii1_rxclk.mii1_rxclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
490 {"mii1_rxd3.mii1_rxd3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN}, 486 {"mii1_rxd3.mii1_rxd3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
491 {"mii1_rxd2.mii1_rxd2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN}, 487 {"mii1_rxd2.mii1_rxd2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
492 {"mii1_rxd1.mii1_rxd1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN}, 488 {"mii1_rxd1.mii1_rxd1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
493 {"mii1_rxd0.mii1_rxd0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN}, 489 {"mii1_rxd0.mii1_rxd0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
494 {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 490 {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
495 {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP}, 491 {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
496 {NULL, 0}, 492 {NULL, 0},
497 }; 493 };
498 494
499 /* Module pin mux for rmii1 */ 495 /* Module pin mux for rmii1 */
500 static struct pinmux_config rmii1_pin_mux[] = { 496 static struct pinmux_config rmii1_pin_mux[] = {
501 {"mii1_crs.rmii1_crs_dv", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN}, 497 {"mii1_crs.rmii1_crs_dv", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
502 {"mii1_rxerr.mii1_rxerr", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN}, 498 {"mii1_rxerr.mii1_rxerr", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
503 {"mii1_txen.mii1_txen", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT}, 499 {"mii1_txen.mii1_txen", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
504 {"mii1_txd1.mii1_txd1", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT}, 500 {"mii1_txd1.mii1_txd1", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
505 {"mii1_txd0.mii1_txd0", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT}, 501 {"mii1_txd0.mii1_txd0", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
506 {"mii1_rxd1.mii1_rxd1", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN}, 502 {"mii1_rxd1.mii1_rxd1", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
507 {"mii1_rxd0.mii1_rxd0", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN}, 503 {"mii1_rxd0.mii1_rxd0", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
508 {"rmii1_refclk.rmii1_refclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN}, 504 {"rmii1_refclk.rmii1_refclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
509 {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 505 {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
510 {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP}, 506 {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
511 {NULL, 0}, 507 {NULL, 0},
512 }; 508 };
513 509
514 static struct pinmux_config i2c1_pin_mux[] = { 510 static struct pinmux_config i2c1_pin_mux[] = {
515 {"spi0_d1.i2c1_sda", OMAP_MUX_MODE2 | AM33XX_SLEWCTRL_SLOW | 511 {"spi0_d1.i2c1_sda", OMAP_MUX_MODE2 | AM33XX_SLEWCTRL_SLOW |
516 AM33XX_PULL_ENBL | AM33XX_INPUT_EN}, 512 AM33XX_PULL_ENBL | AM33XX_INPUT_EN},
517 {"spi0_cs0.i2c1_scl", OMAP_MUX_MODE2 | AM33XX_SLEWCTRL_SLOW | 513 {"spi0_cs0.i2c1_scl", OMAP_MUX_MODE2 | AM33XX_SLEWCTRL_SLOW |
518 AM33XX_PULL_ENBL | AM33XX_INPUT_EN}, 514 AM33XX_PULL_ENBL | AM33XX_INPUT_EN},
519 {NULL, 0}, 515 {NULL, 0},
520 }; 516 };
521 517
522 /* Module pin mux for mcasp1 */ 518 /* Module pin mux for mcasp1 */
523 static struct pinmux_config mcasp1_pin_mux[] = { 519 static struct pinmux_config mcasp1_pin_mux[] = {
524 {"mii1_crs.mcasp1_aclkx", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN}, 520 {"mii1_crs.mcasp1_aclkx", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
525 {"mii1_rxerr.mcasp1_fsx", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN}, 521 {"mii1_rxerr.mcasp1_fsx", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
526 {"mii1_col.mcasp1_axr2", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN}, 522 {"mii1_col.mcasp1_axr2", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
527 {"rmii1_refclk.mcasp1_axr3", OMAP_MUX_MODE4 | 523 {"rmii1_refclk.mcasp1_axr3", OMAP_MUX_MODE4 |
528 AM33XX_PIN_INPUT_PULLDOWN}, 524 AM33XX_PIN_INPUT_PULLDOWN},
529 {NULL, 0}, 525 {NULL, 0},
530 }; 526 };
531 527
532 528
533 /* Module pin mux for mmc0 */ 529 /* Module pin mux for mmc0 */
534 static struct pinmux_config mmc0_pin_mux[] = { 530 static struct pinmux_config mmc0_pin_mux[] = {
535 {"mmc0_dat3.mmc0_dat3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 531 {"mmc0_dat3.mmc0_dat3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
536 {"mmc0_dat2.mmc0_dat2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 532 {"mmc0_dat2.mmc0_dat2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
537 {"mmc0_dat1.mmc0_dat1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 533 {"mmc0_dat1.mmc0_dat1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
538 {"mmc0_dat0.mmc0_dat0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 534 {"mmc0_dat0.mmc0_dat0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
539 {"mmc0_clk.mmc0_clk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 535 {"mmc0_clk.mmc0_clk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
540 {"mmc0_cmd.mmc0_cmd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 536 {"mmc0_cmd.mmc0_cmd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
541 {"mcasp0_aclkr.mmc0_sdwp", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP}, 537 {"mcasp0_aclkr.mmc0_sdwp", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
542 {"spi0_cs1.mmc0_sdcd", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP}, 538 {"spi0_cs1.mmc0_sdcd", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
543 {NULL, 0}, 539 {NULL, 0},
544 }; 540 };
545 541
546 static struct pinmux_config mmc0_no_cd_pin_mux[] = { 542 static struct pinmux_config mmc0_no_cd_pin_mux[] = {
547 {"mmc0_dat3.mmc0_dat3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 543 {"mmc0_dat3.mmc0_dat3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
548 {"mmc0_dat2.mmc0_dat2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 544 {"mmc0_dat2.mmc0_dat2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
549 {"mmc0_dat1.mmc0_dat1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 545 {"mmc0_dat1.mmc0_dat1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
550 {"mmc0_dat0.mmc0_dat0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 546 {"mmc0_dat0.mmc0_dat0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
551 {"mmc0_clk.mmc0_clk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 547 {"mmc0_clk.mmc0_clk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
552 {"mmc0_cmd.mmc0_cmd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 548 {"mmc0_cmd.mmc0_cmd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
553 {"mcasp0_aclkr.mmc0_sdwp", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN}, 549 {"mcasp0_aclkr.mmc0_sdwp", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
554 {NULL, 0}, 550 {NULL, 0},
555 }; 551 };
556 552
557 /* Module pin mux for mmc1 */ 553 /* Module pin mux for mmc1 */
558 static struct pinmux_config mmc1_pin_mux[] = { 554 static struct pinmux_config mmc1_pin_mux[] = {
559 {"gpmc_ad7.mmc1_dat7", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP}, 555 {"gpmc_ad7.mmc1_dat7", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
560 {"gpmc_ad6.mmc1_dat6", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP}, 556 {"gpmc_ad6.mmc1_dat6", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
561 {"gpmc_ad5.mmc1_dat5", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP}, 557 {"gpmc_ad5.mmc1_dat5", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
562 {"gpmc_ad4.mmc1_dat4", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP}, 558 {"gpmc_ad4.mmc1_dat4", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
563 {"gpmc_ad3.mmc1_dat3", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP}, 559 {"gpmc_ad3.mmc1_dat3", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
564 {"gpmc_ad2.mmc1_dat2", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP}, 560 {"gpmc_ad2.mmc1_dat2", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
565 {"gpmc_ad1.mmc1_dat1", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP}, 561 {"gpmc_ad1.mmc1_dat1", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
566 {"gpmc_ad0.mmc1_dat0", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP}, 562 {"gpmc_ad0.mmc1_dat0", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
567 {"gpmc_csn1.mmc1_clk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP}, 563 {"gpmc_csn1.mmc1_clk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
568 {"gpmc_csn2.mmc1_cmd", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP}, 564 {"gpmc_csn2.mmc1_cmd", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
569 {"gpmc_csn0.mmc1_sdwp", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP}, 565 {"gpmc_csn0.mmc1_sdwp", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
570 {"gpmc_advn_ale.mmc1_sdcd", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP}, 566 {"gpmc_advn_ale.mmc1_sdcd", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
571 {NULL, 0}, 567 {NULL, 0},
572 }; 568 };
573 569
574 /* Module pin mux for uart3 */ 570 /* Module pin mux for uart3 */
575 static struct pinmux_config uart3_pin_mux[] = { 571 static struct pinmux_config uart3_pin_mux[] = {
576 {"spi0_cs1.uart3_rxd", AM33XX_PIN_INPUT_PULLUP}, 572 {"spi0_cs1.uart3_rxd", AM33XX_PIN_INPUT_PULLUP},
577 {"ecap0_in_pwm0_out.uart3_txd", AM33XX_PULL_ENBL}, 573 {"ecap0_in_pwm0_out.uart3_txd", AM33XX_PULL_ENBL},
578 {NULL, 0}, 574 {NULL, 0},
579 }; 575 };
580 576
581 static struct pinmux_config d_can_gp_pin_mux[] = { 577 static struct pinmux_config d_can_gp_pin_mux[] = {
582 {"uart0_ctsn.d_can1_tx", OMAP_MUX_MODE2 | AM33XX_PULL_ENBL}, 578 {"uart0_ctsn.d_can1_tx", OMAP_MUX_MODE2 | AM33XX_PULL_ENBL},
583 {"uart0_rtsn.d_can1_rx", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP}, 579 {"uart0_rtsn.d_can1_rx", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
584 {NULL, 0}, 580 {NULL, 0},
585 }; 581 };
586 582
587 static struct pinmux_config d_can_ia_pin_mux[] = { 583 static struct pinmux_config d_can_ia_pin_mux[] = {
588 {"uart0_rxd.d_can0_tx", OMAP_MUX_MODE2 | AM33XX_PULL_ENBL}, 584 {"uart0_rxd.d_can0_tx", OMAP_MUX_MODE2 | AM33XX_PULL_ENBL},
589 {"uart0_txd.d_can0_rx", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP}, 585 {"uart0_txd.d_can0_rx", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
590 {NULL, 0}, 586 {NULL, 0},
591 }; 587 };
592 588
593 /* 589 /*
594 * @pin_mux - single module pin-mux structure which defines pin-mux 590 * @pin_mux - single module pin-mux structure which defines pin-mux
595 * details for all its pins. 591 * details for all its pins.
596 */ 592 */
597 static void setup_pin_mux(struct pinmux_config *pin_mux) 593 static void setup_pin_mux(struct pinmux_config *pin_mux)
598 { 594 {
599 int i; 595 int i;
600 596
601 for (i = 0; pin_mux->string_name != NULL; pin_mux++) 597 for (i = 0; pin_mux->string_name != NULL; pin_mux++)
602 omap_mux_init_signal(pin_mux->string_name, pin_mux->val); 598 omap_mux_init_signal(pin_mux->string_name, pin_mux->val);
603 599
604 } 600 }
605 601
606 /* Matrix GPIO Keypad Support for profile-0 only: TODO */ 602 /* Matrix GPIO Keypad Support for profile-0 only: TODO */
607 #ifdef CONFIG_KEYBOARD_MATRIX 603 #ifdef CONFIG_KEYBOARD_MATRIX
608 604
609 /* pinmux for keypad device */ 605 /* pinmux for keypad device */
610 static struct pinmux_config matrix_keypad_pin_mux[] = { 606 static struct pinmux_config matrix_keypad_pin_mux[] = {
611 {"gpmc_a5.gpio1_21", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT}, 607 {"gpmc_a5.gpio1_21", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
612 {"gpmc_a8.gpio1_22", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT}, 608 {"gpmc_a8.gpio1_22", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
613 {"gpmc_a9.gpio1_25", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT}, 609 {"gpmc_a9.gpio1_25", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
614 {"gpmc_a10.gpio1_26", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT}, 610 {"gpmc_a10.gpio1_26", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
615 {"gpmc_a11.gpio1_27", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT}, 611 {"gpmc_a11.gpio1_27", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
616 {NULL, 0}, 612 {NULL, 0},
617 }; 613 };
618 614
619 /* Keys mapping */ 615 /* Keys mapping */
620 static const uint32_t am335x_evm_matrix_keys[] = { 616 static const uint32_t am335x_evm_matrix_keys[] = {
621 KEY(0, 0, KEY_MENU), 617 KEY(0, 0, KEY_MENU),
622 KEY(1, 0, KEY_BACK), 618 KEY(1, 0, KEY_BACK),
623 KEY(2, 0, KEY_LEFT), 619 KEY(2, 0, KEY_LEFT),
624 620
625 KEY(0, 1, KEY_RIGHT), 621 KEY(0, 1, KEY_RIGHT),
626 KEY(1, 1, KEY_ENTER), 622 KEY(1, 1, KEY_ENTER),
627 KEY(2, 1, KEY_DOWN), 623 KEY(2, 1, KEY_DOWN),
628 }; 624 };
629 625
630 const struct matrix_keymap_data am335x_evm_keymap_data = { 626 const struct matrix_keymap_data am335x_evm_keymap_data = {
631 .keymap = am335x_evm_matrix_keys, 627 .keymap = am335x_evm_matrix_keys,
632 .keymap_size = ARRAY_SIZE(am335x_evm_matrix_keys), 628 .keymap_size = ARRAY_SIZE(am335x_evm_matrix_keys),
633 }; 629 };
634 630
635 static const unsigned int am335x_evm_keypad_row_gpios[] = { 631 static const unsigned int am335x_evm_keypad_row_gpios[] = {
636 GPIO_TO_PIN(1, 25), GPIO_TO_PIN(1, 26), GPIO_TO_PIN(1, 27) 632 GPIO_TO_PIN(1, 25), GPIO_TO_PIN(1, 26), GPIO_TO_PIN(1, 27)
637 }; 633 };
638 634
639 static const unsigned int am335x_evm_keypad_col_gpios[] = { 635 static const unsigned int am335x_evm_keypad_col_gpios[] = {
640 GPIO_TO_PIN(1, 21), GPIO_TO_PIN(1, 22) 636 GPIO_TO_PIN(1, 21), GPIO_TO_PIN(1, 22)
641 }; 637 };
642 638
643 static struct matrix_keypad_platform_data am335x_evm_keypad_platform_data = { 639 static struct matrix_keypad_platform_data am335x_evm_keypad_platform_data = {
644 .keymap_data = &am335x_evm_keymap_data, 640 .keymap_data = &am335x_evm_keymap_data,
645 .row_gpios = am335x_evm_keypad_row_gpios, 641 .row_gpios = am335x_evm_keypad_row_gpios,
646 .num_row_gpios = ARRAY_SIZE(am335x_evm_keypad_row_gpios), 642 .num_row_gpios = ARRAY_SIZE(am335x_evm_keypad_row_gpios),
647 .col_gpios = am335x_evm_keypad_col_gpios, 643 .col_gpios = am335x_evm_keypad_col_gpios,
648 .num_col_gpios = ARRAY_SIZE(am335x_evm_keypad_col_gpios), 644 .num_col_gpios = ARRAY_SIZE(am335x_evm_keypad_col_gpios),
649 .active_low = false, 645 .active_low = false,
650 .debounce_ms = 5, 646 .debounce_ms = 5,
651 .col_scan_delay_us = 2, 647 .col_scan_delay_us = 2,
652 }; 648 };
653 649
654 static struct platform_device am335x_evm_keyboard = { 650 static struct platform_device am335x_evm_keyboard = {
655 .name = "matrix-keypad", 651 .name = "matrix-keypad",
656 .id = -1, 652 .id = -1,
657 .dev = { 653 .dev = {
658 .platform_data = &am335x_evm_keypad_platform_data, 654 .platform_data = &am335x_evm_keypad_platform_data,
659 }, 655 },
660 }; 656 };
661 657
662 static void matrix_keypad_init(int evm_id, int profile) 658 static void matrix_keypad_init(int evm_id, int profile)
663 { 659 {
664 int err; 660 int err;
665 661
666 setup_pin_mux(matrix_keypad_pin_mux); 662 setup_pin_mux(matrix_keypad_pin_mux);
667 err = platform_device_register(&am335x_evm_keyboard); 663 err = platform_device_register(&am335x_evm_keyboard);
668 if (err) { 664 if (err) {
669 pr_err("failed to register matrix keypad (2x3) device\n"); 665 pr_err("failed to register matrix keypad (2x3) device\n");
670 } 666 }
671 } 667 }
672 #endif 668 #endif
673 669
674 670
675 #ifdef CONFIG_KEYBOARD_GPIO 671 #ifdef CONFIG_KEYBOARD_GPIO
676 /* pinmux for keypad device */ 672 /* pinmux for keypad device */
677 static struct pinmux_config volume_keys_pin_mux[] = { 673 static struct pinmux_config volume_keys_pin_mux[] = {
678 {"spi0_sclk.gpio0_2", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT}, 674 {"spi0_sclk.gpio0_2", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
679 {"spi0_d0.gpio0_3", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT}, 675 {"spi0_d0.gpio0_3", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
680 {NULL, 0}, 676 {NULL, 0},
681 }; 677 };
682 678
683 /* Configure GPIOs for Volume Keys */ 679 /* Configure GPIOs for Volume Keys */
684 static struct gpio_keys_button am335x_evm_volume_gpio_buttons[] = { 680 static struct gpio_keys_button am335x_evm_volume_gpio_buttons[] = {
685 { 681 {
686 .code = KEY_VOLUMEUP, 682 .code = KEY_VOLUMEUP,
687 .gpio = GPIO_TO_PIN(0, 2), 683 .gpio = GPIO_TO_PIN(0, 2),
688 .active_low = true, 684 .active_low = true,
689 .desc = "volume-up", 685 .desc = "volume-up",
690 .type = EV_KEY, 686 .type = EV_KEY,
691 .wakeup = 1, 687 .wakeup = 1,
692 }, 688 },
693 { 689 {
694 .code = KEY_VOLUMEDOWN, 690 .code = KEY_VOLUMEDOWN,
695 .gpio = GPIO_TO_PIN(0, 3), 691 .gpio = GPIO_TO_PIN(0, 3),
696 .active_low = true, 692 .active_low = true,
697 .desc = "volume-down", 693 .desc = "volume-down",
698 .type = EV_KEY, 694 .type = EV_KEY,
699 .wakeup = 1, 695 .wakeup = 1,
700 }, 696 },
701 }; 697 };
702 698
703 static struct gpio_keys_platform_data am335x_evm_volume_gpio_key_info = { 699 static struct gpio_keys_platform_data am335x_evm_volume_gpio_key_info = {
704 .buttons = am335x_evm_volume_gpio_buttons, 700 .buttons = am335x_evm_volume_gpio_buttons,
705 .nbuttons = ARRAY_SIZE(am335x_evm_volume_gpio_buttons), 701 .nbuttons = ARRAY_SIZE(am335x_evm_volume_gpio_buttons),
706 }; 702 };
707 703
708 static struct platform_device am335x_evm_volume_keys = { 704 static struct platform_device am335x_evm_volume_keys = {
709 .name = "gpio-keys", 705 .name = "gpio-keys",
710 .id = -1, 706 .id = -1,
711 .dev = { 707 .dev = {
712 .platform_data = &am335x_evm_volume_gpio_key_info, 708 .platform_data = &am335x_evm_volume_gpio_key_info,
713 }, 709 },
714 }; 710 };
715 711
716 static void volume_keys_init(int evm_id, int profile) 712 static void volume_keys_init(int evm_id, int profile)
717 { 713 {
718 int err; 714 int err;
719 715
720 setup_pin_mux(volume_keys_pin_mux); 716 setup_pin_mux(volume_keys_pin_mux);
721 err = platform_device_register(&am335x_evm_volume_keys); 717 err = platform_device_register(&am335x_evm_volume_keys);
722 if (err) 718 if (err)
723 pr_err("failed to register matrix keypad (2x3) device\n"); 719 pr_err("failed to register matrix keypad (2x3) device\n");
724 } 720 }
725 #endif 721 #endif
726 722
727 /* 723 /*
728 * @evm_id - evm id which needs to be configured 724 * @evm_id - evm id which needs to be configured
729 * @dev_cfg - single evm structure which includes 725 * @dev_cfg - single evm structure which includes
730 * all module inits, pin-mux defines 726 * all module inits, pin-mux defines
731 * @profile - if present, else PROFILE_NONE 727 * @profile - if present, else PROFILE_NONE
732 * @dghtr_brd_flg - Whether Daughter board is present or not 728 * @dghtr_brd_flg - Whether Daughter board is present or not
733 */ 729 */
734 static void _configure_device(int evm_id, struct evm_dev_cfg *dev_cfg, 730 static void _configure_device(int evm_id, struct evm_dev_cfg *dev_cfg,
735 int profile) 731 int profile)
736 { 732 {
737 int i; 733 int i;
738 734
739 /* 735 /*
740 * Only General Purpose & Industrial Auto Motro Control 736 * Only General Purpose & Industrial Auto Motro Control
741 * EVM has profiles. So check if this evm has profile. 737 * EVM has profiles. So check if this evm has profile.
742 * If not, ignore the profile comparison 738 * If not, ignore the profile comparison
743 */ 739 */
744 740
745 /* 741 /*
746 * If the device is on baseboard, directly configure it. Else (device on 742 * If the device is on baseboard, directly configure it. Else (device on
747 * Daughter board), check if the daughter card is detected. 743 * Daughter board), check if the daughter card is detected.
748 */ 744 */
749 if (profile == PROFILE_NONE) { 745 if (profile == PROFILE_NONE) {
750 for (i = 0; dev_cfg->device_init != NULL; dev_cfg++) { 746 for (i = 0; dev_cfg->device_init != NULL; dev_cfg++) {
751 if (dev_cfg->device_on == DEV_ON_BASEBOARD) 747 if (dev_cfg->device_on == DEV_ON_BASEBOARD)
752 dev_cfg->device_init(evm_id, profile); 748 dev_cfg->device_init(evm_id, profile);
753 else if (daughter_brd_detected == true) 749 else if (daughter_brd_detected == true)
754 dev_cfg->device_init(evm_id, profile); 750 dev_cfg->device_init(evm_id, profile);
755 } 751 }
756 } else { 752 } else {
757 for (i = 0; dev_cfg->device_init != NULL; dev_cfg++) { 753 for (i = 0; dev_cfg->device_init != NULL; dev_cfg++) {
758 if (dev_cfg->profile & profile) { 754 if (dev_cfg->profile & profile) {
759 if (dev_cfg->device_on == DEV_ON_BASEBOARD) 755 if (dev_cfg->device_on == DEV_ON_BASEBOARD)
760 dev_cfg->device_init(evm_id, profile); 756 dev_cfg->device_init(evm_id, profile);
761 else if (daughter_brd_detected == true) 757 else if (daughter_brd_detected == true)
762 dev_cfg->device_init(evm_id, profile); 758 dev_cfg->device_init(evm_id, profile);
763 } 759 }
764 } 760 }
765 } 761 }
766 } 762 }
767 763
768 #define AM335X_LCD_BL_PIN GPIO_TO_PIN(0, 7) 764 #define AM335X_LCD_BL_PIN GPIO_TO_PIN(0, 7)
769 765
770 /* pinmux for usb0 drvvbus */ 766 /* pinmux for usb0 drvvbus */
771 static struct pinmux_config usb0_pin_mux[] = { 767 static struct pinmux_config usb0_pin_mux[] = {
772 {"usb0_drvvbus.usb0_drvvbus", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, 768 {"usb0_drvvbus.usb0_drvvbus", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
773 {NULL, 0}, 769 {NULL, 0},
774 }; 770 };
775 771
776 /* pinmux for usb1 drvvbus */ 772 /* pinmux for usb1 drvvbus */
777 static struct pinmux_config usb1_pin_mux[] = { 773 static struct pinmux_config usb1_pin_mux[] = {
778 {"usb1_drvvbus.usb1_drvvbus", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, 774 {"usb1_drvvbus.usb1_drvvbus", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
779 {NULL, 0}, 775 {NULL, 0},
780 }; 776 };
781 777
782 /* pinmux for profibus */ 778 /* pinmux for profibus */
783 static struct pinmux_config profibus_pin_mux[] = { 779 static struct pinmux_config profibus_pin_mux[] = {
784 {"uart1_rxd.pr1_uart0_rxd_mux1", OMAP_MUX_MODE5 | AM33XX_PIN_INPUT}, 780 {"uart1_rxd.pr1_uart0_rxd_mux1", OMAP_MUX_MODE5 | AM33XX_PIN_INPUT},
785 {"uart1_txd.pr1_uart0_txd_mux1", OMAP_MUX_MODE5 | AM33XX_PIN_OUTPUT}, 781 {"uart1_txd.pr1_uart0_txd_mux1", OMAP_MUX_MODE5 | AM33XX_PIN_OUTPUT},
786 {"mcasp0_fsr.pr1_pru0_pru_r30_5", OMAP_MUX_MODE5 | AM33XX_PIN_OUTPUT}, 782 {"mcasp0_fsr.pr1_pru0_pru_r30_5", OMAP_MUX_MODE5 | AM33XX_PIN_OUTPUT},
787 {NULL, 0}, 783 {NULL, 0},
788 }; 784 };
789 785
790 /* Module pin mux for eCAP0 */ 786 /* Module pin mux for eCAP0 */
791 static struct pinmux_config ecap0_pin_mux[] = { 787 static struct pinmux_config ecap0_pin_mux[] = {
792 {"ecap0_in_pwm0_out.gpio0_7", AM33XX_PIN_OUTPUT}, 788 {"ecap0_in_pwm0_out.gpio0_7", AM33XX_PIN_OUTPUT},
793 {NULL, 0}, 789 {NULL, 0},
794 }; 790 };
795 791
796 #define AM335XEVM_WLAN_IRQ_GPIO GPIO_TO_PIN(3, 17) 792 #define AM335XEVM_WLAN_IRQ_GPIO GPIO_TO_PIN(3, 17)
797 793
798 struct wl12xx_platform_data am335xevm_wlan_data = { 794 struct wl12xx_platform_data am335xevm_wlan_data = {
799 .irq = OMAP_GPIO_IRQ(AM335XEVM_WLAN_IRQ_GPIO), 795 .irq = OMAP_GPIO_IRQ(AM335XEVM_WLAN_IRQ_GPIO),
800 .board_ref_clock = WL12XX_REFCLOCK_38_XTAL, /* 38.4Mhz */ 796 .board_ref_clock = WL12XX_REFCLOCK_38_XTAL, /* 38.4Mhz */
801 }; 797 };
802 798
803 /* Module pin mux for wlan and bluetooth */ 799 /* Module pin mux for wlan and bluetooth */
804 static struct pinmux_config mmc2_wl12xx_pin_mux[] = { 800 static struct pinmux_config mmc2_wl12xx_pin_mux[] = {
805 {"gpmc_a1.mmc2_dat0", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP}, 801 {"gpmc_a1.mmc2_dat0", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
806 {"gpmc_a2.mmc2_dat1", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP}, 802 {"gpmc_a2.mmc2_dat1", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
807 {"gpmc_a3.mmc2_dat2", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP}, 803 {"gpmc_a3.mmc2_dat2", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
808 {"gpmc_ben1.mmc2_dat3", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP}, 804 {"gpmc_ben1.mmc2_dat3", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
809 {"gpmc_csn3.mmc2_cmd", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP}, 805 {"gpmc_csn3.mmc2_cmd", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
810 {"gpmc_clk.mmc2_clk", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP}, 806 {"gpmc_clk.mmc2_clk", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
811 {NULL, 0}, 807 {NULL, 0},
812 }; 808 };
813 809
814 static struct pinmux_config uart1_wl12xx_pin_mux[] = { 810 static struct pinmux_config uart1_wl12xx_pin_mux[] = {
815 {"uart1_ctsn.uart1_ctsn", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, 811 {"uart1_ctsn.uart1_ctsn", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
816 {"uart1_rtsn.uart1_rtsn", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT}, 812 {"uart1_rtsn.uart1_rtsn", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT},
817 {"uart1_rxd.uart1_rxd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, 813 {"uart1_rxd.uart1_rxd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
818 {"uart1_txd.uart1_txd", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL}, 814 {"uart1_txd.uart1_txd", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL},
819 {NULL, 0}, 815 {NULL, 0},
820 }; 816 };
821 817
822 static struct pinmux_config wl12xx_pin_mux_evm_rev1_1a[] = { 818 static struct pinmux_config wl12xx_pin_mux_evm_rev1_1a[] = {
823 {"gpmc_a0.gpio1_16", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT}, 819 {"gpmc_a0.gpio1_16", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
824 {"mcasp0_ahclkr.gpio3_17", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT}, 820 {"mcasp0_ahclkr.gpio3_17", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
825 {"mcasp0_ahclkx.gpio3_21", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT}, 821 {"mcasp0_ahclkx.gpio3_21", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
826 {NULL, 0}, 822 {NULL, 0},
827 }; 823 };
828 824
829 static struct pinmux_config wl12xx_pin_mux_evm_rev1_0[] = { 825 static struct pinmux_config wl12xx_pin_mux_evm_rev1_0[] = {
830 {"gpmc_csn1.gpio1_30", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT}, 826 {"gpmc_csn1.gpio1_30", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
831 {"mcasp0_ahclkr.gpio3_17", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT}, 827 {"mcasp0_ahclkr.gpio3_17", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
832 {"gpmc_csn2.gpio1_31", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT}, 828 {"gpmc_csn2.gpio1_31", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
833 {NULL, 0}, 829 {NULL, 0},
834 }; 830 };
835 831
836 static int backlight_enable = false; 832 static int backlight_enable = false;
837 833
838 static void enable_ecap0(int evm_id, int profile) 834 static void enable_ecap0(int evm_id, int profile)
839 { 835 {
840 backlight_enable = true; 836 backlight_enable = true;
841 } 837 }
842 838
843 static int __init ecap0_init(void) 839 static int __init ecap0_init(void)
844 { 840 {
845 int status = 0; 841 int status = 0;
846 842
847 if (backlight_enable) { 843 if (backlight_enable) {
848 setup_pin_mux(ecap0_pin_mux); 844 setup_pin_mux(ecap0_pin_mux);
849 845
850 status = gpio_request(AM335X_LCD_BL_PIN, "lcd bl\n"); 846 status = gpio_request(AM335X_LCD_BL_PIN, "lcd bl\n");
851 if (status < 0) 847 if (status < 0)
852 pr_warn("Failed to request gpio for LCD backlight\n"); 848 pr_warn("Failed to request gpio for LCD backlight\n");
853 849
854 gpio_direction_output(AM335X_LCD_BL_PIN, 1); 850 gpio_direction_output(AM335X_LCD_BL_PIN, 1);
855 } 851 }
856 return status; 852 return status;
857 } 853 }
858 late_initcall(ecap0_init); 854 late_initcall(ecap0_init);
859 855
860 static int __init conf_disp_pll(int rate) 856 static int __init conf_disp_pll(int rate)
861 { 857 {
862 struct clk *disp_pll; 858 struct clk *disp_pll;
863 int ret = -EINVAL; 859 int ret = -EINVAL;
864 860
865 disp_pll = clk_get(NULL, "dpll_disp_ck"); 861 disp_pll = clk_get(NULL, "dpll_disp_ck");
866 if (IS_ERR(disp_pll)) { 862 if (IS_ERR(disp_pll)) {
867 pr_err("Cannot clk_get disp_pll\n"); 863 pr_err("Cannot clk_get disp_pll\n");
868 goto out; 864 goto out;
869 } 865 }
870 866
871 ret = clk_set_rate(disp_pll, rate); 867 ret = clk_set_rate(disp_pll, rate);
872 clk_put(disp_pll); 868 clk_put(disp_pll);
873 out: 869 out:
874 return ret; 870 return ret;
875 } 871 }
876 872
877 static void lcdc_init(int evm_id, int profile) 873 static void lcdc_init(int evm_id, int profile)
878 { 874 {
879 875
880 setup_pin_mux(lcdc_pin_mux); 876 setup_pin_mux(lcdc_pin_mux);
881 877
882 if (conf_disp_pll(300000000)) { 878 if (conf_disp_pll(300000000)) {
883 pr_info("Failed configure display PLL, not attempting to" 879 pr_info("Failed configure display PLL, not attempting to"
884 "register LCDC\n"); 880 "register LCDC\n");
885 return; 881 return;
886 } 882 }
887 883
888 if (am33xx_register_lcdc(&TFC_S9700RTWV35TR_01B_pdata)) 884 if (am33xx_register_lcdc(&TFC_S9700RTWV35TR_01B_pdata))
889 pr_info("Failed to register LCDC device\n"); 885 pr_info("Failed to register LCDC device\n");
890 return; 886 return;
891 } 887 }
892 888
893 static void tsc_init(int evm_id, int profile) 889 static void tsc_init(int evm_id, int profile)
894 { 890 {
895 int err; 891 int err;
896 892
897 if (gp_evm_revision == GP_EVM_REV_IS_1_1A) { 893 if (gp_evm_revision == GP_EVM_REV_IS_1_1A) {
898 am335x_touchscreen_data.analog_input = 1; 894 am335x_touchscreen_data.analog_input = 1;
899 pr_info("TSC connected to beta GP EVM\n"); 895 pr_info("TSC connected to beta GP EVM\n");
900 } else { 896 } else {
901 am335x_touchscreen_data.analog_input = 0; 897 am335x_touchscreen_data.analog_input = 0;
902 pr_info("TSC connected to alpha GP EVM\n"); 898 pr_info("TSC connected to alpha GP EVM\n");
903 } 899 }
904 setup_pin_mux(tsc_pin_mux); 900 setup_pin_mux(tsc_pin_mux);
905 err = platform_device_register(&tsc_device); 901 err = platform_device_register(&tsc_device);
906 if (err) 902 if (err)
907 pr_err("failed to register touchscreen device\n"); 903 pr_err("failed to register touchscreen device\n");
908 } 904 }
909 905
910 static void rgmii1_init(int evm_id, int profile) 906 static void rgmii1_init(int evm_id, int profile)
911 { 907 {
912 setup_pin_mux(rgmii1_pin_mux); 908 setup_pin_mux(rgmii1_pin_mux);
913 return; 909 return;
914 } 910 }
915 911
916 static void rgmii2_init(int evm_id, int profile) 912 static void rgmii2_init(int evm_id, int profile)
917 { 913 {
918 setup_pin_mux(rgmii2_pin_mux); 914 setup_pin_mux(rgmii2_pin_mux);
919 return; 915 return;
920 } 916 }
921 917
922 static void mii1_init(int evm_id, int profile) 918 static void mii1_init(int evm_id, int profile)
923 { 919 {
924 setup_pin_mux(mii1_pin_mux); 920 setup_pin_mux(mii1_pin_mux);
925 return; 921 return;
926 } 922 }
927 923
928 static void rmii1_init(int evm_id, int profile) 924 static void rmii1_init(int evm_id, int profile)
929 { 925 {
930 setup_pin_mux(rmii1_pin_mux); 926 setup_pin_mux(rmii1_pin_mux);
931 return; 927 return;
932 } 928 }
933 929
934 static void usb0_init(int evm_id, int profile) 930 static void usb0_init(int evm_id, int profile)
935 { 931 {
936 setup_pin_mux(usb0_pin_mux); 932 setup_pin_mux(usb0_pin_mux);
937 return; 933 return;
938 } 934 }
939 935
940 static void usb1_init(int evm_id, int profile) 936 static void usb1_init(int evm_id, int profile)
941 { 937 {
942 setup_pin_mux(usb1_pin_mux); 938 setup_pin_mux(usb1_pin_mux);
943 return; 939 return;
944 } 940 }
945 941
946 /* setup uart3 */ 942 /* setup uart3 */
947 static void uart3_init(int evm_id, int profile) 943 static void uart3_init(int evm_id, int profile)
948 { 944 {
949 setup_pin_mux(uart3_pin_mux); 945 setup_pin_mux(uart3_pin_mux);
950 return; 946 return;
951 } 947 }
952 948
953 /* NAND partition information */ 949 /* NAND partition information */
954 static struct mtd_partition am335x_nand_partitions[] = { 950 static struct mtd_partition am335x_nand_partitions[] = {
955 /* All the partition sizes are listed in terms of NAND block size */ 951 /* All the partition sizes are listed in terms of NAND block size */
956 { 952 {
957 .name = "SPL", 953 .name = "SPL",
958 .offset = 0, /* Offset = 0x0 */ 954 .offset = 0, /* Offset = 0x0 */
959 .size = SZ_128K, 955 .size = SZ_128K,
960 }, 956 },
961 { 957 {
962 .name = "SPL.backup1", 958 .name = "SPL.backup1",
963 .offset = MTDPART_OFS_APPEND, /* Offset = 0x20000 */ 959 .offset = MTDPART_OFS_APPEND, /* Offset = 0x20000 */
964 .size = SZ_128K, 960 .size = SZ_128K,
965 }, 961 },
966 { 962 {
967 .name = "SPL.backup2", 963 .name = "SPL.backup2",
968 .offset = MTDPART_OFS_APPEND, /* Offset = 0x40000 */ 964 .offset = MTDPART_OFS_APPEND, /* Offset = 0x40000 */
969 .size = SZ_128K, 965 .size = SZ_128K,
970 }, 966 },
971 { 967 {
972 .name = "SPL.backup3", 968 .name = "SPL.backup3",
973 .offset = MTDPART_OFS_APPEND, /* Offset = 0x60000 */ 969 .offset = MTDPART_OFS_APPEND, /* Offset = 0x60000 */
974 .size = SZ_128K, 970 .size = SZ_128K,
975 }, 971 },
976 { 972 {
977 .name = "U-Boot", 973 .name = "U-Boot",
978 .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */ 974 .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */
979 .size = 15 * SZ_128K, 975 .size = 15 * SZ_128K,
980 }, 976 },
981 { 977 {
982 .name = "U-Boot Env", 978 .name = "U-Boot Env",
983 .offset = MTDPART_OFS_APPEND, /* Offset = 0x260000 */ 979 .offset = MTDPART_OFS_APPEND, /* Offset = 0x260000 */
984 .size = 1 * SZ_128K, 980 .size = 1 * SZ_128K,
985 }, 981 },
986 { 982 {
987 .name = "Kernel", 983 .name = "Kernel",
988 .offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */ 984 .offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */
989 .size = 40 * SZ_128K, 985 .size = 40 * SZ_128K,
990 }, 986 },
991 { 987 {
992 .name = "File System", 988 .name = "File System",
993 .offset = MTDPART_OFS_APPEND, /* Offset = 0x780000 */ 989 .offset = MTDPART_OFS_APPEND, /* Offset = 0x780000 */
994 .size = MTDPART_SIZ_FULL, 990 .size = MTDPART_SIZ_FULL,
995 }, 991 },
996 }; 992 };
997 993
998 /* SPI 0/1 Platform Data */ 994 /* SPI 0/1 Platform Data */
999 /* SPI flash information */ 995 /* SPI flash information */
1000 static struct mtd_partition am335x_spi_partitions[] = { 996 static struct mtd_partition am335x_spi_partitions[] = {
1001 /* All the partition sizes are listed in terms of erase size */ 997 /* All the partition sizes are listed in terms of erase size */
1002 { 998 {
1003 .name = "U-Boot-min", 999 .name = "U-Boot-min",
1004 .offset = 0, 1000 .offset = 0,
1005 .size = SZ_128K, 1001 .size = SZ_128K,
1006 .mask_flags = MTD_WRITEABLE, /* force read-only */ 1002 .mask_flags = MTD_WRITEABLE, /* force read-only */
1007 }, 1003 },
1008 { 1004 {
1009 .name = "U-Boot", 1005 .name = "U-Boot",
1010 .offset = MTDPART_OFS_APPEND, 1006 .offset = MTDPART_OFS_APPEND,
1011 .size = 2 * SZ_128K, 1007 .size = 2 * SZ_128K,
1012 .mask_flags = MTD_WRITEABLE, /* force read-only */ 1008 .mask_flags = MTD_WRITEABLE, /* force read-only */
1013 }, 1009 },
1014 { 1010 {
1015 .name = "U-Boot Env", 1011 .name = "U-Boot Env",
1016 .offset = MTDPART_OFS_APPEND, 1012 .offset = MTDPART_OFS_APPEND,
1017 .size = 2 * SZ_4K, 1013 .size = 2 * SZ_4K,
1018 }, 1014 },
1019 { 1015 {
1020 .name = "Kernel", 1016 .name = "Kernel",
1021 .offset = MTDPART_OFS_APPEND, 1017 .offset = MTDPART_OFS_APPEND,
1022 .size = 28 * SZ_128K, 1018 .size = 28 * SZ_128K,
1023 }, 1019 },
1024 { 1020 {
1025 .name = "File System", 1021 .name = "File System",
1026 .offset = MTDPART_OFS_APPEND, 1022 .offset = MTDPART_OFS_APPEND,
1027 .size = MTDPART_SIZ_FULL, /* size ~= 1.1 MiB */ 1023 .size = MTDPART_SIZ_FULL, /* size ~= 1.1 MiB */
1028 } 1024 }
1029 }; 1025 };
1030 1026
1031 static const struct flash_platform_data am335x_spi_flash = { 1027 static const struct flash_platform_data am335x_spi_flash = {
1032 .type = "w25q64", 1028 .type = "w25q64",
1033 .name = "spi_flash", 1029 .name = "spi_flash",
1034 .parts = am335x_spi_partitions, 1030 .parts = am335x_spi_partitions,
1035 .nr_parts = ARRAY_SIZE(am335x_spi_partitions), 1031 .nr_parts = ARRAY_SIZE(am335x_spi_partitions),
1036 }; 1032 };
1037 1033
1038 /* 1034 /*
1039 * SPI Flash works at 80Mhz however SPI Controller works at 48MHz. 1035 * SPI Flash works at 80Mhz however SPI Controller works at 48MHz.
1040 * So setup Max speed to be less than that of Controller speed 1036 * So setup Max speed to be less than that of Controller speed
1041 */ 1037 */
1042 static struct spi_board_info am335x_spi0_slave_info[] = { 1038 static struct spi_board_info am335x_spi0_slave_info[] = {
1043 { 1039 {
1044 .modalias = "m25p80", 1040 .modalias = "m25p80",
1045 .platform_data = &am335x_spi_flash, 1041 .platform_data = &am335x_spi_flash,
1046 .irq = -1, 1042 .irq = -1,
1047 .max_speed_hz = 24000000, 1043 .max_speed_hz = 24000000,
1048 .bus_num = 1, 1044 .bus_num = 1,
1049 .chip_select = 0, 1045 .chip_select = 0,
1050 }, 1046 },
1051 }; 1047 };
1052 1048
1053 static struct spi_board_info am335x_spi1_slave_info[] = { 1049 static struct spi_board_info am335x_spi1_slave_info[] = {
1054 { 1050 {
1055 .modalias = "m25p80", 1051 .modalias = "m25p80",
1056 .platform_data = &am335x_spi_flash, 1052 .platform_data = &am335x_spi_flash,
1057 .irq = -1, 1053 .irq = -1,
1058 .max_speed_hz = 12000000, 1054 .max_speed_hz = 12000000,
1059 .bus_num = 2, 1055 .bus_num = 2,
1060 .chip_select = 0, 1056 .chip_select = 0,
1061 }, 1057 },
1062 }; 1058 };
1063 1059
1064 static void evm_nand_init(int evm_id, int profile) 1060 static void evm_nand_init(int evm_id, int profile)
1065 { 1061 {
1066 setup_pin_mux(nand_pin_mux); 1062 setup_pin_mux(nand_pin_mux);
1067 board_nand_init(am335x_nand_partitions, 1063 board_nand_init(am335x_nand_partitions,
1068 ARRAY_SIZE(am335x_nand_partitions), 0, 0); 1064 ARRAY_SIZE(am335x_nand_partitions), 0, 0);
1069 } 1065 }
1070 1066
1071 static struct lis3lv02d_platform_data lis331dlh_pdata = { 1067 static struct lis3lv02d_platform_data lis331dlh_pdata = {
1072 .click_flags = LIS3_CLICK_SINGLE_X | 1068 .click_flags = LIS3_CLICK_SINGLE_X |
1073 LIS3_CLICK_SINGLE_Y | 1069 LIS3_CLICK_SINGLE_Y |
1074 LIS3_CLICK_SINGLE_Z, 1070 LIS3_CLICK_SINGLE_Z,
1075 .wakeup_flags = LIS3_WAKEUP_X_LO | LIS3_WAKEUP_X_HI | 1071 .wakeup_flags = LIS3_WAKEUP_X_LO | LIS3_WAKEUP_X_HI |
1076 LIS3_WAKEUP_Y_LO | LIS3_WAKEUP_Y_HI | 1072 LIS3_WAKEUP_Y_LO | LIS3_WAKEUP_Y_HI |
1077 LIS3_WAKEUP_Z_LO | LIS3_WAKEUP_Z_HI, 1073 LIS3_WAKEUP_Z_LO | LIS3_WAKEUP_Z_HI,
1078 .irq_cfg = LIS3_IRQ1_CLICK | LIS3_IRQ2_CLICK, 1074 .irq_cfg = LIS3_IRQ1_CLICK | LIS3_IRQ2_CLICK,
1079 .wakeup_thresh = 10, 1075 .wakeup_thresh = 10,
1080 .click_thresh_x = 10, 1076 .click_thresh_x = 10,
1081 .click_thresh_y = 10, 1077 .click_thresh_y = 10,
1082 .click_thresh_z = 10, 1078 .click_thresh_z = 10,
1083 .g_range = 2, 1079 .g_range = 2,
1084 .st_min_limits[0] = 120, 1080 .st_min_limits[0] = 120,
1085 .st_min_limits[1] = 120, 1081 .st_min_limits[1] = 120,
1086 .st_min_limits[2] = 140, 1082 .st_min_limits[2] = 140,
1087 .st_max_limits[0] = 550, 1083 .st_max_limits[0] = 550,
1088 .st_max_limits[1] = 550, 1084 .st_max_limits[1] = 550,
1089 .st_max_limits[2] = 750, 1085 .st_max_limits[2] = 750,
1090 }; 1086 };
1091 1087
1092 static struct i2c_board_info am335x_i2c_boardinfo1[] = { 1088 static struct i2c_board_info am335x_i2c_boardinfo1[] = {
1093 { 1089 {
1094 I2C_BOARD_INFO("tlv320aic3x", 0x1b), 1090 I2C_BOARD_INFO("tlv320aic3x", 0x1b),
1095 }, 1091 },
1096 { 1092 {
1097 I2C_BOARD_INFO("lis331dlh", 0x18), 1093 I2C_BOARD_INFO("lis331dlh", 0x18),
1098 .platform_data = &lis331dlh_pdata, 1094 .platform_data = &lis331dlh_pdata,
1099 }, 1095 },
1100 { 1096 {
1101 I2C_BOARD_INFO("tsl2550", 0x39), 1097 I2C_BOARD_INFO("tsl2550", 0x39),
1102 }, 1098 },
1103 { 1099 {
1104 I2C_BOARD_INFO("tmp275", 0x48), 1100 I2C_BOARD_INFO("tmp275", 0x48),
1105 }, 1101 },
1106 }; 1102 };
1107 1103
1108 static void i2c1_init(int evm_id, int profile) 1104 static void i2c1_init(int evm_id, int profile)
1109 { 1105 {
1110 setup_pin_mux(i2c1_pin_mux); 1106 setup_pin_mux(i2c1_pin_mux);
1111 omap_register_i2c_bus(2, 100, am335x_i2c_boardinfo1, 1107 omap_register_i2c_bus(2, 100, am335x_i2c_boardinfo1,
1112 ARRAY_SIZE(am335x_i2c_boardinfo1)); 1108 ARRAY_SIZE(am335x_i2c_boardinfo1));
1113 return; 1109 return;
1114 } 1110 }
1115 1111
1116 /* Setup McASP 1 */ 1112 /* Setup McASP 1 */
1117 static void mcasp1_init(int evm_id, int profile) 1113 static void mcasp1_init(int evm_id, int profile)
1118 { 1114 {
1119 /* Configure McASP */ 1115 /* Configure McASP */
1120 setup_pin_mux(mcasp1_pin_mux); 1116 setup_pin_mux(mcasp1_pin_mux);
1121 am335x_register_mcasp1(&am335x_evm_snd_data1); 1117 am335x_register_mcasp1(&am335x_evm_snd_data1);
1122 return; 1118 return;
1123 } 1119 }
1124 1120
1125 static void mmc1_init(int evm_id, int profile) 1121 static void mmc1_init(int evm_id, int profile)
1126 { 1122 {
1127 setup_pin_mux(mmc1_pin_mux); 1123 setup_pin_mux(mmc1_pin_mux);
1128 1124
1129 am335x_mmc[1].mmc = 2; 1125 am335x_mmc[1].mmc = 2;
1130 am335x_mmc[1].caps = MMC_CAP_4_BIT_DATA; 1126 am335x_mmc[1].caps = MMC_CAP_4_BIT_DATA;
1131 am335x_mmc[1].gpio_cd = GPIO_TO_PIN(3, 15); 1127 am335x_mmc[1].gpio_cd = GPIO_TO_PIN(3, 15);
1132 am335x_mmc[1].gpio_wp = GPIO_TO_PIN(0, 14); 1128 am335x_mmc[1].gpio_wp = GPIO_TO_PIN(0, 14);
1133 am335x_mmc[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */ 1129 am335x_mmc[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */
1134 1130
1135 /* mmc will be initialized when mmc0_init is called */ 1131 /* mmc will be initialized when mmc0_init is called */
1136 return; 1132 return;
1137 } 1133 }
1138 1134
1139 static void mmc2_wl12xx_init(int evm_id, int profile) 1135 static void mmc2_wl12xx_init(int evm_id, int profile)
1140 { 1136 {
1141 setup_pin_mux(mmc2_wl12xx_pin_mux); 1137 setup_pin_mux(mmc2_wl12xx_pin_mux);
1142 1138
1143 am335x_mmc[1].mmc = 3; 1139 am335x_mmc[1].mmc = 3;
1144 am335x_mmc[1].name = "wl1271"; 1140 am335x_mmc[1].name = "wl1271";
1145 am335x_mmc[1].caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD 1141 am335x_mmc[1].caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD
1146 | MMC_PM_KEEP_POWER; 1142 | MMC_PM_KEEP_POWER;
1147 am335x_mmc[1].nonremovable = true; 1143 am335x_mmc[1].nonremovable = true;
1148 am335x_mmc[1].gpio_cd = -EINVAL; 1144 am335x_mmc[1].gpio_cd = -EINVAL;
1149 am335x_mmc[1].gpio_wp = -EINVAL; 1145 am335x_mmc[1].gpio_wp = -EINVAL;
1150 am335x_mmc[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */ 1146 am335x_mmc[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */
1151 1147
1152 /* mmc will be initialized when mmc0_init is called */ 1148 /* mmc will be initialized when mmc0_init is called */
1153 return; 1149 return;
1154 } 1150 }
1155 1151
1156 static void uart1_wl12xx_init(int evm_id, int profile) 1152 static void uart1_wl12xx_init(int evm_id, int profile)
1157 { 1153 {
1158 setup_pin_mux(uart1_wl12xx_pin_mux); 1154 setup_pin_mux(uart1_wl12xx_pin_mux);
1159 } 1155 }
1160 1156
1161 static void wl12xx_bluetooth_enable(void) 1157 static void wl12xx_bluetooth_enable(void)
1162 { 1158 {
1163 int status = gpio_request(am335xevm_wlan_data.bt_enable_gpio, 1159 int status = gpio_request(am335xevm_wlan_data.bt_enable_gpio,
1164 "bt_en\n"); 1160 "bt_en\n");
1165 if (status < 0) 1161 if (status < 0)
1166 pr_err("Failed to request gpio for bt_enable"); 1162 pr_err("Failed to request gpio for bt_enable");
1167 1163
1168 pr_info("Configure Bluetooth Enable pin...\n"); 1164 pr_info("Configure Bluetooth Enable pin...\n");
1169 gpio_direction_output(am335xevm_wlan_data.bt_enable_gpio, 0); 1165 gpio_direction_output(am335xevm_wlan_data.bt_enable_gpio, 0);
1170 } 1166 }
1171 1167
1172 static int wl12xx_set_power(struct device *dev, int slot, int on, int vdd) 1168 static int wl12xx_set_power(struct device *dev, int slot, int on, int vdd)
1173 { 1169 {
1174 if (on) { 1170 if (on) {
1175 gpio_set_value(am335xevm_wlan_data.wlan_enable_gpio, 1); 1171 gpio_set_value(am335xevm_wlan_data.wlan_enable_gpio, 1);
1176 mdelay(70); 1172 mdelay(70);
1177 } 1173 }
1178 else 1174 else
1179 gpio_set_value(am335xevm_wlan_data.wlan_enable_gpio, 0); 1175 gpio_set_value(am335xevm_wlan_data.wlan_enable_gpio, 0);
1180 1176
1181 return 0; 1177 return 0;
1182 } 1178 }
1183 1179
1184 static void wl12xx_init(int evm_id, int profile) 1180 static void wl12xx_init(int evm_id, int profile)
1185 { 1181 {
1186 struct device *dev; 1182 struct device *dev;
1187 struct omap_mmc_platform_data *pdata; 1183 struct omap_mmc_platform_data *pdata;
1188 int ret; 1184 int ret;
1189 1185
1190 /* Register WLAN and BT enable pins based on the evm board revision */ 1186 /* Register WLAN and BT enable pins based on the evm board revision */
1191 if (gp_evm_revision == GP_EVM_REV_IS_1_1A) { 1187 if (gp_evm_revision == GP_EVM_REV_IS_1_1A) {
1192 am335xevm_wlan_data.wlan_enable_gpio = GPIO_TO_PIN(1, 16); 1188 am335xevm_wlan_data.wlan_enable_gpio = GPIO_TO_PIN(1, 16);
1193 am335xevm_wlan_data.bt_enable_gpio = GPIO_TO_PIN(3, 21); 1189 am335xevm_wlan_data.bt_enable_gpio = GPIO_TO_PIN(3, 21);
1194 } 1190 }
1195 else { 1191 else {
1196 am335xevm_wlan_data.wlan_enable_gpio = GPIO_TO_PIN(1, 30); 1192 am335xevm_wlan_data.wlan_enable_gpio = GPIO_TO_PIN(1, 30);
1197 am335xevm_wlan_data.bt_enable_gpio = GPIO_TO_PIN(1, 31); 1193 am335xevm_wlan_data.bt_enable_gpio = GPIO_TO_PIN(1, 31);
1198 } 1194 }
1199 1195
1200 wl12xx_bluetooth_enable(); 1196 wl12xx_bluetooth_enable();
1201 1197
1202 if (wl12xx_set_platform_data(&am335xevm_wlan_data)) 1198 if (wl12xx_set_platform_data(&am335xevm_wlan_data))
1203 pr_err("error setting wl12xx data\n"); 1199 pr_err("error setting wl12xx data\n");
1204 1200
1205 dev = am335x_mmc[1].dev; 1201 dev = am335x_mmc[1].dev;
1206 if (!dev) { 1202 if (!dev) {
1207 pr_err("wl12xx mmc device initialization failed\n"); 1203 pr_err("wl12xx mmc device initialization failed\n");
1208 goto out; 1204 goto out;
1209 } 1205 }
1210 1206
1211 pdata = dev->platform_data; 1207 pdata = dev->platform_data;
1212 if (!pdata) { 1208 if (!pdata) {
1213 pr_err("Platfrom data of wl12xx device not set\n"); 1209 pr_err("Platfrom data of wl12xx device not set\n");
1214 goto out; 1210 goto out;
1215 } 1211 }
1216 1212
1217 ret = gpio_request_one(am335xevm_wlan_data.wlan_enable_gpio, 1213 ret = gpio_request_one(am335xevm_wlan_data.wlan_enable_gpio,
1218 GPIOF_OUT_INIT_LOW, "wlan_en"); 1214 GPIOF_OUT_INIT_LOW, "wlan_en");
1219 if (ret) { 1215 if (ret) {
1220 pr_err("Error requesting wlan enable gpio: %d\n", ret); 1216 pr_err("Error requesting wlan enable gpio: %d\n", ret);
1221 goto out; 1217 goto out;
1222 } 1218 }
1223 1219
1224 if (gp_evm_revision == GP_EVM_REV_IS_1_1A) 1220 if (gp_evm_revision == GP_EVM_REV_IS_1_1A)
1225 setup_pin_mux(wl12xx_pin_mux_evm_rev1_1a); 1221 setup_pin_mux(wl12xx_pin_mux_evm_rev1_1a);
1226 else 1222 else
1227 setup_pin_mux(wl12xx_pin_mux_evm_rev1_0); 1223 setup_pin_mux(wl12xx_pin_mux_evm_rev1_0);
1228 1224
1229 pdata->slots[0].set_power = wl12xx_set_power; 1225 pdata->slots[0].set_power = wl12xx_set_power;
1230 out: 1226 out:
1231 return; 1227 return;
1232 } 1228 }
1233 1229
1234 static void d_can_init(int evm_id, int profile) 1230 static void d_can_init(int evm_id, int profile)
1235 { 1231 {
1236 switch (evm_id) { 1232 switch (evm_id) {
1237 case IND_AUT_MTR_EVM: 1233 case IND_AUT_MTR_EVM:
1238 if ((profile == PROFILE_0) || (profile == PROFILE_1)) { 1234 if ((profile == PROFILE_0) || (profile == PROFILE_1)) {
1239 setup_pin_mux(d_can_ia_pin_mux); 1235 setup_pin_mux(d_can_ia_pin_mux);
1240 /* Instance Zero */ 1236 /* Instance Zero */
1241 am33xx_d_can_init(0); 1237 am33xx_d_can_init(0);
1242 } 1238 }
1243 break; 1239 break;
1244 case GEN_PURP_EVM: 1240 case GEN_PURP_EVM:
1245 if (profile == PROFILE_1) { 1241 if (profile == PROFILE_1) {
1246 setup_pin_mux(d_can_gp_pin_mux); 1242 setup_pin_mux(d_can_gp_pin_mux);
1247 /* Instance One */ 1243 /* Instance One */
1248 am33xx_d_can_init(1); 1244 am33xx_d_can_init(1);
1249 } 1245 }
1250 break; 1246 break;
1251 default: 1247 default:
1252 break; 1248 break;
1253 } 1249 }
1254 } 1250 }
1255 1251
1256 static void mmc0_init(int evm_id, int profile) 1252 static void mmc0_init(int evm_id, int profile)
1257 { 1253 {
1258 setup_pin_mux(mmc0_pin_mux); 1254 setup_pin_mux(mmc0_pin_mux);
1259 1255
1260 omap2_hsmmc_init(am335x_mmc); 1256 omap2_hsmmc_init(am335x_mmc);
1261 return; 1257 return;
1262 } 1258 }
1263 1259
1264 static void mmc0_no_cd_init(int evm_id, int profile) 1260 static void mmc0_no_cd_init(int evm_id, int profile)
1265 { 1261 {
1266 setup_pin_mux(mmc0_no_cd_pin_mux); 1262 setup_pin_mux(mmc0_no_cd_pin_mux);
1267 1263
1268 omap2_hsmmc_init(am335x_mmc); 1264 omap2_hsmmc_init(am335x_mmc);
1269 return; 1265 return;
1270 } 1266 }
1271 1267
1272 1268
1273 /* setup spi0 */ 1269 /* setup spi0 */
1274 static void spi0_init(int evm_id, int profile) 1270 static void spi0_init(int evm_id, int profile)
1275 { 1271 {
1276 setup_pin_mux(spi0_pin_mux); 1272 setup_pin_mux(spi0_pin_mux);
1277 spi_register_board_info(am335x_spi0_slave_info, 1273 spi_register_board_info(am335x_spi0_slave_info,
1278 ARRAY_SIZE(am335x_spi0_slave_info)); 1274 ARRAY_SIZE(am335x_spi0_slave_info));
1279 return; 1275 return;
1280 } 1276 }
1281 1277
1282 /* setup spi1 */ 1278 /* setup spi1 */
1283 static void spi1_init(int evm_id, int profile) 1279 static void spi1_init(int evm_id, int profile)
1284 { 1280 {
1285 setup_pin_mux(spi1_pin_mux); 1281 setup_pin_mux(spi1_pin_mux);
1286 spi_register_board_info(am335x_spi1_slave_info, 1282 spi_register_board_info(am335x_spi1_slave_info,
1287 ARRAY_SIZE(am335x_spi1_slave_info)); 1283 ARRAY_SIZE(am335x_spi1_slave_info));
1288 return; 1284 return;
1289 } 1285 }
1290 1286
1291 1287
1292 static int beaglebone_phy_fixup(struct phy_device *phydev) 1288 static int beaglebone_phy_fixup(struct phy_device *phydev)
1293 { 1289 {
1294 phydev->supported &= ~(SUPPORTED_100baseT_Half | 1290 phydev->supported &= ~(SUPPORTED_100baseT_Half |
1295 SUPPORTED_100baseT_Full); 1291 SUPPORTED_100baseT_Full);
1296 1292
1297 return 0; 1293 return 0;
1298 } 1294 }
1299 1295
1300 #ifdef CONFIG_TLK110_WORKAROUND 1296 #ifdef CONFIG_TLK110_WORKAROUND
1301 static int am335x_tlk110_phy_fixup(struct phy_device *phydev) 1297 static int am335x_tlk110_phy_fixup(struct phy_device *phydev)
1302 { 1298 {
1303 unsigned int val; 1299 unsigned int val;
1304 1300
1305 /* This is done as a workaround to support TLK110 rev1.0 phy */ 1301 /* This is done as a workaround to support TLK110 rev1.0 phy */
1306 val = phy_read(phydev, TLK110_COARSEGAIN_REG); 1302 val = phy_read(phydev, TLK110_COARSEGAIN_REG);
1307 phy_write(phydev, TLK110_COARSEGAIN_REG, (val | TLK110_COARSEGAIN_VAL)); 1303 phy_write(phydev, TLK110_COARSEGAIN_REG, (val | TLK110_COARSEGAIN_VAL));
1308 1304
1309 val = phy_read(phydev, TLK110_LPFHPF_REG); 1305 val = phy_read(phydev, TLK110_LPFHPF_REG);
1310 phy_write(phydev, TLK110_LPFHPF_REG, (val | TLK110_LPFHPF_VAL)); 1306 phy_write(phydev, TLK110_LPFHPF_REG, (val | TLK110_LPFHPF_VAL));
1311 1307
1312 val = phy_read(phydev, TLK110_SPAREANALOG_REG); 1308 val = phy_read(phydev, TLK110_SPAREANALOG_REG);
1313 phy_write(phydev, TLK110_SPAREANALOG_REG, (val | TLK110_SPANALOG_VAL)); 1309 phy_write(phydev, TLK110_SPAREANALOG_REG, (val | TLK110_SPANALOG_VAL));
1314 1310
1315 val = phy_read(phydev, TLK110_VRCR_REG); 1311 val = phy_read(phydev, TLK110_VRCR_REG);
1316 phy_write(phydev, TLK110_VRCR_REG, (val | TLK110_VRCR_VAL)); 1312 phy_write(phydev, TLK110_VRCR_REG, (val | TLK110_VRCR_VAL));
1317 1313
1318 val = phy_read(phydev, TLK110_SETFFE_REG); 1314 val = phy_read(phydev, TLK110_SETFFE_REG);
1319 phy_write(phydev, TLK110_SETFFE_REG, (val | TLK110_SETFFE_VAL)); 1315 phy_write(phydev, TLK110_SETFFE_REG, (val | TLK110_SETFFE_VAL));
1320 1316
1321 val = phy_read(phydev, TLK110_FTSP_REG); 1317 val = phy_read(phydev, TLK110_FTSP_REG);
1322 phy_write(phydev, TLK110_FTSP_REG, (val | TLK110_FTSP_VAL)); 1318 phy_write(phydev, TLK110_FTSP_REG, (val | TLK110_FTSP_VAL));
1323 1319
1324 val = phy_read(phydev, TLK110_ALFATPIDL_REG); 1320 val = phy_read(phydev, TLK110_ALFATPIDL_REG);
1325 phy_write(phydev, TLK110_ALFATPIDL_REG, (val | TLK110_ALFATPIDL_VAL)); 1321 phy_write(phydev, TLK110_ALFATPIDL_REG, (val | TLK110_ALFATPIDL_VAL));
1326 1322
1327 val = phy_read(phydev, TLK110_PSCOEF21_REG); 1323 val = phy_read(phydev, TLK110_PSCOEF21_REG);
1328 phy_write(phydev, TLK110_PSCOEF21_REG, (val | TLK110_PSCOEF21_VAL)); 1324 phy_write(phydev, TLK110_PSCOEF21_REG, (val | TLK110_PSCOEF21_VAL));
1329 1325
1330 val = phy_read(phydev, TLK110_PSCOEF3_REG); 1326 val = phy_read(phydev, TLK110_PSCOEF3_REG);
1331 phy_write(phydev, TLK110_PSCOEF3_REG, (val | TLK110_PSCOEF3_VAL)); 1327 phy_write(phydev, TLK110_PSCOEF3_REG, (val | TLK110_PSCOEF3_VAL));
1332 1328
1333 val = phy_read(phydev, TLK110_ALFAFACTOR1_REG); 1329 val = phy_read(phydev, TLK110_ALFAFACTOR1_REG);
1334 phy_write(phydev, TLK110_ALFAFACTOR1_REG, (val | TLK110_ALFACTOR1_VAL)); 1330 phy_write(phydev, TLK110_ALFAFACTOR1_REG, (val | TLK110_ALFACTOR1_VAL));
1335 1331
1336 val = phy_read(phydev, TLK110_ALFAFACTOR2_REG); 1332 val = phy_read(phydev, TLK110_ALFAFACTOR2_REG);
1337 phy_write(phydev, TLK110_ALFAFACTOR2_REG, (val | TLK110_ALFACTOR2_VAL)); 1333 phy_write(phydev, TLK110_ALFAFACTOR2_REG, (val | TLK110_ALFACTOR2_VAL));
1338 1334
1339 val = phy_read(phydev, TLK110_CFGPS_REG); 1335 val = phy_read(phydev, TLK110_CFGPS_REG);
1340 phy_write(phydev, TLK110_CFGPS_REG, (val | TLK110_CFGPS_VAL)); 1336 phy_write(phydev, TLK110_CFGPS_REG, (val | TLK110_CFGPS_VAL));
1341 1337
1342 val = phy_read(phydev, TLK110_FTSPTXGAIN_REG); 1338 val = phy_read(phydev, TLK110_FTSPTXGAIN_REG);
1343 phy_write(phydev, TLK110_FTSPTXGAIN_REG, (val | TLK110_FTSPTXGAIN_VAL)); 1339 phy_write(phydev, TLK110_FTSPTXGAIN_REG, (val | TLK110_FTSPTXGAIN_VAL));
1344 1340
1345 val = phy_read(phydev, TLK110_SWSCR3_REG); 1341 val = phy_read(phydev, TLK110_SWSCR3_REG);
1346 phy_write(phydev, TLK110_SWSCR3_REG, (val | TLK110_SWSCR3_VAL)); 1342 phy_write(phydev, TLK110_SWSCR3_REG, (val | TLK110_SWSCR3_VAL));
1347 1343
1348 val = phy_read(phydev, TLK110_SCFALLBACK_REG); 1344 val = phy_read(phydev, TLK110_SCFALLBACK_REG);
1349 phy_write(phydev, TLK110_SCFALLBACK_REG, (val | TLK110_SCFALLBACK_VAL)); 1345 phy_write(phydev, TLK110_SCFALLBACK_REG, (val | TLK110_SCFALLBACK_VAL));
1350 1346
1351 val = phy_read(phydev, TLK110_PHYRCR_REG); 1347 val = phy_read(phydev, TLK110_PHYRCR_REG);
1352 phy_write(phydev, TLK110_PHYRCR_REG, (val | TLK110_PHYRCR_VAL)); 1348 phy_write(phydev, TLK110_PHYRCR_REG, (val | TLK110_PHYRCR_VAL));
1353 1349
1354 return 0; 1350 return 0;
1355 } 1351 }
1356 #endif 1352 #endif
1357 1353
1358 static void profibus_init(int evm_id, int profile) 1354 static void profibus_init(int evm_id, int profile)
1359 { 1355 {
1360 setup_pin_mux(profibus_pin_mux); 1356 setup_pin_mux(profibus_pin_mux);
1361 return; 1357 return;
1362 } 1358 }
1363 1359
1364 /* Low-Cost EVM */ 1360 /* Low-Cost EVM */
1365 static struct evm_dev_cfg low_cost_evm_dev_cfg[] = { 1361 static struct evm_dev_cfg low_cost_evm_dev_cfg[] = {
1366 {rgmii1_init, DEV_ON_BASEBOARD, PROFILE_NONE}, 1362 {rgmii1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1367 {usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE}, 1363 {usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1368 {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE}, 1364 {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1369 {evm_nand_init, DEV_ON_BASEBOARD, PROFILE_NONE}, 1365 {evm_nand_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1370 {NULL, 0, 0}, 1366 {NULL, 0, 0},
1371 }; 1367 };
1372 1368
1373 /* General Purpose EVM */ 1369 /* General Purpose EVM */
1374 static struct evm_dev_cfg gen_purp_evm_dev_cfg[] = { 1370 static struct evm_dev_cfg gen_purp_evm_dev_cfg[] = {
1375 {enable_ecap0, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 | 1371 {enable_ecap0, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 |
1376 PROFILE_2 | PROFILE_7) }, 1372 PROFILE_2 | PROFILE_7) },
1377 {lcdc_init, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 | 1373 {lcdc_init, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 |
1378 PROFILE_2 | PROFILE_7) }, 1374 PROFILE_2 | PROFILE_7) },
1379 {tsc_init, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 | 1375 {tsc_init, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 |
1380 PROFILE_2 | PROFILE_7) }, 1376 PROFILE_2 | PROFILE_7) },
1381 {rgmii1_init, DEV_ON_BASEBOARD, PROFILE_ALL}, 1377 {rgmii1_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1382 {rgmii2_init, DEV_ON_DGHTR_BRD, (PROFILE_1 | PROFILE_2 | 1378 {rgmii2_init, DEV_ON_DGHTR_BRD, (PROFILE_1 | PROFILE_2 |
1383 PROFILE_4 | PROFILE_6) }, 1379 PROFILE_4 | PROFILE_6) },
1384 {usb0_init, DEV_ON_BASEBOARD, PROFILE_ALL}, 1380 {usb0_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1385 {usb1_init, DEV_ON_BASEBOARD, PROFILE_ALL}, 1381 {usb1_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1386 {evm_nand_init, DEV_ON_DGHTR_BRD, 1382 {evm_nand_init, DEV_ON_DGHTR_BRD,
1387 (PROFILE_ALL & ~PROFILE_2 & ~PROFILE_3)}, 1383 (PROFILE_ALL & ~PROFILE_2 & ~PROFILE_3)},
1388 {i2c1_init, DEV_ON_DGHTR_BRD, (PROFILE_ALL & ~PROFILE_2)}, 1384 {i2c1_init, DEV_ON_DGHTR_BRD, (PROFILE_ALL & ~PROFILE_2)},
1389 {mcasp1_init, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_3 | PROFILE_7) }, 1385 {mcasp1_init, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_3 | PROFILE_7) },
1390 {mmc1_init, DEV_ON_DGHTR_BRD, PROFILE_2}, 1386 {mmc1_init, DEV_ON_DGHTR_BRD, PROFILE_2},
1391 {mmc2_wl12xx_init, DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 | 1387 {mmc2_wl12xx_init, DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 |
1392 PROFILE_5)}, 1388 PROFILE_5)},
1393 {mmc0_init, DEV_ON_BASEBOARD, (PROFILE_ALL & ~PROFILE_5)}, 1389 {mmc0_init, DEV_ON_BASEBOARD, (PROFILE_ALL & ~PROFILE_5)},
1394 {mmc0_no_cd_init, DEV_ON_BASEBOARD, PROFILE_5}, 1390 {mmc0_no_cd_init, DEV_ON_BASEBOARD, PROFILE_5},
1395 {spi0_init, DEV_ON_DGHTR_BRD, PROFILE_2}, 1391 {spi0_init, DEV_ON_DGHTR_BRD, PROFILE_2},
1396 {uart1_wl12xx_init, DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 | 1392 {uart1_wl12xx_init, DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 |
1397 PROFILE_5)}, 1393 PROFILE_5)},
1398 {wl12xx_init, DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 | PROFILE_5)}, 1394 {wl12xx_init, DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 | PROFILE_5)},
1399 {d_can_init, DEV_ON_DGHTR_BRD, PROFILE_1}, 1395 {d_can_init, DEV_ON_DGHTR_BRD, PROFILE_1},
1400 #ifdef CONFIG_KEYBOARD_MATRIX 1396 #ifdef CONFIG_KEYBOARD_MATRIX
1401 {matrix_keypad_init, DEV_ON_DGHTR_BRD, PROFILE_0}, 1397 {matrix_keypad_init, DEV_ON_DGHTR_BRD, PROFILE_0},
1402 #endif 1398 #endif
1403 #ifdef CONFIG_KEYBOARD_GPIO 1399 #ifdef CONFIG_KEYBOARD_GPIO
1404 {volume_keys_init, DEV_ON_DGHTR_BRD, PROFILE_0}, 1400 {volume_keys_init, DEV_ON_DGHTR_BRD, PROFILE_0},
1405 #endif 1401 #endif
1406 {NULL, 0, 0}, 1402 {NULL, 0, 0},
1407 }; 1403 };
1408 1404
1409 /* Industrial Auto Motor Control EVM */ 1405 /* Industrial Auto Motor Control EVM */
1410 static struct evm_dev_cfg ind_auto_mtrl_evm_dev_cfg[] = { 1406 static struct evm_dev_cfg ind_auto_mtrl_evm_dev_cfg[] = {
1411 {mii1_init, DEV_ON_DGHTR_BRD, PROFILE_ALL}, 1407 {mii1_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
1412 {usb0_init, DEV_ON_BASEBOARD, PROFILE_ALL}, 1408 {usb0_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1413 {usb1_init, DEV_ON_BASEBOARD, PROFILE_ALL}, 1409 {usb1_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1414 {profibus_init, DEV_ON_DGHTR_BRD, PROFILE_ALL}, 1410 {profibus_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
1415 {evm_nand_init, DEV_ON_DGHTR_BRD, PROFILE_ALL}, 1411 {evm_nand_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
1416 {spi1_init, DEV_ON_DGHTR_BRD, PROFILE_ALL}, 1412 {spi1_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
1417 {uart3_init, DEV_ON_DGHTR_BRD, PROFILE_ALL}, 1413 {uart3_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
1418 {i2c1_init, DEV_ON_BASEBOARD, PROFILE_ALL}, 1414 {i2c1_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1419 {mmc0_no_cd_init, DEV_ON_BASEBOARD, PROFILE_ALL}, 1415 {mmc0_no_cd_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1420 {NULL, 0, 0}, 1416 {NULL, 0, 0},
1421 }; 1417 };
1422 1418
1423 /* IP-Phone EVM */ 1419 /* IP-Phone EVM */
1424 static struct evm_dev_cfg ip_phn_evm_dev_cfg[] = { 1420 static struct evm_dev_cfg ip_phn_evm_dev_cfg[] = {
1425 {enable_ecap0, DEV_ON_DGHTR_BRD, PROFILE_NONE}, 1421 {enable_ecap0, DEV_ON_DGHTR_BRD, PROFILE_NONE},
1426 {lcdc_init, DEV_ON_DGHTR_BRD, PROFILE_NONE}, 1422 {lcdc_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
1427 {tsc_init, DEV_ON_DGHTR_BRD, PROFILE_NONE}, 1423 {tsc_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
1428 {rgmii1_init, DEV_ON_BASEBOARD, PROFILE_NONE}, 1424 {rgmii1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1429 {rgmii2_init, DEV_ON_DGHTR_BRD, PROFILE_NONE}, 1425 {rgmii2_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
1430 {usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE}, 1426 {usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1431 {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE}, 1427 {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1432 {evm_nand_init, DEV_ON_DGHTR_BRD, PROFILE_NONE}, 1428 {evm_nand_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
1433 {i2c1_init, DEV_ON_BASEBOARD, PROFILE_NONE}, 1429 {i2c1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1434 {mcasp1_init, DEV_ON_DGHTR_BRD, PROFILE_NONE}, 1430 {mcasp1_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
1435 {mmc0_init, DEV_ON_BASEBOARD, PROFILE_NONE}, 1431 {mmc0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1436 {NULL, 0, 0}, 1432 {NULL, 0, 0},
1437 }; 1433 };
1438 1434
1439 /* Beaglebone < Rev A3 */ 1435 /* Beaglebone < Rev A3 */
1440 static struct evm_dev_cfg beaglebone_old_dev_cfg[] = { 1436 static struct evm_dev_cfg beaglebone_old_dev_cfg[] = {
1441 {rmii1_init, DEV_ON_BASEBOARD, PROFILE_NONE}, 1437 {rmii1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1442 {usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE}, 1438 {usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1443 {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE}, 1439 {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1444 {mmc0_init, DEV_ON_BASEBOARD, PROFILE_NONE}, 1440 {mmc0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1445 {NULL, 0, 0}, 1441 {NULL, 0, 0},
1446 }; 1442 };
1447 1443
1448 /* Beaglebone Rev A3 and after */ 1444 /* Beaglebone Rev A3 and after */
1449 static struct evm_dev_cfg beaglebone_dev_cfg[] = { 1445 static struct evm_dev_cfg beaglebone_dev_cfg[] = {
1450 {mii1_init, DEV_ON_BASEBOARD, PROFILE_NONE}, 1446 {mii1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1451 {usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE}, 1447 {usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1452 {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE}, 1448 {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1453 {mmc0_init, DEV_ON_BASEBOARD, PROFILE_NONE}, 1449 {mmc0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1454 {NULL, 0, 0}, 1450 {NULL, 0, 0},
1455 }; 1451 };
1456 1452
1457 static void setup_low_cost_evm(void) 1453 static void setup_low_cost_evm(void)
1458 { 1454 {
1459 pr_info("The board is a AM335x Low Cost EVM.\n"); 1455 pr_info("The board is a AM335x Low Cost EVM.\n");
1460 1456
1461 _configure_device(LOW_COST_EVM, low_cost_evm_dev_cfg, PROFILE_NONE); 1457 _configure_device(LOW_COST_EVM, low_cost_evm_dev_cfg, PROFILE_NONE);
1462 } 1458 }
1463 1459
1464 static void setup_general_purpose_evm(void) 1460 static void setup_general_purpose_evm(void)
1465 { 1461 {
1466 u32 prof_sel = am335x_get_profile_selection(); 1462 u32 prof_sel = am335x_get_profile_selection();
1467 pr_info("The board is general purpose EVM in profile %d\n", prof_sel); 1463 pr_info("The board is general purpose EVM in profile %d\n", prof_sel);
1468 1464
1469 if (!strncmp("1.1A", config.version, 4)) { 1465 if (!strncmp("1.1A", config.version, 4)) {
1470 gp_evm_revision = GP_EVM_REV_IS_1_1A; 1466 gp_evm_revision = GP_EVM_REV_IS_1_1A;
1471 } else if (!strncmp("1.0", config.version, 3)) { 1467 } else if (!strncmp("1.0", config.version, 3)) {
1472 gp_evm_revision = GP_EVM_REV_IS_1_0; 1468 gp_evm_revision = GP_EVM_REV_IS_1_0;
1473 } else { 1469 } else {
1474 pr_err("Found invalid GP EVM revision, falling back to Rev1.1A"); 1470 pr_err("Found invalid GP EVM revision, falling back to Rev1.1A");
1475 gp_evm_revision = GP_EVM_REV_IS_1_1A; 1471 gp_evm_revision = GP_EVM_REV_IS_1_1A;
1476 } 1472 }
1477 1473
1478 if (gp_evm_revision == GP_EVM_REV_IS_1_0) 1474 if (gp_evm_revision == GP_EVM_REV_IS_1_0)
1479 gigabit_enable = 0; 1475 gigabit_enable = 0;
1480 else if (gp_evm_revision == GP_EVM_REV_IS_1_1A) 1476 else if (gp_evm_revision == GP_EVM_REV_IS_1_1A)
1481 gigabit_enable = 1; 1477 gigabit_enable = 1;
1482 1478
1483 _configure_device(GEN_PURP_EVM, gen_purp_evm_dev_cfg, (1L << prof_sel)); 1479 _configure_device(GEN_PURP_EVM, gen_purp_evm_dev_cfg, (1L << prof_sel));
1484 } 1480 }
1485 1481
1486 static void setup_ind_auto_motor_ctrl_evm(void) 1482 static void setup_ind_auto_motor_ctrl_evm(void)
1487 { 1483 {
1488 u32 prof_sel = am335x_get_profile_selection(); 1484 u32 prof_sel = am335x_get_profile_selection();
1489 1485
1490 pr_info("The board is an industrial automation EVM in profile %d\n", 1486 pr_info("The board is an industrial automation EVM in profile %d\n",
1491 prof_sel); 1487 prof_sel);
1492 1488
1493 /* Only Profile 0 is supported */ 1489 /* Only Profile 0 is supported */
1494 if ((1L << prof_sel) != PROFILE_0) { 1490 if ((1L << prof_sel) != PROFILE_0) {
1495 pr_err("AM335X: Only Profile 0 is supported\n"); 1491 pr_err("AM335X: Only Profile 0 is supported\n");
1496 pr_err("Assuming profile 0 & continuing\n"); 1492 pr_err("Assuming profile 0 & continuing\n");
1497 prof_sel = PROFILE_0; 1493 prof_sel = PROFILE_0;
1498 } 1494 }
1499 1495
1500 _configure_device(IND_AUT_MTR_EVM, ind_auto_mtrl_evm_dev_cfg, 1496 _configure_device(IND_AUT_MTR_EVM, ind_auto_mtrl_evm_dev_cfg,
1501 PROFILE_0); 1497 PROFILE_0);
1502 1498
1503 /* Fillup global evmid */ 1499 /* Fillup global evmid */
1504 am33xx_evmid_fillup(IND_AUT_MTR_EVM); 1500 am33xx_evmid_fillup(IND_AUT_MTR_EVM);
1505 1501
1506 /* Initialize TLK110 PHY registers for phy version 1.0 */ 1502 /* Initialize TLK110 PHY registers for phy version 1.0 */
1507 am335x_tlk110_phy_init(); 1503 am335x_tlk110_phy_init();
1508 1504
1509 1505
1510 } 1506 }
1511 1507
1512 static void setup_ip_phone_evm(void) 1508 static void setup_ip_phone_evm(void)
1513 { 1509 {
1514 pr_info("The board is an IP phone EVM\n"); 1510 pr_info("The board is an IP phone EVM\n");
1515 1511
1516 _configure_device(IP_PHN_EVM, ip_phn_evm_dev_cfg, PROFILE_NONE); 1512 _configure_device(IP_PHN_EVM, ip_phn_evm_dev_cfg, PROFILE_NONE);
1517 } 1513 }
1518 1514
1519 /* BeagleBone < Rev A3 */ 1515 /* BeagleBone < Rev A3 */
1520 static void setup_beaglebone_old(void) 1516 static void setup_beaglebone_old(void)
1521 { 1517 {
1522 pr_info("The board is a AM335x Beaglebone < Rev A3.\n"); 1518 pr_info("The board is a AM335x Beaglebone < Rev A3.\n");
1523 1519
1524 /* Beagle Bone has Micro-SD slot which doesn't have Write Protect pin */ 1520 /* Beagle Bone has Micro-SD slot which doesn't have Write Protect pin */
1525 am335x_mmc[0].gpio_wp = -EINVAL; 1521 am335x_mmc[0].gpio_wp = -EINVAL;
1526 1522
1527 _configure_device(LOW_COST_EVM, beaglebone_old_dev_cfg, PROFILE_NONE); 1523 _configure_device(LOW_COST_EVM, beaglebone_old_dev_cfg, PROFILE_NONE);
1528 1524
1529 phy_register_fixup_for_uid(BBB_PHY_ID, BBB_PHY_MASK, 1525 phy_register_fixup_for_uid(BBB_PHY_ID, BBB_PHY_MASK,
1530 beaglebone_phy_fixup); 1526 beaglebone_phy_fixup);
1531 } 1527 }
1532 1528
1533 /* BeagleBone after Rev A3 */ 1529 /* BeagleBone after Rev A3 */
1534 static void setup_beaglebone(void) 1530 static void setup_beaglebone(void)
1535 { 1531 {
1536 pr_info("The board is a AM335x Beaglebone.\n"); 1532 pr_info("The board is a AM335x Beaglebone.\n");
1537 1533
1538 /* Beagle Bone has Micro-SD slot which doesn't have Write Protect pin */ 1534 /* Beagle Bone has Micro-SD slot which doesn't have Write Protect pin */
1539 am335x_mmc[0].gpio_wp = -EINVAL; 1535 am335x_mmc[0].gpio_wp = -EINVAL;
1540 1536
1541 _configure_device(LOW_COST_EVM, beaglebone_dev_cfg, PROFILE_NONE); 1537 _configure_device(LOW_COST_EVM, beaglebone_dev_cfg, PROFILE_NONE);
1542 } 1538 }
1543 1539
1544 1540
1545 static void am335x_setup_daughter_board(struct memory_accessor *m, void *c) 1541 static void am335x_setup_daughter_board(struct memory_accessor *m, void *c)
1546 { 1542 {
1547 u8 tmp; 1543 u8 tmp;
1548 int ret; 1544 int ret;
1549 1545
1550 /* 1546 /*
1551 * try reading a byte from the EEPROM to see if it is 1547 * try reading a byte from the EEPROM to see if it is
1552 * present. We could read a lot more, but that would 1548 * present. We could read a lot more, but that would
1553 * just slow the boot process and we have all the information 1549 * just slow the boot process and we have all the information
1554 * we need from the EEPROM on the base board anyway. 1550 * we need from the EEPROM on the base board anyway.
1555 */ 1551 */
1556 ret = m->read(m, &tmp, 0, sizeof(u8)); 1552 ret = m->read(m, &tmp, 0, sizeof(u8));
1557 if (ret == sizeof(u8)) { 1553 if (ret == sizeof(u8)) {
1558 pr_info("Detected a daughter card on AM335x EVM.."); 1554 pr_info("Detected a daughter card on AM335x EVM..");
1559 daughter_brd_detected = true; 1555 daughter_brd_detected = true;
1560 } else { 1556 } else {
1561 pr_info("No daughter card found\n"); 1557 pr_info("No daughter card found\n");
1562 daughter_brd_detected = false; 1558 daughter_brd_detected = false;
1563 } 1559 }
1564 } 1560 }
1565 1561
1566 static void am335x_evm_setup(struct memory_accessor *mem_acc, void *context) 1562 static void am335x_evm_setup(struct memory_accessor *mem_acc, void *context)
1567 { 1563 {
1568 int ret; 1564 int ret;
1569 char tmp[10]; 1565 char tmp[10];
1570 1566
1571 /* 1st get the MAC address from EEPROM */ 1567 /* 1st get the MAC address from EEPROM */
1572 ret = mem_acc->read(mem_acc, (char *)&am335x_mac_addr, 1568 ret = mem_acc->read(mem_acc, (char *)&am335x_mac_addr,
1573 EEPROM_MAC_ADDRESS_OFFSET, sizeof(am335x_mac_addr)); 1569 EEPROM_MAC_ADDRESS_OFFSET, sizeof(am335x_mac_addr));
1574 1570
1575 if (ret != sizeof(am335x_mac_addr)) { 1571 if (ret != sizeof(am335x_mac_addr)) {
1576 pr_warning("AM335X: EVM Config read fail: %d\n", ret); 1572 pr_warning("AM335X: EVM Config read fail: %d\n", ret);
1577 return; 1573 return;
1578 } 1574 }
1579 1575
1580 /* Fillup global mac id */ 1576 /* Fillup global mac id */
1581 am33xx_cpsw_macidfillup(&am335x_mac_addr[0][0], 1577 am33xx_cpsw_macidfillup(&am335x_mac_addr[0][0],
1582 &am335x_mac_addr[1][0]); 1578 &am335x_mac_addr[1][0]);
1583 1579
1584 /* get board specific data */ 1580 /* get board specific data */
1585 ret = mem_acc->read(mem_acc, (char *)&config, 0, sizeof(config)); 1581 ret = mem_acc->read(mem_acc, (char *)&config, 0, sizeof(config));
1586 if (ret != sizeof(config)) { 1582 if (ret != sizeof(config)) {
1587 pr_warning("AM335X EVM config read fail, read %d bytes\n", ret); 1583 pr_warning("AM335X EVM config read fail, read %d bytes\n", ret);
1588 return; 1584 return;
1589 } 1585 }
1590 1586
1591 if (config.header != AM335X_EEPROM_HEADER) { 1587 if (config.header != AM335X_EEPROM_HEADER) {
1592 pr_warning("AM335X: wrong header 0x%x, expected 0x%x\n", 1588 pr_warning("AM335X: wrong header 0x%x, expected 0x%x\n",
1593 config.header, AM335X_EEPROM_HEADER); 1589 config.header, AM335X_EEPROM_HEADER);
1594 goto out; 1590 goto out;
1595 } 1591 }
1596 1592
1597 if (strncmp("A335", config.name, 4)) { 1593 if (strncmp("A335", config.name, 4)) {
1598 pr_err("Board %s doesn't look like an AM335x board\n", 1594 pr_err("Board %s doesn't look like an AM335x board\n",
1599 config.name); 1595 config.name);
1600 goto out; 1596 goto out;
1601 } 1597 }
1602 1598
1603 snprintf(tmp, sizeof(config.name) + 1, "%s", config.name); 1599 snprintf(tmp, sizeof(config.name) + 1, "%s", config.name);
1604 pr_info("Board name: %s\n", tmp); 1600 pr_info("Board name: %s\n", tmp);
1605 snprintf(tmp, sizeof(config.version) + 1, "%s", config.version); 1601 snprintf(tmp, sizeof(config.version) + 1, "%s", config.version);
1606 pr_info("Board version: %s\n", tmp); 1602 pr_info("Board version: %s\n", tmp);
1607 1603
1608 if (!strncmp("A335BONE", config.name, 8)) { 1604 if (!strncmp("A335BONE", config.name, 8)) {
1609 daughter_brd_detected = false; 1605 daughter_brd_detected = false;
1610 if(!strncmp("00A1", config.version, 4) || 1606 if(!strncmp("00A1", config.version, 4) ||
1611 !strncmp("00A2", config.version, 4)) 1607 !strncmp("00A2", config.version, 4))
1612 setup_beaglebone_old(); 1608 setup_beaglebone_old();
1613 else 1609 else
1614 setup_beaglebone(); 1610 setup_beaglebone();
1615 } else { 1611 } else {
1616 /* only 6 characters of options string used for now */ 1612 /* only 6 characters of options string used for now */
1617 snprintf(tmp, 7, "%s", config.opt); 1613 snprintf(tmp, 7, "%s", config.opt);
1618 pr_info("SKU: %s\n", tmp); 1614 pr_info("SKU: %s\n", tmp);
1619 1615
1620 if (!strncmp("SKU#00", config.opt, 6)) 1616 if (!strncmp("SKU#00", config.opt, 6))
1621 setup_low_cost_evm(); 1617 setup_low_cost_evm();
1622 else if (!strncmp("SKU#01", config.opt, 6)) 1618 else if (!strncmp("SKU#01", config.opt, 6))
1623 setup_general_purpose_evm(); 1619 setup_general_purpose_evm();
1624 else if (!strncmp("SKU#02", config.opt, 6)) 1620 else if (!strncmp("SKU#02", config.opt, 6))
1625 setup_ind_auto_motor_ctrl_evm(); 1621 setup_ind_auto_motor_ctrl_evm();
1626 else if (!strncmp("SKU#03", config.opt, 6)) 1622 else if (!strncmp("SKU#03", config.opt, 6))
1627 setup_ip_phone_evm(); 1623 setup_ip_phone_evm();
1628 else 1624 else
1629 goto out; 1625 goto out;
1630 } 1626 }
1631 /* Initialize cpsw after board detection is completed as board 1627 /* Initialize cpsw after board detection is completed as board
1632 * information is required for configuring phy address and hence 1628 * information is required for configuring phy address and hence
1633 * should be call only after board detection 1629 * should be call only after board detection
1634 */ 1630 */
1635 am33xx_cpsw_init(gigabit_enable); 1631 am33xx_cpsw_init(gigabit_enable);
1636 1632
1637 return; 1633 return;
1638 out: 1634 out:
1639 /* 1635 /*
1640 * If the EEPROM hasn't been programed or an incorrect header 1636 * If the EEPROM hasn't been programed or an incorrect header
1641 * or board name are read, assume this is an old beaglebone board 1637 * or board name are read, assume this is an old beaglebone board
1642 * (< Rev A3) 1638 * (< Rev A3)
1643 */ 1639 */
1644 pr_err("Could not detect any board, falling back to: " 1640 pr_err("Could not detect any board, falling back to: "
1645 "Beaglebone (< Rev A3) with no daughter card connected\n"); 1641 "Beaglebone (< Rev A3) with no daughter card connected\n");
1646 daughter_brd_detected = false; 1642 daughter_brd_detected = false;
1647 setup_beaglebone_old(); 1643 setup_beaglebone_old();
1648 1644
1649 /* Initialize cpsw after board detection is completed as board 1645 /* Initialize cpsw after board detection is completed as board
1650 * information is required for configuring phy address and hence 1646 * information is required for configuring phy address and hence
1651 * should be call only after board detection 1647 * should be call only after board detection
1652 */ 1648 */
1653 1649
1654 am33xx_cpsw_init(gigabit_enable); 1650 am33xx_cpsw_init(gigabit_enable);
1655 } 1651 }
1656 1652
1657 static struct at24_platform_data am335x_daughter_board_eeprom_info = { 1653 static struct at24_platform_data am335x_daughter_board_eeprom_info = {
1658 .byte_len = (256*1024) / 8, 1654 .byte_len = (256*1024) / 8,
1659 .page_size = 64, 1655 .page_size = 64,
1660 .flags = AT24_FLAG_ADDR16, 1656 .flags = AT24_FLAG_ADDR16,
1661 .setup = am335x_setup_daughter_board, 1657 .setup = am335x_setup_daughter_board,
1662 .context = (void *)NULL, 1658 .context = (void *)NULL,
1663 }; 1659 };
1664 1660
1665 static struct at24_platform_data am335x_baseboard_eeprom_info = { 1661 static struct at24_platform_data am335x_baseboard_eeprom_info = {
1666 .byte_len = (256*1024) / 8, 1662 .byte_len = (256*1024) / 8,
1667 .page_size = 64, 1663 .page_size = 64,
1668 .flags = AT24_FLAG_ADDR16, 1664 .flags = AT24_FLAG_ADDR16,
1669 .setup = am335x_evm_setup, 1665 .setup = am335x_evm_setup,
1670 .context = (void *)NULL, 1666 .context = (void *)NULL,
1671 }; 1667 };
1672 1668
1673 static struct regulator_init_data am335x_dummy; 1669 static struct regulator_init_data am335x_dummy;
1674 1670
1675 static struct regulator_consumer_supply am335x_vdd1_supply[] = { 1671 static struct regulator_consumer_supply am335x_vdd1_supply[] = {
1676 REGULATOR_SUPPLY("mpu", "mpu.0"), 1672 REGULATOR_SUPPLY("mpu", "mpu.0"),
1677 }; 1673 };
1678 1674
1679 static struct regulator_init_data am335x_vdd1 = { 1675 static struct regulator_init_data am335x_vdd1 = {
1680 .constraints = { 1676 .constraints = {
1681 .min_uV = 600000, 1677 .min_uV = 600000,
1682 .max_uV = 1500000, 1678 .max_uV = 1500000,
1683 .valid_modes_mask = REGULATOR_MODE_NORMAL, 1679 .valid_modes_mask = REGULATOR_MODE_NORMAL,
1684 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, 1680 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
1685 .always_on = 1, 1681 .always_on = 1,
1686 }, 1682 },
1687 .num_consumer_supplies = ARRAY_SIZE(am335x_vdd1_supply), 1683 .num_consumer_supplies = ARRAY_SIZE(am335x_vdd1_supply),
1688 .consumer_supplies = am335x_vdd1_supply, 1684 .consumer_supplies = am335x_vdd1_supply,
1689 }; 1685 };
1690 1686
1691 static struct tps65910_board am335x_tps65910_info = { 1687 static struct tps65910_board am335x_tps65910_info = {
1692 .tps65910_pmic_init_data[TPS65910_REG_VRTC] = &am335x_dummy, 1688 .tps65910_pmic_init_data[TPS65910_REG_VRTC] = &am335x_dummy,
1693 .tps65910_pmic_init_data[TPS65910_REG_VIO] = &am335x_dummy, 1689 .tps65910_pmic_init_data[TPS65910_REG_VIO] = &am335x_dummy,
1694 .tps65910_pmic_init_data[TPS65910_REG_VDD1] = &am335x_vdd1, 1690 .tps65910_pmic_init_data[TPS65910_REG_VDD1] = &am335x_vdd1,
1695 .tps65910_pmic_init_data[TPS65910_REG_VDD2] = &am335x_dummy, 1691 .tps65910_pmic_init_data[TPS65910_REG_VDD2] = &am335x_dummy,
1696 .tps65910_pmic_init_data[TPS65910_REG_VDD3] = &am335x_dummy, 1692 .tps65910_pmic_init_data[TPS65910_REG_VDD3] = &am335x_dummy,
1697 .tps65910_pmic_init_data[TPS65910_REG_VDIG1] = &am335x_dummy, 1693 .tps65910_pmic_init_data[TPS65910_REG_VDIG1] = &am335x_dummy,
1698 .tps65910_pmic_init_data[TPS65910_REG_VDIG2] = &am335x_dummy, 1694 .tps65910_pmic_init_data[TPS65910_REG_VDIG2] = &am335x_dummy,
1699 .tps65910_pmic_init_data[TPS65910_REG_VPLL] = &am335x_dummy, 1695 .tps65910_pmic_init_data[TPS65910_REG_VPLL] = &am335x_dummy,
1700 .tps65910_pmic_init_data[TPS65910_REG_VDAC] = &am335x_dummy, 1696 .tps65910_pmic_init_data[TPS65910_REG_VDAC] = &am335x_dummy,
1701 .tps65910_pmic_init_data[TPS65910_REG_VAUX1] = &am335x_dummy, 1697 .tps65910_pmic_init_data[TPS65910_REG_VAUX1] = &am335x_dummy,
1702 .tps65910_pmic_init_data[TPS65910_REG_VAUX2] = &am335x_dummy, 1698 .tps65910_pmic_init_data[TPS65910_REG_VAUX2] = &am335x_dummy,
1703 .tps65910_pmic_init_data[TPS65910_REG_VAUX33] = &am335x_dummy, 1699 .tps65910_pmic_init_data[TPS65910_REG_VAUX33] = &am335x_dummy,
1704 .tps65910_pmic_init_data[TPS65910_REG_VMMC] = &am335x_dummy, 1700 .tps65910_pmic_init_data[TPS65910_REG_VMMC] = &am335x_dummy,
1705 }; 1701 };
1706 1702
1707 /* 1703 /*
1708 * Daughter board Detection. 1704 * Daughter board Detection.
1709 * Every board has a ID memory (EEPROM) on board. We probe these devices at 1705 * Every board has a ID memory (EEPROM) on board. We probe these devices at
1710 * machine init, starting from daughter board and ending with baseboard. 1706 * machine init, starting from daughter board and ending with baseboard.
1711 * Assumptions : 1707 * Assumptions :
1712 * 1. probe for i2c devices are called in the order they are included in 1708 * 1. probe for i2c devices are called in the order they are included in
1713 * the below struct. Daughter boards eeprom are probed 1st. Baseboard 1709 * the below struct. Daughter boards eeprom are probed 1st. Baseboard
1714 * eeprom probe is called last. 1710 * eeprom probe is called last.
1715 */ 1711 */
1716 static struct i2c_board_info __initdata am335x_i2c_boardinfo[] = { 1712 static struct i2c_board_info __initdata am335x_i2c_boardinfo[] = {
1717 { 1713 {
1718 /* Daughter Board EEPROM */ 1714 /* Daughter Board EEPROM */
1719 I2C_BOARD_INFO("24c256", DAUG_BOARD_I2C_ADDR), 1715 I2C_BOARD_INFO("24c256", DAUG_BOARD_I2C_ADDR),
1720 .platform_data = &am335x_daughter_board_eeprom_info, 1716 .platform_data = &am335x_daughter_board_eeprom_info,
1721 }, 1717 },
1722 { 1718 {
1723 /* Baseboard board EEPROM */ 1719 /* Baseboard board EEPROM */
1724 I2C_BOARD_INFO("24c256", BASEBOARD_I2C_ADDR), 1720 I2C_BOARD_INFO("24c256", BASEBOARD_I2C_ADDR),
1725 .platform_data = &am335x_baseboard_eeprom_info, 1721 .platform_data = &am335x_baseboard_eeprom_info,
1726 }, 1722 },
1727 { 1723 {
1728 I2C_BOARD_INFO("cpld_reg", 0x35), 1724 I2C_BOARD_INFO("cpld_reg", 0x35),
1729 }, 1725 },
1730 { 1726 {
1731 I2C_BOARD_INFO("tlc59108", 0x40), 1727 I2C_BOARD_INFO("tlc59108", 0x40),
1732 }, 1728 },
1733 { 1729 {
1734 I2C_BOARD_INFO("tps65910", TPS65910_I2C_ID1), 1730 I2C_BOARD_INFO("tps65910", TPS65910_I2C_ID1),
1735 .platform_data = &am335x_tps65910_info, 1731 .platform_data = &am335x_tps65910_info,
1736 }, 1732 },
1737 1733
1738 }; 1734 };
1739 1735
1740 static struct omap_musb_board_data musb_board_data = { 1736 static struct omap_musb_board_data musb_board_data = {
1741 .interface_type = MUSB_INTERFACE_ULPI, 1737 .interface_type = MUSB_INTERFACE_ULPI,
1742 .mode = MUSB_OTG, 1738 .mode = MUSB_OTG,
1743 .power = 500, 1739 .power = 500,
1744 .instances = 1, 1740 .instances = 1,
1745 }; 1741 };
1746 1742
1747 static int cpld_reg_probe(struct i2c_client *client, 1743 static int cpld_reg_probe(struct i2c_client *client,
1748 const struct i2c_device_id *id) 1744 const struct i2c_device_id *id)
1749 { 1745 {
1750 cpld_client = client; 1746 cpld_client = client;
1751 return 0; 1747 return 0;
1752 } 1748 }
1753 1749
1754 static int __devexit cpld_reg_remove(struct i2c_client *client) 1750 static int __devexit cpld_reg_remove(struct i2c_client *client)
1755 { 1751 {
1756 cpld_client = NULL; 1752 cpld_client = NULL;
1757 return 0; 1753 return 0;
1758 } 1754 }
1759 1755
1760 static const struct i2c_device_id cpld_reg_id[] = { 1756 static const struct i2c_device_id cpld_reg_id[] = {
1761 { "cpld_reg", 0 }, 1757 { "cpld_reg", 0 },
1762 { } 1758 { }
1763 }; 1759 };
1764 1760
1765 static struct i2c_driver cpld_reg_driver = { 1761 static struct i2c_driver cpld_reg_driver = {
1766 .driver = { 1762 .driver = {
1767 .name = "cpld_reg", 1763 .name = "cpld_reg",
1768 }, 1764 },
1769 .probe = cpld_reg_probe, 1765 .probe = cpld_reg_probe,
1770 .remove = cpld_reg_remove, 1766 .remove = cpld_reg_remove,
1771 .id_table = cpld_reg_id, 1767 .id_table = cpld_reg_id,
1772 }; 1768 };
1773 1769
1774 static void evm_init_cpld(void) 1770 static void evm_init_cpld(void)
1775 { 1771 {
1776 i2c_add_driver(&cpld_reg_driver); 1772 i2c_add_driver(&cpld_reg_driver);
1777 } 1773 }
1778 1774
1779 static void __init am335x_evm_i2c_init(void) 1775 static void __init am335x_evm_i2c_init(void)
1780 { 1776 {
1781 /* Initially assume Low Cost EVM Config */ 1777 /* Initially assume Low Cost EVM Config */
1782 am335x_evm_id = LOW_COST_EVM; 1778 am335x_evm_id = LOW_COST_EVM;
1783 1779
1784 evm_init_cpld(); 1780 evm_init_cpld();
1785 1781
1786 omap_register_i2c_bus(1, 100, am335x_i2c_boardinfo, 1782 omap_register_i2c_bus(1, 100, am335x_i2c_boardinfo,
1787 ARRAY_SIZE(am335x_i2c_boardinfo)); 1783 ARRAY_SIZE(am335x_i2c_boardinfo));
1788 } 1784 }
1789 1785
1790 static struct resource am335x_rtc_resources[] = { 1786 static struct resource am335x_rtc_resources[] = {
1791 { 1787 {
1792 .start = AM33XX_RTC_BASE, 1788 .start = AM33XX_RTC_BASE,
1793 .end = AM33XX_RTC_BASE + SZ_4K - 1, 1789 .end = AM33XX_RTC_BASE + SZ_4K - 1,
1794 .flags = IORESOURCE_MEM, 1790 .flags = IORESOURCE_MEM,
1795 }, 1791 },
1796 { /* timer irq */ 1792 { /* timer irq */
1797 .start = AM33XX_IRQ_RTC_TIMER, 1793 .start = AM33XX_IRQ_RTC_TIMER,
1798 .end = AM33XX_IRQ_RTC_TIMER, 1794 .end = AM33XX_IRQ_RTC_TIMER,
1799 .flags = IORESOURCE_IRQ, 1795 .flags = IORESOURCE_IRQ,
1800 }, 1796 },
1801 { /* alarm irq */ 1797 { /* alarm irq */
1802 .start = AM33XX_IRQ_RTC_ALARM, 1798 .start = AM33XX_IRQ_RTC_ALARM,
1803 .end = AM33XX_IRQ_RTC_ALARM, 1799 .end = AM33XX_IRQ_RTC_ALARM,
1804 .flags = IORESOURCE_IRQ, 1800 .flags = IORESOURCE_IRQ,
1805 }, 1801 },
1806 }; 1802 };
1807 1803
1808 static struct platform_device am335x_rtc_device = { 1804 static struct platform_device am335x_rtc_device = {
1809 .name = "omap_rtc", 1805 .name = "omap_rtc",
1810 .id = -1, 1806 .id = -1,
1811 .num_resources = ARRAY_SIZE(am335x_rtc_resources), 1807 .num_resources = ARRAY_SIZE(am335x_rtc_resources),
1812 .resource = am335x_rtc_resources, 1808 .resource = am335x_rtc_resources,
1813 }; 1809 };
1814 1810
1815 static int am335x_rtc_init(void) 1811 static int am335x_rtc_init(void)
1816 { 1812 {
1817 void __iomem *base; 1813 void __iomem *base;
1818 struct clk *clk; 1814 struct clk *clk;
1819 1815
1820 clk = clk_get(NULL, "rtc_fck"); 1816 clk = clk_get(NULL, "rtc_fck");
1821 if (IS_ERR(clk)) { 1817 if (IS_ERR(clk)) {
1822 pr_err("rtc : Failed to get RTC clock\n"); 1818 pr_err("rtc : Failed to get RTC clock\n");
1823 return -1; 1819 return -1;
1824 } 1820 }
1825 1821
1826 if (clk_enable(clk)) { 1822 if (clk_enable(clk)) {
1827 pr_err("rtc: Clock Enable Failed\n"); 1823 pr_err("rtc: Clock Enable Failed\n");
1828 return -1; 1824 return -1;
1829 } 1825 }
1830 1826
1831 base = ioremap(AM33XX_RTC_BASE, SZ_4K); 1827 base = ioremap(AM33XX_RTC_BASE, SZ_4K);
1832 1828
1833 if (WARN_ON(!base)) 1829 if (WARN_ON(!base))
1834 return -ENOMEM; 1830 return -ENOMEM;
1835 1831
1836 /* Unlock the rtc's registers */ 1832 /* Unlock the rtc's registers */
1837 __raw_writel(0x83e70b13, base + 0x6c); 1833 __raw_writel(0x83e70b13, base + 0x6c);
1838 __raw_writel(0x95a4f1e0, base + 0x70); 1834 __raw_writel(0x95a4f1e0, base + 0x70);
1839 1835
1840 /* 1836 /*
1841 * Enable the 32K OSc 1837 * Enable the 32K OSc
1842 * TODO: Need a better way to handle this 1838 * TODO: Need a better way to handle this
1843 * Since we want the clock to be running before mmc init 1839 * Since we want the clock to be running before mmc init
1844 * we need to do it before the rtc probe happens 1840 * we need to do it before the rtc probe happens
1845 */ 1841 */
1846 __raw_writel(0x48, base + 0x54); 1842 __raw_writel(0x48, base + 0x54);
1847 1843
1848 iounmap(base); 1844 iounmap(base);
1849 1845
1850 return platform_device_register(&am335x_rtc_device); 1846 return platform_device_register(&am335x_rtc_device);
1851 } 1847 }
1852 1848
1853 /* Enable clkout2 */ 1849 /* Enable clkout2 */
1854 static struct pinmux_config clkout2_pin_mux[] = { 1850 static struct pinmux_config clkout2_pin_mux[] = {
1855 {"xdma_event_intr1.clkout2", OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT}, 1851 {"xdma_event_intr1.clkout2", OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT},
1856 {NULL, 0}, 1852 {NULL, 0},
1857 }; 1853 };
1858 1854
1859 static void __init clkout2_enable(void) 1855 static void __init clkout2_enable(void)
1860 { 1856 {
1861 struct clk *ck_32; 1857 struct clk *ck_32;
1862 1858
1863 ck_32 = clk_get(NULL, "clkout2_ck"); 1859 ck_32 = clk_get(NULL, "clkout2_ck");
1864 if (IS_ERR(ck_32)) { 1860 if (IS_ERR(ck_32)) {
1865 pr_err("Cannot clk_get ck_32\n"); 1861 pr_err("Cannot clk_get ck_32\n");
1866 return; 1862 return;
1867 } 1863 }
1868 1864
1869 clk_enable(ck_32); 1865 clk_enable(ck_32);
1870 1866
1871 setup_pin_mux(clkout2_pin_mux); 1867 setup_pin_mux(clkout2_pin_mux);
1872 } 1868 }
1873 1869
1874 void __iomem * __init am33xx_get_mem_ctlr(void) 1870 void __iomem * __init am33xx_get_mem_ctlr(void)
1875 { 1871 {
1876 void __iomem *am33xx_emif_base; 1872 void __iomem *am33xx_emif_base;
1877 1873
1878 am33xx_emif_base = ioremap(AM33XX_EMIF0_BASE, SZ_32K); 1874 am33xx_emif_base = ioremap(AM33XX_EMIF0_BASE, SZ_32K);
1879 1875
1880 if (!am33xx_emif_base) 1876 if (!am33xx_emif_base)
1881 pr_warning("%s: Unable to map DDR2 controller", __func__); 1877 pr_warning("%s: Unable to map DDR2 controller", __func__);
1882 1878
1883 return am33xx_emif_base; 1879 return am33xx_emif_base;
1884 } 1880 }
1885 1881
1886 static struct resource am33xx_cpuidle_resources[] = { 1882 static struct resource am33xx_cpuidle_resources[] = {
1887 { 1883 {
1888 .start = AM33XX_EMIF0_BASE, 1884 .start = AM33XX_EMIF0_BASE,
1889 .end = AM33XX_EMIF0_BASE + SZ_32K - 1, 1885 .end = AM33XX_EMIF0_BASE + SZ_32K - 1,
1890 .flags = IORESOURCE_MEM, 1886 .flags = IORESOURCE_MEM,
1891 }, 1887 },
1892 }; 1888 };
1893 1889
1894 /* AM33XX devices support DDR2 power down */ 1890 /* AM33XX devices support DDR2 power down */
1895 static struct am33xx_cpuidle_config am33xx_cpuidle_pdata = { 1891 static struct am33xx_cpuidle_config am33xx_cpuidle_pdata = {
1896 .ddr2_pdown = 1, 1892 .ddr2_pdown = 1,
1897 }; 1893 };
1898 1894
1899 static struct platform_device am33xx_cpuidle_device = { 1895 static struct platform_device am33xx_cpuidle_device = {
1900 .name = "cpuidle-am33xx", 1896 .name = "cpuidle-am33xx",
1901 .num_resources = ARRAY_SIZE(am33xx_cpuidle_resources), 1897 .num_resources = ARRAY_SIZE(am33xx_cpuidle_resources),
1902 .resource = am33xx_cpuidle_resources, 1898 .resource = am33xx_cpuidle_resources,
1903 .dev = { 1899 .dev = {
1904 .platform_data = &am33xx_cpuidle_pdata, 1900 .platform_data = &am33xx_cpuidle_pdata,
1905 }, 1901 },
1906 }; 1902 };
1907 1903
1908 static void __init am33xx_cpuidle_init(void) 1904 static void __init am33xx_cpuidle_init(void)
1909 { 1905 {
1910 int ret; 1906 int ret;
1911 1907
1912 am33xx_cpuidle_pdata.emif_base = am33xx_get_mem_ctlr(); 1908 am33xx_cpuidle_pdata.emif_base = am33xx_get_mem_ctlr();
1913 1909
1914 ret = platform_device_register(&am33xx_cpuidle_device); 1910 ret = platform_device_register(&am33xx_cpuidle_device);
1915 1911
1916 if (ret) 1912 if (ret)
1917 pr_warning("AM33XX cpuidle registration failed\n"); 1913 pr_warning("AM33XX cpuidle registration failed\n");
1918 1914
1919 } 1915 }
1920 1916
1921 static void __init am335x_evm_init(void) 1917 static void __init am335x_evm_init(void)
1922 { 1918 {
1923 am33xx_cpuidle_init(); 1919 am33xx_cpuidle_init();
1924 am33xx_mux_init(board_mux); 1920 am33xx_mux_init(board_mux);
1925 omap_serial_init(); 1921 omap_serial_init();
1926 am335x_rtc_init(); 1922 am335x_rtc_init();
1927 clkout2_enable(); 1923 clkout2_enable();
1928 am335x_evm_i2c_init(); 1924 am335x_evm_i2c_init();
1929 omap_sdrc_init(NULL, NULL); 1925 omap_sdrc_init(NULL, NULL);
1930 usb_musb_init(&musb_board_data); 1926 usb_musb_init(&musb_board_data);
1931 omap_board_config = am335x_evm_config; 1927 omap_board_config = am335x_evm_config;
1932 omap_board_config_size = ARRAY_SIZE(am335x_evm_config); 1928 omap_board_config_size = ARRAY_SIZE(am335x_evm_config);
1933 /* Create an alias for icss clock */ 1929 /* Create an alias for icss clock */
1934 if (clk_add_alias("pruss", NULL, "icss_uart_gclk", NULL)) 1930 if (clk_add_alias("pruss", NULL, "icss_uart_gclk", NULL))
1935 pr_err("failed to create an alias: icss_uart_gclk --> pruss\n"); 1931 pr_err("failed to create an alias: icss_uart_gclk --> pruss\n");
1936 /* Create an alias for gfx/sgx clock */ 1932 /* Create an alias for gfx/sgx clock */
1937 if (clk_add_alias("sgx_ck", NULL, "gfx_fclk", NULL)) 1933 if (clk_add_alias("sgx_ck", NULL, "gfx_fclk", NULL))
1938 pr_err("failed to create an alias: gfx_fclk --> sgx_ck\n"); 1934 pr_err("failed to create an alias: gfx_fclk --> sgx_ck\n");
1939 } 1935 }
1940 1936
1941 static void __init am335x_evm_map_io(void) 1937 static void __init am335x_evm_map_io(void)
1942 { 1938 {
1943 omap2_set_globals_am33xx(); 1939 omap2_set_globals_am33xx();
1944 omapam33xx_map_common_io(); 1940 omapam33xx_map_common_io();
1945 } 1941 }
1946 1942
1947 MACHINE_START(AM335XEVM, "am335xevm") 1943 MACHINE_START(AM335XEVM, "am335xevm")
1948 /* Maintainer: Texas Instruments */ 1944 /* Maintainer: Texas Instruments */
1949 .atag_offset = 0x100, 1945 .atag_offset = 0x100,
1950 .map_io = am335x_evm_map_io, 1946 .map_io = am335x_evm_map_io,
1951 .init_irq = ti816x_init_irq, 1947 .init_irq = ti816x_init_irq,
1952 .init_early = am335x_init_early, 1948 .init_early = am335x_init_early,
1953 .timer = &omap3_am33xx_timer, 1949 .timer = &omap3_am33xx_timer,
1954 .init_machine = am335x_evm_init, 1950 .init_machine = am335x_evm_init,
1955 MACHINE_END 1951 MACHINE_END
1956 1952
1957 MACHINE_START(AM335XIAEVM, "am335xiaevm") 1953 MACHINE_START(AM335XIAEVM, "am335xiaevm")
1958 /* Maintainer: Texas Instruments */ 1954 /* Maintainer: Texas Instruments */
1959 .atag_offset = 0x100, 1955 .atag_offset = 0x100,
1960 .map_io = am335x_evm_map_io, 1956 .map_io = am335x_evm_map_io,
1961 .init_irq = ti816x_init_irq, 1957 .init_irq = ti816x_init_irq,
1962 .init_early = am335x_init_early, 1958 .init_early = am335x_init_early,
1963 .timer = &omap3_am33xx_timer, 1959 .timer = &omap3_am33xx_timer,
1964 .init_machine = am335x_evm_init, 1960 .init_machine = am335x_evm_init,
1965 MACHINE_END 1961 MACHINE_END