Eric Lee / linux-smarc-t335x-v3.2

Commit df423dc7f2a801b9a45d7c501a8eb5c529455ea1

Authored by Linus Torvalds 2010-09-10 11:28:19 +0800

Exists in master and in 4 other branches

Merge branch 'upstream-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jgarzik/libata-dev

* 'upstream-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jgarzik/libata-dev:
  libata-sff: Reenable Port Multiplier after libata-sff remodeling.
  libata: skip EH autopsy and recovery during suspend
  ahci: AHCI and RAID mode SATA patch for Intel Patsburg DeviceIDs
  ata_piix: IDE Mode SATA patch for Intel Patsburg DeviceIDs
  libata,pata_via: revert ata_wait_idle() removal from ata_sff/via_tf_load()
  ahci: fix hang on failed softreset
  pata_artop: Fix device ID parity check

Showing 10 changed files Inline Diff

drivers/ata/ahci.c
drivers/ata/ata_piix.c
drivers/ata/libahci.c
drivers/ata/libata-core.c
drivers/ata/libata-eh.c
drivers/ata/libata-sff.c
drivers/ata/pata_artop.c
drivers/ata/pata_via.c
drivers/ata/sata_mv.c
include/linux/libata.h

drivers/ata/ahci.c

Diff comments View file @ df423dc

 /*
  *  ahci.c - AHCI SATA support
  *
  *  Maintained by:  Jeff Garzik <jgarzik@pobox.com>
  *    		    Please ALWAYS copy linux-ide@vger.kernel.org
  *		    on emails.
  *
  *  Copyright 2004-2005 Red Hat, Inc.
  *
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
  *  the Free Software Foundation; either version 2, or (at your option)
  *  any later version.
  *
  *  This program is distributed in the hope that it will be useful,
  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  *  GNU General Public License for more details.
  *
  *  You should have received a copy of the GNU General Public License
  *  along with this program; see the file COPYING.  If not, write to
  *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  *
  *
  * libata documentation is available via 'make {ps|pdf}docs',
  * as Documentation/DocBook/libata.*
  *
  * AHCI hardware documentation:
  * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
  * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
  *
  */
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/pci.h>
 #include <linux/init.h>
 #include <linux/blkdev.h>
 #include <linux/delay.h>
 #include <linux/interrupt.h>
 #include <linux/dma-mapping.h>
 #include <linux/device.h>
 #include <linux/dmi.h>
 #include <linux/gfp.h>
 #include <scsi/scsi_host.h>
 #include <scsi/scsi_cmnd.h>
 #include <linux/libata.h>
 #include "ahci.h"
 #define DRV_NAME	"ahci"
 #define DRV_VERSION	"3.0"
 enum {
 	AHCI_PCI_BAR		= 5,
 };
 enum board_ids {
 	/* board IDs by feature in alphabetical order */
 	board_ahci,
 	board_ahci_ign_iferr,
 	board_ahci_nosntf,
 	board_ahci_yes_fbs,
 	/* board IDs for specific chipsets in alphabetical order */
 	board_ahci_mcp65,
 	board_ahci_mcp77,
 	board_ahci_mcp89,
 	board_ahci_mv,
 	board_ahci_sb600,
 	board_ahci_sb700,	/* for SB700 and SB800 */
 	board_ahci_vt8251,
 	/* aliases */
 	board_ahci_mcp_linux	= board_ahci_mcp65,
 	board_ahci_mcp67	= board_ahci_mcp65,
 	board_ahci_mcp73	= board_ahci_mcp65,
 	board_ahci_mcp79	= board_ahci_mcp77,
 };
 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
 static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
 			  unsigned long deadline);
 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
 				 unsigned long deadline);
 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
 				unsigned long deadline);
 #ifdef CONFIG_PM
 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
 static int ahci_pci_device_resume(struct pci_dev *pdev);
 #endif
 static struct ata_port_operations ahci_vt8251_ops = {
 	.inherits		= &ahci_ops,
 	.hardreset		= ahci_vt8251_hardreset,
 };
 static struct ata_port_operations ahci_p5wdh_ops = {
 	.inherits		= &ahci_ops,
 	.hardreset		= ahci_p5wdh_hardreset,
 };
 static struct ata_port_operations ahci_sb600_ops = {
 	.inherits		= &ahci_ops,
 	.softreset		= ahci_sb600_softreset,
 	.pmp_softreset		= ahci_sb600_softreset,
 };
 #define AHCI_HFLAGS(flags)	.private_data	= (void *)(flags)
 static const struct ata_port_info ahci_port_info[] = {
 	/* by features */
 	[board_ahci] =
 	{
 		.flags		= AHCI_FLAG_COMMON,
 		.pio_mask	= ATA_PIO4,
 		.udma_mask	= ATA_UDMA6,
 		.port_ops	= &ahci_ops,
 	},
 	[board_ahci_ign_iferr] =
 	{
 		AHCI_HFLAGS	(AHCI_HFLAG_IGN_IRQ_IF_ERR),
 		.flags		= AHCI_FLAG_COMMON,
 		.pio_mask	= ATA_PIO4,
 		.udma_mask	= ATA_UDMA6,
 		.port_ops	= &ahci_ops,
 	},
 	[board_ahci_nosntf] =
 	{
 		AHCI_HFLAGS	(AHCI_HFLAG_NO_SNTF),
 		.flags		= AHCI_FLAG_COMMON,
 		.pio_mask	= ATA_PIO4,
 		.udma_mask	= ATA_UDMA6,
 		.port_ops	= &ahci_ops,
 	},
 	[board_ahci_yes_fbs] =
 	{
 		AHCI_HFLAGS	(AHCI_HFLAG_YES_FBS),
 		.flags		= AHCI_FLAG_COMMON,
 		.pio_mask	= ATA_PIO4,
 		.udma_mask	= ATA_UDMA6,
 		.port_ops	= &ahci_ops,
 	},
 	/* by chipsets */
 	[board_ahci_mcp65] =
 	{
 		AHCI_HFLAGS	(AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
 				 AHCI_HFLAG_YES_NCQ),
 		.flags		= AHCI_FLAG_COMMON,
 		.pio_mask	= ATA_PIO4,
 		.udma_mask	= ATA_UDMA6,
 		.port_ops	= &ahci_ops,
 	},
 	[board_ahci_mcp77] =
 	{
 		AHCI_HFLAGS	(AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
 		.flags		= AHCI_FLAG_COMMON,
 		.pio_mask	= ATA_PIO4,
 		.udma_mask	= ATA_UDMA6,
 		.port_ops	= &ahci_ops,
 	},
 	[board_ahci_mcp89] =
 	{
 		AHCI_HFLAGS	(AHCI_HFLAG_NO_FPDMA_AA),
 		.flags		= AHCI_FLAG_COMMON,
 		.pio_mask	= ATA_PIO4,
 		.udma_mask	= ATA_UDMA6,
 		.port_ops	= &ahci_ops,
 	},
 	[board_ahci_mv] =
 	{
 		AHCI_HFLAGS	(AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
 				 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
 		.flags		= ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
 				  ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
 		.pio_mask	= ATA_PIO4,
 		.udma_mask	= ATA_UDMA6,
 		.port_ops	= &ahci_ops,
 	},
 	[board_ahci_sb600] =
 	{
 		AHCI_HFLAGS	(AHCI_HFLAG_IGN_SERR_INTERNAL |
 				 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
 				 AHCI_HFLAG_32BIT_ONLY),
 		.flags		= AHCI_FLAG_COMMON,
 		.pio_mask	= ATA_PIO4,
 		.udma_mask	= ATA_UDMA6,
 		.port_ops	= &ahci_sb600_ops,
 	},
 	[board_ahci_sb700] =	/* for SB700 and SB800 */
 	{
 		AHCI_HFLAGS	(AHCI_HFLAG_IGN_SERR_INTERNAL),
 		.flags		= AHCI_FLAG_COMMON,
 		.pio_mask	= ATA_PIO4,
 		.udma_mask	= ATA_UDMA6,
 		.port_ops	= &ahci_sb600_ops,
 	},
 	[board_ahci_vt8251] =
 	{
 		AHCI_HFLAGS	(AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
 		.flags		= AHCI_FLAG_COMMON,
 		.pio_mask	= ATA_PIO4,
 		.udma_mask	= ATA_UDMA6,
 		.port_ops	= &ahci_vt8251_ops,
 	},
 };
 static const struct pci_device_id ahci_pci_tbl[] = {
 	/* Intel */
 	{ PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
 	{ PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
 	{ PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
 	{ PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
 	{ PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
 	{ PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
 	{ PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
 	{ PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
 	{ PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
 	{ PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
 	{ PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
 	{ PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
 	{ PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
 	{ PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
 	{ PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
 	{ PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
 	{ PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
 	{ PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
 	{ PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
 	{ PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
 	{ PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
 	{ PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
 	{ PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
 	{ PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
 	{ PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
 	{ PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
 	{ PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
 	{ PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
 	{ PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
 	{ PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
 	{ PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
 	{ PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
 	{ PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
 	{ PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
 	{ PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
 	{ PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
 	{ PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
 	{ PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
 	{ PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
 	{ PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
 	{ PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
 	{ PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
 	{ PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
 	{ PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
 	{ PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
 	{ PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
+	{ PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
+	{ PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
+	{ PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
 	/* JMicron 360/1/3/5/6, match class to avoid IDE function */
 	{ PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
 	  PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
 	/* ATI */
 	{ PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
 	{ PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
 	{ PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
 	{ PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
 	{ PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
 	{ PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
 	{ PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
 	/* AMD */
 	{ PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
 	/* AMD is using RAID class only for ahci controllers */
 	{ PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
 	  PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
 	/* VIA */
 	{ PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
 	{ PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
 	/* NVIDIA */
 	{ PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 },	/* MCP65 */
 	{ PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 },	/* MCP65 */
 	{ PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 },	/* MCP65 */
 	{ PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 },	/* MCP65 */
 	{ PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 },	/* MCP65 */
 	{ PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 },	/* MCP65 */
 	{ PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 },	/* MCP65 */
 	{ PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 },	/* MCP65 */
 	{ PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 },	/* MCP67 */
 	{ PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 },	/* MCP67 */
 	{ PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 },	/* MCP67 */
 	{ PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 },	/* MCP67 */
 	{ PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 },	/* MCP67 */
 	{ PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 },	/* MCP67 */
 	{ PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 },	/* MCP67 */
 	{ PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 },	/* MCP67 */
 	{ PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 },	/* MCP67 */
 	{ PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 },	/* MCP67 */
 	{ PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 },	/* MCP67 */
 	{ PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 },	/* MCP67 */
 	{ PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux },	/* Linux ID */
 	{ PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux },	/* Linux ID */
 	{ PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux },	/* Linux ID */
 	{ PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux },	/* Linux ID */
 	{ PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux },	/* Linux ID */
 	{ PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux },	/* Linux ID */
 	{ PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux },	/* Linux ID */
 	{ PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux },	/* Linux ID */
 	{ PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux },	/* Linux ID */
 	{ PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux },	/* Linux ID */
 	{ PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux },	/* Linux ID */
 	{ PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux },	/* Linux ID */
 	{ PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux },	/* Linux ID */
 	{ PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux },	/* Linux ID */
 	{ PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux },	/* Linux ID */
 	{ PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux },	/* Linux ID */
 	{ PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 },	/* MCP73 */
 	{ PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 },	/* MCP73 */
 	{ PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 },	/* MCP73 */
 	{ PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 },	/* MCP73 */
 	{ PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 },	/* MCP73 */
 	{ PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 },	/* MCP73 */
 	{ PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 },	/* MCP73 */
 	{ PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 },	/* MCP73 */
 	{ PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 },	/* MCP73 */
 	{ PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 },	/* MCP73 */
 	{ PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 },	/* MCP73 */
 	{ PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 },	/* MCP73 */
 	{ PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 },	/* MCP77 */
 	{ PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 },	/* MCP77 */
 	{ PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 },	/* MCP77 */
 	{ PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 },	/* MCP77 */
 	{ PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 },	/* MCP77 */
 	{ PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 },	/* MCP77 */
 	{ PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 },	/* MCP77 */
 	{ PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 },	/* MCP77 */
 	{ PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 },	/* MCP77 */
 	{ PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 },	/* MCP77 */
 	{ PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 },	/* MCP77 */
 	{ PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 },	/* MCP77 */
 	{ PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 },	/* MCP79 */
 	{ PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 },	/* MCP79 */
 	{ PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 },	/* MCP79 */
 	{ PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 },	/* MCP79 */
 	{ PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 },	/* MCP79 */
 	{ PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 },	/* MCP79 */
 	{ PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 },	/* MCP79 */
 	{ PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 },	/* MCP79 */
 	{ PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 },	/* MCP79 */
 	{ PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 },	/* MCP79 */
 	{ PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 },	/* MCP79 */
 	{ PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 },	/* MCP79 */
 	{ PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 },	/* MCP89 */
 	{ PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 },	/* MCP89 */
 	{ PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 },	/* MCP89 */
 	{ PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 },	/* MCP89 */
 	{ PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 },	/* MCP89 */
 	{ PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 },	/* MCP89 */
 	{ PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 },	/* MCP89 */
 	{ PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 },	/* MCP89 */
 	{ PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 },	/* MCP89 */
 	{ PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 },	/* MCP89 */
 	{ PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 },	/* MCP89 */
 	{ PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 },	/* MCP89 */
 	/* SiS */
 	{ PCI_VDEVICE(SI, 0x1184), board_ahci },		/* SiS 966 */
 	{ PCI_VDEVICE(SI, 0x1185), board_ahci },		/* SiS 968 */
 	{ PCI_VDEVICE(SI, 0x0186), board_ahci },		/* SiS 968 */
 	/* Marvell */
 	{ PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv },	/* 6145 */
 	{ PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv },	/* 6121 */
 	{ PCI_DEVICE(0x1b4b, 0x9123),
 	  .driver_data = board_ahci_yes_fbs },			/* 88se9128 */
 	/* Promise */
 	{ PCI_VDEVICE(PROMISE, 0x3f20), board_ahci },	/* PDC42819 */
 	/* Generic, PCI class code for AHCI */
 	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
 	  PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
 	{ }	/* terminate list */
 };
 static struct pci_driver ahci_pci_driver = {
 	.name			= DRV_NAME,
 	.id_table		= ahci_pci_tbl,
 	.probe			= ahci_init_one,
 	.remove			= ata_pci_remove_one,
 #ifdef CONFIG_PM
 	.suspend		= ahci_pci_device_suspend,
 	.resume			= ahci_pci_device_resume,
 #endif
 };
 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
 static int marvell_enable;
 #else
 static int marvell_enable = 1;
 #endif
 module_param(marvell_enable, int, 0644);
 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
 					 struct ahci_host_priv *hpriv)
 {
 	unsigned int force_port_map = 0;
 	unsigned int mask_port_map = 0;
 	if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
 		dev_info(&pdev->dev, "JMB361 has only one port\n");
 		force_port_map = 1;
 	}
 	/*
 	 * Temporary Marvell 6145 hack: PATA port presence
 	 * is asserted through the standard AHCI port
 	 * presence register, as bit 4 (counting from 0)
 	 */
 	if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
 		if (pdev->device == 0x6121)
 			mask_port_map = 0x3;
 		else
 			mask_port_map = 0xf;
 		dev_info(&pdev->dev,
 			  "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
 	}
 	ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
 				 mask_port_map);
 }
 static int ahci_pci_reset_controller(struct ata_host *host)
 {
 	struct pci_dev *pdev = to_pci_dev(host->dev);
 	ahci_reset_controller(host);
 	if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
 		struct ahci_host_priv *hpriv = host->private_data;
 		u16 tmp16;
 		/* configure PCS */
 		pci_read_config_word(pdev, 0x92, &tmp16);
 		if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
 			tmp16 |= hpriv->port_map;
 			pci_write_config_word(pdev, 0x92, tmp16);
 		}
 	}
 	return 0;
 }
 static void ahci_pci_init_controller(struct ata_host *host)
 {
 	struct ahci_host_priv *hpriv = host->private_data;
 	struct pci_dev *pdev = to_pci_dev(host->dev);
 	void __iomem *port_mmio;
 	u32 tmp;
 	int mv;
 	if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
 		if (pdev->device == 0x6121)
 			mv = 2;
 		else
 			mv = 4;
 		port_mmio = __ahci_port_base(host, mv);
 		writel(0, port_mmio + PORT_IRQ_MASK);
 		/* clear port IRQ */
 		tmp = readl(port_mmio + PORT_IRQ_STAT);
 		VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
 		if (tmp)
 			writel(tmp, port_mmio + PORT_IRQ_STAT);
 	}
 	ahci_init_controller(host);
 }
 static int ahci_sb600_check_ready(struct ata_link *link)
 {
 	void __iomem *port_mmio = ahci_port_base(link->ap);
 	u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
 	u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
 	/*
 	 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
 	 * which can save timeout delay.
 	 */
 	if (irq_status & PORT_IRQ_BAD_PMP)
 		return -EIO;
 	return ata_check_ready(status);
 }
 static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
 				unsigned long deadline)
 {
 	struct ata_port *ap = link->ap;
 	void __iomem *port_mmio = ahci_port_base(ap);
 	int pmp = sata_srst_pmp(link);
 	int rc;
 	u32 irq_sts;
 	DPRINTK("ENTER\n");
 	rc = ahci_do_softreset(link, class, pmp, deadline,
 			       ahci_sb600_check_ready);
 	/*
 	 * Soft reset fails on some ATI chips with IPMS set when PMP
 	 * is enabled but SATA HDD/ODD is connected to SATA port,
 	 * do soft reset again to port 0.
 	 */
 	if (rc == -EIO) {
 		irq_sts = readl(port_mmio + PORT_IRQ_STAT);
 		if (irq_sts & PORT_IRQ_BAD_PMP) {
 			ata_link_printk(link, KERN_WARNING,
 					"applying SB600 PMP SRST workaround "
 					"and retrying\n");
 			rc = ahci_do_softreset(link, class, 0, deadline,
 					       ahci_check_ready);
 		}
 	}
 	return rc;
 }
 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
 				 unsigned long deadline)
 {
 	struct ata_port *ap = link->ap;
 	bool online;
 	int rc;
 	DPRINTK("ENTER\n");
 	ahci_stop_engine(ap);
 	rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
 				 deadline, &online, NULL);
 	ahci_start_engine(ap);
 	DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
 	/* vt8251 doesn't clear BSY on signature FIS reception,
 	 * request follow-up softreset.
 	 */
 	return online ? -EAGAIN : rc;
 }
 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
 				unsigned long deadline)
 {
 	struct ata_port *ap = link->ap;
 	struct ahci_port_priv *pp = ap->private_data;
 	u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
 	struct ata_taskfile tf;
 	bool online;
 	int rc;
 	ahci_stop_engine(ap);
 	/* clear D2H reception area to properly wait for D2H FIS */
 	ata_tf_init(link->device, &tf);
 	tf.command = 0x80;
 	ata_tf_to_fis(&tf, 0, 0, d2h_fis);
 	rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
 				 deadline, &online, NULL);
 	ahci_start_engine(ap);
 	/* The pseudo configuration device on SIMG4726 attached to
 	 * ASUS P5W-DH Deluxe doesn't send signature FIS after
 	 * hardreset if no device is attached to the first downstream
 	 * port && the pseudo device locks up on SRST w/ PMP==0.  To
 	 * work around this, wait for !BSY only briefly.  If BSY isn't
 	 * cleared, perform CLO and proceed to IDENTIFY (achieved by
 	 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
 	 *
 	 * Wait for two seconds.  Devices attached to downstream port
 	 * which can't process the following IDENTIFY after this will
 	 * have to be reset again.  For most cases, this should
 	 * suffice while making probing snappish enough.
 	 */
 	if (online) {
 		rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
 					  ahci_check_ready);
 		if (rc)
 			ahci_kick_engine(ap);
 	}
 	return rc;
 }
 #ifdef CONFIG_PM
 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
 {
 	struct ata_host *host = dev_get_drvdata(&pdev->dev);
 	struct ahci_host_priv *hpriv = host->private_data;
 	void __iomem *mmio = hpriv->mmio;
 	u32 ctl;
 	if (mesg.event & PM_EVENT_SUSPEND &&
 	    hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
 		dev_printk(KERN_ERR, &pdev->dev,
 			   "BIOS update required for suspend/resume\n");
 		return -EIO;
 	}
 	if (mesg.event & PM_EVENT_SLEEP) {
 		/* AHCI spec rev1.1 section 8.3.3:
 		 * Software must disable interrupts prior to requesting a
 		 * transition of the HBA to D3 state.
 		 */
 		ctl = readl(mmio + HOST_CTL);
 		ctl &= ~HOST_IRQ_EN;
 		writel(ctl, mmio + HOST_CTL);
 		readl(mmio + HOST_CTL); /* flush */
 	}
 	return ata_pci_device_suspend(pdev, mesg);
 }
 static int ahci_pci_device_resume(struct pci_dev *pdev)
 {
 	struct ata_host *host = dev_get_drvdata(&pdev->dev);
 	int rc;
 	rc = ata_pci_device_do_resume(pdev);
 	if (rc)
 		return rc;
 	if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
 		rc = ahci_pci_reset_controller(host);
 		if (rc)
 			return rc;
 		ahci_pci_init_controller(host);
 	}
 	ata_host_resume(host);
 	return 0;
 }
 #endif
 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
 {
 	int rc;
 	if (using_dac &&
 	    !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
 		rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
 		if (rc) {
 			rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
 			if (rc) {
 				dev_printk(KERN_ERR, &pdev->dev,
 					   "64-bit DMA enable failed\n");
 				return rc;
 			}
 		}
 	} else {
 		rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
 		if (rc) {
 			dev_printk(KERN_ERR, &pdev->dev,
 				   "32-bit DMA enable failed\n");
 			return rc;
 		}
 		rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
 		if (rc) {
 			dev_printk(KERN_ERR, &pdev->dev,
 				   "32-bit consistent DMA enable failed\n");
 			return rc;
 		}
 	}
 	return 0;
 }
 static void ahci_pci_print_info(struct ata_host *host)
 {
 	struct pci_dev *pdev = to_pci_dev(host->dev);
 	u16 cc;
 	const char *scc_s;
 	pci_read_config_word(pdev, 0x0a, &cc);
 	if (cc == PCI_CLASS_STORAGE_IDE)
 		scc_s = "IDE";
 	else if (cc == PCI_CLASS_STORAGE_SATA)
 		scc_s = "SATA";
 	else if (cc == PCI_CLASS_STORAGE_RAID)
 		scc_s = "RAID";
 	else
 		scc_s = "unknown";
 	ahci_print_info(host, scc_s);
 }
 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
  * hardwired to on-board SIMG 4726.  The chipset is ICH8 and doesn't
  * support PMP and the 4726 either directly exports the device
  * attached to the first downstream port or acts as a hardware storage
  * controller and emulate a single ATA device (can be RAID 0/1 or some
  * other configuration).
  *
  * When there's no device attached to the first downstream port of the
  * 4726, "Config Disk" appears, which is a pseudo ATA device to
  * configure the 4726.  However, ATA emulation of the device is very
  * lame.  It doesn't send signature D2H Reg FIS after the initial
  * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
  *
  * The following function works around the problem by always using
  * hardreset on the port and not depending on receiving signature FIS
  * afterward.  If signature FIS isn't received soon, ATA class is
  * assumed without follow-up softreset.
  */
 static void ahci_p5wdh_workaround(struct ata_host *host)
 {
 	static struct dmi_system_id sysids[] = {
 		{
 			.ident = "P5W DH Deluxe",
 			.matches = {
 				DMI_MATCH(DMI_SYS_VENDOR,
 					  "ASUSTEK COMPUTER INC"),
 				DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
 			},
 		},
 		{ }
 	};
 	struct pci_dev *pdev = to_pci_dev(host->dev);
 	if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
 	    dmi_check_system(sysids)) {
 		struct ata_port *ap = host->ports[1];
 		dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
 			   "Deluxe on-board SIMG4726 workaround\n");
 		ap->ops = &ahci_p5wdh_ops;
 		ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
 	}
 }
 /* only some SB600 ahci controllers can do 64bit DMA */
 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
 {
 	static const struct dmi_system_id sysids[] = {
 		/*
 		 * The oldest version known to be broken is 0901 and
 		 * working is 1501 which was released on 2007-10-26.
 		 * Enable 64bit DMA on 1501 and anything newer.
 		 *
 		 * Please read bko#9412 for more info.
 		 */
 		{
 			.ident = "ASUS M2A-VM",
 			.matches = {
 				DMI_MATCH(DMI_BOARD_VENDOR,
 					  "ASUSTeK Computer INC."),
 				DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
 			},
 			.driver_data = "20071026",	/* yyyymmdd */
 		},
 		/*
 		 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
 		 * support 64bit DMA.
 		 *
 		 * BIOS versions earlier than 1.5 had the Manufacturer DMI
 		 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
 		 * This spelling mistake was fixed in BIOS version 1.5, so
 		 * 1.5 and later have the Manufacturer as
 		 * "MICRO-STAR INTERNATIONAL CO.,LTD".
 		 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
 		 *
 		 * BIOS versions earlier than 1.9 had a Board Product Name
 		 * DMI field of "MS-7376". This was changed to be
 		 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
 		 * match on DMI_BOARD_NAME of "MS-7376".
 		 */
 		{
 			.ident = "MSI K9A2 Platinum",
 			.matches = {
 				DMI_MATCH(DMI_BOARD_VENDOR,
 					  "MICRO-STAR INTER"),
 				DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
 			},
 		},
 		{ }
 	};
 	const struct dmi_system_id *match;
 	int year, month, date;
 	char buf[9];
 	match = dmi_first_match(sysids);
 	if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
 	    !match)
 		return false;
 	if (!match->driver_data)
 		goto enable_64bit;
 	dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
 	snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
 	if (strcmp(buf, match->driver_data) >= 0)
 		goto enable_64bit;
 	else {
 		dev_printk(KERN_WARNING, &pdev->dev, "%s: BIOS too old, "
 			   "forcing 32bit DMA, update BIOS\n", match->ident);
 		return false;
 	}
 enable_64bit:
 	dev_printk(KERN_WARNING, &pdev->dev, "%s: enabling 64bit DMA\n",
 		   match->ident);
 	return true;
 }
 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
 {
 	static const struct dmi_system_id broken_systems[] = {
 		{
 			.ident = "HP Compaq nx6310",
 			.matches = {
 				DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
 				DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
 			},
 			/* PCI slot number of the controller */
 			.driver_data = (void *)0x1FUL,
 		},
 		{
 			.ident = "HP Compaq 6720s",
 			.matches = {
 				DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
 				DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
 			},
 			/* PCI slot number of the controller */
 			.driver_data = (void *)0x1FUL,
 		},
 		{ }	/* terminate list */
 	};
 	const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
 	if (dmi) {
 		unsigned long slot = (unsigned long)dmi->driver_data;
 		/* apply the quirk only to on-board controllers */
 		return slot == PCI_SLOT(pdev->devfn);
 	}
 	return false;
 }
 static bool ahci_broken_suspend(struct pci_dev *pdev)
 {
 	static const struct dmi_system_id sysids[] = {
 		/*
 		 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
 		 * to the harddisk doesn't become online after
 		 * resuming from STR.  Warn and fail suspend.
 		 *
 		 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
 		 *
 		 * Use dates instead of versions to match as HP is
 		 * apparently recycling both product and version
 		 * strings.
 		 *
 		 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
 		 */
 		{
 			.ident = "dv4",
 			.matches = {
 				DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
 				DMI_MATCH(DMI_PRODUCT_NAME,
 					  "HP Pavilion dv4 Notebook PC"),
 			},
 			.driver_data = "20090105",	/* F.30 */
 		},
 		{
 			.ident = "dv5",
 			.matches = {
 				DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
 				DMI_MATCH(DMI_PRODUCT_NAME,
 					  "HP Pavilion dv5 Notebook PC"),
 			},
 			.driver_data = "20090506",	/* F.16 */
 		},
 		{
 			.ident = "dv6",
 			.matches = {
 				DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
 				DMI_MATCH(DMI_PRODUCT_NAME,
 					  "HP Pavilion dv6 Notebook PC"),
 			},
 			.driver_data = "20090423",	/* F.21 */
 		},
 		{
 			.ident = "HDX18",
 			.matches = {
 				DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
 				DMI_MATCH(DMI_PRODUCT_NAME,
 					  "HP HDX18 Notebook PC"),
 			},
 			.driver_data = "20090430",	/* F.23 */
 		},
 		/*
 		 * Acer eMachines G725 has the same problem.  BIOS
 		 * V1.03 is known to be broken.  V3.04 is known to
 		 * work.  Inbetween, there are V1.06, V2.06 and V3.03
 		 * that we don't have much idea about.  For now,
 		 * blacklist anything older than V3.04.
 		 *
 		 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
 		 */
 		{
 			.ident = "G725",
 			.matches = {
 				DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
 				DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
 			},
 			.driver_data = "20091216",	/* V3.04 */
 		},
 		{ }	/* terminate list */
 	};
 	const struct dmi_system_id *dmi = dmi_first_match(sysids);
 	int year, month, date;
 	char buf[9];
 	if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
 		return false;
 	dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
 	snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
 	return strcmp(buf, dmi->driver_data) < 0;
 }
 static bool ahci_broken_online(struct pci_dev *pdev)
 {
 #define ENCODE_BUSDEVFN(bus, slot, func)			\
 	(void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
 	static const struct dmi_system_id sysids[] = {
 		/*
 		 * There are several gigabyte boards which use
 		 * SIMG5723s configured as hardware RAID.  Certain
 		 * 5723 firmware revisions shipped there keep the link
 		 * online but fail to answer properly to SRST or
 		 * IDENTIFY when no device is attached downstream
 		 * causing libata to retry quite a few times leading
 		 * to excessive detection delay.
 		 *
 		 * As these firmwares respond to the second reset try
 		 * with invalid device signature, considering unknown
 		 * sig as offline works around the problem acceptably.
 		 */
 		{
 			.ident = "EP45-DQ6",
 			.matches = {
 				DMI_MATCH(DMI_BOARD_VENDOR,
 					  "Gigabyte Technology Co., Ltd."),
 				DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
 			},
 			.driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
 		},
 		{
 			.ident = "EP45-DS5",
 			.matches = {
 				DMI_MATCH(DMI_BOARD_VENDOR,
 					  "Gigabyte Technology Co., Ltd."),
 				DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
 			},
 			.driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
 		},
 		{ }	/* terminate list */
 	};
 #undef ENCODE_BUSDEVFN
 	const struct dmi_system_id *dmi = dmi_first_match(sysids);
 	unsigned int val;
 	if (!dmi)
 		return false;
 	val = (unsigned long)dmi->driver_data;
 	return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
 }
 #ifdef CONFIG_ATA_ACPI
 static void ahci_gtf_filter_workaround(struct ata_host *host)
 {
 	static const struct dmi_system_id sysids[] = {
 		/*
 		 * Aspire 3810T issues a bunch of SATA enable commands
 		 * via _GTF including an invalid one and one which is
 		 * rejected by the device.  Among the successful ones
 		 * is FPDMA non-zero offset enable which when enabled
 		 * only on the drive side leads to NCQ command
 		 * failures.  Filter it out.
 		 */
 		{
 			.ident = "Aspire 3810T",
 			.matches = {
 				DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
 				DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
 			},
 			.driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
 		},
 		{ }
 	};
 	const struct dmi_system_id *dmi = dmi_first_match(sysids);
 	unsigned int filter;
 	int i;
 	if (!dmi)
 		return;
 	filter = (unsigned long)dmi->driver_data;
 	dev_printk(KERN_INFO, host->dev,
 		   "applying extra ACPI _GTF filter 0x%x for %s\n",
 		   filter, dmi->ident);
 	for (i = 0; i < host->n_ports; i++) {
 		struct ata_port *ap = host->ports[i];
 		struct ata_link *link;
 		struct ata_device *dev;
 		ata_for_each_link(link, ap, EDGE)
 			ata_for_each_dev(dev, link, ALL)
 				dev->gtf_filter |= filter;
 	}
 }
 #else
 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
 {}
 #endif
 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
 {
 	static int printed_version;
 	unsigned int board_id = ent->driver_data;
 	struct ata_port_info pi = ahci_port_info[board_id];
 	const struct ata_port_info *ppi[] = { &pi, NULL };
 	struct device *dev = &pdev->dev;
 	struct ahci_host_priv *hpriv;
 	struct ata_host *host;
 	int n_ports, i, rc;
 	VPRINTK("ENTER\n");
 	WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
 	if (!printed_version++)
 		dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
 	/* The AHCI driver can only drive the SATA ports, the PATA driver
 	   can drive them all so if both drivers are selected make sure
 	   AHCI stays out of the way */
 	if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
 		return -ENODEV;
 	/*
 	 * For some reason, MCP89 on MacBook 7,1 doesn't work with
 	 * ahci, use ata_generic instead.
 	 */
 	if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
 	    pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
 	    pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
 	    pdev->subsystem_device == 0xcb89)
 		return -ENODEV;
 	/* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
 	 * At the moment, we can only use the AHCI mode. Let the users know
 	 * that for SAS drives they're out of luck.
 	 */
 	if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
 		dev_printk(KERN_INFO, &pdev->dev, "PDC42819 "
 			   "can only drive SATA devices with this driver\n");
 	/* acquire resources */
 	rc = pcim_enable_device(pdev);
 	if (rc)
 		return rc;
 	/* AHCI controllers often implement SFF compatible interface.
 	 * Grab all PCI BARs just in case.
 	 */
 	rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
 	if (rc == -EBUSY)
 		pcim_pin_device(pdev);
 	if (rc)
 		return rc;
 	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 	    (pdev->device == 0x2652 || pdev->device == 0x2653)) {
 		u8 map;
 		/* ICH6s share the same PCI ID for both piix and ahci
 		 * modes.  Enabling ahci mode while MAP indicates
 		 * combined mode is a bad idea.  Yield to ata_piix.
 		 */
 		pci_read_config_byte(pdev, ICH_MAP, &map);
 		if (map & 0x3) {
 			dev_printk(KERN_INFO, &pdev->dev, "controller is in "
 				   "combined mode, can't enable AHCI mode\n");
 			return -ENODEV;
 		}
 	}
 	hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
 	if (!hpriv)
 		return -ENOMEM;
 	hpriv->flags |= (unsigned long)pi.private_data;
 	/* MCP65 revision A1 and A2 can't do MSI */
 	if (board_id == board_ahci_mcp65 &&
 	    (pdev->revision == 0xa1 || pdev->revision == 0xa2))
 		hpriv->flags |= AHCI_HFLAG_NO_MSI;
 	/* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
 	if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
 		hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
 	/* only some SB600s can do 64bit DMA */
 	if (ahci_sb600_enable_64bit(pdev))
 		hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
 	if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
 		pci_intx(pdev, 1);
 	hpriv->mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
 	/* save initial config */
 	ahci_pci_save_initial_config(pdev, hpriv);
 	/* prepare host */
 	if (hpriv->cap & HOST_CAP_NCQ) {
 		pi.flags |= ATA_FLAG_NCQ;
 		/*
 		 * Auto-activate optimization is supposed to be
 		 * supported on all AHCI controllers indicating NCQ
 		 * capability, but it seems to be broken on some
 		 * chipsets including NVIDIAs.
 		 */
 		if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
 			pi.flags |= ATA_FLAG_FPDMA_AA;
 	}
 	if (hpriv->cap & HOST_CAP_PMP)
 		pi.flags |= ATA_FLAG_PMP;
 	ahci_set_em_messages(hpriv, &pi);
 	if (ahci_broken_system_poweroff(pdev)) {
 		pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
 		dev_info(&pdev->dev,
 			"quirky BIOS, skipping spindown on poweroff\n");
 	}
 	if (ahci_broken_suspend(pdev)) {
 		hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
 		dev_printk(KERN_WARNING, &pdev->dev,
 			   "BIOS update required for suspend/resume\n");
 	}
 	if (ahci_broken_online(pdev)) {
 		hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
 		dev_info(&pdev->dev,
 			 "online status unreliable, applying workaround\n");
 	}
 	/* CAP.NP sometimes indicate the index of the last enabled
 	 * port, at other times, that of the last possible port, so
 	 * determining the maximum port number requires looking at
 	 * both CAP.NP and port_map.
 	 */
 	n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
 	host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
 	if (!host)
 		return -ENOMEM;
 	host->private_data = hpriv;
 	if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
 		host->flags |= ATA_HOST_PARALLEL_SCAN;
 	else
 		printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
 	if (pi.flags & ATA_FLAG_EM)
 		ahci_reset_em(host);
 	for (i = 0; i < host->n_ports; i++) {
 		struct ata_port *ap = host->ports[i];
 		ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
 		ata_port_pbar_desc(ap, AHCI_PCI_BAR,
 				   0x100 + ap->port_no * 0x80, "port");
 		/* set initial link pm policy */
 		ap->pm_policy = NOT_AVAILABLE;
 		/* set enclosure management message type */
 		if (ap->flags & ATA_FLAG_EM)
 			ap->em_message_type = hpriv->em_msg_type;
 		/* disabled/not-implemented port */
 		if (!(hpriv->port_map & (1 << i)))
 			ap->ops = &ata_dummy_port_ops;
 	}
 	/* apply workaround for ASUS P5W DH Deluxe mainboard */
 	ahci_p5wdh_workaround(host);
 	/* apply gtf filter quirk */
 	ahci_gtf_filter_workaround(host);
 	/* initialize adapter */
 	rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
 	if (rc)
 		return rc;
 	rc = ahci_pci_reset_controller(host);
 	if (rc)
 		return rc;
 	ahci_pci_init_controller(host);
 	ahci_pci_print_info(host);
 	pci_set_master(pdev);
 	return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
 				 &ahci_sht);
 }
 static int __init ahci_init(void)
 {
 	return pci_register_driver(&ahci_pci_driver);
 }
 static void __exit ahci_exit(void)
 {
 	pci_unregister_driver(&ahci_pci_driver);
 }
 MODULE_AUTHOR("Jeff Garzik");
 MODULE_DESCRIPTION("AHCI SATA low-level driver");
 MODULE_LICENSE("GPL");
 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
 MODULE_VERSION(DRV_VERSION);
 module_init(ahci_init);
 module_exit(ahci_exit);

drivers/ata/ata_piix.c

Diff comments View file @ df423dc

 /*
  *    ata_piix.c - Intel PATA/SATA controllers
  *
  *    Maintained by:  Jeff Garzik <jgarzik@pobox.com>
  *    		    Please ALWAYS copy linux-ide@vger.kernel.org
  *		    on emails.
  *
  *
  *	Copyright 2003-2005 Red Hat Inc
  *	Copyright 2003-2005 Jeff Garzik
  *
  *
  *	Copyright header from piix.c:
  *
  *  Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
  *  Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
  *  Copyright (C) 2003 Red Hat Inc
  *
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
  *  the Free Software Foundation; either version 2, or (at your option)
  *  any later version.
  *
  *  This program is distributed in the hope that it will be useful,
  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  *  GNU General Public License for more details.
  *
  *  You should have received a copy of the GNU General Public License
  *  along with this program; see the file COPYING.  If not, write to
  *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  *
  *
  *  libata documentation is available via 'make {ps|pdf}docs',
  *  as Documentation/DocBook/libata.*
  *
  *  Hardware documentation available at http://developer.intel.com/
  *
  * Documentation
  *	Publically available from Intel web site. Errata documentation
  * is also publically available. As an aide to anyone hacking on this
  * driver the list of errata that are relevant is below, going back to
  * PIIX4. Older device documentation is now a bit tricky to find.
  *
  * The chipsets all follow very much the same design. The original Triton
  * series chipsets do _not_ support independant device timings, but this
  * is fixed in Triton II. With the odd mobile exception the chips then
  * change little except in gaining more modes until SATA arrives. This
  * driver supports only the chips with independant timing (that is those
  * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
  * for the early chip drivers.
  *
  * Errata of note:
  *
  * Unfixable
  *	PIIX4    errata #9	- Only on ultra obscure hw
  *	ICH3	 errata #13     - Not observed to affect real hw
  *				  by Intel
  *
  * Things we must deal with
  *	PIIX4	errata #10	- BM IDE hang with non UDMA
  *				  (must stop/start dma to recover)
  *	440MX   errata #15	- As PIIX4 errata #10
  *	PIIX4	errata #15	- Must not read control registers
  * 				  during a PIO transfer
  *	440MX   errata #13	- As PIIX4 errata #15
  *	ICH2	errata #21	- DMA mode 0 doesn't work right
  *	ICH0/1  errata #55	- As ICH2 errata #21
  *	ICH2	spec c #9	- Extra operations needed to handle
  *				  drive hotswap [NOT YET SUPPORTED]
  *	ICH2    spec c #20	- IDE PRD must not cross a 64K boundary
  *				  and must be dword aligned
  *	ICH2    spec c #24	- UDMA mode 4,5 t85/86 should be 6ns not 3.3
  *	ICH7	errata #16	- MWDMA1 timings are incorrect
  *
  * Should have been BIOS fixed:
  *	450NX:	errata #19	- DMA hangs on old 450NX
  *	450NX:  errata #20	- DMA hangs on old 450NX
  *	450NX:  errata #25	- Corruption with DMA on old 450NX
  *	ICH3    errata #15      - IDE deadlock under high load
  *				  (BIOS must set dev 31 fn 0 bit 23)
  *	ICH3	errata #18	- Don't use native mode
  */
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/pci.h>
 #include <linux/init.h>
 #include <linux/blkdev.h>
 #include <linux/delay.h>
 #include <linux/device.h>
 #include <linux/gfp.h>
 #include <scsi/scsi_host.h>
 #include <linux/libata.h>
 #include <linux/dmi.h>
 #define DRV_NAME	"ata_piix"
 #define DRV_VERSION	"2.13"
 enum {
 	PIIX_IOCFG		= 0x54, /* IDE I/O configuration register */
 	ICH5_PMR		= 0x90, /* port mapping register */
 	ICH5_PCS		= 0x92,	/* port control and status */
 	PIIX_SIDPR_BAR		= 5,
 	PIIX_SIDPR_LEN		= 16,
 	PIIX_SIDPR_IDX		= 0,
 	PIIX_SIDPR_DATA		= 4,
 	PIIX_FLAG_CHECKINTR	= (1 << 28), /* make sure PCI INTx enabled */
 	PIIX_FLAG_SIDPR		= (1 << 29), /* SATA idx/data pair regs */
 	PIIX_PATA_FLAGS		= ATA_FLAG_SLAVE_POSS,
 	PIIX_SATA_FLAGS		= ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR,
 	PIIX_80C_PRI		= (1 << 5) | (1 << 4),
 	PIIX_80C_SEC		= (1 << 7) | (1 << 6),
 	/* constants for mapping table */
 	P0			= 0,  /* port 0 */
 	P1			= 1,  /* port 1 */
 	P2			= 2,  /* port 2 */
 	P3			= 3,  /* port 3 */
 	IDE			= -1, /* IDE */
 	NA			= -2, /* not avaliable */
 	RV			= -3, /* reserved */
 	PIIX_AHCI_DEVICE	= 6,
 	/* host->flags bits */
 	PIIX_HOST_BROKEN_SUSPEND = (1 << 24),
 };
 enum piix_controller_ids {
 	/* controller IDs */
 	piix_pata_mwdma,	/* PIIX3 MWDMA only */
 	piix_pata_33,		/* PIIX4 at 33Mhz */
 	ich_pata_33,		/* ICH up to UDMA 33 only */
 	ich_pata_66,		/* ICH up to 66 Mhz */
 	ich_pata_100,		/* ICH up to UDMA 100 */
 	ich_pata_100_nomwdma1,	/* ICH up to UDMA 100 but with no MWDMA1*/
 	ich5_sata,
 	ich6_sata,
 	ich6m_sata,
 	ich8_sata,
 	ich8_2port_sata,
 	ich8m_apple_sata,	/* locks up on second port enable */
 	tolapai_sata,
 	piix_pata_vmw,			/* PIIX4 for VMware, spurious DMA_ERR */
 };
 struct piix_map_db {
 	const u32 mask;
 	const u16 port_enable;
 	const int map[][4];
 };
 struct piix_host_priv {
 	const int *map;
 	u32 saved_iocfg;
 	spinlock_t sidpr_lock;	/* FIXME: remove once locking in EH is fixed */
 	void __iomem *sidpr;
 };
 static int piix_init_one(struct pci_dev *pdev,
 			 const struct pci_device_id *ent);
 static void piix_remove_one(struct pci_dev *pdev);
 static int piix_pata_prereset(struct ata_link *link, unsigned long deadline);
 static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev);
 static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev);
 static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev);
 static int ich_pata_cable_detect(struct ata_port *ap);
 static u8 piix_vmw_bmdma_status(struct ata_port *ap);
 static int piix_sidpr_scr_read(struct ata_link *link,
 			       unsigned int reg, u32 *val);
 static int piix_sidpr_scr_write(struct ata_link *link,
 				unsigned int reg, u32 val);
 static bool piix_irq_check(struct ata_port *ap);
 #ifdef CONFIG_PM
 static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
 static int piix_pci_device_resume(struct pci_dev *pdev);
 #endif
 static unsigned int in_module_init = 1;
 static const struct pci_device_id piix_pci_tbl[] = {
 	/* Intel PIIX3 for the 430HX etc */
 	{ 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma },
 	/* VMware ICH4 */
 	{ 0x8086, 0x7111, 0x15ad, 0x1976, 0, 0, piix_pata_vmw },
 	/* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
 	/* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
 	{ 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
 	/* Intel PIIX4 */
 	{ 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
 	/* Intel PIIX4 */
 	{ 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
 	/* Intel PIIX */
 	{ 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
 	/* Intel ICH (i810, i815, i840) UDMA 66*/
 	{ 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 },
 	/* Intel ICH0 : UDMA 33*/
 	{ 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 },
 	/* Intel ICH2M */
 	{ 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
 	/* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
 	{ 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
 	/*  Intel ICH3M */
 	{ 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
 	/* Intel ICH3 (E7500/1) UDMA 100 */
 	{ 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
 	/* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
 	{ 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
 	{ 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
 	/* Intel ICH5 */
 	{ 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
 	/* C-ICH (i810E2) */
 	{ 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
 	/* ESB (855GME/875P + 6300ESB) UDMA 100  */
 	{ 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
 	/* ICH6 (and 6) (i915) UDMA 100 */
 	{ 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
 	/* ICH7/7-R (i945, i975) UDMA 100*/
 	{ 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 },
 	{ 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 },
 	/* ICH8 Mobile PATA Controller */
 	{ 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
 	/* SATA ports */
 	/* 82801EB (ICH5) */
 	{ 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
 	/* 82801EB (ICH5) */
 	{ 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
 	/* 6300ESB (ICH5 variant with broken PCS present bits) */
 	{ 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
 	/* 6300ESB pretending RAID */
 	{ 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
 	/* 82801FB/FW (ICH6/ICH6W) */
 	{ 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
 	/* 82801FR/FRW (ICH6R/ICH6RW) */
 	{ 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
 	/* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented).
 	 * Attach iff the controller is in IDE mode. */
 	{ 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID,
 	  PCI_CLASS_STORAGE_IDE << 8, 0xffff00, ich6m_sata },
 	/* 82801GB/GR/GH (ICH7, identical to ICH6) */
 	{ 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
 	/* 2801GBM/GHM (ICH7M, identical to ICH6M) */
 	{ 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata },
 	/* Enterprise Southbridge 2 (631xESB/632xESB) */
 	{ 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
 	/* SATA Controller 1 IDE (ICH8) */
 	{ 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
 	/* SATA Controller 2 IDE (ICH8) */
 	{ 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 	/* Mobile SATA Controller IDE (ICH8M), Apple */
 	{ 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata },
 	{ 0x8086, 0x2828, 0x106b, 0x00a1, 0, 0, ich8m_apple_sata },
 	{ 0x8086, 0x2828, 0x106b, 0x00a3, 0, 0, ich8m_apple_sata },
 	/* Mobile SATA Controller IDE (ICH8M) */
 	{ 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
 	/* SATA Controller IDE (ICH9) */
 	{ 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
 	/* SATA Controller IDE (ICH9) */
 	{ 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 	/* SATA Controller IDE (ICH9) */
 	{ 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 	/* SATA Controller IDE (ICH9M) */
 	{ 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 	/* SATA Controller IDE (ICH9M) */
 	{ 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 	/* SATA Controller IDE (ICH9M) */
 	{ 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
 	/* SATA Controller IDE (Tolapai) */
 	{ 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata },
 	/* SATA Controller IDE (ICH10) */
 	{ 0x8086, 0x3a00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
 	/* SATA Controller IDE (ICH10) */
 	{ 0x8086, 0x3a06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 	/* SATA Controller IDE (ICH10) */
 	{ 0x8086, 0x3a20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
 	/* SATA Controller IDE (ICH10) */
 	{ 0x8086, 0x3a26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 	/* SATA Controller IDE (PCH) */
 	{ 0x8086, 0x3b20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
 	/* SATA Controller IDE (PCH) */
 	{ 0x8086, 0x3b21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 	/* SATA Controller IDE (PCH) */
 	{ 0x8086, 0x3b26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 	/* SATA Controller IDE (PCH) */
 	{ 0x8086, 0x3b28, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
 	/* SATA Controller IDE (PCH) */
 	{ 0x8086, 0x3b2d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 	/* SATA Controller IDE (PCH) */
 	{ 0x8086, 0x3b2e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
 	/* SATA Controller IDE (CPT) */
 	{ 0x8086, 0x1c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
 	/* SATA Controller IDE (CPT) */
 	{ 0x8086, 0x1c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
 	/* SATA Controller IDE (CPT) */
 	{ 0x8086, 0x1c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 	/* SATA Controller IDE (CPT) */
 	{ 0x8086, 0x1c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
+	/* SATA Controller IDE (PBG) */
+	{ 0x8086, 0x1d00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
+	/* SATA Controller IDE (PBG) */
+	{ 0x8086, 0x1d08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 	{ }	/* terminate list */
 };
 static struct pci_driver piix_pci_driver = {
 	.name			= DRV_NAME,
 	.id_table		= piix_pci_tbl,
 	.probe			= piix_init_one,
 	.remove			= piix_remove_one,
 #ifdef CONFIG_PM
 	.suspend		= piix_pci_device_suspend,
 	.resume			= piix_pci_device_resume,
 #endif
 };
 static struct scsi_host_template piix_sht = {
 	ATA_BMDMA_SHT(DRV_NAME),
 };
 static struct ata_port_operations piix_sata_ops = {
 	.inherits		= &ata_bmdma32_port_ops,
 	.sff_irq_check		= piix_irq_check,
 };
 static struct ata_port_operations piix_pata_ops = {
 	.inherits		= &piix_sata_ops,
 	.cable_detect		= ata_cable_40wire,
 	.set_piomode		= piix_set_piomode,
 	.set_dmamode		= piix_set_dmamode,
 	.prereset		= piix_pata_prereset,
 };
 static struct ata_port_operations piix_vmw_ops = {
 	.inherits		= &piix_pata_ops,
 	.bmdma_status		= piix_vmw_bmdma_status,
 };
 static struct ata_port_operations ich_pata_ops = {
 	.inherits		= &piix_pata_ops,
 	.cable_detect		= ich_pata_cable_detect,
 	.set_dmamode		= ich_set_dmamode,
 };
 static struct ata_port_operations piix_sidpr_sata_ops = {
 	.inherits		= &piix_sata_ops,
 	.hardreset		= sata_std_hardreset,
 	.scr_read		= piix_sidpr_scr_read,
 	.scr_write		= piix_sidpr_scr_write,
 };
 static const struct piix_map_db ich5_map_db = {
 	.mask = 0x7,
 	.port_enable = 0x3,
 	.map = {
 		/* PM   PS   SM   SS       MAP  */
 		{  P0,  NA,  P1,  NA }, /* 000b */
 		{  P1,  NA,  P0,  NA }, /* 001b */
 		{  RV,  RV,  RV,  RV },
 		{  RV,  RV,  RV,  RV },
 		{  P0,  P1, IDE, IDE }, /* 100b */
 		{  P1,  P0, IDE, IDE }, /* 101b */
 		{ IDE, IDE,  P0,  P1 }, /* 110b */
 		{ IDE, IDE,  P1,  P0 }, /* 111b */
 	},
 };
 static const struct piix_map_db ich6_map_db = {
 	.mask = 0x3,
 	.port_enable = 0xf,
 	.map = {
 		/* PM   PS   SM   SS       MAP */
 		{  P0,  P2,  P1,  P3 }, /* 00b */
 		{ IDE, IDE,  P1,  P3 }, /* 01b */
 		{  P0,  P2, IDE, IDE }, /* 10b */
 		{  RV,  RV,  RV,  RV },
 	},
 };
 static const struct piix_map_db ich6m_map_db = {
 	.mask = 0x3,
 	.port_enable = 0x5,
 	/* Map 01b isn't specified in the doc but some notebooks use
 	 * it anyway.  MAP 01b have been spotted on both ICH6M and
 	 * ICH7M.
 	 */
 	.map = {
 		/* PM   PS   SM   SS       MAP */
 		{  P0,  P2,  NA,  NA }, /* 00b */
 		{ IDE, IDE,  P1,  P3 }, /* 01b */
 		{  P0,  P2, IDE, IDE }, /* 10b */
 		{  RV,  RV,  RV,  RV },
 	},
 };
 static const struct piix_map_db ich8_map_db = {
 	.mask = 0x3,
 	.port_enable = 0xf,
 	.map = {
 		/* PM   PS   SM   SS       MAP */
 		{  P0,  P2,  P1,  P3 }, /* 00b (hardwired when in AHCI) */
 		{  RV,  RV,  RV,  RV },
 		{  P0,  P2, IDE, IDE }, /* 10b (IDE mode) */
 		{  RV,  RV,  RV,  RV },
 	},
 };
 static const struct piix_map_db ich8_2port_map_db = {
 	.mask = 0x3,
 	.port_enable = 0x3,
 	.map = {
 		/* PM   PS   SM   SS       MAP */
 		{  P0,  NA,  P1,  NA }, /* 00b */
 		{  RV,  RV,  RV,  RV }, /* 01b */
 		{  RV,  RV,  RV,  RV }, /* 10b */
 		{  RV,  RV,  RV,  RV },
 	},
 };
 static const struct piix_map_db ich8m_apple_map_db = {
 	.mask = 0x3,
 	.port_enable = 0x1,
 	.map = {
 		/* PM   PS   SM   SS       MAP */
 		{  P0,  NA,  NA,  NA }, /* 00b */
 		{  RV,  RV,  RV,  RV },
 		{  P0,  P2, IDE, IDE }, /* 10b */
 		{  RV,  RV,  RV,  RV },
 	},
 };
 static const struct piix_map_db tolapai_map_db = {
 	.mask = 0x3,
 	.port_enable = 0x3,
 	.map = {
 		/* PM   PS   SM   SS       MAP */
 		{  P0,  NA,  P1,  NA }, /* 00b */
 		{  RV,  RV,  RV,  RV }, /* 01b */
 		{  RV,  RV,  RV,  RV }, /* 10b */
 		{  RV,  RV,  RV,  RV },
 	},
 };
 static const struct piix_map_db *piix_map_db_table[] = {
 	[ich5_sata]		= &ich5_map_db,
 	[ich6_sata]		= &ich6_map_db,
 	[ich6m_sata]		= &ich6m_map_db,
 	[ich8_sata]		= &ich8_map_db,
 	[ich8_2port_sata]	= &ich8_2port_map_db,
 	[ich8m_apple_sata]	= &ich8m_apple_map_db,
 	[tolapai_sata]		= &tolapai_map_db,
 };
 static struct ata_port_info piix_port_info[] = {
 	[piix_pata_mwdma] = 	/* PIIX3 MWDMA only */
 	{
 		.flags		= PIIX_PATA_FLAGS,
 		.pio_mask	= ATA_PIO4,
 		.mwdma_mask	= ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
 		.port_ops	= &piix_pata_ops,
 	},
 	[piix_pata_33] =	/* PIIX4 at 33MHz */
 	{
 		.flags		= PIIX_PATA_FLAGS,
 		.pio_mask	= ATA_PIO4,
 		.mwdma_mask	= ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
 		.udma_mask	= ATA_UDMA2,
 		.port_ops	= &piix_pata_ops,
 	},
 	[ich_pata_33] = 	/* ICH0 - ICH at 33Mhz*/
 	{
 		.flags		= PIIX_PATA_FLAGS,
 		.pio_mask 	= ATA_PIO4,
 		.mwdma_mask	= ATA_MWDMA12_ONLY, /* Check: maybe MWDMA0 is ok  */
 		.udma_mask	= ATA_UDMA2,
 		.port_ops	= &ich_pata_ops,
 	},
 	[ich_pata_66] = 	/* ICH controllers up to 66MHz */
 	{
 		.flags		= PIIX_PATA_FLAGS,
 		.pio_mask 	= ATA_PIO4,
 		.mwdma_mask	= ATA_MWDMA12_ONLY, /* MWDMA0 is broken on chip */
 		.udma_mask	= ATA_UDMA4,
 		.port_ops	= &ich_pata_ops,
 	},
 	[ich_pata_100] =
 	{
 		.flags		= PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
 		.pio_mask	= ATA_PIO4,
 		.mwdma_mask	= ATA_MWDMA12_ONLY,
 		.udma_mask	= ATA_UDMA5,
 		.port_ops	= &ich_pata_ops,
 	},
 	[ich_pata_100_nomwdma1] =
 	{
 		.flags		= PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
 		.pio_mask	= ATA_PIO4,
 		.mwdma_mask	= ATA_MWDMA2_ONLY,
 		.udma_mask	= ATA_UDMA5,
 		.port_ops	= &ich_pata_ops,
 	},
 	[ich5_sata] =
 	{
 		.flags		= PIIX_SATA_FLAGS,
 		.pio_mask	= ATA_PIO4,
 		.mwdma_mask	= ATA_MWDMA2,
 		.udma_mask	= ATA_UDMA6,
 		.port_ops	= &piix_sata_ops,
 	},
 	[ich6_sata] =
 	{
 		.flags		= PIIX_SATA_FLAGS,
 		.pio_mask	= ATA_PIO4,
 		.mwdma_mask	= ATA_MWDMA2,
 		.udma_mask	= ATA_UDMA6,
 		.port_ops	= &piix_sata_ops,
 	},
 	[ich6m_sata] =
 	{
 		.flags		= PIIX_SATA_FLAGS,
 		.pio_mask	= ATA_PIO4,
 		.mwdma_mask	= ATA_MWDMA2,
 		.udma_mask	= ATA_UDMA6,
 		.port_ops	= &piix_sata_ops,
 	},
 	[ich8_sata] =
 	{
 		.flags		= PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
 		.pio_mask	= ATA_PIO4,
 		.mwdma_mask	= ATA_MWDMA2,
 		.udma_mask	= ATA_UDMA6,
 		.port_ops	= &piix_sata_ops,
 	},
 	[ich8_2port_sata] =
 	{
 		.flags		= PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
 		.pio_mask	= ATA_PIO4,
 		.mwdma_mask	= ATA_MWDMA2,
 		.udma_mask	= ATA_UDMA6,
 		.port_ops	= &piix_sata_ops,
 	},
 	[tolapai_sata] =
 	{
 		.flags		= PIIX_SATA_FLAGS,
 		.pio_mask	= ATA_PIO4,
 		.mwdma_mask	= ATA_MWDMA2,
 		.udma_mask	= ATA_UDMA6,
 		.port_ops	= &piix_sata_ops,
 	},
 	[ich8m_apple_sata] =
 	{
 		.flags		= PIIX_SATA_FLAGS,
 		.pio_mask	= ATA_PIO4,
 		.mwdma_mask	= ATA_MWDMA2,
 		.udma_mask	= ATA_UDMA6,
 		.port_ops	= &piix_sata_ops,
 	},
 	[piix_pata_vmw] =
 	{
 		.flags		= PIIX_PATA_FLAGS,
 		.pio_mask	= ATA_PIO4,
 		.mwdma_mask	= ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
 		.udma_mask	= ATA_UDMA2,
 		.port_ops	= &piix_vmw_ops,
 	},
 };
 static struct pci_bits piix_enable_bits[] = {
 	{ 0x41U, 1U, 0x80UL, 0x80UL },	/* port 0 */
 	{ 0x43U, 1U, 0x80UL, 0x80UL },	/* port 1 */
 };
 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
 MODULE_LICENSE("GPL");
 MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
 MODULE_VERSION(DRV_VERSION);
 struct ich_laptop {
 	u16 device;
 	u16 subvendor;
 	u16 subdevice;
 };
 /*
  *	List of laptops that use short cables rather than 80 wire
  */
 static const struct ich_laptop ich_laptop[] = {
 	/* devid, subvendor, subdev */
 	{ 0x27DF, 0x0005, 0x0280 },	/* ICH7 on Acer 5602WLMi */
 	{ 0x27DF, 0x1025, 0x0102 },	/* ICH7 on Acer 5602aWLMi */
 	{ 0x27DF, 0x1025, 0x0110 },	/* ICH7 on Acer 3682WLMi */
 	{ 0x27DF, 0x1028, 0x02b0 },	/* ICH7 on unknown Dell */
 	{ 0x27DF, 0x1043, 0x1267 },	/* ICH7 on Asus W5F */
 	{ 0x27DF, 0x103C, 0x30A1 },	/* ICH7 on HP Compaq nc2400 */
 	{ 0x27DF, 0x103C, 0x361a },	/* ICH7 on unknown HP  */
 	{ 0x27DF, 0x1071, 0xD221 },	/* ICH7 on Hercules EC-900 */
 	{ 0x27DF, 0x152D, 0x0778 },	/* ICH7 on unknown Intel */
 	{ 0x24CA, 0x1025, 0x0061 },	/* ICH4 on ACER Aspire 2023WLMi */
 	{ 0x24CA, 0x1025, 0x003d },	/* ICH4 on ACER TM290 */
 	{ 0x266F, 0x1025, 0x0066 },	/* ICH6 on ACER Aspire 1694WLMi */
 	{ 0x2653, 0x1043, 0x82D8 },	/* ICH6M on Asus Eee 701 */
 	{ 0x27df, 0x104d, 0x900e },	/* ICH7 on Sony TZ-90 */
 	/* end marker */
 	{ 0, }
 };
 /**
  *	ich_pata_cable_detect - Probe host controller cable detect info
  *	@ap: Port for which cable detect info is desired
  *
  *	Read 80c cable indicator from ATA PCI device's PCI config
  *	register.  This register is normally set by firmware (BIOS).
  *
  *	LOCKING:
  *	None (inherited from caller).
  */
 static int ich_pata_cable_detect(struct ata_port *ap)
 {
 	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 	struct piix_host_priv *hpriv = ap->host->private_data;
 	const struct ich_laptop *lap = &ich_laptop[0];
 	u8 mask;
 	/* Check for specials - Acer Aspire 5602WLMi */
 	while (lap->device) {
 		if (lap->device == pdev->device &&
 		    lap->subvendor == pdev->subsystem_vendor &&
 		    lap->subdevice == pdev->subsystem_device)
 			return ATA_CBL_PATA40_SHORT;
 		lap++;
 	}
 	/* check BIOS cable detect results */
 	mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
 	if ((hpriv->saved_iocfg & mask) == 0)
 		return ATA_CBL_PATA40;
 	return ATA_CBL_PATA80;
 }
 /**
  *	piix_pata_prereset - prereset for PATA host controller
  *	@link: Target link
  *	@deadline: deadline jiffies for the operation
  *
  *	LOCKING:
  *	None (inherited from caller).
  */
 static int piix_pata_prereset(struct ata_link *link, unsigned long deadline)
 {
 	struct ata_port *ap = link->ap;
 	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 	if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no]))
 		return -ENOENT;
 	return ata_sff_prereset(link, deadline);
 }
 static DEFINE_SPINLOCK(piix_lock);
 /**
  *	piix_set_piomode - Initialize host controller PATA PIO timings
  *	@ap: Port whose timings we are configuring
  *	@adev: um
  *
  *	Set PIO mode for device, in host controller PCI config space.
  *
  *	LOCKING:
  *	None (inherited from caller).
  */
 static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev)
 {
 	struct pci_dev *dev	= to_pci_dev(ap->host->dev);
 	unsigned long flags;
 	unsigned int pio	= adev->pio_mode - XFER_PIO_0;
 	unsigned int is_slave	= (adev->devno != 0);
 	unsigned int master_port= ap->port_no ? 0x42 : 0x40;
 	unsigned int slave_port	= 0x44;
 	u16 master_data;
 	u8 slave_data;
 	u8 udma_enable;
 	int control = 0;
 	/*
 	 *	See Intel Document 298600-004 for the timing programing rules
 	 *	for ICH controllers.
 	 */
 	static const	 /* ISP  RTC */
 	u8 timings[][2]	= { { 0, 0 },
 			    { 0, 0 },
 			    { 1, 0 },
 			    { 2, 1 },
 			    { 2, 3 }, };
 	if (pio >= 2)
 		control |= 1;	/* TIME1 enable */
 	if (ata_pio_need_iordy(adev))
 		control |= 2;	/* IE enable */
 	/* Intel specifies that the PPE functionality is for disk only */
 	if (adev->class == ATA_DEV_ATA)
 		control |= 4;	/* PPE enable */
 	spin_lock_irqsave(&piix_lock, flags);
 	/* PIO configuration clears DTE unconditionally.  It will be
 	 * programmed in set_dmamode which is guaranteed to be called
 	 * after set_piomode if any DMA mode is available.
 	 */
 	pci_read_config_word(dev, master_port, &master_data);
 	if (is_slave) {
 		/* clear TIME1|IE1|PPE1|DTE1 */
 		master_data &= 0xff0f;
 		/* Enable SITRE (separate slave timing register) */
 		master_data |= 0x4000;
 		/* enable PPE1, IE1 and TIME1 as needed */
 		master_data |= (control << 4);
 		pci_read_config_byte(dev, slave_port, &slave_data);
 		slave_data &= (ap->port_no ? 0x0f : 0xf0);
 		/* Load the timing nibble for this slave */
 		slave_data |= ((timings[pio][0] << 2) | timings[pio][1])
 						<< (ap->port_no ? 4 : 0);
 	} else {
 		/* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */
 		master_data &= 0xccf0;
 		/* Enable PPE, IE and TIME as appropriate */
 		master_data |= control;
 		/* load ISP and RCT */
 		master_data |=
 			(timings[pio][0] << 12) |
 			(timings[pio][1] << 8);
 	}
 	pci_write_config_word(dev, master_port, master_data);
 	if (is_slave)
 		pci_write_config_byte(dev, slave_port, slave_data);
 	/* Ensure the UDMA bit is off - it will be turned back on if
 	   UDMA is selected */
 	if (ap->udma_mask) {
 		pci_read_config_byte(dev, 0x48, &udma_enable);
 		udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
 		pci_write_config_byte(dev, 0x48, udma_enable);
 	}
 	spin_unlock_irqrestore(&piix_lock, flags);
 }
 /**
  *	do_pata_set_dmamode - Initialize host controller PATA PIO timings
  *	@ap: Port whose timings we are configuring
  *	@adev: Drive in question
  *	@isich: set if the chip is an ICH device
  *
  *	Set UDMA mode for device, in host controller PCI config space.
  *
  *	LOCKING:
  *	None (inherited from caller).
  */
 static void do_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev, int isich)
 {
 	struct pci_dev *dev	= to_pci_dev(ap->host->dev);
 	unsigned long flags;
 	u8 master_port		= ap->port_no ? 0x42 : 0x40;
 	u16 master_data;
 	u8 speed		= adev->dma_mode;
 	int devid		= adev->devno + 2 * ap->port_no;
 	u8 udma_enable		= 0;
 	static const	 /* ISP  RTC */
 	u8 timings[][2]	= { { 0, 0 },
 			    { 0, 0 },
 			    { 1, 0 },
 			    { 2, 1 },
 			    { 2, 3 }, };
 	spin_lock_irqsave(&piix_lock, flags);
 	pci_read_config_word(dev, master_port, &master_data);
 	if (ap->udma_mask)
 		pci_read_config_byte(dev, 0x48, &udma_enable);
 	if (speed >= XFER_UDMA_0) {
 		unsigned int udma = adev->dma_mode - XFER_UDMA_0;
 		u16 udma_timing;
 		u16 ideconf;
 		int u_clock, u_speed;
 		/*
 		 * UDMA is handled by a combination of clock switching and
 		 * selection of dividers
 		 *
 		 * Handy rule: Odd modes are UDMATIMx 01, even are 02
 		 *	       except UDMA0 which is 00
 		 */
 		u_speed = min(2 - (udma & 1), udma);
 		if (udma == 5)
 			u_clock = 0x1000;	/* 100Mhz */
 		else if (udma > 2)
 			u_clock = 1;		/* 66Mhz */
 		else
 			u_clock = 0;		/* 33Mhz */
 		udma_enable |= (1 << devid);
 		/* Load the CT/RP selection */
 		pci_read_config_word(dev, 0x4A, &udma_timing);
 		udma_timing &= ~(3 << (4 * devid));
 		udma_timing |= u_speed << (4 * devid);
 		pci_write_config_word(dev, 0x4A, udma_timing);
 		if (isich) {
 			/* Select a 33/66/100Mhz clock */
 			pci_read_config_word(dev, 0x54, &ideconf);
 			ideconf &= ~(0x1001 << devid);
 			ideconf |= u_clock << devid;
 			/* For ICH or later we should set bit 10 for better
 			   performance (WR_PingPong_En) */
 			pci_write_config_word(dev, 0x54, ideconf);
 		}
 	} else {
 		/*
 		 * MWDMA is driven by the PIO timings. We must also enable
 		 * IORDY unconditionally along with TIME1. PPE has already
 		 * been set when the PIO timing was set.
 		 */
 		unsigned int mwdma	= adev->dma_mode - XFER_MW_DMA_0;
 		unsigned int control;
 		u8 slave_data;
 		const unsigned int needed_pio[3] = {
 			XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
 		};
 		int pio = needed_pio[mwdma] - XFER_PIO_0;
 		control = 3;	/* IORDY|TIME1 */
 		/* If the drive MWDMA is faster than it can do PIO then
 		   we must force PIO into PIO0 */
 		if (adev->pio_mode < needed_pio[mwdma])
 			/* Enable DMA timing only */
 			control |= 8;	/* PIO cycles in PIO0 */
 		if (adev->devno) {	/* Slave */
 			master_data &= 0xFF4F;  /* Mask out IORDY|TIME1|DMAONLY */
 			master_data |= control << 4;
 			pci_read_config_byte(dev, 0x44, &slave_data);
 			slave_data &= (ap->port_no ? 0x0f : 0xf0);
 			/* Load the matching timing */
 			slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
 			pci_write_config_byte(dev, 0x44, slave_data);
 		} else { 	/* Master */
 			master_data &= 0xCCF4;	/* Mask out IORDY|TIME1|DMAONLY
 						   and master timing bits */
 			master_data |= control;
 			master_data |=
 				(timings[pio][0] << 12) |
 				(timings[pio][1] << 8);
 		}
 		if (ap->udma_mask)
 			udma_enable &= ~(1 << devid);
 		pci_write_config_word(dev, master_port, master_data);
 	}
 	/* Don't scribble on 0x48 if the controller does not support UDMA */
 	if (ap->udma_mask)
 		pci_write_config_byte(dev, 0x48, udma_enable);
 	spin_unlock_irqrestore(&piix_lock, flags);
 }
 /**
  *	piix_set_dmamode - Initialize host controller PATA DMA timings
  *	@ap: Port whose timings we are configuring
  *	@adev: um
  *
  *	Set MW/UDMA mode for device, in host controller PCI config space.
  *
  *	LOCKING:
  *	None (inherited from caller).
  */
 static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev)
 {
 	do_pata_set_dmamode(ap, adev, 0);
 }
 /**
  *	ich_set_dmamode - Initialize host controller PATA DMA timings
  *	@ap: Port whose timings we are configuring
  *	@adev: um
  *
  *	Set MW/UDMA mode for device, in host controller PCI config space.
  *
  *	LOCKING:
  *	None (inherited from caller).
  */
 static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev)
 {
 	do_pata_set_dmamode(ap, adev, 1);
 }
 /*
  * Serial ATA Index/Data Pair Superset Registers access
  *
  * Beginning from ICH8, there's a sane way to access SCRs using index
  * and data register pair located at BAR5 which means that we have
  * separate SCRs for master and slave.  This is handled using libata
  * slave_link facility.
  */
 static const int piix_sidx_map[] = {
 	[SCR_STATUS]	= 0,
 	[SCR_ERROR]	= 2,
 	[SCR_CONTROL]	= 1,
 };
 static void piix_sidpr_sel(struct ata_link *link, unsigned int reg)
 {
 	struct ata_port *ap = link->ap;
 	struct piix_host_priv *hpriv = ap->host->private_data;
 	iowrite32(((ap->port_no * 2 + link->pmp) << 8) | piix_sidx_map[reg],
 		  hpriv->sidpr + PIIX_SIDPR_IDX);
 }
 static int piix_sidpr_scr_read(struct ata_link *link,
 			       unsigned int reg, u32 *val)
 {
 	struct piix_host_priv *hpriv = link->ap->host->private_data;
 	unsigned long flags;
 	if (reg >= ARRAY_SIZE(piix_sidx_map))
 		return -EINVAL;
 	spin_lock_irqsave(&hpriv->sidpr_lock, flags);
 	piix_sidpr_sel(link, reg);
 	*val = ioread32(hpriv->sidpr + PIIX_SIDPR_DATA);
 	spin_unlock_irqrestore(&hpriv->sidpr_lock, flags);
 	return 0;
 }
 static int piix_sidpr_scr_write(struct ata_link *link,
 				unsigned int reg, u32 val)
 {
 	struct piix_host_priv *hpriv = link->ap->host->private_data;
 	unsigned long flags;
 	if (reg >= ARRAY_SIZE(piix_sidx_map))
 		return -EINVAL;
 	spin_lock_irqsave(&hpriv->sidpr_lock, flags);
 	piix_sidpr_sel(link, reg);
 	iowrite32(val, hpriv->sidpr + PIIX_SIDPR_DATA);
 	spin_unlock_irqrestore(&hpriv->sidpr_lock, flags);
 	return 0;
 }
 static bool piix_irq_check(struct ata_port *ap)
 {
 	if (unlikely(!ap->ioaddr.bmdma_addr))
 		return false;
 	return ap->ops->bmdma_status(ap) & ATA_DMA_INTR;
 }
 #ifdef CONFIG_PM
 static int piix_broken_suspend(void)
 {
 	static const struct dmi_system_id sysids[] = {
 		{
 			.ident = "TECRA M3",
 			.matches = {
 				DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 				DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"),
 			},
 		},
 		{
 			.ident = "TECRA M3",
 			.matches = {
 				DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 				DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M3"),
 			},
 		},
 		{
 			.ident = "TECRA M4",
 			.matches = {
 				DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 				DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M4"),
 			},
 		},
 		{
 			.ident = "TECRA M4",
 			.matches = {
 				DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 				DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M4"),
 			},
 		},
 		{
 			.ident = "TECRA M5",
 			.matches = {
 				DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 				DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"),
 			},
 		},
 		{
 			.ident = "TECRA M6",
 			.matches = {
 				DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 				DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M6"),
 			},
 		},
 		{
 			.ident = "TECRA M7",
 			.matches = {
 				DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 				DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"),
 			},
 		},
 		{
 			.ident = "TECRA A8",
 			.matches = {
 				DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 				DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A8"),
 			},
 		},
 		{
 			.ident = "Satellite R20",
 			.matches = {
 				DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 				DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R20"),
 			},
 		},
 		{
 			.ident = "Satellite R25",
 			.matches = {
 				DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 				DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R25"),
 			},
 		},
 		{
 			.ident = "Satellite U200",
 			.matches = {
 				DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 				DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"),
 			},
 		},
 		{
 			.ident = "Satellite U200",
 			.matches = {
 				DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 				DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U200"),
 			},
 		},
 		{
 			.ident = "Satellite Pro U200",
 			.matches = {
 				DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 				DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE PRO U200"),
 			},
 		},
 		{
 			.ident = "Satellite U205",
 			.matches = {
 				DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 				DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"),
 			},
 		},
 		{
 			.ident = "SATELLITE U205",
 			.matches = {
 				DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 				DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U205"),
 			},
 		},
 		{
 			.ident = "Portege M500",
 			.matches = {
 				DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 				DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"),
 			},
 		},
 		{
 			.ident = "VGN-BX297XP",
 			.matches = {
 				DMI_MATCH(DMI_SYS_VENDOR, "Sony Corporation"),
 				DMI_MATCH(DMI_PRODUCT_NAME, "VGN-BX297XP"),
 			},
 		},
 		{ }	/* terminate list */
 	};
 	static const char *oemstrs[] = {
 		"Tecra M3,",
 	};
 	int i;
 	if (dmi_check_system(sysids))
 		return 1;
 	for (i = 0; i < ARRAY_SIZE(oemstrs); i++)
 		if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL))
 			return 1;
 	/* TECRA M4 sometimes forgets its identify and reports bogus
 	 * DMI information.  As the bogus information is a bit
 	 * generic, match as many entries as possible.  This manual
 	 * matching is necessary because dmi_system_id.matches is
 	 * limited to four entries.
 	 */
 	if (dmi_match(DMI_SYS_VENDOR, "TOSHIBA") &&
 	    dmi_match(DMI_PRODUCT_NAME, "000000") &&
 	    dmi_match(DMI_PRODUCT_VERSION, "000000") &&
 	    dmi_match(DMI_PRODUCT_SERIAL, "000000") &&
 	    dmi_match(DMI_BOARD_VENDOR, "TOSHIBA") &&
 	    dmi_match(DMI_BOARD_NAME, "Portable PC") &&
 	    dmi_match(DMI_BOARD_VERSION, "Version A0"))
 		return 1;
 	return 0;
 }
 static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
 {
 	struct ata_host *host = dev_get_drvdata(&pdev->dev);
 	unsigned long flags;
 	int rc = 0;
 	rc = ata_host_suspend(host, mesg);
 	if (rc)
 		return rc;
 	/* Some braindamaged ACPI suspend implementations expect the
 	 * controller to be awake on entry; otherwise, it burns cpu
 	 * cycles and power trying to do something to the sleeping
 	 * beauty.
 	 */
 	if (piix_broken_suspend() && (mesg.event & PM_EVENT_SLEEP)) {
 		pci_save_state(pdev);
 		/* mark its power state as "unknown", since we don't
 		 * know if e.g. the BIOS will change its device state
 		 * when we suspend.
 		 */
 		if (pdev->current_state == PCI_D0)
 			pdev->current_state = PCI_UNKNOWN;
 		/* tell resume that it's waking up from broken suspend */
 		spin_lock_irqsave(&host->lock, flags);
 		host->flags |= PIIX_HOST_BROKEN_SUSPEND;
 		spin_unlock_irqrestore(&host->lock, flags);
 	} else
 		ata_pci_device_do_suspend(pdev, mesg);
 	return 0;
 }
 static int piix_pci_device_resume(struct pci_dev *pdev)
 {
 	struct ata_host *host = dev_get_drvdata(&pdev->dev);
 	unsigned long flags;
 	int rc;
 	if (host->flags & PIIX_HOST_BROKEN_SUSPEND) {
 		spin_lock_irqsave(&host->lock, flags);
 		host->flags &= ~PIIX_HOST_BROKEN_SUSPEND;
 		spin_unlock_irqrestore(&host->lock, flags);
 		pci_set_power_state(pdev, PCI_D0);
 		pci_restore_state(pdev);
 		/* PCI device wasn't disabled during suspend.  Use
 		 * pci_reenable_device() to avoid affecting the enable
 		 * count.
 		 */
 		rc = pci_reenable_device(pdev);
 		if (rc)
 			dev_printk(KERN_ERR, &pdev->dev, "failed to enable "
 				   "device after resume (%d)\n", rc);
 	} else
 		rc = ata_pci_device_do_resume(pdev);
 	if (rc == 0)
 		ata_host_resume(host);
 	return rc;
 }
 #endif
 static u8 piix_vmw_bmdma_status(struct ata_port *ap)
 {
 	return ata_bmdma_status(ap) & ~ATA_DMA_ERR;
 }
 #define AHCI_PCI_BAR 5
 #define AHCI_GLOBAL_CTL 0x04
 #define AHCI_ENABLE (1 << 31)
 static int piix_disable_ahci(struct pci_dev *pdev)
 {
 	void __iomem *mmio;
 	u32 tmp;
 	int rc = 0;
 	/* BUG: pci_enable_device has not yet been called.  This
 	 * works because this device is usually set up by BIOS.
 	 */
 	if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
 	    !pci_resource_len(pdev, AHCI_PCI_BAR))
 		return 0;
 	mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
 	if (!mmio)
 		return -ENOMEM;
 	tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
 	if (tmp & AHCI_ENABLE) {
 		tmp &= ~AHCI_ENABLE;
 		iowrite32(tmp, mmio + AHCI_GLOBAL_CTL);
 		tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
 		if (tmp & AHCI_ENABLE)
 			rc = -EIO;
 	}
 	pci_iounmap(pdev, mmio);
 	return rc;
 }
 /**
  *	piix_check_450nx_errata	-	Check for problem 450NX setup
  *	@ata_dev: the PCI device to check
  *
  *	Check for the present of 450NX errata #19 and errata #25. If
  *	they are found return an error code so we can turn off DMA
  */
 static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
 {
 	struct pci_dev *pdev = NULL;
 	u16 cfg;
 	int no_piix_dma = 0;
 	while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) {
 		/* Look for 450NX PXB. Check for problem configurations
 		   A PCI quirk checks bit 6 already */
 		pci_read_config_word(pdev, 0x41, &cfg);
 		/* Only on the original revision: IDE DMA can hang */
 		if (pdev->revision == 0x00)
 			no_piix_dma = 1;
 		/* On all revisions below 5 PXB bus lock must be disabled for IDE */
 		else if (cfg & (1<<14) && pdev->revision < 5)
 			no_piix_dma = 2;
 	}
 	if (no_piix_dma)
 		dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n");
 	if (no_piix_dma == 2)
 		dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n");
 	return no_piix_dma;
 }
 static void __devinit piix_init_pcs(struct ata_host *host,
 				    const struct piix_map_db *map_db)
 {
 	struct pci_dev *pdev = to_pci_dev(host->dev);
 	u16 pcs, new_pcs;
 	pci_read_config_word(pdev, ICH5_PCS, &pcs);
 	new_pcs = pcs | map_db->port_enable;
 	if (new_pcs != pcs) {
 		DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
 		pci_write_config_word(pdev, ICH5_PCS, new_pcs);
 		msleep(150);
 	}
 }
 static const int *__devinit piix_init_sata_map(struct pci_dev *pdev,
 					       struct ata_port_info *pinfo,
 					       const struct piix_map_db *map_db)
 {
 	const int *map;
 	int i, invalid_map = 0;
 	u8 map_value;
 	pci_read_config_byte(pdev, ICH5_PMR, &map_value);
 	map = map_db->map[map_value & map_db->mask];
 	dev_printk(KERN_INFO, &pdev->dev, "MAP [");
 	for (i = 0; i < 4; i++) {
 		switch (map[i]) {
 		case RV:
 			invalid_map = 1;
 			printk(" XX");
 			break;
 		case NA:
 			printk(" --");
 			break;
 		case IDE:
 			WARN_ON((i & 1) || map[i + 1] != IDE);
 			pinfo[i / 2] = piix_port_info[ich_pata_100];
 			i++;
 			printk(" IDE IDE");
 			break;
 		default:
 			printk(" P%d", map[i]);
 			if (i & 1)
 				pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS;
 			break;
 		}
 	}
 	printk(" ]\n");
 	if (invalid_map)
 		dev_printk(KERN_ERR, &pdev->dev,
 			   "invalid MAP value %u\n", map_value);
 	return map;
 }
 static bool piix_no_sidpr(struct ata_host *host)
 {
 	struct pci_dev *pdev = to_pci_dev(host->dev);
 	/*
 	 * Samsung DB-P70 only has three ATA ports exposed and
 	 * curiously the unconnected first port reports link online
 	 * while not responding to SRST protocol causing excessive
 	 * detection delay.
 	 *
 	 * Unfortunately, the system doesn't carry enough DMI
 	 * information to identify the machine but does have subsystem
 	 * vendor and device set.  As it's unclear whether the
 	 * subsystem vendor/device is used only for this specific
 	 * board, the port can't be disabled solely with the
 	 * information; however, turning off SIDPR access works around
 	 * the problem.  Turn it off.
 	 *
 	 * This problem is reported in bnc#441240.
 	 *
 	 * https://bugzilla.novell.com/show_bug.cgi?id=441420
 	 */
 	if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2920 &&
 	    pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG &&
 	    pdev->subsystem_device == 0xb049) {
 		dev_printk(KERN_WARNING, host->dev,
 			   "Samsung DB-P70 detected, disabling SIDPR\n");
 		return true;
 	}
 	return false;
 }
 static int __devinit piix_init_sidpr(struct ata_host *host)
 {
 	struct pci_dev *pdev = to_pci_dev(host->dev);
 	struct piix_host_priv *hpriv = host->private_data;
 	struct ata_link *link0 = &host->ports[0]->link;
 	u32 scontrol;
 	int i, rc;
 	/* check for availability */
 	for (i = 0; i < 4; i++)
 		if (hpriv->map[i] == IDE)
 			return 0;
 	/* is it blacklisted? */
 	if (piix_no_sidpr(host))
 		return 0;
 	if (!(host->ports[0]->flags & PIIX_FLAG_SIDPR))
 		return 0;
 	if (pci_resource_start(pdev, PIIX_SIDPR_BAR) == 0 ||
 	    pci_resource_len(pdev, PIIX_SIDPR_BAR) != PIIX_SIDPR_LEN)
 		return 0;
 	if (pcim_iomap_regions(pdev, 1 << PIIX_SIDPR_BAR, DRV_NAME))
 		return 0;
 	hpriv->sidpr = pcim_iomap_table(pdev)[PIIX_SIDPR_BAR];
 	/* SCR access via SIDPR doesn't work on some configurations.
 	 * Give it a test drive by inhibiting power save modes which
 	 * we'll do anyway.
 	 */
 	piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol);
 	/* if IPM is already 3, SCR access is probably working.  Don't
 	 * un-inhibit power save modes as BIOS might have inhibited
 	 * them for a reason.
 	 */
 	if ((scontrol & 0xf00) != 0x300) {
 		scontrol |= 0x300;
 		piix_sidpr_scr_write(link0, SCR_CONTROL, scontrol);
 		piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol);
 		if ((scontrol & 0xf00) != 0x300) {
 			dev_printk(KERN_INFO, host->dev, "SCR access via "
 				   "SIDPR is available but doesn't work\n");
 			return 0;
 		}
 	}
 	/* okay, SCRs available, set ops and ask libata for slave_link */
 	for (i = 0; i < 2; i++) {
 		struct ata_port *ap = host->ports[i];
 		ap->ops = &piix_sidpr_sata_ops;
 		if (ap->flags & ATA_FLAG_SLAVE_POSS) {
 			rc = ata_slave_link_init(ap);
 			if (rc)
 				return rc;
 		}
 	}
 	return 0;
 }
 static void piix_iocfg_bit18_quirk(struct ata_host *host)
 {
 	static const struct dmi_system_id sysids[] = {
 		{
 			/* Clevo M570U sets IOCFG bit 18 if the cdrom
 			 * isn't used to boot the system which
 			 * disables the channel.
 			 */
 			.ident = "M570U",
 			.matches = {
 				DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."),
 				DMI_MATCH(DMI_PRODUCT_NAME, "M570U"),
 			},
 		},
 		{ }	/* terminate list */
 	};
 	struct pci_dev *pdev = to_pci_dev(host->dev);
 	struct piix_host_priv *hpriv = host->private_data;
 	if (!dmi_check_system(sysids))
 		return;
 	/* The datasheet says that bit 18 is NOOP but certain systems
 	 * seem to use it to disable a channel.  Clear the bit on the
 	 * affected systems.
 	 */
 	if (hpriv->saved_iocfg & (1 << 18)) {
 		dev_printk(KERN_INFO, &pdev->dev,
 			   "applying IOCFG bit18 quirk\n");
 		pci_write_config_dword(pdev, PIIX_IOCFG,
 				       hpriv->saved_iocfg & ~(1 << 18));
 	}
 }
 static bool piix_broken_system_poweroff(struct pci_dev *pdev)
 {
 	static const struct dmi_system_id broken_systems[] = {
 		{
 			.ident = "HP Compaq 2510p",
 			.matches = {
 				DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
 				DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 2510p"),
 			},
 			/* PCI slot number of the controller */
 			.driver_data = (void *)0x1FUL,
 		},
 		{
 			.ident = "HP Compaq nc6000",
 			.matches = {
 				DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
 				DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nc6000"),
 			},
 			/* PCI slot number of the controller */
 			.driver_data = (void *)0x1FUL,
 		},
 		{ }	/* terminate list */
 	};
 	const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
 	if (dmi) {
 		unsigned long slot = (unsigned long)dmi->driver_data;
 		/* apply the quirk only to on-board controllers */
 		return slot == PCI_SLOT(pdev->devfn);
 	}
 	return false;
 }
 /**
  *	piix_init_one - Register PIIX ATA PCI device with kernel services
  *	@pdev: PCI device to register
  *	@ent: Entry in piix_pci_tbl matching with @pdev
  *
  *	Called from kernel PCI layer.  We probe for combined mode (sigh),
  *	and then hand over control to libata, for it to do the rest.
  *
  *	LOCKING:
  *	Inherited from PCI layer (may sleep).
  *
  *	RETURNS:
  *	Zero on success, or -ERRNO value.
  */
 static int __devinit piix_init_one(struct pci_dev *pdev,
 				   const struct pci_device_id *ent)
 {
 	static int printed_version;
 	struct device *dev = &pdev->dev;
 	struct ata_port_info port_info[2];
 	const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] };
 	unsigned long port_flags;
 	struct ata_host *host;
 	struct piix_host_priv *hpriv;
 	int rc;
 	if (!printed_version++)
 		dev_printk(KERN_DEBUG, &pdev->dev,
 			   "version " DRV_VERSION "\n");
 	/* no hotplugging support for later devices (FIXME) */
 	if (!in_module_init && ent->driver_data >= ich5_sata)
 		return -ENODEV;
 	if (piix_broken_system_poweroff(pdev)) {
 		piix_port_info[ent->driver_data].flags |=
 				ATA_FLAG_NO_POWEROFF_SPINDOWN |
 					ATA_FLAG_NO_HIBERNATE_SPINDOWN;
 		dev_info(&pdev->dev, "quirky BIOS, skipping spindown "
 				"on poweroff and hibernation\n");
 	}
 	port_info[0] = piix_port_info[ent->driver_data];
 	port_info[1] = piix_port_info[ent->driver_data];
 	port_flags = port_info[0].flags;
 	/* enable device and prepare host */
 	rc = pcim_enable_device(pdev);
 	if (rc)
 		return rc;
 	hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
 	if (!hpriv)
 		return -ENOMEM;
 	spin_lock_init(&hpriv->sidpr_lock);
 	/* Save IOCFG, this will be used for cable detection, quirk
 	 * detection and restoration on detach.  This is necessary
 	 * because some ACPI implementations mess up cable related
 	 * bits on _STM.  Reported on kernel bz#11879.
 	 */
 	pci_read_config_dword(pdev, PIIX_IOCFG, &hpriv->saved_iocfg);
 	/* ICH6R may be driven by either ata_piix or ahci driver
 	 * regardless of BIOS configuration.  Make sure AHCI mode is
 	 * off.
 	 */
 	if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2652) {
 		rc = piix_disable_ahci(pdev);
 		if (rc)
 			return rc;
 	}
 	/* SATA map init can change port_info, do it before prepping host */
 	if (port_flags & ATA_FLAG_SATA)
 		hpriv->map = piix_init_sata_map(pdev, port_info,
 					piix_map_db_table[ent->driver_data]);
 	rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
 	if (rc)
 		return rc;
 	host->private_data = hpriv;
 	/* initialize controller */
 	if (port_flags & ATA_FLAG_SATA) {
 		piix_init_pcs(host, piix_map_db_table[ent->driver_data]);
 		rc = piix_init_sidpr(host);
 		if (rc)
 			return rc;
 	}
 	/* apply IOCFG bit18 quirk */
 	piix_iocfg_bit18_quirk(host);
 	/* On ICH5, some BIOSen disable the interrupt using the
 	 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
 	 * On ICH6, this bit has the same effect, but only when
 	 * MSI is disabled (and it is disabled, as we don't use
 	 * message-signalled interrupts currently).
 	 */
 	if (port_flags & PIIX_FLAG_CHECKINTR)
 		pci_intx(pdev, 1);
 	if (piix_check_450nx_errata(pdev)) {
 		/* This writes into the master table but it does not
 		   really matter for this errata as we will apply it to
 		   all the PIIX devices on the board */
 		host->ports[0]->mwdma_mask = 0;
 		host->ports[0]->udma_mask = 0;
 		host->ports[1]->mwdma_mask = 0;
 		host->ports[1]->udma_mask = 0;
 	}
 	host->flags |= ATA_HOST_PARALLEL_SCAN;
 	pci_set_master(pdev);
 	return ata_pci_sff_activate_host(host, ata_bmdma_interrupt, &piix_sht);
 }
 static void piix_remove_one(struct pci_dev *pdev)
 {
 	struct ata_host *host = dev_get_drvdata(&pdev->dev);
 	struct piix_host_priv *hpriv = host->private_data;
 	pci_write_config_dword(pdev, PIIX_IOCFG, hpriv->saved_iocfg);
 	ata_pci_remove_one(pdev);
 }
 static int __init piix_init(void)
 {
 	int rc;
 	DPRINTK("pci_register_driver\n");
 	rc = pci_register_driver(&piix_pci_driver);
 	if (rc)
 		return rc;
 	in_module_init = 0;
 	DPRINTK("done\n");
 	return 0;
 }
 static void __exit piix_exit(void)
 {
 	pci_unregister_driver(&piix_pci_driver);
 }
 module_init(piix_init);
 module_exit(piix_exit);

drivers/ata/libahci.c

Diff comments View file @ df423dc

1	/*	1	/*
2	* libahci.c - Common AHCI SATA low-level routines	2	* libahci.c - Common AHCI SATA low-level routines
3	*	3	*
4	* Maintained by: Jeff Garzik <jgarzik@pobox.com>	4	* Maintained by: Jeff Garzik <jgarzik@pobox.com>
5	* Please ALWAYS copy linux-ide@vger.kernel.org	5	* Please ALWAYS copy linux-ide@vger.kernel.org
6	* on emails.	6	* on emails.
7	*	7	*
8	* Copyright 2004-2005 Red Hat, Inc.	8	* Copyright 2004-2005 Red Hat, Inc.
9	*	9	*
10	*	10	*
11	* This program is free software; you can redistribute it and/or modify	11	* This program is free software; you can redistribute it and/or modify
12	* it under the terms of the GNU General Public License as published by	12	* it under the terms of the GNU General Public License as published by
13	* the Free Software Foundation; either version 2, or (at your option)	13	* the Free Software Foundation; either version 2, or (at your option)
14	* any later version.	14	* any later version.
15	*	15	*
16	* This program is distributed in the hope that it will be useful,	16	* This program is distributed in the hope that it will be useful,
17	* but WITHOUT ANY WARRANTY; without even the implied warranty of	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19	* GNU General Public License for more details.	19	* GNU General Public License for more details.
20	*	20	*
21	* You should have received a copy of the GNU General Public License	21	* You should have received a copy of the GNU General Public License
22	* along with this program; see the file COPYING. If not, write to	22	* along with this program; see the file COPYING. If not, write to
23	* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.	23	* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24	*	24	*
25	*	25	*
26	* libata documentation is available via 'make {ps\|pdf}docs',	26	* libata documentation is available via 'make {ps\|pdf}docs',
27	* as Documentation/DocBook/libata.*	27	* as Documentation/DocBook/libata.*
28	*	28	*
29	* AHCI hardware documentation:	29	* AHCI hardware documentation:
30	* http://www.intel.com/technology/serialata/pdf/rev1_0.pdf	30	* http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31	* http://www.intel.com/technology/serialata/pdf/rev1_1.pdf	31	* http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32	*	32	*
33	*/	33	*/
34		34
35	#include <linux/kernel.h>	35	#include <linux/kernel.h>
36	#include <linux/gfp.h>	36	#include <linux/gfp.h>
37	#include <linux/module.h>	37	#include <linux/module.h>
38	#include <linux/init.h>	38	#include <linux/init.h>
39	#include <linux/blkdev.h>	39	#include <linux/blkdev.h>
40	#include <linux/delay.h>	40	#include <linux/delay.h>
41	#include <linux/interrupt.h>	41	#include <linux/interrupt.h>
42	#include <linux/dma-mapping.h>	42	#include <linux/dma-mapping.h>
43	#include <linux/device.h>	43	#include <linux/device.h>
44	#include <scsi/scsi_host.h>	44	#include <scsi/scsi_host.h>
45	#include <scsi/scsi_cmnd.h>	45	#include <scsi/scsi_cmnd.h>
46	#include <linux/libata.h>	46	#include <linux/libata.h>
47	#include "ahci.h"	47	#include "ahci.h"
48		48
49	static int ahci_skip_host_reset;	49	static int ahci_skip_host_reset;
50	int ahci_ignore_sss;	50	int ahci_ignore_sss;
51	EXPORT_SYMBOL_GPL(ahci_ignore_sss);	51	EXPORT_SYMBOL_GPL(ahci_ignore_sss);
52		52
53	module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);	53	module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
54	MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");	54	MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
55		55
56	module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);	56	module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
57	MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");	57	MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
58		58
59	static int ahci_enable_alpm(struct ata_port *ap,	59	static int ahci_enable_alpm(struct ata_port *ap,
60	enum link_pm policy);	60	enum link_pm policy);
61	static void ahci_disable_alpm(struct ata_port *ap);	61	static void ahci_disable_alpm(struct ata_port *ap);
62	static ssize_t ahci_led_show(struct ata_port ap, char buf);	62	static ssize_t ahci_led_show(struct ata_port ap, char buf);
63	static ssize_t ahci_led_store(struct ata_port ap, const char buf,	63	static ssize_t ahci_led_store(struct ata_port ap, const char buf,
64	size_t size);	64	size_t size);
65	static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,	65	static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
66	ssize_t size);	66	ssize_t size);
67		67
68		68
69		69
70	static int ahci_scr_read(struct ata_link link, unsigned int sc_reg, u32 val);	70	static int ahci_scr_read(struct ata_link link, unsigned int sc_reg, u32 val);
71	static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);	71	static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
72	static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);	72	static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
73	static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);	73	static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
74	static int ahci_port_start(struct ata_port *ap);	74	static int ahci_port_start(struct ata_port *ap);
75	static void ahci_port_stop(struct ata_port *ap);	75	static void ahci_port_stop(struct ata_port *ap);
76	static void ahci_qc_prep(struct ata_queued_cmd *qc);	76	static void ahci_qc_prep(struct ata_queued_cmd *qc);
77	static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc);	77	static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc);
78	static void ahci_freeze(struct ata_port *ap);	78	static void ahci_freeze(struct ata_port *ap);
79	static void ahci_thaw(struct ata_port *ap);	79	static void ahci_thaw(struct ata_port *ap);
80	static void ahci_enable_fbs(struct ata_port *ap);	80	static void ahci_enable_fbs(struct ata_port *ap);
81	static void ahci_disable_fbs(struct ata_port *ap);	81	static void ahci_disable_fbs(struct ata_port *ap);
82	static void ahci_pmp_attach(struct ata_port *ap);	82	static void ahci_pmp_attach(struct ata_port *ap);
83	static void ahci_pmp_detach(struct ata_port *ap);	83	static void ahci_pmp_detach(struct ata_port *ap);
84	static int ahci_softreset(struct ata_link link, unsigned int class,	84	static int ahci_softreset(struct ata_link link, unsigned int class,
85	unsigned long deadline);	85	unsigned long deadline);
86	static int ahci_hardreset(struct ata_link link, unsigned int class,	86	static int ahci_hardreset(struct ata_link link, unsigned int class,
87	unsigned long deadline);	87	unsigned long deadline);
88	static void ahci_postreset(struct ata_link link, unsigned int class);	88	static void ahci_postreset(struct ata_link link, unsigned int class);
89	static void ahci_error_handler(struct ata_port *ap);	89	static void ahci_error_handler(struct ata_port *ap);
90	static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);	90	static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
91	static int ahci_port_resume(struct ata_port *ap);	91	static int ahci_port_resume(struct ata_port *ap);
92	static void ahci_dev_config(struct ata_device *dev);	92	static void ahci_dev_config(struct ata_device *dev);
93	static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,	93	static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
94	u32 opts);	94	u32 opts);
95	#ifdef CONFIG_PM	95	#ifdef CONFIG_PM
96	static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);	96	static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
97	#endif	97	#endif
98	static ssize_t ahci_activity_show(struct ata_device dev, char buf);	98	static ssize_t ahci_activity_show(struct ata_device dev, char buf);
99	static ssize_t ahci_activity_store(struct ata_device *dev,	99	static ssize_t ahci_activity_store(struct ata_device *dev,
100	enum sw_activity val);	100	enum sw_activity val);
101	static void ahci_init_sw_activity(struct ata_link *link);	101	static void ahci_init_sw_activity(struct ata_link *link);
102		102
103	static ssize_t ahci_show_host_caps(struct device *dev,	103	static ssize_t ahci_show_host_caps(struct device *dev,
104	struct device_attribute attr, char buf);	104	struct device_attribute attr, char buf);
105	static ssize_t ahci_show_host_cap2(struct device *dev,	105	static ssize_t ahci_show_host_cap2(struct device *dev,
106	struct device_attribute attr, char buf);	106	struct device_attribute attr, char buf);
107	static ssize_t ahci_show_host_version(struct device *dev,	107	static ssize_t ahci_show_host_version(struct device *dev,
108	struct device_attribute attr, char buf);	108	struct device_attribute attr, char buf);
109	static ssize_t ahci_show_port_cmd(struct device *dev,	109	static ssize_t ahci_show_port_cmd(struct device *dev,
110	struct device_attribute attr, char buf);	110	struct device_attribute attr, char buf);
111	static ssize_t ahci_read_em_buffer(struct device *dev,	111	static ssize_t ahci_read_em_buffer(struct device *dev,
112	struct device_attribute attr, char buf);	112	struct device_attribute attr, char buf);
113	static ssize_t ahci_store_em_buffer(struct device *dev,	113	static ssize_t ahci_store_em_buffer(struct device *dev,
114	struct device_attribute *attr,	114	struct device_attribute *attr,
115	const char *buf, size_t size);	115	const char *buf, size_t size);
116		116
117	static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);	117	static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);
118	static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL);	118	static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL);
119	static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL);	119	static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL);
120	static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);	120	static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);
121	static DEVICE_ATTR(em_buffer, S_IWUSR \| S_IRUGO,	121	static DEVICE_ATTR(em_buffer, S_IWUSR \| S_IRUGO,
122	ahci_read_em_buffer, ahci_store_em_buffer);	122	ahci_read_em_buffer, ahci_store_em_buffer);
123		123
124	static struct device_attribute *ahci_shost_attrs[] = {	124	static struct device_attribute *ahci_shost_attrs[] = {
125	&dev_attr_link_power_management_policy,	125	&dev_attr_link_power_management_policy,
126	&dev_attr_em_message_type,	126	&dev_attr_em_message_type,
127	&dev_attr_em_message,	127	&dev_attr_em_message,
128	&dev_attr_ahci_host_caps,	128	&dev_attr_ahci_host_caps,
129	&dev_attr_ahci_host_cap2,	129	&dev_attr_ahci_host_cap2,
130	&dev_attr_ahci_host_version,	130	&dev_attr_ahci_host_version,
131	&dev_attr_ahci_port_cmd,	131	&dev_attr_ahci_port_cmd,
132	&dev_attr_em_buffer,	132	&dev_attr_em_buffer,
133	NULL	133	NULL
134	};	134	};
135		135
136	static struct device_attribute *ahci_sdev_attrs[] = {	136	static struct device_attribute *ahci_sdev_attrs[] = {
137	&dev_attr_sw_activity,	137	&dev_attr_sw_activity,
138	&dev_attr_unload_heads,	138	&dev_attr_unload_heads,
139	NULL	139	NULL
140	};	140	};
141		141
142	struct scsi_host_template ahci_sht = {	142	struct scsi_host_template ahci_sht = {
143	ATA_NCQ_SHT("ahci"),	143	ATA_NCQ_SHT("ahci"),
144	.can_queue = AHCI_MAX_CMDS - 1,	144	.can_queue = AHCI_MAX_CMDS - 1,
145	.sg_tablesize = AHCI_MAX_SG,	145	.sg_tablesize = AHCI_MAX_SG,
146	.dma_boundary = AHCI_DMA_BOUNDARY,	146	.dma_boundary = AHCI_DMA_BOUNDARY,
147	.shost_attrs = ahci_shost_attrs,	147	.shost_attrs = ahci_shost_attrs,
148	.sdev_attrs = ahci_sdev_attrs,	148	.sdev_attrs = ahci_sdev_attrs,
149	};	149	};
150	EXPORT_SYMBOL_GPL(ahci_sht);	150	EXPORT_SYMBOL_GPL(ahci_sht);
151		151
152	struct ata_port_operations ahci_ops = {	152	struct ata_port_operations ahci_ops = {
153	.inherits = &sata_pmp_port_ops,	153	.inherits = &sata_pmp_port_ops,
154		154
155	.qc_defer = ahci_pmp_qc_defer,	155	.qc_defer = ahci_pmp_qc_defer,
156	.qc_prep = ahci_qc_prep,	156	.qc_prep = ahci_qc_prep,
157	.qc_issue = ahci_qc_issue,	157	.qc_issue = ahci_qc_issue,
158	.qc_fill_rtf = ahci_qc_fill_rtf,	158	.qc_fill_rtf = ahci_qc_fill_rtf,
159		159
160	.freeze = ahci_freeze,	160	.freeze = ahci_freeze,
161	.thaw = ahci_thaw,	161	.thaw = ahci_thaw,
162	.softreset = ahci_softreset,	162	.softreset = ahci_softreset,
163	.hardreset = ahci_hardreset,	163	.hardreset = ahci_hardreset,
164	.postreset = ahci_postreset,	164	.postreset = ahci_postreset,
165	.pmp_softreset = ahci_softreset,	165	.pmp_softreset = ahci_softreset,
166	.error_handler = ahci_error_handler,	166	.error_handler = ahci_error_handler,
167	.post_internal_cmd = ahci_post_internal_cmd,	167	.post_internal_cmd = ahci_post_internal_cmd,
168	.dev_config = ahci_dev_config,	168	.dev_config = ahci_dev_config,
169		169
170	.scr_read = ahci_scr_read,	170	.scr_read = ahci_scr_read,
171	.scr_write = ahci_scr_write,	171	.scr_write = ahci_scr_write,
172	.pmp_attach = ahci_pmp_attach,	172	.pmp_attach = ahci_pmp_attach,
173	.pmp_detach = ahci_pmp_detach,	173	.pmp_detach = ahci_pmp_detach,
174		174
175	.enable_pm = ahci_enable_alpm,	175	.enable_pm = ahci_enable_alpm,
176	.disable_pm = ahci_disable_alpm,	176	.disable_pm = ahci_disable_alpm,
177	.em_show = ahci_led_show,	177	.em_show = ahci_led_show,
178	.em_store = ahci_led_store,	178	.em_store = ahci_led_store,
179	.sw_activity_show = ahci_activity_show,	179	.sw_activity_show = ahci_activity_show,
180	.sw_activity_store = ahci_activity_store,	180	.sw_activity_store = ahci_activity_store,
181	#ifdef CONFIG_PM	181	#ifdef CONFIG_PM
182	.port_suspend = ahci_port_suspend,	182	.port_suspend = ahci_port_suspend,
183	.port_resume = ahci_port_resume,	183	.port_resume = ahci_port_resume,
184	#endif	184	#endif
185	.port_start = ahci_port_start,	185	.port_start = ahci_port_start,
186	.port_stop = ahci_port_stop,	186	.port_stop = ahci_port_stop,
187	};	187	};
188	EXPORT_SYMBOL_GPL(ahci_ops);	188	EXPORT_SYMBOL_GPL(ahci_ops);
189		189
190	int ahci_em_messages = 1;	190	int ahci_em_messages = 1;
191	EXPORT_SYMBOL_GPL(ahci_em_messages);	191	EXPORT_SYMBOL_GPL(ahci_em_messages);
192	module_param(ahci_em_messages, int, 0444);	192	module_param(ahci_em_messages, int, 0444);
193	/* add other LED protocol types when they become supported */	193	/* add other LED protocol types when they become supported */
194	MODULE_PARM_DESC(ahci_em_messages,	194	MODULE_PARM_DESC(ahci_em_messages,
195	"AHCI Enclosure Management Message control (0 = off, 1 = on)");	195	"AHCI Enclosure Management Message control (0 = off, 1 = on)");
196		196
197	static void ahci_enable_ahci(void __iomem *mmio)	197	static void ahci_enable_ahci(void __iomem *mmio)
198	{	198	{
199	int i;	199	int i;
200	u32 tmp;	200	u32 tmp;
201		201
202	/* turn on AHCI_EN */	202	/* turn on AHCI_EN */
203	tmp = readl(mmio + HOST_CTL);	203	tmp = readl(mmio + HOST_CTL);
204	if (tmp & HOST_AHCI_EN)	204	if (tmp & HOST_AHCI_EN)
205	return;	205	return;
206		206
207	/* Some controllers need AHCI_EN to be written multiple times.	207	/* Some controllers need AHCI_EN to be written multiple times.
208	* Try a few times before giving up.	208	* Try a few times before giving up.
209	*/	209	*/
210	for (i = 0; i < 5; i++) {	210	for (i = 0; i < 5; i++) {
211	tmp \|= HOST_AHCI_EN;	211	tmp \|= HOST_AHCI_EN;
212	writel(tmp, mmio + HOST_CTL);	212	writel(tmp, mmio + HOST_CTL);
213	tmp = readl(mmio + HOST_CTL); /* flush && sanity check */	213	tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
214	if (tmp & HOST_AHCI_EN)	214	if (tmp & HOST_AHCI_EN)
215	return;	215	return;
216	msleep(10);	216	msleep(10);
217	}	217	}
218		218
219	WARN_ON(1);	219	WARN_ON(1);
220	}	220	}
221		221
222	static ssize_t ahci_show_host_caps(struct device *dev,	222	static ssize_t ahci_show_host_caps(struct device *dev,
223	struct device_attribute attr, char buf)	223	struct device_attribute attr, char buf)
224	{	224	{
225	struct Scsi_Host *shost = class_to_shost(dev);	225	struct Scsi_Host *shost = class_to_shost(dev);
226	struct ata_port *ap = ata_shost_to_port(shost);	226	struct ata_port *ap = ata_shost_to_port(shost);
227	struct ahci_host_priv *hpriv = ap->host->private_data;	227	struct ahci_host_priv *hpriv = ap->host->private_data;
228		228
229	return sprintf(buf, "%x\n", hpriv->cap);	229	return sprintf(buf, "%x\n", hpriv->cap);
230	}	230	}
231		231
232	static ssize_t ahci_show_host_cap2(struct device *dev,	232	static ssize_t ahci_show_host_cap2(struct device *dev,
233	struct device_attribute attr, char buf)	233	struct device_attribute attr, char buf)
234	{	234	{
235	struct Scsi_Host *shost = class_to_shost(dev);	235	struct Scsi_Host *shost = class_to_shost(dev);
236	struct ata_port *ap = ata_shost_to_port(shost);	236	struct ata_port *ap = ata_shost_to_port(shost);
237	struct ahci_host_priv *hpriv = ap->host->private_data;	237	struct ahci_host_priv *hpriv = ap->host->private_data;
238		238
239	return sprintf(buf, "%x\n", hpriv->cap2);	239	return sprintf(buf, "%x\n", hpriv->cap2);
240	}	240	}
241		241
242	static ssize_t ahci_show_host_version(struct device *dev,	242	static ssize_t ahci_show_host_version(struct device *dev,
243	struct device_attribute attr, char buf)	243	struct device_attribute attr, char buf)
244	{	244	{
245	struct Scsi_Host *shost = class_to_shost(dev);	245	struct Scsi_Host *shost = class_to_shost(dev);
246	struct ata_port *ap = ata_shost_to_port(shost);	246	struct ata_port *ap = ata_shost_to_port(shost);
247	struct ahci_host_priv *hpriv = ap->host->private_data;	247	struct ahci_host_priv *hpriv = ap->host->private_data;
248	void __iomem *mmio = hpriv->mmio;	248	void __iomem *mmio = hpriv->mmio;
249		249
250	return sprintf(buf, "%x\n", readl(mmio + HOST_VERSION));	250	return sprintf(buf, "%x\n", readl(mmio + HOST_VERSION));
251	}	251	}
252		252
253	static ssize_t ahci_show_port_cmd(struct device *dev,	253	static ssize_t ahci_show_port_cmd(struct device *dev,
254	struct device_attribute attr, char buf)	254	struct device_attribute attr, char buf)
255	{	255	{
256	struct Scsi_Host *shost = class_to_shost(dev);	256	struct Scsi_Host *shost = class_to_shost(dev);
257	struct ata_port *ap = ata_shost_to_port(shost);	257	struct ata_port *ap = ata_shost_to_port(shost);
258	void __iomem *port_mmio = ahci_port_base(ap);	258	void __iomem *port_mmio = ahci_port_base(ap);
259		259
260	return sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));	260	return sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));
261	}	261	}
262		262
263	static ssize_t ahci_read_em_buffer(struct device *dev,	263	static ssize_t ahci_read_em_buffer(struct device *dev,
264	struct device_attribute attr, char buf)	264	struct device_attribute attr, char buf)
265	{	265	{
266	struct Scsi_Host *shost = class_to_shost(dev);	266	struct Scsi_Host *shost = class_to_shost(dev);
267	struct ata_port *ap = ata_shost_to_port(shost);	267	struct ata_port *ap = ata_shost_to_port(shost);
268	struct ahci_host_priv *hpriv = ap->host->private_data;	268	struct ahci_host_priv *hpriv = ap->host->private_data;
269	void __iomem *mmio = hpriv->mmio;	269	void __iomem *mmio = hpriv->mmio;
270	void __iomem *em_mmio = mmio + hpriv->em_loc;	270	void __iomem *em_mmio = mmio + hpriv->em_loc;
271	u32 em_ctl, msg;	271	u32 em_ctl, msg;
272	unsigned long flags;	272	unsigned long flags;
273	size_t count;	273	size_t count;
274	int i;	274	int i;
275		275
276	spin_lock_irqsave(ap->lock, flags);	276	spin_lock_irqsave(ap->lock, flags);
277		277
278	em_ctl = readl(mmio + HOST_EM_CTL);	278	em_ctl = readl(mmio + HOST_EM_CTL);
279	if (!(ap->flags & ATA_FLAG_EM) \|\| em_ctl & EM_CTL_XMT \|\|	279	if (!(ap->flags & ATA_FLAG_EM) \|\| em_ctl & EM_CTL_XMT \|\|
280	!(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) {	280	!(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) {
281	spin_unlock_irqrestore(ap->lock, flags);	281	spin_unlock_irqrestore(ap->lock, flags);
282	return -EINVAL;	282	return -EINVAL;
283	}	283	}
284		284
285	if (!(em_ctl & EM_CTL_MR)) {	285	if (!(em_ctl & EM_CTL_MR)) {
286	spin_unlock_irqrestore(ap->lock, flags);	286	spin_unlock_irqrestore(ap->lock, flags);
287	return -EAGAIN;	287	return -EAGAIN;
288	}	288	}
289		289
290	if (!(em_ctl & EM_CTL_SMB))	290	if (!(em_ctl & EM_CTL_SMB))
291	em_mmio += hpriv->em_buf_sz;	291	em_mmio += hpriv->em_buf_sz;
292		292
293	count = hpriv->em_buf_sz;	293	count = hpriv->em_buf_sz;
294		294
295	/* the count should not be larger than PAGE_SIZE */	295	/* the count should not be larger than PAGE_SIZE */
296	if (count > PAGE_SIZE) {	296	if (count > PAGE_SIZE) {
297	if (printk_ratelimit())	297	if (printk_ratelimit())
298	ata_port_printk(ap, KERN_WARNING,	298	ata_port_printk(ap, KERN_WARNING,
299	"EM read buffer size too large: "	299	"EM read buffer size too large: "
300	"buffer size %u, page size %lu\n",	300	"buffer size %u, page size %lu\n",
301	hpriv->em_buf_sz, PAGE_SIZE);	301	hpriv->em_buf_sz, PAGE_SIZE);
302	count = PAGE_SIZE;	302	count = PAGE_SIZE;
303	}	303	}
304		304
305	for (i = 0; i < count; i += 4) {	305	for (i = 0; i < count; i += 4) {
306	msg = readl(em_mmio + i);	306	msg = readl(em_mmio + i);
307	buf[i] = msg & 0xff;	307	buf[i] = msg & 0xff;
308	buf[i + 1] = (msg >> 8) & 0xff;	308	buf[i + 1] = (msg >> 8) & 0xff;
309	buf[i + 2] = (msg >> 16) & 0xff;	309	buf[i + 2] = (msg >> 16) & 0xff;
310	buf[i + 3] = (msg >> 24) & 0xff;	310	buf[i + 3] = (msg >> 24) & 0xff;
311	}	311	}
312		312
313	spin_unlock_irqrestore(ap->lock, flags);	313	spin_unlock_irqrestore(ap->lock, flags);
314		314
315	return i;	315	return i;
316	}	316	}
317		317
318	static ssize_t ahci_store_em_buffer(struct device *dev,	318	static ssize_t ahci_store_em_buffer(struct device *dev,
319	struct device_attribute *attr,	319	struct device_attribute *attr,
320	const char *buf, size_t size)	320	const char *buf, size_t size)
321	{	321	{
322	struct Scsi_Host *shost = class_to_shost(dev);	322	struct Scsi_Host *shost = class_to_shost(dev);
323	struct ata_port *ap = ata_shost_to_port(shost);	323	struct ata_port *ap = ata_shost_to_port(shost);
324	struct ahci_host_priv *hpriv = ap->host->private_data;	324	struct ahci_host_priv *hpriv = ap->host->private_data;
325	void __iomem *mmio = hpriv->mmio;	325	void __iomem *mmio = hpriv->mmio;
326	void __iomem *em_mmio = mmio + hpriv->em_loc;	326	void __iomem *em_mmio = mmio + hpriv->em_loc;
327	const unsigned char *msg_buf = buf;	327	const unsigned char *msg_buf = buf;
328	u32 em_ctl, msg;	328	u32 em_ctl, msg;
329	unsigned long flags;	329	unsigned long flags;
330	int i;	330	int i;
331		331
332	/* check size validity */	332	/* check size validity */
333	if (!(ap->flags & ATA_FLAG_EM) \|\|	333	if (!(ap->flags & ATA_FLAG_EM) \|\|
334	!(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) \|\|	334	!(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) \|\|
335	size % 4 \|\| size > hpriv->em_buf_sz)	335	size % 4 \|\| size > hpriv->em_buf_sz)
336	return -EINVAL;	336	return -EINVAL;
337		337
338	spin_lock_irqsave(ap->lock, flags);	338	spin_lock_irqsave(ap->lock, flags);
339		339
340	em_ctl = readl(mmio + HOST_EM_CTL);	340	em_ctl = readl(mmio + HOST_EM_CTL);
341	if (em_ctl & EM_CTL_TM) {	341	if (em_ctl & EM_CTL_TM) {
342	spin_unlock_irqrestore(ap->lock, flags);	342	spin_unlock_irqrestore(ap->lock, flags);
343	return -EBUSY;	343	return -EBUSY;
344	}	344	}
345		345
346	for (i = 0; i < size; i += 4) {	346	for (i = 0; i < size; i += 4) {
347	msg = msg_buf[i] \| msg_buf[i + 1] << 8 \|	347	msg = msg_buf[i] \| msg_buf[i + 1] << 8 \|
348	msg_buf[i + 2] << 16 \| msg_buf[i + 3] << 24;	348	msg_buf[i + 2] << 16 \| msg_buf[i + 3] << 24;
349	writel(msg, em_mmio + i);	349	writel(msg, em_mmio + i);
350	}	350	}
351		351
352	writel(em_ctl \| EM_CTL_TM, mmio + HOST_EM_CTL);	352	writel(em_ctl \| EM_CTL_TM, mmio + HOST_EM_CTL);
353		353
354	spin_unlock_irqrestore(ap->lock, flags);	354	spin_unlock_irqrestore(ap->lock, flags);
355		355
356	return size;	356	return size;
357	}	357	}
358		358
359	/**	359	/**
360	* ahci_save_initial_config - Save and fixup initial config values	360	* ahci_save_initial_config - Save and fixup initial config values
361	* @dev: target AHCI device	361	* @dev: target AHCI device
362	* @hpriv: host private area to store config values	362	* @hpriv: host private area to store config values
363	* @force_port_map: force port map to a specified value	363	* @force_port_map: force port map to a specified value
364	* @mask_port_map: mask out particular bits from port map	364	* @mask_port_map: mask out particular bits from port map
365	*	365	*
366	* Some registers containing configuration info might be setup by	366	* Some registers containing configuration info might be setup by
367	* BIOS and might be cleared on reset. This function saves the	367	* BIOS and might be cleared on reset. This function saves the
368	* initial values of those registers into @hpriv such that they	368	* initial values of those registers into @hpriv such that they
369	* can be restored after controller reset.	369	* can be restored after controller reset.
370	*	370	*
371	* If inconsistent, config values are fixed up by this function.	371	* If inconsistent, config values are fixed up by this function.
372	*	372	*
373	* LOCKING:	373	* LOCKING:
374	* None.	374	* None.
375	*/	375	*/
376	void ahci_save_initial_config(struct device *dev,	376	void ahci_save_initial_config(struct device *dev,
377	struct ahci_host_priv *hpriv,	377	struct ahci_host_priv *hpriv,
378	unsigned int force_port_map,	378	unsigned int force_port_map,
379	unsigned int mask_port_map)	379	unsigned int mask_port_map)
380	{	380	{
381	void __iomem *mmio = hpriv->mmio;	381	void __iomem *mmio = hpriv->mmio;
382	u32 cap, cap2, vers, port_map;	382	u32 cap, cap2, vers, port_map;
383	int i;	383	int i;
384		384
385	/* make sure AHCI mode is enabled before accessing CAP */	385	/* make sure AHCI mode is enabled before accessing CAP */
386	ahci_enable_ahci(mmio);	386	ahci_enable_ahci(mmio);
387		387
388	/* Values prefixed with saved_ are written back to host after	388	/* Values prefixed with saved_ are written back to host after
389	* reset. Values without are used for driver operation.	389	* reset. Values without are used for driver operation.
390	*/	390	*/
391	hpriv->saved_cap = cap = readl(mmio + HOST_CAP);	391	hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
392	hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);	392	hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
393		393
394	/* CAP2 register is only defined for AHCI 1.2 and later */	394	/* CAP2 register is only defined for AHCI 1.2 and later */
395	vers = readl(mmio + HOST_VERSION);	395	vers = readl(mmio + HOST_VERSION);
396	if ((vers >> 16) > 1 \|\|	396	if ((vers >> 16) > 1 \|\|
397	((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200))	397	((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200))
398	hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2);	398	hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2);
399	else	399	else
400	hpriv->saved_cap2 = cap2 = 0;	400	hpriv->saved_cap2 = cap2 = 0;
401		401
402	/* some chips have errata preventing 64bit use */	402	/* some chips have errata preventing 64bit use */
403	if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {	403	if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
404	dev_printk(KERN_INFO, dev,	404	dev_printk(KERN_INFO, dev,
405	"controller can't do 64bit DMA, forcing 32bit\n");	405	"controller can't do 64bit DMA, forcing 32bit\n");
406	cap &= ~HOST_CAP_64;	406	cap &= ~HOST_CAP_64;
407	}	407	}
408		408
409	if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {	409	if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
410	dev_printk(KERN_INFO, dev,	410	dev_printk(KERN_INFO, dev,
411	"controller can't do NCQ, turning off CAP_NCQ\n");	411	"controller can't do NCQ, turning off CAP_NCQ\n");
412	cap &= ~HOST_CAP_NCQ;	412	cap &= ~HOST_CAP_NCQ;
413	}	413	}
414		414
415	if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {	415	if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
416	dev_printk(KERN_INFO, dev,	416	dev_printk(KERN_INFO, dev,
417	"controller can do NCQ, turning on CAP_NCQ\n");	417	"controller can do NCQ, turning on CAP_NCQ\n");
418	cap \|= HOST_CAP_NCQ;	418	cap \|= HOST_CAP_NCQ;
419	}	419	}
420		420
421	if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {	421	if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
422	dev_printk(KERN_INFO, dev,	422	dev_printk(KERN_INFO, dev,
423	"controller can't do PMP, turning off CAP_PMP\n");	423	"controller can't do PMP, turning off CAP_PMP\n");
424	cap &= ~HOST_CAP_PMP;	424	cap &= ~HOST_CAP_PMP;
425	}	425	}
426		426
427	if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) {	427	if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) {
428	dev_printk(KERN_INFO, dev,	428	dev_printk(KERN_INFO, dev,
429	"controller can't do SNTF, turning off CAP_SNTF\n");	429	"controller can't do SNTF, turning off CAP_SNTF\n");
430	cap &= ~HOST_CAP_SNTF;	430	cap &= ~HOST_CAP_SNTF;
431	}	431	}
432		432
433	if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) {	433	if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) {
434	dev_printk(KERN_INFO, dev,	434	dev_printk(KERN_INFO, dev,
435	"controller can do FBS, turning on CAP_FBS\n");	435	"controller can do FBS, turning on CAP_FBS\n");
436	cap \|= HOST_CAP_FBS;	436	cap \|= HOST_CAP_FBS;
437	}	437	}
438		438
439	if (force_port_map && port_map != force_port_map) {	439	if (force_port_map && port_map != force_port_map) {
440	dev_printk(KERN_INFO, dev, "forcing port_map 0x%x -> 0x%x\n",	440	dev_printk(KERN_INFO, dev, "forcing port_map 0x%x -> 0x%x\n",
441	port_map, force_port_map);	441	port_map, force_port_map);
442	port_map = force_port_map;	442	port_map = force_port_map;
443	}	443	}
444		444
445	if (mask_port_map) {	445	if (mask_port_map) {
446	dev_printk(KERN_ERR, dev, "masking port_map 0x%x -> 0x%x\n",	446	dev_printk(KERN_ERR, dev, "masking port_map 0x%x -> 0x%x\n",
447	port_map,	447	port_map,
448	port_map & mask_port_map);	448	port_map & mask_port_map);
449	port_map &= mask_port_map;	449	port_map &= mask_port_map;
450	}	450	}
451		451
452	/* cross check port_map and cap.n_ports */	452	/* cross check port_map and cap.n_ports */
453	if (port_map) {	453	if (port_map) {
454	int map_ports = 0;	454	int map_ports = 0;
455		455
456	for (i = 0; i < AHCI_MAX_PORTS; i++)	456	for (i = 0; i < AHCI_MAX_PORTS; i++)
457	if (port_map & (1 << i))	457	if (port_map & (1 << i))
458	map_ports++;	458	map_ports++;
459		459
460	/* If PI has more ports than n_ports, whine, clear	460	/* If PI has more ports than n_ports, whine, clear
461	* port_map and let it be generated from n_ports.	461	* port_map and let it be generated from n_ports.
462	*/	462	*/
463	if (map_ports > ahci_nr_ports(cap)) {	463	if (map_ports > ahci_nr_ports(cap)) {
464	dev_printk(KERN_WARNING, dev,	464	dev_printk(KERN_WARNING, dev,
465	"implemented port map (0x%x) contains more "	465	"implemented port map (0x%x) contains more "
466	"ports than nr_ports (%u), using nr_ports\n",	466	"ports than nr_ports (%u), using nr_ports\n",
467	port_map, ahci_nr_ports(cap));	467	port_map, ahci_nr_ports(cap));
468	port_map = 0;	468	port_map = 0;
469	}	469	}
470	}	470	}
471		471
472	/* fabricate port_map from cap.nr_ports */	472	/* fabricate port_map from cap.nr_ports */
473	if (!port_map) {	473	if (!port_map) {
474	port_map = (1 << ahci_nr_ports(cap)) - 1;	474	port_map = (1 << ahci_nr_ports(cap)) - 1;
475	dev_printk(KERN_WARNING, dev,	475	dev_printk(KERN_WARNING, dev,
476	"forcing PORTS_IMPL to 0x%x\n", port_map);	476	"forcing PORTS_IMPL to 0x%x\n", port_map);
477		477
478	/* write the fixed up value to the PI register */	478	/* write the fixed up value to the PI register */
479	hpriv->saved_port_map = port_map;	479	hpriv->saved_port_map = port_map;
480	}	480	}
481		481
482	/* record values to use during operation */	482	/* record values to use during operation */
483	hpriv->cap = cap;	483	hpriv->cap = cap;
484	hpriv->cap2 = cap2;	484	hpriv->cap2 = cap2;
485	hpriv->port_map = port_map;	485	hpriv->port_map = port_map;
486	}	486	}
487	EXPORT_SYMBOL_GPL(ahci_save_initial_config);	487	EXPORT_SYMBOL_GPL(ahci_save_initial_config);
488		488
489	/**	489	/**
490	* ahci_restore_initial_config - Restore initial config	490	* ahci_restore_initial_config - Restore initial config
491	* @host: target ATA host	491	* @host: target ATA host
492	*	492	*
493	* Restore initial config stored by ahci_save_initial_config().	493	* Restore initial config stored by ahci_save_initial_config().
494	*	494	*
495	* LOCKING:	495	* LOCKING:
496	* None.	496	* None.
497	*/	497	*/
498	static void ahci_restore_initial_config(struct ata_host *host)	498	static void ahci_restore_initial_config(struct ata_host *host)
499	{	499	{
500	struct ahci_host_priv *hpriv = host->private_data;	500	struct ahci_host_priv *hpriv = host->private_data;
501	void __iomem *mmio = hpriv->mmio;	501	void __iomem *mmio = hpriv->mmio;
502		502
503	writel(hpriv->saved_cap, mmio + HOST_CAP);	503	writel(hpriv->saved_cap, mmio + HOST_CAP);
504	if (hpriv->saved_cap2)	504	if (hpriv->saved_cap2)
505	writel(hpriv->saved_cap2, mmio + HOST_CAP2);	505	writel(hpriv->saved_cap2, mmio + HOST_CAP2);
506	writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);	506	writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
507	(void) readl(mmio + HOST_PORTS_IMPL); /* flush */	507	(void) readl(mmio + HOST_PORTS_IMPL); /* flush */
508	}	508	}
509		509
510	static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)	510	static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
511	{	511	{
512	static const int offset[] = {	512	static const int offset[] = {
513	[SCR_STATUS] = PORT_SCR_STAT,	513	[SCR_STATUS] = PORT_SCR_STAT,
514	[SCR_CONTROL] = PORT_SCR_CTL,	514	[SCR_CONTROL] = PORT_SCR_CTL,
515	[SCR_ERROR] = PORT_SCR_ERR,	515	[SCR_ERROR] = PORT_SCR_ERR,
516	[SCR_ACTIVE] = PORT_SCR_ACT,	516	[SCR_ACTIVE] = PORT_SCR_ACT,
517	[SCR_NOTIFICATION] = PORT_SCR_NTF,	517	[SCR_NOTIFICATION] = PORT_SCR_NTF,
518	};	518	};
519	struct ahci_host_priv *hpriv = ap->host->private_data;	519	struct ahci_host_priv *hpriv = ap->host->private_data;
520		520
521	if (sc_reg < ARRAY_SIZE(offset) &&	521	if (sc_reg < ARRAY_SIZE(offset) &&
522	(sc_reg != SCR_NOTIFICATION \|\| (hpriv->cap & HOST_CAP_SNTF)))	522	(sc_reg != SCR_NOTIFICATION \|\| (hpriv->cap & HOST_CAP_SNTF)))
523	return offset[sc_reg];	523	return offset[sc_reg];
524	return 0;	524	return 0;
525	}	525	}
526		526
527	static int ahci_scr_read(struct ata_link link, unsigned int sc_reg, u32 val)	527	static int ahci_scr_read(struct ata_link link, unsigned int sc_reg, u32 val)
528	{	528	{
529	void __iomem *port_mmio = ahci_port_base(link->ap);	529	void __iomem *port_mmio = ahci_port_base(link->ap);
530	int offset = ahci_scr_offset(link->ap, sc_reg);	530	int offset = ahci_scr_offset(link->ap, sc_reg);
531		531
532	if (offset) {	532	if (offset) {
533	*val = readl(port_mmio + offset);	533	*val = readl(port_mmio + offset);
534	return 0;	534	return 0;
535	}	535	}
536	return -EINVAL;	536	return -EINVAL;
537	}	537	}
538		538
539	static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)	539	static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
540	{	540	{
541	void __iomem *port_mmio = ahci_port_base(link->ap);	541	void __iomem *port_mmio = ahci_port_base(link->ap);
542	int offset = ahci_scr_offset(link->ap, sc_reg);	542	int offset = ahci_scr_offset(link->ap, sc_reg);
543		543
544	if (offset) {	544	if (offset) {
545	writel(val, port_mmio + offset);	545	writel(val, port_mmio + offset);
546	return 0;	546	return 0;
547	}	547	}
548	return -EINVAL;	548	return -EINVAL;
549	}	549	}
550		550
551	void ahci_start_engine(struct ata_port *ap)	551	void ahci_start_engine(struct ata_port *ap)
552	{	552	{
553	void __iomem *port_mmio = ahci_port_base(ap);	553	void __iomem *port_mmio = ahci_port_base(ap);
554	u32 tmp;	554	u32 tmp;
555		555
556	/* start DMA */	556	/* start DMA */
557	tmp = readl(port_mmio + PORT_CMD);	557	tmp = readl(port_mmio + PORT_CMD);
558	tmp \|= PORT_CMD_START;	558	tmp \|= PORT_CMD_START;
559	writel(tmp, port_mmio + PORT_CMD);	559	writel(tmp, port_mmio + PORT_CMD);
560	readl(port_mmio + PORT_CMD); /* flush */	560	readl(port_mmio + PORT_CMD); /* flush */
561	}	561	}
562	EXPORT_SYMBOL_GPL(ahci_start_engine);	562	EXPORT_SYMBOL_GPL(ahci_start_engine);
563		563
564	int ahci_stop_engine(struct ata_port *ap)	564	int ahci_stop_engine(struct ata_port *ap)
565	{	565	{
566	void __iomem *port_mmio = ahci_port_base(ap);	566	void __iomem *port_mmio = ahci_port_base(ap);
567	u32 tmp;	567	u32 tmp;
568		568
569	tmp = readl(port_mmio + PORT_CMD);	569	tmp = readl(port_mmio + PORT_CMD);
570		570
571	/* check if the HBA is idle */	571	/* check if the HBA is idle */
572	if ((tmp & (PORT_CMD_START \| PORT_CMD_LIST_ON)) == 0)	572	if ((tmp & (PORT_CMD_START \| PORT_CMD_LIST_ON)) == 0)
573	return 0;	573	return 0;
574		574
575	/* setting HBA to idle */	575	/* setting HBA to idle */
576	tmp &= ~PORT_CMD_START;	576	tmp &= ~PORT_CMD_START;
577	writel(tmp, port_mmio + PORT_CMD);	577	writel(tmp, port_mmio + PORT_CMD);
578		578
579	/* wait for engine to stop. This could be as long as 500 msec */	579	/* wait for engine to stop. This could be as long as 500 msec */
580	tmp = ata_wait_register(port_mmio + PORT_CMD,	580	tmp = ata_wait_register(port_mmio + PORT_CMD,
581	PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);	581	PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
582	if (tmp & PORT_CMD_LIST_ON)	582	if (tmp & PORT_CMD_LIST_ON)
583	return -EIO;	583	return -EIO;
584		584
585	return 0;	585	return 0;
586	}	586	}
587	EXPORT_SYMBOL_GPL(ahci_stop_engine);	587	EXPORT_SYMBOL_GPL(ahci_stop_engine);
588		588
589	static void ahci_start_fis_rx(struct ata_port *ap)	589	static void ahci_start_fis_rx(struct ata_port *ap)
590	{	590	{
591	void __iomem *port_mmio = ahci_port_base(ap);	591	void __iomem *port_mmio = ahci_port_base(ap);
592	struct ahci_host_priv *hpriv = ap->host->private_data;	592	struct ahci_host_priv *hpriv = ap->host->private_data;
593	struct ahci_port_priv *pp = ap->private_data;	593	struct ahci_port_priv *pp = ap->private_data;
594	u32 tmp;	594	u32 tmp;
595		595
596	/* set FIS registers */	596	/* set FIS registers */
597	if (hpriv->cap & HOST_CAP_64)	597	if (hpriv->cap & HOST_CAP_64)
598	writel((pp->cmd_slot_dma >> 16) >> 16,	598	writel((pp->cmd_slot_dma >> 16) >> 16,
599	port_mmio + PORT_LST_ADDR_HI);	599	port_mmio + PORT_LST_ADDR_HI);
600	writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);	600	writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
601		601
602	if (hpriv->cap & HOST_CAP_64)	602	if (hpriv->cap & HOST_CAP_64)
603	writel((pp->rx_fis_dma >> 16) >> 16,	603	writel((pp->rx_fis_dma >> 16) >> 16,
604	port_mmio + PORT_FIS_ADDR_HI);	604	port_mmio + PORT_FIS_ADDR_HI);
605	writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);	605	writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
606		606
607	/* enable FIS reception */	607	/* enable FIS reception */
608	tmp = readl(port_mmio + PORT_CMD);	608	tmp = readl(port_mmio + PORT_CMD);
609	tmp \|= PORT_CMD_FIS_RX;	609	tmp \|= PORT_CMD_FIS_RX;
610	writel(tmp, port_mmio + PORT_CMD);	610	writel(tmp, port_mmio + PORT_CMD);
611		611
612	/* flush */	612	/* flush */
613	readl(port_mmio + PORT_CMD);	613	readl(port_mmio + PORT_CMD);
614	}	614	}
615		615
616	static int ahci_stop_fis_rx(struct ata_port *ap)	616	static int ahci_stop_fis_rx(struct ata_port *ap)
617	{	617	{
618	void __iomem *port_mmio = ahci_port_base(ap);	618	void __iomem *port_mmio = ahci_port_base(ap);
619	u32 tmp;	619	u32 tmp;
620		620
621	/* disable FIS reception */	621	/* disable FIS reception */
622	tmp = readl(port_mmio + PORT_CMD);	622	tmp = readl(port_mmio + PORT_CMD);
623	tmp &= ~PORT_CMD_FIS_RX;	623	tmp &= ~PORT_CMD_FIS_RX;
624	writel(tmp, port_mmio + PORT_CMD);	624	writel(tmp, port_mmio + PORT_CMD);
625		625
626	/* wait for completion, spec says 500ms, give it 1000 */	626	/* wait for completion, spec says 500ms, give it 1000 */
627	tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,	627	tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
628	PORT_CMD_FIS_ON, 10, 1000);	628	PORT_CMD_FIS_ON, 10, 1000);
629	if (tmp & PORT_CMD_FIS_ON)	629	if (tmp & PORT_CMD_FIS_ON)
630	return -EBUSY;	630	return -EBUSY;
631		631
632	return 0;	632	return 0;
633	}	633	}
634		634
635	static void ahci_power_up(struct ata_port *ap)	635	static void ahci_power_up(struct ata_port *ap)
636	{	636	{
637	struct ahci_host_priv *hpriv = ap->host->private_data;	637	struct ahci_host_priv *hpriv = ap->host->private_data;
638	void __iomem *port_mmio = ahci_port_base(ap);	638	void __iomem *port_mmio = ahci_port_base(ap);
639	u32 cmd;	639	u32 cmd;
640		640
641	cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;	641	cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
642		642
643	/* spin up device */	643	/* spin up device */
644	if (hpriv->cap & HOST_CAP_SSS) {	644	if (hpriv->cap & HOST_CAP_SSS) {
645	cmd \|= PORT_CMD_SPIN_UP;	645	cmd \|= PORT_CMD_SPIN_UP;
646	writel(cmd, port_mmio + PORT_CMD);	646	writel(cmd, port_mmio + PORT_CMD);
647	}	647	}
648		648
649	/* wake up link */	649	/* wake up link */
650	writel(cmd \| PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);	650	writel(cmd \| PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
651	}	651	}
652		652
653	static void ahci_disable_alpm(struct ata_port *ap)	653	static void ahci_disable_alpm(struct ata_port *ap)
654	{	654	{
655	struct ahci_host_priv *hpriv = ap->host->private_data;	655	struct ahci_host_priv *hpriv = ap->host->private_data;
656	void __iomem *port_mmio = ahci_port_base(ap);	656	void __iomem *port_mmio = ahci_port_base(ap);
657	u32 cmd;	657	u32 cmd;
658	struct ahci_port_priv *pp = ap->private_data;	658	struct ahci_port_priv *pp = ap->private_data;
659		659
660	/* IPM bits should be disabled by libata-core */	660	/* IPM bits should be disabled by libata-core */
661	/* get the existing command bits */	661	/* get the existing command bits */
662	cmd = readl(port_mmio + PORT_CMD);	662	cmd = readl(port_mmio + PORT_CMD);
663		663
664	/* disable ALPM and ASP */	664	/* disable ALPM and ASP */
665	cmd &= ~PORT_CMD_ASP;	665	cmd &= ~PORT_CMD_ASP;
666	cmd &= ~PORT_CMD_ALPE;	666	cmd &= ~PORT_CMD_ALPE;
667		667
668	/* force the interface back to active */	668	/* force the interface back to active */
669	cmd \|= PORT_CMD_ICC_ACTIVE;	669	cmd \|= PORT_CMD_ICC_ACTIVE;
670		670
671	/* write out new cmd value */	671	/* write out new cmd value */
672	writel(cmd, port_mmio + PORT_CMD);	672	writel(cmd, port_mmio + PORT_CMD);
673	cmd = readl(port_mmio + PORT_CMD);	673	cmd = readl(port_mmio + PORT_CMD);
674		674
675	/* wait 10ms to be sure we've come out of any low power state */	675	/* wait 10ms to be sure we've come out of any low power state */
676	msleep(10);	676	msleep(10);
677		677
678	/* clear out any PhyRdy stuff from interrupt status */	678	/* clear out any PhyRdy stuff from interrupt status */
679	writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT);	679	writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT);
680		680
681	/* go ahead and clean out PhyRdy Change from Serror too */	681	/* go ahead and clean out PhyRdy Change from Serror too */
682	ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) \| (1 << 18)));	682	ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) \| (1 << 18)));
683		683
684	/*	684	/*
685	* Clear flag to indicate that we should ignore all PhyRdy	685	* Clear flag to indicate that we should ignore all PhyRdy
686	* state changes	686	* state changes
687	*/	687	*/
688	hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG;	688	hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG;
689		689
690	/*	690	/*
691	* Enable interrupts on Phy Ready.	691	* Enable interrupts on Phy Ready.
692	*/	692	*/
693	pp->intr_mask \|= PORT_IRQ_PHYRDY;	693	pp->intr_mask \|= PORT_IRQ_PHYRDY;
694	writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);	694	writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
695		695
696	/*	696	/*
697	* don't change the link pm policy - we can be called	697	* don't change the link pm policy - we can be called
698	* just to turn of link pm temporarily	698	* just to turn of link pm temporarily
699	*/	699	*/
700	}	700	}
701		701
702	static int ahci_enable_alpm(struct ata_port *ap,	702	static int ahci_enable_alpm(struct ata_port *ap,
703	enum link_pm policy)	703	enum link_pm policy)
704	{	704	{
705	struct ahci_host_priv *hpriv = ap->host->private_data;	705	struct ahci_host_priv *hpriv = ap->host->private_data;
706	void __iomem *port_mmio = ahci_port_base(ap);	706	void __iomem *port_mmio = ahci_port_base(ap);
707	u32 cmd;	707	u32 cmd;
708	struct ahci_port_priv *pp = ap->private_data;	708	struct ahci_port_priv *pp = ap->private_data;
709	u32 asp;	709	u32 asp;
710		710
711	/* Make sure the host is capable of link power management */	711	/* Make sure the host is capable of link power management */
712	if (!(hpriv->cap & HOST_CAP_ALPM))	712	if (!(hpriv->cap & HOST_CAP_ALPM))
713	return -EINVAL;	713	return -EINVAL;
714		714
715	switch (policy) {	715	switch (policy) {
716	case MAX_PERFORMANCE:	716	case MAX_PERFORMANCE:
717	case NOT_AVAILABLE:	717	case NOT_AVAILABLE:
718	/*	718	/*
719	* if we came here with NOT_AVAILABLE,	719	* if we came here with NOT_AVAILABLE,
720	* it just means this is the first time we	720	* it just means this is the first time we
721	* have tried to enable - default to max performance,	721	* have tried to enable - default to max performance,
722	* and let the user go to lower power modes on request.	722	* and let the user go to lower power modes on request.
723	*/	723	*/
724	ahci_disable_alpm(ap);	724	ahci_disable_alpm(ap);
725	return 0;	725	return 0;
726	case MIN_POWER:	726	case MIN_POWER:
727	/* configure HBA to enter SLUMBER */	727	/* configure HBA to enter SLUMBER */
728	asp = PORT_CMD_ASP;	728	asp = PORT_CMD_ASP;
729	break;	729	break;
730	case MEDIUM_POWER:	730	case MEDIUM_POWER:
731	/* configure HBA to enter PARTIAL */	731	/* configure HBA to enter PARTIAL */
732	asp = 0;	732	asp = 0;
733	break;	733	break;
734	default:	734	default:
735	return -EINVAL;	735	return -EINVAL;
736	}	736	}
737		737
738	/*	738	/*
739	* Disable interrupts on Phy Ready. This keeps us from	739	* Disable interrupts on Phy Ready. This keeps us from
740	* getting woken up due to spurious phy ready interrupts	740	* getting woken up due to spurious phy ready interrupts
741	* TBD - Hot plug should be done via polling now, is	741	* TBD - Hot plug should be done via polling now, is
742	* that even supported?	742	* that even supported?
743	*/	743	*/
744	pp->intr_mask &= ~PORT_IRQ_PHYRDY;	744	pp->intr_mask &= ~PORT_IRQ_PHYRDY;
745	writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);	745	writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
746		746
747	/*	747	/*
748	* Set a flag to indicate that we should ignore all PhyRdy	748	* Set a flag to indicate that we should ignore all PhyRdy
749	* state changes since these can happen now whenever we	749	* state changes since these can happen now whenever we
750	* change link state	750	* change link state
751	*/	751	*/
752	hpriv->flags \|= AHCI_HFLAG_NO_HOTPLUG;	752	hpriv->flags \|= AHCI_HFLAG_NO_HOTPLUG;
753		753
754	/* get the existing command bits */	754	/* get the existing command bits */
755	cmd = readl(port_mmio + PORT_CMD);	755	cmd = readl(port_mmio + PORT_CMD);
756		756
757	/*	757	/*
758	* Set ASP based on Policy	758	* Set ASP based on Policy
759	*/	759	*/
760	cmd \|= asp;	760	cmd \|= asp;
761		761
762	/*	762	/*
763	* Setting this bit will instruct the HBA to aggressively	763	* Setting this bit will instruct the HBA to aggressively
764	* enter a lower power link state when it's appropriate and	764	* enter a lower power link state when it's appropriate and
765	* based on the value set above for ASP	765	* based on the value set above for ASP
766	*/	766	*/
767	cmd \|= PORT_CMD_ALPE;	767	cmd \|= PORT_CMD_ALPE;
768		768
769	/* write out new cmd value */	769	/* write out new cmd value */
770	writel(cmd, port_mmio + PORT_CMD);	770	writel(cmd, port_mmio + PORT_CMD);
771	cmd = readl(port_mmio + PORT_CMD);	771	cmd = readl(port_mmio + PORT_CMD);
772		772
773	/* IPM bits should be set by libata-core */	773	/* IPM bits should be set by libata-core */
774	return 0;	774	return 0;
775	}	775	}
776		776
777	#ifdef CONFIG_PM	777	#ifdef CONFIG_PM
778	static void ahci_power_down(struct ata_port *ap)	778	static void ahci_power_down(struct ata_port *ap)
779	{	779	{
780	struct ahci_host_priv *hpriv = ap->host->private_data;	780	struct ahci_host_priv *hpriv = ap->host->private_data;
781	void __iomem *port_mmio = ahci_port_base(ap);	781	void __iomem *port_mmio = ahci_port_base(ap);
782	u32 cmd, scontrol;	782	u32 cmd, scontrol;
783		783
784	if (!(hpriv->cap & HOST_CAP_SSS))	784	if (!(hpriv->cap & HOST_CAP_SSS))
785	return;	785	return;
786		786
787	/* put device into listen mode, first set PxSCTL.DET to 0 */	787	/* put device into listen mode, first set PxSCTL.DET to 0 */
788	scontrol = readl(port_mmio + PORT_SCR_CTL);	788	scontrol = readl(port_mmio + PORT_SCR_CTL);
789	scontrol &= ~0xf;	789	scontrol &= ~0xf;
790	writel(scontrol, port_mmio + PORT_SCR_CTL);	790	writel(scontrol, port_mmio + PORT_SCR_CTL);
791		791
792	/* then set PxCMD.SUD to 0 */	792	/* then set PxCMD.SUD to 0 */
793	cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;	793	cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
794	cmd &= ~PORT_CMD_SPIN_UP;	794	cmd &= ~PORT_CMD_SPIN_UP;
795	writel(cmd, port_mmio + PORT_CMD);	795	writel(cmd, port_mmio + PORT_CMD);
796	}	796	}
797	#endif	797	#endif
798		798
799	static void ahci_start_port(struct ata_port *ap)	799	static void ahci_start_port(struct ata_port *ap)
800	{	800	{
801	struct ahci_port_priv *pp = ap->private_data;	801	struct ahci_port_priv *pp = ap->private_data;
802	struct ata_link *link;	802	struct ata_link *link;
803	struct ahci_em_priv *emp;	803	struct ahci_em_priv *emp;
804	ssize_t rc;	804	ssize_t rc;
805	int i;	805	int i;
806		806
807	/* enable FIS reception */	807	/* enable FIS reception */
808	ahci_start_fis_rx(ap);	808	ahci_start_fis_rx(ap);
809		809
810	/* enable DMA */	810	/* enable DMA */
811	ahci_start_engine(ap);	811	ahci_start_engine(ap);
812		812
813	/* turn on LEDs */	813	/* turn on LEDs */
814	if (ap->flags & ATA_FLAG_EM) {	814	if (ap->flags & ATA_FLAG_EM) {
815	ata_for_each_link(link, ap, EDGE) {	815	ata_for_each_link(link, ap, EDGE) {
816	emp = &pp->em_priv[link->pmp];	816	emp = &pp->em_priv[link->pmp];
817		817
818	/* EM Transmit bit maybe busy during init */	818	/* EM Transmit bit maybe busy during init */
819	for (i = 0; i < EM_MAX_RETRY; i++) {	819	for (i = 0; i < EM_MAX_RETRY; i++) {
820	rc = ahci_transmit_led_message(ap,	820	rc = ahci_transmit_led_message(ap,
821	emp->led_state,	821	emp->led_state,
822	4);	822	4);
823	if (rc == -EBUSY)	823	if (rc == -EBUSY)
824	msleep(1);	824	msleep(1);
825	else	825	else
826	break;	826	break;
827	}	827	}
828	}	828	}
829	}	829	}
830		830
831	if (ap->flags & ATA_FLAG_SW_ACTIVITY)	831	if (ap->flags & ATA_FLAG_SW_ACTIVITY)
832	ata_for_each_link(link, ap, EDGE)	832	ata_for_each_link(link, ap, EDGE)
833	ahci_init_sw_activity(link);	833	ahci_init_sw_activity(link);
834		834
835	}	835	}
836		836
837	static int ahci_deinit_port(struct ata_port ap, const char *emsg)	837	static int ahci_deinit_port(struct ata_port ap, const char *emsg)
838	{	838	{
839	int rc;	839	int rc;
840		840
841	/* disable DMA */	841	/* disable DMA */
842	rc = ahci_stop_engine(ap);	842	rc = ahci_stop_engine(ap);
843	if (rc) {	843	if (rc) {
844	*emsg = "failed to stop engine";	844	*emsg = "failed to stop engine";
845	return rc;	845	return rc;
846	}	846	}
847		847
848	/* disable FIS reception */	848	/* disable FIS reception */
849	rc = ahci_stop_fis_rx(ap);	849	rc = ahci_stop_fis_rx(ap);
850	if (rc) {	850	if (rc) {
851	*emsg = "failed stop FIS RX";	851	*emsg = "failed stop FIS RX";
852	return rc;	852	return rc;
853	}	853	}
854		854
855	return 0;	855	return 0;
856	}	856	}
857		857
858	int ahci_reset_controller(struct ata_host *host)	858	int ahci_reset_controller(struct ata_host *host)
859	{	859	{
860	struct ahci_host_priv *hpriv = host->private_data;	860	struct ahci_host_priv *hpriv = host->private_data;
861	void __iomem *mmio = hpriv->mmio;	861	void __iomem *mmio = hpriv->mmio;
862	u32 tmp;	862	u32 tmp;
863		863
864	/* we must be in AHCI mode, before using anything	864	/* we must be in AHCI mode, before using anything
865	* AHCI-specific, such as HOST_RESET.	865	* AHCI-specific, such as HOST_RESET.
866	*/	866	*/
867	ahci_enable_ahci(mmio);	867	ahci_enable_ahci(mmio);
868		868
869	/* global controller reset */	869	/* global controller reset */
870	if (!ahci_skip_host_reset) {	870	if (!ahci_skip_host_reset) {
871	tmp = readl(mmio + HOST_CTL);	871	tmp = readl(mmio + HOST_CTL);
872	if ((tmp & HOST_RESET) == 0) {	872	if ((tmp & HOST_RESET) == 0) {
873	writel(tmp \| HOST_RESET, mmio + HOST_CTL);	873	writel(tmp \| HOST_RESET, mmio + HOST_CTL);
874	readl(mmio + HOST_CTL); /* flush */	874	readl(mmio + HOST_CTL); /* flush */
875	}	875	}
876		876
877	/*	877	/*
878	* to perform host reset, OS should set HOST_RESET	878	* to perform host reset, OS should set HOST_RESET
879	* and poll until this bit is read to be "0".	879	* and poll until this bit is read to be "0".
880	* reset must complete within 1 second, or	880	* reset must complete within 1 second, or
881	* the hardware should be considered fried.	881	* the hardware should be considered fried.
882	*/	882	*/
883	tmp = ata_wait_register(mmio + HOST_CTL, HOST_RESET,	883	tmp = ata_wait_register(mmio + HOST_CTL, HOST_RESET,
884	HOST_RESET, 10, 1000);	884	HOST_RESET, 10, 1000);
885		885
886	if (tmp & HOST_RESET) {	886	if (tmp & HOST_RESET) {
887	dev_printk(KERN_ERR, host->dev,	887	dev_printk(KERN_ERR, host->dev,
888	"controller reset failed (0x%x)\n", tmp);	888	"controller reset failed (0x%x)\n", tmp);
889	return -EIO;	889	return -EIO;
890	}	890	}
891		891
892	/* turn on AHCI mode */	892	/* turn on AHCI mode */
893	ahci_enable_ahci(mmio);	893	ahci_enable_ahci(mmio);
894		894
895	/* Some registers might be cleared on reset. Restore	895	/* Some registers might be cleared on reset. Restore
896	* initial values.	896	* initial values.
897	*/	897	*/
898	ahci_restore_initial_config(host);	898	ahci_restore_initial_config(host);
899	} else	899	} else
900	dev_printk(KERN_INFO, host->dev,	900	dev_printk(KERN_INFO, host->dev,
901	"skipping global host reset\n");	901	"skipping global host reset\n");
902		902
903	return 0;	903	return 0;
904	}	904	}
905	EXPORT_SYMBOL_GPL(ahci_reset_controller);	905	EXPORT_SYMBOL_GPL(ahci_reset_controller);
906		906
907	static void ahci_sw_activity(struct ata_link *link)	907	static void ahci_sw_activity(struct ata_link *link)
908	{	908	{
909	struct ata_port *ap = link->ap;	909	struct ata_port *ap = link->ap;
910	struct ahci_port_priv *pp = ap->private_data;	910	struct ahci_port_priv *pp = ap->private_data;
911	struct ahci_em_priv *emp = &pp->em_priv[link->pmp];	911	struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
912		912
913	if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))	913	if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
914	return;	914	return;
915		915
916	emp->activity++;	916	emp->activity++;
917	if (!timer_pending(&emp->timer))	917	if (!timer_pending(&emp->timer))
918	mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));	918	mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
919	}	919	}
920		920
921	static void ahci_sw_activity_blink(unsigned long arg)	921	static void ahci_sw_activity_blink(unsigned long arg)
922	{	922	{
923	struct ata_link link = (struct ata_link )arg;	923	struct ata_link link = (struct ata_link )arg;
924	struct ata_port *ap = link->ap;	924	struct ata_port *ap = link->ap;
925	struct ahci_port_priv *pp = ap->private_data;	925	struct ahci_port_priv *pp = ap->private_data;
926	struct ahci_em_priv *emp = &pp->em_priv[link->pmp];	926	struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
927	unsigned long led_message = emp->led_state;	927	unsigned long led_message = emp->led_state;
928	u32 activity_led_state;	928	u32 activity_led_state;
929	unsigned long flags;	929	unsigned long flags;
930		930
931	led_message &= EM_MSG_LED_VALUE;	931	led_message &= EM_MSG_LED_VALUE;
932	led_message \|= ap->port_no \| (link->pmp << 8);	932	led_message \|= ap->port_no \| (link->pmp << 8);
933		933
934	/* check to see if we've had activity. If so,	934	/* check to see if we've had activity. If so,
935	* toggle state of LED and reset timer. If not,	935	* toggle state of LED and reset timer. If not,
936	* turn LED to desired idle state.	936	* turn LED to desired idle state.
937	*/	937	*/
938	spin_lock_irqsave(ap->lock, flags);	938	spin_lock_irqsave(ap->lock, flags);
939	if (emp->saved_activity != emp->activity) {	939	if (emp->saved_activity != emp->activity) {
940	emp->saved_activity = emp->activity;	940	emp->saved_activity = emp->activity;
941	/* get the current LED state */	941	/* get the current LED state */
942	activity_led_state = led_message & EM_MSG_LED_VALUE_ON;	942	activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
943		943
944	if (activity_led_state)	944	if (activity_led_state)
945	activity_led_state = 0;	945	activity_led_state = 0;
946	else	946	else
947	activity_led_state = 1;	947	activity_led_state = 1;
948		948
949	/* clear old state */	949	/* clear old state */
950	led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;	950	led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
951		951
952	/* toggle state */	952	/* toggle state */
953	led_message \|= (activity_led_state << 16);	953	led_message \|= (activity_led_state << 16);
954	mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));	954	mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
955	} else {	955	} else {
956	/* switch to idle */	956	/* switch to idle */
957	led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;	957	led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
958	if (emp->blink_policy == BLINK_OFF)	958	if (emp->blink_policy == BLINK_OFF)
959	led_message \|= (1 << 16);	959	led_message \|= (1 << 16);
960	}	960	}
961	spin_unlock_irqrestore(ap->lock, flags);	961	spin_unlock_irqrestore(ap->lock, flags);
962	ahci_transmit_led_message(ap, led_message, 4);	962	ahci_transmit_led_message(ap, led_message, 4);
963	}	963	}
964		964
965	static void ahci_init_sw_activity(struct ata_link *link)	965	static void ahci_init_sw_activity(struct ata_link *link)
966	{	966	{
967	struct ata_port *ap = link->ap;	967	struct ata_port *ap = link->ap;
968	struct ahci_port_priv *pp = ap->private_data;	968	struct ahci_port_priv *pp = ap->private_data;
969	struct ahci_em_priv *emp = &pp->em_priv[link->pmp];	969	struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
970		970
971	/* init activity stats, setup timer */	971	/* init activity stats, setup timer */
972	emp->saved_activity = emp->activity = 0;	972	emp->saved_activity = emp->activity = 0;
973	setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link);	973	setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link);
974		974
975	/* check our blink policy and set flag for link if it's enabled */	975	/* check our blink policy and set flag for link if it's enabled */
976	if (emp->blink_policy)	976	if (emp->blink_policy)
977	link->flags \|= ATA_LFLAG_SW_ACTIVITY;	977	link->flags \|= ATA_LFLAG_SW_ACTIVITY;
978	}	978	}
979		979
980	int ahci_reset_em(struct ata_host *host)	980	int ahci_reset_em(struct ata_host *host)
981	{	981	{
982	struct ahci_host_priv *hpriv = host->private_data;	982	struct ahci_host_priv *hpriv = host->private_data;
983	void __iomem *mmio = hpriv->mmio;	983	void __iomem *mmio = hpriv->mmio;
984	u32 em_ctl;	984	u32 em_ctl;
985		985
986	em_ctl = readl(mmio + HOST_EM_CTL);	986	em_ctl = readl(mmio + HOST_EM_CTL);
987	if ((em_ctl & EM_CTL_TM) \|\| (em_ctl & EM_CTL_RST))	987	if ((em_ctl & EM_CTL_TM) \|\| (em_ctl & EM_CTL_RST))
988	return -EINVAL;	988	return -EINVAL;
989		989
990	writel(em_ctl \| EM_CTL_RST, mmio + HOST_EM_CTL);	990	writel(em_ctl \| EM_CTL_RST, mmio + HOST_EM_CTL);
991	return 0;	991	return 0;
992	}	992	}
993	EXPORT_SYMBOL_GPL(ahci_reset_em);	993	EXPORT_SYMBOL_GPL(ahci_reset_em);
994		994
995	static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,	995	static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
996	ssize_t size)	996	ssize_t size)
997	{	997	{
998	struct ahci_host_priv *hpriv = ap->host->private_data;	998	struct ahci_host_priv *hpriv = ap->host->private_data;
999	struct ahci_port_priv *pp = ap->private_data;	999	struct ahci_port_priv *pp = ap->private_data;
1000	void __iomem *mmio = hpriv->mmio;	1000	void __iomem *mmio = hpriv->mmio;
1001	u32 em_ctl;	1001	u32 em_ctl;
1002	u32 message[] = {0, 0};	1002	u32 message[] = {0, 0};
1003	unsigned long flags;	1003	unsigned long flags;
1004	int pmp;	1004	int pmp;
1005	struct ahci_em_priv *emp;	1005	struct ahci_em_priv *emp;
1006		1006
1007	/* get the slot number from the message */	1007	/* get the slot number from the message */
1008	pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;	1008	pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1009	if (pmp < EM_MAX_SLOTS)	1009	if (pmp < EM_MAX_SLOTS)
1010	emp = &pp->em_priv[pmp];	1010	emp = &pp->em_priv[pmp];
1011	else	1011	else
1012	return -EINVAL;	1012	return -EINVAL;
1013		1013
1014	spin_lock_irqsave(ap->lock, flags);	1014	spin_lock_irqsave(ap->lock, flags);
1015		1015
1016	/*	1016	/*
1017	* if we are still busy transmitting a previous message,	1017	* if we are still busy transmitting a previous message,
1018	* do not allow	1018	* do not allow
1019	*/	1019	*/
1020	em_ctl = readl(mmio + HOST_EM_CTL);	1020	em_ctl = readl(mmio + HOST_EM_CTL);
1021	if (em_ctl & EM_CTL_TM) {	1021	if (em_ctl & EM_CTL_TM) {
1022	spin_unlock_irqrestore(ap->lock, flags);	1022	spin_unlock_irqrestore(ap->lock, flags);
1023	return -EBUSY;	1023	return -EBUSY;
1024	}	1024	}
1025		1025
1026	if (hpriv->em_msg_type & EM_MSG_TYPE_LED) {	1026	if (hpriv->em_msg_type & EM_MSG_TYPE_LED) {
1027	/*	1027	/*
1028	* create message header - this is all zero except for	1028	* create message header - this is all zero except for
1029	* the message size, which is 4 bytes.	1029	* the message size, which is 4 bytes.
1030	*/	1030	*/
1031	message[0] \|= (4 << 8);	1031	message[0] \|= (4 << 8);
1032		1032
1033	/* ignore 0:4 of byte zero, fill in port info yourself */	1033	/* ignore 0:4 of byte zero, fill in port info yourself */
1034	message[1] = ((state & ~EM_MSG_LED_HBA_PORT) \| ap->port_no);	1034	message[1] = ((state & ~EM_MSG_LED_HBA_PORT) \| ap->port_no);
1035		1035
1036	/* write message to EM_LOC */	1036	/* write message to EM_LOC */
1037	writel(message[0], mmio + hpriv->em_loc);	1037	writel(message[0], mmio + hpriv->em_loc);
1038	writel(message[1], mmio + hpriv->em_loc+4);	1038	writel(message[1], mmio + hpriv->em_loc+4);
1039		1039
1040	/*	1040	/*
1041	* tell hardware to transmit the message	1041	* tell hardware to transmit the message
1042	*/	1042	*/
1043	writel(em_ctl \| EM_CTL_TM, mmio + HOST_EM_CTL);	1043	writel(em_ctl \| EM_CTL_TM, mmio + HOST_EM_CTL);
1044	}	1044	}
1045		1045
1046	/* save off new led state for port/slot */	1046	/* save off new led state for port/slot */
1047	emp->led_state = state;	1047	emp->led_state = state;
1048		1048
1049	spin_unlock_irqrestore(ap->lock, flags);	1049	spin_unlock_irqrestore(ap->lock, flags);
1050	return size;	1050	return size;
1051	}	1051	}
1052		1052
1053	static ssize_t ahci_led_show(struct ata_port ap, char buf)	1053	static ssize_t ahci_led_show(struct ata_port ap, char buf)
1054	{	1054	{
1055	struct ahci_port_priv *pp = ap->private_data;	1055	struct ahci_port_priv *pp = ap->private_data;
1056	struct ata_link *link;	1056	struct ata_link *link;
1057	struct ahci_em_priv *emp;	1057	struct ahci_em_priv *emp;
1058	int rc = 0;	1058	int rc = 0;
1059		1059
1060	ata_for_each_link(link, ap, EDGE) {	1060	ata_for_each_link(link, ap, EDGE) {
1061	emp = &pp->em_priv[link->pmp];	1061	emp = &pp->em_priv[link->pmp];
1062	rc += sprintf(buf, "%lx\n", emp->led_state);	1062	rc += sprintf(buf, "%lx\n", emp->led_state);
1063	}	1063	}
1064	return rc;	1064	return rc;
1065	}	1065	}
1066		1066
1067	static ssize_t ahci_led_store(struct ata_port ap, const char buf,	1067	static ssize_t ahci_led_store(struct ata_port ap, const char buf,
1068	size_t size)	1068	size_t size)
1069	{	1069	{
1070	int state;	1070	int state;
1071	int pmp;	1071	int pmp;
1072	struct ahci_port_priv *pp = ap->private_data;	1072	struct ahci_port_priv *pp = ap->private_data;
1073	struct ahci_em_priv *emp;	1073	struct ahci_em_priv *emp;
1074		1074
1075	state = simple_strtoul(buf, NULL, 0);	1075	state = simple_strtoul(buf, NULL, 0);
1076		1076
1077	/* get the slot number from the message */	1077	/* get the slot number from the message */
1078	pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;	1078	pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1079	if (pmp < EM_MAX_SLOTS)	1079	if (pmp < EM_MAX_SLOTS)
1080	emp = &pp->em_priv[pmp];	1080	emp = &pp->em_priv[pmp];
1081	else	1081	else
1082	return -EINVAL;	1082	return -EINVAL;
1083		1083
1084	/* mask off the activity bits if we are in sw_activity	1084	/* mask off the activity bits if we are in sw_activity
1085	* mode, user should turn off sw_activity before setting	1085	* mode, user should turn off sw_activity before setting
1086	* activity led through em_message	1086	* activity led through em_message
1087	*/	1087	*/
1088	if (emp->blink_policy)	1088	if (emp->blink_policy)
1089	state &= ~EM_MSG_LED_VALUE_ACTIVITY;	1089	state &= ~EM_MSG_LED_VALUE_ACTIVITY;
1090		1090
1091	return ahci_transmit_led_message(ap, state, size);	1091	return ahci_transmit_led_message(ap, state, size);
1092	}	1092	}
1093		1093
1094	static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)	1094	static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1095	{	1095	{
1096	struct ata_link *link = dev->link;	1096	struct ata_link *link = dev->link;
1097	struct ata_port *ap = link->ap;	1097	struct ata_port *ap = link->ap;
1098	struct ahci_port_priv *pp = ap->private_data;	1098	struct ahci_port_priv *pp = ap->private_data;
1099	struct ahci_em_priv *emp = &pp->em_priv[link->pmp];	1099	struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1100	u32 port_led_state = emp->led_state;	1100	u32 port_led_state = emp->led_state;
1101		1101
1102	/* save the desired Activity LED behavior */	1102	/* save the desired Activity LED behavior */
1103	if (val == OFF) {	1103	if (val == OFF) {
1104	/* clear LFLAG */	1104	/* clear LFLAG */
1105	link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);	1105	link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1106		1106
1107	/* set the LED to OFF */	1107	/* set the LED to OFF */
1108	port_led_state &= EM_MSG_LED_VALUE_OFF;	1108	port_led_state &= EM_MSG_LED_VALUE_OFF;
1109	port_led_state \|= (ap->port_no \| (link->pmp << 8));	1109	port_led_state \|= (ap->port_no \| (link->pmp << 8));
1110	ahci_transmit_led_message(ap, port_led_state, 4);	1110	ahci_transmit_led_message(ap, port_led_state, 4);
1111	} else {	1111	} else {
1112	link->flags \|= ATA_LFLAG_SW_ACTIVITY;	1112	link->flags \|= ATA_LFLAG_SW_ACTIVITY;
1113	if (val == BLINK_OFF) {	1113	if (val == BLINK_OFF) {
1114	/* set LED to ON for idle */	1114	/* set LED to ON for idle */
1115	port_led_state &= EM_MSG_LED_VALUE_OFF;	1115	port_led_state &= EM_MSG_LED_VALUE_OFF;
1116	port_led_state \|= (ap->port_no \| (link->pmp << 8));	1116	port_led_state \|= (ap->port_no \| (link->pmp << 8));
1117	port_led_state \|= EM_MSG_LED_VALUE_ON; /* check this */	1117	port_led_state \|= EM_MSG_LED_VALUE_ON; /* check this */
1118	ahci_transmit_led_message(ap, port_led_state, 4);	1118	ahci_transmit_led_message(ap, port_led_state, 4);
1119	}	1119	}
1120	}	1120	}
1121	emp->blink_policy = val;	1121	emp->blink_policy = val;
1122	return 0;	1122	return 0;
1123	}	1123	}
1124		1124
1125	static ssize_t ahci_activity_show(struct ata_device dev, char buf)	1125	static ssize_t ahci_activity_show(struct ata_device dev, char buf)
1126	{	1126	{
1127	struct ata_link *link = dev->link;	1127	struct ata_link *link = dev->link;
1128	struct ata_port *ap = link->ap;	1128	struct ata_port *ap = link->ap;
1129	struct ahci_port_priv *pp = ap->private_data;	1129	struct ahci_port_priv *pp = ap->private_data;
1130	struct ahci_em_priv *emp = &pp->em_priv[link->pmp];	1130	struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1131		1131
1132	/* display the saved value of activity behavior for this	1132	/* display the saved value of activity behavior for this
1133	* disk.	1133	* disk.
1134	*/	1134	*/
1135	return sprintf(buf, "%d\n", emp->blink_policy);	1135	return sprintf(buf, "%d\n", emp->blink_policy);
1136	}	1136	}
1137		1137
1138	static void ahci_port_init(struct device dev, struct ata_port ap,	1138	static void ahci_port_init(struct device dev, struct ata_port ap,
1139	int port_no, void __iomem *mmio,	1139	int port_no, void __iomem *mmio,
1140	void __iomem *port_mmio)	1140	void __iomem *port_mmio)
1141	{	1141	{
1142	const char *emsg = NULL;	1142	const char *emsg = NULL;
1143	int rc;	1143	int rc;
1144	u32 tmp;	1144	u32 tmp;
1145		1145
1146	/* make sure port is not active */	1146	/* make sure port is not active */
1147	rc = ahci_deinit_port(ap, &emsg);	1147	rc = ahci_deinit_port(ap, &emsg);
1148	if (rc)	1148	if (rc)
1149	dev_warn(dev, "%s (%d)\n", emsg, rc);	1149	dev_warn(dev, "%s (%d)\n", emsg, rc);
1150		1150
1151	/* clear SError */	1151	/* clear SError */
1152	tmp = readl(port_mmio + PORT_SCR_ERR);	1152	tmp = readl(port_mmio + PORT_SCR_ERR);
1153	VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);	1153	VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1154	writel(tmp, port_mmio + PORT_SCR_ERR);	1154	writel(tmp, port_mmio + PORT_SCR_ERR);
1155		1155
1156	/* clear port IRQ */	1156	/* clear port IRQ */
1157	tmp = readl(port_mmio + PORT_IRQ_STAT);	1157	tmp = readl(port_mmio + PORT_IRQ_STAT);
1158	VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);	1158	VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1159	if (tmp)	1159	if (tmp)
1160	writel(tmp, port_mmio + PORT_IRQ_STAT);	1160	writel(tmp, port_mmio + PORT_IRQ_STAT);
1161		1161
1162	writel(1 << port_no, mmio + HOST_IRQ_STAT);	1162	writel(1 << port_no, mmio + HOST_IRQ_STAT);
1163	}	1163	}
1164		1164
1165	void ahci_init_controller(struct ata_host *host)	1165	void ahci_init_controller(struct ata_host *host)
1166	{	1166	{
1167	struct ahci_host_priv *hpriv = host->private_data;	1167	struct ahci_host_priv *hpriv = host->private_data;
1168	void __iomem *mmio = hpriv->mmio;	1168	void __iomem *mmio = hpriv->mmio;
1169	int i;	1169	int i;
1170	void __iomem *port_mmio;	1170	void __iomem *port_mmio;
1171	u32 tmp;	1171	u32 tmp;
1172		1172
1173	for (i = 0; i < host->n_ports; i++) {	1173	for (i = 0; i < host->n_ports; i++) {
1174	struct ata_port *ap = host->ports[i];	1174	struct ata_port *ap = host->ports[i];
1175		1175
1176	port_mmio = ahci_port_base(ap);	1176	port_mmio = ahci_port_base(ap);
1177	if (ata_port_is_dummy(ap))	1177	if (ata_port_is_dummy(ap))
1178	continue;	1178	continue;
1179		1179
1180	ahci_port_init(host->dev, ap, i, mmio, port_mmio);	1180	ahci_port_init(host->dev, ap, i, mmio, port_mmio);
1181	}	1181	}
1182		1182
1183	tmp = readl(mmio + HOST_CTL);	1183	tmp = readl(mmio + HOST_CTL);
1184	VPRINTK("HOST_CTL 0x%x\n", tmp);	1184	VPRINTK("HOST_CTL 0x%x\n", tmp);
1185	writel(tmp \| HOST_IRQ_EN, mmio + HOST_CTL);	1185	writel(tmp \| HOST_IRQ_EN, mmio + HOST_CTL);
1186	tmp = readl(mmio + HOST_CTL);	1186	tmp = readl(mmio + HOST_CTL);
1187	VPRINTK("HOST_CTL 0x%x\n", tmp);	1187	VPRINTK("HOST_CTL 0x%x\n", tmp);
1188	}	1188	}
1189	EXPORT_SYMBOL_GPL(ahci_init_controller);	1189	EXPORT_SYMBOL_GPL(ahci_init_controller);
1190		1190
1191	static void ahci_dev_config(struct ata_device *dev)	1191	static void ahci_dev_config(struct ata_device *dev)
1192	{	1192	{
1193	struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;	1193	struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1194		1194
1195	if (hpriv->flags & AHCI_HFLAG_SECT255) {	1195	if (hpriv->flags & AHCI_HFLAG_SECT255) {
1196	dev->max_sectors = 255;	1196	dev->max_sectors = 255;
1197	ata_dev_printk(dev, KERN_INFO,	1197	ata_dev_printk(dev, KERN_INFO,
1198	"SB600 AHCI: limiting to 255 sectors per cmd\n");	1198	"SB600 AHCI: limiting to 255 sectors per cmd\n");
1199	}	1199	}
1200	}	1200	}
1201		1201
1202	static unsigned int ahci_dev_classify(struct ata_port *ap)	1202	static unsigned int ahci_dev_classify(struct ata_port *ap)
1203	{	1203	{
1204	void __iomem *port_mmio = ahci_port_base(ap);	1204	void __iomem *port_mmio = ahci_port_base(ap);
1205	struct ata_taskfile tf;	1205	struct ata_taskfile tf;
1206	u32 tmp;	1206	u32 tmp;
1207		1207
1208	tmp = readl(port_mmio + PORT_SIG);	1208	tmp = readl(port_mmio + PORT_SIG);
1209	tf.lbah = (tmp >> 24) & 0xff;	1209	tf.lbah = (tmp >> 24) & 0xff;
1210	tf.lbam = (tmp >> 16) & 0xff;	1210	tf.lbam = (tmp >> 16) & 0xff;
1211	tf.lbal = (tmp >> 8) & 0xff;	1211	tf.lbal = (tmp >> 8) & 0xff;
1212	tf.nsect = (tmp) & 0xff;	1212	tf.nsect = (tmp) & 0xff;
1213		1213
1214	return ata_dev_classify(&tf);	1214	return ata_dev_classify(&tf);
1215	}	1215	}
1216		1216
1217	static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,	1217	static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1218	u32 opts)	1218	u32 opts)
1219	{	1219	{
1220	dma_addr_t cmd_tbl_dma;	1220	dma_addr_t cmd_tbl_dma;
1221		1221
1222	cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;	1222	cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1223		1223
1224	pp->cmd_slot[tag].opts = cpu_to_le32(opts);	1224	pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1225	pp->cmd_slot[tag].status = 0;	1225	pp->cmd_slot[tag].status = 0;
1226	pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);	1226	pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1227	pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);	1227	pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1228	}	1228	}
1229		1229
1230	int ahci_kick_engine(struct ata_port *ap)	1230	int ahci_kick_engine(struct ata_port *ap)
1231	{	1231	{
1232	void __iomem *port_mmio = ahci_port_base(ap);	1232	void __iomem *port_mmio = ahci_port_base(ap);
1233	struct ahci_host_priv *hpriv = ap->host->private_data;	1233	struct ahci_host_priv *hpriv = ap->host->private_data;
1234	u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;	1234	u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1235	u32 tmp;	1235	u32 tmp;
1236	int busy, rc;	1236	int busy, rc;
1237		1237
1238	/* stop engine */	1238	/* stop engine */
1239	rc = ahci_stop_engine(ap);	1239	rc = ahci_stop_engine(ap);
1240	if (rc)	1240	if (rc)
1241	goto out_restart;	1241	goto out_restart;
1242		1242
1243	/* need to do CLO?	1243	/* need to do CLO?
1244	* always do CLO if PMP is attached (AHCI-1.3 9.2)	1244	* always do CLO if PMP is attached (AHCI-1.3 9.2)
1245	*/	1245	*/
1246	busy = status & (ATA_BUSY \| ATA_DRQ);	1246	busy = status & (ATA_BUSY \| ATA_DRQ);
1247	if (!busy && !sata_pmp_attached(ap)) {	1247	if (!busy && !sata_pmp_attached(ap)) {
1248	rc = 0;	1248	rc = 0;
1249	goto out_restart;	1249	goto out_restart;
1250	}	1250	}
1251		1251
1252	if (!(hpriv->cap & HOST_CAP_CLO)) {	1252	if (!(hpriv->cap & HOST_CAP_CLO)) {
1253	rc = -EOPNOTSUPP;	1253	rc = -EOPNOTSUPP;
1254	goto out_restart;	1254	goto out_restart;
1255	}	1255	}
1256		1256
1257	/* perform CLO */	1257	/* perform CLO */
1258	tmp = readl(port_mmio + PORT_CMD);	1258	tmp = readl(port_mmio + PORT_CMD);
1259	tmp \|= PORT_CMD_CLO;	1259	tmp \|= PORT_CMD_CLO;
1260	writel(tmp, port_mmio + PORT_CMD);	1260	writel(tmp, port_mmio + PORT_CMD);
1261		1261
1262	rc = 0;	1262	rc = 0;
1263	tmp = ata_wait_register(port_mmio + PORT_CMD,	1263	tmp = ata_wait_register(port_mmio + PORT_CMD,
1264	PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);	1264	PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1265	if (tmp & PORT_CMD_CLO)	1265	if (tmp & PORT_CMD_CLO)
1266	rc = -EIO;	1266	rc = -EIO;
1267		1267
1268	/* restart engine */	1268	/* restart engine */
1269	out_restart:	1269	out_restart:
1270	ahci_start_engine(ap);	1270	ahci_start_engine(ap);
1271	return rc;	1271	return rc;
1272	}	1272	}
1273	EXPORT_SYMBOL_GPL(ahci_kick_engine);	1273	EXPORT_SYMBOL_GPL(ahci_kick_engine);
1274		1274
1275	static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,	1275	static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1276	struct ata_taskfile *tf, int is_cmd, u16 flags,	1276	struct ata_taskfile *tf, int is_cmd, u16 flags,
1277	unsigned long timeout_msec)	1277	unsigned long timeout_msec)
1278	{	1278	{
1279	const u32 cmd_fis_len = 5; /* five dwords */	1279	const u32 cmd_fis_len = 5; /* five dwords */
1280	struct ahci_port_priv *pp = ap->private_data;	1280	struct ahci_port_priv *pp = ap->private_data;
1281	void __iomem *port_mmio = ahci_port_base(ap);	1281	void __iomem *port_mmio = ahci_port_base(ap);
1282	u8 *fis = pp->cmd_tbl;	1282	u8 *fis = pp->cmd_tbl;
1283	u32 tmp;	1283	u32 tmp;
1284		1284
1285	/* prep the command */	1285	/* prep the command */
1286	ata_tf_to_fis(tf, pmp, is_cmd, fis);	1286	ata_tf_to_fis(tf, pmp, is_cmd, fis);
1287	ahci_fill_cmd_slot(pp, 0, cmd_fis_len \| flags \| (pmp << 12));	1287	ahci_fill_cmd_slot(pp, 0, cmd_fis_len \| flags \| (pmp << 12));
1288		1288
1289	/* issue & wait */	1289	/* issue & wait */
1290	writel(1, port_mmio + PORT_CMD_ISSUE);	1290	writel(1, port_mmio + PORT_CMD_ISSUE);
1291		1291
1292	if (timeout_msec) {	1292	if (timeout_msec) {
1293	tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,	1293	tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1294	1, timeout_msec);	1294	1, timeout_msec);
1295	if (tmp & 0x1) {	1295	if (tmp & 0x1) {
1296	ahci_kick_engine(ap);	1296	ahci_kick_engine(ap);
1297	return -EBUSY;	1297	return -EBUSY;
1298	}	1298	}
1299	} else	1299	} else
1300	readl(port_mmio + PORT_CMD_ISSUE); /* flush */	1300	readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1301		1301
1302	return 0;	1302	return 0;
1303	}	1303	}
1304		1304
1305	int ahci_do_softreset(struct ata_link link, unsigned int class,	1305	int ahci_do_softreset(struct ata_link link, unsigned int class,
1306	int pmp, unsigned long deadline,	1306	int pmp, unsigned long deadline,
1307	int (check_ready)(struct ata_link link))	1307	int (check_ready)(struct ata_link link))
1308	{	1308	{
1309	struct ata_port *ap = link->ap;	1309	struct ata_port *ap = link->ap;
1310	struct ahci_host_priv *hpriv = ap->host->private_data;	1310	struct ahci_host_priv *hpriv = ap->host->private_data;
1311	const char *reason = NULL;	1311	const char *reason = NULL;
1312	unsigned long now, msecs;	1312	unsigned long now, msecs;
1313	struct ata_taskfile tf;	1313	struct ata_taskfile tf;
1314	int rc;	1314	int rc;
1315		1315
1316	DPRINTK("ENTER\n");	1316	DPRINTK("ENTER\n");
1317		1317
1318	/* prepare for SRST (AHCI-1.1 10.4.1) */	1318	/* prepare for SRST (AHCI-1.1 10.4.1) */
1319	rc = ahci_kick_engine(ap);	1319	rc = ahci_kick_engine(ap);
1320	if (rc && rc != -EOPNOTSUPP)	1320	if (rc && rc != -EOPNOTSUPP)
1321	ata_link_printk(link, KERN_WARNING,	1321	ata_link_printk(link, KERN_WARNING,
1322	"failed to reset engine (errno=%d)\n", rc);	1322	"failed to reset engine (errno=%d)\n", rc);
1323		1323
1324	ata_tf_init(link->device, &tf);	1324	ata_tf_init(link->device, &tf);
1325		1325
1326	/* issue the first D2H Register FIS */	1326	/* issue the first D2H Register FIS */
1327	msecs = 0;	1327	msecs = 0;
1328	now = jiffies;	1328	now = jiffies;
1329	if (time_after(now, deadline))	1329	if (time_after(deadline, now))
1330	msecs = jiffies_to_msecs(deadline - now);	1330	msecs = jiffies_to_msecs(deadline - now);
1331		1331
1332	tf.ctl \|= ATA_SRST;	1332	tf.ctl \|= ATA_SRST;
1333	if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,	1333	if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1334	AHCI_CMD_RESET \| AHCI_CMD_CLR_BUSY, msecs)) {	1334	AHCI_CMD_RESET \| AHCI_CMD_CLR_BUSY, msecs)) {
1335	rc = -EIO;	1335	rc = -EIO;
1336	reason = "1st FIS failed";	1336	reason = "1st FIS failed";
1337	goto fail;	1337	goto fail;
1338	}	1338	}
1339		1339
1340	/* spec says at least 5us, but be generous and sleep for 1ms */	1340	/* spec says at least 5us, but be generous and sleep for 1ms */
1341	msleep(1);	1341	msleep(1);
1342		1342
1343	/* issue the second D2H Register FIS */	1343	/* issue the second D2H Register FIS */
1344	tf.ctl &= ~ATA_SRST;	1344	tf.ctl &= ~ATA_SRST;
1345	ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);	1345	ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1346		1346
1347	/* wait for link to become ready */	1347	/* wait for link to become ready */
1348	rc = ata_wait_after_reset(link, deadline, check_ready);	1348	rc = ata_wait_after_reset(link, deadline, check_ready);
1349	if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {	1349	if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
1350	/*	1350	/*
1351	* Workaround for cases where link online status can't	1351	* Workaround for cases where link online status can't
1352	* be trusted. Treat device readiness timeout as link	1352	* be trusted. Treat device readiness timeout as link
1353	* offline.	1353	* offline.
1354	*/	1354	*/
1355	ata_link_printk(link, KERN_INFO,	1355	ata_link_printk(link, KERN_INFO,
1356	"device not ready, treating as offline\n");	1356	"device not ready, treating as offline\n");
1357	*class = ATA_DEV_NONE;	1357	*class = ATA_DEV_NONE;
1358	} else if (rc) {	1358	} else if (rc) {
1359	/* link occupied, -ENODEV too is an error */	1359	/* link occupied, -ENODEV too is an error */
1360	reason = "device not ready";	1360	reason = "device not ready";
1361	goto fail;	1361	goto fail;
1362	} else	1362	} else
1363	*class = ahci_dev_classify(ap);	1363	*class = ahci_dev_classify(ap);
1364		1364
1365	DPRINTK("EXIT, class=%u\n", *class);	1365	DPRINTK("EXIT, class=%u\n", *class);
1366	return 0;	1366	return 0;
1367		1367
1368	fail:	1368	fail:
1369	ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);	1369	ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
1370	return rc;	1370	return rc;
1371	}	1371	}
1372		1372
1373	int ahci_check_ready(struct ata_link *link)	1373	int ahci_check_ready(struct ata_link *link)
1374	{	1374	{
1375	void __iomem *port_mmio = ahci_port_base(link->ap);	1375	void __iomem *port_mmio = ahci_port_base(link->ap);
1376	u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;	1376	u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1377		1377
1378	return ata_check_ready(status);	1378	return ata_check_ready(status);
1379	}	1379	}
1380	EXPORT_SYMBOL_GPL(ahci_check_ready);	1380	EXPORT_SYMBOL_GPL(ahci_check_ready);
1381		1381
1382	static int ahci_softreset(struct ata_link link, unsigned int class,	1382	static int ahci_softreset(struct ata_link link, unsigned int class,
1383	unsigned long deadline)	1383	unsigned long deadline)
1384	{	1384	{
1385	int pmp = sata_srst_pmp(link);	1385	int pmp = sata_srst_pmp(link);
1386		1386
1387	DPRINTK("ENTER\n");	1387	DPRINTK("ENTER\n");
1388		1388
1389	return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);	1389	return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1390	}	1390	}
1391	EXPORT_SYMBOL_GPL(ahci_do_softreset);	1391	EXPORT_SYMBOL_GPL(ahci_do_softreset);
1392		1392
1393	static int ahci_hardreset(struct ata_link link, unsigned int class,	1393	static int ahci_hardreset(struct ata_link link, unsigned int class,
1394	unsigned long deadline)	1394	unsigned long deadline)
1395	{	1395	{
1396	const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);	1396	const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1397	struct ata_port *ap = link->ap;	1397	struct ata_port *ap = link->ap;
1398	struct ahci_port_priv *pp = ap->private_data;	1398	struct ahci_port_priv *pp = ap->private_data;
1399	u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;	1399	u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1400	struct ata_taskfile tf;	1400	struct ata_taskfile tf;
1401	bool online;	1401	bool online;
1402	int rc;	1402	int rc;
1403		1403
1404	DPRINTK("ENTER\n");	1404	DPRINTK("ENTER\n");
1405		1405
1406	ahci_stop_engine(ap);	1406	ahci_stop_engine(ap);
1407		1407
1408	/* clear D2H reception area to properly wait for D2H FIS */	1408	/* clear D2H reception area to properly wait for D2H FIS */
1409	ata_tf_init(link->device, &tf);	1409	ata_tf_init(link->device, &tf);
1410	tf.command = 0x80;	1410	tf.command = 0x80;
1411	ata_tf_to_fis(&tf, 0, 0, d2h_fis);	1411	ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1412		1412
1413	rc = sata_link_hardreset(link, timing, deadline, &online,	1413	rc = sata_link_hardreset(link, timing, deadline, &online,
1414	ahci_check_ready);	1414	ahci_check_ready);
1415		1415
1416	ahci_start_engine(ap);	1416	ahci_start_engine(ap);
1417		1417
1418	if (online)	1418	if (online)
1419	*class = ahci_dev_classify(ap);	1419	*class = ahci_dev_classify(ap);
1420		1420
1421	DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);	1421	DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1422	return rc;	1422	return rc;
1423	}	1423	}
1424		1424
1425	static void ahci_postreset(struct ata_link link, unsigned int class)	1425	static void ahci_postreset(struct ata_link link, unsigned int class)
1426	{	1426	{
1427	struct ata_port *ap = link->ap;	1427	struct ata_port *ap = link->ap;
1428	void __iomem *port_mmio = ahci_port_base(ap);	1428	void __iomem *port_mmio = ahci_port_base(ap);
1429	u32 new_tmp, tmp;	1429	u32 new_tmp, tmp;
1430		1430
1431	ata_std_postreset(link, class);	1431	ata_std_postreset(link, class);
1432		1432
1433	/* Make sure port's ATAPI bit is set appropriately */	1433	/* Make sure port's ATAPI bit is set appropriately */
1434	new_tmp = tmp = readl(port_mmio + PORT_CMD);	1434	new_tmp = tmp = readl(port_mmio + PORT_CMD);
1435	if (*class == ATA_DEV_ATAPI)	1435	if (*class == ATA_DEV_ATAPI)
1436	new_tmp \|= PORT_CMD_ATAPI;	1436	new_tmp \|= PORT_CMD_ATAPI;
1437	else	1437	else
1438	new_tmp &= ~PORT_CMD_ATAPI;	1438	new_tmp &= ~PORT_CMD_ATAPI;
1439	if (new_tmp != tmp) {	1439	if (new_tmp != tmp) {
1440	writel(new_tmp, port_mmio + PORT_CMD);	1440	writel(new_tmp, port_mmio + PORT_CMD);
1441	readl(port_mmio + PORT_CMD); /* flush */	1441	readl(port_mmio + PORT_CMD); /* flush */
1442	}	1442	}
1443	}	1443	}
1444		1444
1445	static unsigned int ahci_fill_sg(struct ata_queued_cmd qc, void cmd_tbl)	1445	static unsigned int ahci_fill_sg(struct ata_queued_cmd qc, void cmd_tbl)
1446	{	1446	{
1447	struct scatterlist *sg;	1447	struct scatterlist *sg;
1448	struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;	1448	struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1449	unsigned int si;	1449	unsigned int si;
1450		1450
1451	VPRINTK("ENTER\n");	1451	VPRINTK("ENTER\n");
1452		1452
1453	/*	1453	/*
1454	* Next, the S/G list.	1454	* Next, the S/G list.
1455	*/	1455	*/
1456	for_each_sg(qc->sg, sg, qc->n_elem, si) {	1456	for_each_sg(qc->sg, sg, qc->n_elem, si) {
1457	dma_addr_t addr = sg_dma_address(sg);	1457	dma_addr_t addr = sg_dma_address(sg);
1458	u32 sg_len = sg_dma_len(sg);	1458	u32 sg_len = sg_dma_len(sg);
1459		1459
1460	ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);	1460	ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1461	ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);	1461	ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1462	ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);	1462	ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1463	}	1463	}
1464		1464
1465	return si;	1465	return si;
1466	}	1466	}
1467		1467
1468	static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc)	1468	static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc)
1469	{	1469	{
1470	struct ata_port *ap = qc->ap;	1470	struct ata_port *ap = qc->ap;
1471	struct ahci_port_priv *pp = ap->private_data;	1471	struct ahci_port_priv *pp = ap->private_data;
1472		1472
1473	if (!sata_pmp_attached(ap) \|\| pp->fbs_enabled)	1473	if (!sata_pmp_attached(ap) \|\| pp->fbs_enabled)
1474	return ata_std_qc_defer(qc);	1474	return ata_std_qc_defer(qc);
1475	else	1475	else
1476	return sata_pmp_qc_defer_cmd_switch(qc);	1476	return sata_pmp_qc_defer_cmd_switch(qc);
1477	}	1477	}
1478		1478
1479	static void ahci_qc_prep(struct ata_queued_cmd *qc)	1479	static void ahci_qc_prep(struct ata_queued_cmd *qc)
1480	{	1480	{
1481	struct ata_port *ap = qc->ap;	1481	struct ata_port *ap = qc->ap;
1482	struct ahci_port_priv *pp = ap->private_data;	1482	struct ahci_port_priv *pp = ap->private_data;
1483	int is_atapi = ata_is_atapi(qc->tf.protocol);	1483	int is_atapi = ata_is_atapi(qc->tf.protocol);
1484	void *cmd_tbl;	1484	void *cmd_tbl;
1485	u32 opts;	1485	u32 opts;
1486	const u32 cmd_fis_len = 5; /* five dwords */	1486	const u32 cmd_fis_len = 5; /* five dwords */
1487	unsigned int n_elem;	1487	unsigned int n_elem;
1488		1488
1489	/*	1489	/*
1490	* Fill in command table information. First, the header,	1490	* Fill in command table information. First, the header,
1491	* a SATA Register - Host to Device command FIS.	1491	* a SATA Register - Host to Device command FIS.
1492	*/	1492	*/
1493	cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;	1493	cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1494		1494
1495	ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);	1495	ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1496	if (is_atapi) {	1496	if (is_atapi) {
1497	memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);	1497	memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1498	memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);	1498	memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1499	}	1499	}
1500		1500
1501	n_elem = 0;	1501	n_elem = 0;
1502	if (qc->flags & ATA_QCFLAG_DMAMAP)	1502	if (qc->flags & ATA_QCFLAG_DMAMAP)
1503	n_elem = ahci_fill_sg(qc, cmd_tbl);	1503	n_elem = ahci_fill_sg(qc, cmd_tbl);
1504		1504
1505	/*	1505	/*
1506	* Fill in command slot information.	1506	* Fill in command slot information.
1507	*/	1507	*/
1508	opts = cmd_fis_len \| n_elem << 16 \| (qc->dev->link->pmp << 12);	1508	opts = cmd_fis_len \| n_elem << 16 \| (qc->dev->link->pmp << 12);
1509	if (qc->tf.flags & ATA_TFLAG_WRITE)	1509	if (qc->tf.flags & ATA_TFLAG_WRITE)
1510	opts \|= AHCI_CMD_WRITE;	1510	opts \|= AHCI_CMD_WRITE;
1511	if (is_atapi)	1511	if (is_atapi)
1512	opts \|= AHCI_CMD_ATAPI \| AHCI_CMD_PREFETCH;	1512	opts \|= AHCI_CMD_ATAPI \| AHCI_CMD_PREFETCH;
1513		1513
1514	ahci_fill_cmd_slot(pp, qc->tag, opts);	1514	ahci_fill_cmd_slot(pp, qc->tag, opts);
1515	}	1515	}
1516		1516
1517	static void ahci_fbs_dec_intr(struct ata_port *ap)	1517	static void ahci_fbs_dec_intr(struct ata_port *ap)
1518	{	1518	{
1519	struct ahci_port_priv *pp = ap->private_data;	1519	struct ahci_port_priv *pp = ap->private_data;
1520	void __iomem *port_mmio = ahci_port_base(ap);	1520	void __iomem *port_mmio = ahci_port_base(ap);
1521	u32 fbs = readl(port_mmio + PORT_FBS);	1521	u32 fbs = readl(port_mmio + PORT_FBS);
1522	int retries = 3;	1522	int retries = 3;
1523		1523
1524	DPRINTK("ENTER\n");	1524	DPRINTK("ENTER\n");
1525	BUG_ON(!pp->fbs_enabled);	1525	BUG_ON(!pp->fbs_enabled);
1526		1526
1527	/* time to wait for DEC is not specified by AHCI spec,	1527	/* time to wait for DEC is not specified by AHCI spec,
1528	* add a retry loop for safety.	1528	* add a retry loop for safety.
1529	*/	1529	*/
1530	writel(fbs \| PORT_FBS_DEC, port_mmio + PORT_FBS);	1530	writel(fbs \| PORT_FBS_DEC, port_mmio + PORT_FBS);
1531	fbs = readl(port_mmio + PORT_FBS);	1531	fbs = readl(port_mmio + PORT_FBS);
1532	while ((fbs & PORT_FBS_DEC) && retries--) {	1532	while ((fbs & PORT_FBS_DEC) && retries--) {
1533	udelay(1);	1533	udelay(1);
1534	fbs = readl(port_mmio + PORT_FBS);	1534	fbs = readl(port_mmio + PORT_FBS);
1535	}	1535	}
1536		1536
1537	if (fbs & PORT_FBS_DEC)	1537	if (fbs & PORT_FBS_DEC)
1538	dev_printk(KERN_ERR, ap->host->dev,	1538	dev_printk(KERN_ERR, ap->host->dev,
1539	"failed to clear device error\n");	1539	"failed to clear device error\n");
1540	}	1540	}
1541		1541
1542	static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)	1542	static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1543	{	1543	{
1544	struct ahci_host_priv *hpriv = ap->host->private_data;	1544	struct ahci_host_priv *hpriv = ap->host->private_data;
1545	struct ahci_port_priv *pp = ap->private_data;	1545	struct ahci_port_priv *pp = ap->private_data;
1546	struct ata_eh_info *host_ehi = &ap->link.eh_info;	1546	struct ata_eh_info *host_ehi = &ap->link.eh_info;
1547	struct ata_link *link = NULL;	1547	struct ata_link *link = NULL;
1548	struct ata_queued_cmd *active_qc;	1548	struct ata_queued_cmd *active_qc;
1549	struct ata_eh_info *active_ehi;	1549	struct ata_eh_info *active_ehi;
1550	bool fbs_need_dec = false;	1550	bool fbs_need_dec = false;
1551	u32 serror;	1551	u32 serror;
1552		1552
1553	/* determine active link with error */	1553	/* determine active link with error */
1554	if (pp->fbs_enabled) {	1554	if (pp->fbs_enabled) {
1555	void __iomem *port_mmio = ahci_port_base(ap);	1555	void __iomem *port_mmio = ahci_port_base(ap);
1556	u32 fbs = readl(port_mmio + PORT_FBS);	1556	u32 fbs = readl(port_mmio + PORT_FBS);
1557	int pmp = fbs >> PORT_FBS_DWE_OFFSET;	1557	int pmp = fbs >> PORT_FBS_DWE_OFFSET;
1558		1558
1559	if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links) &&	1559	if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links) &&
1560	ata_link_online(&ap->pmp_link[pmp])) {	1560	ata_link_online(&ap->pmp_link[pmp])) {
1561	link = &ap->pmp_link[pmp];	1561	link = &ap->pmp_link[pmp];
1562	fbs_need_dec = true;	1562	fbs_need_dec = true;
1563	}	1563	}
1564		1564
1565	} else	1565	} else
1566	ata_for_each_link(link, ap, EDGE)	1566	ata_for_each_link(link, ap, EDGE)
1567	if (ata_link_active(link))	1567	if (ata_link_active(link))
1568	break;	1568	break;
1569		1569
1570	if (!link)	1570	if (!link)
1571	link = &ap->link;	1571	link = &ap->link;
1572		1572
1573	active_qc = ata_qc_from_tag(ap, link->active_tag);	1573	active_qc = ata_qc_from_tag(ap, link->active_tag);
1574	active_ehi = &link->eh_info;	1574	active_ehi = &link->eh_info;
1575		1575
1576	/* record irq stat */	1576	/* record irq stat */
1577	ata_ehi_clear_desc(host_ehi);	1577	ata_ehi_clear_desc(host_ehi);
1578	ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);	1578	ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1579		1579
1580	/* AHCI needs SError cleared; otherwise, it might lock up */	1580	/* AHCI needs SError cleared; otherwise, it might lock up */
1581	ahci_scr_read(&ap->link, SCR_ERROR, &serror);	1581	ahci_scr_read(&ap->link, SCR_ERROR, &serror);
1582	ahci_scr_write(&ap->link, SCR_ERROR, serror);	1582	ahci_scr_write(&ap->link, SCR_ERROR, serror);
1583	host_ehi->serror \|= serror;	1583	host_ehi->serror \|= serror;
1584		1584
1585	/* some controllers set IRQ_IF_ERR on device errors, ignore it */	1585	/* some controllers set IRQ_IF_ERR on device errors, ignore it */
1586	if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)	1586	if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1587	irq_stat &= ~PORT_IRQ_IF_ERR;	1587	irq_stat &= ~PORT_IRQ_IF_ERR;
1588		1588
1589	if (irq_stat & PORT_IRQ_TF_ERR) {	1589	if (irq_stat & PORT_IRQ_TF_ERR) {
1590	/* If qc is active, charge it; otherwise, the active	1590	/* If qc is active, charge it; otherwise, the active
1591	* link. There's no active qc on NCQ errors. It will	1591	* link. There's no active qc on NCQ errors. It will
1592	* be determined by EH by reading log page 10h.	1592	* be determined by EH by reading log page 10h.
1593	*/	1593	*/
1594	if (active_qc)	1594	if (active_qc)
1595	active_qc->err_mask \|= AC_ERR_DEV;	1595	active_qc->err_mask \|= AC_ERR_DEV;
1596	else	1596	else
1597	active_ehi->err_mask \|= AC_ERR_DEV;	1597	active_ehi->err_mask \|= AC_ERR_DEV;
1598		1598
1599	if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)	1599	if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1600	host_ehi->serror &= ~SERR_INTERNAL;	1600	host_ehi->serror &= ~SERR_INTERNAL;
1601	}	1601	}
1602		1602
1603	if (irq_stat & PORT_IRQ_UNK_FIS) {	1603	if (irq_stat & PORT_IRQ_UNK_FIS) {
1604	u32 unk = (u32 )(pp->rx_fis + RX_FIS_UNK);	1604	u32 unk = (u32 )(pp->rx_fis + RX_FIS_UNK);
1605		1605
1606	active_ehi->err_mask \|= AC_ERR_HSM;	1606	active_ehi->err_mask \|= AC_ERR_HSM;
1607	active_ehi->action \|= ATA_EH_RESET;	1607	active_ehi->action \|= ATA_EH_RESET;
1608	ata_ehi_push_desc(active_ehi,	1608	ata_ehi_push_desc(active_ehi,
1609	"unknown FIS %08x %08x %08x %08x" ,	1609	"unknown FIS %08x %08x %08x %08x" ,
1610	unk[0], unk[1], unk[2], unk[3]);	1610	unk[0], unk[1], unk[2], unk[3]);
1611	}	1611	}
1612		1612
1613	if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {	1613	if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
1614	active_ehi->err_mask \|= AC_ERR_HSM;	1614	active_ehi->err_mask \|= AC_ERR_HSM;
1615	active_ehi->action \|= ATA_EH_RESET;	1615	active_ehi->action \|= ATA_EH_RESET;
1616	ata_ehi_push_desc(active_ehi, "incorrect PMP");	1616	ata_ehi_push_desc(active_ehi, "incorrect PMP");
1617	}	1617	}
1618		1618
1619	if (irq_stat & (PORT_IRQ_HBUS_ERR \| PORT_IRQ_HBUS_DATA_ERR)) {	1619	if (irq_stat & (PORT_IRQ_HBUS_ERR \| PORT_IRQ_HBUS_DATA_ERR)) {
1620	host_ehi->err_mask \|= AC_ERR_HOST_BUS;	1620	host_ehi->err_mask \|= AC_ERR_HOST_BUS;
1621	host_ehi->action \|= ATA_EH_RESET;	1621	host_ehi->action \|= ATA_EH_RESET;
1622	ata_ehi_push_desc(host_ehi, "host bus error");	1622	ata_ehi_push_desc(host_ehi, "host bus error");
1623	}	1623	}
1624		1624
1625	if (irq_stat & PORT_IRQ_IF_ERR) {	1625	if (irq_stat & PORT_IRQ_IF_ERR) {
1626	if (fbs_need_dec)	1626	if (fbs_need_dec)
1627	active_ehi->err_mask \|= AC_ERR_DEV;	1627	active_ehi->err_mask \|= AC_ERR_DEV;
1628	else {	1628	else {
1629	host_ehi->err_mask \|= AC_ERR_ATA_BUS;	1629	host_ehi->err_mask \|= AC_ERR_ATA_BUS;
1630	host_ehi->action \|= ATA_EH_RESET;	1630	host_ehi->action \|= ATA_EH_RESET;
1631	}	1631	}
1632		1632
1633	ata_ehi_push_desc(host_ehi, "interface fatal error");	1633	ata_ehi_push_desc(host_ehi, "interface fatal error");
1634	}	1634	}
1635		1635
1636	if (irq_stat & (PORT_IRQ_CONNECT \| PORT_IRQ_PHYRDY)) {	1636	if (irq_stat & (PORT_IRQ_CONNECT \| PORT_IRQ_PHYRDY)) {
1637	ata_ehi_hotplugged(host_ehi);	1637	ata_ehi_hotplugged(host_ehi);
1638	ata_ehi_push_desc(host_ehi, "%s",	1638	ata_ehi_push_desc(host_ehi, "%s",
1639	irq_stat & PORT_IRQ_CONNECT ?	1639	irq_stat & PORT_IRQ_CONNECT ?
1640	"connection status changed" : "PHY RDY changed");	1640	"connection status changed" : "PHY RDY changed");
1641	}	1641	}
1642		1642
1643	/* okay, let's hand over to EH */	1643	/* okay, let's hand over to EH */
1644		1644
1645	if (irq_stat & PORT_IRQ_FREEZE)	1645	if (irq_stat & PORT_IRQ_FREEZE)
1646	ata_port_freeze(ap);	1646	ata_port_freeze(ap);
1647	else if (fbs_need_dec) {	1647	else if (fbs_need_dec) {
1648	ata_link_abort(link);	1648	ata_link_abort(link);
1649	ahci_fbs_dec_intr(ap);	1649	ahci_fbs_dec_intr(ap);
1650	} else	1650	} else
1651	ata_port_abort(ap);	1651	ata_port_abort(ap);
1652	}	1652	}
1653		1653
1654	static void ahci_port_intr(struct ata_port *ap)	1654	static void ahci_port_intr(struct ata_port *ap)
1655	{	1655	{
1656	void __iomem *port_mmio = ahci_port_base(ap);	1656	void __iomem *port_mmio = ahci_port_base(ap);
1657	struct ata_eh_info *ehi = &ap->link.eh_info;	1657	struct ata_eh_info *ehi = &ap->link.eh_info;
1658	struct ahci_port_priv *pp = ap->private_data;	1658	struct ahci_port_priv *pp = ap->private_data;
1659	struct ahci_host_priv *hpriv = ap->host->private_data;	1659	struct ahci_host_priv *hpriv = ap->host->private_data;
1660	int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);	1660	int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
1661	u32 status, qc_active = 0;	1661	u32 status, qc_active = 0;
1662	int rc;	1662	int rc;
1663		1663
1664	status = readl(port_mmio + PORT_IRQ_STAT);	1664	status = readl(port_mmio + PORT_IRQ_STAT);
1665	writel(status, port_mmio + PORT_IRQ_STAT);	1665	writel(status, port_mmio + PORT_IRQ_STAT);
1666		1666
1667	/* ignore BAD_PMP while resetting */	1667	/* ignore BAD_PMP while resetting */
1668	if (unlikely(resetting))	1668	if (unlikely(resetting))
1669	status &= ~PORT_IRQ_BAD_PMP;	1669	status &= ~PORT_IRQ_BAD_PMP;
1670		1670
1671	/* If we are getting PhyRdy, this is	1671	/* If we are getting PhyRdy, this is
1672	* just a power state change, we should	1672	* just a power state change, we should
1673	* clear out this, plus the PhyRdy/Comm	1673	* clear out this, plus the PhyRdy/Comm
1674	* Wake bits from Serror	1674	* Wake bits from Serror
1675	*/	1675	*/
1676	if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) &&	1676	if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) &&
1677	(status & PORT_IRQ_PHYRDY)) {	1677	(status & PORT_IRQ_PHYRDY)) {
1678	status &= ~PORT_IRQ_PHYRDY;	1678	status &= ~PORT_IRQ_PHYRDY;
1679	ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) \| (1 << 18)));	1679	ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) \| (1 << 18)));
1680	}	1680	}
1681		1681
1682	if (unlikely(status & PORT_IRQ_ERROR)) {	1682	if (unlikely(status & PORT_IRQ_ERROR)) {
1683	ahci_error_intr(ap, status);	1683	ahci_error_intr(ap, status);
1684	return;	1684	return;
1685	}	1685	}
1686		1686
1687	if (status & PORT_IRQ_SDB_FIS) {	1687	if (status & PORT_IRQ_SDB_FIS) {
1688	/* If SNotification is available, leave notification	1688	/* If SNotification is available, leave notification
1689	* handling to sata_async_notification(). If not,	1689	* handling to sata_async_notification(). If not,
1690	* emulate it by snooping SDB FIS RX area.	1690	* emulate it by snooping SDB FIS RX area.
1691	*	1691	*
1692	* Snooping FIS RX area is probably cheaper than	1692	* Snooping FIS RX area is probably cheaper than
1693	* poking SNotification but some constrollers which	1693	* poking SNotification but some constrollers which
1694	* implement SNotification, ICH9 for example, don't	1694	* implement SNotification, ICH9 for example, don't
1695	* store AN SDB FIS into receive area.	1695	* store AN SDB FIS into receive area.
1696	*/	1696	*/
1697	if (hpriv->cap & HOST_CAP_SNTF)	1697	if (hpriv->cap & HOST_CAP_SNTF)
1698	sata_async_notification(ap);	1698	sata_async_notification(ap);
1699	else {	1699	else {
1700	/* If the 'N' bit in word 0 of the FIS is set,	1700	/* If the 'N' bit in word 0 of the FIS is set,
1701	* we just received asynchronous notification.	1701	* we just received asynchronous notification.
1702	* Tell libata about it.	1702	* Tell libata about it.
1703	*	1703	*
1704	* Lack of SNotification should not appear in	1704	* Lack of SNotification should not appear in
1705	* ahci 1.2, so the workaround is unnecessary	1705	* ahci 1.2, so the workaround is unnecessary
1706	* when FBS is enabled.	1706	* when FBS is enabled.
1707	*/	1707	*/
1708	if (pp->fbs_enabled)	1708	if (pp->fbs_enabled)
1709	WARN_ON_ONCE(1);	1709	WARN_ON_ONCE(1);
1710	else {	1710	else {
1711	const __le32 *f = pp->rx_fis + RX_FIS_SDB;	1711	const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1712	u32 f0 = le32_to_cpu(f[0]);	1712	u32 f0 = le32_to_cpu(f[0]);
1713	if (f0 & (1 << 15))	1713	if (f0 & (1 << 15))
1714	sata_async_notification(ap);	1714	sata_async_notification(ap);
1715	}	1715	}
1716	}	1716	}
1717	}	1717	}
1718		1718
1719	/* pp->active_link is not reliable once FBS is enabled, both	1719	/* pp->active_link is not reliable once FBS is enabled, both
1720	* PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because	1720	* PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because
1721	* NCQ and non-NCQ commands may be in flight at the same time.	1721	* NCQ and non-NCQ commands may be in flight at the same time.
1722	*/	1722	*/
1723	if (pp->fbs_enabled) {	1723	if (pp->fbs_enabled) {
1724	if (ap->qc_active) {	1724	if (ap->qc_active) {
1725	qc_active = readl(port_mmio + PORT_SCR_ACT);	1725	qc_active = readl(port_mmio + PORT_SCR_ACT);
1726	qc_active \|= readl(port_mmio + PORT_CMD_ISSUE);	1726	qc_active \|= readl(port_mmio + PORT_CMD_ISSUE);
1727	}	1727	}
1728	} else {	1728	} else {
1729	/* pp->active_link is valid iff any command is in flight */	1729	/* pp->active_link is valid iff any command is in flight */
1730	if (ap->qc_active && pp->active_link->sactive)	1730	if (ap->qc_active && pp->active_link->sactive)
1731	qc_active = readl(port_mmio + PORT_SCR_ACT);	1731	qc_active = readl(port_mmio + PORT_SCR_ACT);
1732	else	1732	else
1733	qc_active = readl(port_mmio + PORT_CMD_ISSUE);	1733	qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1734	}	1734	}
1735		1735
1736		1736
1737	rc = ata_qc_complete_multiple(ap, qc_active);	1737	rc = ata_qc_complete_multiple(ap, qc_active);
1738		1738
1739	/* while resetting, invalid completions are expected */	1739	/* while resetting, invalid completions are expected */
1740	if (unlikely(rc < 0 && !resetting)) {	1740	if (unlikely(rc < 0 && !resetting)) {
1741	ehi->err_mask \|= AC_ERR_HSM;	1741	ehi->err_mask \|= AC_ERR_HSM;
1742	ehi->action \|= ATA_EH_RESET;	1742	ehi->action \|= ATA_EH_RESET;
1743	ata_port_freeze(ap);	1743	ata_port_freeze(ap);
1744	}	1744	}
1745	}	1745	}
1746		1746
1747	irqreturn_t ahci_interrupt(int irq, void *dev_instance)	1747	irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1748	{	1748	{
1749	struct ata_host *host = dev_instance;	1749	struct ata_host *host = dev_instance;
1750	struct ahci_host_priv *hpriv;	1750	struct ahci_host_priv *hpriv;
1751	unsigned int i, handled = 0;	1751	unsigned int i, handled = 0;
1752	void __iomem *mmio;	1752	void __iomem *mmio;
1753	u32 irq_stat, irq_masked;	1753	u32 irq_stat, irq_masked;
1754		1754
1755	VPRINTK("ENTER\n");	1755	VPRINTK("ENTER\n");
1756		1756
1757	hpriv = host->private_data;	1757	hpriv = host->private_data;
1758	mmio = hpriv->mmio;	1758	mmio = hpriv->mmio;
1759		1759
1760	/* sigh. 0xffffffff is a valid return from h/w */	1760	/* sigh. 0xffffffff is a valid return from h/w */
1761	irq_stat = readl(mmio + HOST_IRQ_STAT);	1761	irq_stat = readl(mmio + HOST_IRQ_STAT);
1762	if (!irq_stat)	1762	if (!irq_stat)
1763	return IRQ_NONE;	1763	return IRQ_NONE;
1764		1764
1765	irq_masked = irq_stat & hpriv->port_map;	1765	irq_masked = irq_stat & hpriv->port_map;
1766		1766
1767	spin_lock(&host->lock);	1767	spin_lock(&host->lock);
1768		1768
1769	for (i = 0; i < host->n_ports; i++) {	1769	for (i = 0; i < host->n_ports; i++) {
1770	struct ata_port *ap;	1770	struct ata_port *ap;
1771		1771
1772	if (!(irq_masked & (1 << i)))	1772	if (!(irq_masked & (1 << i)))
1773	continue;	1773	continue;
1774		1774
1775	ap = host->ports[i];	1775	ap = host->ports[i];
1776	if (ap) {	1776	if (ap) {
1777	ahci_port_intr(ap);	1777	ahci_port_intr(ap);
1778	VPRINTK("port %u\n", i);	1778	VPRINTK("port %u\n", i);
1779	} else {	1779	} else {
1780	VPRINTK("port %u (no irq)\n", i);	1780	VPRINTK("port %u (no irq)\n", i);
1781	if (ata_ratelimit())	1781	if (ata_ratelimit())
1782	dev_printk(KERN_WARNING, host->dev,	1782	dev_printk(KERN_WARNING, host->dev,
1783	"interrupt on disabled port %u\n", i);	1783	"interrupt on disabled port %u\n", i);
1784	}	1784	}
1785		1785
1786	handled = 1;	1786	handled = 1;
1787	}	1787	}
1788		1788
1789	/* HOST_IRQ_STAT behaves as level triggered latch meaning that	1789	/* HOST_IRQ_STAT behaves as level triggered latch meaning that
1790	* it should be cleared after all the port events are cleared;	1790	* it should be cleared after all the port events are cleared;
1791	* otherwise, it will raise a spurious interrupt after each	1791	* otherwise, it will raise a spurious interrupt after each
1792	* valid one. Please read section 10.6.2 of ahci 1.1 for more	1792	* valid one. Please read section 10.6.2 of ahci 1.1 for more
1793	* information.	1793	* information.
1794	*	1794	*
1795	* Also, use the unmasked value to clear interrupt as spurious	1795	* Also, use the unmasked value to clear interrupt as spurious
1796	* pending event on a dummy port might cause screaming IRQ.	1796	* pending event on a dummy port might cause screaming IRQ.
1797	*/	1797	*/
1798	writel(irq_stat, mmio + HOST_IRQ_STAT);	1798	writel(irq_stat, mmio + HOST_IRQ_STAT);
1799		1799
1800	spin_unlock(&host->lock);	1800	spin_unlock(&host->lock);
1801		1801
1802	VPRINTK("EXIT\n");	1802	VPRINTK("EXIT\n");
1803		1803
1804	return IRQ_RETVAL(handled);	1804	return IRQ_RETVAL(handled);
1805	}	1805	}
1806	EXPORT_SYMBOL_GPL(ahci_interrupt);	1806	EXPORT_SYMBOL_GPL(ahci_interrupt);
1807		1807
1808	static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)	1808	static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1809	{	1809	{
1810	struct ata_port *ap = qc->ap;	1810	struct ata_port *ap = qc->ap;
1811	void __iomem *port_mmio = ahci_port_base(ap);	1811	void __iomem *port_mmio = ahci_port_base(ap);
1812	struct ahci_port_priv *pp = ap->private_data;	1812	struct ahci_port_priv *pp = ap->private_data;
1813		1813
1814	/* Keep track of the currently active link. It will be used	1814	/* Keep track of the currently active link. It will be used
1815	* in completion path to determine whether NCQ phase is in	1815	* in completion path to determine whether NCQ phase is in
1816	* progress.	1816	* progress.
1817	*/	1817	*/
1818	pp->active_link = qc->dev->link;	1818	pp->active_link = qc->dev->link;
1819		1819
1820	if (qc->tf.protocol == ATA_PROT_NCQ)	1820	if (qc->tf.protocol == ATA_PROT_NCQ)
1821	writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);	1821	writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1822		1822
1823	if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) {	1823	if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) {
1824	u32 fbs = readl(port_mmio + PORT_FBS);	1824	u32 fbs = readl(port_mmio + PORT_FBS);
1825	fbs &= ~(PORT_FBS_DEV_MASK \| PORT_FBS_DEC);	1825	fbs &= ~(PORT_FBS_DEV_MASK \| PORT_FBS_DEC);
1826	fbs \|= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET;	1826	fbs \|= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET;
1827	writel(fbs, port_mmio + PORT_FBS);	1827	writel(fbs, port_mmio + PORT_FBS);
1828	pp->fbs_last_dev = qc->dev->link->pmp;	1828	pp->fbs_last_dev = qc->dev->link->pmp;
1829	}	1829	}
1830		1830
1831	writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);	1831	writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1832		1832
1833	ahci_sw_activity(qc->dev->link);	1833	ahci_sw_activity(qc->dev->link);
1834		1834
1835	return 0;	1835	return 0;
1836	}	1836	}
1837		1837
1838	static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)	1838	static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
1839	{	1839	{
1840	struct ahci_port_priv *pp = qc->ap->private_data;	1840	struct ahci_port_priv *pp = qc->ap->private_data;
1841	u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;	1841	u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1842		1842
1843	if (pp->fbs_enabled)	1843	if (pp->fbs_enabled)
1844	d2h_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ;	1844	d2h_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ;
1845		1845
1846	ata_tf_from_fis(d2h_fis, &qc->result_tf);	1846	ata_tf_from_fis(d2h_fis, &qc->result_tf);
1847	return true;	1847	return true;
1848	}	1848	}
1849		1849
1850	static void ahci_freeze(struct ata_port *ap)	1850	static void ahci_freeze(struct ata_port *ap)
1851	{	1851	{
1852	void __iomem *port_mmio = ahci_port_base(ap);	1852	void __iomem *port_mmio = ahci_port_base(ap);
1853		1853
1854	/* turn IRQ off */	1854	/* turn IRQ off */
1855	writel(0, port_mmio + PORT_IRQ_MASK);	1855	writel(0, port_mmio + PORT_IRQ_MASK);
1856	}	1856	}
1857		1857
1858	static void ahci_thaw(struct ata_port *ap)	1858	static void ahci_thaw(struct ata_port *ap)
1859	{	1859	{
1860	struct ahci_host_priv *hpriv = ap->host->private_data;	1860	struct ahci_host_priv *hpriv = ap->host->private_data;
1861	void __iomem *mmio = hpriv->mmio;	1861	void __iomem *mmio = hpriv->mmio;
1862	void __iomem *port_mmio = ahci_port_base(ap);	1862	void __iomem *port_mmio = ahci_port_base(ap);
1863	u32 tmp;	1863	u32 tmp;
1864	struct ahci_port_priv *pp = ap->private_data;	1864	struct ahci_port_priv *pp = ap->private_data;
1865		1865
1866	/* clear IRQ */	1866	/* clear IRQ */
1867	tmp = readl(port_mmio + PORT_IRQ_STAT);	1867	tmp = readl(port_mmio + PORT_IRQ_STAT);
1868	writel(tmp, port_mmio + PORT_IRQ_STAT);	1868	writel(tmp, port_mmio + PORT_IRQ_STAT);
1869	writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);	1869	writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
1870		1870
1871	/* turn IRQ back on */	1871	/* turn IRQ back on */
1872	writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);	1872	writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1873	}	1873	}
1874		1874
1875	static void ahci_error_handler(struct ata_port *ap)	1875	static void ahci_error_handler(struct ata_port *ap)
1876	{	1876	{
1877	if (!(ap->pflags & ATA_PFLAG_FROZEN)) {	1877	if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1878	/* restart engine */	1878	/* restart engine */
1879	ahci_stop_engine(ap);	1879	ahci_stop_engine(ap);
1880	ahci_start_engine(ap);	1880	ahci_start_engine(ap);
1881	}	1881	}
1882		1882
1883	sata_pmp_error_handler(ap);	1883	sata_pmp_error_handler(ap);
1884		1884
1885	if (!ata_dev_enabled(ap->link.device))	1885	if (!ata_dev_enabled(ap->link.device))
1886	ahci_stop_engine(ap);	1886	ahci_stop_engine(ap);
1887	}	1887	}
1888		1888
1889	static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)	1889	static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1890	{	1890	{
1891	struct ata_port *ap = qc->ap;	1891	struct ata_port *ap = qc->ap;
1892		1892
1893	/* make DMA engine forget about the failed command */	1893	/* make DMA engine forget about the failed command */
1894	if (qc->flags & ATA_QCFLAG_FAILED)	1894	if (qc->flags & ATA_QCFLAG_FAILED)
1895	ahci_kick_engine(ap);	1895	ahci_kick_engine(ap);
1896	}	1896	}
1897		1897
1898	static void ahci_enable_fbs(struct ata_port *ap)	1898	static void ahci_enable_fbs(struct ata_port *ap)
1899	{	1899	{
1900	struct ahci_port_priv *pp = ap->private_data;	1900	struct ahci_port_priv *pp = ap->private_data;
1901	void __iomem *port_mmio = ahci_port_base(ap);	1901	void __iomem *port_mmio = ahci_port_base(ap);
1902	u32 fbs;	1902	u32 fbs;
1903	int rc;	1903	int rc;
1904		1904
1905	if (!pp->fbs_supported)	1905	if (!pp->fbs_supported)
1906	return;	1906	return;
1907		1907
1908	fbs = readl(port_mmio + PORT_FBS);	1908	fbs = readl(port_mmio + PORT_FBS);
1909	if (fbs & PORT_FBS_EN) {	1909	if (fbs & PORT_FBS_EN) {
1910	pp->fbs_enabled = true;	1910	pp->fbs_enabled = true;
1911	pp->fbs_last_dev = -1; /* initialization */	1911	pp->fbs_last_dev = -1; /* initialization */
1912	return;	1912	return;
1913	}	1913	}
1914		1914
1915	rc = ahci_stop_engine(ap);	1915	rc = ahci_stop_engine(ap);
1916	if (rc)	1916	if (rc)
1917	return;	1917	return;
1918		1918
1919	writel(fbs \| PORT_FBS_EN, port_mmio + PORT_FBS);	1919	writel(fbs \| PORT_FBS_EN, port_mmio + PORT_FBS);
1920	fbs = readl(port_mmio + PORT_FBS);	1920	fbs = readl(port_mmio + PORT_FBS);
1921	if (fbs & PORT_FBS_EN) {	1921	if (fbs & PORT_FBS_EN) {
1922	dev_printk(KERN_INFO, ap->host->dev, "FBS is enabled.\n");	1922	dev_printk(KERN_INFO, ap->host->dev, "FBS is enabled.\n");
1923	pp->fbs_enabled = true;	1923	pp->fbs_enabled = true;
1924	pp->fbs_last_dev = -1; /* initialization */	1924	pp->fbs_last_dev = -1; /* initialization */
1925	} else	1925	} else
1926	dev_printk(KERN_ERR, ap->host->dev, "Failed to enable FBS\n");	1926	dev_printk(KERN_ERR, ap->host->dev, "Failed to enable FBS\n");
1927		1927
1928	ahci_start_engine(ap);	1928	ahci_start_engine(ap);
1929	}	1929	}
1930		1930
1931	static void ahci_disable_fbs(struct ata_port *ap)	1931	static void ahci_disable_fbs(struct ata_port *ap)
1932	{	1932	{
1933	struct ahci_port_priv *pp = ap->private_data;	1933	struct ahci_port_priv *pp = ap->private_data;
1934	void __iomem *port_mmio = ahci_port_base(ap);	1934	void __iomem *port_mmio = ahci_port_base(ap);
1935	u32 fbs;	1935	u32 fbs;
1936	int rc;	1936	int rc;
1937		1937
1938	if (!pp->fbs_supported)	1938	if (!pp->fbs_supported)
1939	return;	1939	return;
1940		1940
1941	fbs = readl(port_mmio + PORT_FBS);	1941	fbs = readl(port_mmio + PORT_FBS);
1942	if ((fbs & PORT_FBS_EN) == 0) {	1942	if ((fbs & PORT_FBS_EN) == 0) {
1943	pp->fbs_enabled = false;	1943	pp->fbs_enabled = false;
1944	return;	1944	return;
1945	}	1945	}
1946		1946
1947	rc = ahci_stop_engine(ap);	1947	rc = ahci_stop_engine(ap);
1948	if (rc)	1948	if (rc)
1949	return;	1949	return;
1950		1950
1951	writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS);	1951	writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS);
1952	fbs = readl(port_mmio + PORT_FBS);	1952	fbs = readl(port_mmio + PORT_FBS);
1953	if (fbs & PORT_FBS_EN)	1953	if (fbs & PORT_FBS_EN)
1954	dev_printk(KERN_ERR, ap->host->dev, "Failed to disable FBS\n");	1954	dev_printk(KERN_ERR, ap->host->dev, "Failed to disable FBS\n");
1955	else {	1955	else {
1956	dev_printk(KERN_INFO, ap->host->dev, "FBS is disabled.\n");	1956	dev_printk(KERN_INFO, ap->host->dev, "FBS is disabled.\n");
1957	pp->fbs_enabled = false;	1957	pp->fbs_enabled = false;
1958	}	1958	}
1959		1959
1960	ahci_start_engine(ap);	1960	ahci_start_engine(ap);
1961	}	1961	}
1962		1962
1963	static void ahci_pmp_attach(struct ata_port *ap)	1963	static void ahci_pmp_attach(struct ata_port *ap)
1964	{	1964	{
1965	void __iomem *port_mmio = ahci_port_base(ap);	1965	void __iomem *port_mmio = ahci_port_base(ap);
1966	struct ahci_port_priv *pp = ap->private_data;	1966	struct ahci_port_priv *pp = ap->private_data;
1967	u32 cmd;	1967	u32 cmd;
1968		1968
1969	cmd = readl(port_mmio + PORT_CMD);	1969	cmd = readl(port_mmio + PORT_CMD);
1970	cmd \|= PORT_CMD_PMP;	1970	cmd \|= PORT_CMD_PMP;
1971	writel(cmd, port_mmio + PORT_CMD);	1971	writel(cmd, port_mmio + PORT_CMD);
1972		1972
1973	ahci_enable_fbs(ap);	1973	ahci_enable_fbs(ap);
1974		1974
1975	pp->intr_mask \|= PORT_IRQ_BAD_PMP;	1975	pp->intr_mask \|= PORT_IRQ_BAD_PMP;
1976	writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);	1976	writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1977	}	1977	}
1978		1978
1979	static void ahci_pmp_detach(struct ata_port *ap)	1979	static void ahci_pmp_detach(struct ata_port *ap)
1980	{	1980	{
1981	void __iomem *port_mmio = ahci_port_base(ap);	1981	void __iomem *port_mmio = ahci_port_base(ap);
1982	struct ahci_port_priv *pp = ap->private_data;	1982	struct ahci_port_priv *pp = ap->private_data;
1983	u32 cmd;	1983	u32 cmd;
1984		1984
1985	ahci_disable_fbs(ap);	1985	ahci_disable_fbs(ap);
1986		1986
1987	cmd = readl(port_mmio + PORT_CMD);	1987	cmd = readl(port_mmio + PORT_CMD);
1988	cmd &= ~PORT_CMD_PMP;	1988	cmd &= ~PORT_CMD_PMP;
1989	writel(cmd, port_mmio + PORT_CMD);	1989	writel(cmd, port_mmio + PORT_CMD);
1990		1990
1991	pp->intr_mask &= ~PORT_IRQ_BAD_PMP;	1991	pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
1992	writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);	1992	writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1993	}	1993	}
1994		1994
1995	static int ahci_port_resume(struct ata_port *ap)	1995	static int ahci_port_resume(struct ata_port *ap)
1996	{	1996	{
1997	ahci_power_up(ap);	1997	ahci_power_up(ap);
1998	ahci_start_port(ap);	1998	ahci_start_port(ap);
1999		1999
2000	if (sata_pmp_attached(ap))	2000	if (sata_pmp_attached(ap))
2001	ahci_pmp_attach(ap);	2001	ahci_pmp_attach(ap);
2002	else	2002	else
2003	ahci_pmp_detach(ap);	2003	ahci_pmp_detach(ap);
2004		2004
2005	return 0;	2005	return 0;
2006	}	2006	}
2007		2007
2008	#ifdef CONFIG_PM	2008	#ifdef CONFIG_PM
2009	static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)	2009	static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
2010	{	2010	{
2011	const char *emsg = NULL;	2011	const char *emsg = NULL;
2012	int rc;	2012	int rc;
2013		2013
2014	rc = ahci_deinit_port(ap, &emsg);	2014	rc = ahci_deinit_port(ap, &emsg);
2015	if (rc == 0)	2015	if (rc == 0)
2016	ahci_power_down(ap);	2016	ahci_power_down(ap);
2017	else {	2017	else {
2018	ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);	2018	ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
2019	ahci_start_port(ap);	2019	ahci_start_port(ap);
2020	}	2020	}
2021		2021
2022	return rc;	2022	return rc;
2023	}	2023	}
2024	#endif	2024	#endif
2025		2025
2026	static int ahci_port_start(struct ata_port *ap)	2026	static int ahci_port_start(struct ata_port *ap)
2027	{	2027	{
2028	struct ahci_host_priv *hpriv = ap->host->private_data;	2028	struct ahci_host_priv *hpriv = ap->host->private_data;
2029	struct device *dev = ap->host->dev;	2029	struct device *dev = ap->host->dev;
2030	struct ahci_port_priv *pp;	2030	struct ahci_port_priv *pp;
2031	void *mem;	2031	void *mem;
2032	dma_addr_t mem_dma;	2032	dma_addr_t mem_dma;
2033	size_t dma_sz, rx_fis_sz;	2033	size_t dma_sz, rx_fis_sz;
2034		2034
2035	pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);	2035	pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
2036	if (!pp)	2036	if (!pp)
2037	return -ENOMEM;	2037	return -ENOMEM;
2038		2038
2039	/* check FBS capability */	2039	/* check FBS capability */
2040	if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {	2040	if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
2041	void __iomem *port_mmio = ahci_port_base(ap);	2041	void __iomem *port_mmio = ahci_port_base(ap);
2042	u32 cmd = readl(port_mmio + PORT_CMD);	2042	u32 cmd = readl(port_mmio + PORT_CMD);
2043	if (cmd & PORT_CMD_FBSCP)	2043	if (cmd & PORT_CMD_FBSCP)
2044	pp->fbs_supported = true;	2044	pp->fbs_supported = true;
2045	else if (hpriv->flags & AHCI_HFLAG_YES_FBS) {	2045	else if (hpriv->flags & AHCI_HFLAG_YES_FBS) {
2046	dev_printk(KERN_INFO, dev,	2046	dev_printk(KERN_INFO, dev,
2047	"port %d can do FBS, forcing FBSCP\n",	2047	"port %d can do FBS, forcing FBSCP\n",
2048	ap->port_no);	2048	ap->port_no);
2049	pp->fbs_supported = true;	2049	pp->fbs_supported = true;
2050	} else	2050	} else
2051	dev_printk(KERN_WARNING, dev,	2051	dev_printk(KERN_WARNING, dev,
2052	"port %d is not capable of FBS\n",	2052	"port %d is not capable of FBS\n",
2053	ap->port_no);	2053	ap->port_no);
2054	}	2054	}
2055		2055
2056	if (pp->fbs_supported) {	2056	if (pp->fbs_supported) {
2057	dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;	2057	dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
2058	rx_fis_sz = AHCI_RX_FIS_SZ * 16;	2058	rx_fis_sz = AHCI_RX_FIS_SZ * 16;
2059	} else {	2059	} else {
2060	dma_sz = AHCI_PORT_PRIV_DMA_SZ;	2060	dma_sz = AHCI_PORT_PRIV_DMA_SZ;
2061	rx_fis_sz = AHCI_RX_FIS_SZ;	2061	rx_fis_sz = AHCI_RX_FIS_SZ;
2062	}	2062	}
2063		2063
2064	mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);	2064	mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
2065	if (!mem)	2065	if (!mem)
2066	return -ENOMEM;	2066	return -ENOMEM;
2067	memset(mem, 0, dma_sz);	2067	memset(mem, 0, dma_sz);
2068		2068
2069	/*	2069	/*
2070	* First item in chunk of DMA memory: 32-slot command table,	2070	* First item in chunk of DMA memory: 32-slot command table,
2071	* 32 bytes each in size	2071	* 32 bytes each in size
2072	*/	2072	*/
2073	pp->cmd_slot = mem;	2073	pp->cmd_slot = mem;
2074	pp->cmd_slot_dma = mem_dma;	2074	pp->cmd_slot_dma = mem_dma;
2075		2075
2076	mem += AHCI_CMD_SLOT_SZ;	2076	mem += AHCI_CMD_SLOT_SZ;
2077	mem_dma += AHCI_CMD_SLOT_SZ;	2077	mem_dma += AHCI_CMD_SLOT_SZ;
2078		2078
2079	/*	2079	/*
2080	* Second item: Received-FIS area	2080	* Second item: Received-FIS area
2081	*/	2081	*/
2082	pp->rx_fis = mem;	2082	pp->rx_fis = mem;
2083	pp->rx_fis_dma = mem_dma;	2083	pp->rx_fis_dma = mem_dma;
2084		2084
2085	mem += rx_fis_sz;	2085	mem += rx_fis_sz;
2086	mem_dma += rx_fis_sz;	2086	mem_dma += rx_fis_sz;
2087		2087
2088	/*	2088	/*
2089	* Third item: data area for storing a single command	2089	* Third item: data area for storing a single command
2090	* and its scatter-gather table	2090	* and its scatter-gather table
2091	*/	2091	*/
2092	pp->cmd_tbl = mem;	2092	pp->cmd_tbl = mem;
2093	pp->cmd_tbl_dma = mem_dma;	2093	pp->cmd_tbl_dma = mem_dma;
2094		2094
2095	/*	2095	/*
2096	* Save off initial list of interrupts to be enabled.	2096	* Save off initial list of interrupts to be enabled.
2097	* This could be changed later	2097	* This could be changed later
2098	*/	2098	*/
2099	pp->intr_mask = DEF_PORT_IRQ;	2099	pp->intr_mask = DEF_PORT_IRQ;
2100		2100
2101	ap->private_data = pp;	2101	ap->private_data = pp;
2102		2102
2103	/* engage engines, captain */	2103	/* engage engines, captain */
2104	return ahci_port_resume(ap);	2104	return ahci_port_resume(ap);
2105	}	2105	}
2106		2106
2107	static void ahci_port_stop(struct ata_port *ap)	2107	static void ahci_port_stop(struct ata_port *ap)
2108	{	2108	{
2109	const char *emsg = NULL;	2109	const char *emsg = NULL;
2110	int rc;	2110	int rc;
2111		2111
2112	/* de-initialize port */	2112	/* de-initialize port */
2113	rc = ahci_deinit_port(ap, &emsg);	2113	rc = ahci_deinit_port(ap, &emsg);
2114	if (rc)	2114	if (rc)
2115	ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);	2115	ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
2116	}	2116	}
2117		2117
2118	void ahci_print_info(struct ata_host host, const char scc_s)	2118	void ahci_print_info(struct ata_host host, const char scc_s)
2119	{	2119	{
2120	struct ahci_host_priv *hpriv = host->private_data;	2120	struct ahci_host_priv *hpriv = host->private_data;
2121	void __iomem *mmio = hpriv->mmio;	2121	void __iomem *mmio = hpriv->mmio;
2122	u32 vers, cap, cap2, impl, speed;	2122	u32 vers, cap, cap2, impl, speed;
2123	const char *speed_s;	2123	const char *speed_s;
2124		2124
2125	vers = readl(mmio + HOST_VERSION);	2125	vers = readl(mmio + HOST_VERSION);
2126	cap = hpriv->cap;	2126	cap = hpriv->cap;
2127	cap2 = hpriv->cap2;	2127	cap2 = hpriv->cap2;
2128	impl = hpriv->port_map;	2128	impl = hpriv->port_map;
2129		2129
2130	speed = (cap >> 20) & 0xf;	2130	speed = (cap >> 20) & 0xf;
2131	if (speed == 1)	2131	if (speed == 1)
2132	speed_s = "1.5";	2132	speed_s = "1.5";
2133	else if (speed == 2)	2133	else if (speed == 2)
2134	speed_s = "3";	2134	speed_s = "3";
2135	else if (speed == 3)	2135	else if (speed == 3)
2136	speed_s = "6";	2136	speed_s = "6";
2137	else	2137	else
2138	speed_s = "?";	2138	speed_s = "?";
2139		2139
2140	dev_info(host->dev,	2140	dev_info(host->dev,
2141	"AHCI %02x%02x.%02x%02x "	2141	"AHCI %02x%02x.%02x%02x "
2142	"%u slots %u ports %s Gbps 0x%x impl %s mode\n"	2142	"%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2143	,	2143	,
2144		2144
2145	(vers >> 24) & 0xff,	2145	(vers >> 24) & 0xff,
2146	(vers >> 16) & 0xff,	2146	(vers >> 16) & 0xff,
2147	(vers >> 8) & 0xff,	2147	(vers >> 8) & 0xff,
2148	vers & 0xff,	2148	vers & 0xff,
2149		2149
2150	((cap >> 8) & 0x1f) + 1,	2150	((cap >> 8) & 0x1f) + 1,
2151	(cap & 0x1f) + 1,	2151	(cap & 0x1f) + 1,
2152	speed_s,	2152	speed_s,
2153	impl,	2153	impl,
2154	scc_s);	2154	scc_s);
2155		2155
2156	dev_info(host->dev,	2156	dev_info(host->dev,
2157	"flags: "	2157	"flags: "
2158	"%s%s%s%s%s%s%s"	2158	"%s%s%s%s%s%s%s"
2159	"%s%s%s%s%s%s%s"	2159	"%s%s%s%s%s%s%s"
2160	"%s%s%s%s%s%s\n"	2160	"%s%s%s%s%s%s\n"
2161	,	2161	,
2162		2162
2163	cap & HOST_CAP_64 ? "64bit " : "",	2163	cap & HOST_CAP_64 ? "64bit " : "",
2164	cap & HOST_CAP_NCQ ? "ncq " : "",	2164	cap & HOST_CAP_NCQ ? "ncq " : "",
2165	cap & HOST_CAP_SNTF ? "sntf " : "",	2165	cap & HOST_CAP_SNTF ? "sntf " : "",
2166	cap & HOST_CAP_MPS ? "ilck " : "",	2166	cap & HOST_CAP_MPS ? "ilck " : "",
2167	cap & HOST_CAP_SSS ? "stag " : "",	2167	cap & HOST_CAP_SSS ? "stag " : "",
2168	cap & HOST_CAP_ALPM ? "pm " : "",	2168	cap & HOST_CAP_ALPM ? "pm " : "",
2169	cap & HOST_CAP_LED ? "led " : "",	2169	cap & HOST_CAP_LED ? "led " : "",
2170	cap & HOST_CAP_CLO ? "clo " : "",	2170	cap & HOST_CAP_CLO ? "clo " : "",
2171	cap & HOST_CAP_ONLY ? "only " : "",	2171	cap & HOST_CAP_ONLY ? "only " : "",
2172	cap & HOST_CAP_PMP ? "pmp " : "",	2172	cap & HOST_CAP_PMP ? "pmp " : "",
2173	cap & HOST_CAP_FBS ? "fbs " : "",	2173	cap & HOST_CAP_FBS ? "fbs " : "",
2174	cap & HOST_CAP_PIO_MULTI ? "pio " : "",	2174	cap & HOST_CAP_PIO_MULTI ? "pio " : "",
2175	cap & HOST_CAP_SSC ? "slum " : "",	2175	cap & HOST_CAP_SSC ? "slum " : "",
2176	cap & HOST_CAP_PART ? "part " : "",	2176	cap & HOST_CAP_PART ? "part " : "",
2177	cap & HOST_CAP_CCC ? "ccc " : "",	2177	cap & HOST_CAP_CCC ? "ccc " : "",
2178	cap & HOST_CAP_EMS ? "ems " : "",	2178	cap & HOST_CAP_EMS ? "ems " : "",
2179	cap & HOST_CAP_SXS ? "sxs " : "",	2179	cap & HOST_CAP_SXS ? "sxs " : "",
2180	cap2 & HOST_CAP2_APST ? "apst " : "",	2180	cap2 & HOST_CAP2_APST ? "apst " : "",
2181	cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "",	2181	cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "",
2182	cap2 & HOST_CAP2_BOH ? "boh " : ""	2182	cap2 & HOST_CAP2_BOH ? "boh " : ""
2183	);	2183	);
2184	}	2184	}
2185	EXPORT_SYMBOL_GPL(ahci_print_info);	2185	EXPORT_SYMBOL_GPL(ahci_print_info);
2186		2186
2187	void ahci_set_em_messages(struct ahci_host_priv *hpriv,	2187	void ahci_set_em_messages(struct ahci_host_priv *hpriv,
2188	struct ata_port_info *pi)	2188	struct ata_port_info *pi)
2189	{	2189	{
2190	u8 messages;	2190	u8 messages;
2191	void __iomem *mmio = hpriv->mmio;	2191	void __iomem *mmio = hpriv->mmio;
2192	u32 em_loc = readl(mmio + HOST_EM_LOC);	2192	u32 em_loc = readl(mmio + HOST_EM_LOC);
2193	u32 em_ctl = readl(mmio + HOST_EM_CTL);	2193	u32 em_ctl = readl(mmio + HOST_EM_CTL);
2194		2194
2195	if (!ahci_em_messages \|\| !(hpriv->cap & HOST_CAP_EMS))	2195	if (!ahci_em_messages \|\| !(hpriv->cap & HOST_CAP_EMS))
2196	return;	2196	return;
2197		2197
2198	messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;	2198	messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
2199		2199
2200	if (messages) {	2200	if (messages) {
2201	/* store em_loc */	2201	/* store em_loc */
2202	hpriv->em_loc = ((em_loc >> 16) * 4);	2202	hpriv->em_loc = ((em_loc >> 16) * 4);
2203	hpriv->em_buf_sz = ((em_loc & 0xff) * 4);	2203	hpriv->em_buf_sz = ((em_loc & 0xff) * 4);
2204	hpriv->em_msg_type = messages;	2204	hpriv->em_msg_type = messages;
2205	pi->flags \|= ATA_FLAG_EM;	2205	pi->flags \|= ATA_FLAG_EM;
2206	if (!(em_ctl & EM_CTL_ALHD))	2206	if (!(em_ctl & EM_CTL_ALHD))
2207	pi->flags \|= ATA_FLAG_SW_ACTIVITY;	2207	pi->flags \|= ATA_FLAG_SW_ACTIVITY;
2208	}	2208	}
2209	}	2209	}
2210	EXPORT_SYMBOL_GPL(ahci_set_em_messages);	2210	EXPORT_SYMBOL_GPL(ahci_set_em_messages);
2211		2211
2212	MODULE_AUTHOR("Jeff Garzik");	2212	MODULE_AUTHOR("Jeff Garzik");
2213	MODULE_DESCRIPTION("Common AHCI SATA low-level routines");	2213	MODULE_DESCRIPTION("Common AHCI SATA low-level routines");
2214	MODULE_LICENSE("GPL");	2214	MODULE_LICENSE("GPL");
2215		2215

drivers/ata/libata-core.c

Diff comments View file @ df423dc

 /*
  *  libata-core.c - helper library for ATA
  *
  *  Maintained by:  Jeff Garzik <jgarzik@pobox.com>
  *    		    Please ALWAYS copy linux-ide@vger.kernel.org
  *		    on emails.
  *
  *  Copyright 2003-2004 Red Hat, Inc.  All rights reserved.
  *  Copyright 2003-2004 Jeff Garzik
  *
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
  *  the Free Software Foundation; either version 2, or (at your option)
  *  any later version.
  *
  *  This program is distributed in the hope that it will be useful,
  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  *  GNU General Public License for more details.
  *
  *  You should have received a copy of the GNU General Public License
  *  along with this program; see the file COPYING.  If not, write to
  *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  *
  *
  *  libata documentation is available via 'make {ps|pdf}docs',
  *  as Documentation/DocBook/libata.*
  *
  *  Hardware documentation available from http://www.t13.org/ and
  *  http://www.sata-io.org/
  *
  *  Standards documents from:
  *	http://www.t13.org (ATA standards, PCI DMA IDE spec)
  *	http://www.t10.org (SCSI MMC - for ATAPI MMC)
  *	http://www.sata-io.org (SATA)
  *	http://www.compactflash.org (CF)
  *	http://www.qic.org (QIC157 - Tape and DSC)
  *	http://www.ce-ata.org (CE-ATA: not supported)
  *
  */
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/pci.h>
 #include <linux/init.h>
 #include <linux/list.h>
 #include <linux/mm.h>
 #include <linux/spinlock.h>
 #include <linux/blkdev.h>
 #include <linux/delay.h>
 #include <linux/timer.h>
 #include <linux/interrupt.h>
 #include <linux/completion.h>
 #include <linux/suspend.h>
 #include <linux/workqueue.h>
 #include <linux/scatterlist.h>
 #include <linux/io.h>
 #include <linux/async.h>
 #include <linux/log2.h>
 #include <linux/slab.h>
 #include <scsi/scsi.h>
 #include <scsi/scsi_cmnd.h>
 #include <scsi/scsi_host.h>
 #include <linux/libata.h>
 #include <asm/byteorder.h>
 #include <linux/cdrom.h>
 #include <linux/ratelimit.h>
 #include "libata.h"
 /* debounce timing parameters in msecs { interval, duration, timeout } */
 const unsigned long sata_deb_timing_normal[]		= {   5,  100, 2000 };
 const unsigned long sata_deb_timing_hotplug[]		= {  25,  500, 2000 };
 const unsigned long sata_deb_timing_long[]		= { 100, 2000, 5000 };
 const struct ata_port_operations ata_base_port_ops = {
 	.prereset		= ata_std_prereset,
 	.postreset		= ata_std_postreset,
 	.error_handler		= ata_std_error_handler,
 };
 const struct ata_port_operations sata_port_ops = {
 	.inherits		= &ata_base_port_ops,
 	.qc_defer		= ata_std_qc_defer,
 	.hardreset		= sata_std_hardreset,
 };
 static unsigned int ata_dev_init_params(struct ata_device *dev,
 					u16 heads, u16 sectors);
 static unsigned int ata_dev_set_xfermode(struct ata_device *dev);
 static unsigned int ata_dev_set_feature(struct ata_device *dev,
 					u8 enable, u8 feature);
 static void ata_dev_xfermask(struct ata_device *dev);
 static unsigned long ata_dev_blacklisted(const struct ata_device *dev);
 unsigned int ata_print_id = 1;
 struct ata_force_param {
 	const char	*name;
 	unsigned int	cbl;
 	int		spd_limit;
 	unsigned long	xfer_mask;
 	unsigned int	horkage_on;
 	unsigned int	horkage_off;
 	unsigned int	lflags;
 };
 struct ata_force_ent {
 	int			port;
 	int			device;
 	struct ata_force_param	param;
 };
 static struct ata_force_ent *ata_force_tbl;
 static int ata_force_tbl_size;
 static char ata_force_param_buf[PAGE_SIZE] __initdata;
 /* param_buf is thrown away after initialization, disallow read */
 module_param_string(force, ata_force_param_buf, sizeof(ata_force_param_buf), 0);
 MODULE_PARM_DESC(force, "Force ATA configurations including cable type, link speed and transfer mode (see Documentation/kernel-parameters.txt for details)");
 static int atapi_enabled = 1;
 module_param(atapi_enabled, int, 0444);
 MODULE_PARM_DESC(atapi_enabled, "Enable discovery of ATAPI devices (0=off, 1=on [default])");
 static int atapi_dmadir = 0;
 module_param(atapi_dmadir, int, 0444);
 MODULE_PARM_DESC(atapi_dmadir, "Enable ATAPI DMADIR bridge support (0=off [default], 1=on)");
 int atapi_passthru16 = 1;
 module_param(atapi_passthru16, int, 0444);
 MODULE_PARM_DESC(atapi_passthru16, "Enable ATA_16 passthru for ATAPI devices (0=off, 1=on [default])");
 int libata_fua = 0;
 module_param_named(fua, libata_fua, int, 0444);
 MODULE_PARM_DESC(fua, "FUA support (0=off [default], 1=on)");
 static int ata_ignore_hpa;
 module_param_named(ignore_hpa, ata_ignore_hpa, int, 0644);
 MODULE_PARM_DESC(ignore_hpa, "Ignore HPA limit (0=keep BIOS limits, 1=ignore limits, using full disk)");
 static int libata_dma_mask = ATA_DMA_MASK_ATA|ATA_DMA_MASK_ATAPI|ATA_DMA_MASK_CFA;
 module_param_named(dma, libata_dma_mask, int, 0444);
 MODULE_PARM_DESC(dma, "DMA enable/disable (0x1==ATA, 0x2==ATAPI, 0x4==CF)");
 static int ata_probe_timeout;
 module_param(ata_probe_timeout, int, 0444);
 MODULE_PARM_DESC(ata_probe_timeout, "Set ATA probing timeout (seconds)");
 int libata_noacpi = 0;
 module_param_named(noacpi, libata_noacpi, int, 0444);
 MODULE_PARM_DESC(noacpi, "Disable the use of ACPI in probe/suspend/resume (0=off [default], 1=on)");
 int libata_allow_tpm = 0;
 module_param_named(allow_tpm, libata_allow_tpm, int, 0444);
 MODULE_PARM_DESC(allow_tpm, "Permit the use of TPM commands (0=off [default], 1=on)");
 static int atapi_an;
 module_param(atapi_an, int, 0444);
 MODULE_PARM_DESC(atapi_an, "Enable ATAPI AN media presence notification (0=0ff [default], 1=on)");
 MODULE_AUTHOR("Jeff Garzik");
 MODULE_DESCRIPTION("Library module for ATA devices");
 MODULE_LICENSE("GPL");
 MODULE_VERSION(DRV_VERSION);
 static bool ata_sstatus_online(u32 sstatus)
 {
 	return (sstatus & 0xf) == 0x3;
 }
 /**
  *	ata_link_next - link iteration helper
  *	@link: the previous link, NULL to start
  *	@ap: ATA port containing links to iterate
  *	@mode: iteration mode, one of ATA_LITER_*
  *
  *	LOCKING:
  *	Host lock or EH context.
  *
  *	RETURNS:
  *	Pointer to the next link.
  */
 struct ata_link *ata_link_next(struct ata_link *link, struct ata_port *ap,
 			       enum ata_link_iter_mode mode)
 {
 	BUG_ON(mode != ATA_LITER_EDGE &&
 	       mode != ATA_LITER_PMP_FIRST && mode != ATA_LITER_HOST_FIRST);
 	/* NULL link indicates start of iteration */
 	if (!link)
 		switch (mode) {
 		case ATA_LITER_EDGE:
 		case ATA_LITER_PMP_FIRST:
 			if (sata_pmp_attached(ap))
 				return ap->pmp_link;
 			/* fall through */
 		case ATA_LITER_HOST_FIRST:
 			return &ap->link;
 		}
 	/* we just iterated over the host link, what's next? */
 	if (link == &ap->link)
 		switch (mode) {
 		case ATA_LITER_HOST_FIRST:
 			if (sata_pmp_attached(ap))
 				return ap->pmp_link;
 			/* fall through */
 		case ATA_LITER_PMP_FIRST:
 			if (unlikely(ap->slave_link))
 				return ap->slave_link;
 			/* fall through */
 		case ATA_LITER_EDGE:
 			return NULL;
 		}
 	/* slave_link excludes PMP */
 	if (unlikely(link == ap->slave_link))
 		return NULL;
 	/* we were over a PMP link */
 	if (++link < ap->pmp_link + ap->nr_pmp_links)
 		return link;
 	if (mode == ATA_LITER_PMP_FIRST)
 		return &ap->link;
 	return NULL;
 }
 /**
  *	ata_dev_next - device iteration helper
  *	@dev: the previous device, NULL to start
  *	@link: ATA link containing devices to iterate
  *	@mode: iteration mode, one of ATA_DITER_*
  *
  *	LOCKING:
  *	Host lock or EH context.
  *
  *	RETURNS:
  *	Pointer to the next device.
  */
 struct ata_device *ata_dev_next(struct ata_device *dev, struct ata_link *link,
 				enum ata_dev_iter_mode mode)
 {
 	BUG_ON(mode != ATA_DITER_ENABLED && mode != ATA_DITER_ENABLED_REVERSE &&
 	       mode != ATA_DITER_ALL && mode != ATA_DITER_ALL_REVERSE);
 	/* NULL dev indicates start of iteration */
 	if (!dev)
 		switch (mode) {
 		case ATA_DITER_ENABLED:
 		case ATA_DITER_ALL:
 			dev = link->device;
 			goto check;
 		case ATA_DITER_ENABLED_REVERSE:
 		case ATA_DITER_ALL_REVERSE:
 			dev = link->device + ata_link_max_devices(link) - 1;
 			goto check;
 		}
  next:
 	/* move to the next one */
 	switch (mode) {
 	case ATA_DITER_ENABLED:
 	case ATA_DITER_ALL:
 		if (++dev < link->device + ata_link_max_devices(link))
 			goto check;
 		return NULL;
 	case ATA_DITER_ENABLED_REVERSE:
 	case ATA_DITER_ALL_REVERSE:
 		if (--dev >= link->device)
 			goto check;
 		return NULL;
 	}
  check:
 	if ((mode == ATA_DITER_ENABLED || mode == ATA_DITER_ENABLED_REVERSE) &&
 	    !ata_dev_enabled(dev))
 		goto next;
 	return dev;
 }
 /**
  *	ata_dev_phys_link - find physical link for a device
  *	@dev: ATA device to look up physical link for
  *
  *	Look up physical link which @dev is attached to.  Note that
  *	this is different from @dev->link only when @dev is on slave
  *	link.  For all other cases, it's the same as @dev->link.
  *
  *	LOCKING:
  *	Don't care.
  *
  *	RETURNS:
  *	Pointer to the found physical link.
  */
 struct ata_link *ata_dev_phys_link(struct ata_device *dev)
 {
 	struct ata_port *ap = dev->link->ap;
 	if (!ap->slave_link)
 		return dev->link;
 	if (!dev->devno)
 		return &ap->link;
 	return ap->slave_link;
 }
 /**
  *	ata_force_cbl - force cable type according to libata.force
  *	@ap: ATA port of interest
  *
  *	Force cable type according to libata.force and whine about it.
  *	The last entry which has matching port number is used, so it
  *	can be specified as part of device force parameters.  For
  *	example, both "a:40c,1.00:udma4" and "1.00:40c,udma4" have the
  *	same effect.
  *
  *	LOCKING:
  *	EH context.
  */
 void ata_force_cbl(struct ata_port *ap)
 {
 	int i;
 	for (i = ata_force_tbl_size - 1; i >= 0; i--) {
 		const struct ata_force_ent *fe = &ata_force_tbl[i];
 		if (fe->port != -1 && fe->port != ap->print_id)
 			continue;
 		if (fe->param.cbl == ATA_CBL_NONE)
 			continue;
 		ap->cbl = fe->param.cbl;
 		ata_port_printk(ap, KERN_NOTICE,
 				"FORCE: cable set to %s\n", fe->param.name);
 		return;
 	}
 }
 /**
  *	ata_force_link_limits - force link limits according to libata.force
  *	@link: ATA link of interest
  *
  *	Force link flags and SATA spd limit according to libata.force
  *	and whine about it.  When only the port part is specified
  *	(e.g. 1:), the limit applies to all links connected to both
  *	the host link and all fan-out ports connected via PMP.  If the
  *	device part is specified as 0 (e.g. 1.00:), it specifies the
  *	first fan-out link not the host link.  Device number 15 always
  *	points to the host link whether PMP is attached or not.  If the
  *	controller has slave link, device number 16 points to it.
  *
  *	LOCKING:
  *	EH context.
  */
 static void ata_force_link_limits(struct ata_link *link)
 {
 	bool did_spd = false;
 	int linkno = link->pmp;
 	int i;
 	if (ata_is_host_link(link))
 		linkno += 15;
 	for (i = ata_force_tbl_size - 1; i >= 0; i--) {
 		const struct ata_force_ent *fe = &ata_force_tbl[i];
 		if (fe->port != -1 && fe->port != link->ap->print_id)
 			continue;
 		if (fe->device != -1 && fe->device != linkno)
 			continue;
 		/* only honor the first spd limit */
 		if (!did_spd && fe->param.spd_limit) {
 			link->hw_sata_spd_limit = (1 << fe->param.spd_limit) - 1;
 			ata_link_printk(link, KERN_NOTICE,
 					"FORCE: PHY spd limit set to %s\n",
 					fe->param.name);
 			did_spd = true;
 		}
 		/* let lflags stack */
 		if (fe->param.lflags) {
 			link->flags |= fe->param.lflags;
 			ata_link_printk(link, KERN_NOTICE,
 					"FORCE: link flag 0x%x forced -> 0x%x\n",
 					fe->param.lflags, link->flags);
 		}
 	}
 }
 /**
  *	ata_force_xfermask - force xfermask according to libata.force
  *	@dev: ATA device of interest
  *
  *	Force xfer_mask according to libata.force and whine about it.
  *	For consistency with link selection, device number 15 selects
  *	the first device connected to the host link.
  *
  *	LOCKING:
  *	EH context.
  */
 static void ata_force_xfermask(struct ata_device *dev)
 {
 	int devno = dev->link->pmp + dev->devno;
 	int alt_devno = devno;
 	int i;
 	/* allow n.15/16 for devices attached to host port */
 	if (ata_is_host_link(dev->link))
 		alt_devno += 15;
 	for (i = ata_force_tbl_size - 1; i >= 0; i--) {
 		const struct ata_force_ent *fe = &ata_force_tbl[i];
 		unsigned long pio_mask, mwdma_mask, udma_mask;
 		if (fe->port != -1 && fe->port != dev->link->ap->print_id)
 			continue;
 		if (fe->device != -1 && fe->device != devno &&
 		    fe->device != alt_devno)
 			continue;
 		if (!fe->param.xfer_mask)
 			continue;
 		ata_unpack_xfermask(fe->param.xfer_mask,
 				    &pio_mask, &mwdma_mask, &udma_mask);
 		if (udma_mask)
 			dev->udma_mask = udma_mask;
 		else if (mwdma_mask) {
 			dev->udma_mask = 0;
 			dev->mwdma_mask = mwdma_mask;
 		} else {
 			dev->udma_mask = 0;
 			dev->mwdma_mask = 0;
 			dev->pio_mask = pio_mask;
 		}
 		ata_dev_printk(dev, KERN_NOTICE,
 			"FORCE: xfer_mask set to %s\n", fe->param.name);
 		return;
 	}
 }
 /**
  *	ata_force_horkage - force horkage according to libata.force
  *	@dev: ATA device of interest
  *
  *	Force horkage according to libata.force and whine about it.
  *	For consistency with link selection, device number 15 selects
  *	the first device connected to the host link.
  *
  *	LOCKING:
  *	EH context.
  */
 static void ata_force_horkage(struct ata_device *dev)
 {
 	int devno = dev->link->pmp + dev->devno;
 	int alt_devno = devno;
 	int i;
 	/* allow n.15/16 for devices attached to host port */
 	if (ata_is_host_link(dev->link))
 		alt_devno += 15;
 	for (i = 0; i < ata_force_tbl_size; i++) {
 		const struct ata_force_ent *fe = &ata_force_tbl[i];
 		if (fe->port != -1 && fe->port != dev->link->ap->print_id)
 			continue;
 		if (fe->device != -1 && fe->device != devno &&
 		    fe->device != alt_devno)
 			continue;
 		if (!(~dev->horkage & fe->param.horkage_on) &&
 		    !(dev->horkage & fe->param.horkage_off))
 			continue;
 		dev->horkage |= fe->param.horkage_on;
 		dev->horkage &= ~fe->param.horkage_off;
 		ata_dev_printk(dev, KERN_NOTICE,
 			"FORCE: horkage modified (%s)\n", fe->param.name);
 	}
 }
 /**
  *	atapi_cmd_type - Determine ATAPI command type from SCSI opcode
  *	@opcode: SCSI opcode
  *
  *	Determine ATAPI command type from @opcode.
  *
  *	LOCKING:
  *	None.
  *
  *	RETURNS:
  *	ATAPI_{READ|WRITE|READ_CD|PASS_THRU|MISC}
  */
 int atapi_cmd_type(u8 opcode)
 {
 	switch (opcode) {
 	case GPCMD_READ_10:
 	case GPCMD_READ_12:
 		return ATAPI_READ;
 	case GPCMD_WRITE_10:
 	case GPCMD_WRITE_12:
 	case GPCMD_WRITE_AND_VERIFY_10:
 		return ATAPI_WRITE;
 	case GPCMD_READ_CD:
 	case GPCMD_READ_CD_MSF:
 		return ATAPI_READ_CD;
 	case ATA_16:
 	case ATA_12:
 		if (atapi_passthru16)
 			return ATAPI_PASS_THRU;
 		/* fall thru */
 	default:
 		return ATAPI_MISC;
 	}
 }
 /**
  *	ata_tf_to_fis - Convert ATA taskfile to SATA FIS structure
  *	@tf: Taskfile to convert
  *	@pmp: Port multiplier port
  *	@is_cmd: This FIS is for command
  *	@fis: Buffer into which data will output
  *
  *	Converts a standard ATA taskfile to a Serial ATA
  *	FIS structure (Register - Host to Device).
  *
  *	LOCKING:
  *	Inherited from caller.
  */
 void ata_tf_to_fis(const struct ata_taskfile *tf, u8 pmp, int is_cmd, u8 *fis)
 {
 	fis[0] = 0x27;			/* Register - Host to Device FIS */
 	fis[1] = pmp & 0xf;		/* Port multiplier number*/
 	if (is_cmd)
 		fis[1] |= (1 << 7);	/* bit 7 indicates Command FIS */
 	fis[2] = tf->command;
 	fis[3] = tf->feature;
 	fis[4] = tf->lbal;
 	fis[5] = tf->lbam;
 	fis[6] = tf->lbah;
 	fis[7] = tf->device;
 	fis[8] = tf->hob_lbal;
 	fis[9] = tf->hob_lbam;
 	fis[10] = tf->hob_lbah;
 	fis[11] = tf->hob_feature;
 	fis[12] = tf->nsect;
 	fis[13] = tf->hob_nsect;
 	fis[14] = 0;
 	fis[15] = tf->ctl;
 	fis[16] = 0;
 	fis[17] = 0;
 	fis[18] = 0;
 	fis[19] = 0;
 }
 /**
  *	ata_tf_from_fis - Convert SATA FIS to ATA taskfile
  *	@fis: Buffer from which data will be input
  *	@tf: Taskfile to output
  *
  *	Converts a serial ATA FIS structure to a standard ATA taskfile.
  *
  *	LOCKING:
  *	Inherited from caller.
  */
 void ata_tf_from_fis(const u8 *fis, struct ata_taskfile *tf)
 {
 	tf->command	= fis[2];	/* status */
 	tf->feature	= fis[3];	/* error */
 	tf->lbal	= fis[4];
 	tf->lbam	= fis[5];
 	tf->lbah	= fis[6];
 	tf->device	= fis[7];
 	tf->hob_lbal	= fis[8];
 	tf->hob_lbam	= fis[9];
 	tf->hob_lbah	= fis[10];
 	tf->nsect	= fis[12];
 	tf->hob_nsect	= fis[13];
 }
 static const u8 ata_rw_cmds[] = {
 	/* pio multi */
 	ATA_CMD_READ_MULTI,
 	ATA_CMD_WRITE_MULTI,
 	ATA_CMD_READ_MULTI_EXT,
 	ATA_CMD_WRITE_MULTI_EXT,
 	0,
 	0,
 	0,
 	ATA_CMD_WRITE_MULTI_FUA_EXT,
 	/* pio */
 	ATA_CMD_PIO_READ,
 	ATA_CMD_PIO_WRITE,
 	ATA_CMD_PIO_READ_EXT,
 	ATA_CMD_PIO_WRITE_EXT,
 	0,
 	0,
 	0,
 	0,
 	/* dma */
 	ATA_CMD_READ,
 	ATA_CMD_WRITE,
 	ATA_CMD_READ_EXT,
 	ATA_CMD_WRITE_EXT,
 	0,
 	0,
 	0,
 	ATA_CMD_WRITE_FUA_EXT
 };
 /**
  *	ata_rwcmd_protocol - set taskfile r/w commands and protocol
  *	@tf: command to examine and configure
  *	@dev: device tf belongs to
  *
  *	Examine the device configuration and tf->flags to calculate
  *	the proper read/write commands and protocol to use.
  *
  *	LOCKING:
  *	caller.
  */
 static int ata_rwcmd_protocol(struct ata_taskfile *tf, struct ata_device *dev)
 {
 	u8 cmd;
 	int index, fua, lba48, write;
 	fua = (tf->flags & ATA_TFLAG_FUA) ? 4 : 0;
 	lba48 = (tf->flags & ATA_TFLAG_LBA48) ? 2 : 0;
 	write = (tf->flags & ATA_TFLAG_WRITE) ? 1 : 0;
 	if (dev->flags & ATA_DFLAG_PIO) {
 		tf->protocol = ATA_PROT_PIO;
 		index = dev->multi_count ? 0 : 8;
 	} else if (lba48 && (dev->link->ap->flags & ATA_FLAG_PIO_LBA48)) {
 		/* Unable to use DMA due to host limitation */
 		tf->protocol = ATA_PROT_PIO;
 		index = dev->multi_count ? 0 : 8;
 	} else {
 		tf->protocol = ATA_PROT_DMA;
 		index = 16;
 	}
 	cmd = ata_rw_cmds[index + fua + lba48 + write];
 	if (cmd) {
 		tf->command = cmd;
 		return 0;
 	}
 	return -1;
 }
 /**
  *	ata_tf_read_block - Read block address from ATA taskfile
  *	@tf: ATA taskfile of interest
  *	@dev: ATA device @tf belongs to
  *
  *	LOCKING:
  *	None.
  *
  *	Read block address from @tf.  This function can handle all
  *	three address formats - LBA, LBA48 and CHS.  tf->protocol and
  *	flags select the address format to use.
  *
  *	RETURNS:
  *	Block address read from @tf.
  */
 u64 ata_tf_read_block(struct ata_taskfile *tf, struct ata_device *dev)
 {
 	u64 block = 0;
 	if (tf->flags & ATA_TFLAG_LBA) {
 		if (tf->flags & ATA_TFLAG_LBA48) {
 			block |= (u64)tf->hob_lbah << 40;
 			block |= (u64)tf->hob_lbam << 32;
 			block |= (u64)tf->hob_lbal << 24;
 		} else
 			block |= (tf->device & 0xf) << 24;
 		block |= tf->lbah << 16;
 		block |= tf->lbam << 8;
 		block |= tf->lbal;
 	} else {
 		u32 cyl, head, sect;
 		cyl = tf->lbam | (tf->lbah << 8);
 		head = tf->device & 0xf;
 		sect = tf->lbal;
 		if (!sect) {
 			ata_dev_printk(dev, KERN_WARNING, "device reported "
 				       "invalid CHS sector 0\n");
 			sect = 1; /* oh well */
 		}
 		block = (cyl * dev->heads + head) * dev->sectors + sect - 1;
 	}
 	return block;
 }
 /**
  *	ata_build_rw_tf - Build ATA taskfile for given read/write request
  *	@tf: Target ATA taskfile
  *	@dev: ATA device @tf belongs to
  *	@block: Block address
  *	@n_block: Number of blocks
  *	@tf_flags: RW/FUA etc...
  *	@tag: tag
  *
  *	LOCKING:
  *	None.
  *
  *	Build ATA taskfile @tf for read/write request described by
  *	@block, @n_block, @tf_flags and @tag on @dev.
  *
  *	RETURNS:
  *
  *	0 on success, -ERANGE if the request is too large for @dev,
  *	-EINVAL if the request is invalid.
  */
 int ata_build_rw_tf(struct ata_taskfile *tf, struct ata_device *dev,
 		    u64 block, u32 n_block, unsigned int tf_flags,
 		    unsigned int tag)
 {
 	tf->flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
 	tf->flags |= tf_flags;
 	if (ata_ncq_enabled(dev) && likely(tag != ATA_TAG_INTERNAL)) {
 		/* yay, NCQ */
 		if (!lba_48_ok(block, n_block))
 			return -ERANGE;
 		tf->protocol = ATA_PROT_NCQ;
 		tf->flags |= ATA_TFLAG_LBA | ATA_TFLAG_LBA48;
 		if (tf->flags & ATA_TFLAG_WRITE)
 			tf->command = ATA_CMD_FPDMA_WRITE;
 		else
 			tf->command = ATA_CMD_FPDMA_READ;
 		tf->nsect = tag << 3;
 		tf->hob_feature = (n_block >> 8) & 0xff;
 		tf->feature = n_block & 0xff;
 		tf->hob_lbah = (block >> 40) & 0xff;
 		tf->hob_lbam = (block >> 32) & 0xff;
 		tf->hob_lbal = (block >> 24) & 0xff;
 		tf->lbah = (block >> 16) & 0xff;
 		tf->lbam = (block >> 8) & 0xff;
 		tf->lbal = block & 0xff;
 		tf->device = 1 << 6;
 		if (tf->flags & ATA_TFLAG_FUA)
 			tf->device |= 1 << 7;
 	} else if (dev->flags & ATA_DFLAG_LBA) {
 		tf->flags |= ATA_TFLAG_LBA;
 		if (lba_28_ok(block, n_block)) {
 			/* use LBA28 */
 			tf->device |= (block >> 24) & 0xf;
 		} else if (lba_48_ok(block, n_block)) {
 			if (!(dev->flags & ATA_DFLAG_LBA48))
 				return -ERANGE;
 			/* use LBA48 */
 			tf->flags |= ATA_TFLAG_LBA48;
 			tf->hob_nsect = (n_block >> 8) & 0xff;
 			tf->hob_lbah = (block >> 40) & 0xff;
 			tf->hob_lbam = (block >> 32) & 0xff;
 			tf->hob_lbal = (block >> 24) & 0xff;
 		} else
 			/* request too large even for LBA48 */
 			return -ERANGE;
 		if (unlikely(ata_rwcmd_protocol(tf, dev) < 0))
 			return -EINVAL;
 		tf->nsect = n_block & 0xff;
 		tf->lbah = (block >> 16) & 0xff;
 		tf->lbam = (block >> 8) & 0xff;
 		tf->lbal = block & 0xff;
 		tf->device |= ATA_LBA;
 	} else {
 		/* CHS */
 		u32 sect, head, cyl, track;
 		/* The request -may- be too large for CHS addressing. */
 		if (!lba_28_ok(block, n_block))
 			return -ERANGE;
 		if (unlikely(ata_rwcmd_protocol(tf, dev) < 0))
 			return -EINVAL;
 		/* Convert LBA to CHS */
 		track = (u32)block / dev->sectors;
 		cyl   = track / dev->heads;
 		head  = track % dev->heads;
 		sect  = (u32)block % dev->sectors + 1;
 		DPRINTK("block %u track %u cyl %u head %u sect %u\n",
 			(u32)block, track, cyl, head, sect);
 		/* Check whether the converted CHS can fit.
 		   Cylinder: 0-65535
 		   Head: 0-15
 		   Sector: 1-255*/
 		if ((cyl >> 16) || (head >> 4) || (sect >> 8) || (!sect))
 			return -ERANGE;
 		tf->nsect = n_block & 0xff; /* Sector count 0 means 256 sectors */
 		tf->lbal = sect;
 		tf->lbam = cyl;
 		tf->lbah = cyl >> 8;
 		tf->device |= head;
 	}
 	return 0;
 }
 /**
  *	ata_pack_xfermask - Pack pio, mwdma and udma masks into xfer_mask
  *	@pio_mask: pio_mask
  *	@mwdma_mask: mwdma_mask
  *	@udma_mask: udma_mask
  *
  *	Pack @pio_mask, @mwdma_mask and @udma_mask into a single
  *	unsigned int xfer_mask.
  *
  *	LOCKING:
  *	None.
  *
  *	RETURNS:
  *	Packed xfer_mask.
  */
 unsigned long ata_pack_xfermask(unsigned long pio_mask,
 				unsigned long mwdma_mask,
 				unsigned long udma_mask)
 {
 	return ((pio_mask << ATA_SHIFT_PIO) & ATA_MASK_PIO) |
 		((mwdma_mask << ATA_SHIFT_MWDMA) & ATA_MASK_MWDMA) |
 		((udma_mask << ATA_SHIFT_UDMA) & ATA_MASK_UDMA);
 }
 /**
  *	ata_unpack_xfermask - Unpack xfer_mask into pio, mwdma and udma masks
  *	@xfer_mask: xfer_mask to unpack
  *	@pio_mask: resulting pio_mask
  *	@mwdma_mask: resulting mwdma_mask
  *	@udma_mask: resulting udma_mask
  *
  *	Unpack @xfer_mask into @pio_mask, @mwdma_mask and @udma_mask.
  *	Any NULL distination masks will be ignored.
  */
 void ata_unpack_xfermask(unsigned long xfer_mask, unsigned long *pio_mask,
 			 unsigned long *mwdma_mask, unsigned long *udma_mask)
 {
 	if (pio_mask)
 		*pio_mask = (xfer_mask & ATA_MASK_PIO) >> ATA_SHIFT_PIO;
 	if (mwdma_mask)
 		*mwdma_mask = (xfer_mask & ATA_MASK_MWDMA) >> ATA_SHIFT_MWDMA;
 	if (udma_mask)
 		*udma_mask = (xfer_mask & ATA_MASK_UDMA) >> ATA_SHIFT_UDMA;
 }
 static const struct ata_xfer_ent {
 	int shift, bits;
 	u8 base;
 } ata_xfer_tbl[] = {
 	{ ATA_SHIFT_PIO, ATA_NR_PIO_MODES, XFER_PIO_0 },
 	{ ATA_SHIFT_MWDMA, ATA_NR_MWDMA_MODES, XFER_MW_DMA_0 },
 	{ ATA_SHIFT_UDMA, ATA_NR_UDMA_MODES, XFER_UDMA_0 },
 	{ -1, },
 };
 /**
  *	ata_xfer_mask2mode - Find matching XFER_* for the given xfer_mask
  *	@xfer_mask: xfer_mask of interest
  *
  *	Return matching XFER_* value for @xfer_mask.  Only the highest
  *	bit of @xfer_mask is considered.
  *
  *	LOCKING:
  *	None.
  *
  *	RETURNS:
  *	Matching XFER_* value, 0xff if no match found.
  */
 u8 ata_xfer_mask2mode(unsigned long xfer_mask)
 {
 	int highbit = fls(xfer_mask) - 1;
 	const struct ata_xfer_ent *ent;
 	for (ent = ata_xfer_tbl; ent->shift >= 0; ent++)
 		if (highbit >= ent->shift && highbit < ent->shift + ent->bits)
 			return ent->base + highbit - ent->shift;
 	return 0xff;
 }
 /**
  *	ata_xfer_mode2mask - Find matching xfer_mask for XFER_*
  *	@xfer_mode: XFER_* of interest
  *
  *	Return matching xfer_mask for @xfer_mode.
  *
  *	LOCKING:
  *	None.
  *
  *	RETURNS:
  *	Matching xfer_mask, 0 if no match found.
  */
 unsigned long ata_xfer_mode2mask(u8 xfer_mode)
 {
 	const struct ata_xfer_ent *ent;
 	for (ent = ata_xfer_tbl; ent->shift >= 0; ent++)
 		if (xfer_mode >= ent->base && xfer_mode < ent->base + ent->bits)
 			return ((2 << (ent->shift + xfer_mode - ent->base)) - 1)
 				& ~((1 << ent->shift) - 1);
 	return 0;
 }
 /**
  *	ata_xfer_mode2shift - Find matching xfer_shift for XFER_*
  *	@xfer_mode: XFER_* of interest
  *
  *	Return matching xfer_shift for @xfer_mode.
  *
  *	LOCKING:
  *	None.
  *
  *	RETURNS:
  *	Matching xfer_shift, -1 if no match found.
  */
 int ata_xfer_mode2shift(unsigned long xfer_mode)
 {
 	const struct ata_xfer_ent *ent;
 	for (ent = ata_xfer_tbl; ent->shift >= 0; ent++)
 		if (xfer_mode >= ent->base && xfer_mode < ent->base + ent->bits)
 			return ent->shift;
 	return -1;
 }
 /**
  *	ata_mode_string - convert xfer_mask to string
  *	@xfer_mask: mask of bits supported; only highest bit counts.
  *
  *	Determine string which represents the highest speed
  *	(highest bit in @modemask).
  *
  *	LOCKING:
  *	None.
  *
  *	RETURNS:
  *	Constant C string representing highest speed listed in
  *	@mode_mask, or the constant C string "<n/a>".
  */
 const char *ata_mode_string(unsigned long xfer_mask)
 {
 	static const char * const xfer_mode_str[] = {
 		"PIO0",
 		"PIO1",
 		"PIO2",
 		"PIO3",
 		"PIO4",
 		"PIO5",
 		"PIO6",
 		"MWDMA0",
 		"MWDMA1",
 		"MWDMA2",
 		"MWDMA3",
 		"MWDMA4",
 		"UDMA/16",
 		"UDMA/25",
 		"UDMA/33",
 		"UDMA/44",
 		"UDMA/66",
 		"UDMA/100",
 		"UDMA/133",
 		"UDMA7",
 	};
 	int highbit;
 	highbit = fls(xfer_mask) - 1;
 	if (highbit >= 0 && highbit < ARRAY_SIZE(xfer_mode_str))
 		return xfer_mode_str[highbit];
 	return "<n/a>";
 }
 static const char *sata_spd_string(unsigned int spd)
 {
 	static const char * const spd_str[] = {
 		"1.5 Gbps",
 		"3.0 Gbps",
 		"6.0 Gbps",
 	};
 	if (spd == 0 || (spd - 1) >= ARRAY_SIZE(spd_str))
 		return "<unknown>";
 	return spd_str[spd - 1];
 }
 static int ata_dev_set_dipm(struct ata_device *dev, enum link_pm policy)
 {
 	struct ata_link *link = dev->link;
 	struct ata_port *ap = link->ap;
 	u32 scontrol;
 	unsigned int err_mask;
 	int rc;
 	/*
 	 * disallow DIPM for drivers which haven't set
 	 * ATA_FLAG_IPM.  This is because when DIPM is enabled,
 	 * phy ready will be set in the interrupt status on
 	 * state changes, which will cause some drivers to
 	 * think there are errors - additionally drivers will
 	 * need to disable hot plug.
 	 */
 	if (!(ap->flags & ATA_FLAG_IPM) || !ata_dev_enabled(dev)) {
 		ap->pm_policy = NOT_AVAILABLE;
 		return -EINVAL;
 	}
 	/*
 	 * For DIPM, we will only enable it for the
 	 * min_power setting.
 	 *
 	 * Why?  Because Disks are too stupid to know that
 	 * If the host rejects a request to go to SLUMBER
 	 * they should retry at PARTIAL, and instead it
 	 * just would give up.  So, for medium_power to
 	 * work at all, we need to only allow HIPM.
 	 */
 	rc = sata_scr_read(link, SCR_CONTROL, &scontrol);
 	if (rc)
 		return rc;
 	switch (policy) {
 	case MIN_POWER:
 		/* no restrictions on IPM transitions */
 		scontrol &= ~(0x3 << 8);
 		rc = sata_scr_write(link, SCR_CONTROL, scontrol);
 		if (rc)
 			return rc;
 		/* enable DIPM */
 		if (dev->flags & ATA_DFLAG_DIPM)
 			err_mask = ata_dev_set_feature(dev,
 					SETFEATURES_SATA_ENABLE, SATA_DIPM);
 		break;
 	case MEDIUM_POWER:
 		/* allow IPM to PARTIAL */
 		scontrol &= ~(0x1 << 8);
 		scontrol |= (0x2 << 8);
 		rc = sata_scr_write(link, SCR_CONTROL, scontrol);
 		if (rc)
 			return rc;
 		/*
 		 * we don't have to disable DIPM since IPM flags
 		 * disallow transitions to SLUMBER, which effectively
 		 * disable DIPM if it does not support PARTIAL
 		 */
 		break;
 	case NOT_AVAILABLE:
 	case MAX_PERFORMANCE:
 		/* disable all IPM transitions */
 		scontrol |= (0x3 << 8);
 		rc = sata_scr_write(link, SCR_CONTROL, scontrol);
 		if (rc)
 			return rc;
 		/*
 		 * we don't have to disable DIPM since IPM flags
 		 * disallow all transitions which effectively
 		 * disable DIPM anyway.
 		 */
 		break;
 	}
 	/* FIXME: handle SET FEATURES failure */
 	(void) err_mask;
 	return 0;
 }
 /**
  *	ata_dev_enable_pm - enable SATA interface power management
  *	@dev:  device to enable power management
  *	@policy: the link power management policy
  *
  *	Enable SATA Interface power management.  This will enable
  *	Device Interface Power Management (DIPM) for min_power
  * 	policy, and then call driver specific callbacks for
  *	enabling Host Initiated Power management.
  *
  *	Locking: Caller.
  *	Returns: -EINVAL if IPM is not supported, 0 otherwise.
  */
 void ata_dev_enable_pm(struct ata_device *dev, enum link_pm policy)
 {
 	int rc = 0;
 	struct ata_port *ap = dev->link->ap;
 	/* set HIPM first, then DIPM */
 	if (ap->ops->enable_pm)
 		rc = ap->ops->enable_pm(ap, policy);
 	if (rc)
 		goto enable_pm_out;
 	rc = ata_dev_set_dipm(dev, policy);
 enable_pm_out:
 	if (rc)
 		ap->pm_policy = MAX_PERFORMANCE;
 	else
 		ap->pm_policy = policy;
 	return /* rc */;	/* hopefully we can use 'rc' eventually */
 }
 #ifdef CONFIG_PM
 /**
  *	ata_dev_disable_pm - disable SATA interface power management
  *	@dev: device to disable power management
  *
  *	Disable SATA Interface power management.  This will disable
  *	Device Interface Power Management (DIPM) without changing
  * 	policy,  call driver specific callbacks for disabling Host
  * 	Initiated Power management.
  *
  *	Locking: Caller.
  *	Returns: void
  */
 static void ata_dev_disable_pm(struct ata_device *dev)
 {
 	struct ata_port *ap = dev->link->ap;
 	ata_dev_set_dipm(dev, MAX_PERFORMANCE);
 	if (ap->ops->disable_pm)
 		ap->ops->disable_pm(ap);
 }
 #endif	/* CONFIG_PM */
 void ata_lpm_schedule(struct ata_port *ap, enum link_pm policy)
 {
 	ap->pm_policy = policy;
 	ap->link.eh_info.action |= ATA_EH_LPM;
 	ap->link.eh_info.flags |= ATA_EHI_NO_AUTOPSY;
 	ata_port_schedule_eh(ap);
 }
 #ifdef CONFIG_PM
 static void ata_lpm_enable(struct ata_host *host)
 {
 	struct ata_link *link;
 	struct ata_port *ap;
 	struct ata_device *dev;
 	int i;
 	for (i = 0; i < host->n_ports; i++) {
 		ap = host->ports[i];
 		ata_for_each_link(link, ap, EDGE) {
 			ata_for_each_dev(dev, link, ALL)
 				ata_dev_disable_pm(dev);
 		}
 	}
 }
 static void ata_lpm_disable(struct ata_host *host)
 {
 	int i;
 	for (i = 0; i < host->n_ports; i++) {
 		struct ata_port *ap = host->ports[i];
 		ata_lpm_schedule(ap, ap->pm_policy);
 	}
 }
 #endif	/* CONFIG_PM */
 /**
  *	ata_dev_classify - determine device type based on ATA-spec signature
  *	@tf: ATA taskfile register set for device to be identified
  *
  *	Determine from taskfile register contents whether a device is
  *	ATA or ATAPI, as per "Signature and persistence" section
  *	of ATA/PI spec (volume 1, sect 5.14).
  *
  *	LOCKING:
  *	None.
  *
  *	RETURNS:
  *	Device type, %ATA_DEV_ATA, %ATA_DEV_ATAPI, %ATA_DEV_PMP or
  *	%ATA_DEV_UNKNOWN the event of failure.
  */
 unsigned int ata_dev_classify(const struct ata_taskfile *tf)
 {
 	/* Apple's open source Darwin code hints that some devices only
 	 * put a proper signature into the LBA mid/high registers,
 	 * So, we only check those.  It's sufficient for uniqueness.
 	 *
 	 * ATA/ATAPI-7 (d1532v1r1: Feb. 19, 2003) specified separate
 	 * signatures for ATA and ATAPI devices attached on SerialATA,
 	 * 0x3c/0xc3 and 0x69/0x96 respectively.  However, SerialATA
 	 * spec has never mentioned about using different signatures
 	 * for ATA/ATAPI devices.  Then, Serial ATA II: Port
 	 * Multiplier specification began to use 0x69/0x96 to identify
 	 * port multpliers and 0x3c/0xc3 to identify SEMB device.
 	 * ATA/ATAPI-7 dropped descriptions about 0x3c/0xc3 and
 	 * 0x69/0x96 shortly and described them as reserved for
 	 * SerialATA.
 	 *
 	 * We follow the current spec and consider that 0x69/0x96
 	 * identifies a port multiplier and 0x3c/0xc3 a SEMB device.
 	 * Unfortunately, WDC WD1600JS-62MHB5 (a hard drive) reports
 	 * SEMB signature.  This is worked around in
 	 * ata_dev_read_id().
 	 */
 	if ((tf->lbam == 0) && (tf->lbah == 0)) {
 		DPRINTK("found ATA device by sig\n");
 		return ATA_DEV_ATA;
 	}
 	if ((tf->lbam == 0x14) && (tf->lbah == 0xeb)) {
 		DPRINTK("found ATAPI device by sig\n");
 		return ATA_DEV_ATAPI;
 	}
 	if ((tf->lbam == 0x69) && (tf->lbah == 0x96)) {
 		DPRINTK("found PMP device by sig\n");
 		return ATA_DEV_PMP;
 	}
 	if ((tf->lbam == 0x3c) && (tf->lbah == 0xc3)) {
 		DPRINTK("found SEMB device by sig (could be ATA device)\n");
 		return ATA_DEV_SEMB;
 	}
 	DPRINTK("unknown device\n");
 	return ATA_DEV_UNKNOWN;
 }
 /**
  *	ata_id_string - Convert IDENTIFY DEVICE page into string
  *	@id: IDENTIFY DEVICE results we will examine
  *	@s: string into which data is output
  *	@ofs: offset into identify device page
  *	@len: length of string to return. must be an even number.
  *
  *	The strings in the IDENTIFY DEVICE page are broken up into
  *	16-bit chunks.  Run through the string, and output each
  *	8-bit chunk linearly, regardless of platform.
  *
  *	LOCKING:
  *	caller.
  */
 void ata_id_string(const u16 *id, unsigned char *s,
 		   unsigned int ofs, unsigned int len)
 {
 	unsigned int c;
 	BUG_ON(len & 1);
 	while (len > 0) {
 		c = id[ofs] >> 8;
 		*s = c;
 		s++;
 		c = id[ofs] & 0xff;
 		*s = c;
 		s++;
 		ofs++;
 		len -= 2;
 	}
 }
 /**
  *	ata_id_c_string - Convert IDENTIFY DEVICE page into C string
  *	@id: IDENTIFY DEVICE results we will examine
  *	@s: string into which data is output
  *	@ofs: offset into identify device page
  *	@len: length of string to return. must be an odd number.
  *
  *	This function is identical to ata_id_string except that it
  *	trims trailing spaces and terminates the resulting string with
  *	null.  @len must be actual maximum length (even number) + 1.
  *
  *	LOCKING:
  *	caller.
  */
 void ata_id_c_string(const u16 *id, unsigned char *s,
 		     unsigned int ofs, unsigned int len)
 {
 	unsigned char *p;
 	ata_id_string(id, s, ofs, len - 1);
 	p = s + strnlen(s, len - 1);
 	while (p > s && p[-1] == ' ')
 		p--;
 	*p = '\0';
 }
 static u64 ata_id_n_sectors(const u16 *id)
 {
 	if (ata_id_has_lba(id)) {
 		if (ata_id_has_lba48(id))
 			return ata_id_u64(id, ATA_ID_LBA_CAPACITY_2);
 		else
 			return ata_id_u32(id, ATA_ID_LBA_CAPACITY);
 	} else {
 		if (ata_id_current_chs_valid(id))
 			return id[ATA_ID_CUR_CYLS] * id[ATA_ID_CUR_HEADS] *
 			       id[ATA_ID_CUR_SECTORS];
 		else
 			return id[ATA_ID_CYLS] * id[ATA_ID_HEADS] *
 			       id[ATA_ID_SECTORS];
 	}
 }
 u64 ata_tf_to_lba48(const struct ata_taskfile *tf)
 {
 	u64 sectors = 0;
 	sectors |= ((u64)(tf->hob_lbah & 0xff)) << 40;
 	sectors |= ((u64)(tf->hob_lbam & 0xff)) << 32;
 	sectors |= ((u64)(tf->hob_lbal & 0xff)) << 24;
 	sectors |= (tf->lbah & 0xff) << 16;
 	sectors |= (tf->lbam & 0xff) << 8;
 	sectors |= (tf->lbal & 0xff);
 	return sectors;
 }
 u64 ata_tf_to_lba(const struct ata_taskfile *tf)
 {
 	u64 sectors = 0;
 	sectors |= (tf->device & 0x0f) << 24;
 	sectors |= (tf->lbah & 0xff) << 16;
 	sectors |= (tf->lbam & 0xff) << 8;
 	sectors |= (tf->lbal & 0xff);
 	return sectors;
 }
 /**
  *	ata_read_native_max_address - Read native max address
  *	@dev: target device
  *	@max_sectors: out parameter for the result native max address
  *
  *	Perform an LBA48 or LBA28 native size query upon the device in
  *	question.
  *
  *	RETURNS:
  *	0 on success, -EACCES if command is aborted by the drive.
  *	-EIO on other errors.
  */
 static int ata_read_native_max_address(struct ata_device *dev, u64 *max_sectors)
 {
 	unsigned int err_mask;
 	struct ata_taskfile tf;
 	int lba48 = ata_id_has_lba48(dev->id);
 	ata_tf_init(dev, &tf);
 	/* always clear all address registers */
 	tf.flags |= ATA_TFLAG_DEVICE | ATA_TFLAG_ISADDR;
 	if (lba48) {
 		tf.command = ATA_CMD_READ_NATIVE_MAX_EXT;
 		tf.flags |= ATA_TFLAG_LBA48;
 	} else
 		tf.command = ATA_CMD_READ_NATIVE_MAX;
 	tf.protocol |= ATA_PROT_NODATA;
 	tf.device |= ATA_LBA;
 	err_mask = ata_exec_internal(dev, &tf, NULL, DMA_NONE, NULL, 0, 0);
 	if (err_mask) {
 		ata_dev_printk(dev, KERN_WARNING, "failed to read native "
 			       "max address (err_mask=0x%x)\n", err_mask);
 		if (err_mask == AC_ERR_DEV && (tf.feature & ATA_ABORTED))
 			return -EACCES;
 		return -EIO;
 	}
 	if (lba48)
 		*max_sectors = ata_tf_to_lba48(&tf) + 1;
 	else
 		*max_sectors = ata_tf_to_lba(&tf) + 1;
 	if (dev->horkage & ATA_HORKAGE_HPA_SIZE)
 		(*max_sectors)--;
 	return 0;
 }
 /**
  *	ata_set_max_sectors - Set max sectors
  *	@dev: target device
  *	@new_sectors: new max sectors value to set for the device
  *
  *	Set max sectors of @dev to @new_sectors.
  *
  *	RETURNS:
  *	0 on success, -EACCES if command is aborted or denied (due to
  *	previous non-volatile SET_MAX) by the drive.  -EIO on other
  *	errors.
  */
 static int ata_set_max_sectors(struct ata_device *dev, u64 new_sectors)
 {
 	unsigned int err_mask;
 	struct ata_taskfile tf;
 	int lba48 = ata_id_has_lba48(dev->id);
 	new_sectors--;
 	ata_tf_init(dev, &tf);
 	tf.flags |= ATA_TFLAG_DEVICE | ATA_TFLAG_ISADDR;
 	if (lba48) {
 		tf.command = ATA_CMD_SET_MAX_EXT;
 		tf.flags |= ATA_TFLAG_LBA48;
 		tf.hob_lbal = (new_sectors >> 24) & 0xff;
 		tf.hob_lbam = (new_sectors >> 32) & 0xff;
 		tf.hob_lbah = (new_sectors >> 40) & 0xff;
 	} else {
 		tf.command = ATA_CMD_SET_MAX;
 		tf.device |= (new_sectors >> 24) & 0xf;
 	}
 	tf.protocol |= ATA_PROT_NODATA;
 	tf.device |= ATA_LBA;
 	tf.lbal = (new_sectors >> 0) & 0xff;
 	tf.lbam = (new_sectors >> 8) & 0xff;
 	tf.lbah = (new_sectors >> 16) & 0xff;
 	err_mask = ata_exec_internal(dev, &tf, NULL, DMA_NONE, NULL, 0, 0);
 	if (err_mask) {
 		ata_dev_printk(dev, KERN_WARNING, "failed to set "
 			       "max address (err_mask=0x%x)\n", err_mask);
 		if (err_mask == AC_ERR_DEV &&
 		    (tf.feature & (ATA_ABORTED | ATA_IDNF)))
 			return -EACCES;
 		return -EIO;
 	}
 	return 0;
 }
 /**
  *	ata_hpa_resize		-	Resize a device with an HPA set
  *	@dev: Device to resize
  *
  *	Read the size of an LBA28 or LBA48 disk with HPA features and resize
  *	it if required to the full size of the media. The caller must check
  *	the drive has the HPA feature set enabled.
  *
  *	RETURNS:
  *	0 on success, -errno on failure.
  */
 static int ata_hpa_resize(struct ata_device *dev)
 {
 	struct ata_eh_context *ehc = &dev->link->eh_context;
 	int print_info = ehc->i.flags & ATA_EHI_PRINTINFO;
 	bool unlock_hpa = ata_ignore_hpa || dev->flags & ATA_DFLAG_UNLOCK_HPA;
 	u64 sectors = ata_id_n_sectors(dev->id);
 	u64 native_sectors;
 	int rc;
 	/* do we need to do it? */
 	if (dev->class != ATA_DEV_ATA ||
 	    !ata_id_has_lba(dev->id) || !ata_id_hpa_enabled(dev->id) ||
 	    (dev->horkage & ATA_HORKAGE_BROKEN_HPA))
 		return 0;
 	/* read native max address */
 	rc = ata_read_native_max_address(dev, &native_sectors);
 	if (rc) {
 		/* If device aborted the command or HPA isn't going to
 		 * be unlocked, skip HPA resizing.
 		 */
 		if (rc == -EACCES || !unlock_hpa) {
 			ata_dev_printk(dev, KERN_WARNING, "HPA support seems "
 				       "broken, skipping HPA handling\n");
 			dev->horkage |= ATA_HORKAGE_BROKEN_HPA;
 			/* we can continue if device aborted the command */
 			if (rc == -EACCES)
 				rc = 0;
 		}
 		return rc;
 	}
 	dev->n_native_sectors = native_sectors;
 	/* nothing to do? */
 	if (native_sectors <= sectors || !unlock_hpa) {
 		if (!print_info || native_sectors == sectors)
 			return 0;
 		if (native_sectors > sectors)
 			ata_dev_printk(dev, KERN_INFO,
 				"HPA detected: current %llu, native %llu\n",
 				(unsigned long long)sectors,
 				(unsigned long long)native_sectors);
 		else if (native_sectors < sectors)
 			ata_dev_printk(dev, KERN_WARNING,
 				"native sectors (%llu) is smaller than "
 				"sectors (%llu)\n",
 				(unsigned long long)native_sectors,
 				(unsigned long long)sectors);
 		return 0;
 	}
 	/* let's unlock HPA */
 	rc = ata_set_max_sectors(dev, native_sectors);
 	if (rc == -EACCES) {
 		/* if device aborted the command, skip HPA resizing */
 		ata_dev_printk(dev, KERN_WARNING, "device aborted resize "
 			       "(%llu -> %llu), skipping HPA handling\n",
 			       (unsigned long long)sectors,
 			       (unsigned long long)native_sectors);
 		dev->horkage |= ATA_HORKAGE_BROKEN_HPA;
 		return 0;
 	} else if (rc)
 		return rc;
 	/* re-read IDENTIFY data */
 	rc = ata_dev_reread_id(dev, 0);
 	if (rc) {
 		ata_dev_printk(dev, KERN_ERR, "failed to re-read IDENTIFY "
 			       "data after HPA resizing\n");
 		return rc;
 	}
 	if (print_info) {
 		u64 new_sectors = ata_id_n_sectors(dev->id);
 		ata_dev_printk(dev, KERN_INFO,
 			"HPA unlocked: %llu -> %llu, native %llu\n",
 			(unsigned long long)sectors,
 			(unsigned long long)new_sectors,
 			(unsigned long long)native_sectors);
 	}
 	return 0;
 }
 /**
  *	ata_dump_id - IDENTIFY DEVICE info debugging output
  *	@id: IDENTIFY DEVICE page to dump
  *
  *	Dump selected 16-bit words from the given IDENTIFY DEVICE
  *	page.
  *
  *	LOCKING:
  *	caller.
  */
 static inline void ata_dump_id(const u16 *id)
 {
 	DPRINTK("49==0x%04x  "
 		"53==0x%04x  "
 		"63==0x%04x  "
 		"64==0x%04x  "
 		"75==0x%04x  \n",
 		id[49],
 		id[53],
 		id[63],
 		id[64],
 		id[75]);
 	DPRINTK("80==0x%04x  "
 		"81==0x%04x  "
 		"82==0x%04x  "
 		"83==0x%04x  "
 		"84==0x%04x  \n",
 		id[80],
 		id[81],
 		id[82],
 		id[83],
 		id[84]);
 	DPRINTK("88==0x%04x  "
 		"93==0x%04x\n",
 		id[88],
 		id[93]);
 }
 /**
  *	ata_id_xfermask - Compute xfermask from the given IDENTIFY data
  *	@id: IDENTIFY data to compute xfer mask from
  *
  *	Compute the xfermask for this device. This is not as trivial
  *	as it seems if we must consider early devices correctly.
  *
  *	FIXME: pre IDE drive timing (do we care ?).
  *
  *	LOCKING:
  *	None.
  *
  *	RETURNS:
  *	Computed xfermask
  */
 unsigned long ata_id_xfermask(const u16 *id)
 {
 	unsigned long pio_mask, mwdma_mask, udma_mask;
 	/* Usual case. Word 53 indicates word 64 is valid */
 	if (id[ATA_ID_FIELD_VALID] & (1 << 1)) {
 		pio_mask = id[ATA_ID_PIO_MODES] & 0x03;
 		pio_mask <<= 3;
 		pio_mask |= 0x7;
 	} else {
 		/* If word 64 isn't valid then Word 51 high byte holds
 		 * the PIO timing number for the maximum. Turn it into
 		 * a mask.
 		 */
 		u8 mode = (id[ATA_ID_OLD_PIO_MODES] >> 8) & 0xFF;
 		if (mode < 5)	/* Valid PIO range */
 			pio_mask = (2 << mode) - 1;
 		else
 			pio_mask = 1;
 		/* But wait.. there's more. Design your standards by
 		 * committee and you too can get a free iordy field to
 		 * process. However its the speeds not the modes that
 		 * are supported... Note drivers using the timing API
 		 * will get this right anyway
 		 */
 	}
 	mwdma_mask = id[ATA_ID_MWDMA_MODES] & 0x07;
 	if (ata_id_is_cfa(id)) {
 		/*
 		 *	Process compact flash extended modes
 		 */
 		int pio = (id[ATA_ID_CFA_MODES] >> 0) & 0x7;
 		int dma = (id[ATA_ID_CFA_MODES] >> 3) & 0x7;
 		if (pio)
 			pio_mask |= (1 << 5);
 		if (pio > 1)
 			pio_mask |= (1 << 6);
 		if (dma)
 			mwdma_mask |= (1 << 3);
 		if (dma > 1)
 			mwdma_mask |= (1 << 4);
 	}
 	udma_mask = 0;
 	if (id[ATA_ID_FIELD_VALID] & (1 << 2))
 		udma_mask = id[ATA_ID_UDMA_MODES] & 0xff;
 	return ata_pack_xfermask(pio_mask, mwdma_mask, udma_mask);
 }
 static void ata_qc_complete_internal(struct ata_queued_cmd *qc)
 {
 	struct completion *waiting = qc->private_data;
 	complete(waiting);
 }
 /**
  *	ata_exec_internal_sg - execute libata internal command
  *	@dev: Device to which the command is sent
  *	@tf: Taskfile registers for the command and the result
  *	@cdb: CDB for packet command
  *	@dma_dir: Data tranfer direction of the command
  *	@sgl: sg list for the data buffer of the command
  *	@n_elem: Number of sg entries
  *	@timeout: Timeout in msecs (0 for default)
  *
  *	Executes libata internal command with timeout.  @tf contains
  *	command on entry and result on return.  Timeout and error
  *	conditions are reported via return value.  No recovery action
  *	is taken after a command times out.  It's caller's duty to
  *	clean up after timeout.
  *
  *	LOCKING:
  *	None.  Should be called with kernel context, might sleep.
  *
  *	RETURNS:
  *	Zero on success, AC_ERR_* mask on failure
  */
 unsigned ata_exec_internal_sg(struct ata_device *dev,
 			      struct ata_taskfile *tf, const u8 *cdb,
 			      int dma_dir, struct scatterlist *sgl,
 			      unsigned int n_elem, unsigned long timeout)
 {
 	struct ata_link *link = dev->link;
 	struct ata_port *ap = link->ap;
 	u8 command = tf->command;
 	int auto_timeout = 0;
 	struct ata_queued_cmd *qc;
 	unsigned int tag, preempted_tag;
 	u32 preempted_sactive, preempted_qc_active;
 	int preempted_nr_active_links;
 	DECLARE_COMPLETION_ONSTACK(wait);
 	unsigned long flags;
 	unsigned int err_mask;
 	int rc;
 	spin_lock_irqsave(ap->lock, flags);
 	/* no internal command while frozen */
 	if (ap->pflags & ATA_PFLAG_FROZEN) {
 		spin_unlock_irqrestore(ap->lock, flags);
 		return AC_ERR_SYSTEM;
 	}
 	/* initialize internal qc */
 	/* XXX: Tag 0 is used for drivers with legacy EH as some
 	 * drivers choke if any other tag is given.  This breaks
 	 * ata_tag_internal() test for those drivers.  Don't use new
 	 * EH stuff without converting to it.
 	 */
 	if (ap->ops->error_handler)
 		tag = ATA_TAG_INTERNAL;
 	else
 		tag = 0;
 	if (test_and_set_bit(tag, &ap->qc_allocated))
 		BUG();
 	qc = __ata_qc_from_tag(ap, tag);
 	qc->tag = tag;
 	qc->scsicmd = NULL;
 	qc->ap = ap;
 	qc->dev = dev;
 	ata_qc_reinit(qc);
 	preempted_tag = link->active_tag;
 	preempted_sactive = link->sactive;
 	preempted_qc_active = ap->qc_active;
 	preempted_nr_active_links = ap->nr_active_links;
 	link->active_tag = ATA_TAG_POISON;
 	link->sactive = 0;
 	ap->qc_active = 0;
 	ap->nr_active_links = 0;
 	/* prepare & issue qc */
 	qc->tf = *tf;
 	if (cdb)
 		memcpy(qc->cdb, cdb, ATAPI_CDB_LEN);
 	qc->flags |= ATA_QCFLAG_RESULT_TF;
 	qc->dma_dir = dma_dir;
 	if (dma_dir != DMA_NONE) {
 		unsigned int i, buflen = 0;
 		struct scatterlist *sg;
 		for_each_sg(sgl, sg, n_elem, i)
 			buflen += sg->length;
 		ata_sg_init(qc, sgl, n_elem);
 		qc->nbytes = buflen;
 	}
 	qc->private_data = &wait;
 	qc->complete_fn = ata_qc_complete_internal;
 	ata_qc_issue(qc);
 	spin_unlock_irqrestore(ap->lock, flags);
 	if (!timeout) {
 		if (ata_probe_timeout)
 			timeout = ata_probe_timeout * 1000;
 		else {
 			timeout = ata_internal_cmd_timeout(dev, command);
 			auto_timeout = 1;
 		}
 	}
 	rc = wait_for_completion_timeout(&wait, msecs_to_jiffies(timeout));
 	ata_sff_flush_pio_task(ap);
 	if (!rc) {
 		spin_lock_irqsave(ap->lock, flags);
 		/* We're racing with irq here.  If we lose, the
 		 * following test prevents us from completing the qc
 		 * twice.  If we win, the port is frozen and will be
 		 * cleaned up by ->post_internal_cmd().
 		 */
 		if (qc->flags & ATA_QCFLAG_ACTIVE) {
 			qc->err_mask |= AC_ERR_TIMEOUT;
 			if (ap->ops->error_handler)
 				ata_port_freeze(ap);
 			else
 				ata_qc_complete(qc);
 			if (ata_msg_warn(ap))
 				ata_dev_printk(dev, KERN_WARNING,
 					"qc timeout (cmd 0x%x)\n", command);
 		}
 		spin_unlock_irqrestore(ap->lock, flags);
 	}
 	/* do post_internal_cmd */
 	if (ap->ops->post_internal_cmd)
 		ap->ops->post_internal_cmd(qc);
 	/* perform minimal error analysis */
 	if (qc->flags & ATA_QCFLAG_FAILED) {
 		if (qc->result_tf.command & (ATA_ERR | ATA_DF))
 			qc->err_mask |= AC_ERR_DEV;
 		if (!qc->err_mask)
 			qc->err_mask |= AC_ERR_OTHER;
 		if (qc->err_mask & ~AC_ERR_OTHER)
 			qc->err_mask &= ~AC_ERR_OTHER;
 	}
 	/* finish up */
 	spin_lock_irqsave(ap->lock, flags);
 	*tf = qc->result_tf;
 	err_mask = qc->err_mask;
 	ata_qc_free(qc);
 	link->active_tag = preempted_tag;
 	link->sactive = preempted_sactive;
 	ap->qc_active = preempted_qc_active;
 	ap->nr_active_links = preempted_nr_active_links;
 	spin_unlock_irqrestore(ap->lock, flags);
 	if ((err_mask & AC_ERR_TIMEOUT) && auto_timeout)
 		ata_internal_cmd_timed_out(dev, command);
 	return err_mask;
 }
 /**
  *	ata_exec_internal - execute libata internal command
  *	@dev: Device to which the command is sent
  *	@tf: Taskfile registers for the command and the result
  *	@cdb: CDB for packet command
  *	@dma_dir: Data tranfer direction of the command
  *	@buf: Data buffer of the command
  *	@buflen: Length of data buffer
  *	@timeout: Timeout in msecs (0 for default)
  *
  *	Wrapper around ata_exec_internal_sg() which takes simple
  *	buffer instead of sg list.
  *
  *	LOCKING:
  *	None.  Should be called with kernel context, might sleep.
  *
  *	RETURNS:
  *	Zero on success, AC_ERR_* mask on failure
  */
 unsigned ata_exec_internal(struct ata_device *dev,
 			   struct ata_taskfile *tf, const u8 *cdb,
 			   int dma_dir, void *buf, unsigned int buflen,
 			   unsigned long timeout)
 {
 	struct scatterlist *psg = NULL, sg;
 	unsigned int n_elem = 0;
 	if (dma_dir != DMA_NONE) {
 		WARN_ON(!buf);
 		sg_init_one(&sg, buf, buflen);
 		psg = &sg;
 		n_elem++;
 	}
 	return ata_exec_internal_sg(dev, tf, cdb, dma_dir, psg, n_elem,
 				    timeout);
 }
 /**
  *	ata_do_simple_cmd - execute simple internal command
  *	@dev: Device to which the command is sent
  *	@cmd: Opcode to execute
  *
  *	Execute a 'simple' command, that only consists of the opcode
  *	'cmd' itself, without filling any other registers
  *
  *	LOCKING:
  *	Kernel thread context (may sleep).
  *
  *	RETURNS:
  *	Zero on success, AC_ERR_* mask on failure
  */
 unsigned int ata_do_simple_cmd(struct ata_device *dev, u8 cmd)
 {
 	struct ata_taskfile tf;
 	ata_tf_init(dev, &tf);
 	tf.command = cmd;
 	tf.flags |= ATA_TFLAG_DEVICE;
 	tf.protocol = ATA_PROT_NODATA;
 	return ata_exec_internal(dev, &tf, NULL, DMA_NONE, NULL, 0, 0);
 }
 /**
  *	ata_pio_need_iordy	-	check if iordy needed
  *	@adev: ATA device
  *
  *	Check if the current speed of the device requires IORDY. Used
  *	by various controllers for chip configuration.
  */
 unsigned int ata_pio_need_iordy(const struct ata_device *adev)
 {
 	/* Don't set IORDY if we're preparing for reset.  IORDY may
 	 * lead to controller lock up on certain controllers if the
 	 * port is not occupied.  See bko#11703 for details.
 	 */
 	if (adev->link->ap->pflags & ATA_PFLAG_RESETTING)
 		return 0;
 	/* Controller doesn't support IORDY.  Probably a pointless
 	 * check as the caller should know this.
 	 */
 	if (adev->link->ap->flags & ATA_FLAG_NO_IORDY)
 		return 0;
 	/* CF spec. r4.1 Table 22 says no iordy on PIO5 and PIO6.  */
 	if (ata_id_is_cfa(adev->id)
 	    && (adev->pio_mode == XFER_PIO_5 || adev->pio_mode == XFER_PIO_6))
 		return 0;
 	/* PIO3 and higher it is mandatory */
 	if (adev->pio_mode > XFER_PIO_2)
 		return 1;
 	/* We turn it on when possible */
 	if (ata_id_has_iordy(adev->id))
 		return 1;
 	return 0;
 }
 /**
  *	ata_pio_mask_no_iordy	-	Return the non IORDY mask
  *	@adev: ATA device
  *
  *	Compute the highest mode possible if we are not using iordy. Return
  *	-1 if no iordy mode is available.
  */
 static u32 ata_pio_mask_no_iordy(const struct ata_device *adev)
 {
 	/* If we have no drive specific rule, then PIO 2 is non IORDY */
 	if (adev->id[ATA_ID_FIELD_VALID] & 2) {	/* EIDE */
 		u16 pio = adev->id[ATA_ID_EIDE_PIO];
 		/* Is the speed faster than the drive allows non IORDY ? */
 		if (pio) {
 			/* This is cycle times not frequency - watch the logic! */
 			if (pio > 240)	/* PIO2 is 240nS per cycle */
 				return 3 << ATA_SHIFT_PIO;
 			return 7 << ATA_SHIFT_PIO;
 		}
 	}
 	return 3 << ATA_SHIFT_PIO;
 }
 /**
  *	ata_do_dev_read_id		-	default ID read method
  *	@dev: device
  *	@tf: proposed taskfile
  *	@id: data buffer
  *
  *	Issue the identify taskfile and hand back the buffer containing
  *	identify data. For some RAID controllers and for pre ATA devices
  *	this function is wrapped or replaced by the driver
  */
 unsigned int ata_do_dev_read_id(struct ata_device *dev,
 					struct ata_taskfile *tf, u16 *id)
 {
 	return ata_exec_internal(dev, tf, NULL, DMA_FROM_DEVICE,
 				     id, sizeof(id[0]) * ATA_ID_WORDS, 0);
 }
 /**
  *	ata_dev_read_id - Read ID data from the specified device
  *	@dev: target device
  *	@p_class: pointer to class of the target device (may be changed)
  *	@flags: ATA_READID_* flags
  *	@id: buffer to read IDENTIFY data into
  *
  *	Read ID data from the specified device.  ATA_CMD_ID_ATA is
  *	performed on ATA devices and ATA_CMD_ID_ATAPI on ATAPI
  *	devices.  This function also issues ATA_CMD_INIT_DEV_PARAMS
  *	for pre-ATA4 drives.
  *
  *	FIXME: ATA_CMD_ID_ATA is optional for early drives and right
  *	now we abort if we hit that case.
  *
  *	LOCKING:
  *	Kernel thread context (may sleep)
  *
  *	RETURNS:
  *	0 on success, -errno otherwise.
  */
 int ata_dev_read_id(struct ata_device *dev, unsigned int *p_class,
 		    unsigned int flags, u16 *id)
 {
 	struct ata_port *ap = dev->link->ap;
 	unsigned int class = *p_class;
 	struct ata_taskfile tf;
 	unsigned int err_mask = 0;
 	const char *reason;
 	bool is_semb = class == ATA_DEV_SEMB;
 	int may_fallback = 1, tried_spinup = 0;
 	int rc;
 	if (ata_msg_ctl(ap))
 		ata_dev_printk(dev, KERN_DEBUG, "%s: ENTER\n", __func__);
 retry:
 	ata_tf_init(dev, &tf);
 	switch (class) {
 	case ATA_DEV_SEMB:
 		class = ATA_DEV_ATA;	/* some hard drives report SEMB sig */
 	case ATA_DEV_ATA:
 		tf.command = ATA_CMD_ID_ATA;
 		break;
 	case ATA_DEV_ATAPI:
 		tf.command = ATA_CMD_ID_ATAPI;
 		break;
 	default:
 		rc = -ENODEV;
 		reason = "unsupported class";
 		goto err_out;
 	}
 	tf.protocol = ATA_PROT_PIO;
 	/* Some devices choke if TF registers contain garbage.  Make
 	 * sure those are properly initialized.
 	 */
 	tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
 	/* Device presence detection is unreliable on some
 	 * controllers.  Always poll IDENTIFY if available.
 	 */
 	tf.flags |= ATA_TFLAG_POLLING;
 	if (ap->ops->read_id)
 		err_mask = ap->ops->read_id(dev, &tf, id);
 	else
 		err_mask = ata_do_dev_read_id(dev, &tf, id);
 	if (err_mask) {
 		if (err_mask & AC_ERR_NODEV_HINT) {
 			ata_dev_printk(dev, KERN_DEBUG,
 				       "NODEV after polling detection\n");
 			return -ENOENT;
 		}
 		if (is_semb) {
 			ata_dev_printk(dev, KERN_INFO, "IDENTIFY failed on "
 				       "device w/ SEMB sig, disabled\n");
 			/* SEMB is not supported yet */
 			*p_class = ATA_DEV_SEMB_UNSUP;
 			return 0;
 		}
 		if ((err_mask == AC_ERR_DEV) && (tf.feature & ATA_ABORTED)) {
 			/* Device or controller might have reported
 			 * the wrong device class.  Give a shot at the
 			 * other IDENTIFY if the current one is
 			 * aborted by the device.
 			 */
 			if (may_fallback) {
 				may_fallback = 0;
 				if (class == ATA_DEV_ATA)
 					class = ATA_DEV_ATAPI;
 				else
 					class = ATA_DEV_ATA;
 				goto retry;
 			}
 			/* Control reaches here iff the device aborted
 			 * both flavors of IDENTIFYs which happens
 			 * sometimes with phantom devices.
 			 */
 			ata_dev_printk(dev, KERN_DEBUG,
 				       "both IDENTIFYs aborted, assuming NODEV\n");
 			return -ENOENT;
 		}
 		rc = -EIO;
 		reason = "I/O error";
 		goto err_out;
 	}
 	if (dev->horkage & ATA_HORKAGE_DUMP_ID) {
 		ata_dev_printk(dev, KERN_DEBUG, "dumping IDENTIFY data, "
 			       "class=%d may_fallback=%d tried_spinup=%d\n",
 			       class, may_fallback, tried_spinup);
 		print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_OFFSET,
 			       16, 2, id, ATA_ID_WORDS * sizeof(*id), true);
 	}
 	/* Falling back doesn't make sense if ID data was read
 	 * successfully at least once.
 	 */
 	may_fallback = 0;
 	swap_buf_le16(id, ATA_ID_WORDS);
 	/* sanity check */
 	rc = -EINVAL;
 	reason = "device reports invalid type";
 	if (class == ATA_DEV_ATA) {
 		if (!ata_id_is_ata(id) && !ata_id_is_cfa(id))
 			goto err_out;
 	} else {
 		if (ata_id_is_ata(id))
 			goto err_out;
 	}
 	if (!tried_spinup && (id[2] == 0x37c8 || id[2] == 0x738c)) {
 		tried_spinup = 1;
 		/*
 		 * Drive powered-up in standby mode, and requires a specific
 		 * SET_FEATURES spin-up subcommand before it will accept
 		 * anything other than the original IDENTIFY command.
 		 */
 		err_mask = ata_dev_set_feature(dev, SETFEATURES_SPINUP, 0);
 		if (err_mask && id[2] != 0x738c) {
 			rc = -EIO;
 			reason = "SPINUP failed";
 			goto err_out;
 		}
 		/*
 		 * If the drive initially returned incomplete IDENTIFY info,
 		 * we now must reissue the IDENTIFY command.
 		 */
 		if (id[2] == 0x37c8)
 			goto retry;
 	}
 	if ((flags & ATA_READID_POSTRESET) && class == ATA_DEV_ATA) {
 		/*
 		 * The exact sequence expected by certain pre-ATA4 drives is:
 		 * SRST RESET
 		 * IDENTIFY (optional in early ATA)
 		 * INITIALIZE DEVICE PARAMETERS (later IDE and ATA)
 		 * anything else..
 		 * Some drives were very specific about that exact sequence.
 		 *
 		 * Note that ATA4 says lba is mandatory so the second check
 		 * should never trigger.
 		 */
 		if (ata_id_major_version(id) < 4 || !ata_id_has_lba(id)) {
 			err_mask = ata_dev_init_params(dev, id[3], id[6]);
 			if (err_mask) {
 				rc = -EIO;
 				reason = "INIT_DEV_PARAMS failed";
 				goto err_out;
 			}
 			/* current CHS translation info (id[53-58]) might be
 			 * changed. reread the identify device info.
 			 */
 			flags &= ~ATA_READID_POSTRESET;
 			goto retry;
 		}
 	}
 	*p_class = class;
 	return 0;
  err_out:
 	if (ata_msg_warn(ap))
 		ata_dev_printk(dev, KERN_WARNING, "failed to IDENTIFY "
 			       "(%s, err_mask=0x%x)\n", reason, err_mask);
 	return rc;
 }
 static int ata_do_link_spd_horkage(struct ata_device *dev)
 {
 	struct ata_link *plink = ata_dev_phys_link(dev);
 	u32 target, target_limit;
 	if (!sata_scr_valid(plink))
 		return 0;
 	if (dev->horkage & ATA_HORKAGE_1_5_GBPS)
 		target = 1;
 	else
 		return 0;
 	target_limit = (1 << target) - 1;
 	/* if already on stricter limit, no need to push further */
 	if (plink->sata_spd_limit <= target_limit)
 		return 0;
 	plink->sata_spd_limit = target_limit;
 	/* Request another EH round by returning -EAGAIN if link is
 	 * going faster than the target speed.  Forward progress is
 	 * guaranteed by setting sata_spd_limit to target_limit above.
 	 */
 	if (plink->sata_spd > target) {
 		ata_dev_printk(dev, KERN_INFO,
 			       "applying link speed limit horkage to %s\n",
 			       sata_spd_string(target));
 		return -EAGAIN;
 	}
 	return 0;
 }
 static inline u8 ata_dev_knobble(struct ata_device *dev)
 {
 	struct ata_port *ap = dev->link->ap;
 	if (ata_dev_blacklisted(dev) & ATA_HORKAGE_BRIDGE_OK)
 		return 0;
 	return ((ap->cbl == ATA_CBL_SATA) && (!ata_id_is_sata(dev->id)));
 }
 static int ata_dev_config_ncq(struct ata_device *dev,
 			       char *desc, size_t desc_sz)
 {
 	struct ata_port *ap = dev->link->ap;
 	int hdepth = 0, ddepth = ata_id_queue_depth(dev->id);
 	unsigned int err_mask;
 	char *aa_desc = "";
 	if (!ata_id_has_ncq(dev->id)) {
 		desc[0] = '\0';
 		return 0;
 	}
 	if (dev->horkage & ATA_HORKAGE_NONCQ) {
 		snprintf(desc, desc_sz, "NCQ (not used)");
 		return 0;
 	}
 	if (ap->flags & ATA_FLAG_NCQ) {
 		hdepth = min(ap->scsi_host->can_queue, ATA_MAX_QUEUE - 1);
 		dev->flags |= ATA_DFLAG_NCQ;
 	}
 	if (!(dev->horkage & ATA_HORKAGE_BROKEN_FPDMA_AA) &&
 		(ap->flags & ATA_FLAG_FPDMA_AA) &&
 		ata_id_has_fpdma_aa(dev->id)) {
 		err_mask = ata_dev_set_feature(dev, SETFEATURES_SATA_ENABLE,
 			SATA_FPDMA_AA);
 		if (err_mask) {
 			ata_dev_printk(dev, KERN_ERR, "failed to enable AA"
 				"(error_mask=0x%x)\n", err_mask);
 			if (err_mask != AC_ERR_DEV) {
 				dev->horkage |= ATA_HORKAGE_BROKEN_FPDMA_AA;
 				return -EIO;
 			}
 		} else
 			aa_desc = ", AA";
 	}
 	if (hdepth >= ddepth)
 		snprintf(desc, desc_sz, "NCQ (depth %d)%s", ddepth, aa_desc);
 	else
 		snprintf(desc, desc_sz, "NCQ (depth %d/%d)%s", hdepth,
 			ddepth, aa_desc);
 	return 0;
 }
 /**
  *	ata_dev_configure - Configure the specified ATA/ATAPI device
  *	@dev: Target device to configure
  *
  *	Configure @dev according to @dev->id.  Generic and low-level
  *	driver specific fixups are also applied.
  *
  *	LOCKING:
  *	Kernel thread context (may sleep)
  *
  *	RETURNS:
  *	0 on success, -errno otherwise
  */
 int ata_dev_configure(struct ata_device *dev)
 {
 	struct ata_port *ap = dev->link->ap;
 	struct ata_eh_context *ehc = &dev->link->eh_context;
 	int print_info = ehc->i.flags & ATA_EHI_PRINTINFO;
 	const u16 *id = dev->id;
 	unsigned long xfer_mask;
 	char revbuf[7];		/* XYZ-99\0 */
 	char fwrevbuf[ATA_ID_FW_REV_LEN+1];
 	char modelbuf[ATA_ID_PROD_LEN+1];
 	int rc;
 	if (!ata_dev_enabled(dev) && ata_msg_info(ap)) {
 		ata_dev_printk(dev, KERN_INFO, "%s: ENTER/EXIT -- nodev\n",
 			       __func__);
 		return 0;
 	}
 	if (ata_msg_probe(ap))
 		ata_dev_printk(dev, KERN_DEBUG, "%s: ENTER\n", __func__);
 	/* set horkage */
 	dev->horkage |= ata_dev_blacklisted(dev);
 	ata_force_horkage(dev);
 	if (dev->horkage & ATA_HORKAGE_DISABLE) {
 		ata_dev_printk(dev, KERN_INFO,
 			       "unsupported device, disabling\n");
 		ata_dev_disable(dev);
 		return 0;
 	}
 	if ((!atapi_enabled || (ap->flags & ATA_FLAG_NO_ATAPI)) &&
 	    dev->class == ATA_DEV_ATAPI) {
 		ata_dev_printk(dev, KERN_WARNING,
 			"WARNING: ATAPI is %s, device ignored.\n",
 			atapi_enabled ? "not supported with this driver"
 				      : "disabled");
 		ata_dev_disable(dev);
 		return 0;
 	}
 	rc = ata_do_link_spd_horkage(dev);
 	if (rc)
 		return rc;
 	/* let ACPI work its magic */
 	rc = ata_acpi_on_devcfg(dev);
 	if (rc)
 		return rc;
 	/* massage HPA, do it early as it might change IDENTIFY data */
 	rc = ata_hpa_resize(dev);
 	if (rc)
 		return rc;
 	/* print device capabilities */
 	if (ata_msg_probe(ap))
 		ata_dev_printk(dev, KERN_DEBUG,
 			       "%s: cfg 49:%04x 82:%04x 83:%04x 84:%04x "
 			       "85:%04x 86:%04x 87:%04x 88:%04x\n",
 			       __func__,
 			       id[49], id[82], id[83], id[84],
 			       id[85], id[86], id[87], id[88]);
 	/* initialize to-be-configured parameters */
 	dev->flags &= ~ATA_DFLAG_CFG_MASK;
 	dev->max_sectors = 0;
 	dev->cdb_len = 0;
 	dev->n_sectors = 0;
 	dev->cylinders = 0;
 	dev->heads = 0;
 	dev->sectors = 0;
 	dev->multi_count = 0;
 	/*
 	 * common ATA, ATAPI feature tests
 	 */
 	/* find max transfer mode; for printk only */
 	xfer_mask = ata_id_xfermask(id);
 	if (ata_msg_probe(ap))
 		ata_dump_id(id);
 	/* SCSI only uses 4-char revisions, dump full 8 chars from ATA */
 	ata_id_c_string(dev->id, fwrevbuf, ATA_ID_FW_REV,
 			sizeof(fwrevbuf));
 	ata_id_c_string(dev->id, modelbuf, ATA_ID_PROD,
 			sizeof(modelbuf));
 	/* ATA-specific feature tests */
 	if (dev->class == ATA_DEV_ATA) {
 		if (ata_id_is_cfa(id)) {
 			/* CPRM may make this media unusable */
 			if (id[ATA_ID_CFA_KEY_MGMT] & 1)
 				ata_dev_printk(dev, KERN_WARNING,
 					       "supports DRM functions and may "
 					       "not be fully accessable.\n");
 			snprintf(revbuf, 7, "CFA");
 		} else {
 			snprintf(revbuf, 7, "ATA-%d", ata_id_major_version(id));
 			/* Warn the user if the device has TPM extensions */
 			if (ata_id_has_tpm(id))
 				ata_dev_printk(dev, KERN_WARNING,
 					       "supports DRM functions and may "
 					       "not be fully accessable.\n");
 		}
 		dev->n_sectors = ata_id_n_sectors(id);
 		/* get current R/W Multiple count setting */
 		if ((dev->id[47] >> 8) == 0x80 && (dev->id[59] & 0x100)) {
 			unsigned int max = dev->id[47] & 0xff;
 			unsigned int cnt = dev->id[59] & 0xff;
 			/* only recognize/allow powers of two here */
 			if (is_power_of_2(max) && is_power_of_2(cnt))
 				if (cnt <= max)
 					dev->multi_count = cnt;
 		}
 		if (ata_id_has_lba(id)) {
 			const char *lba_desc;
 			char ncq_desc[24];
 			lba_desc = "LBA";
 			dev->flags |= ATA_DFLAG_LBA;
 			if (ata_id_has_lba48(id)) {
 				dev->flags |= ATA_DFLAG_LBA48;
 				lba_desc = "LBA48";
 				if (dev->n_sectors >= (1UL << 28) &&
 				    ata_id_has_flush_ext(id))
 					dev->flags |= ATA_DFLAG_FLUSH_EXT;
 			}
 			/* config NCQ */
 			rc = ata_dev_config_ncq(dev, ncq_desc, sizeof(ncq_desc));
 			if (rc)
 				return rc;
 			/* print device info to dmesg */
 			if (ata_msg_drv(ap) && print_info) {
 				ata_dev_printk(dev, KERN_INFO,
 					"%s: %s, %s, max %s\n",
 					revbuf, modelbuf, fwrevbuf,
 					ata_mode_string(xfer_mask));
 				ata_dev_printk(dev, KERN_INFO,
 					"%Lu sectors, multi %u: %s %s\n",
 					(unsigned long long)dev->n_sectors,
 					dev->multi_count, lba_desc, ncq_desc);
 			}
 		} else {
 			/* CHS */
 			/* Default translation */
 			dev->cylinders	= id[1];
 			dev->heads	= id[3];
 			dev->sectors	= id[6];
 			if (ata_id_current_chs_valid(id)) {
 				/* Current CHS translation is valid. */
 				dev->cylinders = id[54];
 				dev->heads     = id[55];
 				dev->sectors   = id[56];
 			}
 			/* print device info to dmesg */
 			if (ata_msg_drv(ap) && print_info) {
 				ata_dev_printk(dev, KERN_INFO,
 					"%s: %s, %s, max %s\n",
 					revbuf,	modelbuf, fwrevbuf,
 					ata_mode_string(xfer_mask));
 				ata_dev_printk(dev, KERN_INFO,
 					"%Lu sectors, multi %u, CHS %u/%u/%u\n",
 					(unsigned long long)dev->n_sectors,
 					dev->multi_count, dev->cylinders,
 					dev->heads, dev->sectors);
 			}
 		}
 		dev->cdb_len = 16;
 	}
 	/* ATAPI-specific feature tests */
 	else if (dev->class == ATA_DEV_ATAPI) {
 		const char *cdb_intr_string = "";
 		const char *atapi_an_string = "";
 		const char *dma_dir_string = "";
 		u32 sntf;
 		rc = atapi_cdb_len(id);
 		if ((rc < 12) || (rc > ATAPI_CDB_LEN)) {
 			if (ata_msg_warn(ap))
 				ata_dev_printk(dev, KERN_WARNING,
 					       "unsupported CDB len\n");
 			rc = -EINVAL;
 			goto err_out_nosup;
 		}
 		dev->cdb_len = (unsigned int) rc;
 		/* Enable ATAPI AN if both the host and device have
 		 * the support.  If PMP is attached, SNTF is required
 		 * to enable ATAPI AN to discern between PHY status
 		 * changed notifications and ATAPI ANs.
 		 */
 		if (atapi_an &&
 		    (ap->flags & ATA_FLAG_AN) && ata_id_has_atapi_AN(id) &&
 		    (!sata_pmp_attached(ap) ||
 		     sata_scr_read(&ap->link, SCR_NOTIFICATION, &sntf) == 0)) {
 			unsigned int err_mask;
 			/* issue SET feature command to turn this on */
 			err_mask = ata_dev_set_feature(dev,
 					SETFEATURES_SATA_ENABLE, SATA_AN);
 			if (err_mask)
 				ata_dev_printk(dev, KERN_ERR,
 					"failed to enable ATAPI AN "
 					"(err_mask=0x%x)\n", err_mask);
 			else {
 				dev->flags |= ATA_DFLAG_AN;
 				atapi_an_string = ", ATAPI AN";
 			}
 		}
 		if (ata_id_cdb_intr(dev->id)) {
 			dev->flags |= ATA_DFLAG_CDB_INTR;
 			cdb_intr_string = ", CDB intr";
 		}
 		if (atapi_dmadir || atapi_id_dmadir(dev->id)) {
 			dev->flags |= ATA_DFLAG_DMADIR;
 			dma_dir_string = ", DMADIR";
 		}
 		/* print device info to dmesg */
 		if (ata_msg_drv(ap) && print_info)
 			ata_dev_printk(dev, KERN_INFO,
 				       "ATAPI: %s, %s, max %s%s%s%s\n",
 				       modelbuf, fwrevbuf,
 				       ata_mode_string(xfer_mask),
 				       cdb_intr_string, atapi_an_string,
 				       dma_dir_string);
 	}
 	/* determine max_sectors */
 	dev->max_sectors = ATA_MAX_SECTORS;
 	if (dev->flags & ATA_DFLAG_LBA48)
 		dev->max_sectors = ATA_MAX_SECTORS_LBA48;
 	if (!(dev->horkage & ATA_HORKAGE_IPM)) {
 		if (ata_id_has_hipm(dev->id))
 			dev->flags |= ATA_DFLAG_HIPM;
 		if (ata_id_has_dipm(dev->id))
 			dev->flags |= ATA_DFLAG_DIPM;
 	}
 	/* Limit PATA drive on SATA cable bridge transfers to udma5,
 	   200 sectors */
 	if (ata_dev_knobble(dev)) {
 		if (ata_msg_drv(ap) && print_info)
 			ata_dev_printk(dev, KERN_INFO,
 				       "applying bridge limits\n");
 		dev->udma_mask &= ATA_UDMA5;
 		dev->max_sectors = ATA_MAX_SECTORS;
 	}
 	if ((dev->class == ATA_DEV_ATAPI) &&
 	    (atapi_command_packet_set(id) == TYPE_TAPE)) {
 		dev->max_sectors = ATA_MAX_SECTORS_TAPE;
 		dev->horkage |= ATA_HORKAGE_STUCK_ERR;
 	}
 	if (dev->horkage & ATA_HORKAGE_MAX_SEC_128)
 		dev->max_sectors = min_t(unsigned int, ATA_MAX_SECTORS_128,
 					 dev->max_sectors);
 	if (ata_dev_blacklisted(dev) & ATA_HORKAGE_IPM) {
 		dev->horkage |= ATA_HORKAGE_IPM;
 		/* reset link pm_policy for this port to no pm */
 		ap->pm_policy = MAX_PERFORMANCE;
 	}
 	if (ap->ops->dev_config)
 		ap->ops->dev_config(dev);
 	if (dev->horkage & ATA_HORKAGE_DIAGNOSTIC) {
 		/* Let the user know. We don't want to disallow opens for
 		   rescue purposes, or in case the vendor is just a blithering
 		   idiot. Do this after the dev_config call as some controllers
 		   with buggy firmware may want to avoid reporting false device
 		   bugs */
 		if (print_info) {
 			ata_dev_printk(dev, KERN_WARNING,
 "Drive reports diagnostics failure. This may indicate a drive\n");
 			ata_dev_printk(dev, KERN_WARNING,
 "fault or invalid emulation. Contact drive vendor for information.\n");
 		}
 	}
 	if ((dev->horkage & ATA_HORKAGE_FIRMWARE_WARN) && print_info) {
 		ata_dev_printk(dev, KERN_WARNING, "WARNING: device requires "
 			       "firmware update to be fully functional.\n");
 		ata_dev_printk(dev, KERN_WARNING, "         contact the vendor "
 			       "or visit http://ata.wiki.kernel.org.\n");
 	}
 	return 0;
 err_out_nosup:
 	if (ata_msg_probe(ap))
 		ata_dev_printk(dev, KERN_DEBUG,
 			       "%s: EXIT, err\n", __func__);
 	return rc;
 }
 /**
  *	ata_cable_40wire	-	return 40 wire cable type
  *	@ap: port
  *
  *	Helper method for drivers which want to hardwire 40 wire cable
  *	detection.
  */
 int ata_cable_40wire(struct ata_port *ap)
 {
 	return ATA_CBL_PATA40;
 }
 /**
  *	ata_cable_80wire	-	return 80 wire cable type
  *	@ap: port
  *
  *	Helper method for drivers which want to hardwire 80 wire cable
  *	detection.
  */
 int ata_cable_80wire(struct ata_port *ap)
 {
 	return ATA_CBL_PATA80;
 }
 /**
  *	ata_cable_unknown	-	return unknown PATA cable.
  *	@ap: port
  *
  *	Helper method for drivers which have no PATA cable detection.
  */
 int ata_cable_unknown(struct ata_port *ap)
 {
 	return ATA_CBL_PATA_UNK;
 }
 /**
  *	ata_cable_ignore	-	return ignored PATA cable.
  *	@ap: port
  *
  *	Helper method for drivers which don't use cable type to limit
  *	transfer mode.
  */
 int ata_cable_ignore(struct ata_port *ap)
 {
 	return ATA_CBL_PATA_IGN;
 }
 /**
  *	ata_cable_sata	-	return SATA cable type
  *	@ap: port
  *
  *	Helper method for drivers which have SATA cables
  */
 int ata_cable_sata(struct ata_port *ap)
 {
 	return ATA_CBL_SATA;
 }
 /**
  *	ata_bus_probe - Reset and probe ATA bus
  *	@ap: Bus to probe
  *
  *	Master ATA bus probing function.  Initiates a hardware-dependent
  *	bus reset, then attempts to identify any devices found on
  *	the bus.
  *
  *	LOCKING:
  *	PCI/etc. bus probe sem.
  *
  *	RETURNS:
  *	Zero on success, negative errno otherwise.
  */
 int ata_bus_probe(struct ata_port *ap)
 {
 	unsigned int classes[ATA_MAX_DEVICES];
 	int tries[ATA_MAX_DEVICES];
 	int rc;
 	struct ata_device *dev;
 	ata_for_each_dev(dev, &ap->link, ALL)
 		tries[dev->devno] = ATA_PROBE_MAX_TRIES;
  retry:
 	ata_for_each_dev(dev, &ap->link, ALL) {
 		/* If we issue an SRST then an ATA drive (not ATAPI)
 		 * may change configuration and be in PIO0 timing. If
 		 * we do a hard reset (or are coming from power on)
 		 * this is true for ATA or ATAPI. Until we've set a
 		 * suitable controller mode we should not touch the
 		 * bus as we may be talking too fast.
 		 */
 		dev->pio_mode = XFER_PIO_0;
 		/* If the controller has a pio mode setup function
 		 * then use it to set the chipset to rights. Don't
 		 * touch the DMA setup as that will be dealt with when
 		 * configuring devices.
 		 */
 		if (ap->ops->set_piomode)
 			ap->ops->set_piomode(ap, dev);
 	}
 	/* reset and determine device classes */
 	ap->ops->phy_reset(ap);
 	ata_for_each_dev(dev, &ap->link, ALL) {
 		if (dev->class != ATA_DEV_UNKNOWN)
 			classes[dev->devno] = dev->class;
 		else
 			classes[dev->devno] = ATA_DEV_NONE;
 		dev->class = ATA_DEV_UNKNOWN;
 	}
 	/* read IDENTIFY page and configure devices. We have to do the identify
 	   specific sequence bass-ackwards so that PDIAG- is released by
 	   the slave device */
 	ata_for_each_dev(dev, &ap->link, ALL_REVERSE) {
 		if (tries[dev->devno])
 			dev->class = classes[dev->devno];
 		if (!ata_dev_enabled(dev))
 			continue;
 		rc = ata_dev_read_id(dev, &dev->class, ATA_READID_POSTRESET,
 				     dev->id);
 		if (rc)
 			goto fail;
 	}
 	/* Now ask for the cable type as PDIAG- should have been released */
 	if (ap->ops->cable_detect)
 		ap->cbl = ap->ops->cable_detect(ap);
 	/* We may have SATA bridge glue hiding here irrespective of
 	 * the reported cable types and sensed types.  When SATA
 	 * drives indicate we have a bridge, we don't know which end
 	 * of the link the bridge is which is a problem.
 	 */
 	ata_for_each_dev(dev, &ap->link, ENABLED)
 		if (ata_id_is_sata(dev->id))
 			ap->cbl = ATA_CBL_SATA;
 	/* After the identify sequence we can now set up the devices. We do
 	   this in the normal order so that the user doesn't get confused */
 	ata_for_each_dev(dev, &ap->link, ENABLED) {
 		ap->link.eh_context.i.flags |= ATA_EHI_PRINTINFO;
 		rc = ata_dev_configure(dev);
 		ap->link.eh_context.i.flags &= ~ATA_EHI_PRINTINFO;
 		if (rc)
 			goto fail;
 	}
 	/* configure transfer mode */
 	rc = ata_set_mode(&ap->link, &dev);
 	if (rc)
 		goto fail;
 	ata_for_each_dev(dev, &ap->link, ENABLED)
 		return 0;
 	return -ENODEV;
  fail:
 	tries[dev->devno]--;
 	switch (rc) {
 	case -EINVAL:
 		/* eeek, something went very wrong, give up */
 		tries[dev->devno] = 0;
 		break;
 	case -ENODEV:
 		/* give it just one more chance */
 		tries[dev->devno] = min(tries[dev->devno], 1);
 	case -EIO:
 		if (tries[dev->devno] == 1) {
 			/* This is the last chance, better to slow
 			 * down than lose it.
 			 */
 			sata_down_spd_limit(&ap->link, 0);
 			ata_down_xfermask_limit(dev, ATA_DNXFER_PIO);
 		}
 	}
 	if (!tries[dev->devno])
 		ata_dev_disable(dev);
 	goto retry;
 }
 /**
  *	sata_print_link_status - Print SATA link status
  *	@link: SATA link to printk link status about
  *
  *	This function prints link speed and status of a SATA link.
  *
  *	LOCKING:
  *	None.
  */
 static void sata_print_link_status(struct ata_link *link)
 {
 	u32 sstatus, scontrol, tmp;
 	if (sata_scr_read(link, SCR_STATUS, &sstatus))
 		return;
 	sata_scr_read(link, SCR_CONTROL, &scontrol);
 	if (ata_phys_link_online(link)) {
 		tmp = (sstatus >> 4) & 0xf;
 		ata_link_printk(link, KERN_INFO,
 				"SATA link up %s (SStatus %X SControl %X)\n",
 				sata_spd_string(tmp), sstatus, scontrol);
 	} else {
 		ata_link_printk(link, KERN_INFO,
 				"SATA link down (SStatus %X SControl %X)\n",
 				sstatus, scontrol);
 	}
 }
 /**
  *	ata_dev_pair		-	return other device on cable
  *	@adev: device
  *
  *	Obtain the other device on the same cable, or if none is
  *	present NULL is returned
  */
 struct ata_device *ata_dev_pair(struct ata_device *adev)
 {
 	struct ata_link *link = adev->link;
 	struct ata_device *pair = &link->device[1 - adev->devno];
 	if (!ata_dev_enabled(pair))
 		return NULL;
 	return pair;
 }
 /**
  *	sata_down_spd_limit - adjust SATA spd limit downward
  *	@link: Link to adjust SATA spd limit for
  *	@spd_limit: Additional limit
  *
  *	Adjust SATA spd limit of @link downward.  Note that this
  *	function only adjusts the limit.  The change must be applied
  *	using sata_set_spd().
  *
  *	If @spd_limit is non-zero, the speed is limited to equal to or
  *	lower than @spd_limit if such speed is supported.  If
  *	@spd_limit is slower than any supported speed, only the lowest
  *	supported speed is allowed.
  *
  *	LOCKING:
  *	Inherited from caller.
  *
  *	RETURNS:
  *	0 on success, negative errno on failure
  */
 int sata_down_spd_limit(struct ata_link *link, u32 spd_limit)
 {
 	u32 sstatus, spd, mask;
 	int rc, bit;
 	if (!sata_scr_valid(link))
 		return -EOPNOTSUPP;
 	/* If SCR can be read, use it to determine the current SPD.
 	 * If not, use cached value in link->sata_spd.
 	 */
 	rc = sata_scr_read(link, SCR_STATUS, &sstatus);
 	if (rc == 0 && ata_sstatus_online(sstatus))
 		spd = (sstatus >> 4) & 0xf;
 	else
 		spd = link->sata_spd;
 	mask = link->sata_spd_limit;
 	if (mask <= 1)
 		return -EINVAL;
 	/* unconditionally mask off the highest bit */
 	bit = fls(mask) - 1;
 	mask &= ~(1 << bit);
 	/* Mask off all speeds higher than or equal to the current
 	 * one.  Force 1.5Gbps if current SPD is not available.
 	 */
 	if (spd > 1)
 		mask &= (1 << (spd - 1)) - 1;
 	else
 		mask &= 1;
 	/* were we already at the bottom? */
 	if (!mask)
 		return -EINVAL;
 	if (spd_limit) {
 		if (mask & ((1 << spd_limit) - 1))
 			mask &= (1 << spd_limit) - 1;
 		else {
 			bit = ffs(mask) - 1;
 			mask = 1 << bit;
 		}
 	}
 	link->sata_spd_limit = mask;
 	ata_link_printk(link, KERN_WARNING, "limiting SATA link speed to %s\n",
 			sata_spd_string(fls(mask)));
 	return 0;
 }
 static int __sata_set_spd_needed(struct ata_link *link, u32 *scontrol)
 {
 	struct ata_link *host_link = &link->ap->link;
 	u32 limit, target, spd;
 	limit = link->sata_spd_limit;
 	/* Don't configure downstream link faster than upstream link.
 	 * It doesn't speed up anything and some PMPs choke on such
 	 * configuration.
 	 */
 	if (!ata_is_host_link(link) && host_link->sata_spd)
 		limit &= (1 << host_link->sata_spd) - 1;
 	if (limit == UINT_MAX)
 		target = 0;
 	else
 		target = fls(limit);
 	spd = (*scontrol >> 4) & 0xf;
 	*scontrol = (*scontrol & ~0xf0) | ((target & 0xf) << 4);
 	return spd != target;
 }
 /**
  *	sata_set_spd_needed - is SATA spd configuration needed
  *	@link: Link in question
  *
  *	Test whether the spd limit in SControl matches
  *	@link->sata_spd_limit.  This function is used to determine
  *	whether hardreset is necessary to apply SATA spd
  *	configuration.
  *
  *	LOCKING:
  *	Inherited from caller.
  *
  *	RETURNS:
  *	1 if SATA spd configuration is needed, 0 otherwise.
  */
 static int sata_set_spd_needed(struct ata_link *link)
 {
 	u32 scontrol;
 	if (sata_scr_read(link, SCR_CONTROL, &scontrol))
 		return 1;
 	return __sata_set_spd_needed(link, &scontrol);
 }
 /**
  *	sata_set_spd - set SATA spd according to spd limit
  *	@link: Link to set SATA spd for
  *
  *	Set SATA spd of @link according to sata_spd_limit.
  *
  *	LOCKING:
  *	Inherited from caller.
  *
  *	RETURNS:
  *	0 if spd doesn't need to be changed, 1 if spd has been
  *	changed.  Negative errno if SCR registers are inaccessible.
  */
 int sata_set_spd(struct ata_link *link)
 {
 	u32 scontrol;
 	int rc;
 	if ((rc = sata_scr_read(link, SCR_CONTROL, &scontrol)))
 		return rc;
 	if (!__sata_set_spd_needed(link, &scontrol))
 		return 0;
 	if ((rc = sata_scr_write(link, SCR_CONTROL, scontrol)))
 		return rc;
 	return 1;
 }
 /*
  * This mode timing computation functionality is ported over from
  * drivers/ide/ide-timing.h and was originally written by Vojtech Pavlik
  */
 /*
  * PIO 0-4, MWDMA 0-2 and UDMA 0-6 timings (in nanoseconds).
  * These were taken from ATA/ATAPI-6 standard, rev 0a, except
  * for UDMA6, which is currently supported only by Maxtor drives.
  *
  * For PIO 5/6 MWDMA 3/4 see the CFA specification 3.0.
  */
 static const struct ata_timing ata_timing[] = {
 /*	{ XFER_PIO_SLOW, 120, 290, 240, 960, 290, 240, 0,  960,   0 }, */
 	{ XFER_PIO_0,     70, 290, 240, 600, 165, 150, 0,  600,   0 },
 	{ XFER_PIO_1,     50, 290,  93, 383, 125, 100, 0,  383,   0 },
 	{ XFER_PIO_2,     30, 290,  40, 330, 100,  90, 0,  240,   0 },
 	{ XFER_PIO_3,     30,  80,  70, 180,  80,  70, 0,  180,   0 },
 	{ XFER_PIO_4,     25,  70,  25, 120,  70,  25, 0,  120,   0 },
 	{ XFER_PIO_5,     15,  65,  25, 100,  65,  25, 0,  100,   0 },
 	{ XFER_PIO_6,     10,  55,  20,  80,  55,  20, 0,   80,   0 },
 	{ XFER_SW_DMA_0, 120,   0,   0,   0, 480, 480, 50, 960,   0 },
 	{ XFER_SW_DMA_1,  90,   0,   0,   0, 240, 240, 30, 480,   0 },
 	{ XFER_SW_DMA_2,  60,   0,   0,   0, 120, 120, 20, 240,   0 },
 	{ XFER_MW_DMA_0,  60,   0,   0,   0, 215, 215, 20, 480,   0 },
 	{ XFER_MW_DMA_1,  45,   0,   0,   0,  80,  50, 5,  150,   0 },
 	{ XFER_MW_DMA_2,  25,   0,   0,   0,  70,  25, 5,  120,   0 },
 	{ XFER_MW_DMA_3,  25,   0,   0,   0,  65,  25, 5,  100,   0 },
 	{ XFER_MW_DMA_4,  25,   0,   0,   0,  55,  20, 5,   80,   0 },
 /*	{ XFER_UDMA_SLOW,  0,   0,   0,   0,   0,   0, 0,    0, 150 }, */
 	{ XFER_UDMA_0,     0,   0,   0,   0,   0,   0, 0,    0, 120 },
 	{ XFER_UDMA_1,     0,   0,   0,   0,   0,   0, 0,    0,  80 },
 	{ XFER_UDMA_2,     0,   0,   0,   0,   0,   0, 0,    0,  60 },
 	{ XFER_UDMA_3,     0,   0,   0,   0,   0,   0, 0,    0,  45 },
 	{ XFER_UDMA_4,     0,   0,   0,   0,   0,   0, 0,    0,  30 },
 	{ XFER_UDMA_5,     0,   0,   0,   0,   0,   0, 0,    0,  20 },
 	{ XFER_UDMA_6,     0,   0,   0,   0,   0,   0, 0,    0,  15 },
 	{ 0xFF }
 };
 #define ENOUGH(v, unit)		(((v)-1)/(unit)+1)
 #define EZ(v, unit)		((v)?ENOUGH(v, unit):0)
 static void ata_timing_quantize(const struct ata_timing *t, struct ata_timing *q, int T, int UT)
 {
 	q->setup	= EZ(t->setup      * 1000,  T);
 	q->act8b	= EZ(t->act8b      * 1000,  T);
 	q->rec8b	= EZ(t->rec8b      * 1000,  T);
 	q->cyc8b	= EZ(t->cyc8b      * 1000,  T);
 	q->active	= EZ(t->active     * 1000,  T);
 	q->recover	= EZ(t->recover    * 1000,  T);
 	q->dmack_hold	= EZ(t->dmack_hold * 1000,  T);
 	q->cycle	= EZ(t->cycle      * 1000,  T);
 	q->udma		= EZ(t->udma       * 1000, UT);
 }
 void ata_timing_merge(const struct ata_timing *a, const struct ata_timing *b,
 		      struct ata_timing *m, unsigned int what)
 {
 	if (what & ATA_TIMING_SETUP  ) m->setup   = max(a->setup,   b->setup);
 	if (what & ATA_TIMING_ACT8B  ) m->act8b   = max(a->act8b,   b->act8b);
 	if (what & ATA_TIMING_REC8B  ) m->rec8b   = max(a->rec8b,   b->rec8b);
 	if (what & ATA_TIMING_CYC8B  ) m->cyc8b   = max(a->cyc8b,   b->cyc8b);
 	if (what & ATA_TIMING_ACTIVE ) m->active  = max(a->active,  b->active);
 	if (what & ATA_TIMING_RECOVER) m->recover = max(a->recover, b->recover);
 	if (what & ATA_TIMING_DMACK_HOLD) m->dmack_hold = max(a->dmack_hold, b->dmack_hold);
 	if (what & ATA_TIMING_CYCLE  ) m->cycle   = max(a->cycle,   b->cycle);
 	if (what & ATA_TIMING_UDMA   ) m->udma    = max(a->udma,    b->udma);
 }
 const struct ata_timing *ata_timing_find_mode(u8 xfer_mode)
 {
 	const struct ata_timing *t = ata_timing;
 	while (xfer_mode > t->mode)
 		t++;
 	if (xfer_mode == t->mode)
 		return t;
 	return NULL;
 }
 int ata_timing_compute(struct ata_device *adev, unsigned short speed,
 		       struct ata_timing *t, int T, int UT)
 {
 	const u16 *id = adev->id;
 	const struct ata_timing *s;
 	struct ata_timing p;
 	/*
 	 * Find the mode.
 	 */
 	if (!(s = ata_timing_find_mode(speed)))
 		return -EINVAL;
 	memcpy(t, s, sizeof(*s));
 	/*
 	 * If the drive is an EIDE drive, it can tell us it needs extended
 	 * PIO/MW_DMA cycle timing.
 	 */
 	if (id[ATA_ID_FIELD_VALID] & 2) {	/* EIDE drive */
 		memset(&p, 0, sizeof(p));
 		if (speed >= XFER_PIO_0 && speed <= XFER_SW_DMA_0) {
 			if (speed <= XFER_PIO_2)
 				p.cycle = p.cyc8b = id[ATA_ID_EIDE_PIO];
 			else if ((speed <= XFER_PIO_4) ||
 				 (speed == XFER_PIO_5 && !ata_id_is_cfa(id)))
 				p.cycle = p.cyc8b = id[ATA_ID_EIDE_PIO_IORDY];
 		} else if (speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2)
 			p.cycle = id[ATA_ID_EIDE_DMA_MIN];
 		ata_timing_merge(&p, t, t, ATA_TIMING_CYCLE | ATA_TIMING_CYC8B);
 	}
 	/*
 	 * Convert the timing to bus clock counts.
 	 */
 	ata_timing_quantize(t, t, T, UT);
 	/*
 	 * Even in DMA/UDMA modes we still use PIO access for IDENTIFY,
 	 * S.M.A.R.T * and some other commands. We have to ensure that the
 	 * DMA cycle timing is slower/equal than the fastest PIO timing.
 	 */
 	if (speed > XFER_PIO_6) {
 		ata_timing_compute(adev, adev->pio_mode, &p, T, UT);
 		ata_timing_merge(&p, t, t, ATA_TIMING_ALL);
 	}
 	/*
 	 * Lengthen active & recovery time so that cycle time is correct.
 	 */
 	if (t->act8b + t->rec8b < t->cyc8b) {
 		t->act8b += (t->cyc8b - (t->act8b + t->rec8b)) / 2;
 		t->rec8b = t->cyc8b - t->act8b;
 	}
 	if (t->active + t->recover < t->cycle) {
 		t->active += (t->cycle - (t->active + t->recover)) / 2;
 		t->recover = t->cycle - t->active;
 	}
 	/* In a few cases quantisation may produce enough errors to
 	   leave t->cycle too low for the sum of active and recovery
 	   if so we must correct this */
 	if (t->active + t->recover > t->cycle)
 		t->cycle = t->active + t->recover;
 	return 0;
 }
 /**
  *	ata_timing_cycle2mode - find xfer mode for the specified cycle duration
  *	@xfer_shift: ATA_SHIFT_* value for transfer type to examine.
  *	@cycle: cycle duration in ns
  *
  *	Return matching xfer mode for @cycle.  The returned mode is of
  *	the transfer type specified by @xfer_shift.  If @cycle is too
  *	slow for @xfer_shift, 0xff is returned.  If @cycle is faster
  *	than the fastest known mode, the fasted mode is returned.
  *
  *	LOCKING:
  *	None.
  *
  *	RETURNS:
  *	Matching xfer_mode, 0xff if no match found.
  */
 u8 ata_timing_cycle2mode(unsigned int xfer_shift, int cycle)
 {
 	u8 base_mode = 0xff, last_mode = 0xff;
 	const struct ata_xfer_ent *ent;
 	const struct ata_timing *t;
 	for (ent = ata_xfer_tbl; ent->shift >= 0; ent++)
 		if (ent->shift == xfer_shift)
 			base_mode = ent->base;
 	for (t = ata_timing_find_mode(base_mode);
 	     t && ata_xfer_mode2shift(t->mode) == xfer_shift; t++) {
 		unsigned short this_cycle;
 		switch (xfer_shift) {
 		case ATA_SHIFT_PIO:
 		case ATA_SHIFT_MWDMA:
 			this_cycle = t->cycle;
 			break;
 		case ATA_SHIFT_UDMA:
 			this_cycle = t->udma;
 			break;
 		default:
 			return 0xff;
 		}
 		if (cycle > this_cycle)
 			break;
 		last_mode = t->mode;
 	}
 	return last_mode;
 }
 /**
  *	ata_down_xfermask_limit - adjust dev xfer masks downward
  *	@dev: Device to adjust xfer masks
  *	@sel: ATA_DNXFER_* selector
  *
  *	Adjust xfer masks of @dev downward.  Note that this function
  *	does not apply the change.  Invoking ata_set_mode() afterwards
  *	will apply the limit.
  *
  *	LOCKING:
  *	Inherited from caller.
  *
  *	RETURNS:
  *	0 on success, negative errno on failure
  */
 int ata_down_xfermask_limit(struct ata_device *dev, unsigned int sel)
 {
 	char buf[32];
 	unsigned long orig_mask, xfer_mask;
 	unsigned long pio_mask, mwdma_mask, udma_mask;
 	int quiet, highbit;
 	quiet = !!(sel & ATA_DNXFER_QUIET);
 	sel &= ~ATA_DNXFER_QUIET;
 	xfer_mask = orig_mask = ata_pack_xfermask(dev->pio_mask,
 						  dev->mwdma_mask,
 						  dev->udma_mask);
 	ata_unpack_xfermask(xfer_mask, &pio_mask, &mwdma_mask, &udma_mask);
 	switch (sel) {
 	case ATA_DNXFER_PIO:
 		highbit = fls(pio_mask) - 1;
 		pio_mask &= ~(1 << highbit);
 		break;
 	case ATA_DNXFER_DMA:
 		if (udma_mask) {
 			highbit = fls(udma_mask) - 1;
 			udma_mask &= ~(1 << highbit);
 			if (!udma_mask)
 				return -ENOENT;
 		} else if (mwdma_mask) {
 			highbit = fls(mwdma_mask) - 1;
 			mwdma_mask &= ~(1 << highbit);
 			if (!mwdma_mask)
 				return -ENOENT;
 		}
 		break;
 	case ATA_DNXFER_40C:
 		udma_mask &= ATA_UDMA_MASK_40C;
 		break;
 	case ATA_DNXFER_FORCE_PIO0:
 		pio_mask &= 1;
 	case ATA_DNXFER_FORCE_PIO:
 		mwdma_mask = 0;
 		udma_mask = 0;
 		break;
 	default:
 		BUG();
 	}
 	xfer_mask &= ata_pack_xfermask(pio_mask, mwdma_mask, udma_mask);
 	if (!(xfer_mask & ATA_MASK_PIO) || xfer_mask == orig_mask)
 		return -ENOENT;
 	if (!quiet) {
 		if (xfer_mask & (ATA_MASK_MWDMA | ATA_MASK_UDMA))
 			snprintf(buf, sizeof(buf), "%s:%s",
 				 ata_mode_string(xfer_mask),
 				 ata_mode_string(xfer_mask & ATA_MASK_PIO));
 		else
 			snprintf(buf, sizeof(buf), "%s",
 				 ata_mode_string(xfer_mask));
 		ata_dev_printk(dev, KERN_WARNING,
 			       "limiting speed to %s\n", buf);
 	}
 	ata_unpack_xfermask(xfer_mask, &dev->pio_mask, &dev->mwdma_mask,
 			    &dev->udma_mask);
 	return 0;
 }
 static int ata_dev_set_mode(struct ata_device *dev)
 {
 	struct ata_port *ap = dev->link->ap;
 	struct ata_eh_context *ehc = &dev->link->eh_context;
 	const bool nosetxfer = dev->horkage & ATA_HORKAGE_NOSETXFER;
 	const char *dev_err_whine = "";
 	int ign_dev_err = 0;
 	unsigned int err_mask = 0;
 	int rc;
 	dev->flags &= ~ATA_DFLAG_PIO;
 	if (dev->xfer_shift == ATA_SHIFT_PIO)
 		dev->flags |= ATA_DFLAG_PIO;
 	if (nosetxfer && ap->flags & ATA_FLAG_SATA && ata_id_is_sata(dev->id))
 		dev_err_whine = " (SET_XFERMODE skipped)";
 	else {
 		if (nosetxfer)
 			ata_dev_printk(dev, KERN_WARNING,
 				       "NOSETXFER but PATA detected - can't "
 				       "skip SETXFER, might malfunction\n");
 		err_mask = ata_dev_set_xfermode(dev);
 	}
 	if (err_mask & ~AC_ERR_DEV)
 		goto fail;
 	/* revalidate */
 	ehc->i.flags |= ATA_EHI_POST_SETMODE;
 	rc = ata_dev_revalidate(dev, ATA_DEV_UNKNOWN, 0);
 	ehc->i.flags &= ~ATA_EHI_POST_SETMODE;
 	if (rc)
 		return rc;
 	if (dev->xfer_shift == ATA_SHIFT_PIO) {
 		/* Old CFA may refuse this command, which is just fine */
 		if (ata_id_is_cfa(dev->id))
 			ign_dev_err = 1;
 		/* Catch several broken garbage emulations plus some pre
 		   ATA devices */
 		if (ata_id_major_version(dev->id) == 0 &&
 					dev->pio_mode <= XFER_PIO_2)
 			ign_dev_err = 1;
 		/* Some very old devices and some bad newer ones fail
 		   any kind of SET_XFERMODE request but support PIO0-2
 		   timings and no IORDY */
 		if (!ata_id_has_iordy(dev->id) && dev->pio_mode <= XFER_PIO_2)
 			ign_dev_err = 1;
 	}
 	/* Early MWDMA devices do DMA but don't allow DMA mode setting.
 	   Don't fail an MWDMA0 set IFF the device indicates it is in MWDMA0 */
 	if (dev->xfer_shift == ATA_SHIFT_MWDMA &&
 	    dev->dma_mode == XFER_MW_DMA_0 &&
 	    (dev->id[63] >> 8) & 1)
 		ign_dev_err = 1;
 	/* if the device is actually configured correctly, ignore dev err */
 	if (dev->xfer_mode == ata_xfer_mask2mode(ata_id_xfermask(dev->id)))
 		ign_dev_err = 1;
 	if (err_mask & AC_ERR_DEV) {
 		if (!ign_dev_err)
 			goto fail;
 		else
 			dev_err_whine = " (device error ignored)";
 	}
 	DPRINTK("xfer_shift=%u, xfer_mode=0x%x\n",
 		dev->xfer_shift, (int)dev->xfer_mode);
 	ata_dev_printk(dev, KERN_INFO, "configured for %s%s\n",
 		       ata_mode_string(ata_xfer_mode2mask(dev->xfer_mode)),
 		       dev_err_whine);
 	return 0;
  fail:
 	ata_dev_printk(dev, KERN_ERR, "failed to set xfermode "
 		       "(err_mask=0x%x)\n", err_mask);
 	return -EIO;
 }
 /**
  *	ata_do_set_mode - Program timings and issue SET FEATURES - XFER
  *	@link: link on which timings will be programmed
  *	@r_failed_dev: out parameter for failed device
  *
  *	Standard implementation of the function used to tune and set
  *	ATA device disk transfer mode (PIO3, UDMA6, etc.).  If
  *	ata_dev_set_mode() fails, pointer to the failing device is
  *	returned in @r_failed_dev.
  *
  *	LOCKING:
  *	PCI/etc. bus probe sem.
  *
  *	RETURNS:
  *	0 on success, negative errno otherwise
  */
 int ata_do_set_mode(struct ata_link *link, struct ata_device **r_failed_dev)
 {
 	struct ata_port *ap = link->ap;
 	struct ata_device *dev;
 	int rc = 0, used_dma = 0, found = 0;
 	/* step 1: calculate xfer_mask */
 	ata_for_each_dev(dev, link, ENABLED) {
 		unsigned long pio_mask, dma_mask;
 		unsigned int mode_mask;
 		mode_mask = ATA_DMA_MASK_ATA;
 		if (dev->class == ATA_DEV_ATAPI)
 			mode_mask = ATA_DMA_MASK_ATAPI;
 		else if (ata_id_is_cfa(dev->id))
 			mode_mask = ATA_DMA_MASK_CFA;
 		ata_dev_xfermask(dev);
 		ata_force_xfermask(dev);
 		pio_mask = ata_pack_xfermask(dev->pio_mask, 0, 0);
 		dma_mask = ata_pack_xfermask(0, dev->mwdma_mask, dev->udma_mask);
 		if (libata_dma_mask & mode_mask)
 			dma_mask = ata_pack_xfermask(0, dev->mwdma_mask, dev->udma_mask);
 		else
 			dma_mask = 0;
 		dev->pio_mode = ata_xfer_mask2mode(pio_mask);
 		dev->dma_mode = ata_xfer_mask2mode(dma_mask);
 		found = 1;
 		if (ata_dma_enabled(dev))
 			used_dma = 1;
 	}
 	if (!found)
 		goto out;
 	/* step 2: always set host PIO timings */
 	ata_for_each_dev(dev, link, ENABLED) {
 		if (dev->pio_mode == 0xff) {
 			ata_dev_printk(dev, KERN_WARNING, "no PIO support\n");
 			rc = -EINVAL;
 			goto out;
 		}
 		dev->xfer_mode = dev->pio_mode;
 		dev->xfer_shift = ATA_SHIFT_PIO;
 		if (ap->ops->set_piomode)
 			ap->ops->set_piomode(ap, dev);
 	}
 	/* step 3: set host DMA timings */
 	ata_for_each_dev(dev, link, ENABLED) {
 		if (!ata_dma_enabled(dev))
 			continue;
 		dev->xfer_mode = dev->dma_mode;
 		dev->xfer_shift = ata_xfer_mode2shift(dev->dma_mode);
 		if (ap->ops->set_dmamode)
 			ap->ops->set_dmamode(ap, dev);
 	}
 	/* step 4: update devices' xfer mode */
 	ata_for_each_dev(dev, link, ENABLED) {
 		rc = ata_dev_set_mode(dev);
 		if (rc)
 			goto out;
 	}
 	/* Record simplex status. If we selected DMA then the other
 	 * host channels are not permitted to do so.
 	 */
 	if (used_dma && (ap->host->flags & ATA_HOST_SIMPLEX))
 		ap->host->simplex_claimed = ap;
  out:
 	if (rc)
 		*r_failed_dev = dev;
 	return rc;
 }
 /**
  *	ata_wait_ready - wait for link to become ready
  *	@link: link to be waited on
  *	@deadline: deadline jiffies for the operation
  *	@check_ready: callback to check link readiness
  *
  *	Wait for @link to become ready.  @check_ready should return
  *	positive number if @link is ready, 0 if it isn't, -ENODEV if
  *	link doesn't seem to be occupied, other errno for other error
  *	conditions.
  *
  *	Transient -ENODEV conditions are allowed for
  *	ATA_TMOUT_FF_WAIT.
  *
  *	LOCKING:
  *	EH context.
  *
  *	RETURNS:
  *	0 if @linke is ready before @deadline; otherwise, -errno.
  */
 int ata_wait_ready(struct ata_link *link, unsigned long deadline,
 		   int (*check_ready)(struct ata_link *link))
 {
 	unsigned long start = jiffies;
 	unsigned long nodev_deadline;
 	int warned = 0;
 	/* choose which 0xff timeout to use, read comment in libata.h */
 	if (link->ap->host->flags & ATA_HOST_PARALLEL_SCAN)
 		nodev_deadline = ata_deadline(start, ATA_TMOUT_FF_WAIT_LONG);
 	else
 		nodev_deadline = ata_deadline(start, ATA_TMOUT_FF_WAIT);
 	/* Slave readiness can't be tested separately from master.  On
 	 * M/S emulation configuration, this function should be called
 	 * only on the master and it will handle both master and slave.
 	 */
 	WARN_ON(link == link->ap->slave_link);
 	if (time_after(nodev_deadline, deadline))
 		nodev_deadline = deadline;
 	while (1) {
 		unsigned long now = jiffies;
 		int ready, tmp;
 		ready = tmp = check_ready(link);
 		if (ready > 0)
 			return 0;
 		/*
 		 * -ENODEV could be transient.  Ignore -ENODEV if link
 		 * is online.  Also, some SATA devices take a long
 		 * time to clear 0xff after reset.  Wait for
 		 * ATA_TMOUT_FF_WAIT[_LONG] on -ENODEV if link isn't
 		 * offline.
 		 *
 		 * Note that some PATA controllers (pata_ali) explode
 		 * if status register is read more than once when
 		 * there's no device attached.
 		 */
 		if (ready == -ENODEV) {
 			if (ata_link_online(link))
 				ready = 0;
 			else if ((link->ap->flags & ATA_FLAG_SATA) &&
 				 !ata_link_offline(link) &&
 				 time_before(now, nodev_deadline))
 				ready = 0;
 		}
 		if (ready)
 			return ready;
 		if (time_after(now, deadline))
 			return -EBUSY;
 		if (!warned && time_after(now, start + 5 * HZ) &&
 		    (deadline - now > 3 * HZ)) {
 			ata_link_printk(link, KERN_WARNING,
 				"link is slow to respond, please be patient "
 				"(ready=%d)\n", tmp);
 			warned = 1;
 		}
 		msleep(50);
 	}
 }
 /**
  *	ata_wait_after_reset - wait for link to become ready after reset
  *	@link: link to be waited on
  *	@deadline: deadline jiffies for the operation
  *	@check_ready: callback to check link readiness
  *
  *	Wait for @link to become ready after reset.
  *
  *	LOCKING:
  *	EH context.
  *
  *	RETURNS:
  *	0 if @linke is ready before @deadline; otherwise, -errno.
  */
 int ata_wait_after_reset(struct ata_link *link, unsigned long deadline,
 				int (*check_ready)(struct ata_link *link))
 {
 	msleep(ATA_WAIT_AFTER_RESET);
 	return ata_wait_ready(link, deadline, check_ready);
 }
 /**
  *	sata_link_debounce - debounce SATA phy status
  *	@link: ATA link to debounce SATA phy status for
  *	@params: timing parameters { interval, duratinon, timeout } in msec
  *	@deadline: deadline jiffies for the operation
  *
 *	Make sure SStatus of @link reaches stable state, determined by
  *	holding the same value where DET is not 1 for @duration polled
  *	every @interval, before @timeout.  Timeout constraints the
  *	beginning of the stable state.  Because DET gets stuck at 1 on
  *	some controllers after hot unplugging, this functions waits
  *	until timeout then returns 0 if DET is stable at 1.
  *
  *	@timeout is further limited by @deadline.  The sooner of the
  *	two is used.
  *
  *	LOCKING:
  *	Kernel thread context (may sleep)
  *
  *	RETURNS:
  *	0 on success, -errno on failure.
  */
 int sata_link_debounce(struct ata_link *link, const unsigned long *params,
 		       unsigned long deadline)
 {
 	unsigned long interval = params[0];
 	unsigned long duration = params[1];
 	unsigned long last_jiffies, t;
 	u32 last, cur;
 	int rc;
 	t = ata_deadline(jiffies, params[2]);
 	if (time_before(t, deadline))
 		deadline = t;
 	if ((rc = sata_scr_read(link, SCR_STATUS, &cur)))
 		return rc;
 	cur &= 0xf;
 	last = cur;
 	last_jiffies = jiffies;
 	while (1) {
 		msleep(interval);
 		if ((rc = sata_scr_read(link, SCR_STATUS, &cur)))
 			return rc;
 		cur &= 0xf;
 		/* DET stable? */
 		if (cur == last) {
 			if (cur == 1 && time_before(jiffies, deadline))
 				continue;
 			if (time_after(jiffies,
 				       ata_deadline(last_jiffies, duration)))
 				return 0;
 			continue;
 		}
 		/* unstable, start over */
 		last = cur;
 		last_jiffies = jiffies;
 		/* Check deadline.  If debouncing failed, return
 		 * -EPIPE to tell upper layer to lower link speed.
 		 */
 		if (time_after(jiffies, deadline))
 			return -EPIPE;
 	}
 }
 /**
  *	sata_link_resume - resume SATA link
  *	@link: ATA link to resume SATA
  *	@params: timing parameters { interval, duratinon, timeout } in msec
  *	@deadline: deadline jiffies for the operation
  *
  *	Resume SATA phy @link and debounce it.
  *
  *	LOCKING:
  *	Kernel thread context (may sleep)
  *
  *	RETURNS:
  *	0 on success, -errno on failure.
  */
 int sata_link_resume(struct ata_link *link, const unsigned long *params,
 		     unsigned long deadline)
 {
 	int tries = ATA_LINK_RESUME_TRIES;
 	u32 scontrol, serror;
 	int rc;
 	if ((rc = sata_scr_read(link, SCR_CONTROL, &scontrol)))
 		return rc;
 	/*
 	 * Writes to SControl sometimes get ignored under certain
 	 * controllers (ata_piix SIDPR).  Make sure DET actually is
 	 * cleared.
 	 */
 	do {
 		scontrol = (scontrol & 0x0f0) | 0x300;
 		if ((rc = sata_scr_write(link, SCR_CONTROL, scontrol)))
 			return rc;
 		/*
 		 * Some PHYs react badly if SStatus is pounded
 		 * immediately after resuming.  Delay 200ms before
 		 * debouncing.
 		 */
 		msleep(200);
 		/* is SControl restored correctly? */
 		if ((rc = sata_scr_read(link, SCR_CONTROL, &scontrol)))
 			return rc;
 	} while ((scontrol & 0xf0f) != 0x300 && --tries);
 	if ((scontrol & 0xf0f) != 0x300) {
 		ata_link_printk(link, KERN_ERR,
 				"failed to resume link (SControl %X)\n",
 				scontrol);
 		return 0;
 	}
 	if (tries < ATA_LINK_RESUME_TRIES)
 		ata_link_printk(link, KERN_WARNING,
 				"link resume succeeded after %d retries\n",
 				ATA_LINK_RESUME_TRIES - tries);
 	if ((rc = sata_link_debounce(link, params, deadline)))
 		return rc;
 	/* clear SError, some PHYs require this even for SRST to work */
 	if (!(rc = sata_scr_read(link, SCR_ERROR, &serror)))
 		rc = sata_scr_write(link, SCR_ERROR, serror);
 	return rc != -EINVAL ? rc : 0;
 }
 /**
  *	ata_std_prereset - prepare for reset
  *	@link: ATA link to be reset
  *	@deadline: deadline jiffies for the operation
  *
  *	@link is about to be reset.  Initialize it.  Failure from
  *	prereset makes libata abort whole reset sequence and give up
  *	that port, so prereset should be best-effort.  It does its
  *	best to prepare for reset sequence but if things go wrong, it
  *	should just whine, not fail.
  *
  *	LOCKING:
  *	Kernel thread context (may sleep)
  *
  *	RETURNS:
  *	0 on success, -errno otherwise.
  */
 int ata_std_prereset(struct ata_link *link, unsigned long deadline)
 {
 	struct ata_port *ap = link->ap;
 	struct ata_eh_context *ehc = &link->eh_context;
 	const unsigned long *timing = sata_ehc_deb_timing(ehc);
 	int rc;
 	/* if we're about to do hardreset, nothing more to do */
 	if (ehc->i.action & ATA_EH_HARDRESET)
 		return 0;
 	/* if SATA, resume link */
 	if (ap->flags & ATA_FLAG_SATA) {
 		rc = sata_link_resume(link, timing, deadline);
 		/* whine about phy resume failure but proceed */
 		if (rc && rc != -EOPNOTSUPP)
 			ata_link_printk(link, KERN_WARNING, "failed to resume "
 					"link for reset (errno=%d)\n", rc);
 	}
 	/* no point in trying softreset on offline link */
 	if (ata_phys_link_offline(link))
 		ehc->i.action &= ~ATA_EH_SOFTRESET;
 	return 0;
 }
 /**
  *	sata_link_hardreset - reset link via SATA phy reset
  *	@link: link to reset
  *	@timing: timing parameters { interval, duratinon, timeout } in msec
  *	@deadline: deadline jiffies for the operation
  *	@online: optional out parameter indicating link onlineness
  *	@check_ready: optional callback to check link readiness
  *
  *	SATA phy-reset @link using DET bits of SControl register.
  *	After hardreset, link readiness is waited upon using
  *	ata_wait_ready() if @check_ready is specified.  LLDs are
  *	allowed to not specify @check_ready and wait itself after this
  *	function returns.  Device classification is LLD's
  *	responsibility.
  *
  *	*@online is set to one iff reset succeeded and @link is online
  *	after reset.
  *
  *	LOCKING:
  *	Kernel thread context (may sleep)
  *
  *	RETURNS:
  *	0 on success, -errno otherwise.
  */
 int sata_link_hardreset(struct ata_link *link, const unsigned long *timing,
 			unsigned long deadline,
 			bool *online, int (*check_ready)(struct ata_link *))
 {
 	u32 scontrol;
 	int rc;
 	DPRINTK("ENTER\n");
 	if (online)
 		*online = false;
 	if (sata_set_spd_needed(link)) {
 		/* SATA spec says nothing about how to reconfigure
 		 * spd.  To be on the safe side, turn off phy during
 		 * reconfiguration.  This works for at least ICH7 AHCI
 		 * and Sil3124.
 		 */
 		if ((rc = sata_scr_read(link, SCR_CONTROL, &scontrol)))
 			goto out;
 		scontrol = (scontrol & 0x0f0) | 0x304;
 		if ((rc = sata_scr_write(link, SCR_CONTROL, scontrol)))
 			goto out;
 		sata_set_spd(link);
 	}
 	/* issue phy wake/reset */
 	if ((rc = sata_scr_read(link, SCR_CONTROL, &scontrol)))
 		goto out;
 	scontrol = (scontrol & 0x0f0) | 0x301;
 	if ((rc = sata_scr_write_flush(link, SCR_CONTROL, scontrol)))
 		goto out;
 	/* Couldn't find anything in SATA I/II specs, but AHCI-1.1
 	 * 10.4.2 says at least 1 ms.
 	 */
 	msleep(1);
 	/* bring link back */
 	rc = sata_link_resume(link, timing, deadline);
 	if (rc)
 		goto out;
 	/* if link is offline nothing more to do */
 	if (ata_phys_link_offline(link))
 		goto out;
 	/* Link is online.  From this point, -ENODEV too is an error. */
 	if (online)
 		*online = true;
 	if (sata_pmp_supported(link->ap) && ata_is_host_link(link)) {
 		/* If PMP is supported, we have to do follow-up SRST.
 		 * Some PMPs don't send D2H Reg FIS after hardreset if
 		 * the first port is empty.  Wait only for
 		 * ATA_TMOUT_PMP_SRST_WAIT.
 		 */
 		if (check_ready) {
 			unsigned long pmp_deadline;
 			pmp_deadline = ata_deadline(jiffies,
 						    ATA_TMOUT_PMP_SRST_WAIT);
 			if (time_after(pmp_deadline, deadline))
 				pmp_deadline = deadline;
 			ata_wait_ready(link, pmp_deadline, check_ready);
 		}
 		rc = -EAGAIN;
 		goto out;
 	}
 	rc = 0;
 	if (check_ready)
 		rc = ata_wait_ready(link, deadline, check_ready);
  out:
 	if (rc && rc != -EAGAIN) {
 		/* online is set iff link is online && reset succeeded */
 		if (online)
 			*online = false;
 		ata_link_printk(link, KERN_ERR,
 				"COMRESET failed (errno=%d)\n", rc);
 	}
 	DPRINTK("EXIT, rc=%d\n", rc);
 	return rc;
 }
 /**
  *	sata_std_hardreset - COMRESET w/o waiting or classification
  *	@link: link to reset
  *	@class: resulting class of attached device
  *	@deadline: deadline jiffies for the operation
  *
  *	Standard SATA COMRESET w/o waiting or classification.
  *
  *	LOCKING:
  *	Kernel thread context (may sleep)
  *
  *	RETURNS:
  *	0 if link offline, -EAGAIN if link online, -errno on errors.
  */
 int sata_std_hardreset(struct ata_link *link, unsigned int *class,
 		       unsigned long deadline)
 {
 	const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
 	bool online;
 	int rc;
 	/* do hardreset */
 	rc = sata_link_hardreset(link, timing, deadline, &online, NULL);
 	return online ? -EAGAIN : rc;
 }
 /**
  *	ata_std_postreset - standard postreset callback
  *	@link: the target ata_link
  *	@classes: classes of attached devices
  *
  *	This function is invoked after a successful reset.  Note that
  *	the device might have been reset more than once using
  *	different reset methods before postreset is invoked.
  *
  *	LOCKING:
  *	Kernel thread context (may sleep)
  */
 void ata_std_postreset(struct ata_link *link, unsigned int *classes)
 {
 	u32 serror;
 	DPRINTK("ENTER\n");
 	/* reset complete, clear SError */
 	if (!sata_scr_read(link, SCR_ERROR, &serror))
 		sata_scr_write(link, SCR_ERROR, serror);
 	/* print link status */
 	sata_print_link_status(link);
 	DPRINTK("EXIT\n");
 }
 /**
  *	ata_dev_same_device - Determine whether new ID matches configured device
  *	@dev: device to compare against
  *	@new_class: class of the new device
  *	@new_id: IDENTIFY page of the new device
  *
  *	Compare @new_class and @new_id against @dev and determine
  *	whether @dev is the device indicated by @new_class and
  *	@new_id.
  *
  *	LOCKING:
  *	None.
  *
  *	RETURNS:
  *	1 if @dev matches @new_class and @new_id, 0 otherwise.
  */
 static int ata_dev_same_device(struct ata_device *dev, unsigned int new_class,
 			       const u16 *new_id)
 {
 	const u16 *old_id = dev->id;
 	unsigned char model[2][ATA_ID_PROD_LEN + 1];
 	unsigned char serial[2][ATA_ID_SERNO_LEN + 1];
 	if (dev->class != new_class) {
 		ata_dev_printk(dev, KERN_INFO, "class mismatch %d != %d\n",
 			       dev->class, new_class);
 		return 0;
 	}
 	ata_id_c_string(old_id, model[0], ATA_ID_PROD, sizeof(model[0]));
 	ata_id_c_string(new_id, model[1], ATA_ID_PROD, sizeof(model[1]));
 	ata_id_c_string(old_id, serial[0], ATA_ID_SERNO, sizeof(serial[0]));
 	ata_id_c_string(new_id, serial[1], ATA_ID_SERNO, sizeof(serial[1]));
 	if (strcmp(model[0], model[1])) {
 		ata_dev_printk(dev, KERN_INFO, "model number mismatch "
 			       "'%s' != '%s'\n", model[0], model[1]);
 		return 0;
 	}
 	if (strcmp(serial[0], serial[1])) {
 		ata_dev_printk(dev, KERN_INFO, "serial number mismatch "
 			       "'%s' != '%s'\n", serial[0], serial[1]);
 		return 0;
 	}
 	return 1;
 }
 /**
  *	ata_dev_reread_id - Re-read IDENTIFY data
  *	@dev: target ATA device
  *	@readid_flags: read ID flags
  *
  *	Re-read IDENTIFY page and make sure @dev is still attached to
  *	the port.
  *
  *	LOCKING:
  *	Kernel thread context (may sleep)
  *
  *	RETURNS:
  *	0 on success, negative errno otherwise
  */
 int ata_dev_reread_id(struct ata_device *dev, unsigned int readid_flags)
 {
 	unsigned int class = dev->class;
 	u16 *id = (void *)dev->link->ap->sector_buf;
 	int rc;
 	/* read ID data */
 	rc = ata_dev_read_id(dev, &class, readid_flags, id);
 	if (rc)
 		return rc;
 	/* is the device still there? */
 	if (!ata_dev_same_device(dev, class, id))
 		return -ENODEV;
 	memcpy(dev->id, id, sizeof(id[0]) * ATA_ID_WORDS);
 	return 0;
 }
 /**
  *	ata_dev_revalidate - Revalidate ATA device
  *	@dev: device to revalidate
  *	@new_class: new class code
  *	@readid_flags: read ID flags
  *
  *	Re-read IDENTIFY page, make sure @dev is still attached to the
  *	port and reconfigure it according to the new IDENTIFY page.
  *
  *	LOCKING:
  *	Kernel thread context (may sleep)
  *
  *	RETURNS:
  *	0 on success, negative errno otherwise
  */
 int ata_dev_revalidate(struct ata_device *dev, unsigned int new_class,
 		       unsigned int readid_flags)
 {
 	u64 n_sectors = dev->n_sectors;
 	u64 n_native_sectors = dev->n_native_sectors;
 	int rc;
 	if (!ata_dev_enabled(dev))
 		return -ENODEV;
 	/* fail early if !ATA && !ATAPI to avoid issuing [P]IDENTIFY to PMP */
 	if (ata_class_enabled(new_class) &&
 	    new_class != ATA_DEV_ATA &&
 	    new_class != ATA_DEV_ATAPI &&
 	    new_class != ATA_DEV_SEMB) {
 		ata_dev_printk(dev, KERN_INFO, "class mismatch %u != %u\n",
 			       dev->class, new_class);
 		rc = -ENODEV;
 		goto fail;
 	}
 	/* re-read ID */
 	rc = ata_dev_reread_id(dev, readid_flags);
 	if (rc)
 		goto fail;
 	/* configure device according to the new ID */
 	rc = ata_dev_configure(dev);
 	if (rc)
 		goto fail;
 	/* verify n_sectors hasn't changed */
 	if (dev->class != ATA_DEV_ATA || !n_sectors ||
 	    dev->n_sectors == n_sectors)
 		return 0;
 	/* n_sectors has changed */
 	ata_dev_printk(dev, KERN_WARNING, "n_sectors mismatch %llu != %llu\n",
 		       (unsigned long long)n_sectors,
 		       (unsigned long long)dev->n_sectors);
 	/*
 	 * Something could have caused HPA to be unlocked
 	 * involuntarily.  If n_native_sectors hasn't changed and the
 	 * new size matches it, keep the device.
 	 */
 	if (dev->n_native_sectors == n_native_sectors &&
 	    dev->n_sectors > n_sectors && dev->n_sectors == n_native_sectors) {
 		ata_dev_printk(dev, KERN_WARNING,
 			       "new n_sectors matches native, probably "
 			       "late HPA unlock, n_sectors updated\n");
 		/* use the larger n_sectors */
 		return 0;
 	}
 	/*
 	 * Some BIOSes boot w/o HPA but resume w/ HPA locked.  Try
 	 * unlocking HPA in those cases.
 	 *
 	 * https://bugzilla.kernel.org/show_bug.cgi?id=15396
 	 */
 	if (dev->n_native_sectors == n_native_sectors &&
 	    dev->n_sectors < n_sectors && n_sectors == n_native_sectors &&
 	    !(dev->horkage & ATA_HORKAGE_BROKEN_HPA)) {
 		ata_dev_printk(dev, KERN_WARNING,
 			       "old n_sectors matches native, probably "
 			       "late HPA lock, will try to unlock HPA\n");
 		/* try unlocking HPA */
 		dev->flags |= ATA_DFLAG_UNLOCK_HPA;
 		rc = -EIO;
 	} else
 		rc = -ENODEV;
 	/* restore original n_[native_]sectors and fail */
 	dev->n_native_sectors = n_native_sectors;
 	dev->n_sectors = n_sectors;
  fail:
 	ata_dev_printk(dev, KERN_ERR, "revalidation failed (errno=%d)\n", rc);
 	return rc;
 }
 struct ata_blacklist_entry {
 	const char *model_num;
 	const char *model_rev;
 	unsigned long horkage;
 };
 static const struct ata_blacklist_entry ata_device_blacklist [] = {
 	/* Devices with DMA related problems under Linux */
 	{ "WDC AC11000H",	NULL,		ATA_HORKAGE_NODMA },
 	{ "WDC AC22100H",	NULL,		ATA_HORKAGE_NODMA },
 	{ "WDC AC32500H",	NULL,		ATA_HORKAGE_NODMA },
 	{ "WDC AC33100H",	NULL,		ATA_HORKAGE_NODMA },
 	{ "WDC AC31600H",	NULL,		ATA_HORKAGE_NODMA },
 	{ "WDC AC32100H",	"24.09P07",	ATA_HORKAGE_NODMA },
 	{ "WDC AC23200L",	"21.10N21",	ATA_HORKAGE_NODMA },
 	{ "Compaq CRD-8241B", 	NULL,		ATA_HORKAGE_NODMA },
 	{ "CRD-8400B",		NULL, 		ATA_HORKAGE_NODMA },
 	{ "CRD-848[02]B",	NULL,		ATA_HORKAGE_NODMA },
 	{ "CRD-84",		NULL,		ATA_HORKAGE_NODMA },
 	{ "SanDisk SDP3B",	NULL,		ATA_HORKAGE_NODMA },
 	{ "SanDisk SDP3B-64",	NULL,		ATA_HORKAGE_NODMA },
 	{ "SANYO CD-ROM CRD",	NULL,		ATA_HORKAGE_NODMA },
 	{ "HITACHI CDR-8",	NULL,		ATA_HORKAGE_NODMA },
 	{ "HITACHI CDR-8[34]35",NULL,		ATA_HORKAGE_NODMA },
 	{ "Toshiba CD-ROM XM-6202B", NULL,	ATA_HORKAGE_NODMA },
 	{ "TOSHIBA CD-ROM XM-1702BC", NULL,	ATA_HORKAGE_NODMA },
 	{ "CD-532E-A", 		NULL,		ATA_HORKAGE_NODMA },
 	{ "E-IDE CD-ROM CR-840",NULL,		ATA_HORKAGE_NODMA },
 	{ "CD-ROM Drive/F5A",	NULL,		ATA_HORKAGE_NODMA },
 	{ "WPI CDD-820", 	NULL,		ATA_HORKAGE_NODMA },
 	{ "SAMSUNG CD-ROM SC-148C", NULL,	ATA_HORKAGE_NODMA },
 	{ "SAMSUNG CD-ROM SC",	NULL,		ATA_HORKAGE_NODMA },
 	{ "ATAPI CD-ROM DRIVE 40X MAXIMUM",NULL,ATA_HORKAGE_NODMA },
 	{ "_NEC DV5800A", 	NULL,		ATA_HORKAGE_NODMA },
 	{ "SAMSUNG CD-ROM SN-124", "N001",	ATA_HORKAGE_NODMA },
 	{ "Seagate STT20000A", NULL,		ATA_HORKAGE_NODMA },
 	/* Odd clown on sil3726/4726 PMPs */
 	{ "Config  Disk",	NULL,		ATA_HORKAGE_DISABLE },
 	/* Weird ATAPI devices */
 	{ "TORiSAN DVD-ROM DRD-N216", NULL,	ATA_HORKAGE_MAX_SEC_128 },
 	{ "QUANTUM DAT    DAT72-000", NULL,	ATA_HORKAGE_ATAPI_MOD16_DMA },
 	/* Devices we expect to fail diagnostics */
 	/* Devices where NCQ should be avoided */
 	/* NCQ is slow */
 	{ "WDC WD740ADFD-00",	NULL,		ATA_HORKAGE_NONCQ },
 	{ "WDC WD740ADFD-00NLR1", NULL,		ATA_HORKAGE_NONCQ, },
 	/* http://thread.gmane.org/gmane.linux.ide/14907 */
 	{ "FUJITSU MHT2060BH",	NULL,		ATA_HORKAGE_NONCQ },
 	/* NCQ is broken */
 	{ "Maxtor *",		"BANC*",	ATA_HORKAGE_NONCQ },
 	{ "Maxtor 7V300F0",	"VA111630",	ATA_HORKAGE_NONCQ },
 	{ "ST380817AS",		"3.42",		ATA_HORKAGE_NONCQ },
 	{ "ST3160023AS",	"3.42",		ATA_HORKAGE_NONCQ },
 	{ "OCZ CORE_SSD",	"02.10104",	ATA_HORKAGE_NONCQ },
 	/* Seagate NCQ + FLUSH CACHE firmware bug */
 	{ "ST31500341AS",	"SD1[5-9]",	ATA_HORKAGE_NONCQ |
 						ATA_HORKAGE_FIRMWARE_WARN },
 	{ "ST31000333AS",	"SD1[5-9]",	ATA_HORKAGE_NONCQ |
 						ATA_HORKAGE_FIRMWARE_WARN },
 	{ "ST3640[36]23AS",	"SD1[5-9]",	ATA_HORKAGE_NONCQ |
 						ATA_HORKAGE_FIRMWARE_WARN },
 	{ "ST3320[68]13AS",	"SD1[5-9]",	ATA_HORKAGE_NONCQ |
 						ATA_HORKAGE_FIRMWARE_WARN },
 	/* Blacklist entries taken from Silicon Image 3124/3132
 	   Windows driver .inf file - also several Linux problem reports */
 	{ "HTS541060G9SA00",    "MB3OC60D",     ATA_HORKAGE_NONCQ, },
 	{ "HTS541080G9SA00",    "MB4OC60D",     ATA_HORKAGE_NONCQ, },
 	{ "HTS541010G9SA00",    "MBZOC60D",     ATA_HORKAGE_NONCQ, },
 	/* https://bugzilla.kernel.org/show_bug.cgi?id=15573 */
 	{ "C300-CTFDDAC128MAG",	"0001",		ATA_HORKAGE_NONCQ, },
 	/* devices which puke on READ_NATIVE_MAX */
 	{ "HDS724040KLSA80",	"KFAOA20N",	ATA_HORKAGE_BROKEN_HPA, },
 	{ "WDC WD3200JD-00KLB0", "WD-WCAMR1130137", ATA_HORKAGE_BROKEN_HPA },
 	{ "WDC WD2500JD-00HBB0", "WD-WMAL71490727", ATA_HORKAGE_BROKEN_HPA },
 	{ "MAXTOR 6L080L4",	"A93.0500",	ATA_HORKAGE_BROKEN_HPA },
 	/* this one allows HPA unlocking but fails IOs on the area */
 	{ "OCZ-VERTEX",		    "1.30",	ATA_HORKAGE_BROKEN_HPA },
 	/* Devices which report 1 sector over size HPA */
 	{ "ST340823A",		NULL,		ATA_HORKAGE_HPA_SIZE, },
 	{ "ST320413A",		NULL,		ATA_HORKAGE_HPA_SIZE, },
 	{ "ST310211A",		NULL,		ATA_HORKAGE_HPA_SIZE, },
 	/* Devices which get the IVB wrong */
 	{ "QUANTUM FIREBALLlct10 05", "A03.0900", ATA_HORKAGE_IVB, },
 	/* Maybe we should just blacklist TSSTcorp... */
 	{ "TSSTcorp CDDVDW SH-S202[HJN]", "SB0[01]",  ATA_HORKAGE_IVB, },
 	/* Devices that do not need bridging limits applied */
 	{ "MTRON MSP-SATA*",		NULL,	ATA_HORKAGE_BRIDGE_OK, },
 	/* Devices which aren't very happy with higher link speeds */
 	{ "WD My Book",			NULL,	ATA_HORKAGE_1_5_GBPS, },
 	/*
 	 * Devices which choke on SETXFER.  Applies only if both the
 	 * device and controller are SATA.
 	 */
 	{ "PIONEER DVD-RW  DVRTD08",	"1.00",	ATA_HORKAGE_NOSETXFER },
 	/* End Marker */
 	{ }
 };
 /**
  *	glob_match - match a text string against a glob-style pattern
  *	@text: the string to be examined
  *	@pattern: the glob-style pattern to be matched against
  *
  *	Either/both of text and pattern can be empty strings.
  *
  *	Match text against a glob-style pattern, with wildcards and simple sets:
  *
  *		?	matches any single character.
  *		*	matches any run of characters.
  *		[xyz]	matches a single character from the set: x, y, or z.
  *		[a-d]	matches a single character from the range: a, b, c, or d.
  *		[a-d0-9] matches a single character from either range.
  *
  *	The special characters ?, [, -, or *, can be matched using a set, eg. [*]
  *	Behaviour with malformed patterns is undefined, though generally reasonable.
  *
  *	Sample patterns:  "SD1?",  "SD1[0-5]",  "*R0",  "SD*1?[012]*xx"
  *
  *	This function uses one level of recursion per '*' in pattern.
  *	Since it calls _nothing_ else, and has _no_ explicit local variables,
  *	this will not cause stack problems for any reasonable use here.
  *
  *	RETURNS:
  *	0 on match, 1 otherwise.
  */
 static int glob_match (const char *text, const char *pattern)
 {
 	do {
 		/* Match single character or a '?' wildcard */
 		if (*text == *pattern || *pattern == '?') {
 			if (!*pattern++)
 				return 0;  /* End of both strings: match */
 		} else {
 			/* Match single char against a '[' bracketed ']' pattern set */
 			if (!*text || *pattern != '[')
 				break;  /* Not a pattern set */
 			while (*++pattern && *pattern != ']' && *text != *pattern) {
 				if (*pattern == '-' && *(pattern - 1) != '[')
 					if (*text > *(pattern - 1) && *text < *(pattern + 1)) {
 						++pattern;
 						break;
 					}
 			}
 			if (!*pattern || *pattern == ']')
 				return 1;  /* No match */
 			while (*pattern && *pattern++ != ']');
 		}
 	} while (*++text && *pattern);
 	/* Match any run of chars against a '*' wildcard */
 	if (*pattern == '*') {
 		if (!*++pattern)
 			return 0;  /* Match: avoid recursion at end of pattern */
 		/* Loop to handle additional pattern chars after the wildcard */
 		while (*text) {
 			if (glob_match(text, pattern) == 0)
 				return 0;  /* Remainder matched */
 			++text;  /* Absorb (match) this char and try again */
 		}
 	}
 	if (!*text && !*pattern)
 		return 0;  /* End of both strings: match */
 	return 1;  /* No match */
 }
 static unsigned long ata_dev_blacklisted(const struct ata_device *dev)
 {
 	unsigned char model_num[ATA_ID_PROD_LEN + 1];
 	unsigned char model_rev[ATA_ID_FW_REV_LEN + 1];
 	const struct ata_blacklist_entry *ad = ata_device_blacklist;
 	ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
 	ata_id_c_string(dev->id, model_rev, ATA_ID_FW_REV, sizeof(model_rev));
 	while (ad->model_num) {
 		if (!glob_match(model_num, ad->model_num)) {
 			if (ad->model_rev == NULL)
 				return ad->horkage;
 			if (!glob_match(model_rev, ad->model_rev))
 				return ad->horkage;
 		}
 		ad++;
 	}
 	return 0;
 }
 static int ata_dma_blacklisted(const struct ata_device *dev)
 {
 	/* We don't support polling DMA.
 	 * DMA blacklist those ATAPI devices with CDB-intr (and use PIO)
 	 * if the LLDD handles only interrupts in the HSM_ST_LAST state.
 	 */
 	if ((dev->link->ap->flags & ATA_FLAG_PIO_POLLING) &&
 	    (dev->flags & ATA_DFLAG_CDB_INTR))
 		return 1;
 	return (dev->horkage & ATA_HORKAGE_NODMA) ? 1 : 0;
 }
 /**
  *	ata_is_40wire		-	check drive side detection
  *	@dev: device
  *
  *	Perform drive side detection decoding, allowing for device vendors
  *	who can't follow the documentation.
  */
 static int ata_is_40wire(struct ata_device *dev)
 {
 	if (dev->horkage & ATA_HORKAGE_IVB)
 		return ata_drive_40wire_relaxed(dev->id);
 	return ata_drive_40wire(dev->id);
 }
 /**
  *	cable_is_40wire		-	40/80/SATA decider
  *	@ap: port to consider
  *
  *	This function encapsulates the policy for speed management
  *	in one place. At the moment we don't cache the result but
  *	there is a good case for setting ap->cbl to the result when
  *	we are called with unknown cables (and figuring out if it
  *	impacts hotplug at all).
  *
  *	Return 1 if the cable appears to be 40 wire.
  */
 static int cable_is_40wire(struct ata_port *ap)
 {
 	struct ata_link *link;
 	struct ata_device *dev;
 	/* If the controller thinks we are 40 wire, we are. */
 	if (ap->cbl == ATA_CBL_PATA40)
 		return 1;
 	/* If the controller thinks we are 80 wire, we are. */
 	if (ap->cbl == ATA_CBL_PATA80 || ap->cbl == ATA_CBL_SATA)
 		return 0;
 	/* If the system is known to be 40 wire short cable (eg
 	 * laptop), then we allow 80 wire modes even if the drive
 	 * isn't sure.
 	 */
 	if (ap->cbl == ATA_CBL_PATA40_SHORT)
 		return 0;
 	/* If the controller doesn't know, we scan.
 	 *
 	 * Note: We look for all 40 wire detects at this point.  Any
 	 *       80 wire detect is taken to be 80 wire cable because
 	 * - in many setups only the one drive (slave if present) will
 	 *   give a valid detect
 	 * - if you have a non detect capable drive you don't want it
 	 *   to colour the choice
 	 */
 	ata_for_each_link(link, ap, EDGE) {
 		ata_for_each_dev(dev, link, ENABLED) {
 			if (!ata_is_40wire(dev))
 				return 0;
 		}
 	}
 	return 1;
 }
 /**
  *	ata_dev_xfermask - Compute supported xfermask of the given device
  *	@dev: Device to compute xfermask for
  *
  *	Compute supported xfermask of @dev and store it in
  *	dev->*_mask.  This function is responsible for applying all
  *	known limits including host controller limits, device
  *	blacklist, etc...
  *
  *	LOCKING:
  *	None.
  */
 static void ata_dev_xfermask(struct ata_device *dev)
 {
 	struct ata_link *link = dev->link;
 	struct ata_port *ap = link->ap;
 	struct ata_host *host = ap->host;
 	unsigned long xfer_mask;
 	/* controller modes available */
 	xfer_mask = ata_pack_xfermask(ap->pio_mask,
 				      ap->mwdma_mask, ap->udma_mask);
 	/* drive modes available */
 	xfer_mask &= ata_pack_xfermask(dev->pio_mask,
 				       dev->mwdma_mask, dev->udma_mask);
 	xfer_mask &= ata_id_xfermask(dev->id);
 	/*
 	 *	CFA Advanced TrueIDE timings are not allowed on a shared
 	 *	cable
 	 */
 	if (ata_dev_pair(dev)) {
 		/* No PIO5 or PIO6 */
 		xfer_mask &= ~(0x03 << (ATA_SHIFT_PIO + 5));
 		/* No MWDMA3 or MWDMA 4 */
 		xfer_mask &= ~(0x03 << (ATA_SHIFT_MWDMA + 3));
 	}
 	if (ata_dma_blacklisted(dev)) {
 		xfer_mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA);
 		ata_dev_printk(dev, KERN_WARNING,
 			       "device is on DMA blacklist, disabling DMA\n");
 	}
 	if ((host->flags & ATA_HOST_SIMPLEX) &&
 	    host->simplex_claimed && host->simplex_claimed != ap) {
 		xfer_mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA);
 		ata_dev_printk(dev, KERN_WARNING, "simplex DMA is claimed by "
 			       "other device, disabling DMA\n");
 	}
 	if (ap->flags & ATA_FLAG_NO_IORDY)
 		xfer_mask &= ata_pio_mask_no_iordy(dev);
 	if (ap->ops->mode_filter)
 		xfer_mask = ap->ops->mode_filter(dev, xfer_mask);
 	/* Apply cable rule here.  Don't apply it early because when
 	 * we handle hot plug the cable type can itself change.
 	 * Check this last so that we know if the transfer rate was
 	 * solely limited by the cable.
 	 * Unknown or 80 wire cables reported host side are checked
 	 * drive side as well. Cases where we know a 40wire cable
 	 * is used safely for 80 are not checked here.
 	 */
 	if (xfer_mask & (0xF8 << ATA_SHIFT_UDMA))
 		/* UDMA/44 or higher would be available */
 		if (cable_is_40wire(ap)) {
 			ata_dev_printk(dev, KERN_WARNING,
 				 "limited to UDMA/33 due to 40-wire cable\n");
 			xfer_mask &= ~(0xF8 << ATA_SHIFT_UDMA);
 		}
 	ata_unpack_xfermask(xfer_mask, &dev->pio_mask,
 			    &dev->mwdma_mask, &dev->udma_mask);
 }
 /**
  *	ata_dev_set_xfermode - Issue SET FEATURES - XFER MODE command
  *	@dev: Device to which command will be sent
  *
  *	Issue SET FEATURES - XFER MODE command to device @dev
  *	on port @ap.
  *
  *	LOCKING:
  *	PCI/etc. bus probe sem.
  *
  *	RETURNS:
  *	0 on success, AC_ERR_* mask otherwise.
  */
 static unsigned int ata_dev_set_xfermode(struct ata_device *dev)
 {
 	struct ata_taskfile tf;
 	unsigned int err_mask;
 	/* set up set-features taskfile */
 	DPRINTK("set features - xfer mode\n");
 	/* Some controllers and ATAPI devices show flaky interrupt
 	 * behavior after setting xfer mode.  Use polling instead.
 	 */
 	ata_tf_init(dev, &tf);
 	tf.command = ATA_CMD_SET_FEATURES;
 	tf.feature = SETFEATURES_XFER;
 	tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE | ATA_TFLAG_POLLING;
 	tf.protocol = ATA_PROT_NODATA;
 	/* If we are using IORDY we must send the mode setting command */
 	if (ata_pio_need_iordy(dev))
 		tf.nsect = dev->xfer_mode;
 	/* If the device has IORDY and the controller does not - turn it off */
  	else if (ata_id_has_iordy(dev->id))
 		tf.nsect = 0x01;
 	else /* In the ancient relic department - skip all of this */
 		return 0;
 	err_mask = ata_exec_internal(dev, &tf, NULL, DMA_NONE, NULL, 0, 0);
 	DPRINTK("EXIT, err_mask=%x\n", err_mask);
 	return err_mask;
 }
 /**
  *	ata_dev_set_feature - Issue SET FEATURES - SATA FEATURES
  *	@dev: Device to which command will be sent
  *	@enable: Whether to enable or disable the feature
  *	@feature: The sector count represents the feature to set
  *
  *	Issue SET FEATURES - SATA FEATURES command to device @dev
  *	on port @ap with sector count
  *
  *	LOCKING:
  *	PCI/etc. bus probe sem.
  *
  *	RETURNS:
  *	0 on success, AC_ERR_* mask otherwise.
  */
 static unsigned int ata_dev_set_feature(struct ata_device *dev, u8 enable,
 					u8 feature)
 {
 	struct ata_taskfile tf;
 	unsigned int err_mask;
 	/* set up set-features taskfile */
 	DPRINTK("set features - SATA features\n");
 	ata_tf_init(dev, &tf);
 	tf.command = ATA_CMD_SET_FEATURES;
 	tf.feature = enable;
 	tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
 	tf.protocol = ATA_PROT_NODATA;
 	tf.nsect = feature;
 	err_mask = ata_exec_internal(dev, &tf, NULL, DMA_NONE, NULL, 0, 0);
 	DPRINTK("EXIT, err_mask=%x\n", err_mask);
 	return err_mask;
 }
 /**
  *	ata_dev_init_params - Issue INIT DEV PARAMS command
  *	@dev: Device to which command will be sent
  *	@heads: Number of heads (taskfile parameter)
  *	@sectors: Number of sectors (taskfile parameter)
  *
  *	LOCKING:
  *	Kernel thread context (may sleep)
  *
  *	RETURNS:
  *	0 on success, AC_ERR_* mask otherwise.
  */
 static unsigned int ata_dev_init_params(struct ata_device *dev,
 					u16 heads, u16 sectors)
 {
 	struct ata_taskfile tf;
 	unsigned int err_mask;
 	/* Number of sectors per track 1-255. Number of heads 1-16 */
 	if (sectors < 1 || sectors > 255 || heads < 1 || heads > 16)
 		return AC_ERR_INVALID;
 	/* set up init dev params taskfile */
 	DPRINTK("init dev params \n");
 	ata_tf_init(dev, &tf);
 	tf.command = ATA_CMD_INIT_DEV_PARAMS;
 	tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
 	tf.protocol = ATA_PROT_NODATA;
 	tf.nsect = sectors;
 	tf.device |= (heads - 1) & 0x0f; /* max head = num. of heads - 1 */
 	err_mask = ata_exec_internal(dev, &tf, NULL, DMA_NONE, NULL, 0, 0);
 	/* A clean abort indicates an original or just out of spec drive
 	   and we should continue as we issue the setup based on the
 	   drive reported working geometry */
 	if (err_mask == AC_ERR_DEV && (tf.feature & ATA_ABORTED))
 		err_mask = 0;
 	DPRINTK("EXIT, err_mask=%x\n", err_mask);
 	return err_mask;
 }
 /**
  *	ata_sg_clean - Unmap DMA memory associated with command
  *	@qc: Command containing DMA memory to be released
  *
  *	Unmap all mapped DMA memory associated with this command.
  *
  *	LOCKING:
  *	spin_lock_irqsave(host lock)
  */
 void ata_sg_clean(struct ata_queued_cmd *qc)
 {
 	struct ata_port *ap = qc->ap;
 	struct scatterlist *sg = qc->sg;
 	int dir = qc->dma_dir;
 	WARN_ON_ONCE(sg == NULL);
 	VPRINTK("unmapping %u sg elements\n", qc->n_elem);
 	if (qc->n_elem)
 		dma_unmap_sg(ap->dev, sg, qc->orig_n_elem, dir);
 	qc->flags &= ~ATA_QCFLAG_DMAMAP;
 	qc->sg = NULL;
 }
 /**
  *	atapi_check_dma - Check whether ATAPI DMA can be supported
  *	@qc: Metadata associated with taskfile to check
  *
  *	Allow low-level driver to filter ATA PACKET commands, returning
  *	a status indicating whether or not it is OK to use DMA for the
  *	supplied PACKET command.
  *
  *	LOCKING:
  *	spin_lock_irqsave(host lock)
  *
  *	RETURNS: 0 when ATAPI DMA can be used
  *               nonzero otherwise
  */
 int atapi_check_dma(struct ata_queued_cmd *qc)
 {
 	struct ata_port *ap = qc->ap;
 	/* Don't allow DMA if it isn't multiple of 16 bytes.  Quite a
 	 * few ATAPI devices choke on such DMA requests.
 	 */
 	if (!(qc->dev->horkage & ATA_HORKAGE_ATAPI_MOD16_DMA) &&
 	    unlikely(qc->nbytes & 15))
 		return 1;
 	if (ap->ops->check_atapi_dma)
 		return ap->ops->check_atapi_dma(qc);
 	return 0;
 }
 /**
  *	ata_std_qc_defer - Check whether a qc needs to be deferred
  *	@qc: ATA command in question
  *
  *	Non-NCQ commands cannot run with any other command, NCQ or
  *	not.  As upper layer only knows the queue depth, we are
  *	responsible for maintaining exclusion.  This function checks
  *	whether a new command @qc can be issued.
  *
  *	LOCKING:
  *	spin_lock_irqsave(host lock)
  *
  *	RETURNS:
  *	ATA_DEFER_* if deferring is needed, 0 otherwise.
  */
 int ata_std_qc_defer(struct ata_queued_cmd *qc)
 {
 	struct ata_link *link = qc->dev->link;
 	if (qc->tf.protocol == ATA_PROT_NCQ) {
 		if (!ata_tag_valid(link->active_tag))
 			return 0;
 	} else {
 		if (!ata_tag_valid(link->active_tag) && !link->sactive)
 			return 0;
 	}
 	return ATA_DEFER_LINK;
 }
 void ata_noop_qc_prep(struct ata_queued_cmd *qc) { }
 /**
  *	ata_sg_init - Associate command with scatter-gather table.
  *	@qc: Command to be associated
  *	@sg: Scatter-gather table.
  *	@n_elem: Number of elements in s/g table.
  *
  *	Initialize the data-related elements of queued_cmd @qc
  *	to point to a scatter-gather table @sg, containing @n_elem
  *	elements.
  *
  *	LOCKING:
  *	spin_lock_irqsave(host lock)
  */
 void ata_sg_init(struct ata_queued_cmd *qc, struct scatterlist *sg,
 		 unsigned int n_elem)
 {
 	qc->sg = sg;
 	qc->n_elem = n_elem;
 	qc->cursg = qc->sg;
 }
 /**
  *	ata_sg_setup - DMA-map the scatter-gather table associated with a command.
  *	@qc: Command with scatter-gather table to be mapped.
  *
  *	DMA-map the scatter-gather table associated with queued_cmd @qc.
  *
  *	LOCKING:
  *	spin_lock_irqsave(host lock)
  *
  *	RETURNS:
  *	Zero on success, negative on error.
  *
  */
 static int ata_sg_setup(struct ata_queued_cmd *qc)
 {
 	struct ata_port *ap = qc->ap;
 	unsigned int n_elem;
 	VPRINTK("ENTER, ata%u\n", ap->print_id);
 	n_elem = dma_map_sg(ap->dev, qc->sg, qc->n_elem, qc->dma_dir);
 	if (n_elem < 1)
 		return -1;
 	DPRINTK("%d sg elements mapped\n", n_elem);
 	qc->orig_n_elem = qc->n_elem;
 	qc->n_elem = n_elem;
 	qc->flags |= ATA_QCFLAG_DMAMAP;
 	return 0;
 }
 /**
  *	swap_buf_le16 - swap halves of 16-bit words in place
  *	@buf:  Buffer to swap
  *	@buf_words:  Number of 16-bit words in buffer.
  *
  *	Swap halves of 16-bit words if needed to convert from
  *	little-endian byte order to native cpu byte order, or
  *	vice-versa.
  *
  *	LOCKING:
  *	Inherited from caller.
  */
 void swap_buf_le16(u16 *buf, unsigned int buf_words)
 {
 #ifdef __BIG_ENDIAN
 	unsigned int i;
 	for (i = 0; i < buf_words; i++)
 		buf[i] = le16_to_cpu(buf[i]);
 #endif /* __BIG_ENDIAN */
 }
 /**
  *	ata_qc_new - Request an available ATA command, for queueing
  *	@ap: target port
  *
  *	LOCKING:
  *	None.
  */
 static struct ata_queued_cmd *ata_qc_new(struct ata_port *ap)
 {
 	struct ata_queued_cmd *qc = NULL;
 	unsigned int i;
 	/* no command while frozen */
 	if (unlikely(ap->pflags & ATA_PFLAG_FROZEN))
 		return NULL;
 	/* the last tag is reserved for internal command. */
 	for (i = 0; i < ATA_MAX_QUEUE - 1; i++)
 		if (!test_and_set_bit(i, &ap->qc_allocated)) {
 			qc = __ata_qc_from_tag(ap, i);
 			break;
 		}
 	if (qc)
 		qc->tag = i;
 	return qc;
 }
 /**
  *	ata_qc_new_init - Request an available ATA command, and initialize it
  *	@dev: Device from whom we request an available command structure
  *
  *	LOCKING:
  *	None.
  */
 struct ata_queued_cmd *ata_qc_new_init(struct ata_device *dev)
 {
 	struct ata_port *ap = dev->link->ap;
 	struct ata_queued_cmd *qc;
 	qc = ata_qc_new(ap);
 	if (qc) {
 		qc->scsicmd = NULL;
 		qc->ap = ap;
 		qc->dev = dev;
 		ata_qc_reinit(qc);
 	}
 	return qc;
 }
 /**
  *	ata_qc_free - free unused ata_queued_cmd
  *	@qc: Command to complete
  *
  *	Designed to free unused ata_queued_cmd object
  *	in case something prevents using it.
  *
  *	LOCKING:
  *	spin_lock_irqsave(host lock)
  */
 void ata_qc_free(struct ata_queued_cmd *qc)
 {
 	struct ata_port *ap;
 	unsigned int tag;
 	WARN_ON_ONCE(qc == NULL); /* ata_qc_from_tag _might_ return NULL */
 	ap = qc->ap;
 	qc->flags = 0;
 	tag = qc->tag;
 	if (likely(ata_tag_valid(tag))) {
 		qc->tag = ATA_TAG_POISON;
 		clear_bit(tag, &ap->qc_allocated);
 	}
 }
 void __ata_qc_complete(struct ata_queued_cmd *qc)
 {
 	struct ata_port *ap;
 	struct ata_link *link;
 	WARN_ON_ONCE(qc == NULL); /* ata_qc_from_tag _might_ return NULL */
 	WARN_ON_ONCE(!(qc->flags & ATA_QCFLAG_ACTIVE));
 	ap = qc->ap;
 	link = qc->dev->link;
 	if (likely(qc->flags & ATA_QCFLAG_DMAMAP))
 		ata_sg_clean(qc);
 	/* command should be marked inactive atomically with qc completion */
 	if (qc->tf.protocol == ATA_PROT_NCQ) {
 		link->sactive &= ~(1 << qc->tag);
 		if (!link->sactive)
 			ap->nr_active_links--;
 	} else {
 		link->active_tag = ATA_TAG_POISON;
 		ap->nr_active_links--;
 	}
 	/* clear exclusive status */
 	if (unlikely(qc->flags & ATA_QCFLAG_CLEAR_EXCL &&
 		     ap->excl_link == link))
 		ap->excl_link = NULL;
 	/* atapi: mark qc as inactive to prevent the interrupt handler
 	 * from completing the command twice later, before the error handler
 	 * is called. (when rc != 0 and atapi request sense is needed)
 	 */
 	qc->flags &= ~ATA_QCFLAG_ACTIVE;
 	ap->qc_active &= ~(1 << qc->tag);
 	/* call completion callback */
 	qc->complete_fn(qc);
 }
 static void fill_result_tf(struct ata_queued_cmd *qc)
 {
 	struct ata_port *ap = qc->ap;
 	qc->result_tf.flags = qc->tf.flags;
 	ap->ops->qc_fill_rtf(qc);
 }
 static void ata_verify_xfer(struct ata_queued_cmd *qc)
 {
 	struct ata_device *dev = qc->dev;
 	if (ata_tag_internal(qc->tag))
 		return;
 	if (ata_is_nodata(qc->tf.protocol))
 		return;
 	if ((dev->mwdma_mask || dev->udma_mask) && ata_is_pio(qc->tf.protocol))
 		return;
 	dev->flags &= ~ATA_DFLAG_DUBIOUS_XFER;
 }
 /**
  *	ata_qc_complete - Complete an active ATA command
  *	@qc: Command to complete
  *
  *	Indicate to the mid and upper layers that an ATA
  *	command has completed, with either an ok or not-ok status.
  *
  *	LOCKING:
  *	spin_lock_irqsave(host lock)
  */
 void ata_qc_complete(struct ata_queued_cmd *qc)
 {
 	struct ata_port *ap = qc->ap;
 	/* XXX: New EH and old EH use different mechanisms to
 	 * synchronize EH with regular execution path.
 	 *
 	 * In new EH, a failed qc is marked with ATA_QCFLAG_FAILED.
 	 * Normal execution path is responsible for not accessing a
 	 * failed qc.  libata core enforces the rule by returning NULL
 	 * from ata_qc_from_tag() for failed qcs.
 	 *
 	 * Old EH depends on ata_qc_complete() nullifying completion
 	 * requests if ATA_QCFLAG_EH_SCHEDULED is set.  Old EH does
 	 * not synchronize with interrupt handler.  Only PIO task is
 	 * taken care of.
 	 */
 	if (ap->ops->error_handler) {
 		struct ata_device *dev = qc->dev;
 		struct ata_eh_info *ehi = &dev->link->eh_info;
 		if (unlikely(qc->err_mask))
 			qc->flags |= ATA_QCFLAG_FAILED;
 		if (unlikely(qc->flags & ATA_QCFLAG_FAILED)) {
 			/* always fill result TF for failed qc */
 			fill_result_tf(qc);
 			if (!ata_tag_internal(qc->tag))
 				ata_qc_schedule_eh(qc);
 			else
 				__ata_qc_complete(qc);
 			return;
 		}
 		WARN_ON_ONCE(ap->pflags & ATA_PFLAG_FROZEN);
 		/* read result TF if requested */
 		if (qc->flags & ATA_QCFLAG_RESULT_TF)
 			fill_result_tf(qc);
 		/* Some commands need post-processing after successful
 		 * completion.
 		 */
 		switch (qc->tf.command) {
 		case ATA_CMD_SET_FEATURES:
 			if (qc->tf.feature != SETFEATURES_WC_ON &&
 			    qc->tf.feature != SETFEATURES_WC_OFF)
 				break;
 			/* fall through */
 		case ATA_CMD_INIT_DEV_PARAMS: /* CHS translation changed */
 		case ATA_CMD_SET_MULTI: /* multi_count changed */
 			/* revalidate device */
 			ehi->dev_action[dev->devno] |= ATA_EH_REVALIDATE;
 			ata_port_schedule_eh(ap);
 			break;
 		case ATA_CMD_SLEEP:
 			dev->flags |= ATA_DFLAG_SLEEPING;
 			break;
 		}
 		if (unlikely(dev->flags & ATA_DFLAG_DUBIOUS_XFER))
 			ata_verify_xfer(qc);
 		__ata_qc_complete(qc);
 	} else {
 		if (qc->flags & ATA_QCFLAG_EH_SCHEDULED)
 			return;
 		/* read result TF if failed or requested */
 		if (qc->err_mask || qc->flags & ATA_QCFLAG_RESULT_TF)
 			fill_result_tf(qc);
 		__ata_qc_complete(qc);
 	}
 }
 /**
  *	ata_qc_complete_multiple - Complete multiple qcs successfully
  *	@ap: port in question
  *	@qc_active: new qc_active mask
  *
  *	Complete in-flight commands.  This functions is meant to be
  *	called from low-level driver's interrupt routine to complete
  *	requests normally.  ap->qc_active and @qc_active is compared
  *	and commands are completed accordingly.
  *
  *	LOCKING:
  *	spin_lock_irqsave(host lock)
  *
  *	RETURNS:
  *	Number of completed commands on success, -errno otherwise.
  */
 int ata_qc_complete_multiple(struct ata_port *ap, u32 qc_active)
 {
 	int nr_done = 0;
 	u32 done_mask;
 	done_mask = ap->qc_active ^ qc_active;
 	if (unlikely(done_mask & qc_active)) {
 		ata_port_printk(ap, KERN_ERR, "illegal qc_active transition "
 				"(%08x->%08x)\n", ap->qc_active, qc_active);
 		return -EINVAL;
 	}
 	while (done_mask) {
 		struct ata_queued_cmd *qc;
 		unsigned int tag = __ffs(done_mask);
 		qc = ata_qc_from_tag(ap, tag);
 		if (qc) {
 			ata_qc_complete(qc);
 			nr_done++;
 		}
 		done_mask &= ~(1 << tag);
 	}
 	return nr_done;
 }
 /**
  *	ata_qc_issue - issue taskfile to device
  *	@qc: command to issue to device
  *
  *	Prepare an ATA command to submission to device.
  *	This includes mapping the data into a DMA-able
  *	area, filling in the S/G table, and finally
  *	writing the taskfile to hardware, starting the command.
  *
  *	LOCKING:
  *	spin_lock_irqsave(host lock)
  */
 void ata_qc_issue(struct ata_queued_cmd *qc)
 {
 	struct ata_port *ap = qc->ap;
 	struct ata_link *link = qc->dev->link;
 	u8 prot = qc->tf.protocol;
 	/* Make sure only one non-NCQ command is outstanding.  The
 	 * check is skipped for old EH because it reuses active qc to
 	 * request ATAPI sense.
 	 */
 	WARN_ON_ONCE(ap->ops->error_handler && ata_tag_valid(link->active_tag));
 	if (ata_is_ncq(prot)) {
 		WARN_ON_ONCE(link->sactive & (1 << qc->tag));
 		if (!link->sactive)
 			ap->nr_active_links++;
 		link->sactive |= 1 << qc->tag;
 	} else {
 		WARN_ON_ONCE(link->sactive);
 		ap->nr_active_links++;
 		link->active_tag = qc->tag;
 	}
 	qc->flags |= ATA_QCFLAG_ACTIVE;
 	ap->qc_active |= 1 << qc->tag;
 	/*
 	 * We guarantee to LLDs that they will have at least one
 	 * non-zero sg if the command is a data command.
 	 */
 	if (WARN_ON_ONCE(ata_is_data(prot) &&
 			 (!qc->sg || !qc->n_elem || !qc->nbytes)))
 		goto sys_err;
 	if (ata_is_dma(prot) || (ata_is_pio(prot) &&
 				 (ap->flags & ATA_FLAG_PIO_DMA)))
 		if (ata_sg_setup(qc))
 			goto sys_err;
 	/* if device is sleeping, schedule reset and abort the link */
 	if (unlikely(qc->dev->flags & ATA_DFLAG_SLEEPING)) {
 		link->eh_info.action |= ATA_EH_RESET;
 		ata_ehi_push_desc(&link->eh_info, "waking up from sleep");
 		ata_link_abort(link);
 		return;
 	}
 	ap->ops->qc_prep(qc);
 	qc->err_mask |= ap->ops->qc_issue(qc);
 	if (unlikely(qc->err_mask))
 		goto err;
 	return;
 sys_err:
 	qc->err_mask |= AC_ERR_SYSTEM;
 err:
 	ata_qc_complete(qc);
 }
 /**
  *	sata_scr_valid - test whether SCRs are accessible
  *	@link: ATA link to test SCR accessibility for
  *
  *	Test whether SCRs are accessible for @link.
  *
  *	LOCKING:
  *	None.
  *
  *	RETURNS:
  *	1 if SCRs are accessible, 0 otherwise.
  */
 int sata_scr_valid(struct ata_link *link)
 {
 	struct ata_port *ap = link->ap;
 	return (ap->flags & ATA_FLAG_SATA) && ap->ops->scr_read;
 }
 /**
  *	sata_scr_read - read SCR register of the specified port
  *	@link: ATA link to read SCR for
  *	@reg: SCR to read
  *	@val: Place to store read value
  *
  *	Read SCR register @reg of @link into *@val.  This function is
  *	guaranteed to succeed if @link is ap->link, the cable type of
  *	the port is SATA and the port implements ->scr_read.
  *
  *	LOCKING:
  *	None if @link is ap->link.  Kernel thread context otherwise.
  *
  *	RETURNS:
  *	0 on success, negative errno on failure.
  */
 int sata_scr_read(struct ata_link *link, int reg, u32 *val)
 {
 	if (ata_is_host_link(link)) {
 		if (sata_scr_valid(link))
 			return link->ap->ops->scr_read(link, reg, val);
 		return -EOPNOTSUPP;
 	}
 	return sata_pmp_scr_read(link, reg, val);
 }
 /**
  *	sata_scr_write - write SCR register of the specified port
  *	@link: ATA link to write SCR for
  *	@reg: SCR to write
  *	@val: value to write
  *
  *	Write @val to SCR register @reg of @link.  This function is
  *	guaranteed to succeed if @link is ap->link, the cable type of
  *	the port is SATA and the port implements ->scr_read.
  *
  *	LOCKING:
  *	None if @link is ap->link.  Kernel thread context otherwise.
  *
  *	RETURNS:
  *	0 on success, negative errno on failure.
  */
 int sata_scr_write(struct ata_link *link, int reg, u32 val)
 {
 	if (ata_is_host_link(link)) {
 		if (sata_scr_valid(link))
 			return link->ap->ops->scr_write(link, reg, val);
 		return -EOPNOTSUPP;
 	}
 	return sata_pmp_scr_write(link, reg, val);
 }
 /**
  *	sata_scr_write_flush - write SCR register of the specified port and flush
  *	@link: ATA link to write SCR for
  *	@reg: SCR to write
  *	@val: value to write
  *
  *	This function is identical to sata_scr_write() except that this
  *	function performs flush after writing to the register.
  *
  *	LOCKING:
  *	None if @link is ap->link.  Kernel thread context otherwise.
  *
  *	RETURNS:
  *	0 on success, negative errno on failure.
  */
 int sata_scr_write_flush(struct ata_link *link, int reg, u32 val)
 {
 	if (ata_is_host_link(link)) {
 		int rc;
 		if (sata_scr_valid(link)) {
 			rc = link->ap->ops->scr_write(link, reg, val);
 			if (rc == 0)
 				rc = link->ap->ops->scr_read(link, reg, &val);
 			return rc;
 		}
 		return -EOPNOTSUPP;
 	}
 	return sata_pmp_scr_write(link, reg, val);
 }
 /**
  *	ata_phys_link_online - test whether the given link is online
  *	@link: ATA link to test
  *
  *	Test whether @link is online.  Note that this function returns
  *	0 if online status of @link cannot be obtained, so
  *	ata_link_online(link) != !ata_link_offline(link).
  *
  *	LOCKING:
  *	None.
  *
  *	RETURNS:
  *	True if the port online status is available and online.
  */
 bool ata_phys_link_online(struct ata_link *link)
 {
 	u32 sstatus;
 	if (sata_scr_read(link, SCR_STATUS, &sstatus) == 0 &&
 	    ata_sstatus_online(sstatus))
 		return true;
 	return false;
 }
 /**
  *	ata_phys_link_offline - test whether the given link is offline
  *	@link: ATA link to test
  *
  *	Test whether @link is offline.  Note that this function
  *	returns 0 if offline status of @link cannot be obtained, so
  *	ata_link_online(link) != !ata_link_offline(link).
  *
  *	LOCKING:
  *	None.
  *
  *	RETURNS:
  *	True if the port offline status is available and offline.
  */
 bool ata_phys_link_offline(struct ata_link *link)
 {
 	u32 sstatus;
 	if (sata_scr_read(link, SCR_STATUS, &sstatus) == 0 &&
 	    !ata_sstatus_online(sstatus))
 		return true;
 	return false;
 }
 /**
  *	ata_link_online - test whether the given link is online
  *	@link: ATA link to test
  *
  *	Test whether @link is online.  This is identical to
  *	ata_phys_link_online() when there's no slave link.  When
  *	there's a slave link, this function should only be called on
  *	the master link and will return true if any of M/S links is
  *	online.
  *
  *	LOCKING:
  *	None.
  *
  *	RETURNS:
  *	True if the port online status is available and online.
  */
 bool ata_link_online(struct ata_link *link)
 {
 	struct ata_link *slave = link->ap->slave_link;
 	WARN_ON(link == slave);	/* shouldn't be called on slave link */
 	return ata_phys_link_online(link) ||
 		(slave && ata_phys_link_online(slave));
 }
 /**
  *	ata_link_offline - test whether the given link is offline
  *	@link: ATA link to test
  *
  *	Test whether @link is offline.  This is identical to
  *	ata_phys_link_offline() when there's no slave link.  When
  *	there's a slave link, this function should only be called on
  *	the master link and will return true if both M/S links are
  *	offline.
  *
  *	LOCKING:
  *	None.
  *
  *	RETURNS:
  *	True if the port offline status is available and offline.
  */
 bool ata_link_offline(struct ata_link *link)
 {
 	struct ata_link *slave = link->ap->slave_link;
 	WARN_ON(link == slave);	/* shouldn't be called on slave link */
 	return ata_phys_link_offline(link) &&
 		(!slave || ata_phys_link_offline(slave));
 }
 #ifdef CONFIG_PM
 static int ata_host_request_pm(struct ata_host *host, pm_message_t mesg,
 			       unsigned int action, unsigned int ehi_flags,
 			       int wait)
 {
 	unsigned long flags;
 	int i, rc;
 	for (i = 0; i < host->n_ports; i++) {
 		struct ata_port *ap = host->ports[i];
 		struct ata_link *link;
 		/* Previous resume operation might still be in
 		 * progress.  Wait for PM_PENDING to clear.
 		 */
 		if (ap->pflags & ATA_PFLAG_PM_PENDING) {
 			ata_port_wait_eh(ap);
 			WARN_ON(ap->pflags & ATA_PFLAG_PM_PENDING);
 		}
 		/* request PM ops to EH */
 		spin_lock_irqsave(ap->lock, flags);
 		ap->pm_mesg = mesg;
 		if (wait) {
 			rc = 0;
 			ap->pm_result = &rc;
 		}
 		ap->pflags |= ATA_PFLAG_PM_PENDING;
 		ata_for_each_link(link, ap, HOST_FIRST) {
 			link->eh_info.action |= action;
 			link->eh_info.flags |= ehi_flags;
 		}
 		ata_port_schedule_eh(ap);
 		spin_unlock_irqrestore(ap->lock, flags);
 		/* wait and check result */
 		if (wait) {
 			ata_port_wait_eh(ap);
 			WARN_ON(ap->pflags & ATA_PFLAG_PM_PENDING);
 			if (rc)
 				return rc;
 		}
 	}
 	return 0;
 }
 /**
  *	ata_host_suspend - suspend host
  *	@host: host to suspend
  *	@mesg: PM message
  *
  *	Suspend @host.  Actual operation is performed by EH.  This
  *	function requests EH to perform PM operations and waits for EH
  *	to finish.
  *
  *	LOCKING:
  *	Kernel thread context (may sleep).
  *
  *	RETURNS:
  *	0 on success, -errno on failure.
  */
 int ata_host_suspend(struct ata_host *host, pm_message_t mesg)
 {
+	unsigned int ehi_flags = ATA_EHI_QUIET;
 	int rc;
 	/*
 	 * disable link pm on all ports before requesting
 	 * any pm activity
 	 */
 	ata_lpm_enable(host);
-	rc = ata_host_request_pm(host, mesg, 0, ATA_EHI_QUIET, 1);
+	/*
+	 * On some hardware, device fails to respond after spun down
+	 * for suspend.  As the device won't be used before being
+	 * resumed, we don't need to touch the device.  Ask EH to skip
+	 * the usual stuff and proceed directly to suspend.
+	 *
+	 * http://thread.gmane.org/gmane.linux.ide/46764
+	 */
+	if (mesg.event == PM_EVENT_SUSPEND)
+		ehi_flags |= ATA_EHI_NO_AUTOPSY | ATA_EHI_NO_RECOVERY;
+	rc = ata_host_request_pm(host, mesg, 0, ehi_flags, 1);
 	if (rc == 0)
 		host->dev->power.power_state = mesg;
 	return rc;
 }
 /**
  *	ata_host_resume - resume host
  *	@host: host to resume
  *
  *	Resume @host.  Actual operation is performed by EH.  This
  *	function requests EH to perform PM operations and returns.
  *	Note that all resume operations are performed parallely.
  *
  *	LOCKING:
  *	Kernel thread context (may sleep).
  */
 void ata_host_resume(struct ata_host *host)
 {
 	ata_host_request_pm(host, PMSG_ON, ATA_EH_RESET,
 			    ATA_EHI_NO_AUTOPSY | ATA_EHI_QUIET, 0);
 	host->dev->power.power_state = PMSG_ON;
 	/* reenable link pm */
 	ata_lpm_disable(host);
 }
 #endif
 /**
  *	ata_dev_init - Initialize an ata_device structure
  *	@dev: Device structure to initialize
  *
  *	Initialize @dev in preparation for probing.
  *
  *	LOCKING:
  *	Inherited from caller.
  */
 void ata_dev_init(struct ata_device *dev)
 {
 	struct ata_link *link = ata_dev_phys_link(dev);
 	struct ata_port *ap = link->ap;
 	unsigned long flags;
 	/* SATA spd limit is bound to the attached device, reset together */
 	link->sata_spd_limit = link->hw_sata_spd_limit;
 	link->sata_spd = 0;
 	/* High bits of dev->flags are used to record warm plug
 	 * requests which occur asynchronously.  Synchronize using
 	 * host lock.
 	 */
 	spin_lock_irqsave(ap->lock, flags);
 	dev->flags &= ~ATA_DFLAG_INIT_MASK;
 	dev->horkage = 0;
 	spin_unlock_irqrestore(ap->lock, flags);
 	memset((void *)dev + ATA_DEVICE_CLEAR_BEGIN, 0,
 	       ATA_DEVICE_CLEAR_END - ATA_DEVICE_CLEAR_BEGIN);
 	dev->pio_mask = UINT_MAX;
 	dev->mwdma_mask = UINT_MAX;
 	dev->udma_mask = UINT_MAX;
 }
 /**
  *	ata_link_init - Initialize an ata_link structure
  *	@ap: ATA port link is attached to
  *	@link: Link structure to initialize
  *	@pmp: Port multiplier port number
  *
  *	Initialize @link.
  *
  *	LOCKING:
  *	Kernel thread context (may sleep)
  */
 void ata_link_init(struct ata_port *ap, struct ata_link *link, int pmp)
 {
 	int i;
 	/* clear everything except for devices */
 	memset(link, 0, offsetof(struct ata_link, device[0]));
 	link->ap = ap;
 	link->pmp = pmp;
 	link->active_tag = ATA_TAG_POISON;
 	link->hw_sata_spd_limit = UINT_MAX;
 	/* can't use iterator, ap isn't initialized yet */
 	for (i = 0; i < ATA_MAX_DEVICES; i++) {
 		struct ata_device *dev = &link->device[i];
 		dev->link = link;
 		dev->devno = dev - link->device;
 #ifdef CONFIG_ATA_ACPI
 		dev->gtf_filter = ata_acpi_gtf_filter;
 #endif
 		ata_dev_init(dev);
 	}
 }
 /**
  *	sata_link_init_spd - Initialize link->sata_spd_limit
  *	@link: Link to configure sata_spd_limit for
  *
  *	Initialize @link->[hw_]sata_spd_limit to the currently
  *	configured value.
  *
  *	LOCKING:
  *	Kernel thread context (may sleep).
  *
  *	RETURNS:
  *	0 on success, -errno on failure.
  */
 int sata_link_init_spd(struct ata_link *link)
 {
 	u8 spd;
 	int rc;
 	rc = sata_scr_read(link, SCR_CONTROL, &link->saved_scontrol);
 	if (rc)
 		return rc;
 	spd = (link->saved_scontrol >> 4) & 0xf;
 	if (spd)
 		link->hw_sata_spd_limit &= (1 << spd) - 1;
 	ata_force_link_limits(link);
 	link->sata_spd_limit = link->hw_sata_spd_limit;
 	return 0;
 }
 /**
  *	ata_port_alloc - allocate and initialize basic ATA port resources
  *	@host: ATA host this allocated port belongs to
  *
  *	Allocate and initialize basic ATA port resources.
  *
  *	RETURNS:
  *	Allocate ATA port on success, NULL on failure.
  *
  *	LOCKING:
  *	Inherited from calling layer (may sleep).
  */
 struct ata_port *ata_port_alloc(struct ata_host *host)
 {
 	struct ata_port *ap;
 	DPRINTK("ENTER\n");
 	ap = kzalloc(sizeof(*ap), GFP_KERNEL);
 	if (!ap)
 		return NULL;
 	ap->pflags |= ATA_PFLAG_INITIALIZING;
 	ap->lock = &host->lock;
 	ap->print_id = -1;
 	ap->host = host;
 	ap->dev = host->dev;
 #if defined(ATA_VERBOSE_DEBUG)
 	/* turn on all debugging levels */
 	ap->msg_enable = 0x00FF;
 #elif defined(ATA_DEBUG)
 	ap->msg_enable = ATA_MSG_DRV | ATA_MSG_INFO | ATA_MSG_CTL | ATA_MSG_WARN | ATA_MSG_ERR;
 #else
 	ap->msg_enable = ATA_MSG_DRV | ATA_MSG_ERR | ATA_MSG_WARN;
 #endif
 	mutex_init(&ap->scsi_scan_mutex);
 	INIT_DELAYED_WORK(&ap->hotplug_task, ata_scsi_hotplug);
 	INIT_WORK(&ap->scsi_rescan_task, ata_scsi_dev_rescan);
 	INIT_LIST_HEAD(&ap->eh_done_q);
 	init_waitqueue_head(&ap->eh_wait_q);
 	init_completion(&ap->park_req_pending);
 	init_timer_deferrable(&ap->fastdrain_timer);
 	ap->fastdrain_timer.function = ata_eh_fastdrain_timerfn;
 	ap->fastdrain_timer.data = (unsigned long)ap;
 	ap->cbl = ATA_CBL_NONE;
 	ata_link_init(ap, &ap->link, 0);
 #ifdef ATA_IRQ_TRAP
 	ap->stats.unhandled_irq = 1;
 	ap->stats.idle_irq = 1;
 #endif
 	ata_sff_port_init(ap);
 	return ap;
 }
 static void ata_host_release(struct device *gendev, void *res)
 {
 	struct ata_host *host = dev_get_drvdata(gendev);
 	int i;
 	for (i = 0; i < host->n_ports; i++) {
 		struct ata_port *ap = host->ports[i];
 		if (!ap)
 			continue;
 		if (ap->scsi_host)
 			scsi_host_put(ap->scsi_host);
 		kfree(ap->pmp_link);
 		kfree(ap->slave_link);
 		kfree(ap);
 		host->ports[i] = NULL;
 	}
 	dev_set_drvdata(gendev, NULL);
 }
 /**
  *	ata_host_alloc - allocate and init basic ATA host resources
  *	@dev: generic device this host is associated with
  *	@max_ports: maximum number of ATA ports associated with this host
  *
  *	Allocate and initialize basic ATA host resources.  LLD calls
  *	this function to allocate a host, initializes it fully and
  *	attaches it using ata_host_register().
  *
  *	@max_ports ports are allocated and host->n_ports is
  *	initialized to @max_ports.  The caller is allowed to decrease
  *	host->n_ports before calling ata_host_register().  The unused
  *	ports will be automatically freed on registration.
  *
  *	RETURNS:
  *	Allocate ATA host on success, NULL on failure.
  *
  *	LOCKING:
  *	Inherited from calling layer (may sleep).
  */
 struct ata_host *ata_host_alloc(struct device *dev, int max_ports)
 {
 	struct ata_host *host;
 	size_t sz;
 	int i;
 	DPRINTK("ENTER\n");
 	if (!devres_open_group(dev, NULL, GFP_KERNEL))
 		return NULL;
 	/* alloc a container for our list of ATA ports (buses) */
 	sz = sizeof(struct ata_host) + (max_ports + 1) * sizeof(void *);
 	/* alloc a container for our list of ATA ports (buses) */
 	host = devres_alloc(ata_host_release, sz, GFP_KERNEL);
 	if (!host)
 		goto err_out;
 	devres_add(dev, host);
 	dev_set_drvdata(dev, host);
 	spin_lock_init(&host->lock);
 	host->dev = dev;
 	host->n_ports = max_ports;
 	/* allocate ports bound to this host */
 	for (i = 0; i < max_ports; i++) {
 		struct ata_port *ap;
 		ap = ata_port_alloc(host);
 		if (!ap)
 			goto err_out;
 		ap->port_no = i;
 		host->ports[i] = ap;
 	}
 	devres_remove_group(dev, NULL);
 	return host;
  err_out:
 	devres_release_group(dev, NULL);
 	return NULL;
 }
 /**
  *	ata_host_alloc_pinfo - alloc host and init with port_info array
  *	@dev: generic device this host is associated with
  *	@ppi: array of ATA port_info to initialize host with
  *	@n_ports: number of ATA ports attached to this host
  *
  *	Allocate ATA host and initialize with info from @ppi.  If NULL
  *	terminated, @ppi may contain fewer entries than @n_ports.  The
  *	last entry will be used for the remaining ports.
  *
  *	RETURNS:
  *	Allocate ATA host on success, NULL on failure.
  *
  *	LOCKING:
  *	Inherited from calling layer (may sleep).
  */
 struct ata_host *ata_host_alloc_pinfo(struct device *dev,
 				      const struct ata_port_info * const * ppi,
 				      int n_ports)
 {
 	const struct ata_port_info *pi;
 	struct ata_host *host;
 	int i, j;
 	host = ata_host_alloc(dev, n_ports);
 	if (!host)
 		return NULL;
 	for (i = 0, j = 0, pi = NULL; i < host->n_ports; i++) {
 		struct ata_port *ap = host->ports[i];
 		if (ppi[j])
 			pi = ppi[j++];
 		ap->pio_mask = pi->pio_mask;
 		ap->mwdma_mask = pi->mwdma_mask;
 		ap->udma_mask = pi->udma_mask;
 		ap->flags |= pi->flags;
 		ap->link.flags |= pi->link_flags;
 		ap->ops = pi->port_ops;
 		if (!host->ops && (pi->port_ops != &ata_dummy_port_ops))
 			host->ops = pi->port_ops;
 	}
 	return host;
 }
 /**
  *	ata_slave_link_init - initialize slave link
  *	@ap: port to initialize slave link for
  *
  *	Create and initialize slave link for @ap.  This enables slave
  *	link handling on the port.
  *
  *	In libata, a port contains links and a link contains devices.
  *	There is single host link but if a PMP is attached to it,
  *	there can be multiple fan-out links.  On SATA, there's usually
  *	a single device connected to a link but PATA and SATA
  *	controllers emulating TF based interface can have two - master
  *	and slave.
  *
  *	However, there are a few controllers which don't fit into this
  *	abstraction too well - SATA controllers which emulate TF
  *	interface with both master and slave devices but also have
  *	separate SCR register sets for each device.  These controllers
  *	need separate links for physical link handling
  *	(e.g. onlineness, link speed) but should be treated like a
  *	traditional M/S controller for everything else (e.g. command
  *	issue, softreset).
  *
  *	slave_link is libata's way of handling this class of
  *	controllers without impacting core layer too much.  For
  *	anything other than physical link handling, the default host
  *	link is used for both master and slave.  For physical link
  *	handling, separate @ap->slave_link is used.  All dirty details
  *	are implemented inside libata core layer.  From LLD's POV, the
  *	only difference is that prereset, hardreset and postreset are
  *	called once more for the slave link, so the reset sequence
  *	looks like the following.
  *
  *	prereset(M) -> prereset(S) -> hardreset(M) -> hardreset(S) ->
  *	softreset(M) -> postreset(M) -> postreset(S)
  *
  *	Note that softreset is called only for the master.  Softreset
  *	resets both M/S by definition, so SRST on master should handle
  *	both (the standard method will work just fine).
  *
  *	LOCKING:
  *	Should be called before host is registered.
  *
  *	RETURNS:
  *	0 on success, -errno on failure.
  */
 int ata_slave_link_init(struct ata_port *ap)
 {
 	struct ata_link *link;
 	WARN_ON(ap->slave_link);
 	WARN_ON(ap->flags & ATA_FLAG_PMP);
 	link = kzalloc(sizeof(*link), GFP_KERNEL);
 	if (!link)
 		return -ENOMEM;
 	ata_link_init(ap, link, 1);
 	ap->slave_link = link;
 	return 0;
 }
 static void ata_host_stop(struct device *gendev, void *res)
 {
 	struct ata_host *host = dev_get_drvdata(gendev);
 	int i;
 	WARN_ON(!(host->flags & ATA_HOST_STARTED));
 	for (i = 0; i < host->n_ports; i++) {
 		struct ata_port *ap = host->ports[i];
 		if (ap->ops->port_stop)
 			ap->ops->port_stop(ap);
 	}
 	if (host->ops->host_stop)
 		host->ops->host_stop(host);
 }
 /**
  *	ata_finalize_port_ops - finalize ata_port_operations
  *	@ops: ata_port_operations to finalize
  *
  *	An ata_port_operations can inherit from another ops and that
  *	ops can again inherit from another.  This can go on as many
  *	times as necessary as long as there is no loop in the
  *	inheritance chain.
  *
  *	Ops tables are finalized when the host is started.  NULL or
  *	unspecified entries are inherited from the closet ancestor
  *	which has the method and the entry is populated with it.
  *	After finalization, the ops table directly points to all the
  *	methods and ->inherits is no longer necessary and cleared.
  *
  *	Using ATA_OP_NULL, inheriting ops can force a method to NULL.
  *
  *	LOCKING:
  *	None.
  */
 static void ata_finalize_port_ops(struct ata_port_operations *ops)
 {
 	static DEFINE_SPINLOCK(lock);
 	const struct ata_port_operations *cur;
 	void **begin = (void **)ops;
 	void **end = (void **)&ops->inherits;
 	void **pp;
 	if (!ops || !ops->inherits)
 		return;
 	spin_lock(&lock);
 	for (cur = ops->inherits; cur; cur = cur->inherits) {
 		void **inherit = (void **)cur;
 		for (pp = begin; pp < end; pp++, inherit++)
 			if (!*pp)
 				*pp = *inherit;
 	}
 	for (pp = begin; pp < end; pp++)
 		if (IS_ERR(*pp))
 			*pp = NULL;
 	ops->inherits = NULL;
 	spin_unlock(&lock);
 }
 /**
  *	ata_host_start - start and freeze ports of an ATA host
  *	@host: ATA host to start ports for
  *
  *	Start and then freeze ports of @host.  Started status is
  *	recorded in host->flags, so this function can be called
  *	multiple times.  Ports are guaranteed to get started only
  *	once.  If host->ops isn't initialized yet, its set to the
  *	first non-dummy port ops.
  *
  *	LOCKING:
  *	Inherited from calling layer (may sleep).
  *
  *	RETURNS:
  *	0 if all ports are started successfully, -errno otherwise.
  */
 int ata_host_start(struct ata_host *host)
 {
 	int have_stop = 0;
 	void *start_dr = NULL;
 	int i, rc;
 	if (host->flags & ATA_HOST_STARTED)
 		return 0;
 	ata_finalize_port_ops(host->ops);
 	for (i = 0; i < host->n_ports; i++) {
 		struct ata_port *ap = host->ports[i];
 		ata_finalize_port_ops(ap->ops);
 		if (!host->ops && !ata_port_is_dummy(ap))
 			host->ops = ap->ops;
 		if (ap->ops->port_stop)
 			have_stop = 1;
 	}
 	if (host->ops->host_stop)
 		have_stop = 1;
 	if (have_stop) {
 		start_dr = devres_alloc(ata_host_stop, 0, GFP_KERNEL);
 		if (!start_dr)
 			return -ENOMEM;
 	}
 	for (i = 0; i < host->n_ports; i++) {
 		struct ata_port *ap = host->ports[i];
 		if (ap->ops->port_start) {
 			rc = ap->ops->port_start(ap);
 			if (rc) {
 				if (rc != -ENODEV)
 					dev_printk(KERN_ERR, host->dev,
 						"failed to start port %d "
 						"(errno=%d)\n", i, rc);
 				goto err_out;
 			}
 		}
 		ata_eh_freeze_port(ap);
 	}
 	if (start_dr)
 		devres_add(host->dev, start_dr);
 	host->flags |= ATA_HOST_STARTED;
 	return 0;
  err_out:
 	while (--i >= 0) {
 		struct ata_port *ap = host->ports[i];
 		if (ap->ops->port_stop)
 			ap->ops->port_stop(ap);
 	}
 	devres_free(start_dr);
 	return rc;
 }
 /**
  *	ata_sas_host_init - Initialize a host struct
  *	@host:	host to initialize
  *	@dev:	device host is attached to
  *	@flags:	host flags
  *	@ops:	port_ops
  *
  *	LOCKING:
  *	PCI/etc. bus probe sem.
  *
  */
 /* KILLME - the only user left is ipr */
 void ata_host_init(struct ata_host *host, struct device *dev,
 		   unsigned long flags, struct ata_port_operations *ops)
 {
 	spin_lock_init(&host->lock);
 	host->dev = dev;
 	host->flags = flags;
 	host->ops = ops;
 }
 static void async_port_probe(void *data, async_cookie_t cookie)
 {
 	int rc;
 	struct ata_port *ap = data;
 	/*
 	 * If we're not allowed to scan this host in parallel,
 	 * we need to wait until all previous scans have completed
 	 * before going further.
 	 * Jeff Garzik says this is only within a controller, so we
 	 * don't need to wait for port 0, only for later ports.
 	 */
 	if (!(ap->host->flags & ATA_HOST_PARALLEL_SCAN) && ap->port_no != 0)
 		async_synchronize_cookie(cookie);
 	/* probe */
 	if (ap->ops->error_handler) {
 		struct ata_eh_info *ehi = &ap->link.eh_info;
 		unsigned long flags;
 		/* kick EH for boot probing */
 		spin_lock_irqsave(ap->lock, flags);
 		ehi->probe_mask |= ATA_ALL_DEVICES;
 		ehi->action |= ATA_EH_RESET | ATA_EH_LPM;
 		ehi->flags |= ATA_EHI_NO_AUTOPSY | ATA_EHI_QUIET;
 		ap->pflags &= ~ATA_PFLAG_INITIALIZING;
 		ap->pflags |= ATA_PFLAG_LOADING;
 		ata_port_schedule_eh(ap);
 		spin_unlock_irqrestore(ap->lock, flags);
 		/* wait for EH to finish */
 		ata_port_wait_eh(ap);
 	} else {
 		DPRINTK("ata%u: bus probe begin\n", ap->print_id);
 		rc = ata_bus_probe(ap);
 		DPRINTK("ata%u: bus probe end\n", ap->print_id);
 		if (rc) {
 			/* FIXME: do something useful here?
 			 * Current libata behavior will
 			 * tear down everything when
 			 * the module is removed
 			 * or the h/w is unplugged.
 			 */
 		}
 	}
 	/* in order to keep device order, we need to synchronize at this point */
 	async_synchronize_cookie(cookie);
 	ata_scsi_scan_host(ap, 1);
 }
 /**
  *	ata_host_register - register initialized ATA host
  *	@host: ATA host to register
  *	@sht: template for SCSI host
  *
  *	Register initialized ATA host.  @host is allocated using
  *	ata_host_alloc() and fully initialized by LLD.  This function
  *	starts ports, registers @host with ATA and SCSI layers and
  *	probe registered devices.
  *
  *	LOCKING:
  *	Inherited from calling layer (may sleep).
  *
  *	RETURNS:
  *	0 on success, -errno otherwise.
  */
 int ata_host_register(struct ata_host *host, struct scsi_host_template *sht)
 {
 	int i, rc;
 	/* host must have been started */
 	if (!(host->flags & ATA_HOST_STARTED)) {
 		dev_printk(KERN_ERR, host->dev,
 			   "BUG: trying to register unstarted host\n");
 		WARN_ON(1);
 		return -EINVAL;
 	}
 	/* Blow away unused ports.  This happens when LLD can't
 	 * determine the exact number of ports to allocate at
 	 * allocation time.
 	 */
 	for (i = host->n_ports; host->ports[i]; i++)
 		kfree(host->ports[i]);
 	/* give ports names and add SCSI hosts */
 	for (i = 0; i < host->n_ports; i++)
 		host->ports[i]->print_id = ata_print_id++;
 	rc = ata_scsi_add_hosts(host, sht);
 	if (rc)
 		return rc;
 	/* associate with ACPI nodes */
 	ata_acpi_associate(host);
 	/* set cable, sata_spd_limit and report */
 	for (i = 0; i < host->n_ports; i++) {
 		struct ata_port *ap = host->ports[i];
 		unsigned long xfer_mask;
 		/* set SATA cable type if still unset */
 		if (ap->cbl == ATA_CBL_NONE && (ap->flags & ATA_FLAG_SATA))
 			ap->cbl = ATA_CBL_SATA;
 		/* init sata_spd_limit to the current value */
 		sata_link_init_spd(&ap->link);
 		if (ap->slave_link)
 			sata_link_init_spd(ap->slave_link);
 		/* print per-port info to dmesg */
 		xfer_mask = ata_pack_xfermask(ap->pio_mask, ap->mwdma_mask,
 					      ap->udma_mask);
 		if (!ata_port_is_dummy(ap)) {
 			ata_port_printk(ap, KERN_INFO,
 					"%cATA max %s %s\n",
 					(ap->flags & ATA_FLAG_SATA) ? 'S' : 'P',
 					ata_mode_string(xfer_mask),
 					ap->link.eh_info.desc);
 			ata_ehi_clear_desc(&ap->link.eh_info);
 		} else
 			ata_port_printk(ap, KERN_INFO, "DUMMY\n");
 	}
 	/* perform each probe asynchronously */
 	for (i = 0; i < host->n_ports; i++) {
 		struct ata_port *ap = host->ports[i];
 		async_schedule(async_port_probe, ap);
 	}
 	return 0;
 }
 /**
  *	ata_host_activate - start host, request IRQ and register it
  *	@host: target ATA host
  *	@irq: IRQ to request
  *	@irq_handler: irq_handler used when requesting IRQ
  *	@irq_flags: irq_flags used when requesting IRQ
  *	@sht: scsi_host_template to use when registering the host
  *
  *	After allocating an ATA host and initializing it, most libata
  *	LLDs perform three steps to activate the host - start host,
  *	request IRQ and register it.  This helper takes necessasry
  *	arguments and performs the three steps in one go.
  *
  *	An invalid IRQ skips the IRQ registration and expects the host to
  *	have set polling mode on the port. In this case, @irq_handler
  *	should be NULL.
  *
  *	LOCKING:
  *	Inherited from calling layer (may sleep).
  *
  *	RETURNS:
  *	0 on success, -errno otherwise.
  */
 int ata_host_activate(struct ata_host *host, int irq,
 		      irq_handler_t irq_handler, unsigned long irq_flags,
 		      struct scsi_host_template *sht)
 {
 	int i, rc;
 	rc = ata_host_start(host);
 	if (rc)
 		return rc;
 	/* Special case for polling mode */
 	if (!irq) {
 		WARN_ON(irq_handler);
 		return ata_host_register(host, sht);
 	}
 	rc = devm_request_irq(host->dev, irq, irq_handler, irq_flags,
 			      dev_driver_string(host->dev), host);
 	if (rc)
 		return rc;
 	for (i = 0; i < host->n_ports; i++)
 		ata_port_desc(host->ports[i], "irq %d", irq);
 	rc = ata_host_register(host, sht);
 	/* if failed, just free the IRQ and leave ports alone */
 	if (rc)
 		devm_free_irq(host->dev, irq, host);
 	return rc;
 }
 /**
  *	ata_port_detach - Detach ATA port in prepration of device removal
  *	@ap: ATA port to be detached
  *
  *	Detach all ATA devices and the associated SCSI devices of @ap;
  *	then, remove the associated SCSI host.  @ap is guaranteed to
  *	be quiescent on return from this function.
  *
  *	LOCKING:
  *	Kernel thread context (may sleep).
  */
 static void ata_port_detach(struct ata_port *ap)
 {
 	unsigned long flags;
 	if (!ap->ops->error_handler)
 		goto skip_eh;
 	/* tell EH we're leaving & flush EH */
 	spin_lock_irqsave(ap->lock, flags);
 	ap->pflags |= ATA_PFLAG_UNLOADING;
 	ata_port_schedule_eh(ap);
 	spin_unlock_irqrestore(ap->lock, flags);
 	/* wait till EH commits suicide */
 	ata_port_wait_eh(ap);
 	/* it better be dead now */
 	WARN_ON(!(ap->pflags & ATA_PFLAG_UNLOADED));
 	cancel_rearming_delayed_work(&ap->hotplug_task);
  skip_eh:
 	/* remove the associated SCSI host */
 	scsi_remove_host(ap->scsi_host);
 }
 /**
  *	ata_host_detach - Detach all ports of an ATA host
  *	@host: Host to detach
  *
  *	Detach all ports of @host.
  *
  *	LOCKING:
  *	Kernel thread context (may sleep).
  */
 void ata_host_detach(struct ata_host *host)
 {
 	int i;
 	for (i = 0; i < host->n_ports; i++)
 		ata_port_detach(host->ports[i]);
 	/* the host is dead now, dissociate ACPI */
 	ata_acpi_dissociate(host);
 }
 #ifdef CONFIG_PCI
 /**
  *	ata_pci_remove_one - PCI layer callback for device removal
  *	@pdev: PCI device that was removed
  *
  *	PCI layer indicates to libata via this hook that hot-unplug or
  *	module unload event has occurred.  Detach all ports.  Resource
  *	release is handled via devres.
  *
  *	LOCKING:
  *	Inherited from PCI layer (may sleep).
  */
 void ata_pci_remove_one(struct pci_dev *pdev)
 {
 	struct device *dev = &pdev->dev;
 	struct ata_host *host = dev_get_drvdata(dev);
 	ata_host_detach(host);
 }
 /* move to PCI subsystem */
 int pci_test_config_bits(struct pci_dev *pdev, const struct pci_bits *bits)
 {
 	unsigned long tmp = 0;
 	switch (bits->width) {
 	case 1: {
 		u8 tmp8 = 0;
 		pci_read_config_byte(pdev, bits->reg, &tmp8);
 		tmp = tmp8;
 		break;
 	}
 	case 2: {
 		u16 tmp16 = 0;
 		pci_read_config_word(pdev, bits->reg, &tmp16);
 		tmp = tmp16;
 		break;
 	}
 	case 4: {
 		u32 tmp32 = 0;
 		pci_read_config_dword(pdev, bits->reg, &tmp32);
 		tmp = tmp32;
 		break;
 	}
 	default:
 		return -EINVAL;
 	}
 	tmp &= bits->mask;
 	return (tmp == bits->val) ? 1 : 0;
 }
 #ifdef CONFIG_PM
 void ata_pci_device_do_suspend(struct pci_dev *pdev, pm_message_t mesg)
 {
 	pci_save_state(pdev);
 	pci_disable_device(pdev);
 	if (mesg.event & PM_EVENT_SLEEP)
 		pci_set_power_state(pdev, PCI_D3hot);
 }
 int ata_pci_device_do_resume(struct pci_dev *pdev)
 {
 	int rc;
 	pci_set_power_state(pdev, PCI_D0);
 	pci_restore_state(pdev);
 	rc = pcim_enable_device(pdev);
 	if (rc) {
 		dev_printk(KERN_ERR, &pdev->dev,
 			   "failed to enable device after resume (%d)\n", rc);
 		return rc;
 	}
 	pci_set_master(pdev);
 	return 0;
 }
 int ata_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
 {
 	struct ata_host *host = dev_get_drvdata(&pdev->dev);
 	int rc = 0;
 	rc = ata_host_suspend(host, mesg);
 	if (rc)
 		return rc;
 	ata_pci_device_do_suspend(pdev, mesg);
 	return 0;
 }
 int ata_pci_device_resume(struct pci_dev *pdev)
 {
 	struct ata_host *host = dev_get_drvdata(&pdev->dev);
 	int rc;
 	rc = ata_pci_device_do_resume(pdev);
 	if (rc == 0)
 		ata_host_resume(host);
 	return rc;
 }
 #endif /* CONFIG_PM */
 #endif /* CONFIG_PCI */
 static int __init ata_parse_force_one(char **cur,
 				      struct ata_force_ent *force_ent,
 				      const char **reason)
 {
 	/* FIXME: Currently, there's no way to tag init const data and
 	 * using __initdata causes build failure on some versions of
 	 * gcc.  Once __initdataconst is implemented, add const to the
 	 * following structure.
 	 */
 	static struct ata_force_param force_tbl[] __initdata = {
 		{ "40c",	.cbl		= ATA_CBL_PATA40 },
 		{ "80c",	.cbl		= ATA_CBL_PATA80 },
 		{ "short40c",	.cbl		= ATA_CBL_PATA40_SHORT },
 		{ "unk",	.cbl		= ATA_CBL_PATA_UNK },
 		{ "ign",	.cbl		= ATA_CBL_PATA_IGN },
 		{ "sata",	.cbl		= ATA_CBL_SATA },
 		{ "1.5Gbps",	.spd_limit	= 1 },
 		{ "3.0Gbps",	.spd_limit	= 2 },
 		{ "noncq",	.horkage_on	= ATA_HORKAGE_NONCQ },
 		{ "ncq",	.horkage_off	= ATA_HORKAGE_NONCQ },
 		{ "dump_id",	.horkage_on	= ATA_HORKAGE_DUMP_ID },
 		{ "pio0",	.xfer_mask	= 1 << (ATA_SHIFT_PIO + 0) },
 		{ "pio1",	.xfer_mask	= 1 << (ATA_SHIFT_PIO + 1) },
 		{ "pio2",	.xfer_mask	= 1 << (ATA_SHIFT_PIO + 2) },
 		{ "pio3",	.xfer_mask	= 1 << (ATA_SHIFT_PIO + 3) },
 		{ "pio4",	.xfer_mask	= 1 << (ATA_SHIFT_PIO + 4) },
 		{ "pio5",	.xfer_mask	= 1 << (ATA_SHIFT_PIO + 5) },
 		{ "pio6",	.xfer_mask	= 1 << (ATA_SHIFT_PIO + 6) },
 		{ "mwdma0",	.xfer_mask	= 1 << (ATA_SHIFT_MWDMA + 0) },
 		{ "mwdma1",	.xfer_mask	= 1 << (ATA_SHIFT_MWDMA + 1) },
 		{ "mwdma2",	.xfer_mask	= 1 << (ATA_SHIFT_MWDMA + 2) },
 		{ "mwdma3",	.xfer_mask	= 1 << (ATA_SHIFT_MWDMA + 3) },
 		{ "mwdma4",	.xfer_mask	= 1 << (ATA_SHIFT_MWDMA + 4) },
 		{ "udma0",	.xfer_mask	= 1 << (ATA_SHIFT_UDMA + 0) },
 		{ "udma16",	.xfer_mask	= 1 << (ATA_SHIFT_UDMA + 0) },
 		{ "udma/16",	.xfer_mask	= 1 << (ATA_SHIFT_UDMA + 0) },
 		{ "udma1",	.xfer_mask	= 1 << (ATA_SHIFT_UDMA + 1) },
 		{ "udma25",	.xfer_mask	= 1 << (ATA_SHIFT_UDMA + 1) },
 		{ "udma/25",	.xfer_mask	= 1 << (ATA_SHIFT_UDMA + 1) },
 		{ "udma2",	.xfer_mask	= 1 << (ATA_SHIFT_UDMA + 2) },
 		{ "udma33",	.xfer_mask	= 1 << (ATA_SHIFT_UDMA + 2) },
 		{ "udma/33",	.xfer_mask	= 1 << (ATA_SHIFT_UDMA + 2) },
 		{ "udma3",	.xfer_mask	= 1 << (ATA_SHIFT_UDMA + 3) },
 		{ "udma44",	.xfer_mask	= 1 << (ATA_SHIFT_UDMA + 3) },
 		{ "udma/44",	.xfer_mask	= 1 << (ATA_SHIFT_UDMA + 3) },
 		{ "udma4",	.xfer_mask	= 1 << (ATA_SHIFT_UDMA + 4) },
 		{ "udma66",	.xfer_mask	= 1 << (ATA_SHIFT_UDMA + 4) },
 		{ "udma/66",	.xfer_mask	= 1 << (ATA_SHIFT_UDMA + 4) },
 		{ "udma5",	.xfer_mask	= 1 << (ATA_SHIFT_UDMA + 5) },
 		{ "udma100",	.xfer_mask	= 1 << (ATA_SHIFT_UDMA + 5) },
 		{ "udma/100",	.xfer_mask	= 1 << (ATA_SHIFT_UDMA + 5) },
 		{ "udma6",	.xfer_mask	= 1 << (ATA_SHIFT_UDMA + 6) },
 		{ "udma133",	.xfer_mask	= 1 << (ATA_SHIFT_UDMA + 6) },
 		{ "udma/133",	.xfer_mask	= 1 << (ATA_SHIFT_UDMA + 6) },
 		{ "udma7",	.xfer_mask	= 1 << (ATA_SHIFT_UDMA + 7) },
 		{ "nohrst",	.lflags		= ATA_LFLAG_NO_HRST },
 		{ "nosrst",	.lflags		= ATA_LFLAG_NO_SRST },
 		{ "norst",	.lflags		= ATA_LFLAG_NO_HRST | ATA_LFLAG_NO_SRST },
 	};
 	char *start = *cur, *p = *cur;
 	char *id, *val, *endp;
 	const struct ata_force_param *match_fp = NULL;
 	int nr_matches = 0, i;
 	/* find where this param ends and update *cur */
 	while (*p != '\0' && *p != ',')
 		p++;
 	if (*p == '\0')
 		*cur = p;
 	else
 		*cur = p + 1;
 	*p = '\0';
 	/* parse */
 	p = strchr(start, ':');
 	if (!p) {
 		val = strstrip(start);
 		goto parse_val;
 	}
 	*p = '\0';
 	id = strstrip(start);
 	val = strstrip(p + 1);
 	/* parse id */
 	p = strchr(id, '.');
 	if (p) {
 		*p++ = '\0';
 		force_ent->device = simple_strtoul(p, &endp, 10);
 		if (p == endp || *endp != '\0') {
 			*reason = "invalid device";
 			return -EINVAL;
 		}
 	}
 	force_ent->port = simple_strtoul(id, &endp, 10);
 	if (p == endp || *endp != '\0') {
 		*reason = "invalid port/link";
 		return -EINVAL;
 	}
  parse_val:
 	/* parse val, allow shortcuts so that both 1.5 and 1.5Gbps work */
 	for (i = 0; i < ARRAY_SIZE(force_tbl); i++) {
 		const struct ata_force_param *fp = &force_tbl[i];
 		if (strncasecmp(val, fp->name, strlen(val)))
 			continue;
 		nr_matches++;
 		match_fp = fp;
 		if (strcasecmp(val, fp->name) == 0) {
 			nr_matches = 1;
 			break;
 		}
 	}
 	if (!nr_matches) {
 		*reason = "unknown value";
 		return -EINVAL;
 	}
 	if (nr_matches > 1) {
 		*reason = "ambigious value";
 		return -EINVAL;
 	}
 	force_ent->param = *match_fp;
 	return 0;
 }
 static void __init ata_parse_force_param(void)
 {
 	int idx = 0, size = 1;
 	int last_port = -1, last_device = -1;
 	char *p, *cur, *next;
 	/* calculate maximum number of params and allocate force_tbl */
 	for (p = ata_force_param_buf; *p; p++)
 		if (*p == ',')
 			size++;
 	ata_force_tbl = kzalloc(sizeof(ata_force_tbl[0]) * size, GFP_KERNEL);
 	if (!ata_force_tbl) {
 		printk(KERN_WARNING "ata: failed to extend force table, "
 		       "libata.force ignored\n");
 		return;
 	}
 	/* parse and populate the table */
 	for (cur = ata_force_param_buf; *cur != '\0'; cur = next) {
 		const char *reason = "";
 		struct ata_force_ent te = { .port = -1, .device = -1 };
 		next = cur;
 		if (ata_parse_force_one(&next, &te, &reason)) {
 			printk(KERN_WARNING "ata: failed to parse force "
 			       "parameter \"%s\" (%s)\n",
 			       cur, reason);
 			continue;
 		}
 		if (te.port == -1) {
 			te.port = last_port;
 			te.device = last_device;
 		}
 		ata_force_tbl[idx++] = te;
 		last_port = te.port;
 		last_device = te.device;
 	}
 	ata_force_tbl_size = idx;
 }
 static int __init ata_init(void)
 {
 	int rc = -ENOMEM;
 	ata_parse_force_param();
 	rc = ata_sff_init();
 	if (rc) {
 		kfree(ata_force_tbl);
 		return rc;
 	}
 	printk(KERN_DEBUG "libata version " DRV_VERSION " loaded.\n");
 	return 0;
 }
 static void __exit ata_exit(void)
 {
 	ata_sff_exit();
 	kfree(ata_force_tbl);
 }
 subsys_initcall(ata_init);
 module_exit(ata_exit);
 static DEFINE_RATELIMIT_STATE(ratelimit, HZ / 5, 1);
 int ata_ratelimit(void)
 {
 	return __ratelimit(&ratelimit);
 }
 /**
  *	ata_wait_register - wait until register value changes
  *	@reg: IO-mapped register
  *	@mask: Mask to apply to read register value
  *	@val: Wait condition
  *	@interval: polling interval in milliseconds
  *	@timeout: timeout in milliseconds
  *
  *	Waiting for some bits of register to change is a common
  *	operation for ATA controllers.  This function reads 32bit LE
  *	IO-mapped register @reg and tests for the following condition.
  *
  *	(*@reg & mask) != val
  *
  *	If the condition is met, it returns; otherwise, the process is
  *	repeated after @interval_msec until timeout.
  *
  *	LOCKING:
  *	Kernel thread context (may sleep)
  *
  *	RETURNS:
  *	The final register value.
  */
 u32 ata_wait_register(void __iomem *reg, u32 mask, u32 val,
 		      unsigned long interval, unsigned long timeout)
 {
 	unsigned long deadline;
 	u32 tmp;
 	tmp = ioread32(reg);
 	/* Calculate timeout _after_ the first read to make sure
 	 * preceding writes reach the controller before starting to
 	 * eat away the timeout.
 	 */
 	deadline = ata_deadline(jiffies, timeout);
 	while ((tmp & mask) == val && time_before(jiffies, deadline)) {
 		msleep(interval);
 		tmp = ioread32(reg);
 	}
 	return tmp;
 }
 /*
  * Dummy port_ops
  */
 static unsigned int ata_dummy_qc_issue(struct ata_queued_cmd *qc)
 {
 	return AC_ERR_SYSTEM;
 }
 static void ata_dummy_error_handler(struct ata_port *ap)
 {
 	/* truly dummy */
 }
 struct ata_port_operations ata_dummy_port_ops = {
 	.qc_prep		= ata_noop_qc_prep,
 	.qc_issue		= ata_dummy_qc_issue,
 	.error_handler		= ata_dummy_error_handler,
 };
 const struct ata_port_info ata_dummy_port_info = {
 	.port_ops		= &ata_dummy_port_ops,
 };
 /*
  * libata is essentially a library of internal helper functions for
  * low-level ATA host controller drivers.  As such, the API/ABI is
  * likely to change as new drivers are added and updated.
  * Do not depend on ABI/API stability.
  */
 EXPORT_SYMBOL_GPL(sata_deb_timing_normal);
 EXPORT_SYMBOL_GPL(sata_deb_timing_hotplug);
 EXPORT_SYMBOL_GPL(sata_deb_timing_long);
 EXPORT_SYMBOL_GPL(ata_base_port_ops);
 EXPORT_SYMBOL_GPL(sata_port_ops);
 EXPORT_SYMBOL_GPL(ata_dummy_port_ops);
 EXPORT_SYMBOL_GPL(ata_dummy_port_info);
 EXPORT_SYMBOL_GPL(ata_link_next);
 EXPORT_SYMBOL_GPL(ata_dev_next);
 EXPORT_SYMBOL_GPL(ata_std_bios_param);
 EXPORT_SYMBOL_GPL(ata_scsi_unlock_native_capacity);
 EXPORT_SYMBOL_GPL(ata_host_init);
 EXPORT_SYMBOL_GPL(ata_host_alloc);
 EXPORT_SYMBOL_GPL(ata_host_alloc_pinfo);
 EXPORT_SYMBOL_GPL(ata_slave_link_init);
 EXPORT_SYMBOL_GPL(ata_host_start);
 EXPORT_SYMBOL_GPL(ata_host_register);
 EXPORT_SYMBOL_GPL(ata_host_activate);
 EXPORT_SYMBOL_GPL(ata_host_detach);
 EXPORT_SYMBOL_GPL(ata_sg_init);
 EXPORT_SYMBOL_GPL(ata_qc_complete);
 EXPORT_SYMBOL_GPL(ata_qc_complete_multiple);
 EXPORT_SYMBOL_GPL(atapi_cmd_type);
 EXPORT_SYMBOL_GPL(ata_tf_to_fis);
 EXPORT_SYMBOL_GPL(ata_tf_from_fis);
 EXPORT_SYMBOL_GPL(ata_pack_xfermask);
 EXPORT_SYMBOL_GPL(ata_unpack_xfermask);
 EXPORT_SYMBOL_GPL(ata_xfer_mask2mode);
 EXPORT_SYMBOL_GPL(ata_xfer_mode2mask);
 EXPORT_SYMBOL_GPL(ata_xfer_mode2shift);
 EXPORT_SYMBOL_GPL(ata_mode_string);
 EXPORT_SYMBOL_GPL(ata_id_xfermask);
 EXPORT_SYMBOL_GPL(ata_do_set_mode);
 EXPORT_SYMBOL_GPL(ata_std_qc_defer);
 EXPORT_SYMBOL_GPL(ata_noop_qc_prep);
 EXPORT_SYMBOL_GPL(ata_dev_disable);
 EXPORT_SYMBOL_GPL(sata_set_spd);
 EXPORT_SYMBOL_GPL(ata_wait_after_reset);
 EXPORT_SYMBOL_GPL(sata_link_debounce);
 EXPORT_SYMBOL_GPL(sata_link_resume);
 EXPORT_SYMBOL_GPL(ata_std_prereset);
 EXPORT_SYMBOL_GPL(sata_link_hardreset);
 EXPORT_SYMBOL_GPL(sata_std_hardreset);
 EXPORT_SYMBOL_GPL(ata_std_postreset);
 EXPORT_SYMBOL_GPL(ata_dev_classify);
 EXPORT_SYMBOL_GPL(ata_dev_pair);
 EXPORT_SYMBOL_GPL(ata_ratelimit);
 EXPORT_SYMBOL_GPL(ata_wait_register);
 EXPORT_SYMBOL_GPL(ata_scsi_queuecmd);
 EXPORT_SYMBOL_GPL(ata_scsi_slave_config);
 EXPORT_SYMBOL_GPL(ata_scsi_slave_destroy);
 EXPORT_SYMBOL_GPL(ata_scsi_change_queue_depth);
 EXPORT_SYMBOL_GPL(sata_scr_valid);
 EXPORT_SYMBOL_GPL(sata_scr_read);
 EXPORT_SYMBOL_GPL(sata_scr_write);
 EXPORT_SYMBOL_GPL(sata_scr_write_flush);
 EXPORT_SYMBOL_GPL(ata_link_online);
 EXPORT_SYMBOL_GPL(ata_link_offline);
 #ifdef CONFIG_PM
 EXPORT_SYMBOL_GPL(ata_host_suspend);
 EXPORT_SYMBOL_GPL(ata_host_resume);
 #endif /* CONFIG_PM */
 EXPORT_SYMBOL_GPL(ata_id_string);
 EXPORT_SYMBOL_GPL(ata_id_c_string);
 EXPORT_SYMBOL_GPL(ata_do_dev_read_id);
 EXPORT_SYMBOL_GPL(ata_scsi_simulate);
 EXPORT_SYMBOL_GPL(ata_pio_need_iordy);
 EXPORT_SYMBOL_GPL(ata_timing_find_mode);
 EXPORT_SYMBOL_GPL(ata_timing_compute);
 EXPORT_SYMBOL_GPL(ata_timing_merge);
 EXPORT_SYMBOL_GPL(ata_timing_cycle2mode);
 #ifdef CONFIG_PCI
 EXPORT_SYMBOL_GPL(pci_test_config_bits);
 EXPORT_SYMBOL_GPL(ata_pci_remove_one);
 #ifdef CONFIG_PM
 EXPORT_SYMBOL_GPL(ata_pci_device_do_suspend);
 EXPORT_SYMBOL_GPL(ata_pci_device_do_resume);
 EXPORT_SYMBOL_GPL(ata_pci_device_suspend);
 EXPORT_SYMBOL_GPL(ata_pci_device_resume);
 #endif /* CONFIG_PM */
 #endif /* CONFIG_PCI */
 EXPORT_SYMBOL_GPL(__ata_ehi_push_desc);
 EXPORT_SYMBOL_GPL(ata_ehi_push_desc);
 EXPORT_SYMBOL_GPL(ata_ehi_clear_desc);
 EXPORT_SYMBOL_GPL(ata_port_desc);
 #ifdef CONFIG_PCI
 EXPORT_SYMBOL_GPL(ata_port_pbar_desc);
 #endif /* CONFIG_PCI */
 EXPORT_SYMBOL_GPL(ata_port_schedule_eh);
 EXPORT_SYMBOL_GPL(ata_link_abort);
 EXPORT_SYMBOL_GPL(ata_port_abort);
 EXPORT_SYMBOL_GPL(ata_port_freeze);
 EXPORT_SYMBOL_GPL(sata_async_notification);
 EXPORT_SYMBOL_GPL(ata_eh_freeze_port);
 EXPORT_SYMBOL_GPL(ata_eh_thaw_port);
 EXPORT_SYMBOL_GPL(ata_eh_qc_complete);
 EXPORT_SYMBOL_GPL(ata_eh_qc_retry);
 EXPORT_SYMBOL_GPL(ata_eh_analyze_ncq_error);
 EXPORT_SYMBOL_GPL(ata_do_eh);
 EXPORT_SYMBOL_GPL(ata_std_error_handler);
 EXPORT_SYMBOL_GPL(ata_cable_40wire);
 EXPORT_SYMBOL_GPL(ata_cable_80wire);
 EXPORT_SYMBOL_GPL(ata_cable_unknown);
 EXPORT_SYMBOL_GPL(ata_cable_ignore);
 EXPORT_SYMBOL_GPL(ata_cable_sata);

drivers/ata/libata-eh.c

Diff comments View file @ df423dc

 /*
  *  libata-eh.c - libata error handling
  *
  *  Maintained by:  Jeff Garzik <jgarzik@pobox.com>
  *    		    Please ALWAYS copy linux-ide@vger.kernel.org
  *		    on emails.
  *
  *  Copyright 2006 Tejun Heo <htejun@gmail.com>
  *
  *
  *  This program is free software; you can redistribute it and/or
  *  modify it under the terms of the GNU General Public License as
  *  published by the Free Software Foundation; either version 2, or
  *  (at your option) any later version.
  *
  *  This program is distributed in the hope that it will be useful,
  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  *  General Public License for more details.
  *
  *  You should have received a copy of the GNU General Public License
  *  along with this program; see the file COPYING.  If not, write to
  *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139,
  *  USA.
  *
  *
  *  libata documentation is available via 'make {ps|pdf}docs',
  *  as Documentation/DocBook/libata.*
  *
  *  Hardware documentation available from http://www.t13.org/ and
  *  http://www.sata-io.org/
  *
  */
 #include <linux/kernel.h>
 #include <linux/blkdev.h>
 #include <linux/pci.h>
 #include <scsi/scsi.h>
 #include <scsi/scsi_host.h>
 #include <scsi/scsi_eh.h>
 #include <scsi/scsi_device.h>
 #include <scsi/scsi_cmnd.h>
 #include <scsi/scsi_dbg.h>
 #include "../scsi/scsi_transport_api.h"
 #include <linux/libata.h>
 #include "libata.h"
 enum {
 	/* speed down verdicts */
 	ATA_EH_SPDN_NCQ_OFF		= (1 << 0),
 	ATA_EH_SPDN_SPEED_DOWN		= (1 << 1),
 	ATA_EH_SPDN_FALLBACK_TO_PIO	= (1 << 2),
 	ATA_EH_SPDN_KEEP_ERRORS		= (1 << 3),
 	/* error flags */
 	ATA_EFLAG_IS_IO			= (1 << 0),
 	ATA_EFLAG_DUBIOUS_XFER		= (1 << 1),
 	/* error categories */
 	ATA_ECAT_NONE			= 0,
 	ATA_ECAT_ATA_BUS		= 1,
 	ATA_ECAT_TOUT_HSM		= 2,
 	ATA_ECAT_UNK_DEV		= 3,
 	ATA_ECAT_DUBIOUS_NONE		= 4,
 	ATA_ECAT_DUBIOUS_ATA_BUS	= 5,
 	ATA_ECAT_DUBIOUS_TOUT_HSM	= 6,
 	ATA_ECAT_DUBIOUS_UNK_DEV	= 7,
 	ATA_ECAT_NR			= 8,
 	ATA_EH_CMD_DFL_TIMEOUT		=  5000,
 	/* always put at least this amount of time between resets */
 	ATA_EH_RESET_COOL_DOWN		=  5000,
 	/* Waiting in ->prereset can never be reliable.  It's
 	 * sometimes nice to wait there but it can't be depended upon;
 	 * otherwise, we wouldn't be resetting.  Just give it enough
 	 * time for most drives to spin up.
 	 */
 	ATA_EH_PRERESET_TIMEOUT		= 10000,
 	ATA_EH_FASTDRAIN_INTERVAL	=  3000,
 	ATA_EH_UA_TRIES			= 5,
 	/* probe speed down parameters, see ata_eh_schedule_probe() */
 	ATA_EH_PROBE_TRIAL_INTERVAL	= 60000,	/* 1 min */
 	ATA_EH_PROBE_TRIALS		= 2,
 };
 /* The following table determines how we sequence resets.  Each entry
  * represents timeout for that try.  The first try can be soft or
  * hardreset.  All others are hardreset if available.  In most cases
  * the first reset w/ 10sec timeout should succeed.  Following entries
  * are mostly for error handling, hotplug and retarded devices.
  */
 static const unsigned long ata_eh_reset_timeouts[] = {
 	10000,	/* most drives spin up by 10sec */
 	10000,	/* > 99% working drives spin up before 20sec */
 	35000,	/* give > 30 secs of idleness for retarded devices */
 	 5000,	/* and sweet one last chance */
 	ULONG_MAX, /* > 1 min has elapsed, give up */
 };
 static const unsigned long ata_eh_identify_timeouts[] = {
 	 5000,	/* covers > 99% of successes and not too boring on failures */
 	10000,  /* combined time till here is enough even for media access */
 	30000,	/* for true idiots */
 	ULONG_MAX,
 };
 static const unsigned long ata_eh_flush_timeouts[] = {
 	15000,	/* be generous with flush */
 	15000,  /* ditto */
 	30000,	/* and even more generous */
 	ULONG_MAX,
 };
 static const unsigned long ata_eh_other_timeouts[] = {
 	 5000,	/* same rationale as identify timeout */
 	10000,	/* ditto */
 	/* but no merciful 30sec for other commands, it just isn't worth it */
 	ULONG_MAX,
 };
 struct ata_eh_cmd_timeout_ent {
 	const u8		*commands;
 	const unsigned long	*timeouts;
 };
 /* The following table determines timeouts to use for EH internal
  * commands.  Each table entry is a command class and matches the
  * commands the entry applies to and the timeout table to use.
  *
  * On the retry after a command timed out, the next timeout value from
  * the table is used.  If the table doesn't contain further entries,
  * the last value is used.
  *
  * ehc->cmd_timeout_idx keeps track of which timeout to use per
  * command class, so if SET_FEATURES times out on the first try, the
  * next try will use the second timeout value only for that class.
  */
 #define CMDS(cmds...)	(const u8 []){ cmds, 0 }
 static const struct ata_eh_cmd_timeout_ent
 ata_eh_cmd_timeout_table[ATA_EH_CMD_TIMEOUT_TABLE_SIZE] = {
 	{ .commands = CMDS(ATA_CMD_ID_ATA, ATA_CMD_ID_ATAPI),
 	  .timeouts = ata_eh_identify_timeouts, },
 	{ .commands = CMDS(ATA_CMD_READ_NATIVE_MAX, ATA_CMD_READ_NATIVE_MAX_EXT),
 	  .timeouts = ata_eh_other_timeouts, },
 	{ .commands = CMDS(ATA_CMD_SET_MAX, ATA_CMD_SET_MAX_EXT),
 	  .timeouts = ata_eh_other_timeouts, },
 	{ .commands = CMDS(ATA_CMD_SET_FEATURES),
 	  .timeouts = ata_eh_other_timeouts, },
 	{ .commands = CMDS(ATA_CMD_INIT_DEV_PARAMS),
 	  .timeouts = ata_eh_other_timeouts, },
 	{ .commands = CMDS(ATA_CMD_FLUSH, ATA_CMD_FLUSH_EXT),
 	  .timeouts = ata_eh_flush_timeouts },
 };
 #undef CMDS
 static void __ata_port_freeze(struct ata_port *ap);
 #ifdef CONFIG_PM
 static void ata_eh_handle_port_suspend(struct ata_port *ap);
 static void ata_eh_handle_port_resume(struct ata_port *ap);
 #else /* CONFIG_PM */
 static void ata_eh_handle_port_suspend(struct ata_port *ap)
 { }
 static void ata_eh_handle_port_resume(struct ata_port *ap)
 { }
 #endif /* CONFIG_PM */
 static void __ata_ehi_pushv_desc(struct ata_eh_info *ehi, const char *fmt,
 				 va_list args)
 {
 	ehi->desc_len += vscnprintf(ehi->desc + ehi->desc_len,
 				     ATA_EH_DESC_LEN - ehi->desc_len,
 				     fmt, args);
 }
 /**
  *	__ata_ehi_push_desc - push error description without adding separator
  *	@ehi: target EHI
  *	@fmt: printf format string
  *
  *	Format string according to @fmt and append it to @ehi->desc.
  *
  *	LOCKING:
  *	spin_lock_irqsave(host lock)
  */
 void __ata_ehi_push_desc(struct ata_eh_info *ehi, const char *fmt, ...)
 {
 	va_list args;
 	va_start(args, fmt);
 	__ata_ehi_pushv_desc(ehi, fmt, args);
 	va_end(args);
 }
 /**
  *	ata_ehi_push_desc - push error description with separator
  *	@ehi: target EHI
  *	@fmt: printf format string
  *
  *	Format string according to @fmt and append it to @ehi->desc.
  *	If @ehi->desc is not empty, ", " is added in-between.
  *
  *	LOCKING:
  *	spin_lock_irqsave(host lock)
  */
 void ata_ehi_push_desc(struct ata_eh_info *ehi, const char *fmt, ...)
 {
 	va_list args;
 	if (ehi->desc_len)
 		__ata_ehi_push_desc(ehi, ", ");
 	va_start(args, fmt);
 	__ata_ehi_pushv_desc(ehi, fmt, args);
 	va_end(args);
 }
 /**
  *	ata_ehi_clear_desc - clean error description
  *	@ehi: target EHI
  *
  *	Clear @ehi->desc.
  *
  *	LOCKING:
  *	spin_lock_irqsave(host lock)
  */
 void ata_ehi_clear_desc(struct ata_eh_info *ehi)
 {
 	ehi->desc[0] = '\0';
 	ehi->desc_len = 0;
 }
 /**
  *	ata_port_desc - append port description
  *	@ap: target ATA port
  *	@fmt: printf format string
  *
  *	Format string according to @fmt and append it to port
  *	description.  If port description is not empty, " " is added
  *	in-between.  This function is to be used while initializing
  *	ata_host.  The description is printed on host registration.
  *
  *	LOCKING:
  *	None.
  */
 void ata_port_desc(struct ata_port *ap, const char *fmt, ...)
 {
 	va_list args;
 	WARN_ON(!(ap->pflags & ATA_PFLAG_INITIALIZING));
 	if (ap->link.eh_info.desc_len)
 		__ata_ehi_push_desc(&ap->link.eh_info, " ");
 	va_start(args, fmt);
 	__ata_ehi_pushv_desc(&ap->link.eh_info, fmt, args);
 	va_end(args);
 }
 #ifdef CONFIG_PCI
 /**
  *	ata_port_pbar_desc - append PCI BAR description
  *	@ap: target ATA port
  *	@bar: target PCI BAR
  *	@offset: offset into PCI BAR
  *	@name: name of the area
  *
  *	If @offset is negative, this function formats a string which
  *	contains the name, address, size and type of the BAR and
  *	appends it to the port description.  If @offset is zero or
  *	positive, only name and offsetted address is appended.
  *
  *	LOCKING:
  *	None.
  */
 void ata_port_pbar_desc(struct ata_port *ap, int bar, ssize_t offset,
 			const char *name)
 {
 	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 	char *type = "";
 	unsigned long long start, len;
 	if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
 		type = "m";
 	else if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
 		type = "i";
 	start = (unsigned long long)pci_resource_start(pdev, bar);
 	len = (unsigned long long)pci_resource_len(pdev, bar);
 	if (offset < 0)
 		ata_port_desc(ap, "%s %s%llu@0x%llx", name, type, len, start);
 	else
 		ata_port_desc(ap, "%s 0x%llx", name,
 				start + (unsigned long long)offset);
 }
 #endif /* CONFIG_PCI */
 static int ata_lookup_timeout_table(u8 cmd)
 {
 	int i;
 	for (i = 0; i < ATA_EH_CMD_TIMEOUT_TABLE_SIZE; i++) {
 		const u8 *cur;
 		for (cur = ata_eh_cmd_timeout_table[i].commands; *cur; cur++)
 			if (*cur == cmd)
 				return i;
 	}
 	return -1;
 }
 /**
  *	ata_internal_cmd_timeout - determine timeout for an internal command
  *	@dev: target device
  *	@cmd: internal command to be issued
  *
  *	Determine timeout for internal command @cmd for @dev.
  *
  *	LOCKING:
  *	EH context.
  *
  *	RETURNS:
  *	Determined timeout.
  */
 unsigned long ata_internal_cmd_timeout(struct ata_device *dev, u8 cmd)
 {
 	struct ata_eh_context *ehc = &dev->link->eh_context;
 	int ent = ata_lookup_timeout_table(cmd);
 	int idx;
 	if (ent < 0)
 		return ATA_EH_CMD_DFL_TIMEOUT;
 	idx = ehc->cmd_timeout_idx[dev->devno][ent];
 	return ata_eh_cmd_timeout_table[ent].timeouts[idx];
 }
 /**
  *	ata_internal_cmd_timed_out - notification for internal command timeout
  *	@dev: target device
  *	@cmd: internal command which timed out
  *
  *	Notify EH that internal command @cmd for @dev timed out.  This
  *	function should be called only for commands whose timeouts are
  *	determined using ata_internal_cmd_timeout().
  *
  *	LOCKING:
  *	EH context.
  */
 void ata_internal_cmd_timed_out(struct ata_device *dev, u8 cmd)
 {
 	struct ata_eh_context *ehc = &dev->link->eh_context;
 	int ent = ata_lookup_timeout_table(cmd);
 	int idx;
 	if (ent < 0)
 		return;
 	idx = ehc->cmd_timeout_idx[dev->devno][ent];
 	if (ata_eh_cmd_timeout_table[ent].timeouts[idx + 1] != ULONG_MAX)
 		ehc->cmd_timeout_idx[dev->devno][ent]++;
 }
 static void ata_ering_record(struct ata_ering *ering, unsigned int eflags,
 			     unsigned int err_mask)
 {
 	struct ata_ering_entry *ent;
 	WARN_ON(!err_mask);
 	ering->cursor++;
 	ering->cursor %= ATA_ERING_SIZE;
 	ent = &ering->ring[ering->cursor];
 	ent->eflags = eflags;
 	ent->err_mask = err_mask;
 	ent->timestamp = get_jiffies_64();
 }
 static struct ata_ering_entry *ata_ering_top(struct ata_ering *ering)
 {
 	struct ata_ering_entry *ent = &ering->ring[ering->cursor];
 	if (ent->err_mask)
 		return ent;
 	return NULL;
 }
 static void ata_ering_clear(struct ata_ering *ering)
 {
 	memset(ering, 0, sizeof(*ering));
 }
 static int ata_ering_map(struct ata_ering *ering,
 			 int (*map_fn)(struct ata_ering_entry *, void *),
 			 void *arg)
 {
 	int idx, rc = 0;
 	struct ata_ering_entry *ent;
 	idx = ering->cursor;
 	do {
 		ent = &ering->ring[idx];
 		if (!ent->err_mask)
 			break;
 		rc = map_fn(ent, arg);
 		if (rc)
 			break;
 		idx = (idx - 1 + ATA_ERING_SIZE) % ATA_ERING_SIZE;
 	} while (idx != ering->cursor);
 	return rc;
 }
 static unsigned int ata_eh_dev_action(struct ata_device *dev)
 {
 	struct ata_eh_context *ehc = &dev->link->eh_context;
 	return ehc->i.action | ehc->i.dev_action[dev->devno];
 }
 static void ata_eh_clear_action(struct ata_link *link, struct ata_device *dev,
 				struct ata_eh_info *ehi, unsigned int action)
 {
 	struct ata_device *tdev;
 	if (!dev) {
 		ehi->action &= ~action;
 		ata_for_each_dev(tdev, link, ALL)
 			ehi->dev_action[tdev->devno] &= ~action;
 	} else {
 		/* doesn't make sense for port-wide EH actions */
 		WARN_ON(!(action & ATA_EH_PERDEV_MASK));
 		/* break ehi->action into ehi->dev_action */
 		if (ehi->action & action) {
 			ata_for_each_dev(tdev, link, ALL)
 				ehi->dev_action[tdev->devno] |=
 					ehi->action & action;
 			ehi->action &= ~action;
 		}
 		/* turn off the specified per-dev action */
 		ehi->dev_action[dev->devno] &= ~action;
 	}
 }
 /**
  *	ata_scsi_timed_out - SCSI layer time out callback
  *	@cmd: timed out SCSI command
  *
  *	Handles SCSI layer timeout.  We race with normal completion of
  *	the qc for @cmd.  If the qc is already gone, we lose and let
  *	the scsi command finish (EH_HANDLED).  Otherwise, the qc has
  *	timed out and EH should be invoked.  Prevent ata_qc_complete()
  *	from finishing it by setting EH_SCHEDULED and return
  *	EH_NOT_HANDLED.
  *
  *	TODO: kill this function once old EH is gone.
  *
  *	LOCKING:
  *	Called from timer context
  *
  *	RETURNS:
  *	EH_HANDLED or EH_NOT_HANDLED
  */
 enum blk_eh_timer_return ata_scsi_timed_out(struct scsi_cmnd *cmd)
 {
 	struct Scsi_Host *host = cmd->device->host;
 	struct ata_port *ap = ata_shost_to_port(host);
 	unsigned long flags;
 	struct ata_queued_cmd *qc;
 	enum blk_eh_timer_return ret;
 	DPRINTK("ENTER\n");
 	if (ap->ops->error_handler) {
 		ret = BLK_EH_NOT_HANDLED;
 		goto out;
 	}
 	ret = BLK_EH_HANDLED;
 	spin_lock_irqsave(ap->lock, flags);
 	qc = ata_qc_from_tag(ap, ap->link.active_tag);
 	if (qc) {
 		WARN_ON(qc->scsicmd != cmd);
 		qc->flags |= ATA_QCFLAG_EH_SCHEDULED;
 		qc->err_mask |= AC_ERR_TIMEOUT;
 		ret = BLK_EH_NOT_HANDLED;
 	}
 	spin_unlock_irqrestore(ap->lock, flags);
  out:
 	DPRINTK("EXIT, ret=%d\n", ret);
 	return ret;
 }
 static void ata_eh_unload(struct ata_port *ap)
 {
 	struct ata_link *link;
 	struct ata_device *dev;
 	unsigned long flags;
 	/* Restore SControl IPM and SPD for the next driver and
 	 * disable attached devices.
 	 */
 	ata_for_each_link(link, ap, PMP_FIRST) {
 		sata_scr_write(link, SCR_CONTROL, link->saved_scontrol & 0xff0);
 		ata_for_each_dev(dev, link, ALL)
 			ata_dev_disable(dev);
 	}
 	/* freeze and set UNLOADED */
 	spin_lock_irqsave(ap->lock, flags);
 	ata_port_freeze(ap);			/* won't be thawed */
 	ap->pflags &= ~ATA_PFLAG_EH_PENDING;	/* clear pending from freeze */
 	ap->pflags |= ATA_PFLAG_UNLOADED;
 	spin_unlock_irqrestore(ap->lock, flags);
 }
 /**
  *	ata_scsi_error - SCSI layer error handler callback
  *	@host: SCSI host on which error occurred
  *
  *	Handles SCSI-layer-thrown error events.
  *
  *	LOCKING:
  *	Inherited from SCSI layer (none, can sleep)
  *
  *	RETURNS:
  *	Zero.
  */
 void ata_scsi_error(struct Scsi_Host *host)
 {
 	struct ata_port *ap = ata_shost_to_port(host);
 	int i;
 	unsigned long flags;
 	DPRINTK("ENTER\n");
 	/* make sure sff pio task is not running */
 	ata_sff_flush_pio_task(ap);
 	/* synchronize with host lock and sort out timeouts */
 	/* For new EH, all qcs are finished in one of three ways -
 	 * normal completion, error completion, and SCSI timeout.
 	 * Both completions can race against SCSI timeout.  When normal
 	 * completion wins, the qc never reaches EH.  When error
 	 * completion wins, the qc has ATA_QCFLAG_FAILED set.
 	 *
 	 * When SCSI timeout wins, things are a bit more complex.
 	 * Normal or error completion can occur after the timeout but
 	 * before this point.  In such cases, both types of
 	 * completions are honored.  A scmd is determined to have
 	 * timed out iff its associated qc is active and not failed.
 	 */
 	if (ap->ops->error_handler) {
 		struct scsi_cmnd *scmd, *tmp;
 		int nr_timedout = 0;
 		spin_lock_irqsave(ap->lock, flags);
 		/* This must occur under the ap->lock as we don't want
 		   a polled recovery to race the real interrupt handler
 		   The lost_interrupt handler checks for any completed but
 		   non-notified command and completes much like an IRQ handler.
 		   We then fall into the error recovery code which will treat
 		   this as if normal completion won the race */
 		if (ap->ops->lost_interrupt)
 			ap->ops->lost_interrupt(ap);
 		list_for_each_entry_safe(scmd, tmp, &host->eh_cmd_q, eh_entry) {
 			struct ata_queued_cmd *qc;
 			for (i = 0; i < ATA_MAX_QUEUE; i++) {
 				qc = __ata_qc_from_tag(ap, i);
 				if (qc->flags & ATA_QCFLAG_ACTIVE &&
 				    qc->scsicmd == scmd)
 					break;
 			}
 			if (i < ATA_MAX_QUEUE) {
 				/* the scmd has an associated qc */
 				if (!(qc->flags & ATA_QCFLAG_FAILED)) {
 					/* which hasn't failed yet, timeout */
 					qc->err_mask |= AC_ERR_TIMEOUT;
 					qc->flags |= ATA_QCFLAG_FAILED;
 					nr_timedout++;
 				}
 			} else {
 				/* Normal completion occurred after
 				 * SCSI timeout but before this point.
 				 * Successfully complete it.
 				 */
 				scmd->retries = scmd->allowed;
 				scsi_eh_finish_cmd(scmd, &ap->eh_done_q);
 			}
 		}
 		/* If we have timed out qcs.  They belong to EH from
 		 * this point but the state of the controller is
 		 * unknown.  Freeze the port to make sure the IRQ
 		 * handler doesn't diddle with those qcs.  This must
 		 * be done atomically w.r.t. setting QCFLAG_FAILED.
 		 */
 		if (nr_timedout)
 			__ata_port_freeze(ap);
 		spin_unlock_irqrestore(ap->lock, flags);
 		/* initialize eh_tries */
 		ap->eh_tries = ATA_EH_MAX_TRIES;
 	} else
 		spin_unlock_wait(ap->lock);
 	/* If we timed raced normal completion and there is nothing to
 	   recover nr_timedout == 0 why exactly are we doing error recovery ? */
  repeat:
 	/* invoke error handler */
 	if (ap->ops->error_handler) {
 		struct ata_link *link;
 		/* kill fast drain timer */
 		del_timer_sync(&ap->fastdrain_timer);
 		/* process port resume request */
 		ata_eh_handle_port_resume(ap);
 		/* fetch & clear EH info */
 		spin_lock_irqsave(ap->lock, flags);
 		ata_for_each_link(link, ap, HOST_FIRST) {
 			struct ata_eh_context *ehc = &link->eh_context;
 			struct ata_device *dev;
 			memset(&link->eh_context, 0, sizeof(link->eh_context));
 			link->eh_context.i = link->eh_info;
 			memset(&link->eh_info, 0, sizeof(link->eh_info));
 			ata_for_each_dev(dev, link, ENABLED) {
 				int devno = dev->devno;
 				ehc->saved_xfer_mode[devno] = dev->xfer_mode;
 				if (ata_ncq_enabled(dev))
 					ehc->saved_ncq_enabled |= 1 << devno;
 			}
 		}
 		ap->pflags |= ATA_PFLAG_EH_IN_PROGRESS;
 		ap->pflags &= ~ATA_PFLAG_EH_PENDING;
 		ap->excl_link = NULL;	/* don't maintain exclusion over EH */
 		spin_unlock_irqrestore(ap->lock, flags);
 		/* invoke EH, skip if unloading or suspended */
 		if (!(ap->pflags & (ATA_PFLAG_UNLOADING | ATA_PFLAG_SUSPENDED)))
 			ap->ops->error_handler(ap);
 		else {
 			/* if unloading, commence suicide */
 			if ((ap->pflags & ATA_PFLAG_UNLOADING) &&
 			    !(ap->pflags & ATA_PFLAG_UNLOADED))
 				ata_eh_unload(ap);
 			ata_eh_finish(ap);
 		}
 		/* process port suspend request */
 		ata_eh_handle_port_suspend(ap);
 		/* Exception might have happend after ->error_handler
 		 * recovered the port but before this point.  Repeat
 		 * EH in such case.
 		 */
 		spin_lock_irqsave(ap->lock, flags);
 		if (ap->pflags & ATA_PFLAG_EH_PENDING) {
 			if (--ap->eh_tries) {
 				spin_unlock_irqrestore(ap->lock, flags);
 				goto repeat;
 			}
 			ata_port_printk(ap, KERN_ERR, "EH pending after %d "
 					"tries, giving up\n", ATA_EH_MAX_TRIES);
 			ap->pflags &= ~ATA_PFLAG_EH_PENDING;
 		}
 		/* this run is complete, make sure EH info is clear */
 		ata_for_each_link(link, ap, HOST_FIRST)
 			memset(&link->eh_info, 0, sizeof(link->eh_info));
 		/* Clear host_eh_scheduled while holding ap->lock such
 		 * that if exception occurs after this point but
 		 * before EH completion, SCSI midlayer will
 		 * re-initiate EH.
 		 */
 		host->host_eh_scheduled = 0;
 		spin_unlock_irqrestore(ap->lock, flags);
 	} else {
 		WARN_ON(ata_qc_from_tag(ap, ap->link.active_tag) == NULL);
 		ap->ops->eng_timeout(ap);
 	}
 	/* finish or retry handled scmd's and clean up */
 	WARN_ON(host->host_failed || !list_empty(&host->eh_cmd_q));
 	scsi_eh_flush_done_q(&ap->eh_done_q);
 	/* clean up */
 	spin_lock_irqsave(ap->lock, flags);
 	if (ap->pflags & ATA_PFLAG_LOADING)
 		ap->pflags &= ~ATA_PFLAG_LOADING;
 	else if (ap->pflags & ATA_PFLAG_SCSI_HOTPLUG)
 		schedule_delayed_work(&ap->hotplug_task, 0);
 	if (ap->pflags & ATA_PFLAG_RECOVERED)
 		ata_port_printk(ap, KERN_INFO, "EH complete\n");
 	ap->pflags &= ~(ATA_PFLAG_SCSI_HOTPLUG | ATA_PFLAG_RECOVERED);
 	/* tell wait_eh that we're done */
 	ap->pflags &= ~ATA_PFLAG_EH_IN_PROGRESS;
 	wake_up_all(&ap->eh_wait_q);
 	spin_unlock_irqrestore(ap->lock, flags);
 	DPRINTK("EXIT\n");
 }
 /**
  *	ata_port_wait_eh - Wait for the currently pending EH to complete
  *	@ap: Port to wait EH for
  *
  *	Wait until the currently pending EH is complete.
  *
  *	LOCKING:
  *	Kernel thread context (may sleep).
  */
 void ata_port_wait_eh(struct ata_port *ap)
 {
 	unsigned long flags;
 	DEFINE_WAIT(wait);
  retry:
 	spin_lock_irqsave(ap->lock, flags);
 	while (ap->pflags & (ATA_PFLAG_EH_PENDING | ATA_PFLAG_EH_IN_PROGRESS)) {
 		prepare_to_wait(&ap->eh_wait_q, &wait, TASK_UNINTERRUPTIBLE);
 		spin_unlock_irqrestore(ap->lock, flags);
 		schedule();
 		spin_lock_irqsave(ap->lock, flags);
 	}
 	finish_wait(&ap->eh_wait_q, &wait);
 	spin_unlock_irqrestore(ap->lock, flags);
 	/* make sure SCSI EH is complete */
 	if (scsi_host_in_recovery(ap->scsi_host)) {
 		msleep(10);
 		goto retry;
 	}
 }
 static int ata_eh_nr_in_flight(struct ata_port *ap)
 {
 	unsigned int tag;
 	int nr = 0;
 	/* count only non-internal commands */
 	for (tag = 0; tag < ATA_MAX_QUEUE - 1; tag++)
 		if (ata_qc_from_tag(ap, tag))
 			nr++;
 	return nr;
 }
 void ata_eh_fastdrain_timerfn(unsigned long arg)
 {
 	struct ata_port *ap = (void *)arg;
 	unsigned long flags;
 	int cnt;
 	spin_lock_irqsave(ap->lock, flags);
 	cnt = ata_eh_nr_in_flight(ap);
 	/* are we done? */
 	if (!cnt)
 		goto out_unlock;
 	if (cnt == ap->fastdrain_cnt) {
 		unsigned int tag;
 		/* No progress during the last interval, tag all
 		 * in-flight qcs as timed out and freeze the port.
 		 */
 		for (tag = 0; tag < ATA_MAX_QUEUE - 1; tag++) {
 			struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag);
 			if (qc)
 				qc->err_mask |= AC_ERR_TIMEOUT;
 		}
 		ata_port_freeze(ap);
 	} else {
 		/* some qcs have finished, give it another chance */
 		ap->fastdrain_cnt = cnt;
 		ap->fastdrain_timer.expires =
 			ata_deadline(jiffies, ATA_EH_FASTDRAIN_INTERVAL);
 		add_timer(&ap->fastdrain_timer);
 	}
  out_unlock:
 	spin_unlock_irqrestore(ap->lock, flags);
 }
 /**
  *	ata_eh_set_pending - set ATA_PFLAG_EH_PENDING and activate fast drain
  *	@ap: target ATA port
  *	@fastdrain: activate fast drain
  *
  *	Set ATA_PFLAG_EH_PENDING and activate fast drain if @fastdrain
  *	is non-zero and EH wasn't pending before.  Fast drain ensures
  *	that EH kicks in in timely manner.
  *
  *	LOCKING:
  *	spin_lock_irqsave(host lock)
  */
 static void ata_eh_set_pending(struct ata_port *ap, int fastdrain)
 {
 	int cnt;
 	/* already scheduled? */
 	if (ap->pflags & ATA_PFLAG_EH_PENDING)
 		return;
 	ap->pflags |= ATA_PFLAG_EH_PENDING;
 	if (!fastdrain)
 		return;
 	/* do we have in-flight qcs? */
 	cnt = ata_eh_nr_in_flight(ap);
 	if (!cnt)
 		return;
 	/* activate fast drain */
 	ap->fastdrain_cnt = cnt;
 	ap->fastdrain_timer.expires =
 		ata_deadline(jiffies, ATA_EH_FASTDRAIN_INTERVAL);
 	add_timer(&ap->fastdrain_timer);
 }
 /**
  *	ata_qc_schedule_eh - schedule qc for error handling
  *	@qc: command to schedule error handling for
  *
  *	Schedule error handling for @qc.  EH will kick in as soon as
  *	other commands are drained.
  *
  *	LOCKING:
  *	spin_lock_irqsave(host lock)
  */
 void ata_qc_schedule_eh(struct ata_queued_cmd *qc)
 {
 	struct ata_port *ap = qc->ap;
 	struct request_queue *q = qc->scsicmd->device->request_queue;
 	unsigned long flags;
 	WARN_ON(!ap->ops->error_handler);
 	qc->flags |= ATA_QCFLAG_FAILED;
 	ata_eh_set_pending(ap, 1);
 	/* The following will fail if timeout has already expired.
 	 * ata_scsi_error() takes care of such scmds on EH entry.
 	 * Note that ATA_QCFLAG_FAILED is unconditionally set after
 	 * this function completes.
 	 */
 	spin_lock_irqsave(q->queue_lock, flags);
 	blk_abort_request(qc->scsicmd->request);
 	spin_unlock_irqrestore(q->queue_lock, flags);
 }
 /**
  *	ata_port_schedule_eh - schedule error handling without a qc
  *	@ap: ATA port to schedule EH for
  *
  *	Schedule error handling for @ap.  EH will kick in as soon as
  *	all commands are drained.
  *
  *	LOCKING:
  *	spin_lock_irqsave(host lock)
  */
 void ata_port_schedule_eh(struct ata_port *ap)
 {
 	WARN_ON(!ap->ops->error_handler);
 	if (ap->pflags & ATA_PFLAG_INITIALIZING)
 		return;
 	ata_eh_set_pending(ap, 1);
 	scsi_schedule_eh(ap->scsi_host);
 	DPRINTK("port EH scheduled\n");
 }
 static int ata_do_link_abort(struct ata_port *ap, struct ata_link *link)
 {
 	int tag, nr_aborted = 0;
 	WARN_ON(!ap->ops->error_handler);
 	/* we're gonna abort all commands, no need for fast drain */
 	ata_eh_set_pending(ap, 0);
 	for (tag = 0; tag < ATA_MAX_QUEUE; tag++) {
 		struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag);
 		if (qc && (!link || qc->dev->link == link)) {
 			qc->flags |= ATA_QCFLAG_FAILED;
 			ata_qc_complete(qc);
 			nr_aborted++;
 		}
 	}
 	if (!nr_aborted)
 		ata_port_schedule_eh(ap);
 	return nr_aborted;
 }
 /**
  *	ata_link_abort - abort all qc's on the link
  *	@link: ATA link to abort qc's for
  *
  *	Abort all active qc's active on @link and schedule EH.
  *
  *	LOCKING:
  *	spin_lock_irqsave(host lock)
  *
  *	RETURNS:
  *	Number of aborted qc's.
  */
 int ata_link_abort(struct ata_link *link)
 {
 	return ata_do_link_abort(link->ap, link);
 }
 /**
  *	ata_port_abort - abort all qc's on the port
  *	@ap: ATA port to abort qc's for
  *
  *	Abort all active qc's of @ap and schedule EH.
  *
  *	LOCKING:
  *	spin_lock_irqsave(host_set lock)
  *
  *	RETURNS:
  *	Number of aborted qc's.
  */
 int ata_port_abort(struct ata_port *ap)
 {
 	return ata_do_link_abort(ap, NULL);
 }
 /**
  *	__ata_port_freeze - freeze port
  *	@ap: ATA port to freeze
  *
  *	This function is called when HSM violation or some other
  *	condition disrupts normal operation of the port.  Frozen port
  *	is not allowed to perform any operation until the port is
  *	thawed, which usually follows a successful reset.
  *
  *	ap->ops->freeze() callback can be used for freezing the port
  *	hardware-wise (e.g. mask interrupt and stop DMA engine).  If a
  *	port cannot be frozen hardware-wise, the interrupt handler
  *	must ack and clear interrupts unconditionally while the port
  *	is frozen.
  *
  *	LOCKING:
  *	spin_lock_irqsave(host lock)
  */
 static void __ata_port_freeze(struct ata_port *ap)
 {
 	WARN_ON(!ap->ops->error_handler);
 	if (ap->ops->freeze)
 		ap->ops->freeze(ap);
 	ap->pflags |= ATA_PFLAG_FROZEN;
 	DPRINTK("ata%u port frozen\n", ap->print_id);
 }
 /**
  *	ata_port_freeze - abort & freeze port
  *	@ap: ATA port to freeze
  *
  *	Abort and freeze @ap.  The freeze operation must be called
  *	first, because some hardware requires special operations
  *	before the taskfile registers are accessible.
  *
  *	LOCKING:
  *	spin_lock_irqsave(host lock)
  *
  *	RETURNS:
  *	Number of aborted commands.
  */
 int ata_port_freeze(struct ata_port *ap)
 {
 	int nr_aborted;
 	WARN_ON(!ap->ops->error_handler);
 	__ata_port_freeze(ap);
 	nr_aborted = ata_port_abort(ap);
 	return nr_aborted;
 }
 /**
  *	sata_async_notification - SATA async notification handler
  *	@ap: ATA port where async notification is received
  *
  *	Handler to be called when async notification via SDB FIS is
  *	received.  This function schedules EH if necessary.
  *
  *	LOCKING:
  *	spin_lock_irqsave(host lock)
  *
  *	RETURNS:
  *	1 if EH is scheduled, 0 otherwise.
  */
 int sata_async_notification(struct ata_port *ap)
 {
 	u32 sntf;
 	int rc;
 	if (!(ap->flags & ATA_FLAG_AN))
 		return 0;
 	rc = sata_scr_read(&ap->link, SCR_NOTIFICATION, &sntf);
 	if (rc == 0)
 		sata_scr_write(&ap->link, SCR_NOTIFICATION, sntf);
 	if (!sata_pmp_attached(ap) || rc) {
 		/* PMP is not attached or SNTF is not available */
 		if (!sata_pmp_attached(ap)) {
 			/* PMP is not attached.  Check whether ATAPI
 			 * AN is configured.  If so, notify media
 			 * change.
 			 */
 			struct ata_device *dev = ap->link.device;
 			if ((dev->class == ATA_DEV_ATAPI) &&
 			    (dev->flags & ATA_DFLAG_AN))
 				ata_scsi_media_change_notify(dev);
 			return 0;
 		} else {
 			/* PMP is attached but SNTF is not available.
 			 * ATAPI async media change notification is
 			 * not used.  The PMP must be reporting PHY
 			 * status change, schedule EH.
 			 */
 			ata_port_schedule_eh(ap);
 			return 1;
 		}
 	} else {
 		/* PMP is attached and SNTF is available */
 		struct ata_link *link;
 		/* check and notify ATAPI AN */
 		ata_for_each_link(link, ap, EDGE) {
 			if (!(sntf & (1 << link->pmp)))
 				continue;
 			if ((link->device->class == ATA_DEV_ATAPI) &&
 			    (link->device->flags & ATA_DFLAG_AN))
 				ata_scsi_media_change_notify(link->device);
 		}
 		/* If PMP is reporting that PHY status of some
 		 * downstream ports has changed, schedule EH.
 		 */
 		if (sntf & (1 << SATA_PMP_CTRL_PORT)) {
 			ata_port_schedule_eh(ap);
 			return 1;
 		}
 		return 0;
 	}
 }
 /**
  *	ata_eh_freeze_port - EH helper to freeze port
  *	@ap: ATA port to freeze
  *
  *	Freeze @ap.
  *
  *	LOCKING:
  *	None.
  */
 void ata_eh_freeze_port(struct ata_port *ap)
 {
 	unsigned long flags;
 	if (!ap->ops->error_handler)
 		return;
 	spin_lock_irqsave(ap->lock, flags);
 	__ata_port_freeze(ap);
 	spin_unlock_irqrestore(ap->lock, flags);
 }
 /**
  *	ata_port_thaw_port - EH helper to thaw port
  *	@ap: ATA port to thaw
  *
  *	Thaw frozen port @ap.
  *
  *	LOCKING:
  *	None.
  */
 void ata_eh_thaw_port(struct ata_port *ap)
 {
 	unsigned long flags;
 	if (!ap->ops->error_handler)
 		return;
 	spin_lock_irqsave(ap->lock, flags);
 	ap->pflags &= ~ATA_PFLAG_FROZEN;
 	if (ap->ops->thaw)
 		ap->ops->thaw(ap);
 	spin_unlock_irqrestore(ap->lock, flags);
 	DPRINTK("ata%u port thawed\n", ap->print_id);
 }
 static void ata_eh_scsidone(struct scsi_cmnd *scmd)
 {
 	/* nada */
 }
 static void __ata_eh_qc_complete(struct ata_queued_cmd *qc)
 {
 	struct ata_port *ap = qc->ap;
 	struct scsi_cmnd *scmd = qc->scsicmd;
 	unsigned long flags;
 	spin_lock_irqsave(ap->lock, flags);
 	qc->scsidone = ata_eh_scsidone;
 	__ata_qc_complete(qc);
 	WARN_ON(ata_tag_valid(qc->tag));
 	spin_unlock_irqrestore(ap->lock, flags);
 	scsi_eh_finish_cmd(scmd, &ap->eh_done_q);
 }
 /**
  *	ata_eh_qc_complete - Complete an active ATA command from EH
  *	@qc: Command to complete
  *
  *	Indicate to the mid and upper layers that an ATA command has
  *	completed.  To be used from EH.
  */
 void ata_eh_qc_complete(struct ata_queued_cmd *qc)
 {
 	struct scsi_cmnd *scmd = qc->scsicmd;
 	scmd->retries = scmd->allowed;
 	__ata_eh_qc_complete(qc);
 }
 /**
  *	ata_eh_qc_retry - Tell midlayer to retry an ATA command after EH
  *	@qc: Command to retry
  *
  *	Indicate to the mid and upper layers that an ATA command
  *	should be retried.  To be used from EH.
  *
  *	SCSI midlayer limits the number of retries to scmd->allowed.
  *	scmd->retries is decremented for commands which get retried
  *	due to unrelated failures (qc->err_mask is zero).
  */
 void ata_eh_qc_retry(struct ata_queued_cmd *qc)
 {
 	struct scsi_cmnd *scmd = qc->scsicmd;
 	if (!qc->err_mask && scmd->retries)
 		scmd->retries--;
 	__ata_eh_qc_complete(qc);
 }
 /**
  *	ata_dev_disable - disable ATA device
  *	@dev: ATA device to disable
  *
  *	Disable @dev.
  *
  *	Locking:
  *	EH context.
  */
 void ata_dev_disable(struct ata_device *dev)
 {
 	if (!ata_dev_enabled(dev))
 		return;
 	if (ata_msg_drv(dev->link->ap))
 		ata_dev_printk(dev, KERN_WARNING, "disabled\n");
 	ata_acpi_on_disable(dev);
 	ata_down_xfermask_limit(dev, ATA_DNXFER_FORCE_PIO0 | ATA_DNXFER_QUIET);
 	dev->class++;
 	/* From now till the next successful probe, ering is used to
 	 * track probe failures.  Clear accumulated device error info.
 	 */
 	ata_ering_clear(&dev->ering);
 }
 /**
  *	ata_eh_detach_dev - detach ATA device
  *	@dev: ATA device to detach
  *
  *	Detach @dev.
  *
  *	LOCKING:
  *	None.
  */
 void ata_eh_detach_dev(struct ata_device *dev)
 {
 	struct ata_link *link = dev->link;
 	struct ata_port *ap = link->ap;
 	struct ata_eh_context *ehc = &link->eh_context;
 	unsigned long flags;
 	ata_dev_disable(dev);
 	spin_lock_irqsave(ap->lock, flags);
 	dev->flags &= ~ATA_DFLAG_DETACH;
 	if (ata_scsi_offline_dev(dev)) {
 		dev->flags |= ATA_DFLAG_DETACHED;
 		ap->pflags |= ATA_PFLAG_SCSI_HOTPLUG;
 	}
 	/* clear per-dev EH info */
 	ata_eh_clear_action(link, dev, &link->eh_info, ATA_EH_PERDEV_MASK);
 	ata_eh_clear_action(link, dev, &link->eh_context.i, ATA_EH_PERDEV_MASK);
 	ehc->saved_xfer_mode[dev->devno] = 0;
 	ehc->saved_ncq_enabled &= ~(1 << dev->devno);
 	spin_unlock_irqrestore(ap->lock, flags);
 }
 /**
  *	ata_eh_about_to_do - about to perform eh_action
  *	@link: target ATA link
  *	@dev: target ATA dev for per-dev action (can be NULL)
  *	@action: action about to be performed
  *
  *	Called just before performing EH actions to clear related bits
  *	in @link->eh_info such that eh actions are not unnecessarily
  *	repeated.
  *
  *	LOCKING:
  *	None.
  */
 void ata_eh_about_to_do(struct ata_link *link, struct ata_device *dev,
 			unsigned int action)
 {
 	struct ata_port *ap = link->ap;
 	struct ata_eh_info *ehi = &link->eh_info;
 	struct ata_eh_context *ehc = &link->eh_context;
 	unsigned long flags;
 	spin_lock_irqsave(ap->lock, flags);
 	ata_eh_clear_action(link, dev, ehi, action);
 	/* About to take EH action, set RECOVERED.  Ignore actions on
 	 * slave links as master will do them again.
 	 */
 	if (!(ehc->i.flags & ATA_EHI_QUIET) && link != ap->slave_link)
 		ap->pflags |= ATA_PFLAG_RECOVERED;
 	spin_unlock_irqrestore(ap->lock, flags);
 }
 /**
  *	ata_eh_done - EH action complete
 *	@ap: target ATA port
  *	@dev: target ATA dev for per-dev action (can be NULL)
  *	@action: action just completed
  *
  *	Called right after performing EH actions to clear related bits
  *	in @link->eh_context.
  *
  *	LOCKING:
  *	None.
  */
 void ata_eh_done(struct ata_link *link, struct ata_device *dev,
 		 unsigned int action)
 {
 	struct ata_eh_context *ehc = &link->eh_context;
 	ata_eh_clear_action(link, dev, &ehc->i, action);
 }
 /**
  *	ata_err_string - convert err_mask to descriptive string
  *	@err_mask: error mask to convert to string
  *
  *	Convert @err_mask to descriptive string.  Errors are
  *	prioritized according to severity and only the most severe
  *	error is reported.
  *
  *	LOCKING:
  *	None.
  *
  *	RETURNS:
  *	Descriptive string for @err_mask
  */
 static const char *ata_err_string(unsigned int err_mask)
 {
 	if (err_mask & AC_ERR_HOST_BUS)
 		return "host bus error";
 	if (err_mask & AC_ERR_ATA_BUS)
 		return "ATA bus error";
 	if (err_mask & AC_ERR_TIMEOUT)
 		return "timeout";
 	if (err_mask & AC_ERR_HSM)
 		return "HSM violation";
 	if (err_mask & AC_ERR_SYSTEM)
 		return "internal error";
 	if (err_mask & AC_ERR_MEDIA)
 		return "media error";
 	if (err_mask & AC_ERR_INVALID)
 		return "invalid argument";
 	if (err_mask & AC_ERR_DEV)
 		return "device error";
 	return "unknown error";
 }
 /**
  *	ata_read_log_page - read a specific log page
  *	@dev: target device
  *	@page: page to read
  *	@buf: buffer to store read page
  *	@sectors: number of sectors to read
  *
  *	Read log page using READ_LOG_EXT command.
  *
  *	LOCKING:
  *	Kernel thread context (may sleep).
  *
  *	RETURNS:
  *	0 on success, AC_ERR_* mask otherwise.
  */
 static unsigned int ata_read_log_page(struct ata_device *dev,
 				      u8 page, void *buf, unsigned int sectors)
 {
 	struct ata_taskfile tf;
 	unsigned int err_mask;
 	DPRINTK("read log page - page %d\n", page);
 	ata_tf_init(dev, &tf);
 	tf.command = ATA_CMD_READ_LOG_EXT;
 	tf.lbal = page;
 	tf.nsect = sectors;
 	tf.hob_nsect = sectors >> 8;
 	tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_LBA48 | ATA_TFLAG_DEVICE;
 	tf.protocol = ATA_PROT_PIO;
 	err_mask = ata_exec_internal(dev, &tf, NULL, DMA_FROM_DEVICE,
 				     buf, sectors * ATA_SECT_SIZE, 0);
 	DPRINTK("EXIT, err_mask=%x\n", err_mask);
 	return err_mask;
 }
 /**
  *	ata_eh_read_log_10h - Read log page 10h for NCQ error details
  *	@dev: Device to read log page 10h from
  *	@tag: Resulting tag of the failed command
  *	@tf: Resulting taskfile registers of the failed command
  *
  *	Read log page 10h to obtain NCQ error details and clear error
  *	condition.
  *
  *	LOCKING:
  *	Kernel thread context (may sleep).
  *
  *	RETURNS:
  *	0 on success, -errno otherwise.
  */
 static int ata_eh_read_log_10h(struct ata_device *dev,
 			       int *tag, struct ata_taskfile *tf)
 {
 	u8 *buf = dev->link->ap->sector_buf;
 	unsigned int err_mask;
 	u8 csum;
 	int i;
 	err_mask = ata_read_log_page(dev, ATA_LOG_SATA_NCQ, buf, 1);
 	if (err_mask)
 		return -EIO;
 	csum = 0;
 	for (i = 0; i < ATA_SECT_SIZE; i++)
 		csum += buf[i];
 	if (csum)
 		ata_dev_printk(dev, KERN_WARNING,
 			       "invalid checksum 0x%x on log page 10h\n", csum);
 	if (buf[0] & 0x80)
 		return -ENOENT;
 	*tag = buf[0] & 0x1f;
 	tf->command = buf[2];
 	tf->feature = buf[3];
 	tf->lbal = buf[4];
 	tf->lbam = buf[5];
 	tf->lbah = buf[6];
 	tf->device = buf[7];
 	tf->hob_lbal = buf[8];
 	tf->hob_lbam = buf[9];
 	tf->hob_lbah = buf[10];
 	tf->nsect = buf[12];
 	tf->hob_nsect = buf[13];
 	return 0;
 }
 /**
  *	atapi_eh_tur - perform ATAPI TEST_UNIT_READY
  *	@dev: target ATAPI device
  *	@r_sense_key: out parameter for sense_key
  *
  *	Perform ATAPI TEST_UNIT_READY.
  *
  *	LOCKING:
  *	EH context (may sleep).
  *
  *	RETURNS:
  *	0 on success, AC_ERR_* mask on failure.
  */
 static unsigned int atapi_eh_tur(struct ata_device *dev, u8 *r_sense_key)
 {
 	u8 cdb[ATAPI_CDB_LEN] = { TEST_UNIT_READY, 0, 0, 0, 0, 0 };
 	struct ata_taskfile tf;
 	unsigned int err_mask;
 	ata_tf_init(dev, &tf);
 	tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
 	tf.command = ATA_CMD_PACKET;
 	tf.protocol = ATAPI_PROT_NODATA;
 	err_mask = ata_exec_internal(dev, &tf, cdb, DMA_NONE, NULL, 0, 0);
 	if (err_mask == AC_ERR_DEV)
 		*r_sense_key = tf.feature >> 4;
 	return err_mask;
 }
 /**
  *	atapi_eh_request_sense - perform ATAPI REQUEST_SENSE
  *	@dev: device to perform REQUEST_SENSE to
  *	@sense_buf: result sense data buffer (SCSI_SENSE_BUFFERSIZE bytes long)
  *	@dfl_sense_key: default sense key to use
  *
  *	Perform ATAPI REQUEST_SENSE after the device reported CHECK
  *	SENSE.  This function is EH helper.
  *
  *	LOCKING:
  *	Kernel thread context (may sleep).
  *
  *	RETURNS:
  *	0 on success, AC_ERR_* mask on failure
  */
 static unsigned int atapi_eh_request_sense(struct ata_device *dev,
 					   u8 *sense_buf, u8 dfl_sense_key)
 {
 	u8 cdb[ATAPI_CDB_LEN] =
 		{ REQUEST_SENSE, 0, 0, 0, SCSI_SENSE_BUFFERSIZE, 0 };
 	struct ata_port *ap = dev->link->ap;
 	struct ata_taskfile tf;
 	DPRINTK("ATAPI request sense\n");
 	/* FIXME: is this needed? */
 	memset(sense_buf, 0, SCSI_SENSE_BUFFERSIZE);
 	/* initialize sense_buf with the error register,
 	 * for the case where they are -not- overwritten
 	 */
 	sense_buf[0] = 0x70;
 	sense_buf[2] = dfl_sense_key;
 	/* some devices time out if garbage left in tf */
 	ata_tf_init(dev, &tf);
 	tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
 	tf.command = ATA_CMD_PACKET;
 	/* is it pointless to prefer PIO for "safety reasons"? */
 	if (ap->flags & ATA_FLAG_PIO_DMA) {
 		tf.protocol = ATAPI_PROT_DMA;
 		tf.feature |= ATAPI_PKT_DMA;
 	} else {
 		tf.protocol = ATAPI_PROT_PIO;
 		tf.lbam = SCSI_SENSE_BUFFERSIZE;
 		tf.lbah = 0;
 	}
 	return ata_exec_internal(dev, &tf, cdb, DMA_FROM_DEVICE,
 				 sense_buf, SCSI_SENSE_BUFFERSIZE, 0);
 }
 /**
  *	ata_eh_analyze_serror - analyze SError for a failed port
  *	@link: ATA link to analyze SError for
  *
  *	Analyze SError if available and further determine cause of
  *	failure.
  *
  *	LOCKING:
  *	None.
  */
 static void ata_eh_analyze_serror(struct ata_link *link)
 {
 	struct ata_eh_context *ehc = &link->eh_context;
 	u32 serror = ehc->i.serror;
 	unsigned int err_mask = 0, action = 0;
 	u32 hotplug_mask;
 	if (serror & (SERR_PERSISTENT | SERR_DATA)) {
 		err_mask |= AC_ERR_ATA_BUS;
 		action |= ATA_EH_RESET;
 	}
 	if (serror & SERR_PROTOCOL) {
 		err_mask |= AC_ERR_HSM;
 		action |= ATA_EH_RESET;
 	}
 	if (serror & SERR_INTERNAL) {
 		err_mask |= AC_ERR_SYSTEM;
 		action |= ATA_EH_RESET;
 	}
 	/* Determine whether a hotplug event has occurred.  Both
 	 * SError.N/X are considered hotplug events for enabled or
 	 * host links.  For disabled PMP links, only N bit is
 	 * considered as X bit is left at 1 for link plugging.
 	 */
 	hotplug_mask = 0;
 	if (!(link->flags & ATA_LFLAG_DISABLED) || ata_is_host_link(link))
 		hotplug_mask = SERR_PHYRDY_CHG | SERR_DEV_XCHG;
 	else
 		hotplug_mask = SERR_PHYRDY_CHG;
 	if (serror & hotplug_mask)
 		ata_ehi_hotplugged(&ehc->i);
 	ehc->i.err_mask |= err_mask;
 	ehc->i.action |= action;
 }
 /**
  *	ata_eh_analyze_ncq_error - analyze NCQ error
  *	@link: ATA link to analyze NCQ error for
  *
  *	Read log page 10h, determine the offending qc and acquire
  *	error status TF.  For NCQ device errors, all LLDDs have to do
  *	is setting AC_ERR_DEV in ehi->err_mask.  This function takes
  *	care of the rest.
  *
  *	LOCKING:
  *	Kernel thread context (may sleep).
  */
 void ata_eh_analyze_ncq_error(struct ata_link *link)
 {
 	struct ata_port *ap = link->ap;
 	struct ata_eh_context *ehc = &link->eh_context;
 	struct ata_device *dev = link->device;
 	struct ata_queued_cmd *qc;
 	struct ata_taskfile tf;
 	int tag, rc;
 	/* if frozen, we can't do much */
 	if (ap->pflags & ATA_PFLAG_FROZEN)
 		return;
 	/* is it NCQ device error? */
 	if (!link->sactive || !(ehc->i.err_mask & AC_ERR_DEV))
 		return;
 	/* has LLDD analyzed already? */
 	for (tag = 0; tag < ATA_MAX_QUEUE; tag++) {
 		qc = __ata_qc_from_tag(ap, tag);
 		if (!(qc->flags & ATA_QCFLAG_FAILED))
 			continue;
 		if (qc->err_mask)
 			return;
 	}
 	/* okay, this error is ours */
 	memset(&tf, 0, sizeof(tf));
 	rc = ata_eh_read_log_10h(dev, &tag, &tf);
 	if (rc) {
 		ata_link_printk(link, KERN_ERR, "failed to read log page 10h "
 				"(errno=%d)\n", rc);
 		return;
 	}
 	if (!(link->sactive & (1 << tag))) {
 		ata_link_printk(link, KERN_ERR, "log page 10h reported "
 				"inactive tag %d\n", tag);
 		return;
 	}
 	/* we've got the perpetrator, condemn it */
 	qc = __ata_qc_from_tag(ap, tag);
 	memcpy(&qc->result_tf, &tf, sizeof(tf));
 	qc->result_tf.flags = ATA_TFLAG_ISADDR | ATA_TFLAG_LBA | ATA_TFLAG_LBA48;
 	qc->err_mask |= AC_ERR_DEV | AC_ERR_NCQ;
 	ehc->i.err_mask &= ~AC_ERR_DEV;
 }
 /**
  *	ata_eh_analyze_tf - analyze taskfile of a failed qc
  *	@qc: qc to analyze
  *	@tf: Taskfile registers to analyze
  *
  *	Analyze taskfile of @qc and further determine cause of
  *	failure.  This function also requests ATAPI sense data if
  *	avaliable.
  *
  *	LOCKING:
  *	Kernel thread context (may sleep).
  *
  *	RETURNS:
  *	Determined recovery action
  */
 static unsigned int ata_eh_analyze_tf(struct ata_queued_cmd *qc,
 				      const struct ata_taskfile *tf)
 {
 	unsigned int tmp, action = 0;
 	u8 stat = tf->command, err = tf->feature;
 	if ((stat & (ATA_BUSY | ATA_DRQ | ATA_DRDY)) != ATA_DRDY) {
 		qc->err_mask |= AC_ERR_HSM;
 		return ATA_EH_RESET;
 	}
 	if (stat & (ATA_ERR | ATA_DF))
 		qc->err_mask |= AC_ERR_DEV;
 	else
 		return 0;
 	switch (qc->dev->class) {
 	case ATA_DEV_ATA:
 		if (err & ATA_ICRC)
 			qc->err_mask |= AC_ERR_ATA_BUS;
 		if (err & ATA_UNC)
 			qc->err_mask |= AC_ERR_MEDIA;
 		if (err & ATA_IDNF)
 			qc->err_mask |= AC_ERR_INVALID;
 		break;
 	case ATA_DEV_ATAPI:
 		if (!(qc->ap->pflags & ATA_PFLAG_FROZEN)) {
 			tmp = atapi_eh_request_sense(qc->dev,
 						qc->scsicmd->sense_buffer,
 						qc->result_tf.feature >> 4);
 			if (!tmp) {
 				/* ATA_QCFLAG_SENSE_VALID is used to
 				 * tell atapi_qc_complete() that sense
 				 * data is already valid.
 				 *
 				 * TODO: interpret sense data and set
 				 * appropriate err_mask.
 				 */
 				qc->flags |= ATA_QCFLAG_SENSE_VALID;
 			} else
 				qc->err_mask |= tmp;
 		}
 	}
 	if (qc->err_mask & (AC_ERR_HSM | AC_ERR_TIMEOUT | AC_ERR_ATA_BUS))
 		action |= ATA_EH_RESET;
 	return action;
 }
 static int ata_eh_categorize_error(unsigned int eflags, unsigned int err_mask,
 				   int *xfer_ok)
 {
 	int base = 0;
 	if (!(eflags & ATA_EFLAG_DUBIOUS_XFER))
 		*xfer_ok = 1;
 	if (!*xfer_ok)
 		base = ATA_ECAT_DUBIOUS_NONE;
 	if (err_mask & AC_ERR_ATA_BUS)
 		return base + ATA_ECAT_ATA_BUS;
 	if (err_mask & AC_ERR_TIMEOUT)
 		return base + ATA_ECAT_TOUT_HSM;
 	if (eflags & ATA_EFLAG_IS_IO) {
 		if (err_mask & AC_ERR_HSM)
 			return base + ATA_ECAT_TOUT_HSM;
 		if ((err_mask &
 		     (AC_ERR_DEV|AC_ERR_MEDIA|AC_ERR_INVALID)) == AC_ERR_DEV)
 			return base + ATA_ECAT_UNK_DEV;
 	}
 	return 0;
 }
 struct speed_down_verdict_arg {
 	u64 since;
 	int xfer_ok;
 	int nr_errors[ATA_ECAT_NR];
 };
 static int speed_down_verdict_cb(struct ata_ering_entry *ent, void *void_arg)
 {
 	struct speed_down_verdict_arg *arg = void_arg;
 	int cat;
 	if (ent->timestamp < arg->since)
 		return -1;
 	cat = ata_eh_categorize_error(ent->eflags, ent->err_mask,
 				      &arg->xfer_ok);
 	arg->nr_errors[cat]++;
 	return 0;
 }
 /**
  *	ata_eh_speed_down_verdict - Determine speed down verdict
  *	@dev: Device of interest
  *
  *	This function examines error ring of @dev and determines
  *	whether NCQ needs to be turned off, transfer speed should be
  *	stepped down, or falling back to PIO is necessary.
  *
  *	ECAT_ATA_BUS	: ATA_BUS error for any command
  *
  *	ECAT_TOUT_HSM	: TIMEOUT for any command or HSM violation for
  *			  IO commands
  *
  *	ECAT_UNK_DEV	: Unknown DEV error for IO commands
  *
  *	ECAT_DUBIOUS_*	: Identical to above three but occurred while
  *			  data transfer hasn't been verified.
  *
  *	Verdicts are
  *
  *	NCQ_OFF		: Turn off NCQ.
  *
  *	SPEED_DOWN	: Speed down transfer speed but don't fall back
  *			  to PIO.
  *
  *	FALLBACK_TO_PIO	: Fall back to PIO.
  *
  *	Even if multiple verdicts are returned, only one action is
  *	taken per error.  An action triggered by non-DUBIOUS errors
  *	clears ering, while one triggered by DUBIOUS_* errors doesn't.
  *	This is to expedite speed down decisions right after device is
  *	initially configured.
  *
  *	The followings are speed down rules.  #1 and #2 deal with
  *	DUBIOUS errors.
  *
  *	1. If more than one DUBIOUS_ATA_BUS or DUBIOUS_TOUT_HSM errors
  *	   occurred during last 5 mins, SPEED_DOWN and FALLBACK_TO_PIO.
  *
  *	2. If more than one DUBIOUS_TOUT_HSM or DUBIOUS_UNK_DEV errors
  *	   occurred during last 5 mins, NCQ_OFF.
  *
  *	3. If more than 8 ATA_BUS, TOUT_HSM or UNK_DEV errors
  *	   ocurred during last 5 mins, FALLBACK_TO_PIO
  *
  *	4. If more than 3 TOUT_HSM or UNK_DEV errors occurred
  *	   during last 10 mins, NCQ_OFF.
  *
  *	5. If more than 3 ATA_BUS or TOUT_HSM errors, or more than 6
  *	   UNK_DEV errors occurred during last 10 mins, SPEED_DOWN.
  *
  *	LOCKING:
  *	Inherited from caller.
  *
  *	RETURNS:
  *	OR of ATA_EH_SPDN_* flags.
  */
 static unsigned int ata_eh_speed_down_verdict(struct ata_device *dev)
 {
 	const u64 j5mins = 5LLU * 60 * HZ, j10mins = 10LLU * 60 * HZ;
 	u64 j64 = get_jiffies_64();
 	struct speed_down_verdict_arg arg;
 	unsigned int verdict = 0;
 	/* scan past 5 mins of error history */
 	memset(&arg, 0, sizeof(arg));
 	arg.since = j64 - min(j64, j5mins);
 	ata_ering_map(&dev->ering, speed_down_verdict_cb, &arg);
 	if (arg.nr_errors[ATA_ECAT_DUBIOUS_ATA_BUS] +
 	    arg.nr_errors[ATA_ECAT_DUBIOUS_TOUT_HSM] > 1)
 		verdict |= ATA_EH_SPDN_SPEED_DOWN |
 			ATA_EH_SPDN_FALLBACK_TO_PIO | ATA_EH_SPDN_KEEP_ERRORS;
 	if (arg.nr_errors[ATA_ECAT_DUBIOUS_TOUT_HSM] +
 	    arg.nr_errors[ATA_ECAT_DUBIOUS_UNK_DEV] > 1)
 		verdict |= ATA_EH_SPDN_NCQ_OFF | ATA_EH_SPDN_KEEP_ERRORS;
 	if (arg.nr_errors[ATA_ECAT_ATA_BUS] +
 	    arg.nr_errors[ATA_ECAT_TOUT_HSM] +
 	    arg.nr_errors[ATA_ECAT_UNK_DEV] > 6)
 		verdict |= ATA_EH_SPDN_FALLBACK_TO_PIO;
 	/* scan past 10 mins of error history */
 	memset(&arg, 0, sizeof(arg));
 	arg.since = j64 - min(j64, j10mins);
 	ata_ering_map(&dev->ering, speed_down_verdict_cb, &arg);
 	if (arg.nr_errors[ATA_ECAT_TOUT_HSM] +
 	    arg.nr_errors[ATA_ECAT_UNK_DEV] > 3)
 		verdict |= ATA_EH_SPDN_NCQ_OFF;
 	if (arg.nr_errors[ATA_ECAT_ATA_BUS] +
 	    arg.nr_errors[ATA_ECAT_TOUT_HSM] > 3 ||
 	    arg.nr_errors[ATA_ECAT_UNK_DEV] > 6)
 		verdict |= ATA_EH_SPDN_SPEED_DOWN;
 	return verdict;
 }
 /**
  *	ata_eh_speed_down - record error and speed down if necessary
  *	@dev: Failed device
  *	@eflags: mask of ATA_EFLAG_* flags
  *	@err_mask: err_mask of the error
  *
  *	Record error and examine error history to determine whether
  *	adjusting transmission speed is necessary.  It also sets
  *	transmission limits appropriately if such adjustment is
  *	necessary.
  *
  *	LOCKING:
  *	Kernel thread context (may sleep).
  *
  *	RETURNS:
  *	Determined recovery action.
  */
 static unsigned int ata_eh_speed_down(struct ata_device *dev,
 				unsigned int eflags, unsigned int err_mask)
 {
 	struct ata_link *link = ata_dev_phys_link(dev);
 	int xfer_ok = 0;
 	unsigned int verdict;
 	unsigned int action = 0;
 	/* don't bother if Cat-0 error */
 	if (ata_eh_categorize_error(eflags, err_mask, &xfer_ok) == 0)
 		return 0;
 	/* record error and determine whether speed down is necessary */
 	ata_ering_record(&dev->ering, eflags, err_mask);
 	verdict = ata_eh_speed_down_verdict(dev);
 	/* turn off NCQ? */
 	if ((verdict & ATA_EH_SPDN_NCQ_OFF) &&
 	    (dev->flags & (ATA_DFLAG_PIO | ATA_DFLAG_NCQ |
 			   ATA_DFLAG_NCQ_OFF)) == ATA_DFLAG_NCQ) {
 		dev->flags |= ATA_DFLAG_NCQ_OFF;
 		ata_dev_printk(dev, KERN_WARNING,
 			       "NCQ disabled due to excessive errors\n");
 		goto done;
 	}
 	/* speed down? */
 	if (verdict & ATA_EH_SPDN_SPEED_DOWN) {
 		/* speed down SATA link speed if possible */
 		if (sata_down_spd_limit(link, 0) == 0) {
 			action |= ATA_EH_RESET;
 			goto done;
 		}
 		/* lower transfer mode */
 		if (dev->spdn_cnt < 2) {
 			static const int dma_dnxfer_sel[] =
 				{ ATA_DNXFER_DMA, ATA_DNXFER_40C };
 			static const int pio_dnxfer_sel[] =
 				{ ATA_DNXFER_PIO, ATA_DNXFER_FORCE_PIO0 };
 			int sel;
 			if (dev->xfer_shift != ATA_SHIFT_PIO)
 				sel = dma_dnxfer_sel[dev->spdn_cnt];
 			else
 				sel = pio_dnxfer_sel[dev->spdn_cnt];
 			dev->spdn_cnt++;
 			if (ata_down_xfermask_limit(dev, sel) == 0) {
 				action |= ATA_EH_RESET;
 				goto done;
 			}
 		}
 	}
 	/* Fall back to PIO?  Slowing down to PIO is meaningless for
 	 * SATA ATA devices.  Consider it only for PATA and SATAPI.
 	 */
 	if ((verdict & ATA_EH_SPDN_FALLBACK_TO_PIO) && (dev->spdn_cnt >= 2) &&
 	    (link->ap->cbl != ATA_CBL_SATA || dev->class == ATA_DEV_ATAPI) &&
 	    (dev->xfer_shift != ATA_SHIFT_PIO)) {
 		if (ata_down_xfermask_limit(dev, ATA_DNXFER_FORCE_PIO) == 0) {
 			dev->spdn_cnt = 0;
 			action |= ATA_EH_RESET;
 			goto done;
 		}
 	}
 	return 0;
  done:
 	/* device has been slowed down, blow error history */
 	if (!(verdict & ATA_EH_SPDN_KEEP_ERRORS))
 		ata_ering_clear(&dev->ering);
 	return action;
 }
 /**
  *	ata_eh_link_autopsy - analyze error and determine recovery action
  *	@link: host link to perform autopsy on
  *
  *	Analyze why @link failed and determine which recovery actions
  *	are needed.  This function also sets more detailed AC_ERR_*
  *	values and fills sense data for ATAPI CHECK SENSE.
  *
  *	LOCKING:
  *	Kernel thread context (may sleep).
  */
 static void ata_eh_link_autopsy(struct ata_link *link)
 {
 	struct ata_port *ap = link->ap;
 	struct ata_eh_context *ehc = &link->eh_context;
 	struct ata_device *dev;
 	unsigned int all_err_mask = 0, eflags = 0;
 	int tag;
 	u32 serror;
 	int rc;
 	DPRINTK("ENTER\n");
 	if (ehc->i.flags & ATA_EHI_NO_AUTOPSY)
 		return;
 	/* obtain and analyze SError */
 	rc = sata_scr_read(link, SCR_ERROR, &serror);
 	if (rc == 0) {
 		ehc->i.serror |= serror;
 		ata_eh_analyze_serror(link);
 	} else if (rc != -EOPNOTSUPP) {
 		/* SError read failed, force reset and probing */
 		ehc->i.probe_mask |= ATA_ALL_DEVICES;
 		ehc->i.action |= ATA_EH_RESET;
 		ehc->i.err_mask |= AC_ERR_OTHER;
 	}
 	/* analyze NCQ failure */
 	ata_eh_analyze_ncq_error(link);
 	/* any real error trumps AC_ERR_OTHER */
 	if (ehc->i.err_mask & ~AC_ERR_OTHER)
 		ehc->i.err_mask &= ~AC_ERR_OTHER;
 	all_err_mask |= ehc->i.err_mask;
 	for (tag = 0; tag < ATA_MAX_QUEUE; tag++) {
 		struct ata_queued_cmd *qc = __ata_qc_from_tag(ap, tag);
 		if (!(qc->flags & ATA_QCFLAG_FAILED) ||
 		    ata_dev_phys_link(qc->dev) != link)
 			continue;
 		/* inherit upper level err_mask */
 		qc->err_mask |= ehc->i.err_mask;
 		/* analyze TF */
 		ehc->i.action |= ata_eh_analyze_tf(qc, &qc->result_tf);
 		/* DEV errors are probably spurious in case of ATA_BUS error */
 		if (qc->err_mask & AC_ERR_ATA_BUS)
 			qc->err_mask &= ~(AC_ERR_DEV | AC_ERR_MEDIA |
 					  AC_ERR_INVALID);
 		/* any real error trumps unknown error */
 		if (qc->err_mask & ~AC_ERR_OTHER)
 			qc->err_mask &= ~AC_ERR_OTHER;
 		/* SENSE_VALID trumps dev/unknown error and revalidation */
 		if (qc->flags & ATA_QCFLAG_SENSE_VALID)
 			qc->err_mask &= ~(AC_ERR_DEV | AC_ERR_OTHER);
 		/* determine whether the command is worth retrying */
 		if (qc->flags & ATA_QCFLAG_IO ||
 		    (!(qc->err_mask & AC_ERR_INVALID) &&
 		     qc->err_mask != AC_ERR_DEV))
 			qc->flags |= ATA_QCFLAG_RETRY;
 		/* accumulate error info */
 		ehc->i.dev = qc->dev;
 		all_err_mask |= qc->err_mask;
 		if (qc->flags & ATA_QCFLAG_IO)
 			eflags |= ATA_EFLAG_IS_IO;
 	}
 	/* enforce default EH actions */
 	if (ap->pflags & ATA_PFLAG_FROZEN ||
 	    all_err_mask & (AC_ERR_HSM | AC_ERR_TIMEOUT))
 		ehc->i.action |= ATA_EH_RESET;
 	else if (((eflags & ATA_EFLAG_IS_IO) && all_err_mask) ||
 		 (!(eflags & ATA_EFLAG_IS_IO) && (all_err_mask & ~AC_ERR_DEV)))
 		ehc->i.action |= ATA_EH_REVALIDATE;
 	/* If we have offending qcs and the associated failed device,
 	 * perform per-dev EH action only on the offending device.
 	 */
 	if (ehc->i.dev) {
 		ehc->i.dev_action[ehc->i.dev->devno] |=
 			ehc->i.action & ATA_EH_PERDEV_MASK;
 		ehc->i.action &= ~ATA_EH_PERDEV_MASK;
 	}
 	/* propagate timeout to host link */
 	if ((all_err_mask & AC_ERR_TIMEOUT) && !ata_is_host_link(link))
 		ap->link.eh_context.i.err_mask |= AC_ERR_TIMEOUT;
 	/* record error and consider speeding down */
 	dev = ehc->i.dev;
 	if (!dev && ((ata_link_max_devices(link) == 1 &&
 		      ata_dev_enabled(link->device))))
 	    dev = link->device;
 	if (dev) {
 		if (dev->flags & ATA_DFLAG_DUBIOUS_XFER)
 			eflags |= ATA_EFLAG_DUBIOUS_XFER;
 		ehc->i.action |= ata_eh_speed_down(dev, eflags, all_err_mask);
 	}
 	DPRINTK("EXIT\n");
 }
 /**
  *	ata_eh_autopsy - analyze error and determine recovery action
  *	@ap: host port to perform autopsy on
  *
  *	Analyze all links of @ap and determine why they failed and
  *	which recovery actions are needed.
  *
  *	LOCKING:
  *	Kernel thread context (may sleep).
  */
 void ata_eh_autopsy(struct ata_port *ap)
 {
 	struct ata_link *link;
 	ata_for_each_link(link, ap, EDGE)
 		ata_eh_link_autopsy(link);
 	/* Handle the frigging slave link.  Autopsy is done similarly
 	 * but actions and flags are transferred over to the master
 	 * link and handled from there.
 	 */
 	if (ap->slave_link) {
 		struct ata_eh_context *mehc = &ap->link.eh_context;
 		struct ata_eh_context *sehc = &ap->slave_link->eh_context;
 		/* transfer control flags from master to slave */
 		sehc->i.flags |= mehc->i.flags & ATA_EHI_TO_SLAVE_MASK;
 		/* perform autopsy on the slave link */
 		ata_eh_link_autopsy(ap->slave_link);
 		/* transfer actions from slave to master and clear slave */
 		ata_eh_about_to_do(ap->slave_link, NULL, ATA_EH_ALL_ACTIONS);
 		mehc->i.action		|= sehc->i.action;
 		mehc->i.dev_action[1]	|= sehc->i.dev_action[1];
 		mehc->i.flags		|= sehc->i.flags;
 		ata_eh_done(ap->slave_link, NULL, ATA_EH_ALL_ACTIONS);
 	}
 	/* Autopsy of fanout ports can affect host link autopsy.
 	 * Perform host link autopsy last.
 	 */
 	if (sata_pmp_attached(ap))
 		ata_eh_link_autopsy(&ap->link);
 }
 /**
  *	ata_get_cmd_descript - get description for ATA command
  *	@command: ATA command code to get description for
  *
  *	Return a textual description of the given command, or NULL if the
  *	command is not known.
  *
  *	LOCKING:
  *	None
  */
 const char *ata_get_cmd_descript(u8 command)
 {
 #ifdef CONFIG_ATA_VERBOSE_ERROR
 	static const struct
 	{
 		u8 command;
 		const char *text;
 	} cmd_descr[] = {
 		{ ATA_CMD_DEV_RESET,		"DEVICE RESET" },
 		{ ATA_CMD_CHK_POWER, 		"CHECK POWER MODE" },
 		{ ATA_CMD_STANDBY, 		"STANDBY" },
 		{ ATA_CMD_IDLE, 		"IDLE" },
 		{ ATA_CMD_EDD, 			"EXECUTE DEVICE DIAGNOSTIC" },
 		{ ATA_CMD_DOWNLOAD_MICRO,   	"DOWNLOAD MICROCODE" },
 		{ ATA_CMD_NOP,			"NOP" },
 		{ ATA_CMD_FLUSH, 		"FLUSH CACHE" },
 		{ ATA_CMD_FLUSH_EXT, 		"FLUSH CACHE EXT" },
 		{ ATA_CMD_ID_ATA,  		"IDENTIFY DEVICE" },
 		{ ATA_CMD_ID_ATAPI, 		"IDENTIFY PACKET DEVICE" },
 		{ ATA_CMD_SERVICE, 		"SERVICE" },
 		{ ATA_CMD_READ, 		"READ DMA" },
 		{ ATA_CMD_READ_EXT, 		"READ DMA EXT" },
 		{ ATA_CMD_READ_QUEUED, 		"READ DMA QUEUED" },
 		{ ATA_CMD_READ_STREAM_EXT, 	"READ STREAM EXT" },
 		{ ATA_CMD_READ_STREAM_DMA_EXT,  "READ STREAM DMA EXT" },
 		{ ATA_CMD_WRITE, 		"WRITE DMA" },
 		{ ATA_CMD_WRITE_EXT, 		"WRITE DMA EXT" },
 		{ ATA_CMD_WRITE_QUEUED, 	"WRITE DMA QUEUED EXT" },
 		{ ATA_CMD_WRITE_STREAM_EXT, 	"WRITE STREAM EXT" },
 		{ ATA_CMD_WRITE_STREAM_DMA_EXT, "WRITE STREAM DMA EXT" },
 		{ ATA_CMD_WRITE_FUA_EXT,	"WRITE DMA FUA EXT" },
 		{ ATA_CMD_WRITE_QUEUED_FUA_EXT, "WRITE DMA QUEUED FUA EXT" },
 		{ ATA_CMD_FPDMA_READ,		"READ FPDMA QUEUED" },
 		{ ATA_CMD_FPDMA_WRITE,		"WRITE FPDMA QUEUED" },
 		{ ATA_CMD_PIO_READ,		"READ SECTOR(S)" },
 		{ ATA_CMD_PIO_READ_EXT,		"READ SECTOR(S) EXT" },
 		{ ATA_CMD_PIO_WRITE,		"WRITE SECTOR(S)" },
 		{ ATA_CMD_PIO_WRITE_EXT,	"WRITE SECTOR(S) EXT" },
 		{ ATA_CMD_READ_MULTI,		"READ MULTIPLE" },
 		{ ATA_CMD_READ_MULTI_EXT,	"READ MULTIPLE EXT" },
 		{ ATA_CMD_WRITE_MULTI,		"WRITE MULTIPLE" },
 		{ ATA_CMD_WRITE_MULTI_EXT,	"WRITE MULTIPLE EXT" },
 		{ ATA_CMD_WRITE_MULTI_FUA_EXT, 	"WRITE MULTIPLE FUA EXT" },
 		{ ATA_CMD_SET_FEATURES,		"SET FEATURES" },
 		{ ATA_CMD_SET_MULTI,		"SET MULTIPLE MODE" },
 		{ ATA_CMD_VERIFY,		"READ VERIFY SECTOR(S)" },
 		{ ATA_CMD_VERIFY_EXT,		"READ VERIFY SECTOR(S) EXT" },
 		{ ATA_CMD_WRITE_UNCORR_EXT,	"WRITE UNCORRECTABLE EXT" },
 		{ ATA_CMD_STANDBYNOW1,		"STANDBY IMMEDIATE" },
 		{ ATA_CMD_IDLEIMMEDIATE,	"IDLE IMMEDIATE" },
 		{ ATA_CMD_SLEEP,		"SLEEP" },
 		{ ATA_CMD_INIT_DEV_PARAMS,	"INITIALIZE DEVICE PARAMETERS" },
 		{ ATA_CMD_READ_NATIVE_MAX,	"READ NATIVE MAX ADDRESS" },
 		{ ATA_CMD_READ_NATIVE_MAX_EXT,	"READ NATIVE MAX ADDRESS EXT" },
 		{ ATA_CMD_SET_MAX,		"SET MAX ADDRESS" },
 		{ ATA_CMD_SET_MAX_EXT,		"SET MAX ADDRESS EXT" },
 		{ ATA_CMD_READ_LOG_EXT,		"READ LOG EXT" },
 		{ ATA_CMD_WRITE_LOG_EXT,	"WRITE LOG EXT" },
 		{ ATA_CMD_READ_LOG_DMA_EXT,	"READ LOG DMA EXT" },
 		{ ATA_CMD_WRITE_LOG_DMA_EXT, 	"WRITE LOG DMA EXT" },
 		{ ATA_CMD_TRUSTED_RCV,		"TRUSTED RECEIVE" },
 		{ ATA_CMD_TRUSTED_RCV_DMA, 	"TRUSTED RECEIVE DMA" },
 		{ ATA_CMD_TRUSTED_SND,		"TRUSTED SEND" },
 		{ ATA_CMD_TRUSTED_SND_DMA, 	"TRUSTED SEND DMA" },
 		{ ATA_CMD_PMP_READ,		"READ BUFFER" },
 		{ ATA_CMD_PMP_WRITE,		"WRITE BUFFER" },
 		{ ATA_CMD_CONF_OVERLAY,		"DEVICE CONFIGURATION OVERLAY" },
 		{ ATA_CMD_SEC_SET_PASS,		"SECURITY SET PASSWORD" },
 		{ ATA_CMD_SEC_UNLOCK,		"SECURITY UNLOCK" },
 		{ ATA_CMD_SEC_ERASE_PREP,	"SECURITY ERASE PREPARE" },
 		{ ATA_CMD_SEC_ERASE_UNIT,	"SECURITY ERASE UNIT" },
 		{ ATA_CMD_SEC_FREEZE_LOCK,	"SECURITY FREEZE LOCK" },
 		{ ATA_CMD_SEC_DISABLE_PASS,	"SECURITY DISABLE PASSWORD" },
 		{ ATA_CMD_CONFIG_STREAM,	"CONFIGURE STREAM" },
 		{ ATA_CMD_SMART,		"SMART" },
 		{ ATA_CMD_MEDIA_LOCK,		"DOOR LOCK" },
 		{ ATA_CMD_MEDIA_UNLOCK,		"DOOR UNLOCK" },
 		{ ATA_CMD_DSM,			"DATA SET MANAGEMENT" },
 		{ ATA_CMD_CHK_MED_CRD_TYP, 	"CHECK MEDIA CARD TYPE" },
 		{ ATA_CMD_CFA_REQ_EXT_ERR, 	"CFA REQUEST EXTENDED ERROR" },
 		{ ATA_CMD_CFA_WRITE_NE,		"CFA WRITE SECTORS WITHOUT ERASE" },
 		{ ATA_CMD_CFA_TRANS_SECT,	"CFA TRANSLATE SECTOR" },
 		{ ATA_CMD_CFA_ERASE,		"CFA ERASE SECTORS" },
 		{ ATA_CMD_CFA_WRITE_MULT_NE, 	"CFA WRITE MULTIPLE WITHOUT ERASE" },
 		{ ATA_CMD_READ_LONG,		"READ LONG (with retries)" },
 		{ ATA_CMD_READ_LONG_ONCE,	"READ LONG (without retries)" },
 		{ ATA_CMD_WRITE_LONG,		"WRITE LONG (with retries)" },
 		{ ATA_CMD_WRITE_LONG_ONCE,	"WRITE LONG (without retries)" },
 		{ ATA_CMD_RESTORE,		"RECALIBRATE" },
 		{ 0,				NULL } /* terminate list */
 	};
 	unsigned int i;
 	for (i = 0; cmd_descr[i].text; i++)
 		if (cmd_descr[i].command == command)
 			return cmd_descr[i].text;
 #endif
 	return NULL;
 }
 /**
  *	ata_eh_link_report - report error handling to user
  *	@link: ATA link EH is going on
  *
  *	Report EH to user.
  *
  *	LOCKING:
  *	None.
  */
 static void ata_eh_link_report(struct ata_link *link)
 {
 	struct ata_port *ap = link->ap;
 	struct ata_eh_context *ehc = &link->eh_context;
 	const char *frozen, *desc;
 	char tries_buf[6];
 	int tag, nr_failed = 0;
 	if (ehc->i.flags & ATA_EHI_QUIET)
 		return;
 	desc = NULL;
 	if (ehc->i.desc[0] != '\0')
 		desc = ehc->i.desc;
 	for (tag = 0; tag < ATA_MAX_QUEUE; tag++) {
 		struct ata_queued_cmd *qc = __ata_qc_from_tag(ap, tag);
 		if (!(qc->flags & ATA_QCFLAG_FAILED) ||
 		    ata_dev_phys_link(qc->dev) != link ||
 		    ((qc->flags & ATA_QCFLAG_QUIET) &&
 		     qc->err_mask == AC_ERR_DEV))
 			continue;
 		if (qc->flags & ATA_QCFLAG_SENSE_VALID && !qc->err_mask)
 			continue;
 		nr_failed++;
 	}
 	if (!nr_failed && !ehc->i.err_mask)
 		return;
 	frozen = "";
 	if (ap->pflags & ATA_PFLAG_FROZEN)
 		frozen = " frozen";
 	memset(tries_buf, 0, sizeof(tries_buf));
 	if (ap->eh_tries < ATA_EH_MAX_TRIES)
 		snprintf(tries_buf, sizeof(tries_buf) - 1, " t%d",
 			 ap->eh_tries);
 	if (ehc->i.dev) {
 		ata_dev_printk(ehc->i.dev, KERN_ERR, "exception Emask 0x%x "
 			       "SAct 0x%x SErr 0x%x action 0x%x%s%s\n",
 			       ehc->i.err_mask, link->sactive, ehc->i.serror,
 			       ehc->i.action, frozen, tries_buf);
 		if (desc)
 			ata_dev_printk(ehc->i.dev, KERN_ERR, "%s\n", desc);
 	} else {
 		ata_link_printk(link, KERN_ERR, "exception Emask 0x%x "
 				"SAct 0x%x SErr 0x%x action 0x%x%s%s\n",
 				ehc->i.err_mask, link->sactive, ehc->i.serror,
 				ehc->i.action, frozen, tries_buf);
 		if (desc)
 			ata_link_printk(link, KERN_ERR, "%s\n", desc);
 	}
 #ifdef CONFIG_ATA_VERBOSE_ERROR
 	if (ehc->i.serror)
 		ata_link_printk(link, KERN_ERR,
 		  "SError: { %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s}\n",
 		  ehc->i.serror & SERR_DATA_RECOVERED ? "RecovData " : "",
 		  ehc->i.serror & SERR_COMM_RECOVERED ? "RecovComm " : "",
 		  ehc->i.serror & SERR_DATA ? "UnrecovData " : "",
 		  ehc->i.serror & SERR_PERSISTENT ? "Persist " : "",
 		  ehc->i.serror & SERR_PROTOCOL ? "Proto " : "",
 		  ehc->i.serror & SERR_INTERNAL ? "HostInt " : "",
 		  ehc->i.serror & SERR_PHYRDY_CHG ? "PHYRdyChg " : "",
 		  ehc->i.serror & SERR_PHY_INT_ERR ? "PHYInt " : "",
 		  ehc->i.serror & SERR_COMM_WAKE ? "CommWake " : "",
 		  ehc->i.serror & SERR_10B_8B_ERR ? "10B8B " : "",
 		  ehc->i.serror & SERR_DISPARITY ? "Dispar " : "",
 		  ehc->i.serror & SERR_CRC ? "BadCRC " : "",
 		  ehc->i.serror & SERR_HANDSHAKE ? "Handshk " : "",
 		  ehc->i.serror & SERR_LINK_SEQ_ERR ? "LinkSeq " : "",
 		  ehc->i.serror & SERR_TRANS_ST_ERROR ? "TrStaTrns " : "",
 		  ehc->i.serror & SERR_UNRECOG_FIS ? "UnrecFIS " : "",
 		  ehc->i.serror & SERR_DEV_XCHG ? "DevExch " : "");
 #endif
 	for (tag = 0; tag < ATA_MAX_QUEUE; tag++) {
 		struct ata_queued_cmd *qc = __ata_qc_from_tag(ap, tag);
 		struct ata_taskfile *cmd = &qc->tf, *res = &qc->result_tf;
 		const u8 *cdb = qc->cdb;
 		char data_buf[20] = "";
 		char cdb_buf[70] = "";
 		if (!(qc->flags & ATA_QCFLAG_FAILED) ||
 		    ata_dev_phys_link(qc->dev) != link || !qc->err_mask)
 			continue;
 		if (qc->dma_dir != DMA_NONE) {
 			static const char *dma_str[] = {
 				[DMA_BIDIRECTIONAL]	= "bidi",
 				[DMA_TO_DEVICE]		= "out",
 				[DMA_FROM_DEVICE]	= "in",
 			};
 			static const char *prot_str[] = {
 				[ATA_PROT_PIO]		= "pio",
 				[ATA_PROT_DMA]		= "dma",
 				[ATA_PROT_NCQ]		= "ncq",
 				[ATAPI_PROT_PIO]	= "pio",
 				[ATAPI_PROT_DMA]	= "dma",
 			};
 			snprintf(data_buf, sizeof(data_buf), " %s %u %s",
 				 prot_str[qc->tf.protocol], qc->nbytes,
 				 dma_str[qc->dma_dir]);
 		}
 		if (ata_is_atapi(qc->tf.protocol)) {
 			if (qc->scsicmd)
 				scsi_print_command(qc->scsicmd);
 			else
 				snprintf(cdb_buf, sizeof(cdb_buf),
 				 "cdb %02x %02x %02x %02x %02x %02x %02x %02x  "
 				 "%02x %02x %02x %02x %02x %02x %02x %02x\n         ",
 				 cdb[0], cdb[1], cdb[2], cdb[3],
 				 cdb[4], cdb[5], cdb[6], cdb[7],
 				 cdb[8], cdb[9], cdb[10], cdb[11],
 				 cdb[12], cdb[13], cdb[14], cdb[15]);
 		} else {
 			const char *descr = ata_get_cmd_descript(cmd->command);
 			if (descr)
 				ata_dev_printk(qc->dev, KERN_ERR,
 					"failed command: %s\n", descr);
 		}
 		ata_dev_printk(qc->dev, KERN_ERR,
 			"cmd %02x/%02x:%02x:%02x:%02x:%02x/%02x:%02x:%02x:%02x:%02x/%02x "
 			"tag %d%s\n         %s"
 			"res %02x/%02x:%02x:%02x:%02x:%02x/%02x:%02x:%02x:%02x:%02x/%02x "
 			"Emask 0x%x (%s)%s\n",
 			cmd->command, cmd->feature, cmd->nsect,
 			cmd->lbal, cmd->lbam, cmd->lbah,
 			cmd->hob_feature, cmd->hob_nsect,
 			cmd->hob_lbal, cmd->hob_lbam, cmd->hob_lbah,
 			cmd->device, qc->tag, data_buf, cdb_buf,
 			res->command, res->feature, res->nsect,
 			res->lbal, res->lbam, res->lbah,
 			res->hob_feature, res->hob_nsect,
 			res->hob_lbal, res->hob_lbam, res->hob_lbah,
 			res->device, qc->err_mask, ata_err_string(qc->err_mask),
 			qc->err_mask & AC_ERR_NCQ ? " <F>" : "");
 #ifdef CONFIG_ATA_VERBOSE_ERROR
 		if (res->command & (ATA_BUSY | ATA_DRDY | ATA_DF | ATA_DRQ |
 				    ATA_ERR)) {
 			if (res->command & ATA_BUSY)
 				ata_dev_printk(qc->dev, KERN_ERR,
 				  "status: { Busy }\n");
 			else
 				ata_dev_printk(qc->dev, KERN_ERR,
 				  "status: { %s%s%s%s}\n",
 				  res->command & ATA_DRDY ? "DRDY " : "",
 				  res->command & ATA_DF ? "DF " : "",
 				  res->command & ATA_DRQ ? "DRQ " : "",
 				  res->command & ATA_ERR ? "ERR " : "");
 		}
 		if (cmd->command != ATA_CMD_PACKET &&
 		    (res->feature & (ATA_ICRC | ATA_UNC | ATA_IDNF |
 				     ATA_ABORTED)))
 			ata_dev_printk(qc->dev, KERN_ERR,
 			  "error: { %s%s%s%s}\n",
 			  res->feature & ATA_ICRC ? "ICRC " : "",
 			  res->feature & ATA_UNC ? "UNC " : "",
 			  res->feature & ATA_IDNF ? "IDNF " : "",
 			  res->feature & ATA_ABORTED ? "ABRT " : "");
 #endif
 	}
 }
 /**
  *	ata_eh_report - report error handling to user
  *	@ap: ATA port to report EH about
  *
  *	Report EH to user.
  *
  *	LOCKING:
  *	None.
  */
 void ata_eh_report(struct ata_port *ap)
 {
 	struct ata_link *link;
 	ata_for_each_link(link, ap, HOST_FIRST)
 		ata_eh_link_report(link);
 }
 static int ata_do_reset(struct ata_link *link, ata_reset_fn_t reset,
 			unsigned int *classes, unsigned long deadline,
 			bool clear_classes)
 {
 	struct ata_device *dev;
 	if (clear_classes)
 		ata_for_each_dev(dev, link, ALL)
 			classes[dev->devno] = ATA_DEV_UNKNOWN;
 	return reset(link, classes, deadline);
 }
 static int ata_eh_followup_srst_needed(struct ata_link *link,
 				       int rc, const unsigned int *classes)
 {
 	if ((link->flags & ATA_LFLAG_NO_SRST) || ata_link_offline(link))
 		return 0;
 	if (rc == -EAGAIN)
 		return 1;
 	if (sata_pmp_supported(link->ap) && ata_is_host_link(link))
 		return 1;
 	return 0;
 }
 int ata_eh_reset(struct ata_link *link, int classify,
 		 ata_prereset_fn_t prereset, ata_reset_fn_t softreset,
 		 ata_reset_fn_t hardreset, ata_postreset_fn_t postreset)
 {
 	struct ata_port *ap = link->ap;
 	struct ata_link *slave = ap->slave_link;
 	struct ata_eh_context *ehc = &link->eh_context;
 	struct ata_eh_context *sehc = slave ? &slave->eh_context : NULL;
 	unsigned int *classes = ehc->classes;
 	unsigned int lflags = link->flags;
 	int verbose = !(ehc->i.flags & ATA_EHI_QUIET);
 	int max_tries = 0, try = 0;
 	struct ata_link *failed_link;
 	struct ata_device *dev;
 	unsigned long deadline, now;
 	ata_reset_fn_t reset;
 	unsigned long flags;
 	u32 sstatus;
 	int nr_unknown, rc;
 	/*
 	 * Prepare to reset
 	 */
 	while (ata_eh_reset_timeouts[max_tries] != ULONG_MAX)
 		max_tries++;
 	if (link->flags & ATA_LFLAG_NO_HRST)
 		hardreset = NULL;
 	if (link->flags & ATA_LFLAG_NO_SRST)
 		softreset = NULL;
 	/* make sure each reset attemp is at least COOL_DOWN apart */
 	if (ehc->i.flags & ATA_EHI_DID_RESET) {
 		now = jiffies;
 		WARN_ON(time_after(ehc->last_reset, now));
 		deadline = ata_deadline(ehc->last_reset,
 					ATA_EH_RESET_COOL_DOWN);
 		if (time_before(now, deadline))
 			schedule_timeout_uninterruptible(deadline - now);
 	}
 	spin_lock_irqsave(ap->lock, flags);
 	ap->pflags |= ATA_PFLAG_RESETTING;
 	spin_unlock_irqrestore(ap->lock, flags);
 	ata_eh_about_to_do(link, NULL, ATA_EH_RESET);
 	ata_for_each_dev(dev, link, ALL) {
 		/* If we issue an SRST then an ATA drive (not ATAPI)
 		 * may change configuration and be in PIO0 timing. If
 		 * we do a hard reset (or are coming from power on)
 		 * this is true for ATA or ATAPI. Until we've set a
 		 * suitable controller mode we should not touch the
 		 * bus as we may be talking too fast.
 		 */
 		dev->pio_mode = XFER_PIO_0;
 		/* If the controller has a pio mode setup function
 		 * then use it to set the chipset to rights. Don't
 		 * touch the DMA setup as that will be dealt with when
 		 * configuring devices.
 		 */
 		if (ap->ops->set_piomode)
 			ap->ops->set_piomode(ap, dev);
 	}
 	/* prefer hardreset */
 	reset = NULL;
 	ehc->i.action &= ~ATA_EH_RESET;
 	if (hardreset) {
 		reset = hardreset;
 		ehc->i.action |= ATA_EH_HARDRESET;
 	} else if (softreset) {
 		reset = softreset;
 		ehc->i.action |= ATA_EH_SOFTRESET;
 	}
 	if (prereset) {
 		unsigned long deadline = ata_deadline(jiffies,
 						      ATA_EH_PRERESET_TIMEOUT);
 		if (slave) {
 			sehc->i.action &= ~ATA_EH_RESET;
 			sehc->i.action |= ehc->i.action;
 		}
 		rc = prereset(link, deadline);
 		/* If present, do prereset on slave link too.  Reset
 		 * is skipped iff both master and slave links report
 		 * -ENOENT or clear ATA_EH_RESET.
 		 */
 		if (slave && (rc == 0 || rc == -ENOENT)) {
 			int tmp;
 			tmp = prereset(slave, deadline);
 			if (tmp != -ENOENT)
 				rc = tmp;
 			ehc->i.action |= sehc->i.action;
 		}
 		if (rc) {
 			if (rc == -ENOENT) {
 				ata_link_printk(link, KERN_DEBUG,
 						"port disabled. ignoring.\n");
 				ehc->i.action &= ~ATA_EH_RESET;
 				ata_for_each_dev(dev, link, ALL)
 					classes[dev->devno] = ATA_DEV_NONE;
 				rc = 0;
 			} else
 				ata_link_printk(link, KERN_ERR,
 					"prereset failed (errno=%d)\n", rc);
 			goto out;
 		}
 		/* prereset() might have cleared ATA_EH_RESET.  If so,
 		 * bang classes, thaw and return.
 		 */
 		if (reset && !(ehc->i.action & ATA_EH_RESET)) {
 			ata_for_each_dev(dev, link, ALL)
 				classes[dev->devno] = ATA_DEV_NONE;
 			if ((ap->pflags & ATA_PFLAG_FROZEN) &&
 			    ata_is_host_link(link))
 				ata_eh_thaw_port(ap);
 			rc = 0;
 			goto out;
 		}
 	}
  retry:
 	/*
 	 * Perform reset
 	 */
 	if (ata_is_host_link(link))
 		ata_eh_freeze_port(ap);
 	deadline = ata_deadline(jiffies, ata_eh_reset_timeouts[try++]);
 	if (reset) {
 		if (verbose)
 			ata_link_printk(link, KERN_INFO, "%s resetting link\n",
 					reset == softreset ? "soft" : "hard");
 		/* mark that this EH session started with reset */
 		ehc->last_reset = jiffies;
 		if (reset == hardreset)
 			ehc->i.flags |= ATA_EHI_DID_HARDRESET;
 		else
 			ehc->i.flags |= ATA_EHI_DID_SOFTRESET;
 		rc = ata_do_reset(link, reset, classes, deadline, true);
 		if (rc && rc != -EAGAIN) {
 			failed_link = link;
 			goto fail;
 		}
 		/* hardreset slave link if existent */
 		if (slave && reset == hardreset) {
 			int tmp;
 			if (verbose)
 				ata_link_printk(slave, KERN_INFO,
 						"hard resetting link\n");
 			ata_eh_about_to_do(slave, NULL, ATA_EH_RESET);
 			tmp = ata_do_reset(slave, reset, classes, deadline,
 					   false);
 			switch (tmp) {
 			case -EAGAIN:
 				rc = -EAGAIN;
 			case 0:
 				break;
 			default:
 				failed_link = slave;
 				rc = tmp;
 				goto fail;
 			}
 		}
 		/* perform follow-up SRST if necessary */
 		if (reset == hardreset &&
 		    ata_eh_followup_srst_needed(link, rc, classes)) {
 			reset = softreset;
 			if (!reset) {
 				ata_link_printk(link, KERN_ERR,
 						"follow-up softreset required "
 						"but no softreset avaliable\n");
 				failed_link = link;
 				rc = -EINVAL;
 				goto fail;
 			}
 			ata_eh_about_to_do(link, NULL, ATA_EH_RESET);
 			rc = ata_do_reset(link, reset, classes, deadline, true);
 			if (rc) {
 				failed_link = link;
 				goto fail;
 			}
 		}
 	} else {
 		if (verbose)
 			ata_link_printk(link, KERN_INFO, "no reset method "
 					"available, skipping reset\n");
 		if (!(lflags & ATA_LFLAG_ASSUME_CLASS))
 			lflags |= ATA_LFLAG_ASSUME_ATA;
 	}
 	/*
 	 * Post-reset processing
 	 */
 	ata_for_each_dev(dev, link, ALL) {
 		/* After the reset, the device state is PIO 0 and the
 		 * controller state is undefined.  Reset also wakes up
 		 * drives from sleeping mode.
 		 */
 		dev->pio_mode = XFER_PIO_0;
 		dev->flags &= ~ATA_DFLAG_SLEEPING;
 		if (ata_phys_link_offline(ata_dev_phys_link(dev)))
 			continue;
 		/* apply class override */
 		if (lflags & ATA_LFLAG_ASSUME_ATA)
 			classes[dev->devno] = ATA_DEV_ATA;
 		else if (lflags & ATA_LFLAG_ASSUME_SEMB)
 			classes[dev->devno] = ATA_DEV_SEMB_UNSUP;
 	}
 	/* record current link speed */
 	if (sata_scr_read(link, SCR_STATUS, &sstatus) == 0)
 		link->sata_spd = (sstatus >> 4) & 0xf;
 	if (slave && sata_scr_read(slave, SCR_STATUS, &sstatus) == 0)
 		slave->sata_spd = (sstatus >> 4) & 0xf;
 	/* thaw the port */
 	if (ata_is_host_link(link))
 		ata_eh_thaw_port(ap);
 	/* postreset() should clear hardware SError.  Although SError
 	 * is cleared during link resume, clearing SError here is
 	 * necessary as some PHYs raise hotplug events after SRST.
 	 * This introduces race condition where hotplug occurs between
 	 * reset and here.  This race is mediated by cross checking
 	 * link onlineness and classification result later.
 	 */
 	if (postreset) {
 		postreset(link, classes);
 		if (slave)
 			postreset(slave, classes);
 	}
 	/*
 	 * Some controllers can't be frozen very well and may set
 	 * spuruious error conditions during reset.  Clear accumulated
 	 * error information.  As reset is the final recovery action,
 	 * nothing is lost by doing this.
 	 */
 	spin_lock_irqsave(link->ap->lock, flags);
 	memset(&link->eh_info, 0, sizeof(link->eh_info));
 	if (slave)
 		memset(&slave->eh_info, 0, sizeof(link->eh_info));
 	ap->pflags &= ~ATA_PFLAG_EH_PENDING;
 	spin_unlock_irqrestore(link->ap->lock, flags);
 	/*
 	 * Make sure onlineness and classification result correspond.
 	 * Hotplug could have happened during reset and some
 	 * controllers fail to wait while a drive is spinning up after
 	 * being hotplugged causing misdetection.  By cross checking
 	 * link on/offlineness and classification result, those
 	 * conditions can be reliably detected and retried.
 	 */
 	nr_unknown = 0;
 	ata_for_each_dev(dev, link, ALL) {
 		if (ata_phys_link_online(ata_dev_phys_link(dev))) {
 			if (classes[dev->devno] == ATA_DEV_UNKNOWN) {
 				ata_dev_printk(dev, KERN_DEBUG, "link online "
 					       "but device misclassifed\n");
 				classes[dev->devno] = ATA_DEV_NONE;
 				nr_unknown++;
 			}
 		} else if (ata_phys_link_offline(ata_dev_phys_link(dev))) {
 			if (ata_class_enabled(classes[dev->devno]))
 				ata_dev_printk(dev, KERN_DEBUG, "link offline, "
 					       "clearing class %d to NONE\n",
 					       classes[dev->devno]);
 			classes[dev->devno] = ATA_DEV_NONE;
 		} else if (classes[dev->devno] == ATA_DEV_UNKNOWN) {
 			ata_dev_printk(dev, KERN_DEBUG, "link status unknown, "
 				       "clearing UNKNOWN to NONE\n");
 			classes[dev->devno] = ATA_DEV_NONE;
 		}
 	}
 	if (classify && nr_unknown) {
 		if (try < max_tries) {
 			ata_link_printk(link, KERN_WARNING, "link online but "
 					"%d devices misclassified, retrying\n",
 					nr_unknown);
 			failed_link = link;
 			rc = -EAGAIN;
 			goto fail;
 		}
 		ata_link_printk(link, KERN_WARNING,
 				"link online but %d devices misclassified, "
 				"device detection might fail\n", nr_unknown);
 	}
 	/* reset successful, schedule revalidation */
 	ata_eh_done(link, NULL, ATA_EH_RESET);
 	if (slave)
 		ata_eh_done(slave, NULL, ATA_EH_RESET);
 	ehc->last_reset = jiffies;	/* update to completion time */
 	ehc->i.action |= ATA_EH_REVALIDATE;
 	rc = 0;
  out:
 	/* clear hotplug flag */
 	ehc->i.flags &= ~ATA_EHI_HOTPLUGGED;
 	if (slave)
 		sehc->i.flags &= ~ATA_EHI_HOTPLUGGED;
 	spin_lock_irqsave(ap->lock, flags);
 	ap->pflags &= ~ATA_PFLAG_RESETTING;
 	spin_unlock_irqrestore(ap->lock, flags);
 	return rc;
  fail:
 	/* if SCR isn't accessible on a fan-out port, PMP needs to be reset */
 	if (!ata_is_host_link(link) &&
 	    sata_scr_read(link, SCR_STATUS, &sstatus))
 		rc = -ERESTART;
 	if (rc == -ERESTART || try >= max_tries)
 		goto out;
 	now = jiffies;
 	if (time_before(now, deadline)) {
 		unsigned long delta = deadline - now;
 		ata_link_printk(failed_link, KERN_WARNING,
 			"reset failed (errno=%d), retrying in %u secs\n",
 			rc, DIV_ROUND_UP(jiffies_to_msecs(delta), 1000));
 		while (delta)
 			delta = schedule_timeout_uninterruptible(delta);
 	}
 	if (try == max_tries - 1) {
 		sata_down_spd_limit(link, 0);
 		if (slave)
 			sata_down_spd_limit(slave, 0);
 	} else if (rc == -EPIPE)
 		sata_down_spd_limit(failed_link, 0);
 	if (hardreset)
 		reset = hardreset;
 	goto retry;
 }
 static inline void ata_eh_pull_park_action(struct ata_port *ap)
 {
 	struct ata_link *link;
 	struct ata_device *dev;
 	unsigned long flags;
 	/*
 	 * This function can be thought of as an extended version of
 	 * ata_eh_about_to_do() specially crafted to accommodate the
 	 * requirements of ATA_EH_PARK handling. Since the EH thread
 	 * does not leave the do {} while () loop in ata_eh_recover as
 	 * long as the timeout for a park request to *one* device on
 	 * the port has not expired, and since we still want to pick
 	 * up park requests to other devices on the same port or
 	 * timeout updates for the same device, we have to pull
 	 * ATA_EH_PARK actions from eh_info into eh_context.i
 	 * ourselves at the beginning of each pass over the loop.
 	 *
 	 * Additionally, all write accesses to &ap->park_req_pending
 	 * through INIT_COMPLETION() (see below) or complete_all()
 	 * (see ata_scsi_park_store()) are protected by the host lock.
 	 * As a result we have that park_req_pending.done is zero on
 	 * exit from this function, i.e. when ATA_EH_PARK actions for
 	 * *all* devices on port ap have been pulled into the
 	 * respective eh_context structs. If, and only if,
 	 * park_req_pending.done is non-zero by the time we reach
 	 * wait_for_completion_timeout(), another ATA_EH_PARK action
 	 * has been scheduled for at least one of the devices on port
 	 * ap and we have to cycle over the do {} while () loop in
 	 * ata_eh_recover() again.
 	 */
 	spin_lock_irqsave(ap->lock, flags);
 	INIT_COMPLETION(ap->park_req_pending);
 	ata_for_each_link(link, ap, EDGE) {
 		ata_for_each_dev(dev, link, ALL) {
 			struct ata_eh_info *ehi = &link->eh_info;
 			link->eh_context.i.dev_action[dev->devno] |=
 				ehi->dev_action[dev->devno] & ATA_EH_PARK;
 			ata_eh_clear_action(link, dev, ehi, ATA_EH_PARK);
 		}
 	}
 	spin_unlock_irqrestore(ap->lock, flags);
 }
 static void ata_eh_park_issue_cmd(struct ata_device *dev, int park)
 {
 	struct ata_eh_context *ehc = &dev->link->eh_context;
 	struct ata_taskfile tf;
 	unsigned int err_mask;
 	ata_tf_init(dev, &tf);
 	if (park) {
 		ehc->unloaded_mask |= 1 << dev->devno;
 		tf.command = ATA_CMD_IDLEIMMEDIATE;
 		tf.feature = 0x44;
 		tf.lbal = 0x4c;
 		tf.lbam = 0x4e;
 		tf.lbah = 0x55;
 	} else {
 		ehc->unloaded_mask &= ~(1 << dev->devno);
 		tf.command = ATA_CMD_CHK_POWER;
 	}
 	tf.flags |= ATA_TFLAG_DEVICE | ATA_TFLAG_ISADDR;
 	tf.protocol |= ATA_PROT_NODATA;
 	err_mask = ata_exec_internal(dev, &tf, NULL, DMA_NONE, NULL, 0, 0);
 	if (park && (err_mask || tf.lbal != 0xc4)) {
 		ata_dev_printk(dev, KERN_ERR, "head unload failed!\n");
 		ehc->unloaded_mask &= ~(1 << dev->devno);
 	}
 }
 static int ata_eh_revalidate_and_attach(struct ata_link *link,
 					struct ata_device **r_failed_dev)
 {
 	struct ata_port *ap = link->ap;
 	struct ata_eh_context *ehc = &link->eh_context;
 	struct ata_device *dev;
 	unsigned int new_mask = 0;
 	unsigned long flags;
 	int rc = 0;
 	DPRINTK("ENTER\n");
 	/* For PATA drive side cable detection to work, IDENTIFY must
 	 * be done backwards such that PDIAG- is released by the slave
 	 * device before the master device is identified.
 	 */
 	ata_for_each_dev(dev, link, ALL_REVERSE) {
 		unsigned int action = ata_eh_dev_action(dev);
 		unsigned int readid_flags = 0;
 		if (ehc->i.flags & ATA_EHI_DID_RESET)
 			readid_flags |= ATA_READID_POSTRESET;
 		if ((action & ATA_EH_REVALIDATE) && ata_dev_enabled(dev)) {
 			WARN_ON(dev->class == ATA_DEV_PMP);
 			if (ata_phys_link_offline(ata_dev_phys_link(dev))) {
 				rc = -EIO;
 				goto err;
 			}
 			ata_eh_about_to_do(link, dev, ATA_EH_REVALIDATE);
 			rc = ata_dev_revalidate(dev, ehc->classes[dev->devno],
 						readid_flags);
 			if (rc)
 				goto err;
 			ata_eh_done(link, dev, ATA_EH_REVALIDATE);
 			/* Configuration may have changed, reconfigure
 			 * transfer mode.
 			 */
 			ehc->i.flags |= ATA_EHI_SETMODE;
 			/* schedule the scsi_rescan_device() here */
 			schedule_work(&(ap->scsi_rescan_task));
 		} else if (dev->class == ATA_DEV_UNKNOWN &&
 			   ehc->tries[dev->devno] &&
 			   ata_class_enabled(ehc->classes[dev->devno])) {
 			/* Temporarily set dev->class, it will be
 			 * permanently set once all configurations are
 			 * complete.  This is necessary because new
 			 * device configuration is done in two
 			 * separate loops.
 			 */
 			dev->class = ehc->classes[dev->devno];
 			if (dev->class == ATA_DEV_PMP)
 				rc = sata_pmp_attach(dev);
 			else
 				rc = ata_dev_read_id(dev, &dev->class,
 						     readid_flags, dev->id);
 			/* read_id might have changed class, store and reset */
 			ehc->classes[dev->devno] = dev->class;
 			dev->class = ATA_DEV_UNKNOWN;
 			switch (rc) {
 			case 0:
 				/* clear error info accumulated during probe */
 				ata_ering_clear(&dev->ering);
 				new_mask |= 1 << dev->devno;
 				break;
 			case -ENOENT:
 				/* IDENTIFY was issued to non-existent
 				 * device.  No need to reset.  Just
 				 * thaw and ignore the device.
 				 */
 				ata_eh_thaw_port(ap);
 				break;
 			default:
 				goto err;
 			}
 		}
 	}
 	/* PDIAG- should have been released, ask cable type if post-reset */
 	if ((ehc->i.flags & ATA_EHI_DID_RESET) && ata_is_host_link(link)) {
 		if (ap->ops->cable_detect)
 			ap->cbl = ap->ops->cable_detect(ap);
 		ata_force_cbl(ap);
 	}
 	/* Configure new devices forward such that user doesn't see
 	 * device detection messages backwards.
 	 */
 	ata_for_each_dev(dev, link, ALL) {
 		if (!(new_mask & (1 << dev->devno)))
 			continue;
 		dev->class = ehc->classes[dev->devno];
 		if (dev->class == ATA_DEV_PMP)
 			continue;
 		ehc->i.flags |= ATA_EHI_PRINTINFO;
 		rc = ata_dev_configure(dev);
 		ehc->i.flags &= ~ATA_EHI_PRINTINFO;
 		if (rc) {
 			dev->class = ATA_DEV_UNKNOWN;
 			goto err;
 		}
 		spin_lock_irqsave(ap->lock, flags);
 		ap->pflags |= ATA_PFLAG_SCSI_HOTPLUG;
 		spin_unlock_irqrestore(ap->lock, flags);
 		/* new device discovered, configure xfermode */
 		ehc->i.flags |= ATA_EHI_SETMODE;
 	}
 	return 0;
  err:
 	*r_failed_dev = dev;
 	DPRINTK("EXIT rc=%d\n", rc);
 	return rc;
 }
 /**
  *	ata_set_mode - Program timings and issue SET FEATURES - XFER
  *	@link: link on which timings will be programmed
  *	@r_failed_dev: out parameter for failed device
  *
  *	Set ATA device disk transfer mode (PIO3, UDMA6, etc.).  If
  *	ata_set_mode() fails, pointer to the failing device is
  *	returned in @r_failed_dev.
  *
  *	LOCKING:
  *	PCI/etc. bus probe sem.
  *
  *	RETURNS:
  *	0 on success, negative errno otherwise
  */
 int ata_set_mode(struct ata_link *link, struct ata_device **r_failed_dev)
 {
 	struct ata_port *ap = link->ap;
 	struct ata_device *dev;
 	int rc;
 	/* if data transfer is verified, clear DUBIOUS_XFER on ering top */
 	ata_for_each_dev(dev, link, ENABLED) {
 		if (!(dev->flags & ATA_DFLAG_DUBIOUS_XFER)) {
 			struct ata_ering_entry *ent;
 			ent = ata_ering_top(&dev->ering);
 			if (ent)
 				ent->eflags &= ~ATA_EFLAG_DUBIOUS_XFER;
 		}
 	}
 	/* has private set_mode? */
 	if (ap->ops->set_mode)
 		rc = ap->ops->set_mode(link, r_failed_dev);
 	else
 		rc = ata_do_set_mode(link, r_failed_dev);
 	/* if transfer mode has changed, set DUBIOUS_XFER on device */
 	ata_for_each_dev(dev, link, ENABLED) {
 		struct ata_eh_context *ehc = &link->eh_context;
 		u8 saved_xfer_mode = ehc->saved_xfer_mode[dev->devno];
 		u8 saved_ncq = !!(ehc->saved_ncq_enabled & (1 << dev->devno));
 		if (dev->xfer_mode != saved_xfer_mode ||
 		    ata_ncq_enabled(dev) != saved_ncq)
 			dev->flags |= ATA_DFLAG_DUBIOUS_XFER;
 	}
 	return rc;
 }
 /**
  *	atapi_eh_clear_ua - Clear ATAPI UNIT ATTENTION after reset
  *	@dev: ATAPI device to clear UA for
  *
  *	Resets and other operations can make an ATAPI device raise
  *	UNIT ATTENTION which causes the next operation to fail.  This
  *	function clears UA.
  *
  *	LOCKING:
  *	EH context (may sleep).
  *
  *	RETURNS:
  *	0 on success, -errno on failure.
  */
 static int atapi_eh_clear_ua(struct ata_device *dev)
 {
 	int i;
 	for (i = 0; i < ATA_EH_UA_TRIES; i++) {
 		u8 *sense_buffer = dev->link->ap->sector_buf;
 		u8 sense_key = 0;
 		unsigned int err_mask;
 		err_mask = atapi_eh_tur(dev, &sense_key);
 		if (err_mask != 0 && err_mask != AC_ERR_DEV) {
 			ata_dev_printk(dev, KERN_WARNING, "TEST_UNIT_READY "
 				"failed (err_mask=0x%x)\n", err_mask);
 			return -EIO;
 		}
 		if (!err_mask || sense_key != UNIT_ATTENTION)
 			return 0;
 		err_mask = atapi_eh_request_sense(dev, sense_buffer, sense_key);
 		if (err_mask) {
 			ata_dev_printk(dev, KERN_WARNING, "failed to clear "
 				"UNIT ATTENTION (err_mask=0x%x)\n", err_mask);
 			return -EIO;
 		}
 	}
 	ata_dev_printk(dev, KERN_WARNING,
 		"UNIT ATTENTION persists after %d tries\n", ATA_EH_UA_TRIES);
 	return 0;
 }
 /**
  *	ata_eh_maybe_retry_flush - Retry FLUSH if necessary
  *	@dev: ATA device which may need FLUSH retry
  *
  *	If @dev failed FLUSH, it needs to be reported upper layer
  *	immediately as it means that @dev failed to remap and already
  *	lost at least a sector and further FLUSH retrials won't make
  *	any difference to the lost sector.  However, if FLUSH failed
  *	for other reasons, for example transmission error, FLUSH needs
  *	to be retried.
  *
  *	This function determines whether FLUSH failure retry is
  *	necessary and performs it if so.
  *
  *	RETURNS:
  *	0 if EH can continue, -errno if EH needs to be repeated.
  */
 static int ata_eh_maybe_retry_flush(struct ata_device *dev)
 {
 	struct ata_link *link = dev->link;
 	struct ata_port *ap = link->ap;
 	struct ata_queued_cmd *qc;
 	struct ata_taskfile tf;
 	unsigned int err_mask;
 	int rc = 0;
 	/* did flush fail for this device? */
 	if (!ata_tag_valid(link->active_tag))
 		return 0;
 	qc = __ata_qc_from_tag(ap, link->active_tag);
 	if (qc->dev != dev || (qc->tf.command != ATA_CMD_FLUSH_EXT &&
 			       qc->tf.command != ATA_CMD_FLUSH))
 		return 0;
 	/* if the device failed it, it should be reported to upper layers */
 	if (qc->err_mask & AC_ERR_DEV)
 		return 0;
 	/* flush failed for some other reason, give it another shot */
 	ata_tf_init(dev, &tf);
 	tf.command = qc->tf.command;
 	tf.flags |= ATA_TFLAG_DEVICE;
 	tf.protocol = ATA_PROT_NODATA;
 	ata_dev_printk(dev, KERN_WARNING, "retrying FLUSH 0x%x Emask 0x%x\n",
 		       tf.command, qc->err_mask);
 	err_mask = ata_exec_internal(dev, &tf, NULL, DMA_NONE, NULL, 0, 0);
 	if (!err_mask) {
 		/*
 		 * FLUSH is complete but there's no way to
 		 * successfully complete a failed command from EH.
 		 * Making sure retry is allowed at least once and
 		 * retrying it should do the trick - whatever was in
 		 * the cache is already on the platter and this won't
 		 * cause infinite loop.
 		 */
 		qc->scsicmd->allowed = max(qc->scsicmd->allowed, 1);
 	} else {
 		ata_dev_printk(dev, KERN_WARNING, "FLUSH failed Emask 0x%x\n",
 			       err_mask);
 		rc = -EIO;
 		/* if device failed it, report it to upper layers */
 		if (err_mask & AC_ERR_DEV) {
 			qc->err_mask |= AC_ERR_DEV;
 			qc->result_tf = tf;
 			if (!(ap->pflags & ATA_PFLAG_FROZEN))
 				rc = 0;
 		}
 	}
 	return rc;
 }
 static int ata_link_nr_enabled(struct ata_link *link)
 {
 	struct ata_device *dev;
 	int cnt = 0;
 	ata_for_each_dev(dev, link, ENABLED)
 		cnt++;
 	return cnt;
 }
 static int ata_link_nr_vacant(struct ata_link *link)
 {
 	struct ata_device *dev;
 	int cnt = 0;
 	ata_for_each_dev(dev, link, ALL)
 		if (dev->class == ATA_DEV_UNKNOWN)
 			cnt++;
 	return cnt;
 }
 static int ata_eh_skip_recovery(struct ata_link *link)
 {
 	struct ata_port *ap = link->ap;
 	struct ata_eh_context *ehc = &link->eh_context;
 	struct ata_device *dev;
 	/* skip disabled links */
 	if (link->flags & ATA_LFLAG_DISABLED)
 		return 1;
+	/* skip if explicitly requested */
+	if (ehc->i.flags & ATA_EHI_NO_RECOVERY)
+		return 1;
 	/* thaw frozen port and recover failed devices */
 	if ((ap->pflags & ATA_PFLAG_FROZEN) || ata_link_nr_enabled(link))
 		return 0;
 	/* reset at least once if reset is requested */
 	if ((ehc->i.action & ATA_EH_RESET) &&
 	    !(ehc->i.flags & ATA_EHI_DID_RESET))
 		return 0;
 	/* skip if class codes for all vacant slots are ATA_DEV_NONE */
 	ata_for_each_dev(dev, link, ALL) {
 		if (dev->class == ATA_DEV_UNKNOWN &&
 		    ehc->classes[dev->devno] != ATA_DEV_NONE)
 			return 0;
 	}
 	return 1;
 }
 static int ata_count_probe_trials_cb(struct ata_ering_entry *ent, void *void_arg)
 {
 	u64 interval = msecs_to_jiffies(ATA_EH_PROBE_TRIAL_INTERVAL);
 	u64 now = get_jiffies_64();
 	int *trials = void_arg;
 	if (ent->timestamp < now - min(now, interval))
 		return -1;
 	(*trials)++;
 	return 0;
 }
 static int ata_eh_schedule_probe(struct ata_device *dev)
 {
 	struct ata_eh_context *ehc = &dev->link->eh_context;
 	struct ata_link *link = ata_dev_phys_link(dev);
 	int trials = 0;
 	if (!(ehc->i.probe_mask & (1 << dev->devno)) ||
 	    (ehc->did_probe_mask & (1 << dev->devno)))
 		return 0;
 	ata_eh_detach_dev(dev);
 	ata_dev_init(dev);
 	ehc->did_probe_mask |= (1 << dev->devno);
 	ehc->i.action |= ATA_EH_RESET;
 	ehc->saved_xfer_mode[dev->devno] = 0;
 	ehc->saved_ncq_enabled &= ~(1 << dev->devno);
 	/* Record and count probe trials on the ering.  The specific
 	 * error mask used is irrelevant.  Because a successful device
 	 * detection clears the ering, this count accumulates only if
 	 * there are consecutive failed probes.
 	 *
 	 * If the count is equal to or higher than ATA_EH_PROBE_TRIALS
 	 * in the last ATA_EH_PROBE_TRIAL_INTERVAL, link speed is
 	 * forced to 1.5Gbps.
 	 *
 	 * This is to work around cases where failed link speed
 	 * negotiation results in device misdetection leading to
 	 * infinite DEVXCHG or PHRDY CHG events.
 	 */
 	ata_ering_record(&dev->ering, 0, AC_ERR_OTHER);
 	ata_ering_map(&dev->ering, ata_count_probe_trials_cb, &trials);
 	if (trials > ATA_EH_PROBE_TRIALS)
 		sata_down_spd_limit(link, 1);
 	return 1;
 }
 static int ata_eh_handle_dev_fail(struct ata_device *dev, int err)
 {
 	struct ata_eh_context *ehc = &dev->link->eh_context;
 	/* -EAGAIN from EH routine indicates retry without prejudice.
 	 * The requester is responsible for ensuring forward progress.
 	 */
 	if (err != -EAGAIN)
 		ehc->tries[dev->devno]--;
 	switch (err) {
 	case -ENODEV:
 		/* device missing or wrong IDENTIFY data, schedule probing */
 		ehc->i.probe_mask |= (1 << dev->devno);
 	case -EINVAL:
 		/* give it just one more chance */
 		ehc->tries[dev->devno] = min(ehc->tries[dev->devno], 1);
 	case -EIO:
 		if (ehc->tries[dev->devno] == 1) {
 			/* This is the last chance, better to slow
 			 * down than lose it.
 			 */
 			sata_down_spd_limit(ata_dev_phys_link(dev), 0);
 			if (dev->pio_mode > XFER_PIO_0)
 				ata_down_xfermask_limit(dev, ATA_DNXFER_PIO);
 		}
 	}
 	if (ata_dev_enabled(dev) && !ehc->tries[dev->devno]) {
 		/* disable device if it has used up all its chances */
 		ata_dev_disable(dev);
 		/* detach if offline */
 		if (ata_phys_link_offline(ata_dev_phys_link(dev)))
 			ata_eh_detach_dev(dev);
 		/* schedule probe if necessary */
 		if (ata_eh_schedule_probe(dev)) {
 			ehc->tries[dev->devno] = ATA_EH_DEV_TRIES;
 			memset(ehc->cmd_timeout_idx[dev->devno], 0,
 			       sizeof(ehc->cmd_timeout_idx[dev->devno]));
 		}
 		return 1;
 	} else {
 		ehc->i.action |= ATA_EH_RESET;
 		return 0;
 	}
 }
 /**
  *	ata_eh_recover - recover host port after error
  *	@ap: host port to recover
  *	@prereset: prereset method (can be NULL)
  *	@softreset: softreset method (can be NULL)
  *	@hardreset: hardreset method (can be NULL)
  *	@postreset: postreset method (can be NULL)
  *	@r_failed_link: out parameter for failed link
  *
  *	This is the alpha and omega, eum and yang, heart and soul of
  *	libata exception handling.  On entry, actions required to
  *	recover each link and hotplug requests are recorded in the
  *	link's eh_context.  This function executes all the operations
  *	with appropriate retrials and fallbacks to resurrect failed
  *	devices, detach goners and greet newcomers.
  *
  *	LOCKING:
  *	Kernel thread context (may sleep).
  *
  *	RETURNS:
  *	0 on success, -errno on failure.
  */
 int ata_eh_recover(struct ata_port *ap, ata_prereset_fn_t prereset,
 		   ata_reset_fn_t softreset, ata_reset_fn_t hardreset,
 		   ata_postreset_fn_t postreset,
 		   struct ata_link **r_failed_link)
 {
 	struct ata_link *link;
 	struct ata_device *dev;
 	int nr_failed_devs;
 	int rc;
 	unsigned long flags, deadline;
 	DPRINTK("ENTER\n");
 	/* prep for recovery */
 	ata_for_each_link(link, ap, EDGE) {
 		struct ata_eh_context *ehc = &link->eh_context;
 		/* re-enable link? */
 		if (ehc->i.action & ATA_EH_ENABLE_LINK) {
 			ata_eh_about_to_do(link, NULL, ATA_EH_ENABLE_LINK);
 			spin_lock_irqsave(ap->lock, flags);
 			link->flags &= ~ATA_LFLAG_DISABLED;
 			spin_unlock_irqrestore(ap->lock, flags);
 			ata_eh_done(link, NULL, ATA_EH_ENABLE_LINK);
 		}
 		ata_for_each_dev(dev, link, ALL) {
 			if (link->flags & ATA_LFLAG_NO_RETRY)
 				ehc->tries[dev->devno] = 1;
 			else
 				ehc->tries[dev->devno] = ATA_EH_DEV_TRIES;
 			/* collect port action mask recorded in dev actions */
 			ehc->i.action |= ehc->i.dev_action[dev->devno] &
 					 ~ATA_EH_PERDEV_MASK;
 			ehc->i.dev_action[dev->devno] &= ATA_EH_PERDEV_MASK;
 			/* process hotplug request */
 			if (dev->flags & ATA_DFLAG_DETACH)
 				ata_eh_detach_dev(dev);
 			/* schedule probe if necessary */
 			if (!ata_dev_enabled(dev))
 				ata_eh_schedule_probe(dev);
 		}
 	}
  retry:
 	rc = 0;
 	nr_failed_devs = 0;
 	/* if UNLOADING, finish immediately */
 	if (ap->pflags & ATA_PFLAG_UNLOADING)
 		goto out;
 	/* prep for EH */
 	ata_for_each_link(link, ap, EDGE) {
 		struct ata_eh_context *ehc = &link->eh_context;
 		/* skip EH if possible. */
 		if (ata_eh_skip_recovery(link))
 			ehc->i.action = 0;
 		ata_for_each_dev(dev, link, ALL)
 			ehc->classes[dev->devno] = ATA_DEV_UNKNOWN;
 	}
 	/* reset */
 	ata_for_each_link(link, ap, EDGE) {
 		struct ata_eh_context *ehc = &link->eh_context;
 		if (!(ehc->i.action & ATA_EH_RESET))
 			continue;
 		rc = ata_eh_reset(link, ata_link_nr_vacant(link),
 				  prereset, softreset, hardreset, postreset);
 		if (rc) {
 			ata_link_printk(link, KERN_ERR,
 					"reset failed, giving up\n");
 			goto out;
 		}
 	}
 	do {
 		unsigned long now;
 		/*
 		 * clears ATA_EH_PARK in eh_info and resets
 		 * ap->park_req_pending
 		 */
 		ata_eh_pull_park_action(ap);
 		deadline = jiffies;
 		ata_for_each_link(link, ap, EDGE) {
 			ata_for_each_dev(dev, link, ALL) {
 				struct ata_eh_context *ehc = &link->eh_context;
 				unsigned long tmp;
 				if (dev->class != ATA_DEV_ATA)
 					continue;
 				if (!(ehc->i.dev_action[dev->devno] &
 				      ATA_EH_PARK))
 					continue;
 				tmp = dev->unpark_deadline;
 				if (time_before(deadline, tmp))
 					deadline = tmp;
 				else if (time_before_eq(tmp, jiffies))
 					continue;
 				if (ehc->unloaded_mask & (1 << dev->devno))
 					continue;
 				ata_eh_park_issue_cmd(dev, 1);
 			}
 		}
 		now = jiffies;
 		if (time_before_eq(deadline, now))
 			break;
 		deadline = wait_for_completion_timeout(&ap->park_req_pending,
 						       deadline - now);
 	} while (deadline);
 	ata_for_each_link(link, ap, EDGE) {
 		ata_for_each_dev(dev, link, ALL) {
 			if (!(link->eh_context.unloaded_mask &
 			      (1 << dev->devno)))
 				continue;
 			ata_eh_park_issue_cmd(dev, 0);
 			ata_eh_done(link, dev, ATA_EH_PARK);
 		}
 	}
 	/* the rest */
 	ata_for_each_link(link, ap, EDGE) {
 		struct ata_eh_context *ehc = &link->eh_context;
 		/* revalidate existing devices and attach new ones */
 		rc = ata_eh_revalidate_and_attach(link, &dev);
 		if (rc)
 			goto dev_fail;
 		/* if PMP got attached, return, pmp EH will take care of it */
 		if (link->device->class == ATA_DEV_PMP) {
 			ehc->i.action = 0;
 			return 0;
 		}
 		/* configure transfer mode if necessary */
 		if (ehc->i.flags & ATA_EHI_SETMODE) {
 			rc = ata_set_mode(link, &dev);
 			if (rc)
 				goto dev_fail;
 			ehc->i.flags &= ~ATA_EHI_SETMODE;
 		}
 		/* If reset has been issued, clear UA to avoid
 		 * disrupting the current users of the device.
 		 */
 		if (ehc->i.flags & ATA_EHI_DID_RESET) {
 			ata_for_each_dev(dev, link, ALL) {
 				if (dev->class != ATA_DEV_ATAPI)
 					continue;
 				rc = atapi_eh_clear_ua(dev);
 				if (rc)
 					goto dev_fail;
 			}
 		}
 		/* retry flush if necessary */
 		ata_for_each_dev(dev, link, ALL) {
 			if (dev->class != ATA_DEV_ATA)
 				continue;
 			rc = ata_eh_maybe_retry_flush(dev);
 			if (rc)
 				goto dev_fail;
 		}
 		/* configure link power saving */
 		if (ehc->i.action & ATA_EH_LPM)
 			ata_for_each_dev(dev, link, ALL)
 				ata_dev_enable_pm(dev, ap->pm_policy);
 		/* this link is okay now */
 		ehc->i.flags = 0;
 		continue;
 dev_fail:
 		nr_failed_devs++;
 		ata_eh_handle_dev_fail(dev, rc);
 		if (ap->pflags & ATA_PFLAG_FROZEN) {
 			/* PMP reset requires working host port.
 			 * Can't retry if it's frozen.
 			 */
 			if (sata_pmp_attached(ap))
 				goto out;
 			break;
 		}
 	}
 	if (nr_failed_devs)
 		goto retry;
  out:
 	if (rc && r_failed_link)
 		*r_failed_link = link;
 	DPRINTK("EXIT, rc=%d\n", rc);
 	return rc;
 }
 /**
  *	ata_eh_finish - finish up EH
  *	@ap: host port to finish EH for
  *
  *	Recovery is complete.  Clean up EH states and retry or finish
  *	failed qcs.
  *
  *	LOCKING:
  *	None.
  */
 void ata_eh_finish(struct ata_port *ap)
 {
 	int tag;
 	/* retry or finish qcs */
 	for (tag = 0; tag < ATA_MAX_QUEUE; tag++) {
 		struct ata_queued_cmd *qc = __ata_qc_from_tag(ap, tag);
 		if (!(qc->flags & ATA_QCFLAG_FAILED))
 			continue;
 		if (qc->err_mask) {
 			/* FIXME: Once EH migration is complete,
 			 * generate sense data in this function,
 			 * considering both err_mask and tf.
 			 */
 			if (qc->flags & ATA_QCFLAG_RETRY)
 				ata_eh_qc_retry(qc);
 			else
 				ata_eh_qc_complete(qc);
 		} else {
 			if (qc->flags & ATA_QCFLAG_SENSE_VALID) {
 				ata_eh_qc_complete(qc);
 			} else {
 				/* feed zero TF to sense generation */
 				memset(&qc->result_tf, 0, sizeof(qc->result_tf));
 				ata_eh_qc_retry(qc);
 			}
 		}
 	}
 	/* make sure nr_active_links is zero after EH */
 	WARN_ON(ap->nr_active_links);
 	ap->nr_active_links = 0;
 }
 /**
  *	ata_do_eh - do standard error handling
  *	@ap: host port to handle error for
  *
  *	@prereset: prereset method (can be NULL)
  *	@softreset: softreset method (can be NULL)
  *	@hardreset: hardreset method (can be NULL)
  *	@postreset: postreset method (can be NULL)
  *
  *	Perform standard error handling sequence.
  *
  *	LOCKING:
  *	Kernel thread context (may sleep).
  */
 void ata_do_eh(struct ata_port *ap, ata_prereset_fn_t prereset,
 	       ata_reset_fn_t softreset, ata_reset_fn_t hardreset,
 	       ata_postreset_fn_t postreset)
 {
 	struct ata_device *dev;
 	int rc;
 	ata_eh_autopsy(ap);
 	ata_eh_report(ap);
 	rc = ata_eh_recover(ap, prereset, softreset, hardreset, postreset,
 			    NULL);
 	if (rc) {
 		ata_for_each_dev(dev, &ap->link, ALL)
 			ata_dev_disable(dev);
 	}
 	ata_eh_finish(ap);
 }
 /**
  *	ata_std_error_handler - standard error handler
  *	@ap: host port to handle error for
  *
  *	Standard error handler
  *
  *	LOCKING:
  *	Kernel thread context (may sleep).
  */
 void ata_std_error_handler(struct ata_port *ap)
 {
 	struct ata_port_operations *ops = ap->ops;
 	ata_reset_fn_t hardreset = ops->hardreset;
 	/* ignore built-in hardreset if SCR access is not available */
 	if (hardreset == sata_std_hardreset && !sata_scr_valid(&ap->link))
 		hardreset = NULL;
 	ata_do_eh(ap, ops->prereset, ops->softreset, hardreset, ops->postreset);
 }
 #ifdef CONFIG_PM
 /**
  *	ata_eh_handle_port_suspend - perform port suspend operation
  *	@ap: port to suspend
  *
  *	Suspend @ap.
  *
  *	LOCKING:
  *	Kernel thread context (may sleep).
  */
 static void ata_eh_handle_port_suspend(struct ata_port *ap)
 {
 	unsigned long flags;
 	int rc = 0;
 	/* are we suspending? */
 	spin_lock_irqsave(ap->lock, flags);
 	if (!(ap->pflags & ATA_PFLAG_PM_PENDING) ||
 	    ap->pm_mesg.event == PM_EVENT_ON) {
 		spin_unlock_irqrestore(ap->lock, flags);
 		return;
 	}
 	spin_unlock_irqrestore(ap->lock, flags);
 	WARN_ON(ap->pflags & ATA_PFLAG_SUSPENDED);
 	/* tell ACPI we're suspending */
 	rc = ata_acpi_on_suspend(ap);
 	if (rc)
 		goto out;
 	/* suspend */
 	ata_eh_freeze_port(ap);
 	if (ap->ops->port_suspend)
 		rc = ap->ops->port_suspend(ap, ap->pm_mesg);
 	ata_acpi_set_state(ap, PMSG_SUSPEND);
  out:
 	/* report result */
 	spin_lock_irqsave(ap->lock, flags);
 	ap->pflags &= ~ATA_PFLAG_PM_PENDING;
 	if (rc == 0)
 		ap->pflags |= ATA_PFLAG_SUSPENDED;
 	else if (ap->pflags & ATA_PFLAG_FROZEN)
 		ata_port_schedule_eh(ap);
 	if (ap->pm_result) {
 		*ap->pm_result = rc;
 		ap->pm_result = NULL;
 	}
 	spin_unlock_irqrestore(ap->lock, flags);
 	return;
 }
 /**
  *	ata_eh_handle_port_resume - perform port resume operation
  *	@ap: port to resume
  *
  *	Resume @ap.
  *
  *	LOCKING:
  *	Kernel thread context (may sleep).
  */
 static void ata_eh_handle_port_resume(struct ata_port *ap)
 {
 	struct ata_link *link;
 	struct ata_device *dev;
 	unsigned long flags;
 	int rc = 0;
 	/* are we resuming? */
 	spin_lock_irqsave(ap->lock, flags);
 	if (!(ap->pflags & ATA_PFLAG_PM_PENDING) ||
 	    ap->pm_mesg.event != PM_EVENT_ON) {
 		spin_unlock_irqrestore(ap->lock, flags);
 		return;
 	}
 	spin_unlock_irqrestore(ap->lock, flags);
 	WARN_ON(!(ap->pflags & ATA_PFLAG_SUSPENDED));
 	/*
 	 * Error timestamps are in jiffies which doesn't run while
 	 * suspended and PHY events during resume isn't too uncommon.
 	 * When the two are combined, it can lead to unnecessary speed
 	 * downs if the machine is suspended and resumed repeatedly.
 	 * Clear error history.
 	 */
 	ata_for_each_link(link, ap, HOST_FIRST)
 		ata_for_each_dev(dev, link, ALL)
 			ata_ering_clear(&dev->ering);
 	ata_acpi_set_state(ap, PMSG_ON);
 	if (ap->ops->port_resume)
 		rc = ap->ops->port_resume(ap);
 	/* tell ACPI that we're resuming */
 	ata_acpi_on_resume(ap);
 	/* report result */
 	spin_lock_irqsave(ap->lock, flags);
 	ap->pflags &= ~(ATA_PFLAG_PM_PENDING | ATA_PFLAG_SUSPENDED);
 	if (ap->pm_result) {
 		*ap->pm_result = rc;
 		ap->pm_result = NULL;
 	}
 	spin_unlock_irqrestore(ap->lock, flags);
 }
 #endif /* CONFIG_PM */

drivers/ata/libata-sff.c

Diff comments View file @ df423dc

 /*
  *  libata-sff.c - helper library for PCI IDE BMDMA
  *
  *  Maintained by:  Jeff Garzik <jgarzik@pobox.com>
  *    		    Please ALWAYS copy linux-ide@vger.kernel.org
  *		    on emails.
  *
  *  Copyright 2003-2006 Red Hat, Inc.  All rights reserved.
  *  Copyright 2003-2006 Jeff Garzik
  *
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
  *  the Free Software Foundation; either version 2, or (at your option)
  *  any later version.
  *
  *  This program is distributed in the hope that it will be useful,
  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  *  GNU General Public License for more details.
  *
  *  You should have received a copy of the GNU General Public License
  *  along with this program; see the file COPYING.  If not, write to
  *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  *
  *
  *  libata documentation is available via 'make {ps|pdf}docs',
  *  as Documentation/DocBook/libata.*
  *
  *  Hardware documentation available from http://www.t13.org/ and
  *  http://www.sata-io.org/
  *
  */
 #include <linux/kernel.h>
 #include <linux/gfp.h>
 #include <linux/pci.h>
 #include <linux/libata.h>
 #include <linux/highmem.h>
 #include "libata.h"
 static struct workqueue_struct *ata_sff_wq;
 const struct ata_port_operations ata_sff_port_ops = {
 	.inherits		= &ata_base_port_ops,
 	.qc_prep		= ata_noop_qc_prep,
 	.qc_issue		= ata_sff_qc_issue,
 	.qc_fill_rtf		= ata_sff_qc_fill_rtf,
 	.freeze			= ata_sff_freeze,
 	.thaw			= ata_sff_thaw,
 	.prereset		= ata_sff_prereset,
 	.softreset		= ata_sff_softreset,
 	.hardreset		= sata_sff_hardreset,
 	.postreset		= ata_sff_postreset,
 	.error_handler		= ata_sff_error_handler,
 	.sff_dev_select		= ata_sff_dev_select,
 	.sff_check_status	= ata_sff_check_status,
 	.sff_tf_load		= ata_sff_tf_load,
 	.sff_tf_read		= ata_sff_tf_read,
 	.sff_exec_command	= ata_sff_exec_command,
 	.sff_data_xfer		= ata_sff_data_xfer,
 	.sff_drain_fifo		= ata_sff_drain_fifo,
 	.lost_interrupt		= ata_sff_lost_interrupt,
 };
 EXPORT_SYMBOL_GPL(ata_sff_port_ops);
 /**
  *	ata_sff_check_status - Read device status reg & clear interrupt
  *	@ap: port where the device is
  *
  *	Reads ATA taskfile status register for currently-selected device
  *	and return its value. This also clears pending interrupts
  *      from this device
  *
  *	LOCKING:
  *	Inherited from caller.
  */
 u8 ata_sff_check_status(struct ata_port *ap)
 {
 	return ioread8(ap->ioaddr.status_addr);
 }
 EXPORT_SYMBOL_GPL(ata_sff_check_status);
 /**
  *	ata_sff_altstatus - Read device alternate status reg
  *	@ap: port where the device is
  *
  *	Reads ATA taskfile alternate status register for
  *	currently-selected device and return its value.
  *
  *	Note: may NOT be used as the check_altstatus() entry in
  *	ata_port_operations.
  *
  *	LOCKING:
  *	Inherited from caller.
  */
 static u8 ata_sff_altstatus(struct ata_port *ap)
 {
 	if (ap->ops->sff_check_altstatus)
 		return ap->ops->sff_check_altstatus(ap);
 	return ioread8(ap->ioaddr.altstatus_addr);
 }
 /**
  *	ata_sff_irq_status - Check if the device is busy
  *	@ap: port where the device is
  *
  *	Determine if the port is currently busy. Uses altstatus
  *	if available in order to avoid clearing shared IRQ status
  *	when finding an IRQ source. Non ctl capable devices don't
  *	share interrupt lines fortunately for us.
  *
  *	LOCKING:
  *	Inherited from caller.
  */
 static u8 ata_sff_irq_status(struct ata_port *ap)
 {
 	u8 status;
 	if (ap->ops->sff_check_altstatus || ap->ioaddr.altstatus_addr) {
 		status = ata_sff_altstatus(ap);
 		/* Not us: We are busy */
 		if (status & ATA_BUSY)
 			return status;
 	}
 	/* Clear INTRQ latch */
 	status = ap->ops->sff_check_status(ap);
 	return status;
 }
 /**
  *	ata_sff_sync - Flush writes
  *	@ap: Port to wait for.
  *
  *	CAUTION:
  *	If we have an mmio device with no ctl and no altstatus
  *	method this will fail. No such devices are known to exist.
  *
  *	LOCKING:
  *	Inherited from caller.
  */
 static void ata_sff_sync(struct ata_port *ap)
 {
 	if (ap->ops->sff_check_altstatus)
 		ap->ops->sff_check_altstatus(ap);
 	else if (ap->ioaddr.altstatus_addr)
 		ioread8(ap->ioaddr.altstatus_addr);
 }
 /**
  *	ata_sff_pause		-	Flush writes and wait 400nS
  *	@ap: Port to pause for.
  *
  *	CAUTION:
  *	If we have an mmio device with no ctl and no altstatus
  *	method this will fail. No such devices are known to exist.
  *
  *	LOCKING:
  *	Inherited from caller.
  */
 void ata_sff_pause(struct ata_port *ap)
 {
 	ata_sff_sync(ap);
 	ndelay(400);
 }
 EXPORT_SYMBOL_GPL(ata_sff_pause);
 /**
  *	ata_sff_dma_pause	-	Pause before commencing DMA
  *	@ap: Port to pause for.
  *
  *	Perform I/O fencing and ensure sufficient cycle delays occur
  *	for the HDMA1:0 transition
  */
 void ata_sff_dma_pause(struct ata_port *ap)
 {
 	if (ap->ops->sff_check_altstatus || ap->ioaddr.altstatus_addr) {
 		/* An altstatus read will cause the needed delay without
 		   messing up the IRQ status */
 		ata_sff_altstatus(ap);
 		return;
 	}
 	/* There are no DMA controllers without ctl. BUG here to ensure
 	   we never violate the HDMA1:0 transition timing and risk
 	   corruption. */
 	BUG();
 }
 EXPORT_SYMBOL_GPL(ata_sff_dma_pause);
 /**
  *	ata_sff_busy_sleep - sleep until BSY clears, or timeout
  *	@ap: port containing status register to be polled
  *	@tmout_pat: impatience timeout in msecs
  *	@tmout: overall timeout in msecs
  *
  *	Sleep until ATA Status register bit BSY clears,
  *	or a timeout occurs.
  *
  *	LOCKING:
  *	Kernel thread context (may sleep).
  *
  *	RETURNS:
  *	0 on success, -errno otherwise.
  */
 int ata_sff_busy_sleep(struct ata_port *ap,
 		       unsigned long tmout_pat, unsigned long tmout)
 {
 	unsigned long timer_start, timeout;
 	u8 status;
 	status = ata_sff_busy_wait(ap, ATA_BUSY, 300);
 	timer_start = jiffies;
 	timeout = ata_deadline(timer_start, tmout_pat);
 	while (status != 0xff && (status & ATA_BUSY) &&
 	       time_before(jiffies, timeout)) {
 		msleep(50);
 		status = ata_sff_busy_wait(ap, ATA_BUSY, 3);
 	}
 	if (status != 0xff && (status & ATA_BUSY))
 		ata_port_printk(ap, KERN_WARNING,
 				"port is slow to respond, please be patient "
 				"(Status 0x%x)\n", status);
 	timeout = ata_deadline(timer_start, tmout);
 	while (status != 0xff && (status & ATA_BUSY) &&
 	       time_before(jiffies, timeout)) {
 		msleep(50);
 		status = ap->ops->sff_check_status(ap);
 	}
 	if (status == 0xff)
 		return -ENODEV;
 	if (status & ATA_BUSY) {
 		ata_port_printk(ap, KERN_ERR, "port failed to respond "
 				"(%lu secs, Status 0x%x)\n",
 				DIV_ROUND_UP(tmout, 1000), status);
 		return -EBUSY;
 	}
 	return 0;
 }
 EXPORT_SYMBOL_GPL(ata_sff_busy_sleep);
 static int ata_sff_check_ready(struct ata_link *link)
 {
 	u8 status = link->ap->ops->sff_check_status(link->ap);
 	return ata_check_ready(status);
 }
 /**
  *	ata_sff_wait_ready - sleep until BSY clears, or timeout
  *	@link: SFF link to wait ready status for
  *	@deadline: deadline jiffies for the operation
  *
  *	Sleep until ATA Status register bit BSY clears, or timeout
  *	occurs.
  *
  *	LOCKING:
  *	Kernel thread context (may sleep).
  *
  *	RETURNS:
  *	0 on success, -errno otherwise.
  */
 int ata_sff_wait_ready(struct ata_link *link, unsigned long deadline)
 {
 	return ata_wait_ready(link, deadline, ata_sff_check_ready);
 }
 EXPORT_SYMBOL_GPL(ata_sff_wait_ready);
 /**
  *	ata_sff_set_devctl - Write device control reg
  *	@ap: port where the device is
  *	@ctl: value to write
  *
  *	Writes ATA taskfile device control register.
  *
  *	Note: may NOT be used as the sff_set_devctl() entry in
  *	ata_port_operations.
  *
  *	LOCKING:
  *	Inherited from caller.
  */
 static void ata_sff_set_devctl(struct ata_port *ap, u8 ctl)
 {
 	if (ap->ops->sff_set_devctl)
 		ap->ops->sff_set_devctl(ap, ctl);
 	else
 		iowrite8(ctl, ap->ioaddr.ctl_addr);
 }
 /**
  *	ata_sff_dev_select - Select device 0/1 on ATA bus
  *	@ap: ATA channel to manipulate
  *	@device: ATA device (numbered from zero) to select
  *
  *	Use the method defined in the ATA specification to
  *	make either device 0, or device 1, active on the
  *	ATA channel.  Works with both PIO and MMIO.
  *
  *	May be used as the dev_select() entry in ata_port_operations.
  *
  *	LOCKING:
  *	caller.
  */
 void ata_sff_dev_select(struct ata_port *ap, unsigned int device)
 {
 	u8 tmp;
 	if (device == 0)
 		tmp = ATA_DEVICE_OBS;
 	else
 		tmp = ATA_DEVICE_OBS | ATA_DEV1;
 	iowrite8(tmp, ap->ioaddr.device_addr);
 	ata_sff_pause(ap);	/* needed; also flushes, for mmio */
 }
 EXPORT_SYMBOL_GPL(ata_sff_dev_select);
 /**
  *	ata_dev_select - Select device 0/1 on ATA bus
  *	@ap: ATA channel to manipulate
  *	@device: ATA device (numbered from zero) to select
  *	@wait: non-zero to wait for Status register BSY bit to clear
  *	@can_sleep: non-zero if context allows sleeping
  *
  *	Use the method defined in the ATA specification to
  *	make either device 0, or device 1, active on the
  *	ATA channel.
  *
  *	This is a high-level version of ata_sff_dev_select(), which
  *	additionally provides the services of inserting the proper
  *	pauses and status polling, where needed.
  *
  *	LOCKING:
  *	caller.
  */
 static void ata_dev_select(struct ata_port *ap, unsigned int device,
 			   unsigned int wait, unsigned int can_sleep)
 {
 	if (ata_msg_probe(ap))
 		ata_port_printk(ap, KERN_INFO, "ata_dev_select: ENTER, "
 				"device %u, wait %u\n", device, wait);
 	if (wait)
 		ata_wait_idle(ap);
 	ap->ops->sff_dev_select(ap, device);
 	if (wait) {
 		if (can_sleep && ap->link.device[device].class == ATA_DEV_ATAPI)
 			msleep(150);
 		ata_wait_idle(ap);
 	}
 }
 /**
  *	ata_sff_irq_on - Enable interrupts on a port.
  *	@ap: Port on which interrupts are enabled.
  *
  *	Enable interrupts on a legacy IDE device using MMIO or PIO,
  *	wait for idle, clear any pending interrupts.
  *
  *	Note: may NOT be used as the sff_irq_on() entry in
  *	ata_port_operations.
  *
  *	LOCKING:
  *	Inherited from caller.
  */
 void ata_sff_irq_on(struct ata_port *ap)
 {
 	struct ata_ioports *ioaddr = &ap->ioaddr;
 	if (ap->ops->sff_irq_on) {
 		ap->ops->sff_irq_on(ap);
 		return;
 	}
 	ap->ctl &= ~ATA_NIEN;
 	ap->last_ctl = ap->ctl;
 	if (ap->ops->sff_set_devctl || ioaddr->ctl_addr)
 		ata_sff_set_devctl(ap, ap->ctl);
 	ata_wait_idle(ap);
 	if (ap->ops->sff_irq_clear)
 		ap->ops->sff_irq_clear(ap);
 }
 EXPORT_SYMBOL_GPL(ata_sff_irq_on);
 /**
  *	ata_sff_tf_load - send taskfile registers to host controller
  *	@ap: Port to which output is sent
  *	@tf: ATA taskfile register set
  *
  *	Outputs ATA taskfile to standard ATA host controller.
  *
  *	LOCKING:
  *	Inherited from caller.
  */
 void ata_sff_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
 {
 	struct ata_ioports *ioaddr = &ap->ioaddr;
 	unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
 	if (tf->ctl != ap->last_ctl) {
 		if (ioaddr->ctl_addr)
 			iowrite8(tf->ctl, ioaddr->ctl_addr);
 		ap->last_ctl = tf->ctl;
+		ata_wait_idle(ap);
 	}
 	if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
 		WARN_ON_ONCE(!ioaddr->ctl_addr);
 		iowrite8(tf->hob_feature, ioaddr->feature_addr);
 		iowrite8(tf->hob_nsect, ioaddr->nsect_addr);
 		iowrite8(tf->hob_lbal, ioaddr->lbal_addr);
 		iowrite8(tf->hob_lbam, ioaddr->lbam_addr);
 		iowrite8(tf->hob_lbah, ioaddr->lbah_addr);
 		VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
 			tf->hob_feature,
 			tf->hob_nsect,
 			tf->hob_lbal,
 			tf->hob_lbam,
 			tf->hob_lbah);
 	}
 	if (is_addr) {
 		iowrite8(tf->feature, ioaddr->feature_addr);
 		iowrite8(tf->nsect, ioaddr->nsect_addr);
 		iowrite8(tf->lbal, ioaddr->lbal_addr);
 		iowrite8(tf->lbam, ioaddr->lbam_addr);
 		iowrite8(tf->lbah, ioaddr->lbah_addr);
 		VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
 			tf->feature,
 			tf->nsect,
 			tf->lbal,
 			tf->lbam,
 			tf->lbah);
 	}
 	if (tf->flags & ATA_TFLAG_DEVICE) {
 		iowrite8(tf->device, ioaddr->device_addr);
 		VPRINTK("device 0x%X\n", tf->device);
 	}
+	ata_wait_idle(ap);
 }
 EXPORT_SYMBOL_GPL(ata_sff_tf_load);
 /**
  *	ata_sff_tf_read - input device's ATA taskfile shadow registers
  *	@ap: Port from which input is read
  *	@tf: ATA taskfile register set for storing input
  *
  *	Reads ATA taskfile registers for currently-selected device
  *	into @tf. Assumes the device has a fully SFF compliant task file
  *	layout and behaviour. If you device does not (eg has a different
  *	status method) then you will need to provide a replacement tf_read
  *
  *	LOCKING:
  *	Inherited from caller.
  */
 void ata_sff_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
 {
 	struct ata_ioports *ioaddr = &ap->ioaddr;
 	tf->command = ata_sff_check_status(ap);
 	tf->feature = ioread8(ioaddr->error_addr);
 	tf->nsect = ioread8(ioaddr->nsect_addr);
 	tf->lbal = ioread8(ioaddr->lbal_addr);
 	tf->lbam = ioread8(ioaddr->lbam_addr);
 	tf->lbah = ioread8(ioaddr->lbah_addr);
 	tf->device = ioread8(ioaddr->device_addr);
 	if (tf->flags & ATA_TFLAG_LBA48) {
 		if (likely(ioaddr->ctl_addr)) {
 			iowrite8(tf->ctl | ATA_HOB, ioaddr->ctl_addr);
 			tf->hob_feature = ioread8(ioaddr->error_addr);
 			tf->hob_nsect = ioread8(ioaddr->nsect_addr);
 			tf->hob_lbal = ioread8(ioaddr->lbal_addr);
 			tf->hob_lbam = ioread8(ioaddr->lbam_addr);
 			tf->hob_lbah = ioread8(ioaddr->lbah_addr);
 			iowrite8(tf->ctl, ioaddr->ctl_addr);
 			ap->last_ctl = tf->ctl;
 		} else
 			WARN_ON_ONCE(1);
 	}
 }
 EXPORT_SYMBOL_GPL(ata_sff_tf_read);
 /**
  *	ata_sff_exec_command - issue ATA command to host controller
  *	@ap: port to which command is being issued
  *	@tf: ATA taskfile register set
  *
  *	Issues ATA command, with proper synchronization with interrupt
  *	handler / other threads.
  *
  *	LOCKING:
  *	spin_lock_irqsave(host lock)
  */
 void ata_sff_exec_command(struct ata_port *ap, const struct ata_taskfile *tf)
 {
 	DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
 	iowrite8(tf->command, ap->ioaddr.command_addr);
 	ata_sff_pause(ap);
 }
 EXPORT_SYMBOL_GPL(ata_sff_exec_command);
 /**
  *	ata_tf_to_host - issue ATA taskfile to host controller
  *	@ap: port to which command is being issued
  *	@tf: ATA taskfile register set
  *
  *	Issues ATA taskfile register set to ATA host controller,
  *	with proper synchronization with interrupt handler and
  *	other threads.
  *
  *	LOCKING:
  *	spin_lock_irqsave(host lock)
  */
 static inline void ata_tf_to_host(struct ata_port *ap,
 				  const struct ata_taskfile *tf)
 {
 	ap->ops->sff_tf_load(ap, tf);
 	ap->ops->sff_exec_command(ap, tf);
 }
 /**
  *	ata_sff_data_xfer - Transfer data by PIO
  *	@dev: device to target
  *	@buf: data buffer
  *	@buflen: buffer length
  *	@rw: read/write
  *
  *	Transfer data from/to the device data register by PIO.
  *
  *	LOCKING:
  *	Inherited from caller.
  *
  *	RETURNS:
  *	Bytes consumed.
  */
 unsigned int ata_sff_data_xfer(struct ata_device *dev, unsigned char *buf,
 			       unsigned int buflen, int rw)
 {
 	struct ata_port *ap = dev->link->ap;
 	void __iomem *data_addr = ap->ioaddr.data_addr;
 	unsigned int words = buflen >> 1;
 	/* Transfer multiple of 2 bytes */
 	if (rw == READ)
 		ioread16_rep(data_addr, buf, words);
 	else
 		iowrite16_rep(data_addr, buf, words);
 	/* Transfer trailing byte, if any. */
 	if (unlikely(buflen & 0x01)) {
 		unsigned char pad[2];
 		/* Point buf to the tail of buffer */
 		buf += buflen - 1;
 		/*
 		 * Use io*16_rep() accessors here as well to avoid pointlessly
 		 * swapping bytes to and from on the big endian machines...
 		 */
 		if (rw == READ) {
 			ioread16_rep(data_addr, pad, 1);
 			*buf = pad[0];
 		} else {
 			pad[0] = *buf;
 			iowrite16_rep(data_addr, pad, 1);
 		}
 		words++;
 	}
 	return words << 1;
 }
 EXPORT_SYMBOL_GPL(ata_sff_data_xfer);
 /**
  *	ata_sff_data_xfer32 - Transfer data by PIO
  *	@dev: device to target
  *	@buf: data buffer
  *	@buflen: buffer length
  *	@rw: read/write
  *
  *	Transfer data from/to the device data register by PIO using 32bit
  *	I/O operations.
  *
  *	LOCKING:
  *	Inherited from caller.
  *
  *	RETURNS:
  *	Bytes consumed.
  */
 unsigned int ata_sff_data_xfer32(struct ata_device *dev, unsigned char *buf,
 			       unsigned int buflen, int rw)
 {
 	struct ata_port *ap = dev->link->ap;
 	void __iomem *data_addr = ap->ioaddr.data_addr;
 	unsigned int words = buflen >> 2;
 	int slop = buflen & 3;
 	if (!(ap->pflags & ATA_PFLAG_PIO32))
 		return ata_sff_data_xfer(dev, buf, buflen, rw);
 	/* Transfer multiple of 4 bytes */
 	if (rw == READ)
 		ioread32_rep(data_addr, buf, words);
 	else
 		iowrite32_rep(data_addr, buf, words);
 	/* Transfer trailing bytes, if any */
 	if (unlikely(slop)) {
 		unsigned char pad[4];
 		/* Point buf to the tail of buffer */
 		buf += buflen - slop;
 		/*
 		 * Use io*_rep() accessors here as well to avoid pointlessly
 		 * swapping bytes to and from on the big endian machines...
 		 */
 		if (rw == READ) {
 			if (slop < 3)
 				ioread16_rep(data_addr, pad, 1);
 			else
 				ioread32_rep(data_addr, pad, 1);
 			memcpy(buf, pad, slop);
 		} else {
 			memcpy(pad, buf, slop);
 			if (slop < 3)
 				iowrite16_rep(data_addr, pad, 1);
 			else
 				iowrite32_rep(data_addr, pad, 1);
 		}
 	}
 	return (buflen + 1) & ~1;
 }
 EXPORT_SYMBOL_GPL(ata_sff_data_xfer32);
 /**
  *	ata_sff_data_xfer_noirq - Transfer data by PIO
  *	@dev: device to target
  *	@buf: data buffer
  *	@buflen: buffer length
  *	@rw: read/write
  *
  *	Transfer data from/to the device data register by PIO. Do the
  *	transfer with interrupts disabled.
  *
  *	LOCKING:
  *	Inherited from caller.
  *
  *	RETURNS:
  *	Bytes consumed.
  */
 unsigned int ata_sff_data_xfer_noirq(struct ata_device *dev, unsigned char *buf,
 				     unsigned int buflen, int rw)
 {
 	unsigned long flags;
 	unsigned int consumed;
 	local_irq_save(flags);
 	consumed = ata_sff_data_xfer(dev, buf, buflen, rw);
 	local_irq_restore(flags);
 	return consumed;
 }
 EXPORT_SYMBOL_GPL(ata_sff_data_xfer_noirq);
 /**
  *	ata_pio_sector - Transfer a sector of data.
  *	@qc: Command on going
  *
  *	Transfer qc->sect_size bytes of data from/to the ATA device.
  *
  *	LOCKING:
  *	Inherited from caller.
  */
 static void ata_pio_sector(struct ata_queued_cmd *qc)
 {
 	int do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
 	struct ata_port *ap = qc->ap;
 	struct page *page;
 	unsigned int offset;
 	unsigned char *buf;
 	if (qc->curbytes == qc->nbytes - qc->sect_size)
 		ap->hsm_task_state = HSM_ST_LAST;
 	page = sg_page(qc->cursg);
 	offset = qc->cursg->offset + qc->cursg_ofs;
 	/* get the current page and offset */
 	page = nth_page(page, (offset >> PAGE_SHIFT));
 	offset %= PAGE_SIZE;
 	DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
 	if (PageHighMem(page)) {
 		unsigned long flags;
 		/* FIXME: use a bounce buffer */
 		local_irq_save(flags);
 		buf = kmap_atomic(page, KM_IRQ0);
 		/* do the actual data transfer */
 		ap->ops->sff_data_xfer(qc->dev, buf + offset, qc->sect_size,
 				       do_write);
 		kunmap_atomic(buf, KM_IRQ0);
 		local_irq_restore(flags);
 	} else {
 		buf = page_address(page);
 		ap->ops->sff_data_xfer(qc->dev, buf + offset, qc->sect_size,
 				       do_write);
 	}
 	if (!do_write && !PageSlab(page))
 		flush_dcache_page(page);
 	qc->curbytes += qc->sect_size;
 	qc->cursg_ofs += qc->sect_size;
 	if (qc->cursg_ofs == qc->cursg->length) {
 		qc->cursg = sg_next(qc->cursg);
 		qc->cursg_ofs = 0;
 	}
 }
 /**
  *	ata_pio_sectors - Transfer one or many sectors.
  *	@qc: Command on going
  *
  *	Transfer one or many sectors of data from/to the
  *	ATA device for the DRQ request.
  *
  *	LOCKING:
  *	Inherited from caller.
  */
 static void ata_pio_sectors(struct ata_queued_cmd *qc)
 {
 	if (is_multi_taskfile(&qc->tf)) {
 		/* READ/WRITE MULTIPLE */
 		unsigned int nsect;
 		WARN_ON_ONCE(qc->dev->multi_count == 0);
 		nsect = min((qc->nbytes - qc->curbytes) / qc->sect_size,
 			    qc->dev->multi_count);
 		while (nsect--)
 			ata_pio_sector(qc);
 	} else
 		ata_pio_sector(qc);
 	ata_sff_sync(qc->ap); /* flush */
 }
 /**
  *	atapi_send_cdb - Write CDB bytes to hardware
  *	@ap: Port to which ATAPI device is attached.
  *	@qc: Taskfile currently active
  *
  *	When device has indicated its readiness to accept
  *	a CDB, this function is called.  Send the CDB.
  *
  *	LOCKING:
  *	caller.
  */
 static void atapi_send_cdb(struct ata_port *ap, struct ata_queued_cmd *qc)
 {
 	/* send SCSI cdb */
 	DPRINTK("send cdb\n");
 	WARN_ON_ONCE(qc->dev->cdb_len < 12);
 	ap->ops->sff_data_xfer(qc->dev, qc->cdb, qc->dev->cdb_len, 1);
 	ata_sff_sync(ap);
 	/* FIXME: If the CDB is for DMA do we need to do the transition delay
 	   or is bmdma_start guaranteed to do it ? */
 	switch (qc->tf.protocol) {
 	case ATAPI_PROT_PIO:
 		ap->hsm_task_state = HSM_ST;
 		break;
 	case ATAPI_PROT_NODATA:
 		ap->hsm_task_state = HSM_ST_LAST;
 		break;
 #ifdef CONFIG_ATA_BMDMA
 	case ATAPI_PROT_DMA:
 		ap->hsm_task_state = HSM_ST_LAST;
 		/* initiate bmdma */
 		ap->ops->bmdma_start(qc);
 		break;
 #endif /* CONFIG_ATA_BMDMA */
 	default:
 		BUG();
 	}
 }
 /**
  *	__atapi_pio_bytes - Transfer data from/to the ATAPI device.
  *	@qc: Command on going
  *	@bytes: number of bytes
  *
  *	Transfer Transfer data from/to the ATAPI device.
  *
  *	LOCKING:
  *	Inherited from caller.
  *
  */
 static int __atapi_pio_bytes(struct ata_queued_cmd *qc, unsigned int bytes)
 {
 	int rw = (qc->tf.flags & ATA_TFLAG_WRITE) ? WRITE : READ;
 	struct ata_port *ap = qc->ap;
 	struct ata_device *dev = qc->dev;
 	struct ata_eh_info *ehi = &dev->link->eh_info;
 	struct scatterlist *sg;
 	struct page *page;
 	unsigned char *buf;
 	unsigned int offset, count, consumed;
 next_sg:
 	sg = qc->cursg;
 	if (unlikely(!sg)) {
 		ata_ehi_push_desc(ehi, "unexpected or too much trailing data "
 				  "buf=%u cur=%u bytes=%u",
 				  qc->nbytes, qc->curbytes, bytes);
 		return -1;
 	}
 	page = sg_page(sg);
 	offset = sg->offset + qc->cursg_ofs;
 	/* get the current page and offset */
 	page = nth_page(page, (offset >> PAGE_SHIFT));
 	offset %= PAGE_SIZE;
 	/* don't overrun current sg */
 	count = min(sg->length - qc->cursg_ofs, bytes);
 	/* don't cross page boundaries */
 	count = min(count, (unsigned int)PAGE_SIZE - offset);
 	DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
 	if (PageHighMem(page)) {
 		unsigned long flags;
 		/* FIXME: use bounce buffer */
 		local_irq_save(flags);
 		buf = kmap_atomic(page, KM_IRQ0);
 		/* do the actual data transfer */
 		consumed = ap->ops->sff_data_xfer(dev,  buf + offset,
 								count, rw);
 		kunmap_atomic(buf, KM_IRQ0);
 		local_irq_restore(flags);
 	} else {
 		buf = page_address(page);
 		consumed = ap->ops->sff_data_xfer(dev,  buf + offset,
 								count, rw);
 	}
 	bytes -= min(bytes, consumed);
 	qc->curbytes += count;
 	qc->cursg_ofs += count;
 	if (qc->cursg_ofs == sg->length) {
 		qc->cursg = sg_next(qc->cursg);
 		qc->cursg_ofs = 0;
 	}
 	/*
 	 * There used to be a  WARN_ON_ONCE(qc->cursg && count != consumed);
 	 * Unfortunately __atapi_pio_bytes doesn't know enough to do the WARN
 	 * check correctly as it doesn't know if it is the last request being
 	 * made. Somebody should implement a proper sanity check.
 	 */
 	if (bytes)
 		goto next_sg;
 	return 0;
 }
 /**
  *	atapi_pio_bytes - Transfer data from/to the ATAPI device.
  *	@qc: Command on going
  *
  *	Transfer Transfer data from/to the ATAPI device.
  *
  *	LOCKING:
  *	Inherited from caller.
  */
 static void atapi_pio_bytes(struct ata_queued_cmd *qc)
 {
 	struct ata_port *ap = qc->ap;
 	struct ata_device *dev = qc->dev;
 	struct ata_eh_info *ehi = &dev->link->eh_info;
 	unsigned int ireason, bc_lo, bc_hi, bytes;
 	int i_write, do_write = (qc->tf.flags & ATA_TFLAG_WRITE) ? 1 : 0;
 	/* Abuse qc->result_tf for temp storage of intermediate TF
 	 * here to save some kernel stack usage.
 	 * For normal completion, qc->result_tf is not relevant. For
 	 * error, qc->result_tf is later overwritten by ata_qc_complete().
 	 * So, the correctness of qc->result_tf is not affected.
 	 */
 	ap->ops->sff_tf_read(ap, &qc->result_tf);
 	ireason = qc->result_tf.nsect;
 	bc_lo = qc->result_tf.lbam;
 	bc_hi = qc->result_tf.lbah;
 	bytes = (bc_hi << 8) | bc_lo;
 	/* shall be cleared to zero, indicating xfer of data */
 	if (unlikely(ireason & (1 << 0)))
 		goto atapi_check;
 	/* make sure transfer direction matches expected */
 	i_write = ((ireason & (1 << 1)) == 0) ? 1 : 0;
 	if (unlikely(do_write != i_write))
 		goto atapi_check;
 	if (unlikely(!bytes))
 		goto atapi_check;
 	VPRINTK("ata%u: xfering %d bytes\n", ap->print_id, bytes);
 	if (unlikely(__atapi_pio_bytes(qc, bytes)))
 		goto err_out;
 	ata_sff_sync(ap); /* flush */
 	return;
  atapi_check:
 	ata_ehi_push_desc(ehi, "ATAPI check failed (ireason=0x%x bytes=%u)",
 			  ireason, bytes);
  err_out:
 	qc->err_mask |= AC_ERR_HSM;
 	ap->hsm_task_state = HSM_ST_ERR;
 }
 /**
  *	ata_hsm_ok_in_wq - Check if the qc can be handled in the workqueue.
  *	@ap: the target ata_port
  *	@qc: qc on going
  *
  *	RETURNS:
  *	1 if ok in workqueue, 0 otherwise.
  */
 static inline int ata_hsm_ok_in_wq(struct ata_port *ap,
 						struct ata_queued_cmd *qc)
 {
 	if (qc->tf.flags & ATA_TFLAG_POLLING)
 		return 1;
 	if (ap->hsm_task_state == HSM_ST_FIRST) {
 		if (qc->tf.protocol == ATA_PROT_PIO &&
 		   (qc->tf.flags & ATA_TFLAG_WRITE))
 		    return 1;
 		if (ata_is_atapi(qc->tf.protocol) &&
 		   !(qc->dev->flags & ATA_DFLAG_CDB_INTR))
 			return 1;
 	}
 	return 0;
 }
 /**
  *	ata_hsm_qc_complete - finish a qc running on standard HSM
  *	@qc: Command to complete
  *	@in_wq: 1 if called from workqueue, 0 otherwise
  *
  *	Finish @qc which is running on standard HSM.
  *
  *	LOCKING:
  *	If @in_wq is zero, spin_lock_irqsave(host lock).
  *	Otherwise, none on entry and grabs host lock.
  */
 static void ata_hsm_qc_complete(struct ata_queued_cmd *qc, int in_wq)
 {
 	struct ata_port *ap = qc->ap;
 	unsigned long flags;
 	if (ap->ops->error_handler) {
 		if (in_wq) {
 			spin_lock_irqsave(ap->lock, flags);
 			/* EH might have kicked in while host lock is
 			 * released.
 			 */
 			qc = ata_qc_from_tag(ap, qc->tag);
 			if (qc) {
 				if (likely(!(qc->err_mask & AC_ERR_HSM))) {
 					ata_sff_irq_on(ap);
 					ata_qc_complete(qc);
 				} else
 					ata_port_freeze(ap);
 			}
 			spin_unlock_irqrestore(ap->lock, flags);
 		} else {
 			if (likely(!(qc->err_mask & AC_ERR_HSM)))
 				ata_qc_complete(qc);
 			else
 				ata_port_freeze(ap);
 		}
 	} else {
 		if (in_wq) {
 			spin_lock_irqsave(ap->lock, flags);
 			ata_sff_irq_on(ap);
 			ata_qc_complete(qc);
 			spin_unlock_irqrestore(ap->lock, flags);
 		} else
 			ata_qc_complete(qc);
 	}
 }
 /**
  *	ata_sff_hsm_move - move the HSM to the next state.
  *	@ap: the target ata_port
  *	@qc: qc on going
  *	@status: current device status
  *	@in_wq: 1 if called from workqueue, 0 otherwise
  *
  *	RETURNS:
  *	1 when poll next status needed, 0 otherwise.
  */
 int ata_sff_hsm_move(struct ata_port *ap, struct ata_queued_cmd *qc,
 		     u8 status, int in_wq)
 {
-	struct ata_eh_info *ehi = &ap->link.eh_info;
+	struct ata_link *link = qc->dev->link;
+	struct ata_eh_info *ehi = &link->eh_info;
 	unsigned long flags = 0;
 	int poll_next;
 	WARN_ON_ONCE((qc->flags & ATA_QCFLAG_ACTIVE) == 0);
 	/* Make sure ata_sff_qc_issue() does not throw things
 	 * like DMA polling into the workqueue. Notice that
 	 * in_wq is not equivalent to (qc->tf.flags & ATA_TFLAG_POLLING).
 	 */
 	WARN_ON_ONCE(in_wq != ata_hsm_ok_in_wq(ap, qc));
 fsm_start:
 	DPRINTK("ata%u: protocol %d task_state %d (dev_stat 0x%X)\n",
 		ap->print_id, qc->tf.protocol, ap->hsm_task_state, status);
 	switch (ap->hsm_task_state) {
 	case HSM_ST_FIRST:
 		/* Send first data block or PACKET CDB */
 		/* If polling, we will stay in the work queue after
 		 * sending the data. Otherwise, interrupt handler
 		 * takes over after sending the data.
 		 */
 		poll_next = (qc->tf.flags & ATA_TFLAG_POLLING);
 		/* check device status */
 		if (unlikely((status & ATA_DRQ) == 0)) {
 			/* handle BSY=0, DRQ=0 as error */
 			if (likely(status & (ATA_ERR | ATA_DF)))
 				/* device stops HSM for abort/error */
 				qc->err_mask |= AC_ERR_DEV;
 			else {
 				/* HSM violation. Let EH handle this */
 				ata_ehi_push_desc(ehi,
 					"ST_FIRST: !(DRQ|ERR|DF)");
 				qc->err_mask |= AC_ERR_HSM;
 			}
 			ap->hsm_task_state = HSM_ST_ERR;
 			goto fsm_start;
 		}
 		/* Device should not ask for data transfer (DRQ=1)
 		 * when it finds something wrong.
 		 * We ignore DRQ here and stop the HSM by
 		 * changing hsm_task_state to HSM_ST_ERR and
 		 * let the EH abort the command or reset the device.
 		 */
 		if (unlikely(status & (ATA_ERR | ATA_DF))) {
 			/* Some ATAPI tape drives forget to clear the ERR bit
 			 * when doing the next command (mostly request sense).
 			 * We ignore ERR here to workaround and proceed sending
 			 * the CDB.
 			 */
 			if (!(qc->dev->horkage & ATA_HORKAGE_STUCK_ERR)) {
 				ata_ehi_push_desc(ehi, "ST_FIRST: "
 					"DRQ=1 with device error, "
 					"dev_stat 0x%X", status);
 				qc->err_mask |= AC_ERR_HSM;
 				ap->hsm_task_state = HSM_ST_ERR;
 				goto fsm_start;
 			}
 		}
 		/* Send the CDB (atapi) or the first data block (ata pio out).
 		 * During the state transition, interrupt handler shouldn't
 		 * be invoked before the data transfer is complete and
 		 * hsm_task_state is changed. Hence, the following locking.
 		 */
 		if (in_wq)
 			spin_lock_irqsave(ap->lock, flags);
 		if (qc->tf.protocol == ATA_PROT_PIO) {
 			/* PIO data out protocol.
 			 * send first data block.
 			 */
 			/* ata_pio_sectors() might change the state
 			 * to HSM_ST_LAST. so, the state is changed here
 			 * before ata_pio_sectors().
 			 */
 			ap->hsm_task_state = HSM_ST;
 			ata_pio_sectors(qc);
 		} else
 			/* send CDB */
 			atapi_send_cdb(ap, qc);
 		if (in_wq)
 			spin_unlock_irqrestore(ap->lock, flags);
 		/* if polling, ata_sff_pio_task() handles the rest.
 		 * otherwise, interrupt handler takes over from here.
 		 */
 		break;
 	case HSM_ST:
 		/* complete command or read/write the data register */
 		if (qc->tf.protocol == ATAPI_PROT_PIO) {
 			/* ATAPI PIO protocol */
 			if ((status & ATA_DRQ) == 0) {
 				/* No more data to transfer or device error.
 				 * Device error will be tagged in HSM_ST_LAST.
 				 */
 				ap->hsm_task_state = HSM_ST_LAST;
 				goto fsm_start;
 			}
 			/* Device should not ask for data transfer (DRQ=1)
 			 * when it finds something wrong.
 			 * We ignore DRQ here and stop the HSM by
 			 * changing hsm_task_state to HSM_ST_ERR and
 			 * let the EH abort the command or reset the device.
 			 */
 			if (unlikely(status & (ATA_ERR | ATA_DF))) {
 				ata_ehi_push_desc(ehi, "ST-ATAPI: "
 					"DRQ=1 with device error, "
 					"dev_stat 0x%X", status);
 				qc->err_mask |= AC_ERR_HSM;
 				ap->hsm_task_state = HSM_ST_ERR;
 				goto fsm_start;
 			}
 			atapi_pio_bytes(qc);
 			if (unlikely(ap->hsm_task_state == HSM_ST_ERR))
 				/* bad ireason reported by device */
 				goto fsm_start;
 		} else {
 			/* ATA PIO protocol */
 			if (unlikely((status & ATA_DRQ) == 0)) {
 				/* handle BSY=0, DRQ=0 as error */
 				if (likely(status & (ATA_ERR | ATA_DF))) {
 					/* device stops HSM for abort/error */
 					qc->err_mask |= AC_ERR_DEV;
 					/* If diagnostic failed and this is
 					 * IDENTIFY, it's likely a phantom
 					 * device.  Mark hint.
 					 */
 					if (qc->dev->horkage &
 					    ATA_HORKAGE_DIAGNOSTIC)
 						qc->err_mask |=
 							AC_ERR_NODEV_HINT;
 				} else {
 					/* HSM violation. Let EH handle this.
 					 * Phantom devices also trigger this
 					 * condition.  Mark hint.
 					 */
 					ata_ehi_push_desc(ehi, "ST-ATA: "
 						"DRQ=0 without device error, "
 						"dev_stat 0x%X", status);
 					qc->err_mask |= AC_ERR_HSM |
 							AC_ERR_NODEV_HINT;
 				}
 				ap->hsm_task_state = HSM_ST_ERR;
 				goto fsm_start;
 			}
 			/* For PIO reads, some devices may ask for
 			 * data transfer (DRQ=1) alone with ERR=1.
 			 * We respect DRQ here and transfer one
 			 * block of junk data before changing the
 			 * hsm_task_state to HSM_ST_ERR.
 			 *
 			 * For PIO writes, ERR=1 DRQ=1 doesn't make
 			 * sense since the data block has been
 			 * transferred to the device.
 			 */
 			if (unlikely(status & (ATA_ERR | ATA_DF))) {
 				/* data might be corrputed */
 				qc->err_mask |= AC_ERR_DEV;
 				if (!(qc->tf.flags & ATA_TFLAG_WRITE)) {
 					ata_pio_sectors(qc);
 					status = ata_wait_idle(ap);
 				}
 				if (status & (ATA_BUSY | ATA_DRQ)) {
 					ata_ehi_push_desc(ehi, "ST-ATA: "
 						"BUSY|DRQ persists on ERR|DF, "
 						"dev_stat 0x%X", status);
 					qc->err_mask |= AC_ERR_HSM;
 				}
 				/* There are oddball controllers with
 				 * status register stuck at 0x7f and
 				 * lbal/m/h at zero which makes it
 				 * pass all other presence detection
 				 * mechanisms we have.  Set NODEV_HINT
 				 * for it.  Kernel bz#7241.
 				 */
 				if (status == 0x7f)
 					qc->err_mask |= AC_ERR_NODEV_HINT;
 				/* ata_pio_sectors() might change the
 				 * state to HSM_ST_LAST. so, the state
 				 * is changed after ata_pio_sectors().
 				 */
 				ap->hsm_task_state = HSM_ST_ERR;
 				goto fsm_start;
 			}
 			ata_pio_sectors(qc);
 			if (ap->hsm_task_state == HSM_ST_LAST &&
 			    (!(qc->tf.flags & ATA_TFLAG_WRITE))) {
 				/* all data read */
 				status = ata_wait_idle(ap);
 				goto fsm_start;
 			}
 		}
 		poll_next = 1;
 		break;
 	case HSM_ST_LAST:
 		if (unlikely(!ata_ok(status))) {
 			qc->err_mask |= __ac_err_mask(status);
 			ap->hsm_task_state = HSM_ST_ERR;
 			goto fsm_start;
 		}
 		/* no more data to transfer */
 		DPRINTK("ata%u: dev %u command complete, drv_stat 0x%x\n",
 			ap->print_id, qc->dev->devno, status);
 		WARN_ON_ONCE(qc->err_mask & (AC_ERR_DEV | AC_ERR_HSM));
 		ap->hsm_task_state = HSM_ST_IDLE;
 		/* complete taskfile transaction */
 		ata_hsm_qc_complete(qc, in_wq);
 		poll_next = 0;
 		break;
 	case HSM_ST_ERR:
 		ap->hsm_task_state = HSM_ST_IDLE;
 		/* complete taskfile transaction */
 		ata_hsm_qc_complete(qc, in_wq);
 		poll_next = 0;
 		break;
 	default:
 		poll_next = 0;
 		BUG();
 	}
 	return poll_next;
 }
 EXPORT_SYMBOL_GPL(ata_sff_hsm_move);
-void ata_sff_queue_pio_task(struct ata_port *ap, unsigned long delay)
+void ata_sff_queue_pio_task(struct ata_link *link, unsigned long delay)
 {
+	struct ata_port *ap = link->ap;
+	WARN_ON((ap->sff_pio_task_link != NULL) &&
+		(ap->sff_pio_task_link != link));
+	ap->sff_pio_task_link = link;
 	/* may fail if ata_sff_flush_pio_task() in progress */
 	queue_delayed_work(ata_sff_wq, &ap->sff_pio_task,
 			   msecs_to_jiffies(delay));
 }
 EXPORT_SYMBOL_GPL(ata_sff_queue_pio_task);
 void ata_sff_flush_pio_task(struct ata_port *ap)
 {
 	DPRINTK("ENTER\n");
 	cancel_rearming_delayed_work(&ap->sff_pio_task);
 	ap->hsm_task_state = HSM_ST_IDLE;
 	if (ata_msg_ctl(ap))
 		ata_port_printk(ap, KERN_DEBUG, "%s: EXIT\n", __func__);
 }
 static void ata_sff_pio_task(struct work_struct *work)
 {
 	struct ata_port *ap =
 		container_of(work, struct ata_port, sff_pio_task.work);
+	struct ata_link *link = ap->sff_pio_task_link;
 	struct ata_queued_cmd *qc;
 	u8 status;
 	int poll_next;
+	BUG_ON(ap->sff_pio_task_link == NULL);
 	/* qc can be NULL if timeout occurred */
-	qc = ata_qc_from_tag(ap, ap->link.active_tag);
+	qc = ata_qc_from_tag(ap, link->active_tag);
-	if (!qc)
+	if (!qc) {
+		ap->sff_pio_task_link = NULL;
 		return;
+	}
 fsm_start:
 	WARN_ON_ONCE(ap->hsm_task_state == HSM_ST_IDLE);
 	/*
 	 * This is purely heuristic.  This is a fast path.
 	 * Sometimes when we enter, BSY will be cleared in
 	 * a chk-status or two.  If not, the drive is probably seeking
 	 * or something.  Snooze for a couple msecs, then
 	 * chk-status again.  If still busy, queue delayed work.
 	 */
 	status = ata_sff_busy_wait(ap, ATA_BUSY, 5);
 	if (status & ATA_BUSY) {
 		msleep(2);
 		status = ata_sff_busy_wait(ap, ATA_BUSY, 10);
 		if (status & ATA_BUSY) {
-			ata_sff_queue_pio_task(ap, ATA_SHORT_PAUSE);
+			ata_sff_queue_pio_task(link, ATA_SHORT_PAUSE);
 			return;
 		}
 	}
+	/*
+	 * hsm_move() may trigger another command to be processed.
+	 * clean the link beforehand.
+	 */
+	ap->sff_pio_task_link = NULL;
 	/* move the HSM */
 	poll_next = ata_sff_hsm_move(ap, qc, status, 1);
 	/* another command or interrupt handler
 	 * may be running at this point.
 	 */
 	if (poll_next)
 		goto fsm_start;
 }
 /**
  *	ata_sff_qc_issue - issue taskfile to a SFF controller
  *	@qc: command to issue to device
  *
  *	This function issues a PIO or NODATA command to a SFF
  *	controller.
  *
  *	LOCKING:
  *	spin_lock_irqsave(host lock)
  *
  *	RETURNS:
  *	Zero on success, AC_ERR_* mask on failure
  */
 unsigned int ata_sff_qc_issue(struct ata_queued_cmd *qc)
 {
 	struct ata_port *ap = qc->ap;
+	struct ata_link *link = qc->dev->link;
 	/* Use polling pio if the LLD doesn't handle
 	 * interrupt driven pio and atapi CDB interrupt.
 	 */
 	if (ap->flags & ATA_FLAG_PIO_POLLING)
 		qc->tf.flags |= ATA_TFLAG_POLLING;
 	/* select the device */
 	ata_dev_select(ap, qc->dev->devno, 1, 0);
 	/* start the command */
 	switch (qc->tf.protocol) {
 	case ATA_PROT_NODATA:
 		if (qc->tf.flags & ATA_TFLAG_POLLING)
 			ata_qc_set_polling(qc);
 		ata_tf_to_host(ap, &qc->tf);
 		ap->hsm_task_state = HSM_ST_LAST;
 		if (qc->tf.flags & ATA_TFLAG_POLLING)
-			ata_sff_queue_pio_task(ap, 0);
+			ata_sff_queue_pio_task(link, 0);
 		break;
 	case ATA_PROT_PIO:
 		if (qc->tf.flags & ATA_TFLAG_POLLING)
 			ata_qc_set_polling(qc);
 		ata_tf_to_host(ap, &qc->tf);
 		if (qc->tf.flags & ATA_TFLAG_WRITE) {
 			/* PIO data out protocol */
 			ap->hsm_task_state = HSM_ST_FIRST;
-			ata_sff_queue_pio_task(ap, 0);
+			ata_sff_queue_pio_task(link, 0);
 			/* always send first data block using the
 			 * ata_sff_pio_task() codepath.
 			 */
 		} else {
 			/* PIO data in protocol */
 			ap->hsm_task_state = HSM_ST;
 			if (qc->tf.flags & ATA_TFLAG_POLLING)
-				ata_sff_queue_pio_task(ap, 0);
+				ata_sff_queue_pio_task(link, 0);
 			/* if polling, ata_sff_pio_task() handles the
 			 * rest.  otherwise, interrupt handler takes
 			 * over from here.
 			 */
 		}
 		break;
 	case ATAPI_PROT_PIO:
 	case ATAPI_PROT_NODATA:
 		if (qc->tf.flags & ATA_TFLAG_POLLING)
 			ata_qc_set_polling(qc);
 		ata_tf_to_host(ap, &qc->tf);
 		ap->hsm_task_state = HSM_ST_FIRST;
 		/* send cdb by polling if no cdb interrupt */
 		if ((!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) ||
 		    (qc->tf.flags & ATA_TFLAG_POLLING))
-			ata_sff_queue_pio_task(ap, 0);
+			ata_sff_queue_pio_task(link, 0);
 		break;
 	default:
 		WARN_ON_ONCE(1);
 		return AC_ERR_SYSTEM;
 	}
 	return 0;
 }
 EXPORT_SYMBOL_GPL(ata_sff_qc_issue);
 /**
  *	ata_sff_qc_fill_rtf - fill result TF using ->sff_tf_read
  *	@qc: qc to fill result TF for
  *
  *	@qc is finished and result TF needs to be filled.  Fill it
  *	using ->sff_tf_read.
  *
  *	LOCKING:
  *	spin_lock_irqsave(host lock)
  *
  *	RETURNS:
  *	true indicating that result TF is successfully filled.
  */
 bool ata_sff_qc_fill_rtf(struct ata_queued_cmd *qc)
 {
 	qc->ap->ops->sff_tf_read(qc->ap, &qc->result_tf);
 	return true;
 }
 EXPORT_SYMBOL_GPL(ata_sff_qc_fill_rtf);
 static unsigned int ata_sff_idle_irq(struct ata_port *ap)
 {
 	ap->stats.idle_irq++;
 #ifdef ATA_IRQ_TRAP
 	if ((ap->stats.idle_irq % 1000) == 0) {
 		ap->ops->sff_check_status(ap);
 		if (ap->ops->sff_irq_clear)
 			ap->ops->sff_irq_clear(ap);
 		ata_port_printk(ap, KERN_WARNING, "irq trap\n");
 		return 1;
 	}
 #endif
 	return 0;	/* irq not handled */
 }
 static unsigned int __ata_sff_port_intr(struct ata_port *ap,
 					struct ata_queued_cmd *qc,
 					bool hsmv_on_idle)
 {
 	u8 status;
 	VPRINTK("ata%u: protocol %d task_state %d\n",
 		ap->print_id, qc->tf.protocol, ap->hsm_task_state);
 	/* Check whether we are expecting interrupt in this state */
 	switch (ap->hsm_task_state) {
 	case HSM_ST_FIRST:
 		/* Some pre-ATAPI-4 devices assert INTRQ
 		 * at this state when ready to receive CDB.
 		 */
 		/* Check the ATA_DFLAG_CDB_INTR flag is enough here.
 		 * The flag was turned on only for atapi devices.  No
 		 * need to check ata_is_atapi(qc->tf.protocol) again.
 		 */
 		if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
 			return ata_sff_idle_irq(ap);
 		break;
 	case HSM_ST:
 	case HSM_ST_LAST:
 		break;
 	default:
 		return ata_sff_idle_irq(ap);
 	}
 	/* check main status, clearing INTRQ if needed */
 	status = ata_sff_irq_status(ap);
 	if (status & ATA_BUSY) {
 		if (hsmv_on_idle) {
 			/* BMDMA engine is already stopped, we're screwed */
 			qc->err_mask |= AC_ERR_HSM;
 			ap->hsm_task_state = HSM_ST_ERR;
 		} else
 			return ata_sff_idle_irq(ap);
 	}
 	/* clear irq events */
 	if (ap->ops->sff_irq_clear)
 		ap->ops->sff_irq_clear(ap);
 	ata_sff_hsm_move(ap, qc, status, 0);
 	return 1;	/* irq handled */
 }
 /**
  *	ata_sff_port_intr - Handle SFF port interrupt
  *	@ap: Port on which interrupt arrived (possibly...)
  *	@qc: Taskfile currently active in engine
  *
  *	Handle port interrupt for given queued command.
  *
  *	LOCKING:
  *	spin_lock_irqsave(host lock)
  *
  *	RETURNS:
  *	One if interrupt was handled, zero if not (shared irq).
  */
 unsigned int ata_sff_port_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
 {
 	return __ata_sff_port_intr(ap, qc, false);
 }
 EXPORT_SYMBOL_GPL(ata_sff_port_intr);
 static inline irqreturn_t __ata_sff_interrupt(int irq, void *dev_instance,
 	unsigned int (*port_intr)(struct ata_port *, struct ata_queued_cmd *))
 {
 	struct ata_host *host = dev_instance;
 	bool retried = false;
 	unsigned int i;
 	unsigned int handled, idle, polling;
 	unsigned long flags;
 	/* TODO: make _irqsave conditional on x86 PCI IDE legacy mode */
 	spin_lock_irqsave(&host->lock, flags);
 retry:
 	handled = idle = polling = 0;
 	for (i = 0; i < host->n_ports; i++) {
 		struct ata_port *ap = host->ports[i];
 		struct ata_queued_cmd *qc;
 		qc = ata_qc_from_tag(ap, ap->link.active_tag);
 		if (qc) {
 			if (!(qc->tf.flags & ATA_TFLAG_POLLING))
 				handled |= port_intr(ap, qc);
 			else
 				polling |= 1 << i;
 		} else
 			idle |= 1 << i;
 	}
 	/*
 	 * If no port was expecting IRQ but the controller is actually
 	 * asserting IRQ line, nobody cared will ensue.  Check IRQ
 	 * pending status if available and clear spurious IRQ.
 	 */
 	if (!handled && !retried) {
 		bool retry = false;
 		for (i = 0; i < host->n_ports; i++) {
 			struct ata_port *ap = host->ports[i];
 			if (polling & (1 << i))
 				continue;
 			if (!ap->ops->sff_irq_check ||
 			    !ap->ops->sff_irq_check(ap))
 				continue;
 			if (idle & (1 << i)) {
 				ap->ops->sff_check_status(ap);
 				if (ap->ops->sff_irq_clear)
 					ap->ops->sff_irq_clear(ap);
 			} else {
 				/* clear INTRQ and check if BUSY cleared */
 				if (!(ap->ops->sff_check_status(ap) & ATA_BUSY))
 					retry |= true;
 				/*
 				 * With command in flight, we can't do
 				 * sff_irq_clear() w/o racing with completion.
 				 */
 			}
 		}
 		if (retry) {
 			retried = true;
 			goto retry;
 		}
 	}
 	spin_unlock_irqrestore(&host->lock, flags);
 	return IRQ_RETVAL(handled);
 }
 /**
  *	ata_sff_interrupt - Default SFF ATA host interrupt handler
  *	@irq: irq line (unused)
  *	@dev_instance: pointer to our ata_host information structure
  *
  *	Default interrupt handler for PCI IDE devices.  Calls
  *	ata_sff_port_intr() for each port that is not disabled.
  *
  *	LOCKING:
  *	Obtains host lock during operation.
  *
  *	RETURNS:
  *	IRQ_NONE or IRQ_HANDLED.
  */
 irqreturn_t ata_sff_interrupt(int irq, void *dev_instance)
 {
 	return __ata_sff_interrupt(irq, dev_instance, ata_sff_port_intr);
 }
 EXPORT_SYMBOL_GPL(ata_sff_interrupt);
 /**
  *	ata_sff_lost_interrupt	-	Check for an apparent lost interrupt
  *	@ap: port that appears to have timed out
  *
  *	Called from the libata error handlers when the core code suspects
  *	an interrupt has been lost. If it has complete anything we can and
  *	then return. Interface must support altstatus for this faster
  *	recovery to occur.
  *
  *	Locking:
  *	Caller holds host lock
  */
 void ata_sff_lost_interrupt(struct ata_port *ap)
 {
 	u8 status;
 	struct ata_queued_cmd *qc;
 	/* Only one outstanding command per SFF channel */
 	qc = ata_qc_from_tag(ap, ap->link.active_tag);
 	/* We cannot lose an interrupt on a non-existent or polled command */
 	if (!qc || qc->tf.flags & ATA_TFLAG_POLLING)
 		return;
 	/* See if the controller thinks it is still busy - if so the command
 	   isn't a lost IRQ but is still in progress */
 	status = ata_sff_altstatus(ap);
 	if (status & ATA_BUSY)
 		return;
 	/* There was a command running, we are no longer busy and we have
 	   no interrupt. */
 	ata_port_printk(ap, KERN_WARNING, "lost interrupt (Status 0x%x)\n",
 								status);
 	/* Run the host interrupt logic as if the interrupt had not been
 	   lost */
 	ata_sff_port_intr(ap, qc);
 }
 EXPORT_SYMBOL_GPL(ata_sff_lost_interrupt);
 /**
  *	ata_sff_freeze - Freeze SFF controller port
  *	@ap: port to freeze
  *
  *	Freeze SFF controller port.
  *
  *	LOCKING:
  *	Inherited from caller.
  */
 void ata_sff_freeze(struct ata_port *ap)
 {
 	ap->ctl |= ATA_NIEN;
 	ap->last_ctl = ap->ctl;
 	if (ap->ops->sff_set_devctl || ap->ioaddr.ctl_addr)
 		ata_sff_set_devctl(ap, ap->ctl);
 	/* Under certain circumstances, some controllers raise IRQ on
 	 * ATA_NIEN manipulation.  Also, many controllers fail to mask
 	 * previously pending IRQ on ATA_NIEN assertion.  Clear it.
 	 */
 	ap->ops->sff_check_status(ap);
 	if (ap->ops->sff_irq_clear)
 		ap->ops->sff_irq_clear(ap);
 }
 EXPORT_SYMBOL_GPL(ata_sff_freeze);
 /**
  *	ata_sff_thaw - Thaw SFF controller port
  *	@ap: port to thaw
  *
  *	Thaw SFF controller port.
  *
  *	LOCKING:
  *	Inherited from caller.
  */
 void ata_sff_thaw(struct ata_port *ap)
 {
 	/* clear & re-enable interrupts */
 	ap->ops->sff_check_status(ap);
 	if (ap->ops->sff_irq_clear)
 		ap->ops->sff_irq_clear(ap);
 	ata_sff_irq_on(ap);
 }
 EXPORT_SYMBOL_GPL(ata_sff_thaw);
 /**
  *	ata_sff_prereset - prepare SFF link for reset
  *	@link: SFF link to be reset
  *	@deadline: deadline jiffies for the operation
  *
  *	SFF link @link is about to be reset.  Initialize it.  It first
  *	calls ata_std_prereset() and wait for !BSY if the port is
  *	being softreset.
  *
  *	LOCKING:
  *	Kernel thread context (may sleep)
  *
  *	RETURNS:
  *	0 on success, -errno otherwise.
  */
 int ata_sff_prereset(struct ata_link *link, unsigned long deadline)
 {
 	struct ata_eh_context *ehc = &link->eh_context;
 	int rc;
 	rc = ata_std_prereset(link, deadline);
 	if (rc)
 		return rc;
 	/* if we're about to do hardreset, nothing more to do */
 	if (ehc->i.action & ATA_EH_HARDRESET)
 		return 0;
 	/* wait for !BSY if we don't know that no device is attached */
 	if (!ata_link_offline(link)) {
 		rc = ata_sff_wait_ready(link, deadline);
 		if (rc && rc != -ENODEV) {
 			ata_link_printk(link, KERN_WARNING, "device not ready "
 					"(errno=%d), forcing hardreset\n", rc);
 			ehc->i.action |= ATA_EH_HARDRESET;
 		}
 	}
 	return 0;
 }
 EXPORT_SYMBOL_GPL(ata_sff_prereset);
 /**
  *	ata_devchk - PATA device presence detection
  *	@ap: ATA channel to examine
  *	@device: Device to examine (starting at zero)
  *
  *	This technique was originally described in
  *	Hale Landis's ATADRVR (www.ata-atapi.com), and
  *	later found its way into the ATA/ATAPI spec.
  *
  *	Write a pattern to the ATA shadow registers,
  *	and if a device is present, it will respond by
  *	correctly storing and echoing back the
  *	ATA shadow register contents.
  *
  *	LOCKING:
  *	caller.
  */
 static unsigned int ata_devchk(struct ata_port *ap, unsigned int device)
 {
 	struct ata_ioports *ioaddr = &ap->ioaddr;
 	u8 nsect, lbal;
 	ap->ops->sff_dev_select(ap, device);
 	iowrite8(0x55, ioaddr->nsect_addr);
 	iowrite8(0xaa, ioaddr->lbal_addr);
 	iowrite8(0xaa, ioaddr->nsect_addr);
 	iowrite8(0x55, ioaddr->lbal_addr);
 	iowrite8(0x55, ioaddr->nsect_addr);
 	iowrite8(0xaa, ioaddr->lbal_addr);
 	nsect = ioread8(ioaddr->nsect_addr);
 	lbal = ioread8(ioaddr->lbal_addr);
 	if ((nsect == 0x55) && (lbal == 0xaa))
 		return 1;	/* we found a device */
 	return 0;		/* nothing found */
 }
 /**
  *	ata_sff_dev_classify - Parse returned ATA device signature
  *	@dev: ATA device to classify (starting at zero)
  *	@present: device seems present
  *	@r_err: Value of error register on completion
  *
  *	After an event -- SRST, E.D.D., or SATA COMRESET -- occurs,
  *	an ATA/ATAPI-defined set of values is placed in the ATA
  *	shadow registers, indicating the results of device detection
  *	and diagnostics.
  *
  *	Select the ATA device, and read the values from the ATA shadow
  *	registers.  Then parse according to the Error register value,
  *	and the spec-defined values examined by ata_dev_classify().
  *
  *	LOCKING:
  *	caller.
  *
  *	RETURNS:
  *	Device type - %ATA_DEV_ATA, %ATA_DEV_ATAPI or %ATA_DEV_NONE.
  */
 unsigned int ata_sff_dev_classify(struct ata_device *dev, int present,
 				  u8 *r_err)
 {
 	struct ata_port *ap = dev->link->ap;
 	struct ata_taskfile tf;
 	unsigned int class;
 	u8 err;
 	ap->ops->sff_dev_select(ap, dev->devno);
 	memset(&tf, 0, sizeof(tf));
 	ap->ops->sff_tf_read(ap, &tf);
 	err = tf.feature;
 	if (r_err)
 		*r_err = err;
 	/* see if device passed diags: continue and warn later */
 	if (err == 0)
 		/* diagnostic fail : do nothing _YET_ */
 		dev->horkage |= ATA_HORKAGE_DIAGNOSTIC;
 	else if (err == 1)
 		/* do nothing */ ;
 	else if ((dev->devno == 0) && (err == 0x81))
 		/* do nothing */ ;
 	else
 		return ATA_DEV_NONE;
 	/* determine if device is ATA or ATAPI */
 	class = ata_dev_classify(&tf);
 	if (class == ATA_DEV_UNKNOWN) {
 		/* If the device failed diagnostic, it's likely to
 		 * have reported incorrect device signature too.
 		 * Assume ATA device if the device seems present but
 		 * device signature is invalid with diagnostic
 		 * failure.
 		 */
 		if (present && (dev->horkage & ATA_HORKAGE_DIAGNOSTIC))
 			class = ATA_DEV_ATA;
 		else
 			class = ATA_DEV_NONE;
 	} else if ((class == ATA_DEV_ATA) &&
 		   (ap->ops->sff_check_status(ap) == 0))
 		class = ATA_DEV_NONE;
 	return class;
 }
 EXPORT_SYMBOL_GPL(ata_sff_dev_classify);
 /**
  *	ata_sff_wait_after_reset - wait for devices to become ready after reset
  *	@link: SFF link which is just reset
  *	@devmask: mask of present devices
  *	@deadline: deadline jiffies for the operation
  *
  *	Wait devices attached to SFF @link to become ready after
  *	reset.  It contains preceding 150ms wait to avoid accessing TF
  *	status register too early.
  *
  *	LOCKING:
  *	Kernel thread context (may sleep).
  *
  *	RETURNS:
  *	0 on success, -ENODEV if some or all of devices in @devmask
  *	don't seem to exist.  -errno on other errors.
  */
 int ata_sff_wait_after_reset(struct ata_link *link, unsigned int devmask,
 			     unsigned long deadline)
 {
 	struct ata_port *ap = link->ap;
 	struct ata_ioports *ioaddr = &ap->ioaddr;
 	unsigned int dev0 = devmask & (1 << 0);
 	unsigned int dev1 = devmask & (1 << 1);
 	int rc, ret = 0;
 	msleep(ATA_WAIT_AFTER_RESET);
 	/* always check readiness of the master device */
 	rc = ata_sff_wait_ready(link, deadline);
 	/* -ENODEV means the odd clown forgot the D7 pulldown resistor
 	 * and TF status is 0xff, bail out on it too.
 	 */
 	if (rc)
 		return rc;
 	/* if device 1 was found in ata_devchk, wait for register
 	 * access briefly, then wait for BSY to clear.
 	 */
 	if (dev1) {
 		int i;
 		ap->ops->sff_dev_select(ap, 1);
 		/* Wait for register access.  Some ATAPI devices fail
 		 * to set nsect/lbal after reset, so don't waste too
 		 * much time on it.  We're gonna wait for !BSY anyway.
 		 */
 		for (i = 0; i < 2; i++) {
 			u8 nsect, lbal;
 			nsect = ioread8(ioaddr->nsect_addr);
 			lbal = ioread8(ioaddr->lbal_addr);
 			if ((nsect == 1) && (lbal == 1))
 				break;
 			msleep(50);	/* give drive a breather */
 		}
 		rc = ata_sff_wait_ready(link, deadline);
 		if (rc) {
 			if (rc != -ENODEV)
 				return rc;
 			ret = rc;
 		}
 	}
 	/* is all this really necessary? */
 	ap->ops->sff_dev_select(ap, 0);
 	if (dev1)
 		ap->ops->sff_dev_select(ap, 1);
 	if (dev0)
 		ap->ops->sff_dev_select(ap, 0);
 	return ret;
 }
 EXPORT_SYMBOL_GPL(ata_sff_wait_after_reset);
 static int ata_bus_softreset(struct ata_port *ap, unsigned int devmask,
 			     unsigned long deadline)
 {
 	struct ata_ioports *ioaddr = &ap->ioaddr;
 	DPRINTK("ata%u: bus reset via SRST\n", ap->print_id);
 	/* software reset.  causes dev0 to be selected */
 	iowrite8(ap->ctl, ioaddr->ctl_addr);
 	udelay(20);	/* FIXME: flush */
 	iowrite8(ap->ctl | ATA_SRST, ioaddr->ctl_addr);
 	udelay(20);	/* FIXME: flush */
 	iowrite8(ap->ctl, ioaddr->ctl_addr);
 	ap->last_ctl = ap->ctl;
 	/* wait the port to become ready */
 	return ata_sff_wait_after_reset(&ap->link, devmask, deadline);
 }
 /**
  *	ata_sff_softreset - reset host port via ATA SRST
  *	@link: ATA link to reset
  *	@classes: resulting classes of attached devices
  *	@deadline: deadline jiffies for the operation
  *
  *	Reset host port using ATA SRST.
  *
  *	LOCKING:
  *	Kernel thread context (may sleep)
  *
  *	RETURNS:
  *	0 on success, -errno otherwise.
  */
 int ata_sff_softreset(struct ata_link *link, unsigned int *classes,
 		      unsigned long deadline)
 {
 	struct ata_port *ap = link->ap;
 	unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
 	unsigned int devmask = 0;
 	int rc;
 	u8 err;
 	DPRINTK("ENTER\n");
 	/* determine if device 0/1 are present */
 	if (ata_devchk(ap, 0))
 		devmask |= (1 << 0);
 	if (slave_possible && ata_devchk(ap, 1))
 		devmask |= (1 << 1);
 	/* select device 0 again */
 	ap->ops->sff_dev_select(ap, 0);
 	/* issue bus reset */
 	DPRINTK("about to softreset, devmask=%x\n", devmask);
 	rc = ata_bus_softreset(ap, devmask, deadline);
 	/* if link is occupied, -ENODEV too is an error */
 	if (rc && (rc != -ENODEV || sata_scr_valid(link))) {
 		ata_link_printk(link, KERN_ERR, "SRST failed (errno=%d)\n", rc);
 		return rc;
 	}
 	/* determine by signature whether we have ATA or ATAPI devices */
 	classes[0] = ata_sff_dev_classify(&link->device[0],
 					  devmask & (1 << 0), &err);
 	if (slave_possible && err != 0x81)
 		classes[1] = ata_sff_dev_classify(&link->device[1],
 						  devmask & (1 << 1), &err);
 	DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]);
 	return 0;
 }
 EXPORT_SYMBOL_GPL(ata_sff_softreset);
 /**
  *	sata_sff_hardreset - reset host port via SATA phy reset
  *	@link: link to reset
  *	@class: resulting class of attached device
  *	@deadline: deadline jiffies for the operation
  *
  *	SATA phy-reset host port using DET bits of SControl register,
  *	wait for !BSY and classify the attached device.
  *
  *	LOCKING:
  *	Kernel thread context (may sleep)
  *
  *	RETURNS:
  *	0 on success, -errno otherwise.
  */
 int sata_sff_hardreset(struct ata_link *link, unsigned int *class,
 		       unsigned long deadline)
 {
 	struct ata_eh_context *ehc = &link->eh_context;
 	const unsigned long *timing = sata_ehc_deb_timing(ehc);
 	bool online;
 	int rc;
 	rc = sata_link_hardreset(link, timing, deadline, &online,
 				 ata_sff_check_ready);
 	if (online)
 		*class = ata_sff_dev_classify(link->device, 1, NULL);
 	DPRINTK("EXIT, class=%u\n", *class);
 	return rc;
 }
 EXPORT_SYMBOL_GPL(sata_sff_hardreset);
 /**
  *	ata_sff_postreset - SFF postreset callback
  *	@link: the target SFF ata_link
  *	@classes: classes of attached devices
  *
  *	This function is invoked after a successful reset.  It first
  *	calls ata_std_postreset() and performs SFF specific postreset
  *	processing.
  *
  *	LOCKING:
  *	Kernel thread context (may sleep)
  */
 void ata_sff_postreset(struct ata_link *link, unsigned int *classes)
 {
 	struct ata_port *ap = link->ap;
 	ata_std_postreset(link, classes);
 	/* is double-select really necessary? */
 	if (classes[0] != ATA_DEV_NONE)
 		ap->ops->sff_dev_select(ap, 1);
 	if (classes[1] != ATA_DEV_NONE)
 		ap->ops->sff_dev_select(ap, 0);
 	/* bail out if no device is present */
 	if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) {
 		DPRINTK("EXIT, no device\n");
 		return;
 	}
 	/* set up device control */
 	if (ap->ops->sff_set_devctl || ap->ioaddr.ctl_addr) {
 		ata_sff_set_devctl(ap, ap->ctl);
 		ap->last_ctl = ap->ctl;
 	}
 }
 EXPORT_SYMBOL_GPL(ata_sff_postreset);
 /**
  *	ata_sff_drain_fifo - Stock FIFO drain logic for SFF controllers
  *	@qc: command
  *
  *	Drain the FIFO and device of any stuck data following a command
  *	failing to complete. In some cases this is necessary before a
  *	reset will recover the device.
  *
  */
 void ata_sff_drain_fifo(struct ata_queued_cmd *qc)
 {
 	int count;
 	struct ata_port *ap;
 	/* We only need to flush incoming data when a command was running */
 	if (qc == NULL || qc->dma_dir == DMA_TO_DEVICE)
 		return;
 	ap = qc->ap;
 	/* Drain up to 64K of data before we give up this recovery method */
 	for (count = 0; (ap->ops->sff_check_status(ap) & ATA_DRQ)
 						&& count < 65536; count += 2)
 		ioread16(ap->ioaddr.data_addr);
 	/* Can become DEBUG later */
 	if (count)
 		ata_port_printk(ap, KERN_DEBUG,
 			"drained %d bytes to clear DRQ.\n", count);
 }
 EXPORT_SYMBOL_GPL(ata_sff_drain_fifo);
 /**
  *	ata_sff_error_handler - Stock error handler for SFF controller
  *	@ap: port to handle error for
  *
  *	Stock error handler for SFF controller.  It can handle both
  *	PATA and SATA controllers.  Many controllers should be able to
  *	use this EH as-is or with some added handling before and
  *	after.
  *
  *	LOCKING:
  *	Kernel thread context (may sleep)
  */
 void ata_sff_error_handler(struct ata_port *ap)
 {
 	ata_reset_fn_t softreset = ap->ops->softreset;
 	ata_reset_fn_t hardreset = ap->ops->hardreset;
 	struct ata_queued_cmd *qc;
 	unsigned long flags;
 	qc = __ata_qc_from_tag(ap, ap->link.active_tag);
 	if (qc && !(qc->flags & ATA_QCFLAG_FAILED))
 		qc = NULL;
 	spin_lock_irqsave(ap->lock, flags);
 	/*
 	 * We *MUST* do FIFO draining before we issue a reset as
 	 * several devices helpfully clear their internal state and
 	 * will lock solid if we touch the data port post reset. Pass
 	 * qc in case anyone wants to do different PIO/DMA recovery or
 	 * has per command fixups
 	 */
 	if (ap->ops->sff_drain_fifo)
 		ap->ops->sff_drain_fifo(qc);
 	spin_unlock_irqrestore(ap->lock, flags);
 	/* ignore ata_sff_softreset if ctl isn't accessible */
 	if (softreset == ata_sff_softreset && !ap->ioaddr.ctl_addr)
 		softreset = NULL;
 	/* ignore built-in hardresets if SCR access is not available */
 	if ((hardreset == sata_std_hardreset ||
 	     hardreset == sata_sff_hardreset) && !sata_scr_valid(&ap->link))
 		hardreset = NULL;
 	ata_do_eh(ap, ap->ops->prereset, softreset, hardreset,
 		  ap->ops->postreset);
 }
 EXPORT_SYMBOL_GPL(ata_sff_error_handler);
 /**
  *	ata_sff_std_ports - initialize ioaddr with standard port offsets.
  *	@ioaddr: IO address structure to be initialized
  *
  *	Utility function which initializes data_addr, error_addr,
  *	feature_addr, nsect_addr, lbal_addr, lbam_addr, lbah_addr,
  *	device_addr, status_addr, and command_addr to standard offsets
  *	relative to cmd_addr.
  *
  *	Does not set ctl_addr, altstatus_addr, bmdma_addr, or scr_addr.
  */
 void ata_sff_std_ports(struct ata_ioports *ioaddr)
 {
 	ioaddr->data_addr = ioaddr->cmd_addr + ATA_REG_DATA;
 	ioaddr->error_addr = ioaddr->cmd_addr + ATA_REG_ERR;
 	ioaddr->feature_addr = ioaddr->cmd_addr + ATA_REG_FEATURE;
 	ioaddr->nsect_addr = ioaddr->cmd_addr + ATA_REG_NSECT;
 	ioaddr->lbal_addr = ioaddr->cmd_addr + ATA_REG_LBAL;
 	ioaddr->lbam_addr = ioaddr->cmd_addr + ATA_REG_LBAM;
 	ioaddr->lbah_addr = ioaddr->cmd_addr + ATA_REG_LBAH;
 	ioaddr->device_addr = ioaddr->cmd_addr + ATA_REG_DEVICE;
 	ioaddr->status_addr = ioaddr->cmd_addr + ATA_REG_STATUS;
 	ioaddr->command_addr = ioaddr->cmd_addr + ATA_REG_CMD;
 }
 EXPORT_SYMBOL_GPL(ata_sff_std_ports);
 #ifdef CONFIG_PCI
 static int ata_resources_present(struct pci_dev *pdev, int port)
 {
 	int i;
 	/* Check the PCI resources for this channel are enabled */
 	port = port * 2;
 	for (i = 0; i < 2; i++) {
 		if (pci_resource_start(pdev, port + i) == 0 ||
 		    pci_resource_len(pdev, port + i) == 0)
 			return 0;
 	}
 	return 1;
 }
 /**
  *	ata_pci_sff_init_host - acquire native PCI ATA resources and init host
  *	@host: target ATA host
  *
  *	Acquire native PCI ATA resources for @host and initialize the
  *	first two ports of @host accordingly.  Ports marked dummy are
  *	skipped and allocation failure makes the port dummy.
  *
  *	Note that native PCI resources are valid even for legacy hosts
  *	as we fix up pdev resources array early in boot, so this
  *	function can be used for both native and legacy SFF hosts.
  *
  *	LOCKING:
  *	Inherited from calling layer (may sleep).
  *
  *	RETURNS:
  *	0 if at least one port is initialized, -ENODEV if no port is
  *	available.
  */
 int ata_pci_sff_init_host(struct ata_host *host)
 {
 	struct device *gdev = host->dev;
 	struct pci_dev *pdev = to_pci_dev(gdev);
 	unsigned int mask = 0;
 	int i, rc;
 	/* request, iomap BARs and init port addresses accordingly */
 	for (i = 0; i < 2; i++) {
 		struct ata_port *ap = host->ports[i];
 		int base = i * 2;
 		void __iomem * const *iomap;
 		if (ata_port_is_dummy(ap))
 			continue;
 		/* Discard disabled ports.  Some controllers show
 		 * their unused channels this way.  Disabled ports are
 		 * made dummy.
 		 */
 		if (!ata_resources_present(pdev, i)) {
 			ap->ops = &ata_dummy_port_ops;
 			continue;
 		}
 		rc = pcim_iomap_regions(pdev, 0x3 << base,
 					dev_driver_string(gdev));
 		if (rc) {
 			dev_printk(KERN_WARNING, gdev,
 				   "failed to request/iomap BARs for port %d "
 				   "(errno=%d)\n", i, rc);
 			if (rc == -EBUSY)
 				pcim_pin_device(pdev);
 			ap->ops = &ata_dummy_port_ops;
 			continue;
 		}
 		host->iomap = iomap = pcim_iomap_table(pdev);
 		ap->ioaddr.cmd_addr = iomap[base];
 		ap->ioaddr.altstatus_addr =
 		ap->ioaddr.ctl_addr = (void __iomem *)
 			((unsigned long)iomap[base + 1] | ATA_PCI_CTL_OFS);
 		ata_sff_std_ports(&ap->ioaddr);
 		ata_port_desc(ap, "cmd 0x%llx ctl 0x%llx",
 			(unsigned long long)pci_resource_start(pdev, base),
 			(unsigned long long)pci_resource_start(pdev, base + 1));
 		mask |= 1 << i;
 	}
 	if (!mask) {
 		dev_printk(KERN_ERR, gdev, "no available native port\n");
 		return -ENODEV;
 	}
 	return 0;
 }
 EXPORT_SYMBOL_GPL(ata_pci_sff_init_host);
 /**
  *	ata_pci_sff_prepare_host - helper to prepare PCI PIO-only SFF ATA host
  *	@pdev: target PCI device
  *	@ppi: array of port_info, must be enough for two ports
  *	@r_host: out argument for the initialized ATA host
  *
  *	Helper to allocate PIO-only SFF ATA host for @pdev, acquire
  *	all PCI resources and initialize it accordingly in one go.
  *
  *	LOCKING:
  *	Inherited from calling layer (may sleep).
  *
  *	RETURNS:
  *	0 on success, -errno otherwise.
  */
 int ata_pci_sff_prepare_host(struct pci_dev *pdev,
 			     const struct ata_port_info * const *ppi,
 			     struct ata_host **r_host)
 {
 	struct ata_host *host;
 	int rc;
 	if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL))
 		return -ENOMEM;
 	host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
 	if (!host) {
 		dev_printk(KERN_ERR, &pdev->dev,
 			   "failed to allocate ATA host\n");
 		rc = -ENOMEM;
 		goto err_out;
 	}
 	rc = ata_pci_sff_init_host(host);
 	if (rc)
 		goto err_out;
 	devres_remove_group(&pdev->dev, NULL);
 	*r_host = host;
 	return 0;
 err_out:
 	devres_release_group(&pdev->dev, NULL);
 	return rc;
 }
 EXPORT_SYMBOL_GPL(ata_pci_sff_prepare_host);
 /**
  *	ata_pci_sff_activate_host - start SFF host, request IRQ and register it
  *	@host: target SFF ATA host
  *	@irq_handler: irq_handler used when requesting IRQ(s)
  *	@sht: scsi_host_template to use when registering the host
  *
  *	This is the counterpart of ata_host_activate() for SFF ATA
  *	hosts.  This separate helper is necessary because SFF hosts
  *	use two separate interrupts in legacy mode.
  *
  *	LOCKING:
  *	Inherited from calling layer (may sleep).
  *
  *	RETURNS:
  *	0 on success, -errno otherwise.
  */
 int ata_pci_sff_activate_host(struct ata_host *host,
 			      irq_handler_t irq_handler,
 			      struct scsi_host_template *sht)
 {
 	struct device *dev = host->dev;
 	struct pci_dev *pdev = to_pci_dev(dev);
 	const char *drv_name = dev_driver_string(host->dev);
 	int legacy_mode = 0, rc;
 	rc = ata_host_start(host);
 	if (rc)
 		return rc;
 	if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
 		u8 tmp8, mask;
 		/* TODO: What if one channel is in native mode ... */
 		pci_read_config_byte(pdev, PCI_CLASS_PROG, &tmp8);
 		mask = (1 << 2) | (1 << 0);
 		if ((tmp8 & mask) != mask)
 			legacy_mode = 1;
 #if defined(CONFIG_NO_ATA_LEGACY)
 		/* Some platforms with PCI limits cannot address compat
 		   port space. In that case we punt if their firmware has
 		   left a device in compatibility mode */
 		if (legacy_mode) {
 			printk(KERN_ERR "ata: Compatibility mode ATA is not supported on this platform, skipping.\n");
 			return -EOPNOTSUPP;
 		}
 #endif
 	}
 	if (!devres_open_group(dev, NULL, GFP_KERNEL))
 		return -ENOMEM;
 	if (!legacy_mode && pdev->irq) {
 		rc = devm_request_irq(dev, pdev->irq, irq_handler,
 				      IRQF_SHARED, drv_name, host);
 		if (rc)
 			goto out;
 		ata_port_desc(host->ports[0], "irq %d", pdev->irq);
 		ata_port_desc(host->ports[1], "irq %d", pdev->irq);
 	} else if (legacy_mode) {
 		if (!ata_port_is_dummy(host->ports[0])) {
 			rc = devm_request_irq(dev, ATA_PRIMARY_IRQ(pdev),
 					      irq_handler, IRQF_SHARED,
 					      drv_name, host);
 			if (rc)
 				goto out;
 			ata_port_desc(host->ports[0], "irq %d",
 				      ATA_PRIMARY_IRQ(pdev));
 		}
 		if (!ata_port_is_dummy(host->ports[1])) {
 			rc = devm_request_irq(dev, ATA_SECONDARY_IRQ(pdev),
 					      irq_handler, IRQF_SHARED,
 					      drv_name, host);
 			if (rc)
 				goto out;
 			ata_port_desc(host->ports[1], "irq %d",
 				      ATA_SECONDARY_IRQ(pdev));
 		}
 	}
 	rc = ata_host_register(host, sht);
 out:
 	if (rc == 0)
 		devres_remove_group(dev, NULL);
 	else
 		devres_release_group(dev, NULL);
 	return rc;
 }
 EXPORT_SYMBOL_GPL(ata_pci_sff_activate_host);
 static const struct ata_port_info *ata_sff_find_valid_pi(
 					const struct ata_port_info * const *ppi)
 {
 	int i;
 	/* look up the first valid port_info */
 	for (i = 0; i < 2 && ppi[i]; i++)
 		if (ppi[i]->port_ops != &ata_dummy_port_ops)
 			return ppi[i];
 	return NULL;
 }
 /**
  *	ata_pci_sff_init_one - Initialize/register PIO-only PCI IDE controller
  *	@pdev: Controller to be initialized
  *	@ppi: array of port_info, must be enough for two ports
  *	@sht: scsi_host_template to use when registering the host
  *	@host_priv: host private_data
  *	@hflag: host flags
  *
  *	This is a helper function which can be called from a driver's
  *	xxx_init_one() probe function if the hardware uses traditional
  *	IDE taskfile registers and is PIO only.
  *
  *	ASSUMPTION:
  *	Nobody makes a single channel controller that appears solely as
  *	the secondary legacy port on PCI.
  *
  *	LOCKING:
  *	Inherited from PCI layer (may sleep).
  *
  *	RETURNS:
  *	Zero on success, negative on errno-based value on error.
  */
 int ata_pci_sff_init_one(struct pci_dev *pdev,
 		 const struct ata_port_info * const *ppi,
 		 struct scsi_host_template *sht, void *host_priv, int hflag)
 {
 	struct device *dev = &pdev->dev;
 	const struct ata_port_info *pi;
 	struct ata_host *host = NULL;
 	int rc;
 	DPRINTK("ENTER\n");
 	pi = ata_sff_find_valid_pi(ppi);
 	if (!pi) {
 		dev_printk(KERN_ERR, &pdev->dev,
 			   "no valid port_info specified\n");
 		return -EINVAL;
 	}
 	if (!devres_open_group(dev, NULL, GFP_KERNEL))
 		return -ENOMEM;
 	rc = pcim_enable_device(pdev);
 	if (rc)
 		goto out;
 	/* prepare and activate SFF host */
 	rc = ata_pci_sff_prepare_host(pdev, ppi, &host);
 	if (rc)
 		goto out;
 	host->private_data = host_priv;
 	host->flags |= hflag;
 	rc = ata_pci_sff_activate_host(host, ata_sff_interrupt, sht);
 out:
 	if (rc == 0)
 		devres_remove_group(&pdev->dev, NULL);
 	else
 		devres_release_group(&pdev->dev, NULL);
 	return rc;
 }
 EXPORT_SYMBOL_GPL(ata_pci_sff_init_one);
 #endif /* CONFIG_PCI */
 /*
  *	BMDMA support
  */
 #ifdef CONFIG_ATA_BMDMA
 const struct ata_port_operations ata_bmdma_port_ops = {
 	.inherits		= &ata_sff_port_ops,
 	.error_handler		= ata_bmdma_error_handler,
 	.post_internal_cmd	= ata_bmdma_post_internal_cmd,
 	.qc_prep		= ata_bmdma_qc_prep,
 	.qc_issue		= ata_bmdma_qc_issue,
 	.sff_irq_clear		= ata_bmdma_irq_clear,
 	.bmdma_setup		= ata_bmdma_setup,
 	.bmdma_start		= ata_bmdma_start,
 	.bmdma_stop		= ata_bmdma_stop,
 	.bmdma_status		= ata_bmdma_status,
 	.port_start		= ata_bmdma_port_start,
 };
 EXPORT_SYMBOL_GPL(ata_bmdma_port_ops);
 const struct ata_port_operations ata_bmdma32_port_ops = {
 	.inherits		= &ata_bmdma_port_ops,
 	.sff_data_xfer		= ata_sff_data_xfer32,
 	.port_start		= ata_bmdma_port_start32,
 };
 EXPORT_SYMBOL_GPL(ata_bmdma32_port_ops);
 /**
  *	ata_bmdma_fill_sg - Fill PCI IDE PRD table
  *	@qc: Metadata associated with taskfile to be transferred
  *
  *	Fill PCI IDE PRD (scatter-gather) table with segments
  *	associated with the current disk command.
  *
  *	LOCKING:
  *	spin_lock_irqsave(host lock)
  *
  */
 static void ata_bmdma_fill_sg(struct ata_queued_cmd *qc)
 {
 	struct ata_port *ap = qc->ap;
 	struct ata_bmdma_prd *prd = ap->bmdma_prd;
 	struct scatterlist *sg;
 	unsigned int si, pi;
 	pi = 0;
 	for_each_sg(qc->sg, sg, qc->n_elem, si) {
 		u32 addr, offset;
 		u32 sg_len, len;
 		/* determine if physical DMA addr spans 64K boundary.
 		 * Note h/w doesn't support 64-bit, so we unconditionally
 		 * truncate dma_addr_t to u32.
 		 */
 		addr = (u32) sg_dma_address(sg);
 		sg_len = sg_dma_len(sg);
 		while (sg_len) {
 			offset = addr & 0xffff;
 			len = sg_len;
 			if ((offset + sg_len) > 0x10000)
 				len = 0x10000 - offset;
 			prd[pi].addr = cpu_to_le32(addr);
 			prd[pi].flags_len = cpu_to_le32(len & 0xffff);
 			VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len);
 			pi++;
 			sg_len -= len;
 			addr += len;
 		}
 	}
 	prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
 }
 /**
  *	ata_bmdma_fill_sg_dumb - Fill PCI IDE PRD table
  *	@qc: Metadata associated with taskfile to be transferred
  *
  *	Fill PCI IDE PRD (scatter-gather) table with segments
  *	associated with the current disk command. Perform the fill
  *	so that we avoid writing any length 64K records for
  *	controllers that don't follow the spec.
  *
  *	LOCKING:
  *	spin_lock_irqsave(host lock)
  *
  */
 static void ata_bmdma_fill_sg_dumb(struct ata_queued_cmd *qc)
 {
 	struct ata_port *ap = qc->ap;
 	struct ata_bmdma_prd *prd = ap->bmdma_prd;
 	struct scatterlist *sg;
 	unsigned int si, pi;
 	pi = 0;
 	for_each_sg(qc->sg, sg, qc->n_elem, si) {
 		u32 addr, offset;
 		u32 sg_len, len, blen;
 		/* determine if physical DMA addr spans 64K boundary.
 		 * Note h/w doesn't support 64-bit, so we unconditionally
 		 * truncate dma_addr_t to u32.
 		 */
 		addr = (u32) sg_dma_address(sg);
 		sg_len = sg_dma_len(sg);
 		while (sg_len) {
 			offset = addr & 0xffff;
 			len = sg_len;
 			if ((offset + sg_len) > 0x10000)
 				len = 0x10000 - offset;
 			blen = len & 0xffff;
 			prd[pi].addr = cpu_to_le32(addr);
 			if (blen == 0) {
 				/* Some PATA chipsets like the CS5530 can't
 				   cope with 0x0000 meaning 64K as the spec
 				   says */
 				prd[pi].flags_len = cpu_to_le32(0x8000);
 				blen = 0x8000;
 				prd[++pi].addr = cpu_to_le32(addr + 0x8000);
 			}
 			prd[pi].flags_len = cpu_to_le32(blen);
 			VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len);
 			pi++;
 			sg_len -= len;
 			addr += len;
 		}
 	}
 	prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
 }
 /**
  *	ata_bmdma_qc_prep - Prepare taskfile for submission
  *	@qc: Metadata associated with taskfile to be prepared
  *
  *	Prepare ATA taskfile for submission.
  *
  *	LOCKING:
  *	spin_lock_irqsave(host lock)
  */
 void ata_bmdma_qc_prep(struct ata_queued_cmd *qc)
 {
 	if (!(qc->flags & ATA_QCFLAG_DMAMAP))
 		return;
 	ata_bmdma_fill_sg(qc);
 }
 EXPORT_SYMBOL_GPL(ata_bmdma_qc_prep);
 /**
  *	ata_bmdma_dumb_qc_prep - Prepare taskfile for submission
  *	@qc: Metadata associated with taskfile to be prepared
  *
  *	Prepare ATA taskfile for submission.
  *
  *	LOCKING:
  *	spin_lock_irqsave(host lock)
  */
 void ata_bmdma_dumb_qc_prep(struct ata_queued_cmd *qc)
 {
 	if (!(qc->flags & ATA_QCFLAG_DMAMAP))
 		return;
 	ata_bmdma_fill_sg_dumb(qc);
 }
 EXPORT_SYMBOL_GPL(ata_bmdma_dumb_qc_prep);
 /**
  *	ata_bmdma_qc_issue - issue taskfile to a BMDMA controller
  *	@qc: command to issue to device
  *
  *	This function issues a PIO, NODATA or DMA command to a
  *	SFF/BMDMA controller.  PIO and NODATA are handled by
  *	ata_sff_qc_issue().
  *
  *	LOCKING:
  *	spin_lock_irqsave(host lock)
  *
  *	RETURNS:
  *	Zero on success, AC_ERR_* mask on failure
  */
 unsigned int ata_bmdma_qc_issue(struct ata_queued_cmd *qc)
 {
 	struct ata_port *ap = qc->ap;
+	struct ata_link *link = qc->dev->link;
 	/* defer PIO handling to sff_qc_issue */
 	if (!ata_is_dma(qc->tf.protocol))
 		return ata_sff_qc_issue(qc);
 	/* select the device */
 	ata_dev_select(ap, qc->dev->devno, 1, 0);
 	/* start the command */
 	switch (qc->tf.protocol) {
 	case ATA_PROT_DMA:
 		WARN_ON_ONCE(qc->tf.flags & ATA_TFLAG_POLLING);
 		ap->ops->sff_tf_load(ap, &qc->tf);  /* load tf registers */
 		ap->ops->bmdma_setup(qc);	    /* set up bmdma */
 		ap->ops->bmdma_start(qc);	    /* initiate bmdma */
 		ap->hsm_task_state = HSM_ST_LAST;
 		break;
 	case ATAPI_PROT_DMA:
 		WARN_ON_ONCE(qc->tf.flags & ATA_TFLAG_POLLING);
 		ap->ops->sff_tf_load(ap, &qc->tf);  /* load tf registers */
 		ap->ops->bmdma_setup(qc);	    /* set up bmdma */
 		ap->hsm_task_state = HSM_ST_FIRST;
 		/* send cdb by polling if no cdb interrupt */
 		if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
-			ata_sff_queue_pio_task(ap, 0);
+			ata_sff_queue_pio_task(link, 0);
 		break;
 	default:
 		WARN_ON(1);
 		return AC_ERR_SYSTEM;
 	}
 	return 0;
 }
 EXPORT_SYMBOL_GPL(ata_bmdma_qc_issue);
 /**
  *	ata_bmdma_port_intr - Handle BMDMA port interrupt
  *	@ap: Port on which interrupt arrived (possibly...)
  *	@qc: Taskfile currently active in engine
  *
  *	Handle port interrupt for given queued command.
  *
  *	LOCKING:
  *	spin_lock_irqsave(host lock)
  *
  *	RETURNS:
  *	One if interrupt was handled, zero if not (shared irq).
  */
 unsigned int ata_bmdma_port_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
 {
 	struct ata_eh_info *ehi = &ap->link.eh_info;
 	u8 host_stat = 0;
 	bool bmdma_stopped = false;
 	unsigned int handled;
 	if (ap->hsm_task_state == HSM_ST_LAST && ata_is_dma(qc->tf.protocol)) {
 		/* check status of DMA engine */
 		host_stat = ap->ops->bmdma_status(ap);
 		VPRINTK("ata%u: host_stat 0x%X\n", ap->print_id, host_stat);
 		/* if it's not our irq... */
 		if (!(host_stat & ATA_DMA_INTR))
 			return ata_sff_idle_irq(ap);
 		/* before we do anything else, clear DMA-Start bit */
 		ap->ops->bmdma_stop(qc);
 		bmdma_stopped = true;
 		if (unlikely(host_stat & ATA_DMA_ERR)) {
 			/* error when transfering data to/from memory */
 			qc->err_mask |= AC_ERR_HOST_BUS;
 			ap->hsm_task_state = HSM_ST_ERR;
 		}
 	}
 	handled = __ata_sff_port_intr(ap, qc, bmdma_stopped);
 	if (unlikely(qc->err_mask) && ata_is_dma(qc->tf.protocol))
 		ata_ehi_push_desc(ehi, "BMDMA stat 0x%x", host_stat);
 	return handled;
 }
 EXPORT_SYMBOL_GPL(ata_bmdma_port_intr);
 /**
  *	ata_bmdma_interrupt - Default BMDMA ATA host interrupt handler
  *	@irq: irq line (unused)
  *	@dev_instance: pointer to our ata_host information structure
  *
  *	Default interrupt handler for PCI IDE devices.  Calls
  *	ata_bmdma_port_intr() for each port that is not disabled.
  *
  *	LOCKING:
  *	Obtains host lock during operation.
  *
  *	RETURNS:
  *	IRQ_NONE or IRQ_HANDLED.
  */
 irqreturn_t ata_bmdma_interrupt(int irq, void *dev_instance)
 {
 	return __ata_sff_interrupt(irq, dev_instance, ata_bmdma_port_intr);
 }
 EXPORT_SYMBOL_GPL(ata_bmdma_interrupt);
 /**
  *	ata_bmdma_error_handler - Stock error handler for BMDMA controller
  *	@ap: port to handle error for
  *
  *	Stock error handler for BMDMA controller.  It can handle both
  *	PATA and SATA controllers.  Most BMDMA controllers should be
  *	able to use this EH as-is or with some added handling before
  *	and after.
  *
  *	LOCKING:
  *	Kernel thread context (may sleep)
  */
 void ata_bmdma_error_handler(struct ata_port *ap)
 {
 	struct ata_queued_cmd *qc;
 	unsigned long flags;
 	bool thaw = false;
 	qc = __ata_qc_from_tag(ap, ap->link.active_tag);
 	if (qc && !(qc->flags & ATA_QCFLAG_FAILED))
 		qc = NULL;
 	/* reset PIO HSM and stop DMA engine */
 	spin_lock_irqsave(ap->lock, flags);
 	if (qc && ata_is_dma(qc->tf.protocol)) {
 		u8 host_stat;
 		host_stat = ap->ops->bmdma_status(ap);
 		/* BMDMA controllers indicate host bus error by
 		 * setting DMA_ERR bit and timing out.  As it wasn't
 		 * really a timeout event, adjust error mask and
 		 * cancel frozen state.
 		 */
 		if (qc->err_mask == AC_ERR_TIMEOUT && (host_stat & ATA_DMA_ERR)) {
 			qc->err_mask = AC_ERR_HOST_BUS;
 			thaw = true;
 		}
 		ap->ops->bmdma_stop(qc);
 		/* if we're gonna thaw, make sure IRQ is clear */
 		if (thaw) {
 			ap->ops->sff_check_status(ap);
 			if (ap->ops->sff_irq_clear)
 				ap->ops->sff_irq_clear(ap);
 		}
 	}
 	spin_unlock_irqrestore(ap->lock, flags);
 	if (thaw)
 		ata_eh_thaw_port(ap);
 	ata_sff_error_handler(ap);
 }
 EXPORT_SYMBOL_GPL(ata_bmdma_error_handler);
 /**
  *	ata_bmdma_post_internal_cmd - Stock post_internal_cmd for BMDMA
  *	@qc: internal command to clean up
  *
  *	LOCKING:
  *	Kernel thread context (may sleep)
  */
 void ata_bmdma_post_internal_cmd(struct ata_queued_cmd *qc)
 {
 	struct ata_port *ap = qc->ap;
 	unsigned long flags;
 	if (ata_is_dma(qc->tf.protocol)) {
 		spin_lock_irqsave(ap->lock, flags);
 		ap->ops->bmdma_stop(qc);
 		spin_unlock_irqrestore(ap->lock, flags);
 	}
 }
 EXPORT_SYMBOL_GPL(ata_bmdma_post_internal_cmd);
 /**
  *	ata_bmdma_irq_clear - Clear PCI IDE BMDMA interrupt.
  *	@ap: Port associated with this ATA transaction.
  *
  *	Clear interrupt and error flags in DMA status register.
  *
  *	May be used as the irq_clear() entry in ata_port_operations.
  *
  *	LOCKING:
  *	spin_lock_irqsave(host lock)
  */
 void ata_bmdma_irq_clear(struct ata_port *ap)
 {
 	void __iomem *mmio = ap->ioaddr.bmdma_addr;
 	if (!mmio)
 		return;
 	iowrite8(ioread8(mmio + ATA_DMA_STATUS), mmio + ATA_DMA_STATUS);
 }
 EXPORT_SYMBOL_GPL(ata_bmdma_irq_clear);
 /**
  *	ata_bmdma_setup - Set up PCI IDE BMDMA transaction
  *	@qc: Info associated with this ATA transaction.
  *
  *	LOCKING:
  *	spin_lock_irqsave(host lock)
  */
 void ata_bmdma_setup(struct ata_queued_cmd *qc)
 {
 	struct ata_port *ap = qc->ap;
 	unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
 	u8 dmactl;
 	/* load PRD table addr. */
 	mb();	/* make sure PRD table writes are visible to controller */
 	iowrite32(ap->bmdma_prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS);
 	/* specify data direction, triple-check start bit is clear */
 	dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
 	dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
 	if (!rw)
 		dmactl |= ATA_DMA_WR;
 	iowrite8(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
 	/* issue r/w command */
 	ap->ops->sff_exec_command(ap, &qc->tf);
 }
 EXPORT_SYMBOL_GPL(ata_bmdma_setup);
 /**
  *	ata_bmdma_start - Start a PCI IDE BMDMA transaction
  *	@qc: Info associated with this ATA transaction.
  *
  *	LOCKING:
  *	spin_lock_irqsave(host lock)
  */
 void ata_bmdma_start(struct ata_queued_cmd *qc)
 {
 	struct ata_port *ap = qc->ap;
 	u8 dmactl;
 	/* start host DMA transaction */
 	dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
 	iowrite8(dmactl | ATA_DMA_START, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
 	/* Strictly, one may wish to issue an ioread8() here, to
 	 * flush the mmio write.  However, control also passes
 	 * to the hardware at this point, and it will interrupt
 	 * us when we are to resume control.  So, in effect,
 	 * we don't care when the mmio write flushes.
 	 * Further, a read of the DMA status register _immediately_
 	 * following the write may not be what certain flaky hardware
 	 * is expected, so I think it is best to not add a readb()
 	 * without first all the MMIO ATA cards/mobos.
 	 * Or maybe I'm just being paranoid.
 	 *
 	 * FIXME: The posting of this write means I/O starts are
 	 * unneccessarily delayed for MMIO
 	 */
 }
 EXPORT_SYMBOL_GPL(ata_bmdma_start);
 /**
  *	ata_bmdma_stop - Stop PCI IDE BMDMA transfer
  *	@qc: Command we are ending DMA for
  *
  *	Clears the ATA_DMA_START flag in the dma control register
  *
  *	May be used as the bmdma_stop() entry in ata_port_operations.
  *
  *	LOCKING:
  *	spin_lock_irqsave(host lock)
  */
 void ata_bmdma_stop(struct ata_queued_cmd *qc)
 {
 	struct ata_port *ap = qc->ap;
 	void __iomem *mmio = ap->ioaddr.bmdma_addr;
 	/* clear start/stop bit */
 	iowrite8(ioread8(mmio + ATA_DMA_CMD) & ~ATA_DMA_START,
 		 mmio + ATA_DMA_CMD);
 	/* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
 	ata_sff_dma_pause(ap);
 }
 EXPORT_SYMBOL_GPL(ata_bmdma_stop);
 /**
  *	ata_bmdma_status - Read PCI IDE BMDMA status
  *	@ap: Port associated with this ATA transaction.
  *
  *	Read and return BMDMA status register.
  *
  *	May be used as the bmdma_status() entry in ata_port_operations.
  *
  *	LOCKING:
  *	spin_lock_irqsave(host lock)
  */
 u8 ata_bmdma_status(struct ata_port *ap)
 {
 	return ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
 }
 EXPORT_SYMBOL_GPL(ata_bmdma_status);
 /**
  *	ata_bmdma_port_start - Set port up for bmdma.
  *	@ap: Port to initialize
  *
  *	Called just after data structures for each port are
  *	initialized.  Allocates space for PRD table.
  *
  *	May be used as the port_start() entry in ata_port_operations.
  *
  *	LOCKING:
  *	Inherited from caller.
  */
 int ata_bmdma_port_start(struct ata_port *ap)
 {
 	if (ap->mwdma_mask || ap->udma_mask) {
 		ap->bmdma_prd =
 			dmam_alloc_coherent(ap->host->dev, ATA_PRD_TBL_SZ,
 					    &ap->bmdma_prd_dma, GFP_KERNEL);
 		if (!ap->bmdma_prd)
 			return -ENOMEM;
 	}
 	return 0;
 }
 EXPORT_SYMBOL_GPL(ata_bmdma_port_start);
 /**
  *	ata_bmdma_port_start32 - Set port up for dma.
  *	@ap: Port to initialize
  *
  *	Called just after data structures for each port are
  *	initialized.  Enables 32bit PIO and allocates space for PRD
  *	table.
  *
  *	May be used as the port_start() entry in ata_port_operations for
  *	devices that are capable of 32bit PIO.
  *
  *	LOCKING:
  *	Inherited from caller.
  */
 int ata_bmdma_port_start32(struct ata_port *ap)
 {
 	ap->pflags |= ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE;
 	return ata_bmdma_port_start(ap);
 }
 EXPORT_SYMBOL_GPL(ata_bmdma_port_start32);
 #ifdef CONFIG_PCI
 /**
  *	ata_pci_bmdma_clear_simplex -	attempt to kick device out of simplex
  *	@pdev: PCI device
  *
  *	Some PCI ATA devices report simplex mode but in fact can be told to
  *	enter non simplex mode. This implements the necessary logic to
  *	perform the task on such devices. Calling it on other devices will
  *	have -undefined- behaviour.
  */
 int ata_pci_bmdma_clear_simplex(struct pci_dev *pdev)
 {
 	unsigned long bmdma = pci_resource_start(pdev, 4);
 	u8 simplex;
 	if (bmdma == 0)
 		return -ENOENT;
 	simplex = inb(bmdma + 0x02);
 	outb(simplex & 0x60, bmdma + 0x02);
 	simplex = inb(bmdma + 0x02);
 	if (simplex & 0x80)
 		return -EOPNOTSUPP;
 	return 0;
 }
 EXPORT_SYMBOL_GPL(ata_pci_bmdma_clear_simplex);
 static void ata_bmdma_nodma(struct ata_host *host, const char *reason)
 {
 	int i;
 	dev_printk(KERN_ERR, host->dev, "BMDMA: %s, falling back to PIO\n",
 		   reason);
 	for (i = 0; i < 2; i++) {
 		host->ports[i]->mwdma_mask = 0;
 		host->ports[i]->udma_mask = 0;
 	}
 }
 /**
  *	ata_pci_bmdma_init - acquire PCI BMDMA resources and init ATA host
  *	@host: target ATA host
  *
  *	Acquire PCI BMDMA resources and initialize @host accordingly.
  *
  *	LOCKING:
  *	Inherited from calling layer (may sleep).
  */
 void ata_pci_bmdma_init(struct ata_host *host)
 {
 	struct device *gdev = host->dev;
 	struct pci_dev *pdev = to_pci_dev(gdev);
 	int i, rc;
 	/* No BAR4 allocation: No DMA */
 	if (pci_resource_start(pdev, 4) == 0) {
 		ata_bmdma_nodma(host, "BAR4 is zero");
 		return;
 	}
 	/*
 	 * Some controllers require BMDMA region to be initialized
 	 * even if DMA is not in use to clear IRQ status via
 	 * ->sff_irq_clear method.  Try to initialize bmdma_addr
 	 * regardless of dma masks.
 	 */
 	rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
 	if (rc)
 		ata_bmdma_nodma(host, "failed to set dma mask");
 	if (!rc) {
 		rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
 		if (rc)
 			ata_bmdma_nodma(host,
 					"failed to set consistent dma mask");
 	}
 	/* request and iomap DMA region */
 	rc = pcim_iomap_regions(pdev, 1 << 4, dev_driver_string(gdev));
 	if (rc) {
 		ata_bmdma_nodma(host, "failed to request/iomap BAR4");
 		return;
 	}
 	host->iomap = pcim_iomap_table(pdev);
 	for (i = 0; i < 2; i++) {
 		struct ata_port *ap = host->ports[i];
 		void __iomem *bmdma = host->iomap[4] + 8 * i;
 		if (ata_port_is_dummy(ap))
 			continue;
 		ap->ioaddr.bmdma_addr = bmdma;
 		if ((!(ap->flags & ATA_FLAG_IGN_SIMPLEX)) &&
 		    (ioread8(bmdma + 2) & 0x80))
 			host->flags |= ATA_HOST_SIMPLEX;
 		ata_port_desc(ap, "bmdma 0x%llx",
 		    (unsigned long long)pci_resource_start(pdev, 4) + 8 * i);
 	}
 }
 EXPORT_SYMBOL_GPL(ata_pci_bmdma_init);
 /**
  *	ata_pci_bmdma_prepare_host - helper to prepare PCI BMDMA ATA host
  *	@pdev: target PCI device
  *	@ppi: array of port_info, must be enough for two ports
  *	@r_host: out argument for the initialized ATA host
  *
  *	Helper to allocate BMDMA ATA host for @pdev, acquire all PCI
  *	resources and initialize it accordingly in one go.
  *
  *	LOCKING:
  *	Inherited from calling layer (may sleep).
  *
  *	RETURNS:
  *	0 on success, -errno otherwise.
  */
 int ata_pci_bmdma_prepare_host(struct pci_dev *pdev,
 			       const struct ata_port_info * const * ppi,
 			       struct ata_host **r_host)
 {
 	int rc;
 	rc = ata_pci_sff_prepare_host(pdev, ppi, r_host);
 	if (rc)
 		return rc;
 	ata_pci_bmdma_init(*r_host);
 	return 0;
 }
 EXPORT_SYMBOL_GPL(ata_pci_bmdma_prepare_host);
 /**
  *	ata_pci_bmdma_init_one - Initialize/register BMDMA PCI IDE controller
  *	@pdev: Controller to be initialized
  *	@ppi: array of port_info, must be enough for two ports
  *	@sht: scsi_host_template to use when registering the host
  *	@host_priv: host private_data
  *	@hflags: host flags
  *
  *	This function is similar to ata_pci_sff_init_one() but also
  *	takes care of BMDMA initialization.
  *
  *	LOCKING:
  *	Inherited from PCI layer (may sleep).
  *
  *	RETURNS:
  *	Zero on success, negative on errno-based value on error.
  */
 int ata_pci_bmdma_init_one(struct pci_dev *pdev,
 			   const struct ata_port_info * const * ppi,
 			   struct scsi_host_template *sht, void *host_priv,
 			   int hflags)
 {
 	struct device *dev = &pdev->dev;
 	const struct ata_port_info *pi;
 	struct ata_host *host = NULL;
 	int rc;
 	DPRINTK("ENTER\n");
 	pi = ata_sff_find_valid_pi(ppi);
 	if (!pi) {
 		dev_printk(KERN_ERR, &pdev->dev,
 			   "no valid port_info specified\n");
 		return -EINVAL;
 	}
 	if (!devres_open_group(dev, NULL, GFP_KERNEL))
 		return -ENOMEM;
 	rc = pcim_enable_device(pdev);
 	if (rc)
 		goto out;
 	/* prepare and activate BMDMA host */
 	rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
 	if (rc)
 		goto out;
 	host->private_data = host_priv;
 	host->flags |= hflags;
 	pci_set_master(pdev);
 	rc = ata_pci_sff_activate_host(host, ata_bmdma_interrupt, sht);
  out:
 	if (rc == 0)
 		devres_remove_group(&pdev->dev, NULL);
 	else
 		devres_release_group(&pdev->dev, NULL);
 	return rc;
 }
 EXPORT_SYMBOL_GPL(ata_pci_bmdma_init_one);
 #endif /* CONFIG_PCI */
 #endif /* CONFIG_ATA_BMDMA */
 /**
  *	ata_sff_port_init - Initialize SFF/BMDMA ATA port
  *	@ap: Port to initialize
  *
  *	Called on port allocation to initialize SFF/BMDMA specific
  *	fields.
  *
  *	LOCKING:
  *	None.
  */
 void ata_sff_port_init(struct ata_port *ap)
 {
 	INIT_DELAYED_WORK(&ap->sff_pio_task, ata_sff_pio_task);
 	ap->ctl = ATA_DEVCTL_OBS;
 	ap->last_ctl = 0xFF;
 }
 int __init ata_sff_init(void)
 {
 	ata_sff_wq = alloc_workqueue("ata_sff", WQ_RESCUER, WQ_MAX_ACTIVE);
 	if (!ata_sff_wq)
 		return -ENOMEM;
 	return 0;
 }
 void __exit ata_sff_exit(void)
 {
 	destroy_workqueue(ata_sff_wq);
 }

drivers/ata/pata_artop.c

Diff comments View file @ df423dc

 /*
  *    pata_artop.c - ARTOP ATA controller driver
  *
  *	(C) 2006 Red Hat
  *	(C) 2007 Bartlomiej Zolnierkiewicz
  *
  *    Based in part on drivers/ide/pci/aec62xx.c
  *	Copyright (C) 1999-2002	Andre Hedrick <andre@linux-ide.org>
  *	865/865R fixes for Macintosh card version from a patch to the old
  *		driver by Thibaut VARENE <varenet@parisc-linux.org>
  *	When setting the PCI latency we must set 0x80 or higher for burst
  *		performance Alessandro Zummo <alessandro.zummo@towertech.it>
  *
  *	TODO
  *	Investigate no_dsc on 850R
  *	Clock detect
  */
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/pci.h>
 #include <linux/init.h>
 #include <linux/blkdev.h>
 #include <linux/delay.h>
 #include <linux/device.h>
 #include <scsi/scsi_host.h>
 #include <linux/libata.h>
 #include <linux/ata.h>
 #define DRV_NAME	"pata_artop"
 #define DRV_VERSION	"0.4.5"
 /*
  *	The ARTOP has 33 Mhz and "over clocked" timing tables. Until we
  *	get PCI bus speed functionality we leave this as 0. Its a variable
  *	for when we get the functionality and also for folks wanting to
  *	test stuff.
  */
 static int clock = 0;
 static int artop6210_pre_reset(struct ata_link *link, unsigned long deadline)
 {
 	struct ata_port *ap = link->ap;
 	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 	const struct pci_bits artop_enable_bits[] = {
 		{ 0x4AU, 1U, 0x02UL, 0x02UL },	/* port 0 */
 		{ 0x4AU, 1U, 0x04UL, 0x04UL },	/* port 1 */
 	};
 	if (!pci_test_config_bits(pdev, &artop_enable_bits[ap->port_no]))
 		return -ENOENT;
 	return ata_sff_prereset(link, deadline);
 }
 /**
  *	artop6260_pre_reset	-	check for 40/80 pin
  *	@link: link
  *	@deadline: deadline jiffies for the operation
  *
  *	The ARTOP hardware reports the cable detect bits in register 0x49.
  *	Nothing complicated needed here.
  */
 static int artop6260_pre_reset(struct ata_link *link, unsigned long deadline)
 {
 	static const struct pci_bits artop_enable_bits[] = {
 		{ 0x4AU, 1U, 0x02UL, 0x02UL },	/* port 0 */
 		{ 0x4AU, 1U, 0x04UL, 0x04UL },	/* port 1 */
 	};
 	struct ata_port *ap = link->ap;
 	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 	/* Odd numbered device ids are the units with enable bits (the -R cards) */
-	if (pdev->device % 1 && !pci_test_config_bits(pdev, &artop_enable_bits[ap->port_no]))
+	if ((pdev->device & 1) &&
+	    !pci_test_config_bits(pdev, &artop_enable_bits[ap->port_no]))
 		return -ENOENT;
 	return ata_sff_prereset(link, deadline);
 }
 /**
  *	artop6260_cable_detect	-	identify cable type
  *	@ap: Port
  *
  *	Identify the cable type for the ARTOP interface in question
  */
 static int artop6260_cable_detect(struct ata_port *ap)
 {
 	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 	u8 tmp;
 	pci_read_config_byte(pdev, 0x49, &tmp);
 	if (tmp & (1 << ap->port_no))
 		return ATA_CBL_PATA40;
 	return ATA_CBL_PATA80;
 }
 /**
  *	artop6210_load_piomode - Load a set of PATA PIO timings
  *	@ap: Port whose timings we are configuring
  *	@adev: Device
  *	@pio: PIO mode
  *
  *	Set PIO mode for device, in host controller PCI config space. This
  *	is used both to set PIO timings in PIO mode and also to set the
  *	matching PIO clocking for UDMA, as well as the MWDMA timings.
  *
  *	LOCKING:
  *	None (inherited from caller).
  */
 static void artop6210_load_piomode(struct ata_port *ap, struct ata_device *adev, unsigned int pio)
 {
 	struct pci_dev *pdev	= to_pci_dev(ap->host->dev);
 	int dn = adev->devno + 2 * ap->port_no;
 	const u16 timing[2][5] = {
 		{ 0x0000, 0x000A, 0x0008, 0x0303, 0x0301 },
 		{ 0x0700, 0x070A, 0x0708, 0x0403, 0x0401 }
 	};
 	/* Load the PIO timing active/recovery bits */
 	pci_write_config_word(pdev, 0x40 + 2 * dn, timing[clock][pio]);
 }
 /**
  *	artop6210_set_piomode - Initialize host controller PATA PIO timings
  *	@ap: Port whose timings we are configuring
  *	@adev: Device we are configuring
  *
  *	Set PIO mode for device, in host controller PCI config space. For
  *	ARTOP we must also clear the UDMA bits if we are not doing UDMA. In
  *	the event UDMA is used the later call to set_dmamode will set the
  *	bits as required.
  *
  *	LOCKING:
  *	None (inherited from caller).
  */
 static void artop6210_set_piomode(struct ata_port *ap, struct ata_device *adev)
 {
 	struct pci_dev *pdev	= to_pci_dev(ap->host->dev);
 	int dn = adev->devno + 2 * ap->port_no;
 	u8 ultra;
 	artop6210_load_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
 	/* Clear the UDMA mode bits (set_dmamode will redo this if needed) */
 	pci_read_config_byte(pdev, 0x54, &ultra);
 	ultra &= ~(3 << (2 * dn));
 	pci_write_config_byte(pdev, 0x54, ultra);
 }
 /**
  *	artop6260_load_piomode - Initialize host controller PATA PIO timings
  *	@ap: Port whose timings we are configuring
  *	@adev: Device we are configuring
  *	@pio: PIO mode
  *
  *	Set PIO mode for device, in host controller PCI config space. The
  *	ARTOP6260 and relatives store the timing data differently.
  *
  *	LOCKING:
  *	None (inherited from caller).
  */
 static void artop6260_load_piomode (struct ata_port *ap, struct ata_device *adev, unsigned int pio)
 {
 	struct pci_dev *pdev	= to_pci_dev(ap->host->dev);
 	int dn = adev->devno + 2 * ap->port_no;
 	const u8 timing[2][5] = {
 		{ 0x00, 0x0A, 0x08, 0x33, 0x31 },
 		{ 0x70, 0x7A, 0x78, 0x43, 0x41 }
 	};
 	/* Load the PIO timing active/recovery bits */
 	pci_write_config_byte(pdev, 0x40 + dn, timing[clock][pio]);
 }
 /**
  *	artop6260_set_piomode - Initialize host controller PATA PIO timings
  *	@ap: Port whose timings we are configuring
  *	@adev: Device we are configuring
  *
  *	Set PIO mode for device, in host controller PCI config space. For
  *	ARTOP we must also clear the UDMA bits if we are not doing UDMA. In
  *	the event UDMA is used the later call to set_dmamode will set the
  *	bits as required.
  *
  *	LOCKING:
  *	None (inherited from caller).
  */
 static void artop6260_set_piomode(struct ata_port *ap, struct ata_device *adev)
 {
 	struct pci_dev *pdev	= to_pci_dev(ap->host->dev);
 	u8 ultra;
 	artop6260_load_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
 	/* Clear the UDMA mode bits (set_dmamode will redo this if needed) */
 	pci_read_config_byte(pdev, 0x44 + ap->port_no, &ultra);
 	ultra &= ~(7 << (4  * adev->devno));	/* One nibble per drive */
 	pci_write_config_byte(pdev, 0x44 + ap->port_no, ultra);
 }
 /**
  *	artop6210_set_dmamode - Initialize host controller PATA PIO timings
  *	@ap: Port whose timings we are configuring
  *	@adev: Device whose timings we are configuring
  *
  *	Set DMA mode for device, in host controller PCI config space.
  *
  *	LOCKING:
  *	None (inherited from caller).
  */
 static void artop6210_set_dmamode (struct ata_port *ap, struct ata_device *adev)
 {
 	unsigned int pio;
 	struct pci_dev *pdev	= to_pci_dev(ap->host->dev);
 	int dn = adev->devno + 2 * ap->port_no;
 	u8 ultra;
 	if (adev->dma_mode == XFER_MW_DMA_0)
 		pio = 1;
 	else
 		pio = 4;
 	/* Load the PIO timing active/recovery bits */
 	artop6210_load_piomode(ap, adev, pio);
 	pci_read_config_byte(pdev, 0x54, &ultra);
 	ultra &= ~(3 << (2 * dn));
 	/* Add ultra DMA bits if in UDMA mode */
 	if (adev->dma_mode >= XFER_UDMA_0) {
 		u8 mode = (adev->dma_mode - XFER_UDMA_0) + 1 - clock;
 		if (mode == 0)
 			mode = 1;
 		ultra |= (mode << (2 * dn));
 	}
 	pci_write_config_byte(pdev, 0x54, ultra);
 }
 /**
  *	artop6260_set_dmamode - Initialize host controller PATA PIO timings
  *	@ap: Port whose timings we are configuring
  *	@adev: Device we are configuring
  *
  *	Set DMA mode for device, in host controller PCI config space. The
  *	ARTOP6260 and relatives store the timing data differently.
  *
  *	LOCKING:
  *	None (inherited from caller).
  */
 static void artop6260_set_dmamode (struct ata_port *ap, struct ata_device *adev)
 {
 	unsigned int pio	= adev->pio_mode - XFER_PIO_0;
 	struct pci_dev *pdev	= to_pci_dev(ap->host->dev);
 	u8 ultra;
 	if (adev->dma_mode == XFER_MW_DMA_0)
 		pio = 1;
 	else
 		pio = 4;
 	/* Load the PIO timing active/recovery bits */
 	artop6260_load_piomode(ap, adev, pio);
 	/* Add ultra DMA bits if in UDMA mode */
 	pci_read_config_byte(pdev, 0x44 + ap->port_no, &ultra);
 	ultra &= ~(7 << (4  * adev->devno));	/* One nibble per drive */
 	if (adev->dma_mode >= XFER_UDMA_0) {
 		u8 mode = adev->dma_mode - XFER_UDMA_0 + 1 - clock;
 		if (mode == 0)
 			mode = 1;
 		ultra |= (mode << (4 * adev->devno));
 	}
 	pci_write_config_byte(pdev, 0x44 + ap->port_no, ultra);
 }
 /**
  *	artop_6210_qc_defer	-	implement serialization
  *	@qc: command
  *
  *	Issue commands per host on this chip.
  */
 static int artop6210_qc_defer(struct ata_queued_cmd *qc)
 {
 	struct ata_host *host = qc->ap->host;
 	struct ata_port *alt = host->ports[1 ^ qc->ap->port_no];
 	int rc;
 	/* First apply the usual rules */
 	rc = ata_std_qc_defer(qc);
 	if (rc != 0)
 		return rc;
 	/* Now apply serialization rules. Only allow a command if the
 	   other channel state machine is idle */
 	if (alt && alt->qc_active)
 		return	ATA_DEFER_PORT;
 	return 0;
 }
 static struct scsi_host_template artop_sht = {
 	ATA_BMDMA_SHT(DRV_NAME),
 };
 static struct ata_port_operations artop6210_ops = {
 	.inherits		= &ata_bmdma_port_ops,
 	.cable_detect		= ata_cable_40wire,
 	.set_piomode		= artop6210_set_piomode,
 	.set_dmamode		= artop6210_set_dmamode,
 	.prereset		= artop6210_pre_reset,
 	.qc_defer		= artop6210_qc_defer,
 };
 static struct ata_port_operations artop6260_ops = {
 	.inherits		= &ata_bmdma_port_ops,
 	.cable_detect		= artop6260_cable_detect,
 	.set_piomode		= artop6260_set_piomode,
 	.set_dmamode		= artop6260_set_dmamode,
 	.prereset		= artop6260_pre_reset,
 };
 /**
  *	artop_init_one - Register ARTOP ATA PCI device with kernel services
  *	@pdev: PCI device to register
  *	@ent: Entry in artop_pci_tbl matching with @pdev
  *
  *	Called from kernel PCI layer.
  *
  *	LOCKING:
  *	Inherited from PCI layer (may sleep).
  *
  *	RETURNS:
  *	Zero on success, or -ERRNO value.
  */
 static int artop_init_one (struct pci_dev *pdev, const struct pci_device_id *id)
 {
 	static int printed_version;
 	static const struct ata_port_info info_6210 = {
 		.flags		= ATA_FLAG_SLAVE_POSS,
 		.pio_mask	= ATA_PIO4,
 		.mwdma_mask	= ATA_MWDMA2,
 		.udma_mask 	= ATA_UDMA2,
 		.port_ops	= &artop6210_ops,
 	};
 	static const struct ata_port_info info_626x = {
 		.flags		= ATA_FLAG_SLAVE_POSS,
 		.pio_mask	= ATA_PIO4,
 		.mwdma_mask	= ATA_MWDMA2,
 		.udma_mask 	= ATA_UDMA4,
 		.port_ops	= &artop6260_ops,
 	};
 	static const struct ata_port_info info_628x = {
 		.flags		= ATA_FLAG_SLAVE_POSS,
 		.pio_mask	= ATA_PIO4,
 		.mwdma_mask	= ATA_MWDMA2,
 		.udma_mask 	= ATA_UDMA5,
 		.port_ops	= &artop6260_ops,
 	};
 	static const struct ata_port_info info_628x_fast = {
 		.flags		= ATA_FLAG_SLAVE_POSS,
 		.pio_mask	= ATA_PIO4,
 		.mwdma_mask	= ATA_MWDMA2,
 		.udma_mask 	= ATA_UDMA6,
 		.port_ops	= &artop6260_ops,
 	};
 	const struct ata_port_info *ppi[] = { NULL, NULL };
 	int rc;
 	if (!printed_version++)
 		dev_printk(KERN_DEBUG, &pdev->dev,
 			   "version " DRV_VERSION "\n");
 	rc = pcim_enable_device(pdev);
 	if (rc)
 		return rc;
 	if (id->driver_data == 0) {	/* 6210 variant */
 		ppi[0] = &info_6210;
 		/* BIOS may have left us in UDMA, clear it before libata probe */
 		pci_write_config_byte(pdev, 0x54, 0);
 	}
 	else if (id->driver_data == 1)	/* 6260 */
 		ppi[0] = &info_626x;
 	else if (id->driver_data == 2)	{ /* 6280 or 6280 + fast */
 		unsigned long io = pci_resource_start(pdev, 4);
 		u8 reg;
 		ppi[0] = &info_628x;
 		if (inb(io) & 0x10)
 			ppi[0] = &info_628x_fast;
 		/* Mac systems come up with some registers not set as we
 		   will need them */
 		/* Clear reset & test bits */
 		pci_read_config_byte(pdev, 0x49, &reg);
 		pci_write_config_byte(pdev, 0x49, reg & ~ 0x30);
 		/* PCI latency must be > 0x80 for burst mode, tweak it
 		 * if required.
 		 */
 		pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &reg);
 		if (reg <= 0x80)
 			pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x90);
 		/* Enable IRQ output and burst mode */
 		pci_read_config_byte(pdev, 0x4a, &reg);
 		pci_write_config_byte(pdev, 0x4a, (reg & ~0x01) | 0x80);
 	}
 	BUG_ON(ppi[0] == NULL);
 	return ata_pci_bmdma_init_one(pdev, ppi, &artop_sht, NULL, 0);
 }
 static const struct pci_device_id artop_pci_tbl[] = {
 	{ PCI_VDEVICE(ARTOP, 0x0005), 0 },
 	{ PCI_VDEVICE(ARTOP, 0x0006), 1 },
 	{ PCI_VDEVICE(ARTOP, 0x0007), 1 },
 	{ PCI_VDEVICE(ARTOP, 0x0008), 2 },
 	{ PCI_VDEVICE(ARTOP, 0x0009), 2 },
 	{ }	/* terminate list */
 };
 static struct pci_driver artop_pci_driver = {
 	.name			= DRV_NAME,
 	.id_table		= artop_pci_tbl,
 	.probe			= artop_init_one,
 	.remove			= ata_pci_remove_one,
 };
 static int __init artop_init(void)
 {
 	return pci_register_driver(&artop_pci_driver);
 }
 static void __exit artop_exit(void)
 {
 	pci_unregister_driver(&artop_pci_driver);
 }
 module_init(artop_init);
 module_exit(artop_exit);
 MODULE_AUTHOR("Alan Cox");
 MODULE_DESCRIPTION("SCSI low-level driver for ARTOP PATA");
 MODULE_LICENSE("GPL");
 MODULE_DEVICE_TABLE(pci, artop_pci_tbl);
 MODULE_VERSION(DRV_VERSION);

drivers/ata/pata_via.c

Diff comments View file @ df423dc

 /*
  * pata_via.c 	- VIA PATA for new ATA layer
  *			  (C) 2005-2006 Red Hat Inc
  *
  *  Documentation
  *	Most chipset documentation available under NDA only
  *
  *  VIA version guide
  *	VIA VT82C561	-	early design, uses ata_generic currently
  *	VIA VT82C576	-	MWDMA, 33Mhz
  *	VIA VT82C586	-	MWDMA, 33Mhz
  *	VIA VT82C586a	-	Added UDMA to 33Mhz
  *	VIA VT82C586b	-	UDMA33
  *	VIA VT82C596a	-	Nonfunctional UDMA66
  *	VIA VT82C596b	-	Working UDMA66
  *	VIA VT82C686	-	Nonfunctional UDMA66
  *	VIA VT82C686a	-	Working UDMA66
  *	VIA VT82C686b	-	Updated to UDMA100
  *	VIA VT8231	-	UDMA100
  *	VIA VT8233	-	UDMA100
  *	VIA VT8233a	-	UDMA133
  *	VIA VT8233c	-	UDMA100
  *	VIA VT8235	-	UDMA133
  *	VIA VT8237	-	UDMA133
  *	VIA VT8237A	-	UDMA133
  *	VIA VT8237S	-	UDMA133
  *	VIA VT8251	-	UDMA133
  *
  *	Most registers remain compatible across chips. Others start reserved
  *	and acquire sensible semantics if set to 1 (eg cable detect). A few
  *	exceptions exist, notably around the FIFO settings.
  *
  *	One additional quirk of the VIA design is that like ALi they use few
  *	PCI IDs for a lot of chips.
  *
  *	Based heavily on:
  *
  * Version 3.38
  *
  * VIA IDE driver for Linux. Supported southbridges:
  *
  *   vt82c576, vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b,
  *   vt82c686, vt82c686a, vt82c686b, vt8231, vt8233, vt8233c, vt8233a,
  *   vt8235, vt8237
  *
  * Copyright (c) 2000-2002 Vojtech Pavlik
  *
  * Based on the work of:
  *	Michel Aubry
  *	Jeff Garzik
  *	Andre Hedrick
  */
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/pci.h>
 #include <linux/init.h>
 #include <linux/blkdev.h>
 #include <linux/delay.h>
 #include <linux/gfp.h>
 #include <scsi/scsi_host.h>
 #include <linux/libata.h>
 #include <linux/dmi.h>
 #define DRV_NAME "pata_via"
 #define DRV_VERSION "0.3.4"
 enum {
 	VIA_BAD_PREQ	= 0x01, /* Crashes if PREQ# till DDACK# set */
 	VIA_BAD_CLK66	= 0x02, /* 66 MHz clock doesn't work correctly */
 	VIA_SET_FIFO	= 0x04, /* Needs to have FIFO split set */
 	VIA_NO_UNMASK	= 0x08, /* Doesn't work with IRQ unmasking on */
 	VIA_BAD_ID	= 0x10, /* Has wrong vendor ID (0x1107) */
 	VIA_BAD_AST	= 0x20, /* Don't touch Address Setup Timing */
 	VIA_NO_ENABLES	= 0x40, /* Has no enablebits */
 	VIA_SATA_PATA	= 0x80, /* SATA/PATA combined configuration */
 };
 enum {
 	VIA_IDFLAG_SINGLE = (1 << 0), /* single channel controller) */
 };
 /*
  * VIA SouthBridge chips.
  */
 static const struct via_isa_bridge {
 	const char *name;
 	u16 id;
 	u8 rev_min;
 	u8 rev_max;
 	u8 udma_mask;
 	u8 flags;
 } via_isa_bridges[] = {
 	{ "vx855",	PCI_DEVICE_ID_VIA_VX855,    0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_SATA_PATA },
 	{ "vx800",	PCI_DEVICE_ID_VIA_VX800,    0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_SATA_PATA },
 	{ "vt8261",	PCI_DEVICE_ID_VIA_8261,     0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
 	{ "vt8237s",	PCI_DEVICE_ID_VIA_8237S,    0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
 	{ "vt8251",	PCI_DEVICE_ID_VIA_8251,     0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
 	{ "cx700",	PCI_DEVICE_ID_VIA_CX700,    0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_SATA_PATA },
 	{ "vt6410",	PCI_DEVICE_ID_VIA_6410,     0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_NO_ENABLES },
 	{ "vt6415",	PCI_DEVICE_ID_VIA_6415,     0x00, 0xff, ATA_UDMA6, VIA_BAD_AST | VIA_NO_ENABLES },
 	{ "vt8237a",	PCI_DEVICE_ID_VIA_8237A,    0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
 	{ "vt8237",	PCI_DEVICE_ID_VIA_8237,     0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
 	{ "vt8235",	PCI_DEVICE_ID_VIA_8235,     0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
 	{ "vt8233a",	PCI_DEVICE_ID_VIA_8233A,    0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
 	{ "vt8233c",	PCI_DEVICE_ID_VIA_8233C_0,  0x00, 0x2f, ATA_UDMA5, },
 	{ "vt8233",	PCI_DEVICE_ID_VIA_8233_0,   0x00, 0x2f, ATA_UDMA5, },
 	{ "vt8231",	PCI_DEVICE_ID_VIA_8231,     0x00, 0x2f, ATA_UDMA5, },
 	{ "vt82c686b",	PCI_DEVICE_ID_VIA_82C686,   0x40, 0x4f, ATA_UDMA5, },
 	{ "vt82c686a",	PCI_DEVICE_ID_VIA_82C686,   0x10, 0x2f, ATA_UDMA4, },
 	{ "vt82c686",	PCI_DEVICE_ID_VIA_82C686,   0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 },
 	{ "vt82c596b",	PCI_DEVICE_ID_VIA_82C596,   0x10, 0x2f, ATA_UDMA4, },
 	{ "vt82c596a",	PCI_DEVICE_ID_VIA_82C596,   0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 },
 	{ "vt82c586b",	PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, ATA_UDMA2, VIA_SET_FIFO },
 	{ "vt82c586b",	PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, ATA_UDMA2, VIA_SET_FIFO | VIA_BAD_PREQ },
 	{ "vt82c586b",	PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, ATA_UDMA2, VIA_SET_FIFO },
 	{ "vt82c586a",	PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, ATA_UDMA2, VIA_SET_FIFO },
 	{ "vt82c586",	PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f,      0x00, VIA_SET_FIFO },
 	{ "vt82c576",	PCI_DEVICE_ID_VIA_82C576,   0x00, 0x2f,      0x00, VIA_SET_FIFO | VIA_NO_UNMASK },
 	{ "vt82c576",	PCI_DEVICE_ID_VIA_82C576,   0x00, 0x2f,      0x00, VIA_SET_FIFO | VIA_NO_UNMASK | VIA_BAD_ID },
 	{ "vtxxxx",	PCI_DEVICE_ID_VIA_ANON,     0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
 	{ NULL }
 };
 struct via_port {
 	u8 cached_device;
 };
 /*
  *	Cable special cases
  */
 static const struct dmi_system_id cable_dmi_table[] = {
 	{
 		.ident = "Acer Ferrari 3400",
 		.matches = {
 			DMI_MATCH(DMI_BOARD_VENDOR, "Acer,Inc."),
 			DMI_MATCH(DMI_BOARD_NAME, "Ferrari 3400"),
 		},
 	},
 	{ }
 };
 static int via_cable_override(struct pci_dev *pdev)
 {
 	/* Systems by DMI */
 	if (dmi_check_system(cable_dmi_table))
 		return 1;
 	/* Arima W730-K8/Targa Visionary 811/... */
 	if (pdev->subsystem_vendor == 0x161F && pdev->subsystem_device == 0x2032)
 		return 1;
 	return 0;
 }
 /**
  *	via_cable_detect	-	cable detection
  *	@ap: ATA port
  *
  *	Perform cable detection. Actually for the VIA case the BIOS
  *	already did this for us. We read the values provided by the
  *	BIOS. If you are using an 8235 in a non-PC configuration you
  *	may need to update this code.
  *
  *	Hotplug also impacts on this.
  */
 static int via_cable_detect(struct ata_port *ap) {
 	const struct via_isa_bridge *config = ap->host->private_data;
 	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 	u32 ata66;
 	if (via_cable_override(pdev))
 		return ATA_CBL_PATA40_SHORT;
 	if ((config->flags & VIA_SATA_PATA) && ap->port_no == 0)
 		return ATA_CBL_SATA;
 	/* Early chips are 40 wire */
 	if (config->udma_mask < ATA_UDMA4)
 		return ATA_CBL_PATA40;
 	/* UDMA 66 chips have only drive side logic */
 	else if (config->udma_mask < ATA_UDMA5)
 		return ATA_CBL_PATA_UNK;
 	/* UDMA 100 or later */
 	pci_read_config_dword(pdev, 0x50, &ata66);
 	/* Check both the drive cable reporting bits, we might not have
 	   two drives */
 	if (ata66 & (0x10100000 >> (16 * ap->port_no)))
 		return ATA_CBL_PATA80;
 	/* Check with ACPI so we can spot BIOS reported SATA bridges */
 	if (ata_acpi_init_gtm(ap) &&
 	    ata_acpi_cbl_80wire(ap, ata_acpi_init_gtm(ap)))
 		return ATA_CBL_PATA80;
 	return ATA_CBL_PATA40;
 }
 static int via_pre_reset(struct ata_link *link, unsigned long deadline)
 {
 	struct ata_port *ap = link->ap;
 	const struct via_isa_bridge *config = ap->host->private_data;
 	if (!(config->flags & VIA_NO_ENABLES)) {
 		static const struct pci_bits via_enable_bits[] = {
 			{ 0x40, 1, 0x02, 0x02 },
 			{ 0x40, 1, 0x01, 0x01 }
 		};
 		struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 		if (!pci_test_config_bits(pdev, &via_enable_bits[ap->port_no]))
 			return -ENOENT;
 	}
 	return ata_sff_prereset(link, deadline);
 }
 /**
  *	via_do_set_mode	-	set transfer mode data
  *	@ap: ATA interface
  *	@adev: ATA device
  *	@mode: ATA mode being programmed
  *	@set_ast: Set to program address setup
  *	@udma_type: UDMA mode/format of registers
  *
  *	Program the VIA registers for DMA and PIO modes. Uses the ata timing
  *	support in order to compute modes.
  *
  *	FIXME: Hotplug will require we serialize multiple mode changes
  *	on the two channels.
  */
 static void via_do_set_mode(struct ata_port *ap, struct ata_device *adev,
 			    int mode, int set_ast, int udma_type)
 {
 	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 	struct ata_device *peer = ata_dev_pair(adev);
 	struct ata_timing t, p;
 	static int via_clock = 33333;	/* Bus clock in kHZ */
 	unsigned long T =  1000000000 / via_clock;
 	unsigned long UT = T;
 	int ut;
 	int offset = 3 - (2*ap->port_no) - adev->devno;
 	switch (udma_type) {
 	case ATA_UDMA4:
 		UT = T / 2; break;
 	case ATA_UDMA5:
 		UT = T / 3; break;
 	case ATA_UDMA6:
 		UT = T / 4; break;
 	}
 	/* Calculate the timing values we require */
 	ata_timing_compute(adev, mode, &t, T, UT);
 	/* We share 8bit timing so we must merge the constraints */
 	if (peer) {
 		if (peer->pio_mode) {
 			ata_timing_compute(peer, peer->pio_mode, &p, T, UT);
 			ata_timing_merge(&p, &t, &t, ATA_TIMING_8BIT);
 		}
 	}
 	/* Address setup is programmable but breaks on UDMA133 setups */
 	if (set_ast) {
 		u8 setup;	/* 2 bits per drive */
 		int shift = 2 * offset;
 		pci_read_config_byte(pdev, 0x4C, &setup);
 		setup &= ~(3 << shift);
 		setup |= (clamp_val(t.setup, 1, 4) - 1) << shift;
 		pci_write_config_byte(pdev, 0x4C, setup);
 	}
 	/* Load the PIO mode bits */
 	pci_write_config_byte(pdev, 0x4F - ap->port_no,
 		((clamp_val(t.act8b, 1, 16) - 1) << 4) | (clamp_val(t.rec8b, 1, 16) - 1));
 	pci_write_config_byte(pdev, 0x48 + offset,
 		((clamp_val(t.active, 1, 16) - 1) << 4) | (clamp_val(t.recover, 1, 16) - 1));
 	/* Load the UDMA bits according to type */
 	switch (udma_type) {
 	case ATA_UDMA2:
 	default:
 		ut = t.udma ? (0xe0 | (clamp_val(t.udma, 2, 5) - 2)) : 0x03;
 		break;
 	case ATA_UDMA4:
 		ut = t.udma ? (0xe8 | (clamp_val(t.udma, 2, 9) - 2)) : 0x0f;
 		break;
 	case ATA_UDMA5:
 		ut = t.udma ? (0xe0 | (clamp_val(t.udma, 2, 9) - 2)) : 0x07;
 		break;
 	case ATA_UDMA6:
 		ut = t.udma ? (0xe0 | (clamp_val(t.udma, 2, 9) - 2)) : 0x07;
 		break;
 	}
 	/* Set UDMA unless device is not UDMA capable */
 	if (udma_type) {
 		u8 udma_etc;
 		pci_read_config_byte(pdev, 0x50 + offset, &udma_etc);
 		/* clear transfer mode bit */
 		udma_etc &= ~0x20;
 		if (t.udma) {
 			/* preserve 80-wire cable detection bit */
 			udma_etc &= 0x10;
 			udma_etc |= ut;
 		}
 		pci_write_config_byte(pdev, 0x50 + offset, udma_etc);
 	}
 }
 static void via_set_piomode(struct ata_port *ap, struct ata_device *adev)
 {
 	const struct via_isa_bridge *config = ap->host->private_data;
 	int set_ast = (config->flags & VIA_BAD_AST) ? 0 : 1;
 	via_do_set_mode(ap, adev, adev->pio_mode, set_ast, config->udma_mask);
 }
 static void via_set_dmamode(struct ata_port *ap, struct ata_device *adev)
 {
 	const struct via_isa_bridge *config = ap->host->private_data;
 	int set_ast = (config->flags & VIA_BAD_AST) ? 0 : 1;
 	via_do_set_mode(ap, adev, adev->dma_mode, set_ast, config->udma_mask);
 }
 /**
  *	via_mode_filter		-	filter buggy device/mode pairs
  *	@dev: ATA device
  *	@mask: Mode bitmask
  *
  *	We need to apply some minimal filtering for old controllers and at least
  *	one breed of Transcend SSD. Return the updated mask.
  */
 static unsigned long via_mode_filter(struct ata_device *dev, unsigned long mask)
 {
 	struct ata_host *host = dev->link->ap->host;
 	const struct via_isa_bridge *config = host->private_data;
 	unsigned char model_num[ATA_ID_PROD_LEN + 1];
 	if (config->id == PCI_DEVICE_ID_VIA_82C586_0) {
 		ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
 		if (strcmp(model_num, "TS64GSSD25-M") == 0) {
 			ata_dev_printk(dev, KERN_WARNING,
 	"disabling UDMA mode due to reported lockups with this device.\n");
 			mask &= ~ ATA_MASK_UDMA;
 		}
 	}
 	return mask;
 }
 /**
  *	via_tf_load - send taskfile registers to host controller
  *	@ap: Port to which output is sent
  *	@tf: ATA taskfile register set
  *
  *	Outputs ATA taskfile to standard ATA host controller.
  *
  *	Note: This is to fix the internal bug of via chipsets, which
  *	will reset the device register after changing the IEN bit on
  *	ctl register
  */
 static void via_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
 {
 	struct ata_ioports *ioaddr = &ap->ioaddr;
 	struct via_port *vp = ap->private_data;
 	unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
 	int newctl = 0;
 	if (tf->ctl != ap->last_ctl) {
 		iowrite8(tf->ctl, ioaddr->ctl_addr);
 		ap->last_ctl = tf->ctl;
 		ata_wait_idle(ap);
 		newctl = 1;
 	}
 	if (tf->flags & ATA_TFLAG_DEVICE) {
 		iowrite8(tf->device, ioaddr->device_addr);
 		vp->cached_device = tf->device;
 	} else if (newctl)
 		iowrite8(vp->cached_device, ioaddr->device_addr);
 	if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
 		WARN_ON_ONCE(!ioaddr->ctl_addr);
 		iowrite8(tf->hob_feature, ioaddr->feature_addr);
 		iowrite8(tf->hob_nsect, ioaddr->nsect_addr);
 		iowrite8(tf->hob_lbal, ioaddr->lbal_addr);
 		iowrite8(tf->hob_lbam, ioaddr->lbam_addr);
 		iowrite8(tf->hob_lbah, ioaddr->lbah_addr);
 		VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
 			tf->hob_feature,
 			tf->hob_nsect,
 			tf->hob_lbal,
 			tf->hob_lbam,
 			tf->hob_lbah);
 	}
 	if (is_addr) {
 		iowrite8(tf->feature, ioaddr->feature_addr);
 		iowrite8(tf->nsect, ioaddr->nsect_addr);
 		iowrite8(tf->lbal, ioaddr->lbal_addr);
 		iowrite8(tf->lbam, ioaddr->lbam_addr);
 		iowrite8(tf->lbah, ioaddr->lbah_addr);
 		VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
 			tf->feature,
 			tf->nsect,
 			tf->lbal,
 			tf->lbam,
 			tf->lbah);
 	}
+	ata_wait_idle(ap);
 }
 static int via_port_start(struct ata_port *ap)
 {
 	struct via_port *vp;
 	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 	int ret = ata_bmdma_port_start(ap);
 	if (ret < 0)
 		return ret;
 	vp = devm_kzalloc(&pdev->dev, sizeof(struct via_port), GFP_KERNEL);
 	if (vp == NULL)
 		return -ENOMEM;
 	ap->private_data = vp;
 	return 0;
 }
 static struct scsi_host_template via_sht = {
 	ATA_BMDMA_SHT(DRV_NAME),
 };
 static struct ata_port_operations via_port_ops = {
 	.inherits	= &ata_bmdma_port_ops,
 	.cable_detect	= via_cable_detect,
 	.set_piomode	= via_set_piomode,
 	.set_dmamode	= via_set_dmamode,
 	.prereset	= via_pre_reset,
 	.sff_tf_load	= via_tf_load,
 	.port_start	= via_port_start,
 	.mode_filter	= via_mode_filter,
 };
 static struct ata_port_operations via_port_ops_noirq = {
 	.inherits	= &via_port_ops,
 	.sff_data_xfer	= ata_sff_data_xfer_noirq,
 };
 /**
  *	via_config_fifo		-	set up the FIFO
  *	@pdev: PCI device
  *	@flags: configuration flags
  *
  *	Set the FIFO properties for this device if necessary. Used both on
  *	set up and on and the resume path
  */
 static void via_config_fifo(struct pci_dev *pdev, unsigned int flags)
 {
 	u8 enable;
 	/* 0x40 low bits indicate enabled channels */
 	pci_read_config_byte(pdev, 0x40 , &enable);
 	enable &= 3;
 	if (flags & VIA_SET_FIFO) {
 		static const u8 fifo_setting[4] = {0x00, 0x60, 0x00, 0x20};
 		u8 fifo;
 		pci_read_config_byte(pdev, 0x43, &fifo);
 		/* Clear PREQ# until DDACK# for errata */
 		if (flags & VIA_BAD_PREQ)
 			fifo &= 0x7F;
 		else
 			fifo &= 0x9f;
 		/* Turn on FIFO for enabled channels */
 		fifo |= fifo_setting[enable];
 		pci_write_config_byte(pdev, 0x43, fifo);
 	}
 }
 /**
  *	via_init_one		-	discovery callback
  *	@pdev: PCI device
  *	@id: PCI table info
  *
  *	A VIA IDE interface has been discovered. Figure out what revision
  *	and perform configuration work before handing it to the ATA layer
  */
 static int via_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
 {
 	/* Early VIA without UDMA support */
 	static const struct ata_port_info via_mwdma_info = {
 		.flags = ATA_FLAG_SLAVE_POSS,
 		.pio_mask = ATA_PIO4,
 		.mwdma_mask = ATA_MWDMA2,
 		.port_ops = &via_port_ops
 	};
 	/* Ditto with IRQ masking required */
 	static const struct ata_port_info via_mwdma_info_borked = {
 		.flags = ATA_FLAG_SLAVE_POSS,
 		.pio_mask = ATA_PIO4,
 		.mwdma_mask = ATA_MWDMA2,
 		.port_ops = &via_port_ops_noirq,
 	};
 	/* VIA UDMA 33 devices (and borked 66) */
 	static const struct ata_port_info via_udma33_info = {
 		.flags = ATA_FLAG_SLAVE_POSS,
 		.pio_mask = ATA_PIO4,
 		.mwdma_mask = ATA_MWDMA2,
 		.udma_mask = ATA_UDMA2,
 		.port_ops = &via_port_ops
 	};
 	/* VIA UDMA 66 devices */
 	static const struct ata_port_info via_udma66_info = {
 		.flags = ATA_FLAG_SLAVE_POSS,
 		.pio_mask = ATA_PIO4,
 		.mwdma_mask = ATA_MWDMA2,
 		.udma_mask = ATA_UDMA4,
 		.port_ops = &via_port_ops
 	};
 	/* VIA UDMA 100 devices */
 	static const struct ata_port_info via_udma100_info = {
 		.flags = ATA_FLAG_SLAVE_POSS,
 		.pio_mask = ATA_PIO4,
 		.mwdma_mask = ATA_MWDMA2,
 		.udma_mask = ATA_UDMA5,
 		.port_ops = &via_port_ops
 	};
 	/* UDMA133 with bad AST (All current 133) */
 	static const struct ata_port_info via_udma133_info = {
 		.flags = ATA_FLAG_SLAVE_POSS,
 		.pio_mask = ATA_PIO4,
 		.mwdma_mask = ATA_MWDMA2,
 		.udma_mask = ATA_UDMA6,	/* FIXME: should check north bridge */
 		.port_ops = &via_port_ops
 	};
 	const struct ata_port_info *ppi[] = { NULL, NULL };
 	struct pci_dev *isa;
 	const struct via_isa_bridge *config;
 	static int printed_version;
 	u8 enable;
 	u32 timing;
 	unsigned long flags = id->driver_data;
 	int rc;
 	if (!printed_version++)
 		dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
 	rc = pcim_enable_device(pdev);
 	if (rc)
 		return rc;
 	if (flags & VIA_IDFLAG_SINGLE)
 		ppi[1] = &ata_dummy_port_info;
 	/* To find out how the IDE will behave and what features we
 	   actually have to look at the bridge not the IDE controller */
 	for (config = via_isa_bridges; config->id != PCI_DEVICE_ID_VIA_ANON;
 	     config++)
 		if ((isa = pci_get_device(PCI_VENDOR_ID_VIA +
 			!!(config->flags & VIA_BAD_ID),
 			config->id, NULL))) {
 			u8 rev = isa->revision;
 			pci_dev_put(isa);
 			if ((id->device == 0x0415 || id->device == 0x3164) &&
 			    (config->id != id->device))
 				continue;
 			if (rev >= config->rev_min && rev <= config->rev_max)
 				break;
 		}
 	if (!(config->flags & VIA_NO_ENABLES)) {
 		/* 0x40 low bits indicate enabled channels */
 		pci_read_config_byte(pdev, 0x40 , &enable);
 		enable &= 3;
 		if (enable == 0)
 			return -ENODEV;
 	}
 	/* Initialise the FIFO for the enabled channels. */
 	via_config_fifo(pdev, config->flags);
 	/* Clock set up */
 	switch (config->udma_mask) {
 	case 0x00:
 		if (config->flags & VIA_NO_UNMASK)
 			ppi[0] = &via_mwdma_info_borked;
 		else
 			ppi[0] = &via_mwdma_info;
 		break;
 	case ATA_UDMA2:
 		ppi[0] = &via_udma33_info;
 		break;
 	case ATA_UDMA4:
 		ppi[0] = &via_udma66_info;
 		break;
 	case ATA_UDMA5:
 		ppi[0] = &via_udma100_info;
 		break;
 	case ATA_UDMA6:
 		ppi[0] = &via_udma133_info;
 		break;
 	default:
 		WARN_ON(1);
 		return -ENODEV;
  	}
 	if (config->flags & VIA_BAD_CLK66) {
 		/* Disable the 66MHz clock on problem devices */
 		pci_read_config_dword(pdev, 0x50, &timing);
 		timing &= ~0x80008;
 		pci_write_config_dword(pdev, 0x50, timing);
 	}
 	/* We have established the device type, now fire it up */
 	return ata_pci_bmdma_init_one(pdev, ppi, &via_sht, (void *)config, 0);
 }
 #ifdef CONFIG_PM
 /**
  *	via_reinit_one		-	reinit after resume
  *	@pdev; PCI device
  *
  *	Called when the VIA PATA device is resumed. We must then
  *	reconfigure the fifo and other setup we may have altered. In
  *	addition the kernel needs to have the resume methods on PCI
  *	quirk supported.
  */
 static int via_reinit_one(struct pci_dev *pdev)
 {
 	u32 timing;
 	struct ata_host *host = dev_get_drvdata(&pdev->dev);
 	const struct via_isa_bridge *config = host->private_data;
 	int rc;
 	rc = ata_pci_device_do_resume(pdev);
 	if (rc)
 		return rc;
 	via_config_fifo(pdev, config->flags);
 	if (config->udma_mask == ATA_UDMA4) {
 		/* The 66 MHz devices require we enable the clock */
 		pci_read_config_dword(pdev, 0x50, &timing);
 		timing |= 0x80008;
 		pci_write_config_dword(pdev, 0x50, timing);
 	}
 	if (config->flags & VIA_BAD_CLK66) {
 		/* Disable the 66MHz clock on problem devices */
 		pci_read_config_dword(pdev, 0x50, &timing);
 		timing &= ~0x80008;
 		pci_write_config_dword(pdev, 0x50, timing);
 	}
 	ata_host_resume(host);
 	return 0;
 }
 #endif
 static const struct pci_device_id via[] = {
 	{ PCI_VDEVICE(VIA, 0x0415), },
 	{ PCI_VDEVICE(VIA, 0x0571), },
 	{ PCI_VDEVICE(VIA, 0x0581), },
 	{ PCI_VDEVICE(VIA, 0x1571), },
 	{ PCI_VDEVICE(VIA, 0x3164), },
 	{ PCI_VDEVICE(VIA, 0x5324), },
 	{ PCI_VDEVICE(VIA, 0xC409), VIA_IDFLAG_SINGLE },
 	{ PCI_VDEVICE(VIA, 0x9001), VIA_IDFLAG_SINGLE },
 	{ },
 };
 static struct pci_driver via_pci_driver = {
 	.name 		= DRV_NAME,
 	.id_table	= via,
 	.probe 		= via_init_one,
 	.remove		= ata_pci_remove_one,
 #ifdef CONFIG_PM
 	.suspend	= ata_pci_device_suspend,
 	.resume		= via_reinit_one,
 #endif
 };
 static int __init via_init(void)
 {
 	return pci_register_driver(&via_pci_driver);
 }
 static void __exit via_exit(void)
 {
 	pci_unregister_driver(&via_pci_driver);
 }
 MODULE_AUTHOR("Alan Cox");
 MODULE_DESCRIPTION("low-level driver for VIA PATA");
 MODULE_LICENSE("GPL");
 MODULE_DEVICE_TABLE(pci, via);
 MODULE_VERSION(DRV_VERSION);
 module_init(via_init);
 module_exit(via_exit);

drivers/ata/sata_mv.c

Diff comments View file @ df423dc

1	/*	1	/*
2	* sata_mv.c - Marvell SATA support	2	* sata_mv.c - Marvell SATA support
3	*	3	*
4	* Copyright 2008-2009: Marvell Corporation, all rights reserved.	4	* Copyright 2008-2009: Marvell Corporation, all rights reserved.
5	* Copyright 2005: EMC Corporation, all rights reserved.	5	* Copyright 2005: EMC Corporation, all rights reserved.
6	* Copyright 2005 Red Hat, Inc. All rights reserved.	6	* Copyright 2005 Red Hat, Inc. All rights reserved.
7	*	7	*
8	* Originally written by Brett Russ.	8	* Originally written by Brett Russ.
9	* Extensive overhaul and enhancement by Mark Lord <mlord@pobox.com>.	9	* Extensive overhaul and enhancement by Mark Lord <mlord@pobox.com>.
10	*	10	*
11	* Please ALWAYS copy linux-ide@vger.kernel.org on emails.	11	* Please ALWAYS copy linux-ide@vger.kernel.org on emails.
12	*	12	*
13	* This program is free software; you can redistribute it and/or modify	13	* This program is free software; you can redistribute it and/or modify
14	* it under the terms of the GNU General Public License as published by	14	* it under the terms of the GNU General Public License as published by
15	* the Free Software Foundation; version 2 of the License.	15	* the Free Software Foundation; version 2 of the License.
16	*	16	*
17	* This program is distributed in the hope that it will be useful,	17	* This program is distributed in the hope that it will be useful,
18	* but WITHOUT ANY WARRANTY; without even the implied warranty of	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20	* GNU General Public License for more details.	20	* GNU General Public License for more details.
21	*	21	*
22	* You should have received a copy of the GNU General Public License	22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, write to the Free Software	23	* along with this program; if not, write to the Free Software
24	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA	24	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25	*	25	*
26	*/	26	*/
27		27
28	/*	28	/*
29	* sata_mv TODO list:	29	* sata_mv TODO list:
30	*	30	*
31	* --> Develop a low-power-consumption strategy, and implement it.	31	* --> Develop a low-power-consumption strategy, and implement it.
32	*	32	*
33	* --> Add sysfs attributes for per-chip / per-HC IRQ coalescing thresholds.	33	* --> Add sysfs attributes for per-chip / per-HC IRQ coalescing thresholds.
34	*	34	*
35	* --> [Experiment, Marvell value added] Is it possible to use target	35	* --> [Experiment, Marvell value added] Is it possible to use target
36	* mode to cross-connect two Linux boxes with Marvell cards? If so,	36	* mode to cross-connect two Linux boxes with Marvell cards? If so,
37	* creating LibATA target mode support would be very interesting.	37	* creating LibATA target mode support would be very interesting.
38	*	38	*
39	* Target mode, for those without docs, is the ability to directly	39	* Target mode, for those without docs, is the ability to directly
40	* connect two SATA ports.	40	* connect two SATA ports.
41	*/	41	*/
42		42
43	/*	43	/*
44	* 80x1-B2 errata PCI#11:	44	* 80x1-B2 errata PCI#11:
45	*	45	*
46	* Users of the 6041/6081 Rev.B2 chips (current is C0)	46	* Users of the 6041/6081 Rev.B2 chips (current is C0)
47	* should be careful to insert those cards only onto PCI-X bus #0,	47	* should be careful to insert those cards only onto PCI-X bus #0,
48	* and only in device slots 0..7, not higher. The chips may not	48	* and only in device slots 0..7, not higher. The chips may not
49	* work correctly otherwise (note: this is a pretty rare condition).	49	* work correctly otherwise (note: this is a pretty rare condition).
50	*/	50	*/
51		51
52	#include <linux/kernel.h>	52	#include <linux/kernel.h>
53	#include <linux/module.h>	53	#include <linux/module.h>
54	#include <linux/pci.h>	54	#include <linux/pci.h>
55	#include <linux/init.h>	55	#include <linux/init.h>
56	#include <linux/blkdev.h>	56	#include <linux/blkdev.h>
57	#include <linux/delay.h>	57	#include <linux/delay.h>
58	#include <linux/interrupt.h>	58	#include <linux/interrupt.h>
59	#include <linux/dmapool.h>	59	#include <linux/dmapool.h>
60	#include <linux/dma-mapping.h>	60	#include <linux/dma-mapping.h>
61	#include <linux/device.h>	61	#include <linux/device.h>
62	#include <linux/clk.h>	62	#include <linux/clk.h>
63	#include <linux/platform_device.h>	63	#include <linux/platform_device.h>
64	#include <linux/ata_platform.h>	64	#include <linux/ata_platform.h>
65	#include <linux/mbus.h>	65	#include <linux/mbus.h>
66	#include <linux/bitops.h>	66	#include <linux/bitops.h>
67	#include <linux/gfp.h>	67	#include <linux/gfp.h>
68	#include <scsi/scsi_host.h>	68	#include <scsi/scsi_host.h>
69	#include <scsi/scsi_cmnd.h>	69	#include <scsi/scsi_cmnd.h>
70	#include <scsi/scsi_device.h>	70	#include <scsi/scsi_device.h>
71	#include <linux/libata.h>	71	#include <linux/libata.h>
72		72
73	#define DRV_NAME "sata_mv"	73	#define DRV_NAME "sata_mv"
74	#define DRV_VERSION "1.28"	74	#define DRV_VERSION "1.28"
75		75
76	/*	76	/*
77	* module options	77	* module options
78	*/	78	*/
79		79
80	static int msi;	80	static int msi;
81	#ifdef CONFIG_PCI	81	#ifdef CONFIG_PCI
82	module_param(msi, int, S_IRUGO);	82	module_param(msi, int, S_IRUGO);
83	MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");	83	MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
84	#endif	84	#endif
85		85
86	static int irq_coalescing_io_count;	86	static int irq_coalescing_io_count;
87	module_param(irq_coalescing_io_count, int, S_IRUGO);	87	module_param(irq_coalescing_io_count, int, S_IRUGO);
88	MODULE_PARM_DESC(irq_coalescing_io_count,	88	MODULE_PARM_DESC(irq_coalescing_io_count,
89	"IRQ coalescing I/O count threshold (0..255)");	89	"IRQ coalescing I/O count threshold (0..255)");
90		90
91	static int irq_coalescing_usecs;	91	static int irq_coalescing_usecs;
92	module_param(irq_coalescing_usecs, int, S_IRUGO);	92	module_param(irq_coalescing_usecs, int, S_IRUGO);
93	MODULE_PARM_DESC(irq_coalescing_usecs,	93	MODULE_PARM_DESC(irq_coalescing_usecs,
94	"IRQ coalescing time threshold in usecs");	94	"IRQ coalescing time threshold in usecs");
95		95
96	enum {	96	enum {
97	/* BAR's are enumerated in terms of pci_resource_start() terms */	97	/* BAR's are enumerated in terms of pci_resource_start() terms */
98	MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */	98	MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
99	MV_IO_BAR = 2, /* offset 0x18: IO space */	99	MV_IO_BAR = 2, /* offset 0x18: IO space */
100	MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */	100	MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
101		101
102	MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */	102	MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
103	MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */	103	MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
104		104
105	/* For use with both IRQ coalescing methods ("all ports" or "per-HC" */	105	/* For use with both IRQ coalescing methods ("all ports" or "per-HC" */
106	COAL_CLOCKS_PER_USEC = 150, /* for calculating COAL_TIMEs */	106	COAL_CLOCKS_PER_USEC = 150, /* for calculating COAL_TIMEs */
107	MAX_COAL_TIME_THRESHOLD = ((1 << 24) - 1), /* internal clocks count */	107	MAX_COAL_TIME_THRESHOLD = ((1 << 24) - 1), /* internal clocks count */
108	MAX_COAL_IO_COUNT = 255, /* completed I/O count */	108	MAX_COAL_IO_COUNT = 255, /* completed I/O count */
109		109
110	MV_PCI_REG_BASE = 0,	110	MV_PCI_REG_BASE = 0,
111		111
112	/*	112	/*
113	* Per-chip ("all ports") interrupt coalescing feature.	113	* Per-chip ("all ports") interrupt coalescing feature.
114	* This is only for GEN_II / GEN_IIE hardware.	114	* This is only for GEN_II / GEN_IIE hardware.
115	*	115	*
116	* Coalescing defers the interrupt until either the IO_THRESHOLD	116	* Coalescing defers the interrupt until either the IO_THRESHOLD
117	* (count of completed I/Os) is met, or the TIME_THRESHOLD is met.	117	* (count of completed I/Os) is met, or the TIME_THRESHOLD is met.
118	*/	118	*/
119	COAL_REG_BASE = 0x18000,	119	COAL_REG_BASE = 0x18000,
120	IRQ_COAL_CAUSE = (COAL_REG_BASE + 0x08),	120	IRQ_COAL_CAUSE = (COAL_REG_BASE + 0x08),
121	ALL_PORTS_COAL_IRQ = (1 << 4), /* all ports irq event */	121	ALL_PORTS_COAL_IRQ = (1 << 4), /* all ports irq event */
122		122
123	IRQ_COAL_IO_THRESHOLD = (COAL_REG_BASE + 0xcc),	123	IRQ_COAL_IO_THRESHOLD = (COAL_REG_BASE + 0xcc),
124	IRQ_COAL_TIME_THRESHOLD = (COAL_REG_BASE + 0xd0),	124	IRQ_COAL_TIME_THRESHOLD = (COAL_REG_BASE + 0xd0),
125		125
126	/*	126	/*
127	* Registers for the (unused here) transaction coalescing feature:	127	* Registers for the (unused here) transaction coalescing feature:
128	*/	128	*/
129	TRAN_COAL_CAUSE_LO = (COAL_REG_BASE + 0x88),	129	TRAN_COAL_CAUSE_LO = (COAL_REG_BASE + 0x88),
130	TRAN_COAL_CAUSE_HI = (COAL_REG_BASE + 0x8c),	130	TRAN_COAL_CAUSE_HI = (COAL_REG_BASE + 0x8c),
131		131
132	SATAHC0_REG_BASE = 0x20000,	132	SATAHC0_REG_BASE = 0x20000,
133	FLASH_CTL = 0x1046c,	133	FLASH_CTL = 0x1046c,
134	GPIO_PORT_CTL = 0x104f0,	134	GPIO_PORT_CTL = 0x104f0,
135	RESET_CFG = 0x180d8,	135	RESET_CFG = 0x180d8,
136		136
137	MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,	137	MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
138	MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,	138	MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
139	MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */	139	MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
140	MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,	140	MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
141		141
142	MV_MAX_Q_DEPTH = 32,	142	MV_MAX_Q_DEPTH = 32,
143	MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,	143	MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
144		144
145	/* CRQB needs alignment on a 1KB boundary. Size == 1KB	145	/* CRQB needs alignment on a 1KB boundary. Size == 1KB
146	* CRPB needs alignment on a 256B boundary. Size == 256B	146	* CRPB needs alignment on a 256B boundary. Size == 256B
147	* ePRD (SG) entries need alignment on a 16B boundary. Size == 16B	147	* ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
148	*/	148	*/
149	MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),	149	MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
150	MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),	150	MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
151	MV_MAX_SG_CT = 256,	151	MV_MAX_SG_CT = 256,
152	MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),	152	MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
153		153
154	/* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */	154	/* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */
155	MV_PORT_HC_SHIFT = 2,	155	MV_PORT_HC_SHIFT = 2,
156	MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */	156	MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */
157	/* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */	157	/* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */
158	MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */	158	MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */
159		159
160	/* Host Flags */	160	/* Host Flags */
161	MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */	161	MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
162		162
163	MV_COMMON_FLAGS = ATA_FLAG_SATA \| ATA_FLAG_NO_LEGACY \|	163	MV_COMMON_FLAGS = ATA_FLAG_SATA \| ATA_FLAG_NO_LEGACY \|
164	ATA_FLAG_MMIO \| ATA_FLAG_PIO_POLLING,	164	ATA_FLAG_MMIO \| ATA_FLAG_PIO_POLLING,
165		165
166	MV_GEN_I_FLAGS = MV_COMMON_FLAGS \| ATA_FLAG_NO_ATAPI,	166	MV_GEN_I_FLAGS = MV_COMMON_FLAGS \| ATA_FLAG_NO_ATAPI,
167		167
168	MV_GEN_II_FLAGS = MV_COMMON_FLAGS \| ATA_FLAG_NCQ \|	168	MV_GEN_II_FLAGS = MV_COMMON_FLAGS \| ATA_FLAG_NCQ \|
169	ATA_FLAG_PMP \| ATA_FLAG_ACPI_SATA,	169	ATA_FLAG_PMP \| ATA_FLAG_ACPI_SATA,
170		170
171	MV_GEN_IIE_FLAGS = MV_GEN_II_FLAGS \| ATA_FLAG_AN,	171	MV_GEN_IIE_FLAGS = MV_GEN_II_FLAGS \| ATA_FLAG_AN,
172		172
173	CRQB_FLAG_READ = (1 << 0),	173	CRQB_FLAG_READ = (1 << 0),
174	CRQB_TAG_SHIFT = 1,	174	CRQB_TAG_SHIFT = 1,
175	CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */	175	CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */
176	CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */	176	CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */
177	CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */	177	CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */
178	CRQB_CMD_ADDR_SHIFT = 8,	178	CRQB_CMD_ADDR_SHIFT = 8,
179	CRQB_CMD_CS = (0x2 << 11),	179	CRQB_CMD_CS = (0x2 << 11),
180	CRQB_CMD_LAST = (1 << 15),	180	CRQB_CMD_LAST = (1 << 15),
181		181
182	CRPB_FLAG_STATUS_SHIFT = 8,	182	CRPB_FLAG_STATUS_SHIFT = 8,
183	CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */	183	CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */
184	CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */	184	CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */
185		185
186	EPRD_FLAG_END_OF_TBL = (1 << 31),	186	EPRD_FLAG_END_OF_TBL = (1 << 31),
187		187
188	/* PCI interface registers */	188	/* PCI interface registers */
189		189
190	MV_PCI_COMMAND = 0xc00,	190	MV_PCI_COMMAND = 0xc00,
191	MV_PCI_COMMAND_MWRCOM = (1 << 4), /* PCI Master Write Combining */	191	MV_PCI_COMMAND_MWRCOM = (1 << 4), /* PCI Master Write Combining */
192	MV_PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */	192	MV_PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */
193		193
194	PCI_MAIN_CMD_STS = 0xd30,	194	PCI_MAIN_CMD_STS = 0xd30,
195	STOP_PCI_MASTER = (1 << 2),	195	STOP_PCI_MASTER = (1 << 2),
196	PCI_MASTER_EMPTY = (1 << 3),	196	PCI_MASTER_EMPTY = (1 << 3),
197	GLOB_SFT_RST = (1 << 4),	197	GLOB_SFT_RST = (1 << 4),
198		198
199	MV_PCI_MODE = 0xd00,	199	MV_PCI_MODE = 0xd00,
200	MV_PCI_MODE_MASK = 0x30,	200	MV_PCI_MODE_MASK = 0x30,
201		201
202	MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,	202	MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
203	MV_PCI_DISC_TIMER = 0xd04,	203	MV_PCI_DISC_TIMER = 0xd04,
204	MV_PCI_MSI_TRIGGER = 0xc38,	204	MV_PCI_MSI_TRIGGER = 0xc38,
205	MV_PCI_SERR_MASK = 0xc28,	205	MV_PCI_SERR_MASK = 0xc28,
206	MV_PCI_XBAR_TMOUT = 0x1d04,	206	MV_PCI_XBAR_TMOUT = 0x1d04,
207	MV_PCI_ERR_LOW_ADDRESS = 0x1d40,	207	MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
208	MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,	208	MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
209	MV_PCI_ERR_ATTRIBUTE = 0x1d48,	209	MV_PCI_ERR_ATTRIBUTE = 0x1d48,
210	MV_PCI_ERR_COMMAND = 0x1d50,	210	MV_PCI_ERR_COMMAND = 0x1d50,
211		211
212	PCI_IRQ_CAUSE = 0x1d58,	212	PCI_IRQ_CAUSE = 0x1d58,
213	PCI_IRQ_MASK = 0x1d5c,	213	PCI_IRQ_MASK = 0x1d5c,
214	PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */	214	PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
215		215
216	PCIE_IRQ_CAUSE = 0x1900,	216	PCIE_IRQ_CAUSE = 0x1900,
217	PCIE_IRQ_MASK = 0x1910,	217	PCIE_IRQ_MASK = 0x1910,
218	PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */	218	PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */
219		219
220	/* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */	220	/* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */
221	PCI_HC_MAIN_IRQ_CAUSE = 0x1d60,	221	PCI_HC_MAIN_IRQ_CAUSE = 0x1d60,
222	PCI_HC_MAIN_IRQ_MASK = 0x1d64,	222	PCI_HC_MAIN_IRQ_MASK = 0x1d64,
223	SOC_HC_MAIN_IRQ_CAUSE = 0x20020,	223	SOC_HC_MAIN_IRQ_CAUSE = 0x20020,
224	SOC_HC_MAIN_IRQ_MASK = 0x20024,	224	SOC_HC_MAIN_IRQ_MASK = 0x20024,
225	ERR_IRQ = (1 << 0), /* shift by (2 * port #) */	225	ERR_IRQ = (1 << 0), /* shift by (2 * port #) */
226	DONE_IRQ = (1 << 1), /* shift by (2 * port #) */	226	DONE_IRQ = (1 << 1), /* shift by (2 * port #) */
227	HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */	227	HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
228	HC_SHIFT = 9, /* bits 9-17 = HC1's ports */	228	HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
229	DONE_IRQ_0_3 = 0x000000aa, /* DONE_IRQ ports 0,1,2,3 */	229	DONE_IRQ_0_3 = 0x000000aa, /* DONE_IRQ ports 0,1,2,3 */
230	DONE_IRQ_4_7 = (DONE_IRQ_0_3 << HC_SHIFT), /* 4,5,6,7 */	230	DONE_IRQ_4_7 = (DONE_IRQ_0_3 << HC_SHIFT), /* 4,5,6,7 */
231	PCI_ERR = (1 << 18),	231	PCI_ERR = (1 << 18),
232	TRAN_COAL_LO_DONE = (1 << 19), /* transaction coalescing */	232	TRAN_COAL_LO_DONE = (1 << 19), /* transaction coalescing */
233	TRAN_COAL_HI_DONE = (1 << 20), /* transaction coalescing */	233	TRAN_COAL_HI_DONE = (1 << 20), /* transaction coalescing */
234	PORTS_0_3_COAL_DONE = (1 << 8), /* HC0 IRQ coalescing */	234	PORTS_0_3_COAL_DONE = (1 << 8), /* HC0 IRQ coalescing */
235	PORTS_4_7_COAL_DONE = (1 << 17), /* HC1 IRQ coalescing */	235	PORTS_4_7_COAL_DONE = (1 << 17), /* HC1 IRQ coalescing */
236	ALL_PORTS_COAL_DONE = (1 << 21), /* GEN_II(E) IRQ coalescing */	236	ALL_PORTS_COAL_DONE = (1 << 21), /* GEN_II(E) IRQ coalescing */
237	GPIO_INT = (1 << 22),	237	GPIO_INT = (1 << 22),
238	SELF_INT = (1 << 23),	238	SELF_INT = (1 << 23),
239	TWSI_INT = (1 << 24),	239	TWSI_INT = (1 << 24),
240	HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */	240	HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
241	HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */	241	HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */
242	HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */	242	HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */
243		243
244	/* SATAHC registers */	244	/* SATAHC registers */
245	HC_CFG = 0x00,	245	HC_CFG = 0x00,
246		246
247	HC_IRQ_CAUSE = 0x14,	247	HC_IRQ_CAUSE = 0x14,
248	DMA_IRQ = (1 << 0), /* shift by port # */	248	DMA_IRQ = (1 << 0), /* shift by port # */
249	HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */	249	HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */
250	DEV_IRQ = (1 << 8), /* shift by port # */	250	DEV_IRQ = (1 << 8), /* shift by port # */
251		251
252	/*	252	/*
253	* Per-HC (Host-Controller) interrupt coalescing feature.	253	* Per-HC (Host-Controller) interrupt coalescing feature.
254	* This is present on all chip generations.	254	* This is present on all chip generations.
255	*	255	*
256	* Coalescing defers the interrupt until either the IO_THRESHOLD	256	* Coalescing defers the interrupt until either the IO_THRESHOLD
257	* (count of completed I/Os) is met, or the TIME_THRESHOLD is met.	257	* (count of completed I/Os) is met, or the TIME_THRESHOLD is met.
258	*/	258	*/
259	HC_IRQ_COAL_IO_THRESHOLD = 0x000c,	259	HC_IRQ_COAL_IO_THRESHOLD = 0x000c,
260	HC_IRQ_COAL_TIME_THRESHOLD = 0x0010,	260	HC_IRQ_COAL_TIME_THRESHOLD = 0x0010,
261		261
262	SOC_LED_CTRL = 0x2c,	262	SOC_LED_CTRL = 0x2c,
263	SOC_LED_CTRL_BLINK = (1 << 0), /* Active LED blink */	263	SOC_LED_CTRL_BLINK = (1 << 0), /* Active LED blink */
264	SOC_LED_CTRL_ACT_PRESENCE = (1 << 2), /* Multiplex dev presence */	264	SOC_LED_CTRL_ACT_PRESENCE = (1 << 2), /* Multiplex dev presence */
265	/* with dev activity LED */	265	/* with dev activity LED */
266		266
267	/* Shadow block registers */	267	/* Shadow block registers */
268	SHD_BLK = 0x100,	268	SHD_BLK = 0x100,
269	SHD_CTL_AST = 0x20, /* ofs from SHD_BLK */	269	SHD_CTL_AST = 0x20, /* ofs from SHD_BLK */
270		270
271	/* SATA registers */	271	/* SATA registers */
272	SATA_STATUS = 0x300, /* ctrl, err regs follow status */	272	SATA_STATUS = 0x300, /* ctrl, err regs follow status */
273	SATA_ACTIVE = 0x350,	273	SATA_ACTIVE = 0x350,
274	FIS_IRQ_CAUSE = 0x364,	274	FIS_IRQ_CAUSE = 0x364,
275	FIS_IRQ_CAUSE_AN = (1 << 9), /* async notification */	275	FIS_IRQ_CAUSE_AN = (1 << 9), /* async notification */
276		276
277	LTMODE = 0x30c, /* requires read-after-write */	277	LTMODE = 0x30c, /* requires read-after-write */
278	LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */	278	LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */
279		279
280	PHY_MODE2 = 0x330,	280	PHY_MODE2 = 0x330,
281	PHY_MODE3 = 0x310,	281	PHY_MODE3 = 0x310,
282		282
283	PHY_MODE4 = 0x314, /* requires read-after-write */	283	PHY_MODE4 = 0x314, /* requires read-after-write */
284	PHY_MODE4_CFG_MASK = 0x00000003, /* phy internal config field */	284	PHY_MODE4_CFG_MASK = 0x00000003, /* phy internal config field */
285	PHY_MODE4_CFG_VALUE = 0x00000001, /* phy internal config field */	285	PHY_MODE4_CFG_VALUE = 0x00000001, /* phy internal config field */
286	PHY_MODE4_RSVD_ZEROS = 0x5de3fffa, /* Gen2e always write zeros */	286	PHY_MODE4_RSVD_ZEROS = 0x5de3fffa, /* Gen2e always write zeros */
287	PHY_MODE4_RSVD_ONES = 0x00000005, /* Gen2e always write ones */	287	PHY_MODE4_RSVD_ONES = 0x00000005, /* Gen2e always write ones */
288		288
289	SATA_IFCTL = 0x344,	289	SATA_IFCTL = 0x344,
290	SATA_TESTCTL = 0x348,	290	SATA_TESTCTL = 0x348,
291	SATA_IFSTAT = 0x34c,	291	SATA_IFSTAT = 0x34c,
292	VENDOR_UNIQUE_FIS = 0x35c,	292	VENDOR_UNIQUE_FIS = 0x35c,
293		293
294	FISCFG = 0x360,	294	FISCFG = 0x360,
295	FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */	295	FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */
296	FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */	296	FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */
297		297
298	PHY_MODE9_GEN2 = 0x398,	298	PHY_MODE9_GEN2 = 0x398,
299	PHY_MODE9_GEN1 = 0x39c,	299	PHY_MODE9_GEN1 = 0x39c,
300	PHYCFG_OFS = 0x3a0, /* only in 65n devices */	300	PHYCFG_OFS = 0x3a0, /* only in 65n devices */
301		301
302	MV5_PHY_MODE = 0x74,	302	MV5_PHY_MODE = 0x74,
303	MV5_LTMODE = 0x30,	303	MV5_LTMODE = 0x30,
304	MV5_PHY_CTL = 0x0C,	304	MV5_PHY_CTL = 0x0C,
305	SATA_IFCFG = 0x050,	305	SATA_IFCFG = 0x050,
306		306
307	MV_M2_PREAMP_MASK = 0x7e0,	307	MV_M2_PREAMP_MASK = 0x7e0,
308		308
309	/* Port registers */	309	/* Port registers */
310	EDMA_CFG = 0,	310	EDMA_CFG = 0,
311	EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */	311	EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */
312	EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */	312	EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */
313	EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */	313	EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
314	EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */	314	EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
315	EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */	315	EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
316	EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */	316	EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */
317	EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */	317	EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */
318		318
319	EDMA_ERR_IRQ_CAUSE = 0x8,	319	EDMA_ERR_IRQ_CAUSE = 0x8,
320	EDMA_ERR_IRQ_MASK = 0xc,	320	EDMA_ERR_IRQ_MASK = 0xc,
321	EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */	321	EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */
322	EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */	322	EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */
323	EDMA_ERR_DEV = (1 << 2), /* device error */	323	EDMA_ERR_DEV = (1 << 2), /* device error */
324	EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */	324	EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */
325	EDMA_ERR_DEV_CON = (1 << 4), /* device connected */	325	EDMA_ERR_DEV_CON = (1 << 4), /* device connected */
326	EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */	326	EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */
327	EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */	327	EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */
328	EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */	328	EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */
329	EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */	329	EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */
330	EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */	330	EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */
331	EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */	331	EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */
332	EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */	332	EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */
333	EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */	333	EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */
334	EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */	334	EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */
335		335
336	EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */	336	EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */
337	EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */	337	EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */
338	EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */	338	EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */
339	EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */	339	EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */
340	EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */	340	EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */
341		341
342	EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */	342	EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */
343		343
344	EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */	344	EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */
345	EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */	345	EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */
346	EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */	346	EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */
347	EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */	347	EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */
348	EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */	348	EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */
349	EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */	349	EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */
350		350
351	EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */	351	EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */
352		352
353	EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */	353	EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */
354	EDMA_ERR_OVERRUN_5 = (1 << 5),	354	EDMA_ERR_OVERRUN_5 = (1 << 5),
355	EDMA_ERR_UNDERRUN_5 = (1 << 6),	355	EDMA_ERR_UNDERRUN_5 = (1 << 6),
356		356
357	EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 \|	357	EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 \|
358	EDMA_ERR_LNK_CTRL_RX_1 \|	358	EDMA_ERR_LNK_CTRL_RX_1 \|
359	EDMA_ERR_LNK_CTRL_RX_3 \|	359	EDMA_ERR_LNK_CTRL_RX_3 \|
360	EDMA_ERR_LNK_CTRL_TX,	360	EDMA_ERR_LNK_CTRL_TX,
361		361
362	EDMA_EH_FREEZE = EDMA_ERR_D_PAR \|	362	EDMA_EH_FREEZE = EDMA_ERR_D_PAR \|
363	EDMA_ERR_PRD_PAR \|	363	EDMA_ERR_PRD_PAR \|
364	EDMA_ERR_DEV_DCON \|	364	EDMA_ERR_DEV_DCON \|
365	EDMA_ERR_DEV_CON \|	365	EDMA_ERR_DEV_CON \|
366	EDMA_ERR_SERR \|	366	EDMA_ERR_SERR \|
367	EDMA_ERR_SELF_DIS \|	367	EDMA_ERR_SELF_DIS \|
368	EDMA_ERR_CRQB_PAR \|	368	EDMA_ERR_CRQB_PAR \|
369	EDMA_ERR_CRPB_PAR \|	369	EDMA_ERR_CRPB_PAR \|
370	EDMA_ERR_INTRL_PAR \|	370	EDMA_ERR_INTRL_PAR \|
371	EDMA_ERR_IORDY \|	371	EDMA_ERR_IORDY \|
372	EDMA_ERR_LNK_CTRL_RX_2 \|	372	EDMA_ERR_LNK_CTRL_RX_2 \|
373	EDMA_ERR_LNK_DATA_RX \|	373	EDMA_ERR_LNK_DATA_RX \|
374	EDMA_ERR_LNK_DATA_TX \|	374	EDMA_ERR_LNK_DATA_TX \|
375	EDMA_ERR_TRANS_PROTO,	375	EDMA_ERR_TRANS_PROTO,
376		376
377	EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR \|	377	EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR \|
378	EDMA_ERR_PRD_PAR \|	378	EDMA_ERR_PRD_PAR \|
379	EDMA_ERR_DEV_DCON \|	379	EDMA_ERR_DEV_DCON \|
380	EDMA_ERR_DEV_CON \|	380	EDMA_ERR_DEV_CON \|
381	EDMA_ERR_OVERRUN_5 \|	381	EDMA_ERR_OVERRUN_5 \|
382	EDMA_ERR_UNDERRUN_5 \|	382	EDMA_ERR_UNDERRUN_5 \|
383	EDMA_ERR_SELF_DIS_5 \|	383	EDMA_ERR_SELF_DIS_5 \|
384	EDMA_ERR_CRQB_PAR \|	384	EDMA_ERR_CRQB_PAR \|
385	EDMA_ERR_CRPB_PAR \|	385	EDMA_ERR_CRPB_PAR \|
386	EDMA_ERR_INTRL_PAR \|	386	EDMA_ERR_INTRL_PAR \|
387	EDMA_ERR_IORDY,	387	EDMA_ERR_IORDY,
388		388
389	EDMA_REQ_Q_BASE_HI = 0x10,	389	EDMA_REQ_Q_BASE_HI = 0x10,
390	EDMA_REQ_Q_IN_PTR = 0x14, /* also contains BASE_LO */	390	EDMA_REQ_Q_IN_PTR = 0x14, /* also contains BASE_LO */
391		391
392	EDMA_REQ_Q_OUT_PTR = 0x18,	392	EDMA_REQ_Q_OUT_PTR = 0x18,
393	EDMA_REQ_Q_PTR_SHIFT = 5,	393	EDMA_REQ_Q_PTR_SHIFT = 5,
394		394
395	EDMA_RSP_Q_BASE_HI = 0x1c,	395	EDMA_RSP_Q_BASE_HI = 0x1c,
396	EDMA_RSP_Q_IN_PTR = 0x20,	396	EDMA_RSP_Q_IN_PTR = 0x20,
397	EDMA_RSP_Q_OUT_PTR = 0x24, /* also contains BASE_LO */	397	EDMA_RSP_Q_OUT_PTR = 0x24, /* also contains BASE_LO */
398	EDMA_RSP_Q_PTR_SHIFT = 3,	398	EDMA_RSP_Q_PTR_SHIFT = 3,
399		399
400	EDMA_CMD = 0x28, /* EDMA command register */	400	EDMA_CMD = 0x28, /* EDMA command register */
401	EDMA_EN = (1 << 0), /* enable EDMA */	401	EDMA_EN = (1 << 0), /* enable EDMA */
402	EDMA_DS = (1 << 1), /* disable EDMA; self-negated */	402	EDMA_DS = (1 << 1), /* disable EDMA; self-negated */
403	EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */	403	EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */
404		404
405	EDMA_STATUS = 0x30, /* EDMA engine status */	405	EDMA_STATUS = 0x30, /* EDMA engine status */
406	EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */	406	EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */
407	EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */	407	EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */
408		408
409	EDMA_IORDY_TMOUT = 0x34,	409	EDMA_IORDY_TMOUT = 0x34,
410	EDMA_ARB_CFG = 0x38,	410	EDMA_ARB_CFG = 0x38,
411		411
412	EDMA_HALTCOND = 0x60, /* GenIIe halt conditions */	412	EDMA_HALTCOND = 0x60, /* GenIIe halt conditions */
413	EDMA_UNKNOWN_RSVD = 0x6C, /* GenIIe unknown/reserved */	413	EDMA_UNKNOWN_RSVD = 0x6C, /* GenIIe unknown/reserved */
414		414
415	BMDMA_CMD = 0x224, /* bmdma command register */	415	BMDMA_CMD = 0x224, /* bmdma command register */
416	BMDMA_STATUS = 0x228, /* bmdma status register */	416	BMDMA_STATUS = 0x228, /* bmdma status register */
417	BMDMA_PRD_LOW = 0x22c, /* bmdma PRD addr 31:0 */	417	BMDMA_PRD_LOW = 0x22c, /* bmdma PRD addr 31:0 */
418	BMDMA_PRD_HIGH = 0x230, /* bmdma PRD addr 63:32 */	418	BMDMA_PRD_HIGH = 0x230, /* bmdma PRD addr 63:32 */
419		419
420	/* Host private flags (hp_flags) */	420	/* Host private flags (hp_flags) */
421	MV_HP_FLAG_MSI = (1 << 0),	421	MV_HP_FLAG_MSI = (1 << 0),
422	MV_HP_ERRATA_50XXB0 = (1 << 1),	422	MV_HP_ERRATA_50XXB0 = (1 << 1),
423	MV_HP_ERRATA_50XXB2 = (1 << 2),	423	MV_HP_ERRATA_50XXB2 = (1 << 2),
424	MV_HP_ERRATA_60X1B2 = (1 << 3),	424	MV_HP_ERRATA_60X1B2 = (1 << 3),
425	MV_HP_ERRATA_60X1C0 = (1 << 4),	425	MV_HP_ERRATA_60X1C0 = (1 << 4),
426	MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */	426	MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */
427	MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */	427	MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */
428	MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */	428	MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */
429	MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */	429	MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */
430	MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */	430	MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */
431	MV_HP_FLAG_SOC = (1 << 11), /* SystemOnChip, no PCI */	431	MV_HP_FLAG_SOC = (1 << 11), /* SystemOnChip, no PCI */
432	MV_HP_QUIRK_LED_BLINK_EN = (1 << 12), /* is led blinking enabled? */	432	MV_HP_QUIRK_LED_BLINK_EN = (1 << 12), /* is led blinking enabled? */
433		433
434	/* Port private flags (pp_flags) */	434	/* Port private flags (pp_flags) */
435	MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */	435	MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */
436	MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */	436	MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */
437	MV_PP_FLAG_FBS_EN = (1 << 2), /* is EDMA set up for FBS? */	437	MV_PP_FLAG_FBS_EN = (1 << 2), /* is EDMA set up for FBS? */
438	MV_PP_FLAG_DELAYED_EH = (1 << 3), /* delayed dev err handling */	438	MV_PP_FLAG_DELAYED_EH = (1 << 3), /* delayed dev err handling */
439	MV_PP_FLAG_FAKE_ATA_BUSY = (1 << 4), /* ignore initial ATA_DRDY */	439	MV_PP_FLAG_FAKE_ATA_BUSY = (1 << 4), /* ignore initial ATA_DRDY */
440	};	440	};
441		441
442	#define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)	442	#define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)
443	#define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)	443	#define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)
444	#define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)	444	#define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
445	#define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE)	445	#define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE)
446	#define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC)	446	#define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC)
447		447
448	#define WINDOW_CTRL(i) (0x20030 + ((i) << 4))	448	#define WINDOW_CTRL(i) (0x20030 + ((i) << 4))
449	#define WINDOW_BASE(i) (0x20034 + ((i) << 4))	449	#define WINDOW_BASE(i) (0x20034 + ((i) << 4))
450		450
451	enum {	451	enum {
452	/* DMA boundary 0xffff is required by the s/g splitting	452	/* DMA boundary 0xffff is required by the s/g splitting
453	* we need on /length/ in mv_fill-sg().	453	* we need on /length/ in mv_fill-sg().
454	*/	454	*/
455	MV_DMA_BOUNDARY = 0xffffU,	455	MV_DMA_BOUNDARY = 0xffffU,
456		456
457	/* mask of register bits containing lower 32 bits	457	/* mask of register bits containing lower 32 bits
458	* of EDMA request queue DMA address	458	* of EDMA request queue DMA address
459	*/	459	*/
460	EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,	460	EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
461		461
462	/* ditto, for response queue */	462	/* ditto, for response queue */
463	EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,	463	EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
464	};	464	};
465		465
466	enum chip_type {	466	enum chip_type {
467	chip_504x,	467	chip_504x,
468	chip_508x,	468	chip_508x,
469	chip_5080,	469	chip_5080,
470	chip_604x,	470	chip_604x,
471	chip_608x,	471	chip_608x,
472	chip_6042,	472	chip_6042,
473	chip_7042,	473	chip_7042,
474	chip_soc,	474	chip_soc,
475	};	475	};
476		476
477	/* Command ReQuest Block: 32B */	477	/* Command ReQuest Block: 32B */
478	struct mv_crqb {	478	struct mv_crqb {
479	__le32 sg_addr;	479	__le32 sg_addr;
480	__le32 sg_addr_hi;	480	__le32 sg_addr_hi;
481	__le16 ctrl_flags;	481	__le16 ctrl_flags;
482	__le16 ata_cmd[11];	482	__le16 ata_cmd[11];
483	};	483	};
484		484
485	struct mv_crqb_iie {	485	struct mv_crqb_iie {
486	__le32 addr;	486	__le32 addr;
487	__le32 addr_hi;	487	__le32 addr_hi;
488	__le32 flags;	488	__le32 flags;
489	__le32 len;	489	__le32 len;
490	__le32 ata_cmd[4];	490	__le32 ata_cmd[4];
491	};	491	};
492		492
493	/* Command ResPonse Block: 8B */	493	/* Command ResPonse Block: 8B */
494	struct mv_crpb {	494	struct mv_crpb {
495	__le16 id;	495	__le16 id;
496	__le16 flags;	496	__le16 flags;
497	__le32 tmstmp;	497	__le32 tmstmp;
498	};	498	};
499		499
500	/* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */	500	/* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
501	struct mv_sg {	501	struct mv_sg {
502	__le32 addr;	502	__le32 addr;
503	__le32 flags_size;	503	__le32 flags_size;
504	__le32 addr_hi;	504	__le32 addr_hi;
505	__le32 reserved;	505	__le32 reserved;
506	};	506	};
507		507
508	/*	508	/*
509	* We keep a local cache of a few frequently accessed port	509	* We keep a local cache of a few frequently accessed port
510	* registers here, to avoid having to read them (very slow)	510	* registers here, to avoid having to read them (very slow)
511	* when switching between EDMA and non-EDMA modes.	511	* when switching between EDMA and non-EDMA modes.
512	*/	512	*/
513	struct mv_cached_regs {	513	struct mv_cached_regs {
514	u32 fiscfg;	514	u32 fiscfg;
515	u32 ltmode;	515	u32 ltmode;
516	u32 haltcond;	516	u32 haltcond;
517	u32 unknown_rsvd;	517	u32 unknown_rsvd;
518	};	518	};
519		519
520	struct mv_port_priv {	520	struct mv_port_priv {
521	struct mv_crqb *crqb;	521	struct mv_crqb *crqb;
522	dma_addr_t crqb_dma;	522	dma_addr_t crqb_dma;
523	struct mv_crpb *crpb;	523	struct mv_crpb *crpb;
524	dma_addr_t crpb_dma;	524	dma_addr_t crpb_dma;
525	struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH];	525	struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH];
526	dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH];	526	dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH];
527		527
528	unsigned int req_idx;	528	unsigned int req_idx;
529	unsigned int resp_idx;	529	unsigned int resp_idx;
530		530
531	u32 pp_flags;	531	u32 pp_flags;
532	struct mv_cached_regs cached;	532	struct mv_cached_regs cached;
533	unsigned int delayed_eh_pmp_map;	533	unsigned int delayed_eh_pmp_map;
534	};	534	};
535		535
536	struct mv_port_signal {	536	struct mv_port_signal {
537	u32 amps;	537	u32 amps;
538	u32 pre;	538	u32 pre;
539	};	539	};
540		540
541	struct mv_host_priv {	541	struct mv_host_priv {
542	u32 hp_flags;	542	u32 hp_flags;
543	unsigned int board_idx;	543	unsigned int board_idx;
544	u32 main_irq_mask;	544	u32 main_irq_mask;
545	struct mv_port_signal signal[8];	545	struct mv_port_signal signal[8];
546	const struct mv_hw_ops *ops;	546	const struct mv_hw_ops *ops;
547	int n_ports;	547	int n_ports;
548	void __iomem *base;	548	void __iomem *base;
549	void __iomem *main_irq_cause_addr;	549	void __iomem *main_irq_cause_addr;
550	void __iomem *main_irq_mask_addr;	550	void __iomem *main_irq_mask_addr;
551	u32 irq_cause_offset;	551	u32 irq_cause_offset;
552	u32 irq_mask_offset;	552	u32 irq_mask_offset;
553	u32 unmask_all_irqs;	553	u32 unmask_all_irqs;
554		554
555	#if defined(CONFIG_HAVE_CLK)	555	#if defined(CONFIG_HAVE_CLK)
556	struct clk *clk;	556	struct clk *clk;
557	#endif	557	#endif
558	/*	558	/*
559	* These consistent DMA memory pools give us guaranteed	559	* These consistent DMA memory pools give us guaranteed
560	* alignment for hardware-accessed data structures,	560	* alignment for hardware-accessed data structures,
561	* and less memory waste in accomplishing the alignment.	561	* and less memory waste in accomplishing the alignment.
562	*/	562	*/
563	struct dma_pool *crqb_pool;	563	struct dma_pool *crqb_pool;
564	struct dma_pool *crpb_pool;	564	struct dma_pool *crpb_pool;
565	struct dma_pool *sg_tbl_pool;	565	struct dma_pool *sg_tbl_pool;
566	};	566	};
567		567
568	struct mv_hw_ops {	568	struct mv_hw_ops {
569	void (phy_errata)(struct mv_host_priv hpriv, void __iomem *mmio,	569	void (phy_errata)(struct mv_host_priv hpriv, void __iomem *mmio,
570	unsigned int port);	570	unsigned int port);
571	void (enable_leds)(struct mv_host_priv hpriv, void __iomem *mmio);	571	void (enable_leds)(struct mv_host_priv hpriv, void __iomem *mmio);
572	void (read_preamp)(struct mv_host_priv hpriv, int idx,	572	void (read_preamp)(struct mv_host_priv hpriv, int idx,
573	void __iomem *mmio);	573	void __iomem *mmio);
574	int (reset_hc)(struct mv_host_priv hpriv, void __iomem *mmio,	574	int (reset_hc)(struct mv_host_priv hpriv, void __iomem *mmio,
575	unsigned int n_hc);	575	unsigned int n_hc);
576	void (reset_flash)(struct mv_host_priv hpriv, void __iomem *mmio);	576	void (reset_flash)(struct mv_host_priv hpriv, void __iomem *mmio);
577	void (reset_bus)(struct ata_host host, void __iomem *mmio);	577	void (reset_bus)(struct ata_host host, void __iomem *mmio);
578	};	578	};
579		579
580	static int mv_scr_read(struct ata_link link, unsigned int sc_reg_in, u32 val);	580	static int mv_scr_read(struct ata_link link, unsigned int sc_reg_in, u32 val);
581	static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);	581	static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
582	static int mv5_scr_read(struct ata_link link, unsigned int sc_reg_in, u32 val);	582	static int mv5_scr_read(struct ata_link link, unsigned int sc_reg_in, u32 val);
583	static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);	583	static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
584	static int mv_port_start(struct ata_port *ap);	584	static int mv_port_start(struct ata_port *ap);
585	static void mv_port_stop(struct ata_port *ap);	585	static void mv_port_stop(struct ata_port *ap);
586	static int mv_qc_defer(struct ata_queued_cmd *qc);	586	static int mv_qc_defer(struct ata_queued_cmd *qc);
587	static void mv_qc_prep(struct ata_queued_cmd *qc);	587	static void mv_qc_prep(struct ata_queued_cmd *qc);
588	static void mv_qc_prep_iie(struct ata_queued_cmd *qc);	588	static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
589	static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);	589	static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
590	static int mv_hardreset(struct ata_link link, unsigned int class,	590	static int mv_hardreset(struct ata_link link, unsigned int class,
591	unsigned long deadline);	591	unsigned long deadline);
592	static void mv_eh_freeze(struct ata_port *ap);	592	static void mv_eh_freeze(struct ata_port *ap);
593	static void mv_eh_thaw(struct ata_port *ap);	593	static void mv_eh_thaw(struct ata_port *ap);
594	static void mv6_dev_config(struct ata_device *dev);	594	static void mv6_dev_config(struct ata_device *dev);
595		595
596	static void mv5_phy_errata(struct mv_host_priv hpriv, void __iomem mmio,	596	static void mv5_phy_errata(struct mv_host_priv hpriv, void __iomem mmio,
597	unsigned int port);	597	unsigned int port);
598	static void mv5_enable_leds(struct mv_host_priv hpriv, void __iomem mmio);	598	static void mv5_enable_leds(struct mv_host_priv hpriv, void __iomem mmio);
599	static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,	599	static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
600	void __iomem *mmio);	600	void __iomem *mmio);
601	static int mv5_reset_hc(struct mv_host_priv hpriv, void __iomem mmio,	601	static int mv5_reset_hc(struct mv_host_priv hpriv, void __iomem mmio,
602	unsigned int n_hc);	602	unsigned int n_hc);
603	static void mv5_reset_flash(struct mv_host_priv hpriv, void __iomem mmio);	603	static void mv5_reset_flash(struct mv_host_priv hpriv, void __iomem mmio);
604	static void mv5_reset_bus(struct ata_host host, void __iomem mmio);	604	static void mv5_reset_bus(struct ata_host host, void __iomem mmio);
605		605
606	static void mv6_phy_errata(struct mv_host_priv hpriv, void __iomem mmio,	606	static void mv6_phy_errata(struct mv_host_priv hpriv, void __iomem mmio,
607	unsigned int port);	607	unsigned int port);
608	static void mv6_enable_leds(struct mv_host_priv hpriv, void __iomem mmio);	608	static void mv6_enable_leds(struct mv_host_priv hpriv, void __iomem mmio);
609	static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,	609	static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
610	void __iomem *mmio);	610	void __iomem *mmio);
611	static int mv6_reset_hc(struct mv_host_priv hpriv, void __iomem mmio,	611	static int mv6_reset_hc(struct mv_host_priv hpriv, void __iomem mmio,
612	unsigned int n_hc);	612	unsigned int n_hc);
613	static void mv6_reset_flash(struct mv_host_priv hpriv, void __iomem mmio);	613	static void mv6_reset_flash(struct mv_host_priv hpriv, void __iomem mmio);
614	static void mv_soc_enable_leds(struct mv_host_priv *hpriv,	614	static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
615	void __iomem *mmio);	615	void __iomem *mmio);
616	static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,	616	static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
617	void __iomem *mmio);	617	void __iomem *mmio);
618	static int mv_soc_reset_hc(struct mv_host_priv *hpriv,	618	static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
619	void __iomem *mmio, unsigned int n_hc);	619	void __iomem *mmio, unsigned int n_hc);
620	static void mv_soc_reset_flash(struct mv_host_priv *hpriv,	620	static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
621	void __iomem *mmio);	621	void __iomem *mmio);
622	static void mv_soc_reset_bus(struct ata_host host, void __iomem mmio);	622	static void mv_soc_reset_bus(struct ata_host host, void __iomem mmio);
623	static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv,	623	static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv,
624	void __iomem *mmio, unsigned int port);	624	void __iomem *mmio, unsigned int port);
625	static void mv_reset_pci_bus(struct ata_host host, void __iomem mmio);	625	static void mv_reset_pci_bus(struct ata_host host, void __iomem mmio);
626	static void mv_reset_channel(struct mv_host_priv hpriv, void __iomem mmio,	626	static void mv_reset_channel(struct mv_host_priv hpriv, void __iomem mmio,
627	unsigned int port_no);	627	unsigned int port_no);
628	static int mv_stop_edma(struct ata_port *ap);	628	static int mv_stop_edma(struct ata_port *ap);
629	static int mv_stop_edma_engine(void __iomem *port_mmio);	629	static int mv_stop_edma_engine(void __iomem *port_mmio);
630	static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma);	630	static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma);
631		631
632	static void mv_pmp_select(struct ata_port *ap, int pmp);	632	static void mv_pmp_select(struct ata_port *ap, int pmp);
633	static int mv_pmp_hardreset(struct ata_link link, unsigned int class,	633	static int mv_pmp_hardreset(struct ata_link link, unsigned int class,
634	unsigned long deadline);	634	unsigned long deadline);
635	static int mv_softreset(struct ata_link link, unsigned int class,	635	static int mv_softreset(struct ata_link link, unsigned int class,
636	unsigned long deadline);	636	unsigned long deadline);
637	static void mv_pmp_error_handler(struct ata_port *ap);	637	static void mv_pmp_error_handler(struct ata_port *ap);
638	static void mv_process_crpb_entries(struct ata_port *ap,	638	static void mv_process_crpb_entries(struct ata_port *ap,
639	struct mv_port_priv *pp);	639	struct mv_port_priv *pp);
640		640
641	static void mv_sff_irq_clear(struct ata_port *ap);	641	static void mv_sff_irq_clear(struct ata_port *ap);
642	static int mv_check_atapi_dma(struct ata_queued_cmd *qc);	642	static int mv_check_atapi_dma(struct ata_queued_cmd *qc);
643	static void mv_bmdma_setup(struct ata_queued_cmd *qc);	643	static void mv_bmdma_setup(struct ata_queued_cmd *qc);
644	static void mv_bmdma_start(struct ata_queued_cmd *qc);	644	static void mv_bmdma_start(struct ata_queued_cmd *qc);
645	static void mv_bmdma_stop(struct ata_queued_cmd *qc);	645	static void mv_bmdma_stop(struct ata_queued_cmd *qc);
646	static u8 mv_bmdma_status(struct ata_port *ap);	646	static u8 mv_bmdma_status(struct ata_port *ap);
647	static u8 mv_sff_check_status(struct ata_port *ap);	647	static u8 mv_sff_check_status(struct ata_port *ap);
648		648
649	/* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below	649	/* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below
650	* because we have to allow room for worst case splitting of	650	* because we have to allow room for worst case splitting of
651	* PRDs for 64K boundaries in mv_fill_sg().	651	* PRDs for 64K boundaries in mv_fill_sg().
652	*/	652	*/
653	static struct scsi_host_template mv5_sht = {	653	static struct scsi_host_template mv5_sht = {
654	ATA_BASE_SHT(DRV_NAME),	654	ATA_BASE_SHT(DRV_NAME),
655	.sg_tablesize = MV_MAX_SG_CT / 2,	655	.sg_tablesize = MV_MAX_SG_CT / 2,
656	.dma_boundary = MV_DMA_BOUNDARY,	656	.dma_boundary = MV_DMA_BOUNDARY,
657	};	657	};
658		658
659	static struct scsi_host_template mv6_sht = {	659	static struct scsi_host_template mv6_sht = {
660	ATA_NCQ_SHT(DRV_NAME),	660	ATA_NCQ_SHT(DRV_NAME),
661	.can_queue = MV_MAX_Q_DEPTH - 1,	661	.can_queue = MV_MAX_Q_DEPTH - 1,
662	.sg_tablesize = MV_MAX_SG_CT / 2,	662	.sg_tablesize = MV_MAX_SG_CT / 2,
663	.dma_boundary = MV_DMA_BOUNDARY,	663	.dma_boundary = MV_DMA_BOUNDARY,
664	};	664	};
665		665
666	static struct ata_port_operations mv5_ops = {	666	static struct ata_port_operations mv5_ops = {
667	.inherits = &ata_sff_port_ops,	667	.inherits = &ata_sff_port_ops,
668		668
669	.lost_interrupt = ATA_OP_NULL,	669	.lost_interrupt = ATA_OP_NULL,
670		670
671	.qc_defer = mv_qc_defer,	671	.qc_defer = mv_qc_defer,
672	.qc_prep = mv_qc_prep,	672	.qc_prep = mv_qc_prep,
673	.qc_issue = mv_qc_issue,	673	.qc_issue = mv_qc_issue,
674		674
675	.freeze = mv_eh_freeze,	675	.freeze = mv_eh_freeze,
676	.thaw = mv_eh_thaw,	676	.thaw = mv_eh_thaw,
677	.hardreset = mv_hardreset,	677	.hardreset = mv_hardreset,
678		678
679	.scr_read = mv5_scr_read,	679	.scr_read = mv5_scr_read,
680	.scr_write = mv5_scr_write,	680	.scr_write = mv5_scr_write,
681		681
682	.port_start = mv_port_start,	682	.port_start = mv_port_start,
683	.port_stop = mv_port_stop,	683	.port_stop = mv_port_stop,
684	};	684	};
685		685
686	static struct ata_port_operations mv6_ops = {	686	static struct ata_port_operations mv6_ops = {
687	.inherits = &ata_bmdma_port_ops,	687	.inherits = &ata_bmdma_port_ops,
688		688
689	.lost_interrupt = ATA_OP_NULL,	689	.lost_interrupt = ATA_OP_NULL,
690		690
691	.qc_defer = mv_qc_defer,	691	.qc_defer = mv_qc_defer,
692	.qc_prep = mv_qc_prep,	692	.qc_prep = mv_qc_prep,
693	.qc_issue = mv_qc_issue,	693	.qc_issue = mv_qc_issue,
694		694
695	.dev_config = mv6_dev_config,	695	.dev_config = mv6_dev_config,
696		696
697	.freeze = mv_eh_freeze,	697	.freeze = mv_eh_freeze,
698	.thaw = mv_eh_thaw,	698	.thaw = mv_eh_thaw,
699	.hardreset = mv_hardreset,	699	.hardreset = mv_hardreset,
700	.softreset = mv_softreset,	700	.softreset = mv_softreset,
701	.pmp_hardreset = mv_pmp_hardreset,	701	.pmp_hardreset = mv_pmp_hardreset,
702	.pmp_softreset = mv_softreset,	702	.pmp_softreset = mv_softreset,
703	.error_handler = mv_pmp_error_handler,	703	.error_handler = mv_pmp_error_handler,
704		704
705	.scr_read = mv_scr_read,	705	.scr_read = mv_scr_read,
706	.scr_write = mv_scr_write,	706	.scr_write = mv_scr_write,
707		707
708	.sff_check_status = mv_sff_check_status,	708	.sff_check_status = mv_sff_check_status,
709	.sff_irq_clear = mv_sff_irq_clear,	709	.sff_irq_clear = mv_sff_irq_clear,
710	.check_atapi_dma = mv_check_atapi_dma,	710	.check_atapi_dma = mv_check_atapi_dma,
711	.bmdma_setup = mv_bmdma_setup,	711	.bmdma_setup = mv_bmdma_setup,
712	.bmdma_start = mv_bmdma_start,	712	.bmdma_start = mv_bmdma_start,
713	.bmdma_stop = mv_bmdma_stop,	713	.bmdma_stop = mv_bmdma_stop,
714	.bmdma_status = mv_bmdma_status,	714	.bmdma_status = mv_bmdma_status,
715		715
716	.port_start = mv_port_start,	716	.port_start = mv_port_start,
717	.port_stop = mv_port_stop,	717	.port_stop = mv_port_stop,
718	};	718	};
719		719
720	static struct ata_port_operations mv_iie_ops = {	720	static struct ata_port_operations mv_iie_ops = {
721	.inherits = &mv6_ops,	721	.inherits = &mv6_ops,
722	.dev_config = ATA_OP_NULL,	722	.dev_config = ATA_OP_NULL,
723	.qc_prep = mv_qc_prep_iie,	723	.qc_prep = mv_qc_prep_iie,
724	};	724	};
725		725
726	static const struct ata_port_info mv_port_info[] = {	726	static const struct ata_port_info mv_port_info[] = {
727	{ /* chip_504x */	727	{ /* chip_504x */
728	.flags = MV_GEN_I_FLAGS,	728	.flags = MV_GEN_I_FLAGS,
729	.pio_mask = ATA_PIO4,	729	.pio_mask = ATA_PIO4,
730	.udma_mask = ATA_UDMA6,	730	.udma_mask = ATA_UDMA6,
731	.port_ops = &mv5_ops,	731	.port_ops = &mv5_ops,
732	},	732	},
733	{ /* chip_508x */	733	{ /* chip_508x */
734	.flags = MV_GEN_I_FLAGS \| MV_FLAG_DUAL_HC,	734	.flags = MV_GEN_I_FLAGS \| MV_FLAG_DUAL_HC,
735	.pio_mask = ATA_PIO4,	735	.pio_mask = ATA_PIO4,
736	.udma_mask = ATA_UDMA6,	736	.udma_mask = ATA_UDMA6,
737	.port_ops = &mv5_ops,	737	.port_ops = &mv5_ops,
738	},	738	},
739	{ /* chip_5080 */	739	{ /* chip_5080 */
740	.flags = MV_GEN_I_FLAGS \| MV_FLAG_DUAL_HC,	740	.flags = MV_GEN_I_FLAGS \| MV_FLAG_DUAL_HC,
741	.pio_mask = ATA_PIO4,	741	.pio_mask = ATA_PIO4,
742	.udma_mask = ATA_UDMA6,	742	.udma_mask = ATA_UDMA6,
743	.port_ops = &mv5_ops,	743	.port_ops = &mv5_ops,
744	},	744	},
745	{ /* chip_604x */	745	{ /* chip_604x */
746	.flags = MV_GEN_II_FLAGS,	746	.flags = MV_GEN_II_FLAGS,
747	.pio_mask = ATA_PIO4,	747	.pio_mask = ATA_PIO4,
748	.udma_mask = ATA_UDMA6,	748	.udma_mask = ATA_UDMA6,
749	.port_ops = &mv6_ops,	749	.port_ops = &mv6_ops,
750	},	750	},
751	{ /* chip_608x */	751	{ /* chip_608x */
752	.flags = MV_GEN_II_FLAGS \| MV_FLAG_DUAL_HC,	752	.flags = MV_GEN_II_FLAGS \| MV_FLAG_DUAL_HC,
753	.pio_mask = ATA_PIO4,	753	.pio_mask = ATA_PIO4,
754	.udma_mask = ATA_UDMA6,	754	.udma_mask = ATA_UDMA6,
755	.port_ops = &mv6_ops,	755	.port_ops = &mv6_ops,
756	},	756	},
757	{ /* chip_6042 */	757	{ /* chip_6042 */
758	.flags = MV_GEN_IIE_FLAGS,	758	.flags = MV_GEN_IIE_FLAGS,
759	.pio_mask = ATA_PIO4,	759	.pio_mask = ATA_PIO4,
760	.udma_mask = ATA_UDMA6,	760	.udma_mask = ATA_UDMA6,
761	.port_ops = &mv_iie_ops,	761	.port_ops = &mv_iie_ops,
762	},	762	},
763	{ /* chip_7042 */	763	{ /* chip_7042 */
764	.flags = MV_GEN_IIE_FLAGS,	764	.flags = MV_GEN_IIE_FLAGS,
765	.pio_mask = ATA_PIO4,	765	.pio_mask = ATA_PIO4,
766	.udma_mask = ATA_UDMA6,	766	.udma_mask = ATA_UDMA6,
767	.port_ops = &mv_iie_ops,	767	.port_ops = &mv_iie_ops,
768	},	768	},
769	{ /* chip_soc */	769	{ /* chip_soc */
770	.flags = MV_GEN_IIE_FLAGS,	770	.flags = MV_GEN_IIE_FLAGS,
771	.pio_mask = ATA_PIO4,	771	.pio_mask = ATA_PIO4,
772	.udma_mask = ATA_UDMA6,	772	.udma_mask = ATA_UDMA6,
773	.port_ops = &mv_iie_ops,	773	.port_ops = &mv_iie_ops,
774	},	774	},
775	};	775	};
776		776
777	static const struct pci_device_id mv_pci_tbl[] = {	777	static const struct pci_device_id mv_pci_tbl[] = {
778	{ PCI_VDEVICE(MARVELL, 0x5040), chip_504x },	778	{ PCI_VDEVICE(MARVELL, 0x5040), chip_504x },
779	{ PCI_VDEVICE(MARVELL, 0x5041), chip_504x },	779	{ PCI_VDEVICE(MARVELL, 0x5041), chip_504x },
780	{ PCI_VDEVICE(MARVELL, 0x5080), chip_5080 },	780	{ PCI_VDEVICE(MARVELL, 0x5080), chip_5080 },
781	{ PCI_VDEVICE(MARVELL, 0x5081), chip_508x },	781	{ PCI_VDEVICE(MARVELL, 0x5081), chip_508x },
782	/* RocketRAID 1720/174x have different identifiers */	782	/* RocketRAID 1720/174x have different identifiers */
783	{ PCI_VDEVICE(TTI, 0x1720), chip_6042 },	783	{ PCI_VDEVICE(TTI, 0x1720), chip_6042 },
784	{ PCI_VDEVICE(TTI, 0x1740), chip_6042 },	784	{ PCI_VDEVICE(TTI, 0x1740), chip_6042 },
785	{ PCI_VDEVICE(TTI, 0x1742), chip_6042 },	785	{ PCI_VDEVICE(TTI, 0x1742), chip_6042 },
786		786
787	{ PCI_VDEVICE(MARVELL, 0x6040), chip_604x },	787	{ PCI_VDEVICE(MARVELL, 0x6040), chip_604x },
788	{ PCI_VDEVICE(MARVELL, 0x6041), chip_604x },	788	{ PCI_VDEVICE(MARVELL, 0x6041), chip_604x },
789	{ PCI_VDEVICE(MARVELL, 0x6042), chip_6042 },	789	{ PCI_VDEVICE(MARVELL, 0x6042), chip_6042 },
790	{ PCI_VDEVICE(MARVELL, 0x6080), chip_608x },	790	{ PCI_VDEVICE(MARVELL, 0x6080), chip_608x },
791	{ PCI_VDEVICE(MARVELL, 0x6081), chip_608x },	791	{ PCI_VDEVICE(MARVELL, 0x6081), chip_608x },
792		792
793	{ PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x },	793	{ PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x },
794		794
795	/* Adaptec 1430SA */	795	/* Adaptec 1430SA */
796	{ PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 },	796	{ PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 },
797		797
798	/* Marvell 7042 support */	798	/* Marvell 7042 support */
799	{ PCI_VDEVICE(MARVELL, 0x7042), chip_7042 },	799	{ PCI_VDEVICE(MARVELL, 0x7042), chip_7042 },
800		800
801	/* Highpoint RocketRAID PCIe series */	801	/* Highpoint RocketRAID PCIe series */
802	{ PCI_VDEVICE(TTI, 0x2300), chip_7042 },	802	{ PCI_VDEVICE(TTI, 0x2300), chip_7042 },
803	{ PCI_VDEVICE(TTI, 0x2310), chip_7042 },	803	{ PCI_VDEVICE(TTI, 0x2310), chip_7042 },
804		804
805	{ } /* terminate list */	805	{ } /* terminate list */
806	};	806	};
807		807
808	static const struct mv_hw_ops mv5xxx_ops = {	808	static const struct mv_hw_ops mv5xxx_ops = {
809	.phy_errata = mv5_phy_errata,	809	.phy_errata = mv5_phy_errata,
810	.enable_leds = mv5_enable_leds,	810	.enable_leds = mv5_enable_leds,
811	.read_preamp = mv5_read_preamp,	811	.read_preamp = mv5_read_preamp,
812	.reset_hc = mv5_reset_hc,	812	.reset_hc = mv5_reset_hc,
813	.reset_flash = mv5_reset_flash,	813	.reset_flash = mv5_reset_flash,
814	.reset_bus = mv5_reset_bus,	814	.reset_bus = mv5_reset_bus,
815	};	815	};
816		816
817	static const struct mv_hw_ops mv6xxx_ops = {	817	static const struct mv_hw_ops mv6xxx_ops = {
818	.phy_errata = mv6_phy_errata,	818	.phy_errata = mv6_phy_errata,
819	.enable_leds = mv6_enable_leds,	819	.enable_leds = mv6_enable_leds,
820	.read_preamp = mv6_read_preamp,	820	.read_preamp = mv6_read_preamp,
821	.reset_hc = mv6_reset_hc,	821	.reset_hc = mv6_reset_hc,
822	.reset_flash = mv6_reset_flash,	822	.reset_flash = mv6_reset_flash,
823	.reset_bus = mv_reset_pci_bus,	823	.reset_bus = mv_reset_pci_bus,
824	};	824	};
825		825
826	static const struct mv_hw_ops mv_soc_ops = {	826	static const struct mv_hw_ops mv_soc_ops = {
827	.phy_errata = mv6_phy_errata,	827	.phy_errata = mv6_phy_errata,
828	.enable_leds = mv_soc_enable_leds,	828	.enable_leds = mv_soc_enable_leds,
829	.read_preamp = mv_soc_read_preamp,	829	.read_preamp = mv_soc_read_preamp,
830	.reset_hc = mv_soc_reset_hc,	830	.reset_hc = mv_soc_reset_hc,
831	.reset_flash = mv_soc_reset_flash,	831	.reset_flash = mv_soc_reset_flash,
832	.reset_bus = mv_soc_reset_bus,	832	.reset_bus = mv_soc_reset_bus,
833	};	833	};
834		834
835	static const struct mv_hw_ops mv_soc_65n_ops = {	835	static const struct mv_hw_ops mv_soc_65n_ops = {
836	.phy_errata = mv_soc_65n_phy_errata,	836	.phy_errata = mv_soc_65n_phy_errata,
837	.enable_leds = mv_soc_enable_leds,	837	.enable_leds = mv_soc_enable_leds,
838	.reset_hc = mv_soc_reset_hc,	838	.reset_hc = mv_soc_reset_hc,
839	.reset_flash = mv_soc_reset_flash,	839	.reset_flash = mv_soc_reset_flash,
840	.reset_bus = mv_soc_reset_bus,	840	.reset_bus = mv_soc_reset_bus,
841	};	841	};
842		842
843	/*	843	/*
844	* Functions	844	* Functions
845	*/	845	*/
846		846
847	static inline void writelfl(unsigned long data, void __iomem *addr)	847	static inline void writelfl(unsigned long data, void __iomem *addr)
848	{	848	{
849	writel(data, addr);	849	writel(data, addr);
850	(void) readl(addr); /* flush to avoid PCI posted write */	850	(void) readl(addr); /* flush to avoid PCI posted write */
851	}	851	}
852		852
853	static inline unsigned int mv_hc_from_port(unsigned int port)	853	static inline unsigned int mv_hc_from_port(unsigned int port)
854	{	854	{
855	return port >> MV_PORT_HC_SHIFT;	855	return port >> MV_PORT_HC_SHIFT;
856	}	856	}
857		857
858	static inline unsigned int mv_hardport_from_port(unsigned int port)	858	static inline unsigned int mv_hardport_from_port(unsigned int port)
859	{	859	{
860	return port & MV_PORT_MASK;	860	return port & MV_PORT_MASK;
861	}	861	}
862		862
863	/*	863	/*
864	* Consolidate some rather tricky bit shift calculations.	864	* Consolidate some rather tricky bit shift calculations.
865	* This is hot-path stuff, so not a function.	865	* This is hot-path stuff, so not a function.
866	* Simple code, with two return values, so macro rather than inline.	866	* Simple code, with two return values, so macro rather than inline.
867	*	867	*
868	* port is the sole input, in range 0..7.	868	* port is the sole input, in range 0..7.
869	* shift is one output, for use with main_irq_cause / main_irq_mask registers.	869	* shift is one output, for use with main_irq_cause / main_irq_mask registers.
870	* hardport is the other output, in range 0..3.	870	* hardport is the other output, in range 0..3.
871	*	871	*
872	* Note that port and hardport may be the same variable in some cases.	872	* Note that port and hardport may be the same variable in some cases.
873	*/	873	*/
874	#define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \	874	#define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \
875	{ \	875	{ \
876	shift = mv_hc_from_port(port) * HC_SHIFT; \	876	shift = mv_hc_from_port(port) * HC_SHIFT; \
877	hardport = mv_hardport_from_port(port); \	877	hardport = mv_hardport_from_port(port); \
878	shift += hardport * 2; \	878	shift += hardport * 2; \
879	}	879	}
880		880
881	static inline void __iomem mv_hc_base(void __iomem base, unsigned int hc)	881	static inline void __iomem mv_hc_base(void __iomem base, unsigned int hc)
882	{	882	{
883	return (base + SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));	883	return (base + SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
884	}	884	}
885		885
886	static inline void __iomem mv_hc_base_from_port(void __iomem base,	886	static inline void __iomem mv_hc_base_from_port(void __iomem base,
887	unsigned int port)	887	unsigned int port)
888	{	888	{
889	return mv_hc_base(base, mv_hc_from_port(port));	889	return mv_hc_base(base, mv_hc_from_port(port));
890	}	890	}
891		891
892	static inline void __iomem mv_port_base(void __iomem base, unsigned int port)	892	static inline void __iomem mv_port_base(void __iomem base, unsigned int port)
893	{	893	{
894	return mv_hc_base_from_port(base, port) +	894	return mv_hc_base_from_port(base, port) +
895	MV_SATAHC_ARBTR_REG_SZ +	895	MV_SATAHC_ARBTR_REG_SZ +
896	(mv_hardport_from_port(port) * MV_PORT_REG_SZ);	896	(mv_hardport_from_port(port) * MV_PORT_REG_SZ);
897	}	897	}
898		898
899	static void __iomem mv5_phy_base(void __iomem mmio, unsigned int port)	899	static void __iomem mv5_phy_base(void __iomem mmio, unsigned int port)
900	{	900	{
901	void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);	901	void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
902	unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;	902	unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
903		903
904	return hc_mmio + ofs;	904	return hc_mmio + ofs;
905	}	905	}
906		906
907	static inline void __iomem mv_host_base(struct ata_host host)	907	static inline void __iomem mv_host_base(struct ata_host host)
908	{	908	{
909	struct mv_host_priv *hpriv = host->private_data;	909	struct mv_host_priv *hpriv = host->private_data;
910	return hpriv->base;	910	return hpriv->base;
911	}	911	}
912		912
913	static inline void __iomem mv_ap_base(struct ata_port ap)	913	static inline void __iomem mv_ap_base(struct ata_port ap)
914	{	914	{
915	return mv_port_base(mv_host_base(ap->host), ap->port_no);	915	return mv_port_base(mv_host_base(ap->host), ap->port_no);
916	}	916	}
917		917
918	static inline int mv_get_hc_count(unsigned long port_flags)	918	static inline int mv_get_hc_count(unsigned long port_flags)
919	{	919	{
920	return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1);	920	return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
921	}	921	}
922		922
923	/**	923	/**
924	* mv_save_cached_regs - (re-)initialize cached port registers	924	* mv_save_cached_regs - (re-)initialize cached port registers
925	* @ap: the port whose registers we are caching	925	* @ap: the port whose registers we are caching
926	*	926	*
927	* Initialize the local cache of port registers,	927	* Initialize the local cache of port registers,
928	* so that reading them over and over again can	928	* so that reading them over and over again can
929	* be avoided on the hotter paths of this driver.	929	* be avoided on the hotter paths of this driver.
930	* This saves a few microseconds each time we switch	930	* This saves a few microseconds each time we switch
931	* to/from EDMA mode to perform (eg.) a drive cache flush.	931	* to/from EDMA mode to perform (eg.) a drive cache flush.
932	*/	932	*/
933	static void mv_save_cached_regs(struct ata_port *ap)	933	static void mv_save_cached_regs(struct ata_port *ap)
934	{	934	{
935	void __iomem *port_mmio = mv_ap_base(ap);	935	void __iomem *port_mmio = mv_ap_base(ap);
936	struct mv_port_priv *pp = ap->private_data;	936	struct mv_port_priv *pp = ap->private_data;
937		937
938	pp->cached.fiscfg = readl(port_mmio + FISCFG);	938	pp->cached.fiscfg = readl(port_mmio + FISCFG);
939	pp->cached.ltmode = readl(port_mmio + LTMODE);	939	pp->cached.ltmode = readl(port_mmio + LTMODE);
940	pp->cached.haltcond = readl(port_mmio + EDMA_HALTCOND);	940	pp->cached.haltcond = readl(port_mmio + EDMA_HALTCOND);
941	pp->cached.unknown_rsvd = readl(port_mmio + EDMA_UNKNOWN_RSVD);	941	pp->cached.unknown_rsvd = readl(port_mmio + EDMA_UNKNOWN_RSVD);
942	}	942	}
943		943
944	/**	944	/**
945	* mv_write_cached_reg - write to a cached port register	945	* mv_write_cached_reg - write to a cached port register
946	* @addr: hardware address of the register	946	* @addr: hardware address of the register
947	* @old: pointer to cached value of the register	947	* @old: pointer to cached value of the register
948	* @new: new value for the register	948	* @new: new value for the register
949	*	949	*
950	* Write a new value to a cached register,	950	* Write a new value to a cached register,
951	* but only if the value is different from before.	951	* but only if the value is different from before.
952	*/	952	*/
953	static inline void mv_write_cached_reg(void __iomem addr, u32 old, u32 new)	953	static inline void mv_write_cached_reg(void __iomem addr, u32 old, u32 new)
954	{	954	{
955	if (new != *old) {	955	if (new != *old) {
956	unsigned long laddr;	956	unsigned long laddr;
957	*old = new;	957	*old = new;
958	/*	958	/*
959	* Workaround for 88SX60x1-B2 FEr SATA#13:	959	* Workaround for 88SX60x1-B2 FEr SATA#13:
960	* Read-after-write is needed to prevent generating 64-bit	960	* Read-after-write is needed to prevent generating 64-bit
961	* write cycles on the PCI bus for SATA interface registers	961	* write cycles on the PCI bus for SATA interface registers
962	* at offsets ending in 0x4 or 0xc.	962	* at offsets ending in 0x4 or 0xc.
963	*	963	*
964	* Looks like a lot of fuss, but it avoids an unnecessary	964	* Looks like a lot of fuss, but it avoids an unnecessary
965	* +1 usec read-after-write delay for unaffected registers.	965	* +1 usec read-after-write delay for unaffected registers.
966	*/	966	*/
967	laddr = (long)addr & 0xffff;	967	laddr = (long)addr & 0xffff;
968	if (laddr >= 0x300 && laddr <= 0x33c) {	968	if (laddr >= 0x300 && laddr <= 0x33c) {
969	laddr &= 0x000f;	969	laddr &= 0x000f;
970	if (laddr == 0x4 \|\| laddr == 0xc) {	970	if (laddr == 0x4 \|\| laddr == 0xc) {
971	writelfl(new, addr); /* read after write */	971	writelfl(new, addr); /* read after write */
972	return;	972	return;
973	}	973	}
974	}	974	}
975	writel(new, addr); /* unaffected by the errata */	975	writel(new, addr); /* unaffected by the errata */
976	}	976	}
977	}	977	}
978		978
979	static void mv_set_edma_ptrs(void __iomem *port_mmio,	979	static void mv_set_edma_ptrs(void __iomem *port_mmio,
980	struct mv_host_priv *hpriv,	980	struct mv_host_priv *hpriv,
981	struct mv_port_priv *pp)	981	struct mv_port_priv *pp)
982	{	982	{
983	u32 index;	983	u32 index;
984		984
985	/*	985	/*
986	* initialize request queue	986	* initialize request queue
987	*/	987	*/
988	pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */	988	pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
989	index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;	989	index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
990		990
991	WARN_ON(pp->crqb_dma & 0x3ff);	991	WARN_ON(pp->crqb_dma & 0x3ff);
992	writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI);	992	writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI);
993	writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) \| index,	993	writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) \| index,
994	port_mmio + EDMA_REQ_Q_IN_PTR);	994	port_mmio + EDMA_REQ_Q_IN_PTR);
995	writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR);	995	writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR);
996		996
997	/*	997	/*
998	* initialize response queue	998	* initialize response queue
999	*/	999	*/
1000	pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */	1000	pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
1001	index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT;	1001	index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT;
1002		1002
1003	WARN_ON(pp->crpb_dma & 0xff);	1003	WARN_ON(pp->crpb_dma & 0xff);
1004	writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI);	1004	writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI);
1005	writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR);	1005	writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR);
1006	writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) \| index,	1006	writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) \| index,
1007	port_mmio + EDMA_RSP_Q_OUT_PTR);	1007	port_mmio + EDMA_RSP_Q_OUT_PTR);
1008	}	1008	}
1009		1009
1010	static void mv_write_main_irq_mask(u32 mask, struct mv_host_priv *hpriv)	1010	static void mv_write_main_irq_mask(u32 mask, struct mv_host_priv *hpriv)
1011	{	1011	{
1012	/*	1012	/*
1013	* When writing to the main_irq_mask in hardware,	1013	* When writing to the main_irq_mask in hardware,
1014	* we must ensure exclusivity between the interrupt coalescing bits	1014	* we must ensure exclusivity between the interrupt coalescing bits
1015	* and the corresponding individual port DONE_IRQ bits.	1015	* and the corresponding individual port DONE_IRQ bits.
1016	*	1016	*
1017	* Note that this register is really an "IRQ enable" register,	1017	* Note that this register is really an "IRQ enable" register,
1018	* not an "IRQ mask" register as Marvell's naming might suggest.	1018	* not an "IRQ mask" register as Marvell's naming might suggest.
1019	*/	1019	*/
1020	if (mask & (ALL_PORTS_COAL_DONE \| PORTS_0_3_COAL_DONE))	1020	if (mask & (ALL_PORTS_COAL_DONE \| PORTS_0_3_COAL_DONE))
1021	mask &= ~DONE_IRQ_0_3;	1021	mask &= ~DONE_IRQ_0_3;
1022	if (mask & (ALL_PORTS_COAL_DONE \| PORTS_4_7_COAL_DONE))	1022	if (mask & (ALL_PORTS_COAL_DONE \| PORTS_4_7_COAL_DONE))
1023	mask &= ~DONE_IRQ_4_7;	1023	mask &= ~DONE_IRQ_4_7;
1024	writelfl(mask, hpriv->main_irq_mask_addr);	1024	writelfl(mask, hpriv->main_irq_mask_addr);
1025	}	1025	}
1026		1026
1027	static void mv_set_main_irq_mask(struct ata_host *host,	1027	static void mv_set_main_irq_mask(struct ata_host *host,
1028	u32 disable_bits, u32 enable_bits)	1028	u32 disable_bits, u32 enable_bits)
1029	{	1029	{
1030	struct mv_host_priv *hpriv = host->private_data;	1030	struct mv_host_priv *hpriv = host->private_data;
1031	u32 old_mask, new_mask;	1031	u32 old_mask, new_mask;
1032		1032
1033	old_mask = hpriv->main_irq_mask;	1033	old_mask = hpriv->main_irq_mask;
1034	new_mask = (old_mask & ~disable_bits) \| enable_bits;	1034	new_mask = (old_mask & ~disable_bits) \| enable_bits;
1035	if (new_mask != old_mask) {	1035	if (new_mask != old_mask) {
1036	hpriv->main_irq_mask = new_mask;	1036	hpriv->main_irq_mask = new_mask;
1037	mv_write_main_irq_mask(new_mask, hpriv);	1037	mv_write_main_irq_mask(new_mask, hpriv);
1038	}	1038	}
1039	}	1039	}
1040		1040
1041	static void mv_enable_port_irqs(struct ata_port *ap,	1041	static void mv_enable_port_irqs(struct ata_port *ap,
1042	unsigned int port_bits)	1042	unsigned int port_bits)
1043	{	1043	{
1044	unsigned int shift, hardport, port = ap->port_no;	1044	unsigned int shift, hardport, port = ap->port_no;
1045	u32 disable_bits, enable_bits;	1045	u32 disable_bits, enable_bits;
1046		1046
1047	MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);	1047	MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
1048		1048
1049	disable_bits = (DONE_IRQ \| ERR_IRQ) << shift;	1049	disable_bits = (DONE_IRQ \| ERR_IRQ) << shift;
1050	enable_bits = port_bits << shift;	1050	enable_bits = port_bits << shift;
1051	mv_set_main_irq_mask(ap->host, disable_bits, enable_bits);	1051	mv_set_main_irq_mask(ap->host, disable_bits, enable_bits);
1052	}	1052	}
1053		1053
1054	static void mv_clear_and_enable_port_irqs(struct ata_port *ap,	1054	static void mv_clear_and_enable_port_irqs(struct ata_port *ap,
1055	void __iomem *port_mmio,	1055	void __iomem *port_mmio,
1056	unsigned int port_irqs)	1056	unsigned int port_irqs)
1057	{	1057	{
1058	struct mv_host_priv *hpriv = ap->host->private_data;	1058	struct mv_host_priv *hpriv = ap->host->private_data;
1059	int hardport = mv_hardport_from_port(ap->port_no);	1059	int hardport = mv_hardport_from_port(ap->port_no);
1060	void __iomem *hc_mmio = mv_hc_base_from_port(	1060	void __iomem *hc_mmio = mv_hc_base_from_port(
1061	mv_host_base(ap->host), ap->port_no);	1061	mv_host_base(ap->host), ap->port_no);
1062	u32 hc_irq_cause;	1062	u32 hc_irq_cause;
1063		1063
1064	/* clear EDMA event indicators, if any */	1064	/* clear EDMA event indicators, if any */
1065	writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE);	1065	writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE);
1066		1066
1067	/* clear pending irq events */	1067	/* clear pending irq events */
1068	hc_irq_cause = ~((DEV_IRQ \| DMA_IRQ) << hardport);	1068	hc_irq_cause = ~((DEV_IRQ \| DMA_IRQ) << hardport);
1069	writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE);	1069	writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE);
1070		1070
1071	/* clear FIS IRQ Cause */	1071	/* clear FIS IRQ Cause */
1072	if (IS_GEN_IIE(hpriv))	1072	if (IS_GEN_IIE(hpriv))
1073	writelfl(0, port_mmio + FIS_IRQ_CAUSE);	1073	writelfl(0, port_mmio + FIS_IRQ_CAUSE);
1074		1074
1075	mv_enable_port_irqs(ap, port_irqs);	1075	mv_enable_port_irqs(ap, port_irqs);
1076	}	1076	}
1077		1077
1078	static void mv_set_irq_coalescing(struct ata_host *host,	1078	static void mv_set_irq_coalescing(struct ata_host *host,
1079	unsigned int count, unsigned int usecs)	1079	unsigned int count, unsigned int usecs)
1080	{	1080	{
1081	struct mv_host_priv *hpriv = host->private_data;	1081	struct mv_host_priv *hpriv = host->private_data;
1082	void __iomem mmio = hpriv->base, hc_mmio;	1082	void __iomem mmio = hpriv->base, hc_mmio;
1083	u32 coal_enable = 0;	1083	u32 coal_enable = 0;
1084	unsigned long flags;	1084	unsigned long flags;
1085	unsigned int clks, is_dual_hc = hpriv->n_ports > MV_PORTS_PER_HC;	1085	unsigned int clks, is_dual_hc = hpriv->n_ports > MV_PORTS_PER_HC;
1086	const u32 coal_disable = PORTS_0_3_COAL_DONE \| PORTS_4_7_COAL_DONE \|	1086	const u32 coal_disable = PORTS_0_3_COAL_DONE \| PORTS_4_7_COAL_DONE \|
1087	ALL_PORTS_COAL_DONE;	1087	ALL_PORTS_COAL_DONE;
1088		1088
1089	/* Disable IRQ coalescing if either threshold is zero */	1089	/* Disable IRQ coalescing if either threshold is zero */
1090	if (!usecs \|\| !count) {	1090	if (!usecs \|\| !count) {
1091	clks = count = 0;	1091	clks = count = 0;
1092	} else {	1092	} else {
1093	/* Respect maximum limits of the hardware */	1093	/* Respect maximum limits of the hardware */
1094	clks = usecs * COAL_CLOCKS_PER_USEC;	1094	clks = usecs * COAL_CLOCKS_PER_USEC;
1095	if (clks > MAX_COAL_TIME_THRESHOLD)	1095	if (clks > MAX_COAL_TIME_THRESHOLD)
1096	clks = MAX_COAL_TIME_THRESHOLD;	1096	clks = MAX_COAL_TIME_THRESHOLD;
1097	if (count > MAX_COAL_IO_COUNT)	1097	if (count > MAX_COAL_IO_COUNT)
1098	count = MAX_COAL_IO_COUNT;	1098	count = MAX_COAL_IO_COUNT;
1099	}	1099	}
1100		1100
1101	spin_lock_irqsave(&host->lock, flags);	1101	spin_lock_irqsave(&host->lock, flags);
1102	mv_set_main_irq_mask(host, coal_disable, 0);	1102	mv_set_main_irq_mask(host, coal_disable, 0);
1103		1103
1104	if (is_dual_hc && !IS_GEN_I(hpriv)) {	1104	if (is_dual_hc && !IS_GEN_I(hpriv)) {
1105	/*	1105	/*
1106	* GEN_II/GEN_IIE with dual host controllers:	1106	* GEN_II/GEN_IIE with dual host controllers:
1107	* one set of global thresholds for the entire chip.	1107	* one set of global thresholds for the entire chip.
1108	*/	1108	*/
1109	writel(clks, mmio + IRQ_COAL_TIME_THRESHOLD);	1109	writel(clks, mmio + IRQ_COAL_TIME_THRESHOLD);
1110	writel(count, mmio + IRQ_COAL_IO_THRESHOLD);	1110	writel(count, mmio + IRQ_COAL_IO_THRESHOLD);
1111	/* clear leftover coal IRQ bit */	1111	/* clear leftover coal IRQ bit */
1112	writel(~ALL_PORTS_COAL_IRQ, mmio + IRQ_COAL_CAUSE);	1112	writel(~ALL_PORTS_COAL_IRQ, mmio + IRQ_COAL_CAUSE);
1113	if (count)	1113	if (count)
1114	coal_enable = ALL_PORTS_COAL_DONE;	1114	coal_enable = ALL_PORTS_COAL_DONE;
1115	clks = count = 0; /* force clearing of regular regs below */	1115	clks = count = 0; /* force clearing of regular regs below */
1116	}	1116	}
1117		1117
1118	/*	1118	/*
1119	* All chips: independent thresholds for each HC on the chip.	1119	* All chips: independent thresholds for each HC on the chip.
1120	*/	1120	*/
1121	hc_mmio = mv_hc_base_from_port(mmio, 0);	1121	hc_mmio = mv_hc_base_from_port(mmio, 0);
1122	writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD);	1122	writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD);
1123	writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD);	1123	writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD);
1124	writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE);	1124	writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE);
1125	if (count)	1125	if (count)
1126	coal_enable \|= PORTS_0_3_COAL_DONE;	1126	coal_enable \|= PORTS_0_3_COAL_DONE;
1127	if (is_dual_hc) {	1127	if (is_dual_hc) {
1128	hc_mmio = mv_hc_base_from_port(mmio, MV_PORTS_PER_HC);	1128	hc_mmio = mv_hc_base_from_port(mmio, MV_PORTS_PER_HC);
1129	writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD);	1129	writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD);
1130	writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD);	1130	writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD);
1131	writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE);	1131	writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE);
1132	if (count)	1132	if (count)
1133	coal_enable \|= PORTS_4_7_COAL_DONE;	1133	coal_enable \|= PORTS_4_7_COAL_DONE;
1134	}	1134	}
1135		1135
1136	mv_set_main_irq_mask(host, 0, coal_enable);	1136	mv_set_main_irq_mask(host, 0, coal_enable);
1137	spin_unlock_irqrestore(&host->lock, flags);	1137	spin_unlock_irqrestore(&host->lock, flags);
1138	}	1138	}
1139		1139
1140	/**	1140	/**
1141	* mv_start_edma - Enable eDMA engine	1141	* mv_start_edma - Enable eDMA engine
1142	* @base: port base address	1142	* @base: port base address
1143	* @pp: port private data	1143	* @pp: port private data
1144	*	1144	*
1145	* Verify the local cache of the eDMA state is accurate with a	1145	* Verify the local cache of the eDMA state is accurate with a
1146	* WARN_ON.	1146	* WARN_ON.
1147	*	1147	*
1148	* LOCKING:	1148	* LOCKING:
1149	* Inherited from caller.	1149	* Inherited from caller.
1150	*/	1150	*/
1151	static void mv_start_edma(struct ata_port ap, void __iomem port_mmio,	1151	static void mv_start_edma(struct ata_port ap, void __iomem port_mmio,
1152	struct mv_port_priv *pp, u8 protocol)	1152	struct mv_port_priv *pp, u8 protocol)
1153	{	1153	{
1154	int want_ncq = (protocol == ATA_PROT_NCQ);	1154	int want_ncq = (protocol == ATA_PROT_NCQ);
1155		1155
1156	if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {	1156	if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
1157	int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0);	1157	int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0);
1158	if (want_ncq != using_ncq)	1158	if (want_ncq != using_ncq)
1159	mv_stop_edma(ap);	1159	mv_stop_edma(ap);
1160	}	1160	}
1161	if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) {	1161	if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) {
1162	struct mv_host_priv *hpriv = ap->host->private_data;	1162	struct mv_host_priv *hpriv = ap->host->private_data;
1163		1163
1164	mv_edma_cfg(ap, want_ncq, 1);	1164	mv_edma_cfg(ap, want_ncq, 1);
1165		1165
1166	mv_set_edma_ptrs(port_mmio, hpriv, pp);	1166	mv_set_edma_ptrs(port_mmio, hpriv, pp);
1167	mv_clear_and_enable_port_irqs(ap, port_mmio, DONE_IRQ\|ERR_IRQ);	1167	mv_clear_and_enable_port_irqs(ap, port_mmio, DONE_IRQ\|ERR_IRQ);
1168		1168
1169	writelfl(EDMA_EN, port_mmio + EDMA_CMD);	1169	writelfl(EDMA_EN, port_mmio + EDMA_CMD);
1170	pp->pp_flags \|= MV_PP_FLAG_EDMA_EN;	1170	pp->pp_flags \|= MV_PP_FLAG_EDMA_EN;
1171	}	1171	}
1172	}	1172	}
1173		1173
1174	static void mv_wait_for_edma_empty_idle(struct ata_port *ap)	1174	static void mv_wait_for_edma_empty_idle(struct ata_port *ap)
1175	{	1175	{
1176	void __iomem *port_mmio = mv_ap_base(ap);	1176	void __iomem *port_mmio = mv_ap_base(ap);
1177	const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY \| EDMA_STATUS_IDLE);	1177	const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY \| EDMA_STATUS_IDLE);
1178	const int per_loop = 5, timeout = (15 * 1000 / per_loop);	1178	const int per_loop = 5, timeout = (15 * 1000 / per_loop);
1179	int i;	1179	int i;
1180		1180
1181	/*	1181	/*
1182	* Wait for the EDMA engine to finish transactions in progress.	1182	* Wait for the EDMA engine to finish transactions in progress.
1183	* No idea what a good "timeout" value might be, but measurements	1183	* No idea what a good "timeout" value might be, but measurements
1184	* indicate that it often requires hundreds of microseconds	1184	* indicate that it often requires hundreds of microseconds
1185	* with two drives in-use. So we use the 15msec value above	1185	* with two drives in-use. So we use the 15msec value above
1186	* as a rough guess at what even more drives might require.	1186	* as a rough guess at what even more drives might require.
1187	*/	1187	*/
1188	for (i = 0; i < timeout; ++i) {	1188	for (i = 0; i < timeout; ++i) {
1189	u32 edma_stat = readl(port_mmio + EDMA_STATUS);	1189	u32 edma_stat = readl(port_mmio + EDMA_STATUS);
1190	if ((edma_stat & empty_idle) == empty_idle)	1190	if ((edma_stat & empty_idle) == empty_idle)
1191	break;	1191	break;
1192	udelay(per_loop);	1192	udelay(per_loop);
1193	}	1193	}
1194	/* ata_port_printk(ap, KERN_INFO, "%s: %u+ usecs\n", __func__, i); */	1194	/* ata_port_printk(ap, KERN_INFO, "%s: %u+ usecs\n", __func__, i); */
1195	}	1195	}
1196		1196
1197	/**	1197	/**
1198	* mv_stop_edma_engine - Disable eDMA engine	1198	* mv_stop_edma_engine - Disable eDMA engine
1199	* @port_mmio: io base address	1199	* @port_mmio: io base address
1200	*	1200	*
1201	* LOCKING:	1201	* LOCKING:
1202	* Inherited from caller.	1202	* Inherited from caller.
1203	*/	1203	*/
1204	static int mv_stop_edma_engine(void __iomem *port_mmio)	1204	static int mv_stop_edma_engine(void __iomem *port_mmio)
1205	{	1205	{
1206	int i;	1206	int i;
1207		1207
1208	/* Disable eDMA. The disable bit auto clears. */	1208	/* Disable eDMA. The disable bit auto clears. */
1209	writelfl(EDMA_DS, port_mmio + EDMA_CMD);	1209	writelfl(EDMA_DS, port_mmio + EDMA_CMD);
1210		1210
1211	/* Wait for the chip to confirm eDMA is off. */	1211	/* Wait for the chip to confirm eDMA is off. */
1212	for (i = 10000; i > 0; i--) {	1212	for (i = 10000; i > 0; i--) {
1213	u32 reg = readl(port_mmio + EDMA_CMD);	1213	u32 reg = readl(port_mmio + EDMA_CMD);
1214	if (!(reg & EDMA_EN))	1214	if (!(reg & EDMA_EN))
1215	return 0;	1215	return 0;
1216	udelay(10);	1216	udelay(10);
1217	}	1217	}
1218	return -EIO;	1218	return -EIO;
1219	}	1219	}
1220		1220
1221	static int mv_stop_edma(struct ata_port *ap)	1221	static int mv_stop_edma(struct ata_port *ap)
1222	{	1222	{
1223	void __iomem *port_mmio = mv_ap_base(ap);	1223	void __iomem *port_mmio = mv_ap_base(ap);
1224	struct mv_port_priv *pp = ap->private_data;	1224	struct mv_port_priv *pp = ap->private_data;
1225	int err = 0;	1225	int err = 0;
1226		1226
1227	if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))	1227	if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
1228	return 0;	1228	return 0;
1229	pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;	1229	pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1230	mv_wait_for_edma_empty_idle(ap);	1230	mv_wait_for_edma_empty_idle(ap);
1231	if (mv_stop_edma_engine(port_mmio)) {	1231	if (mv_stop_edma_engine(port_mmio)) {
1232	ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n");	1232	ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n");
1233	err = -EIO;	1233	err = -EIO;
1234	}	1234	}
1235	mv_edma_cfg(ap, 0, 0);	1235	mv_edma_cfg(ap, 0, 0);
1236	return err;	1236	return err;
1237	}	1237	}
1238		1238
1239	#ifdef ATA_DEBUG	1239	#ifdef ATA_DEBUG
1240	static void mv_dump_mem(void __iomem *start, unsigned bytes)	1240	static void mv_dump_mem(void __iomem *start, unsigned bytes)
1241	{	1241	{
1242	int b, w;	1242	int b, w;
1243	for (b = 0; b < bytes; ) {	1243	for (b = 0; b < bytes; ) {
1244	DPRINTK("%p: ", start + b);	1244	DPRINTK("%p: ", start + b);
1245	for (w = 0; b < bytes && w < 4; w++) {	1245	for (w = 0; b < bytes && w < 4; w++) {
1246	printk("%08x ", readl(start + b));	1246	printk("%08x ", readl(start + b));
1247	b += sizeof(u32);	1247	b += sizeof(u32);
1248	}	1248	}
1249	printk("\n");	1249	printk("\n");
1250	}	1250	}
1251	}	1251	}
1252	#endif	1252	#endif
1253		1253
1254	static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)	1254	static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
1255	{	1255	{
1256	#ifdef ATA_DEBUG	1256	#ifdef ATA_DEBUG
1257	int b, w;	1257	int b, w;
1258	u32 dw;	1258	u32 dw;
1259	for (b = 0; b < bytes; ) {	1259	for (b = 0; b < bytes; ) {
1260	DPRINTK("%02x: ", b);	1260	DPRINTK("%02x: ", b);
1261	for (w = 0; b < bytes && w < 4; w++) {	1261	for (w = 0; b < bytes && w < 4; w++) {
1262	(void) pci_read_config_dword(pdev, b, &dw);	1262	(void) pci_read_config_dword(pdev, b, &dw);
1263	printk("%08x ", dw);	1263	printk("%08x ", dw);
1264	b += sizeof(u32);	1264	b += sizeof(u32);
1265	}	1265	}
1266	printk("\n");	1266	printk("\n");
1267	}	1267	}
1268	#endif	1268	#endif
1269	}	1269	}
1270	static void mv_dump_all_regs(void __iomem *mmio_base, int port,	1270	static void mv_dump_all_regs(void __iomem *mmio_base, int port,
1271	struct pci_dev *pdev)	1271	struct pci_dev *pdev)
1272	{	1272	{
1273	#ifdef ATA_DEBUG	1273	#ifdef ATA_DEBUG
1274	void __iomem *hc_base = mv_hc_base(mmio_base,	1274	void __iomem *hc_base = mv_hc_base(mmio_base,
1275	port >> MV_PORT_HC_SHIFT);	1275	port >> MV_PORT_HC_SHIFT);
1276	void __iomem *port_base;	1276	void __iomem *port_base;
1277	int start_port, num_ports, p, start_hc, num_hcs, hc;	1277	int start_port, num_ports, p, start_hc, num_hcs, hc;
1278		1278
1279	if (0 > port) {	1279	if (0 > port) {
1280	start_hc = start_port = 0;	1280	start_hc = start_port = 0;
1281	num_ports = 8; /* shld be benign for 4 port devs */	1281	num_ports = 8; /* shld be benign for 4 port devs */
1282	num_hcs = 2;	1282	num_hcs = 2;
1283	} else {	1283	} else {
1284	start_hc = port >> MV_PORT_HC_SHIFT;	1284	start_hc = port >> MV_PORT_HC_SHIFT;
1285	start_port = port;	1285	start_port = port;
1286	num_ports = num_hcs = 1;	1286	num_ports = num_hcs = 1;
1287	}	1287	}
1288	DPRINTK("All registers for port(s) %u-%u:\n", start_port,	1288	DPRINTK("All registers for port(s) %u-%u:\n", start_port,
1289	num_ports > 1 ? num_ports - 1 : start_port);	1289	num_ports > 1 ? num_ports - 1 : start_port);
1290		1290
1291	if (NULL != pdev) {	1291	if (NULL != pdev) {
1292	DPRINTK("PCI config space regs:\n");	1292	DPRINTK("PCI config space regs:\n");
1293	mv_dump_pci_cfg(pdev, 0x68);	1293	mv_dump_pci_cfg(pdev, 0x68);
1294	}	1294	}
1295	DPRINTK("PCI regs:\n");	1295	DPRINTK("PCI regs:\n");
1296	mv_dump_mem(mmio_base+0xc00, 0x3c);	1296	mv_dump_mem(mmio_base+0xc00, 0x3c);
1297	mv_dump_mem(mmio_base+0xd00, 0x34);	1297	mv_dump_mem(mmio_base+0xd00, 0x34);
1298	mv_dump_mem(mmio_base+0xf00, 0x4);	1298	mv_dump_mem(mmio_base+0xf00, 0x4);
1299	mv_dump_mem(mmio_base+0x1d00, 0x6c);	1299	mv_dump_mem(mmio_base+0x1d00, 0x6c);
1300	for (hc = start_hc; hc < start_hc + num_hcs; hc++) {	1300	for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
1301	hc_base = mv_hc_base(mmio_base, hc);	1301	hc_base = mv_hc_base(mmio_base, hc);
1302	DPRINTK("HC regs (HC %i):\n", hc);	1302	DPRINTK("HC regs (HC %i):\n", hc);
1303	mv_dump_mem(hc_base, 0x1c);	1303	mv_dump_mem(hc_base, 0x1c);
1304	}	1304	}
1305	for (p = start_port; p < start_port + num_ports; p++) {	1305	for (p = start_port; p < start_port + num_ports; p++) {
1306	port_base = mv_port_base(mmio_base, p);	1306	port_base = mv_port_base(mmio_base, p);
1307	DPRINTK("EDMA regs (port %i):\n", p);	1307	DPRINTK("EDMA regs (port %i):\n", p);
1308	mv_dump_mem(port_base, 0x54);	1308	mv_dump_mem(port_base, 0x54);
1309	DPRINTK("SATA regs (port %i):\n", p);	1309	DPRINTK("SATA regs (port %i):\n", p);
1310	mv_dump_mem(port_base+0x300, 0x60);	1310	mv_dump_mem(port_base+0x300, 0x60);
1311	}	1311	}
1312	#endif	1312	#endif
1313	}	1313	}
1314		1314
1315	static unsigned int mv_scr_offset(unsigned int sc_reg_in)	1315	static unsigned int mv_scr_offset(unsigned int sc_reg_in)
1316	{	1316	{
1317	unsigned int ofs;	1317	unsigned int ofs;
1318		1318
1319	switch (sc_reg_in) {	1319	switch (sc_reg_in) {
1320	case SCR_STATUS:	1320	case SCR_STATUS:
1321	case SCR_CONTROL:	1321	case SCR_CONTROL:
1322	case SCR_ERROR:	1322	case SCR_ERROR:
1323	ofs = SATA_STATUS + (sc_reg_in * sizeof(u32));	1323	ofs = SATA_STATUS + (sc_reg_in * sizeof(u32));
1324	break;	1324	break;
1325	case SCR_ACTIVE:	1325	case SCR_ACTIVE:
1326	ofs = SATA_ACTIVE; /* active is not with the others */	1326	ofs = SATA_ACTIVE; /* active is not with the others */
1327	break;	1327	break;
1328	default:	1328	default:
1329	ofs = 0xffffffffU;	1329	ofs = 0xffffffffU;
1330	break;	1330	break;
1331	}	1331	}
1332	return ofs;	1332	return ofs;
1333	}	1333	}
1334		1334
1335	static int mv_scr_read(struct ata_link link, unsigned int sc_reg_in, u32 val)	1335	static int mv_scr_read(struct ata_link link, unsigned int sc_reg_in, u32 val)
1336	{	1336	{
1337	unsigned int ofs = mv_scr_offset(sc_reg_in);	1337	unsigned int ofs = mv_scr_offset(sc_reg_in);
1338		1338
1339	if (ofs != 0xffffffffU) {	1339	if (ofs != 0xffffffffU) {
1340	*val = readl(mv_ap_base(link->ap) + ofs);	1340	*val = readl(mv_ap_base(link->ap) + ofs);
1341	return 0;	1341	return 0;
1342	} else	1342	} else
1343	return -EINVAL;	1343	return -EINVAL;
1344	}	1344	}
1345		1345
1346	static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)	1346	static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
1347	{	1347	{
1348	unsigned int ofs = mv_scr_offset(sc_reg_in);	1348	unsigned int ofs = mv_scr_offset(sc_reg_in);
1349		1349
1350	if (ofs != 0xffffffffU) {	1350	if (ofs != 0xffffffffU) {
1351	void __iomem *addr = mv_ap_base(link->ap) + ofs;	1351	void __iomem *addr = mv_ap_base(link->ap) + ofs;
1352	if (sc_reg_in == SCR_CONTROL) {	1352	if (sc_reg_in == SCR_CONTROL) {
1353	/*	1353	/*
1354	* Workaround for 88SX60x1 FEr SATA#26:	1354	* Workaround for 88SX60x1 FEr SATA#26:
1355	*	1355	*
1356	* COMRESETs have to take care not to accidently	1356	* COMRESETs have to take care not to accidently
1357	* put the drive to sleep when writing SCR_CONTROL.	1357	* put the drive to sleep when writing SCR_CONTROL.
1358	* Setting bits 12..15 prevents this problem.	1358	* Setting bits 12..15 prevents this problem.
1359	*	1359	*
1360	* So if we see an outbound COMMRESET, set those bits.	1360	* So if we see an outbound COMMRESET, set those bits.
1361	* Ditto for the followup write that clears the reset.	1361	* Ditto for the followup write that clears the reset.
1362	*	1362	*
1363	* The proprietary driver does this for	1363	* The proprietary driver does this for
1364	* all chip versions, and so do we.	1364	* all chip versions, and so do we.
1365	*/	1365	*/
1366	if ((val & 0xf) == 1 \|\| (readl(addr) & 0xf) == 1)	1366	if ((val & 0xf) == 1 \|\| (readl(addr) & 0xf) == 1)
1367	val \|= 0xf000;	1367	val \|= 0xf000;
1368	}	1368	}
1369	writelfl(val, addr);	1369	writelfl(val, addr);
1370	return 0;	1370	return 0;
1371	} else	1371	} else
1372	return -EINVAL;	1372	return -EINVAL;
1373	}	1373	}
1374		1374
1375	static void mv6_dev_config(struct ata_device *adev)	1375	static void mv6_dev_config(struct ata_device *adev)
1376	{	1376	{
1377	/*	1377	/*
1378	* Deal with Gen-II ("mv6") hardware quirks/restrictions:	1378	* Deal with Gen-II ("mv6") hardware quirks/restrictions:
1379	*	1379	*
1380	* Gen-II does not support NCQ over a port multiplier	1380	* Gen-II does not support NCQ over a port multiplier
1381	* (no FIS-based switching).	1381	* (no FIS-based switching).
1382	*/	1382	*/
1383	if (adev->flags & ATA_DFLAG_NCQ) {	1383	if (adev->flags & ATA_DFLAG_NCQ) {
1384	if (sata_pmp_attached(adev->link->ap)) {	1384	if (sata_pmp_attached(adev->link->ap)) {
1385	adev->flags &= ~ATA_DFLAG_NCQ;	1385	adev->flags &= ~ATA_DFLAG_NCQ;
1386	ata_dev_printk(adev, KERN_INFO,	1386	ata_dev_printk(adev, KERN_INFO,
1387	"NCQ disabled for command-based switching\n");	1387	"NCQ disabled for command-based switching\n");
1388	}	1388	}
1389	}	1389	}
1390	}	1390	}
1391		1391
1392	static int mv_qc_defer(struct ata_queued_cmd *qc)	1392	static int mv_qc_defer(struct ata_queued_cmd *qc)
1393	{	1393	{
1394	struct ata_link *link = qc->dev->link;	1394	struct ata_link *link = qc->dev->link;
1395	struct ata_port *ap = link->ap;	1395	struct ata_port *ap = link->ap;
1396	struct mv_port_priv *pp = ap->private_data;	1396	struct mv_port_priv *pp = ap->private_data;
1397		1397
1398	/*	1398	/*
1399	* Don't allow new commands if we're in a delayed EH state	1399	* Don't allow new commands if we're in a delayed EH state
1400	* for NCQ and/or FIS-based switching.	1400	* for NCQ and/or FIS-based switching.
1401	*/	1401	*/
1402	if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)	1402	if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
1403	return ATA_DEFER_PORT;	1403	return ATA_DEFER_PORT;
1404		1404
1405	/* PIO commands need exclusive link: no other commands [DMA or PIO]	1405	/* PIO commands need exclusive link: no other commands [DMA or PIO]
1406	* can run concurrently.	1406	* can run concurrently.
1407	* set excl_link when we want to send a PIO command in DMA mode	1407	* set excl_link when we want to send a PIO command in DMA mode
1408	* or a non-NCQ command in NCQ mode.	1408	* or a non-NCQ command in NCQ mode.
1409	* When we receive a command from that link, and there are no	1409	* When we receive a command from that link, and there are no
1410	* outstanding commands, mark a flag to clear excl_link and let	1410	* outstanding commands, mark a flag to clear excl_link and let
1411	* the command go through.	1411	* the command go through.
1412	*/	1412	*/
1413	if (unlikely(ap->excl_link)) {	1413	if (unlikely(ap->excl_link)) {
1414	if (link == ap->excl_link) {	1414	if (link == ap->excl_link) {
1415	if (ap->nr_active_links)	1415	if (ap->nr_active_links)
1416	return ATA_DEFER_PORT;	1416	return ATA_DEFER_PORT;
1417	qc->flags \|= ATA_QCFLAG_CLEAR_EXCL;	1417	qc->flags \|= ATA_QCFLAG_CLEAR_EXCL;
1418	return 0;	1418	return 0;
1419	} else	1419	} else
1420	return ATA_DEFER_PORT;	1420	return ATA_DEFER_PORT;
1421	}	1421	}
1422		1422
1423	/*	1423	/*
1424	* If the port is completely idle, then allow the new qc.	1424	* If the port is completely idle, then allow the new qc.
1425	*/	1425	*/
1426	if (ap->nr_active_links == 0)	1426	if (ap->nr_active_links == 0)
1427	return 0;	1427	return 0;
1428		1428
1429	/*	1429	/*
1430	* The port is operating in host queuing mode (EDMA) with NCQ	1430	* The port is operating in host queuing mode (EDMA) with NCQ
1431	* enabled, allow multiple NCQ commands. EDMA also allows	1431	* enabled, allow multiple NCQ commands. EDMA also allows
1432	* queueing multiple DMA commands but libata core currently	1432	* queueing multiple DMA commands but libata core currently
1433	* doesn't allow it.	1433	* doesn't allow it.
1434	*/	1434	*/
1435	if ((pp->pp_flags & MV_PP_FLAG_EDMA_EN) &&	1435	if ((pp->pp_flags & MV_PP_FLAG_EDMA_EN) &&
1436	(pp->pp_flags & MV_PP_FLAG_NCQ_EN)) {	1436	(pp->pp_flags & MV_PP_FLAG_NCQ_EN)) {
1437	if (ata_is_ncq(qc->tf.protocol))	1437	if (ata_is_ncq(qc->tf.protocol))
1438	return 0;	1438	return 0;
1439	else {	1439	else {
1440	ap->excl_link = link;	1440	ap->excl_link = link;
1441	return ATA_DEFER_PORT;	1441	return ATA_DEFER_PORT;
1442	}	1442	}
1443	}	1443	}
1444		1444
1445	return ATA_DEFER_PORT;	1445	return ATA_DEFER_PORT;
1446	}	1446	}
1447		1447
1448	static void mv_config_fbs(struct ata_port *ap, int want_ncq, int want_fbs)	1448	static void mv_config_fbs(struct ata_port *ap, int want_ncq, int want_fbs)
1449	{	1449	{
1450	struct mv_port_priv *pp = ap->private_data;	1450	struct mv_port_priv *pp = ap->private_data;
1451	void __iomem *port_mmio;	1451	void __iomem *port_mmio;
1452		1452
1453	u32 fiscfg, *old_fiscfg = &pp->cached.fiscfg;	1453	u32 fiscfg, *old_fiscfg = &pp->cached.fiscfg;
1454	u32 ltmode, *old_ltmode = &pp->cached.ltmode;	1454	u32 ltmode, *old_ltmode = &pp->cached.ltmode;
1455	u32 haltcond, *old_haltcond = &pp->cached.haltcond;	1455	u32 haltcond, *old_haltcond = &pp->cached.haltcond;
1456		1456
1457	ltmode = *old_ltmode & ~LTMODE_BIT8;	1457	ltmode = *old_ltmode & ~LTMODE_BIT8;
1458	haltcond = *old_haltcond \| EDMA_ERR_DEV;	1458	haltcond = *old_haltcond \| EDMA_ERR_DEV;
1459		1459
1460	if (want_fbs) {	1460	if (want_fbs) {
1461	fiscfg = *old_fiscfg \| FISCFG_SINGLE_SYNC;	1461	fiscfg = *old_fiscfg \| FISCFG_SINGLE_SYNC;
1462	ltmode = *old_ltmode \| LTMODE_BIT8;	1462	ltmode = *old_ltmode \| LTMODE_BIT8;
1463	if (want_ncq)	1463	if (want_ncq)
1464	haltcond &= ~EDMA_ERR_DEV;	1464	haltcond &= ~EDMA_ERR_DEV;
1465	else	1465	else
1466	fiscfg \|= FISCFG_WAIT_DEV_ERR;	1466	fiscfg \|= FISCFG_WAIT_DEV_ERR;
1467	} else {	1467	} else {
1468	fiscfg = *old_fiscfg & ~(FISCFG_SINGLE_SYNC \| FISCFG_WAIT_DEV_ERR);	1468	fiscfg = *old_fiscfg & ~(FISCFG_SINGLE_SYNC \| FISCFG_WAIT_DEV_ERR);
1469	}	1469	}
1470		1470
1471	port_mmio = mv_ap_base(ap);	1471	port_mmio = mv_ap_base(ap);
1472	mv_write_cached_reg(port_mmio + FISCFG, old_fiscfg, fiscfg);	1472	mv_write_cached_reg(port_mmio + FISCFG, old_fiscfg, fiscfg);
1473	mv_write_cached_reg(port_mmio + LTMODE, old_ltmode, ltmode);	1473	mv_write_cached_reg(port_mmio + LTMODE, old_ltmode, ltmode);
1474	mv_write_cached_reg(port_mmio + EDMA_HALTCOND, old_haltcond, haltcond);	1474	mv_write_cached_reg(port_mmio + EDMA_HALTCOND, old_haltcond, haltcond);
1475	}	1475	}
1476		1476
1477	static void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq)	1477	static void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq)
1478	{	1478	{
1479	struct mv_host_priv *hpriv = ap->host->private_data;	1479	struct mv_host_priv *hpriv = ap->host->private_data;
1480	u32 old, new;	1480	u32 old, new;
1481		1481
1482	/* workaround for 88SX60x1 FEr SATA#25 (part 1) */	1482	/* workaround for 88SX60x1 FEr SATA#25 (part 1) */
1483	old = readl(hpriv->base + GPIO_PORT_CTL);	1483	old = readl(hpriv->base + GPIO_PORT_CTL);
1484	if (want_ncq)	1484	if (want_ncq)
1485	new = old \| (1 << 22);	1485	new = old \| (1 << 22);
1486	else	1486	else
1487	new = old & ~(1 << 22);	1487	new = old & ~(1 << 22);
1488	if (new != old)	1488	if (new != old)
1489	writel(new, hpriv->base + GPIO_PORT_CTL);	1489	writel(new, hpriv->base + GPIO_PORT_CTL);
1490	}	1490	}
1491		1491
1492	/**	1492	/**
1493	* mv_bmdma_enable - set a magic bit on GEN_IIE to allow bmdma	1493	* mv_bmdma_enable - set a magic bit on GEN_IIE to allow bmdma
1494	* @ap: Port being initialized	1494	* @ap: Port being initialized
1495	*	1495	*
1496	* There are two DMA modes on these chips: basic DMA, and EDMA.	1496	* There are two DMA modes on these chips: basic DMA, and EDMA.
1497	*	1497	*
1498	* Bit-0 of the "EDMA RESERVED" register enables/disables use	1498	* Bit-0 of the "EDMA RESERVED" register enables/disables use
1499	* of basic DMA on the GEN_IIE versions of the chips.	1499	* of basic DMA on the GEN_IIE versions of the chips.
1500	*	1500	*
1501	* This bit survives EDMA resets, and must be set for basic DMA	1501	* This bit survives EDMA resets, and must be set for basic DMA
1502	* to function, and should be cleared when EDMA is active.	1502	* to function, and should be cleared when EDMA is active.
1503	*/	1503	*/
1504	static void mv_bmdma_enable_iie(struct ata_port *ap, int enable_bmdma)	1504	static void mv_bmdma_enable_iie(struct ata_port *ap, int enable_bmdma)
1505	{	1505	{
1506	struct mv_port_priv *pp = ap->private_data;	1506	struct mv_port_priv *pp = ap->private_data;
1507	u32 new, *old = &pp->cached.unknown_rsvd;	1507	u32 new, *old = &pp->cached.unknown_rsvd;
1508		1508
1509	if (enable_bmdma)	1509	if (enable_bmdma)
1510	new = *old \| 1;	1510	new = *old \| 1;
1511	else	1511	else
1512	new = *old & ~1;	1512	new = *old & ~1;
1513	mv_write_cached_reg(mv_ap_base(ap) + EDMA_UNKNOWN_RSVD, old, new);	1513	mv_write_cached_reg(mv_ap_base(ap) + EDMA_UNKNOWN_RSVD, old, new);
1514	}	1514	}
1515		1515
1516	/*	1516	/*
1517	* SOC chips have an issue whereby the HDD LEDs don't always blink	1517	* SOC chips have an issue whereby the HDD LEDs don't always blink
1518	* during I/O when NCQ is enabled. Enabling a special "LED blink" mode	1518	* during I/O when NCQ is enabled. Enabling a special "LED blink" mode
1519	* of the SOC takes care of it, generating a steady blink rate when	1519	* of the SOC takes care of it, generating a steady blink rate when
1520	* any drive on the chip is active.	1520	* any drive on the chip is active.
1521	*	1521	*
1522	* Unfortunately, the blink mode is a global hardware setting for the SOC,	1522	* Unfortunately, the blink mode is a global hardware setting for the SOC,
1523	* so we must use it whenever at least one port on the SOC has NCQ enabled.	1523	* so we must use it whenever at least one port on the SOC has NCQ enabled.
1524	*	1524	*
1525	* We turn "LED blink" off when NCQ is not in use anywhere, because the normal	1525	* We turn "LED blink" off when NCQ is not in use anywhere, because the normal
1526	* LED operation works then, and provides better (more accurate) feedback.	1526	* LED operation works then, and provides better (more accurate) feedback.
1527	*	1527	*
1528	* Note that this code assumes that an SOC never has more than one HC onboard.	1528	* Note that this code assumes that an SOC never has more than one HC onboard.
1529	*/	1529	*/
1530	static void mv_soc_led_blink_enable(struct ata_port *ap)	1530	static void mv_soc_led_blink_enable(struct ata_port *ap)
1531	{	1531	{
1532	struct ata_host *host = ap->host;	1532	struct ata_host *host = ap->host;
1533	struct mv_host_priv *hpriv = host->private_data;	1533	struct mv_host_priv *hpriv = host->private_data;
1534	void __iomem *hc_mmio;	1534	void __iomem *hc_mmio;
1535	u32 led_ctrl;	1535	u32 led_ctrl;
1536		1536
1537	if (hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN)	1537	if (hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN)
1538	return;	1538	return;
1539	hpriv->hp_flags \|= MV_HP_QUIRK_LED_BLINK_EN;	1539	hpriv->hp_flags \|= MV_HP_QUIRK_LED_BLINK_EN;
1540	hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no);	1540	hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no);
1541	led_ctrl = readl(hc_mmio + SOC_LED_CTRL);	1541	led_ctrl = readl(hc_mmio + SOC_LED_CTRL);
1542	writel(led_ctrl \| SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL);	1542	writel(led_ctrl \| SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL);
1543	}	1543	}
1544		1544
1545	static void mv_soc_led_blink_disable(struct ata_port *ap)	1545	static void mv_soc_led_blink_disable(struct ata_port *ap)
1546	{	1546	{
1547	struct ata_host *host = ap->host;	1547	struct ata_host *host = ap->host;
1548	struct mv_host_priv *hpriv = host->private_data;	1548	struct mv_host_priv *hpriv = host->private_data;
1549	void __iomem *hc_mmio;	1549	void __iomem *hc_mmio;
1550	u32 led_ctrl;	1550	u32 led_ctrl;
1551	unsigned int port;	1551	unsigned int port;
1552		1552
1553	if (!(hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN))	1553	if (!(hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN))
1554	return;	1554	return;
1555		1555
1556	/* disable led-blink only if no ports are using NCQ */	1556	/* disable led-blink only if no ports are using NCQ */
1557	for (port = 0; port < hpriv->n_ports; port++) {	1557	for (port = 0; port < hpriv->n_ports; port++) {
1558	struct ata_port *this_ap = host->ports[port];	1558	struct ata_port *this_ap = host->ports[port];
1559	struct mv_port_priv *pp = this_ap->private_data;	1559	struct mv_port_priv *pp = this_ap->private_data;
1560		1560
1561	if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)	1561	if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
1562	return;	1562	return;
1563	}	1563	}
1564		1564
1565	hpriv->hp_flags &= ~MV_HP_QUIRK_LED_BLINK_EN;	1565	hpriv->hp_flags &= ~MV_HP_QUIRK_LED_BLINK_EN;
1566	hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no);	1566	hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no);
1567	led_ctrl = readl(hc_mmio + SOC_LED_CTRL);	1567	led_ctrl = readl(hc_mmio + SOC_LED_CTRL);
1568	writel(led_ctrl & ~SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL);	1568	writel(led_ctrl & ~SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL);
1569	}	1569	}
1570		1570
1571	static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma)	1571	static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma)
1572	{	1572	{
1573	u32 cfg;	1573	u32 cfg;
1574	struct mv_port_priv *pp = ap->private_data;	1574	struct mv_port_priv *pp = ap->private_data;
1575	struct mv_host_priv *hpriv = ap->host->private_data;	1575	struct mv_host_priv *hpriv = ap->host->private_data;
1576	void __iomem *port_mmio = mv_ap_base(ap);	1576	void __iomem *port_mmio = mv_ap_base(ap);
1577		1577
1578	/* set up non-NCQ EDMA configuration */	1578	/* set up non-NCQ EDMA configuration */
1579	cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for all chips */	1579	cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for all chips */
1580	pp->pp_flags &=	1580	pp->pp_flags &=
1581	~(MV_PP_FLAG_FBS_EN \| MV_PP_FLAG_NCQ_EN \| MV_PP_FLAG_FAKE_ATA_BUSY);	1581	~(MV_PP_FLAG_FBS_EN \| MV_PP_FLAG_NCQ_EN \| MV_PP_FLAG_FAKE_ATA_BUSY);
1582		1582
1583	if (IS_GEN_I(hpriv))	1583	if (IS_GEN_I(hpriv))
1584	cfg \|= (1 << 8); /* enab config burst size mask */	1584	cfg \|= (1 << 8); /* enab config burst size mask */
1585		1585
1586	else if (IS_GEN_II(hpriv)) {	1586	else if (IS_GEN_II(hpriv)) {
1587	cfg \|= EDMA_CFG_RD_BRST_EXT \| EDMA_CFG_WR_BUFF_LEN;	1587	cfg \|= EDMA_CFG_RD_BRST_EXT \| EDMA_CFG_WR_BUFF_LEN;
1588	mv_60x1_errata_sata25(ap, want_ncq);	1588	mv_60x1_errata_sata25(ap, want_ncq);
1589		1589
1590	} else if (IS_GEN_IIE(hpriv)) {	1590	} else if (IS_GEN_IIE(hpriv)) {
1591	int want_fbs = sata_pmp_attached(ap);	1591	int want_fbs = sata_pmp_attached(ap);
1592	/*	1592	/*
1593	* Possible future enhancement:	1593	* Possible future enhancement:
1594	*	1594	*
1595	* The chip can use FBS with non-NCQ, if we allow it,	1595	* The chip can use FBS with non-NCQ, if we allow it,
1596	* But first we need to have the error handling in place	1596	* But first we need to have the error handling in place
1597	* for this mode (datasheet section 7.3.15.4.2.3).	1597	* for this mode (datasheet section 7.3.15.4.2.3).
1598	* So disallow non-NCQ FBS for now.	1598	* So disallow non-NCQ FBS for now.
1599	*/	1599	*/
1600	want_fbs &= want_ncq;	1600	want_fbs &= want_ncq;
1601		1601
1602	mv_config_fbs(ap, want_ncq, want_fbs);	1602	mv_config_fbs(ap, want_ncq, want_fbs);
1603		1603
1604	if (want_fbs) {	1604	if (want_fbs) {
1605	pp->pp_flags \|= MV_PP_FLAG_FBS_EN;	1605	pp->pp_flags \|= MV_PP_FLAG_FBS_EN;
1606	cfg \|= EDMA_CFG_EDMA_FBS; /* FIS-based switching */	1606	cfg \|= EDMA_CFG_EDMA_FBS; /* FIS-based switching */
1607	}	1607	}
1608		1608
1609	cfg \|= (1 << 23); /* do not mask PM field in rx'd FIS */	1609	cfg \|= (1 << 23); /* do not mask PM field in rx'd FIS */
1610	if (want_edma) {	1610	if (want_edma) {
1611	cfg \|= (1 << 22); /* enab 4-entry host queue cache */	1611	cfg \|= (1 << 22); /* enab 4-entry host queue cache */
1612	if (!IS_SOC(hpriv))	1612	if (!IS_SOC(hpriv))
1613	cfg \|= (1 << 18); /* enab early completion */	1613	cfg \|= (1 << 18); /* enab early completion */
1614	}	1614	}
1615	if (hpriv->hp_flags & MV_HP_CUT_THROUGH)	1615	if (hpriv->hp_flags & MV_HP_CUT_THROUGH)
1616	cfg \|= (1 << 17); /* enab cut-thru (dis stor&forwrd) */	1616	cfg \|= (1 << 17); /* enab cut-thru (dis stor&forwrd) */
1617	mv_bmdma_enable_iie(ap, !want_edma);	1617	mv_bmdma_enable_iie(ap, !want_edma);
1618		1618
1619	if (IS_SOC(hpriv)) {	1619	if (IS_SOC(hpriv)) {
1620	if (want_ncq)	1620	if (want_ncq)
1621	mv_soc_led_blink_enable(ap);	1621	mv_soc_led_blink_enable(ap);
1622	else	1622	else
1623	mv_soc_led_blink_disable(ap);	1623	mv_soc_led_blink_disable(ap);
1624	}	1624	}
1625	}	1625	}
1626		1626
1627	if (want_ncq) {	1627	if (want_ncq) {
1628	cfg \|= EDMA_CFG_NCQ;	1628	cfg \|= EDMA_CFG_NCQ;
1629	pp->pp_flags \|= MV_PP_FLAG_NCQ_EN;	1629	pp->pp_flags \|= MV_PP_FLAG_NCQ_EN;
1630	}	1630	}
1631		1631
1632	writelfl(cfg, port_mmio + EDMA_CFG);	1632	writelfl(cfg, port_mmio + EDMA_CFG);
1633	}	1633	}
1634		1634
1635	static void mv_port_free_dma_mem(struct ata_port *ap)	1635	static void mv_port_free_dma_mem(struct ata_port *ap)
1636	{	1636	{
1637	struct mv_host_priv *hpriv = ap->host->private_data;	1637	struct mv_host_priv *hpriv = ap->host->private_data;
1638	struct mv_port_priv *pp = ap->private_data;	1638	struct mv_port_priv *pp = ap->private_data;
1639	int tag;	1639	int tag;
1640		1640
1641	if (pp->crqb) {	1641	if (pp->crqb) {
1642	dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma);	1642	dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma);
1643	pp->crqb = NULL;	1643	pp->crqb = NULL;
1644	}	1644	}
1645	if (pp->crpb) {	1645	if (pp->crpb) {
1646	dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma);	1646	dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma);
1647	pp->crpb = NULL;	1647	pp->crpb = NULL;
1648	}	1648	}
1649	/*	1649	/*
1650	* For GEN_I, there's no NCQ, so we have only a single sg_tbl.	1650	* For GEN_I, there's no NCQ, so we have only a single sg_tbl.
1651	* For later hardware, we have one unique sg_tbl per NCQ tag.	1651	* For later hardware, we have one unique sg_tbl per NCQ tag.
1652	*/	1652	*/
1653	for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {	1653	for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1654	if (pp->sg_tbl[tag]) {	1654	if (pp->sg_tbl[tag]) {
1655	if (tag == 0 \|\| !IS_GEN_I(hpriv))	1655	if (tag == 0 \|\| !IS_GEN_I(hpriv))
1656	dma_pool_free(hpriv->sg_tbl_pool,	1656	dma_pool_free(hpriv->sg_tbl_pool,
1657	pp->sg_tbl[tag],	1657	pp->sg_tbl[tag],
1658	pp->sg_tbl_dma[tag]);	1658	pp->sg_tbl_dma[tag]);
1659	pp->sg_tbl[tag] = NULL;	1659	pp->sg_tbl[tag] = NULL;
1660	}	1660	}
1661	}	1661	}
1662	}	1662	}
1663		1663
1664	/**	1664	/**
1665	* mv_port_start - Port specific init/start routine.	1665	* mv_port_start - Port specific init/start routine.
1666	* @ap: ATA channel to manipulate	1666	* @ap: ATA channel to manipulate
1667	*	1667	*
1668	* Allocate and point to DMA memory, init port private memory,	1668	* Allocate and point to DMA memory, init port private memory,
1669	* zero indices.	1669	* zero indices.
1670	*	1670	*
1671	* LOCKING:	1671	* LOCKING:
1672	* Inherited from caller.	1672	* Inherited from caller.
1673	*/	1673	*/
1674	static int mv_port_start(struct ata_port *ap)	1674	static int mv_port_start(struct ata_port *ap)
1675	{	1675	{
1676	struct device *dev = ap->host->dev;	1676	struct device *dev = ap->host->dev;
1677	struct mv_host_priv *hpriv = ap->host->private_data;	1677	struct mv_host_priv *hpriv = ap->host->private_data;
1678	struct mv_port_priv *pp;	1678	struct mv_port_priv *pp;
1679	unsigned long flags;	1679	unsigned long flags;
1680	int tag;	1680	int tag;
1681		1681
1682	pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);	1682	pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1683	if (!pp)	1683	if (!pp)
1684	return -ENOMEM;	1684	return -ENOMEM;
1685	ap->private_data = pp;	1685	ap->private_data = pp;
1686		1686
1687	pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma);	1687	pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma);
1688	if (!pp->crqb)	1688	if (!pp->crqb)
1689	return -ENOMEM;	1689	return -ENOMEM;
1690	memset(pp->crqb, 0, MV_CRQB_Q_SZ);	1690	memset(pp->crqb, 0, MV_CRQB_Q_SZ);
1691		1691
1692	pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma);	1692	pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma);
1693	if (!pp->crpb)	1693	if (!pp->crpb)
1694	goto out_port_free_dma_mem;	1694	goto out_port_free_dma_mem;
1695	memset(pp->crpb, 0, MV_CRPB_Q_SZ);	1695	memset(pp->crpb, 0, MV_CRPB_Q_SZ);
1696		1696
1697	/* 6041/6081 Rev. "C0" (and newer) are okay with async notify */	1697	/* 6041/6081 Rev. "C0" (and newer) are okay with async notify */
1698	if (hpriv->hp_flags & MV_HP_ERRATA_60X1C0)	1698	if (hpriv->hp_flags & MV_HP_ERRATA_60X1C0)
1699	ap->flags \|= ATA_FLAG_AN;	1699	ap->flags \|= ATA_FLAG_AN;
1700	/*	1700	/*
1701	* For GEN_I, there's no NCQ, so we only allocate a single sg_tbl.	1701	* For GEN_I, there's no NCQ, so we only allocate a single sg_tbl.
1702	* For later hardware, we need one unique sg_tbl per NCQ tag.	1702	* For later hardware, we need one unique sg_tbl per NCQ tag.
1703	*/	1703	*/
1704	for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {	1704	for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1705	if (tag == 0 \|\| !IS_GEN_I(hpriv)) {	1705	if (tag == 0 \|\| !IS_GEN_I(hpriv)) {
1706	pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool,	1706	pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool,
1707	GFP_KERNEL, &pp->sg_tbl_dma[tag]);	1707	GFP_KERNEL, &pp->sg_tbl_dma[tag]);
1708	if (!pp->sg_tbl[tag])	1708	if (!pp->sg_tbl[tag])
1709	goto out_port_free_dma_mem;	1709	goto out_port_free_dma_mem;
1710	} else {	1710	} else {
1711	pp->sg_tbl[tag] = pp->sg_tbl[0];	1711	pp->sg_tbl[tag] = pp->sg_tbl[0];
1712	pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0];	1712	pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0];
1713	}	1713	}
1714	}	1714	}
1715		1715
1716	spin_lock_irqsave(ap->lock, flags);	1716	spin_lock_irqsave(ap->lock, flags);
1717	mv_save_cached_regs(ap);	1717	mv_save_cached_regs(ap);
1718	mv_edma_cfg(ap, 0, 0);	1718	mv_edma_cfg(ap, 0, 0);
1719	spin_unlock_irqrestore(ap->lock, flags);	1719	spin_unlock_irqrestore(ap->lock, flags);
1720		1720
1721	return 0;	1721	return 0;
1722		1722
1723	out_port_free_dma_mem:	1723	out_port_free_dma_mem:
1724	mv_port_free_dma_mem(ap);	1724	mv_port_free_dma_mem(ap);
1725	return -ENOMEM;	1725	return -ENOMEM;
1726	}	1726	}
1727		1727
1728	/**	1728	/**
1729	* mv_port_stop - Port specific cleanup/stop routine.	1729	* mv_port_stop - Port specific cleanup/stop routine.
1730	* @ap: ATA channel to manipulate	1730	* @ap: ATA channel to manipulate
1731	*	1731	*
1732	* Stop DMA, cleanup port memory.	1732	* Stop DMA, cleanup port memory.
1733	*	1733	*
1734	* LOCKING:	1734	* LOCKING:
1735	* This routine uses the host lock to protect the DMA stop.	1735	* This routine uses the host lock to protect the DMA stop.
1736	*/	1736	*/
1737	static void mv_port_stop(struct ata_port *ap)	1737	static void mv_port_stop(struct ata_port *ap)
1738	{	1738	{
1739	unsigned long flags;	1739	unsigned long flags;
1740		1740
1741	spin_lock_irqsave(ap->lock, flags);	1741	spin_lock_irqsave(ap->lock, flags);
1742	mv_stop_edma(ap);	1742	mv_stop_edma(ap);
1743	mv_enable_port_irqs(ap, 0);	1743	mv_enable_port_irqs(ap, 0);
1744	spin_unlock_irqrestore(ap->lock, flags);	1744	spin_unlock_irqrestore(ap->lock, flags);
1745	mv_port_free_dma_mem(ap);	1745	mv_port_free_dma_mem(ap);
1746	}	1746	}
1747		1747
1748	/**	1748	/**
1749	* mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries	1749	* mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
1750	* @qc: queued command whose SG list to source from	1750	* @qc: queued command whose SG list to source from
1751	*	1751	*
1752	* Populate the SG list and mark the last entry.	1752	* Populate the SG list and mark the last entry.
1753	*	1753	*
1754	* LOCKING:	1754	* LOCKING:
1755	* Inherited from caller.	1755	* Inherited from caller.
1756	*/	1756	*/
1757	static void mv_fill_sg(struct ata_queued_cmd *qc)	1757	static void mv_fill_sg(struct ata_queued_cmd *qc)
1758	{	1758	{
1759	struct mv_port_priv *pp = qc->ap->private_data;	1759	struct mv_port_priv *pp = qc->ap->private_data;
1760	struct scatterlist *sg;	1760	struct scatterlist *sg;
1761	struct mv_sg mv_sg, last_sg = NULL;	1761	struct mv_sg mv_sg, last_sg = NULL;
1762	unsigned int si;	1762	unsigned int si;
1763		1763
1764	mv_sg = pp->sg_tbl[qc->tag];	1764	mv_sg = pp->sg_tbl[qc->tag];
1765	for_each_sg(qc->sg, sg, qc->n_elem, si) {	1765	for_each_sg(qc->sg, sg, qc->n_elem, si) {
1766	dma_addr_t addr = sg_dma_address(sg);	1766	dma_addr_t addr = sg_dma_address(sg);
1767	u32 sg_len = sg_dma_len(sg);	1767	u32 sg_len = sg_dma_len(sg);
1768		1768
1769	while (sg_len) {	1769	while (sg_len) {
1770	u32 offset = addr & 0xffff;	1770	u32 offset = addr & 0xffff;
1771	u32 len = sg_len;	1771	u32 len = sg_len;
1772		1772
1773	if (offset + len > 0x10000)	1773	if (offset + len > 0x10000)
1774	len = 0x10000 - offset;	1774	len = 0x10000 - offset;
1775		1775
1776	mv_sg->addr = cpu_to_le32(addr & 0xffffffff);	1776	mv_sg->addr = cpu_to_le32(addr & 0xffffffff);
1777	mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);	1777	mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
1778	mv_sg->flags_size = cpu_to_le32(len & 0xffff);	1778	mv_sg->flags_size = cpu_to_le32(len & 0xffff);
1779	mv_sg->reserved = 0;	1779	mv_sg->reserved = 0;
1780		1780
1781	sg_len -= len;	1781	sg_len -= len;
1782	addr += len;	1782	addr += len;
1783		1783
1784	last_sg = mv_sg;	1784	last_sg = mv_sg;
1785	mv_sg++;	1785	mv_sg++;
1786	}	1786	}
1787	}	1787	}
1788		1788
1789	if (likely(last_sg))	1789	if (likely(last_sg))
1790	last_sg->flags_size \|= cpu_to_le32(EPRD_FLAG_END_OF_TBL);	1790	last_sg->flags_size \|= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
1791	mb(); /* ensure data structure is visible to the chipset */	1791	mb(); /* ensure data structure is visible to the chipset */
1792	}	1792	}
1793		1793
1794	static void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last)	1794	static void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last)
1795	{	1795	{
1796	u16 tmp = data \| (addr << CRQB_CMD_ADDR_SHIFT) \| CRQB_CMD_CS \|	1796	u16 tmp = data \| (addr << CRQB_CMD_ADDR_SHIFT) \| CRQB_CMD_CS \|
1797	(last ? CRQB_CMD_LAST : 0);	1797	(last ? CRQB_CMD_LAST : 0);
1798	*cmdw = cpu_to_le16(tmp);	1798	*cmdw = cpu_to_le16(tmp);
1799	}	1799	}
1800		1800
1801	/**	1801	/**
1802	* mv_sff_irq_clear - Clear hardware interrupt after DMA.	1802	* mv_sff_irq_clear - Clear hardware interrupt after DMA.
1803	* @ap: Port associated with this ATA transaction.	1803	* @ap: Port associated with this ATA transaction.
1804	*	1804	*
1805	* We need this only for ATAPI bmdma transactions,	1805	* We need this only for ATAPI bmdma transactions,
1806	* as otherwise we experience spurious interrupts	1806	* as otherwise we experience spurious interrupts
1807	* after libata-sff handles the bmdma interrupts.	1807	* after libata-sff handles the bmdma interrupts.
1808	*/	1808	*/
1809	static void mv_sff_irq_clear(struct ata_port *ap)	1809	static void mv_sff_irq_clear(struct ata_port *ap)
1810	{	1810	{
1811	mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), ERR_IRQ);	1811	mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), ERR_IRQ);
1812	}	1812	}
1813		1813
1814	/**	1814	/**
1815	* mv_check_atapi_dma - Filter ATAPI cmds which are unsuitable for DMA.	1815	* mv_check_atapi_dma - Filter ATAPI cmds which are unsuitable for DMA.
1816	* @qc: queued command to check for chipset/DMA compatibility.	1816	* @qc: queued command to check for chipset/DMA compatibility.
1817	*	1817	*
1818	* The bmdma engines cannot handle speculative data sizes	1818	* The bmdma engines cannot handle speculative data sizes
1819	* (bytecount under/over flow). So only allow DMA for	1819	* (bytecount under/over flow). So only allow DMA for
1820	* data transfer commands with known data sizes.	1820	* data transfer commands with known data sizes.
1821	*	1821	*
1822	* LOCKING:	1822	* LOCKING:
1823	* Inherited from caller.	1823	* Inherited from caller.
1824	*/	1824	*/
1825	static int mv_check_atapi_dma(struct ata_queued_cmd *qc)	1825	static int mv_check_atapi_dma(struct ata_queued_cmd *qc)
1826	{	1826	{
1827	struct scsi_cmnd *scmd = qc->scsicmd;	1827	struct scsi_cmnd *scmd = qc->scsicmd;
1828		1828
1829	if (scmd) {	1829	if (scmd) {
1830	switch (scmd->cmnd[0]) {	1830	switch (scmd->cmnd[0]) {
1831	case READ_6:	1831	case READ_6:
1832	case READ_10:	1832	case READ_10:
1833	case READ_12:	1833	case READ_12:
1834	case WRITE_6:	1834	case WRITE_6:
1835	case WRITE_10:	1835	case WRITE_10:
1836	case WRITE_12:	1836	case WRITE_12:
1837	case GPCMD_READ_CD:	1837	case GPCMD_READ_CD:
1838	case GPCMD_SEND_DVD_STRUCTURE:	1838	case GPCMD_SEND_DVD_STRUCTURE:
1839	case GPCMD_SEND_CUE_SHEET:	1839	case GPCMD_SEND_CUE_SHEET:
1840	return 0; /* DMA is safe */	1840	return 0; /* DMA is safe */
1841	}	1841	}
1842	}	1842	}
1843	return -EOPNOTSUPP; /* use PIO instead */	1843	return -EOPNOTSUPP; /* use PIO instead */
1844	}	1844	}
1845		1845
1846	/**	1846	/**
1847	* mv_bmdma_setup - Set up BMDMA transaction	1847	* mv_bmdma_setup - Set up BMDMA transaction
1848	* @qc: queued command to prepare DMA for.	1848	* @qc: queued command to prepare DMA for.
1849	*	1849	*
1850	* LOCKING:	1850	* LOCKING:
1851	* Inherited from caller.	1851	* Inherited from caller.
1852	*/	1852	*/
1853	static void mv_bmdma_setup(struct ata_queued_cmd *qc)	1853	static void mv_bmdma_setup(struct ata_queued_cmd *qc)
1854	{	1854	{
1855	struct ata_port *ap = qc->ap;	1855	struct ata_port *ap = qc->ap;
1856	void __iomem *port_mmio = mv_ap_base(ap);	1856	void __iomem *port_mmio = mv_ap_base(ap);
1857	struct mv_port_priv *pp = ap->private_data;	1857	struct mv_port_priv *pp = ap->private_data;
1858		1858
1859	mv_fill_sg(qc);	1859	mv_fill_sg(qc);
1860		1860
1861	/* clear all DMA cmd bits */	1861	/* clear all DMA cmd bits */
1862	writel(0, port_mmio + BMDMA_CMD);	1862	writel(0, port_mmio + BMDMA_CMD);
1863		1863
1864	/* load PRD table addr. */	1864	/* load PRD table addr. */
1865	writel((pp->sg_tbl_dma[qc->tag] >> 16) >> 16,	1865	writel((pp->sg_tbl_dma[qc->tag] >> 16) >> 16,
1866	port_mmio + BMDMA_PRD_HIGH);	1866	port_mmio + BMDMA_PRD_HIGH);
1867	writelfl(pp->sg_tbl_dma[qc->tag],	1867	writelfl(pp->sg_tbl_dma[qc->tag],
1868	port_mmio + BMDMA_PRD_LOW);	1868	port_mmio + BMDMA_PRD_LOW);
1869		1869
1870	/* issue r/w command */	1870	/* issue r/w command */
1871	ap->ops->sff_exec_command(ap, &qc->tf);	1871	ap->ops->sff_exec_command(ap, &qc->tf);
1872	}	1872	}
1873		1873
1874	/**	1874	/**
1875	* mv_bmdma_start - Start a BMDMA transaction	1875	* mv_bmdma_start - Start a BMDMA transaction
1876	* @qc: queued command to start DMA on.	1876	* @qc: queued command to start DMA on.
1877	*	1877	*
1878	* LOCKING:	1878	* LOCKING:
1879	* Inherited from caller.	1879	* Inherited from caller.
1880	*/	1880	*/
1881	static void mv_bmdma_start(struct ata_queued_cmd *qc)	1881	static void mv_bmdma_start(struct ata_queued_cmd *qc)
1882	{	1882	{
1883	struct ata_port *ap = qc->ap;	1883	struct ata_port *ap = qc->ap;
1884	void __iomem *port_mmio = mv_ap_base(ap);	1884	void __iomem *port_mmio = mv_ap_base(ap);
1885	unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);	1885	unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
1886	u32 cmd = (rw ? 0 : ATA_DMA_WR) \| ATA_DMA_START;	1886	u32 cmd = (rw ? 0 : ATA_DMA_WR) \| ATA_DMA_START;
1887		1887
1888	/* start host DMA transaction */	1888	/* start host DMA transaction */
1889	writelfl(cmd, port_mmio + BMDMA_CMD);	1889	writelfl(cmd, port_mmio + BMDMA_CMD);
1890	}	1890	}
1891		1891
1892	/**	1892	/**
1893	* mv_bmdma_stop - Stop BMDMA transfer	1893	* mv_bmdma_stop - Stop BMDMA transfer
1894	* @qc: queued command to stop DMA on.	1894	* @qc: queued command to stop DMA on.
1895	*	1895	*
1896	* Clears the ATA_DMA_START flag in the bmdma control register	1896	* Clears the ATA_DMA_START flag in the bmdma control register
1897	*	1897	*
1898	* LOCKING:	1898	* LOCKING:
1899	* Inherited from caller.	1899	* Inherited from caller.
1900	*/	1900	*/
1901	static void mv_bmdma_stop_ap(struct ata_port *ap)	1901	static void mv_bmdma_stop_ap(struct ata_port *ap)
1902	{	1902	{
1903	void __iomem *port_mmio = mv_ap_base(ap);	1903	void __iomem *port_mmio = mv_ap_base(ap);
1904	u32 cmd;	1904	u32 cmd;
1905		1905
1906	/* clear start/stop bit */	1906	/* clear start/stop bit */
1907	cmd = readl(port_mmio + BMDMA_CMD);	1907	cmd = readl(port_mmio + BMDMA_CMD);
1908	if (cmd & ATA_DMA_START) {	1908	if (cmd & ATA_DMA_START) {
1909	cmd &= ~ATA_DMA_START;	1909	cmd &= ~ATA_DMA_START;
1910	writelfl(cmd, port_mmio + BMDMA_CMD);	1910	writelfl(cmd, port_mmio + BMDMA_CMD);
1911		1911
1912	/* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */	1912	/* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
1913	ata_sff_dma_pause(ap);	1913	ata_sff_dma_pause(ap);
1914	}	1914	}
1915	}	1915	}
1916		1916
1917	static void mv_bmdma_stop(struct ata_queued_cmd *qc)	1917	static void mv_bmdma_stop(struct ata_queued_cmd *qc)
1918	{	1918	{
1919	mv_bmdma_stop_ap(qc->ap);	1919	mv_bmdma_stop_ap(qc->ap);
1920	}	1920	}
1921		1921
1922	/**	1922	/**
1923	* mv_bmdma_status - Read BMDMA status	1923	* mv_bmdma_status - Read BMDMA status
1924	* @ap: port for which to retrieve DMA status.	1924	* @ap: port for which to retrieve DMA status.
1925	*	1925	*
1926	* Read and return equivalent of the sff BMDMA status register.	1926	* Read and return equivalent of the sff BMDMA status register.
1927	*	1927	*
1928	* LOCKING:	1928	* LOCKING:
1929	* Inherited from caller.	1929	* Inherited from caller.
1930	*/	1930	*/
1931	static u8 mv_bmdma_status(struct ata_port *ap)	1931	static u8 mv_bmdma_status(struct ata_port *ap)
1932	{	1932	{
1933	void __iomem *port_mmio = mv_ap_base(ap);	1933	void __iomem *port_mmio = mv_ap_base(ap);
1934	u32 reg, status;	1934	u32 reg, status;
1935		1935
1936	/*	1936	/*
1937	* Other bits are valid only if ATA_DMA_ACTIVE==0,	1937	* Other bits are valid only if ATA_DMA_ACTIVE==0,
1938	* and the ATA_DMA_INTR bit doesn't exist.	1938	* and the ATA_DMA_INTR bit doesn't exist.
1939	*/	1939	*/
1940	reg = readl(port_mmio + BMDMA_STATUS);	1940	reg = readl(port_mmio + BMDMA_STATUS);
1941	if (reg & ATA_DMA_ACTIVE)	1941	if (reg & ATA_DMA_ACTIVE)
1942	status = ATA_DMA_ACTIVE;	1942	status = ATA_DMA_ACTIVE;
1943	else if (reg & ATA_DMA_ERR)	1943	else if (reg & ATA_DMA_ERR)
1944	status = (reg & ATA_DMA_ERR) \| ATA_DMA_INTR;	1944	status = (reg & ATA_DMA_ERR) \| ATA_DMA_INTR;
1945	else {	1945	else {
1946	/*	1946	/*
1947	* Just because DMA_ACTIVE is 0 (DMA completed),	1947	* Just because DMA_ACTIVE is 0 (DMA completed),
1948	* this does _not_ mean the device is "done".	1948	* this does _not_ mean the device is "done".
1949	* So we should not yet be signalling ATA_DMA_INTR	1949	* So we should not yet be signalling ATA_DMA_INTR
1950	* in some cases. Eg. DSM/TRIM, and perhaps others.	1950	* in some cases. Eg. DSM/TRIM, and perhaps others.
1951	*/	1951	*/
1952	mv_bmdma_stop_ap(ap);	1952	mv_bmdma_stop_ap(ap);
1953	if (ioread8(ap->ioaddr.altstatus_addr) & ATA_BUSY)	1953	if (ioread8(ap->ioaddr.altstatus_addr) & ATA_BUSY)
1954	status = 0;	1954	status = 0;
1955	else	1955	else
1956	status = ATA_DMA_INTR;	1956	status = ATA_DMA_INTR;
1957	}	1957	}
1958	return status;	1958	return status;
1959	}	1959	}
1960		1960
1961	static void mv_rw_multi_errata_sata24(struct ata_queued_cmd *qc)	1961	static void mv_rw_multi_errata_sata24(struct ata_queued_cmd *qc)
1962	{	1962	{
1963	struct ata_taskfile *tf = &qc->tf;	1963	struct ata_taskfile *tf = &qc->tf;
1964	/*	1964	/*
1965	* Workaround for 88SX60x1 FEr SATA#24.	1965	* Workaround for 88SX60x1 FEr SATA#24.
1966	*	1966	*
1967	* Chip may corrupt WRITEs if multi_count >= 4kB.	1967	* Chip may corrupt WRITEs if multi_count >= 4kB.
1968	* Note that READs are unaffected.	1968	* Note that READs are unaffected.
1969	*	1969	*
1970	* It's not clear if this errata really means "4K bytes",	1970	* It's not clear if this errata really means "4K bytes",
1971	* or if it always happens for multi_count > 7	1971	* or if it always happens for multi_count > 7
1972	* regardless of device sector_size.	1972	* regardless of device sector_size.
1973	*	1973	*
1974	* So, for safety, any write with multi_count > 7	1974	* So, for safety, any write with multi_count > 7
1975	* gets converted here into a regular PIO write instead:	1975	* gets converted here into a regular PIO write instead:
1976	*/	1976	*/
1977	if ((tf->flags & ATA_TFLAG_WRITE) && is_multi_taskfile(tf)) {	1977	if ((tf->flags & ATA_TFLAG_WRITE) && is_multi_taskfile(tf)) {
1978	if (qc->dev->multi_count > 7) {	1978	if (qc->dev->multi_count > 7) {
1979	switch (tf->command) {	1979	switch (tf->command) {
1980	case ATA_CMD_WRITE_MULTI:	1980	case ATA_CMD_WRITE_MULTI:
1981	tf->command = ATA_CMD_PIO_WRITE;	1981	tf->command = ATA_CMD_PIO_WRITE;
1982	break;	1982	break;
1983	case ATA_CMD_WRITE_MULTI_FUA_EXT:	1983	case ATA_CMD_WRITE_MULTI_FUA_EXT:
1984	tf->flags &= ~ATA_TFLAG_FUA; /* ugh */	1984	tf->flags &= ~ATA_TFLAG_FUA; /* ugh */
1985	/* fall through */	1985	/* fall through */
1986	case ATA_CMD_WRITE_MULTI_EXT:	1986	case ATA_CMD_WRITE_MULTI_EXT:
1987	tf->command = ATA_CMD_PIO_WRITE_EXT;	1987	tf->command = ATA_CMD_PIO_WRITE_EXT;
1988	break;	1988	break;
1989	}	1989	}
1990	}	1990	}
1991	}	1991	}
1992	}	1992	}
1993		1993
1994	/**	1994	/**
1995	* mv_qc_prep - Host specific command preparation.	1995	* mv_qc_prep - Host specific command preparation.
1996	* @qc: queued command to prepare	1996	* @qc: queued command to prepare
1997	*	1997	*
1998	* This routine simply redirects to the general purpose routine	1998	* This routine simply redirects to the general purpose routine
1999	* if command is not DMA. Else, it handles prep of the CRQB	1999	* if command is not DMA. Else, it handles prep of the CRQB
2000	* (command request block), does some sanity checking, and calls	2000	* (command request block), does some sanity checking, and calls
2001	* the SG load routine.	2001	* the SG load routine.
2002	*	2002	*
2003	* LOCKING:	2003	* LOCKING:
2004	* Inherited from caller.	2004	* Inherited from caller.
2005	*/	2005	*/
2006	static void mv_qc_prep(struct ata_queued_cmd *qc)	2006	static void mv_qc_prep(struct ata_queued_cmd *qc)
2007	{	2007	{
2008	struct ata_port *ap = qc->ap;	2008	struct ata_port *ap = qc->ap;
2009	struct mv_port_priv *pp = ap->private_data;	2009	struct mv_port_priv *pp = ap->private_data;
2010	__le16 *cw;	2010	__le16 *cw;
2011	struct ata_taskfile *tf = &qc->tf;	2011	struct ata_taskfile *tf = &qc->tf;
2012	u16 flags = 0;	2012	u16 flags = 0;
2013	unsigned in_index;	2013	unsigned in_index;
2014		2014
2015	switch (tf->protocol) {	2015	switch (tf->protocol) {
2016	case ATA_PROT_DMA:	2016	case ATA_PROT_DMA:
2017	if (tf->command == ATA_CMD_DSM)	2017	if (tf->command == ATA_CMD_DSM)
2018	return;	2018	return;
2019	/* fall-thru */	2019	/* fall-thru */
2020	case ATA_PROT_NCQ:	2020	case ATA_PROT_NCQ:
2021	break; /* continue below */	2021	break; /* continue below */
2022	case ATA_PROT_PIO:	2022	case ATA_PROT_PIO:
2023	mv_rw_multi_errata_sata24(qc);	2023	mv_rw_multi_errata_sata24(qc);
2024	return;	2024	return;
2025	default:	2025	default:
2026	return;	2026	return;
2027	}	2027	}
2028		2028
2029	/* Fill in command request block	2029	/* Fill in command request block
2030	*/	2030	*/
2031	if (!(tf->flags & ATA_TFLAG_WRITE))	2031	if (!(tf->flags & ATA_TFLAG_WRITE))
2032	flags \|= CRQB_FLAG_READ;	2032	flags \|= CRQB_FLAG_READ;
2033	WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);	2033	WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
2034	flags \|= qc->tag << CRQB_TAG_SHIFT;	2034	flags \|= qc->tag << CRQB_TAG_SHIFT;
2035	flags \|= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;	2035	flags \|= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
2036		2036
2037	/* get current queue index from software */	2037	/* get current queue index from software */
2038	in_index = pp->req_idx;	2038	in_index = pp->req_idx;
2039		2039
2040	pp->crqb[in_index].sg_addr =	2040	pp->crqb[in_index].sg_addr =
2041	cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);	2041	cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
2042	pp->crqb[in_index].sg_addr_hi =	2042	pp->crqb[in_index].sg_addr_hi =
2043	cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);	2043	cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
2044	pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);	2044	pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
2045		2045
2046	cw = &pp->crqb[in_index].ata_cmd[0];	2046	cw = &pp->crqb[in_index].ata_cmd[0];
2047		2047
2048	/* Sadly, the CRQB cannot accomodate all registers--there are	2048	/* Sadly, the CRQB cannot accomodate all registers--there are
2049	* only 11 bytes...so we must pick and choose required	2049	* only 11 bytes...so we must pick and choose required
2050	* registers based on the command. So, we drop feature and	2050	* registers based on the command. So, we drop feature and
2051	* hob_feature for [RW] DMA commands, but they are needed for	2051	* hob_feature for [RW] DMA commands, but they are needed for
2052	* NCQ. NCQ will drop hob_nsect, which is not needed there	2052	* NCQ. NCQ will drop hob_nsect, which is not needed there
2053	* (nsect is used only for the tag; feat/hob_feat hold true nsect).	2053	* (nsect is used only for the tag; feat/hob_feat hold true nsect).
2054	*/	2054	*/
2055	switch (tf->command) {	2055	switch (tf->command) {
2056	case ATA_CMD_READ:	2056	case ATA_CMD_READ:
2057	case ATA_CMD_READ_EXT:	2057	case ATA_CMD_READ_EXT:
2058	case ATA_CMD_WRITE:	2058	case ATA_CMD_WRITE:
2059	case ATA_CMD_WRITE_EXT:	2059	case ATA_CMD_WRITE_EXT:
2060	case ATA_CMD_WRITE_FUA_EXT:	2060	case ATA_CMD_WRITE_FUA_EXT:
2061	mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);	2061	mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
2062	break;	2062	break;
2063	case ATA_CMD_FPDMA_READ:	2063	case ATA_CMD_FPDMA_READ:
2064	case ATA_CMD_FPDMA_WRITE:	2064	case ATA_CMD_FPDMA_WRITE:
2065	mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);	2065	mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
2066	mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);	2066	mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
2067	break;	2067	break;
2068	default:	2068	default:
2069	/* The only other commands EDMA supports in non-queued and	2069	/* The only other commands EDMA supports in non-queued and
2070	* non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none	2070	* non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
2071	* of which are defined/used by Linux. If we get here, this	2071	* of which are defined/used by Linux. If we get here, this
2072	* driver needs work.	2072	* driver needs work.
2073	*	2073	*
2074	* FIXME: modify libata to give qc_prep a return value and	2074	* FIXME: modify libata to give qc_prep a return value and
2075	* return error here.	2075	* return error here.
2076	*/	2076	*/
2077	BUG_ON(tf->command);	2077	BUG_ON(tf->command);
2078	break;	2078	break;
2079	}	2079	}
2080	mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);	2080	mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
2081	mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);	2081	mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
2082	mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);	2082	mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
2083	mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);	2083	mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
2084	mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);	2084	mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
2085	mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);	2085	mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
2086	mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);	2086	mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
2087	mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);	2087	mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
2088	mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */	2088	mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
2089		2089
2090	if (!(qc->flags & ATA_QCFLAG_DMAMAP))	2090	if (!(qc->flags & ATA_QCFLAG_DMAMAP))
2091	return;	2091	return;
2092	mv_fill_sg(qc);	2092	mv_fill_sg(qc);
2093	}	2093	}
2094		2094
2095	/**	2095	/**
2096	* mv_qc_prep_iie - Host specific command preparation.	2096	* mv_qc_prep_iie - Host specific command preparation.
2097	* @qc: queued command to prepare	2097	* @qc: queued command to prepare
2098	*	2098	*
2099	* This routine simply redirects to the general purpose routine	2099	* This routine simply redirects to the general purpose routine
2100	* if command is not DMA. Else, it handles prep of the CRQB	2100	* if command is not DMA. Else, it handles prep of the CRQB
2101	* (command request block), does some sanity checking, and calls	2101	* (command request block), does some sanity checking, and calls
2102	* the SG load routine.	2102	* the SG load routine.
2103	*	2103	*
2104	* LOCKING:	2104	* LOCKING:
2105	* Inherited from caller.	2105	* Inherited from caller.
2106	*/	2106	*/
2107	static void mv_qc_prep_iie(struct ata_queued_cmd *qc)	2107	static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
2108	{	2108	{
2109	struct ata_port *ap = qc->ap;	2109	struct ata_port *ap = qc->ap;
2110	struct mv_port_priv *pp = ap->private_data;	2110	struct mv_port_priv *pp = ap->private_data;
2111	struct mv_crqb_iie *crqb;	2111	struct mv_crqb_iie *crqb;
2112	struct ata_taskfile *tf = &qc->tf;	2112	struct ata_taskfile *tf = &qc->tf;
2113	unsigned in_index;	2113	unsigned in_index;
2114	u32 flags = 0;	2114	u32 flags = 0;
2115		2115
2116	if ((tf->protocol != ATA_PROT_DMA) &&	2116	if ((tf->protocol != ATA_PROT_DMA) &&
2117	(tf->protocol != ATA_PROT_NCQ))	2117	(tf->protocol != ATA_PROT_NCQ))
2118	return;	2118	return;
2119	if (tf->command == ATA_CMD_DSM)	2119	if (tf->command == ATA_CMD_DSM)
2120	return; /* use bmdma for this */	2120	return; /* use bmdma for this */
2121		2121
2122	/* Fill in Gen IIE command request block */	2122	/* Fill in Gen IIE command request block */
2123	if (!(tf->flags & ATA_TFLAG_WRITE))	2123	if (!(tf->flags & ATA_TFLAG_WRITE))
2124	flags \|= CRQB_FLAG_READ;	2124	flags \|= CRQB_FLAG_READ;
2125		2125
2126	WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);	2126	WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
2127	flags \|= qc->tag << CRQB_TAG_SHIFT;	2127	flags \|= qc->tag << CRQB_TAG_SHIFT;
2128	flags \|= qc->tag << CRQB_HOSTQ_SHIFT;	2128	flags \|= qc->tag << CRQB_HOSTQ_SHIFT;
2129	flags \|= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;	2129	flags \|= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
2130		2130
2131	/* get current queue index from software */	2131	/* get current queue index from software */
2132	in_index = pp->req_idx;	2132	in_index = pp->req_idx;
2133		2133
2134	crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];	2134	crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
2135	crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);	2135	crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
2136	crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);	2136	crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
2137	crqb->flags = cpu_to_le32(flags);	2137	crqb->flags = cpu_to_le32(flags);
2138		2138
2139	crqb->ata_cmd[0] = cpu_to_le32(	2139	crqb->ata_cmd[0] = cpu_to_le32(
2140	(tf->command << 16) \|	2140	(tf->command << 16) \|
2141	(tf->feature << 24)	2141	(tf->feature << 24)
2142	);	2142	);
2143	crqb->ata_cmd[1] = cpu_to_le32(	2143	crqb->ata_cmd[1] = cpu_to_le32(
2144	(tf->lbal << 0) \|	2144	(tf->lbal << 0) \|
2145	(tf->lbam << 8) \|	2145	(tf->lbam << 8) \|
2146	(tf->lbah << 16) \|	2146	(tf->lbah << 16) \|
2147	(tf->device << 24)	2147	(tf->device << 24)
2148	);	2148	);
2149	crqb->ata_cmd[2] = cpu_to_le32(	2149	crqb->ata_cmd[2] = cpu_to_le32(
2150	(tf->hob_lbal << 0) \|	2150	(tf->hob_lbal << 0) \|
2151	(tf->hob_lbam << 8) \|	2151	(tf->hob_lbam << 8) \|
2152	(tf->hob_lbah << 16) \|	2152	(tf->hob_lbah << 16) \|
2153	(tf->hob_feature << 24)	2153	(tf->hob_feature << 24)
2154	);	2154	);
2155	crqb->ata_cmd[3] = cpu_to_le32(	2155	crqb->ata_cmd[3] = cpu_to_le32(
2156	(tf->nsect << 0) \|	2156	(tf->nsect << 0) \|
2157	(tf->hob_nsect << 8)	2157	(tf->hob_nsect << 8)
2158	);	2158	);
2159		2159
2160	if (!(qc->flags & ATA_QCFLAG_DMAMAP))	2160	if (!(qc->flags & ATA_QCFLAG_DMAMAP))
2161	return;	2161	return;
2162	mv_fill_sg(qc);	2162	mv_fill_sg(qc);
2163	}	2163	}
2164		2164
2165	/**	2165	/**
2166	* mv_sff_check_status - fetch device status, if valid	2166	* mv_sff_check_status - fetch device status, if valid
2167	* @ap: ATA port to fetch status from	2167	* @ap: ATA port to fetch status from
2168	*	2168	*
2169	* When using command issue via mv_qc_issue_fis(),	2169	* When using command issue via mv_qc_issue_fis(),
2170	* the initial ATA_BUSY state does not show up in the	2170	* the initial ATA_BUSY state does not show up in the
2171	* ATA status (shadow) register. This can confuse libata!	2171	* ATA status (shadow) register. This can confuse libata!
2172	*	2172	*
2173	* So we have a hook here to fake ATA_BUSY for that situation,	2173	* So we have a hook here to fake ATA_BUSY for that situation,
2174	* until the first time a BUSY, DRQ, or ERR bit is seen.	2174	* until the first time a BUSY, DRQ, or ERR bit is seen.
2175	*	2175	*
2176	* The rest of the time, it simply returns the ATA status register.	2176	* The rest of the time, it simply returns the ATA status register.
2177	*/	2177	*/
2178	static u8 mv_sff_check_status(struct ata_port *ap)	2178	static u8 mv_sff_check_status(struct ata_port *ap)
2179	{	2179	{
2180	u8 stat = ioread8(ap->ioaddr.status_addr);	2180	u8 stat = ioread8(ap->ioaddr.status_addr);
2181	struct mv_port_priv *pp = ap->private_data;	2181	struct mv_port_priv *pp = ap->private_data;
2182		2182
2183	if (pp->pp_flags & MV_PP_FLAG_FAKE_ATA_BUSY) {	2183	if (pp->pp_flags & MV_PP_FLAG_FAKE_ATA_BUSY) {
2184	if (stat & (ATA_BUSY \| ATA_DRQ \| ATA_ERR))	2184	if (stat & (ATA_BUSY \| ATA_DRQ \| ATA_ERR))
2185	pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY;	2185	pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY;
2186	else	2186	else
2187	stat = ATA_BUSY;	2187	stat = ATA_BUSY;
2188	}	2188	}
2189	return stat;	2189	return stat;
2190	}	2190	}
2191		2191
2192	/**	2192	/**
2193	* mv_send_fis - Send a FIS, using the "Vendor-Unique FIS" register	2193	* mv_send_fis - Send a FIS, using the "Vendor-Unique FIS" register
2194	* @fis: fis to be sent	2194	* @fis: fis to be sent
2195	* @nwords: number of 32-bit words in the fis	2195	* @nwords: number of 32-bit words in the fis
2196	*/	2196	*/
2197	static unsigned int mv_send_fis(struct ata_port ap, u32 fis, int nwords)	2197	static unsigned int mv_send_fis(struct ata_port ap, u32 fis, int nwords)
2198	{	2198	{
2199	void __iomem *port_mmio = mv_ap_base(ap);	2199	void __iomem *port_mmio = mv_ap_base(ap);
2200	u32 ifctl, old_ifctl, ifstat;	2200	u32 ifctl, old_ifctl, ifstat;
2201	int i, timeout = 200, final_word = nwords - 1;	2201	int i, timeout = 200, final_word = nwords - 1;
2202		2202
2203	/* Initiate FIS transmission mode */	2203	/* Initiate FIS transmission mode */
2204	old_ifctl = readl(port_mmio + SATA_IFCTL);	2204	old_ifctl = readl(port_mmio + SATA_IFCTL);
2205	ifctl = 0x100 \| (old_ifctl & 0xf);	2205	ifctl = 0x100 \| (old_ifctl & 0xf);
2206	writelfl(ifctl, port_mmio + SATA_IFCTL);	2206	writelfl(ifctl, port_mmio + SATA_IFCTL);
2207		2207
2208	/* Send all words of the FIS except for the final word */	2208	/* Send all words of the FIS except for the final word */
2209	for (i = 0; i < final_word; ++i)	2209	for (i = 0; i < final_word; ++i)
2210	writel(fis[i], port_mmio + VENDOR_UNIQUE_FIS);	2210	writel(fis[i], port_mmio + VENDOR_UNIQUE_FIS);
2211		2211
2212	/* Flag end-of-transmission, and then send the final word */	2212	/* Flag end-of-transmission, and then send the final word */
2213	writelfl(ifctl \| 0x200, port_mmio + SATA_IFCTL);	2213	writelfl(ifctl \| 0x200, port_mmio + SATA_IFCTL);
2214	writelfl(fis[final_word], port_mmio + VENDOR_UNIQUE_FIS);	2214	writelfl(fis[final_word], port_mmio + VENDOR_UNIQUE_FIS);
2215		2215
2216	/*	2216	/*
2217	* Wait for FIS transmission to complete.	2217	* Wait for FIS transmission to complete.
2218	* This typically takes just a single iteration.	2218	* This typically takes just a single iteration.
2219	*/	2219	*/
2220	do {	2220	do {
2221	ifstat = readl(port_mmio + SATA_IFSTAT);	2221	ifstat = readl(port_mmio + SATA_IFSTAT);
2222	} while (!(ifstat & 0x1000) && --timeout);	2222	} while (!(ifstat & 0x1000) && --timeout);
2223		2223
2224	/* Restore original port configuration */	2224	/* Restore original port configuration */
2225	writelfl(old_ifctl, port_mmio + SATA_IFCTL);	2225	writelfl(old_ifctl, port_mmio + SATA_IFCTL);
2226		2226
2227	/* See if it worked */	2227	/* See if it worked */
2228	if ((ifstat & 0x3000) != 0x1000) {	2228	if ((ifstat & 0x3000) != 0x1000) {
2229	ata_port_printk(ap, KERN_WARNING,	2229	ata_port_printk(ap, KERN_WARNING,
2230	"%s transmission error, ifstat=%08x\n",	2230	"%s transmission error, ifstat=%08x\n",
2231	__func__, ifstat);	2231	__func__, ifstat);
2232	return AC_ERR_OTHER;	2232	return AC_ERR_OTHER;
2233	}	2233	}
2234	return 0;	2234	return 0;
2235	}	2235	}
2236		2236
2237	/**	2237	/**
2238	* mv_qc_issue_fis - Issue a command directly as a FIS	2238	* mv_qc_issue_fis - Issue a command directly as a FIS
2239	* @qc: queued command to start	2239	* @qc: queued command to start
2240	*	2240	*
2241	* Note that the ATA shadow registers are not updated	2241	* Note that the ATA shadow registers are not updated
2242	* after command issue, so the device will appear "READY"	2242	* after command issue, so the device will appear "READY"
2243	* if polled, even while it is BUSY processing the command.	2243	* if polled, even while it is BUSY processing the command.
2244	*	2244	*
2245	* So we use a status hook to fake ATA_BUSY until the drive changes state.	2245	* So we use a status hook to fake ATA_BUSY until the drive changes state.
2246	*	2246	*
2247	* Note: we don't get updated shadow regs on completion	2247	* Note: we don't get updated shadow regs on completion
2248	* of non-data commands. So avoid sending them via this function,	2248	* of non-data commands. So avoid sending them via this function,
2249	* as they will appear to have completed immediately.	2249	* as they will appear to have completed immediately.
2250	*	2250	*
2251	* GEN_IIE has special registers that we could get the result tf from,	2251	* GEN_IIE has special registers that we could get the result tf from,
2252	* but earlier chipsets do not. For now, we ignore those registers.	2252	* but earlier chipsets do not. For now, we ignore those registers.
2253	*/	2253	*/
2254	static unsigned int mv_qc_issue_fis(struct ata_queued_cmd *qc)	2254	static unsigned int mv_qc_issue_fis(struct ata_queued_cmd *qc)
2255	{	2255	{
2256	struct ata_port *ap = qc->ap;	2256	struct ata_port *ap = qc->ap;
2257	struct mv_port_priv *pp = ap->private_data;	2257	struct mv_port_priv *pp = ap->private_data;
2258	struct ata_link *link = qc->dev->link;	2258	struct ata_link *link = qc->dev->link;
2259	u32 fis[5];	2259	u32 fis[5];
2260	int err = 0;	2260	int err = 0;
2261		2261
2262	ata_tf_to_fis(&qc->tf, link->pmp, 1, (void *)fis);	2262	ata_tf_to_fis(&qc->tf, link->pmp, 1, (void *)fis);
2263	err = mv_send_fis(ap, fis, ARRAY_SIZE(fis));	2263	err = mv_send_fis(ap, fis, ARRAY_SIZE(fis));
2264	if (err)	2264	if (err)
2265	return err;	2265	return err;
2266		2266
2267	switch (qc->tf.protocol) {	2267	switch (qc->tf.protocol) {
2268	case ATAPI_PROT_PIO:	2268	case ATAPI_PROT_PIO:
2269	pp->pp_flags \|= MV_PP_FLAG_FAKE_ATA_BUSY;	2269	pp->pp_flags \|= MV_PP_FLAG_FAKE_ATA_BUSY;
2270	/* fall through */	2270	/* fall through */
2271	case ATAPI_PROT_NODATA:	2271	case ATAPI_PROT_NODATA:
2272	ap->hsm_task_state = HSM_ST_FIRST;	2272	ap->hsm_task_state = HSM_ST_FIRST;
2273	break;	2273	break;
2274	case ATA_PROT_PIO:	2274	case ATA_PROT_PIO:
2275	pp->pp_flags \|= MV_PP_FLAG_FAKE_ATA_BUSY;	2275	pp->pp_flags \|= MV_PP_FLAG_FAKE_ATA_BUSY;
2276	if (qc->tf.flags & ATA_TFLAG_WRITE)	2276	if (qc->tf.flags & ATA_TFLAG_WRITE)
2277	ap->hsm_task_state = HSM_ST_FIRST;	2277	ap->hsm_task_state = HSM_ST_FIRST;
2278	else	2278	else
2279	ap->hsm_task_state = HSM_ST;	2279	ap->hsm_task_state = HSM_ST;
2280	break;	2280	break;
2281	default:	2281	default:
2282	ap->hsm_task_state = HSM_ST_LAST;	2282	ap->hsm_task_state = HSM_ST_LAST;
2283	break;	2283	break;
2284	}	2284	}
2285		2285
2286	if (qc->tf.flags & ATA_TFLAG_POLLING)	2286	if (qc->tf.flags & ATA_TFLAG_POLLING)
2287	ata_sff_queue_pio_task(ap, 0);	2287	ata_sff_queue_pio_task(link, 0);
2288	return 0;	2288	return 0;
2289	}	2289	}
2290		2290
2291	/**	2291	/**
2292	* mv_qc_issue - Initiate a command to the host	2292	* mv_qc_issue - Initiate a command to the host
2293	* @qc: queued command to start	2293	* @qc: queued command to start
2294	*	2294	*
2295	* This routine simply redirects to the general purpose routine	2295	* This routine simply redirects to the general purpose routine
2296	* if command is not DMA. Else, it sanity checks our local	2296	* if command is not DMA. Else, it sanity checks our local
2297	* caches of the request producer/consumer indices then enables	2297	* caches of the request producer/consumer indices then enables
2298	* DMA and bumps the request producer index.	2298	* DMA and bumps the request producer index.
2299	*	2299	*
2300	* LOCKING:	2300	* LOCKING:
2301	* Inherited from caller.	2301	* Inherited from caller.
2302	*/	2302	*/
2303	static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)	2303	static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
2304	{	2304	{
2305	static int limit_warnings = 10;	2305	static int limit_warnings = 10;
2306	struct ata_port *ap = qc->ap;	2306	struct ata_port *ap = qc->ap;
2307	void __iomem *port_mmio = mv_ap_base(ap);	2307	void __iomem *port_mmio = mv_ap_base(ap);
2308	struct mv_port_priv *pp = ap->private_data;	2308	struct mv_port_priv *pp = ap->private_data;
2309	u32 in_index;	2309	u32 in_index;
2310	unsigned int port_irqs;	2310	unsigned int port_irqs;
2311		2311
2312	pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY; /* paranoia */	2312	pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY; /* paranoia */
2313		2313
2314	switch (qc->tf.protocol) {	2314	switch (qc->tf.protocol) {
2315	case ATA_PROT_DMA:	2315	case ATA_PROT_DMA:
2316	if (qc->tf.command == ATA_CMD_DSM) {	2316	if (qc->tf.command == ATA_CMD_DSM) {
2317	if (!ap->ops->bmdma_setup) /* no bmdma on GEN_I */	2317	if (!ap->ops->bmdma_setup) /* no bmdma on GEN_I */
2318	return AC_ERR_OTHER;	2318	return AC_ERR_OTHER;
2319	break; /* use bmdma for this */	2319	break; /* use bmdma for this */
2320	}	2320	}
2321	/* fall thru */	2321	/* fall thru */
2322	case ATA_PROT_NCQ:	2322	case ATA_PROT_NCQ:
2323	mv_start_edma(ap, port_mmio, pp, qc->tf.protocol);	2323	mv_start_edma(ap, port_mmio, pp, qc->tf.protocol);
2324	pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK;	2324	pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK;
2325	in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;	2325	in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
2326		2326
2327	/* Write the request in pointer to kick the EDMA to life */	2327	/* Write the request in pointer to kick the EDMA to life */
2328	writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) \| in_index,	2328	writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) \| in_index,
2329	port_mmio + EDMA_REQ_Q_IN_PTR);	2329	port_mmio + EDMA_REQ_Q_IN_PTR);
2330	return 0;	2330	return 0;
2331		2331
2332	case ATA_PROT_PIO:	2332	case ATA_PROT_PIO:
2333	/*	2333	/*
2334	* Errata SATA#16, SATA#24: warn if multiple DRQs expected.	2334	* Errata SATA#16, SATA#24: warn if multiple DRQs expected.
2335	*	2335	*
2336	* Someday, we might implement special polling workarounds	2336	* Someday, we might implement special polling workarounds
2337	* for these, but it all seems rather unnecessary since we	2337	* for these, but it all seems rather unnecessary since we
2338	* normally use only DMA for commands which transfer more	2338	* normally use only DMA for commands which transfer more
2339	* than a single block of data.	2339	* than a single block of data.
2340	*	2340	*
2341	* Much of the time, this could just work regardless.	2341	* Much of the time, this could just work regardless.
2342	* So for now, just log the incident, and allow the attempt.	2342	* So for now, just log the incident, and allow the attempt.
2343	*/	2343	*/
2344	if (limit_warnings > 0 && (qc->nbytes / qc->sect_size) > 1) {	2344	if (limit_warnings > 0 && (qc->nbytes / qc->sect_size) > 1) {
2345	--limit_warnings;	2345	--limit_warnings;
2346	ata_link_printk(qc->dev->link, KERN_WARNING, DRV_NAME	2346	ata_link_printk(qc->dev->link, KERN_WARNING, DRV_NAME
2347	": attempting PIO w/multiple DRQ: "	2347	": attempting PIO w/multiple DRQ: "
2348	"this may fail due to h/w errata\n");	2348	"this may fail due to h/w errata\n");
2349	}	2349	}
2350	/* drop through */	2350	/* drop through */
2351	case ATA_PROT_NODATA:	2351	case ATA_PROT_NODATA:
2352	case ATAPI_PROT_PIO:	2352	case ATAPI_PROT_PIO:
2353	case ATAPI_PROT_NODATA:	2353	case ATAPI_PROT_NODATA:
2354	if (ap->flags & ATA_FLAG_PIO_POLLING)	2354	if (ap->flags & ATA_FLAG_PIO_POLLING)
2355	qc->tf.flags \|= ATA_TFLAG_POLLING;	2355	qc->tf.flags \|= ATA_TFLAG_POLLING;
2356	break;	2356	break;
2357	}	2357	}
2358		2358
2359	if (qc->tf.flags & ATA_TFLAG_POLLING)	2359	if (qc->tf.flags & ATA_TFLAG_POLLING)
2360	port_irqs = ERR_IRQ; /* mask device interrupt when polling */	2360	port_irqs = ERR_IRQ; /* mask device interrupt when polling */
2361	else	2361	else
2362	port_irqs = ERR_IRQ \| DONE_IRQ; /* unmask all interrupts */	2362	port_irqs = ERR_IRQ \| DONE_IRQ; /* unmask all interrupts */
2363		2363
2364	/*	2364	/*
2365	* We're about to send a non-EDMA capable command to the	2365	* We're about to send a non-EDMA capable command to the
2366	* port. Turn off EDMA so there won't be problems accessing	2366	* port. Turn off EDMA so there won't be problems accessing
2367	* shadow block, etc registers.	2367	* shadow block, etc registers.
2368	*/	2368	*/
2369	mv_stop_edma(ap);	2369	mv_stop_edma(ap);
2370	mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), port_irqs);	2370	mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), port_irqs);
2371	mv_pmp_select(ap, qc->dev->link->pmp);	2371	mv_pmp_select(ap, qc->dev->link->pmp);
2372		2372
2373	if (qc->tf.command == ATA_CMD_READ_LOG_EXT) {	2373	if (qc->tf.command == ATA_CMD_READ_LOG_EXT) {
2374	struct mv_host_priv *hpriv = ap->host->private_data;	2374	struct mv_host_priv *hpriv = ap->host->private_data;
2375	/*	2375	/*
2376	* Workaround for 88SX60x1 FEr SATA#25 (part 2).	2376	* Workaround for 88SX60x1 FEr SATA#25 (part 2).
2377	*	2377	*
2378	* After any NCQ error, the READ_LOG_EXT command	2378	* After any NCQ error, the READ_LOG_EXT command
2379	* from libata-eh must use mv_qc_issue_fis().	2379	* from libata-eh must use mv_qc_issue_fis().
2380	* Otherwise it might fail, due to chip errata.	2380	* Otherwise it might fail, due to chip errata.
2381	*	2381	*
2382	* Rather than special-case it, we'll just always	2382	* Rather than special-case it, we'll just always
2383	* use this method here for READ_LOG_EXT, making for	2383	* use this method here for READ_LOG_EXT, making for
2384	* easier testing.	2384	* easier testing.
2385	*/	2385	*/
2386	if (IS_GEN_II(hpriv))	2386	if (IS_GEN_II(hpriv))
2387	return mv_qc_issue_fis(qc);	2387	return mv_qc_issue_fis(qc);
2388	}	2388	}
2389	return ata_bmdma_qc_issue(qc);	2389	return ata_bmdma_qc_issue(qc);
2390	}	2390	}
2391		2391
2392	static struct ata_queued_cmd mv_get_active_qc(struct ata_port ap)	2392	static struct ata_queued_cmd mv_get_active_qc(struct ata_port ap)
2393	{	2393	{
2394	struct mv_port_priv *pp = ap->private_data;	2394	struct mv_port_priv *pp = ap->private_data;
2395	struct ata_queued_cmd *qc;	2395	struct ata_queued_cmd *qc;
2396		2396
2397	if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)	2397	if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
2398	return NULL;	2398	return NULL;
2399	qc = ata_qc_from_tag(ap, ap->link.active_tag);	2399	qc = ata_qc_from_tag(ap, ap->link.active_tag);
2400	if (qc && !(qc->tf.flags & ATA_TFLAG_POLLING))	2400	if (qc && !(qc->tf.flags & ATA_TFLAG_POLLING))
2401	return qc;	2401	return qc;
2402	return NULL;	2402	return NULL;
2403	}	2403	}
2404		2404
2405	static void mv_pmp_error_handler(struct ata_port *ap)	2405	static void mv_pmp_error_handler(struct ata_port *ap)
2406	{	2406	{
2407	unsigned int pmp, pmp_map;	2407	unsigned int pmp, pmp_map;
2408	struct mv_port_priv *pp = ap->private_data;	2408	struct mv_port_priv *pp = ap->private_data;
2409		2409
2410	if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) {	2410	if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) {
2411	/*	2411	/*
2412	* Perform NCQ error analysis on failed PMPs	2412	* Perform NCQ error analysis on failed PMPs
2413	* before we freeze the port entirely.	2413	* before we freeze the port entirely.
2414	*	2414	*
2415	* The failed PMPs are marked earlier by mv_pmp_eh_prep().	2415	* The failed PMPs are marked earlier by mv_pmp_eh_prep().
2416	*/	2416	*/
2417	pmp_map = pp->delayed_eh_pmp_map;	2417	pmp_map = pp->delayed_eh_pmp_map;
2418	pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH;	2418	pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH;
2419	for (pmp = 0; pmp_map != 0; pmp++) {	2419	for (pmp = 0; pmp_map != 0; pmp++) {
2420	unsigned int this_pmp = (1 << pmp);	2420	unsigned int this_pmp = (1 << pmp);
2421	if (pmp_map & this_pmp) {	2421	if (pmp_map & this_pmp) {
2422	struct ata_link *link = &ap->pmp_link[pmp];	2422	struct ata_link *link = &ap->pmp_link[pmp];
2423	pmp_map &= ~this_pmp;	2423	pmp_map &= ~this_pmp;
2424	ata_eh_analyze_ncq_error(link);	2424	ata_eh_analyze_ncq_error(link);
2425	}	2425	}
2426	}	2426	}
2427	ata_port_freeze(ap);	2427	ata_port_freeze(ap);
2428	}	2428	}
2429	sata_pmp_error_handler(ap);	2429	sata_pmp_error_handler(ap);
2430	}	2430	}
2431		2431
2432	static unsigned int mv_get_err_pmp_map(struct ata_port *ap)	2432	static unsigned int mv_get_err_pmp_map(struct ata_port *ap)
2433	{	2433	{
2434	void __iomem *port_mmio = mv_ap_base(ap);	2434	void __iomem *port_mmio = mv_ap_base(ap);
2435		2435
2436	return readl(port_mmio + SATA_TESTCTL) >> 16;	2436	return readl(port_mmio + SATA_TESTCTL) >> 16;
2437	}	2437	}
2438		2438
2439	static void mv_pmp_eh_prep(struct ata_port *ap, unsigned int pmp_map)	2439	static void mv_pmp_eh_prep(struct ata_port *ap, unsigned int pmp_map)
2440	{	2440	{
2441	struct ata_eh_info *ehi;	2441	struct ata_eh_info *ehi;
2442	unsigned int pmp;	2442	unsigned int pmp;
2443		2443
2444	/*	2444	/*
2445	* Initialize EH info for PMPs which saw device errors	2445	* Initialize EH info for PMPs which saw device errors
2446	*/	2446	*/
2447	ehi = &ap->link.eh_info;	2447	ehi = &ap->link.eh_info;
2448	for (pmp = 0; pmp_map != 0; pmp++) {	2448	for (pmp = 0; pmp_map != 0; pmp++) {
2449	unsigned int this_pmp = (1 << pmp);	2449	unsigned int this_pmp = (1 << pmp);
2450	if (pmp_map & this_pmp) {	2450	if (pmp_map & this_pmp) {
2451	struct ata_link *link = &ap->pmp_link[pmp];	2451	struct ata_link *link = &ap->pmp_link[pmp];
2452		2452
2453	pmp_map &= ~this_pmp;	2453	pmp_map &= ~this_pmp;
2454	ehi = &link->eh_info;	2454	ehi = &link->eh_info;
2455	ata_ehi_clear_desc(ehi);	2455	ata_ehi_clear_desc(ehi);
2456	ata_ehi_push_desc(ehi, "dev err");	2456	ata_ehi_push_desc(ehi, "dev err");
2457	ehi->err_mask \|= AC_ERR_DEV;	2457	ehi->err_mask \|= AC_ERR_DEV;
2458	ehi->action \|= ATA_EH_RESET;	2458	ehi->action \|= ATA_EH_RESET;
2459	ata_link_abort(link);	2459	ata_link_abort(link);
2460	}	2460	}
2461	}	2461	}
2462	}	2462	}
2463		2463
2464	static int mv_req_q_empty(struct ata_port *ap)	2464	static int mv_req_q_empty(struct ata_port *ap)
2465	{	2465	{
2466	void __iomem *port_mmio = mv_ap_base(ap);	2466	void __iomem *port_mmio = mv_ap_base(ap);
2467	u32 in_ptr, out_ptr;	2467	u32 in_ptr, out_ptr;
2468		2468
2469	in_ptr = (readl(port_mmio + EDMA_REQ_Q_IN_PTR)	2469	in_ptr = (readl(port_mmio + EDMA_REQ_Q_IN_PTR)
2470	>> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;	2470	>> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2471	out_ptr = (readl(port_mmio + EDMA_REQ_Q_OUT_PTR)	2471	out_ptr = (readl(port_mmio + EDMA_REQ_Q_OUT_PTR)
2472	>> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;	2472	>> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2473	return (in_ptr == out_ptr); /* 1 == queue_is_empty */	2473	return (in_ptr == out_ptr); /* 1 == queue_is_empty */
2474	}	2474	}
2475		2475
2476	static int mv_handle_fbs_ncq_dev_err(struct ata_port *ap)	2476	static int mv_handle_fbs_ncq_dev_err(struct ata_port *ap)
2477	{	2477	{
2478	struct mv_port_priv *pp = ap->private_data;	2478	struct mv_port_priv *pp = ap->private_data;
2479	int failed_links;	2479	int failed_links;
2480	unsigned int old_map, new_map;	2480	unsigned int old_map, new_map;
2481		2481
2482	/*	2482	/*
2483	* Device error during FBS+NCQ operation:	2483	* Device error during FBS+NCQ operation:
2484	*	2484	*
2485	* Set a port flag to prevent further I/O being enqueued.	2485	* Set a port flag to prevent further I/O being enqueued.
2486	* Leave the EDMA running to drain outstanding commands from this port.	2486	* Leave the EDMA running to drain outstanding commands from this port.
2487	* Perform the post-mortem/EH only when all responses are complete.	2487	* Perform the post-mortem/EH only when all responses are complete.
2488	* Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.2).	2488	* Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.2).
2489	*/	2489	*/
2490	if (!(pp->pp_flags & MV_PP_FLAG_DELAYED_EH)) {	2490	if (!(pp->pp_flags & MV_PP_FLAG_DELAYED_EH)) {
2491	pp->pp_flags \|= MV_PP_FLAG_DELAYED_EH;	2491	pp->pp_flags \|= MV_PP_FLAG_DELAYED_EH;
2492	pp->delayed_eh_pmp_map = 0;	2492	pp->delayed_eh_pmp_map = 0;
2493	}	2493	}
2494	old_map = pp->delayed_eh_pmp_map;	2494	old_map = pp->delayed_eh_pmp_map;
2495	new_map = old_map \| mv_get_err_pmp_map(ap);	2495	new_map = old_map \| mv_get_err_pmp_map(ap);
2496		2496
2497	if (old_map != new_map) {	2497	if (old_map != new_map) {
2498	pp->delayed_eh_pmp_map = new_map;	2498	pp->delayed_eh_pmp_map = new_map;
2499	mv_pmp_eh_prep(ap, new_map & ~old_map);	2499	mv_pmp_eh_prep(ap, new_map & ~old_map);
2500	}	2500	}
2501	failed_links = hweight16(new_map);	2501	failed_links = hweight16(new_map);
2502		2502
2503	ata_port_printk(ap, KERN_INFO, "%s: pmp_map=%04x qc_map=%04x "	2503	ata_port_printk(ap, KERN_INFO, "%s: pmp_map=%04x qc_map=%04x "
2504	"failed_links=%d nr_active_links=%d\n",	2504	"failed_links=%d nr_active_links=%d\n",
2505	__func__, pp->delayed_eh_pmp_map,	2505	__func__, pp->delayed_eh_pmp_map,
2506	ap->qc_active, failed_links,	2506	ap->qc_active, failed_links,
2507	ap->nr_active_links);	2507	ap->nr_active_links);
2508		2508
2509	if (ap->nr_active_links <= failed_links && mv_req_q_empty(ap)) {	2509	if (ap->nr_active_links <= failed_links && mv_req_q_empty(ap)) {
2510	mv_process_crpb_entries(ap, pp);	2510	mv_process_crpb_entries(ap, pp);
2511	mv_stop_edma(ap);	2511	mv_stop_edma(ap);
2512	mv_eh_freeze(ap);	2512	mv_eh_freeze(ap);
2513	ata_port_printk(ap, KERN_INFO, "%s: done\n", __func__);	2513	ata_port_printk(ap, KERN_INFO, "%s: done\n", __func__);
2514	return 1; /* handled */	2514	return 1; /* handled */
2515	}	2515	}
2516	ata_port_printk(ap, KERN_INFO, "%s: waiting\n", __func__);	2516	ata_port_printk(ap, KERN_INFO, "%s: waiting\n", __func__);
2517	return 1; /* handled */	2517	return 1; /* handled */
2518	}	2518	}
2519		2519
2520	static int mv_handle_fbs_non_ncq_dev_err(struct ata_port *ap)	2520	static int mv_handle_fbs_non_ncq_dev_err(struct ata_port *ap)
2521	{	2521	{
2522	/*	2522	/*
2523	* Possible future enhancement:	2523	* Possible future enhancement:
2524	*	2524	*
2525	* FBS+non-NCQ operation is not yet implemented.	2525	* FBS+non-NCQ operation is not yet implemented.
2526	* See related notes in mv_edma_cfg().	2526	* See related notes in mv_edma_cfg().
2527	*	2527	*
2528	* Device error during FBS+non-NCQ operation:	2528	* Device error during FBS+non-NCQ operation:
2529	*	2529	*
2530	* We need to snapshot the shadow registers for each failed command.	2530	* We need to snapshot the shadow registers for each failed command.
2531	* Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.3).	2531	* Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.3).
2532	*/	2532	*/
2533	return 0; /* not handled */	2533	return 0; /* not handled */
2534	}	2534	}
2535		2535
2536	static int mv_handle_dev_err(struct ata_port *ap, u32 edma_err_cause)	2536	static int mv_handle_dev_err(struct ata_port *ap, u32 edma_err_cause)
2537	{	2537	{
2538	struct mv_port_priv *pp = ap->private_data;	2538	struct mv_port_priv *pp = ap->private_data;
2539		2539
2540	if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))	2540	if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
2541	return 0; /* EDMA was not active: not handled */	2541	return 0; /* EDMA was not active: not handled */
2542	if (!(pp->pp_flags & MV_PP_FLAG_FBS_EN))	2542	if (!(pp->pp_flags & MV_PP_FLAG_FBS_EN))
2543	return 0; /* FBS was not active: not handled */	2543	return 0; /* FBS was not active: not handled */
2544		2544
2545	if (!(edma_err_cause & EDMA_ERR_DEV))	2545	if (!(edma_err_cause & EDMA_ERR_DEV))
2546	return 0; /* non DEV error: not handled */	2546	return 0; /* non DEV error: not handled */
2547	edma_err_cause &= ~EDMA_ERR_IRQ_TRANSIENT;	2547	edma_err_cause &= ~EDMA_ERR_IRQ_TRANSIENT;
2548	if (edma_err_cause & ~(EDMA_ERR_DEV \| EDMA_ERR_SELF_DIS))	2548	if (edma_err_cause & ~(EDMA_ERR_DEV \| EDMA_ERR_SELF_DIS))
2549	return 0; /* other problems: not handled */	2549	return 0; /* other problems: not handled */
2550		2550
2551	if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) {	2551	if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) {
2552	/*	2552	/*
2553	* EDMA should NOT have self-disabled for this case.	2553	* EDMA should NOT have self-disabled for this case.
2554	* If it did, then something is wrong elsewhere,	2554	* If it did, then something is wrong elsewhere,
2555	* and we cannot handle it here.	2555	* and we cannot handle it here.
2556	*/	2556	*/
2557	if (edma_err_cause & EDMA_ERR_SELF_DIS) {	2557	if (edma_err_cause & EDMA_ERR_SELF_DIS) {
2558	ata_port_printk(ap, KERN_WARNING,	2558	ata_port_printk(ap, KERN_WARNING,
2559	"%s: err_cause=0x%x pp_flags=0x%x\n",	2559	"%s: err_cause=0x%x pp_flags=0x%x\n",
2560	__func__, edma_err_cause, pp->pp_flags);	2560	__func__, edma_err_cause, pp->pp_flags);
2561	return 0; /* not handled */	2561	return 0; /* not handled */
2562	}	2562	}
2563	return mv_handle_fbs_ncq_dev_err(ap);	2563	return mv_handle_fbs_ncq_dev_err(ap);
2564	} else {	2564	} else {
2565	/*	2565	/*
2566	* EDMA should have self-disabled for this case.	2566	* EDMA should have self-disabled for this case.
2567	* If it did not, then something is wrong elsewhere,	2567	* If it did not, then something is wrong elsewhere,
2568	* and we cannot handle it here.	2568	* and we cannot handle it here.
2569	*/	2569	*/
2570	if (!(edma_err_cause & EDMA_ERR_SELF_DIS)) {	2570	if (!(edma_err_cause & EDMA_ERR_SELF_DIS)) {
2571	ata_port_printk(ap, KERN_WARNING,	2571	ata_port_printk(ap, KERN_WARNING,
2572	"%s: err_cause=0x%x pp_flags=0x%x\n",	2572	"%s: err_cause=0x%x pp_flags=0x%x\n",
2573	__func__, edma_err_cause, pp->pp_flags);	2573	__func__, edma_err_cause, pp->pp_flags);
2574	return 0; /* not handled */	2574	return 0; /* not handled */
2575	}	2575	}
2576	return mv_handle_fbs_non_ncq_dev_err(ap);	2576	return mv_handle_fbs_non_ncq_dev_err(ap);
2577	}	2577	}
2578	return 0; /* not handled */	2578	return 0; /* not handled */
2579	}	2579	}
2580		2580
2581	static void mv_unexpected_intr(struct ata_port *ap, int edma_was_enabled)	2581	static void mv_unexpected_intr(struct ata_port *ap, int edma_was_enabled)
2582	{	2582	{
2583	struct ata_eh_info *ehi = &ap->link.eh_info;	2583	struct ata_eh_info *ehi = &ap->link.eh_info;
2584	char *when = "idle";	2584	char *when = "idle";
2585		2585
2586	ata_ehi_clear_desc(ehi);	2586	ata_ehi_clear_desc(ehi);
2587	if (edma_was_enabled) {	2587	if (edma_was_enabled) {
2588	when = "EDMA enabled";	2588	when = "EDMA enabled";
2589	} else {	2589	} else {
2590	struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);	2590	struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
2591	if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))	2591	if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
2592	when = "polling";	2592	when = "polling";
2593	}	2593	}
2594	ata_ehi_push_desc(ehi, "unexpected device interrupt while %s", when);	2594	ata_ehi_push_desc(ehi, "unexpected device interrupt while %s", when);
2595	ehi->err_mask \|= AC_ERR_OTHER;	2595	ehi->err_mask \|= AC_ERR_OTHER;
2596	ehi->action \|= ATA_EH_RESET;	2596	ehi->action \|= ATA_EH_RESET;
2597	ata_port_freeze(ap);	2597	ata_port_freeze(ap);
2598	}	2598	}
2599		2599
2600	/**	2600	/**
2601	* mv_err_intr - Handle error interrupts on the port	2601	* mv_err_intr - Handle error interrupts on the port
2602	* @ap: ATA channel to manipulate	2602	* @ap: ATA channel to manipulate
2603	*	2603	*
2604	* Most cases require a full reset of the chip's state machine,	2604	* Most cases require a full reset of the chip's state machine,
2605	* which also performs a COMRESET.	2605	* which also performs a COMRESET.
2606	* Also, if the port disabled DMA, update our cached copy to match.	2606	* Also, if the port disabled DMA, update our cached copy to match.
2607	*	2607	*
2608	* LOCKING:	2608	* LOCKING:
2609	* Inherited from caller.	2609	* Inherited from caller.
2610	*/	2610	*/
2611	static void mv_err_intr(struct ata_port *ap)	2611	static void mv_err_intr(struct ata_port *ap)
2612	{	2612	{
2613	void __iomem *port_mmio = mv_ap_base(ap);	2613	void __iomem *port_mmio = mv_ap_base(ap);
2614	u32 edma_err_cause, eh_freeze_mask, serr = 0;	2614	u32 edma_err_cause, eh_freeze_mask, serr = 0;
2615	u32 fis_cause = 0;	2615	u32 fis_cause = 0;
2616	struct mv_port_priv *pp = ap->private_data;	2616	struct mv_port_priv *pp = ap->private_data;
2617	struct mv_host_priv *hpriv = ap->host->private_data;	2617	struct mv_host_priv *hpriv = ap->host->private_data;
2618	unsigned int action = 0, err_mask = 0;	2618	unsigned int action = 0, err_mask = 0;
2619	struct ata_eh_info *ehi = &ap->link.eh_info;	2619	struct ata_eh_info *ehi = &ap->link.eh_info;
2620	struct ata_queued_cmd *qc;	2620	struct ata_queued_cmd *qc;
2621	int abort = 0;	2621	int abort = 0;
2622		2622
2623	/*	2623	/*
2624	* Read and clear the SError and err_cause bits.	2624	* Read and clear the SError and err_cause bits.
2625	* For GenIIe, if EDMA_ERR_TRANS_IRQ_7 is set, we also must read/clear	2625	* For GenIIe, if EDMA_ERR_TRANS_IRQ_7 is set, we also must read/clear
2626	* the FIS_IRQ_CAUSE register before clearing edma_err_cause.	2626	* the FIS_IRQ_CAUSE register before clearing edma_err_cause.
2627	*/	2627	*/
2628	sata_scr_read(&ap->link, SCR_ERROR, &serr);	2628	sata_scr_read(&ap->link, SCR_ERROR, &serr);
2629	sata_scr_write_flush(&ap->link, SCR_ERROR, serr);	2629	sata_scr_write_flush(&ap->link, SCR_ERROR, serr);
2630		2630
2631	edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE);	2631	edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE);
2632	if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {	2632	if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
2633	fis_cause = readl(port_mmio + FIS_IRQ_CAUSE);	2633	fis_cause = readl(port_mmio + FIS_IRQ_CAUSE);
2634	writelfl(~fis_cause, port_mmio + FIS_IRQ_CAUSE);	2634	writelfl(~fis_cause, port_mmio + FIS_IRQ_CAUSE);
2635	}	2635	}
2636	writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE);	2636	writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE);
2637		2637
2638	if (edma_err_cause & EDMA_ERR_DEV) {	2638	if (edma_err_cause & EDMA_ERR_DEV) {
2639	/*	2639	/*
2640	* Device errors during FIS-based switching operation	2640	* Device errors during FIS-based switching operation
2641	* require special handling.	2641	* require special handling.
2642	*/	2642	*/
2643	if (mv_handle_dev_err(ap, edma_err_cause))	2643	if (mv_handle_dev_err(ap, edma_err_cause))
2644	return;	2644	return;
2645	}	2645	}
2646		2646
2647	qc = mv_get_active_qc(ap);	2647	qc = mv_get_active_qc(ap);
2648	ata_ehi_clear_desc(ehi);	2648	ata_ehi_clear_desc(ehi);
2649	ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x",	2649	ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x",
2650	edma_err_cause, pp->pp_flags);	2650	edma_err_cause, pp->pp_flags);
2651		2651
2652	if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {	2652	if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
2653	ata_ehi_push_desc(ehi, "fis_cause=%08x", fis_cause);	2653	ata_ehi_push_desc(ehi, "fis_cause=%08x", fis_cause);
2654	if (fis_cause & FIS_IRQ_CAUSE_AN) {	2654	if (fis_cause & FIS_IRQ_CAUSE_AN) {
2655	u32 ec = edma_err_cause &	2655	u32 ec = edma_err_cause &
2656	~(EDMA_ERR_TRANS_IRQ_7 \| EDMA_ERR_IRQ_TRANSIENT);	2656	~(EDMA_ERR_TRANS_IRQ_7 \| EDMA_ERR_IRQ_TRANSIENT);
2657	sata_async_notification(ap);	2657	sata_async_notification(ap);
2658	if (!ec)	2658	if (!ec)
2659	return; /* Just an AN; no need for the nukes */	2659	return; /* Just an AN; no need for the nukes */
2660	ata_ehi_push_desc(ehi, "SDB notify");	2660	ata_ehi_push_desc(ehi, "SDB notify");
2661	}	2661	}
2662	}	2662	}
2663	/*	2663	/*
2664	* All generations share these EDMA error cause bits:	2664	* All generations share these EDMA error cause bits:
2665	*/	2665	*/
2666	if (edma_err_cause & EDMA_ERR_DEV) {	2666	if (edma_err_cause & EDMA_ERR_DEV) {
2667	err_mask \|= AC_ERR_DEV;	2667	err_mask \|= AC_ERR_DEV;
2668	action \|= ATA_EH_RESET;	2668	action \|= ATA_EH_RESET;
2669	ata_ehi_push_desc(ehi, "dev error");	2669	ata_ehi_push_desc(ehi, "dev error");
2670	}	2670	}
2671	if (edma_err_cause & (EDMA_ERR_D_PAR \| EDMA_ERR_PRD_PAR \|	2671	if (edma_err_cause & (EDMA_ERR_D_PAR \| EDMA_ERR_PRD_PAR \|
2672	EDMA_ERR_CRQB_PAR \| EDMA_ERR_CRPB_PAR \|	2672	EDMA_ERR_CRQB_PAR \| EDMA_ERR_CRPB_PAR \|
2673	EDMA_ERR_INTRL_PAR)) {	2673	EDMA_ERR_INTRL_PAR)) {
2674	err_mask \|= AC_ERR_ATA_BUS;	2674	err_mask \|= AC_ERR_ATA_BUS;
2675	action \|= ATA_EH_RESET;	2675	action \|= ATA_EH_RESET;
2676	ata_ehi_push_desc(ehi, "parity error");	2676	ata_ehi_push_desc(ehi, "parity error");
2677	}	2677	}
2678	if (edma_err_cause & (EDMA_ERR_DEV_DCON \| EDMA_ERR_DEV_CON)) {	2678	if (edma_err_cause & (EDMA_ERR_DEV_DCON \| EDMA_ERR_DEV_CON)) {
2679	ata_ehi_hotplugged(ehi);	2679	ata_ehi_hotplugged(ehi);
2680	ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ?	2680	ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ?
2681	"dev disconnect" : "dev connect");	2681	"dev disconnect" : "dev connect");
2682	action \|= ATA_EH_RESET;	2682	action \|= ATA_EH_RESET;
2683	}	2683	}
2684		2684
2685	/*	2685	/*
2686	* Gen-I has a different SELF_DIS bit,	2686	* Gen-I has a different SELF_DIS bit,
2687	* different FREEZE bits, and no SERR bit:	2687	* different FREEZE bits, and no SERR bit:
2688	*/	2688	*/
2689	if (IS_GEN_I(hpriv)) {	2689	if (IS_GEN_I(hpriv)) {
2690	eh_freeze_mask = EDMA_EH_FREEZE_5;	2690	eh_freeze_mask = EDMA_EH_FREEZE_5;
2691	if (edma_err_cause & EDMA_ERR_SELF_DIS_5) {	2691	if (edma_err_cause & EDMA_ERR_SELF_DIS_5) {
2692	pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;	2692	pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
2693	ata_ehi_push_desc(ehi, "EDMA self-disable");	2693	ata_ehi_push_desc(ehi, "EDMA self-disable");
2694	}	2694	}
2695	} else {	2695	} else {
2696	eh_freeze_mask = EDMA_EH_FREEZE;	2696	eh_freeze_mask = EDMA_EH_FREEZE;
2697	if (edma_err_cause & EDMA_ERR_SELF_DIS) {	2697	if (edma_err_cause & EDMA_ERR_SELF_DIS) {
2698	pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;	2698	pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
2699	ata_ehi_push_desc(ehi, "EDMA self-disable");	2699	ata_ehi_push_desc(ehi, "EDMA self-disable");
2700	}	2700	}
2701	if (edma_err_cause & EDMA_ERR_SERR) {	2701	if (edma_err_cause & EDMA_ERR_SERR) {
2702	ata_ehi_push_desc(ehi, "SError=%08x", serr);	2702	ata_ehi_push_desc(ehi, "SError=%08x", serr);
2703	err_mask \|= AC_ERR_ATA_BUS;	2703	err_mask \|= AC_ERR_ATA_BUS;
2704	action \|= ATA_EH_RESET;	2704	action \|= ATA_EH_RESET;
2705	}	2705	}
2706	}	2706	}
2707		2707
2708	if (!err_mask) {	2708	if (!err_mask) {
2709	err_mask = AC_ERR_OTHER;	2709	err_mask = AC_ERR_OTHER;
2710	action \|= ATA_EH_RESET;	2710	action \|= ATA_EH_RESET;
2711	}	2711	}
2712		2712
2713	ehi->serror \|= serr;	2713	ehi->serror \|= serr;
2714	ehi->action \|= action;	2714	ehi->action \|= action;
2715		2715
2716	if (qc)	2716	if (qc)
2717	qc->err_mask \|= err_mask;	2717	qc->err_mask \|= err_mask;
2718	else	2718	else
2719	ehi->err_mask \|= err_mask;	2719	ehi->err_mask \|= err_mask;
2720		2720
2721	if (err_mask == AC_ERR_DEV) {	2721	if (err_mask == AC_ERR_DEV) {
2722	/*	2722	/*
2723	* Cannot do ata_port_freeze() here,	2723	* Cannot do ata_port_freeze() here,
2724	* because it would kill PIO access,	2724	* because it would kill PIO access,
2725	* which is needed for further diagnosis.	2725	* which is needed for further diagnosis.
2726	*/	2726	*/
2727	mv_eh_freeze(ap);	2727	mv_eh_freeze(ap);
2728	abort = 1;	2728	abort = 1;
2729	} else if (edma_err_cause & eh_freeze_mask) {	2729	} else if (edma_err_cause & eh_freeze_mask) {
2730	/*	2730	/*
2731	* Note to self: ata_port_freeze() calls ata_port_abort()	2731	* Note to self: ata_port_freeze() calls ata_port_abort()
2732	*/	2732	*/
2733	ata_port_freeze(ap);	2733	ata_port_freeze(ap);
2734	} else {	2734	} else {
2735	abort = 1;	2735	abort = 1;
2736	}	2736	}
2737		2737
2738	if (abort) {	2738	if (abort) {
2739	if (qc)	2739	if (qc)
2740	ata_link_abort(qc->dev->link);	2740	ata_link_abort(qc->dev->link);
2741	else	2741	else
2742	ata_port_abort(ap);	2742	ata_port_abort(ap);
2743	}	2743	}
2744	}	2744	}
2745		2745
2746	static void mv_process_crpb_response(struct ata_port *ap,	2746	static void mv_process_crpb_response(struct ata_port *ap,
2747	struct mv_crpb *response, unsigned int tag, int ncq_enabled)	2747	struct mv_crpb *response, unsigned int tag, int ncq_enabled)
2748	{	2748	{
2749	u8 ata_status;	2749	u8 ata_status;
2750	u16 edma_status = le16_to_cpu(response->flags);	2750	u16 edma_status = le16_to_cpu(response->flags);
2751	struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag);	2751	struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag);
2752		2752
2753	if (unlikely(!qc)) {	2753	if (unlikely(!qc)) {
2754	ata_port_printk(ap, KERN_ERR, "%s: no qc for tag=%d\n",	2754	ata_port_printk(ap, KERN_ERR, "%s: no qc for tag=%d\n",
2755	__func__, tag);	2755	__func__, tag);
2756	return;	2756	return;
2757	}	2757	}
2758		2758
2759	/*	2759	/*
2760	* edma_status from a response queue entry:	2760	* edma_status from a response queue entry:
2761	* LSB is from EDMA_ERR_IRQ_CAUSE (non-NCQ only).	2761	* LSB is from EDMA_ERR_IRQ_CAUSE (non-NCQ only).
2762	* MSB is saved ATA status from command completion.	2762	* MSB is saved ATA status from command completion.
2763	*/	2763	*/
2764	if (!ncq_enabled) {	2764	if (!ncq_enabled) {
2765	u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV;	2765	u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV;
2766	if (err_cause) {	2766	if (err_cause) {
2767	/*	2767	/*
2768	* Error will be seen/handled by	2768	* Error will be seen/handled by
2769	* mv_err_intr(). So do nothing at all here.	2769	* mv_err_intr(). So do nothing at all here.
2770	*/	2770	*/
2771	return;	2771	return;
2772	}	2772	}
2773	}	2773	}
2774	ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT;	2774	ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT;
2775	if (!ac_err_mask(ata_status))	2775	if (!ac_err_mask(ata_status))
2776	ata_qc_complete(qc);	2776	ata_qc_complete(qc);
2777	/* else: leave it for mv_err_intr() */	2777	/* else: leave it for mv_err_intr() */
2778	}	2778	}
2779		2779
2780	static void mv_process_crpb_entries(struct ata_port ap, struct mv_port_priv pp)	2780	static void mv_process_crpb_entries(struct ata_port ap, struct mv_port_priv pp)
2781	{	2781	{
2782	void __iomem *port_mmio = mv_ap_base(ap);	2782	void __iomem *port_mmio = mv_ap_base(ap);
2783	struct mv_host_priv *hpriv = ap->host->private_data;	2783	struct mv_host_priv *hpriv = ap->host->private_data;
2784	u32 in_index;	2784	u32 in_index;
2785	bool work_done = false;	2785	bool work_done = false;
2786	int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN);	2786	int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN);
2787		2787
2788	/* Get the hardware queue position index */	2788	/* Get the hardware queue position index */
2789	in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR)	2789	in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR)
2790	>> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;	2790	>> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2791		2791
2792	/* Process new responses from since the last time we looked */	2792	/* Process new responses from since the last time we looked */
2793	while (in_index != pp->resp_idx) {	2793	while (in_index != pp->resp_idx) {
2794	unsigned int tag;	2794	unsigned int tag;
2795	struct mv_crpb *response = &pp->crpb[pp->resp_idx];	2795	struct mv_crpb *response = &pp->crpb[pp->resp_idx];
2796		2796
2797	pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK;	2797	pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK;
2798		2798
2799	if (IS_GEN_I(hpriv)) {	2799	if (IS_GEN_I(hpriv)) {
2800	/* 50xx: no NCQ, only one command active at a time */	2800	/* 50xx: no NCQ, only one command active at a time */
2801	tag = ap->link.active_tag;	2801	tag = ap->link.active_tag;
2802	} else {	2802	} else {
2803	/* Gen II/IIE: get command tag from CRPB entry */	2803	/* Gen II/IIE: get command tag from CRPB entry */
2804	tag = le16_to_cpu(response->id) & 0x1f;	2804	tag = le16_to_cpu(response->id) & 0x1f;
2805	}	2805	}
2806	mv_process_crpb_response(ap, response, tag, ncq_enabled);	2806	mv_process_crpb_response(ap, response, tag, ncq_enabled);
2807	work_done = true;	2807	work_done = true;
2808	}	2808	}
2809		2809
2810	/* Update the software queue position index in hardware */	2810	/* Update the software queue position index in hardware */
2811	if (work_done)	2811	if (work_done)
2812	writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) \|	2812	writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) \|
2813	(pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT),	2813	(pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT),
2814	port_mmio + EDMA_RSP_Q_OUT_PTR);	2814	port_mmio + EDMA_RSP_Q_OUT_PTR);
2815	}	2815	}
2816		2816
2817	static void mv_port_intr(struct ata_port *ap, u32 port_cause)	2817	static void mv_port_intr(struct ata_port *ap, u32 port_cause)
2818	{	2818	{
2819	struct mv_port_priv *pp;	2819	struct mv_port_priv *pp;
2820	int edma_was_enabled;	2820	int edma_was_enabled;
2821		2821
2822	/*	2822	/*
2823	* Grab a snapshot of the EDMA_EN flag setting,	2823	* Grab a snapshot of the EDMA_EN flag setting,
2824	* so that we have a consistent view for this port,	2824	* so that we have a consistent view for this port,
2825	* even if something we call of our routines changes it.	2825	* even if something we call of our routines changes it.
2826	*/	2826	*/
2827	pp = ap->private_data;	2827	pp = ap->private_data;
2828	edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN);	2828	edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN);
2829	/*	2829	/*
2830	* Process completed CRPB response(s) before other events.	2830	* Process completed CRPB response(s) before other events.
2831	*/	2831	*/
2832	if (edma_was_enabled && (port_cause & DONE_IRQ)) {	2832	if (edma_was_enabled && (port_cause & DONE_IRQ)) {
2833	mv_process_crpb_entries(ap, pp);	2833	mv_process_crpb_entries(ap, pp);
2834	if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)	2834	if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
2835	mv_handle_fbs_ncq_dev_err(ap);	2835	mv_handle_fbs_ncq_dev_err(ap);
2836	}	2836	}
2837	/*	2837	/*
2838	* Handle chip-reported errors, or continue on to handle PIO.	2838	* Handle chip-reported errors, or continue on to handle PIO.
2839	*/	2839	*/
2840	if (unlikely(port_cause & ERR_IRQ)) {	2840	if (unlikely(port_cause & ERR_IRQ)) {
2841	mv_err_intr(ap);	2841	mv_err_intr(ap);
2842	} else if (!edma_was_enabled) {	2842	} else if (!edma_was_enabled) {
2843	struct ata_queued_cmd *qc = mv_get_active_qc(ap);	2843	struct ata_queued_cmd *qc = mv_get_active_qc(ap);
2844	if (qc)	2844	if (qc)
2845	ata_bmdma_port_intr(ap, qc);	2845	ata_bmdma_port_intr(ap, qc);
2846	else	2846	else
2847	mv_unexpected_intr(ap, edma_was_enabled);	2847	mv_unexpected_intr(ap, edma_was_enabled);
2848	}	2848	}
2849	}	2849	}
2850		2850
2851	/**	2851	/**
2852	* mv_host_intr - Handle all interrupts on the given host controller	2852	* mv_host_intr - Handle all interrupts on the given host controller
2853	* @host: host specific structure	2853	* @host: host specific structure
2854	* @main_irq_cause: Main interrupt cause register for the chip.	2854	* @main_irq_cause: Main interrupt cause register for the chip.
2855	*	2855	*
2856	* LOCKING:	2856	* LOCKING:
2857	* Inherited from caller.	2857	* Inherited from caller.
2858	*/	2858	*/
2859	static int mv_host_intr(struct ata_host *host, u32 main_irq_cause)	2859	static int mv_host_intr(struct ata_host *host, u32 main_irq_cause)
2860	{	2860	{
2861	struct mv_host_priv *hpriv = host->private_data;	2861	struct mv_host_priv *hpriv = host->private_data;
2862	void __iomem mmio = hpriv->base, hc_mmio;	2862	void __iomem mmio = hpriv->base, hc_mmio;
2863	unsigned int handled = 0, port;	2863	unsigned int handled = 0, port;
2864		2864
2865	/* If asserted, clear the "all ports" IRQ coalescing bit */	2865	/* If asserted, clear the "all ports" IRQ coalescing bit */
2866	if (main_irq_cause & ALL_PORTS_COAL_DONE)	2866	if (main_irq_cause & ALL_PORTS_COAL_DONE)
2867	writel(~ALL_PORTS_COAL_IRQ, mmio + IRQ_COAL_CAUSE);	2867	writel(~ALL_PORTS_COAL_IRQ, mmio + IRQ_COAL_CAUSE);
2868		2868
2869	for (port = 0; port < hpriv->n_ports; port++) {	2869	for (port = 0; port < hpriv->n_ports; port++) {
2870	struct ata_port *ap = host->ports[port];	2870	struct ata_port *ap = host->ports[port];
2871	unsigned int p, shift, hardport, port_cause;	2871	unsigned int p, shift, hardport, port_cause;
2872		2872
2873	MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);	2873	MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
2874	/*	2874	/*
2875	* Each hc within the host has its own hc_irq_cause register,	2875	* Each hc within the host has its own hc_irq_cause register,
2876	* where the interrupting ports bits get ack'd.	2876	* where the interrupting ports bits get ack'd.
2877	*/	2877	*/
2878	if (hardport == 0) { /* first port on this hc ? */	2878	if (hardport == 0) { /* first port on this hc ? */
2879	u32 hc_cause = (main_irq_cause >> shift) & HC0_IRQ_PEND;	2879	u32 hc_cause = (main_irq_cause >> shift) & HC0_IRQ_PEND;
2880	u32 port_mask, ack_irqs;	2880	u32 port_mask, ack_irqs;
2881	/*	2881	/*
2882	* Skip this entire hc if nothing pending for any ports	2882	* Skip this entire hc if nothing pending for any ports
2883	*/	2883	*/
2884	if (!hc_cause) {	2884	if (!hc_cause) {
2885	port += MV_PORTS_PER_HC - 1;	2885	port += MV_PORTS_PER_HC - 1;
2886	continue;	2886	continue;
2887	}	2887	}
2888	/*	2888	/*
2889	* We don't need/want to read the hc_irq_cause register,	2889	* We don't need/want to read the hc_irq_cause register,
2890	* because doing so hurts performance, and	2890	* because doing so hurts performance, and
2891	* main_irq_cause already gives us everything we need.	2891	* main_irq_cause already gives us everything we need.
2892	*	2892	*
2893	* But we do have to write to the hc_irq_cause to ack	2893	* But we do have to write to the hc_irq_cause to ack
2894	* the ports that we are handling this time through.	2894	* the ports that we are handling this time through.
2895	*	2895	*
2896	* This requires that we create a bitmap for those	2896	* This requires that we create a bitmap for those
2897	* ports which interrupted us, and use that bitmap	2897	* ports which interrupted us, and use that bitmap
2898	* to ack (only) those ports via hc_irq_cause.	2898	* to ack (only) those ports via hc_irq_cause.
2899	*/	2899	*/
2900	ack_irqs = 0;	2900	ack_irqs = 0;
2901	if (hc_cause & PORTS_0_3_COAL_DONE)	2901	if (hc_cause & PORTS_0_3_COAL_DONE)
2902	ack_irqs = HC_COAL_IRQ;	2902	ack_irqs = HC_COAL_IRQ;
2903	for (p = 0; p < MV_PORTS_PER_HC; ++p) {	2903	for (p = 0; p < MV_PORTS_PER_HC; ++p) {
2904	if ((port + p) >= hpriv->n_ports)	2904	if ((port + p) >= hpriv->n_ports)
2905	break;	2905	break;
2906	port_mask = (DONE_IRQ \| ERR_IRQ) << (p * 2);	2906	port_mask = (DONE_IRQ \| ERR_IRQ) << (p * 2);
2907	if (hc_cause & port_mask)	2907	if (hc_cause & port_mask)
2908	ack_irqs \|= (DMA_IRQ \| DEV_IRQ) << p;	2908	ack_irqs \|= (DMA_IRQ \| DEV_IRQ) << p;
2909	}	2909	}
2910	hc_mmio = mv_hc_base_from_port(mmio, port);	2910	hc_mmio = mv_hc_base_from_port(mmio, port);
2911	writelfl(~ack_irqs, hc_mmio + HC_IRQ_CAUSE);	2911	writelfl(~ack_irqs, hc_mmio + HC_IRQ_CAUSE);
2912	handled = 1;	2912	handled = 1;
2913	}	2913	}
2914	/*	2914	/*
2915	* Handle interrupts signalled for this port:	2915	* Handle interrupts signalled for this port:
2916	*/	2916	*/
2917	port_cause = (main_irq_cause >> shift) & (DONE_IRQ \| ERR_IRQ);	2917	port_cause = (main_irq_cause >> shift) & (DONE_IRQ \| ERR_IRQ);
2918	if (port_cause)	2918	if (port_cause)
2919	mv_port_intr(ap, port_cause);	2919	mv_port_intr(ap, port_cause);
2920	}	2920	}
2921	return handled;	2921	return handled;
2922	}	2922	}
2923		2923
2924	static int mv_pci_error(struct ata_host host, void __iomem mmio)	2924	static int mv_pci_error(struct ata_host host, void __iomem mmio)
2925	{	2925	{
2926	struct mv_host_priv *hpriv = host->private_data;	2926	struct mv_host_priv *hpriv = host->private_data;
2927	struct ata_port *ap;	2927	struct ata_port *ap;
2928	struct ata_queued_cmd *qc;	2928	struct ata_queued_cmd *qc;
2929	struct ata_eh_info *ehi;	2929	struct ata_eh_info *ehi;
2930	unsigned int i, err_mask, printed = 0;	2930	unsigned int i, err_mask, printed = 0;
2931	u32 err_cause;	2931	u32 err_cause;
2932		2932
2933	err_cause = readl(mmio + hpriv->irq_cause_offset);	2933	err_cause = readl(mmio + hpriv->irq_cause_offset);
2934		2934
2935	dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n",	2935	dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n",
2936	err_cause);	2936	err_cause);
2937		2937
2938	DPRINTK("All regs @ PCI error\n");	2938	DPRINTK("All regs @ PCI error\n");
2939	mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));	2939	mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));
2940		2940
2941	writelfl(0, mmio + hpriv->irq_cause_offset);	2941	writelfl(0, mmio + hpriv->irq_cause_offset);
2942		2942
2943	for (i = 0; i < host->n_ports; i++) {	2943	for (i = 0; i < host->n_ports; i++) {
2944	ap = host->ports[i];	2944	ap = host->ports[i];
2945	if (!ata_link_offline(&ap->link)) {	2945	if (!ata_link_offline(&ap->link)) {
2946	ehi = &ap->link.eh_info;	2946	ehi = &ap->link.eh_info;
2947	ata_ehi_clear_desc(ehi);	2947	ata_ehi_clear_desc(ehi);
2948	if (!printed++)	2948	if (!printed++)
2949	ata_ehi_push_desc(ehi,	2949	ata_ehi_push_desc(ehi,
2950	"PCI err cause 0x%08x", err_cause);	2950	"PCI err cause 0x%08x", err_cause);
2951	err_mask = AC_ERR_HOST_BUS;	2951	err_mask = AC_ERR_HOST_BUS;
2952	ehi->action = ATA_EH_RESET;	2952	ehi->action = ATA_EH_RESET;
2953	qc = ata_qc_from_tag(ap, ap->link.active_tag);	2953	qc = ata_qc_from_tag(ap, ap->link.active_tag);
2954	if (qc)	2954	if (qc)
2955	qc->err_mask \|= err_mask;	2955	qc->err_mask \|= err_mask;
2956	else	2956	else
2957	ehi->err_mask \|= err_mask;	2957	ehi->err_mask \|= err_mask;
2958		2958
2959	ata_port_freeze(ap);	2959	ata_port_freeze(ap);
2960	}	2960	}
2961	}	2961	}
2962	return 1; /* handled */	2962	return 1; /* handled */
2963	}	2963	}
2964		2964
2965	/**	2965	/**
2966	* mv_interrupt - Main interrupt event handler	2966	* mv_interrupt - Main interrupt event handler
2967	* @irq: unused	2967	* @irq: unused
2968	* @dev_instance: private data; in this case the host structure	2968	* @dev_instance: private data; in this case the host structure
2969	*	2969	*
2970	* Read the read only register to determine if any host	2970	* Read the read only register to determine if any host
2971	* controllers have pending interrupts. If so, call lower level	2971	* controllers have pending interrupts. If so, call lower level
2972	* routine to handle. Also check for PCI errors which are only	2972	* routine to handle. Also check for PCI errors which are only
2973	* reported here.	2973	* reported here.
2974	*	2974	*
2975	* LOCKING:	2975	* LOCKING:
2976	* This routine holds the host lock while processing pending	2976	* This routine holds the host lock while processing pending
2977	* interrupts.	2977	* interrupts.
2978	*/	2978	*/
2979	static irqreturn_t mv_interrupt(int irq, void *dev_instance)	2979	static irqreturn_t mv_interrupt(int irq, void *dev_instance)
2980	{	2980	{
2981	struct ata_host *host = dev_instance;	2981	struct ata_host *host = dev_instance;
2982	struct mv_host_priv *hpriv = host->private_data;	2982	struct mv_host_priv *hpriv = host->private_data;
2983	unsigned int handled = 0;	2983	unsigned int handled = 0;
2984	int using_msi = hpriv->hp_flags & MV_HP_FLAG_MSI;	2984	int using_msi = hpriv->hp_flags & MV_HP_FLAG_MSI;
2985	u32 main_irq_cause, pending_irqs;	2985	u32 main_irq_cause, pending_irqs;
2986		2986
2987	spin_lock(&host->lock);	2987	spin_lock(&host->lock);
2988		2988
2989	/* for MSI: block new interrupts while in here */	2989	/* for MSI: block new interrupts while in here */
2990	if (using_msi)	2990	if (using_msi)
2991	mv_write_main_irq_mask(0, hpriv);	2991	mv_write_main_irq_mask(0, hpriv);
2992		2992
2993	main_irq_cause = readl(hpriv->main_irq_cause_addr);	2993	main_irq_cause = readl(hpriv->main_irq_cause_addr);
2994	pending_irqs = main_irq_cause & hpriv->main_irq_mask;	2994	pending_irqs = main_irq_cause & hpriv->main_irq_mask;
2995	/*	2995	/*
2996	* Deal with cases where we either have nothing pending, or have read	2996	* Deal with cases where we either have nothing pending, or have read
2997	* a bogus register value which can indicate HW removal or PCI fault.	2997	* a bogus register value which can indicate HW removal or PCI fault.
2998	*/	2998	*/
2999	if (pending_irqs && main_irq_cause != 0xffffffffU) {	2999	if (pending_irqs && main_irq_cause != 0xffffffffU) {
3000	if (unlikely((pending_irqs & PCI_ERR) && !IS_SOC(hpriv)))	3000	if (unlikely((pending_irqs & PCI_ERR) && !IS_SOC(hpriv)))
3001	handled = mv_pci_error(host, hpriv->base);	3001	handled = mv_pci_error(host, hpriv->base);
3002	else	3002	else
3003	handled = mv_host_intr(host, pending_irqs);	3003	handled = mv_host_intr(host, pending_irqs);
3004	}	3004	}
3005		3005
3006	/* for MSI: unmask; interrupt cause bits will retrigger now */	3006	/* for MSI: unmask; interrupt cause bits will retrigger now */
3007	if (using_msi)	3007	if (using_msi)
3008	mv_write_main_irq_mask(hpriv->main_irq_mask, hpriv);	3008	mv_write_main_irq_mask(hpriv->main_irq_mask, hpriv);
3009		3009
3010	spin_unlock(&host->lock);	3010	spin_unlock(&host->lock);
3011		3011
3012	return IRQ_RETVAL(handled);	3012	return IRQ_RETVAL(handled);
3013	}	3013	}
3014		3014
3015	static unsigned int mv5_scr_offset(unsigned int sc_reg_in)	3015	static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
3016	{	3016	{
3017	unsigned int ofs;	3017	unsigned int ofs;
3018		3018
3019	switch (sc_reg_in) {	3019	switch (sc_reg_in) {
3020	case SCR_STATUS:	3020	case SCR_STATUS:
3021	case SCR_ERROR:	3021	case SCR_ERROR:
3022	case SCR_CONTROL:	3022	case SCR_CONTROL:
3023	ofs = sc_reg_in * sizeof(u32);	3023	ofs = sc_reg_in * sizeof(u32);
3024	break;	3024	break;
3025	default:	3025	default:
3026	ofs = 0xffffffffU;	3026	ofs = 0xffffffffU;
3027	break;	3027	break;
3028	}	3028	}
3029	return ofs;	3029	return ofs;
3030	}	3030	}
3031		3031
3032	static int mv5_scr_read(struct ata_link link, unsigned int sc_reg_in, u32 val)	3032	static int mv5_scr_read(struct ata_link link, unsigned int sc_reg_in, u32 val)
3033	{	3033	{
3034	struct mv_host_priv *hpriv = link->ap->host->private_data;	3034	struct mv_host_priv *hpriv = link->ap->host->private_data;
3035	void __iomem *mmio = hpriv->base;	3035	void __iomem *mmio = hpriv->base;
3036	void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);	3036	void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
3037	unsigned int ofs = mv5_scr_offset(sc_reg_in);	3037	unsigned int ofs = mv5_scr_offset(sc_reg_in);
3038		3038
3039	if (ofs != 0xffffffffU) {	3039	if (ofs != 0xffffffffU) {
3040	*val = readl(addr + ofs);	3040	*val = readl(addr + ofs);
3041	return 0;	3041	return 0;
3042	} else	3042	} else
3043	return -EINVAL;	3043	return -EINVAL;
3044	}	3044	}
3045		3045
3046	static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)	3046	static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
3047	{	3047	{
3048	struct mv_host_priv *hpriv = link->ap->host->private_data;	3048	struct mv_host_priv *hpriv = link->ap->host->private_data;
3049	void __iomem *mmio = hpriv->base;	3049	void __iomem *mmio = hpriv->base;
3050	void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);	3050	void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
3051	unsigned int ofs = mv5_scr_offset(sc_reg_in);	3051	unsigned int ofs = mv5_scr_offset(sc_reg_in);
3052		3052
3053	if (ofs != 0xffffffffU) {	3053	if (ofs != 0xffffffffU) {
3054	writelfl(val, addr + ofs);	3054	writelfl(val, addr + ofs);
3055	return 0;	3055	return 0;
3056	} else	3056	} else
3057	return -EINVAL;	3057	return -EINVAL;
3058	}	3058	}
3059		3059
3060	static void mv5_reset_bus(struct ata_host host, void __iomem mmio)	3060	static void mv5_reset_bus(struct ata_host host, void __iomem mmio)
3061	{	3061	{
3062	struct pci_dev *pdev = to_pci_dev(host->dev);	3062	struct pci_dev *pdev = to_pci_dev(host->dev);
3063	int early_5080;	3063	int early_5080;
3064		3064
3065	early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0);	3065	early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0);
3066		3066
3067	if (!early_5080) {	3067	if (!early_5080) {
3068	u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);	3068	u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
3069	tmp \|= (1 << 0);	3069	tmp \|= (1 << 0);
3070	writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);	3070	writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
3071	}	3071	}
3072		3072
3073	mv_reset_pci_bus(host, mmio);	3073	mv_reset_pci_bus(host, mmio);
3074	}	3074	}
3075		3075
3076	static void mv5_reset_flash(struct mv_host_priv hpriv, void __iomem mmio)	3076	static void mv5_reset_flash(struct mv_host_priv hpriv, void __iomem mmio)
3077	{	3077	{
3078	writel(0x0fcfffff, mmio + FLASH_CTL);	3078	writel(0x0fcfffff, mmio + FLASH_CTL);
3079	}	3079	}
3080		3080
3081	static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,	3081	static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
3082	void __iomem *mmio)	3082	void __iomem *mmio)
3083	{	3083	{
3084	void __iomem *phy_mmio = mv5_phy_base(mmio, idx);	3084	void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
3085	u32 tmp;	3085	u32 tmp;
3086		3086
3087	tmp = readl(phy_mmio + MV5_PHY_MODE);	3087	tmp = readl(phy_mmio + MV5_PHY_MODE);
3088		3088
3089	hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */	3089	hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
3090	hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */	3090	hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
3091	}	3091	}
3092		3092
3093	static void mv5_enable_leds(struct mv_host_priv hpriv, void __iomem mmio)	3093	static void mv5_enable_leds(struct mv_host_priv hpriv, void __iomem mmio)
3094	{	3094	{
3095	u32 tmp;	3095	u32 tmp;
3096		3096
3097	writel(0, mmio + GPIO_PORT_CTL);	3097	writel(0, mmio + GPIO_PORT_CTL);
3098		3098
3099	/* FIXME: handle MV_HP_ERRATA_50XXB2 errata */	3099	/* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
3100		3100
3101	tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);	3101	tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
3102	tmp \|= ~(1 << 0);	3102	tmp \|= ~(1 << 0);
3103	writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);	3103	writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
3104	}	3104	}
3105		3105
3106	static void mv5_phy_errata(struct mv_host_priv hpriv, void __iomem mmio,	3106	static void mv5_phy_errata(struct mv_host_priv hpriv, void __iomem mmio,
3107	unsigned int port)	3107	unsigned int port)
3108	{	3108	{
3109	void __iomem *phy_mmio = mv5_phy_base(mmio, port);	3109	void __iomem *phy_mmio = mv5_phy_base(mmio, port);
3110	const u32 mask = (1<<12) \| (1<<11) \| (1<<7) \| (1<<6) \| (1<<5);	3110	const u32 mask = (1<<12) \| (1<<11) \| (1<<7) \| (1<<6) \| (1<<5);
3111	u32 tmp;	3111	u32 tmp;
3112	int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);	3112	int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
3113		3113
3114	if (fix_apm_sq) {	3114	if (fix_apm_sq) {
3115	tmp = readl(phy_mmio + MV5_LTMODE);	3115	tmp = readl(phy_mmio + MV5_LTMODE);
3116	tmp \|= (1 << 19);	3116	tmp \|= (1 << 19);
3117	writel(tmp, phy_mmio + MV5_LTMODE);	3117	writel(tmp, phy_mmio + MV5_LTMODE);
3118		3118
3119	tmp = readl(phy_mmio + MV5_PHY_CTL);	3119	tmp = readl(phy_mmio + MV5_PHY_CTL);
3120	tmp &= ~0x3;	3120	tmp &= ~0x3;
3121	tmp \|= 0x1;	3121	tmp \|= 0x1;
3122	writel(tmp, phy_mmio + MV5_PHY_CTL);	3122	writel(tmp, phy_mmio + MV5_PHY_CTL);
3123	}	3123	}
3124		3124
3125	tmp = readl(phy_mmio + MV5_PHY_MODE);	3125	tmp = readl(phy_mmio + MV5_PHY_MODE);
3126	tmp &= ~mask;	3126	tmp &= ~mask;
3127	tmp \|= hpriv->signal[port].pre;	3127	tmp \|= hpriv->signal[port].pre;
3128	tmp \|= hpriv->signal[port].amps;	3128	tmp \|= hpriv->signal[port].amps;
3129	writel(tmp, phy_mmio + MV5_PHY_MODE);	3129	writel(tmp, phy_mmio + MV5_PHY_MODE);
3130	}	3130	}
3131		3131
3132		3132
3133	#undef ZERO	3133	#undef ZERO
3134	#define ZERO(reg) writel(0, port_mmio + (reg))	3134	#define ZERO(reg) writel(0, port_mmio + (reg))
3135	static void mv5_reset_hc_port(struct mv_host_priv hpriv, void __iomem mmio,	3135	static void mv5_reset_hc_port(struct mv_host_priv hpriv, void __iomem mmio,
3136	unsigned int port)	3136	unsigned int port)
3137	{	3137	{
3138	void __iomem *port_mmio = mv_port_base(mmio, port);	3138	void __iomem *port_mmio = mv_port_base(mmio, port);
3139		3139
3140	mv_reset_channel(hpriv, mmio, port);	3140	mv_reset_channel(hpriv, mmio, port);
3141		3141
3142	ZERO(0x028); /* command */	3142	ZERO(0x028); /* command */
3143	writel(0x11f, port_mmio + EDMA_CFG);	3143	writel(0x11f, port_mmio + EDMA_CFG);
3144	ZERO(0x004); /* timer */	3144	ZERO(0x004); /* timer */
3145	ZERO(0x008); /* irq err cause */	3145	ZERO(0x008); /* irq err cause */
3146	ZERO(0x00c); /* irq err mask */	3146	ZERO(0x00c); /* irq err mask */
3147	ZERO(0x010); /* rq bah */	3147	ZERO(0x010); /* rq bah */
3148	ZERO(0x014); /* rq inp */	3148	ZERO(0x014); /* rq inp */
3149	ZERO(0x018); /* rq outp */	3149	ZERO(0x018); /* rq outp */
3150	ZERO(0x01c); /* respq bah */	3150	ZERO(0x01c); /* respq bah */
3151	ZERO(0x024); /* respq outp */	3151	ZERO(0x024); /* respq outp */
3152	ZERO(0x020); /* respq inp */	3152	ZERO(0x020); /* respq inp */
3153	ZERO(0x02c); /* test control */	3153	ZERO(0x02c); /* test control */
3154	writel(0xbc, port_mmio + EDMA_IORDY_TMOUT);	3154	writel(0xbc, port_mmio + EDMA_IORDY_TMOUT);
3155	}	3155	}
3156	#undef ZERO	3156	#undef ZERO
3157		3157
3158	#define ZERO(reg) writel(0, hc_mmio + (reg))	3158	#define ZERO(reg) writel(0, hc_mmio + (reg))
3159	static void mv5_reset_one_hc(struct mv_host_priv hpriv, void __iomem mmio,	3159	static void mv5_reset_one_hc(struct mv_host_priv hpriv, void __iomem mmio,
3160	unsigned int hc)	3160	unsigned int hc)
3161	{	3161	{
3162	void __iomem *hc_mmio = mv_hc_base(mmio, hc);	3162	void __iomem *hc_mmio = mv_hc_base(mmio, hc);
3163	u32 tmp;	3163	u32 tmp;
3164		3164
3165	ZERO(0x00c);	3165	ZERO(0x00c);
3166	ZERO(0x010);	3166	ZERO(0x010);
3167	ZERO(0x014);	3167	ZERO(0x014);
3168	ZERO(0x018);	3168	ZERO(0x018);
3169		3169
3170	tmp = readl(hc_mmio + 0x20);	3170	tmp = readl(hc_mmio + 0x20);
3171	tmp &= 0x1c1c1c1c;	3171	tmp &= 0x1c1c1c1c;
3172	tmp \|= 0x03030303;	3172	tmp \|= 0x03030303;
3173	writel(tmp, hc_mmio + 0x20);	3173	writel(tmp, hc_mmio + 0x20);
3174	}	3174	}
3175	#undef ZERO	3175	#undef ZERO
3176		3176
3177	static int mv5_reset_hc(struct mv_host_priv hpriv, void __iomem mmio,	3177	static int mv5_reset_hc(struct mv_host_priv hpriv, void __iomem mmio,
3178	unsigned int n_hc)	3178	unsigned int n_hc)
3179	{	3179	{
3180	unsigned int hc, port;	3180	unsigned int hc, port;
3181		3181
3182	for (hc = 0; hc < n_hc; hc++) {	3182	for (hc = 0; hc < n_hc; hc++) {
3183	for (port = 0; port < MV_PORTS_PER_HC; port++)	3183	for (port = 0; port < MV_PORTS_PER_HC; port++)
3184	mv5_reset_hc_port(hpriv, mmio,	3184	mv5_reset_hc_port(hpriv, mmio,
3185	(hc * MV_PORTS_PER_HC) + port);	3185	(hc * MV_PORTS_PER_HC) + port);
3186		3186
3187	mv5_reset_one_hc(hpriv, mmio, hc);	3187	mv5_reset_one_hc(hpriv, mmio, hc);
3188	}	3188	}
3189		3189
3190	return 0;	3190	return 0;
3191	}	3191	}
3192		3192
3193	#undef ZERO	3193	#undef ZERO
3194	#define ZERO(reg) writel(0, mmio + (reg))	3194	#define ZERO(reg) writel(0, mmio + (reg))
3195	static void mv_reset_pci_bus(struct ata_host host, void __iomem mmio)	3195	static void mv_reset_pci_bus(struct ata_host host, void __iomem mmio)
3196	{	3196	{
3197	struct mv_host_priv *hpriv = host->private_data;	3197	struct mv_host_priv *hpriv = host->private_data;
3198	u32 tmp;	3198	u32 tmp;
3199		3199
3200	tmp = readl(mmio + MV_PCI_MODE);	3200	tmp = readl(mmio + MV_PCI_MODE);
3201	tmp &= 0xff00ffff;	3201	tmp &= 0xff00ffff;
3202	writel(tmp, mmio + MV_PCI_MODE);	3202	writel(tmp, mmio + MV_PCI_MODE);
3203		3203
3204	ZERO(MV_PCI_DISC_TIMER);	3204	ZERO(MV_PCI_DISC_TIMER);
3205	ZERO(MV_PCI_MSI_TRIGGER);	3205	ZERO(MV_PCI_MSI_TRIGGER);
3206	writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT);	3206	writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT);
3207	ZERO(MV_PCI_SERR_MASK);	3207	ZERO(MV_PCI_SERR_MASK);
3208	ZERO(hpriv->irq_cause_offset);	3208	ZERO(hpriv->irq_cause_offset);
3209	ZERO(hpriv->irq_mask_offset);	3209	ZERO(hpriv->irq_mask_offset);
3210	ZERO(MV_PCI_ERR_LOW_ADDRESS);	3210	ZERO(MV_PCI_ERR_LOW_ADDRESS);
3211	ZERO(MV_PCI_ERR_HIGH_ADDRESS);	3211	ZERO(MV_PCI_ERR_HIGH_ADDRESS);
3212	ZERO(MV_PCI_ERR_ATTRIBUTE);	3212	ZERO(MV_PCI_ERR_ATTRIBUTE);
3213	ZERO(MV_PCI_ERR_COMMAND);	3213	ZERO(MV_PCI_ERR_COMMAND);
3214	}	3214	}
3215	#undef ZERO	3215	#undef ZERO
3216		3216
3217	static void mv6_reset_flash(struct mv_host_priv hpriv, void __iomem mmio)	3217	static void mv6_reset_flash(struct mv_host_priv hpriv, void __iomem mmio)
3218	{	3218	{
3219	u32 tmp;	3219	u32 tmp;
3220		3220
3221	mv5_reset_flash(hpriv, mmio);	3221	mv5_reset_flash(hpriv, mmio);
3222		3222
3223	tmp = readl(mmio + GPIO_PORT_CTL);	3223	tmp = readl(mmio + GPIO_PORT_CTL);
3224	tmp &= 0x3;	3224	tmp &= 0x3;
3225	tmp \|= (1 << 5) \| (1 << 6);	3225	tmp \|= (1 << 5) \| (1 << 6);
3226	writel(tmp, mmio + GPIO_PORT_CTL);	3226	writel(tmp, mmio + GPIO_PORT_CTL);
3227	}	3227	}
3228		3228
3229	/**	3229	/**
3230	* mv6_reset_hc - Perform the 6xxx global soft reset	3230	* mv6_reset_hc - Perform the 6xxx global soft reset
3231	* @mmio: base address of the HBA	3231	* @mmio: base address of the HBA
3232	*	3232	*
3233	* This routine only applies to 6xxx parts.	3233	* This routine only applies to 6xxx parts.
3234	*	3234	*
3235	* LOCKING:	3235	* LOCKING:
3236	* Inherited from caller.	3236	* Inherited from caller.
3237	*/	3237	*/
3238	static int mv6_reset_hc(struct mv_host_priv hpriv, void __iomem mmio,	3238	static int mv6_reset_hc(struct mv_host_priv hpriv, void __iomem mmio,
3239	unsigned int n_hc)	3239	unsigned int n_hc)
3240	{	3240	{
3241	void __iomem *reg = mmio + PCI_MAIN_CMD_STS;	3241	void __iomem *reg = mmio + PCI_MAIN_CMD_STS;
3242	int i, rc = 0;	3242	int i, rc = 0;
3243	u32 t;	3243	u32 t;
3244		3244
3245	/* Following procedure defined in PCI "main command and status	3245	/* Following procedure defined in PCI "main command and status
3246	* register" table.	3246	* register" table.
3247	*/	3247	*/
3248	t = readl(reg);	3248	t = readl(reg);
3249	writel(t \| STOP_PCI_MASTER, reg);	3249	writel(t \| STOP_PCI_MASTER, reg);
3250		3250
3251	for (i = 0; i < 1000; i++) {	3251	for (i = 0; i < 1000; i++) {
3252	udelay(1);	3252	udelay(1);
3253	t = readl(reg);	3253	t = readl(reg);
3254	if (PCI_MASTER_EMPTY & t)	3254	if (PCI_MASTER_EMPTY & t)
3255	break;	3255	break;
3256	}	3256	}
3257	if (!(PCI_MASTER_EMPTY & t)) {	3257	if (!(PCI_MASTER_EMPTY & t)) {
3258	printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");	3258	printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
3259	rc = 1;	3259	rc = 1;
3260	goto done;	3260	goto done;
3261	}	3261	}
3262		3262
3263	/* set reset */	3263	/* set reset */
3264	i = 5;	3264	i = 5;
3265	do {	3265	do {
3266	writel(t \| GLOB_SFT_RST, reg);	3266	writel(t \| GLOB_SFT_RST, reg);
3267	t = readl(reg);	3267	t = readl(reg);
3268	udelay(1);	3268	udelay(1);
3269	} while (!(GLOB_SFT_RST & t) && (i-- > 0));	3269	} while (!(GLOB_SFT_RST & t) && (i-- > 0));
3270		3270
3271	if (!(GLOB_SFT_RST & t)) {	3271	if (!(GLOB_SFT_RST & t)) {
3272	printk(KERN_ERR DRV_NAME ": can't set global reset\n");	3272	printk(KERN_ERR DRV_NAME ": can't set global reset\n");
3273	rc = 1;	3273	rc = 1;
3274	goto done;	3274	goto done;
3275	}	3275	}
3276		3276
3277	/* clear reset and reenable the PCI master (not mentioned in spec) */	3277	/* clear reset and reenable the PCI master (not mentioned in spec) */
3278	i = 5;	3278	i = 5;
3279	do {	3279	do {
3280	writel(t & ~(GLOB_SFT_RST \| STOP_PCI_MASTER), reg);	3280	writel(t & ~(GLOB_SFT_RST \| STOP_PCI_MASTER), reg);
3281	t = readl(reg);	3281	t = readl(reg);
3282	udelay(1);	3282	udelay(1);
3283	} while ((GLOB_SFT_RST & t) && (i-- > 0));	3283	} while ((GLOB_SFT_RST & t) && (i-- > 0));
3284		3284
3285	if (GLOB_SFT_RST & t) {	3285	if (GLOB_SFT_RST & t) {
3286	printk(KERN_ERR DRV_NAME ": can't clear global reset\n");	3286	printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
3287	rc = 1;	3287	rc = 1;
3288	}	3288	}
3289	done:	3289	done:
3290	return rc;	3290	return rc;
3291	}	3291	}
3292		3292
3293	static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,	3293	static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
3294	void __iomem *mmio)	3294	void __iomem *mmio)
3295	{	3295	{
3296	void __iomem *port_mmio;	3296	void __iomem *port_mmio;
3297	u32 tmp;	3297	u32 tmp;
3298		3298
3299	tmp = readl(mmio + RESET_CFG);	3299	tmp = readl(mmio + RESET_CFG);
3300	if ((tmp & (1 << 0)) == 0) {	3300	if ((tmp & (1 << 0)) == 0) {
3301	hpriv->signal[idx].amps = 0x7 << 8;	3301	hpriv->signal[idx].amps = 0x7 << 8;
3302	hpriv->signal[idx].pre = 0x1 << 5;	3302	hpriv->signal[idx].pre = 0x1 << 5;
3303	return;	3303	return;
3304	}	3304	}
3305		3305
3306	port_mmio = mv_port_base(mmio, idx);	3306	port_mmio = mv_port_base(mmio, idx);
3307	tmp = readl(port_mmio + PHY_MODE2);	3307	tmp = readl(port_mmio + PHY_MODE2);
3308		3308
3309	hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */	3309	hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
3310	hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */	3310	hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
3311	}	3311	}
3312		3312
3313	static void mv6_enable_leds(struct mv_host_priv hpriv, void __iomem mmio)	3313	static void mv6_enable_leds(struct mv_host_priv hpriv, void __iomem mmio)
3314	{	3314	{
3315	writel(0x00000060, mmio + GPIO_PORT_CTL);	3315	writel(0x00000060, mmio + GPIO_PORT_CTL);
3316	}	3316	}
3317		3317
3318	static void mv6_phy_errata(struct mv_host_priv hpriv, void __iomem mmio,	3318	static void mv6_phy_errata(struct mv_host_priv hpriv, void __iomem mmio,
3319	unsigned int port)	3319	unsigned int port)
3320	{	3320	{
3321	void __iomem *port_mmio = mv_port_base(mmio, port);	3321	void __iomem *port_mmio = mv_port_base(mmio, port);
3322		3322
3323	u32 hp_flags = hpriv->hp_flags;	3323	u32 hp_flags = hpriv->hp_flags;
3324	int fix_phy_mode2 =	3324	int fix_phy_mode2 =
3325	hp_flags & (MV_HP_ERRATA_60X1B2 \| MV_HP_ERRATA_60X1C0);	3325	hp_flags & (MV_HP_ERRATA_60X1B2 \| MV_HP_ERRATA_60X1C0);
3326	int fix_phy_mode4 =	3326	int fix_phy_mode4 =
3327	hp_flags & (MV_HP_ERRATA_60X1B2 \| MV_HP_ERRATA_60X1C0);	3327	hp_flags & (MV_HP_ERRATA_60X1B2 \| MV_HP_ERRATA_60X1C0);
3328	u32 m2, m3;	3328	u32 m2, m3;
3329		3329
3330	if (fix_phy_mode2) {	3330	if (fix_phy_mode2) {
3331	m2 = readl(port_mmio + PHY_MODE2);	3331	m2 = readl(port_mmio + PHY_MODE2);
3332	m2 &= ~(1 << 16);	3332	m2 &= ~(1 << 16);
3333	m2 \|= (1 << 31);	3333	m2 \|= (1 << 31);
3334	writel(m2, port_mmio + PHY_MODE2);	3334	writel(m2, port_mmio + PHY_MODE2);
3335		3335
3336	udelay(200);	3336	udelay(200);
3337		3337
3338	m2 = readl(port_mmio + PHY_MODE2);	3338	m2 = readl(port_mmio + PHY_MODE2);
3339	m2 &= ~((1 << 16) \| (1 << 31));	3339	m2 &= ~((1 << 16) \| (1 << 31));
3340	writel(m2, port_mmio + PHY_MODE2);	3340	writel(m2, port_mmio + PHY_MODE2);
3341		3341
3342	udelay(200);	3342	udelay(200);
3343	}	3343	}
3344		3344
3345	/*	3345	/*
3346	* Gen-II/IIe PHY_MODE3 errata RM#2:	3346	* Gen-II/IIe PHY_MODE3 errata RM#2:
3347	* Achieves better receiver noise performance than the h/w default:	3347	* Achieves better receiver noise performance than the h/w default:
3348	*/	3348	*/
3349	m3 = readl(port_mmio + PHY_MODE3);	3349	m3 = readl(port_mmio + PHY_MODE3);
3350	m3 = (m3 & 0x1f) \| (0x5555601 << 5);	3350	m3 = (m3 & 0x1f) \| (0x5555601 << 5);
3351		3351
3352	/* Guideline 88F5182 (GL# SATA-S11) */	3352	/* Guideline 88F5182 (GL# SATA-S11) */
3353	if (IS_SOC(hpriv))	3353	if (IS_SOC(hpriv))
3354	m3 &= ~0x1c;	3354	m3 &= ~0x1c;
3355		3355
3356	if (fix_phy_mode4) {	3356	if (fix_phy_mode4) {
3357	u32 m4 = readl(port_mmio + PHY_MODE4);	3357	u32 m4 = readl(port_mmio + PHY_MODE4);
3358	/*	3358	/*
3359	* Enforce reserved-bit restrictions on GenIIe devices only.	3359	* Enforce reserved-bit restrictions on GenIIe devices only.
3360	* For earlier chipsets, force only the internal config field	3360	* For earlier chipsets, force only the internal config field
3361	* (workaround for errata FEr SATA#10 part 1).	3361	* (workaround for errata FEr SATA#10 part 1).
3362	*/	3362	*/
3363	if (IS_GEN_IIE(hpriv))	3363	if (IS_GEN_IIE(hpriv))
3364	m4 = (m4 & ~PHY_MODE4_RSVD_ZEROS) \| PHY_MODE4_RSVD_ONES;	3364	m4 = (m4 & ~PHY_MODE4_RSVD_ZEROS) \| PHY_MODE4_RSVD_ONES;
3365	else	3365	else
3366	m4 = (m4 & ~PHY_MODE4_CFG_MASK) \| PHY_MODE4_CFG_VALUE;	3366	m4 = (m4 & ~PHY_MODE4_CFG_MASK) \| PHY_MODE4_CFG_VALUE;
3367	writel(m4, port_mmio + PHY_MODE4);	3367	writel(m4, port_mmio + PHY_MODE4);
3368	}	3368	}
3369	/*	3369	/*
3370	* Workaround for 60x1-B2 errata SATA#13:	3370	* Workaround for 60x1-B2 errata SATA#13:
3371	* Any write to PHY_MODE4 (above) may corrupt PHY_MODE3,	3371	* Any write to PHY_MODE4 (above) may corrupt PHY_MODE3,
3372	* so we must always rewrite PHY_MODE3 after PHY_MODE4.	3372	* so we must always rewrite PHY_MODE3 after PHY_MODE4.
3373	* Or ensure we use writelfl() when writing PHY_MODE4.	3373	* Or ensure we use writelfl() when writing PHY_MODE4.
3374	*/	3374	*/
3375	writel(m3, port_mmio + PHY_MODE3);	3375	writel(m3, port_mmio + PHY_MODE3);
3376		3376
3377	/* Revert values of pre-emphasis and signal amps to the saved ones */	3377	/* Revert values of pre-emphasis and signal amps to the saved ones */
3378	m2 = readl(port_mmio + PHY_MODE2);	3378	m2 = readl(port_mmio + PHY_MODE2);
3379		3379
3380	m2 &= ~MV_M2_PREAMP_MASK;	3380	m2 &= ~MV_M2_PREAMP_MASK;
3381	m2 \|= hpriv->signal[port].amps;	3381	m2 \|= hpriv->signal[port].amps;
3382	m2 \|= hpriv->signal[port].pre;	3382	m2 \|= hpriv->signal[port].pre;
3383	m2 &= ~(1 << 16);	3383	m2 &= ~(1 << 16);
3384		3384
3385	/* according to mvSata 3.6.1, some IIE values are fixed */	3385	/* according to mvSata 3.6.1, some IIE values are fixed */
3386	if (IS_GEN_IIE(hpriv)) {	3386	if (IS_GEN_IIE(hpriv)) {
3387	m2 &= ~0xC30FF01F;	3387	m2 &= ~0xC30FF01F;
3388	m2 \|= 0x0000900F;	3388	m2 \|= 0x0000900F;
3389	}	3389	}
3390		3390
3391	writel(m2, port_mmio + PHY_MODE2);	3391	writel(m2, port_mmio + PHY_MODE2);
3392	}	3392	}
3393		3393
3394	/* TODO: use the generic LED interface to configure the SATA Presence */	3394	/* TODO: use the generic LED interface to configure the SATA Presence */
3395	/* & Acitivy LEDs on the board */	3395	/* & Acitivy LEDs on the board */
3396	static void mv_soc_enable_leds(struct mv_host_priv *hpriv,	3396	static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
3397	void __iomem *mmio)	3397	void __iomem *mmio)
3398	{	3398	{
3399	return;	3399	return;
3400	}	3400	}
3401		3401
3402	static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,	3402	static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
3403	void __iomem *mmio)	3403	void __iomem *mmio)
3404	{	3404	{
3405	void __iomem *port_mmio;	3405	void __iomem *port_mmio;
3406	u32 tmp;	3406	u32 tmp;
3407		3407
3408	port_mmio = mv_port_base(mmio, idx);	3408	port_mmio = mv_port_base(mmio, idx);
3409	tmp = readl(port_mmio + PHY_MODE2);	3409	tmp = readl(port_mmio + PHY_MODE2);
3410		3410
3411	hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */	3411	hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
3412	hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */	3412	hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
3413	}	3413	}
3414		3414
3415	#undef ZERO	3415	#undef ZERO
3416	#define ZERO(reg) writel(0, port_mmio + (reg))	3416	#define ZERO(reg) writel(0, port_mmio + (reg))
3417	static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv,	3417	static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv,
3418	void __iomem *mmio, unsigned int port)	3418	void __iomem *mmio, unsigned int port)
3419	{	3419	{
3420	void __iomem *port_mmio = mv_port_base(mmio, port);	3420	void __iomem *port_mmio = mv_port_base(mmio, port);
3421		3421
3422	mv_reset_channel(hpriv, mmio, port);	3422	mv_reset_channel(hpriv, mmio, port);
3423		3423
3424	ZERO(0x028); /* command */	3424	ZERO(0x028); /* command */
3425	writel(0x101f, port_mmio + EDMA_CFG);	3425	writel(0x101f, port_mmio + EDMA_CFG);
3426	ZERO(0x004); /* timer */	3426	ZERO(0x004); /* timer */
3427	ZERO(0x008); /* irq err cause */	3427	ZERO(0x008); /* irq err cause */
3428	ZERO(0x00c); /* irq err mask */	3428	ZERO(0x00c); /* irq err mask */
3429	ZERO(0x010); /* rq bah */	3429	ZERO(0x010); /* rq bah */
3430	ZERO(0x014); /* rq inp */	3430	ZERO(0x014); /* rq inp */
3431	ZERO(0x018); /* rq outp */	3431	ZERO(0x018); /* rq outp */
3432	ZERO(0x01c); /* respq bah */	3432	ZERO(0x01c); /* respq bah */
3433	ZERO(0x024); /* respq outp */	3433	ZERO(0x024); /* respq outp */
3434	ZERO(0x020); /* respq inp */	3434	ZERO(0x020); /* respq inp */
3435	ZERO(0x02c); /* test control */	3435	ZERO(0x02c); /* test control */
3436	writel(0x800, port_mmio + EDMA_IORDY_TMOUT);	3436	writel(0x800, port_mmio + EDMA_IORDY_TMOUT);
3437	}	3437	}
3438		3438
3439	#undef ZERO	3439	#undef ZERO
3440		3440
3441	#define ZERO(reg) writel(0, hc_mmio + (reg))	3441	#define ZERO(reg) writel(0, hc_mmio + (reg))
3442	static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv,	3442	static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv,
3443	void __iomem *mmio)	3443	void __iomem *mmio)
3444	{	3444	{
3445	void __iomem *hc_mmio = mv_hc_base(mmio, 0);	3445	void __iomem *hc_mmio = mv_hc_base(mmio, 0);
3446		3446
3447	ZERO(0x00c);	3447	ZERO(0x00c);
3448	ZERO(0x010);	3448	ZERO(0x010);
3449	ZERO(0x014);	3449	ZERO(0x014);
3450		3450
3451	}	3451	}
3452		3452
3453	#undef ZERO	3453	#undef ZERO
3454		3454
3455	static int mv_soc_reset_hc(struct mv_host_priv *hpriv,	3455	static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
3456	void __iomem *mmio, unsigned int n_hc)	3456	void __iomem *mmio, unsigned int n_hc)
3457	{	3457	{
3458	unsigned int port;	3458	unsigned int port;
3459		3459
3460	for (port = 0; port < hpriv->n_ports; port++)	3460	for (port = 0; port < hpriv->n_ports; port++)
3461	mv_soc_reset_hc_port(hpriv, mmio, port);	3461	mv_soc_reset_hc_port(hpriv, mmio, port);
3462		3462
3463	mv_soc_reset_one_hc(hpriv, mmio);	3463	mv_soc_reset_one_hc(hpriv, mmio);
3464		3464
3465	return 0;	3465	return 0;
3466	}	3466	}
3467		3467
3468	static void mv_soc_reset_flash(struct mv_host_priv *hpriv,	3468	static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
3469	void __iomem *mmio)	3469	void __iomem *mmio)
3470	{	3470	{
3471	return;	3471	return;
3472	}	3472	}
3473		3473
3474	static void mv_soc_reset_bus(struct ata_host host, void __iomem mmio)	3474	static void mv_soc_reset_bus(struct ata_host host, void __iomem mmio)
3475	{	3475	{
3476	return;	3476	return;
3477	}	3477	}
3478		3478
3479	static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv,	3479	static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv,
3480	void __iomem *mmio, unsigned int port)	3480	void __iomem *mmio, unsigned int port)
3481	{	3481	{
3482	void __iomem *port_mmio = mv_port_base(mmio, port);	3482	void __iomem *port_mmio = mv_port_base(mmio, port);
3483	u32 reg;	3483	u32 reg;
3484		3484
3485	reg = readl(port_mmio + PHY_MODE3);	3485	reg = readl(port_mmio + PHY_MODE3);
3486	reg &= ~(0x3 << 27); /* SELMUPF (bits 28:27) to 1 */	3486	reg &= ~(0x3 << 27); /* SELMUPF (bits 28:27) to 1 */
3487	reg \|= (0x1 << 27);	3487	reg \|= (0x1 << 27);
3488	reg &= ~(0x3 << 29); /* SELMUPI (bits 30:29) to 1 */	3488	reg &= ~(0x3 << 29); /* SELMUPI (bits 30:29) to 1 */
3489	reg \|= (0x1 << 29);	3489	reg \|= (0x1 << 29);
3490	writel(reg, port_mmio + PHY_MODE3);	3490	writel(reg, port_mmio + PHY_MODE3);
3491		3491
3492	reg = readl(port_mmio + PHY_MODE4);	3492	reg = readl(port_mmio + PHY_MODE4);
3493	reg &= ~0x1; /* SATU_OD8 (bit 0) to 0, reserved bit 16 must be set */	3493	reg &= ~0x1; /* SATU_OD8 (bit 0) to 0, reserved bit 16 must be set */
3494	reg \|= (0x1 << 16);	3494	reg \|= (0x1 << 16);
3495	writel(reg, port_mmio + PHY_MODE4);	3495	writel(reg, port_mmio + PHY_MODE4);
3496		3496
3497	reg = readl(port_mmio + PHY_MODE9_GEN2);	3497	reg = readl(port_mmio + PHY_MODE9_GEN2);
3498	reg &= ~0xf; /* TXAMP[3:0] (bits 3:0) to 8 */	3498	reg &= ~0xf; /* TXAMP[3:0] (bits 3:0) to 8 */
3499	reg \|= 0x8;	3499	reg \|= 0x8;
3500	reg &= ~(0x1 << 14); /* TXAMP[4] (bit 14) to 0 */	3500	reg &= ~(0x1 << 14); /* TXAMP[4] (bit 14) to 0 */
3501	writel(reg, port_mmio + PHY_MODE9_GEN2);	3501	writel(reg, port_mmio + PHY_MODE9_GEN2);
3502		3502
3503	reg = readl(port_mmio + PHY_MODE9_GEN1);	3503	reg = readl(port_mmio + PHY_MODE9_GEN1);
3504	reg &= ~0xf; /* TXAMP[3:0] (bits 3:0) to 8 */	3504	reg &= ~0xf; /* TXAMP[3:0] (bits 3:0) to 8 */
3505	reg \|= 0x8;	3505	reg \|= 0x8;
3506	reg &= ~(0x1 << 14); /* TXAMP[4] (bit 14) to 0 */	3506	reg &= ~(0x1 << 14); /* TXAMP[4] (bit 14) to 0 */
3507	writel(reg, port_mmio + PHY_MODE9_GEN1);	3507	writel(reg, port_mmio + PHY_MODE9_GEN1);
3508	}	3508	}
3509		3509
3510	/**	3510	/**
3511	* soc_is_65 - check if the soc is 65 nano device	3511	* soc_is_65 - check if the soc is 65 nano device
3512	*	3512	*
3513	* Detect the type of the SoC, this is done by reading the PHYCFG_OFS	3513	* Detect the type of the SoC, this is done by reading the PHYCFG_OFS
3514	* register, this register should contain non-zero value and it exists only	3514	* register, this register should contain non-zero value and it exists only
3515	* in the 65 nano devices, when reading it from older devices we get 0.	3515	* in the 65 nano devices, when reading it from older devices we get 0.
3516	*/	3516	*/
3517	static bool soc_is_65n(struct mv_host_priv *hpriv)	3517	static bool soc_is_65n(struct mv_host_priv *hpriv)
3518	{	3518	{
3519	void __iomem *port0_mmio = mv_port_base(hpriv->base, 0);	3519	void __iomem *port0_mmio = mv_port_base(hpriv->base, 0);
3520		3520
3521	if (readl(port0_mmio + PHYCFG_OFS))	3521	if (readl(port0_mmio + PHYCFG_OFS))
3522	return true;	3522	return true;
3523	return false;	3523	return false;
3524	}	3524	}
3525		3525
3526	static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i)	3526	static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i)
3527	{	3527	{
3528	u32 ifcfg = readl(port_mmio + SATA_IFCFG);	3528	u32 ifcfg = readl(port_mmio + SATA_IFCFG);
3529		3529
3530	ifcfg = (ifcfg & 0xf7f) \| 0x9b1000; /* from chip spec */	3530	ifcfg = (ifcfg & 0xf7f) \| 0x9b1000; /* from chip spec */
3531	if (want_gen2i)	3531	if (want_gen2i)
3532	ifcfg \|= (1 << 7); /* enable gen2i speed */	3532	ifcfg \|= (1 << 7); /* enable gen2i speed */
3533	writelfl(ifcfg, port_mmio + SATA_IFCFG);	3533	writelfl(ifcfg, port_mmio + SATA_IFCFG);
3534	}	3534	}
3535		3535
3536	static void mv_reset_channel(struct mv_host_priv hpriv, void __iomem mmio,	3536	static void mv_reset_channel(struct mv_host_priv hpriv, void __iomem mmio,
3537	unsigned int port_no)	3537	unsigned int port_no)
3538	{	3538	{
3539	void __iomem *port_mmio = mv_port_base(mmio, port_no);	3539	void __iomem *port_mmio = mv_port_base(mmio, port_no);
3540		3540
3541	/*	3541	/*
3542	* The datasheet warns against setting EDMA_RESET when EDMA is active	3542	* The datasheet warns against setting EDMA_RESET when EDMA is active
3543	* (but doesn't say what the problem might be). So we first try	3543	* (but doesn't say what the problem might be). So we first try
3544	* to disable the EDMA engine before doing the EDMA_RESET operation.	3544	* to disable the EDMA engine before doing the EDMA_RESET operation.
3545	*/	3545	*/
3546	mv_stop_edma_engine(port_mmio);	3546	mv_stop_edma_engine(port_mmio);
3547	writelfl(EDMA_RESET, port_mmio + EDMA_CMD);	3547	writelfl(EDMA_RESET, port_mmio + EDMA_CMD);
3548		3548
3549	if (!IS_GEN_I(hpriv)) {	3549	if (!IS_GEN_I(hpriv)) {
3550	/* Enable 3.0gb/s link speed: this survives EDMA_RESET */	3550	/* Enable 3.0gb/s link speed: this survives EDMA_RESET */
3551	mv_setup_ifcfg(port_mmio, 1);	3551	mv_setup_ifcfg(port_mmio, 1);
3552	}	3552	}
3553	/*	3553	/*
3554	* Strobing EDMA_RESET here causes a hard reset of the SATA transport,	3554	* Strobing EDMA_RESET here causes a hard reset of the SATA transport,
3555	* link, and physical layers. It resets all SATA interface registers	3555	* link, and physical layers. It resets all SATA interface registers
3556	* (except for SATA_IFCFG), and issues a COMRESET to the dev.	3556	* (except for SATA_IFCFG), and issues a COMRESET to the dev.
3557	*/	3557	*/
3558	writelfl(EDMA_RESET, port_mmio + EDMA_CMD);	3558	writelfl(EDMA_RESET, port_mmio + EDMA_CMD);
3559	udelay(25); /* allow reset propagation */	3559	udelay(25); /* allow reset propagation */
3560	writelfl(0, port_mmio + EDMA_CMD);	3560	writelfl(0, port_mmio + EDMA_CMD);
3561		3561
3562	hpriv->ops->phy_errata(hpriv, mmio, port_no);	3562	hpriv->ops->phy_errata(hpriv, mmio, port_no);
3563		3563
3564	if (IS_GEN_I(hpriv))	3564	if (IS_GEN_I(hpriv))
3565	mdelay(1);	3565	mdelay(1);
3566	}	3566	}
3567		3567
3568	static void mv_pmp_select(struct ata_port *ap, int pmp)	3568	static void mv_pmp_select(struct ata_port *ap, int pmp)
3569	{	3569	{
3570	if (sata_pmp_supported(ap)) {	3570	if (sata_pmp_supported(ap)) {
3571	void __iomem *port_mmio = mv_ap_base(ap);	3571	void __iomem *port_mmio = mv_ap_base(ap);
3572	u32 reg = readl(port_mmio + SATA_IFCTL);	3572	u32 reg = readl(port_mmio + SATA_IFCTL);
3573	int old = reg & 0xf;	3573	int old = reg & 0xf;
3574		3574
3575	if (old != pmp) {	3575	if (old != pmp) {
3576	reg = (reg & ~0xf) \| pmp;	3576	reg = (reg & ~0xf) \| pmp;
3577	writelfl(reg, port_mmio + SATA_IFCTL);	3577	writelfl(reg, port_mmio + SATA_IFCTL);
3578	}	3578	}
3579	}	3579	}
3580	}	3580	}
3581		3581
3582	static int mv_pmp_hardreset(struct ata_link link, unsigned int class,	3582	static int mv_pmp_hardreset(struct ata_link link, unsigned int class,
3583	unsigned long deadline)	3583	unsigned long deadline)
3584	{	3584	{
3585	mv_pmp_select(link->ap, sata_srst_pmp(link));	3585	mv_pmp_select(link->ap, sata_srst_pmp(link));
3586	return sata_std_hardreset(link, class, deadline);	3586	return sata_std_hardreset(link, class, deadline);
3587	}	3587	}
3588		3588
3589	static int mv_softreset(struct ata_link link, unsigned int class,	3589	static int mv_softreset(struct ata_link link, unsigned int class,
3590	unsigned long deadline)	3590	unsigned long deadline)
3591	{	3591	{
3592	mv_pmp_select(link->ap, sata_srst_pmp(link));	3592	mv_pmp_select(link->ap, sata_srst_pmp(link));
3593	return ata_sff_softreset(link, class, deadline);	3593	return ata_sff_softreset(link, class, deadline);
3594	}	3594	}
3595		3595
3596	static int mv_hardreset(struct ata_link link, unsigned int class,	3596	static int mv_hardreset(struct ata_link link, unsigned int class,
3597	unsigned long deadline)	3597	unsigned long deadline)
3598	{	3598	{
3599	struct ata_port *ap = link->ap;	3599	struct ata_port *ap = link->ap;
3600	struct mv_host_priv *hpriv = ap->host->private_data;	3600	struct mv_host_priv *hpriv = ap->host->private_data;
3601	struct mv_port_priv *pp = ap->private_data;	3601	struct mv_port_priv *pp = ap->private_data;
3602	void __iomem *mmio = hpriv->base;	3602	void __iomem *mmio = hpriv->base;
3603	int rc, attempts = 0, extra = 0;	3603	int rc, attempts = 0, extra = 0;
3604	u32 sstatus;	3604	u32 sstatus;
3605	bool online;	3605	bool online;
3606		3606
3607	mv_reset_channel(hpriv, mmio, ap->port_no);	3607	mv_reset_channel(hpriv, mmio, ap->port_no);
3608	pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;	3608	pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
3609	pp->pp_flags &=	3609	pp->pp_flags &=
3610	~(MV_PP_FLAG_FBS_EN \| MV_PP_FLAG_NCQ_EN \| MV_PP_FLAG_FAKE_ATA_BUSY);	3610	~(MV_PP_FLAG_FBS_EN \| MV_PP_FLAG_NCQ_EN \| MV_PP_FLAG_FAKE_ATA_BUSY);
3611		3611
3612	/* Workaround for errata FEr SATA#10 (part 2) */	3612	/* Workaround for errata FEr SATA#10 (part 2) */
3613	do {	3613	do {
3614	const unsigned long *timing =	3614	const unsigned long *timing =
3615	sata_ehc_deb_timing(&link->eh_context);	3615	sata_ehc_deb_timing(&link->eh_context);
3616		3616
3617	rc = sata_link_hardreset(link, timing, deadline + extra,	3617	rc = sata_link_hardreset(link, timing, deadline + extra,
3618	&online, NULL);	3618	&online, NULL);
3619	rc = online ? -EAGAIN : rc;	3619	rc = online ? -EAGAIN : rc;
3620	if (rc)	3620	if (rc)
3621	return rc;	3621	return rc;
3622	sata_scr_read(link, SCR_STATUS, &sstatus);	3622	sata_scr_read(link, SCR_STATUS, &sstatus);
3623	if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) {	3623	if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) {
3624	/* Force 1.5gb/s link speed and try again */	3624	/* Force 1.5gb/s link speed and try again */
3625	mv_setup_ifcfg(mv_ap_base(ap), 0);	3625	mv_setup_ifcfg(mv_ap_base(ap), 0);
3626	if (time_after(jiffies + HZ, deadline))	3626	if (time_after(jiffies + HZ, deadline))
3627	extra = HZ; /* only extend it once, max */	3627	extra = HZ; /* only extend it once, max */
3628	}	3628	}
3629	} while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123);	3629	} while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123);
3630	mv_save_cached_regs(ap);	3630	mv_save_cached_regs(ap);
3631	mv_edma_cfg(ap, 0, 0);	3631	mv_edma_cfg(ap, 0, 0);
3632		3632
3633	return rc;	3633	return rc;
3634	}	3634	}
3635		3635
3636	static void mv_eh_freeze(struct ata_port *ap)	3636	static void mv_eh_freeze(struct ata_port *ap)
3637	{	3637	{
3638	mv_stop_edma(ap);	3638	mv_stop_edma(ap);
3639	mv_enable_port_irqs(ap, 0);	3639	mv_enable_port_irqs(ap, 0);
3640	}	3640	}
3641		3641
3642	static void mv_eh_thaw(struct ata_port *ap)	3642	static void mv_eh_thaw(struct ata_port *ap)
3643	{	3643	{
3644	struct mv_host_priv *hpriv = ap->host->private_data;	3644	struct mv_host_priv *hpriv = ap->host->private_data;
3645	unsigned int port = ap->port_no;	3645	unsigned int port = ap->port_no;
3646	unsigned int hardport = mv_hardport_from_port(port);	3646	unsigned int hardport = mv_hardport_from_port(port);
3647	void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port);	3647	void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port);
3648	void __iomem *port_mmio = mv_ap_base(ap);	3648	void __iomem *port_mmio = mv_ap_base(ap);
3649	u32 hc_irq_cause;	3649	u32 hc_irq_cause;
3650		3650
3651	/* clear EDMA errors on this port */	3651	/* clear EDMA errors on this port */
3652	writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE);	3652	writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE);
3653		3653
3654	/* clear pending irq events */	3654	/* clear pending irq events */
3655	hc_irq_cause = ~((DEV_IRQ \| DMA_IRQ) << hardport);	3655	hc_irq_cause = ~((DEV_IRQ \| DMA_IRQ) << hardport);
3656	writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE);	3656	writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE);
3657		3657
3658	mv_enable_port_irqs(ap, ERR_IRQ);	3658	mv_enable_port_irqs(ap, ERR_IRQ);
3659	}	3659	}
3660		3660
3661	/**	3661	/**
3662	* mv_port_init - Perform some early initialization on a single port.	3662	* mv_port_init - Perform some early initialization on a single port.
3663	* @port: libata data structure storing shadow register addresses	3663	* @port: libata data structure storing shadow register addresses
3664	* @port_mmio: base address of the port	3664	* @port_mmio: base address of the port
3665	*	3665	*
3666	* Initialize shadow register mmio addresses, clear outstanding	3666	* Initialize shadow register mmio addresses, clear outstanding
3667	* interrupts on the port, and unmask interrupts for the future	3667	* interrupts on the port, and unmask interrupts for the future
3668	* start of the port.	3668	* start of the port.
3669	*	3669	*
3670	* LOCKING:	3670	* LOCKING:
3671	* Inherited from caller.	3671	* Inherited from caller.
3672	*/	3672	*/
3673	static void mv_port_init(struct ata_ioports port, void __iomem port_mmio)	3673	static void mv_port_init(struct ata_ioports port, void __iomem port_mmio)
3674	{	3674	{
3675	void __iomem serr, shd_base = port_mmio + SHD_BLK;	3675	void __iomem serr, shd_base = port_mmio + SHD_BLK;
3676		3676
3677	/* PIO related setup	3677	/* PIO related setup
3678	*/	3678	*/
3679	port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);	3679	port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
3680	port->error_addr =	3680	port->error_addr =
3681	port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);	3681	port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
3682	port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);	3682	port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
3683	port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);	3683	port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
3684	port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);	3684	port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
3685	port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);	3685	port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
3686	port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);	3686	port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
3687	port->status_addr =	3687	port->status_addr =
3688	port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);	3688	port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
3689	/* special case: control/altstatus doesn't have ATA_REG_ address */	3689	/* special case: control/altstatus doesn't have ATA_REG_ address */
3690	port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST;	3690	port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST;
3691		3691
3692	/* Clear any currently outstanding port interrupt conditions */	3692	/* Clear any currently outstanding port interrupt conditions */
3693	serr = port_mmio + mv_scr_offset(SCR_ERROR);	3693	serr = port_mmio + mv_scr_offset(SCR_ERROR);
3694	writelfl(readl(serr), serr);	3694	writelfl(readl(serr), serr);
3695	writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE);	3695	writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE);
3696		3696
3697	/* unmask all non-transient EDMA error interrupts */	3697	/* unmask all non-transient EDMA error interrupts */
3698	writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK);	3698	writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK);
3699		3699
3700	VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",	3700	VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
3701	readl(port_mmio + EDMA_CFG),	3701	readl(port_mmio + EDMA_CFG),
3702	readl(port_mmio + EDMA_ERR_IRQ_CAUSE),	3702	readl(port_mmio + EDMA_ERR_IRQ_CAUSE),
3703	readl(port_mmio + EDMA_ERR_IRQ_MASK));	3703	readl(port_mmio + EDMA_ERR_IRQ_MASK));
3704	}	3704	}
3705		3705
3706	static unsigned int mv_in_pcix_mode(struct ata_host *host)	3706	static unsigned int mv_in_pcix_mode(struct ata_host *host)
3707	{	3707	{
3708	struct mv_host_priv *hpriv = host->private_data;	3708	struct mv_host_priv *hpriv = host->private_data;
3709	void __iomem *mmio = hpriv->base;	3709	void __iomem *mmio = hpriv->base;
3710	u32 reg;	3710	u32 reg;
3711		3711
3712	if (IS_SOC(hpriv) \|\| !IS_PCIE(hpriv))	3712	if (IS_SOC(hpriv) \|\| !IS_PCIE(hpriv))
3713	return 0; /* not PCI-X capable */	3713	return 0; /* not PCI-X capable */
3714	reg = readl(mmio + MV_PCI_MODE);	3714	reg = readl(mmio + MV_PCI_MODE);
3715	if ((reg & MV_PCI_MODE_MASK) == 0)	3715	if ((reg & MV_PCI_MODE_MASK) == 0)
3716	return 0; /* conventional PCI mode */	3716	return 0; /* conventional PCI mode */
3717	return 1; /* chip is in PCI-X mode */	3717	return 1; /* chip is in PCI-X mode */
3718	}	3718	}
3719		3719
3720	static int mv_pci_cut_through_okay(struct ata_host *host)	3720	static int mv_pci_cut_through_okay(struct ata_host *host)
3721	{	3721	{
3722	struct mv_host_priv *hpriv = host->private_data;	3722	struct mv_host_priv *hpriv = host->private_data;
3723	void __iomem *mmio = hpriv->base;	3723	void __iomem *mmio = hpriv->base;
3724	u32 reg;	3724	u32 reg;
3725		3725
3726	if (!mv_in_pcix_mode(host)) {	3726	if (!mv_in_pcix_mode(host)) {
3727	reg = readl(mmio + MV_PCI_COMMAND);	3727	reg = readl(mmio + MV_PCI_COMMAND);
3728	if (reg & MV_PCI_COMMAND_MRDTRIG)	3728	if (reg & MV_PCI_COMMAND_MRDTRIG)
3729	return 0; /* not okay */	3729	return 0; /* not okay */
3730	}	3730	}
3731	return 1; /* okay */	3731	return 1; /* okay */
3732	}	3732	}
3733		3733
3734	static void mv_60x1b2_errata_pci7(struct ata_host *host)	3734	static void mv_60x1b2_errata_pci7(struct ata_host *host)
3735	{	3735	{
3736	struct mv_host_priv *hpriv = host->private_data;	3736	struct mv_host_priv *hpriv = host->private_data;
3737	void __iomem *mmio = hpriv->base;	3737	void __iomem *mmio = hpriv->base;
3738		3738
3739	/* workaround for 60x1-B2 errata PCI#7 */	3739	/* workaround for 60x1-B2 errata PCI#7 */
3740	if (mv_in_pcix_mode(host)) {	3740	if (mv_in_pcix_mode(host)) {
3741	u32 reg = readl(mmio + MV_PCI_COMMAND);	3741	u32 reg = readl(mmio + MV_PCI_COMMAND);
3742	writelfl(reg & ~MV_PCI_COMMAND_MWRCOM, mmio + MV_PCI_COMMAND);	3742	writelfl(reg & ~MV_PCI_COMMAND_MWRCOM, mmio + MV_PCI_COMMAND);
3743	}	3743	}
3744	}	3744	}
3745		3745
3746	static int mv_chip_id(struct ata_host *host, unsigned int board_idx)	3746	static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
3747	{	3747	{
3748	struct pci_dev *pdev = to_pci_dev(host->dev);	3748	struct pci_dev *pdev = to_pci_dev(host->dev);
3749	struct mv_host_priv *hpriv = host->private_data;	3749	struct mv_host_priv *hpriv = host->private_data;
3750	u32 hp_flags = hpriv->hp_flags;	3750	u32 hp_flags = hpriv->hp_flags;
3751		3751
3752	switch (board_idx) {	3752	switch (board_idx) {
3753	case chip_5080:	3753	case chip_5080:
3754	hpriv->ops = &mv5xxx_ops;	3754	hpriv->ops = &mv5xxx_ops;
3755	hp_flags \|= MV_HP_GEN_I;	3755	hp_flags \|= MV_HP_GEN_I;
3756		3756
3757	switch (pdev->revision) {	3757	switch (pdev->revision) {
3758	case 0x1:	3758	case 0x1:
3759	hp_flags \|= MV_HP_ERRATA_50XXB0;	3759	hp_flags \|= MV_HP_ERRATA_50XXB0;
3760	break;	3760	break;
3761	case 0x3:	3761	case 0x3:
3762	hp_flags \|= MV_HP_ERRATA_50XXB2;	3762	hp_flags \|= MV_HP_ERRATA_50XXB2;
3763	break;	3763	break;
3764	default:	3764	default:
3765	dev_printk(KERN_WARNING, &pdev->dev,	3765	dev_printk(KERN_WARNING, &pdev->dev,
3766	"Applying 50XXB2 workarounds to unknown rev\n");	3766	"Applying 50XXB2 workarounds to unknown rev\n");
3767	hp_flags \|= MV_HP_ERRATA_50XXB2;	3767	hp_flags \|= MV_HP_ERRATA_50XXB2;
3768	break;	3768	break;
3769	}	3769	}
3770	break;	3770	break;
3771		3771
3772	case chip_504x:	3772	case chip_504x:
3773	case chip_508x:	3773	case chip_508x:
3774	hpriv->ops = &mv5xxx_ops;	3774	hpriv->ops = &mv5xxx_ops;
3775	hp_flags \|= MV_HP_GEN_I;	3775	hp_flags \|= MV_HP_GEN_I;
3776		3776
3777	switch (pdev->revision) {	3777	switch (pdev->revision) {
3778	case 0x0:	3778	case 0x0:
3779	hp_flags \|= MV_HP_ERRATA_50XXB0;	3779	hp_flags \|= MV_HP_ERRATA_50XXB0;
3780	break;	3780	break;
3781	case 0x3:	3781	case 0x3:
3782	hp_flags \|= MV_HP_ERRATA_50XXB2;	3782	hp_flags \|= MV_HP_ERRATA_50XXB2;
3783	break;	3783	break;
3784	default:	3784	default:
3785	dev_printk(KERN_WARNING, &pdev->dev,	3785	dev_printk(KERN_WARNING, &pdev->dev,
3786	"Applying B2 workarounds to unknown rev\n");	3786	"Applying B2 workarounds to unknown rev\n");
3787	hp_flags \|= MV_HP_ERRATA_50XXB2;	3787	hp_flags \|= MV_HP_ERRATA_50XXB2;
3788	break;	3788	break;
3789	}	3789	}
3790	break;	3790	break;
3791		3791
3792	case chip_604x:	3792	case chip_604x:
3793	case chip_608x:	3793	case chip_608x:
3794	hpriv->ops = &mv6xxx_ops;	3794	hpriv->ops = &mv6xxx_ops;
3795	hp_flags \|= MV_HP_GEN_II;	3795	hp_flags \|= MV_HP_GEN_II;
3796		3796
3797	switch (pdev->revision) {	3797	switch (pdev->revision) {
3798	case 0x7:	3798	case 0x7:
3799	mv_60x1b2_errata_pci7(host);	3799	mv_60x1b2_errata_pci7(host);
3800	hp_flags \|= MV_HP_ERRATA_60X1B2;	3800	hp_flags \|= MV_HP_ERRATA_60X1B2;
3801	break;	3801	break;
3802	case 0x9:	3802	case 0x9:
3803	hp_flags \|= MV_HP_ERRATA_60X1C0;	3803	hp_flags \|= MV_HP_ERRATA_60X1C0;
3804	break;	3804	break;
3805	default:	3805	default:
3806	dev_printk(KERN_WARNING, &pdev->dev,	3806	dev_printk(KERN_WARNING, &pdev->dev,
3807	"Applying B2 workarounds to unknown rev\n");	3807	"Applying B2 workarounds to unknown rev\n");
3808	hp_flags \|= MV_HP_ERRATA_60X1B2;	3808	hp_flags \|= MV_HP_ERRATA_60X1B2;
3809	break;	3809	break;
3810	}	3810	}
3811	break;	3811	break;
3812		3812
3813	case chip_7042:	3813	case chip_7042:
3814	hp_flags \|= MV_HP_PCIE \| MV_HP_CUT_THROUGH;	3814	hp_flags \|= MV_HP_PCIE \| MV_HP_CUT_THROUGH;
3815	if (pdev->vendor == PCI_VENDOR_ID_TTI &&	3815	if (pdev->vendor == PCI_VENDOR_ID_TTI &&
3816	(pdev->device == 0x2300 \|\| pdev->device == 0x2310))	3816	(pdev->device == 0x2300 \|\| pdev->device == 0x2310))
3817	{	3817	{
3818	/*	3818	/*
3819	* Highpoint RocketRAID PCIe 23xx series cards:	3819	* Highpoint RocketRAID PCIe 23xx series cards:
3820	*	3820	*
3821	* Unconfigured drives are treated as "Legacy"	3821	* Unconfigured drives are treated as "Legacy"
3822	* by the BIOS, and it overwrites sector 8 with	3822	* by the BIOS, and it overwrites sector 8 with
3823	* a "Lgcy" metadata block prior to Linux boot.	3823	* a "Lgcy" metadata block prior to Linux boot.
3824	*	3824	*
3825	* Configured drives (RAID or JBOD) leave sector 8	3825	* Configured drives (RAID or JBOD) leave sector 8
3826	* alone, but instead overwrite a high numbered	3826	* alone, but instead overwrite a high numbered
3827	* sector for the RAID metadata. This sector can	3827	* sector for the RAID metadata. This sector can
3828	* be determined exactly, by truncating the physical	3828	* be determined exactly, by truncating the physical
3829	* drive capacity to a nice even GB value.	3829	* drive capacity to a nice even GB value.
3830	*	3830	*
3831	* RAID metadata is at: (dev->n_sectors & ~0xfffff)	3831	* RAID metadata is at: (dev->n_sectors & ~0xfffff)
3832	*	3832	*
3833	* Warn the user, lest they think we're just buggy.	3833	* Warn the user, lest they think we're just buggy.
3834	*/	3834	*/
3835	printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID"	3835	printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID"
3836	" BIOS CORRUPTS DATA on all attached drives,"	3836	" BIOS CORRUPTS DATA on all attached drives,"
3837	" regardless of if/how they are configured."	3837	" regardless of if/how they are configured."
3838	" BEWARE!\n");	3838	" BEWARE!\n");
3839	printk(KERN_WARNING DRV_NAME ": For data safety, do not"	3839	printk(KERN_WARNING DRV_NAME ": For data safety, do not"
3840	" use sectors 8-9 on \"Legacy\" drives,"	3840	" use sectors 8-9 on \"Legacy\" drives,"
3841	" and avoid the final two gigabytes on"	3841	" and avoid the final two gigabytes on"
3842	" all RocketRAID BIOS initialized drives.\n");	3842	" all RocketRAID BIOS initialized drives.\n");
3843	}	3843	}
3844	/* drop through */	3844	/* drop through */
3845	case chip_6042:	3845	case chip_6042:
3846	hpriv->ops = &mv6xxx_ops;	3846	hpriv->ops = &mv6xxx_ops;
3847	hp_flags \|= MV_HP_GEN_IIE;	3847	hp_flags \|= MV_HP_GEN_IIE;
3848	if (board_idx == chip_6042 && mv_pci_cut_through_okay(host))	3848	if (board_idx == chip_6042 && mv_pci_cut_through_okay(host))
3849	hp_flags \|= MV_HP_CUT_THROUGH;	3849	hp_flags \|= MV_HP_CUT_THROUGH;
3850		3850
3851	switch (pdev->revision) {	3851	switch (pdev->revision) {
3852	case 0x2: /* Rev.B0: the first/only public release */	3852	case 0x2: /* Rev.B0: the first/only public release */
3853	hp_flags \|= MV_HP_ERRATA_60X1C0;	3853	hp_flags \|= MV_HP_ERRATA_60X1C0;
3854	break;	3854	break;
3855	default:	3855	default:
3856	dev_printk(KERN_WARNING, &pdev->dev,	3856	dev_printk(KERN_WARNING, &pdev->dev,
3857	"Applying 60X1C0 workarounds to unknown rev\n");	3857	"Applying 60X1C0 workarounds to unknown rev\n");
3858	hp_flags \|= MV_HP_ERRATA_60X1C0;	3858	hp_flags \|= MV_HP_ERRATA_60X1C0;
3859	break;	3859	break;
3860	}	3860	}
3861	break;	3861	break;
3862	case chip_soc:	3862	case chip_soc:
3863	if (soc_is_65n(hpriv))	3863	if (soc_is_65n(hpriv))
3864	hpriv->ops = &mv_soc_65n_ops;	3864	hpriv->ops = &mv_soc_65n_ops;
3865	else	3865	else
3866	hpriv->ops = &mv_soc_ops;	3866	hpriv->ops = &mv_soc_ops;
3867	hp_flags \|= MV_HP_FLAG_SOC \| MV_HP_GEN_IIE \|	3867	hp_flags \|= MV_HP_FLAG_SOC \| MV_HP_GEN_IIE \|
3868	MV_HP_ERRATA_60X1C0;	3868	MV_HP_ERRATA_60X1C0;
3869	break;	3869	break;
3870		3870
3871	default:	3871	default:
3872	dev_printk(KERN_ERR, host->dev,	3872	dev_printk(KERN_ERR, host->dev,
3873	"BUG: invalid board index %u\n", board_idx);	3873	"BUG: invalid board index %u\n", board_idx);
3874	return 1;	3874	return 1;
3875	}	3875	}
3876		3876
3877	hpriv->hp_flags = hp_flags;	3877	hpriv->hp_flags = hp_flags;
3878	if (hp_flags & MV_HP_PCIE) {	3878	if (hp_flags & MV_HP_PCIE) {
3879	hpriv->irq_cause_offset = PCIE_IRQ_CAUSE;	3879	hpriv->irq_cause_offset = PCIE_IRQ_CAUSE;
3880	hpriv->irq_mask_offset = PCIE_IRQ_MASK;	3880	hpriv->irq_mask_offset = PCIE_IRQ_MASK;
3881	hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS;	3881	hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS;
3882	} else {	3882	} else {
3883	hpriv->irq_cause_offset = PCI_IRQ_CAUSE;	3883	hpriv->irq_cause_offset = PCI_IRQ_CAUSE;
3884	hpriv->irq_mask_offset = PCI_IRQ_MASK;	3884	hpriv->irq_mask_offset = PCI_IRQ_MASK;
3885	hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS;	3885	hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS;
3886	}	3886	}
3887		3887
3888	return 0;	3888	return 0;
3889	}	3889	}
3890		3890
3891	/**	3891	/**
3892	* mv_init_host - Perform some early initialization of the host.	3892	* mv_init_host - Perform some early initialization of the host.
3893	* @host: ATA host to initialize	3893	* @host: ATA host to initialize
3894	*	3894	*
3895	* If possible, do an early global reset of the host. Then do	3895	* If possible, do an early global reset of the host. Then do
3896	* our port init and clear/unmask all/relevant host interrupts.	3896	* our port init and clear/unmask all/relevant host interrupts.
3897	*	3897	*
3898	* LOCKING:	3898	* LOCKING:
3899	* Inherited from caller.	3899	* Inherited from caller.
3900	*/	3900	*/
3901	static int mv_init_host(struct ata_host *host)	3901	static int mv_init_host(struct ata_host *host)
3902	{	3902	{
3903	int rc = 0, n_hc, port, hc;	3903	int rc = 0, n_hc, port, hc;
3904	struct mv_host_priv *hpriv = host->private_data;	3904	struct mv_host_priv *hpriv = host->private_data;
3905	void __iomem *mmio = hpriv->base;	3905	void __iomem *mmio = hpriv->base;
3906		3906
3907	rc = mv_chip_id(host, hpriv->board_idx);	3907	rc = mv_chip_id(host, hpriv->board_idx);
3908	if (rc)	3908	if (rc)
3909	goto done;	3909	goto done;
3910		3910
3911	if (IS_SOC(hpriv)) {	3911	if (IS_SOC(hpriv)) {
3912	hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE;	3912	hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE;
3913	hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK;	3913	hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK;
3914	} else {	3914	} else {
3915	hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE;	3915	hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE;
3916	hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK;	3916	hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK;
3917	}	3917	}
3918		3918
3919	/* initialize shadow irq mask with register's value */	3919	/* initialize shadow irq mask with register's value */
3920	hpriv->main_irq_mask = readl(hpriv->main_irq_mask_addr);	3920	hpriv->main_irq_mask = readl(hpriv->main_irq_mask_addr);
3921		3921
3922	/* global interrupt mask: 0 == mask everything */	3922	/* global interrupt mask: 0 == mask everything */
3923	mv_set_main_irq_mask(host, ~0, 0);	3923	mv_set_main_irq_mask(host, ~0, 0);
3924		3924
3925	n_hc = mv_get_hc_count(host->ports[0]->flags);	3925	n_hc = mv_get_hc_count(host->ports[0]->flags);
3926		3926
3927	for (port = 0; port < host->n_ports; port++)	3927	for (port = 0; port < host->n_ports; port++)
3928	if (hpriv->ops->read_preamp)	3928	if (hpriv->ops->read_preamp)
3929	hpriv->ops->read_preamp(hpriv, port, mmio);	3929	hpriv->ops->read_preamp(hpriv, port, mmio);
3930		3930
3931	rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);	3931	rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
3932	if (rc)	3932	if (rc)
3933	goto done;	3933	goto done;
3934		3934
3935	hpriv->ops->reset_flash(hpriv, mmio);	3935	hpriv->ops->reset_flash(hpriv, mmio);
3936	hpriv->ops->reset_bus(host, mmio);	3936	hpriv->ops->reset_bus(host, mmio);
3937	hpriv->ops->enable_leds(hpriv, mmio);	3937	hpriv->ops->enable_leds(hpriv, mmio);
3938		3938
3939	for (port = 0; port < host->n_ports; port++) {	3939	for (port = 0; port < host->n_ports; port++) {
3940	struct ata_port *ap = host->ports[port];	3940	struct ata_port *ap = host->ports[port];
3941	void __iomem *port_mmio = mv_port_base(mmio, port);	3941	void __iomem *port_mmio = mv_port_base(mmio, port);
3942		3942
3943	mv_port_init(&ap->ioaddr, port_mmio);	3943	mv_port_init(&ap->ioaddr, port_mmio);
3944	}	3944	}
3945		3945
3946	for (hc = 0; hc < n_hc; hc++) {	3946	for (hc = 0; hc < n_hc; hc++) {
3947	void __iomem *hc_mmio = mv_hc_base(mmio, hc);	3947	void __iomem *hc_mmio = mv_hc_base(mmio, hc);
3948		3948
3949	VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "	3949	VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
3950	"(before clear)=0x%08x\n", hc,	3950	"(before clear)=0x%08x\n", hc,
3951	readl(hc_mmio + HC_CFG),	3951	readl(hc_mmio + HC_CFG),
3952	readl(hc_mmio + HC_IRQ_CAUSE));	3952	readl(hc_mmio + HC_IRQ_CAUSE));
3953		3953
3954	/* Clear any currently outstanding hc interrupt conditions */	3954	/* Clear any currently outstanding hc interrupt conditions */
3955	writelfl(0, hc_mmio + HC_IRQ_CAUSE);	3955	writelfl(0, hc_mmio + HC_IRQ_CAUSE);
3956	}	3956	}
3957		3957
3958	if (!IS_SOC(hpriv)) {	3958	if (!IS_SOC(hpriv)) {
3959	/* Clear any currently outstanding host interrupt conditions */	3959	/* Clear any currently outstanding host interrupt conditions */
3960	writelfl(0, mmio + hpriv->irq_cause_offset);	3960	writelfl(0, mmio + hpriv->irq_cause_offset);
3961		3961
3962	/* and unmask interrupt generation for host regs */	3962	/* and unmask interrupt generation for host regs */
3963	writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_offset);	3963	writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_offset);
3964	}	3964	}
3965		3965
3966	/*	3966	/*
3967	* enable only global host interrupts for now.	3967	* enable only global host interrupts for now.
3968	* The per-port interrupts get done later as ports are set up.	3968	* The per-port interrupts get done later as ports are set up.
3969	*/	3969	*/
3970	mv_set_main_irq_mask(host, 0, PCI_ERR);	3970	mv_set_main_irq_mask(host, 0, PCI_ERR);
3971	mv_set_irq_coalescing(host, irq_coalescing_io_count,	3971	mv_set_irq_coalescing(host, irq_coalescing_io_count,
3972	irq_coalescing_usecs);	3972	irq_coalescing_usecs);
3973	done:	3973	done:
3974	return rc;	3974	return rc;
3975	}	3975	}
3976		3976
3977	static int mv_create_dma_pools(struct mv_host_priv hpriv, struct device dev)	3977	static int mv_create_dma_pools(struct mv_host_priv hpriv, struct device dev)
3978	{	3978	{
3979	hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ,	3979	hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ,
3980	MV_CRQB_Q_SZ, 0);	3980	MV_CRQB_Q_SZ, 0);
3981	if (!hpriv->crqb_pool)	3981	if (!hpriv->crqb_pool)
3982	return -ENOMEM;	3982	return -ENOMEM;
3983		3983
3984	hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ,	3984	hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ,
3985	MV_CRPB_Q_SZ, 0);	3985	MV_CRPB_Q_SZ, 0);
3986	if (!hpriv->crpb_pool)	3986	if (!hpriv->crpb_pool)
3987	return -ENOMEM;	3987	return -ENOMEM;
3988		3988
3989	hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ,	3989	hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ,
3990	MV_SG_TBL_SZ, 0);	3990	MV_SG_TBL_SZ, 0);
3991	if (!hpriv->sg_tbl_pool)	3991	if (!hpriv->sg_tbl_pool)
3992	return -ENOMEM;	3992	return -ENOMEM;
3993		3993
3994	return 0;	3994	return 0;
3995	}	3995	}
3996		3996
3997	static void mv_conf_mbus_windows(struct mv_host_priv *hpriv,	3997	static void mv_conf_mbus_windows(struct mv_host_priv *hpriv,
3998	struct mbus_dram_target_info *dram)	3998	struct mbus_dram_target_info *dram)
3999	{	3999	{
4000	int i;	4000	int i;
4001		4001
4002	for (i = 0; i < 4; i++) {	4002	for (i = 0; i < 4; i++) {
4003	writel(0, hpriv->base + WINDOW_CTRL(i));	4003	writel(0, hpriv->base + WINDOW_CTRL(i));
4004	writel(0, hpriv->base + WINDOW_BASE(i));	4004	writel(0, hpriv->base + WINDOW_BASE(i));
4005	}	4005	}
4006		4006
4007	for (i = 0; i < dram->num_cs; i++) {	4007	for (i = 0; i < dram->num_cs; i++) {
4008	struct mbus_dram_window *cs = dram->cs + i;	4008	struct mbus_dram_window *cs = dram->cs + i;
4009		4009
4010	writel(((cs->size - 1) & 0xffff0000) \|	4010	writel(((cs->size - 1) & 0xffff0000) \|
4011	(cs->mbus_attr << 8) \|	4011	(cs->mbus_attr << 8) \|
4012	(dram->mbus_dram_target_id << 4) \| 1,	4012	(dram->mbus_dram_target_id << 4) \| 1,
4013	hpriv->base + WINDOW_CTRL(i));	4013	hpriv->base + WINDOW_CTRL(i));
4014	writel(cs->base, hpriv->base + WINDOW_BASE(i));	4014	writel(cs->base, hpriv->base + WINDOW_BASE(i));
4015	}	4015	}
4016	}	4016	}
4017		4017
4018	/**	4018	/**
4019	* mv_platform_probe - handle a positive probe of an soc Marvell	4019	* mv_platform_probe - handle a positive probe of an soc Marvell
4020	* host	4020	* host
4021	* @pdev: platform device found	4021	* @pdev: platform device found
4022	*	4022	*
4023	* LOCKING:	4023	* LOCKING:
4024	* Inherited from caller.	4024	* Inherited from caller.
4025	*/	4025	*/
4026	static int mv_platform_probe(struct platform_device *pdev)	4026	static int mv_platform_probe(struct platform_device *pdev)
4027	{	4027	{
4028	static int printed_version;	4028	static int printed_version;
4029	const struct mv_sata_platform_data *mv_platform_data;	4029	const struct mv_sata_platform_data *mv_platform_data;
4030	const struct ata_port_info *ppi[] =	4030	const struct ata_port_info *ppi[] =
4031	{ &mv_port_info[chip_soc], NULL };	4031	{ &mv_port_info[chip_soc], NULL };
4032	struct ata_host *host;	4032	struct ata_host *host;
4033	struct mv_host_priv *hpriv;	4033	struct mv_host_priv *hpriv;
4034	struct resource *res;	4034	struct resource *res;
4035	int n_ports, rc;	4035	int n_ports, rc;
4036		4036
4037	if (!printed_version++)	4037	if (!printed_version++)
4038	dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");	4038	dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
4039		4039
4040	/*	4040	/*
4041	* Simple resource validation ..	4041	* Simple resource validation ..
4042	*/	4042	*/
4043	if (unlikely(pdev->num_resources != 2)) {	4043	if (unlikely(pdev->num_resources != 2)) {
4044	dev_err(&pdev->dev, "invalid number of resources\n");	4044	dev_err(&pdev->dev, "invalid number of resources\n");
4045	return -EINVAL;	4045	return -EINVAL;
4046	}	4046	}
4047		4047
4048	/*	4048	/*
4049	* Get the register base first	4049	* Get the register base first
4050	*/	4050	*/
4051	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);	4051	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4052	if (res == NULL)	4052	if (res == NULL)
4053	return -EINVAL;	4053	return -EINVAL;
4054		4054
4055	/* allocate host */	4055	/* allocate host */
4056	mv_platform_data = pdev->dev.platform_data;	4056	mv_platform_data = pdev->dev.platform_data;
4057	n_ports = mv_platform_data->n_ports;	4057	n_ports = mv_platform_data->n_ports;
4058		4058
4059	host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);	4059	host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4060	hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);	4060	hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
4061		4061
4062	if (!host \|\| !hpriv)	4062	if (!host \|\| !hpriv)
4063	return -ENOMEM;	4063	return -ENOMEM;
4064	host->private_data = hpriv;	4064	host->private_data = hpriv;
4065	hpriv->n_ports = n_ports;	4065	hpriv->n_ports = n_ports;
4066	hpriv->board_idx = chip_soc;	4066	hpriv->board_idx = chip_soc;
4067		4067
4068	host->iomap = NULL;	4068	host->iomap = NULL;
4069	hpriv->base = devm_ioremap(&pdev->dev, res->start,	4069	hpriv->base = devm_ioremap(&pdev->dev, res->start,
4070	resource_size(res));	4070	resource_size(res));
4071	hpriv->base -= SATAHC0_REG_BASE;	4071	hpriv->base -= SATAHC0_REG_BASE;
4072		4072
4073	#if defined(CONFIG_HAVE_CLK)	4073	#if defined(CONFIG_HAVE_CLK)
4074	hpriv->clk = clk_get(&pdev->dev, NULL);	4074	hpriv->clk = clk_get(&pdev->dev, NULL);
4075	if (IS_ERR(hpriv->clk))	4075	if (IS_ERR(hpriv->clk))
4076	dev_notice(&pdev->dev, "cannot get clkdev\n");	4076	dev_notice(&pdev->dev, "cannot get clkdev\n");
4077	else	4077	else
4078	clk_enable(hpriv->clk);	4078	clk_enable(hpriv->clk);
4079	#endif	4079	#endif
4080		4080
4081	/*	4081	/*
4082	* (Re-)program MBUS remapping windows if we are asked to.	4082	* (Re-)program MBUS remapping windows if we are asked to.
4083	*/	4083	*/
4084	if (mv_platform_data->dram != NULL)	4084	if (mv_platform_data->dram != NULL)
4085	mv_conf_mbus_windows(hpriv, mv_platform_data->dram);	4085	mv_conf_mbus_windows(hpriv, mv_platform_data->dram);
4086		4086
4087	rc = mv_create_dma_pools(hpriv, &pdev->dev);	4087	rc = mv_create_dma_pools(hpriv, &pdev->dev);
4088	if (rc)	4088	if (rc)
4089	goto err;	4089	goto err;
4090		4090
4091	/* initialize adapter */	4091	/* initialize adapter */
4092	rc = mv_init_host(host);	4092	rc = mv_init_host(host);
4093	if (rc)	4093	if (rc)
4094	goto err;	4094	goto err;
4095		4095
4096	dev_printk(KERN_INFO, &pdev->dev,	4096	dev_printk(KERN_INFO, &pdev->dev,
4097	"slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH,	4097	"slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH,
4098	host->n_ports);	4098	host->n_ports);
4099		4099
4100	return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt,	4100	return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt,
4101	IRQF_SHARED, &mv6_sht);	4101	IRQF_SHARED, &mv6_sht);
4102	err:	4102	err:
4103	#if defined(CONFIG_HAVE_CLK)	4103	#if defined(CONFIG_HAVE_CLK)
4104	if (!IS_ERR(hpriv->clk)) {	4104	if (!IS_ERR(hpriv->clk)) {
4105	clk_disable(hpriv->clk);	4105	clk_disable(hpriv->clk);
4106	clk_put(hpriv->clk);	4106	clk_put(hpriv->clk);
4107	}	4107	}
4108	#endif	4108	#endif
4109		4109
4110	return rc;	4110	return rc;
4111	}	4111	}
4112		4112
4113	/*	4113	/*
4114	*	4114	*
4115	* mv_platform_remove - unplug a platform interface	4115	* mv_platform_remove - unplug a platform interface
4116	* @pdev: platform device	4116	* @pdev: platform device
4117	*	4117	*
4118	* A platform bus SATA device has been unplugged. Perform the needed	4118	* A platform bus SATA device has been unplugged. Perform the needed
4119	* cleanup. Also called on module unload for any active devices.	4119	* cleanup. Also called on module unload for any active devices.
4120	*/	4120	*/
4121	static int __devexit mv_platform_remove(struct platform_device *pdev)	4121	static int __devexit mv_platform_remove(struct platform_device *pdev)
4122	{	4122	{
4123	struct device *dev = &pdev->dev;	4123	struct device *dev = &pdev->dev;
4124	struct ata_host *host = dev_get_drvdata(dev);	4124	struct ata_host *host = dev_get_drvdata(dev);
4125	#if defined(CONFIG_HAVE_CLK)	4125	#if defined(CONFIG_HAVE_CLK)
4126	struct mv_host_priv *hpriv = host->private_data;	4126	struct mv_host_priv *hpriv = host->private_data;
4127	#endif	4127	#endif
4128	ata_host_detach(host);	4128	ata_host_detach(host);
4129		4129
4130	#if defined(CONFIG_HAVE_CLK)	4130	#if defined(CONFIG_HAVE_CLK)
4131	if (!IS_ERR(hpriv->clk)) {	4131	if (!IS_ERR(hpriv->clk)) {
4132	clk_disable(hpriv->clk);	4132	clk_disable(hpriv->clk);
4133	clk_put(hpriv->clk);	4133	clk_put(hpriv->clk);
4134	}	4134	}
4135	#endif	4135	#endif
4136	return 0;	4136	return 0;
4137	}	4137	}
4138		4138
4139	#ifdef CONFIG_PM	4139	#ifdef CONFIG_PM
4140	static int mv_platform_suspend(struct platform_device *pdev, pm_message_t state)	4140	static int mv_platform_suspend(struct platform_device *pdev, pm_message_t state)
4141	{	4141	{
4142	struct ata_host *host = dev_get_drvdata(&pdev->dev);	4142	struct ata_host *host = dev_get_drvdata(&pdev->dev);
4143	if (host)	4143	if (host)
4144	return ata_host_suspend(host, state);	4144	return ata_host_suspend(host, state);
4145	else	4145	else
4146	return 0;	4146	return 0;
4147	}	4147	}
4148		4148
4149	static int mv_platform_resume(struct platform_device *pdev)	4149	static int mv_platform_resume(struct platform_device *pdev)
4150	{	4150	{
4151	struct ata_host *host = dev_get_drvdata(&pdev->dev);	4151	struct ata_host *host = dev_get_drvdata(&pdev->dev);
4152	int ret;	4152	int ret;
4153		4153
4154	if (host) {	4154	if (host) {
4155	struct mv_host_priv *hpriv = host->private_data;	4155	struct mv_host_priv *hpriv = host->private_data;
4156	const struct mv_sata_platform_data *mv_platform_data = \	4156	const struct mv_sata_platform_data *mv_platform_data = \
4157	pdev->dev.platform_data;	4157	pdev->dev.platform_data;
4158	/*	4158	/*
4159	* (Re-)program MBUS remapping windows if we are asked to.	4159	* (Re-)program MBUS remapping windows if we are asked to.
4160	*/	4160	*/
4161	if (mv_platform_data->dram != NULL)	4161	if (mv_platform_data->dram != NULL)
4162	mv_conf_mbus_windows(hpriv, mv_platform_data->dram);	4162	mv_conf_mbus_windows(hpriv, mv_platform_data->dram);
4163		4163
4164	/* initialize adapter */	4164	/* initialize adapter */
4165	ret = mv_init_host(host);	4165	ret = mv_init_host(host);
4166	if (ret) {	4166	if (ret) {
4167	printk(KERN_ERR DRV_NAME ": Error during HW init\n");	4167	printk(KERN_ERR DRV_NAME ": Error during HW init\n");
4168	return ret;	4168	return ret;
4169	}	4169	}
4170	ata_host_resume(host);	4170	ata_host_resume(host);
4171	}	4171	}
4172		4172
4173	return 0;	4173	return 0;
4174	}	4174	}
4175	#else	4175	#else
4176	#define mv_platform_suspend NULL	4176	#define mv_platform_suspend NULL
4177	#define mv_platform_resume NULL	4177	#define mv_platform_resume NULL
4178	#endif	4178	#endif
4179		4179
4180	static struct platform_driver mv_platform_driver = {	4180	static struct platform_driver mv_platform_driver = {
4181	.probe = mv_platform_probe,	4181	.probe = mv_platform_probe,
4182	.remove = __devexit_p(mv_platform_remove),	4182	.remove = __devexit_p(mv_platform_remove),
4183	.suspend = mv_platform_suspend,	4183	.suspend = mv_platform_suspend,
4184	.resume = mv_platform_resume,	4184	.resume = mv_platform_resume,
4185	.driver = {	4185	.driver = {
4186	.name = DRV_NAME,	4186	.name = DRV_NAME,
4187	.owner = THIS_MODULE,	4187	.owner = THIS_MODULE,
4188	},	4188	},
4189	};	4189	};
4190		4190
4191		4191
4192	#ifdef CONFIG_PCI	4192	#ifdef CONFIG_PCI
4193	static int mv_pci_init_one(struct pci_dev *pdev,	4193	static int mv_pci_init_one(struct pci_dev *pdev,
4194	const struct pci_device_id *ent);	4194	const struct pci_device_id *ent);
4195	#ifdef CONFIG_PM	4195	#ifdef CONFIG_PM
4196	static int mv_pci_device_resume(struct pci_dev *pdev);	4196	static int mv_pci_device_resume(struct pci_dev *pdev);
4197	#endif	4197	#endif
4198		4198
4199		4199
4200	static struct pci_driver mv_pci_driver = {	4200	static struct pci_driver mv_pci_driver = {
4201	.name = DRV_NAME,	4201	.name = DRV_NAME,
4202	.id_table = mv_pci_tbl,	4202	.id_table = mv_pci_tbl,
4203	.probe = mv_pci_init_one,	4203	.probe = mv_pci_init_one,
4204	.remove = ata_pci_remove_one,	4204	.remove = ata_pci_remove_one,
4205	#ifdef CONFIG_PM	4205	#ifdef CONFIG_PM
4206	.suspend = ata_pci_device_suspend,	4206	.suspend = ata_pci_device_suspend,
4207	.resume = mv_pci_device_resume,	4207	.resume = mv_pci_device_resume,
4208	#endif	4208	#endif
4209		4209
4210	};	4210	};
4211		4211
4212	/* move to PCI layer or libata core? */	4212	/* move to PCI layer or libata core? */
4213	static int pci_go_64(struct pci_dev *pdev)	4213	static int pci_go_64(struct pci_dev *pdev)
4214	{	4214	{
4215	int rc;	4215	int rc;
4216		4216
4217	if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {	4217	if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
4218	rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));	4218	rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4219	if (rc) {	4219	if (rc) {
4220	rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));	4220	rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
4221	if (rc) {	4221	if (rc) {
4222	dev_printk(KERN_ERR, &pdev->dev,	4222	dev_printk(KERN_ERR, &pdev->dev,
4223	"64-bit DMA enable failed\n");	4223	"64-bit DMA enable failed\n");
4224	return rc;	4224	return rc;
4225	}	4225	}
4226	}	4226	}
4227	} else {	4227	} else {
4228	rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));	4228	rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4229	if (rc) {	4229	if (rc) {
4230	dev_printk(KERN_ERR, &pdev->dev,	4230	dev_printk(KERN_ERR, &pdev->dev,
4231	"32-bit DMA enable failed\n");	4231	"32-bit DMA enable failed\n");
4232	return rc;	4232	return rc;
4233	}	4233	}
4234	rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));	4234	rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
4235	if (rc) {	4235	if (rc) {
4236	dev_printk(KERN_ERR, &pdev->dev,	4236	dev_printk(KERN_ERR, &pdev->dev,
4237	"32-bit consistent DMA enable failed\n");	4237	"32-bit consistent DMA enable failed\n");
4238	return rc;	4238	return rc;
4239	}	4239	}
4240	}	4240	}
4241		4241
4242	return rc;	4242	return rc;
4243	}	4243	}
4244		4244
4245	/**	4245	/**
4246	* mv_print_info - Dump key info to kernel log for perusal.	4246	* mv_print_info - Dump key info to kernel log for perusal.
4247	* @host: ATA host to print info about	4247	* @host: ATA host to print info about
4248	*	4248	*
4249	* FIXME: complete this.	4249	* FIXME: complete this.
4250	*	4250	*
4251	* LOCKING:	4251	* LOCKING:
4252	* Inherited from caller.	4252	* Inherited from caller.
4253	*/	4253	*/
4254	static void mv_print_info(struct ata_host *host)	4254	static void mv_print_info(struct ata_host *host)
4255	{	4255	{
4256	struct pci_dev *pdev = to_pci_dev(host->dev);	4256	struct pci_dev *pdev = to_pci_dev(host->dev);
4257	struct mv_host_priv *hpriv = host->private_data;	4257	struct mv_host_priv *hpriv = host->private_data;
4258	u8 scc;	4258	u8 scc;
4259	const char scc_s, gen;	4259	const char scc_s, gen;
4260		4260
4261	/* Use this to determine the HW stepping of the chip so we know	4261	/* Use this to determine the HW stepping of the chip so we know
4262	* what errata to workaround	4262	* what errata to workaround
4263	*/	4263	*/
4264	pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);	4264	pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
4265	if (scc == 0)	4265	if (scc == 0)
4266	scc_s = "SCSI";	4266	scc_s = "SCSI";
4267	else if (scc == 0x01)	4267	else if (scc == 0x01)
4268	scc_s = "RAID";	4268	scc_s = "RAID";
4269	else	4269	else
4270	scc_s = "?";	4270	scc_s = "?";
4271		4271
4272	if (IS_GEN_I(hpriv))	4272	if (IS_GEN_I(hpriv))
4273	gen = "I";	4273	gen = "I";
4274	else if (IS_GEN_II(hpriv))	4274	else if (IS_GEN_II(hpriv))
4275	gen = "II";	4275	gen = "II";
4276	else if (IS_GEN_IIE(hpriv))	4276	else if (IS_GEN_IIE(hpriv))
4277	gen = "IIE";	4277	gen = "IIE";
4278	else	4278	else
4279	gen = "?";	4279	gen = "?";
4280		4280
4281	dev_printk(KERN_INFO, &pdev->dev,	4281	dev_printk(KERN_INFO, &pdev->dev,
4282	"Gen-%s %u slots %u ports %s mode IRQ via %s\n",	4282	"Gen-%s %u slots %u ports %s mode IRQ via %s\n",
4283	gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports,	4283	gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports,
4284	scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");	4284	scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
4285	}	4285	}
4286		4286
4287	/**	4287	/**
4288	* mv_pci_init_one - handle a positive probe of a PCI Marvell host	4288	* mv_pci_init_one - handle a positive probe of a PCI Marvell host
4289	* @pdev: PCI device found	4289	* @pdev: PCI device found
4290	* @ent: PCI device ID entry for the matched host	4290	* @ent: PCI device ID entry for the matched host
4291	*	4291	*
4292	* LOCKING:	4292	* LOCKING:
4293	* Inherited from caller.	4293	* Inherited from caller.
4294	*/	4294	*/
4295	static int mv_pci_init_one(struct pci_dev *pdev,	4295	static int mv_pci_init_one(struct pci_dev *pdev,
4296	const struct pci_device_id *ent)	4296	const struct pci_device_id *ent)
4297	{	4297	{
4298	static int printed_version;	4298	static int printed_version;
4299	unsigned int board_idx = (unsigned int)ent->driver_data;	4299	unsigned int board_idx = (unsigned int)ent->driver_data;
4300	const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL };	4300	const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL };
4301	struct ata_host *host;	4301	struct ata_host *host;
4302	struct mv_host_priv *hpriv;	4302	struct mv_host_priv *hpriv;
4303	int n_ports, port, rc;	4303	int n_ports, port, rc;
4304		4304
4305	if (!printed_version++)	4305	if (!printed_version++)
4306	dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");	4306	dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
4307		4307
4308	/* allocate host */	4308	/* allocate host */
4309	n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC;	4309	n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC;
4310		4310
4311	host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);	4311	host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4312	hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);	4312	hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
4313	if (!host \|\| !hpriv)	4313	if (!host \|\| !hpriv)
4314	return -ENOMEM;	4314	return -ENOMEM;
4315	host->private_data = hpriv;	4315	host->private_data = hpriv;
4316	hpriv->n_ports = n_ports;	4316	hpriv->n_ports = n_ports;
4317	hpriv->board_idx = board_idx;	4317	hpriv->board_idx = board_idx;
4318		4318
4319	/* acquire resources */	4319	/* acquire resources */
4320	rc = pcim_enable_device(pdev);	4320	rc = pcim_enable_device(pdev);
4321	if (rc)	4321	if (rc)
4322	return rc;	4322	return rc;
4323		4323
4324	rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME);	4324	rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME);
4325	if (rc == -EBUSY)	4325	if (rc == -EBUSY)
4326	pcim_pin_device(pdev);	4326	pcim_pin_device(pdev);
4327	if (rc)	4327	if (rc)
4328	return rc;	4328	return rc;
4329	host->iomap = pcim_iomap_table(pdev);	4329	host->iomap = pcim_iomap_table(pdev);
4330	hpriv->base = host->iomap[MV_PRIMARY_BAR];	4330	hpriv->base = host->iomap[MV_PRIMARY_BAR];
4331		4331
4332	rc = pci_go_64(pdev);	4332	rc = pci_go_64(pdev);
4333	if (rc)	4333	if (rc)
4334	return rc;	4334	return rc;
4335		4335
4336	rc = mv_create_dma_pools(hpriv, &pdev->dev);	4336	rc = mv_create_dma_pools(hpriv, &pdev->dev);
4337	if (rc)	4337	if (rc)
4338	return rc;	4338	return rc;
4339		4339
4340	for (port = 0; port < host->n_ports; port++) {	4340	for (port = 0; port < host->n_ports; port++) {
4341	struct ata_port *ap = host->ports[port];	4341	struct ata_port *ap = host->ports[port];
4342	void __iomem *port_mmio = mv_port_base(hpriv->base, port);	4342	void __iomem *port_mmio = mv_port_base(hpriv->base, port);
4343	unsigned int offset = port_mmio - hpriv->base;	4343	unsigned int offset = port_mmio - hpriv->base;
4344		4344
4345	ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio");	4345	ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio");
4346	ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port");	4346	ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port");
4347	}	4347	}
4348		4348
4349	/* initialize adapter */	4349	/* initialize adapter */
4350	rc = mv_init_host(host);	4350	rc = mv_init_host(host);
4351	if (rc)	4351	if (rc)
4352	return rc;	4352	return rc;
4353		4353
4354	/* Enable message-switched interrupts, if requested */	4354	/* Enable message-switched interrupts, if requested */
4355	if (msi && pci_enable_msi(pdev) == 0)	4355	if (msi && pci_enable_msi(pdev) == 0)
4356	hpriv->hp_flags \|= MV_HP_FLAG_MSI;	4356	hpriv->hp_flags \|= MV_HP_FLAG_MSI;
4357		4357
4358	mv_dump_pci_cfg(pdev, 0x68);	4358	mv_dump_pci_cfg(pdev, 0x68);
4359	mv_print_info(host);	4359	mv_print_info(host);
4360		4360
4361	pci_set_master(pdev);	4361	pci_set_master(pdev);
4362	pci_try_set_mwi(pdev);	4362	pci_try_set_mwi(pdev);
4363	return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED,	4363	return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED,
4364	IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht);	4364	IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht);
4365	}	4365	}
4366		4366
4367	#ifdef CONFIG_PM	4367	#ifdef CONFIG_PM
4368	static int mv_pci_device_resume(struct pci_dev *pdev)	4368	static int mv_pci_device_resume(struct pci_dev *pdev)
4369	{	4369	{
4370	struct ata_host *host = dev_get_drvdata(&pdev->dev);	4370	struct ata_host *host = dev_get_drvdata(&pdev->dev);
4371	int rc;	4371	int rc;
4372		4372
4373	rc = ata_pci_device_do_resume(pdev);	4373	rc = ata_pci_device_do_resume(pdev);
4374	if (rc)	4374	if (rc)
4375	return rc;	4375	return rc;
4376		4376
4377	/* initialize adapter */	4377	/* initialize adapter */
4378	rc = mv_init_host(host);	4378	rc = mv_init_host(host);
4379	if (rc)	4379	if (rc)
4380	return rc;	4380	return rc;
4381		4381
4382	ata_host_resume(host);	4382	ata_host_resume(host);
4383		4383
4384	return 0;	4384	return 0;
4385	}	4385	}
4386	#endif	4386	#endif
4387	#endif	4387	#endif
4388		4388
4389	static int mv_platform_probe(struct platform_device *pdev);	4389	static int mv_platform_probe(struct platform_device *pdev);
4390	static int __devexit mv_platform_remove(struct platform_device *pdev);	4390	static int __devexit mv_platform_remove(struct platform_device *pdev);
4391		4391
4392	static int __init mv_init(void)	4392	static int __init mv_init(void)
4393	{	4393	{
4394	int rc = -ENODEV;	4394	int rc = -ENODEV;
4395	#ifdef CONFIG_PCI	4395	#ifdef CONFIG_PCI
4396	rc = pci_register_driver(&mv_pci_driver);	4396	rc = pci_register_driver(&mv_pci_driver);
4397	if (rc < 0)	4397	if (rc < 0)
4398	return rc;	4398	return rc;
4399	#endif	4399	#endif
4400	rc = platform_driver_register(&mv_platform_driver);	4400	rc = platform_driver_register(&mv_platform_driver);
4401		4401
4402	#ifdef CONFIG_PCI	4402	#ifdef CONFIG_PCI
4403	if (rc < 0)	4403	if (rc < 0)
4404	pci_unregister_driver(&mv_pci_driver);	4404	pci_unregister_driver(&mv_pci_driver);
4405	#endif	4405	#endif
4406	return rc;	4406	return rc;
4407	}	4407	}
4408		4408
4409	static void __exit mv_exit(void)	4409	static void __exit mv_exit(void)
4410	{	4410	{
4411	#ifdef CONFIG_PCI	4411	#ifdef CONFIG_PCI
4412	pci_unregister_driver(&mv_pci_driver);	4412	pci_unregister_driver(&mv_pci_driver);
4413	#endif	4413	#endif
4414	platform_driver_unregister(&mv_platform_driver);	4414	platform_driver_unregister(&mv_platform_driver);
4415	}	4415	}
4416		4416
4417	MODULE_AUTHOR("Brett Russ");	4417	MODULE_AUTHOR("Brett Russ");
4418	MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");	4418	MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
4419	MODULE_LICENSE("GPL");	4419	MODULE_LICENSE("GPL");
4420	MODULE_DEVICE_TABLE(pci, mv_pci_tbl);	4420	MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
4421	MODULE_VERSION(DRV_VERSION);	4421	MODULE_VERSION(DRV_VERSION);
4422	MODULE_ALIAS("platform:" DRV_NAME);	4422	MODULE_ALIAS("platform:" DRV_NAME);
4423		4423
4424	module_init(mv_init);	4424	module_init(mv_init);
4425	module_exit(mv_exit);	4425	module_exit(mv_exit);
4426		4426

include/linux/libata.h

Diff comments View file @ df423dc

 /*
  *  Copyright 2003-2005 Red Hat, Inc.  All rights reserved.
  *  Copyright 2003-2005 Jeff Garzik
  *
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
  *  the Free Software Foundation; either version 2, or (at your option)
  *  any later version.
  *
  *  This program is distributed in the hope that it will be useful,
  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  *  GNU General Public License for more details.
  *
  *  You should have received a copy of the GNU General Public License
  *  along with this program; see the file COPYING.  If not, write to
  *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  *
  *
  *  libata documentation is available via 'make {ps|pdf}docs',
  *  as Documentation/DocBook/libata.*
  *
  */
 #ifndef __LINUX_LIBATA_H__
 #define __LINUX_LIBATA_H__
 #include <linux/delay.h>
 #include <linux/jiffies.h>
 #include <linux/interrupt.h>
 #include <linux/dma-mapping.h>
 #include <linux/scatterlist.h>
 #include <linux/io.h>
 #include <linux/ata.h>
 #include <linux/workqueue.h>
 #include <scsi/scsi_host.h>
 #include <linux/acpi.h>
 #include <linux/cdrom.h>
 /*
  * Define if arch has non-standard setup.  This is a _PCI_ standard
  * not a legacy or ISA standard.
  */
 #ifdef CONFIG_ATA_NONSTANDARD
 #include <asm/libata-portmap.h>
 #else
 #include <asm-generic/libata-portmap.h>
 #endif
 /*
  * compile-time options: to be removed as soon as all the drivers are
  * converted to the new debugging mechanism
  */
 #undef ATA_DEBUG		/* debugging output */
 #undef ATA_VERBOSE_DEBUG	/* yet more debugging output */
 #undef ATA_IRQ_TRAP		/* define to ack screaming irqs */
 #undef ATA_NDEBUG		/* define to disable quick runtime checks */
 /* note: prints function name for you */
 #ifdef ATA_DEBUG
 #define DPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__, ## args)
 #ifdef ATA_VERBOSE_DEBUG
 #define VPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__, ## args)
 #else
 #define VPRINTK(fmt, args...)
 #endif	/* ATA_VERBOSE_DEBUG */
 #else
 #define DPRINTK(fmt, args...)
 #define VPRINTK(fmt, args...)
 #endif	/* ATA_DEBUG */
 #define BPRINTK(fmt, args...) if (ap->flags & ATA_FLAG_DEBUGMSG) printk(KERN_ERR "%s: " fmt, __func__, ## args)
 /* NEW: debug levels */
 #define HAVE_LIBATA_MSG 1
 enum {
 	ATA_MSG_DRV	= 0x0001,
 	ATA_MSG_INFO	= 0x0002,
 	ATA_MSG_PROBE	= 0x0004,
 	ATA_MSG_WARN	= 0x0008,
 	ATA_MSG_MALLOC	= 0x0010,
 	ATA_MSG_CTL	= 0x0020,
 	ATA_MSG_INTR	= 0x0040,
 	ATA_MSG_ERR	= 0x0080,
 };
 #define ata_msg_drv(p)    ((p)->msg_enable & ATA_MSG_DRV)
 #define ata_msg_info(p)   ((p)->msg_enable & ATA_MSG_INFO)
 #define ata_msg_probe(p)  ((p)->msg_enable & ATA_MSG_PROBE)
 #define ata_msg_warn(p)   ((p)->msg_enable & ATA_MSG_WARN)
 #define ata_msg_malloc(p) ((p)->msg_enable & ATA_MSG_MALLOC)
 #define ata_msg_ctl(p)    ((p)->msg_enable & ATA_MSG_CTL)
 #define ata_msg_intr(p)   ((p)->msg_enable & ATA_MSG_INTR)
 #define ata_msg_err(p)    ((p)->msg_enable & ATA_MSG_ERR)
 static inline u32 ata_msg_init(int dval, int default_msg_enable_bits)
 {
 	if (dval < 0 || dval >= (sizeof(u32) * 8))
 		return default_msg_enable_bits; /* should be 0x1 - only driver info msgs */
 	if (!dval)
 		return 0;
 	return (1 << dval) - 1;
 }
 /* defines only for the constants which don't work well as enums */
 #define ATA_TAG_POISON		0xfafbfcfdU
 enum {
 	/* various global constants */
 	LIBATA_MAX_PRD		= ATA_MAX_PRD / 2,
 	LIBATA_DUMB_MAX_PRD	= ATA_MAX_PRD / 4,	/* Worst case */
 	ATA_DEF_QUEUE		= 1,
 	/* tag ATA_MAX_QUEUE - 1 is reserved for internal commands */
 	ATA_MAX_QUEUE		= 32,
 	ATA_TAG_INTERNAL	= ATA_MAX_QUEUE - 1,
 	ATA_SHORT_PAUSE		= 16,
 	ATAPI_MAX_DRAIN		= 16 << 10,
 	ATA_ALL_DEVICES		= (1 << ATA_MAX_DEVICES) - 1,
 	ATA_SHT_EMULATED	= 1,
 	ATA_SHT_CMD_PER_LUN	= 1,
 	ATA_SHT_THIS_ID		= -1,
 	ATA_SHT_USE_CLUSTERING	= 1,
 	/* struct ata_device stuff */
 	ATA_DFLAG_LBA		= (1 << 0), /* device supports LBA */
 	ATA_DFLAG_LBA48		= (1 << 1), /* device supports LBA48 */
 	ATA_DFLAG_CDB_INTR	= (1 << 2), /* device asserts INTRQ when ready for CDB */
 	ATA_DFLAG_NCQ		= (1 << 3), /* device supports NCQ */
 	ATA_DFLAG_FLUSH_EXT	= (1 << 4), /* do FLUSH_EXT instead of FLUSH */
 	ATA_DFLAG_ACPI_PENDING	= (1 << 5), /* ACPI resume action pending */
 	ATA_DFLAG_ACPI_FAILED	= (1 << 6), /* ACPI on devcfg has failed */
 	ATA_DFLAG_AN		= (1 << 7), /* AN configured */
 	ATA_DFLAG_HIPM		= (1 << 8), /* device supports HIPM */
 	ATA_DFLAG_DIPM		= (1 << 9), /* device supports DIPM */
 	ATA_DFLAG_DMADIR	= (1 << 10), /* device requires DMADIR */
 	ATA_DFLAG_CFG_MASK	= (1 << 12) - 1,
 	ATA_DFLAG_PIO		= (1 << 12), /* device limited to PIO mode */
 	ATA_DFLAG_NCQ_OFF	= (1 << 13), /* device limited to non-NCQ mode */
 	ATA_DFLAG_SLEEPING	= (1 << 15), /* device is sleeping */
 	ATA_DFLAG_DUBIOUS_XFER	= (1 << 16), /* data transfer not verified */
 	ATA_DFLAG_NO_UNLOAD	= (1 << 17), /* device doesn't support unload */
 	ATA_DFLAG_UNLOCK_HPA	= (1 << 18), /* unlock HPA */
 	ATA_DFLAG_INIT_MASK	= (1 << 24) - 1,
 	ATA_DFLAG_DETACH	= (1 << 24),
 	ATA_DFLAG_DETACHED	= (1 << 25),
 	ATA_DEV_UNKNOWN		= 0,	/* unknown device */
 	ATA_DEV_ATA		= 1,	/* ATA device */
 	ATA_DEV_ATA_UNSUP	= 2,	/* ATA device (unsupported) */
 	ATA_DEV_ATAPI		= 3,	/* ATAPI device */
 	ATA_DEV_ATAPI_UNSUP	= 4,	/* ATAPI device (unsupported) */
 	ATA_DEV_PMP		= 5,	/* SATA port multiplier */
 	ATA_DEV_PMP_UNSUP	= 6,	/* SATA port multiplier (unsupported) */
 	ATA_DEV_SEMB		= 7,	/* SEMB */
 	ATA_DEV_SEMB_UNSUP	= 8,	/* SEMB (unsupported) */
 	ATA_DEV_NONE		= 9,	/* no device */
 	/* struct ata_link flags */
 	ATA_LFLAG_NO_HRST	= (1 << 1), /* avoid hardreset */
 	ATA_LFLAG_NO_SRST	= (1 << 2), /* avoid softreset */
 	ATA_LFLAG_ASSUME_ATA	= (1 << 3), /* assume ATA class */
 	ATA_LFLAG_ASSUME_SEMB	= (1 << 4), /* assume SEMB class */
 	ATA_LFLAG_ASSUME_CLASS	= ATA_LFLAG_ASSUME_ATA | ATA_LFLAG_ASSUME_SEMB,
 	ATA_LFLAG_NO_RETRY	= (1 << 5), /* don't retry this link */
 	ATA_LFLAG_DISABLED	= (1 << 6), /* link is disabled */
 	ATA_LFLAG_SW_ACTIVITY	= (1 << 7), /* keep activity stats */
 	/* struct ata_port flags */
 	ATA_FLAG_SLAVE_POSS	= (1 << 0), /* host supports slave dev */
 					    /* (doesn't imply presence) */
 	ATA_FLAG_SATA		= (1 << 1),
 	ATA_FLAG_NO_LEGACY	= (1 << 2), /* no legacy mode check */
 	ATA_FLAG_MMIO		= (1 << 3), /* use MMIO, not PIO */
 	ATA_FLAG_SRST		= (1 << 4), /* (obsolete) use ATA SRST, not E.D.D. */
 	ATA_FLAG_SATA_RESET	= (1 << 5), /* (obsolete) use COMRESET */
 	ATA_FLAG_NO_ATAPI	= (1 << 6), /* No ATAPI support */
 	ATA_FLAG_PIO_DMA	= (1 << 7), /* PIO cmds via DMA */
 	ATA_FLAG_PIO_LBA48	= (1 << 8), /* Host DMA engine is LBA28 only */
 	ATA_FLAG_PIO_POLLING	= (1 << 9), /* use polling PIO if LLD
 					     * doesn't handle PIO interrupts */
 	ATA_FLAG_NCQ		= (1 << 10), /* host supports NCQ */
 	ATA_FLAG_NO_POWEROFF_SPINDOWN = (1 << 11), /* don't spindown before poweroff */
 	ATA_FLAG_NO_HIBERNATE_SPINDOWN = (1 << 12), /* don't spindown before hibernation */
 	ATA_FLAG_DEBUGMSG	= (1 << 13),
 	ATA_FLAG_FPDMA_AA		= (1 << 14), /* driver supports Auto-Activate */
 	ATA_FLAG_IGN_SIMPLEX	= (1 << 15), /* ignore SIMPLEX */
 	ATA_FLAG_NO_IORDY	= (1 << 16), /* controller lacks iordy */
 	ATA_FLAG_ACPI_SATA	= (1 << 17), /* need native SATA ACPI layout */
 	ATA_FLAG_AN		= (1 << 18), /* controller supports AN */
 	ATA_FLAG_PMP		= (1 << 19), /* controller supports PMP */
 	ATA_FLAG_IPM		= (1 << 20), /* driver can handle IPM */
 	ATA_FLAG_EM		= (1 << 21), /* driver supports enclosure
 					      * management */
 	ATA_FLAG_SW_ACTIVITY	= (1 << 22), /* driver supports sw activity
 					      * led */
 	/* bits 24:31 of ap->flags are reserved for LLD specific flags */
 	/* struct ata_port pflags */
 	ATA_PFLAG_EH_PENDING	= (1 << 0), /* EH pending */
 	ATA_PFLAG_EH_IN_PROGRESS = (1 << 1), /* EH in progress */
 	ATA_PFLAG_FROZEN	= (1 << 2), /* port is frozen */
 	ATA_PFLAG_RECOVERED	= (1 << 3), /* recovery action performed */
 	ATA_PFLAG_LOADING	= (1 << 4), /* boot/loading probe */
 	ATA_PFLAG_SCSI_HOTPLUG	= (1 << 6), /* SCSI hotplug scheduled */
 	ATA_PFLAG_INITIALIZING	= (1 << 7), /* being initialized, don't touch */
 	ATA_PFLAG_RESETTING	= (1 << 8), /* reset in progress */
 	ATA_PFLAG_UNLOADING	= (1 << 9), /* driver is being unloaded */
 	ATA_PFLAG_UNLOADED	= (1 << 10), /* driver is unloaded */
 	ATA_PFLAG_SUSPENDED	= (1 << 17), /* port is suspended (power) */
 	ATA_PFLAG_PM_PENDING	= (1 << 18), /* PM operation pending */
 	ATA_PFLAG_INIT_GTM_VALID = (1 << 19), /* initial gtm data valid */
 	ATA_PFLAG_PIO32		= (1 << 20),  /* 32bit PIO */
 	ATA_PFLAG_PIO32CHANGE	= (1 << 21),  /* 32bit PIO can be turned on/off */
 	/* struct ata_queued_cmd flags */
 	ATA_QCFLAG_ACTIVE	= (1 << 0), /* cmd not yet ack'd to scsi lyer */
 	ATA_QCFLAG_DMAMAP	= (1 << 1), /* SG table is DMA mapped */
 	ATA_QCFLAG_IO		= (1 << 3), /* standard IO command */
 	ATA_QCFLAG_RESULT_TF	= (1 << 4), /* result TF requested */
 	ATA_QCFLAG_CLEAR_EXCL	= (1 << 5), /* clear excl_link on completion */
 	ATA_QCFLAG_QUIET	= (1 << 6), /* don't report device error */
 	ATA_QCFLAG_RETRY	= (1 << 7), /* retry after failure */
 	ATA_QCFLAG_FAILED	= (1 << 16), /* cmd failed and is owned by EH */
 	ATA_QCFLAG_SENSE_VALID	= (1 << 17), /* sense data valid */
 	ATA_QCFLAG_EH_SCHEDULED = (1 << 18), /* EH scheduled (obsolete) */
 	/* host set flags */
 	ATA_HOST_SIMPLEX	= (1 << 0),	/* Host is simplex, one DMA channel per host only */
 	ATA_HOST_STARTED	= (1 << 1),	/* Host started */
 	ATA_HOST_PARALLEL_SCAN	= (1 << 2),	/* Ports on this host can be scanned in parallel */
 	/* bits 24:31 of host->flags are reserved for LLD specific flags */
 	/* various lengths of time */
 	ATA_TMOUT_BOOT		= 30000,	/* heuristic */
 	ATA_TMOUT_BOOT_QUICK	=  7000,	/* heuristic */
 	ATA_TMOUT_INTERNAL_QUICK = 5000,
 	ATA_TMOUT_MAX_PARK	= 30000,
 	/*
 	 * GoVault needs 2s and iVDR disk HHD424020F7SV00 800ms.  2s
 	 * is too much without parallel probing.  Use 2s if parallel
 	 * probing is available, 800ms otherwise.
 	 */
 	ATA_TMOUT_FF_WAIT_LONG	=  2000,
 	ATA_TMOUT_FF_WAIT	=   800,
 	/* Spec mandates to wait for ">= 2ms" before checking status
 	 * after reset.  We wait 150ms, because that was the magic
 	 * delay used for ATAPI devices in Hale Landis's ATADRVR, for
 	 * the period of time between when the ATA command register is
 	 * written, and then status is checked.  Because waiting for
 	 * "a while" before checking status is fine, post SRST, we
 	 * perform this magic delay here as well.
 	 *
 	 * Old drivers/ide uses the 2mS rule and then waits for ready.
 	 */
 	ATA_WAIT_AFTER_RESET	=  150,
 	/* If PMP is supported, we have to do follow-up SRST.  As some
 	 * PMPs don't send D2H Reg FIS after hardreset, LLDs are
 	 * advised to wait only for the following duration before
 	 * doing SRST.
 	 */
 	ATA_TMOUT_PMP_SRST_WAIT	= 5000,
 	/* ATA bus states */
 	BUS_UNKNOWN		= 0,
 	BUS_DMA			= 1,
 	BUS_IDLE		= 2,
 	BUS_NOINTR		= 3,
 	BUS_NODATA		= 4,
 	BUS_TIMER		= 5,
 	BUS_PIO			= 6,
 	BUS_EDD			= 7,
 	BUS_IDENTIFY		= 8,
 	BUS_PACKET		= 9,
 	/* SATA port states */
 	PORT_UNKNOWN		= 0,
 	PORT_ENABLED		= 1,
 	PORT_DISABLED		= 2,
 	/* encoding various smaller bitmaps into a single
 	 * unsigned long bitmap
 	 */
 	ATA_NR_PIO_MODES	= 7,
 	ATA_NR_MWDMA_MODES	= 5,
 	ATA_NR_UDMA_MODES	= 8,
 	ATA_SHIFT_PIO		= 0,
 	ATA_SHIFT_MWDMA		= ATA_SHIFT_PIO + ATA_NR_PIO_MODES,
 	ATA_SHIFT_UDMA		= ATA_SHIFT_MWDMA + ATA_NR_MWDMA_MODES,
 	/* size of buffer to pad xfers ending on unaligned boundaries */
 	ATA_DMA_PAD_SZ		= 4,
 	/* ering size */
 	ATA_ERING_SIZE		= 32,
 	/* return values for ->qc_defer */
 	ATA_DEFER_LINK		= 1,
 	ATA_DEFER_PORT		= 2,
 	/* desc_len for ata_eh_info and context */
 	ATA_EH_DESC_LEN		= 80,
 	/* reset / recovery action types */
 	ATA_EH_REVALIDATE	= (1 << 0),
 	ATA_EH_SOFTRESET	= (1 << 1), /* meaningful only in ->prereset */
 	ATA_EH_HARDRESET	= (1 << 2), /* meaningful only in ->prereset */
 	ATA_EH_RESET		= ATA_EH_SOFTRESET | ATA_EH_HARDRESET,
 	ATA_EH_ENABLE_LINK	= (1 << 3),
 	ATA_EH_LPM		= (1 << 4),  /* link power management action */
 	ATA_EH_PARK		= (1 << 5), /* unload heads and stop I/O */
 	ATA_EH_PERDEV_MASK	= ATA_EH_REVALIDATE | ATA_EH_PARK,
 	ATA_EH_ALL_ACTIONS	= ATA_EH_REVALIDATE | ATA_EH_RESET |
 				  ATA_EH_ENABLE_LINK | ATA_EH_LPM,
 	/* ata_eh_info->flags */
 	ATA_EHI_HOTPLUGGED	= (1 << 0),  /* could have been hotplugged */
 	ATA_EHI_NO_AUTOPSY	= (1 << 2),  /* no autopsy */
 	ATA_EHI_QUIET		= (1 << 3),  /* be quiet */
+	ATA_EHI_NO_RECOVERY	= (1 << 4),  /* no recovery */
 	ATA_EHI_DID_SOFTRESET	= (1 << 16), /* already soft-reset this port */
 	ATA_EHI_DID_HARDRESET	= (1 << 17), /* already soft-reset this port */
 	ATA_EHI_PRINTINFO	= (1 << 18), /* print configuration info */
 	ATA_EHI_SETMODE		= (1 << 19), /* configure transfer mode */
 	ATA_EHI_POST_SETMODE	= (1 << 20), /* revaildating after setmode */
 	ATA_EHI_DID_RESET	= ATA_EHI_DID_SOFTRESET | ATA_EHI_DID_HARDRESET,
 	/* mask of flags to transfer *to* the slave link */
 	ATA_EHI_TO_SLAVE_MASK	= ATA_EHI_NO_AUTOPSY | ATA_EHI_QUIET,
 	/* max tries if error condition is still set after ->error_handler */
 	ATA_EH_MAX_TRIES	= 5,
 	/* sometimes resuming a link requires several retries */
 	ATA_LINK_RESUME_TRIES	= 5,
 	/* how hard are we gonna try to probe/recover devices */
 	ATA_PROBE_MAX_TRIES	= 3,
 	ATA_EH_DEV_TRIES	= 3,
 	ATA_EH_PMP_TRIES	= 5,
 	ATA_EH_PMP_LINK_TRIES	= 3,
 	SATA_PMP_RW_TIMEOUT	= 3000,		/* PMP read/write timeout */
 	/* This should match the actual table size of
 	 * ata_eh_cmd_timeout_table in libata-eh.c.
 	 */
 	ATA_EH_CMD_TIMEOUT_TABLE_SIZE = 6,
 	/* Horkage types. May be set by libata or controller on drives
 	   (some horkage may be drive/controller pair dependant */
 	ATA_HORKAGE_DIAGNOSTIC	= (1 << 0),	/* Failed boot diag */
 	ATA_HORKAGE_NODMA	= (1 << 1),	/* DMA problems */
 	ATA_HORKAGE_NONCQ	= (1 << 2),	/* Don't use NCQ */
 	ATA_HORKAGE_MAX_SEC_128	= (1 << 3),	/* Limit max sects to 128 */
 	ATA_HORKAGE_BROKEN_HPA	= (1 << 4),	/* Broken HPA */
 	ATA_HORKAGE_DISABLE	= (1 << 5),	/* Disable it */
 	ATA_HORKAGE_HPA_SIZE	= (1 << 6),	/* native size off by one */
 	ATA_HORKAGE_IPM		= (1 << 7),	/* Link PM problems */
 	ATA_HORKAGE_IVB		= (1 << 8),	/* cbl det validity bit bugs */
 	ATA_HORKAGE_STUCK_ERR	= (1 << 9),	/* stuck ERR on next PACKET */
 	ATA_HORKAGE_BRIDGE_OK	= (1 << 10),	/* no bridge limits */
 	ATA_HORKAGE_ATAPI_MOD16_DMA = (1 << 11), /* use ATAPI DMA for commands
 						    not multiple of 16 bytes */
 	ATA_HORKAGE_FIRMWARE_WARN = (1 << 12),	/* firmware update warning */
 	ATA_HORKAGE_1_5_GBPS	= (1 << 13),	/* force 1.5 Gbps */
 	ATA_HORKAGE_NOSETXFER	= (1 << 14),	/* skip SETXFER, SATA only */
 	ATA_HORKAGE_BROKEN_FPDMA_AA	= (1 << 15),	/* skip AA */
 	ATA_HORKAGE_DUMP_ID	= (1 << 16),	/* dump IDENTIFY data */
 	 /* DMA mask for user DMA control: User visible values; DO NOT
 	    renumber */
 	ATA_DMA_MASK_ATA	= (1 << 0),	/* DMA on ATA Disk */
 	ATA_DMA_MASK_ATAPI	= (1 << 1),	/* DMA on ATAPI */
 	ATA_DMA_MASK_CFA	= (1 << 2),	/* DMA on CF Card */
 	/* ATAPI command types */
 	ATAPI_READ		= 0,		/* READs */
 	ATAPI_WRITE		= 1,		/* WRITEs */
 	ATAPI_READ_CD		= 2,		/* READ CD [MSF] */
 	ATAPI_PASS_THRU		= 3,		/* SAT pass-thru */
 	ATAPI_MISC		= 4,		/* the rest */
 	/* Timing constants */
 	ATA_TIMING_SETUP	= (1 << 0),
 	ATA_TIMING_ACT8B	= (1 << 1),
 	ATA_TIMING_REC8B	= (1 << 2),
 	ATA_TIMING_CYC8B	= (1 << 3),
 	ATA_TIMING_8BIT		= ATA_TIMING_ACT8B | ATA_TIMING_REC8B |
 				  ATA_TIMING_CYC8B,
 	ATA_TIMING_ACTIVE	= (1 << 4),
 	ATA_TIMING_RECOVER	= (1 << 5),
 	ATA_TIMING_DMACK_HOLD	= (1 << 6),
 	ATA_TIMING_CYCLE	= (1 << 7),
 	ATA_TIMING_UDMA		= (1 << 8),
 	ATA_TIMING_ALL		= ATA_TIMING_SETUP | ATA_TIMING_ACT8B |
 				  ATA_TIMING_REC8B | ATA_TIMING_CYC8B |
 				  ATA_TIMING_ACTIVE | ATA_TIMING_RECOVER |
 				  ATA_TIMING_DMACK_HOLD | ATA_TIMING_CYCLE |
 				  ATA_TIMING_UDMA,
 	/* ACPI constants */
 	ATA_ACPI_FILTER_SETXFER	= 1 << 0,
 	ATA_ACPI_FILTER_LOCK	= 1 << 1,
 	ATA_ACPI_FILTER_DIPM	= 1 << 2,
 	ATA_ACPI_FILTER_FPDMA_OFFSET = 1 << 3,	/* FPDMA non-zero offset */
 	ATA_ACPI_FILTER_FPDMA_AA = 1 << 4,	/* FPDMA auto activate */
 	ATA_ACPI_FILTER_DEFAULT	= ATA_ACPI_FILTER_SETXFER |
 				  ATA_ACPI_FILTER_LOCK |
 				  ATA_ACPI_FILTER_DIPM,
 };
 enum ata_xfer_mask {
 	ATA_MASK_PIO		= ((1LU << ATA_NR_PIO_MODES) - 1)
 					<< ATA_SHIFT_PIO,
 	ATA_MASK_MWDMA		= ((1LU << ATA_NR_MWDMA_MODES) - 1)
 					<< ATA_SHIFT_MWDMA,
 	ATA_MASK_UDMA		= ((1LU << ATA_NR_UDMA_MODES) - 1)
 					<< ATA_SHIFT_UDMA,
 };
 enum hsm_task_states {
 	HSM_ST_IDLE,		/* no command on going */
 	HSM_ST_FIRST,		/* (waiting the device to)
 				   write CDB or first data block */
 	HSM_ST,			/* (waiting the device to) transfer data */
 	HSM_ST_LAST,		/* (waiting the device to) complete command */
 	HSM_ST_ERR,		/* error */
 };
 enum ata_completion_errors {
 	AC_ERR_DEV		= (1 << 0), /* device reported error */
 	AC_ERR_HSM		= (1 << 1), /* host state machine violation */
 	AC_ERR_TIMEOUT		= (1 << 2), /* timeout */
 	AC_ERR_MEDIA		= (1 << 3), /* media error */
 	AC_ERR_ATA_BUS		= (1 << 4), /* ATA bus error */
 	AC_ERR_HOST_BUS		= (1 << 5), /* host bus error */
 	AC_ERR_SYSTEM		= (1 << 6), /* system error */
 	AC_ERR_INVALID		= (1 << 7), /* invalid argument */
 	AC_ERR_OTHER		= (1 << 8), /* unknown */
 	AC_ERR_NODEV_HINT	= (1 << 9), /* polling device detection hint */
 	AC_ERR_NCQ		= (1 << 10), /* marker for offending NCQ qc */
 };
 /* forward declarations */
 struct scsi_device;
 struct ata_port_operations;
 struct ata_port;
 struct ata_link;
 struct ata_queued_cmd;
 /* typedefs */
 typedef void (*ata_qc_cb_t) (struct ata_queued_cmd *qc);
 typedef int (*ata_prereset_fn_t)(struct ata_link *link, unsigned long deadline);
 typedef int (*ata_reset_fn_t)(struct ata_link *link, unsigned int *classes,
 			      unsigned long deadline);
 typedef void (*ata_postreset_fn_t)(struct ata_link *link, unsigned int *classes);
 /*
  * host pm policy: If you alter this, you also need to alter libata-scsi.c
  * (for the ascii descriptions)
  */
 enum link_pm {
 	NOT_AVAILABLE,
 	MIN_POWER,
 	MAX_PERFORMANCE,
 	MEDIUM_POWER,
 };
 extern struct device_attribute dev_attr_link_power_management_policy;
 extern struct device_attribute dev_attr_unload_heads;
 extern struct device_attribute dev_attr_em_message_type;
 extern struct device_attribute dev_attr_em_message;
 extern struct device_attribute dev_attr_sw_activity;
 enum sw_activity {
 	OFF,
 	BLINK_ON,
 	BLINK_OFF,
 };
 #ifdef CONFIG_ATA_SFF
 struct ata_ioports {
 	void __iomem		*cmd_addr;
 	void __iomem		*data_addr;
 	void __iomem		*error_addr;
 	void __iomem		*feature_addr;
 	void __iomem		*nsect_addr;
 	void __iomem		*lbal_addr;
 	void __iomem		*lbam_addr;
 	void __iomem		*lbah_addr;
 	void __iomem		*device_addr;
 	void __iomem		*status_addr;
 	void __iomem		*command_addr;
 	void __iomem		*altstatus_addr;
 	void __iomem		*ctl_addr;
 #ifdef CONFIG_ATA_BMDMA
 	void __iomem		*bmdma_addr;
 #endif /* CONFIG_ATA_BMDMA */
 	void __iomem		*scr_addr;
 };
 #endif /* CONFIG_ATA_SFF */
 struct ata_host {
 	spinlock_t		lock;
 	struct device 		*dev;
 	void __iomem * const	*iomap;
 	unsigned int		n_ports;
 	void			*private_data;
 	struct ata_port_operations *ops;
 	unsigned long		flags;
 #ifdef CONFIG_ATA_ACPI
 	acpi_handle		acpi_handle;
 #endif
 	struct ata_port		*simplex_claimed;	/* channel owning the DMA */
 	struct ata_port		*ports[0];
 };
 struct ata_queued_cmd {
 	struct ata_port		*ap;
 	struct ata_device	*dev;
 	struct scsi_cmnd	*scsicmd;
 	void			(*scsidone)(struct scsi_cmnd *);
 	struct ata_taskfile	tf;
 	u8			cdb[ATAPI_CDB_LEN];
 	unsigned long		flags;		/* ATA_QCFLAG_xxx */
 	unsigned int		tag;
 	unsigned int		n_elem;
 	unsigned int		orig_n_elem;
 	int			dma_dir;
 	unsigned int		sect_size;
 	unsigned int		nbytes;
 	unsigned int		extrabytes;
 	unsigned int		curbytes;
 	struct scatterlist	*cursg;
 	unsigned int		cursg_ofs;
 	struct scatterlist	sgent;
 	struct scatterlist	*sg;
 	unsigned int		err_mask;
 	struct ata_taskfile	result_tf;
 	ata_qc_cb_t		complete_fn;
 	void			*private_data;
 	void			*lldd_task;
 };
 struct ata_port_stats {
 	unsigned long		unhandled_irq;
 	unsigned long		idle_irq;
 	unsigned long		rw_reqbuf;
 };
 struct ata_ering_entry {
 	unsigned int		eflags;
 	unsigned int		err_mask;
 	u64			timestamp;
 };
 struct ata_ering {
 	int			cursor;
 	struct ata_ering_entry	ring[ATA_ERING_SIZE];
 };
 struct ata_device {
 	struct ata_link		*link;
 	unsigned int		devno;		/* 0 or 1 */
 	unsigned int		horkage;	/* List of broken features */
 	unsigned long		flags;		/* ATA_DFLAG_xxx */
 	struct scsi_device	*sdev;		/* attached SCSI device */
 	void			*private_data;
 #ifdef CONFIG_ATA_ACPI
 	acpi_handle		acpi_handle;
 	union acpi_object	*gtf_cache;
 	unsigned int		gtf_filter;
 #endif
 	/* n_sector is CLEAR_BEGIN, read comment above CLEAR_BEGIN */
 	u64			n_sectors;	/* size of device, if ATA */
 	u64			n_native_sectors; /* native size, if ATA */
 	unsigned int		class;		/* ATA_DEV_xxx */
 	unsigned long		unpark_deadline;
 	u8			pio_mode;
 	u8			dma_mode;
 	u8			xfer_mode;
 	unsigned int		xfer_shift;	/* ATA_SHIFT_xxx */
 	unsigned int		multi_count;	/* sectors count for
 						   READ/WRITE MULTIPLE */
 	unsigned int		max_sectors;	/* per-device max sectors */
 	unsigned int		cdb_len;
 	/* per-dev xfer mask */
 	unsigned long		pio_mask;
 	unsigned long		mwdma_mask;
 	unsigned long		udma_mask;
 	/* for CHS addressing */
 	u16			cylinders;	/* Number of cylinders */
 	u16			heads;		/* Number of heads */
 	u16			sectors;	/* Number of sectors per track */
 	union {
 		u16		id[ATA_ID_WORDS]; /* IDENTIFY xxx DEVICE data */
 		u32		gscr[SATA_PMP_GSCR_DWORDS]; /* PMP GSCR block */
 	};
 	/* error history */
 	int			spdn_cnt;
 	/* ering is CLEAR_END, read comment above CLEAR_END */
 	struct ata_ering	ering;
 };
 /* Fields between ATA_DEVICE_CLEAR_BEGIN and ATA_DEVICE_CLEAR_END are
  * cleared to zero on ata_dev_init().
  */
 #define ATA_DEVICE_CLEAR_BEGIN		offsetof(struct ata_device, n_sectors)
 #define ATA_DEVICE_CLEAR_END		offsetof(struct ata_device, ering)
 struct ata_eh_info {
 	struct ata_device	*dev;		/* offending device */
 	u32			serror;		/* SError from LLDD */
 	unsigned int		err_mask;	/* port-wide err_mask */
 	unsigned int		action;		/* ATA_EH_* action mask */
 	unsigned int		dev_action[ATA_MAX_DEVICES]; /* dev EH action */
 	unsigned int		flags;		/* ATA_EHI_* flags */
 	unsigned int		probe_mask;
 	char			desc[ATA_EH_DESC_LEN];
 	int			desc_len;
 };
 struct ata_eh_context {
 	struct ata_eh_info	i;
 	int			tries[ATA_MAX_DEVICES];
 	int			cmd_timeout_idx[ATA_MAX_DEVICES]
 					       [ATA_EH_CMD_TIMEOUT_TABLE_SIZE];
 	unsigned int		classes[ATA_MAX_DEVICES];
 	unsigned int		did_probe_mask;
 	unsigned int		unloaded_mask;
 	unsigned int		saved_ncq_enabled;
 	u8			saved_xfer_mode[ATA_MAX_DEVICES];
 	/* timestamp for the last reset attempt or success */
 	unsigned long		last_reset;
 };
 struct ata_acpi_drive
 {
 	u32 pio;
 	u32 dma;
 } __packed;
 struct ata_acpi_gtm {
 	struct ata_acpi_drive drive[2];
 	u32 flags;
 } __packed;
 struct ata_link {
 	struct ata_port		*ap;
 	int			pmp;		/* port multiplier port # */
 	unsigned int		active_tag;	/* active tag on this link */
 	u32			sactive;	/* active NCQ commands */
 	unsigned int		flags;		/* ATA_LFLAG_xxx */
 	u32			saved_scontrol;	/* SControl on probe */
 	unsigned int		hw_sata_spd_limit;
 	unsigned int		sata_spd_limit;
 	unsigned int		sata_spd;	/* current SATA PHY speed */
 	/* record runtime error info, protected by host_set lock */
 	struct ata_eh_info	eh_info;
 	/* EH context */
 	struct ata_eh_context	eh_context;
 	struct ata_device	device[ATA_MAX_DEVICES];
 };
 struct ata_port {
 	struct Scsi_Host	*scsi_host; /* our co-allocated scsi host */
 	struct ata_port_operations *ops;
 	spinlock_t		*lock;
 	/* Flags owned by the EH context. Only EH should touch these once the
 	   port is active */
 	unsigned long		flags;	/* ATA_FLAG_xxx */
 	/* Flags that change dynamically, protected by ap->lock */
 	unsigned int		pflags; /* ATA_PFLAG_xxx */
 	unsigned int		print_id; /* user visible unique port ID */
 	unsigned int		port_no; /* 0 based port no. inside the host */
 #ifdef CONFIG_ATA_SFF
 	struct ata_ioports	ioaddr;	/* ATA cmd/ctl/dma register blocks */
 	u8			ctl;	/* cache of ATA control register */
 	u8			last_ctl;	/* Cache last written value */
+	struct ata_link*	sff_pio_task_link; /* link currently used */
 	struct delayed_work	sff_pio_task;
 #ifdef CONFIG_ATA_BMDMA
 	struct ata_bmdma_prd	*bmdma_prd;	/* BMDMA SG list */
 	dma_addr_t		bmdma_prd_dma;	/* and its DMA mapping */
 #endif /* CONFIG_ATA_BMDMA */
 #endif /* CONFIG_ATA_SFF */
 	unsigned int		pio_mask;
 	unsigned int		mwdma_mask;
 	unsigned int		udma_mask;
 	unsigned int		cbl;	/* cable type; ATA_CBL_xxx */
 	struct ata_queued_cmd	qcmd[ATA_MAX_QUEUE];
 	unsigned long		qc_allocated;
 	unsigned int		qc_active;
 	int			nr_active_links; /* #links with active qcs */
 	struct ata_link		link;		/* host default link */
 	struct ata_link		*slave_link;	/* see ata_slave_link_init() */
 	int			nr_pmp_links;	/* nr of available PMP links */
 	struct ata_link		*pmp_link;	/* array of PMP links */
 	struct ata_link		*excl_link;	/* for PMP qc exclusion */
 	struct ata_port_stats	stats;
 	struct ata_host		*host;
 	struct device 		*dev;
 	struct mutex		scsi_scan_mutex;
 	struct delayed_work	hotplug_task;
 	struct work_struct	scsi_rescan_task;
 	unsigned int		hsm_task_state;
 	u32			msg_enable;
 	struct list_head	eh_done_q;
 	wait_queue_head_t	eh_wait_q;
 	int			eh_tries;
 	struct completion	park_req_pending;
 	pm_message_t		pm_mesg;
 	int			*pm_result;
 	enum link_pm		pm_policy;
 	struct timer_list	fastdrain_timer;
 	unsigned long		fastdrain_cnt;
 	int			em_message_type;
 	void			*private_data;
 #ifdef CONFIG_ATA_ACPI
 	acpi_handle		acpi_handle;
 	struct ata_acpi_gtm	__acpi_init_gtm; /* use ata_acpi_init_gtm() */
 #endif
 	/* owned by EH */
 	u8			sector_buf[ATA_SECT_SIZE] ____cacheline_aligned;
 };
 /* The following initializer overrides a method to NULL whether one of
  * its parent has the method defined or not.  This is equivalent to
  * ERR_PTR(-ENOENT).  Unfortunately, ERR_PTR doesn't render a constant
  * expression and thus can't be used as an initializer.
  */
 #define ATA_OP_NULL		(void *)(unsigned long)(-ENOENT)
 struct ata_port_operations {
 	/*
 	 * Command execution
 	 */
 	int  (*qc_defer)(struct ata_queued_cmd *qc);
 	int  (*check_atapi_dma)(struct ata_queued_cmd *qc);
 	void (*qc_prep)(struct ata_queued_cmd *qc);
 	unsigned int (*qc_issue)(struct ata_queued_cmd *qc);
 	bool (*qc_fill_rtf)(struct ata_queued_cmd *qc);
 	/*
 	 * Configuration and exception handling
 	 */
 	int  (*cable_detect)(struct ata_port *ap);
 	unsigned long (*mode_filter)(struct ata_device *dev, unsigned long xfer_mask);
 	void (*set_piomode)(struct ata_port *ap, struct ata_device *dev);
 	void (*set_dmamode)(struct ata_port *ap, struct ata_device *dev);
 	int  (*set_mode)(struct ata_link *link, struct ata_device **r_failed_dev);
 	unsigned int (*read_id)(struct ata_device *dev, struct ata_taskfile *tf, u16 *id);
 	void (*dev_config)(struct ata_device *dev);
 	void (*freeze)(struct ata_port *ap);
 	void (*thaw)(struct ata_port *ap);
 	ata_prereset_fn_t	prereset;
 	ata_reset_fn_t		softreset;
 	ata_reset_fn_t		hardreset;
 	ata_postreset_fn_t	postreset;
 	ata_prereset_fn_t	pmp_prereset;
 	ata_reset_fn_t		pmp_softreset;
 	ata_reset_fn_t		pmp_hardreset;
 	ata_postreset_fn_t	pmp_postreset;
 	void (*error_handler)(struct ata_port *ap);
 	void (*lost_interrupt)(struct ata_port *ap);
 	void (*post_internal_cmd)(struct ata_queued_cmd *qc);
 	/*
 	 * Optional features
 	 */
 	int  (*scr_read)(struct ata_link *link, unsigned int sc_reg, u32 *val);
 	int  (*scr_write)(struct ata_link *link, unsigned int sc_reg, u32 val);
 	void (*pmp_attach)(struct ata_port *ap);
 	void (*pmp_detach)(struct ata_port *ap);
 	int  (*enable_pm)(struct ata_port *ap, enum link_pm policy);
 	void (*disable_pm)(struct ata_port *ap);
 	/*
 	 * Start, stop, suspend and resume
 	 */
 	int  (*port_suspend)(struct ata_port *ap, pm_message_t mesg);
 	int  (*port_resume)(struct ata_port *ap);
 	int  (*port_start)(struct ata_port *ap);
 	void (*port_stop)(struct ata_port *ap);
 	void (*host_stop)(struct ata_host *host);
 #ifdef CONFIG_ATA_SFF
 	/*
 	 * SFF / taskfile oriented ops
 	 */
 	void (*sff_dev_select)(struct ata_port *ap, unsigned int device);
 	void (*sff_set_devctl)(struct ata_port *ap, u8 ctl);
 	u8   (*sff_check_status)(struct ata_port *ap);
 	u8   (*sff_check_altstatus)(struct ata_port *ap);
 	void (*sff_tf_load)(struct ata_port *ap, const struct ata_taskfile *tf);
 	void (*sff_tf_read)(struct ata_port *ap, struct ata_taskfile *tf);
 	void (*sff_exec_command)(struct ata_port *ap,
 				 const struct ata_taskfile *tf);
 	unsigned int (*sff_data_xfer)(struct ata_device *dev,
 			unsigned char *buf, unsigned int buflen, int rw);
 	void (*sff_irq_on)(struct ata_port *);
 	bool (*sff_irq_check)(struct ata_port *);
 	void (*sff_irq_clear)(struct ata_port *);
 	void (*sff_drain_fifo)(struct ata_queued_cmd *qc);
 #ifdef CONFIG_ATA_BMDMA
 	void (*bmdma_setup)(struct ata_queued_cmd *qc);
 	void (*bmdma_start)(struct ata_queued_cmd *qc);
 	void (*bmdma_stop)(struct ata_queued_cmd *qc);
 	u8   (*bmdma_status)(struct ata_port *ap);
 #endif /* CONFIG_ATA_BMDMA */
 #endif /* CONFIG_ATA_SFF */
 	ssize_t (*em_show)(struct ata_port *ap, char *buf);
 	ssize_t (*em_store)(struct ata_port *ap, const char *message,
 			    size_t size);
 	ssize_t (*sw_activity_show)(struct ata_device *dev, char *buf);
 	ssize_t (*sw_activity_store)(struct ata_device *dev,
 				     enum sw_activity val);
 	/*
 	 * Obsolete
 	 */
 	void (*phy_reset)(struct ata_port *ap);
 	void (*eng_timeout)(struct ata_port *ap);
 	/*
 	 * ->inherits must be the last field and all the preceding
 	 * fields must be pointers.
 	 */
 	const struct ata_port_operations	*inherits;
 };
 struct ata_port_info {
 	unsigned long		flags;
 	unsigned long		link_flags;
 	unsigned long		pio_mask;
 	unsigned long		mwdma_mask;
 	unsigned long		udma_mask;
 	struct ata_port_operations *port_ops;
 	void 			*private_data;
 };
 struct ata_timing {
 	unsigned short mode;		/* ATA mode */
 	unsigned short setup;		/* t1 */
 	unsigned short act8b;		/* t2 for 8-bit I/O */
 	unsigned short rec8b;		/* t2i for 8-bit I/O */
 	unsigned short cyc8b;		/* t0 for 8-bit I/O */
 	unsigned short active;		/* t2 or tD */
 	unsigned short recover;		/* t2i or tK */
 	unsigned short dmack_hold;	/* tj */
 	unsigned short cycle;		/* t0 */
 	unsigned short udma;		/* t2CYCTYP/2 */
 };
 /*
  * Core layer - drivers/ata/libata-core.c
  */
 extern const unsigned long sata_deb_timing_normal[];
 extern const unsigned long sata_deb_timing_hotplug[];
 extern const unsigned long sata_deb_timing_long[];
 extern struct ata_port_operations ata_dummy_port_ops;
 extern const struct ata_port_info ata_dummy_port_info;
 static inline const unsigned long *
 sata_ehc_deb_timing(struct ata_eh_context *ehc)
 {
 	if (ehc->i.flags & ATA_EHI_HOTPLUGGED)
 		return sata_deb_timing_hotplug;
 	else
 		return sata_deb_timing_normal;
 }
 static inline int ata_port_is_dummy(struct ata_port *ap)
 {
 	return ap->ops == &ata_dummy_port_ops;
 }
 extern int sata_set_spd(struct ata_link *link);
 extern int ata_std_prereset(struct ata_link *link, unsigned long deadline);
 extern int ata_wait_after_reset(struct ata_link *link, unsigned long deadline,
 				int (*check_ready)(struct ata_link *link));
 extern int sata_link_debounce(struct ata_link *link,
 			const unsigned long *params, unsigned long deadline);
 extern int sata_link_resume(struct ata_link *link, const unsigned long *params,
 			    unsigned long deadline);
 extern int sata_link_hardreset(struct ata_link *link,
 			const unsigned long *timing, unsigned long deadline,
 			bool *online, int (*check_ready)(struct ata_link *));
 extern int sata_std_hardreset(struct ata_link *link, unsigned int *class,
 			      unsigned long deadline);
 extern void ata_std_postreset(struct ata_link *link, unsigned int *classes);
 extern struct ata_host *ata_host_alloc(struct device *dev, int max_ports);
 extern struct ata_host *ata_host_alloc_pinfo(struct device *dev,
 			const struct ata_port_info * const * ppi, int n_ports);
 extern int ata_slave_link_init(struct ata_port *ap);
 extern int ata_host_start(struct ata_host *host);
 extern int ata_host_register(struct ata_host *host,
 			     struct scsi_host_template *sht);
 extern int ata_host_activate(struct ata_host *host, int irq,
 			     irq_handler_t irq_handler, unsigned long irq_flags,
 			     struct scsi_host_template *sht);
 extern void ata_host_detach(struct ata_host *host);
 extern void ata_host_init(struct ata_host *, struct device *,
 			  unsigned long, struct ata_port_operations *);
 extern int ata_scsi_detect(struct scsi_host_template *sht);
 extern int ata_scsi_ioctl(struct scsi_device *dev, int cmd, void __user *arg);
 extern int ata_scsi_queuecmd(struct scsi_cmnd *cmd, void (*done)(struct scsi_cmnd *));
 extern int ata_sas_scsi_ioctl(struct ata_port *ap, struct scsi_device *dev,
 			    int cmd, void __user *arg);
 extern void ata_sas_port_destroy(struct ata_port *);
 extern struct ata_port *ata_sas_port_alloc(struct ata_host *,
 					   struct ata_port_info *, struct Scsi_Host *);
 extern int ata_sas_port_init(struct ata_port *);
 extern int ata_sas_port_start(struct ata_port *ap);
 extern void ata_sas_port_stop(struct ata_port *ap);
 extern int ata_sas_slave_configure(struct scsi_device *, struct ata_port *);
 extern int ata_sas_queuecmd(struct scsi_cmnd *cmd, void (*done)(struct scsi_cmnd *),
 			    struct ata_port *ap);
 extern int sata_scr_valid(struct ata_link *link);
 extern int sata_scr_read(struct ata_link *link, int reg, u32 *val);
 extern int sata_scr_write(struct ata_link *link, int reg, u32 val);
 extern int sata_scr_write_flush(struct ata_link *link, int reg, u32 val);
 extern bool ata_link_online(struct ata_link *link);
 extern bool ata_link_offline(struct ata_link *link);
 #ifdef CONFIG_PM
 extern int ata_host_suspend(struct ata_host *host, pm_message_t mesg);
 extern void ata_host_resume(struct ata_host *host);
 #endif
 extern int ata_ratelimit(void);
 extern u32 ata_wait_register(void __iomem *reg, u32 mask, u32 val,
 			     unsigned long interval, unsigned long timeout);
 extern int atapi_cmd_type(u8 opcode);
 extern void ata_tf_to_fis(const struct ata_taskfile *tf,
 			  u8 pmp, int is_cmd, u8 *fis);
 extern void ata_tf_from_fis(const u8 *fis, struct ata_taskfile *tf);
 extern unsigned long ata_pack_xfermask(unsigned long pio_mask,
 			unsigned long mwdma_mask, unsigned long udma_mask);
 extern void ata_unpack_xfermask(unsigned long xfer_mask,
 			unsigned long *pio_mask, unsigned long *mwdma_mask,
 			unsigned long *udma_mask);
 extern u8 ata_xfer_mask2mode(unsigned long xfer_mask);
 extern unsigned long ata_xfer_mode2mask(u8 xfer_mode);
 extern int ata_xfer_mode2shift(unsigned long xfer_mode);
 extern const char *ata_mode_string(unsigned long xfer_mask);
 extern unsigned long ata_id_xfermask(const u16 *id);
 extern int ata_std_qc_defer(struct ata_queued_cmd *qc);
 extern void ata_noop_qc_prep(struct ata_queued_cmd *qc);
 extern void ata_sg_init(struct ata_queued_cmd *qc, struct scatterlist *sg,
 		 unsigned int n_elem);
 extern unsigned int ata_dev_classify(const struct ata_taskfile *tf);
 extern void ata_dev_disable(struct ata_device *adev);
 extern void ata_id_string(const u16 *id, unsigned char *s,
 			  unsigned int ofs, unsigned int len);
 extern void ata_id_c_string(const u16 *id, unsigned char *s,
 			    unsigned int ofs, unsigned int len);
 extern unsigned int ata_do_dev_read_id(struct ata_device *dev,
 					struct ata_taskfile *tf, u16 *id);
 extern void ata_qc_complete(struct ata_queued_cmd *qc);
 extern int ata_qc_complete_multiple(struct ata_port *ap, u32 qc_active);
 extern void ata_scsi_simulate(struct ata_device *dev, struct scsi_cmnd *cmd,
 			      void (*done)(struct scsi_cmnd *));
 extern int ata_std_bios_param(struct scsi_device *sdev,
 			      struct block_device *bdev,
 			      sector_t capacity, int geom[]);
 extern void ata_scsi_unlock_native_capacity(struct scsi_device *sdev);
 extern int ata_scsi_slave_config(struct scsi_device *sdev);
 extern void ata_scsi_slave_destroy(struct scsi_device *sdev);
 extern int ata_scsi_change_queue_depth(struct scsi_device *sdev,
 				       int queue_depth, int reason);
 extern struct ata_device *ata_dev_pair(struct ata_device *adev);
 extern int ata_do_set_mode(struct ata_link *link, struct ata_device **r_failed_dev);
 extern int ata_cable_40wire(struct ata_port *ap);
 extern int ata_cable_80wire(struct ata_port *ap);
 extern int ata_cable_sata(struct ata_port *ap);
 extern int ata_cable_ignore(struct ata_port *ap);
 extern int ata_cable_unknown(struct ata_port *ap);
 /* Timing helpers */
 extern unsigned int ata_pio_need_iordy(const struct ata_device *);
 extern const struct ata_timing *ata_timing_find_mode(u8 xfer_mode);
 extern int ata_timing_compute(struct ata_device *, unsigned short,
 			      struct ata_timing *, int, int);
 extern void ata_timing_merge(const struct ata_timing *,
 			     const struct ata_timing *, struct ata_timing *,
 			     unsigned int);
 extern u8 ata_timing_cycle2mode(unsigned int xfer_shift, int cycle);
 /* PCI */
 #ifdef CONFIG_PCI
 struct pci_dev;
 struct pci_bits {
 	unsigned int		reg;	/* PCI config register to read */
 	unsigned int		width;	/* 1 (8 bit), 2 (16 bit), 4 (32 bit) */
 	unsigned long		mask;
 	unsigned long		val;
 };
 extern int pci_test_config_bits(struct pci_dev *pdev, const struct pci_bits *bits);
 extern void ata_pci_remove_one(struct pci_dev *pdev);
 #ifdef CONFIG_PM
 extern void ata_pci_device_do_suspend(struct pci_dev *pdev, pm_message_t mesg);
 extern int __must_check ata_pci_device_do_resume(struct pci_dev *pdev);
 extern int ata_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
 extern int ata_pci_device_resume(struct pci_dev *pdev);
 #endif /* CONFIG_PM */
 #endif /* CONFIG_PCI */
 /*
  * ACPI - drivers/ata/libata-acpi.c
  */
 #ifdef CONFIG_ATA_ACPI
 static inline const struct ata_acpi_gtm *ata_acpi_init_gtm(struct ata_port *ap)
 {
 	if (ap->pflags & ATA_PFLAG_INIT_GTM_VALID)
 		return &ap->__acpi_init_gtm;
 	return NULL;
 }
 int ata_acpi_stm(struct ata_port *ap, const struct ata_acpi_gtm *stm);
 int ata_acpi_gtm(struct ata_port *ap, struct ata_acpi_gtm *stm);
 unsigned long ata_acpi_gtm_xfermask(struct ata_device *dev,
 				    const struct ata_acpi_gtm *gtm);
 int ata_acpi_cbl_80wire(struct ata_port *ap, const struct ata_acpi_gtm *gtm);
 #else
 static inline const struct ata_acpi_gtm *ata_acpi_init_gtm(struct ata_port *ap)
 {
 	return NULL;
 }
 static inline int ata_acpi_stm(const struct ata_port *ap,
 			       struct ata_acpi_gtm *stm)
 {
 	return -ENOSYS;
 }
 static inline int ata_acpi_gtm(const struct ata_port *ap,
 			       struct ata_acpi_gtm *stm)
 {
 	return -ENOSYS;
 }
 static inline unsigned int ata_acpi_gtm_xfermask(struct ata_device *dev,
 					const struct ata_acpi_gtm *gtm)
 {
 	return 0;
 }
 static inline int ata_acpi_cbl_80wire(struct ata_port *ap,
 				      const struct ata_acpi_gtm *gtm)
 {
 	return 0;
 }
 #endif
 /*
  * EH - drivers/ata/libata-eh.c
  */
 extern void ata_port_schedule_eh(struct ata_port *ap);
 extern int ata_link_abort(struct ata_link *link);
 extern int ata_port_abort(struct ata_port *ap);
 extern int ata_port_freeze(struct ata_port *ap);
 extern int sata_async_notification(struct ata_port *ap);
 extern void ata_eh_freeze_port(struct ata_port *ap);
 extern void ata_eh_thaw_port(struct ata_port *ap);
 extern void ata_eh_qc_complete(struct ata_queued_cmd *qc);
 extern void ata_eh_qc_retry(struct ata_queued_cmd *qc);
 extern void ata_eh_analyze_ncq_error(struct ata_link *link);
 extern void ata_do_eh(struct ata_port *ap, ata_prereset_fn_t prereset,
 		      ata_reset_fn_t softreset, ata_reset_fn_t hardreset,
 		      ata_postreset_fn_t postreset);
 extern void ata_std_error_handler(struct ata_port *ap);
 /*
  * Base operations to inherit from and initializers for sht
  *
  * Operations
  *
  * base  : Common to all libata drivers.
  * sata  : SATA controllers w/ native interface.
  * pmp   : SATA controllers w/ PMP support.
  * sff   : SFF ATA controllers w/o BMDMA support.
  * bmdma : SFF ATA controllers w/ BMDMA support.
  *
  * sht initializers
  *
  * BASE  : Common to all libata drivers.  The user must set
  *	   sg_tablesize and dma_boundary.
  * PIO   : SFF ATA controllers w/ only PIO support.
  * BMDMA : SFF ATA controllers w/ BMDMA support.  sg_tablesize and
  *	   dma_boundary are set to BMDMA limits.
  * NCQ   : SATA controllers supporting NCQ.  The user must set
  *	   sg_tablesize, dma_boundary and can_queue.
  */
 extern const struct ata_port_operations ata_base_port_ops;
 extern const struct ata_port_operations sata_port_ops;
 extern struct device_attribute *ata_common_sdev_attrs[];
 #define ATA_BASE_SHT(drv_name)					\
 	.module			= THIS_MODULE,			\
 	.name			= drv_name,			\
 	.ioctl			= ata_scsi_ioctl,		\
 	.queuecommand		= ata_scsi_queuecmd,		\
 	.can_queue		= ATA_DEF_QUEUE,		\
 	.this_id		= ATA_SHT_THIS_ID,		\
 	.cmd_per_lun		= ATA_SHT_CMD_PER_LUN,		\
 	.emulated		= ATA_SHT_EMULATED,		\
 	.use_clustering		= ATA_SHT_USE_CLUSTERING,	\
 	.proc_name		= drv_name,			\
 	.slave_configure	= ata_scsi_slave_config,	\
 	.slave_destroy		= ata_scsi_slave_destroy,	\
 	.bios_param		= ata_std_bios_param,		\
 	.unlock_native_capacity	= ata_scsi_unlock_native_capacity, \
 	.sdev_attrs		= ata_common_sdev_attrs
 #define ATA_NCQ_SHT(drv_name)					\
 	ATA_BASE_SHT(drv_name),					\
 	.change_queue_depth	= ata_scsi_change_queue_depth
 /*
  * PMP helpers
  */
 #ifdef CONFIG_SATA_PMP
 static inline bool sata_pmp_supported(struct ata_port *ap)
 {
 	return ap->flags & ATA_FLAG_PMP;
 }
 static inline bool sata_pmp_attached(struct ata_port *ap)
 {
 	return ap->nr_pmp_links != 0;
 }
 static inline int ata_is_host_link(const struct ata_link *link)
 {
 	return link == &link->ap->link || link == link->ap->slave_link;
 }
 #else /* CONFIG_SATA_PMP */
 static inline bool sata_pmp_supported(struct ata_port *ap)
 {
 	return false;
 }
 static inline bool sata_pmp_attached(struct ata_port *ap)
 {
 	return false;
 }
 static inline int ata_is_host_link(const struct ata_link *link)
 {
 	return 1;
 }
 #endif /* CONFIG_SATA_PMP */
 static inline int sata_srst_pmp(struct ata_link *link)
 {
 	if (sata_pmp_supported(link->ap) && ata_is_host_link(link))
 		return SATA_PMP_CTRL_PORT;
 	return link->pmp;
 }
 /*
  * printk helpers
  */
 #define ata_port_printk(ap, lv, fmt, args...) \
 	printk("%sata%u: "fmt, lv, (ap)->print_id , ##args)
 #define ata_link_printk(link, lv, fmt, args...) do { \
 	if (sata_pmp_attached((link)->ap) || (link)->ap->slave_link)	\
 		printk("%sata%u.%02u: "fmt, lv, (link)->ap->print_id,	\
 		       (link)->pmp , ##args); \
 	else \
 		printk("%sata%u: "fmt, lv, (link)->ap->print_id , ##args); \
 	} while(0)
 #define ata_dev_printk(dev, lv, fmt, args...) \
 	printk("%sata%u.%02u: "fmt, lv, (dev)->link->ap->print_id,	\
 	       (dev)->link->pmp + (dev)->devno , ##args)
 /*
  * ata_eh_info helpers
  */
 extern void __ata_ehi_push_desc(struct ata_eh_info *ehi, const char *fmt, ...)
 	__attribute__ ((format (printf, 2, 3)));
 extern void ata_ehi_push_desc(struct ata_eh_info *ehi, const char *fmt, ...)
 	__attribute__ ((format (printf, 2, 3)));
 extern void ata_ehi_clear_desc(struct ata_eh_info *ehi);
 static inline void ata_ehi_hotplugged(struct ata_eh_info *ehi)
 {
 	ehi->probe_mask |= (1 << ATA_MAX_DEVICES) - 1;
 	ehi->flags |= ATA_EHI_HOTPLUGGED;
 	ehi->action |= ATA_EH_RESET | ATA_EH_ENABLE_LINK;
 	ehi->err_mask |= AC_ERR_ATA_BUS;
 }
 /*
  * port description helpers
  */
 extern void ata_port_desc(struct ata_port *ap, const char *fmt, ...)
 	__attribute__ ((format (printf, 2, 3)));
 #ifdef CONFIG_PCI
 extern void ata_port_pbar_desc(struct ata_port *ap, int bar, ssize_t offset,
 			       const char *name);
 #endif
 static inline unsigned int ata_tag_valid(unsigned int tag)
 {
 	return (tag < ATA_MAX_QUEUE) ? 1 : 0;
 }
 static inline unsigned int ata_tag_internal(unsigned int tag)
 {
 	return tag == ATA_TAG_INTERNAL;
 }
 /*
  * device helpers
  */
 static inline unsigned int ata_class_enabled(unsigned int class)
 {
 	return class == ATA_DEV_ATA || class == ATA_DEV_ATAPI ||
 		class == ATA_DEV_PMP || class == ATA_DEV_SEMB;
 }
 static inline unsigned int ata_class_disabled(unsigned int class)
 {
 	return class == ATA_DEV_ATA_UNSUP || class == ATA_DEV_ATAPI_UNSUP ||
 		class == ATA_DEV_PMP_UNSUP || class == ATA_DEV_SEMB_UNSUP;
 }
 static inline unsigned int ata_class_absent(unsigned int class)
 {
 	return !ata_class_enabled(class) && !ata_class_disabled(class);
 }
 static inline unsigned int ata_dev_enabled(const struct ata_device *dev)
 {
 	return ata_class_enabled(dev->class);
 }
 static inline unsigned int ata_dev_disabled(const struct ata_device *dev)
 {
 	return ata_class_disabled(dev->class);
 }
 static inline unsigned int ata_dev_absent(const struct ata_device *dev)
 {
 	return ata_class_absent(dev->class);
 }
 /*
  * link helpers
  */
 static inline int ata_link_max_devices(const struct ata_link *link)
 {
 	if (ata_is_host_link(link) && link->ap->flags & ATA_FLAG_SLAVE_POSS)
 		return 2;
 	return 1;
 }
 static inline int ata_link_active(struct ata_link *link)
 {
 	return ata_tag_valid(link->active_tag) || link->sactive;
 }
 /*
  * Iterators
  *
  * ATA_LITER_* constants are used to select link iteration mode and
  * ATA_DITER_* device iteration mode.
  *
  * For a custom iteration directly using ata_{link|dev}_next(), if
  * @link or @dev, respectively, is NULL, the first element is
  * returned.  @dev and @link can be any valid device or link and the
  * next element according to the iteration mode will be returned.
  * After the last element, NULL is returned.
  */
 enum ata_link_iter_mode {
 	ATA_LITER_EDGE,		/* if present, PMP links only; otherwise,
 				 * host link.  no slave link */
 	ATA_LITER_HOST_FIRST,	/* host link followed by PMP or slave links */
 	ATA_LITER_PMP_FIRST,	/* PMP links followed by host link,
 				 * slave link still comes after host link */
 };
 enum ata_dev_iter_mode {
 	ATA_DITER_ENABLED,
 	ATA_DITER_ENABLED_REVERSE,
 	ATA_DITER_ALL,
 	ATA_DITER_ALL_REVERSE,
 };
 extern struct ata_link *ata_link_next(struct ata_link *link,
 				      struct ata_port *ap,
 				      enum ata_link_iter_mode mode);
 extern struct ata_device *ata_dev_next(struct ata_device *dev,
 				       struct ata_link *link,
 				       enum ata_dev_iter_mode mode);
 /*
  * Shortcut notation for iterations
  *
  * ata_for_each_link() iterates over each link of @ap according to
  * @mode.  @link points to the current link in the loop.  @link is
  * NULL after loop termination.  ata_for_each_dev() works the same way
  * except that it iterates over each device of @link.
  *
  * Note that the mode prefixes ATA_{L|D}ITER_ shouldn't need to be
  * specified when using the following shorthand notations.  Only the
  * mode itself (EDGE, HOST_FIRST, ENABLED, etc...) should be
  * specified.  This not only increases brevity but also makes it
  * impossible to use ATA_LITER_* for device iteration or vice-versa.
  */
 #define ata_for_each_link(link, ap, mode) \
 	for ((link) = ata_link_next(NULL, (ap), ATA_LITER_##mode); (link); \
 	     (link) = ata_link_next((link), (ap), ATA_LITER_##mode))
 #define ata_for_each_dev(dev, link, mode) \
 	for ((dev) = ata_dev_next(NULL, (link), ATA_DITER_##mode); (dev); \
 	     (dev) = ata_dev_next((dev), (link), ATA_DITER_##mode))
 /**
  *	ata_ncq_enabled - Test whether NCQ is enabled
  *	@dev: ATA device to test for
  *
  *	LOCKING:
  *	spin_lock_irqsave(host lock)
  *
  *	RETURNS:
  *	1 if NCQ is enabled for @dev, 0 otherwise.
  */
 static inline int ata_ncq_enabled(struct ata_device *dev)
 {
 	return (dev->flags & (ATA_DFLAG_PIO | ATA_DFLAG_NCQ_OFF |
 			      ATA_DFLAG_NCQ)) == ATA_DFLAG_NCQ;
 }
 static inline void ata_qc_set_polling(struct ata_queued_cmd *qc)
 {
 	qc->tf.ctl |= ATA_NIEN;
 }
 static inline struct ata_queued_cmd *__ata_qc_from_tag(struct ata_port *ap,
 						       unsigned int tag)
 {
 	if (likely(ata_tag_valid(tag)))
 		return &ap->qcmd[tag];
 	return NULL;
 }
 static inline struct ata_queued_cmd *ata_qc_from_tag(struct ata_port *ap,
 						     unsigned int tag)
 {
 	struct ata_queued_cmd *qc = __ata_qc_from_tag(ap, tag);
 	if (unlikely(!qc) || !ap->ops->error_handler)
 		return qc;
 	if ((qc->flags & (ATA_QCFLAG_ACTIVE |
 			  ATA_QCFLAG_FAILED)) == ATA_QCFLAG_ACTIVE)
 		return qc;
 	return NULL;
 }
 static inline unsigned int ata_qc_raw_nbytes(struct ata_queued_cmd *qc)
 {
 	return qc->nbytes - min(qc->extrabytes, qc->nbytes);
 }
 static inline void ata_tf_init(struct ata_device *dev, struct ata_taskfile *tf)
 {
 	memset(tf, 0, sizeof(*tf));
 #ifdef CONFIG_ATA_SFF
 	tf->ctl = dev->link->ap->ctl;
 #else
 	tf->ctl = ATA_DEVCTL_OBS;
 #endif
 	if (dev->devno == 0)
 		tf->device = ATA_DEVICE_OBS;
 	else
 		tf->device = ATA_DEVICE_OBS | ATA_DEV1;
 }
 static inline void ata_qc_reinit(struct ata_queued_cmd *qc)
 {
 	qc->dma_dir = DMA_NONE;
 	qc->sg = NULL;
 	qc->flags = 0;
 	qc->cursg = NULL;
 	qc->cursg_ofs = 0;
 	qc->nbytes = qc->extrabytes = qc->curbytes = 0;
 	qc->n_elem = 0;
 	qc->err_mask = 0;
 	qc->sect_size = ATA_SECT_SIZE;
 	ata_tf_init(qc->dev, &qc->tf);
 	/* init result_tf such that it indicates normal completion */
 	qc->result_tf.command = ATA_DRDY;
 	qc->result_tf.feature = 0;
 }
 static inline int ata_try_flush_cache(const struct ata_device *dev)
 {
 	return ata_id_wcache_enabled(dev->id) ||
 	       ata_id_has_flush(dev->id) ||
 	       ata_id_has_flush_ext(dev->id);
 }
 static inline unsigned int ac_err_mask(u8 status)
 {
 	if (status & (ATA_BUSY | ATA_DRQ))
 		return AC_ERR_HSM;
 	if (status & (ATA_ERR | ATA_DF))
 		return AC_ERR_DEV;
 	return 0;
 }
 static inline unsigned int __ac_err_mask(u8 status)
 {
 	unsigned int mask = ac_err_mask(status);
 	if (mask == 0)
 		return AC_ERR_OTHER;
 	return mask;
 }
 static inline struct ata_port *ata_shost_to_port(struct Scsi_Host *host)
 {
 	return *(struct ata_port **)&host->hostdata[0];
 }
 static inline int ata_check_ready(u8 status)
 {
 	if (!(status & ATA_BUSY))
 		return 1;
 	/* 0xff indicates either no device or device not ready */
 	if (status == 0xff)
 		return -ENODEV;
 	return 0;
 }
 static inline unsigned long ata_deadline(unsigned long from_jiffies,
 					 unsigned long timeout_msecs)
 {
 	return from_jiffies + msecs_to_jiffies(timeout_msecs);
 }
 /* Don't open code these in drivers as there are traps. Firstly the range may
    change in future hardware and specs, secondly 0xFF means 'no DMA' but is
    > UDMA_0. Dyma ddreigiau */
 static inline int ata_using_mwdma(struct ata_device *adev)
 {
 	if (adev->dma_mode >= XFER_MW_DMA_0 && adev->dma_mode <= XFER_MW_DMA_4)
 		return 1;
 	return 0;
 }
 static inline int ata_using_udma(struct ata_device *adev)
 {
 	if (adev->dma_mode >= XFER_UDMA_0 && adev->dma_mode <= XFER_UDMA_7)
 		return 1;
 	return 0;
 }
 static inline int ata_dma_enabled(struct ata_device *adev)
 {
 	return (adev->dma_mode == 0xFF ? 0 : 1);
 }
 /**************************************************************************
  * PMP - drivers/ata/libata-pmp.c
  */
 #ifdef CONFIG_SATA_PMP
 extern const struct ata_port_operations sata_pmp_port_ops;
 extern int sata_pmp_qc_defer_cmd_switch(struct ata_queued_cmd *qc);
 extern void sata_pmp_error_handler(struct ata_port *ap);
 #else /* CONFIG_SATA_PMP */
 #define sata_pmp_port_ops		sata_port_ops
 #define sata_pmp_qc_defer_cmd_switch	ata_std_qc_defer
 #define sata_pmp_error_handler		ata_std_error_handler
 #endif /* CONFIG_SATA_PMP */
 /**************************************************************************
  * SFF - drivers/ata/libata-sff.c
  */
 #ifdef CONFIG_ATA_SFF
 extern const struct ata_port_operations ata_sff_port_ops;
 extern const struct ata_port_operations ata_bmdma32_port_ops;
 /* PIO only, sg_tablesize and dma_boundary limits can be removed */
 #define ATA_PIO_SHT(drv_name)					\
 	ATA_BASE_SHT(drv_name),					\
 	.sg_tablesize		= LIBATA_MAX_PRD,		\
 	.dma_boundary		= ATA_DMA_BOUNDARY
 extern void ata_sff_dev_select(struct ata_port *ap, unsigned int device);
 extern u8 ata_sff_check_status(struct ata_port *ap);
 extern void ata_sff_pause(struct ata_port *ap);
 extern void ata_sff_dma_pause(struct ata_port *ap);
 extern int ata_sff_busy_sleep(struct ata_port *ap,
 			      unsigned long timeout_pat, unsigned long timeout);
 extern int ata_sff_wait_ready(struct ata_link *link, unsigned long deadline);
 extern void ata_sff_tf_load(struct ata_port *ap, const struct ata_taskfile *tf);
 extern void ata_sff_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
 extern void ata_sff_exec_command(struct ata_port *ap,
 				 const struct ata_taskfile *tf);
 extern unsigned int ata_sff_data_xfer(struct ata_device *dev,
 			unsigned char *buf, unsigned int buflen, int rw);
 extern unsigned int ata_sff_data_xfer32(struct ata_device *dev,
 			unsigned char *buf, unsigned int buflen, int rw);
 extern unsigned int ata_sff_data_xfer_noirq(struct ata_device *dev,
 			unsigned char *buf, unsigned int buflen, int rw);
 extern void ata_sff_irq_on(struct ata_port *ap);
 extern void ata_sff_irq_clear(struct ata_port *ap);
 extern int ata_sff_hsm_move(struct ata_port *ap, struct ata_queued_cmd *qc,
 			    u8 status, int in_wq);
-extern void ata_sff_queue_pio_task(struct ata_port *ap, unsigned long delay);
+extern void ata_sff_queue_pio_task(struct ata_link *link, unsigned long delay);
 extern unsigned int ata_sff_qc_issue(struct ata_queued_cmd *qc);
 extern bool ata_sff_qc_fill_rtf(struct ata_queued_cmd *qc);
 extern unsigned int ata_sff_port_intr(struct ata_port *ap,
 				      struct ata_queued_cmd *qc);
 extern irqreturn_t ata_sff_interrupt(int irq, void *dev_instance);
 extern void ata_sff_lost_interrupt(struct ata_port *ap);
 extern void ata_sff_freeze(struct ata_port *ap);
 extern void ata_sff_thaw(struct ata_port *ap);
 extern int ata_sff_prereset(struct ata_link *link, unsigned long deadline);
 extern unsigned int ata_sff_dev_classify(struct ata_device *dev, int present,
 					  u8 *r_err);
 extern int ata_sff_wait_after_reset(struct ata_link *link, unsigned int devmask,
 				    unsigned long deadline);
 extern int ata_sff_softreset(struct ata_link *link, unsigned int *classes,
 			     unsigned long deadline);
 extern int sata_sff_hardreset(struct ata_link *link, unsigned int *class,
 			       unsigned long deadline);
 extern void ata_sff_postreset(struct ata_link *link, unsigned int *classes);
 extern void ata_sff_drain_fifo(struct ata_queued_cmd *qc);
 extern void ata_sff_error_handler(struct ata_port *ap);
 extern void ata_sff_std_ports(struct ata_ioports *ioaddr);
 #ifdef CONFIG_PCI
 extern int ata_pci_sff_init_host(struct ata_host *host);
 extern int ata_pci_sff_prepare_host(struct pci_dev *pdev,
 				    const struct ata_port_info * const * ppi,
 				    struct ata_host **r_host);
 extern int ata_pci_sff_activate_host(struct ata_host *host,
 				     irq_handler_t irq_handler,
 				     struct scsi_host_template *sht);
 extern int ata_pci_sff_init_one(struct pci_dev *pdev,
 		const struct ata_port_info * const * ppi,
 		struct scsi_host_template *sht, void *host_priv, int hflags);
 #endif /* CONFIG_PCI */
 #ifdef CONFIG_ATA_BMDMA
 extern const struct ata_port_operations ata_bmdma_port_ops;
 #define ATA_BMDMA_SHT(drv_name)					\
 	ATA_BASE_SHT(drv_name),					\
 	.sg_tablesize		= LIBATA_MAX_PRD,		\
 	.dma_boundary		= ATA_DMA_BOUNDARY
 extern void ata_bmdma_qc_prep(struct ata_queued_cmd *qc);
 extern unsigned int ata_bmdma_qc_issue(struct ata_queued_cmd *qc);
 extern void ata_bmdma_dumb_qc_prep(struct ata_queued_cmd *qc);
 extern unsigned int ata_bmdma_port_intr(struct ata_port *ap,
 				      struct ata_queued_cmd *qc);
 extern irqreturn_t ata_bmdma_interrupt(int irq, void *dev_instance);
 extern void ata_bmdma_error_handler(struct ata_port *ap);
 extern void ata_bmdma_post_internal_cmd(struct ata_queued_cmd *qc);
 extern void ata_bmdma_irq_clear(struct ata_port *ap);
 extern void ata_bmdma_setup(struct ata_queued_cmd *qc);
 extern void ata_bmdma_start(struct ata_queued_cmd *qc);
 extern void ata_bmdma_stop(struct ata_queued_cmd *qc);
 extern u8 ata_bmdma_status(struct ata_port *ap);
 extern int ata_bmdma_port_start(struct ata_port *ap);
 extern int ata_bmdma_port_start32(struct ata_port *ap);
 #ifdef CONFIG_PCI
 extern int ata_pci_bmdma_clear_simplex(struct pci_dev *pdev);
 extern void ata_pci_bmdma_init(struct ata_host *host);
 extern int ata_pci_bmdma_prepare_host(struct pci_dev *pdev,
 				      const struct ata_port_info * const * ppi,
 				      struct ata_host **r_host);
 extern int ata_pci_bmdma_init_one(struct pci_dev *pdev,
 				  const struct ata_port_info * const * ppi,
 				  struct scsi_host_template *sht,
 				  void *host_priv, int hflags);
 #endif /* CONFIG_PCI */
 #endif /* CONFIG_ATA_BMDMA */
 /**
  *	ata_sff_busy_wait - Wait for a port status register
  *	@ap: Port to wait for.
  *	@bits: bits that must be clear
  *	@max: number of 10uS waits to perform
  *
  *	Waits up to max*10 microseconds for the selected bits in the port's
  *	status register to be cleared.
  *	Returns final value of status register.
  *
  *	LOCKING:
  *	Inherited from caller.
  */
 static inline u8 ata_sff_busy_wait(struct ata_port *ap, unsigned int bits,
 				   unsigned int max)
 {
 	u8 status;
 	do {
 		udelay(10);
 		status = ap->ops->sff_check_status(ap);
 		max--;
 	} while (status != 0xff && (status & bits) && (max > 0));
 	return status;
 }
 /**
  *	ata_wait_idle - Wait for a port to be idle.
  *	@ap: Port to wait for.
  *
  *	Waits up to 10ms for port's BUSY and DRQ signals to clear.
  *	Returns final value of status register.
  *
  *	LOCKING:
  *	Inherited from caller.
  */
 static inline u8 ata_wait_idle(struct ata_port *ap)
 {
 	u8 status = ata_sff_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
 #ifdef ATA_DEBUG
 	if (status != 0xff && (status & (ATA_BUSY | ATA_DRQ)))
 		ata_port_printk(ap, KERN_DEBUG, "abnormal Status 0x%X\n",
 				status);
 #endif
 	return status;
 }
 #endif /* CONFIG_ATA_SFF */
 #endif /* __LINUX_LIBATA_H__ */