Eric Lee / linux-smarc-t335x-v3.2

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Commit e07b1aa8b3ebedd3c7e0e1b4b524f1b2d62707cf

Authored by Stephen Hemminger
Committed by Jeff Garzik
1 parent c4b1580e8a
Exists in master and in 4 other branches v3.2_AM335xPSP_04.06.00.11, v3.2_NEWT335xPSP_04.06.00.11, v3.2_SBC_SMARTMEN, v3.2_SMARCT335xPSP_04.06.00.11

[PATCH] sky2: rework of NAPI and IRQ management 

Redo the interupt handling of sky2 driver based on the IRQ mangement
documentation. All interrupts are handled by the device0 NAPI poll
routine.

Don't need to adjust interrupt mask in IRQ context, done only when
changing device under RTNL. Therefore don't need hwlock anymore.

Signed-off-by: Stephen Hemminger <shemminger@osdl.org>
Signed-off-by: Jeff Garzik <jeff@garzik.org>

Showing 2 changed files with 111 additions and 180 deletions Inline Diff

1 /* 1 /*
2 * New driver for Marvell Yukon 2 chipset. 2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver. 3 * Based on earlier sk98lin, and skge driver.
4 * 4 *
5 * This driver intentionally does not support all the features 5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because 6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels. 7 * those should be done at higher levels.
8 * 8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org> 9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 * 10 *
11 * This program is free software; you can redistribute it and/or modify 11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by 12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or 13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version. 14 * (at your option) any later version.
15 * 15 *
16 * This program is distributed in the hope that it will be useful, 16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details. 19 * GNU General Public License for more details.
20 * 20 *
21 * You should have received a copy of the GNU General Public License 21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software 22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */ 24 */
25 25
26 #include <linux/config.h> 26 #include <linux/config.h>
27 #include <linux/crc32.h> 27 #include <linux/crc32.h>
28 #include <linux/kernel.h> 28 #include <linux/kernel.h>
29 #include <linux/version.h> 29 #include <linux/version.h>
30 #include <linux/module.h> 30 #include <linux/module.h>
31 #include <linux/netdevice.h> 31 #include <linux/netdevice.h>
32 #include <linux/dma-mapping.h> 32 #include <linux/dma-mapping.h>
33 #include <linux/etherdevice.h> 33 #include <linux/etherdevice.h>
34 #include <linux/ethtool.h> 34 #include <linux/ethtool.h>
35 #include <linux/pci.h> 35 #include <linux/pci.h>
36 #include <linux/ip.h> 36 #include <linux/ip.h>
37 #include <linux/tcp.h> 37 #include <linux/tcp.h>
38 #include <linux/in.h> 38 #include <linux/in.h>
39 #include <linux/delay.h> 39 #include <linux/delay.h>
40 #include <linux/workqueue.h> 40 #include <linux/workqueue.h>
41 #include <linux/if_vlan.h> 41 #include <linux/if_vlan.h>
42 #include <linux/prefetch.h> 42 #include <linux/prefetch.h>
43 #include <linux/mii.h> 43 #include <linux/mii.h>
44 44
45 #include <asm/irq.h> 45 #include <asm/irq.h>
46 46
47 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) 47 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48 #define SKY2_VLAN_TAG_USED 1 48 #define SKY2_VLAN_TAG_USED 1
49 #endif 49 #endif
50 50
51 #include "sky2.h" 51 #include "sky2.h"
52 52
53 #define DRV_NAME "sky2" 53 #define DRV_NAME "sky2"
54 #define DRV_VERSION "0.15" 54 #define DRV_VERSION "0.15"
55 #define PFX DRV_NAME " " 55 #define PFX DRV_NAME " "
56 56
57 /* 57 /*
58 * The Yukon II chipset takes 64 bit command blocks (called list elements) 58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings 59 * that are organized into three (receive, transmit, status) different rings
60 * similar to Tigon3. A transmit can require several elements; 60 * similar to Tigon3. A transmit can require several elements;
61 * a receive requires one (or two if using 64 bit dma). 61 * a receive requires one (or two if using 64 bit dma).
62 */ 62 */
63 63
64 #define RX_LE_SIZE 512 64 #define RX_LE_SIZE 512
65 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le)) 65 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
66 #define RX_MAX_PENDING (RX_LE_SIZE/2 - 2) 66 #define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
67 #define RX_DEF_PENDING RX_MAX_PENDING 67 #define RX_DEF_PENDING RX_MAX_PENDING
68 #define RX_SKB_ALIGN 8 68 #define RX_SKB_ALIGN 8
69 69
70 #define TX_RING_SIZE 512 70 #define TX_RING_SIZE 512
71 #define TX_DEF_PENDING (TX_RING_SIZE - 1) 71 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
72 #define TX_MIN_PENDING 64 72 #define TX_MIN_PENDING 64
73 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS) 73 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
74 74
75 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */ 75 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
76 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le)) 76 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
77 #define ETH_JUMBO_MTU 9000 77 #define ETH_JUMBO_MTU 9000
78 #define TX_WATCHDOG (5 * HZ) 78 #define TX_WATCHDOG (5 * HZ)
79 #define NAPI_WEIGHT 64 79 #define NAPI_WEIGHT 64
80 #define PHY_RETRIES 1000 80 #define PHY_RETRIES 1000
81 81
82 static const u32 default_msg = 82 static const u32 default_msg =
83 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK 83 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
84 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR 84 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
85 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN; 85 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
86 86
87 static int debug = -1; /* defaults above */ 87 static int debug = -1; /* defaults above */
88 module_param(debug, int, 0); 88 module_param(debug, int, 0);
89 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 89 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
90 90
91 static int copybreak __read_mostly = 256; 91 static int copybreak __read_mostly = 256;
92 module_param(copybreak, int, 0); 92 module_param(copybreak, int, 0);
93 MODULE_PARM_DESC(copybreak, "Receive copy threshold"); 93 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
94 94
95 static const struct pci_device_id sky2_id_table[] = { 95 static const struct pci_device_id sky2_id_table[] = {
96 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, 96 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
97 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, 97 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
98 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, 98 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) },
99 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) }, 99 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) },
100 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, 100 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
101 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, 101 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
102 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, 102 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
103 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, 103 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
104 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, 104 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
105 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, 105 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
106 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, 106 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
107 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, 107 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, 108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, 109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, 110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, 111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, 112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, 113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, 114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },
115 { 0 } 115 { 0 }
116 }; 116 };
117 117
118 MODULE_DEVICE_TABLE(pci, sky2_id_table); 118 MODULE_DEVICE_TABLE(pci, sky2_id_table);
119 119
120 /* Avoid conditionals by using array */ 120 /* Avoid conditionals by using array */
121 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 }; 121 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
122 static const unsigned rxqaddr[] = { Q_R1, Q_R2 }; 122 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
123 123
124 /* This driver supports yukon2 chipset only */ 124 /* This driver supports yukon2 chipset only */
125 static const char *yukon2_name[] = { 125 static const char *yukon2_name[] = {
126 "XL", /* 0xb3 */ 126 "XL", /* 0xb3 */
127 "EC Ultra", /* 0xb4 */ 127 "EC Ultra", /* 0xb4 */
128 "UNKNOWN", /* 0xb5 */ 128 "UNKNOWN", /* 0xb5 */
129 "EC", /* 0xb6 */ 129 "EC", /* 0xb6 */
130 "FE", /* 0xb7 */ 130 "FE", /* 0xb7 */
131 }; 131 };
132 132
133 /* Access to external PHY */ 133 /* Access to external PHY */
134 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val) 134 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
135 { 135 {
136 int i; 136 int i;
137 137
138 gma_write16(hw, port, GM_SMI_DATA, val); 138 gma_write16(hw, port, GM_SMI_DATA, val);
139 gma_write16(hw, port, GM_SMI_CTRL, 139 gma_write16(hw, port, GM_SMI_CTRL,
140 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg)); 140 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
141 141
142 for (i = 0; i < PHY_RETRIES; i++) { 142 for (i = 0; i < PHY_RETRIES; i++) {
143 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY)) 143 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
144 return 0; 144 return 0;
145 udelay(1); 145 udelay(1);
146 } 146 }
147 147
148 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name); 148 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
149 return -ETIMEDOUT; 149 return -ETIMEDOUT;
150 } 150 }
151 151
152 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val) 152 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
153 { 153 {
154 int i; 154 int i;
155 155
156 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) 156 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
157 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD); 157 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
158 158
159 for (i = 0; i < PHY_RETRIES; i++) { 159 for (i = 0; i < PHY_RETRIES; i++) {
160 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) { 160 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
161 *val = gma_read16(hw, port, GM_SMI_DATA); 161 *val = gma_read16(hw, port, GM_SMI_DATA);
162 return 0; 162 return 0;
163 } 163 }
164 164
165 udelay(1); 165 udelay(1);
166 } 166 }
167 167
168 return -ETIMEDOUT; 168 return -ETIMEDOUT;
169 } 169 }
170 170
171 static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg) 171 static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
172 { 172 {
173 u16 v; 173 u16 v;
174 174
175 if (__gm_phy_read(hw, port, reg, &v) != 0) 175 if (__gm_phy_read(hw, port, reg, &v) != 0)
176 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name); 176 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
177 return v; 177 return v;
178 } 178 }
179 179
180 static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state) 180 static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
181 { 181 {
182 u16 power_control; 182 u16 power_control;
183 u32 reg1; 183 u32 reg1;
184 int vaux; 184 int vaux;
185 int ret = 0; 185 int ret = 0;
186 186
187 pr_debug("sky2_set_power_state %d\n", state); 187 pr_debug("sky2_set_power_state %d\n", state);
188 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 188 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
189 189
190 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_PMC); 190 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_PMC);
191 vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) && 191 vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
192 (power_control & PCI_PM_CAP_PME_D3cold); 192 (power_control & PCI_PM_CAP_PME_D3cold);
193 193
194 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_CTRL); 194 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_CTRL);
195 195
196 power_control |= PCI_PM_CTRL_PME_STATUS; 196 power_control |= PCI_PM_CTRL_PME_STATUS;
197 power_control &= ~(PCI_PM_CTRL_STATE_MASK); 197 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
198 198
199 switch (state) { 199 switch (state) {
200 case PCI_D0: 200 case PCI_D0:
201 /* switch power to VCC (WA for VAUX problem) */ 201 /* switch power to VCC (WA for VAUX problem) */
202 sky2_write8(hw, B0_POWER_CTRL, 202 sky2_write8(hw, B0_POWER_CTRL,
203 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON); 203 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
204 204
205 /* disable Core Clock Division, */ 205 /* disable Core Clock Division, */
206 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS); 206 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
207 207
208 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) 208 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
209 /* enable bits are inverted */ 209 /* enable bits are inverted */
210 sky2_write8(hw, B2_Y2_CLK_GATE, 210 sky2_write8(hw, B2_Y2_CLK_GATE,
211 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 211 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
212 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 212 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
213 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS); 213 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
214 else 214 else
215 sky2_write8(hw, B2_Y2_CLK_GATE, 0); 215 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
216 216
217 /* Turn off phy power saving */ 217 /* Turn off phy power saving */
218 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); 218 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
219 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); 219 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
220 220
221 /* looks like this XL is back asswards .. */ 221 /* looks like this XL is back asswards .. */
222 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) { 222 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) {
223 reg1 |= PCI_Y2_PHY1_COMA; 223 reg1 |= PCI_Y2_PHY1_COMA;
224 if (hw->ports > 1) 224 if (hw->ports > 1)
225 reg1 |= PCI_Y2_PHY2_COMA; 225 reg1 |= PCI_Y2_PHY2_COMA;
226 } 226 }
227 227
228 if (hw->chip_id == CHIP_ID_YUKON_EC_U) { 228 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
229 sky2_pci_write32(hw, PCI_DEV_REG3, 0); 229 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
230 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4); 230 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
231 reg1 &= P_ASPM_CONTROL_MSK; 231 reg1 &= P_ASPM_CONTROL_MSK;
232 sky2_pci_write32(hw, PCI_DEV_REG4, reg1); 232 sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
233 sky2_pci_write32(hw, PCI_DEV_REG5, 0); 233 sky2_pci_write32(hw, PCI_DEV_REG5, 0);
234 } 234 }
235 235
236 sky2_pci_write32(hw, PCI_DEV_REG1, reg1); 236 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
237 237
238 break; 238 break;
239 239
240 case PCI_D3hot: 240 case PCI_D3hot:
241 case PCI_D3cold: 241 case PCI_D3cold:
242 /* Turn on phy power saving */ 242 /* Turn on phy power saving */
243 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); 243 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
244 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) 244 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
245 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); 245 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
246 else 246 else
247 reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); 247 reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
248 sky2_pci_write32(hw, PCI_DEV_REG1, reg1); 248 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
249 249
250 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) 250 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
251 sky2_write8(hw, B2_Y2_CLK_GATE, 0); 251 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
252 else 252 else
253 /* enable bits are inverted */ 253 /* enable bits are inverted */
254 sky2_write8(hw, B2_Y2_CLK_GATE, 254 sky2_write8(hw, B2_Y2_CLK_GATE,
255 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 255 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
256 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 256 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
257 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS); 257 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
258 258
259 /* switch power to VAUX */ 259 /* switch power to VAUX */
260 if (vaux && state != PCI_D3cold) 260 if (vaux && state != PCI_D3cold)
261 sky2_write8(hw, B0_POWER_CTRL, 261 sky2_write8(hw, B0_POWER_CTRL,
262 (PC_VAUX_ENA | PC_VCC_ENA | 262 (PC_VAUX_ENA | PC_VCC_ENA |
263 PC_VAUX_ON | PC_VCC_OFF)); 263 PC_VAUX_ON | PC_VCC_OFF));
264 break; 264 break;
265 default: 265 default:
266 printk(KERN_ERR PFX "Unknown power state %d\n", state); 266 printk(KERN_ERR PFX "Unknown power state %d\n", state);
267 ret = -1; 267 ret = -1;
268 } 268 }
269 269
270 sky2_pci_write16(hw, hw->pm_cap + PCI_PM_CTRL, power_control); 270 sky2_pci_write16(hw, hw->pm_cap + PCI_PM_CTRL, power_control);
271 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 271 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
272 return ret; 272 return ret;
273 } 273 }
274 274
275 static void sky2_phy_reset(struct sky2_hw *hw, unsigned port) 275 static void sky2_phy_reset(struct sky2_hw *hw, unsigned port)
276 { 276 {
277 u16 reg; 277 u16 reg;
278 278
279 /* disable all GMAC IRQ's */ 279 /* disable all GMAC IRQ's */
280 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0); 280 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
281 /* disable PHY IRQs */ 281 /* disable PHY IRQs */
282 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0); 282 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
283 283
284 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */ 284 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
285 gma_write16(hw, port, GM_MC_ADDR_H2, 0); 285 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
286 gma_write16(hw, port, GM_MC_ADDR_H3, 0); 286 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
287 gma_write16(hw, port, GM_MC_ADDR_H4, 0); 287 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
288 288
289 reg = gma_read16(hw, port, GM_RX_CTRL); 289 reg = gma_read16(hw, port, GM_RX_CTRL);
290 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA; 290 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
291 gma_write16(hw, port, GM_RX_CTRL, reg); 291 gma_write16(hw, port, GM_RX_CTRL, reg);
292 } 292 }
293 293
294 static void sky2_phy_init(struct sky2_hw *hw, unsigned port) 294 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
295 { 295 {
296 struct sky2_port *sky2 = netdev_priv(hw->dev[port]); 296 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
297 u16 ctrl, ct1000, adv, pg, ledctrl, ledover; 297 u16 ctrl, ct1000, adv, pg, ledctrl, ledover;
298 298
299 if (sky2->autoneg == AUTONEG_ENABLE && hw->chip_id != CHIP_ID_YUKON_XL) { 299 if (sky2->autoneg == AUTONEG_ENABLE && hw->chip_id != CHIP_ID_YUKON_XL) {
300 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL); 300 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
301 301
302 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK | 302 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
303 PHY_M_EC_MAC_S_MSK); 303 PHY_M_EC_MAC_S_MSK);
304 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ); 304 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
305 305
306 if (hw->chip_id == CHIP_ID_YUKON_EC) 306 if (hw->chip_id == CHIP_ID_YUKON_EC)
307 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA; 307 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
308 else 308 else
309 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3); 309 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
310 310
311 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl); 311 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
312 } 312 }
313 313
314 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); 314 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
315 if (hw->copper) { 315 if (hw->copper) {
316 if (hw->chip_id == CHIP_ID_YUKON_FE) { 316 if (hw->chip_id == CHIP_ID_YUKON_FE) {
317 /* enable automatic crossover */ 317 /* enable automatic crossover */
318 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1; 318 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
319 } else { 319 } else {
320 /* disable energy detect */ 320 /* disable energy detect */
321 ctrl &= ~PHY_M_PC_EN_DET_MSK; 321 ctrl &= ~PHY_M_PC_EN_DET_MSK;
322 322
323 /* enable automatic crossover */ 323 /* enable automatic crossover */
324 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO); 324 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
325 325
326 if (sky2->autoneg == AUTONEG_ENABLE && 326 if (sky2->autoneg == AUTONEG_ENABLE &&
327 hw->chip_id == CHIP_ID_YUKON_XL) { 327 hw->chip_id == CHIP_ID_YUKON_XL) {
328 ctrl &= ~PHY_M_PC_DSC_MSK; 328 ctrl &= ~PHY_M_PC_DSC_MSK;
329 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA; 329 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
330 } 330 }
331 } 331 }
332 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); 332 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
333 } else { 333 } else {
334 /* workaround for deviation #4.88 (CRC errors) */ 334 /* workaround for deviation #4.88 (CRC errors) */
335 /* disable Automatic Crossover */ 335 /* disable Automatic Crossover */
336 336
337 ctrl &= ~PHY_M_PC_MDIX_MSK; 337 ctrl &= ~PHY_M_PC_MDIX_MSK;
338 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); 338 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
339 339
340 if (hw->chip_id == CHIP_ID_YUKON_XL) { 340 if (hw->chip_id == CHIP_ID_YUKON_XL) {
341 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */ 341 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
342 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2); 342 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
343 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); 343 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
344 ctrl &= ~PHY_M_MAC_MD_MSK; 344 ctrl &= ~PHY_M_MAC_MD_MSK;
345 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX); 345 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
346 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); 346 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
347 347
348 /* select page 1 to access Fiber registers */ 348 /* select page 1 to access Fiber registers */
349 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1); 349 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
350 } 350 }
351 } 351 }
352 352
353 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL); 353 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
354 if (sky2->autoneg == AUTONEG_DISABLE) 354 if (sky2->autoneg == AUTONEG_DISABLE)
355 ctrl &= ~PHY_CT_ANE; 355 ctrl &= ~PHY_CT_ANE;
356 else 356 else
357 ctrl |= PHY_CT_ANE; 357 ctrl |= PHY_CT_ANE;
358 358
359 ctrl |= PHY_CT_RESET; 359 ctrl |= PHY_CT_RESET;
360 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); 360 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
361 361
362 ctrl = 0; 362 ctrl = 0;
363 ct1000 = 0; 363 ct1000 = 0;
364 adv = PHY_AN_CSMA; 364 adv = PHY_AN_CSMA;
365 365
366 if (sky2->autoneg == AUTONEG_ENABLE) { 366 if (sky2->autoneg == AUTONEG_ENABLE) {
367 if (hw->copper) { 367 if (hw->copper) {
368 if (sky2->advertising & ADVERTISED_1000baseT_Full) 368 if (sky2->advertising & ADVERTISED_1000baseT_Full)
369 ct1000 |= PHY_M_1000C_AFD; 369 ct1000 |= PHY_M_1000C_AFD;
370 if (sky2->advertising & ADVERTISED_1000baseT_Half) 370 if (sky2->advertising & ADVERTISED_1000baseT_Half)
371 ct1000 |= PHY_M_1000C_AHD; 371 ct1000 |= PHY_M_1000C_AHD;
372 if (sky2->advertising & ADVERTISED_100baseT_Full) 372 if (sky2->advertising & ADVERTISED_100baseT_Full)
373 adv |= PHY_M_AN_100_FD; 373 adv |= PHY_M_AN_100_FD;
374 if (sky2->advertising & ADVERTISED_100baseT_Half) 374 if (sky2->advertising & ADVERTISED_100baseT_Half)
375 adv |= PHY_M_AN_100_HD; 375 adv |= PHY_M_AN_100_HD;
376 if (sky2->advertising & ADVERTISED_10baseT_Full) 376 if (sky2->advertising & ADVERTISED_10baseT_Full)
377 adv |= PHY_M_AN_10_FD; 377 adv |= PHY_M_AN_10_FD;
378 if (sky2->advertising & ADVERTISED_10baseT_Half) 378 if (sky2->advertising & ADVERTISED_10baseT_Half)
379 adv |= PHY_M_AN_10_HD; 379 adv |= PHY_M_AN_10_HD;
380 } else /* special defines for FIBER (88E1011S only) */ 380 } else /* special defines for FIBER (88E1011S only) */
381 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD; 381 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
382 382
383 /* Set Flow-control capabilities */ 383 /* Set Flow-control capabilities */
384 if (sky2->tx_pause && sky2->rx_pause) 384 if (sky2->tx_pause && sky2->rx_pause)
385 adv |= PHY_AN_PAUSE_CAP; /* symmetric */ 385 adv |= PHY_AN_PAUSE_CAP; /* symmetric */
386 else if (sky2->rx_pause && !sky2->tx_pause) 386 else if (sky2->rx_pause && !sky2->tx_pause)
387 adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP; 387 adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;
388 else if (!sky2->rx_pause && sky2->tx_pause) 388 else if (!sky2->rx_pause && sky2->tx_pause)
389 adv |= PHY_AN_PAUSE_ASYM; /* local */ 389 adv |= PHY_AN_PAUSE_ASYM; /* local */
390 390
391 /* Restart Auto-negotiation */ 391 /* Restart Auto-negotiation */
392 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG; 392 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
393 } else { 393 } else {
394 /* forced speed/duplex settings */ 394 /* forced speed/duplex settings */
395 ct1000 = PHY_M_1000C_MSE; 395 ct1000 = PHY_M_1000C_MSE;
396 396
397 if (sky2->duplex == DUPLEX_FULL) 397 if (sky2->duplex == DUPLEX_FULL)
398 ctrl |= PHY_CT_DUP_MD; 398 ctrl |= PHY_CT_DUP_MD;
399 399
400 switch (sky2->speed) { 400 switch (sky2->speed) {
401 case SPEED_1000: 401 case SPEED_1000:
402 ctrl |= PHY_CT_SP1000; 402 ctrl |= PHY_CT_SP1000;
403 break; 403 break;
404 case SPEED_100: 404 case SPEED_100:
405 ctrl |= PHY_CT_SP100; 405 ctrl |= PHY_CT_SP100;
406 break; 406 break;
407 } 407 }
408 408
409 ctrl |= PHY_CT_RESET; 409 ctrl |= PHY_CT_RESET;
410 } 410 }
411 411
412 if (hw->chip_id != CHIP_ID_YUKON_FE) 412 if (hw->chip_id != CHIP_ID_YUKON_FE)
413 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000); 413 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
414 414
415 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv); 415 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
416 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); 416 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
417 417
418 /* Setup Phy LED's */ 418 /* Setup Phy LED's */
419 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS); 419 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
420 ledover = 0; 420 ledover = 0;
421 421
422 switch (hw->chip_id) { 422 switch (hw->chip_id) {
423 case CHIP_ID_YUKON_FE: 423 case CHIP_ID_YUKON_FE:
424 /* on 88E3082 these bits are at 11..9 (shifted left) */ 424 /* on 88E3082 these bits are at 11..9 (shifted left) */
425 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1; 425 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
426 426
427 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR); 427 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
428 428
429 /* delete ACT LED control bits */ 429 /* delete ACT LED control bits */
430 ctrl &= ~PHY_M_FELP_LED1_MSK; 430 ctrl &= ~PHY_M_FELP_LED1_MSK;
431 /* change ACT LED control to blink mode */ 431 /* change ACT LED control to blink mode */
432 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL); 432 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
433 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl); 433 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
434 break; 434 break;
435 435
436 case CHIP_ID_YUKON_XL: 436 case CHIP_ID_YUKON_XL:
437 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); 437 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
438 438
439 /* select page 3 to access LED control register */ 439 /* select page 3 to access LED control register */
440 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); 440 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
441 441
442 /* set LED Function Control register */ 442 /* set LED Function Control register */
443 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */ 443 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
444 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */ 444 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
445 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */ 445 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
446 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */ 446 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
447 447
448 /* set Polarity Control register */ 448 /* set Polarity Control register */
449 gm_phy_write(hw, port, PHY_MARV_PHY_STAT, 449 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
450 (PHY_M_POLC_LS1_P_MIX(4) | 450 (PHY_M_POLC_LS1_P_MIX(4) |
451 PHY_M_POLC_IS0_P_MIX(4) | 451 PHY_M_POLC_IS0_P_MIX(4) |
452 PHY_M_POLC_LOS_CTRL(2) | 452 PHY_M_POLC_LOS_CTRL(2) |
453 PHY_M_POLC_INIT_CTRL(2) | 453 PHY_M_POLC_INIT_CTRL(2) |
454 PHY_M_POLC_STA1_CTRL(2) | 454 PHY_M_POLC_STA1_CTRL(2) |
455 PHY_M_POLC_STA0_CTRL(2))); 455 PHY_M_POLC_STA0_CTRL(2)));
456 456
457 /* restore page register */ 457 /* restore page register */
458 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); 458 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
459 break; 459 break;
460 460
461 default: 461 default:
462 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */ 462 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
463 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL; 463 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
464 /* turn off the Rx LED (LED_RX) */ 464 /* turn off the Rx LED (LED_RX) */
465 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF); 465 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
466 } 466 }
467 467
468 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) { 468 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
469 /* apply fixes in PHY AFE */ 469 /* apply fixes in PHY AFE */
470 gm_phy_write(hw, port, 22, 255); 470 gm_phy_write(hw, port, 22, 255);
471 /* increase differential signal amplitude in 10BASE-T */ 471 /* increase differential signal amplitude in 10BASE-T */
472 gm_phy_write(hw, port, 24, 0xaa99); 472 gm_phy_write(hw, port, 24, 0xaa99);
473 gm_phy_write(hw, port, 23, 0x2011); 473 gm_phy_write(hw, port, 23, 0x2011);
474 474
475 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */ 475 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
476 gm_phy_write(hw, port, 24, 0xa204); 476 gm_phy_write(hw, port, 24, 0xa204);
477 gm_phy_write(hw, port, 23, 0x2002); 477 gm_phy_write(hw, port, 23, 0x2002);
478 478
479 /* set page register to 0 */ 479 /* set page register to 0 */
480 gm_phy_write(hw, port, 22, 0); 480 gm_phy_write(hw, port, 22, 0);
481 } else { 481 } else {
482 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl); 482 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
483 483
484 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) { 484 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
485 /* turn on 100 Mbps LED (LED_LINK100) */ 485 /* turn on 100 Mbps LED (LED_LINK100) */
486 ledover |= PHY_M_LED_MO_100(MO_LED_ON); 486 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
487 } 487 }
488 488
489 if (ledover) 489 if (ledover)
490 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover); 490 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
491 491
492 } 492 }
493 /* Enable phy interrupt on auto-negotiation complete (or link up) */ 493 /* Enable phy interrupt on auto-negotiation complete (or link up) */
494 if (sky2->autoneg == AUTONEG_ENABLE) 494 if (sky2->autoneg == AUTONEG_ENABLE)
495 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL); 495 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
496 else 496 else
497 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); 497 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
498 } 498 }
499 499
500 /* Force a renegotiation */ 500 /* Force a renegotiation */
501 static void sky2_phy_reinit(struct sky2_port *sky2) 501 static void sky2_phy_reinit(struct sky2_port *sky2)
502 { 502 {
503 down(&sky2->phy_sema); 503 spin_lock_bh(&sky2->phy_lock);
504 sky2_phy_init(sky2->hw, sky2->port); 504 sky2_phy_init(sky2->hw, sky2->port);
505 up(&sky2->phy_sema); 505 spin_unlock_bh(&sky2->phy_lock);
506 } 506 }
507 507
508 static void sky2_mac_init(struct sky2_hw *hw, unsigned port) 508 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
509 { 509 {
510 struct sky2_port *sky2 = netdev_priv(hw->dev[port]); 510 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
511 u16 reg; 511 u16 reg;
512 int i; 512 int i;
513 const u8 *addr = hw->dev[port]->dev_addr; 513 const u8 *addr = hw->dev[port]->dev_addr;
514 514
515 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); 515 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
516 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE); 516 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
517 517
518 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); 518 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
519 519
520 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) { 520 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
521 /* WA DEV_472 -- looks like crossed wires on port 2 */ 521 /* WA DEV_472 -- looks like crossed wires on port 2 */
522 /* clear GMAC 1 Control reset */ 522 /* clear GMAC 1 Control reset */
523 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR); 523 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
524 do { 524 do {
525 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET); 525 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
526 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR); 526 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
527 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL || 527 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
528 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 || 528 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
529 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0); 529 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
530 } 530 }
531 531
532 if (sky2->autoneg == AUTONEG_DISABLE) { 532 if (sky2->autoneg == AUTONEG_DISABLE) {
533 reg = gma_read16(hw, port, GM_GP_CTRL); 533 reg = gma_read16(hw, port, GM_GP_CTRL);
534 reg |= GM_GPCR_AU_ALL_DIS; 534 reg |= GM_GPCR_AU_ALL_DIS;
535 gma_write16(hw, port, GM_GP_CTRL, reg); 535 gma_write16(hw, port, GM_GP_CTRL, reg);
536 gma_read16(hw, port, GM_GP_CTRL); 536 gma_read16(hw, port, GM_GP_CTRL);
537 537
538 switch (sky2->speed) { 538 switch (sky2->speed) {
539 case SPEED_1000: 539 case SPEED_1000:
540 reg &= ~GM_GPCR_SPEED_100; 540 reg &= ~GM_GPCR_SPEED_100;
541 reg |= GM_GPCR_SPEED_1000; 541 reg |= GM_GPCR_SPEED_1000;
542 break; 542 break;
543 case SPEED_100: 543 case SPEED_100:
544 reg &= ~GM_GPCR_SPEED_1000; 544 reg &= ~GM_GPCR_SPEED_1000;
545 reg |= GM_GPCR_SPEED_100; 545 reg |= GM_GPCR_SPEED_100;
546 break; 546 break;
547 case SPEED_10: 547 case SPEED_10:
548 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100); 548 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
549 break; 549 break;
550 } 550 }
551 551
552 if (sky2->duplex == DUPLEX_FULL) 552 if (sky2->duplex == DUPLEX_FULL)
553 reg |= GM_GPCR_DUP_FULL; 553 reg |= GM_GPCR_DUP_FULL;
554 } else 554 } else
555 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL; 555 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
556 556
557 if (!sky2->tx_pause && !sky2->rx_pause) { 557 if (!sky2->tx_pause && !sky2->rx_pause) {
558 sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); 558 sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
559 reg |= 559 reg |=
560 GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS; 560 GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
561 } else if (sky2->tx_pause && !sky2->rx_pause) { 561 } else if (sky2->tx_pause && !sky2->rx_pause) {
562 /* disable Rx flow-control */ 562 /* disable Rx flow-control */
563 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS; 563 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
564 } 564 }
565 565
566 gma_write16(hw, port, GM_GP_CTRL, reg); 566 gma_write16(hw, port, GM_GP_CTRL, reg);
567 567
568 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC)); 568 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
569 569
570 down(&sky2->phy_sema); 570 spin_lock_bh(&sky2->phy_lock);
571 sky2_phy_init(hw, port); 571 sky2_phy_init(hw, port);
572 up(&sky2->phy_sema); 572 spin_unlock_bh(&sky2->phy_lock);
573 573
574 /* MIB clear */ 574 /* MIB clear */
575 reg = gma_read16(hw, port, GM_PHY_ADDR); 575 reg = gma_read16(hw, port, GM_PHY_ADDR);
576 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR); 576 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
577 577
578 for (i = 0; i < GM_MIB_CNT_SIZE; i++) 578 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
579 gma_read16(hw, port, GM_MIB_CNT_BASE + 8 * i); 579 gma_read16(hw, port, GM_MIB_CNT_BASE + 8 * i);
580 gma_write16(hw, port, GM_PHY_ADDR, reg); 580 gma_write16(hw, port, GM_PHY_ADDR, reg);
581 581
582 /* transmit control */ 582 /* transmit control */
583 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); 583 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
584 584
585 /* receive control reg: unicast + multicast + no FCS */ 585 /* receive control reg: unicast + multicast + no FCS */
586 gma_write16(hw, port, GM_RX_CTRL, 586 gma_write16(hw, port, GM_RX_CTRL,
587 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA); 587 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
588 588
589 /* transmit flow control */ 589 /* transmit flow control */
590 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff); 590 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
591 591
592 /* transmit parameter */ 592 /* transmit parameter */
593 gma_write16(hw, port, GM_TX_PARAM, 593 gma_write16(hw, port, GM_TX_PARAM,
594 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | 594 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
595 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) | 595 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
596 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) | 596 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
597 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF)); 597 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
598 598
599 /* serial mode register */ 599 /* serial mode register */
600 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) | 600 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
601 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF); 601 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
602 602
603 if (hw->dev[port]->mtu > ETH_DATA_LEN) 603 if (hw->dev[port]->mtu > ETH_DATA_LEN)
604 reg |= GM_SMOD_JUMBO_ENA; 604 reg |= GM_SMOD_JUMBO_ENA;
605 605
606 gma_write16(hw, port, GM_SERIAL_MODE, reg); 606 gma_write16(hw, port, GM_SERIAL_MODE, reg);
607 607
608 /* virtual address for data */ 608 /* virtual address for data */
609 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr); 609 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
610 610
611 /* physical address: used for pause frames */ 611 /* physical address: used for pause frames */
612 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr); 612 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
613 613
614 /* ignore counter overflows */ 614 /* ignore counter overflows */
615 gma_write16(hw, port, GM_TX_IRQ_MSK, 0); 615 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
616 gma_write16(hw, port, GM_RX_IRQ_MSK, 0); 616 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
617 gma_write16(hw, port, GM_TR_IRQ_MSK, 0); 617 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
618 618
619 /* Configure Rx MAC FIFO */ 619 /* Configure Rx MAC FIFO */
620 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR); 620 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
621 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), 621 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
622 GMF_OPER_ON | GMF_RX_F_FL_ON); 622 GMF_OPER_ON | GMF_RX_F_FL_ON);
623 623
624 /* Flush Rx MAC FIFO on any flow control or error */ 624 /* Flush Rx MAC FIFO on any flow control or error */
625 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR); 625 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
626 626
627 /* Set threshold to 0xa (64 bytes) 627 /* Set threshold to 0xa (64 bytes)
628 * ASF disabled so no need to do WA dev #4.30 628 * ASF disabled so no need to do WA dev #4.30
629 */ 629 */
630 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF); 630 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
631 631
632 /* Configure Tx MAC FIFO */ 632 /* Configure Tx MAC FIFO */
633 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR); 633 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
634 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON); 634 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
635 635
636 if (hw->chip_id == CHIP_ID_YUKON_EC_U) { 636 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
637 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8); 637 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
638 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8); 638 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
639 if (hw->dev[port]->mtu > ETH_DATA_LEN) { 639 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
640 /* set Tx GMAC FIFO Almost Empty Threshold */ 640 /* set Tx GMAC FIFO Almost Empty Threshold */
641 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180); 641 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
642 /* Disable Store & Forward mode for TX */ 642 /* Disable Store & Forward mode for TX */
643 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS); 643 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
644 } 644 }
645 } 645 }
646 646
647 } 647 }
648 648
649 /* Assign Ram Buffer allocation. 649 /* Assign Ram Buffer allocation.
650 * start and end are in units of 4k bytes 650 * start and end are in units of 4k bytes
651 * ram registers are in units of 64bit words 651 * ram registers are in units of 64bit words
652 */ 652 */
653 static void sky2_ramset(struct sky2_hw *hw, u16 q, u8 startk, u8 endk) 653 static void sky2_ramset(struct sky2_hw *hw, u16 q, u8 startk, u8 endk)
654 { 654 {
655 u32 start, end; 655 u32 start, end;
656 656
657 start = startk * 4096/8; 657 start = startk * 4096/8;
658 end = (endk * 4096/8) - 1; 658 end = (endk * 4096/8) - 1;
659 659
660 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR); 660 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
661 sky2_write32(hw, RB_ADDR(q, RB_START), start); 661 sky2_write32(hw, RB_ADDR(q, RB_START), start);
662 sky2_write32(hw, RB_ADDR(q, RB_END), end); 662 sky2_write32(hw, RB_ADDR(q, RB_END), end);
663 sky2_write32(hw, RB_ADDR(q, RB_WP), start); 663 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
664 sky2_write32(hw, RB_ADDR(q, RB_RP), start); 664 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
665 665
666 if (q == Q_R1 || q == Q_R2) { 666 if (q == Q_R1 || q == Q_R2) {
667 u32 space = (endk - startk) * 4096/8; 667 u32 space = (endk - startk) * 4096/8;
668 u32 tp = space - space/4; 668 u32 tp = space - space/4;
669 669
670 /* On receive queue's set the thresholds 670 /* On receive queue's set the thresholds
671 * give receiver priority when > 3/4 full 671 * give receiver priority when > 3/4 full
672 * send pause when down to 2K 672 * send pause when down to 2K
673 */ 673 */
674 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp); 674 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
675 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2); 675 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
676 676
677 tp = space - 2048/8; 677 tp = space - 2048/8;
678 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp); 678 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
679 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4); 679 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
680 } else { 680 } else {
681 /* Enable store & forward on Tx queue's because 681 /* Enable store & forward on Tx queue's because
682 * Tx FIFO is only 1K on Yukon 682 * Tx FIFO is only 1K on Yukon
683 */ 683 */
684 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD); 684 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
685 } 685 }
686 686
687 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD); 687 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
688 sky2_read8(hw, RB_ADDR(q, RB_CTRL)); 688 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
689 } 689 }
690 690
691 /* Setup Bus Memory Interface */ 691 /* Setup Bus Memory Interface */
692 static void sky2_qset(struct sky2_hw *hw, u16 q) 692 static void sky2_qset(struct sky2_hw *hw, u16 q)
693 { 693 {
694 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET); 694 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
695 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT); 695 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
696 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON); 696 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
697 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT); 697 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
698 } 698 }
699 699
700 /* Setup prefetch unit registers. This is the interface between 700 /* Setup prefetch unit registers. This is the interface between
701 * hardware and driver list elements 701 * hardware and driver list elements
702 */ 702 */
703 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr, 703 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
704 u64 addr, u32 last) 704 u64 addr, u32 last)
705 { 705 {
706 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET); 706 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
707 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR); 707 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
708 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32); 708 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
709 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr); 709 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
710 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last); 710 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
711 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON); 711 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
712 712
713 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL)); 713 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
714 } 714 }
715 715
716 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2) 716 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
717 { 717 {
718 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod; 718 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
719 719
720 sky2->tx_prod = (sky2->tx_prod + 1) % TX_RING_SIZE; 720 sky2->tx_prod = (sky2->tx_prod + 1) % TX_RING_SIZE;
721 return le; 721 return le;
722 } 722 }
723 723
724 /* Update chip's next pointer */ 724 /* Update chip's next pointer */
725 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx) 725 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
726 { 726 {
727 wmb(); 727 wmb();
728 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx); 728 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
729 mmiowb(); 729 mmiowb();
730 } 730 }
731 731
732 732
733 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2) 733 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
734 { 734 {
735 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put; 735 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
736 sky2->rx_put = (sky2->rx_put + 1) % RX_LE_SIZE; 736 sky2->rx_put = (sky2->rx_put + 1) % RX_LE_SIZE;
737 return le; 737 return le;
738 } 738 }
739 739
740 /* Return high part of DMA address (could be 32 or 64 bit) */ 740 /* Return high part of DMA address (could be 32 or 64 bit) */
741 static inline u32 high32(dma_addr_t a) 741 static inline u32 high32(dma_addr_t a)
742 { 742 {
743 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0; 743 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
744 } 744 }
745 745
746 /* Build description to hardware about buffer */ 746 /* Build description to hardware about buffer */
747 static void sky2_rx_add(struct sky2_port *sky2, dma_addr_t map) 747 static void sky2_rx_add(struct sky2_port *sky2, dma_addr_t map)
748 { 748 {
749 struct sky2_rx_le *le; 749 struct sky2_rx_le *le;
750 u32 hi = high32(map); 750 u32 hi = high32(map);
751 u16 len = sky2->rx_bufsize; 751 u16 len = sky2->rx_bufsize;
752 752
753 if (sky2->rx_addr64 != hi) { 753 if (sky2->rx_addr64 != hi) {
754 le = sky2_next_rx(sky2); 754 le = sky2_next_rx(sky2);
755 le->addr = cpu_to_le32(hi); 755 le->addr = cpu_to_le32(hi);
756 le->ctrl = 0; 756 le->ctrl = 0;
757 le->opcode = OP_ADDR64 | HW_OWNER; 757 le->opcode = OP_ADDR64 | HW_OWNER;
758 sky2->rx_addr64 = high32(map + len); 758 sky2->rx_addr64 = high32(map + len);
759 } 759 }
760 760
761 le = sky2_next_rx(sky2); 761 le = sky2_next_rx(sky2);
762 le->addr = cpu_to_le32((u32) map); 762 le->addr = cpu_to_le32((u32) map);
763 le->length = cpu_to_le16(len); 763 le->length = cpu_to_le16(len);
764 le->ctrl = 0; 764 le->ctrl = 0;
765 le->opcode = OP_PACKET | HW_OWNER; 765 le->opcode = OP_PACKET | HW_OWNER;
766 } 766 }
767 767
768 768
769 /* Tell chip where to start receive checksum. 769 /* Tell chip where to start receive checksum.
770 * Actually has two checksums, but set both same to avoid possible byte 770 * Actually has two checksums, but set both same to avoid possible byte
771 * order problems. 771 * order problems.
772 */ 772 */
773 static void rx_set_checksum(struct sky2_port *sky2) 773 static void rx_set_checksum(struct sky2_port *sky2)
774 { 774 {
775 struct sky2_rx_le *le; 775 struct sky2_rx_le *le;
776 776
777 le = sky2_next_rx(sky2); 777 le = sky2_next_rx(sky2);
778 le->addr = (ETH_HLEN << 16) | ETH_HLEN; 778 le->addr = (ETH_HLEN << 16) | ETH_HLEN;
779 le->ctrl = 0; 779 le->ctrl = 0;
780 le->opcode = OP_TCPSTART | HW_OWNER; 780 le->opcode = OP_TCPSTART | HW_OWNER;
781 781
782 sky2_write32(sky2->hw, 782 sky2_write32(sky2->hw,
783 Q_ADDR(rxqaddr[sky2->port], Q_CSR), 783 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
784 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM); 784 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
785 785
786 } 786 }
787 787
788 /* 788 /*
789 * The RX Stop command will not work for Yukon-2 if the BMU does not 789 * The RX Stop command will not work for Yukon-2 if the BMU does not
790 * reach the end of packet and since we can't make sure that we have 790 * reach the end of packet and since we can't make sure that we have
791 * incoming data, we must reset the BMU while it is not doing a DMA 791 * incoming data, we must reset the BMU while it is not doing a DMA
792 * transfer. Since it is possible that the RX path is still active, 792 * transfer. Since it is possible that the RX path is still active,
793 * the RX RAM buffer will be stopped first, so any possible incoming 793 * the RX RAM buffer will be stopped first, so any possible incoming
794 * data will not trigger a DMA. After the RAM buffer is stopped, the 794 * data will not trigger a DMA. After the RAM buffer is stopped, the
795 * BMU is polled until any DMA in progress is ended and only then it 795 * BMU is polled until any DMA in progress is ended and only then it
796 * will be reset. 796 * will be reset.
797 */ 797 */
798 static void sky2_rx_stop(struct sky2_port *sky2) 798 static void sky2_rx_stop(struct sky2_port *sky2)
799 { 799 {
800 struct sky2_hw *hw = sky2->hw; 800 struct sky2_hw *hw = sky2->hw;
801 unsigned rxq = rxqaddr[sky2->port]; 801 unsigned rxq = rxqaddr[sky2->port];
802 int i; 802 int i;
803 803
804 /* disable the RAM Buffer receive queue */ 804 /* disable the RAM Buffer receive queue */
805 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD); 805 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
806 806
807 for (i = 0; i < 0xffff; i++) 807 for (i = 0; i < 0xffff; i++)
808 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL)) 808 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
809 == sky2_read8(hw, RB_ADDR(rxq, Q_RL))) 809 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
810 goto stopped; 810 goto stopped;
811 811
812 printk(KERN_WARNING PFX "%s: receiver stop failed\n", 812 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
813 sky2->netdev->name); 813 sky2->netdev->name);
814 stopped: 814 stopped:
815 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST); 815 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
816 816
817 /* reset the Rx prefetch unit */ 817 /* reset the Rx prefetch unit */
818 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET); 818 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
819 } 819 }
820 820
821 /* Clean out receive buffer area, assumes receiver hardware stopped */ 821 /* Clean out receive buffer area, assumes receiver hardware stopped */
822 static void sky2_rx_clean(struct sky2_port *sky2) 822 static void sky2_rx_clean(struct sky2_port *sky2)
823 { 823 {
824 unsigned i; 824 unsigned i;
825 825
826 memset(sky2->rx_le, 0, RX_LE_BYTES); 826 memset(sky2->rx_le, 0, RX_LE_BYTES);
827 for (i = 0; i < sky2->rx_pending; i++) { 827 for (i = 0; i < sky2->rx_pending; i++) {
828 struct ring_info *re = sky2->rx_ring + i; 828 struct ring_info *re = sky2->rx_ring + i;
829 829
830 if (re->skb) { 830 if (re->skb) {
831 pci_unmap_single(sky2->hw->pdev, 831 pci_unmap_single(sky2->hw->pdev,
832 re->mapaddr, sky2->rx_bufsize, 832 re->mapaddr, sky2->rx_bufsize,
833 PCI_DMA_FROMDEVICE); 833 PCI_DMA_FROMDEVICE);
834 kfree_skb(re->skb); 834 kfree_skb(re->skb);
835 re->skb = NULL; 835 re->skb = NULL;
836 } 836 }
837 } 837 }
838 } 838 }
839 839
840 /* Basic MII support */ 840 /* Basic MII support */
841 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 841 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
842 { 842 {
843 struct mii_ioctl_data *data = if_mii(ifr); 843 struct mii_ioctl_data *data = if_mii(ifr);
844 struct sky2_port *sky2 = netdev_priv(dev); 844 struct sky2_port *sky2 = netdev_priv(dev);
845 struct sky2_hw *hw = sky2->hw; 845 struct sky2_hw *hw = sky2->hw;
846 int err = -EOPNOTSUPP; 846 int err = -EOPNOTSUPP;
847 847
848 if (!netif_running(dev)) 848 if (!netif_running(dev))
849 return -ENODEV; /* Phy still in reset */ 849 return -ENODEV; /* Phy still in reset */
850 850
851 switch(cmd) { 851 switch(cmd) {
852 case SIOCGMIIPHY: 852 case SIOCGMIIPHY:
853 data->phy_id = PHY_ADDR_MARV; 853 data->phy_id = PHY_ADDR_MARV;
854 854
855 /* fallthru */ 855 /* fallthru */
856 case SIOCGMIIREG: { 856 case SIOCGMIIREG: {
857 u16 val = 0; 857 u16 val = 0;
858 858
859 down(&sky2->phy_sema); 859 spin_lock_bh(&sky2->phy_lock);
860 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val); 860 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
861 up(&sky2->phy_sema); 861 spin_unlock_bh(&sky2->phy_lock);
862 862
863 data->val_out = val; 863 data->val_out = val;
864 break; 864 break;
865 } 865 }
866 866
867 case SIOCSMIIREG: 867 case SIOCSMIIREG:
868 if (!capable(CAP_NET_ADMIN)) 868 if (!capable(CAP_NET_ADMIN))
869 return -EPERM; 869 return -EPERM;
870 870
871 down(&sky2->phy_sema); 871 spin_lock_bh(&sky2->phy_lock);
872 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f, 872 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
873 data->val_in); 873 data->val_in);
874 up(&sky2->phy_sema); 874 spin_unlock_bh(&sky2->phy_lock);
875 break; 875 break;
876 } 876 }
877 return err; 877 return err;
878 } 878 }
879 879
880 #ifdef SKY2_VLAN_TAG_USED 880 #ifdef SKY2_VLAN_TAG_USED
881 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp) 881 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
882 { 882 {
883 struct sky2_port *sky2 = netdev_priv(dev); 883 struct sky2_port *sky2 = netdev_priv(dev);
884 struct sky2_hw *hw = sky2->hw; 884 struct sky2_hw *hw = sky2->hw;
885 u16 port = sky2->port; 885 u16 port = sky2->port;
886 886
887 spin_lock_bh(&sky2->tx_lock); 887 spin_lock_bh(&sky2->tx_lock);
888 888
889 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON); 889 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
890 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON); 890 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
891 sky2->vlgrp = grp; 891 sky2->vlgrp = grp;
892 892
893 spin_unlock_bh(&sky2->tx_lock); 893 spin_unlock_bh(&sky2->tx_lock);
894 } 894 }
895 895
896 static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid) 896 static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
897 { 897 {
898 struct sky2_port *sky2 = netdev_priv(dev); 898 struct sky2_port *sky2 = netdev_priv(dev);
899 struct sky2_hw *hw = sky2->hw; 899 struct sky2_hw *hw = sky2->hw;
900 u16 port = sky2->port; 900 u16 port = sky2->port;
901 901
902 spin_lock_bh(&sky2->tx_lock); 902 spin_lock_bh(&sky2->tx_lock);
903 903
904 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF); 904 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
905 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF); 905 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
906 if (sky2->vlgrp) 906 if (sky2->vlgrp)
907 sky2->vlgrp->vlan_devices[vid] = NULL; 907 sky2->vlgrp->vlan_devices[vid] = NULL;
908 908
909 spin_unlock_bh(&sky2->tx_lock); 909 spin_unlock_bh(&sky2->tx_lock);
910 } 910 }
911 #endif 911 #endif
912 912
913 /* 913 /*
914 * It appears the hardware has a bug in the FIFO logic that 914 * It appears the hardware has a bug in the FIFO logic that
915 * cause it to hang if the FIFO gets overrun and the receive buffer 915 * cause it to hang if the FIFO gets overrun and the receive buffer
916 * is not aligned. ALso alloc_skb() won't align properly if slab 916 * is not aligned. ALso alloc_skb() won't align properly if slab
917 * debugging is enabled. 917 * debugging is enabled.
918 */ 918 */
919 static inline struct sk_buff *sky2_alloc_skb(unsigned int size, gfp_t gfp_mask) 919 static inline struct sk_buff *sky2_alloc_skb(unsigned int size, gfp_t gfp_mask)
920 { 920 {
921 struct sk_buff *skb; 921 struct sk_buff *skb;
922 922
923 skb = alloc_skb(size + RX_SKB_ALIGN, gfp_mask); 923 skb = alloc_skb(size + RX_SKB_ALIGN, gfp_mask);
924 if (likely(skb)) { 924 if (likely(skb)) {
925 unsigned long p = (unsigned long) skb->data; 925 unsigned long p = (unsigned long) skb->data;
926 skb_reserve(skb, 926 skb_reserve(skb,
927 ((p + RX_SKB_ALIGN - 1) & ~(RX_SKB_ALIGN - 1)) - p); 927 ((p + RX_SKB_ALIGN - 1) & ~(RX_SKB_ALIGN - 1)) - p);
928 } 928 }
929 929
930 return skb; 930 return skb;
931 } 931 }
932 932
933 /* 933 /*
934 * Allocate and setup receiver buffer pool. 934 * Allocate and setup receiver buffer pool.
935 * In case of 64 bit dma, there are 2X as many list elements 935 * In case of 64 bit dma, there are 2X as many list elements
936 * available as ring entries 936 * available as ring entries
937 * and need to reserve one list element so we don't wrap around. 937 * and need to reserve one list element so we don't wrap around.
938 */ 938 */
939 static int sky2_rx_start(struct sky2_port *sky2) 939 static int sky2_rx_start(struct sky2_port *sky2)
940 { 940 {
941 struct sky2_hw *hw = sky2->hw; 941 struct sky2_hw *hw = sky2->hw;
942 unsigned rxq = rxqaddr[sky2->port]; 942 unsigned rxq = rxqaddr[sky2->port];
943 int i; 943 int i;
944 944
945 sky2->rx_put = sky2->rx_next = 0; 945 sky2->rx_put = sky2->rx_next = 0;
946 sky2_qset(hw, rxq); 946 sky2_qset(hw, rxq);
947 947
948 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) { 948 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
949 /* MAC Rx RAM Read is controlled by hardware */ 949 /* MAC Rx RAM Read is controlled by hardware */
950 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS); 950 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
951 } 951 }
952 952
953 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1); 953 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
954 954
955 rx_set_checksum(sky2); 955 rx_set_checksum(sky2);
956 for (i = 0; i < sky2->rx_pending; i++) { 956 for (i = 0; i < sky2->rx_pending; i++) {
957 struct ring_info *re = sky2->rx_ring + i; 957 struct ring_info *re = sky2->rx_ring + i;
958 958
959 re->skb = sky2_alloc_skb(sky2->rx_bufsize, GFP_KERNEL); 959 re->skb = sky2_alloc_skb(sky2->rx_bufsize, GFP_KERNEL);
960 if (!re->skb) 960 if (!re->skb)
961 goto nomem; 961 goto nomem;
962 962
963 re->mapaddr = pci_map_single(hw->pdev, re->skb->data, 963 re->mapaddr = pci_map_single(hw->pdev, re->skb->data,
964 sky2->rx_bufsize, PCI_DMA_FROMDEVICE); 964 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
965 sky2_rx_add(sky2, re->mapaddr); 965 sky2_rx_add(sky2, re->mapaddr);
966 } 966 }
967 967
968 /* Truncate oversize frames */ 968 /* Truncate oversize frames */
969 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), sky2->rx_bufsize - 8); 969 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), sky2->rx_bufsize - 8);
970 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON); 970 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
971 971
972 /* Tell chip about available buffers */ 972 /* Tell chip about available buffers */
973 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put); 973 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
974 return 0; 974 return 0;
975 nomem: 975 nomem:
976 sky2_rx_clean(sky2); 976 sky2_rx_clean(sky2);
977 return -ENOMEM; 977 return -ENOMEM;
978 } 978 }
979 979
980 /* Bring up network interface. */ 980 /* Bring up network interface. */
981 static int sky2_up(struct net_device *dev) 981 static int sky2_up(struct net_device *dev)
982 { 982 {
983 struct sky2_port *sky2 = netdev_priv(dev); 983 struct sky2_port *sky2 = netdev_priv(dev);
984 struct sky2_hw *hw = sky2->hw; 984 struct sky2_hw *hw = sky2->hw;
985 unsigned port = sky2->port; 985 unsigned port = sky2->port;
986 u32 ramsize, rxspace; 986 u32 ramsize, rxspace, imask;
987 int err = -ENOMEM; 987 int err = -ENOMEM;
988 988
989 if (netif_msg_ifup(sky2)) 989 if (netif_msg_ifup(sky2))
990 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name); 990 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
991 991
992 /* must be power of 2 */ 992 /* must be power of 2 */
993 sky2->tx_le = pci_alloc_consistent(hw->pdev, 993 sky2->tx_le = pci_alloc_consistent(hw->pdev,
994 TX_RING_SIZE * 994 TX_RING_SIZE *
995 sizeof(struct sky2_tx_le), 995 sizeof(struct sky2_tx_le),
996 &sky2->tx_le_map); 996 &sky2->tx_le_map);
997 if (!sky2->tx_le) 997 if (!sky2->tx_le)
998 goto err_out; 998 goto err_out;
999 999
1000 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info), 1000 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
1001 GFP_KERNEL); 1001 GFP_KERNEL);
1002 if (!sky2->tx_ring) 1002 if (!sky2->tx_ring)
1003 goto err_out; 1003 goto err_out;
1004 sky2->tx_prod = sky2->tx_cons = 0; 1004 sky2->tx_prod = sky2->tx_cons = 0;
1005 1005
1006 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES, 1006 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1007 &sky2->rx_le_map); 1007 &sky2->rx_le_map);
1008 if (!sky2->rx_le) 1008 if (!sky2->rx_le)
1009 goto err_out; 1009 goto err_out;
1010 memset(sky2->rx_le, 0, RX_LE_BYTES); 1010 memset(sky2->rx_le, 0, RX_LE_BYTES);
1011 1011
1012 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct ring_info), 1012 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct ring_info),
1013 GFP_KERNEL); 1013 GFP_KERNEL);
1014 if (!sky2->rx_ring) 1014 if (!sky2->rx_ring)
1015 goto err_out; 1015 goto err_out;
1016 1016
1017 sky2_mac_init(hw, port); 1017 sky2_mac_init(hw, port);
1018 1018
1019 /* Determine available ram buffer space (in 4K blocks). 1019 /* Determine available ram buffer space (in 4K blocks).
1020 * Note: not sure about the FE setting below yet 1020 * Note: not sure about the FE setting below yet
1021 */ 1021 */
1022 if (hw->chip_id == CHIP_ID_YUKON_FE) 1022 if (hw->chip_id == CHIP_ID_YUKON_FE)
1023 ramsize = 4; 1023 ramsize = 4;
1024 else 1024 else
1025 ramsize = sky2_read8(hw, B2_E_0); 1025 ramsize = sky2_read8(hw, B2_E_0);
1026 1026
1027 /* Give transmitter one third (rounded up) */ 1027 /* Give transmitter one third (rounded up) */
1028 rxspace = ramsize - (ramsize + 2) / 3; 1028 rxspace = ramsize - (ramsize + 2) / 3;
1029 1029
1030 sky2_ramset(hw, rxqaddr[port], 0, rxspace); 1030 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1031 sky2_ramset(hw, txqaddr[port], rxspace, ramsize); 1031 sky2_ramset(hw, txqaddr[port], rxspace, ramsize);
1032 1032
1033 /* Make sure SyncQ is disabled */ 1033 /* Make sure SyncQ is disabled */
1034 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL), 1034 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1035 RB_RST_SET); 1035 RB_RST_SET);
1036 1036
1037 sky2_qset(hw, txqaddr[port]); 1037 sky2_qset(hw, txqaddr[port]);
1038 1038
1039 /* Set almost empty threshold */ 1039 /* Set almost empty threshold */
1040 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == 1) 1040 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == 1)
1041 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0); 1041 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
1042 1042
1043 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map, 1043 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1044 TX_RING_SIZE - 1); 1044 TX_RING_SIZE - 1);
1045 1045
1046 err = sky2_rx_start(sky2); 1046 err = sky2_rx_start(sky2);
1047 if (err) 1047 if (err)
1048 goto err_out; 1048 goto err_out;
1049 1049
1050 /* Enable interrupts from phy/mac for port */ 1050 /* Enable interrupts from phy/mac for port */
1051 spin_lock_irq(&hw->hw_lock); 1051 imask = sky2_read32(hw, B0_IMSK);
1052 hw->intr_mask |= (port == 0) ? Y2_IS_PORT_1 : Y2_IS_PORT_2; 1052 imask |= (port == 0) ? Y2_IS_PORT_1 : Y2_IS_PORT_2;
1053 sky2_write32(hw, B0_IMSK, hw->intr_mask); 1053 sky2_write32(hw, B0_IMSK, imask);
1054 spin_unlock_irq(&hw->hw_lock); 1054
1055 return 0; 1055 return 0;
1056 1056
1057 err_out: 1057 err_out:
1058 if (sky2->rx_le) { 1058 if (sky2->rx_le) {
1059 pci_free_consistent(hw->pdev, RX_LE_BYTES, 1059 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1060 sky2->rx_le, sky2->rx_le_map); 1060 sky2->rx_le, sky2->rx_le_map);
1061 sky2->rx_le = NULL; 1061 sky2->rx_le = NULL;
1062 } 1062 }
1063 if (sky2->tx_le) { 1063 if (sky2->tx_le) {
1064 pci_free_consistent(hw->pdev, 1064 pci_free_consistent(hw->pdev,
1065 TX_RING_SIZE * sizeof(struct sky2_tx_le), 1065 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1066 sky2->tx_le, sky2->tx_le_map); 1066 sky2->tx_le, sky2->tx_le_map);
1067 sky2->tx_le = NULL; 1067 sky2->tx_le = NULL;
1068 } 1068 }
1069 kfree(sky2->tx_ring); 1069 kfree(sky2->tx_ring);
1070 kfree(sky2->rx_ring); 1070 kfree(sky2->rx_ring);
1071 1071
1072 sky2->tx_ring = NULL; 1072 sky2->tx_ring = NULL;
1073 sky2->rx_ring = NULL; 1073 sky2->rx_ring = NULL;
1074 return err; 1074 return err;
1075 } 1075 }
1076 1076
1077 /* Modular subtraction in ring */ 1077 /* Modular subtraction in ring */
1078 static inline int tx_dist(unsigned tail, unsigned head) 1078 static inline int tx_dist(unsigned tail, unsigned head)
1079 { 1079 {
1080 return (head - tail) % TX_RING_SIZE; 1080 return (head - tail) % TX_RING_SIZE;
1081 } 1081 }
1082 1082
1083 /* Number of list elements available for next tx */ 1083 /* Number of list elements available for next tx */
1084 static inline int tx_avail(const struct sky2_port *sky2) 1084 static inline int tx_avail(const struct sky2_port *sky2)
1085 { 1085 {
1086 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod); 1086 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1087 } 1087 }
1088 1088
1089 /* Estimate of number of transmit list elements required */ 1089 /* Estimate of number of transmit list elements required */
1090 static unsigned tx_le_req(const struct sk_buff *skb) 1090 static unsigned tx_le_req(const struct sk_buff *skb)
1091 { 1091 {
1092 unsigned count; 1092 unsigned count;
1093 1093
1094 count = sizeof(dma_addr_t) / sizeof(u32); 1094 count = sizeof(dma_addr_t) / sizeof(u32);
1095 count += skb_shinfo(skb)->nr_frags * count; 1095 count += skb_shinfo(skb)->nr_frags * count;
1096 1096
1097 if (skb_shinfo(skb)->tso_size) 1097 if (skb_shinfo(skb)->tso_size)
1098 ++count; 1098 ++count;
1099 1099
1100 if (skb->ip_summed == CHECKSUM_HW) 1100 if (skb->ip_summed == CHECKSUM_HW)
1101 ++count; 1101 ++count;
1102 1102
1103 return count; 1103 return count;
1104 } 1104 }
1105 1105
1106 /* 1106 /*
1107 * Put one packet in ring for transmit. 1107 * Put one packet in ring for transmit.
1108 * A single packet can generate multiple list elements, and 1108 * A single packet can generate multiple list elements, and
1109 * the number of ring elements will probably be less than the number 1109 * the number of ring elements will probably be less than the number
1110 * of list elements used. 1110 * of list elements used.
1111 * 1111 *
1112 * No BH disabling for tx_lock here (like tg3) 1112 * No BH disabling for tx_lock here (like tg3)
1113 */ 1113 */
1114 static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev) 1114 static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1115 { 1115 {
1116 struct sky2_port *sky2 = netdev_priv(dev); 1116 struct sky2_port *sky2 = netdev_priv(dev);
1117 struct sky2_hw *hw = sky2->hw; 1117 struct sky2_hw *hw = sky2->hw;
1118 struct sky2_tx_le *le = NULL; 1118 struct sky2_tx_le *le = NULL;
1119 struct tx_ring_info *re; 1119 struct tx_ring_info *re;
1120 unsigned i, len; 1120 unsigned i, len;
1121 int avail; 1121 int avail;
1122 dma_addr_t mapping; 1122 dma_addr_t mapping;
1123 u32 addr64; 1123 u32 addr64;
1124 u16 mss; 1124 u16 mss;
1125 u8 ctrl; 1125 u8 ctrl;
1126 1126
1127 /* No BH disabling for tx_lock here. We are running in BH disabled 1127 /* No BH disabling for tx_lock here. We are running in BH disabled
1128 * context and TX reclaim runs via poll inside of a software 1128 * context and TX reclaim runs via poll inside of a software
1129 * interrupt, and no related locks in IRQ processing. 1129 * interrupt, and no related locks in IRQ processing.
1130 */ 1130 */
1131 if (!spin_trylock(&sky2->tx_lock)) 1131 if (!spin_trylock(&sky2->tx_lock))
1132 return NETDEV_TX_LOCKED; 1132 return NETDEV_TX_LOCKED;
1133 1133
1134 if (unlikely(tx_avail(sky2) < tx_le_req(skb))) { 1134 if (unlikely(tx_avail(sky2) < tx_le_req(skb))) {
1135 /* There is a known but harmless race with lockless tx 1135 /* There is a known but harmless race with lockless tx
1136 * and netif_stop_queue. 1136 * and netif_stop_queue.
1137 */ 1137 */
1138 if (!netif_queue_stopped(dev)) { 1138 if (!netif_queue_stopped(dev)) {
1139 netif_stop_queue(dev); 1139 netif_stop_queue(dev);
1140 if (net_ratelimit()) 1140 if (net_ratelimit())
1141 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n", 1141 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
1142 dev->name); 1142 dev->name);
1143 } 1143 }
1144 spin_unlock(&sky2->tx_lock); 1144 spin_unlock(&sky2->tx_lock);
1145 1145
1146 return NETDEV_TX_BUSY; 1146 return NETDEV_TX_BUSY;
1147 } 1147 }
1148 1148
1149 if (unlikely(netif_msg_tx_queued(sky2))) 1149 if (unlikely(netif_msg_tx_queued(sky2)))
1150 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n", 1150 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1151 dev->name, sky2->tx_prod, skb->len); 1151 dev->name, sky2->tx_prod, skb->len);
1152 1152
1153 len = skb_headlen(skb); 1153 len = skb_headlen(skb);
1154 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE); 1154 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1155 addr64 = high32(mapping); 1155 addr64 = high32(mapping);
1156 1156
1157 re = sky2->tx_ring + sky2->tx_prod; 1157 re = sky2->tx_ring + sky2->tx_prod;
1158 1158
1159 /* Send high bits if changed or crosses boundary */ 1159 /* Send high bits if changed or crosses boundary */
1160 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) { 1160 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
1161 le = get_tx_le(sky2); 1161 le = get_tx_le(sky2);
1162 le->tx.addr = cpu_to_le32(addr64); 1162 le->tx.addr = cpu_to_le32(addr64);
1163 le->ctrl = 0; 1163 le->ctrl = 0;
1164 le->opcode = OP_ADDR64 | HW_OWNER; 1164 le->opcode = OP_ADDR64 | HW_OWNER;
1165 sky2->tx_addr64 = high32(mapping + len); 1165 sky2->tx_addr64 = high32(mapping + len);
1166 } 1166 }
1167 1167
1168 /* Check for TCP Segmentation Offload */ 1168 /* Check for TCP Segmentation Offload */
1169 mss = skb_shinfo(skb)->tso_size; 1169 mss = skb_shinfo(skb)->tso_size;
1170 if (mss != 0) { 1170 if (mss != 0) {
1171 /* just drop the packet if non-linear expansion fails */ 1171 /* just drop the packet if non-linear expansion fails */
1172 if (skb_header_cloned(skb) && 1172 if (skb_header_cloned(skb) &&
1173 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) { 1173 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
1174 dev_kfree_skb_any(skb); 1174 dev_kfree_skb_any(skb);
1175 goto out_unlock; 1175 goto out_unlock;
1176 } 1176 }
1177 1177
1178 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */ 1178 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1179 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr); 1179 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1180 mss += ETH_HLEN; 1180 mss += ETH_HLEN;
1181 } 1181 }
1182 1182
1183 if (mss != sky2->tx_last_mss) { 1183 if (mss != sky2->tx_last_mss) {
1184 le = get_tx_le(sky2); 1184 le = get_tx_le(sky2);
1185 le->tx.tso.size = cpu_to_le16(mss); 1185 le->tx.tso.size = cpu_to_le16(mss);
1186 le->tx.tso.rsvd = 0; 1186 le->tx.tso.rsvd = 0;
1187 le->opcode = OP_LRGLEN | HW_OWNER; 1187 le->opcode = OP_LRGLEN | HW_OWNER;
1188 le->ctrl = 0; 1188 le->ctrl = 0;
1189 sky2->tx_last_mss = mss; 1189 sky2->tx_last_mss = mss;
1190 } 1190 }
1191 1191
1192 ctrl = 0; 1192 ctrl = 0;
1193 #ifdef SKY2_VLAN_TAG_USED 1193 #ifdef SKY2_VLAN_TAG_USED
1194 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */ 1194 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1195 if (sky2->vlgrp && vlan_tx_tag_present(skb)) { 1195 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1196 if (!le) { 1196 if (!le) {
1197 le = get_tx_le(sky2); 1197 le = get_tx_le(sky2);
1198 le->tx.addr = 0; 1198 le->tx.addr = 0;
1199 le->opcode = OP_VLAN|HW_OWNER; 1199 le->opcode = OP_VLAN|HW_OWNER;
1200 le->ctrl = 0; 1200 le->ctrl = 0;
1201 } else 1201 } else
1202 le->opcode |= OP_VLAN; 1202 le->opcode |= OP_VLAN;
1203 le->length = cpu_to_be16(vlan_tx_tag_get(skb)); 1203 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1204 ctrl |= INS_VLAN; 1204 ctrl |= INS_VLAN;
1205 } 1205 }
1206 #endif 1206 #endif
1207 1207
1208 /* Handle TCP checksum offload */ 1208 /* Handle TCP checksum offload */
1209 if (skb->ip_summed == CHECKSUM_HW) { 1209 if (skb->ip_summed == CHECKSUM_HW) {
1210 u16 hdr = skb->h.raw - skb->data; 1210 u16 hdr = skb->h.raw - skb->data;
1211 u16 offset = hdr + skb->csum; 1211 u16 offset = hdr + skb->csum;
1212 1212
1213 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM; 1213 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1214 if (skb->nh.iph->protocol == IPPROTO_UDP) 1214 if (skb->nh.iph->protocol == IPPROTO_UDP)
1215 ctrl |= UDPTCP; 1215 ctrl |= UDPTCP;
1216 1216
1217 le = get_tx_le(sky2); 1217 le = get_tx_le(sky2);
1218 le->tx.csum.start = cpu_to_le16(hdr); 1218 le->tx.csum.start = cpu_to_le16(hdr);
1219 le->tx.csum.offset = cpu_to_le16(offset); 1219 le->tx.csum.offset = cpu_to_le16(offset);
1220 le->length = 0; /* initial checksum value */ 1220 le->length = 0; /* initial checksum value */
1221 le->ctrl = 1; /* one packet */ 1221 le->ctrl = 1; /* one packet */
1222 le->opcode = OP_TCPLISW | HW_OWNER; 1222 le->opcode = OP_TCPLISW | HW_OWNER;
1223 } 1223 }
1224 1224
1225 le = get_tx_le(sky2); 1225 le = get_tx_le(sky2);
1226 le->tx.addr = cpu_to_le32((u32) mapping); 1226 le->tx.addr = cpu_to_le32((u32) mapping);
1227 le->length = cpu_to_le16(len); 1227 le->length = cpu_to_le16(len);
1228 le->ctrl = ctrl; 1228 le->ctrl = ctrl;
1229 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER); 1229 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1230 1230
1231 /* Record the transmit mapping info */ 1231 /* Record the transmit mapping info */
1232 re->skb = skb; 1232 re->skb = skb;
1233 pci_unmap_addr_set(re, mapaddr, mapping); 1233 pci_unmap_addr_set(re, mapaddr, mapping);
1234 1234
1235 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1235 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1236 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1236 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1237 struct tx_ring_info *fre; 1237 struct tx_ring_info *fre;
1238 1238
1239 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset, 1239 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1240 frag->size, PCI_DMA_TODEVICE); 1240 frag->size, PCI_DMA_TODEVICE);
1241 addr64 = high32(mapping); 1241 addr64 = high32(mapping);
1242 if (addr64 != sky2->tx_addr64) { 1242 if (addr64 != sky2->tx_addr64) {
1243 le = get_tx_le(sky2); 1243 le = get_tx_le(sky2);
1244 le->tx.addr = cpu_to_le32(addr64); 1244 le->tx.addr = cpu_to_le32(addr64);
1245 le->ctrl = 0; 1245 le->ctrl = 0;
1246 le->opcode = OP_ADDR64 | HW_OWNER; 1246 le->opcode = OP_ADDR64 | HW_OWNER;
1247 sky2->tx_addr64 = addr64; 1247 sky2->tx_addr64 = addr64;
1248 } 1248 }
1249 1249
1250 le = get_tx_le(sky2); 1250 le = get_tx_le(sky2);
1251 le->tx.addr = cpu_to_le32((u32) mapping); 1251 le->tx.addr = cpu_to_le32((u32) mapping);
1252 le->length = cpu_to_le16(frag->size); 1252 le->length = cpu_to_le16(frag->size);
1253 le->ctrl = ctrl; 1253 le->ctrl = ctrl;
1254 le->opcode = OP_BUFFER | HW_OWNER; 1254 le->opcode = OP_BUFFER | HW_OWNER;
1255 1255
1256 fre = sky2->tx_ring 1256 fre = sky2->tx_ring
1257 + ((re - sky2->tx_ring) + i + 1) % TX_RING_SIZE; 1257 + ((re - sky2->tx_ring) + i + 1) % TX_RING_SIZE;
1258 pci_unmap_addr_set(fre, mapaddr, mapping); 1258 pci_unmap_addr_set(fre, mapaddr, mapping);
1259 } 1259 }
1260 1260
1261 re->idx = sky2->tx_prod; 1261 re->idx = sky2->tx_prod;
1262 le->ctrl |= EOP; 1262 le->ctrl |= EOP;
1263 1263
1264 avail = tx_avail(sky2); 1264 avail = tx_avail(sky2);
1265 if (mss != 0 || avail < TX_MIN_PENDING) { 1265 if (mss != 0 || avail < TX_MIN_PENDING) {
1266 le->ctrl |= FRC_STAT; 1266 le->ctrl |= FRC_STAT;
1267 if (avail <= MAX_SKB_TX_LE) 1267 if (avail <= MAX_SKB_TX_LE)
1268 netif_stop_queue(dev); 1268 netif_stop_queue(dev);
1269 } 1269 }
1270 1270
1271 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod); 1271 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1272 1272
1273 out_unlock: 1273 out_unlock:
1274 spin_unlock(&sky2->tx_lock); 1274 spin_unlock(&sky2->tx_lock);
1275 1275
1276 dev->trans_start = jiffies; 1276 dev->trans_start = jiffies;
1277 return NETDEV_TX_OK; 1277 return NETDEV_TX_OK;
1278 } 1278 }
1279 1279
1280 /* 1280 /*
1281 * Free ring elements from starting at tx_cons until "done" 1281 * Free ring elements from starting at tx_cons until "done"
1282 * 1282 *
1283 * NB: the hardware will tell us about partial completion of multi-part 1283 * NB: the hardware will tell us about partial completion of multi-part
1284 * buffers; these are deferred until completion. 1284 * buffers; these are deferred until completion.
1285 */ 1285 */
1286 static void sky2_tx_complete(struct sky2_port *sky2, u16 done) 1286 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1287 { 1287 {
1288 struct net_device *dev = sky2->netdev; 1288 struct net_device *dev = sky2->netdev;
1289 struct pci_dev *pdev = sky2->hw->pdev; 1289 struct pci_dev *pdev = sky2->hw->pdev;
1290 u16 nxt, put; 1290 u16 nxt, put;
1291 unsigned i; 1291 unsigned i;
1292 1292
1293 BUG_ON(done >= TX_RING_SIZE); 1293 BUG_ON(done >= TX_RING_SIZE);
1294 1294
1295 if (unlikely(netif_msg_tx_done(sky2))) 1295 if (unlikely(netif_msg_tx_done(sky2)))
1296 printk(KERN_DEBUG "%s: tx done, up to %u\n", 1296 printk(KERN_DEBUG "%s: tx done, up to %u\n",
1297 dev->name, done); 1297 dev->name, done);
1298 1298
1299 for (put = sky2->tx_cons; put != done; put = nxt) { 1299 for (put = sky2->tx_cons; put != done; put = nxt) {
1300 struct tx_ring_info *re = sky2->tx_ring + put; 1300 struct tx_ring_info *re = sky2->tx_ring + put;
1301 struct sk_buff *skb = re->skb; 1301 struct sk_buff *skb = re->skb;
1302 1302
1303 nxt = re->idx; 1303 nxt = re->idx;
1304 BUG_ON(nxt >= TX_RING_SIZE); 1304 BUG_ON(nxt >= TX_RING_SIZE);
1305 prefetch(sky2->tx_ring + nxt); 1305 prefetch(sky2->tx_ring + nxt);
1306 1306
1307 /* Check for partial status */ 1307 /* Check for partial status */
1308 if (tx_dist(put, done) < tx_dist(put, nxt)) 1308 if (tx_dist(put, done) < tx_dist(put, nxt))
1309 break; 1309 break;
1310 1310
1311 skb = re->skb; 1311 skb = re->skb;
1312 pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr), 1312 pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
1313 skb_headlen(skb), PCI_DMA_TODEVICE); 1313 skb_headlen(skb), PCI_DMA_TODEVICE);
1314 1314
1315 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1315 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1316 struct tx_ring_info *fre; 1316 struct tx_ring_info *fre;
1317 fre = sky2->tx_ring + (put + i + 1) % TX_RING_SIZE; 1317 fre = sky2->tx_ring + (put + i + 1) % TX_RING_SIZE;
1318 pci_unmap_page(pdev, pci_unmap_addr(fre, mapaddr), 1318 pci_unmap_page(pdev, pci_unmap_addr(fre, mapaddr),
1319 skb_shinfo(skb)->frags[i].size, 1319 skb_shinfo(skb)->frags[i].size,
1320 PCI_DMA_TODEVICE); 1320 PCI_DMA_TODEVICE);
1321 } 1321 }
1322 1322
1323 dev_kfree_skb_any(skb); 1323 dev_kfree_skb_any(skb);
1324 } 1324 }
1325 1325
1326 sky2->tx_cons = put; 1326 sky2->tx_cons = put;
1327 if (netif_queue_stopped(dev) && tx_avail(sky2) > MAX_SKB_TX_LE) 1327 if (netif_queue_stopped(dev) && tx_avail(sky2) > MAX_SKB_TX_LE)
1328 netif_wake_queue(dev); 1328 netif_wake_queue(dev);
1329 } 1329 }
1330 1330
1331 /* Cleanup all untransmitted buffers, assume transmitter not running */ 1331 /* Cleanup all untransmitted buffers, assume transmitter not running */
1332 static void sky2_tx_clean(struct sky2_port *sky2) 1332 static void sky2_tx_clean(struct sky2_port *sky2)
1333 { 1333 {
1334 spin_lock_bh(&sky2->tx_lock); 1334 spin_lock_bh(&sky2->tx_lock);
1335 sky2_tx_complete(sky2, sky2->tx_prod); 1335 sky2_tx_complete(sky2, sky2->tx_prod);
1336 spin_unlock_bh(&sky2->tx_lock); 1336 spin_unlock_bh(&sky2->tx_lock);
1337 } 1337 }
1338 1338
1339 /* Network shutdown */ 1339 /* Network shutdown */
1340 static int sky2_down(struct net_device *dev) 1340 static int sky2_down(struct net_device *dev)
1341 { 1341 {
1342 struct sky2_port *sky2 = netdev_priv(dev); 1342 struct sky2_port *sky2 = netdev_priv(dev);
1343 struct sky2_hw *hw = sky2->hw; 1343 struct sky2_hw *hw = sky2->hw;
1344 unsigned port = sky2->port; 1344 unsigned port = sky2->port;
1345 u16 ctrl; 1345 u16 ctrl;
1346 u32 imask;
1346 1347
1347 /* Never really got started! */ 1348 /* Never really got started! */
1348 if (!sky2->tx_le) 1349 if (!sky2->tx_le)
1349 return 0; 1350 return 0;
1350 1351
1351 if (netif_msg_ifdown(sky2)) 1352 if (netif_msg_ifdown(sky2))
1352 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name); 1353 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1353 1354
1354 /* Stop more packets from being queued */ 1355 /* Stop more packets from being queued */
1355 netif_stop_queue(dev); 1356 netif_stop_queue(dev);
1356 1357
1357 /* Disable port IRQ */
1358 spin_lock_irq(&hw->hw_lock);
1359 hw->intr_mask &= ~((sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);
1360 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1361 spin_unlock_irq(&hw->hw_lock);
1362
1363 flush_scheduled_work();
1364
1365 sky2_phy_reset(hw, port); 1358 sky2_phy_reset(hw, port);
1366 1359
1367 /* Stop transmitter */ 1360 /* Stop transmitter */
1368 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP); 1361 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1369 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR)); 1362 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1370 1363
1371 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), 1364 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1372 RB_RST_SET | RB_DIS_OP_MD); 1365 RB_RST_SET | RB_DIS_OP_MD);
1373 1366
1374 ctrl = gma_read16(hw, port, GM_GP_CTRL); 1367 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1375 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA); 1368 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1376 gma_write16(hw, port, GM_GP_CTRL, ctrl); 1369 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1377 1370
1378 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); 1371 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1379 1372
1380 /* Workaround shared GMAC reset */ 1373 /* Workaround shared GMAC reset */
1381 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 1374 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1382 && port == 0 && hw->dev[1] && netif_running(hw->dev[1]))) 1375 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1383 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET); 1376 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1384 1377
1385 /* Disable Force Sync bit and Enable Alloc bit */ 1378 /* Disable Force Sync bit and Enable Alloc bit */
1386 sky2_write8(hw, SK_REG(port, TXA_CTRL), 1379 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1387 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); 1380 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1388 1381
1389 /* Stop Interval Timer and Limit Counter of Tx Arbiter */ 1382 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1390 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L); 1383 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1391 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L); 1384 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1392 1385
1393 /* Reset the PCI FIFO of the async Tx queue */ 1386 /* Reset the PCI FIFO of the async Tx queue */
1394 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), 1387 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1395 BMU_RST_SET | BMU_FIFO_RST); 1388 BMU_RST_SET | BMU_FIFO_RST);
1396 1389
1397 /* Reset the Tx prefetch units */ 1390 /* Reset the Tx prefetch units */
1398 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL), 1391 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1399 PREF_UNIT_RST_SET); 1392 PREF_UNIT_RST_SET);
1400 1393
1401 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET); 1394 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1402 1395
1403 sky2_rx_stop(sky2); 1396 sky2_rx_stop(sky2);
1404 1397
1405 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); 1398 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1406 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET); 1399 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1407 1400
1401 /* Disable port IRQ */
1402 imask = sky2_read32(hw, B0_IMSK);
1403 imask &= ~(sky2->port == 0) ? Y2_IS_PORT_1 : Y2_IS_PORT_2;
1404 sky2_write32(hw, B0_IMSK, imask);
1405
1408 /* turn off LED's */ 1406 /* turn off LED's */
1409 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF); 1407 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1410 1408
1411 synchronize_irq(hw->pdev->irq); 1409 synchronize_irq(hw->pdev->irq);
1412 1410
1413 sky2_tx_clean(sky2); 1411 sky2_tx_clean(sky2);
1414 sky2_rx_clean(sky2); 1412 sky2_rx_clean(sky2);
1415 1413
1416 pci_free_consistent(hw->pdev, RX_LE_BYTES, 1414 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1417 sky2->rx_le, sky2->rx_le_map); 1415 sky2->rx_le, sky2->rx_le_map);
1418 kfree(sky2->rx_ring); 1416 kfree(sky2->rx_ring);
1419 1417
1420 pci_free_consistent(hw->pdev, 1418 pci_free_consistent(hw->pdev,
1421 TX_RING_SIZE * sizeof(struct sky2_tx_le), 1419 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1422 sky2->tx_le, sky2->tx_le_map); 1420 sky2->tx_le, sky2->tx_le_map);
1423 kfree(sky2->tx_ring); 1421 kfree(sky2->tx_ring);
1424 1422
1425 sky2->tx_le = NULL; 1423 sky2->tx_le = NULL;
1426 sky2->rx_le = NULL; 1424 sky2->rx_le = NULL;
1427 1425
1428 sky2->rx_ring = NULL; 1426 sky2->rx_ring = NULL;
1429 sky2->tx_ring = NULL; 1427 sky2->tx_ring = NULL;
1430 1428
1431 return 0; 1429 return 0;
1432 } 1430 }
1433 1431
1434 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux) 1432 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1435 { 1433 {
1436 if (!hw->copper) 1434 if (!hw->copper)
1437 return SPEED_1000; 1435 return SPEED_1000;
1438 1436
1439 if (hw->chip_id == CHIP_ID_YUKON_FE) 1437 if (hw->chip_id == CHIP_ID_YUKON_FE)
1440 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10; 1438 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1441 1439
1442 switch (aux & PHY_M_PS_SPEED_MSK) { 1440 switch (aux & PHY_M_PS_SPEED_MSK) {
1443 case PHY_M_PS_SPEED_1000: 1441 case PHY_M_PS_SPEED_1000:
1444 return SPEED_1000; 1442 return SPEED_1000;
1445 case PHY_M_PS_SPEED_100: 1443 case PHY_M_PS_SPEED_100:
1446 return SPEED_100; 1444 return SPEED_100;
1447 default: 1445 default:
1448 return SPEED_10; 1446 return SPEED_10;
1449 } 1447 }
1450 } 1448 }
1451 1449
1452 static void sky2_link_up(struct sky2_port *sky2) 1450 static void sky2_link_up(struct sky2_port *sky2)
1453 { 1451 {
1454 struct sky2_hw *hw = sky2->hw; 1452 struct sky2_hw *hw = sky2->hw;
1455 unsigned port = sky2->port; 1453 unsigned port = sky2->port;
1456 u16 reg; 1454 u16 reg;
1457 1455
1458 /* Enable Transmit FIFO Underrun */ 1456 /* Enable Transmit FIFO Underrun */
1459 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK); 1457 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
1460 1458
1461 reg = gma_read16(hw, port, GM_GP_CTRL); 1459 reg = gma_read16(hw, port, GM_GP_CTRL);
1462 if (sky2->autoneg == AUTONEG_DISABLE) { 1460 if (sky2->autoneg == AUTONEG_DISABLE) {
1463 reg |= GM_GPCR_AU_ALL_DIS; 1461 reg |= GM_GPCR_AU_ALL_DIS;
1464 1462
1465 /* Is write/read necessary? Copied from sky2_mac_init */ 1463 /* Is write/read necessary? Copied from sky2_mac_init */
1466 gma_write16(hw, port, GM_GP_CTRL, reg); 1464 gma_write16(hw, port, GM_GP_CTRL, reg);
1467 gma_read16(hw, port, GM_GP_CTRL); 1465 gma_read16(hw, port, GM_GP_CTRL);
1468 1466
1469 switch (sky2->speed) { 1467 switch (sky2->speed) {
1470 case SPEED_1000: 1468 case SPEED_1000:
1471 reg &= ~GM_GPCR_SPEED_100; 1469 reg &= ~GM_GPCR_SPEED_100;
1472 reg |= GM_GPCR_SPEED_1000; 1470 reg |= GM_GPCR_SPEED_1000;
1473 break; 1471 break;
1474 case SPEED_100: 1472 case SPEED_100:
1475 reg &= ~GM_GPCR_SPEED_1000; 1473 reg &= ~GM_GPCR_SPEED_1000;
1476 reg |= GM_GPCR_SPEED_100; 1474 reg |= GM_GPCR_SPEED_100;
1477 break; 1475 break;
1478 case SPEED_10: 1476 case SPEED_10:
1479 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100); 1477 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
1480 break; 1478 break;
1481 } 1479 }
1482 } else 1480 } else
1483 reg &= ~GM_GPCR_AU_ALL_DIS; 1481 reg &= ~GM_GPCR_AU_ALL_DIS;
1484 1482
1485 if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE) 1483 if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE)
1486 reg |= GM_GPCR_DUP_FULL; 1484 reg |= GM_GPCR_DUP_FULL;
1487 1485
1488 /* enable Rx/Tx */ 1486 /* enable Rx/Tx */
1489 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA; 1487 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1490 gma_write16(hw, port, GM_GP_CTRL, reg); 1488 gma_write16(hw, port, GM_GP_CTRL, reg);
1491 gma_read16(hw, port, GM_GP_CTRL); 1489 gma_read16(hw, port, GM_GP_CTRL);
1492 1490
1493 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); 1491 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1494 1492
1495 netif_carrier_on(sky2->netdev); 1493 netif_carrier_on(sky2->netdev);
1496 netif_wake_queue(sky2->netdev); 1494 netif_wake_queue(sky2->netdev);
1497 1495
1498 /* Turn on link LED */ 1496 /* Turn on link LED */
1499 sky2_write8(hw, SK_REG(port, LNK_LED_REG), 1497 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1500 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF); 1498 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1501 1499
1502 if (hw->chip_id == CHIP_ID_YUKON_XL) { 1500 if (hw->chip_id == CHIP_ID_YUKON_XL) {
1503 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); 1501 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
1504 1502
1505 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); 1503 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
1506 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */ 1504 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
1507 PHY_M_LEDC_INIT_CTRL(sky2->speed == 1505 PHY_M_LEDC_INIT_CTRL(sky2->speed ==
1508 SPEED_10 ? 7 : 0) | 1506 SPEED_10 ? 7 : 0) |
1509 PHY_M_LEDC_STA1_CTRL(sky2->speed == 1507 PHY_M_LEDC_STA1_CTRL(sky2->speed ==
1510 SPEED_100 ? 7 : 0) | 1508 SPEED_100 ? 7 : 0) |
1511 PHY_M_LEDC_STA0_CTRL(sky2->speed == 1509 PHY_M_LEDC_STA0_CTRL(sky2->speed ==
1512 SPEED_1000 ? 7 : 0)); 1510 SPEED_1000 ? 7 : 0));
1513 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); 1511 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1514 } 1512 }
1515 1513
1516 if (netif_msg_link(sky2)) 1514 if (netif_msg_link(sky2))
1517 printk(KERN_INFO PFX 1515 printk(KERN_INFO PFX
1518 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n", 1516 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1519 sky2->netdev->name, sky2->speed, 1517 sky2->netdev->name, sky2->speed,
1520 sky2->duplex == DUPLEX_FULL ? "full" : "half", 1518 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1521 (sky2->tx_pause && sky2->rx_pause) ? "both" : 1519 (sky2->tx_pause && sky2->rx_pause) ? "both" :
1522 sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none"); 1520 sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
1523 } 1521 }
1524 1522
1525 static void sky2_link_down(struct sky2_port *sky2) 1523 static void sky2_link_down(struct sky2_port *sky2)
1526 { 1524 {
1527 struct sky2_hw *hw = sky2->hw; 1525 struct sky2_hw *hw = sky2->hw;
1528 unsigned port = sky2->port; 1526 unsigned port = sky2->port;
1529 u16 reg; 1527 u16 reg;
1530 1528
1531 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0); 1529 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1532 1530
1533 reg = gma_read16(hw, port, GM_GP_CTRL); 1531 reg = gma_read16(hw, port, GM_GP_CTRL);
1534 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 1532 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1535 gma_write16(hw, port, GM_GP_CTRL, reg); 1533 gma_write16(hw, port, GM_GP_CTRL, reg);
1536 gma_read16(hw, port, GM_GP_CTRL); /* PCI post */ 1534 gma_read16(hw, port, GM_GP_CTRL); /* PCI post */
1537 1535
1538 if (sky2->rx_pause && !sky2->tx_pause) { 1536 if (sky2->rx_pause && !sky2->tx_pause) {
1539 /* restore Asymmetric Pause bit */ 1537 /* restore Asymmetric Pause bit */
1540 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, 1538 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1541 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV) 1539 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1542 | PHY_M_AN_ASP); 1540 | PHY_M_AN_ASP);
1543 } 1541 }
1544 1542
1545 netif_carrier_off(sky2->netdev); 1543 netif_carrier_off(sky2->netdev);
1546 netif_stop_queue(sky2->netdev); 1544 netif_stop_queue(sky2->netdev);
1547 1545
1548 /* Turn on link LED */ 1546 /* Turn on link LED */
1549 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF); 1547 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1550 1548
1551 if (netif_msg_link(sky2)) 1549 if (netif_msg_link(sky2))
1552 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name); 1550 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1553 sky2_phy_init(hw, port); 1551 sky2_phy_init(hw, port);
1554 } 1552 }
1555 1553
1556 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux) 1554 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1557 { 1555 {
1558 struct sky2_hw *hw = sky2->hw; 1556 struct sky2_hw *hw = sky2->hw;
1559 unsigned port = sky2->port; 1557 unsigned port = sky2->port;
1560 u16 lpa; 1558 u16 lpa;
1561 1559
1562 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP); 1560 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1563 1561
1564 if (lpa & PHY_M_AN_RF) { 1562 if (lpa & PHY_M_AN_RF) {
1565 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name); 1563 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1566 return -1; 1564 return -1;
1567 } 1565 }
1568 1566
1569 if (hw->chip_id != CHIP_ID_YUKON_FE && 1567 if (hw->chip_id != CHIP_ID_YUKON_FE &&
1570 gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) { 1568 gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1571 printk(KERN_ERR PFX "%s: master/slave fault", 1569 printk(KERN_ERR PFX "%s: master/slave fault",
1572 sky2->netdev->name); 1570 sky2->netdev->name);
1573 return -1; 1571 return -1;
1574 } 1572 }
1575 1573
1576 if (!(aux & PHY_M_PS_SPDUP_RES)) { 1574 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1577 printk(KERN_ERR PFX "%s: speed/duplex mismatch", 1575 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1578 sky2->netdev->name); 1576 sky2->netdev->name);
1579 return -1; 1577 return -1;
1580 } 1578 }
1581 1579
1582 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF; 1580 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1583 1581
1584 sky2->speed = sky2_phy_speed(hw, aux); 1582 sky2->speed = sky2_phy_speed(hw, aux);
1585 1583
1586 /* Pause bits are offset (9..8) */ 1584 /* Pause bits are offset (9..8) */
1587 if (hw->chip_id == CHIP_ID_YUKON_XL) 1585 if (hw->chip_id == CHIP_ID_YUKON_XL)
1588 aux >>= 6; 1586 aux >>= 6;
1589 1587
1590 sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0; 1588 sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
1591 sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0; 1589 sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;
1592 1590
1593 if ((sky2->tx_pause || sky2->rx_pause) 1591 if ((sky2->tx_pause || sky2->rx_pause)
1594 && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF)) 1592 && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF))
1595 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON); 1593 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1596 else 1594 else
1597 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); 1595 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1598 1596
1599 return 0; 1597 return 0;
1600 } 1598 }
1601 1599
1602 /* 1600 /* Interrupt from PHY */
1603 * Interrupt from PHY are handled outside of interrupt context 1601 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
1604 * because accessing phy registers requires spin wait which might
1605 * cause excess interrupt latency.
1606 */
1607 static void sky2_phy_task(void *arg)
1608 { 1602 {
1609 struct sky2_port *sky2 = arg; 1603 struct net_device *dev = hw->dev[port];
1610 struct sky2_hw *hw = sky2->hw; 1604 struct sky2_port *sky2 = netdev_priv(dev);
1611 u16 istatus, phystat; 1605 u16 istatus, phystat;
1612 1606
1613 down(&sky2->phy_sema); 1607 spin_lock(&sky2->phy_lock);
1614 istatus = gm_phy_read(hw, sky2->port, PHY_MARV_INT_STAT); 1608 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1615 phystat = gm_phy_read(hw, sky2->port, PHY_MARV_PHY_STAT); 1609 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1616 1610
1611 if (!netif_running(dev))
1612 goto out;
1613
1617 if (netif_msg_intr(sky2)) 1614 if (netif_msg_intr(sky2))
1618 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n", 1615 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1619 sky2->netdev->name, istatus, phystat); 1616 sky2->netdev->name, istatus, phystat);
1620 1617
1621 if (istatus & PHY_M_IS_AN_COMPL) { 1618 if (istatus & PHY_M_IS_AN_COMPL) {
1622 if (sky2_autoneg_done(sky2, phystat) == 0) 1619 if (sky2_autoneg_done(sky2, phystat) == 0)
1623 sky2_link_up(sky2); 1620 sky2_link_up(sky2);
1624 goto out; 1621 goto out;
1625 } 1622 }
1626 1623
1627 if (istatus & PHY_M_IS_LSP_CHANGE) 1624 if (istatus & PHY_M_IS_LSP_CHANGE)
1628 sky2->speed = sky2_phy_speed(hw, phystat); 1625 sky2->speed = sky2_phy_speed(hw, phystat);
1629 1626
1630 if (istatus & PHY_M_IS_DUP_CHANGE) 1627 if (istatus & PHY_M_IS_DUP_CHANGE)
1631 sky2->duplex = 1628 sky2->duplex =
1632 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF; 1629 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1633 1630
1634 if (istatus & PHY_M_IS_LST_CHANGE) { 1631 if (istatus & PHY_M_IS_LST_CHANGE) {
1635 if (phystat & PHY_M_PS_LINK_UP) 1632 if (phystat & PHY_M_PS_LINK_UP)
1636 sky2_link_up(sky2); 1633 sky2_link_up(sky2);
1637 else 1634 else
1638 sky2_link_down(sky2); 1635 sky2_link_down(sky2);
1639 } 1636 }
1640 out: 1637 out:
1641 up(&sky2->phy_sema); 1638 spin_unlock(&sky2->phy_lock);
1642
1643 spin_lock_irq(&hw->hw_lock);
1644 hw->intr_mask |= (sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2;
1645 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1646 spin_unlock_irq(&hw->hw_lock);
1647 } 1639 }
1648 1640
1649 1641
1650 /* Transmit timeout is only called if we are running, carries is up 1642 /* Transmit timeout is only called if we are running, carries is up
1651 * and tx queue is full (stopped). 1643 * and tx queue is full (stopped).
1652 */ 1644 */
1653 static void sky2_tx_timeout(struct net_device *dev) 1645 static void sky2_tx_timeout(struct net_device *dev)
1654 { 1646 {
1655 struct sky2_port *sky2 = netdev_priv(dev); 1647 struct sky2_port *sky2 = netdev_priv(dev);
1656 struct sky2_hw *hw = sky2->hw; 1648 struct sky2_hw *hw = sky2->hw;
1657 unsigned txq = txqaddr[sky2->port]; 1649 unsigned txq = txqaddr[sky2->port];
1658 u16 ridx;
1659 1650
1660 /* Maybe we just missed an status interrupt */
1661 spin_lock(&sky2->tx_lock);
1662 ridx = sky2_read16(hw,
1663 sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX);
1664 sky2_tx_complete(sky2, ridx);
1665 spin_unlock(&sky2->tx_lock);
1666
1667 if (!netif_queue_stopped(dev)) {
1668 if (net_ratelimit())
1669 pr_info(PFX "transmit interrupt missed? recovered\n");
1670 return;
1671 }
1672
1673 if (netif_msg_timer(sky2)) 1651 if (netif_msg_timer(sky2))
1674 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name); 1652 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1675 1653
1676 sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP); 1654 sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP);
1677 sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET); 1655 sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1678 1656
1679 sky2_tx_clean(sky2); 1657 sky2_tx_clean(sky2);
1680 1658
1681 sky2_qset(hw, txq); 1659 sky2_qset(hw, txq);
1682 sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1); 1660 sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1);
1683 } 1661 }
1684 1662
1685 1663
1686 #define roundup(x, y) ((((x)+((y)-1))/(y))*(y)) 1664 #define roundup(x, y) ((((x)+((y)-1))/(y))*(y))
1687 /* Want receive buffer size to be multiple of 64 bits 1665 /* Want receive buffer size to be multiple of 64 bits
1688 * and incl room for vlan and truncation 1666 * and incl room for vlan and truncation
1689 */ 1667 */
1690 static inline unsigned sky2_buf_size(int mtu) 1668 static inline unsigned sky2_buf_size(int mtu)
1691 { 1669 {
1692 return roundup(mtu + ETH_HLEN + VLAN_HLEN, 8) + 8; 1670 return roundup(mtu + ETH_HLEN + VLAN_HLEN, 8) + 8;
1693 } 1671 }
1694 1672
1695 static int sky2_change_mtu(struct net_device *dev, int new_mtu) 1673 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1696 { 1674 {
1697 struct sky2_port *sky2 = netdev_priv(dev); 1675 struct sky2_port *sky2 = netdev_priv(dev);
1698 struct sky2_hw *hw = sky2->hw; 1676 struct sky2_hw *hw = sky2->hw;
1699 int err; 1677 int err;
1700 u16 ctl, mode; 1678 u16 ctl, mode;
1679 u32 imask;
1701 1680
1702 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU) 1681 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1703 return -EINVAL; 1682 return -EINVAL;
1704 1683
1705 if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN) 1684 if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
1706 return -EINVAL; 1685 return -EINVAL;
1707 1686
1708 if (!netif_running(dev)) { 1687 if (!netif_running(dev)) {
1709 dev->mtu = new_mtu; 1688 dev->mtu = new_mtu;
1710 return 0; 1689 return 0;
1711 } 1690 }
1712 1691
1692 imask = sky2_read32(hw, B0_IMSK);
1713 sky2_write32(hw, B0_IMSK, 0); 1693 sky2_write32(hw, B0_IMSK, 0);
1714 1694
1715 dev->trans_start = jiffies; /* prevent tx timeout */ 1695 dev->trans_start = jiffies; /* prevent tx timeout */
1716 netif_stop_queue(dev); 1696 netif_stop_queue(dev);
1717 netif_poll_disable(hw->dev[0]); 1697 netif_poll_disable(hw->dev[0]);
1718 1698
1699 synchronize_irq(hw->pdev->irq);
1700
1719 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL); 1701 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1720 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA); 1702 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1721 sky2_rx_stop(sky2); 1703 sky2_rx_stop(sky2);
1722 sky2_rx_clean(sky2); 1704 sky2_rx_clean(sky2);
1723 1705
1724 dev->mtu = new_mtu; 1706 dev->mtu = new_mtu;
1725 sky2->rx_bufsize = sky2_buf_size(new_mtu); 1707 sky2->rx_bufsize = sky2_buf_size(new_mtu);
1726 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) | 1708 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1727 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF); 1709 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1728 1710
1729 if (dev->mtu > ETH_DATA_LEN) 1711 if (dev->mtu > ETH_DATA_LEN)
1730 mode |= GM_SMOD_JUMBO_ENA; 1712 mode |= GM_SMOD_JUMBO_ENA;
1731 1713
1732 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode); 1714 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
1733 1715
1734 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD); 1716 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
1735 1717
1736 err = sky2_rx_start(sky2); 1718 err = sky2_rx_start(sky2);
1737 sky2_write32(hw, B0_IMSK, hw->intr_mask); 1719 sky2_write32(hw, B0_IMSK, imask);
1738 1720
1739 if (err) 1721 if (err)
1740 dev_close(dev); 1722 dev_close(dev);
1741 else { 1723 else {
1742 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl); 1724 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1743 1725
1744 netif_poll_enable(hw->dev[0]); 1726 netif_poll_enable(hw->dev[0]);
1745 netif_wake_queue(dev); 1727 netif_wake_queue(dev);
1746 } 1728 }
1747 1729
1748 return err; 1730 return err;
1749 } 1731 }
1750 1732
1751 /* 1733 /*
1752 * Receive one packet. 1734 * Receive one packet.
1753 * For small packets or errors, just reuse existing skb. 1735 * For small packets or errors, just reuse existing skb.
1754 * For larger packets, get new buffer. 1736 * For larger packets, get new buffer.
1755 */ 1737 */
1756 static struct sk_buff *sky2_receive(struct sky2_port *sky2, 1738 static struct sk_buff *sky2_receive(struct sky2_port *sky2,
1757 u16 length, u32 status) 1739 u16 length, u32 status)
1758 { 1740 {
1759 struct ring_info *re = sky2->rx_ring + sky2->rx_next; 1741 struct ring_info *re = sky2->rx_ring + sky2->rx_next;
1760 struct sk_buff *skb = NULL; 1742 struct sk_buff *skb = NULL;
1761 1743
1762 if (unlikely(netif_msg_rx_status(sky2))) 1744 if (unlikely(netif_msg_rx_status(sky2)))
1763 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n", 1745 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
1764 sky2->netdev->name, sky2->rx_next, status, length); 1746 sky2->netdev->name, sky2->rx_next, status, length);
1765 1747
1766 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending; 1748 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
1767 prefetch(sky2->rx_ring + sky2->rx_next); 1749 prefetch(sky2->rx_ring + sky2->rx_next);
1768 1750
1769 if (status & GMR_FS_ANY_ERR) 1751 if (status & GMR_FS_ANY_ERR)
1770 goto error; 1752 goto error;
1771 1753
1772 if (!(status & GMR_FS_RX_OK)) 1754 if (!(status & GMR_FS_RX_OK))
1773 goto resubmit; 1755 goto resubmit;
1774 1756
1775 if (length > sky2->netdev->mtu + ETH_HLEN) 1757 if (length > sky2->netdev->mtu + ETH_HLEN)
1776 goto oversize; 1758 goto oversize;
1777 1759
1778 if (length < copybreak) { 1760 if (length < copybreak) {
1779 skb = alloc_skb(length + 2, GFP_ATOMIC); 1761 skb = alloc_skb(length + 2, GFP_ATOMIC);
1780 if (!skb) 1762 if (!skb)
1781 goto resubmit; 1763 goto resubmit;
1782 1764
1783 skb_reserve(skb, 2); 1765 skb_reserve(skb, 2);
1784 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr, 1766 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr,
1785 length, PCI_DMA_FROMDEVICE); 1767 length, PCI_DMA_FROMDEVICE);
1786 memcpy(skb->data, re->skb->data, length); 1768 memcpy(skb->data, re->skb->data, length);
1787 skb->ip_summed = re->skb->ip_summed; 1769 skb->ip_summed = re->skb->ip_summed;
1788 skb->csum = re->skb->csum; 1770 skb->csum = re->skb->csum;
1789 pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr, 1771 pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr,
1790 length, PCI_DMA_FROMDEVICE); 1772 length, PCI_DMA_FROMDEVICE);
1791 } else { 1773 } else {
1792 struct sk_buff *nskb; 1774 struct sk_buff *nskb;
1793 1775
1794 nskb = sky2_alloc_skb(sky2->rx_bufsize, GFP_ATOMIC); 1776 nskb = sky2_alloc_skb(sky2->rx_bufsize, GFP_ATOMIC);
1795 if (!nskb) 1777 if (!nskb)
1796 goto resubmit; 1778 goto resubmit;
1797 1779
1798 skb = re->skb; 1780 skb = re->skb;
1799 re->skb = nskb; 1781 re->skb = nskb;
1800 pci_unmap_single(sky2->hw->pdev, re->mapaddr, 1782 pci_unmap_single(sky2->hw->pdev, re->mapaddr,
1801 sky2->rx_bufsize, PCI_DMA_FROMDEVICE); 1783 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
1802 prefetch(skb->data); 1784 prefetch(skb->data);
1803 1785
1804 re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data, 1786 re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,
1805 sky2->rx_bufsize, PCI_DMA_FROMDEVICE); 1787 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
1806 } 1788 }
1807 1789
1808 skb_put(skb, length); 1790 skb_put(skb, length);
1809 resubmit: 1791 resubmit:
1810 re->skb->ip_summed = CHECKSUM_NONE; 1792 re->skb->ip_summed = CHECKSUM_NONE;
1811 sky2_rx_add(sky2, re->mapaddr); 1793 sky2_rx_add(sky2, re->mapaddr);
1812 1794
1813 /* Tell receiver about new buffers. */ 1795 /* Tell receiver about new buffers. */
1814 sky2_put_idx(sky2->hw, rxqaddr[sky2->port], sky2->rx_put); 1796 sky2_put_idx(sky2->hw, rxqaddr[sky2->port], sky2->rx_put);
1815 1797
1816 return skb; 1798 return skb;
1817 1799
1818 oversize: 1800 oversize:
1819 ++sky2->net_stats.rx_over_errors; 1801 ++sky2->net_stats.rx_over_errors;
1820 goto resubmit; 1802 goto resubmit;
1821 1803
1822 error: 1804 error:
1823 ++sky2->net_stats.rx_errors; 1805 ++sky2->net_stats.rx_errors;
1824 1806
1825 if (netif_msg_rx_err(sky2) && net_ratelimit()) 1807 if (netif_msg_rx_err(sky2) && net_ratelimit())
1826 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n", 1808 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
1827 sky2->netdev->name, status, length); 1809 sky2->netdev->name, status, length);
1828 1810
1829 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE)) 1811 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
1830 sky2->net_stats.rx_length_errors++; 1812 sky2->net_stats.rx_length_errors++;
1831 if (status & GMR_FS_FRAGMENT) 1813 if (status & GMR_FS_FRAGMENT)
1832 sky2->net_stats.rx_frame_errors++; 1814 sky2->net_stats.rx_frame_errors++;
1833 if (status & GMR_FS_CRC_ERR) 1815 if (status & GMR_FS_CRC_ERR)
1834 sky2->net_stats.rx_crc_errors++; 1816 sky2->net_stats.rx_crc_errors++;
1835 if (status & GMR_FS_RX_FF_OV) 1817 if (status & GMR_FS_RX_FF_OV)
1836 sky2->net_stats.rx_fifo_errors++; 1818 sky2->net_stats.rx_fifo_errors++;
1837 1819
1838 goto resubmit; 1820 goto resubmit;
1839 } 1821 }
1840 1822
1841 /* 1823 /* Transmit complete */
1842 * Check for transmit complete 1824 static inline void sky2_tx_done(struct net_device *dev, u16 last)
1843 */
1844 #define TX_NO_STATUS 0xffff
1845
1846 static void sky2_tx_check(struct sky2_hw *hw, int port, u16 last)
1847 { 1825 {
1848 if (last != TX_NO_STATUS) { 1826 struct sky2_port *sky2 = netdev_priv(dev);
1849 struct net_device *dev = hw->dev[port];
1850 if (dev && netif_running(dev)) {
1851 struct sky2_port *sky2 = netdev_priv(dev);
1852 1827
1853 spin_lock(&sky2->tx_lock); 1828 if (netif_running(dev)) {
1854 sky2_tx_complete(sky2, last); 1829 spin_lock(&sky2->tx_lock);
1855 spin_unlock(&sky2->tx_lock); 1830 sky2_tx_complete(sky2, last);
1856 } 1831 spin_unlock(&sky2->tx_lock);
1857 } 1832 }
1858 } 1833 }
1859 1834
1860 /* 1835 /* Process status response ring */
1861 * Both ports share the same status interrupt, therefore there is only 1836 static int sky2_status_intr(struct sky2_hw *hw, int to_do)
1862 * one poll routine.
1863 */
1864 static int sky2_poll(struct net_device *dev0, int *budget)
1865 { 1837 {
1866 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw; 1838 int work_done = 0;
1867 unsigned int to_do = min(dev0->quota, *budget);
1868 unsigned int work_done = 0;
1869 u16 hwidx;
1870 u16 tx_done[2] = { TX_NO_STATUS, TX_NO_STATUS };
1871 1839
1872 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
1873
1874 /*
1875 * Kick the STAT_LEV_TIMER_CTRL timer.
1876 * This fixes my hangs on Yukon-EC (0xb6) rev 1.
1877 * The if clause is there to start the timer only if it has been
1878 * configured correctly and not been disabled via ethtool.
1879 */
1880 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_START) {
1881 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
1882 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
1883 }
1884
1885 hwidx = sky2_read16(hw, STAT_PUT_IDX);
1886 BUG_ON(hwidx >= STATUS_RING_SIZE);
1887 rmb(); 1840 rmb();
1888 1841
1889 while (hwidx != hw->st_idx) { 1842 for(;;) {
1890 struct sky2_status_le *le = hw->st_le + hw->st_idx; 1843 struct sky2_status_le *le = hw->st_le + hw->st_idx;
1891 struct net_device *dev; 1844 struct net_device *dev;
1892 struct sky2_port *sky2; 1845 struct sky2_port *sky2;
1893 struct sk_buff *skb; 1846 struct sk_buff *skb;
1894 u32 status; 1847 u32 status;
1895 u16 length; 1848 u16 length;
1849 u8 link, opcode;
1896 1850
1897 le = hw->st_le + hw->st_idx; 1851 opcode = le->opcode;
1852 if (!opcode)
1853 break;
1854 opcode &= ~HW_OWNER;
1855
1898 hw->st_idx = (hw->st_idx + 1) % STATUS_RING_SIZE; 1856 hw->st_idx = (hw->st_idx + 1) % STATUS_RING_SIZE;
1899 prefetch(hw->st_le + hw->st_idx); 1857 le->opcode = 0;
1900 1858
1901 BUG_ON(le->link >= 2); 1859 link = le->link;
1902 dev = hw->dev[le->link]; 1860 BUG_ON(link >= 2);
1903 if (dev == NULL || !netif_running(dev)) 1861 dev = hw->dev[link];
1904 continue;
1905 1862
1906 sky2 = netdev_priv(dev); 1863 sky2 = netdev_priv(dev);
1907 status = le32_to_cpu(le->status); 1864 length = le->length;
1908 length = le16_to_cpu(le->length); 1865 status = le->status;
1909 1866
1910 switch (le->opcode & ~HW_OWNER) { 1867 switch (opcode) {
1911 case OP_RXSTAT: 1868 case OP_RXSTAT:
1912 skb = sky2_receive(sky2, length, status); 1869 skb = sky2_receive(sky2, length, status);
1913 if (!skb) 1870 if (!skb)
1914 break; 1871 break;
1915 1872
1916 skb->dev = dev; 1873 skb->dev = dev;
1917 skb->protocol = eth_type_trans(skb, dev); 1874 skb->protocol = eth_type_trans(skb, dev);
1918 dev->last_rx = jiffies; 1875 dev->last_rx = jiffies;
1919 1876
1920 #ifdef SKY2_VLAN_TAG_USED 1877 #ifdef SKY2_VLAN_TAG_USED
1921 if (sky2->vlgrp && (status & GMR_FS_VLAN)) { 1878 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
1922 vlan_hwaccel_receive_skb(skb, 1879 vlan_hwaccel_receive_skb(skb,
1923 sky2->vlgrp, 1880 sky2->vlgrp,
1924 be16_to_cpu(sky2->rx_tag)); 1881 be16_to_cpu(sky2->rx_tag));
1925 } else 1882 } else
1926 #endif 1883 #endif
1927 netif_receive_skb(skb); 1884 netif_receive_skb(skb);
1928 1885
1929 if (++work_done >= to_do) 1886 if (++work_done >= to_do)
1930 goto exit_loop; 1887 goto exit_loop;
1931 break; 1888 break;
1932 1889
1933 #ifdef SKY2_VLAN_TAG_USED 1890 #ifdef SKY2_VLAN_TAG_USED
1934 case OP_RXVLAN: 1891 case OP_RXVLAN:
1935 sky2->rx_tag = length; 1892 sky2->rx_tag = length;
1936 break; 1893 break;
1937 1894
1938 case OP_RXCHKSVLAN: 1895 case OP_RXCHKSVLAN:
1939 sky2->rx_tag = length; 1896 sky2->rx_tag = length;
1940 /* fall through */ 1897 /* fall through */
1941 #endif 1898 #endif
1942 case OP_RXCHKS: 1899 case OP_RXCHKS:
1943 skb = sky2->rx_ring[sky2->rx_next].skb; 1900 skb = sky2->rx_ring[sky2->rx_next].skb;
1944 skb->ip_summed = CHECKSUM_HW; 1901 skb->ip_summed = CHECKSUM_HW;
1945 skb->csum = le16_to_cpu(status); 1902 skb->csum = le16_to_cpu(status);
1946 break; 1903 break;
1947 1904
1948 case OP_TXINDEXLE: 1905 case OP_TXINDEXLE:
1949 /* TX index reports status for both ports */ 1906 /* TX index reports status for both ports */
1950 tx_done[0] = status & 0xffff; 1907 sky2_tx_done(hw->dev[0], status & 0xffff);
1951 tx_done[1] = ((status >> 24) & 0xff) 1908 if (hw->dev[1])
1952 | (u16)(length & 0xf) << 8; 1909 sky2_tx_done(hw->dev[1],
1910 ((status >> 24) & 0xff)
1911 | (u16)(length & 0xf) << 8);
1953 break; 1912 break;
1954 1913
1955 default: 1914 default:
1956 if (net_ratelimit()) 1915 if (net_ratelimit())
1957 printk(KERN_WARNING PFX 1916 printk(KERN_WARNING PFX
1958 "unknown status opcode 0x%x\n", le->opcode); 1917 "unknown status opcode 0x%x\n", opcode);
1959 break; 1918 break;
1960 } 1919 }
1961 } 1920 }
1962 1921
1963 exit_loop: 1922 exit_loop:
1964 sky2_tx_check(hw, 0, tx_done[0]); 1923 return work_done;
1965 sky2_tx_check(hw, 1, tx_done[1]);
1966
1967 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_START) {
1968 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1969 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1970 }
1971
1972 if (likely(work_done < to_do)) {
1973 spin_lock_irq(&hw->hw_lock);
1974 __netif_rx_complete(dev0);
1975
1976 hw->intr_mask |= Y2_IS_STAT_BMU;
1977 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1978 spin_unlock_irq(&hw->hw_lock);
1979
1980 return 0;
1981 } else {
1982 *budget -= work_done;
1983 dev0->quota -= work_done;
1984 return 1;
1985 }
1986 } 1924 }
1987 1925
1988 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status) 1926 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
1989 { 1927 {
1990 struct net_device *dev = hw->dev[port]; 1928 struct net_device *dev = hw->dev[port];
1991 1929
1992 if (net_ratelimit()) 1930 if (net_ratelimit())
1993 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n", 1931 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
1994 dev->name, status); 1932 dev->name, status);
1995 1933
1996 if (status & Y2_IS_PAR_RD1) { 1934 if (status & Y2_IS_PAR_RD1) {
1997 if (net_ratelimit()) 1935 if (net_ratelimit())
1998 printk(KERN_ERR PFX "%s: ram data read parity error\n", 1936 printk(KERN_ERR PFX "%s: ram data read parity error\n",
1999 dev->name); 1937 dev->name);
2000 /* Clear IRQ */ 1938 /* Clear IRQ */
2001 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR); 1939 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2002 } 1940 }
2003 1941
2004 if (status & Y2_IS_PAR_WR1) { 1942 if (status & Y2_IS_PAR_WR1) {
2005 if (net_ratelimit()) 1943 if (net_ratelimit())
2006 printk(KERN_ERR PFX "%s: ram data write parity error\n", 1944 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2007 dev->name); 1945 dev->name);
2008 1946
2009 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR); 1947 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2010 } 1948 }
2011 1949
2012 if (status & Y2_IS_PAR_MAC1) { 1950 if (status & Y2_IS_PAR_MAC1) {
2013 if (net_ratelimit()) 1951 if (net_ratelimit())
2014 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name); 1952 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
2015 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE); 1953 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2016 } 1954 }
2017 1955
2018 if (status & Y2_IS_PAR_RX1) { 1956 if (status & Y2_IS_PAR_RX1) {
2019 if (net_ratelimit()) 1957 if (net_ratelimit())
2020 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name); 1958 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
2021 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR); 1959 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2022 } 1960 }
2023 1961
2024 if (status & Y2_IS_TCP_TXA1) { 1962 if (status & Y2_IS_TCP_TXA1) {
2025 if (net_ratelimit()) 1963 if (net_ratelimit())
2026 printk(KERN_ERR PFX "%s: TCP segmentation error\n", 1964 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2027 dev->name); 1965 dev->name);
2028 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP); 1966 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2029 } 1967 }
2030 } 1968 }
2031 1969
2032 static void sky2_hw_intr(struct sky2_hw *hw) 1970 static void sky2_hw_intr(struct sky2_hw *hw)
2033 { 1971 {
2034 u32 status = sky2_read32(hw, B0_HWE_ISRC); 1972 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2035 1973
2036 if (status & Y2_IS_TIST_OV) 1974 if (status & Y2_IS_TIST_OV)
2037 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 1975 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2038 1976
2039 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) { 1977 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2040 u16 pci_err; 1978 u16 pci_err;
2041 1979
2042 pci_err = sky2_pci_read16(hw, PCI_STATUS); 1980 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2043 if (net_ratelimit()) 1981 if (net_ratelimit())
2044 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n", 1982 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
2045 pci_name(hw->pdev), pci_err); 1983 pci_name(hw->pdev), pci_err);
2046 1984
2047 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 1985 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2048 sky2_pci_write16(hw, PCI_STATUS, 1986 sky2_pci_write16(hw, PCI_STATUS,
2049 pci_err | PCI_STATUS_ERROR_BITS); 1987 pci_err | PCI_STATUS_ERROR_BITS);
2050 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 1988 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2051 } 1989 }
2052 1990
2053 if (status & Y2_IS_PCI_EXP) { 1991 if (status & Y2_IS_PCI_EXP) {
2054 /* PCI-Express uncorrectable Error occurred */ 1992 /* PCI-Express uncorrectable Error occurred */
2055 u32 pex_err; 1993 u32 pex_err;
2056 1994
2057 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT); 1995 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
2058 1996
2059 if (net_ratelimit()) 1997 if (net_ratelimit())
2060 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n", 1998 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
2061 pci_name(hw->pdev), pex_err); 1999 pci_name(hw->pdev), pex_err);
2062 2000
2063 /* clear the interrupt */ 2001 /* clear the interrupt */
2064 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 2002 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2065 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 2003 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
2066 0xffffffffUL); 2004 0xffffffffUL);
2067 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 2005 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2068 2006
2069 if (pex_err & PEX_FATAL_ERRORS) { 2007 if (pex_err & PEX_FATAL_ERRORS) {
2070 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK); 2008 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2071 hwmsk &= ~Y2_IS_PCI_EXP; 2009 hwmsk &= ~Y2_IS_PCI_EXP;
2072 sky2_write32(hw, B0_HWE_IMSK, hwmsk); 2010 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2073 } 2011 }
2074 } 2012 }
2075 2013
2076 if (status & Y2_HWE_L1_MASK) 2014 if (status & Y2_HWE_L1_MASK)
2077 sky2_hw_error(hw, 0, status); 2015 sky2_hw_error(hw, 0, status);
2078 status >>= 8; 2016 status >>= 8;
2079 if (status & Y2_HWE_L1_MASK) 2017 if (status & Y2_HWE_L1_MASK)
2080 sky2_hw_error(hw, 1, status); 2018 sky2_hw_error(hw, 1, status);
2081 } 2019 }
2082 2020
2083 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port) 2021 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2084 { 2022 {
2085 struct net_device *dev = hw->dev[port]; 2023 struct net_device *dev = hw->dev[port];
2086 struct sky2_port *sky2 = netdev_priv(dev); 2024 struct sky2_port *sky2 = netdev_priv(dev);
2087 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC)); 2025 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2088 2026
2089 if (netif_msg_intr(sky2)) 2027 if (netif_msg_intr(sky2))
2090 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n", 2028 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2091 dev->name, status); 2029 dev->name, status);
2092 2030
2093 if (status & GM_IS_RX_FF_OR) { 2031 if (status & GM_IS_RX_FF_OR) {
2094 ++sky2->net_stats.rx_fifo_errors; 2032 ++sky2->net_stats.rx_fifo_errors;
2095 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO); 2033 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2096 } 2034 }
2097 2035
2098 if (status & GM_IS_TX_FF_UR) { 2036 if (status & GM_IS_TX_FF_UR) {
2099 ++sky2->net_stats.tx_fifo_errors; 2037 ++sky2->net_stats.tx_fifo_errors;
2100 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU); 2038 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2101 } 2039 }
2102 } 2040 }
2103 2041
2104 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
2105 {
2106 struct net_device *dev = hw->dev[port];
2107 struct sky2_port *sky2 = netdev_priv(dev);
2108 2042
2109 hw->intr_mask &= ~(port == 0 ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2); 2043 static int sky2_poll(struct net_device *dev0, int *budget)
2110 sky2_write32(hw, B0_IMSK, hw->intr_mask);
2111
2112 schedule_work(&sky2->phy_task);
2113 }
2114
2115 static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
2116 { 2044 {
2117 struct sky2_hw *hw = dev_id; 2045 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
2118 struct net_device *dev0 = hw->dev[0]; 2046 int work_limit = min(dev0->quota, *budget);
2119 u32 status; 2047 int work_done = 0;
2048 u32 status = sky2_read32(hw, B0_ISRC);
2120 2049
2121 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2122 if (status == 0 || status == ~0)
2123 return IRQ_NONE;
2124
2125 spin_lock(&hw->hw_lock);
2126 if (status & Y2_IS_HW_ERR) 2050 if (status & Y2_IS_HW_ERR)
2127 sky2_hw_intr(hw); 2051 sky2_hw_intr(hw);
2128 2052
2129 /* Do NAPI for Rx and Tx status */
2130 if (status & Y2_IS_STAT_BMU) {
2131 hw->intr_mask &= ~Y2_IS_STAT_BMU;
2132 sky2_write32(hw, B0_IMSK, hw->intr_mask);
2133
2134 if (likely(__netif_rx_schedule_prep(dev0))) {
2135 prefetch(&hw->st_le[hw->st_idx]);
2136 __netif_rx_schedule(dev0);
2137 }
2138 }
2139
2140 if (status & Y2_IS_IRQ_PHY1) 2053 if (status & Y2_IS_IRQ_PHY1)
2141 sky2_phy_intr(hw, 0); 2054 sky2_phy_intr(hw, 0);
2142 2055
2143 if (status & Y2_IS_IRQ_PHY2) 2056 if (status & Y2_IS_IRQ_PHY2)
2144 sky2_phy_intr(hw, 1); 2057 sky2_phy_intr(hw, 1);
2145 2058
2146 if (status & Y2_IS_IRQ_MAC1) 2059 if (status & Y2_IS_IRQ_MAC1)
2147 sky2_mac_intr(hw, 0); 2060 sky2_mac_intr(hw, 0);
2148 2061
2149 if (status & Y2_IS_IRQ_MAC2) 2062 if (status & Y2_IS_IRQ_MAC2)
2150 sky2_mac_intr(hw, 1); 2063 sky2_mac_intr(hw, 1);
2151 2064
2065 if (status & Y2_IS_STAT_BMU) {
2066 work_done = sky2_status_intr(hw, work_limit);
2067 *budget -= work_done;
2068 dev0->quota -= work_done;
2069
2070 if (work_done >= work_limit)
2071 return 1;
2072
2073 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2074 }
2075
2076 netif_rx_complete(dev0);
2077
2078 /* Ack interrupt and re-enable */
2152 sky2_write32(hw, B0_Y2_SP_ICR, 2); 2079 sky2_write32(hw, B0_Y2_SP_ICR, 2);
2080 return 0;
2081 }
2153 2082
2154 spin_unlock(&hw->hw_lock); 2083 static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
2084 {
2085 struct sky2_hw *hw = dev_id;
2086 struct net_device *dev0 = hw->dev[0];
2087 u32 status;
2155 2088
2089 /* Reading this mask interrupts as side effect */
2090 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2091 if (status == 0 || status == ~0)
2092 return IRQ_NONE;
2093
2094 prefetch(&hw->st_le[hw->st_idx]);
2095 if (likely(__netif_rx_schedule_prep(dev0)))
2096 __netif_rx_schedule(dev0);
2097
2156 return IRQ_HANDLED; 2098 return IRQ_HANDLED;
2157 } 2099 }
2158 2100
2159 #ifdef CONFIG_NET_POLL_CONTROLLER 2101 #ifdef CONFIG_NET_POLL_CONTROLLER
2160 static void sky2_netpoll(struct net_device *dev) 2102 static void sky2_netpoll(struct net_device *dev)
2161 { 2103 {
2162 struct sky2_port *sky2 = netdev_priv(dev); 2104 struct sky2_port *sky2 = netdev_priv(dev);
2163 2105
2164 sky2_intr(sky2->hw->pdev->irq, sky2->hw, NULL); 2106 sky2_intr(sky2->hw->pdev->irq, sky2->hw, NULL);
2165 } 2107 }
2166 #endif 2108 #endif
2167 2109
2168 /* Chip internal frequency for clock calculations */ 2110 /* Chip internal frequency for clock calculations */
2169 static inline u32 sky2_mhz(const struct sky2_hw *hw) 2111 static inline u32 sky2_mhz(const struct sky2_hw *hw)
2170 { 2112 {
2171 switch (hw->chip_id) { 2113 switch (hw->chip_id) {
2172 case CHIP_ID_YUKON_EC: 2114 case CHIP_ID_YUKON_EC:
2173 case CHIP_ID_YUKON_EC_U: 2115 case CHIP_ID_YUKON_EC_U:
2174 return 125; /* 125 Mhz */ 2116 return 125; /* 125 Mhz */
2175 case CHIP_ID_YUKON_FE: 2117 case CHIP_ID_YUKON_FE:
2176 return 100; /* 100 Mhz */ 2118 return 100; /* 100 Mhz */
2177 default: /* YUKON_XL */ 2119 default: /* YUKON_XL */
2178 return 156; /* 156 Mhz */ 2120 return 156; /* 156 Mhz */
2179 } 2121 }
2180 } 2122 }
2181 2123
2182 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us) 2124 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2183 { 2125 {
2184 return sky2_mhz(hw) * us; 2126 return sky2_mhz(hw) * us;
2185 } 2127 }
2186 2128
2187 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk) 2129 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2188 { 2130 {
2189 return clk / sky2_mhz(hw); 2131 return clk / sky2_mhz(hw);
2190 } 2132 }
2191 2133
2192 2134
2193 static int sky2_reset(struct sky2_hw *hw) 2135 static int sky2_reset(struct sky2_hw *hw)
2194 { 2136 {
2195 u16 status; 2137 u16 status;
2196 u8 t8, pmd_type; 2138 u8 t8, pmd_type;
2197 int i; 2139 int i;
2198 2140
2199 sky2_write8(hw, B0_CTST, CS_RST_CLR); 2141 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2200 2142
2201 hw->chip_id = sky2_read8(hw, B2_CHIP_ID); 2143 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2202 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) { 2144 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2203 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n", 2145 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2204 pci_name(hw->pdev), hw->chip_id); 2146 pci_name(hw->pdev), hw->chip_id);
2205 return -EOPNOTSUPP; 2147 return -EOPNOTSUPP;
2206 } 2148 }
2207 2149
2208 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4; 2150 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2209 2151
2210 /* This rev is really old, and requires untested workarounds */ 2152 /* This rev is really old, and requires untested workarounds */
2211 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) { 2153 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
2212 printk(KERN_ERR PFX "%s: unsupported revision Yukon-%s (0x%x) rev %d\n", 2154 printk(KERN_ERR PFX "%s: unsupported revision Yukon-%s (0x%x) rev %d\n",
2213 pci_name(hw->pdev), yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL], 2155 pci_name(hw->pdev), yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2214 hw->chip_id, hw->chip_rev); 2156 hw->chip_id, hw->chip_rev);
2215 return -EOPNOTSUPP; 2157 return -EOPNOTSUPP;
2216 } 2158 }
2217 2159
2218 /* This chip is new and not tested yet */ 2160 /* This chip is new and not tested yet */
2219 if (hw->chip_id == CHIP_ID_YUKON_EC_U) { 2161 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
2220 pr_info(PFX "%s: is a version of Yukon 2 chipset that has not been tested yet.\n", 2162 pr_info(PFX "%s: is a version of Yukon 2 chipset that has not been tested yet.\n",
2221 pci_name(hw->pdev)); 2163 pci_name(hw->pdev));
2222 pr_info("Please report success/failure to maintainer <shemminger@osdl.org>\n"); 2164 pr_info("Please report success/failure to maintainer <shemminger@osdl.org>\n");
2223 } 2165 }
2224 2166
2225 /* disable ASF */ 2167 /* disable ASF */
2226 if (hw->chip_id <= CHIP_ID_YUKON_EC) { 2168 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
2227 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET); 2169 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2228 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE); 2170 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2229 } 2171 }
2230 2172
2231 /* do a SW reset */ 2173 /* do a SW reset */
2232 sky2_write8(hw, B0_CTST, CS_RST_SET); 2174 sky2_write8(hw, B0_CTST, CS_RST_SET);
2233 sky2_write8(hw, B0_CTST, CS_RST_CLR); 2175 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2234 2176
2235 /* clear PCI errors, if any */ 2177 /* clear PCI errors, if any */
2236 status = sky2_pci_read16(hw, PCI_STATUS); 2178 status = sky2_pci_read16(hw, PCI_STATUS);
2237 2179
2238 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 2180 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2239 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS); 2181 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2240 2182
2241 2183
2242 sky2_write8(hw, B0_CTST, CS_MRST_CLR); 2184 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2243 2185
2244 /* clear any PEX errors */ 2186 /* clear any PEX errors */
2245 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP)) 2187 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
2246 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL); 2188 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2247 2189
2248 2190
2249 pmd_type = sky2_read8(hw, B2_PMD_TYP); 2191 pmd_type = sky2_read8(hw, B2_PMD_TYP);
2250 hw->copper = !(pmd_type == 'L' || pmd_type == 'S'); 2192 hw->copper = !(pmd_type == 'L' || pmd_type == 'S');
2251 2193
2252 hw->ports = 1; 2194 hw->ports = 1;
2253 t8 = sky2_read8(hw, B2_Y2_HW_RES); 2195 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2254 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) { 2196 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2255 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC)) 2197 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2256 ++hw->ports; 2198 ++hw->ports;
2257 } 2199 }
2258 2200
2259 sky2_set_power_state(hw, PCI_D0); 2201 sky2_set_power_state(hw, PCI_D0);
2260 2202
2261 for (i = 0; i < hw->ports; i++) { 2203 for (i = 0; i < hw->ports; i++) {
2262 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET); 2204 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2263 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR); 2205 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2264 } 2206 }
2265 2207
2266 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 2208 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2267 2209
2268 /* Clear I2C IRQ noise */ 2210 /* Clear I2C IRQ noise */
2269 sky2_write32(hw, B2_I2C_IRQ, 1); 2211 sky2_write32(hw, B2_I2C_IRQ, 1);
2270 2212
2271 /* turn off hardware timer (unused) */ 2213 /* turn off hardware timer (unused) */
2272 sky2_write8(hw, B2_TI_CTRL, TIM_STOP); 2214 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2273 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ); 2215 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2274 2216
2275 sky2_write8(hw, B0_Y2LED, LED_STAT_ON); 2217 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2276 2218
2277 /* Turn off descriptor polling */ 2219 /* Turn off descriptor polling */
2278 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP); 2220 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
2279 2221
2280 /* Turn off receive timestamp */ 2222 /* Turn off receive timestamp */
2281 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP); 2223 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
2282 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 2224 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2283 2225
2284 /* enable the Tx Arbiters */ 2226 /* enable the Tx Arbiters */
2285 for (i = 0; i < hw->ports; i++) 2227 for (i = 0; i < hw->ports; i++)
2286 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB); 2228 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2287 2229
2288 /* Initialize ram interface */ 2230 /* Initialize ram interface */
2289 for (i = 0; i < hw->ports; i++) { 2231 for (i = 0; i < hw->ports; i++) {
2290 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR); 2232 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
2291 2233
2292 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53); 2234 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2293 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53); 2235 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2294 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53); 2236 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2295 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53); 2237 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2296 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53); 2238 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2297 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53); 2239 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2298 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53); 2240 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2299 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53); 2241 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2300 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53); 2242 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2301 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53); 2243 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2302 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53); 2244 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2303 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53); 2245 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2304 } 2246 }
2305 2247
2306 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK); 2248 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2307 2249
2308 for (i = 0; i < hw->ports; i++) 2250 for (i = 0; i < hw->ports; i++)
2309 sky2_phy_reset(hw, i); 2251 sky2_phy_reset(hw, i);
2310 2252
2311 memset(hw->st_le, 0, STATUS_LE_BYTES); 2253 memset(hw->st_le, 0, STATUS_LE_BYTES);
2312 hw->st_idx = 0; 2254 hw->st_idx = 0;
2313 2255
2314 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET); 2256 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2315 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR); 2257 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2316 2258
2317 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma); 2259 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
2318 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32); 2260 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
2319 2261
2320 /* Set the list last index */ 2262 /* Set the list last index */
2321 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1); 2263 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
2322 2264
2323 /* These status setup values are copied from SysKonnect's driver */
2324 sky2_write16(hw, STAT_TX_IDX_TH, 10); 2265 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2325 sky2_write8(hw, STAT_FIFO_WM, 16); 2266 sky2_write8(hw, STAT_FIFO_WM, 16);
2326 2267
2327 /* set Status-FIFO ISR watermark */ 2268 /* set Status-FIFO ISR watermark */
2328 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0) 2269 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2329 sky2_write8(hw, STAT_FIFO_ISR_WM, 4); 2270 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2330 else 2271 else
2331 sky2_write8(hw, STAT_FIFO_ISR_WM, 16); 2272 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
2332 2273
2333 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000)); 2274 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
2334 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 7)); 2275 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 7));
2335 2276
2336 /* enable status unit */ 2277 /* enable status unit */
2337 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON); 2278 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2338 2279
2339 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START); 2280 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2340 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START); 2281 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2341 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START); 2282 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2342 2283
2343 return 0; 2284 return 0;
2344 } 2285 }
2345 2286
2346 static u32 sky2_supported_modes(const struct sky2_hw *hw) 2287 static u32 sky2_supported_modes(const struct sky2_hw *hw)
2347 { 2288 {
2348 u32 modes; 2289 u32 modes;
2349 if (hw->copper) { 2290 if (hw->copper) {
2350 modes = SUPPORTED_10baseT_Half 2291 modes = SUPPORTED_10baseT_Half
2351 | SUPPORTED_10baseT_Full 2292 | SUPPORTED_10baseT_Full
2352 | SUPPORTED_100baseT_Half 2293 | SUPPORTED_100baseT_Half
2353 | SUPPORTED_100baseT_Full 2294 | SUPPORTED_100baseT_Full
2354 | SUPPORTED_Autoneg | SUPPORTED_TP; 2295 | SUPPORTED_Autoneg | SUPPORTED_TP;
2355 2296
2356 if (hw->chip_id != CHIP_ID_YUKON_FE) 2297 if (hw->chip_id != CHIP_ID_YUKON_FE)
2357 modes |= SUPPORTED_1000baseT_Half 2298 modes |= SUPPORTED_1000baseT_Half
2358 | SUPPORTED_1000baseT_Full; 2299 | SUPPORTED_1000baseT_Full;
2359 } else 2300 } else
2360 modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE 2301 modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
2361 | SUPPORTED_Autoneg; 2302 | SUPPORTED_Autoneg;
2362 return modes; 2303 return modes;
2363 } 2304 }
2364 2305
2365 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd) 2306 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2366 { 2307 {
2367 struct sky2_port *sky2 = netdev_priv(dev); 2308 struct sky2_port *sky2 = netdev_priv(dev);
2368 struct sky2_hw *hw = sky2->hw; 2309 struct sky2_hw *hw = sky2->hw;
2369 2310
2370 ecmd->transceiver = XCVR_INTERNAL; 2311 ecmd->transceiver = XCVR_INTERNAL;
2371 ecmd->supported = sky2_supported_modes(hw); 2312 ecmd->supported = sky2_supported_modes(hw);
2372 ecmd->phy_address = PHY_ADDR_MARV; 2313 ecmd->phy_address = PHY_ADDR_MARV;
2373 if (hw->copper) { 2314 if (hw->copper) {
2374 ecmd->supported = SUPPORTED_10baseT_Half 2315 ecmd->supported = SUPPORTED_10baseT_Half
2375 | SUPPORTED_10baseT_Full 2316 | SUPPORTED_10baseT_Full
2376 | SUPPORTED_100baseT_Half 2317 | SUPPORTED_100baseT_Half
2377 | SUPPORTED_100baseT_Full 2318 | SUPPORTED_100baseT_Full
2378 | SUPPORTED_1000baseT_Half 2319 | SUPPORTED_1000baseT_Half
2379 | SUPPORTED_1000baseT_Full 2320 | SUPPORTED_1000baseT_Full
2380 | SUPPORTED_Autoneg | SUPPORTED_TP; 2321 | SUPPORTED_Autoneg | SUPPORTED_TP;
2381 ecmd->port = PORT_TP; 2322 ecmd->port = PORT_TP;
2382 } else 2323 } else
2383 ecmd->port = PORT_FIBRE; 2324 ecmd->port = PORT_FIBRE;
2384 2325
2385 ecmd->advertising = sky2->advertising; 2326 ecmd->advertising = sky2->advertising;
2386 ecmd->autoneg = sky2->autoneg; 2327 ecmd->autoneg = sky2->autoneg;
2387 ecmd->speed = sky2->speed; 2328 ecmd->speed = sky2->speed;
2388 ecmd->duplex = sky2->duplex; 2329 ecmd->duplex = sky2->duplex;
2389 return 0; 2330 return 0;
2390 } 2331 }
2391 2332
2392 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd) 2333 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2393 { 2334 {
2394 struct sky2_port *sky2 = netdev_priv(dev); 2335 struct sky2_port *sky2 = netdev_priv(dev);
2395 const struct sky2_hw *hw = sky2->hw; 2336 const struct sky2_hw *hw = sky2->hw;
2396 u32 supported = sky2_supported_modes(hw); 2337 u32 supported = sky2_supported_modes(hw);
2397 2338
2398 if (ecmd->autoneg == AUTONEG_ENABLE) { 2339 if (ecmd->autoneg == AUTONEG_ENABLE) {
2399 ecmd->advertising = supported; 2340 ecmd->advertising = supported;
2400 sky2->duplex = -1; 2341 sky2->duplex = -1;
2401 sky2->speed = -1; 2342 sky2->speed = -1;
2402 } else { 2343 } else {
2403 u32 setting; 2344 u32 setting;
2404 2345
2405 switch (ecmd->speed) { 2346 switch (ecmd->speed) {
2406 case SPEED_1000: 2347 case SPEED_1000:
2407 if (ecmd->duplex == DUPLEX_FULL) 2348 if (ecmd->duplex == DUPLEX_FULL)
2408 setting = SUPPORTED_1000baseT_Full; 2349 setting = SUPPORTED_1000baseT_Full;
2409 else if (ecmd->duplex == DUPLEX_HALF) 2350 else if (ecmd->duplex == DUPLEX_HALF)
2410 setting = SUPPORTED_1000baseT_Half; 2351 setting = SUPPORTED_1000baseT_Half;
2411 else 2352 else
2412 return -EINVAL; 2353 return -EINVAL;
2413 break; 2354 break;
2414 case SPEED_100: 2355 case SPEED_100:
2415 if (ecmd->duplex == DUPLEX_FULL) 2356 if (ecmd->duplex == DUPLEX_FULL)
2416 setting = SUPPORTED_100baseT_Full; 2357 setting = SUPPORTED_100baseT_Full;
2417 else if (ecmd->duplex == DUPLEX_HALF) 2358 else if (ecmd->duplex == DUPLEX_HALF)
2418 setting = SUPPORTED_100baseT_Half; 2359 setting = SUPPORTED_100baseT_Half;
2419 else 2360 else
2420 return -EINVAL; 2361 return -EINVAL;
2421 break; 2362 break;
2422 2363
2423 case SPEED_10: 2364 case SPEED_10:
2424 if (ecmd->duplex == DUPLEX_FULL) 2365 if (ecmd->duplex == DUPLEX_FULL)
2425 setting = SUPPORTED_10baseT_Full; 2366 setting = SUPPORTED_10baseT_Full;
2426 else if (ecmd->duplex == DUPLEX_HALF) 2367 else if (ecmd->duplex == DUPLEX_HALF)
2427 setting = SUPPORTED_10baseT_Half; 2368 setting = SUPPORTED_10baseT_Half;
2428 else 2369 else
2429 return -EINVAL; 2370 return -EINVAL;
2430 break; 2371 break;
2431 default: 2372 default:
2432 return -EINVAL; 2373 return -EINVAL;
2433 } 2374 }
2434 2375
2435 if ((setting & supported) == 0) 2376 if ((setting & supported) == 0)
2436 return -EINVAL; 2377 return -EINVAL;
2437 2378
2438 sky2->speed = ecmd->speed; 2379 sky2->speed = ecmd->speed;
2439 sky2->duplex = ecmd->duplex; 2380 sky2->duplex = ecmd->duplex;
2440 } 2381 }
2441 2382
2442 sky2->autoneg = ecmd->autoneg; 2383 sky2->autoneg = ecmd->autoneg;
2443 sky2->advertising = ecmd->advertising; 2384 sky2->advertising = ecmd->advertising;
2444 2385
2445 if (netif_running(dev)) 2386 if (netif_running(dev))
2446 sky2_phy_reinit(sky2); 2387 sky2_phy_reinit(sky2);
2447 2388
2448 return 0; 2389 return 0;
2449 } 2390 }
2450 2391
2451 static void sky2_get_drvinfo(struct net_device *dev, 2392 static void sky2_get_drvinfo(struct net_device *dev,
2452 struct ethtool_drvinfo *info) 2393 struct ethtool_drvinfo *info)
2453 { 2394 {
2454 struct sky2_port *sky2 = netdev_priv(dev); 2395 struct sky2_port *sky2 = netdev_priv(dev);
2455 2396
2456 strcpy(info->driver, DRV_NAME); 2397 strcpy(info->driver, DRV_NAME);
2457 strcpy(info->version, DRV_VERSION); 2398 strcpy(info->version, DRV_VERSION);
2458 strcpy(info->fw_version, "N/A"); 2399 strcpy(info->fw_version, "N/A");
2459 strcpy(info->bus_info, pci_name(sky2->hw->pdev)); 2400 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2460 } 2401 }
2461 2402
2462 static const struct sky2_stat { 2403 static const struct sky2_stat {
2463 char name[ETH_GSTRING_LEN]; 2404 char name[ETH_GSTRING_LEN];
2464 u16 offset; 2405 u16 offset;
2465 } sky2_stats[] = { 2406 } sky2_stats[] = {
2466 { "tx_bytes", GM_TXO_OK_HI }, 2407 { "tx_bytes", GM_TXO_OK_HI },
2467 { "rx_bytes", GM_RXO_OK_HI }, 2408 { "rx_bytes", GM_RXO_OK_HI },
2468 { "tx_broadcast", GM_TXF_BC_OK }, 2409 { "tx_broadcast", GM_TXF_BC_OK },
2469 { "rx_broadcast", GM_RXF_BC_OK }, 2410 { "rx_broadcast", GM_RXF_BC_OK },
2470 { "tx_multicast", GM_TXF_MC_OK }, 2411 { "tx_multicast", GM_TXF_MC_OK },
2471 { "rx_multicast", GM_RXF_MC_OK }, 2412 { "rx_multicast", GM_RXF_MC_OK },
2472 { "tx_unicast", GM_TXF_UC_OK }, 2413 { "tx_unicast", GM_TXF_UC_OK },
2473 { "rx_unicast", GM_RXF_UC_OK }, 2414 { "rx_unicast", GM_RXF_UC_OK },
2474 { "tx_mac_pause", GM_TXF_MPAUSE }, 2415 { "tx_mac_pause", GM_TXF_MPAUSE },
2475 { "rx_mac_pause", GM_RXF_MPAUSE }, 2416 { "rx_mac_pause", GM_RXF_MPAUSE },
2476 { "collisions", GM_TXF_SNG_COL }, 2417 { "collisions", GM_TXF_SNG_COL },
2477 { "late_collision",GM_TXF_LAT_COL }, 2418 { "late_collision",GM_TXF_LAT_COL },
2478 { "aborted", GM_TXF_ABO_COL }, 2419 { "aborted", GM_TXF_ABO_COL },
2479 { "multi_collisions", GM_TXF_MUL_COL }, 2420 { "multi_collisions", GM_TXF_MUL_COL },
2480 { "fifo_underrun", GM_TXE_FIFO_UR }, 2421 { "fifo_underrun", GM_TXE_FIFO_UR },
2481 { "fifo_overflow", GM_RXE_FIFO_OV }, 2422 { "fifo_overflow", GM_RXE_FIFO_OV },
2482 { "rx_toolong", GM_RXF_LNG_ERR }, 2423 { "rx_toolong", GM_RXF_LNG_ERR },
2483 { "rx_jabber", GM_RXF_JAB_PKT }, 2424 { "rx_jabber", GM_RXF_JAB_PKT },
2484 { "rx_runt", GM_RXE_FRAG }, 2425 { "rx_runt", GM_RXE_FRAG },
2485 { "rx_too_long", GM_RXF_LNG_ERR }, 2426 { "rx_too_long", GM_RXF_LNG_ERR },
2486 { "rx_fcs_error", GM_RXF_FCS_ERR }, 2427 { "rx_fcs_error", GM_RXF_FCS_ERR },
2487 }; 2428 };
2488 2429
2489 static u32 sky2_get_rx_csum(struct net_device *dev) 2430 static u32 sky2_get_rx_csum(struct net_device *dev)
2490 { 2431 {
2491 struct sky2_port *sky2 = netdev_priv(dev); 2432 struct sky2_port *sky2 = netdev_priv(dev);
2492 2433
2493 return sky2->rx_csum; 2434 return sky2->rx_csum;
2494 } 2435 }
2495 2436
2496 static int sky2_set_rx_csum(struct net_device *dev, u32 data) 2437 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2497 { 2438 {
2498 struct sky2_port *sky2 = netdev_priv(dev); 2439 struct sky2_port *sky2 = netdev_priv(dev);
2499 2440
2500 sky2->rx_csum = data; 2441 sky2->rx_csum = data;
2501 2442
2502 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR), 2443 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2503 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM); 2444 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2504 2445
2505 return 0; 2446 return 0;
2506 } 2447 }
2507 2448
2508 static u32 sky2_get_msglevel(struct net_device *netdev) 2449 static u32 sky2_get_msglevel(struct net_device *netdev)
2509 { 2450 {
2510 struct sky2_port *sky2 = netdev_priv(netdev); 2451 struct sky2_port *sky2 = netdev_priv(netdev);
2511 return sky2->msg_enable; 2452 return sky2->msg_enable;
2512 } 2453 }
2513 2454
2514 static int sky2_nway_reset(struct net_device *dev) 2455 static int sky2_nway_reset(struct net_device *dev)
2515 { 2456 {
2516 struct sky2_port *sky2 = netdev_priv(dev); 2457 struct sky2_port *sky2 = netdev_priv(dev);
2517 2458
2518 if (sky2->autoneg != AUTONEG_ENABLE) 2459 if (sky2->autoneg != AUTONEG_ENABLE)
2519 return -EINVAL; 2460 return -EINVAL;
2520 2461
2521 sky2_phy_reinit(sky2); 2462 sky2_phy_reinit(sky2);
2522 2463
2523 return 0; 2464 return 0;
2524 } 2465 }
2525 2466
2526 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count) 2467 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
2527 { 2468 {
2528 struct sky2_hw *hw = sky2->hw; 2469 struct sky2_hw *hw = sky2->hw;
2529 unsigned port = sky2->port; 2470 unsigned port = sky2->port;
2530 int i; 2471 int i;
2531 2472
2532 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32 2473 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2533 | (u64) gma_read32(hw, port, GM_TXO_OK_LO); 2474 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
2534 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32 2475 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2535 | (u64) gma_read32(hw, port, GM_RXO_OK_LO); 2476 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
2536 2477
2537 for (i = 2; i < count; i++) 2478 for (i = 2; i < count; i++)
2538 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset); 2479 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2539 } 2480 }
2540 2481
2541 static void sky2_set_msglevel(struct net_device *netdev, u32 value) 2482 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2542 { 2483 {
2543 struct sky2_port *sky2 = netdev_priv(netdev); 2484 struct sky2_port *sky2 = netdev_priv(netdev);
2544 sky2->msg_enable = value; 2485 sky2->msg_enable = value;
2545 } 2486 }
2546 2487
2547 static int sky2_get_stats_count(struct net_device *dev) 2488 static int sky2_get_stats_count(struct net_device *dev)
2548 { 2489 {
2549 return ARRAY_SIZE(sky2_stats); 2490 return ARRAY_SIZE(sky2_stats);
2550 } 2491 }
2551 2492
2552 static void sky2_get_ethtool_stats(struct net_device *dev, 2493 static void sky2_get_ethtool_stats(struct net_device *dev,
2553 struct ethtool_stats *stats, u64 * data) 2494 struct ethtool_stats *stats, u64 * data)
2554 { 2495 {
2555 struct sky2_port *sky2 = netdev_priv(dev); 2496 struct sky2_port *sky2 = netdev_priv(dev);
2556 2497
2557 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats)); 2498 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
2558 } 2499 }
2559 2500
2560 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data) 2501 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
2561 { 2502 {
2562 int i; 2503 int i;
2563 2504
2564 switch (stringset) { 2505 switch (stringset) {
2565 case ETH_SS_STATS: 2506 case ETH_SS_STATS:
2566 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++) 2507 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2567 memcpy(data + i * ETH_GSTRING_LEN, 2508 memcpy(data + i * ETH_GSTRING_LEN,
2568 sky2_stats[i].name, ETH_GSTRING_LEN); 2509 sky2_stats[i].name, ETH_GSTRING_LEN);
2569 break; 2510 break;
2570 } 2511 }
2571 } 2512 }
2572 2513
2573 /* Use hardware MIB variables for critical path statistics and 2514 /* Use hardware MIB variables for critical path statistics and
2574 * transmit feedback not reported at interrupt. 2515 * transmit feedback not reported at interrupt.
2575 * Other errors are accounted for in interrupt handler. 2516 * Other errors are accounted for in interrupt handler.
2576 */ 2517 */
2577 static struct net_device_stats *sky2_get_stats(struct net_device *dev) 2518 static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2578 { 2519 {
2579 struct sky2_port *sky2 = netdev_priv(dev); 2520 struct sky2_port *sky2 = netdev_priv(dev);
2580 u64 data[13]; 2521 u64 data[13];
2581 2522
2582 sky2_phy_stats(sky2, data, ARRAY_SIZE(data)); 2523 sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
2583 2524
2584 sky2->net_stats.tx_bytes = data[0]; 2525 sky2->net_stats.tx_bytes = data[0];
2585 sky2->net_stats.rx_bytes = data[1]; 2526 sky2->net_stats.rx_bytes = data[1];
2586 sky2->net_stats.tx_packets = data[2] + data[4] + data[6]; 2527 sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2587 sky2->net_stats.rx_packets = data[3] + data[5] + data[7]; 2528 sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
2588 sky2->net_stats.multicast = data[5] + data[7]; 2529 sky2->net_stats.multicast = data[5] + data[7];
2589 sky2->net_stats.collisions = data[10]; 2530 sky2->net_stats.collisions = data[10];
2590 sky2->net_stats.tx_aborted_errors = data[12]; 2531 sky2->net_stats.tx_aborted_errors = data[12];
2591 2532
2592 return &sky2->net_stats; 2533 return &sky2->net_stats;
2593 } 2534 }
2594 2535
2595 static int sky2_set_mac_address(struct net_device *dev, void *p) 2536 static int sky2_set_mac_address(struct net_device *dev, void *p)
2596 { 2537 {
2597 struct sky2_port *sky2 = netdev_priv(dev); 2538 struct sky2_port *sky2 = netdev_priv(dev);
2598 struct sky2_hw *hw = sky2->hw; 2539 struct sky2_hw *hw = sky2->hw;
2599 unsigned port = sky2->port; 2540 unsigned port = sky2->port;
2600 const struct sockaddr *addr = p; 2541 const struct sockaddr *addr = p;
2601 2542
2602 if (!is_valid_ether_addr(addr->sa_data)) 2543 if (!is_valid_ether_addr(addr->sa_data))
2603 return -EADDRNOTAVAIL; 2544 return -EADDRNOTAVAIL;
2604 2545
2605 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); 2546 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2606 memcpy_toio(hw->regs + B2_MAC_1 + port * 8, 2547 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
2607 dev->dev_addr, ETH_ALEN); 2548 dev->dev_addr, ETH_ALEN);
2608 memcpy_toio(hw->regs + B2_MAC_2 + port * 8, 2549 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
2609 dev->dev_addr, ETH_ALEN); 2550 dev->dev_addr, ETH_ALEN);
2610 2551
2611 /* virtual address for data */ 2552 /* virtual address for data */
2612 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr); 2553 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2613 2554
2614 /* physical address: used for pause frames */ 2555 /* physical address: used for pause frames */
2615 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr); 2556 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
2616 2557
2617 return 0; 2558 return 0;
2618 } 2559 }
2619 2560
2620 static void sky2_set_multicast(struct net_device *dev) 2561 static void sky2_set_multicast(struct net_device *dev)
2621 { 2562 {
2622 struct sky2_port *sky2 = netdev_priv(dev); 2563 struct sky2_port *sky2 = netdev_priv(dev);
2623 struct sky2_hw *hw = sky2->hw; 2564 struct sky2_hw *hw = sky2->hw;
2624 unsigned port = sky2->port; 2565 unsigned port = sky2->port;
2625 struct dev_mc_list *list = dev->mc_list; 2566 struct dev_mc_list *list = dev->mc_list;
2626 u16 reg; 2567 u16 reg;
2627 u8 filter[8]; 2568 u8 filter[8];
2628 2569
2629 memset(filter, 0, sizeof(filter)); 2570 memset(filter, 0, sizeof(filter));
2630 2571
2631 reg = gma_read16(hw, port, GM_RX_CTRL); 2572 reg = gma_read16(hw, port, GM_RX_CTRL);
2632 reg |= GM_RXCR_UCF_ENA; 2573 reg |= GM_RXCR_UCF_ENA;
2633 2574
2634 if (dev->flags & IFF_PROMISC) /* promiscuous */ 2575 if (dev->flags & IFF_PROMISC) /* promiscuous */
2635 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); 2576 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2636 else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */ 2577 else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */
2637 memset(filter, 0xff, sizeof(filter)); 2578 memset(filter, 0xff, sizeof(filter));
2638 else if (dev->mc_count == 0) /* no multicast */ 2579 else if (dev->mc_count == 0) /* no multicast */
2639 reg &= ~GM_RXCR_MCF_ENA; 2580 reg &= ~GM_RXCR_MCF_ENA;
2640 else { 2581 else {
2641 int i; 2582 int i;
2642 reg |= GM_RXCR_MCF_ENA; 2583 reg |= GM_RXCR_MCF_ENA;
2643 2584
2644 for (i = 0; list && i < dev->mc_count; i++, list = list->next) { 2585 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2645 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f; 2586 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2646 filter[bit / 8] |= 1 << (bit % 8); 2587 filter[bit / 8] |= 1 << (bit % 8);
2647 } 2588 }
2648 } 2589 }
2649 2590
2650 gma_write16(hw, port, GM_MC_ADDR_H1, 2591 gma_write16(hw, port, GM_MC_ADDR_H1,
2651 (u16) filter[0] | ((u16) filter[1] << 8)); 2592 (u16) filter[0] | ((u16) filter[1] << 8));
2652 gma_write16(hw, port, GM_MC_ADDR_H2, 2593 gma_write16(hw, port, GM_MC_ADDR_H2,
2653 (u16) filter[2] | ((u16) filter[3] << 8)); 2594 (u16) filter[2] | ((u16) filter[3] << 8));
2654 gma_write16(hw, port, GM_MC_ADDR_H3, 2595 gma_write16(hw, port, GM_MC_ADDR_H3,
2655 (u16) filter[4] | ((u16) filter[5] << 8)); 2596 (u16) filter[4] | ((u16) filter[5] << 8));
2656 gma_write16(hw, port, GM_MC_ADDR_H4, 2597 gma_write16(hw, port, GM_MC_ADDR_H4,
2657 (u16) filter[6] | ((u16) filter[7] << 8)); 2598 (u16) filter[6] | ((u16) filter[7] << 8));
2658 2599
2659 gma_write16(hw, port, GM_RX_CTRL, reg); 2600 gma_write16(hw, port, GM_RX_CTRL, reg);
2660 } 2601 }
2661 2602
2662 /* Can have one global because blinking is controlled by 2603 /* Can have one global because blinking is controlled by
2663 * ethtool and that is always under RTNL mutex 2604 * ethtool and that is always under RTNL mutex
2664 */ 2605 */
2665 static void sky2_led(struct sky2_hw *hw, unsigned port, int on) 2606 static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
2666 { 2607 {
2667 u16 pg; 2608 u16 pg;
2668 2609
2669 switch (hw->chip_id) { 2610 switch (hw->chip_id) {
2670 case CHIP_ID_YUKON_XL: 2611 case CHIP_ID_YUKON_XL:
2671 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); 2612 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2672 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); 2613 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2673 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, 2614 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2674 on ? (PHY_M_LEDC_LOS_CTRL(1) | 2615 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2675 PHY_M_LEDC_INIT_CTRL(7) | 2616 PHY_M_LEDC_INIT_CTRL(7) |
2676 PHY_M_LEDC_STA1_CTRL(7) | 2617 PHY_M_LEDC_STA1_CTRL(7) |
2677 PHY_M_LEDC_STA0_CTRL(7)) 2618 PHY_M_LEDC_STA0_CTRL(7))
2678 : 0); 2619 : 0);
2679 2620
2680 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); 2621 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2681 break; 2622 break;
2682 2623
2683 default: 2624 default:
2684 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0); 2625 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
2685 gm_phy_write(hw, port, PHY_MARV_LED_OVER, 2626 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
2686 on ? PHY_M_LED_MO_DUP(MO_LED_ON) | 2627 on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2687 PHY_M_LED_MO_10(MO_LED_ON) | 2628 PHY_M_LED_MO_10(MO_LED_ON) |
2688 PHY_M_LED_MO_100(MO_LED_ON) | 2629 PHY_M_LED_MO_100(MO_LED_ON) |
2689 PHY_M_LED_MO_1000(MO_LED_ON) | 2630 PHY_M_LED_MO_1000(MO_LED_ON) |
2690 PHY_M_LED_MO_RX(MO_LED_ON) 2631 PHY_M_LED_MO_RX(MO_LED_ON)
2691 : PHY_M_LED_MO_DUP(MO_LED_OFF) | 2632 : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2692 PHY_M_LED_MO_10(MO_LED_OFF) | 2633 PHY_M_LED_MO_10(MO_LED_OFF) |
2693 PHY_M_LED_MO_100(MO_LED_OFF) | 2634 PHY_M_LED_MO_100(MO_LED_OFF) |
2694 PHY_M_LED_MO_1000(MO_LED_OFF) | 2635 PHY_M_LED_MO_1000(MO_LED_OFF) |
2695 PHY_M_LED_MO_RX(MO_LED_OFF)); 2636 PHY_M_LED_MO_RX(MO_LED_OFF));
2696 2637
2697 } 2638 }
2698 } 2639 }
2699 2640
2700 /* blink LED's for finding board */ 2641 /* blink LED's for finding board */
2701 static int sky2_phys_id(struct net_device *dev, u32 data) 2642 static int sky2_phys_id(struct net_device *dev, u32 data)
2702 { 2643 {
2703 struct sky2_port *sky2 = netdev_priv(dev); 2644 struct sky2_port *sky2 = netdev_priv(dev);
2704 struct sky2_hw *hw = sky2->hw; 2645 struct sky2_hw *hw = sky2->hw;
2705 unsigned port = sky2->port; 2646 unsigned port = sky2->port;
2706 u16 ledctrl, ledover = 0; 2647 u16 ledctrl, ledover = 0;
2707 long ms; 2648 long ms;
2708 int interrupted; 2649 int interrupted;
2709 int onoff = 1; 2650 int onoff = 1;
2710 2651
2711 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ)) 2652 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
2712 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT); 2653 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2713 else 2654 else
2714 ms = data * 1000; 2655 ms = data * 1000;
2715 2656
2716 /* save initial values */ 2657 /* save initial values */
2717 down(&sky2->phy_sema); 2658 spin_lock_bh(&sky2->phy_lock);
2718 if (hw->chip_id == CHIP_ID_YUKON_XL) { 2659 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2719 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); 2660 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2720 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); 2661 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2721 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); 2662 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2722 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); 2663 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2723 } else { 2664 } else {
2724 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL); 2665 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2725 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER); 2666 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2726 } 2667 }
2727 2668
2728 interrupted = 0; 2669 interrupted = 0;
2729 while (!interrupted && ms > 0) { 2670 while (!interrupted && ms > 0) {
2730 sky2_led(hw, port, onoff); 2671 sky2_led(hw, port, onoff);
2731 onoff = !onoff; 2672 onoff = !onoff;
2732 2673
2733 up(&sky2->phy_sema); 2674 spin_unlock_bh(&sky2->phy_lock);
2734 interrupted = msleep_interruptible(250); 2675 interrupted = msleep_interruptible(250);
2735 down(&sky2->phy_sema); 2676 spin_lock_bh(&sky2->phy_lock);
2736 2677
2737 ms -= 250; 2678 ms -= 250;
2738 } 2679 }
2739 2680
2740 /* resume regularly scheduled programming */ 2681 /* resume regularly scheduled programming */
2741 if (hw->chip_id == CHIP_ID_YUKON_XL) { 2682 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2742 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); 2683 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2743 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); 2684 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2744 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl); 2685 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2745 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); 2686 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2746 } else { 2687 } else {
2747 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl); 2688 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2748 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover); 2689 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2749 } 2690 }
2750 up(&sky2->phy_sema); 2691 spin_unlock_bh(&sky2->phy_lock);
2751 2692
2752 return 0; 2693 return 0;
2753 } 2694 }
2754 2695
2755 static void sky2_get_pauseparam(struct net_device *dev, 2696 static void sky2_get_pauseparam(struct net_device *dev,
2756 struct ethtool_pauseparam *ecmd) 2697 struct ethtool_pauseparam *ecmd)
2757 { 2698 {
2758 struct sky2_port *sky2 = netdev_priv(dev); 2699 struct sky2_port *sky2 = netdev_priv(dev);
2759 2700
2760 ecmd->tx_pause = sky2->tx_pause; 2701 ecmd->tx_pause = sky2->tx_pause;
2761 ecmd->rx_pause = sky2->rx_pause; 2702 ecmd->rx_pause = sky2->rx_pause;
2762 ecmd->autoneg = sky2->autoneg; 2703 ecmd->autoneg = sky2->autoneg;
2763 } 2704 }
2764 2705
2765 static int sky2_set_pauseparam(struct net_device *dev, 2706 static int sky2_set_pauseparam(struct net_device *dev,
2766 struct ethtool_pauseparam *ecmd) 2707 struct ethtool_pauseparam *ecmd)
2767 { 2708 {
2768 struct sky2_port *sky2 = netdev_priv(dev); 2709 struct sky2_port *sky2 = netdev_priv(dev);
2769 int err = 0; 2710 int err = 0;
2770 2711
2771 sky2->autoneg = ecmd->autoneg; 2712 sky2->autoneg = ecmd->autoneg;
2772 sky2->tx_pause = ecmd->tx_pause != 0; 2713 sky2->tx_pause = ecmd->tx_pause != 0;
2773 sky2->rx_pause = ecmd->rx_pause != 0; 2714 sky2->rx_pause = ecmd->rx_pause != 0;
2774 2715
2775 sky2_phy_reinit(sky2); 2716 sky2_phy_reinit(sky2);
2776 2717
2777 return err; 2718 return err;
2778 } 2719 }
2779 2720
2780 static int sky2_get_coalesce(struct net_device *dev, 2721 static int sky2_get_coalesce(struct net_device *dev,
2781 struct ethtool_coalesce *ecmd) 2722 struct ethtool_coalesce *ecmd)
2782 { 2723 {
2783 struct sky2_port *sky2 = netdev_priv(dev); 2724 struct sky2_port *sky2 = netdev_priv(dev);
2784 struct sky2_hw *hw = sky2->hw; 2725 struct sky2_hw *hw = sky2->hw;
2785 2726
2786 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP) 2727 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
2787 ecmd->tx_coalesce_usecs = 0; 2728 ecmd->tx_coalesce_usecs = 0;
2788 else { 2729 else {
2789 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI); 2730 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
2790 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks); 2731 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
2791 } 2732 }
2792 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH); 2733 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
2793 2734
2794 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP) 2735 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
2795 ecmd->rx_coalesce_usecs = 0; 2736 ecmd->rx_coalesce_usecs = 0;
2796 else { 2737 else {
2797 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI); 2738 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
2798 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks); 2739 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
2799 } 2740 }
2800 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM); 2741 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
2801 2742
2802 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP) 2743 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
2803 ecmd->rx_coalesce_usecs_irq = 0; 2744 ecmd->rx_coalesce_usecs_irq = 0;
2804 else { 2745 else {
2805 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI); 2746 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
2806 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks); 2747 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
2807 } 2748 }
2808 2749
2809 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM); 2750 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
2810 2751
2811 return 0; 2752 return 0;
2812 } 2753 }
2813 2754
2814 /* Note: this affect both ports */ 2755 /* Note: this affect both ports */
2815 static int sky2_set_coalesce(struct net_device *dev, 2756 static int sky2_set_coalesce(struct net_device *dev,
2816 struct ethtool_coalesce *ecmd) 2757 struct ethtool_coalesce *ecmd)
2817 { 2758 {
2818 struct sky2_port *sky2 = netdev_priv(dev); 2759 struct sky2_port *sky2 = netdev_priv(dev);
2819 struct sky2_hw *hw = sky2->hw; 2760 struct sky2_hw *hw = sky2->hw;
2820 const u32 tmin = sky2_clk2us(hw, 1); 2761 const u32 tmin = sky2_clk2us(hw, 1);
2821 const u32 tmax = 5000; 2762 const u32 tmax = 5000;
2822 2763
2823 if (ecmd->tx_coalesce_usecs != 0 && 2764 if (ecmd->tx_coalesce_usecs != 0 &&
2824 (ecmd->tx_coalesce_usecs < tmin || ecmd->tx_coalesce_usecs > tmax)) 2765 (ecmd->tx_coalesce_usecs < tmin || ecmd->tx_coalesce_usecs > tmax))
2825 return -EINVAL; 2766 return -EINVAL;
2826 2767
2827 if (ecmd->rx_coalesce_usecs != 0 && 2768 if (ecmd->rx_coalesce_usecs != 0 &&
2828 (ecmd->rx_coalesce_usecs < tmin || ecmd->rx_coalesce_usecs > tmax)) 2769 (ecmd->rx_coalesce_usecs < tmin || ecmd->rx_coalesce_usecs > tmax))
2829 return -EINVAL; 2770 return -EINVAL;
2830 2771
2831 if (ecmd->rx_coalesce_usecs_irq != 0 && 2772 if (ecmd->rx_coalesce_usecs_irq != 0 &&
2832 (ecmd->rx_coalesce_usecs_irq < tmin || ecmd->rx_coalesce_usecs_irq > tmax)) 2773 (ecmd->rx_coalesce_usecs_irq < tmin || ecmd->rx_coalesce_usecs_irq > tmax))
2833 return -EINVAL; 2774 return -EINVAL;
2834 2775
2835 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1) 2776 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
2836 return -EINVAL; 2777 return -EINVAL;
2837 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING) 2778 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
2838 return -EINVAL; 2779 return -EINVAL;
2839 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING) 2780 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
2840 return -EINVAL; 2781 return -EINVAL;
2841 2782
2842 if (ecmd->tx_coalesce_usecs == 0) 2783 if (ecmd->tx_coalesce_usecs == 0)
2843 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP); 2784 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2844 else { 2785 else {
2845 sky2_write32(hw, STAT_TX_TIMER_INI, 2786 sky2_write32(hw, STAT_TX_TIMER_INI,
2846 sky2_us2clk(hw, ecmd->tx_coalesce_usecs)); 2787 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
2847 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START); 2788 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2848 } 2789 }
2849 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames); 2790 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
2850 2791
2851 if (ecmd->rx_coalesce_usecs == 0) 2792 if (ecmd->rx_coalesce_usecs == 0)
2852 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP); 2793 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
2853 else { 2794 else {
2854 sky2_write32(hw, STAT_LEV_TIMER_INI, 2795 sky2_write32(hw, STAT_LEV_TIMER_INI,
2855 sky2_us2clk(hw, ecmd->rx_coalesce_usecs)); 2796 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
2856 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START); 2797 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2857 } 2798 }
2858 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames); 2799 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
2859 2800
2860 if (ecmd->rx_coalesce_usecs_irq == 0) 2801 if (ecmd->rx_coalesce_usecs_irq == 0)
2861 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP); 2802 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
2862 else { 2803 else {
2863 sky2_write32(hw, STAT_ISR_TIMER_INI, 2804 sky2_write32(hw, STAT_ISR_TIMER_INI,
2864 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq)); 2805 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
2865 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START); 2806 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2866 } 2807 }
2867 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq); 2808 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
2868 return 0; 2809 return 0;
2869 } 2810 }
2870 2811
2871 static void sky2_get_ringparam(struct net_device *dev, 2812 static void sky2_get_ringparam(struct net_device *dev,
2872 struct ethtool_ringparam *ering) 2813 struct ethtool_ringparam *ering)
2873 { 2814 {
2874 struct sky2_port *sky2 = netdev_priv(dev); 2815 struct sky2_port *sky2 = netdev_priv(dev);
2875 2816
2876 ering->rx_max_pending = RX_MAX_PENDING; 2817 ering->rx_max_pending = RX_MAX_PENDING;
2877 ering->rx_mini_max_pending = 0; 2818 ering->rx_mini_max_pending = 0;
2878 ering->rx_jumbo_max_pending = 0; 2819 ering->rx_jumbo_max_pending = 0;
2879 ering->tx_max_pending = TX_RING_SIZE - 1; 2820 ering->tx_max_pending = TX_RING_SIZE - 1;
2880 2821
2881 ering->rx_pending = sky2->rx_pending; 2822 ering->rx_pending = sky2->rx_pending;
2882 ering->rx_mini_pending = 0; 2823 ering->rx_mini_pending = 0;
2883 ering->rx_jumbo_pending = 0; 2824 ering->rx_jumbo_pending = 0;
2884 ering->tx_pending = sky2->tx_pending; 2825 ering->tx_pending = sky2->tx_pending;
2885 } 2826 }
2886 2827
2887 static int sky2_set_ringparam(struct net_device *dev, 2828 static int sky2_set_ringparam(struct net_device *dev,
2888 struct ethtool_ringparam *ering) 2829 struct ethtool_ringparam *ering)
2889 { 2830 {
2890 struct sky2_port *sky2 = netdev_priv(dev); 2831 struct sky2_port *sky2 = netdev_priv(dev);
2891 int err = 0; 2832 int err = 0;
2892 2833
2893 if (ering->rx_pending > RX_MAX_PENDING || 2834 if (ering->rx_pending > RX_MAX_PENDING ||
2894 ering->rx_pending < 8 || 2835 ering->rx_pending < 8 ||
2895 ering->tx_pending < MAX_SKB_TX_LE || 2836 ering->tx_pending < MAX_SKB_TX_LE ||
2896 ering->tx_pending > TX_RING_SIZE - 1) 2837 ering->tx_pending > TX_RING_SIZE - 1)
2897 return -EINVAL; 2838 return -EINVAL;
2898 2839
2899 if (netif_running(dev)) 2840 if (netif_running(dev))
2900 sky2_down(dev); 2841 sky2_down(dev);
2901 2842
2902 sky2->rx_pending = ering->rx_pending; 2843 sky2->rx_pending = ering->rx_pending;
2903 sky2->tx_pending = ering->tx_pending; 2844 sky2->tx_pending = ering->tx_pending;
2904 2845
2905 if (netif_running(dev)) { 2846 if (netif_running(dev)) {
2906 err = sky2_up(dev); 2847 err = sky2_up(dev);
2907 if (err) 2848 if (err)
2908 dev_close(dev); 2849 dev_close(dev);
2909 else 2850 else
2910 sky2_set_multicast(dev); 2851 sky2_set_multicast(dev);
2911 } 2852 }
2912 2853
2913 return err; 2854 return err;
2914 } 2855 }
2915 2856
2916 static int sky2_get_regs_len(struct net_device *dev) 2857 static int sky2_get_regs_len(struct net_device *dev)
2917 { 2858 {
2918 return 0x4000; 2859 return 0x4000;
2919 } 2860 }
2920 2861
2921 /* 2862 /*
2922 * Returns copy of control register region 2863 * Returns copy of control register region
2923 * Note: access to the RAM address register set will cause timeouts. 2864 * Note: access to the RAM address register set will cause timeouts.
2924 */ 2865 */
2925 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs, 2866 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2926 void *p) 2867 void *p)
2927 { 2868 {
2928 const struct sky2_port *sky2 = netdev_priv(dev); 2869 const struct sky2_port *sky2 = netdev_priv(dev);
2929 const void __iomem *io = sky2->hw->regs; 2870 const void __iomem *io = sky2->hw->regs;
2930 2871
2931 BUG_ON(regs->len < B3_RI_WTO_R1); 2872 BUG_ON(regs->len < B3_RI_WTO_R1);
2932 regs->version = 1; 2873 regs->version = 1;
2933 memset(p, 0, regs->len); 2874 memset(p, 0, regs->len);
2934 2875
2935 memcpy_fromio(p, io, B3_RAM_ADDR); 2876 memcpy_fromio(p, io, B3_RAM_ADDR);
2936 2877
2937 memcpy_fromio(p + B3_RI_WTO_R1, 2878 memcpy_fromio(p + B3_RI_WTO_R1,
2938 io + B3_RI_WTO_R1, 2879 io + B3_RI_WTO_R1,
2939 regs->len - B3_RI_WTO_R1); 2880 regs->len - B3_RI_WTO_R1);
2940 } 2881 }
2941 2882
2942 static struct ethtool_ops sky2_ethtool_ops = { 2883 static struct ethtool_ops sky2_ethtool_ops = {
2943 .get_settings = sky2_get_settings, 2884 .get_settings = sky2_get_settings,
2944 .set_settings = sky2_set_settings, 2885 .set_settings = sky2_set_settings,
2945 .get_drvinfo = sky2_get_drvinfo, 2886 .get_drvinfo = sky2_get_drvinfo,
2946 .get_msglevel = sky2_get_msglevel, 2887 .get_msglevel = sky2_get_msglevel,
2947 .set_msglevel = sky2_set_msglevel, 2888 .set_msglevel = sky2_set_msglevel,
2948 .nway_reset = sky2_nway_reset, 2889 .nway_reset = sky2_nway_reset,
2949 .get_regs_len = sky2_get_regs_len, 2890 .get_regs_len = sky2_get_regs_len,
2950 .get_regs = sky2_get_regs, 2891 .get_regs = sky2_get_regs,
2951 .get_link = ethtool_op_get_link, 2892 .get_link = ethtool_op_get_link,
2952 .get_sg = ethtool_op_get_sg, 2893 .get_sg = ethtool_op_get_sg,
2953 .set_sg = ethtool_op_set_sg, 2894 .set_sg = ethtool_op_set_sg,
2954 .get_tx_csum = ethtool_op_get_tx_csum, 2895 .get_tx_csum = ethtool_op_get_tx_csum,
2955 .set_tx_csum = ethtool_op_set_tx_csum, 2896 .set_tx_csum = ethtool_op_set_tx_csum,
2956 .get_tso = ethtool_op_get_tso, 2897 .get_tso = ethtool_op_get_tso,
2957 .set_tso = ethtool_op_set_tso, 2898 .set_tso = ethtool_op_set_tso,
2958 .get_rx_csum = sky2_get_rx_csum, 2899 .get_rx_csum = sky2_get_rx_csum,
2959 .set_rx_csum = sky2_set_rx_csum, 2900 .set_rx_csum = sky2_set_rx_csum,
2960 .get_strings = sky2_get_strings, 2901 .get_strings = sky2_get_strings,
2961 .get_coalesce = sky2_get_coalesce, 2902 .get_coalesce = sky2_get_coalesce,
2962 .set_coalesce = sky2_set_coalesce, 2903 .set_coalesce = sky2_set_coalesce,
2963 .get_ringparam = sky2_get_ringparam, 2904 .get_ringparam = sky2_get_ringparam,
2964 .set_ringparam = sky2_set_ringparam, 2905 .set_ringparam = sky2_set_ringparam,
2965 .get_pauseparam = sky2_get_pauseparam, 2906 .get_pauseparam = sky2_get_pauseparam,
2966 .set_pauseparam = sky2_set_pauseparam, 2907 .set_pauseparam = sky2_set_pauseparam,
2967 .phys_id = sky2_phys_id, 2908 .phys_id = sky2_phys_id,
2968 .get_stats_count = sky2_get_stats_count, 2909 .get_stats_count = sky2_get_stats_count,
2969 .get_ethtool_stats = sky2_get_ethtool_stats, 2910 .get_ethtool_stats = sky2_get_ethtool_stats,
2970 .get_perm_addr = ethtool_op_get_perm_addr, 2911 .get_perm_addr = ethtool_op_get_perm_addr,
2971 }; 2912 };
2972 2913
2973 /* Initialize network device */ 2914 /* Initialize network device */
2974 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw, 2915 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
2975 unsigned port, int highmem) 2916 unsigned port, int highmem)
2976 { 2917 {
2977 struct sky2_port *sky2; 2918 struct sky2_port *sky2;
2978 struct net_device *dev = alloc_etherdev(sizeof(*sky2)); 2919 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
2979 2920
2980 if (!dev) { 2921 if (!dev) {
2981 printk(KERN_ERR "sky2 etherdev alloc failed"); 2922 printk(KERN_ERR "sky2 etherdev alloc failed");
2982 return NULL; 2923 return NULL;
2983 } 2924 }
2984 2925
2985 SET_MODULE_OWNER(dev); 2926 SET_MODULE_OWNER(dev);
2986 SET_NETDEV_DEV(dev, &hw->pdev->dev); 2927 SET_NETDEV_DEV(dev, &hw->pdev->dev);
2987 dev->irq = hw->pdev->irq; 2928 dev->irq = hw->pdev->irq;
2988 dev->open = sky2_up; 2929 dev->open = sky2_up;
2989 dev->stop = sky2_down; 2930 dev->stop = sky2_down;
2990 dev->do_ioctl = sky2_ioctl; 2931 dev->do_ioctl = sky2_ioctl;
2991 dev->hard_start_xmit = sky2_xmit_frame; 2932 dev->hard_start_xmit = sky2_xmit_frame;
2992 dev->get_stats = sky2_get_stats; 2933 dev->get_stats = sky2_get_stats;
2993 dev->set_multicast_list = sky2_set_multicast; 2934 dev->set_multicast_list = sky2_set_multicast;
2994 dev->set_mac_address = sky2_set_mac_address; 2935 dev->set_mac_address = sky2_set_mac_address;
2995 dev->change_mtu = sky2_change_mtu; 2936 dev->change_mtu = sky2_change_mtu;
2996 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops); 2937 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
2997 dev->tx_timeout = sky2_tx_timeout; 2938 dev->tx_timeout = sky2_tx_timeout;
2998 dev->watchdog_timeo = TX_WATCHDOG; 2939 dev->watchdog_timeo = TX_WATCHDOG;
2999 if (port == 0) 2940 if (port == 0)
3000 dev->poll = sky2_poll; 2941 dev->poll = sky2_poll;
3001 dev->weight = NAPI_WEIGHT; 2942 dev->weight = NAPI_WEIGHT;
3002 #ifdef CONFIG_NET_POLL_CONTROLLER 2943 #ifdef CONFIG_NET_POLL_CONTROLLER
3003 dev->poll_controller = sky2_netpoll; 2944 dev->poll_controller = sky2_netpoll;
3004 #endif 2945 #endif
3005 2946
3006 sky2 = netdev_priv(dev); 2947 sky2 = netdev_priv(dev);
3007 sky2->netdev = dev; 2948 sky2->netdev = dev;
3008 sky2->hw = hw; 2949 sky2->hw = hw;
3009 sky2->msg_enable = netif_msg_init(debug, default_msg); 2950 sky2->msg_enable = netif_msg_init(debug, default_msg);
3010 2951
3011 spin_lock_init(&sky2->tx_lock); 2952 spin_lock_init(&sky2->tx_lock);
3012 /* Auto speed and flow control */ 2953 /* Auto speed and flow control */
3013 sky2->autoneg = AUTONEG_ENABLE; 2954 sky2->autoneg = AUTONEG_ENABLE;
3014 sky2->tx_pause = 1; 2955 sky2->tx_pause = 1;
3015 sky2->rx_pause = 1; 2956 sky2->rx_pause = 1;
3016 sky2->duplex = -1; 2957 sky2->duplex = -1;
3017 sky2->speed = -1; 2958 sky2->speed = -1;
3018 sky2->advertising = sky2_supported_modes(hw); 2959 sky2->advertising = sky2_supported_modes(hw);
3019 2960
3020 /* Receive checksum disabled for Yukon XL 2961 /* Receive checksum disabled for Yukon XL
3021 * because of observed problems with incorrect 2962 * because of observed problems with incorrect
3022 * values when multiple packets are received in one interrupt 2963 * values when multiple packets are received in one interrupt
3023 */ 2964 */
3024 sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL); 2965 sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);
3025 2966
3026 INIT_WORK(&sky2->phy_task, sky2_phy_task, sky2); 2967 spin_lock_init(&sky2->phy_lock);
3027 init_MUTEX(&sky2->phy_sema);
3028 sky2->tx_pending = TX_DEF_PENDING; 2968 sky2->tx_pending = TX_DEF_PENDING;
3029 sky2->rx_pending = RX_DEF_PENDING; 2969 sky2->rx_pending = RX_DEF_PENDING;
3030 sky2->rx_bufsize = sky2_buf_size(ETH_DATA_LEN); 2970 sky2->rx_bufsize = sky2_buf_size(ETH_DATA_LEN);
3031 2971
3032 hw->dev[port] = dev; 2972 hw->dev[port] = dev;
3033 2973
3034 sky2->port = port; 2974 sky2->port = port;
3035 2975
3036 dev->features |= NETIF_F_LLTX; 2976 dev->features |= NETIF_F_LLTX;
3037 if (hw->chip_id != CHIP_ID_YUKON_EC_U) 2977 if (hw->chip_id != CHIP_ID_YUKON_EC_U)
3038 dev->features |= NETIF_F_TSO; 2978 dev->features |= NETIF_F_TSO;
3039 if (highmem) 2979 if (highmem)
3040 dev->features |= NETIF_F_HIGHDMA; 2980 dev->features |= NETIF_F_HIGHDMA;
3041 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG; 2981 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3042 2982
3043 #ifdef SKY2_VLAN_TAG_USED 2983 #ifdef SKY2_VLAN_TAG_USED
3044 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; 2984 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3045 dev->vlan_rx_register = sky2_vlan_rx_register; 2985 dev->vlan_rx_register = sky2_vlan_rx_register;
3046 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid; 2986 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
3047 #endif 2987 #endif
3048 2988
3049 /* read the mac address */ 2989 /* read the mac address */
3050 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN); 2990 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
3051 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); 2991 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3052 2992
3053 /* device is off until link detection */ 2993 /* device is off until link detection */
3054 netif_carrier_off(dev); 2994 netif_carrier_off(dev);
3055 netif_stop_queue(dev); 2995 netif_stop_queue(dev);
3056 2996
3057 return dev; 2997 return dev;
3058 } 2998 }
3059 2999
3060 static void __devinit sky2_show_addr(struct net_device *dev) 3000 static void __devinit sky2_show_addr(struct net_device *dev)
3061 { 3001 {
3062 const struct sky2_port *sky2 = netdev_priv(dev); 3002 const struct sky2_port *sky2 = netdev_priv(dev);
3063 3003
3064 if (netif_msg_probe(sky2)) 3004 if (netif_msg_probe(sky2))
3065 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n", 3005 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3066 dev->name, 3006 dev->name,
3067 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2], 3007 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3068 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]); 3008 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3069 } 3009 }
3070 3010
3071 static int __devinit sky2_probe(struct pci_dev *pdev, 3011 static int __devinit sky2_probe(struct pci_dev *pdev,
3072 const struct pci_device_id *ent) 3012 const struct pci_device_id *ent)
3073 { 3013 {
3074 struct net_device *dev, *dev1 = NULL; 3014 struct net_device *dev, *dev1 = NULL;
3075 struct sky2_hw *hw; 3015 struct sky2_hw *hw;
3076 int err, pm_cap, using_dac = 0; 3016 int err, pm_cap, using_dac = 0;
3077 3017
3078 err = pci_enable_device(pdev); 3018 err = pci_enable_device(pdev);
3079 if (err) { 3019 if (err) {
3080 printk(KERN_ERR PFX "%s cannot enable PCI device\n", 3020 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3081 pci_name(pdev)); 3021 pci_name(pdev));
3082 goto err_out; 3022 goto err_out;
3083 } 3023 }
3084 3024
3085 err = pci_request_regions(pdev, DRV_NAME); 3025 err = pci_request_regions(pdev, DRV_NAME);
3086 if (err) { 3026 if (err) {
3087 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n", 3027 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3088 pci_name(pdev)); 3028 pci_name(pdev));
3089 goto err_out; 3029 goto err_out;
3090 } 3030 }
3091 3031
3092 pci_set_master(pdev); 3032 pci_set_master(pdev);
3093 3033
3094 /* Find power-management capability. */ 3034 /* Find power-management capability. */
3095 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); 3035 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
3096 if (pm_cap == 0) { 3036 if (pm_cap == 0) {
3097 printk(KERN_ERR PFX "Cannot find PowerManagement capability, " 3037 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
3098 "aborting.\n"); 3038 "aborting.\n");
3099 err = -EIO; 3039 err = -EIO;
3100 goto err_out_free_regions; 3040 goto err_out_free_regions;
3101 } 3041 }
3102 3042
3103 if (sizeof(dma_addr_t) > sizeof(u32) && 3043 if (sizeof(dma_addr_t) > sizeof(u32) &&
3104 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) { 3044 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3105 using_dac = 1; 3045 using_dac = 1;
3106 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); 3046 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3107 if (err < 0) { 3047 if (err < 0) {
3108 printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA " 3048 printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA "
3109 "for consistent allocations\n", pci_name(pdev)); 3049 "for consistent allocations\n", pci_name(pdev));
3110 goto err_out_free_regions; 3050 goto err_out_free_regions;
3111 } 3051 }
3112 3052
3113 } else { 3053 } else {
3114 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK); 3054 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3115 if (err) { 3055 if (err) {
3116 printk(KERN_ERR PFX "%s no usable DMA configuration\n", 3056 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3117 pci_name(pdev)); 3057 pci_name(pdev));
3118 goto err_out_free_regions; 3058 goto err_out_free_regions;
3119 } 3059 }
3120 } 3060 }
3121 3061
3122 err = -ENOMEM; 3062 err = -ENOMEM;
3123 hw = kzalloc(sizeof(*hw), GFP_KERNEL); 3063 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
3124 if (!hw) { 3064 if (!hw) {
3125 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n", 3065 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3126 pci_name(pdev)); 3066 pci_name(pdev));
3127 goto err_out_free_regions; 3067 goto err_out_free_regions;
3128 } 3068 }
3129 3069
3130 hw->pdev = pdev; 3070 hw->pdev = pdev;
3131 3071
3132 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000); 3072 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3133 if (!hw->regs) { 3073 if (!hw->regs) {
3134 printk(KERN_ERR PFX "%s: cannot map device registers\n", 3074 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3135 pci_name(pdev)); 3075 pci_name(pdev));
3136 goto err_out_free_hw; 3076 goto err_out_free_hw;
3137 } 3077 }
3138 hw->pm_cap = pm_cap; 3078 hw->pm_cap = pm_cap;
3139 spin_lock_init(&hw->hw_lock);
3140 3079
3141 #ifdef __BIG_ENDIAN 3080 #ifdef __BIG_ENDIAN
3142 /* byte swap descriptors in hardware */ 3081 /* byte swap descriptors in hardware */
3143 { 3082 {
3144 u32 reg; 3083 u32 reg;
3145 3084
3146 reg = sky2_pci_read32(hw, PCI_DEV_REG2); 3085 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
3147 reg |= PCI_REV_DESC; 3086 reg |= PCI_REV_DESC;
3148 sky2_pci_write32(hw, PCI_DEV_REG2, reg); 3087 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3149 } 3088 }
3150 #endif 3089 #endif
3151 3090
3152 /* ring for status responses */ 3091 /* ring for status responses */
3153 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES, 3092 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3154 &hw->st_dma); 3093 &hw->st_dma);
3155 if (!hw->st_le) 3094 if (!hw->st_le)
3156 goto err_out_iounmap; 3095 goto err_out_iounmap;
3157 3096
3158 err = sky2_reset(hw); 3097 err = sky2_reset(hw);
3159 if (err) 3098 if (err)
3160 goto err_out_iounmap; 3099 goto err_out_iounmap;
3161 3100
3162 printk(KERN_INFO PFX "v%s addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n", 3101 printk(KERN_INFO PFX "v%s addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n",
3163 DRV_VERSION, pci_resource_start(pdev, 0), pdev->irq, 3102 DRV_VERSION, pci_resource_start(pdev, 0), pdev->irq,
3164 yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL], 3103 yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
3165 hw->chip_id, hw->chip_rev); 3104 hw->chip_id, hw->chip_rev);
3166 3105
3167 dev = sky2_init_netdev(hw, 0, using_dac); 3106 dev = sky2_init_netdev(hw, 0, using_dac);
3168 if (!dev) 3107 if (!dev)
3169 goto err_out_free_pci; 3108 goto err_out_free_pci;
3170 3109
3171 err = register_netdev(dev); 3110 err = register_netdev(dev);
3172 if (err) { 3111 if (err) {
3173 printk(KERN_ERR PFX "%s: cannot register net device\n", 3112 printk(KERN_ERR PFX "%s: cannot register net device\n",
3174 pci_name(pdev)); 3113 pci_name(pdev));
3175 goto err_out_free_netdev; 3114 goto err_out_free_netdev;
3176 } 3115 }
3177 3116
3178 sky2_show_addr(dev); 3117 sky2_show_addr(dev);
3179 3118
3180 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) { 3119 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
3181 if (register_netdev(dev1) == 0) 3120 if (register_netdev(dev1) == 0)
3182 sky2_show_addr(dev1); 3121 sky2_show_addr(dev1);
3183 else { 3122 else {
3184 /* Failure to register second port need not be fatal */ 3123 /* Failure to register second port need not be fatal */
3185 printk(KERN_WARNING PFX 3124 printk(KERN_WARNING PFX
3186 "register of second port failed\n"); 3125 "register of second port failed\n");
3187 hw->dev[1] = NULL; 3126 hw->dev[1] = NULL;
3188 free_netdev(dev1); 3127 free_netdev(dev1);
3189 } 3128 }
3190 } 3129 }
3191 3130
3192 err = request_irq(pdev->irq, sky2_intr, SA_SHIRQ, DRV_NAME, hw); 3131 err = request_irq(pdev->irq, sky2_intr, SA_SHIRQ, DRV_NAME, hw);
3193 if (err) { 3132 if (err) {
3194 printk(KERN_ERR PFX "%s: cannot assign irq %d\n", 3133 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3195 pci_name(pdev), pdev->irq); 3134 pci_name(pdev), pdev->irq);
3196 goto err_out_unregister; 3135 goto err_out_unregister;
3197 } 3136 }
3198 3137
3199 hw->intr_mask = Y2_IS_BASE; 3138 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3200 sky2_write32(hw, B0_IMSK, hw->intr_mask);
3201 3139
3202 pci_set_drvdata(pdev, hw); 3140 pci_set_drvdata(pdev, hw);
3203 3141
3204 return 0; 3142 return 0;
3205 3143
3206 err_out_unregister: 3144 err_out_unregister:
3207 if (dev1) { 3145 if (dev1) {
3208 unregister_netdev(dev1); 3146 unregister_netdev(dev1);
3209 free_netdev(dev1); 3147 free_netdev(dev1);
3210 } 3148 }
3211 unregister_netdev(dev); 3149 unregister_netdev(dev);
3212 err_out_free_netdev: 3150 err_out_free_netdev:
3213 free_netdev(dev); 3151 free_netdev(dev);
3214 err_out_free_pci: 3152 err_out_free_pci:
3215 sky2_write8(hw, B0_CTST, CS_RST_SET); 3153 sky2_write8(hw, B0_CTST, CS_RST_SET);
3216 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma); 3154 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3217 err_out_iounmap: 3155 err_out_iounmap:
3218 iounmap(hw->regs); 3156 iounmap(hw->regs);
3219 err_out_free_hw: 3157 err_out_free_hw:
3220 kfree(hw); 3158 kfree(hw);
3221 err_out_free_regions: 3159 err_out_free_regions:
3222 pci_release_regions(pdev); 3160 pci_release_regions(pdev);
3223 pci_disable_device(pdev); 3161 pci_disable_device(pdev);
3224 err_out: 3162 err_out:
3225 return err; 3163 return err;
3226 } 3164 }
3227 3165
3228 static void __devexit sky2_remove(struct pci_dev *pdev) 3166 static void __devexit sky2_remove(struct pci_dev *pdev)
3229 { 3167 {
3230 struct sky2_hw *hw = pci_get_drvdata(pdev); 3168 struct sky2_hw *hw = pci_get_drvdata(pdev);
3231 struct net_device *dev0, *dev1; 3169 struct net_device *dev0, *dev1;
3232 3170
3233 if (!hw) 3171 if (!hw)
3234 return; 3172 return;
3235 3173
3236 dev0 = hw->dev[0]; 3174 dev0 = hw->dev[0];
3237 dev1 = hw->dev[1]; 3175 dev1 = hw->dev[1];
3238 if (dev1) 3176 if (dev1)
3239 unregister_netdev(dev1); 3177 unregister_netdev(dev1);
3240 unregister_netdev(dev0); 3178 unregister_netdev(dev0);
3241 3179
3242 sky2_write32(hw, B0_IMSK, 0); 3180 sky2_write32(hw, B0_IMSK, 0);
3243 sky2_set_power_state(hw, PCI_D3hot); 3181 sky2_set_power_state(hw, PCI_D3hot);
3244 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF); 3182 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
3245 sky2_write8(hw, B0_CTST, CS_RST_SET); 3183 sky2_write8(hw, B0_CTST, CS_RST_SET);
3246 sky2_read8(hw, B0_CTST); 3184 sky2_read8(hw, B0_CTST);
3247 3185
3248 free_irq(pdev->irq, hw); 3186 free_irq(pdev->irq, hw);
3249 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma); 3187 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3250 pci_release_regions(pdev); 3188 pci_release_regions(pdev);
3251 pci_disable_device(pdev); 3189 pci_disable_device(pdev);
3252 3190
3253 if (dev1) 3191 if (dev1)
3254 free_netdev(dev1); 3192 free_netdev(dev1);
3255 free_netdev(dev0); 3193 free_netdev(dev0);
3256 iounmap(hw->regs); 3194 iounmap(hw->regs);
3257 kfree(hw); 3195 kfree(hw);
3258 3196
3259 pci_set_drvdata(pdev, NULL); 3197 pci_set_drvdata(pdev, NULL);
3260 } 3198 }
3261 3199
3262 #ifdef CONFIG_PM 3200 #ifdef CONFIG_PM
3263 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state) 3201 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3264 { 3202 {
3265 struct sky2_hw *hw = pci_get_drvdata(pdev); 3203 struct sky2_hw *hw = pci_get_drvdata(pdev);
3266 int i; 3204 int i;
3267 3205
3268 for (i = 0; i < 2; i++) { 3206 for (i = 0; i < 2; i++) {
3269 struct net_device *dev = hw->dev[i]; 3207 struct net_device *dev = hw->dev[i];
3270 3208
3271 if (dev) { 3209 if (dev) {
3272 if (!netif_running(dev)) 3210 if (!netif_running(dev))
3273 continue; 3211 continue;
3274 3212
3275 sky2_down(dev); 3213 sky2_down(dev);
3276 netif_device_detach(dev); 3214 netif_device_detach(dev);
3277 } 3215 }
3278 } 3216 }
3279 3217
3280 return sky2_set_power_state(hw, pci_choose_state(pdev, state)); 3218 return sky2_set_power_state(hw, pci_choose_state(pdev, state));
3281 } 3219 }
3282 3220
3283 static int sky2_resume(struct pci_dev *pdev) 3221 static int sky2_resume(struct pci_dev *pdev)
3284 { 3222 {
3285 struct sky2_hw *hw = pci_get_drvdata(pdev); 3223 struct sky2_hw *hw = pci_get_drvdata(pdev);
3286 int i, err; 3224 int i, err;
3287 3225
3288 pci_restore_state(pdev); 3226 pci_restore_state(pdev);
3289 pci_enable_wake(pdev, PCI_D0, 0); 3227 pci_enable_wake(pdev, PCI_D0, 0);
3290 err = sky2_set_power_state(hw, PCI_D0); 3228 err = sky2_set_power_state(hw, PCI_D0);
3291 if (err) 3229 if (err)
3292 goto out; 3230 goto out;
3293 3231
3294 err = sky2_reset(hw); 3232 err = sky2_reset(hw);
1 /* 1 /*
2 * Definitions for the new Marvell Yukon 2 driver. 2 * Definitions for the new Marvell Yukon 2 driver.
3 */ 3 */
4 #ifndef _SKY2_H 4 #ifndef _SKY2_H
5 #define _SKY2_H 5 #define _SKY2_H
6 6
7 /* PCI config registers */ 7 /* PCI config registers */
8 enum { 8 enum {
9 PCI_DEV_REG1 = 0x40, 9 PCI_DEV_REG1 = 0x40,
10 PCI_DEV_REG2 = 0x44, 10 PCI_DEV_REG2 = 0x44,
11 PCI_DEV_STATUS = 0x7c, 11 PCI_DEV_STATUS = 0x7c,
12 PCI_DEV_REG3 = 0x80, 12 PCI_DEV_REG3 = 0x80,
13 PCI_DEV_REG4 = 0x84, 13 PCI_DEV_REG4 = 0x84,
14 PCI_DEV_REG5 = 0x88, 14 PCI_DEV_REG5 = 0x88,
15 }; 15 };
16 16
17 enum { 17 enum {
18 PEX_DEV_CAP = 0xe4, 18 PEX_DEV_CAP = 0xe4,
19 PEX_DEV_CTRL = 0xe8, 19 PEX_DEV_CTRL = 0xe8,
20 PEX_DEV_STA = 0xea, 20 PEX_DEV_STA = 0xea,
21 PEX_LNK_STAT = 0xf2, 21 PEX_LNK_STAT = 0xf2,
22 PEX_UNC_ERR_STAT= 0x104, 22 PEX_UNC_ERR_STAT= 0x104,
23 }; 23 };
24 24
25 /* Yukon-2 */ 25 /* Yukon-2 */
26 enum pci_dev_reg_1 { 26 enum pci_dev_reg_1 {
27 PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */ 27 PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */
28 PCI_Y2_DLL_DIS = 1<<30, /* Disable PCI DLL (YUKON-2) */ 28 PCI_Y2_DLL_DIS = 1<<30, /* Disable PCI DLL (YUKON-2) */
29 PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */ 29 PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */
30 PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */ 30 PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */
31 PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */ 31 PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */
32 PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */ 32 PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */
33 }; 33 };
34 34
35 enum pci_dev_reg_2 { 35 enum pci_dev_reg_2 {
36 PCI_VPD_WR_THR = 0xffL<<24, /* Bit 31..24: VPD Write Threshold */ 36 PCI_VPD_WR_THR = 0xffL<<24, /* Bit 31..24: VPD Write Threshold */
37 PCI_DEV_SEL = 0x7fL<<17, /* Bit 23..17: EEPROM Device Select */ 37 PCI_DEV_SEL = 0x7fL<<17, /* Bit 23..17: EEPROM Device Select */
38 PCI_VPD_ROM_SZ = 7L<<14, /* Bit 16..14: VPD ROM Size */ 38 PCI_VPD_ROM_SZ = 7L<<14, /* Bit 16..14: VPD ROM Size */
39 39
40 PCI_PATCH_DIR = 0xfL<<8, /* Bit 11.. 8: Ext Patches dir 3..0 */ 40 PCI_PATCH_DIR = 0xfL<<8, /* Bit 11.. 8: Ext Patches dir 3..0 */
41 PCI_EXT_PATCHS = 0xfL<<4, /* Bit 7.. 4: Extended Patches 3..0 */ 41 PCI_EXT_PATCHS = 0xfL<<4, /* Bit 7.. 4: Extended Patches 3..0 */
42 PCI_EN_DUMMY_RD = 1<<3, /* Enable Dummy Read */ 42 PCI_EN_DUMMY_RD = 1<<3, /* Enable Dummy Read */
43 PCI_REV_DESC = 1<<2, /* Reverse Desc. Bytes */ 43 PCI_REV_DESC = 1<<2, /* Reverse Desc. Bytes */
44 44
45 PCI_USEDATA64 = 1<<0, /* Use 64Bit Data bus ext */ 45 PCI_USEDATA64 = 1<<0, /* Use 64Bit Data bus ext */
46 }; 46 };
47 47
48 /* PCI_OUR_REG_4 32 bit Our Register 4 (Yukon-ECU only) */ 48 /* PCI_OUR_REG_4 32 bit Our Register 4 (Yukon-ECU only) */
49 enum pci_dev_reg_4 { 49 enum pci_dev_reg_4 {
50 /* (Link Training & Status State Machine) */ 50 /* (Link Training & Status State Machine) */
51 P_TIMER_VALUE_MSK = 0xffL<<16, /* Bit 23..16: Timer Value Mask */ 51 P_TIMER_VALUE_MSK = 0xffL<<16, /* Bit 23..16: Timer Value Mask */
52 /* (Active State Power Management) */ 52 /* (Active State Power Management) */
53 P_FORCE_ASPM_REQUEST = 1<<15, /* Force ASPM Request (A1 only) */ 53 P_FORCE_ASPM_REQUEST = 1<<15, /* Force ASPM Request (A1 only) */
54 P_ASPM_GPHY_LINK_DOWN = 1<<14, /* GPHY Link Down (A1 only) */ 54 P_ASPM_GPHY_LINK_DOWN = 1<<14, /* GPHY Link Down (A1 only) */
55 P_ASPM_INT_FIFO_EMPTY = 1<<13, /* Internal FIFO Empty (A1 only) */ 55 P_ASPM_INT_FIFO_EMPTY = 1<<13, /* Internal FIFO Empty (A1 only) */
56 P_ASPM_CLKRUN_REQUEST = 1<<12, /* CLKRUN Request (A1 only) */ 56 P_ASPM_CLKRUN_REQUEST = 1<<12, /* CLKRUN Request (A1 only) */
57 57
58 P_ASPM_FORCE_CLKREQ_ENA = 1<<4, /* Force CLKREQ Enable (A1b only) */ 58 P_ASPM_FORCE_CLKREQ_ENA = 1<<4, /* Force CLKREQ Enable (A1b only) */
59 P_ASPM_CLKREQ_PAD_CTL = 1<<3, /* CLKREQ PAD Control (A1 only) */ 59 P_ASPM_CLKREQ_PAD_CTL = 1<<3, /* CLKREQ PAD Control (A1 only) */
60 P_ASPM_A1_MODE_SELECT = 1<<2, /* A1 Mode Select (A1 only) */ 60 P_ASPM_A1_MODE_SELECT = 1<<2, /* A1 Mode Select (A1 only) */
61 P_CLK_GATE_PEX_UNIT_ENA = 1<<1, /* Enable Gate PEX Unit Clock */ 61 P_CLK_GATE_PEX_UNIT_ENA = 1<<1, /* Enable Gate PEX Unit Clock */
62 P_CLK_GATE_ROOT_COR_ENA = 1<<0, /* Enable Gate Root Core Clock */ 62 P_CLK_GATE_ROOT_COR_ENA = 1<<0, /* Enable Gate Root Core Clock */
63 P_ASPM_CONTROL_MSK = P_FORCE_ASPM_REQUEST | P_ASPM_GPHY_LINK_DOWN 63 P_ASPM_CONTROL_MSK = P_FORCE_ASPM_REQUEST | P_ASPM_GPHY_LINK_DOWN
64 | P_ASPM_CLKRUN_REQUEST | P_ASPM_INT_FIFO_EMPTY, 64 | P_ASPM_CLKRUN_REQUEST | P_ASPM_INT_FIFO_EMPTY,
65 }; 65 };
66 66
67 67
68 #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \ 68 #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
69 PCI_STATUS_SIG_SYSTEM_ERROR | \ 69 PCI_STATUS_SIG_SYSTEM_ERROR | \
70 PCI_STATUS_REC_MASTER_ABORT | \ 70 PCI_STATUS_REC_MASTER_ABORT | \
71 PCI_STATUS_REC_TARGET_ABORT | \ 71 PCI_STATUS_REC_TARGET_ABORT | \
72 PCI_STATUS_PARITY) 72 PCI_STATUS_PARITY)
73 73
74 enum pex_dev_ctrl { 74 enum pex_dev_ctrl {
75 PEX_DC_MAX_RRS_MSK = 7<<12, /* Bit 14..12: Max. Read Request Size */ 75 PEX_DC_MAX_RRS_MSK = 7<<12, /* Bit 14..12: Max. Read Request Size */
76 PEX_DC_EN_NO_SNOOP = 1<<11,/* Enable No Snoop */ 76 PEX_DC_EN_NO_SNOOP = 1<<11,/* Enable No Snoop */
77 PEX_DC_EN_AUX_POW = 1<<10,/* Enable AUX Power */ 77 PEX_DC_EN_AUX_POW = 1<<10,/* Enable AUX Power */
78 PEX_DC_EN_PHANTOM = 1<<9, /* Enable Phantom Functions */ 78 PEX_DC_EN_PHANTOM = 1<<9, /* Enable Phantom Functions */
79 PEX_DC_EN_EXT_TAG = 1<<8, /* Enable Extended Tag Field */ 79 PEX_DC_EN_EXT_TAG = 1<<8, /* Enable Extended Tag Field */
80 PEX_DC_MAX_PLS_MSK = 7<<5, /* Bit 7.. 5: Max. Payload Size Mask */ 80 PEX_DC_MAX_PLS_MSK = 7<<5, /* Bit 7.. 5: Max. Payload Size Mask */
81 PEX_DC_EN_REL_ORD = 1<<4, /* Enable Relaxed Ordering */ 81 PEX_DC_EN_REL_ORD = 1<<4, /* Enable Relaxed Ordering */
82 PEX_DC_EN_UNS_RQ_RP = 1<<3, /* Enable Unsupported Request Reporting */ 82 PEX_DC_EN_UNS_RQ_RP = 1<<3, /* Enable Unsupported Request Reporting */
83 PEX_DC_EN_FAT_ER_RP = 1<<2, /* Enable Fatal Error Reporting */ 83 PEX_DC_EN_FAT_ER_RP = 1<<2, /* Enable Fatal Error Reporting */
84 PEX_DC_EN_NFA_ER_RP = 1<<1, /* Enable Non-Fatal Error Reporting */ 84 PEX_DC_EN_NFA_ER_RP = 1<<1, /* Enable Non-Fatal Error Reporting */
85 PEX_DC_EN_COR_ER_RP = 1<<0, /* Enable Correctable Error Reporting */ 85 PEX_DC_EN_COR_ER_RP = 1<<0, /* Enable Correctable Error Reporting */
86 }; 86 };
87 #define PEX_DC_MAX_RD_RQ_SIZE(x) (((x)<<12) & PEX_DC_MAX_RRS_MSK) 87 #define PEX_DC_MAX_RD_RQ_SIZE(x) (((x)<<12) & PEX_DC_MAX_RRS_MSK)
88 88
89 /* PEX_UNC_ERR_STAT PEX Uncorrectable Errors Status Register (Yukon-2) */ 89 /* PEX_UNC_ERR_STAT PEX Uncorrectable Errors Status Register (Yukon-2) */
90 enum pex_err { 90 enum pex_err {
91 PEX_UNSUP_REQ = 1<<20, /* Unsupported Request Error */ 91 PEX_UNSUP_REQ = 1<<20, /* Unsupported Request Error */
92 92
93 PEX_MALFOR_TLP = 1<<18, /* Malformed TLP */ 93 PEX_MALFOR_TLP = 1<<18, /* Malformed TLP */
94 94
95 PEX_UNEXP_COMP = 1<<16, /* Unexpected Completion */ 95 PEX_UNEXP_COMP = 1<<16, /* Unexpected Completion */
96 96
97 PEX_COMP_TO = 1<<14, /* Completion Timeout */ 97 PEX_COMP_TO = 1<<14, /* Completion Timeout */
98 PEX_FLOW_CTRL_P = 1<<13, /* Flow Control Protocol Error */ 98 PEX_FLOW_CTRL_P = 1<<13, /* Flow Control Protocol Error */
99 PEX_POIS_TLP = 1<<12, /* Poisoned TLP */ 99 PEX_POIS_TLP = 1<<12, /* Poisoned TLP */
100 100
101 PEX_DATA_LINK_P = 1<<4, /* Data Link Protocol Error */ 101 PEX_DATA_LINK_P = 1<<4, /* Data Link Protocol Error */
102 PEX_FATAL_ERRORS= (PEX_MALFOR_TLP | PEX_FLOW_CTRL_P | PEX_DATA_LINK_P), 102 PEX_FATAL_ERRORS= (PEX_MALFOR_TLP | PEX_FLOW_CTRL_P | PEX_DATA_LINK_P),
103 }; 103 };
104 104
105 105
106 enum csr_regs { 106 enum csr_regs {
107 B0_RAP = 0x0000, 107 B0_RAP = 0x0000,
108 B0_CTST = 0x0004, 108 B0_CTST = 0x0004,
109 B0_Y2LED = 0x0005, 109 B0_Y2LED = 0x0005,
110 B0_POWER_CTRL = 0x0007, 110 B0_POWER_CTRL = 0x0007,
111 B0_ISRC = 0x0008, 111 B0_ISRC = 0x0008,
112 B0_IMSK = 0x000c, 112 B0_IMSK = 0x000c,
113 B0_HWE_ISRC = 0x0010, 113 B0_HWE_ISRC = 0x0010,
114 B0_HWE_IMSK = 0x0014, 114 B0_HWE_IMSK = 0x0014,
115 115
116 /* Special ISR registers (Yukon-2 only) */ 116 /* Special ISR registers (Yukon-2 only) */
117 B0_Y2_SP_ISRC2 = 0x001c, 117 B0_Y2_SP_ISRC2 = 0x001c,
118 B0_Y2_SP_ISRC3 = 0x0020, 118 B0_Y2_SP_ISRC3 = 0x0020,
119 B0_Y2_SP_EISR = 0x0024, 119 B0_Y2_SP_EISR = 0x0024,
120 B0_Y2_SP_LISR = 0x0028, 120 B0_Y2_SP_LISR = 0x0028,
121 B0_Y2_SP_ICR = 0x002c, 121 B0_Y2_SP_ICR = 0x002c,
122 122
123 B2_MAC_1 = 0x0100, 123 B2_MAC_1 = 0x0100,
124 B2_MAC_2 = 0x0108, 124 B2_MAC_2 = 0x0108,
125 B2_MAC_3 = 0x0110, 125 B2_MAC_3 = 0x0110,
126 B2_CONN_TYP = 0x0118, 126 B2_CONN_TYP = 0x0118,
127 B2_PMD_TYP = 0x0119, 127 B2_PMD_TYP = 0x0119,
128 B2_MAC_CFG = 0x011a, 128 B2_MAC_CFG = 0x011a,
129 B2_CHIP_ID = 0x011b, 129 B2_CHIP_ID = 0x011b,
130 B2_E_0 = 0x011c, 130 B2_E_0 = 0x011c,
131 131
132 B2_Y2_CLK_GATE = 0x011d, 132 B2_Y2_CLK_GATE = 0x011d,
133 B2_Y2_HW_RES = 0x011e, 133 B2_Y2_HW_RES = 0x011e,
134 B2_E_3 = 0x011f, 134 B2_E_3 = 0x011f,
135 B2_Y2_CLK_CTRL = 0x0120, 135 B2_Y2_CLK_CTRL = 0x0120,
136 136
137 B2_TI_INI = 0x0130, 137 B2_TI_INI = 0x0130,
138 B2_TI_VAL = 0x0134, 138 B2_TI_VAL = 0x0134,
139 B2_TI_CTRL = 0x0138, 139 B2_TI_CTRL = 0x0138,
140 B2_TI_TEST = 0x0139, 140 B2_TI_TEST = 0x0139,
141 141
142 B2_TST_CTRL1 = 0x0158, 142 B2_TST_CTRL1 = 0x0158,
143 B2_TST_CTRL2 = 0x0159, 143 B2_TST_CTRL2 = 0x0159,
144 B2_GP_IO = 0x015c, 144 B2_GP_IO = 0x015c,
145 145
146 B2_I2C_CTRL = 0x0160, 146 B2_I2C_CTRL = 0x0160,
147 B2_I2C_DATA = 0x0164, 147 B2_I2C_DATA = 0x0164,
148 B2_I2C_IRQ = 0x0168, 148 B2_I2C_IRQ = 0x0168,
149 B2_I2C_SW = 0x016c, 149 B2_I2C_SW = 0x016c,
150 150
151 B3_RAM_ADDR = 0x0180, 151 B3_RAM_ADDR = 0x0180,
152 B3_RAM_DATA_LO = 0x0184, 152 B3_RAM_DATA_LO = 0x0184,
153 B3_RAM_DATA_HI = 0x0188, 153 B3_RAM_DATA_HI = 0x0188,
154 154
155 /* RAM Interface Registers */ 155 /* RAM Interface Registers */
156 /* Yukon-2: use RAM_BUFFER() to access the RAM buffer */ 156 /* Yukon-2: use RAM_BUFFER() to access the RAM buffer */
157 /* 157 /*
158 * The HW-Spec. calls this registers Timeout Value 0..11. But this names are 158 * The HW-Spec. calls this registers Timeout Value 0..11. But this names are
159 * not usable in SW. Please notice these are NOT real timeouts, these are 159 * not usable in SW. Please notice these are NOT real timeouts, these are
160 * the number of qWords transferred continuously. 160 * the number of qWords transferred continuously.
161 */ 161 */
162 #define RAM_BUFFER(port, reg) (reg | (port <<6)) 162 #define RAM_BUFFER(port, reg) (reg | (port <<6))
163 163
164 B3_RI_WTO_R1 = 0x0190, 164 B3_RI_WTO_R1 = 0x0190,
165 B3_RI_WTO_XA1 = 0x0191, 165 B3_RI_WTO_XA1 = 0x0191,
166 B3_RI_WTO_XS1 = 0x0192, 166 B3_RI_WTO_XS1 = 0x0192,
167 B3_RI_RTO_R1 = 0x0193, 167 B3_RI_RTO_R1 = 0x0193,
168 B3_RI_RTO_XA1 = 0x0194, 168 B3_RI_RTO_XA1 = 0x0194,
169 B3_RI_RTO_XS1 = 0x0195, 169 B3_RI_RTO_XS1 = 0x0195,
170 B3_RI_WTO_R2 = 0x0196, 170 B3_RI_WTO_R2 = 0x0196,
171 B3_RI_WTO_XA2 = 0x0197, 171 B3_RI_WTO_XA2 = 0x0197,
172 B3_RI_WTO_XS2 = 0x0198, 172 B3_RI_WTO_XS2 = 0x0198,
173 B3_RI_RTO_R2 = 0x0199, 173 B3_RI_RTO_R2 = 0x0199,
174 B3_RI_RTO_XA2 = 0x019a, 174 B3_RI_RTO_XA2 = 0x019a,
175 B3_RI_RTO_XS2 = 0x019b, 175 B3_RI_RTO_XS2 = 0x019b,
176 B3_RI_TO_VAL = 0x019c, 176 B3_RI_TO_VAL = 0x019c,
177 B3_RI_CTRL = 0x01a0, 177 B3_RI_CTRL = 0x01a0,
178 B3_RI_TEST = 0x01a2, 178 B3_RI_TEST = 0x01a2,
179 B3_MA_TOINI_RX1 = 0x01b0, 179 B3_MA_TOINI_RX1 = 0x01b0,
180 B3_MA_TOINI_RX2 = 0x01b1, 180 B3_MA_TOINI_RX2 = 0x01b1,
181 B3_MA_TOINI_TX1 = 0x01b2, 181 B3_MA_TOINI_TX1 = 0x01b2,
182 B3_MA_TOINI_TX2 = 0x01b3, 182 B3_MA_TOINI_TX2 = 0x01b3,
183 B3_MA_TOVAL_RX1 = 0x01b4, 183 B3_MA_TOVAL_RX1 = 0x01b4,
184 B3_MA_TOVAL_RX2 = 0x01b5, 184 B3_MA_TOVAL_RX2 = 0x01b5,
185 B3_MA_TOVAL_TX1 = 0x01b6, 185 B3_MA_TOVAL_TX1 = 0x01b6,
186 B3_MA_TOVAL_TX2 = 0x01b7, 186 B3_MA_TOVAL_TX2 = 0x01b7,
187 B3_MA_TO_CTRL = 0x01b8, 187 B3_MA_TO_CTRL = 0x01b8,
188 B3_MA_TO_TEST = 0x01ba, 188 B3_MA_TO_TEST = 0x01ba,
189 B3_MA_RCINI_RX1 = 0x01c0, 189 B3_MA_RCINI_RX1 = 0x01c0,
190 B3_MA_RCINI_RX2 = 0x01c1, 190 B3_MA_RCINI_RX2 = 0x01c1,
191 B3_MA_RCINI_TX1 = 0x01c2, 191 B3_MA_RCINI_TX1 = 0x01c2,
192 B3_MA_RCINI_TX2 = 0x01c3, 192 B3_MA_RCINI_TX2 = 0x01c3,
193 B3_MA_RCVAL_RX1 = 0x01c4, 193 B3_MA_RCVAL_RX1 = 0x01c4,
194 B3_MA_RCVAL_RX2 = 0x01c5, 194 B3_MA_RCVAL_RX2 = 0x01c5,
195 B3_MA_RCVAL_TX1 = 0x01c6, 195 B3_MA_RCVAL_TX1 = 0x01c6,
196 B3_MA_RCVAL_TX2 = 0x01c7, 196 B3_MA_RCVAL_TX2 = 0x01c7,
197 B3_MA_RC_CTRL = 0x01c8, 197 B3_MA_RC_CTRL = 0x01c8,
198 B3_MA_RC_TEST = 0x01ca, 198 B3_MA_RC_TEST = 0x01ca,
199 B3_PA_TOINI_RX1 = 0x01d0, 199 B3_PA_TOINI_RX1 = 0x01d0,
200 B3_PA_TOINI_RX2 = 0x01d4, 200 B3_PA_TOINI_RX2 = 0x01d4,
201 B3_PA_TOINI_TX1 = 0x01d8, 201 B3_PA_TOINI_TX1 = 0x01d8,
202 B3_PA_TOINI_TX2 = 0x01dc, 202 B3_PA_TOINI_TX2 = 0x01dc,
203 B3_PA_TOVAL_RX1 = 0x01e0, 203 B3_PA_TOVAL_RX1 = 0x01e0,
204 B3_PA_TOVAL_RX2 = 0x01e4, 204 B3_PA_TOVAL_RX2 = 0x01e4,
205 B3_PA_TOVAL_TX1 = 0x01e8, 205 B3_PA_TOVAL_TX1 = 0x01e8,
206 B3_PA_TOVAL_TX2 = 0x01ec, 206 B3_PA_TOVAL_TX2 = 0x01ec,
207 B3_PA_CTRL = 0x01f0, 207 B3_PA_CTRL = 0x01f0,
208 B3_PA_TEST = 0x01f2, 208 B3_PA_TEST = 0x01f2,
209 209
210 Y2_CFG_SPC = 0x1c00, 210 Y2_CFG_SPC = 0x1c00,
211 }; 211 };
212 212
213 /* B0_CTST 16 bit Control/Status register */ 213 /* B0_CTST 16 bit Control/Status register */
214 enum { 214 enum {
215 Y2_VMAIN_AVAIL = 1<<17,/* VMAIN available (YUKON-2 only) */ 215 Y2_VMAIN_AVAIL = 1<<17,/* VMAIN available (YUKON-2 only) */
216 Y2_VAUX_AVAIL = 1<<16,/* VAUX available (YUKON-2 only) */ 216 Y2_VAUX_AVAIL = 1<<16,/* VAUX available (YUKON-2 only) */
217 Y2_ASF_ENABLE = 1<<13,/* ASF Unit Enable (YUKON-2 only) */ 217 Y2_ASF_ENABLE = 1<<13,/* ASF Unit Enable (YUKON-2 only) */
218 Y2_ASF_DISABLE = 1<<12,/* ASF Unit Disable (YUKON-2 only) */ 218 Y2_ASF_DISABLE = 1<<12,/* ASF Unit Disable (YUKON-2 only) */
219 Y2_CLK_RUN_ENA = 1<<11,/* CLK_RUN Enable (YUKON-2 only) */ 219 Y2_CLK_RUN_ENA = 1<<11,/* CLK_RUN Enable (YUKON-2 only) */
220 Y2_CLK_RUN_DIS = 1<<10,/* CLK_RUN Disable (YUKON-2 only) */ 220 Y2_CLK_RUN_DIS = 1<<10,/* CLK_RUN Disable (YUKON-2 only) */
221 Y2_LED_STAT_ON = 1<<9, /* Status LED On (YUKON-2 only) */ 221 Y2_LED_STAT_ON = 1<<9, /* Status LED On (YUKON-2 only) */
222 Y2_LED_STAT_OFF = 1<<8, /* Status LED Off (YUKON-2 only) */ 222 Y2_LED_STAT_OFF = 1<<8, /* Status LED Off (YUKON-2 only) */
223 223
224 CS_ST_SW_IRQ = 1<<7, /* Set IRQ SW Request */ 224 CS_ST_SW_IRQ = 1<<7, /* Set IRQ SW Request */
225 CS_CL_SW_IRQ = 1<<6, /* Clear IRQ SW Request */ 225 CS_CL_SW_IRQ = 1<<6, /* Clear IRQ SW Request */
226 CS_STOP_DONE = 1<<5, /* Stop Master is finished */ 226 CS_STOP_DONE = 1<<5, /* Stop Master is finished */
227 CS_STOP_MAST = 1<<4, /* Command Bit to stop the master */ 227 CS_STOP_MAST = 1<<4, /* Command Bit to stop the master */
228 CS_MRST_CLR = 1<<3, /* Clear Master reset */ 228 CS_MRST_CLR = 1<<3, /* Clear Master reset */
229 CS_MRST_SET = 1<<2, /* Set Master reset */ 229 CS_MRST_SET = 1<<2, /* Set Master reset */
230 CS_RST_CLR = 1<<1, /* Clear Software reset */ 230 CS_RST_CLR = 1<<1, /* Clear Software reset */
231 CS_RST_SET = 1, /* Set Software reset */ 231 CS_RST_SET = 1, /* Set Software reset */
232 }; 232 };
233 233
234 /* B0_LED 8 Bit LED register */ 234 /* B0_LED 8 Bit LED register */
235 enum { 235 enum {
236 /* Bit 7.. 2: reserved */ 236 /* Bit 7.. 2: reserved */
237 LED_STAT_ON = 1<<1, /* Status LED on */ 237 LED_STAT_ON = 1<<1, /* Status LED on */
238 LED_STAT_OFF = 1, /* Status LED off */ 238 LED_STAT_OFF = 1, /* Status LED off */
239 }; 239 };
240 240
241 /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */ 241 /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
242 enum { 242 enum {
243 PC_VAUX_ENA = 1<<7, /* Switch VAUX Enable */ 243 PC_VAUX_ENA = 1<<7, /* Switch VAUX Enable */
244 PC_VAUX_DIS = 1<<6, /* Switch VAUX Disable */ 244 PC_VAUX_DIS = 1<<6, /* Switch VAUX Disable */
245 PC_VCC_ENA = 1<<5, /* Switch VCC Enable */ 245 PC_VCC_ENA = 1<<5, /* Switch VCC Enable */
246 PC_VCC_DIS = 1<<4, /* Switch VCC Disable */ 246 PC_VCC_DIS = 1<<4, /* Switch VCC Disable */
247 PC_VAUX_ON = 1<<3, /* Switch VAUX On */ 247 PC_VAUX_ON = 1<<3, /* Switch VAUX On */
248 PC_VAUX_OFF = 1<<2, /* Switch VAUX Off */ 248 PC_VAUX_OFF = 1<<2, /* Switch VAUX Off */
249 PC_VCC_ON = 1<<1, /* Switch VCC On */ 249 PC_VCC_ON = 1<<1, /* Switch VCC On */
250 PC_VCC_OFF = 1<<0, /* Switch VCC Off */ 250 PC_VCC_OFF = 1<<0, /* Switch VCC Off */
251 }; 251 };
252 252
253 /* B2_IRQM_MSK 32 bit IRQ Moderation Mask */ 253 /* B2_IRQM_MSK 32 bit IRQ Moderation Mask */
254 254
255 /* B0_Y2_SP_ISRC2 32 bit Special Interrupt Source Reg 2 */ 255 /* B0_Y2_SP_ISRC2 32 bit Special Interrupt Source Reg 2 */
256 /* B0_Y2_SP_ISRC3 32 bit Special Interrupt Source Reg 3 */ 256 /* B0_Y2_SP_ISRC3 32 bit Special Interrupt Source Reg 3 */
257 /* B0_Y2_SP_EISR 32 bit Enter ISR Reg */ 257 /* B0_Y2_SP_EISR 32 bit Enter ISR Reg */
258 /* B0_Y2_SP_LISR 32 bit Leave ISR Reg */ 258 /* B0_Y2_SP_LISR 32 bit Leave ISR Reg */
259 enum { 259 enum {
260 Y2_IS_HW_ERR = 1<<31, /* Interrupt HW Error */ 260 Y2_IS_HW_ERR = 1<<31, /* Interrupt HW Error */
261 Y2_IS_STAT_BMU = 1<<30, /* Status BMU Interrupt */ 261 Y2_IS_STAT_BMU = 1<<30, /* Status BMU Interrupt */
262 Y2_IS_ASF = 1<<29, /* ASF subsystem Interrupt */ 262 Y2_IS_ASF = 1<<29, /* ASF subsystem Interrupt */
263 263
264 Y2_IS_POLL_CHK = 1<<27, /* Check IRQ from polling unit */ 264 Y2_IS_POLL_CHK = 1<<27, /* Check IRQ from polling unit */
265 Y2_IS_TWSI_RDY = 1<<26, /* IRQ on end of TWSI Tx */ 265 Y2_IS_TWSI_RDY = 1<<26, /* IRQ on end of TWSI Tx */
266 Y2_IS_IRQ_SW = 1<<25, /* SW forced IRQ */ 266 Y2_IS_IRQ_SW = 1<<25, /* SW forced IRQ */
267 Y2_IS_TIMINT = 1<<24, /* IRQ from Timer */ 267 Y2_IS_TIMINT = 1<<24, /* IRQ from Timer */
268 268
269 Y2_IS_IRQ_PHY2 = 1<<12, /* Interrupt from PHY 2 */ 269 Y2_IS_IRQ_PHY2 = 1<<12, /* Interrupt from PHY 2 */
270 Y2_IS_IRQ_MAC2 = 1<<11, /* Interrupt from MAC 2 */ 270 Y2_IS_IRQ_MAC2 = 1<<11, /* Interrupt from MAC 2 */
271 Y2_IS_CHK_RX2 = 1<<10, /* Descriptor error Rx 2 */ 271 Y2_IS_CHK_RX2 = 1<<10, /* Descriptor error Rx 2 */
272 Y2_IS_CHK_TXS2 = 1<<9, /* Descriptor error TXS 2 */ 272 Y2_IS_CHK_TXS2 = 1<<9, /* Descriptor error TXS 2 */
273 Y2_IS_CHK_TXA2 = 1<<8, /* Descriptor error TXA 2 */ 273 Y2_IS_CHK_TXA2 = 1<<8, /* Descriptor error TXA 2 */
274 274
275 Y2_IS_IRQ_PHY1 = 1<<4, /* Interrupt from PHY 1 */ 275 Y2_IS_IRQ_PHY1 = 1<<4, /* Interrupt from PHY 1 */
276 Y2_IS_IRQ_MAC1 = 1<<3, /* Interrupt from MAC 1 */ 276 Y2_IS_IRQ_MAC1 = 1<<3, /* Interrupt from MAC 1 */
277 Y2_IS_CHK_RX1 = 1<<2, /* Descriptor error Rx 1 */ 277 Y2_IS_CHK_RX1 = 1<<2, /* Descriptor error Rx 1 */
278 Y2_IS_CHK_TXS1 = 1<<1, /* Descriptor error TXS 1 */ 278 Y2_IS_CHK_TXS1 = 1<<1, /* Descriptor error TXS 1 */
279 Y2_IS_CHK_TXA1 = 1<<0, /* Descriptor error TXA 1 */ 279 Y2_IS_CHK_TXA1 = 1<<0, /* Descriptor error TXA 1 */
280 280
281 Y2_IS_BASE = Y2_IS_HW_ERR | Y2_IS_STAT_BMU | 281 Y2_IS_BASE = Y2_IS_HW_ERR | Y2_IS_STAT_BMU,
282 Y2_IS_POLL_CHK | Y2_IS_TWSI_RDY | 282 Y2_IS_PORT_1 = Y2_IS_IRQ_PHY1 | Y2_IS_IRQ_MAC1,
283 Y2_IS_IRQ_SW | Y2_IS_TIMINT, 283 Y2_IS_PORT_2 = Y2_IS_IRQ_PHY2 | Y2_IS_IRQ_MAC2,
284 Y2_IS_PORT_1 = Y2_IS_IRQ_PHY1 | Y2_IS_IRQ_MAC1 |
285 Y2_IS_CHK_RX1 | Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXS1,
286 Y2_IS_PORT_2 = Y2_IS_IRQ_PHY2 | Y2_IS_IRQ_MAC2 |
287 Y2_IS_CHK_RX2 | Y2_IS_CHK_TXA2 | Y2_IS_CHK_TXS2,
288 }; 284 };
289 285
290 /* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */ 286 /* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */
291 enum { 287 enum {
292 IS_ERR_MSK = 0x00003fff,/* All Error bits */ 288 IS_ERR_MSK = 0x00003fff,/* All Error bits */
293 289
294 IS_IRQ_TIST_OV = 1<<13, /* Time Stamp Timer Overflow (YUKON only) */ 290 IS_IRQ_TIST_OV = 1<<13, /* Time Stamp Timer Overflow (YUKON only) */
295 IS_IRQ_SENSOR = 1<<12, /* IRQ from Sensor (YUKON only) */ 291 IS_IRQ_SENSOR = 1<<12, /* IRQ from Sensor (YUKON only) */
296 IS_IRQ_MST_ERR = 1<<11, /* IRQ master error detected */ 292 IS_IRQ_MST_ERR = 1<<11, /* IRQ master error detected */
297 IS_IRQ_STAT = 1<<10, /* IRQ status exception */ 293 IS_IRQ_STAT = 1<<10, /* IRQ status exception */
298 IS_NO_STAT_M1 = 1<<9, /* No Rx Status from MAC 1 */ 294 IS_NO_STAT_M1 = 1<<9, /* No Rx Status from MAC 1 */
299 IS_NO_STAT_M2 = 1<<8, /* No Rx Status from MAC 2 */ 295 IS_NO_STAT_M2 = 1<<8, /* No Rx Status from MAC 2 */
300 IS_NO_TIST_M1 = 1<<7, /* No Time Stamp from MAC 1 */ 296 IS_NO_TIST_M1 = 1<<7, /* No Time Stamp from MAC 1 */
301 IS_NO_TIST_M2 = 1<<6, /* No Time Stamp from MAC 2 */ 297 IS_NO_TIST_M2 = 1<<6, /* No Time Stamp from MAC 2 */
302 IS_RAM_RD_PAR = 1<<5, /* RAM Read Parity Error */ 298 IS_RAM_RD_PAR = 1<<5, /* RAM Read Parity Error */
303 IS_RAM_WR_PAR = 1<<4, /* RAM Write Parity Error */ 299 IS_RAM_WR_PAR = 1<<4, /* RAM Write Parity Error */
304 IS_M1_PAR_ERR = 1<<3, /* MAC 1 Parity Error */ 300 IS_M1_PAR_ERR = 1<<3, /* MAC 1 Parity Error */
305 IS_M2_PAR_ERR = 1<<2, /* MAC 2 Parity Error */ 301 IS_M2_PAR_ERR = 1<<2, /* MAC 2 Parity Error */
306 IS_R1_PAR_ERR = 1<<1, /* Queue R1 Parity Error */ 302 IS_R1_PAR_ERR = 1<<1, /* Queue R1 Parity Error */
307 IS_R2_PAR_ERR = 1<<0, /* Queue R2 Parity Error */ 303 IS_R2_PAR_ERR = 1<<0, /* Queue R2 Parity Error */
308 }; 304 };
309 305
310 /* Hardware error interrupt mask for Yukon 2 */ 306 /* Hardware error interrupt mask for Yukon 2 */
311 enum { 307 enum {
312 Y2_IS_TIST_OV = 1<<29,/* Time Stamp Timer overflow interrupt */ 308 Y2_IS_TIST_OV = 1<<29,/* Time Stamp Timer overflow interrupt */
313 Y2_IS_SENSOR = 1<<28, /* Sensor interrupt */ 309 Y2_IS_SENSOR = 1<<28, /* Sensor interrupt */
314 Y2_IS_MST_ERR = 1<<27, /* Master error interrupt */ 310 Y2_IS_MST_ERR = 1<<27, /* Master error interrupt */
315 Y2_IS_IRQ_STAT = 1<<26, /* Status exception interrupt */ 311 Y2_IS_IRQ_STAT = 1<<26, /* Status exception interrupt */
316 Y2_IS_PCI_EXP = 1<<25, /* PCI-Express interrupt */ 312 Y2_IS_PCI_EXP = 1<<25, /* PCI-Express interrupt */
317 Y2_IS_PCI_NEXP = 1<<24, /* PCI-Express error similar to PCI error */ 313 Y2_IS_PCI_NEXP = 1<<24, /* PCI-Express error similar to PCI error */
318 /* Link 2 */ 314 /* Link 2 */
319 Y2_IS_PAR_RD2 = 1<<13, /* Read RAM parity error interrupt */ 315 Y2_IS_PAR_RD2 = 1<<13, /* Read RAM parity error interrupt */
320 Y2_IS_PAR_WR2 = 1<<12, /* Write RAM parity error interrupt */ 316 Y2_IS_PAR_WR2 = 1<<12, /* Write RAM parity error interrupt */
321 Y2_IS_PAR_MAC2 = 1<<11, /* MAC hardware fault interrupt */ 317 Y2_IS_PAR_MAC2 = 1<<11, /* MAC hardware fault interrupt */
322 Y2_IS_PAR_RX2 = 1<<10, /* Parity Error Rx Queue 2 */ 318 Y2_IS_PAR_RX2 = 1<<10, /* Parity Error Rx Queue 2 */
323 Y2_IS_TCP_TXS2 = 1<<9, /* TCP length mismatch sync Tx queue IRQ */ 319 Y2_IS_TCP_TXS2 = 1<<9, /* TCP length mismatch sync Tx queue IRQ */
324 Y2_IS_TCP_TXA2 = 1<<8, /* TCP length mismatch async Tx queue IRQ */ 320 Y2_IS_TCP_TXA2 = 1<<8, /* TCP length mismatch async Tx queue IRQ */
325 /* Link 1 */ 321 /* Link 1 */
326 Y2_IS_PAR_RD1 = 1<<5, /* Read RAM parity error interrupt */ 322 Y2_IS_PAR_RD1 = 1<<5, /* Read RAM parity error interrupt */
327 Y2_IS_PAR_WR1 = 1<<4, /* Write RAM parity error interrupt */ 323 Y2_IS_PAR_WR1 = 1<<4, /* Write RAM parity error interrupt */
328 Y2_IS_PAR_MAC1 = 1<<3, /* MAC hardware fault interrupt */ 324 Y2_IS_PAR_MAC1 = 1<<3, /* MAC hardware fault interrupt */
329 Y2_IS_PAR_RX1 = 1<<2, /* Parity Error Rx Queue 1 */ 325 Y2_IS_PAR_RX1 = 1<<2, /* Parity Error Rx Queue 1 */
330 Y2_IS_TCP_TXS1 = 1<<1, /* TCP length mismatch sync Tx queue IRQ */ 326 Y2_IS_TCP_TXS1 = 1<<1, /* TCP length mismatch sync Tx queue IRQ */
331 Y2_IS_TCP_TXA1 = 1<<0, /* TCP length mismatch async Tx queue IRQ */ 327 Y2_IS_TCP_TXA1 = 1<<0, /* TCP length mismatch async Tx queue IRQ */
332 328
333 Y2_HWE_L1_MASK = Y2_IS_PAR_RD1 | Y2_IS_PAR_WR1 | Y2_IS_PAR_MAC1 | 329 Y2_HWE_L1_MASK = Y2_IS_PAR_RD1 | Y2_IS_PAR_WR1 | Y2_IS_PAR_MAC1 |
334 Y2_IS_PAR_RX1 | Y2_IS_TCP_TXS1| Y2_IS_TCP_TXA1, 330 Y2_IS_PAR_RX1 | Y2_IS_TCP_TXS1| Y2_IS_TCP_TXA1,
335 Y2_HWE_L2_MASK = Y2_IS_PAR_RD2 | Y2_IS_PAR_WR2 | Y2_IS_PAR_MAC2 | 331 Y2_HWE_L2_MASK = Y2_IS_PAR_RD2 | Y2_IS_PAR_WR2 | Y2_IS_PAR_MAC2 |
336 Y2_IS_PAR_RX2 | Y2_IS_TCP_TXS2| Y2_IS_TCP_TXA2, 332 Y2_IS_PAR_RX2 | Y2_IS_TCP_TXS2| Y2_IS_TCP_TXA2,
337 333
338 Y2_HWE_ALL_MASK = Y2_IS_TIST_OV | Y2_IS_MST_ERR | Y2_IS_IRQ_STAT | 334 Y2_HWE_ALL_MASK = Y2_IS_TIST_OV | Y2_IS_MST_ERR | Y2_IS_IRQ_STAT |
339 Y2_IS_PCI_EXP | 335 Y2_IS_PCI_EXP |
340 Y2_HWE_L1_MASK | Y2_HWE_L2_MASK, 336 Y2_HWE_L1_MASK | Y2_HWE_L2_MASK,
341 }; 337 };
342 338
343 /* B28_DPT_CTRL 8 bit Descriptor Poll Timer Ctrl Reg */ 339 /* B28_DPT_CTRL 8 bit Descriptor Poll Timer Ctrl Reg */
344 enum { 340 enum {
345 DPT_START = 1<<1, 341 DPT_START = 1<<1,
346 DPT_STOP = 1<<0, 342 DPT_STOP = 1<<0,
347 }; 343 };
348 344
349 /* B2_TST_CTRL1 8 bit Test Control Register 1 */ 345 /* B2_TST_CTRL1 8 bit Test Control Register 1 */
350 enum { 346 enum {
351 TST_FRC_DPERR_MR = 1<<7, /* force DATAPERR on MST RD */ 347 TST_FRC_DPERR_MR = 1<<7, /* force DATAPERR on MST RD */
352 TST_FRC_DPERR_MW = 1<<6, /* force DATAPERR on MST WR */ 348 TST_FRC_DPERR_MW = 1<<6, /* force DATAPERR on MST WR */
353 TST_FRC_DPERR_TR = 1<<5, /* force DATAPERR on TRG RD */ 349 TST_FRC_DPERR_TR = 1<<5, /* force DATAPERR on TRG RD */
354 TST_FRC_DPERR_TW = 1<<4, /* force DATAPERR on TRG WR */ 350 TST_FRC_DPERR_TW = 1<<4, /* force DATAPERR on TRG WR */
355 TST_FRC_APERR_M = 1<<3, /* force ADDRPERR on MST */ 351 TST_FRC_APERR_M = 1<<3, /* force ADDRPERR on MST */
356 TST_FRC_APERR_T = 1<<2, /* force ADDRPERR on TRG */ 352 TST_FRC_APERR_T = 1<<2, /* force ADDRPERR on TRG */
357 TST_CFG_WRITE_ON = 1<<1, /* Enable Config Reg WR */ 353 TST_CFG_WRITE_ON = 1<<1, /* Enable Config Reg WR */
358 TST_CFG_WRITE_OFF= 1<<0, /* Disable Config Reg WR */ 354 TST_CFG_WRITE_OFF= 1<<0, /* Disable Config Reg WR */
359 }; 355 };
360 356
361 /* B2_MAC_CFG 8 bit MAC Configuration / Chip Revision */ 357 /* B2_MAC_CFG 8 bit MAC Configuration / Chip Revision */
362 enum { 358 enum {
363 CFG_CHIP_R_MSK = 0xf<<4, /* Bit 7.. 4: Chip Revision */ 359 CFG_CHIP_R_MSK = 0xf<<4, /* Bit 7.. 4: Chip Revision */
364 /* Bit 3.. 2: reserved */ 360 /* Bit 3.. 2: reserved */
365 CFG_DIS_M2_CLK = 1<<1, /* Disable Clock for 2nd MAC */ 361 CFG_DIS_M2_CLK = 1<<1, /* Disable Clock for 2nd MAC */
366 CFG_SNG_MAC = 1<<0, /* MAC Config: 0=2 MACs / 1=1 MAC*/ 362 CFG_SNG_MAC = 1<<0, /* MAC Config: 0=2 MACs / 1=1 MAC*/
367 }; 363 };
368 364
369 /* B2_CHIP_ID 8 bit Chip Identification Number */ 365 /* B2_CHIP_ID 8 bit Chip Identification Number */
370 enum { 366 enum {
371 CHIP_ID_GENESIS = 0x0a, /* Chip ID for GENESIS */ 367 CHIP_ID_GENESIS = 0x0a, /* Chip ID for GENESIS */
372 CHIP_ID_YUKON = 0xb0, /* Chip ID for YUKON */ 368 CHIP_ID_YUKON = 0xb0, /* Chip ID for YUKON */
373 CHIP_ID_YUKON_LITE = 0xb1, /* Chip ID for YUKON-Lite (Rev. A1-A3) */ 369 CHIP_ID_YUKON_LITE = 0xb1, /* Chip ID for YUKON-Lite (Rev. A1-A3) */
374 CHIP_ID_YUKON_LP = 0xb2, /* Chip ID for YUKON-LP */ 370 CHIP_ID_YUKON_LP = 0xb2, /* Chip ID for YUKON-LP */
375 CHIP_ID_YUKON_XL = 0xb3, /* Chip ID for YUKON-2 XL */ 371 CHIP_ID_YUKON_XL = 0xb3, /* Chip ID for YUKON-2 XL */
376 CHIP_ID_YUKON_EC_U = 0xb4, /* Chip ID for YUKON-2 EC Ultra */ 372 CHIP_ID_YUKON_EC_U = 0xb4, /* Chip ID for YUKON-2 EC Ultra */
377 CHIP_ID_YUKON_EC = 0xb6, /* Chip ID for YUKON-2 EC */ 373 CHIP_ID_YUKON_EC = 0xb6, /* Chip ID for YUKON-2 EC */
378 CHIP_ID_YUKON_FE = 0xb7, /* Chip ID for YUKON-2 FE */ 374 CHIP_ID_YUKON_FE = 0xb7, /* Chip ID for YUKON-2 FE */
379 375
380 CHIP_REV_YU_EC_A1 = 0, /* Chip Rev. for Yukon-EC A1/A0 */ 376 CHIP_REV_YU_EC_A1 = 0, /* Chip Rev. for Yukon-EC A1/A0 */
381 CHIP_REV_YU_EC_A2 = 1, /* Chip Rev. for Yukon-EC A2 */ 377 CHIP_REV_YU_EC_A2 = 1, /* Chip Rev. for Yukon-EC A2 */
382 CHIP_REV_YU_EC_A3 = 2, /* Chip Rev. for Yukon-EC A3 */ 378 CHIP_REV_YU_EC_A3 = 2, /* Chip Rev. for Yukon-EC A3 */
383 }; 379 };
384 380
385 /* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */ 381 /* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */
386 enum { 382 enum {
387 Y2_STATUS_LNK2_INAC = 1<<7, /* Status Link 2 inactive (0 = active) */ 383 Y2_STATUS_LNK2_INAC = 1<<7, /* Status Link 2 inactive (0 = active) */
388 Y2_CLK_GAT_LNK2_DIS = 1<<6, /* Disable clock gating Link 2 */ 384 Y2_CLK_GAT_LNK2_DIS = 1<<6, /* Disable clock gating Link 2 */
389 Y2_COR_CLK_LNK2_DIS = 1<<5, /* Disable Core clock Link 2 */ 385 Y2_COR_CLK_LNK2_DIS = 1<<5, /* Disable Core clock Link 2 */
390 Y2_PCI_CLK_LNK2_DIS = 1<<4, /* Disable PCI clock Link 2 */ 386 Y2_PCI_CLK_LNK2_DIS = 1<<4, /* Disable PCI clock Link 2 */
391 Y2_STATUS_LNK1_INAC = 1<<3, /* Status Link 1 inactive (0 = active) */ 387 Y2_STATUS_LNK1_INAC = 1<<3, /* Status Link 1 inactive (0 = active) */
392 Y2_CLK_GAT_LNK1_DIS = 1<<2, /* Disable clock gating Link 1 */ 388 Y2_CLK_GAT_LNK1_DIS = 1<<2, /* Disable clock gating Link 1 */
393 Y2_COR_CLK_LNK1_DIS = 1<<1, /* Disable Core clock Link 1 */ 389 Y2_COR_CLK_LNK1_DIS = 1<<1, /* Disable Core clock Link 1 */
394 Y2_PCI_CLK_LNK1_DIS = 1<<0, /* Disable PCI clock Link 1 */ 390 Y2_PCI_CLK_LNK1_DIS = 1<<0, /* Disable PCI clock Link 1 */
395 }; 391 };
396 392
397 /* B2_Y2_HW_RES 8 bit HW Resources (Yukon-2 only) */ 393 /* B2_Y2_HW_RES 8 bit HW Resources (Yukon-2 only) */
398 enum { 394 enum {
399 CFG_LED_MODE_MSK = 7<<2, /* Bit 4.. 2: LED Mode Mask */ 395 CFG_LED_MODE_MSK = 7<<2, /* Bit 4.. 2: LED Mode Mask */
400 CFG_LINK_2_AVAIL = 1<<1, /* Link 2 available */ 396 CFG_LINK_2_AVAIL = 1<<1, /* Link 2 available */
401 CFG_LINK_1_AVAIL = 1<<0, /* Link 1 available */ 397 CFG_LINK_1_AVAIL = 1<<0, /* Link 1 available */
402 }; 398 };
403 #define CFG_LED_MODE(x) (((x) & CFG_LED_MODE_MSK) >> 2) 399 #define CFG_LED_MODE(x) (((x) & CFG_LED_MODE_MSK) >> 2)
404 #define CFG_DUAL_MAC_MSK (CFG_LINK_2_AVAIL | CFG_LINK_1_AVAIL) 400 #define CFG_DUAL_MAC_MSK (CFG_LINK_2_AVAIL | CFG_LINK_1_AVAIL)
405 401
406 402
407 /* B2_Y2_CLK_CTRL 32 bit Clock Frequency Control Register (Yukon-2/EC) */ 403 /* B2_Y2_CLK_CTRL 32 bit Clock Frequency Control Register (Yukon-2/EC) */
408 enum { 404 enum {
409 Y2_CLK_DIV_VAL_MSK = 0xff<<16,/* Bit 23..16: Clock Divisor Value */ 405 Y2_CLK_DIV_VAL_MSK = 0xff<<16,/* Bit 23..16: Clock Divisor Value */
410 #define Y2_CLK_DIV_VAL(x) (((x)<<16) & Y2_CLK_DIV_VAL_MSK) 406 #define Y2_CLK_DIV_VAL(x) (((x)<<16) & Y2_CLK_DIV_VAL_MSK)
411 Y2_CLK_DIV_VAL2_MSK = 7<<21, /* Bit 23..21: Clock Divisor Value */ 407 Y2_CLK_DIV_VAL2_MSK = 7<<21, /* Bit 23..21: Clock Divisor Value */
412 Y2_CLK_SELECT2_MSK = 0x1f<<16,/* Bit 20..16: Clock Select */ 408 Y2_CLK_SELECT2_MSK = 0x1f<<16,/* Bit 20..16: Clock Select */
413 #define Y2_CLK_DIV_VAL_2(x) (((x)<<21) & Y2_CLK_DIV_VAL2_MSK) 409 #define Y2_CLK_DIV_VAL_2(x) (((x)<<21) & Y2_CLK_DIV_VAL2_MSK)
414 #define Y2_CLK_SEL_VAL_2(x) (((x)<<16) & Y2_CLK_SELECT2_MSK) 410 #define Y2_CLK_SEL_VAL_2(x) (((x)<<16) & Y2_CLK_SELECT2_MSK)
415 Y2_CLK_DIV_ENA = 1<<1, /* Enable Core Clock Division */ 411 Y2_CLK_DIV_ENA = 1<<1, /* Enable Core Clock Division */
416 Y2_CLK_DIV_DIS = 1<<0, /* Disable Core Clock Division */ 412 Y2_CLK_DIV_DIS = 1<<0, /* Disable Core Clock Division */
417 }; 413 };
418 414
419 /* B2_TI_CTRL 8 bit Timer control */ 415 /* B2_TI_CTRL 8 bit Timer control */
420 /* B2_IRQM_CTRL 8 bit IRQ Moderation Timer Control */ 416 /* B2_IRQM_CTRL 8 bit IRQ Moderation Timer Control */
421 enum { 417 enum {
422 TIM_START = 1<<2, /* Start Timer */ 418 TIM_START = 1<<2, /* Start Timer */
423 TIM_STOP = 1<<1, /* Stop Timer */ 419 TIM_STOP = 1<<1, /* Stop Timer */
424 TIM_CLR_IRQ = 1<<0, /* Clear Timer IRQ (!IRQM) */ 420 TIM_CLR_IRQ = 1<<0, /* Clear Timer IRQ (!IRQM) */
425 }; 421 };
426 422
427 /* B2_TI_TEST 8 Bit Timer Test */ 423 /* B2_TI_TEST 8 Bit Timer Test */
428 /* B2_IRQM_TEST 8 bit IRQ Moderation Timer Test */ 424 /* B2_IRQM_TEST 8 bit IRQ Moderation Timer Test */
429 /* B28_DPT_TST 8 bit Descriptor Poll Timer Test Reg */ 425 /* B28_DPT_TST 8 bit Descriptor Poll Timer Test Reg */
430 enum { 426 enum {
431 TIM_T_ON = 1<<2, /* Test mode on */ 427 TIM_T_ON = 1<<2, /* Test mode on */
432 TIM_T_OFF = 1<<1, /* Test mode off */ 428 TIM_T_OFF = 1<<1, /* Test mode off */
433 TIM_T_STEP = 1<<0, /* Test step */ 429 TIM_T_STEP = 1<<0, /* Test step */
434 }; 430 };
435 431
436 /* B3_RAM_ADDR 32 bit RAM Address, to read or write */ 432 /* B3_RAM_ADDR 32 bit RAM Address, to read or write */
437 /* Bit 31..19: reserved */ 433 /* Bit 31..19: reserved */
438 #define RAM_ADR_RAN 0x0007ffffL /* Bit 18.. 0: RAM Address Range */ 434 #define RAM_ADR_RAN 0x0007ffffL /* Bit 18.. 0: RAM Address Range */
439 /* RAM Interface Registers */ 435 /* RAM Interface Registers */
440 436
441 /* B3_RI_CTRL 16 bit RAM Interface Control Register */ 437 /* B3_RI_CTRL 16 bit RAM Interface Control Register */
442 enum { 438 enum {
443 RI_CLR_RD_PERR = 1<<9, /* Clear IRQ RAM Read Parity Err */ 439 RI_CLR_RD_PERR = 1<<9, /* Clear IRQ RAM Read Parity Err */
444 RI_CLR_WR_PERR = 1<<8, /* Clear IRQ RAM Write Parity Err*/ 440 RI_CLR_WR_PERR = 1<<8, /* Clear IRQ RAM Write Parity Err*/
445 441
446 RI_RST_CLR = 1<<1, /* Clear RAM Interface Reset */ 442 RI_RST_CLR = 1<<1, /* Clear RAM Interface Reset */
447 RI_RST_SET = 1<<0, /* Set RAM Interface Reset */ 443 RI_RST_SET = 1<<0, /* Set RAM Interface Reset */
448 }; 444 };
449 445
450 #define SK_RI_TO_53 36 /* RAM interface timeout */ 446 #define SK_RI_TO_53 36 /* RAM interface timeout */
451 447
452 448
453 /* Port related registers FIFO, and Arbiter */ 449 /* Port related registers FIFO, and Arbiter */
454 #define SK_REG(port,reg) (((port)<<7)+(reg)) 450 #define SK_REG(port,reg) (((port)<<7)+(reg))
455 451
456 /* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */ 452 /* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
457 /* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */ 453 /* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */
458 /* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */ 454 /* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */
459 /* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */ 455 /* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */
460 /* TXA_LIM_VAL 32 bit Tx Arb Limit Counter Value */ 456 /* TXA_LIM_VAL 32 bit Tx Arb Limit Counter Value */
461 457
462 #define TXA_MAX_VAL 0x00ffffffUL /* Bit 23.. 0: Max TXA Timer/Cnt Val */ 458 #define TXA_MAX_VAL 0x00ffffffUL /* Bit 23.. 0: Max TXA Timer/Cnt Val */
463 459
464 /* TXA_CTRL 8 bit Tx Arbiter Control Register */ 460 /* TXA_CTRL 8 bit Tx Arbiter Control Register */
465 enum { 461 enum {
466 TXA_ENA_FSYNC = 1<<7, /* Enable force of sync Tx queue */ 462 TXA_ENA_FSYNC = 1<<7, /* Enable force of sync Tx queue */
467 TXA_DIS_FSYNC = 1<<6, /* Disable force of sync Tx queue */ 463 TXA_DIS_FSYNC = 1<<6, /* Disable force of sync Tx queue */
468 TXA_ENA_ALLOC = 1<<5, /* Enable alloc of free bandwidth */ 464 TXA_ENA_ALLOC = 1<<5, /* Enable alloc of free bandwidth */
469 TXA_DIS_ALLOC = 1<<4, /* Disable alloc of free bandwidth */ 465 TXA_DIS_ALLOC = 1<<4, /* Disable alloc of free bandwidth */
470 TXA_START_RC = 1<<3, /* Start sync Rate Control */ 466 TXA_START_RC = 1<<3, /* Start sync Rate Control */
471 TXA_STOP_RC = 1<<2, /* Stop sync Rate Control */ 467 TXA_STOP_RC = 1<<2, /* Stop sync Rate Control */
472 TXA_ENA_ARB = 1<<1, /* Enable Tx Arbiter */ 468 TXA_ENA_ARB = 1<<1, /* Enable Tx Arbiter */
473 TXA_DIS_ARB = 1<<0, /* Disable Tx Arbiter */ 469 TXA_DIS_ARB = 1<<0, /* Disable Tx Arbiter */
474 }; 470 };
475 471
476 /* 472 /*
477 * Bank 4 - 5 473 * Bank 4 - 5
478 */ 474 */
479 /* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */ 475 /* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
480 enum { 476 enum {
481 TXA_ITI_INI = 0x0200,/* 32 bit Tx Arb Interval Timer Init Val*/ 477 TXA_ITI_INI = 0x0200,/* 32 bit Tx Arb Interval Timer Init Val*/
482 TXA_ITI_VAL = 0x0204,/* 32 bit Tx Arb Interval Timer Value */ 478 TXA_ITI_VAL = 0x0204,/* 32 bit Tx Arb Interval Timer Value */
483 TXA_LIM_INI = 0x0208,/* 32 bit Tx Arb Limit Counter Init Val */ 479 TXA_LIM_INI = 0x0208,/* 32 bit Tx Arb Limit Counter Init Val */
484 TXA_LIM_VAL = 0x020c,/* 32 bit Tx Arb Limit Counter Value */ 480 TXA_LIM_VAL = 0x020c,/* 32 bit Tx Arb Limit Counter Value */
485 TXA_CTRL = 0x0210,/* 8 bit Tx Arbiter Control Register */ 481 TXA_CTRL = 0x0210,/* 8 bit Tx Arbiter Control Register */
486 TXA_TEST = 0x0211,/* 8 bit Tx Arbiter Test Register */ 482 TXA_TEST = 0x0211,/* 8 bit Tx Arbiter Test Register */
487 TXA_STAT = 0x0212,/* 8 bit Tx Arbiter Status Register */ 483 TXA_STAT = 0x0212,/* 8 bit Tx Arbiter Status Register */
488 }; 484 };
489 485
490 486
491 enum { 487 enum {
492 B6_EXT_REG = 0x0300,/* External registers (GENESIS only) */ 488 B6_EXT_REG = 0x0300,/* External registers (GENESIS only) */
493 B7_CFG_SPC = 0x0380,/* copy of the Configuration register */ 489 B7_CFG_SPC = 0x0380,/* copy of the Configuration register */
494 B8_RQ1_REGS = 0x0400,/* Receive Queue 1 */ 490 B8_RQ1_REGS = 0x0400,/* Receive Queue 1 */
495 B8_RQ2_REGS = 0x0480,/* Receive Queue 2 */ 491 B8_RQ2_REGS = 0x0480,/* Receive Queue 2 */
496 B8_TS1_REGS = 0x0600,/* Transmit sync queue 1 */ 492 B8_TS1_REGS = 0x0600,/* Transmit sync queue 1 */
497 B8_TA1_REGS = 0x0680,/* Transmit async queue 1 */ 493 B8_TA1_REGS = 0x0680,/* Transmit async queue 1 */
498 B8_TS2_REGS = 0x0700,/* Transmit sync queue 2 */ 494 B8_TS2_REGS = 0x0700,/* Transmit sync queue 2 */
499 B8_TA2_REGS = 0x0780,/* Transmit sync queue 2 */ 495 B8_TA2_REGS = 0x0780,/* Transmit sync queue 2 */
500 B16_RAM_REGS = 0x0800,/* RAM Buffer Registers */ 496 B16_RAM_REGS = 0x0800,/* RAM Buffer Registers */
501 }; 497 };
502 498
503 /* Queue Register Offsets, use Q_ADDR() to access */ 499 /* Queue Register Offsets, use Q_ADDR() to access */
504 enum { 500 enum {
505 B8_Q_REGS = 0x0400, /* base of Queue registers */ 501 B8_Q_REGS = 0x0400, /* base of Queue registers */
506 Q_D = 0x00, /* 8*32 bit Current Descriptor */ 502 Q_D = 0x00, /* 8*32 bit Current Descriptor */
507 Q_DA_L = 0x20, /* 32 bit Current Descriptor Address Low dWord */ 503 Q_DA_L = 0x20, /* 32 bit Current Descriptor Address Low dWord */
508 Q_DA_H = 0x24, /* 32 bit Current Descriptor Address High dWord */ 504 Q_DA_H = 0x24, /* 32 bit Current Descriptor Address High dWord */
509 Q_AC_L = 0x28, /* 32 bit Current Address Counter Low dWord */ 505 Q_AC_L = 0x28, /* 32 bit Current Address Counter Low dWord */
510 Q_AC_H = 0x2c, /* 32 bit Current Address Counter High dWord */ 506 Q_AC_H = 0x2c, /* 32 bit Current Address Counter High dWord */
511 Q_BC = 0x30, /* 32 bit Current Byte Counter */ 507 Q_BC = 0x30, /* 32 bit Current Byte Counter */
512 Q_CSR = 0x34, /* 32 bit BMU Control/Status Register */ 508 Q_CSR = 0x34, /* 32 bit BMU Control/Status Register */
513 Q_F = 0x38, /* 32 bit Flag Register */ 509 Q_F = 0x38, /* 32 bit Flag Register */
514 Q_T1 = 0x3c, /* 32 bit Test Register 1 */ 510 Q_T1 = 0x3c, /* 32 bit Test Register 1 */
515 Q_T1_TR = 0x3c, /* 8 bit Test Register 1 Transfer SM */ 511 Q_T1_TR = 0x3c, /* 8 bit Test Register 1 Transfer SM */
516 Q_T1_WR = 0x3d, /* 8 bit Test Register 1 Write Descriptor SM */ 512 Q_T1_WR = 0x3d, /* 8 bit Test Register 1 Write Descriptor SM */
517 Q_T1_RD = 0x3e, /* 8 bit Test Register 1 Read Descriptor SM */ 513 Q_T1_RD = 0x3e, /* 8 bit Test Register 1 Read Descriptor SM */
518 Q_T1_SV = 0x3f, /* 8 bit Test Register 1 Supervisor SM */ 514 Q_T1_SV = 0x3f, /* 8 bit Test Register 1 Supervisor SM */
519 Q_T2 = 0x40, /* 32 bit Test Register 2 */ 515 Q_T2 = 0x40, /* 32 bit Test Register 2 */
520 Q_T3 = 0x44, /* 32 bit Test Register 3 */ 516 Q_T3 = 0x44, /* 32 bit Test Register 3 */
521 517
522 /* Yukon-2 */ 518 /* Yukon-2 */
523 Q_DONE = 0x24, /* 16 bit Done Index (Yukon-2 only) */ 519 Q_DONE = 0x24, /* 16 bit Done Index (Yukon-2 only) */
524 Q_WM = 0x40, /* 16 bit FIFO Watermark */ 520 Q_WM = 0x40, /* 16 bit FIFO Watermark */
525 Q_AL = 0x42, /* 8 bit FIFO Alignment */ 521 Q_AL = 0x42, /* 8 bit FIFO Alignment */
526 Q_RSP = 0x44, /* 16 bit FIFO Read Shadow Pointer */ 522 Q_RSP = 0x44, /* 16 bit FIFO Read Shadow Pointer */
527 Q_RSL = 0x46, /* 8 bit FIFO Read Shadow Level */ 523 Q_RSL = 0x46, /* 8 bit FIFO Read Shadow Level */
528 Q_RP = 0x48, /* 8 bit FIFO Read Pointer */ 524 Q_RP = 0x48, /* 8 bit FIFO Read Pointer */
529 Q_RL = 0x4a, /* 8 bit FIFO Read Level */ 525 Q_RL = 0x4a, /* 8 bit FIFO Read Level */
530 Q_WP = 0x4c, /* 8 bit FIFO Write Pointer */ 526 Q_WP = 0x4c, /* 8 bit FIFO Write Pointer */
531 Q_WSP = 0x4d, /* 8 bit FIFO Write Shadow Pointer */ 527 Q_WSP = 0x4d, /* 8 bit FIFO Write Shadow Pointer */
532 Q_WL = 0x4e, /* 8 bit FIFO Write Level */ 528 Q_WL = 0x4e, /* 8 bit FIFO Write Level */
533 Q_WSL = 0x4f, /* 8 bit FIFO Write Shadow Level */ 529 Q_WSL = 0x4f, /* 8 bit FIFO Write Shadow Level */
534 }; 530 };
535 #define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs)) 531 #define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs))
536 532
537 /* Q_F 32 bit Flag Register */ 533 /* Q_F 32 bit Flag Register */
538 enum { 534 enum {
539 F_ALM_FULL = 1<<27, /* Rx FIFO: almost full */ 535 F_ALM_FULL = 1<<27, /* Rx FIFO: almost full */
540 F_EMPTY = 1<<27, /* Tx FIFO: empty flag */ 536 F_EMPTY = 1<<27, /* Tx FIFO: empty flag */
541 F_FIFO_EOF = 1<<26, /* Tag (EOF Flag) bit in FIFO */ 537 F_FIFO_EOF = 1<<26, /* Tag (EOF Flag) bit in FIFO */
542 F_WM_REACHED = 1<<25, /* Watermark reached */ 538 F_WM_REACHED = 1<<25, /* Watermark reached */
543 F_M_RX_RAM_DIS = 1<<24, /* MAC Rx RAM Read Port disable */ 539 F_M_RX_RAM_DIS = 1<<24, /* MAC Rx RAM Read Port disable */
544 F_FIFO_LEVEL = 0x1fL<<16, /* Bit 23..16: # of Qwords in FIFO */ 540 F_FIFO_LEVEL = 0x1fL<<16, /* Bit 23..16: # of Qwords in FIFO */
545 F_WATER_MARK = 0x0007ffL, /* Bit 10.. 0: Watermark */ 541 F_WATER_MARK = 0x0007ffL, /* Bit 10.. 0: Watermark */
546 }; 542 };
547 543
548 /* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/ 544 /* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/
549 enum { 545 enum {
550 Y2_B8_PREF_REGS = 0x0450, 546 Y2_B8_PREF_REGS = 0x0450,
551 547
552 PREF_UNIT_CTRL = 0x00, /* 32 bit Control register */ 548 PREF_UNIT_CTRL = 0x00, /* 32 bit Control register */
553 PREF_UNIT_LAST_IDX = 0x04, /* 16 bit Last Index */ 549 PREF_UNIT_LAST_IDX = 0x04, /* 16 bit Last Index */
554 PREF_UNIT_ADDR_LO = 0x08, /* 32 bit List start addr, low part */ 550 PREF_UNIT_ADDR_LO = 0x08, /* 32 bit List start addr, low part */
555 PREF_UNIT_ADDR_HI = 0x0c, /* 32 bit List start addr, high part*/ 551 PREF_UNIT_ADDR_HI = 0x0c, /* 32 bit List start addr, high part*/
556 PREF_UNIT_GET_IDX = 0x10, /* 16 bit Get Index */ 552 PREF_UNIT_GET_IDX = 0x10, /* 16 bit Get Index */
557 PREF_UNIT_PUT_IDX = 0x14, /* 16 bit Put Index */ 553 PREF_UNIT_PUT_IDX = 0x14, /* 16 bit Put Index */
558 PREF_UNIT_FIFO_WP = 0x20, /* 8 bit FIFO write pointer */ 554 PREF_UNIT_FIFO_WP = 0x20, /* 8 bit FIFO write pointer */
559 PREF_UNIT_FIFO_RP = 0x24, /* 8 bit FIFO read pointer */ 555 PREF_UNIT_FIFO_RP = 0x24, /* 8 bit FIFO read pointer */
560 PREF_UNIT_FIFO_WM = 0x28, /* 8 bit FIFO watermark */ 556 PREF_UNIT_FIFO_WM = 0x28, /* 8 bit FIFO watermark */
561 PREF_UNIT_FIFO_LEV = 0x2c, /* 8 bit FIFO level */ 557 PREF_UNIT_FIFO_LEV = 0x2c, /* 8 bit FIFO level */
562 558
563 PREF_UNIT_MASK_IDX = 0x0fff, 559 PREF_UNIT_MASK_IDX = 0x0fff,
564 }; 560 };
565 #define Y2_QADDR(q,reg) (Y2_B8_PREF_REGS + (q) + (reg)) 561 #define Y2_QADDR(q,reg) (Y2_B8_PREF_REGS + (q) + (reg))
566 562
567 /* RAM Buffer Register Offsets */ 563 /* RAM Buffer Register Offsets */
568 enum { 564 enum {
569 565
570 RB_START = 0x00,/* 32 bit RAM Buffer Start Address */ 566 RB_START = 0x00,/* 32 bit RAM Buffer Start Address */
571 RB_END = 0x04,/* 32 bit RAM Buffer End Address */ 567 RB_END = 0x04,/* 32 bit RAM Buffer End Address */
572 RB_WP = 0x08,/* 32 bit RAM Buffer Write Pointer */ 568 RB_WP = 0x08,/* 32 bit RAM Buffer Write Pointer */
573 RB_RP = 0x0c,/* 32 bit RAM Buffer Read Pointer */ 569 RB_RP = 0x0c,/* 32 bit RAM Buffer Read Pointer */
574 RB_RX_UTPP = 0x10,/* 32 bit Rx Upper Threshold, Pause Packet */ 570 RB_RX_UTPP = 0x10,/* 32 bit Rx Upper Threshold, Pause Packet */
575 RB_RX_LTPP = 0x14,/* 32 bit Rx Lower Threshold, Pause Packet */ 571 RB_RX_LTPP = 0x14,/* 32 bit Rx Lower Threshold, Pause Packet */
576 RB_RX_UTHP = 0x18,/* 32 bit Rx Upper Threshold, High Prio */ 572 RB_RX_UTHP = 0x18,/* 32 bit Rx Upper Threshold, High Prio */
577 RB_RX_LTHP = 0x1c,/* 32 bit Rx Lower Threshold, High Prio */ 573 RB_RX_LTHP = 0x1c,/* 32 bit Rx Lower Threshold, High Prio */
578 /* 0x10 - 0x1f: reserved at Tx RAM Buffer Registers */ 574 /* 0x10 - 0x1f: reserved at Tx RAM Buffer Registers */
579 RB_PC = 0x20,/* 32 bit RAM Buffer Packet Counter */ 575 RB_PC = 0x20,/* 32 bit RAM Buffer Packet Counter */
580 RB_LEV = 0x24,/* 32 bit RAM Buffer Level Register */ 576 RB_LEV = 0x24,/* 32 bit RAM Buffer Level Register */
581 RB_CTRL = 0x28,/* 32 bit RAM Buffer Control Register */ 577 RB_CTRL = 0x28,/* 32 bit RAM Buffer Control Register */
582 RB_TST1 = 0x29,/* 8 bit RAM Buffer Test Register 1 */ 578 RB_TST1 = 0x29,/* 8 bit RAM Buffer Test Register 1 */
583 RB_TST2 = 0x2a,/* 8 bit RAM Buffer Test Register 2 */ 579 RB_TST2 = 0x2a,/* 8 bit RAM Buffer Test Register 2 */
584 }; 580 };
585 581
586 /* Receive and Transmit Queues */ 582 /* Receive and Transmit Queues */
587 enum { 583 enum {
588 Q_R1 = 0x0000, /* Receive Queue 1 */ 584 Q_R1 = 0x0000, /* Receive Queue 1 */
589 Q_R2 = 0x0080, /* Receive Queue 2 */ 585 Q_R2 = 0x0080, /* Receive Queue 2 */
590 Q_XS1 = 0x0200, /* Synchronous Transmit Queue 1 */ 586 Q_XS1 = 0x0200, /* Synchronous Transmit Queue 1 */
591 Q_XA1 = 0x0280, /* Asynchronous Transmit Queue 1 */ 587 Q_XA1 = 0x0280, /* Asynchronous Transmit Queue 1 */
592 Q_XS2 = 0x0300, /* Synchronous Transmit Queue 2 */ 588 Q_XS2 = 0x0300, /* Synchronous Transmit Queue 2 */
593 Q_XA2 = 0x0380, /* Asynchronous Transmit Queue 2 */ 589 Q_XA2 = 0x0380, /* Asynchronous Transmit Queue 2 */
594 }; 590 };
595 591
596 /* Different PHY Types */ 592 /* Different PHY Types */
597 enum { 593 enum {
598 PHY_ADDR_MARV = 0, 594 PHY_ADDR_MARV = 0,
599 }; 595 };
600 596
601 #define RB_ADDR(offs, queue) (B16_RAM_REGS + (queue) + (offs)) 597 #define RB_ADDR(offs, queue) (B16_RAM_REGS + (queue) + (offs))
602 598
603 599
604 enum { 600 enum {
605 LNK_SYNC_INI = 0x0c30,/* 32 bit Link Sync Cnt Init Value */ 601 LNK_SYNC_INI = 0x0c30,/* 32 bit Link Sync Cnt Init Value */
606 LNK_SYNC_VAL = 0x0c34,/* 32 bit Link Sync Cnt Current Value */ 602 LNK_SYNC_VAL = 0x0c34,/* 32 bit Link Sync Cnt Current Value */
607 LNK_SYNC_CTRL = 0x0c38,/* 8 bit Link Sync Cnt Control Register */ 603 LNK_SYNC_CTRL = 0x0c38,/* 8 bit Link Sync Cnt Control Register */
608 LNK_SYNC_TST = 0x0c39,/* 8 bit Link Sync Cnt Test Register */ 604 LNK_SYNC_TST = 0x0c39,/* 8 bit Link Sync Cnt Test Register */
609 605
610 LNK_LED_REG = 0x0c3c,/* 8 bit Link LED Register */ 606 LNK_LED_REG = 0x0c3c,/* 8 bit Link LED Register */
611 607
612 /* Receive GMAC FIFO (YUKON and Yukon-2) */ 608 /* Receive GMAC FIFO (YUKON and Yukon-2) */
613 609
614 RX_GMF_EA = 0x0c40,/* 32 bit Rx GMAC FIFO End Address */ 610 RX_GMF_EA = 0x0c40,/* 32 bit Rx GMAC FIFO End Address */
615 RX_GMF_AF_THR = 0x0c44,/* 32 bit Rx GMAC FIFO Almost Full Thresh. */ 611 RX_GMF_AF_THR = 0x0c44,/* 32 bit Rx GMAC FIFO Almost Full Thresh. */
616 RX_GMF_CTRL_T = 0x0c48,/* 32 bit Rx GMAC FIFO Control/Test */ 612 RX_GMF_CTRL_T = 0x0c48,/* 32 bit Rx GMAC FIFO Control/Test */
617 RX_GMF_FL_MSK = 0x0c4c,/* 32 bit Rx GMAC FIFO Flush Mask */ 613 RX_GMF_FL_MSK = 0x0c4c,/* 32 bit Rx GMAC FIFO Flush Mask */
618 RX_GMF_FL_THR = 0x0c50,/* 32 bit Rx GMAC FIFO Flush Threshold */ 614 RX_GMF_FL_THR = 0x0c50,/* 32 bit Rx GMAC FIFO Flush Threshold */
619 RX_GMF_TR_THR = 0x0c54,/* 32 bit Rx Truncation Threshold (Yukon-2) */ 615 RX_GMF_TR_THR = 0x0c54,/* 32 bit Rx Truncation Threshold (Yukon-2) */
620 RX_GMF_UP_THR = 0x0c58,/* 8 bit Rx Upper Pause Thr (Yukon-EC_U) */ 616 RX_GMF_UP_THR = 0x0c58,/* 8 bit Rx Upper Pause Thr (Yukon-EC_U) */
621 RX_GMF_LP_THR = 0x0c5a,/* 8 bit Rx Lower Pause Thr (Yukon-EC_U) */ 617 RX_GMF_LP_THR = 0x0c5a,/* 8 bit Rx Lower Pause Thr (Yukon-EC_U) */
622 RX_GMF_VLAN = 0x0c5c,/* 32 bit Rx VLAN Type Register (Yukon-2) */ 618 RX_GMF_VLAN = 0x0c5c,/* 32 bit Rx VLAN Type Register (Yukon-2) */
623 RX_GMF_WP = 0x0c60,/* 32 bit Rx GMAC FIFO Write Pointer */ 619 RX_GMF_WP = 0x0c60,/* 32 bit Rx GMAC FIFO Write Pointer */
624 620
625 RX_GMF_WLEV = 0x0c68,/* 32 bit Rx GMAC FIFO Write Level */ 621 RX_GMF_WLEV = 0x0c68,/* 32 bit Rx GMAC FIFO Write Level */
626 622
627 RX_GMF_RP = 0x0c70,/* 32 bit Rx GMAC FIFO Read Pointer */ 623 RX_GMF_RP = 0x0c70,/* 32 bit Rx GMAC FIFO Read Pointer */
628 624
629 RX_GMF_RLEV = 0x0c78,/* 32 bit Rx GMAC FIFO Read Level */ 625 RX_GMF_RLEV = 0x0c78,/* 32 bit Rx GMAC FIFO Read Level */
630 }; 626 };
631 627
632 628
633 /* Q_BC 32 bit Current Byte Counter */ 629 /* Q_BC 32 bit Current Byte Counter */
634 630
635 /* BMU Control Status Registers */ 631 /* BMU Control Status Registers */
636 /* B0_R1_CSR 32 bit BMU Ctrl/Stat Rx Queue 1 */ 632 /* B0_R1_CSR 32 bit BMU Ctrl/Stat Rx Queue 1 */
637 /* B0_R2_CSR 32 bit BMU Ctrl/Stat Rx Queue 2 */ 633 /* B0_R2_CSR 32 bit BMU Ctrl/Stat Rx Queue 2 */
638 /* B0_XA1_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */ 634 /* B0_XA1_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */
639 /* B0_XS1_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 1 */ 635 /* B0_XS1_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 1 */
640 /* B0_XA2_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 2 */ 636 /* B0_XA2_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 2 */
641 /* B0_XS2_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 2 */ 637 /* B0_XS2_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 2 */
642 /* Q_CSR 32 bit BMU Control/Status Register */ 638 /* Q_CSR 32 bit BMU Control/Status Register */
643 639
644 /* Rx BMU Control / Status Registers (Yukon-2) */ 640 /* Rx BMU Control / Status Registers (Yukon-2) */
645 enum { 641 enum {
646 BMU_IDLE = 1<<31, /* BMU Idle State */ 642 BMU_IDLE = 1<<31, /* BMU Idle State */
647 BMU_RX_TCP_PKT = 1<<30, /* Rx TCP Packet (when RSS Hash enabled) */ 643 BMU_RX_TCP_PKT = 1<<30, /* Rx TCP Packet (when RSS Hash enabled) */
648 BMU_RX_IP_PKT = 1<<29, /* Rx IP Packet (when RSS Hash enabled) */ 644 BMU_RX_IP_PKT = 1<<29, /* Rx IP Packet (when RSS Hash enabled) */
649 645
650 BMU_ENA_RX_RSS_HASH = 1<<15, /* Enable Rx RSS Hash */ 646 BMU_ENA_RX_RSS_HASH = 1<<15, /* Enable Rx RSS Hash */
651 BMU_DIS_RX_RSS_HASH = 1<<14, /* Disable Rx RSS Hash */ 647 BMU_DIS_RX_RSS_HASH = 1<<14, /* Disable Rx RSS Hash */
652 BMU_ENA_RX_CHKSUM = 1<<13, /* Enable Rx TCP/IP Checksum Check */ 648 BMU_ENA_RX_CHKSUM = 1<<13, /* Enable Rx TCP/IP Checksum Check */
653 BMU_DIS_RX_CHKSUM = 1<<12, /* Disable Rx TCP/IP Checksum Check */ 649 BMU_DIS_RX_CHKSUM = 1<<12, /* Disable Rx TCP/IP Checksum Check */
654 BMU_CLR_IRQ_PAR = 1<<11, /* Clear IRQ on Parity errors (Rx) */ 650 BMU_CLR_IRQ_PAR = 1<<11, /* Clear IRQ on Parity errors (Rx) */
655 BMU_CLR_IRQ_TCP = 1<<11, /* Clear IRQ on TCP segment. error (Tx) */ 651 BMU_CLR_IRQ_TCP = 1<<11, /* Clear IRQ on TCP segment. error (Tx) */
656 BMU_CLR_IRQ_CHK = 1<<10, /* Clear IRQ Check */ 652 BMU_CLR_IRQ_CHK = 1<<10, /* Clear IRQ Check */
657 BMU_STOP = 1<<9, /* Stop Rx/Tx Queue */ 653 BMU_STOP = 1<<9, /* Stop Rx/Tx Queue */
658 BMU_START = 1<<8, /* Start Rx/Tx Queue */ 654 BMU_START = 1<<8, /* Start Rx/Tx Queue */
659 BMU_FIFO_OP_ON = 1<<7, /* FIFO Operational On */ 655 BMU_FIFO_OP_ON = 1<<7, /* FIFO Operational On */
660 BMU_FIFO_OP_OFF = 1<<6, /* FIFO Operational Off */ 656 BMU_FIFO_OP_OFF = 1<<6, /* FIFO Operational Off */
661 BMU_FIFO_ENA = 1<<5, /* Enable FIFO */ 657 BMU_FIFO_ENA = 1<<5, /* Enable FIFO */
662 BMU_FIFO_RST = 1<<4, /* Reset FIFO */ 658 BMU_FIFO_RST = 1<<4, /* Reset FIFO */
663 BMU_OP_ON = 1<<3, /* BMU Operational On */ 659 BMU_OP_ON = 1<<3, /* BMU Operational On */
664 BMU_OP_OFF = 1<<2, /* BMU Operational Off */ 660 BMU_OP_OFF = 1<<2, /* BMU Operational Off */
665 BMU_RST_CLR = 1<<1, /* Clear BMU Reset (Enable) */ 661 BMU_RST_CLR = 1<<1, /* Clear BMU Reset (Enable) */
666 BMU_RST_SET = 1<<0, /* Set BMU Reset */ 662 BMU_RST_SET = 1<<0, /* Set BMU Reset */
667 663
668 BMU_CLR_RESET = BMU_FIFO_RST | BMU_OP_OFF | BMU_RST_CLR, 664 BMU_CLR_RESET = BMU_FIFO_RST | BMU_OP_OFF | BMU_RST_CLR,
669 BMU_OPER_INIT = BMU_CLR_IRQ_PAR | BMU_CLR_IRQ_CHK | BMU_START | 665 BMU_OPER_INIT = BMU_CLR_IRQ_PAR | BMU_CLR_IRQ_CHK | BMU_START |
670 BMU_FIFO_ENA | BMU_OP_ON, 666 BMU_FIFO_ENA | BMU_OP_ON,
671 667
672 BMU_WM_DEFAULT = 0x600, 668 BMU_WM_DEFAULT = 0x600,
673 }; 669 };
674 670
675 /* Tx BMU Control / Status Registers (Yukon-2) */ 671 /* Tx BMU Control / Status Registers (Yukon-2) */
676 /* Bit 31: same as for Rx */ 672 /* Bit 31: same as for Rx */
677 enum { 673 enum {
678 BMU_TX_IPIDINCR_ON = 1<<13, /* Enable IP ID Increment */ 674 BMU_TX_IPIDINCR_ON = 1<<13, /* Enable IP ID Increment */
679 BMU_TX_IPIDINCR_OFF = 1<<12, /* Disable IP ID Increment */ 675 BMU_TX_IPIDINCR_OFF = 1<<12, /* Disable IP ID Increment */
680 BMU_TX_CLR_IRQ_TCP = 1<<11, /* Clear IRQ on TCP segment length mismatch */ 676 BMU_TX_CLR_IRQ_TCP = 1<<11, /* Clear IRQ on TCP segment length mismatch */
681 }; 677 };
682 678
683 /* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/ 679 /* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/
684 /* PREF_UNIT_CTRL 32 bit Prefetch Control register */ 680 /* PREF_UNIT_CTRL 32 bit Prefetch Control register */
685 enum { 681 enum {
686 PREF_UNIT_OP_ON = 1<<3, /* prefetch unit operational */ 682 PREF_UNIT_OP_ON = 1<<3, /* prefetch unit operational */
687 PREF_UNIT_OP_OFF = 1<<2, /* prefetch unit not operational */ 683 PREF_UNIT_OP_OFF = 1<<2, /* prefetch unit not operational */
688 PREF_UNIT_RST_CLR = 1<<1, /* Clear Prefetch Unit Reset */ 684 PREF_UNIT_RST_CLR = 1<<1, /* Clear Prefetch Unit Reset */
689 PREF_UNIT_RST_SET = 1<<0, /* Set Prefetch Unit Reset */ 685 PREF_UNIT_RST_SET = 1<<0, /* Set Prefetch Unit Reset */
690 }; 686 };
691 687
692 /* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */ 688 /* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */
693 /* RB_START 32 bit RAM Buffer Start Address */ 689 /* RB_START 32 bit RAM Buffer Start Address */
694 /* RB_END 32 bit RAM Buffer End Address */ 690 /* RB_END 32 bit RAM Buffer End Address */
695 /* RB_WP 32 bit RAM Buffer Write Pointer */ 691 /* RB_WP 32 bit RAM Buffer Write Pointer */
696 /* RB_RP 32 bit RAM Buffer Read Pointer */ 692 /* RB_RP 32 bit RAM Buffer Read Pointer */
697 /* RB_RX_UTPP 32 bit Rx Upper Threshold, Pause Pack */ 693 /* RB_RX_UTPP 32 bit Rx Upper Threshold, Pause Pack */
698 /* RB_RX_LTPP 32 bit Rx Lower Threshold, Pause Pack */ 694 /* RB_RX_LTPP 32 bit Rx Lower Threshold, Pause Pack */
699 /* RB_RX_UTHP 32 bit Rx Upper Threshold, High Prio */ 695 /* RB_RX_UTHP 32 bit Rx Upper Threshold, High Prio */
700 /* RB_RX_LTHP 32 bit Rx Lower Threshold, High Prio */ 696 /* RB_RX_LTHP 32 bit Rx Lower Threshold, High Prio */
701 /* RB_PC 32 bit RAM Buffer Packet Counter */ 697 /* RB_PC 32 bit RAM Buffer Packet Counter */
702 /* RB_LEV 32 bit RAM Buffer Level Register */ 698 /* RB_LEV 32 bit RAM Buffer Level Register */
703 699
704 #define RB_MSK 0x0007ffff /* Bit 18.. 0: RAM Buffer Pointer Bits */ 700 #define RB_MSK 0x0007ffff /* Bit 18.. 0: RAM Buffer Pointer Bits */
705 /* RB_TST2 8 bit RAM Buffer Test Register 2 */ 701 /* RB_TST2 8 bit RAM Buffer Test Register 2 */
706 /* RB_TST1 8 bit RAM Buffer Test Register 1 */ 702 /* RB_TST1 8 bit RAM Buffer Test Register 1 */
707 703
708 /* RB_CTRL 8 bit RAM Buffer Control Register */ 704 /* RB_CTRL 8 bit RAM Buffer Control Register */
709 enum { 705 enum {
710 RB_ENA_STFWD = 1<<5, /* Enable Store & Forward */ 706 RB_ENA_STFWD = 1<<5, /* Enable Store & Forward */
711 RB_DIS_STFWD = 1<<4, /* Disable Store & Forward */ 707 RB_DIS_STFWD = 1<<4, /* Disable Store & Forward */
712 RB_ENA_OP_MD = 1<<3, /* Enable Operation Mode */ 708 RB_ENA_OP_MD = 1<<3, /* Enable Operation Mode */
713 RB_DIS_OP_MD = 1<<2, /* Disable Operation Mode */ 709 RB_DIS_OP_MD = 1<<2, /* Disable Operation Mode */
714 RB_RST_CLR = 1<<1, /* Clear RAM Buf STM Reset */ 710 RB_RST_CLR = 1<<1, /* Clear RAM Buf STM Reset */
715 RB_RST_SET = 1<<0, /* Set RAM Buf STM Reset */ 711 RB_RST_SET = 1<<0, /* Set RAM Buf STM Reset */
716 }; 712 };
717 713
718 714
719 /* Transmit GMAC FIFO (YUKON only) */ 715 /* Transmit GMAC FIFO (YUKON only) */
720 enum { 716 enum {
721 TX_GMF_EA = 0x0d40,/* 32 bit Tx GMAC FIFO End Address */ 717 TX_GMF_EA = 0x0d40,/* 32 bit Tx GMAC FIFO End Address */
722 TX_GMF_AE_THR = 0x0d44,/* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/ 718 TX_GMF_AE_THR = 0x0d44,/* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/
723 TX_GMF_CTRL_T = 0x0d48,/* 32 bit Tx GMAC FIFO Control/Test */ 719 TX_GMF_CTRL_T = 0x0d48,/* 32 bit Tx GMAC FIFO Control/Test */
724 720
725 TX_GMF_WP = 0x0d60,/* 32 bit Tx GMAC FIFO Write Pointer */ 721 TX_GMF_WP = 0x0d60,/* 32 bit Tx GMAC FIFO Write Pointer */
726 TX_GMF_WSP = 0x0d64,/* 32 bit Tx GMAC FIFO Write Shadow Ptr. */ 722 TX_GMF_WSP = 0x0d64,/* 32 bit Tx GMAC FIFO Write Shadow Ptr. */
727 TX_GMF_WLEV = 0x0d68,/* 32 bit Tx GMAC FIFO Write Level */ 723 TX_GMF_WLEV = 0x0d68,/* 32 bit Tx GMAC FIFO Write Level */
728 724
729 TX_GMF_RP = 0x0d70,/* 32 bit Tx GMAC FIFO Read Pointer */ 725 TX_GMF_RP = 0x0d70,/* 32 bit Tx GMAC FIFO Read Pointer */
730 TX_GMF_RSTP = 0x0d74,/* 32 bit Tx GMAC FIFO Restart Pointer */ 726 TX_GMF_RSTP = 0x0d74,/* 32 bit Tx GMAC FIFO Restart Pointer */
731 TX_GMF_RLEV = 0x0d78,/* 32 bit Tx GMAC FIFO Read Level */ 727 TX_GMF_RLEV = 0x0d78,/* 32 bit Tx GMAC FIFO Read Level */
732 }; 728 };
733 729
734 /* Descriptor Poll Timer Registers */ 730 /* Descriptor Poll Timer Registers */
735 enum { 731 enum {
736 B28_DPT_INI = 0x0e00,/* 24 bit Descriptor Poll Timer Init Val */ 732 B28_DPT_INI = 0x0e00,/* 24 bit Descriptor Poll Timer Init Val */
737 B28_DPT_VAL = 0x0e04,/* 24 bit Descriptor Poll Timer Curr Val */ 733 B28_DPT_VAL = 0x0e04,/* 24 bit Descriptor Poll Timer Curr Val */
738 B28_DPT_CTRL = 0x0e08,/* 8 bit Descriptor Poll Timer Ctrl Reg */ 734 B28_DPT_CTRL = 0x0e08,/* 8 bit Descriptor Poll Timer Ctrl Reg */
739 735
740 B28_DPT_TST = 0x0e0a,/* 8 bit Descriptor Poll Timer Test Reg */ 736 B28_DPT_TST = 0x0e0a,/* 8 bit Descriptor Poll Timer Test Reg */
741 }; 737 };
742 738
743 /* Time Stamp Timer Registers (YUKON only) */ 739 /* Time Stamp Timer Registers (YUKON only) */
744 enum { 740 enum {
745 GMAC_TI_ST_VAL = 0x0e14,/* 32 bit Time Stamp Timer Curr Val */ 741 GMAC_TI_ST_VAL = 0x0e14,/* 32 bit Time Stamp Timer Curr Val */
746 GMAC_TI_ST_CTRL = 0x0e18,/* 8 bit Time Stamp Timer Ctrl Reg */ 742 GMAC_TI_ST_CTRL = 0x0e18,/* 8 bit Time Stamp Timer Ctrl Reg */
747 GMAC_TI_ST_TST = 0x0e1a,/* 8 bit Time Stamp Timer Test Reg */ 743 GMAC_TI_ST_TST = 0x0e1a,/* 8 bit Time Stamp Timer Test Reg */
748 }; 744 };
749 745
750 /* Polling Unit Registers (Yukon-2 only) */ 746 /* Polling Unit Registers (Yukon-2 only) */
751 enum { 747 enum {
752 POLL_CTRL = 0x0e20, /* 32 bit Polling Unit Control Reg */ 748 POLL_CTRL = 0x0e20, /* 32 bit Polling Unit Control Reg */
753 POLL_LAST_IDX = 0x0e24,/* 16 bit Polling Unit List Last Index */ 749 POLL_LAST_IDX = 0x0e24,/* 16 bit Polling Unit List Last Index */
754 750
755 POLL_LIST_ADDR_LO= 0x0e28,/* 32 bit Poll. List Start Addr (low) */ 751 POLL_LIST_ADDR_LO= 0x0e28,/* 32 bit Poll. List Start Addr (low) */
756 POLL_LIST_ADDR_HI= 0x0e2c,/* 32 bit Poll. List Start Addr (high) */ 752 POLL_LIST_ADDR_HI= 0x0e2c,/* 32 bit Poll. List Start Addr (high) */
757 }; 753 };
758 754
759 /* ASF Subsystem Registers (Yukon-2 only) */ 755 /* ASF Subsystem Registers (Yukon-2 only) */
760 enum { 756 enum {
761 B28_Y2_SMB_CONFIG = 0x0e40,/* 32 bit ASF SMBus Config Register */ 757 B28_Y2_SMB_CONFIG = 0x0e40,/* 32 bit ASF SMBus Config Register */
762 B28_Y2_SMB_CSD_REG = 0x0e44,/* 32 bit ASF SMB Control/Status/Data */ 758 B28_Y2_SMB_CSD_REG = 0x0e44,/* 32 bit ASF SMB Control/Status/Data */
763 B28_Y2_ASF_IRQ_V_BASE=0x0e60,/* 32 bit ASF IRQ Vector Base */ 759 B28_Y2_ASF_IRQ_V_BASE=0x0e60,/* 32 bit ASF IRQ Vector Base */
764 760
765 B28_Y2_ASF_STAT_CMD= 0x0e68,/* 32 bit ASF Status and Command Reg */ 761 B28_Y2_ASF_STAT_CMD= 0x0e68,/* 32 bit ASF Status and Command Reg */
766 B28_Y2_ASF_HOST_COM= 0x0e6c,/* 32 bit ASF Host Communication Reg */ 762 B28_Y2_ASF_HOST_COM= 0x0e6c,/* 32 bit ASF Host Communication Reg */
767 B28_Y2_DATA_REG_1 = 0x0e70,/* 32 bit ASF/Host Data Register 1 */ 763 B28_Y2_DATA_REG_1 = 0x0e70,/* 32 bit ASF/Host Data Register 1 */
768 B28_Y2_DATA_REG_2 = 0x0e74,/* 32 bit ASF/Host Data Register 2 */ 764 B28_Y2_DATA_REG_2 = 0x0e74,/* 32 bit ASF/Host Data Register 2 */
769 B28_Y2_DATA_REG_3 = 0x0e78,/* 32 bit ASF/Host Data Register 3 */ 765 B28_Y2_DATA_REG_3 = 0x0e78,/* 32 bit ASF/Host Data Register 3 */
770 B28_Y2_DATA_REG_4 = 0x0e7c,/* 32 bit ASF/Host Data Register 4 */ 766 B28_Y2_DATA_REG_4 = 0x0e7c,/* 32 bit ASF/Host Data Register 4 */
771 }; 767 };
772 768
773 /* Status BMU Registers (Yukon-2 only)*/ 769 /* Status BMU Registers (Yukon-2 only)*/
774 enum { 770 enum {
775 STAT_CTRL = 0x0e80,/* 32 bit Status BMU Control Reg */ 771 STAT_CTRL = 0x0e80,/* 32 bit Status BMU Control Reg */
776 STAT_LAST_IDX = 0x0e84,/* 16 bit Status BMU Last Index */ 772 STAT_LAST_IDX = 0x0e84,/* 16 bit Status BMU Last Index */
777 773
778 STAT_LIST_ADDR_LO= 0x0e88,/* 32 bit Status List Start Addr (low) */ 774 STAT_LIST_ADDR_LO= 0x0e88,/* 32 bit Status List Start Addr (low) */
779 STAT_LIST_ADDR_HI= 0x0e8c,/* 32 bit Status List Start Addr (high) */ 775 STAT_LIST_ADDR_HI= 0x0e8c,/* 32 bit Status List Start Addr (high) */
780 STAT_TXA1_RIDX = 0x0e90,/* 16 bit Status TxA1 Report Index Reg */ 776 STAT_TXA1_RIDX = 0x0e90,/* 16 bit Status TxA1 Report Index Reg */
781 STAT_TXS1_RIDX = 0x0e92,/* 16 bit Status TxS1 Report Index Reg */ 777 STAT_TXS1_RIDX = 0x0e92,/* 16 bit Status TxS1 Report Index Reg */
782 STAT_TXA2_RIDX = 0x0e94,/* 16 bit Status TxA2 Report Index Reg */ 778 STAT_TXA2_RIDX = 0x0e94,/* 16 bit Status TxA2 Report Index Reg */
783 STAT_TXS2_RIDX = 0x0e96,/* 16 bit Status TxS2 Report Index Reg */ 779 STAT_TXS2_RIDX = 0x0e96,/* 16 bit Status TxS2 Report Index Reg */
784 STAT_TX_IDX_TH = 0x0e98,/* 16 bit Status Tx Index Threshold Reg */ 780 STAT_TX_IDX_TH = 0x0e98,/* 16 bit Status Tx Index Threshold Reg */
785 STAT_PUT_IDX = 0x0e9c,/* 16 bit Status Put Index Reg */ 781 STAT_PUT_IDX = 0x0e9c,/* 16 bit Status Put Index Reg */
786 782
787 /* FIFO Control/Status Registers (Yukon-2 only)*/ 783 /* FIFO Control/Status Registers (Yukon-2 only)*/
788 STAT_FIFO_WP = 0x0ea0,/* 8 bit Status FIFO Write Pointer Reg */ 784 STAT_FIFO_WP = 0x0ea0,/* 8 bit Status FIFO Write Pointer Reg */
789 STAT_FIFO_RP = 0x0ea4,/* 8 bit Status FIFO Read Pointer Reg */ 785 STAT_FIFO_RP = 0x0ea4,/* 8 bit Status FIFO Read Pointer Reg */
790 STAT_FIFO_RSP = 0x0ea6,/* 8 bit Status FIFO Read Shadow Ptr */ 786 STAT_FIFO_RSP = 0x0ea6,/* 8 bit Status FIFO Read Shadow Ptr */
791 STAT_FIFO_LEVEL = 0x0ea8,/* 8 bit Status FIFO Level Reg */ 787 STAT_FIFO_LEVEL = 0x0ea8,/* 8 bit Status FIFO Level Reg */
792 STAT_FIFO_SHLVL = 0x0eaa,/* 8 bit Status FIFO Shadow Level Reg */ 788 STAT_FIFO_SHLVL = 0x0eaa,/* 8 bit Status FIFO Shadow Level Reg */
793 STAT_FIFO_WM = 0x0eac,/* 8 bit Status FIFO Watermark Reg */ 789 STAT_FIFO_WM = 0x0eac,/* 8 bit Status FIFO Watermark Reg */
794 STAT_FIFO_ISR_WM= 0x0ead,/* 8 bit Status FIFO ISR Watermark Reg */ 790 STAT_FIFO_ISR_WM= 0x0ead,/* 8 bit Status FIFO ISR Watermark Reg */
795 791
796 /* Level and ISR Timer Registers (Yukon-2 only)*/ 792 /* Level and ISR Timer Registers (Yukon-2 only)*/
797 STAT_LEV_TIMER_INI= 0x0eb0,/* 32 bit Level Timer Init. Value Reg */ 793 STAT_LEV_TIMER_INI= 0x0eb0,/* 32 bit Level Timer Init. Value Reg */
798 STAT_LEV_TIMER_CNT= 0x0eb4,/* 32 bit Level Timer Counter Reg */ 794 STAT_LEV_TIMER_CNT= 0x0eb4,/* 32 bit Level Timer Counter Reg */
799 STAT_LEV_TIMER_CTRL= 0x0eb8,/* 8 bit Level Timer Control Reg */ 795 STAT_LEV_TIMER_CTRL= 0x0eb8,/* 8 bit Level Timer Control Reg */
800 STAT_LEV_TIMER_TEST= 0x0eb9,/* 8 bit Level Timer Test Reg */ 796 STAT_LEV_TIMER_TEST= 0x0eb9,/* 8 bit Level Timer Test Reg */
801 STAT_TX_TIMER_INI = 0x0ec0,/* 32 bit Tx Timer Init. Value Reg */ 797 STAT_TX_TIMER_INI = 0x0ec0,/* 32 bit Tx Timer Init. Value Reg */
802 STAT_TX_TIMER_CNT = 0x0ec4,/* 32 bit Tx Timer Counter Reg */ 798 STAT_TX_TIMER_CNT = 0x0ec4,/* 32 bit Tx Timer Counter Reg */
803 STAT_TX_TIMER_CTRL = 0x0ec8,/* 8 bit Tx Timer Control Reg */ 799 STAT_TX_TIMER_CTRL = 0x0ec8,/* 8 bit Tx Timer Control Reg */
804 STAT_TX_TIMER_TEST = 0x0ec9,/* 8 bit Tx Timer Test Reg */ 800 STAT_TX_TIMER_TEST = 0x0ec9,/* 8 bit Tx Timer Test Reg */
805 STAT_ISR_TIMER_INI = 0x0ed0,/* 32 bit ISR Timer Init. Value Reg */ 801 STAT_ISR_TIMER_INI = 0x0ed0,/* 32 bit ISR Timer Init. Value Reg */
806 STAT_ISR_TIMER_CNT = 0x0ed4,/* 32 bit ISR Timer Counter Reg */ 802 STAT_ISR_TIMER_CNT = 0x0ed4,/* 32 bit ISR Timer Counter Reg */
807 STAT_ISR_TIMER_CTRL= 0x0ed8,/* 8 bit ISR Timer Control Reg */ 803 STAT_ISR_TIMER_CTRL= 0x0ed8,/* 8 bit ISR Timer Control Reg */
808 STAT_ISR_TIMER_TEST= 0x0ed9,/* 8 bit ISR Timer Test Reg */ 804 STAT_ISR_TIMER_TEST= 0x0ed9,/* 8 bit ISR Timer Test Reg */
809 }; 805 };
810 806
811 enum { 807 enum {
812 LINKLED_OFF = 0x01, 808 LINKLED_OFF = 0x01,
813 LINKLED_ON = 0x02, 809 LINKLED_ON = 0x02,
814 LINKLED_LINKSYNC_OFF = 0x04, 810 LINKLED_LINKSYNC_OFF = 0x04,
815 LINKLED_LINKSYNC_ON = 0x08, 811 LINKLED_LINKSYNC_ON = 0x08,
816 LINKLED_BLINK_OFF = 0x10, 812 LINKLED_BLINK_OFF = 0x10,
817 LINKLED_BLINK_ON = 0x20, 813 LINKLED_BLINK_ON = 0x20,
818 }; 814 };
819 815
820 /* GMAC and GPHY Control Registers (YUKON only) */ 816 /* GMAC and GPHY Control Registers (YUKON only) */
821 enum { 817 enum {
822 GMAC_CTRL = 0x0f00,/* 32 bit GMAC Control Reg */ 818 GMAC_CTRL = 0x0f00,/* 32 bit GMAC Control Reg */
823 GPHY_CTRL = 0x0f04,/* 32 bit GPHY Control Reg */ 819 GPHY_CTRL = 0x0f04,/* 32 bit GPHY Control Reg */
824 GMAC_IRQ_SRC = 0x0f08,/* 8 bit GMAC Interrupt Source Reg */ 820 GMAC_IRQ_SRC = 0x0f08,/* 8 bit GMAC Interrupt Source Reg */
825 GMAC_IRQ_MSK = 0x0f0c,/* 8 bit GMAC Interrupt Mask Reg */ 821 GMAC_IRQ_MSK = 0x0f0c,/* 8 bit GMAC Interrupt Mask Reg */
826 GMAC_LINK_CTRL = 0x0f10,/* 16 bit Link Control Reg */ 822 GMAC_LINK_CTRL = 0x0f10,/* 16 bit Link Control Reg */
827 823
828 /* Wake-up Frame Pattern Match Control Registers (YUKON only) */ 824 /* Wake-up Frame Pattern Match Control Registers (YUKON only) */
829 825
830 WOL_REG_OFFS = 0x20,/* HW-Bug: Address is + 0x20 against spec. */ 826 WOL_REG_OFFS = 0x20,/* HW-Bug: Address is + 0x20 against spec. */
831 827
832 WOL_CTRL_STAT = 0x0f20,/* 16 bit WOL Control/Status Reg */ 828 WOL_CTRL_STAT = 0x0f20,/* 16 bit WOL Control/Status Reg */
833 WOL_MATCH_CTL = 0x0f22,/* 8 bit WOL Match Control Reg */ 829 WOL_MATCH_CTL = 0x0f22,/* 8 bit WOL Match Control Reg */
834 WOL_MATCH_RES = 0x0f23,/* 8 bit WOL Match Result Reg */ 830 WOL_MATCH_RES = 0x0f23,/* 8 bit WOL Match Result Reg */
835 WOL_MAC_ADDR = 0x0f24,/* 32 bit WOL MAC Address */ 831 WOL_MAC_ADDR = 0x0f24,/* 32 bit WOL MAC Address */
836 WOL_PATT_PME = 0x0f2a,/* 8 bit WOL PME Match Enable (Yukon-2) */ 832 WOL_PATT_PME = 0x0f2a,/* 8 bit WOL PME Match Enable (Yukon-2) */
837 WOL_PATT_ASFM = 0x0f2b,/* 8 bit WOL ASF Match Enable (Yukon-2) */ 833 WOL_PATT_ASFM = 0x0f2b,/* 8 bit WOL ASF Match Enable (Yukon-2) */
838 WOL_PATT_RPTR = 0x0f2c,/* 8 bit WOL Pattern Read Pointer */ 834 WOL_PATT_RPTR = 0x0f2c,/* 8 bit WOL Pattern Read Pointer */
839 835
840 /* WOL Pattern Length Registers (YUKON only) */ 836 /* WOL Pattern Length Registers (YUKON only) */
841 837
842 WOL_PATT_LEN_LO = 0x0f30,/* 32 bit WOL Pattern Length 3..0 */ 838 WOL_PATT_LEN_LO = 0x0f30,/* 32 bit WOL Pattern Length 3..0 */
843 WOL_PATT_LEN_HI = 0x0f34,/* 24 bit WOL Pattern Length 6..4 */ 839 WOL_PATT_LEN_HI = 0x0f34,/* 24 bit WOL Pattern Length 6..4 */
844 840
845 /* WOL Pattern Counter Registers (YUKON only) */ 841 /* WOL Pattern Counter Registers (YUKON only) */
846 842
847 843
848 WOL_PATT_CNT_0 = 0x0f38,/* 32 bit WOL Pattern Counter 3..0 */ 844 WOL_PATT_CNT_0 = 0x0f38,/* 32 bit WOL Pattern Counter 3..0 */
849 WOL_PATT_CNT_4 = 0x0f3c,/* 24 bit WOL Pattern Counter 6..4 */ 845 WOL_PATT_CNT_4 = 0x0f3c,/* 24 bit WOL Pattern Counter 6..4 */
850 }; 846 };
851 847
852 enum { 848 enum {
853 WOL_PATT_RAM_1 = 0x1000,/* WOL Pattern RAM Link 1 */ 849 WOL_PATT_RAM_1 = 0x1000,/* WOL Pattern RAM Link 1 */
854 WOL_PATT_RAM_2 = 0x1400,/* WOL Pattern RAM Link 2 */ 850 WOL_PATT_RAM_2 = 0x1400,/* WOL Pattern RAM Link 2 */
855 }; 851 };
856 852
857 enum { 853 enum {
858 BASE_GMAC_1 = 0x2800,/* GMAC 1 registers */ 854 BASE_GMAC_1 = 0x2800,/* GMAC 1 registers */
859 BASE_GMAC_2 = 0x3800,/* GMAC 2 registers */ 855 BASE_GMAC_2 = 0x3800,/* GMAC 2 registers */
860 }; 856 };
861 857
862 /* 858 /*
863 * Marvel-PHY Registers, indirect addressed over GMAC 859 * Marvel-PHY Registers, indirect addressed over GMAC
864 */ 860 */
865 enum { 861 enum {
866 PHY_MARV_CTRL = 0x00,/* 16 bit r/w PHY Control Register */ 862 PHY_MARV_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
867 PHY_MARV_STAT = 0x01,/* 16 bit r/o PHY Status Register */ 863 PHY_MARV_STAT = 0x01,/* 16 bit r/o PHY Status Register */
868 PHY_MARV_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */ 864 PHY_MARV_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
869 PHY_MARV_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */ 865 PHY_MARV_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
870 PHY_MARV_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */ 866 PHY_MARV_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
871 PHY_MARV_AUNE_LP = 0x05,/* 16 bit r/o Link Part Ability Reg */ 867 PHY_MARV_AUNE_LP = 0x05,/* 16 bit r/o Link Part Ability Reg */
872 PHY_MARV_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */ 868 PHY_MARV_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
873 PHY_MARV_NEPG = 0x07,/* 16 bit r/w Next Page Register */ 869 PHY_MARV_NEPG = 0x07,/* 16 bit r/w Next Page Register */
874 PHY_MARV_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */ 870 PHY_MARV_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */
875 /* Marvel-specific registers */ 871 /* Marvel-specific registers */
876 PHY_MARV_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */ 872 PHY_MARV_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
877 PHY_MARV_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */ 873 PHY_MARV_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
878 PHY_MARV_EXT_STAT = 0x0f,/* 16 bit r/o Extended Status Reg */ 874 PHY_MARV_EXT_STAT = 0x0f,/* 16 bit r/o Extended Status Reg */
879 PHY_MARV_PHY_CTRL = 0x10,/* 16 bit r/w PHY Specific Ctrl Reg */ 875 PHY_MARV_PHY_CTRL = 0x10,/* 16 bit r/w PHY Specific Ctrl Reg */
880 PHY_MARV_PHY_STAT = 0x11,/* 16 bit r/o PHY Specific Stat Reg */ 876 PHY_MARV_PHY_STAT = 0x11,/* 16 bit r/o PHY Specific Stat Reg */
881 PHY_MARV_INT_MASK = 0x12,/* 16 bit r/w Interrupt Mask Reg */ 877 PHY_MARV_INT_MASK = 0x12,/* 16 bit r/w Interrupt Mask Reg */
882 PHY_MARV_INT_STAT = 0x13,/* 16 bit r/o Interrupt Status Reg */ 878 PHY_MARV_INT_STAT = 0x13,/* 16 bit r/o Interrupt Status Reg */
883 PHY_MARV_EXT_CTRL = 0x14,/* 16 bit r/w Ext. PHY Specific Ctrl */ 879 PHY_MARV_EXT_CTRL = 0x14,/* 16 bit r/w Ext. PHY Specific Ctrl */
884 PHY_MARV_RXE_CNT = 0x15,/* 16 bit r/w Receive Error Counter */ 880 PHY_MARV_RXE_CNT = 0x15,/* 16 bit r/w Receive Error Counter */
885 PHY_MARV_EXT_ADR = 0x16,/* 16 bit r/w Ext. Ad. for Cable Diag. */ 881 PHY_MARV_EXT_ADR = 0x16,/* 16 bit r/w Ext. Ad. for Cable Diag. */
886 PHY_MARV_PORT_IRQ = 0x17,/* 16 bit r/o Port 0 IRQ (88E1111 only) */ 882 PHY_MARV_PORT_IRQ = 0x17,/* 16 bit r/o Port 0 IRQ (88E1111 only) */
887 PHY_MARV_LED_CTRL = 0x18,/* 16 bit r/w LED Control Reg */ 883 PHY_MARV_LED_CTRL = 0x18,/* 16 bit r/w LED Control Reg */
888 PHY_MARV_LED_OVER = 0x19,/* 16 bit r/w Manual LED Override Reg */ 884 PHY_MARV_LED_OVER = 0x19,/* 16 bit r/w Manual LED Override Reg */
889 PHY_MARV_EXT_CTRL_2 = 0x1a,/* 16 bit r/w Ext. PHY Specific Ctrl 2 */ 885 PHY_MARV_EXT_CTRL_2 = 0x1a,/* 16 bit r/w Ext. PHY Specific Ctrl 2 */
890 PHY_MARV_EXT_P_STAT = 0x1b,/* 16 bit r/w Ext. PHY Spec. Stat Reg */ 886 PHY_MARV_EXT_P_STAT = 0x1b,/* 16 bit r/w Ext. PHY Spec. Stat Reg */
891 PHY_MARV_CABLE_DIAG = 0x1c,/* 16 bit r/o Cable Diagnostic Reg */ 887 PHY_MARV_CABLE_DIAG = 0x1c,/* 16 bit r/o Cable Diagnostic Reg */
892 PHY_MARV_PAGE_ADDR = 0x1d,/* 16 bit r/w Extended Page Address Reg */ 888 PHY_MARV_PAGE_ADDR = 0x1d,/* 16 bit r/w Extended Page Address Reg */
893 PHY_MARV_PAGE_DATA = 0x1e,/* 16 bit r/w Extended Page Data Reg */ 889 PHY_MARV_PAGE_DATA = 0x1e,/* 16 bit r/w Extended Page Data Reg */
894 890
895 /* for 10/100 Fast Ethernet PHY (88E3082 only) */ 891 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
896 PHY_MARV_FE_LED_PAR = 0x16,/* 16 bit r/w LED Parallel Select Reg. */ 892 PHY_MARV_FE_LED_PAR = 0x16,/* 16 bit r/w LED Parallel Select Reg. */
897 PHY_MARV_FE_LED_SER = 0x17,/* 16 bit r/w LED Stream Select S. LED */ 893 PHY_MARV_FE_LED_SER = 0x17,/* 16 bit r/w LED Stream Select S. LED */
898 PHY_MARV_FE_VCT_TX = 0x1a,/* 16 bit r/w VCT Reg. for TXP/N Pins */ 894 PHY_MARV_FE_VCT_TX = 0x1a,/* 16 bit r/w VCT Reg. for TXP/N Pins */
899 PHY_MARV_FE_VCT_RX = 0x1b,/* 16 bit r/o VCT Reg. for RXP/N Pins */ 895 PHY_MARV_FE_VCT_RX = 0x1b,/* 16 bit r/o VCT Reg. for RXP/N Pins */
900 PHY_MARV_FE_SPEC_2 = 0x1c,/* 16 bit r/w Specific Control Reg. 2 */ 896 PHY_MARV_FE_SPEC_2 = 0x1c,/* 16 bit r/w Specific Control Reg. 2 */
901 }; 897 };
902 898
903 enum { 899 enum {
904 PHY_CT_RESET = 1<<15, /* Bit 15: (sc) clear all PHY related regs */ 900 PHY_CT_RESET = 1<<15, /* Bit 15: (sc) clear all PHY related regs */
905 PHY_CT_LOOP = 1<<14, /* Bit 14: enable Loopback over PHY */ 901 PHY_CT_LOOP = 1<<14, /* Bit 14: enable Loopback over PHY */
906 PHY_CT_SPS_LSB = 1<<13, /* Bit 13: Speed select, lower bit */ 902 PHY_CT_SPS_LSB = 1<<13, /* Bit 13: Speed select, lower bit */
907 PHY_CT_ANE = 1<<12, /* Bit 12: Auto-Negotiation Enabled */ 903 PHY_CT_ANE = 1<<12, /* Bit 12: Auto-Negotiation Enabled */
908 PHY_CT_PDOWN = 1<<11, /* Bit 11: Power Down Mode */ 904 PHY_CT_PDOWN = 1<<11, /* Bit 11: Power Down Mode */
909 PHY_CT_ISOL = 1<<10, /* Bit 10: Isolate Mode */ 905 PHY_CT_ISOL = 1<<10, /* Bit 10: Isolate Mode */
910 PHY_CT_RE_CFG = 1<<9, /* Bit 9: (sc) Restart Auto-Negotiation */ 906 PHY_CT_RE_CFG = 1<<9, /* Bit 9: (sc) Restart Auto-Negotiation */
911 PHY_CT_DUP_MD = 1<<8, /* Bit 8: Duplex Mode */ 907 PHY_CT_DUP_MD = 1<<8, /* Bit 8: Duplex Mode */
912 PHY_CT_COL_TST = 1<<7, /* Bit 7: Collision Test enabled */ 908 PHY_CT_COL_TST = 1<<7, /* Bit 7: Collision Test enabled */
913 PHY_CT_SPS_MSB = 1<<6, /* Bit 6: Speed select, upper bit */ 909 PHY_CT_SPS_MSB = 1<<6, /* Bit 6: Speed select, upper bit */
914 }; 910 };
915 911
916 enum { 912 enum {
917 PHY_CT_SP1000 = PHY_CT_SPS_MSB, /* enable speed of 1000 Mbps */ 913 PHY_CT_SP1000 = PHY_CT_SPS_MSB, /* enable speed of 1000 Mbps */
918 PHY_CT_SP100 = PHY_CT_SPS_LSB, /* enable speed of 100 Mbps */ 914 PHY_CT_SP100 = PHY_CT_SPS_LSB, /* enable speed of 100 Mbps */
919 PHY_CT_SP10 = 0, /* enable speed of 10 Mbps */ 915 PHY_CT_SP10 = 0, /* enable speed of 10 Mbps */
920 }; 916 };
921 917
922 enum { 918 enum {
923 PHY_ST_EXT_ST = 1<<8, /* Bit 8: Extended Status Present */ 919 PHY_ST_EXT_ST = 1<<8, /* Bit 8: Extended Status Present */
924 920
925 PHY_ST_PRE_SUP = 1<<6, /* Bit 6: Preamble Suppression */ 921 PHY_ST_PRE_SUP = 1<<6, /* Bit 6: Preamble Suppression */
926 PHY_ST_AN_OVER = 1<<5, /* Bit 5: Auto-Negotiation Over */ 922 PHY_ST_AN_OVER = 1<<5, /* Bit 5: Auto-Negotiation Over */
927 PHY_ST_REM_FLT = 1<<4, /* Bit 4: Remote Fault Condition Occured */ 923 PHY_ST_REM_FLT = 1<<4, /* Bit 4: Remote Fault Condition Occured */
928 PHY_ST_AN_CAP = 1<<3, /* Bit 3: Auto-Negotiation Capability */ 924 PHY_ST_AN_CAP = 1<<3, /* Bit 3: Auto-Negotiation Capability */
929 PHY_ST_LSYNC = 1<<2, /* Bit 2: Link Synchronized */ 925 PHY_ST_LSYNC = 1<<2, /* Bit 2: Link Synchronized */
930 PHY_ST_JAB_DET = 1<<1, /* Bit 1: Jabber Detected */ 926 PHY_ST_JAB_DET = 1<<1, /* Bit 1: Jabber Detected */
931 PHY_ST_EXT_REG = 1<<0, /* Bit 0: Extended Register available */ 927 PHY_ST_EXT_REG = 1<<0, /* Bit 0: Extended Register available */
932 }; 928 };
933 929
934 enum { 930 enum {
935 PHY_I1_OUI_MSK = 0x3f<<10, /* Bit 15..10: Organization Unique ID */ 931 PHY_I1_OUI_MSK = 0x3f<<10, /* Bit 15..10: Organization Unique ID */
936 PHY_I1_MOD_NUM = 0x3f<<4, /* Bit 9.. 4: Model Number */ 932 PHY_I1_MOD_NUM = 0x3f<<4, /* Bit 9.. 4: Model Number */
937 PHY_I1_REV_MSK = 0xf, /* Bit 3.. 0: Revision Number */ 933 PHY_I1_REV_MSK = 0xf, /* Bit 3.. 0: Revision Number */
938 }; 934 };
939 935
940 /* different Marvell PHY Ids */ 936 /* different Marvell PHY Ids */
941 enum { 937 enum {
942 PHY_MARV_ID0_VAL= 0x0141, /* Marvell Unique Identifier */ 938 PHY_MARV_ID0_VAL= 0x0141, /* Marvell Unique Identifier */
943 939
944 PHY_BCOM_ID1_A1 = 0x6041, 940 PHY_BCOM_ID1_A1 = 0x6041,
945 PHY_BCOM_ID1_B2 = 0x6043, 941 PHY_BCOM_ID1_B2 = 0x6043,
946 PHY_BCOM_ID1_C0 = 0x6044, 942 PHY_BCOM_ID1_C0 = 0x6044,
947 PHY_BCOM_ID1_C5 = 0x6047, 943 PHY_BCOM_ID1_C5 = 0x6047,
948 944
949 PHY_MARV_ID1_B0 = 0x0C23, /* Yukon (PHY 88E1011) */ 945 PHY_MARV_ID1_B0 = 0x0C23, /* Yukon (PHY 88E1011) */
950 PHY_MARV_ID1_B2 = 0x0C25, /* Yukon-Plus (PHY 88E1011) */ 946 PHY_MARV_ID1_B2 = 0x0C25, /* Yukon-Plus (PHY 88E1011) */
951 PHY_MARV_ID1_C2 = 0x0CC2, /* Yukon-EC (PHY 88E1111) */ 947 PHY_MARV_ID1_C2 = 0x0CC2, /* Yukon-EC (PHY 88E1111) */
952 PHY_MARV_ID1_Y2 = 0x0C91, /* Yukon-2 (PHY 88E1112) */ 948 PHY_MARV_ID1_Y2 = 0x0C91, /* Yukon-2 (PHY 88E1112) */
953 PHY_MARV_ID1_FE = 0x0C83, /* Yukon-FE (PHY 88E3082 Rev.A1) */ 949 PHY_MARV_ID1_FE = 0x0C83, /* Yukon-FE (PHY 88E3082 Rev.A1) */
954 PHY_MARV_ID1_ECU= 0x0CB0, /* Yukon-ECU (PHY 88E1149 Rev.B2?) */ 950 PHY_MARV_ID1_ECU= 0x0CB0, /* Yukon-ECU (PHY 88E1149 Rev.B2?) */
955 }; 951 };
956 952
957 /* Advertisement register bits */ 953 /* Advertisement register bits */
958 enum { 954 enum {
959 PHY_AN_NXT_PG = 1<<15, /* Bit 15: Request Next Page */ 955 PHY_AN_NXT_PG = 1<<15, /* Bit 15: Request Next Page */
960 PHY_AN_ACK = 1<<14, /* Bit 14: (ro) Acknowledge Received */ 956 PHY_AN_ACK = 1<<14, /* Bit 14: (ro) Acknowledge Received */
961 PHY_AN_RF = 1<<13, /* Bit 13: Remote Fault Bits */ 957 PHY_AN_RF = 1<<13, /* Bit 13: Remote Fault Bits */
962 958
963 PHY_AN_PAUSE_ASYM = 1<<11,/* Bit 11: Try for asymmetric */ 959 PHY_AN_PAUSE_ASYM = 1<<11,/* Bit 11: Try for asymmetric */
964 PHY_AN_PAUSE_CAP = 1<<10, /* Bit 10: Try for pause */ 960 PHY_AN_PAUSE_CAP = 1<<10, /* Bit 10: Try for pause */
965 PHY_AN_100BASE4 = 1<<9, /* Bit 9: Try for 100mbps 4k packets */ 961 PHY_AN_100BASE4 = 1<<9, /* Bit 9: Try for 100mbps 4k packets */
966 PHY_AN_100FULL = 1<<8, /* Bit 8: Try for 100mbps full-duplex */ 962 PHY_AN_100FULL = 1<<8, /* Bit 8: Try for 100mbps full-duplex */
967 PHY_AN_100HALF = 1<<7, /* Bit 7: Try for 100mbps half-duplex */ 963 PHY_AN_100HALF = 1<<7, /* Bit 7: Try for 100mbps half-duplex */
968 PHY_AN_10FULL = 1<<6, /* Bit 6: Try for 10mbps full-duplex */ 964 PHY_AN_10FULL = 1<<6, /* Bit 6: Try for 10mbps full-duplex */
969 PHY_AN_10HALF = 1<<5, /* Bit 5: Try for 10mbps half-duplex */ 965 PHY_AN_10HALF = 1<<5, /* Bit 5: Try for 10mbps half-duplex */
970 PHY_AN_CSMA = 1<<0, /* Bit 0: Only selector supported */ 966 PHY_AN_CSMA = 1<<0, /* Bit 0: Only selector supported */
971 PHY_AN_SEL = 0x1f, /* Bit 4..0: Selector Field, 00001=Ethernet*/ 967 PHY_AN_SEL = 0x1f, /* Bit 4..0: Selector Field, 00001=Ethernet*/
972 PHY_AN_FULL = PHY_AN_100FULL | PHY_AN_10FULL | PHY_AN_CSMA, 968 PHY_AN_FULL = PHY_AN_100FULL | PHY_AN_10FULL | PHY_AN_CSMA,
973 PHY_AN_ALL = PHY_AN_10HALF | PHY_AN_10FULL | 969 PHY_AN_ALL = PHY_AN_10HALF | PHY_AN_10FULL |
974 PHY_AN_100HALF | PHY_AN_100FULL, 970 PHY_AN_100HALF | PHY_AN_100FULL,
975 }; 971 };
976 972
977 /***** PHY_BCOM_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/ 973 /***** PHY_BCOM_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
978 /***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/ 974 /***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
979 enum { 975 enum {
980 PHY_B_1000S_MSF = 1<<15, /* Bit 15: Master/Slave Fault */ 976 PHY_B_1000S_MSF = 1<<15, /* Bit 15: Master/Slave Fault */
981 PHY_B_1000S_MSR = 1<<14, /* Bit 14: Master/Slave Result */ 977 PHY_B_1000S_MSR = 1<<14, /* Bit 14: Master/Slave Result */
982 PHY_B_1000S_LRS = 1<<13, /* Bit 13: Local Receiver Status */ 978 PHY_B_1000S_LRS = 1<<13, /* Bit 13: Local Receiver Status */
983 PHY_B_1000S_RRS = 1<<12, /* Bit 12: Remote Receiver Status */ 979 PHY_B_1000S_RRS = 1<<12, /* Bit 12: Remote Receiver Status */
984 PHY_B_1000S_LP_FD = 1<<11, /* Bit 11: Link Partner can FD */ 980 PHY_B_1000S_LP_FD = 1<<11, /* Bit 11: Link Partner can FD */
985 PHY_B_1000S_LP_HD = 1<<10, /* Bit 10: Link Partner can HD */ 981 PHY_B_1000S_LP_HD = 1<<10, /* Bit 10: Link Partner can HD */
986 /* Bit 9..8: reserved */ 982 /* Bit 9..8: reserved */
987 PHY_B_1000S_IEC = 0xff, /* Bit 7..0: Idle Error Count */ 983 PHY_B_1000S_IEC = 0xff, /* Bit 7..0: Idle Error Count */
988 }; 984 };
989 985
990 /** Marvell-Specific */ 986 /** Marvell-Specific */
991 enum { 987 enum {
992 PHY_M_AN_NXT_PG = 1<<15, /* Request Next Page */ 988 PHY_M_AN_NXT_PG = 1<<15, /* Request Next Page */
993 PHY_M_AN_ACK = 1<<14, /* (ro) Acknowledge Received */ 989 PHY_M_AN_ACK = 1<<14, /* (ro) Acknowledge Received */
994 PHY_M_AN_RF = 1<<13, /* Remote Fault */ 990 PHY_M_AN_RF = 1<<13, /* Remote Fault */
995 991
996 PHY_M_AN_ASP = 1<<11, /* Asymmetric Pause */ 992 PHY_M_AN_ASP = 1<<11, /* Asymmetric Pause */
997 PHY_M_AN_PC = 1<<10, /* MAC Pause implemented */ 993 PHY_M_AN_PC = 1<<10, /* MAC Pause implemented */
998 PHY_M_AN_100_T4 = 1<<9, /* Not cap. 100Base-T4 (always 0) */ 994 PHY_M_AN_100_T4 = 1<<9, /* Not cap. 100Base-T4 (always 0) */
999 PHY_M_AN_100_FD = 1<<8, /* Advertise 100Base-TX Full Duplex */ 995 PHY_M_AN_100_FD = 1<<8, /* Advertise 100Base-TX Full Duplex */
1000 PHY_M_AN_100_HD = 1<<7, /* Advertise 100Base-TX Half Duplex */ 996 PHY_M_AN_100_HD = 1<<7, /* Advertise 100Base-TX Half Duplex */
1001 PHY_M_AN_10_FD = 1<<6, /* Advertise 10Base-TX Full Duplex */ 997 PHY_M_AN_10_FD = 1<<6, /* Advertise 10Base-TX Full Duplex */
1002 PHY_M_AN_10_HD = 1<<5, /* Advertise 10Base-TX Half Duplex */ 998 PHY_M_AN_10_HD = 1<<5, /* Advertise 10Base-TX Half Duplex */
1003 PHY_M_AN_SEL_MSK =0x1f<<4, /* Bit 4.. 0: Selector Field Mask */ 999 PHY_M_AN_SEL_MSK =0x1f<<4, /* Bit 4.. 0: Selector Field Mask */
1004 }; 1000 };
1005 1001
1006 /* special defines for FIBER (88E1011S only) */ 1002 /* special defines for FIBER (88E1011S only) */
1007 enum { 1003 enum {
1008 PHY_M_AN_ASP_X = 1<<8, /* Asymmetric Pause */ 1004 PHY_M_AN_ASP_X = 1<<8, /* Asymmetric Pause */
1009 PHY_M_AN_PC_X = 1<<7, /* MAC Pause implemented */ 1005 PHY_M_AN_PC_X = 1<<7, /* MAC Pause implemented */
1010 PHY_M_AN_1000X_AHD = 1<<6, /* Advertise 10000Base-X Half Duplex */ 1006 PHY_M_AN_1000X_AHD = 1<<6, /* Advertise 10000Base-X Half Duplex */
1011 PHY_M_AN_1000X_AFD = 1<<5, /* Advertise 10000Base-X Full Duplex */ 1007 PHY_M_AN_1000X_AFD = 1<<5, /* Advertise 10000Base-X Full Duplex */
1012 }; 1008 };
1013 1009
1014 /* Pause Bits (PHY_M_AN_ASP_X and PHY_M_AN_PC_X) encoding */ 1010 /* Pause Bits (PHY_M_AN_ASP_X and PHY_M_AN_PC_X) encoding */
1015 enum { 1011 enum {
1016 PHY_M_P_NO_PAUSE_X = 0<<7,/* Bit 8.. 7: no Pause Mode */ 1012 PHY_M_P_NO_PAUSE_X = 0<<7,/* Bit 8.. 7: no Pause Mode */
1017 PHY_M_P_SYM_MD_X = 1<<7, /* Bit 8.. 7: symmetric Pause Mode */ 1013 PHY_M_P_SYM_MD_X = 1<<7, /* Bit 8.. 7: symmetric Pause Mode */
1018 PHY_M_P_ASYM_MD_X = 2<<7,/* Bit 8.. 7: asymmetric Pause Mode */ 1014 PHY_M_P_ASYM_MD_X = 2<<7,/* Bit 8.. 7: asymmetric Pause Mode */
1019 PHY_M_P_BOTH_MD_X = 3<<7,/* Bit 8.. 7: both Pause Mode */ 1015 PHY_M_P_BOTH_MD_X = 3<<7,/* Bit 8.. 7: both Pause Mode */
1020 }; 1016 };
1021 1017
1022 /***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/ 1018 /***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1023 enum { 1019 enum {
1024 PHY_M_1000C_TEST = 7<<13,/* Bit 15..13: Test Modes */ 1020 PHY_M_1000C_TEST = 7<<13,/* Bit 15..13: Test Modes */
1025 PHY_M_1000C_MSE = 1<<12, /* Manual Master/Slave Enable */ 1021 PHY_M_1000C_MSE = 1<<12, /* Manual Master/Slave Enable */
1026 PHY_M_1000C_MSC = 1<<11, /* M/S Configuration (1=Master) */ 1022 PHY_M_1000C_MSC = 1<<11, /* M/S Configuration (1=Master) */
1027 PHY_M_1000C_MPD = 1<<10, /* Multi-Port Device */ 1023 PHY_M_1000C_MPD = 1<<10, /* Multi-Port Device */
1028 PHY_M_1000C_AFD = 1<<9, /* Advertise Full Duplex */ 1024 PHY_M_1000C_AFD = 1<<9, /* Advertise Full Duplex */
1029 PHY_M_1000C_AHD = 1<<8, /* Advertise Half Duplex */ 1025 PHY_M_1000C_AHD = 1<<8, /* Advertise Half Duplex */
1030 }; 1026 };
1031 1027
1032 /***** PHY_MARV_PHY_CTRL 16 bit r/w PHY Specific Ctrl Reg *****/ 1028 /***** PHY_MARV_PHY_CTRL 16 bit r/w PHY Specific Ctrl Reg *****/
1033 enum { 1029 enum {
1034 PHY_M_PC_TX_FFD_MSK = 3<<14,/* Bit 15..14: Tx FIFO Depth Mask */ 1030 PHY_M_PC_TX_FFD_MSK = 3<<14,/* Bit 15..14: Tx FIFO Depth Mask */
1035 PHY_M_PC_RX_FFD_MSK = 3<<12,/* Bit 13..12: Rx FIFO Depth Mask */ 1031 PHY_M_PC_RX_FFD_MSK = 3<<12,/* Bit 13..12: Rx FIFO Depth Mask */
1036 PHY_M_PC_ASS_CRS_TX = 1<<11, /* Assert CRS on Transmit */ 1032 PHY_M_PC_ASS_CRS_TX = 1<<11, /* Assert CRS on Transmit */
1037 PHY_M_PC_FL_GOOD = 1<<10, /* Force Link Good */ 1033 PHY_M_PC_FL_GOOD = 1<<10, /* Force Link Good */
1038 PHY_M_PC_EN_DET_MSK = 3<<8,/* Bit 9.. 8: Energy Detect Mask */ 1034 PHY_M_PC_EN_DET_MSK = 3<<8,/* Bit 9.. 8: Energy Detect Mask */
1039 PHY_M_PC_ENA_EXT_D = 1<<7, /* Enable Ext. Distance (10BT) */ 1035 PHY_M_PC_ENA_EXT_D = 1<<7, /* Enable Ext. Distance (10BT) */
1040 PHY_M_PC_MDIX_MSK = 3<<5,/* Bit 6.. 5: MDI/MDIX Config. Mask */ 1036 PHY_M_PC_MDIX_MSK = 3<<5,/* Bit 6.. 5: MDI/MDIX Config. Mask */
1041 PHY_M_PC_DIS_125CLK = 1<<4, /* Disable 125 CLK */ 1037 PHY_M_PC_DIS_125CLK = 1<<4, /* Disable 125 CLK */
1042 PHY_M_PC_MAC_POW_UP = 1<<3, /* MAC Power up */ 1038 PHY_M_PC_MAC_POW_UP = 1<<3, /* MAC Power up */
1043 PHY_M_PC_SQE_T_ENA = 1<<2, /* SQE Test Enabled */ 1039 PHY_M_PC_SQE_T_ENA = 1<<2, /* SQE Test Enabled */
1044 PHY_M_PC_POL_R_DIS = 1<<1, /* Polarity Reversal Disabled */ 1040 PHY_M_PC_POL_R_DIS = 1<<1, /* Polarity Reversal Disabled */
1045 PHY_M_PC_DIS_JABBER = 1<<0, /* Disable Jabber */ 1041 PHY_M_PC_DIS_JABBER = 1<<0, /* Disable Jabber */
1046 }; 1042 };
1047 1043
1048 enum { 1044 enum {
1049 PHY_M_PC_EN_DET = 2<<8, /* Energy Detect (Mode 1) */ 1045 PHY_M_PC_EN_DET = 2<<8, /* Energy Detect (Mode 1) */
1050 PHY_M_PC_EN_DET_PLUS = 3<<8, /* Energy Detect Plus (Mode 2) */ 1046 PHY_M_PC_EN_DET_PLUS = 3<<8, /* Energy Detect Plus (Mode 2) */
1051 }; 1047 };
1052 1048
1053 #define PHY_M_PC_MDI_XMODE(x) (((x)<<5) & PHY_M_PC_MDIX_MSK) 1049 #define PHY_M_PC_MDI_XMODE(x) (((x)<<5) & PHY_M_PC_MDIX_MSK)
1054 1050
1055 enum { 1051 enum {
1056 PHY_M_PC_MAN_MDI = 0, /* 00 = Manual MDI configuration */ 1052 PHY_M_PC_MAN_MDI = 0, /* 00 = Manual MDI configuration */
1057 PHY_M_PC_MAN_MDIX = 1, /* 01 = Manual MDIX configuration */ 1053 PHY_M_PC_MAN_MDIX = 1, /* 01 = Manual MDIX configuration */
1058 PHY_M_PC_ENA_AUTO = 3, /* 11 = Enable Automatic Crossover */ 1054 PHY_M_PC_ENA_AUTO = 3, /* 11 = Enable Automatic Crossover */
1059 }; 1055 };
1060 1056
1061 /* for 10/100 Fast Ethernet PHY (88E3082 only) */ 1057 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1062 enum { 1058 enum {
1063 PHY_M_PC_ENA_DTE_DT = 1<<15, /* Enable Data Terminal Equ. (DTE) Detect */ 1059 PHY_M_PC_ENA_DTE_DT = 1<<15, /* Enable Data Terminal Equ. (DTE) Detect */
1064 PHY_M_PC_ENA_ENE_DT = 1<<14, /* Enable Energy Detect (sense & pulse) */ 1060 PHY_M_PC_ENA_ENE_DT = 1<<14, /* Enable Energy Detect (sense & pulse) */
1065 PHY_M_PC_DIS_NLP_CK = 1<<13, /* Disable Normal Link Puls (NLP) Check */ 1061 PHY_M_PC_DIS_NLP_CK = 1<<13, /* Disable Normal Link Puls (NLP) Check */
1066 PHY_M_PC_ENA_LIP_NP = 1<<12, /* Enable Link Partner Next Page Reg. */ 1062 PHY_M_PC_ENA_LIP_NP = 1<<12, /* Enable Link Partner Next Page Reg. */
1067 PHY_M_PC_DIS_NLP_GN = 1<<11, /* Disable Normal Link Puls Generation */ 1063 PHY_M_PC_DIS_NLP_GN = 1<<11, /* Disable Normal Link Puls Generation */
1068 1064
1069 PHY_M_PC_DIS_SCRAMB = 1<<9, /* Disable Scrambler */ 1065 PHY_M_PC_DIS_SCRAMB = 1<<9, /* Disable Scrambler */
1070 PHY_M_PC_DIS_FEFI = 1<<8, /* Disable Far End Fault Indic. (FEFI) */ 1066 PHY_M_PC_DIS_FEFI = 1<<8, /* Disable Far End Fault Indic. (FEFI) */
1071 1067
1072 PHY_M_PC_SH_TP_SEL = 1<<6, /* Shielded Twisted Pair Select */ 1068 PHY_M_PC_SH_TP_SEL = 1<<6, /* Shielded Twisted Pair Select */
1073 PHY_M_PC_RX_FD_MSK = 3<<2,/* Bit 3.. 2: Rx FIFO Depth Mask */ 1069 PHY_M_PC_RX_FD_MSK = 3<<2,/* Bit 3.. 2: Rx FIFO Depth Mask */
1074 }; 1070 };
1075 1071
1076 /***** PHY_MARV_PHY_STAT 16 bit r/o PHY Specific Status Reg *****/ 1072 /***** PHY_MARV_PHY_STAT 16 bit r/o PHY Specific Status Reg *****/
1077 enum { 1073 enum {
1078 PHY_M_PS_SPEED_MSK = 3<<14, /* Bit 15..14: Speed Mask */ 1074 PHY_M_PS_SPEED_MSK = 3<<14, /* Bit 15..14: Speed Mask */
1079 PHY_M_PS_SPEED_1000 = 1<<15, /* 10 = 1000 Mbps */ 1075 PHY_M_PS_SPEED_1000 = 1<<15, /* 10 = 1000 Mbps */
1080 PHY_M_PS_SPEED_100 = 1<<14, /* 01 = 100 Mbps */ 1076 PHY_M_PS_SPEED_100 = 1<<14, /* 01 = 100 Mbps */
1081 PHY_M_PS_SPEED_10 = 0, /* 00 = 10 Mbps */ 1077 PHY_M_PS_SPEED_10 = 0, /* 00 = 10 Mbps */
1082 PHY_M_PS_FULL_DUP = 1<<13, /* Full Duplex */ 1078 PHY_M_PS_FULL_DUP = 1<<13, /* Full Duplex */
1083 PHY_M_PS_PAGE_REC = 1<<12, /* Page Received */ 1079 PHY_M_PS_PAGE_REC = 1<<12, /* Page Received */
1084 PHY_M_PS_SPDUP_RES = 1<<11, /* Speed & Duplex Resolved */ 1080 PHY_M_PS_SPDUP_RES = 1<<11, /* Speed & Duplex Resolved */
1085 PHY_M_PS_LINK_UP = 1<<10, /* Link Up */ 1081 PHY_M_PS_LINK_UP = 1<<10, /* Link Up */
1086 PHY_M_PS_CABLE_MSK = 7<<7, /* Bit 9.. 7: Cable Length Mask */ 1082 PHY_M_PS_CABLE_MSK = 7<<7, /* Bit 9.. 7: Cable Length Mask */
1087 PHY_M_PS_MDI_X_STAT = 1<<6, /* MDI Crossover Stat (1=MDIX) */ 1083 PHY_M_PS_MDI_X_STAT = 1<<6, /* MDI Crossover Stat (1=MDIX) */
1088 PHY_M_PS_DOWNS_STAT = 1<<5, /* Downshift Status (1=downsh.) */ 1084 PHY_M_PS_DOWNS_STAT = 1<<5, /* Downshift Status (1=downsh.) */
1089 PHY_M_PS_ENDET_STAT = 1<<4, /* Energy Detect Status (1=act) */ 1085 PHY_M_PS_ENDET_STAT = 1<<4, /* Energy Detect Status (1=act) */
1090 PHY_M_PS_TX_P_EN = 1<<3, /* Tx Pause Enabled */ 1086 PHY_M_PS_TX_P_EN = 1<<3, /* Tx Pause Enabled */
1091 PHY_M_PS_RX_P_EN = 1<<2, /* Rx Pause Enabled */ 1087 PHY_M_PS_RX_P_EN = 1<<2, /* Rx Pause Enabled */
1092 PHY_M_PS_POL_REV = 1<<1, /* Polarity Reversed */ 1088 PHY_M_PS_POL_REV = 1<<1, /* Polarity Reversed */
1093 PHY_M_PS_JABBER = 1<<0, /* Jabber */ 1089 PHY_M_PS_JABBER = 1<<0, /* Jabber */
1094 }; 1090 };
1095 1091
1096 #define PHY_M_PS_PAUSE_MSK (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN) 1092 #define PHY_M_PS_PAUSE_MSK (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN)
1097 1093
1098 /* for 10/100 Fast Ethernet PHY (88E3082 only) */ 1094 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1099 enum { 1095 enum {
1100 PHY_M_PS_DTE_DETECT = 1<<15, /* Data Terminal Equipment (DTE) Detected */ 1096 PHY_M_PS_DTE_DETECT = 1<<15, /* Data Terminal Equipment (DTE) Detected */
1101 PHY_M_PS_RES_SPEED = 1<<14, /* Resolved Speed (1=100 Mbps, 0=10 Mbps */ 1097 PHY_M_PS_RES_SPEED = 1<<14, /* Resolved Speed (1=100 Mbps, 0=10 Mbps */
1102 }; 1098 };
1103 1099
1104 enum { 1100 enum {
1105 PHY_M_IS_AN_ERROR = 1<<15, /* Auto-Negotiation Error */ 1101 PHY_M_IS_AN_ERROR = 1<<15, /* Auto-Negotiation Error */
1106 PHY_M_IS_LSP_CHANGE = 1<<14, /* Link Speed Changed */ 1102 PHY_M_IS_LSP_CHANGE = 1<<14, /* Link Speed Changed */
1107 PHY_M_IS_DUP_CHANGE = 1<<13, /* Duplex Mode Changed */ 1103 PHY_M_IS_DUP_CHANGE = 1<<13, /* Duplex Mode Changed */
1108 PHY_M_IS_AN_PR = 1<<12, /* Page Received */ 1104 PHY_M_IS_AN_PR = 1<<12, /* Page Received */
1109 PHY_M_IS_AN_COMPL = 1<<11, /* Auto-Negotiation Completed */ 1105 PHY_M_IS_AN_COMPL = 1<<11, /* Auto-Negotiation Completed */
1110 PHY_M_IS_LST_CHANGE = 1<<10, /* Link Status Changed */ 1106 PHY_M_IS_LST_CHANGE = 1<<10, /* Link Status Changed */
1111 PHY_M_IS_SYMB_ERROR = 1<<9, /* Symbol Error */ 1107 PHY_M_IS_SYMB_ERROR = 1<<9, /* Symbol Error */
1112 PHY_M_IS_FALSE_CARR = 1<<8, /* False Carrier */ 1108 PHY_M_IS_FALSE_CARR = 1<<8, /* False Carrier */
1113 PHY_M_IS_FIFO_ERROR = 1<<7, /* FIFO Overflow/Underrun Error */ 1109 PHY_M_IS_FIFO_ERROR = 1<<7, /* FIFO Overflow/Underrun Error */
1114 PHY_M_IS_MDI_CHANGE = 1<<6, /* MDI Crossover Changed */ 1110 PHY_M_IS_MDI_CHANGE = 1<<6, /* MDI Crossover Changed */
1115 PHY_M_IS_DOWNSH_DET = 1<<5, /* Downshift Detected */ 1111 PHY_M_IS_DOWNSH_DET = 1<<5, /* Downshift Detected */
1116 PHY_M_IS_END_CHANGE = 1<<4, /* Energy Detect Changed */ 1112 PHY_M_IS_END_CHANGE = 1<<4, /* Energy Detect Changed */
1117 1113
1118 PHY_M_IS_DTE_CHANGE = 1<<2, /* DTE Power Det. Status Changed */ 1114 PHY_M_IS_DTE_CHANGE = 1<<2, /* DTE Power Det. Status Changed */
1119 PHY_M_IS_POL_CHANGE = 1<<1, /* Polarity Changed */ 1115 PHY_M_IS_POL_CHANGE = 1<<1, /* Polarity Changed */
1120 PHY_M_IS_JABBER = 1<<0, /* Jabber */ 1116 PHY_M_IS_JABBER = 1<<0, /* Jabber */
1121 1117
1122 PHY_M_DEF_MSK = PHY_M_IS_LSP_CHANGE | PHY_M_IS_LST_CHANGE 1118 PHY_M_DEF_MSK = PHY_M_IS_LSP_CHANGE | PHY_M_IS_LST_CHANGE
1123 | PHY_M_IS_FIFO_ERROR, 1119 | PHY_M_IS_FIFO_ERROR,
1124 PHY_M_AN_MSK = PHY_M_IS_AN_ERROR | PHY_M_IS_AN_COMPL, 1120 PHY_M_AN_MSK = PHY_M_IS_AN_ERROR | PHY_M_IS_AN_COMPL,
1125 }; 1121 };
1126 1122
1127 1123
1128 /***** PHY_MARV_EXT_CTRL 16 bit r/w Ext. PHY Specific Ctrl *****/ 1124 /***** PHY_MARV_EXT_CTRL 16 bit r/w Ext. PHY Specific Ctrl *****/
1129 enum { 1125 enum {
1130 PHY_M_EC_ENA_BC_EXT = 1<<15, /* Enable Block Carr. Ext. (88E1111 only) */ 1126 PHY_M_EC_ENA_BC_EXT = 1<<15, /* Enable Block Carr. Ext. (88E1111 only) */
1131 PHY_M_EC_ENA_LIN_LB = 1<<14, /* Enable Line Loopback (88E1111 only) */ 1127 PHY_M_EC_ENA_LIN_LB = 1<<14, /* Enable Line Loopback (88E1111 only) */
1132 1128
1133 PHY_M_EC_DIS_LINK_P = 1<<12, /* Disable Link Pulses (88E1111 only) */ 1129 PHY_M_EC_DIS_LINK_P = 1<<12, /* Disable Link Pulses (88E1111 only) */
1134 PHY_M_EC_M_DSC_MSK = 3<<10, /* Bit 11..10: Master Downshift Counter */ 1130 PHY_M_EC_M_DSC_MSK = 3<<10, /* Bit 11..10: Master Downshift Counter */
1135 /* (88E1011 only) */ 1131 /* (88E1011 only) */
1136 PHY_M_EC_S_DSC_MSK = 3<<8,/* Bit 9.. 8: Slave Downshift Counter */ 1132 PHY_M_EC_S_DSC_MSK = 3<<8,/* Bit 9.. 8: Slave Downshift Counter */
1137 /* (88E1011 only) */ 1133 /* (88E1011 only) */
1138 PHY_M_EC_M_DSC_MSK2 = 7<<9,/* Bit 11.. 9: Master Downshift Counter */ 1134 PHY_M_EC_M_DSC_MSK2 = 7<<9,/* Bit 11.. 9: Master Downshift Counter */
1139 /* (88E1111 only) */ 1135 /* (88E1111 only) */
1140 PHY_M_EC_DOWN_S_ENA = 1<<8, /* Downshift Enable (88E1111 only) */ 1136 PHY_M_EC_DOWN_S_ENA = 1<<8, /* Downshift Enable (88E1111 only) */
1141 /* !!! Errata in spec. (1 = disable) */ 1137 /* !!! Errata in spec. (1 = disable) */
1142 PHY_M_EC_RX_TIM_CT = 1<<7, /* RGMII Rx Timing Control*/ 1138 PHY_M_EC_RX_TIM_CT = 1<<7, /* RGMII Rx Timing Control*/
1143 PHY_M_EC_MAC_S_MSK = 7<<4,/* Bit 6.. 4: Def. MAC interface speed */ 1139 PHY_M_EC_MAC_S_MSK = 7<<4,/* Bit 6.. 4: Def. MAC interface speed */
1144 PHY_M_EC_FIB_AN_ENA = 1<<3, /* Fiber Auto-Neg. Enable (88E1011S only) */ 1140 PHY_M_EC_FIB_AN_ENA = 1<<3, /* Fiber Auto-Neg. Enable (88E1011S only) */
1145 PHY_M_EC_DTE_D_ENA = 1<<2, /* DTE Detect Enable (88E1111 only) */ 1141 PHY_M_EC_DTE_D_ENA = 1<<2, /* DTE Detect Enable (88E1111 only) */
1146 PHY_M_EC_TX_TIM_CT = 1<<1, /* RGMII Tx Timing Control */ 1142 PHY_M_EC_TX_TIM_CT = 1<<1, /* RGMII Tx Timing Control */
1147 PHY_M_EC_TRANS_DIS = 1<<0, /* Transmitter Disable (88E1111 only) */}; 1143 PHY_M_EC_TRANS_DIS = 1<<0, /* Transmitter Disable (88E1111 only) */};
1148 1144
1149 #define PHY_M_EC_M_DSC(x) ((x)<<10 & PHY_M_EC_M_DSC_MSK) 1145 #define PHY_M_EC_M_DSC(x) ((x)<<10 & PHY_M_EC_M_DSC_MSK)
1150 /* 00=1x; 01=2x; 10=3x; 11=4x */ 1146 /* 00=1x; 01=2x; 10=3x; 11=4x */
1151 #define PHY_M_EC_S_DSC(x) ((x)<<8 & PHY_M_EC_S_DSC_MSK) 1147 #define PHY_M_EC_S_DSC(x) ((x)<<8 & PHY_M_EC_S_DSC_MSK)
1152 /* 00=dis; 01=1x; 10=2x; 11=3x */ 1148 /* 00=dis; 01=1x; 10=2x; 11=3x */
1153 #define PHY_M_EC_DSC_2(x) ((x)<<9 & PHY_M_EC_M_DSC_MSK2) 1149 #define PHY_M_EC_DSC_2(x) ((x)<<9 & PHY_M_EC_M_DSC_MSK2)
1154 /* 000=1x; 001=2x; 010=3x; 011=4x */ 1150 /* 000=1x; 001=2x; 010=3x; 011=4x */
1155 #define PHY_M_EC_MAC_S(x) ((x)<<4 & PHY_M_EC_MAC_S_MSK) 1151 #define PHY_M_EC_MAC_S(x) ((x)<<4 & PHY_M_EC_MAC_S_MSK)
1156 /* 01X=0; 110=2.5; 111=25 (MHz) */ 1152 /* 01X=0; 110=2.5; 111=25 (MHz) */
1157 1153
1158 /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */ 1154 /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
1159 enum { 1155 enum {
1160 PHY_M_PC_DIS_LINK_Pa = 1<<15,/* Disable Link Pulses */ 1156 PHY_M_PC_DIS_LINK_Pa = 1<<15,/* Disable Link Pulses */
1161 PHY_M_PC_DSC_MSK = 7<<12,/* Bit 14..12: Downshift Counter */ 1157 PHY_M_PC_DSC_MSK = 7<<12,/* Bit 14..12: Downshift Counter */
1162 PHY_M_PC_DOWN_S_ENA = 1<<11,/* Downshift Enable */ 1158 PHY_M_PC_DOWN_S_ENA = 1<<11,/* Downshift Enable */
1163 }; 1159 };
1164 /* !!! Errata in spec. (1 = disable) */ 1160 /* !!! Errata in spec. (1 = disable) */
1165 1161
1166 #define PHY_M_PC_DSC(x) (((x)<<12) & PHY_M_PC_DSC_MSK) 1162 #define PHY_M_PC_DSC(x) (((x)<<12) & PHY_M_PC_DSC_MSK)
1167 /* 100=5x; 101=6x; 110=7x; 111=8x */ 1163 /* 100=5x; 101=6x; 110=7x; 111=8x */
1168 enum { 1164 enum {
1169 MAC_TX_CLK_0_MHZ = 2, 1165 MAC_TX_CLK_0_MHZ = 2,
1170 MAC_TX_CLK_2_5_MHZ = 6, 1166 MAC_TX_CLK_2_5_MHZ = 6,
1171 MAC_TX_CLK_25_MHZ = 7, 1167 MAC_TX_CLK_25_MHZ = 7,
1172 }; 1168 };
1173 1169
1174 /***** PHY_MARV_LED_CTRL 16 bit r/w LED Control Reg *****/ 1170 /***** PHY_MARV_LED_CTRL 16 bit r/w LED Control Reg *****/
1175 enum { 1171 enum {
1176 PHY_M_LEDC_DIS_LED = 1<<15, /* Disable LED */ 1172 PHY_M_LEDC_DIS_LED = 1<<15, /* Disable LED */
1177 PHY_M_LEDC_PULS_MSK = 7<<12,/* Bit 14..12: Pulse Stretch Mask */ 1173 PHY_M_LEDC_PULS_MSK = 7<<12,/* Bit 14..12: Pulse Stretch Mask */
1178 PHY_M_LEDC_F_INT = 1<<11, /* Force Interrupt */ 1174 PHY_M_LEDC_F_INT = 1<<11, /* Force Interrupt */
1179 PHY_M_LEDC_BL_R_MSK = 7<<8,/* Bit 10.. 8: Blink Rate Mask */ 1175 PHY_M_LEDC_BL_R_MSK = 7<<8,/* Bit 10.. 8: Blink Rate Mask */
1180 PHY_M_LEDC_DP_C_LSB = 1<<7, /* Duplex Control (LSB, 88E1111 only) */ 1176 PHY_M_LEDC_DP_C_LSB = 1<<7, /* Duplex Control (LSB, 88E1111 only) */
1181 PHY_M_LEDC_TX_C_LSB = 1<<6, /* Tx Control (LSB, 88E1111 only) */ 1177 PHY_M_LEDC_TX_C_LSB = 1<<6, /* Tx Control (LSB, 88E1111 only) */
1182 PHY_M_LEDC_LK_C_MSK = 7<<3,/* Bit 5.. 3: Link Control Mask */ 1178 PHY_M_LEDC_LK_C_MSK = 7<<3,/* Bit 5.. 3: Link Control Mask */
1183 /* (88E1111 only) */ 1179 /* (88E1111 only) */
1184 }; 1180 };
1185 1181
1186 enum { 1182 enum {
1187 PHY_M_LEDC_LINK_MSK = 3<<3,/* Bit 4.. 3: Link Control Mask */ 1183 PHY_M_LEDC_LINK_MSK = 3<<3,/* Bit 4.. 3: Link Control Mask */
1188 /* (88E1011 only) */ 1184 /* (88E1011 only) */
1189 PHY_M_LEDC_DP_CTRL = 1<<2, /* Duplex Control */ 1185 PHY_M_LEDC_DP_CTRL = 1<<2, /* Duplex Control */
1190 PHY_M_LEDC_DP_C_MSB = 1<<2, /* Duplex Control (MSB, 88E1111 only) */ 1186 PHY_M_LEDC_DP_C_MSB = 1<<2, /* Duplex Control (MSB, 88E1111 only) */
1191 PHY_M_LEDC_RX_CTRL = 1<<1, /* Rx Activity / Link */ 1187 PHY_M_LEDC_RX_CTRL = 1<<1, /* Rx Activity / Link */
1192 PHY_M_LEDC_TX_CTRL = 1<<0, /* Tx Activity / Link */ 1188 PHY_M_LEDC_TX_CTRL = 1<<0, /* Tx Activity / Link */
1193 PHY_M_LEDC_TX_C_MSB = 1<<0, /* Tx Control (MSB, 88E1111 only) */ 1189 PHY_M_LEDC_TX_C_MSB = 1<<0, /* Tx Control (MSB, 88E1111 only) */
1194 }; 1190 };
1195 1191
1196 #define PHY_M_LED_PULS_DUR(x) (((x)<<12) & PHY_M_LEDC_PULS_MSK) 1192 #define PHY_M_LED_PULS_DUR(x) (((x)<<12) & PHY_M_LEDC_PULS_MSK)
1197 1193
1198 /***** PHY_MARV_PHY_STAT (page 3)16 bit r/w Polarity Control Reg. *****/ 1194 /***** PHY_MARV_PHY_STAT (page 3)16 bit r/w Polarity Control Reg. *****/
1199 enum { 1195 enum {
1200 PHY_M_POLC_LS1M_MSK = 0xf<<12, /* Bit 15..12: LOS,STAT1 Mix % Mask */ 1196 PHY_M_POLC_LS1M_MSK = 0xf<<12, /* Bit 15..12: LOS,STAT1 Mix % Mask */
1201 PHY_M_POLC_IS0M_MSK = 0xf<<8, /* Bit 11.. 8: INIT,STAT0 Mix % Mask */ 1197 PHY_M_POLC_IS0M_MSK = 0xf<<8, /* Bit 11.. 8: INIT,STAT0 Mix % Mask */
1202 PHY_M_POLC_LOS_MSK = 0x3<<6, /* Bit 7.. 6: LOS Pol. Ctrl. Mask */ 1198 PHY_M_POLC_LOS_MSK = 0x3<<6, /* Bit 7.. 6: LOS Pol. Ctrl. Mask */
1203 PHY_M_POLC_INIT_MSK = 0x3<<4, /* Bit 5.. 4: INIT Pol. Ctrl. Mask */ 1199 PHY_M_POLC_INIT_MSK = 0x3<<4, /* Bit 5.. 4: INIT Pol. Ctrl. Mask */
1204 PHY_M_POLC_STA1_MSK = 0x3<<2, /* Bit 3.. 2: STAT1 Pol. Ctrl. Mask */ 1200 PHY_M_POLC_STA1_MSK = 0x3<<2, /* Bit 3.. 2: STAT1 Pol. Ctrl. Mask */
1205 PHY_M_POLC_STA0_MSK = 0x3, /* Bit 1.. 0: STAT0 Pol. Ctrl. Mask */ 1201 PHY_M_POLC_STA0_MSK = 0x3, /* Bit 1.. 0: STAT0 Pol. Ctrl. Mask */
1206 }; 1202 };
1207 1203
1208 #define PHY_M_POLC_LS1_P_MIX(x) (((x)<<12) & PHY_M_POLC_LS1M_MSK) 1204 #define PHY_M_POLC_LS1_P_MIX(x) (((x)<<12) & PHY_M_POLC_LS1M_MSK)
1209 #define PHY_M_POLC_IS0_P_MIX(x) (((x)<<8) & PHY_M_POLC_IS0M_MSK) 1205 #define PHY_M_POLC_IS0_P_MIX(x) (((x)<<8) & PHY_M_POLC_IS0M_MSK)
1210 #define PHY_M_POLC_LOS_CTRL(x) (((x)<<6) & PHY_M_POLC_LOS_MSK) 1206 #define PHY_M_POLC_LOS_CTRL(x) (((x)<<6) & PHY_M_POLC_LOS_MSK)
1211 #define PHY_M_POLC_INIT_CTRL(x) (((x)<<4) & PHY_M_POLC_INIT_MSK) 1207 #define PHY_M_POLC_INIT_CTRL(x) (((x)<<4) & PHY_M_POLC_INIT_MSK)
1212 #define PHY_M_POLC_STA1_CTRL(x) (((x)<<2) & PHY_M_POLC_STA1_MSK) 1208 #define PHY_M_POLC_STA1_CTRL(x) (((x)<<2) & PHY_M_POLC_STA1_MSK)
1213 #define PHY_M_POLC_STA0_CTRL(x) (((x)<<0) & PHY_M_POLC_STA0_MSK) 1209 #define PHY_M_POLC_STA0_CTRL(x) (((x)<<0) & PHY_M_POLC_STA0_MSK)
1214 1210
1215 enum { 1211 enum {
1216 PULS_NO_STR = 0,/* no pulse stretching */ 1212 PULS_NO_STR = 0,/* no pulse stretching */
1217 PULS_21MS = 1,/* 21 ms to 42 ms */ 1213 PULS_21MS = 1,/* 21 ms to 42 ms */
1218 PULS_42MS = 2,/* 42 ms to 84 ms */ 1214 PULS_42MS = 2,/* 42 ms to 84 ms */
1219 PULS_84MS = 3,/* 84 ms to 170 ms */ 1215 PULS_84MS = 3,/* 84 ms to 170 ms */
1220 PULS_170MS = 4,/* 170 ms to 340 ms */ 1216 PULS_170MS = 4,/* 170 ms to 340 ms */
1221 PULS_340MS = 5,/* 340 ms to 670 ms */ 1217 PULS_340MS = 5,/* 340 ms to 670 ms */
1222 PULS_670MS = 6,/* 670 ms to 1.3 s */ 1218 PULS_670MS = 6,/* 670 ms to 1.3 s */
1223 PULS_1300MS = 7,/* 1.3 s to 2.7 s */ 1219 PULS_1300MS = 7,/* 1.3 s to 2.7 s */
1224 }; 1220 };
1225 1221
1226 #define PHY_M_LED_BLINK_RT(x) (((x)<<8) & PHY_M_LEDC_BL_R_MSK) 1222 #define PHY_M_LED_BLINK_RT(x) (((x)<<8) & PHY_M_LEDC_BL_R_MSK)
1227 1223
1228 enum { 1224 enum {
1229 BLINK_42MS = 0,/* 42 ms */ 1225 BLINK_42MS = 0,/* 42 ms */
1230 BLINK_84MS = 1,/* 84 ms */ 1226 BLINK_84MS = 1,/* 84 ms */
1231 BLINK_170MS = 2,/* 170 ms */ 1227 BLINK_170MS = 2,/* 170 ms */
1232 BLINK_340MS = 3,/* 340 ms */ 1228 BLINK_340MS = 3,/* 340 ms */
1233 BLINK_670MS = 4,/* 670 ms */ 1229 BLINK_670MS = 4,/* 670 ms */
1234 }; 1230 };
1235 1231
1236 /***** PHY_MARV_LED_OVER 16 bit r/w Manual LED Override Reg *****/ 1232 /***** PHY_MARV_LED_OVER 16 bit r/w Manual LED Override Reg *****/
1237 #define PHY_M_LED_MO_SGMII(x) ((x)<<14) /* Bit 15..14: SGMII AN Timer */ 1233 #define PHY_M_LED_MO_SGMII(x) ((x)<<14) /* Bit 15..14: SGMII AN Timer */
1238 /* Bit 13..12: reserved */ 1234 /* Bit 13..12: reserved */
1239 #define PHY_M_LED_MO_DUP(x) ((x)<<10) /* Bit 11..10: Duplex */ 1235 #define PHY_M_LED_MO_DUP(x) ((x)<<10) /* Bit 11..10: Duplex */
1240 #define PHY_M_LED_MO_10(x) ((x)<<8) /* Bit 9.. 8: Link 10 */ 1236 #define PHY_M_LED_MO_10(x) ((x)<<8) /* Bit 9.. 8: Link 10 */
1241 #define PHY_M_LED_MO_100(x) ((x)<<6) /* Bit 7.. 6: Link 100 */ 1237 #define PHY_M_LED_MO_100(x) ((x)<<6) /* Bit 7.. 6: Link 100 */
1242 #define PHY_M_LED_MO_1000(x) ((x)<<4) /* Bit 5.. 4: Link 1000 */ 1238 #define PHY_M_LED_MO_1000(x) ((x)<<4) /* Bit 5.. 4: Link 1000 */
1243 #define PHY_M_LED_MO_RX(x) ((x)<<2) /* Bit 3.. 2: Rx */ 1239 #define PHY_M_LED_MO_RX(x) ((x)<<2) /* Bit 3.. 2: Rx */
1244 #define PHY_M_LED_MO_TX(x) ((x)<<0) /* Bit 1.. 0: Tx */ 1240 #define PHY_M_LED_MO_TX(x) ((x)<<0) /* Bit 1.. 0: Tx */
1245 1241
1246 enum { 1242 enum {
1247 MO_LED_NORM = 0, 1243 MO_LED_NORM = 0,
1248 MO_LED_BLINK = 1, 1244 MO_LED_BLINK = 1,
1249 MO_LED_OFF = 2, 1245 MO_LED_OFF = 2,
1250 MO_LED_ON = 3, 1246 MO_LED_ON = 3,
1251 }; 1247 };
1252 1248
1253 /***** PHY_MARV_EXT_CTRL_2 16 bit r/w Ext. PHY Specific Ctrl 2 *****/ 1249 /***** PHY_MARV_EXT_CTRL_2 16 bit r/w Ext. PHY Specific Ctrl 2 *****/
1254 enum { 1250 enum {
1255 PHY_M_EC2_FI_IMPED = 1<<6, /* Fiber Input Impedance */ 1251 PHY_M_EC2_FI_IMPED = 1<<6, /* Fiber Input Impedance */
1256 PHY_M_EC2_FO_IMPED = 1<<5, /* Fiber Output Impedance */ 1252 PHY_M_EC2_FO_IMPED = 1<<5, /* Fiber Output Impedance */
1257 PHY_M_EC2_FO_M_CLK = 1<<4, /* Fiber Mode Clock Enable */ 1253 PHY_M_EC2_FO_M_CLK = 1<<4, /* Fiber Mode Clock Enable */
1258 PHY_M_EC2_FO_BOOST = 1<<3, /* Fiber Output Boost */ 1254 PHY_M_EC2_FO_BOOST = 1<<3, /* Fiber Output Boost */
1259 PHY_M_EC2_FO_AM_MSK = 7,/* Bit 2.. 0: Fiber Output Amplitude */ 1255 PHY_M_EC2_FO_AM_MSK = 7,/* Bit 2.. 0: Fiber Output Amplitude */
1260 }; 1256 };
1261 1257
1262 /***** PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status *****/ 1258 /***** PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status *****/
1263 enum { 1259 enum {
1264 PHY_M_FC_AUTO_SEL = 1<<15, /* Fiber/Copper Auto Sel. Dis. */ 1260 PHY_M_FC_AUTO_SEL = 1<<15, /* Fiber/Copper Auto Sel. Dis. */
1265 PHY_M_FC_AN_REG_ACC = 1<<14, /* Fiber/Copper AN Reg. Access */ 1261 PHY_M_FC_AN_REG_ACC = 1<<14, /* Fiber/Copper AN Reg. Access */
1266 PHY_M_FC_RESOLUTION = 1<<13, /* Fiber/Copper Resolution */ 1262 PHY_M_FC_RESOLUTION = 1<<13, /* Fiber/Copper Resolution */
1267 PHY_M_SER_IF_AN_BP = 1<<12, /* Ser. IF AN Bypass Enable */ 1263 PHY_M_SER_IF_AN_BP = 1<<12, /* Ser. IF AN Bypass Enable */
1268 PHY_M_SER_IF_BP_ST = 1<<11, /* Ser. IF AN Bypass Status */ 1264 PHY_M_SER_IF_BP_ST = 1<<11, /* Ser. IF AN Bypass Status */
1269 PHY_M_IRQ_POLARITY = 1<<10, /* IRQ polarity */ 1265 PHY_M_IRQ_POLARITY = 1<<10, /* IRQ polarity */
1270 PHY_M_DIS_AUT_MED = 1<<9, /* Disable Aut. Medium Reg. Selection */ 1266 PHY_M_DIS_AUT_MED = 1<<9, /* Disable Aut. Medium Reg. Selection */
1271 /* (88E1111 only) */ 1267 /* (88E1111 only) */
1272 1268
1273 PHY_M_UNDOC1 = 1<<7, /* undocumented bit !! */ 1269 PHY_M_UNDOC1 = 1<<7, /* undocumented bit !! */
1274 PHY_M_DTE_POW_STAT = 1<<4, /* DTE Power Status (88E1111 only) */ 1270 PHY_M_DTE_POW_STAT = 1<<4, /* DTE Power Status (88E1111 only) */
1275 PHY_M_MODE_MASK = 0xf, /* Bit 3.. 0: copy of HWCFG MODE[3:0] */ 1271 PHY_M_MODE_MASK = 0xf, /* Bit 3.. 0: copy of HWCFG MODE[3:0] */
1276 }; 1272 };
1277 1273
1278 /* for 10/100 Fast Ethernet PHY (88E3082 only) */ 1274 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1279 /***** PHY_MARV_FE_LED_PAR 16 bit r/w LED Parallel Select Reg. *****/ 1275 /***** PHY_MARV_FE_LED_PAR 16 bit r/w LED Parallel Select Reg. *****/
1280 /* Bit 15..12: reserved (used internally) */ 1276 /* Bit 15..12: reserved (used internally) */
1281 enum { 1277 enum {
1282 PHY_M_FELP_LED2_MSK = 0xf<<8, /* Bit 11.. 8: LED2 Mask (LINK) */ 1278 PHY_M_FELP_LED2_MSK = 0xf<<8, /* Bit 11.. 8: LED2 Mask (LINK) */
1283 PHY_M_FELP_LED1_MSK = 0xf<<4, /* Bit 7.. 4: LED1 Mask (ACT) */ 1279 PHY_M_FELP_LED1_MSK = 0xf<<4, /* Bit 7.. 4: LED1 Mask (ACT) */
1284 PHY_M_FELP_LED0_MSK = 0xf, /* Bit 3.. 0: LED0 Mask (SPEED) */ 1280 PHY_M_FELP_LED0_MSK = 0xf, /* Bit 3.. 0: LED0 Mask (SPEED) */
1285 }; 1281 };
1286 1282
1287 #define PHY_M_FELP_LED2_CTRL(x) (((x)<<8) & PHY_M_FELP_LED2_MSK) 1283 #define PHY_M_FELP_LED2_CTRL(x) (((x)<<8) & PHY_M_FELP_LED2_MSK)
1288 #define PHY_M_FELP_LED1_CTRL(x) (((x)<<4) & PHY_M_FELP_LED1_MSK) 1284 #define PHY_M_FELP_LED1_CTRL(x) (((x)<<4) & PHY_M_FELP_LED1_MSK)
1289 #define PHY_M_FELP_LED0_CTRL(x) (((x)<<0) & PHY_M_FELP_LED0_MSK) 1285 #define PHY_M_FELP_LED0_CTRL(x) (((x)<<0) & PHY_M_FELP_LED0_MSK)
1290 1286
1291 enum { 1287 enum {
1292 LED_PAR_CTRL_COLX = 0x00, 1288 LED_PAR_CTRL_COLX = 0x00,
1293 LED_PAR_CTRL_ERROR = 0x01, 1289 LED_PAR_CTRL_ERROR = 0x01,
1294 LED_PAR_CTRL_DUPLEX = 0x02, 1290 LED_PAR_CTRL_DUPLEX = 0x02,
1295 LED_PAR_CTRL_DP_COL = 0x03, 1291 LED_PAR_CTRL_DP_COL = 0x03,
1296 LED_PAR_CTRL_SPEED = 0x04, 1292 LED_PAR_CTRL_SPEED = 0x04,
1297 LED_PAR_CTRL_LINK = 0x05, 1293 LED_PAR_CTRL_LINK = 0x05,
1298 LED_PAR_CTRL_TX = 0x06, 1294 LED_PAR_CTRL_TX = 0x06,
1299 LED_PAR_CTRL_RX = 0x07, 1295 LED_PAR_CTRL_RX = 0x07,
1300 LED_PAR_CTRL_ACT = 0x08, 1296 LED_PAR_CTRL_ACT = 0x08,
1301 LED_PAR_CTRL_LNK_RX = 0x09, 1297 LED_PAR_CTRL_LNK_RX = 0x09,
1302 LED_PAR_CTRL_LNK_AC = 0x0a, 1298 LED_PAR_CTRL_LNK_AC = 0x0a,
1303 LED_PAR_CTRL_ACT_BL = 0x0b, 1299 LED_PAR_CTRL_ACT_BL = 0x0b,
1304 LED_PAR_CTRL_TX_BL = 0x0c, 1300 LED_PAR_CTRL_TX_BL = 0x0c,
1305 LED_PAR_CTRL_RX_BL = 0x0d, 1301 LED_PAR_CTRL_RX_BL = 0x0d,
1306 LED_PAR_CTRL_COL_BL = 0x0e, 1302 LED_PAR_CTRL_COL_BL = 0x0e,
1307 LED_PAR_CTRL_INACT = 0x0f 1303 LED_PAR_CTRL_INACT = 0x0f
1308 }; 1304 };
1309 1305
1310 /*****,PHY_MARV_FE_SPEC_2 16 bit r/w Specific Control Reg. 2 *****/ 1306 /*****,PHY_MARV_FE_SPEC_2 16 bit r/w Specific Control Reg. 2 *****/
1311 enum { 1307 enum {
1312 PHY_M_FESC_DIS_WAIT = 1<<2, /* Disable TDR Waiting Period */ 1308 PHY_M_FESC_DIS_WAIT = 1<<2, /* Disable TDR Waiting Period */
1313 PHY_M_FESC_ENA_MCLK = 1<<1, /* Enable MAC Rx Clock in sleep mode */ 1309 PHY_M_FESC_ENA_MCLK = 1<<1, /* Enable MAC Rx Clock in sleep mode */
1314 PHY_M_FESC_SEL_CL_A = 1<<0, /* Select Class A driver (100B-TX) */ 1310 PHY_M_FESC_SEL_CL_A = 1<<0, /* Select Class A driver (100B-TX) */
1315 }; 1311 };
1316 1312
1317 /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */ 1313 /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
1318 /***** PHY_MARV_PHY_CTRL (page 2) 16 bit r/w MAC Specific Ctrl *****/ 1314 /***** PHY_MARV_PHY_CTRL (page 2) 16 bit r/w MAC Specific Ctrl *****/
1319 enum { 1315 enum {
1320 PHY_M_MAC_MD_MSK = 7<<7, /* Bit 9.. 7: Mode Select Mask */ 1316 PHY_M_MAC_MD_MSK = 7<<7, /* Bit 9.. 7: Mode Select Mask */
1321 PHY_M_MAC_MD_AUTO = 3,/* Auto Copper/1000Base-X */ 1317 PHY_M_MAC_MD_AUTO = 3,/* Auto Copper/1000Base-X */
1322 PHY_M_MAC_MD_COPPER = 5,/* Copper only */ 1318 PHY_M_MAC_MD_COPPER = 5,/* Copper only */
1323 PHY_M_MAC_MD_1000BX = 7,/* 1000Base-X only */ 1319 PHY_M_MAC_MD_1000BX = 7,/* 1000Base-X only */
1324 }; 1320 };
1325 #define PHY_M_MAC_MODE_SEL(x) (((x)<<7) & PHY_M_MAC_MD_MSK) 1321 #define PHY_M_MAC_MODE_SEL(x) (((x)<<7) & PHY_M_MAC_MD_MSK)
1326 1322
1327 /***** PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. *****/ 1323 /***** PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. *****/
1328 enum { 1324 enum {
1329 PHY_M_LEDC_LOS_MSK = 0xf<<12,/* Bit 15..12: LOS LED Ctrl. Mask */ 1325 PHY_M_LEDC_LOS_MSK = 0xf<<12,/* Bit 15..12: LOS LED Ctrl. Mask */
1330 PHY_M_LEDC_INIT_MSK = 0xf<<8, /* Bit 11.. 8: INIT LED Ctrl. Mask */ 1326 PHY_M_LEDC_INIT_MSK = 0xf<<8, /* Bit 11.. 8: INIT LED Ctrl. Mask */
1331 PHY_M_LEDC_STA1_MSK = 0xf<<4,/* Bit 7.. 4: STAT1 LED Ctrl. Mask */ 1327 PHY_M_LEDC_STA1_MSK = 0xf<<4,/* Bit 7.. 4: STAT1 LED Ctrl. Mask */
1332 PHY_M_LEDC_STA0_MSK = 0xf, /* Bit 3.. 0: STAT0 LED Ctrl. Mask */ 1328 PHY_M_LEDC_STA0_MSK = 0xf, /* Bit 3.. 0: STAT0 LED Ctrl. Mask */
1333 }; 1329 };
1334 1330
1335 #define PHY_M_LEDC_LOS_CTRL(x) (((x)<<12) & PHY_M_LEDC_LOS_MSK) 1331 #define PHY_M_LEDC_LOS_CTRL(x) (((x)<<12) & PHY_M_LEDC_LOS_MSK)
1336 #define PHY_M_LEDC_INIT_CTRL(x) (((x)<<8) & PHY_M_LEDC_INIT_MSK) 1332 #define PHY_M_LEDC_INIT_CTRL(x) (((x)<<8) & PHY_M_LEDC_INIT_MSK)
1337 #define PHY_M_LEDC_STA1_CTRL(x) (((x)<<4) & PHY_M_LEDC_STA1_MSK) 1333 #define PHY_M_LEDC_STA1_CTRL(x) (((x)<<4) & PHY_M_LEDC_STA1_MSK)
1338 #define PHY_M_LEDC_STA0_CTRL(x) (((x)<<0) & PHY_M_LEDC_STA0_MSK) 1334 #define PHY_M_LEDC_STA0_CTRL(x) (((x)<<0) & PHY_M_LEDC_STA0_MSK)
1339 1335
1340 /* GMAC registers */ 1336 /* GMAC registers */
1341 /* Port Registers */ 1337 /* Port Registers */
1342 enum { 1338 enum {
1343 GM_GP_STAT = 0x0000, /* 16 bit r/o General Purpose Status */ 1339 GM_GP_STAT = 0x0000, /* 16 bit r/o General Purpose Status */
1344 GM_GP_CTRL = 0x0004, /* 16 bit r/w General Purpose Control */ 1340 GM_GP_CTRL = 0x0004, /* 16 bit r/w General Purpose Control */
1345 GM_TX_CTRL = 0x0008, /* 16 bit r/w Transmit Control Reg. */ 1341 GM_TX_CTRL = 0x0008, /* 16 bit r/w Transmit Control Reg. */
1346 GM_RX_CTRL = 0x000c, /* 16 bit r/w Receive Control Reg. */ 1342 GM_RX_CTRL = 0x000c, /* 16 bit r/w Receive Control Reg. */
1347 GM_TX_FLOW_CTRL = 0x0010, /* 16 bit r/w Transmit Flow-Control */ 1343 GM_TX_FLOW_CTRL = 0x0010, /* 16 bit r/w Transmit Flow-Control */
1348 GM_TX_PARAM = 0x0014, /* 16 bit r/w Transmit Parameter Reg. */ 1344 GM_TX_PARAM = 0x0014, /* 16 bit r/w Transmit Parameter Reg. */
1349 GM_SERIAL_MODE = 0x0018, /* 16 bit r/w Serial Mode Register */ 1345 GM_SERIAL_MODE = 0x0018, /* 16 bit r/w Serial Mode Register */
1350 /* Source Address Registers */ 1346 /* Source Address Registers */
1351 GM_SRC_ADDR_1L = 0x001c, /* 16 bit r/w Source Address 1 (low) */ 1347 GM_SRC_ADDR_1L = 0x001c, /* 16 bit r/w Source Address 1 (low) */
1352 GM_SRC_ADDR_1M = 0x0020, /* 16 bit r/w Source Address 1 (middle) */ 1348 GM_SRC_ADDR_1M = 0x0020, /* 16 bit r/w Source Address 1 (middle) */
1353 GM_SRC_ADDR_1H = 0x0024, /* 16 bit r/w Source Address 1 (high) */ 1349 GM_SRC_ADDR_1H = 0x0024, /* 16 bit r/w Source Address 1 (high) */
1354 GM_SRC_ADDR_2L = 0x0028, /* 16 bit r/w Source Address 2 (low) */ 1350 GM_SRC_ADDR_2L = 0x0028, /* 16 bit r/w Source Address 2 (low) */
1355 GM_SRC_ADDR_2M = 0x002c, /* 16 bit r/w Source Address 2 (middle) */ 1351 GM_SRC_ADDR_2M = 0x002c, /* 16 bit r/w Source Address 2 (middle) */
1356 GM_SRC_ADDR_2H = 0x0030, /* 16 bit r/w Source Address 2 (high) */ 1352 GM_SRC_ADDR_2H = 0x0030, /* 16 bit r/w Source Address 2 (high) */
1357 1353
1358 /* Multicast Address Hash Registers */ 1354 /* Multicast Address Hash Registers */
1359 GM_MC_ADDR_H1 = 0x0034, /* 16 bit r/w Multicast Address Hash 1 */ 1355 GM_MC_ADDR_H1 = 0x0034, /* 16 bit r/w Multicast Address Hash 1 */
1360 GM_MC_ADDR_H2 = 0x0038, /* 16 bit r/w Multicast Address Hash 2 */ 1356 GM_MC_ADDR_H2 = 0x0038, /* 16 bit r/w Multicast Address Hash 2 */
1361 GM_MC_ADDR_H3 = 0x003c, /* 16 bit r/w Multicast Address Hash 3 */ 1357 GM_MC_ADDR_H3 = 0x003c, /* 16 bit r/w Multicast Address Hash 3 */
1362 GM_MC_ADDR_H4 = 0x0040, /* 16 bit r/w Multicast Address Hash 4 */ 1358 GM_MC_ADDR_H4 = 0x0040, /* 16 bit r/w Multicast Address Hash 4 */
1363 1359
1364 /* Interrupt Source Registers */ 1360 /* Interrupt Source Registers */
1365 GM_TX_IRQ_SRC = 0x0044, /* 16 bit r/o Tx Overflow IRQ Source */ 1361 GM_TX_IRQ_SRC = 0x0044, /* 16 bit r/o Tx Overflow IRQ Source */
1366 GM_RX_IRQ_SRC = 0x0048, /* 16 bit r/o Rx Overflow IRQ Source */ 1362 GM_RX_IRQ_SRC = 0x0048, /* 16 bit r/o Rx Overflow IRQ Source */
1367 GM_TR_IRQ_SRC = 0x004c, /* 16 bit r/o Tx/Rx Over. IRQ Source */ 1363 GM_TR_IRQ_SRC = 0x004c, /* 16 bit r/o Tx/Rx Over. IRQ Source */
1368 1364
1369 /* Interrupt Mask Registers */ 1365 /* Interrupt Mask Registers */
1370 GM_TX_IRQ_MSK = 0x0050, /* 16 bit r/w Tx Overflow IRQ Mask */ 1366 GM_TX_IRQ_MSK = 0x0050, /* 16 bit r/w Tx Overflow IRQ Mask */
1371 GM_RX_IRQ_MSK = 0x0054, /* 16 bit r/w Rx Overflow IRQ Mask */ 1367 GM_RX_IRQ_MSK = 0x0054, /* 16 bit r/w Rx Overflow IRQ Mask */
1372 GM_TR_IRQ_MSK = 0x0058, /* 16 bit r/w Tx/Rx Over. IRQ Mask */ 1368 GM_TR_IRQ_MSK = 0x0058, /* 16 bit r/w Tx/Rx Over. IRQ Mask */
1373 1369
1374 /* Serial Management Interface (SMI) Registers */ 1370 /* Serial Management Interface (SMI) Registers */
1375 GM_SMI_CTRL = 0x0080, /* 16 bit r/w SMI Control Register */ 1371 GM_SMI_CTRL = 0x0080, /* 16 bit r/w SMI Control Register */
1376 GM_SMI_DATA = 0x0084, /* 16 bit r/w SMI Data Register */ 1372 GM_SMI_DATA = 0x0084, /* 16 bit r/w SMI Data Register */
1377 GM_PHY_ADDR = 0x0088, /* 16 bit r/w GPHY Address Register */ 1373 GM_PHY_ADDR = 0x0088, /* 16 bit r/w GPHY Address Register */
1378 }; 1374 };
1379 1375
1380 /* MIB Counters */ 1376 /* MIB Counters */
1381 #define GM_MIB_CNT_BASE 0x0100 /* Base Address of MIB Counters */ 1377 #define GM_MIB_CNT_BASE 0x0100 /* Base Address of MIB Counters */
1382 #define GM_MIB_CNT_SIZE 44 /* Number of MIB Counters */ 1378 #define GM_MIB_CNT_SIZE 44 /* Number of MIB Counters */
1383 1379
1384 /* 1380 /*
1385 * MIB Counters base address definitions (low word) - 1381 * MIB Counters base address definitions (low word) -
1386 * use offset 4 for access to high word (32 bit r/o) 1382 * use offset 4 for access to high word (32 bit r/o)
1387 */ 1383 */
1388 enum { 1384 enum {
1389 GM_RXF_UC_OK = GM_MIB_CNT_BASE + 0, /* Unicast Frames Received OK */ 1385 GM_RXF_UC_OK = GM_MIB_CNT_BASE + 0, /* Unicast Frames Received OK */
1390 GM_RXF_BC_OK = GM_MIB_CNT_BASE + 8, /* Broadcast Frames Received OK */ 1386 GM_RXF_BC_OK = GM_MIB_CNT_BASE + 8, /* Broadcast Frames Received OK */
1391 GM_RXF_MPAUSE = GM_MIB_CNT_BASE + 16, /* Pause MAC Ctrl Frames Received */ 1387 GM_RXF_MPAUSE = GM_MIB_CNT_BASE + 16, /* Pause MAC Ctrl Frames Received */
1392 GM_RXF_MC_OK = GM_MIB_CNT_BASE + 24, /* Multicast Frames Received OK */ 1388 GM_RXF_MC_OK = GM_MIB_CNT_BASE + 24, /* Multicast Frames Received OK */
1393 GM_RXF_FCS_ERR = GM_MIB_CNT_BASE + 32, /* Rx Frame Check Seq. Error */ 1389 GM_RXF_FCS_ERR = GM_MIB_CNT_BASE + 32, /* Rx Frame Check Seq. Error */
1394 /* GM_MIB_CNT_BASE + 40: reserved */ 1390 /* GM_MIB_CNT_BASE + 40: reserved */
1395 GM_RXO_OK_LO = GM_MIB_CNT_BASE + 48, /* Octets Received OK Low */ 1391 GM_RXO_OK_LO = GM_MIB_CNT_BASE + 48, /* Octets Received OK Low */
1396 GM_RXO_OK_HI = GM_MIB_CNT_BASE + 56, /* Octets Received OK High */ 1392 GM_RXO_OK_HI = GM_MIB_CNT_BASE + 56, /* Octets Received OK High */
1397 GM_RXO_ERR_LO = GM_MIB_CNT_BASE + 64, /* Octets Received Invalid Low */ 1393 GM_RXO_ERR_LO = GM_MIB_CNT_BASE + 64, /* Octets Received Invalid Low */
1398 GM_RXO_ERR_HI = GM_MIB_CNT_BASE + 72, /* Octets Received Invalid High */ 1394 GM_RXO_ERR_HI = GM_MIB_CNT_BASE + 72, /* Octets Received Invalid High */
1399 GM_RXF_SHT = GM_MIB_CNT_BASE + 80, /* Frames <64 Byte Received OK */ 1395 GM_RXF_SHT = GM_MIB_CNT_BASE + 80, /* Frames <64 Byte Received OK */
1400 GM_RXE_FRAG = GM_MIB_CNT_BASE + 88, /* Frames <64 Byte Received with FCS Err */ 1396 GM_RXE_FRAG = GM_MIB_CNT_BASE + 88, /* Frames <64 Byte Received with FCS Err */
1401 GM_RXF_64B = GM_MIB_CNT_BASE + 96, /* 64 Byte Rx Frame */ 1397 GM_RXF_64B = GM_MIB_CNT_BASE + 96, /* 64 Byte Rx Frame */
1402 GM_RXF_127B = GM_MIB_CNT_BASE + 104, /* 65-127 Byte Rx Frame */ 1398 GM_RXF_127B = GM_MIB_CNT_BASE + 104, /* 65-127 Byte Rx Frame */
1403 GM_RXF_255B = GM_MIB_CNT_BASE + 112, /* 128-255 Byte Rx Frame */ 1399 GM_RXF_255B = GM_MIB_CNT_BASE + 112, /* 128-255 Byte Rx Frame */
1404 GM_RXF_511B = GM_MIB_CNT_BASE + 120, /* 256-511 Byte Rx Frame */ 1400 GM_RXF_511B = GM_MIB_CNT_BASE + 120, /* 256-511 Byte Rx Frame */
1405 GM_RXF_1023B = GM_MIB_CNT_BASE + 128, /* 512-1023 Byte Rx Frame */ 1401 GM_RXF_1023B = GM_MIB_CNT_BASE + 128, /* 512-1023 Byte Rx Frame */
1406 GM_RXF_1518B = GM_MIB_CNT_BASE + 136, /* 1024-1518 Byte Rx Frame */ 1402 GM_RXF_1518B = GM_MIB_CNT_BASE + 136, /* 1024-1518 Byte Rx Frame */
1407 GM_RXF_MAX_SZ = GM_MIB_CNT_BASE + 144, /* 1519-MaxSize Byte Rx Frame */ 1403 GM_RXF_MAX_SZ = GM_MIB_CNT_BASE + 144, /* 1519-MaxSize Byte Rx Frame */
1408 GM_RXF_LNG_ERR = GM_MIB_CNT_BASE + 152, /* Rx Frame too Long Error */ 1404 GM_RXF_LNG_ERR = GM_MIB_CNT_BASE + 152, /* Rx Frame too Long Error */
1409 GM_RXF_JAB_PKT = GM_MIB_CNT_BASE + 160, /* Rx Jabber Packet Frame */ 1405 GM_RXF_JAB_PKT = GM_MIB_CNT_BASE + 160, /* Rx Jabber Packet Frame */
1410 /* GM_MIB_CNT_BASE + 168: reserved */ 1406 /* GM_MIB_CNT_BASE + 168: reserved */
1411 GM_RXE_FIFO_OV = GM_MIB_CNT_BASE + 176, /* Rx FIFO overflow Event */ 1407 GM_RXE_FIFO_OV = GM_MIB_CNT_BASE + 176, /* Rx FIFO overflow Event */
1412 /* GM_MIB_CNT_BASE + 184: reserved */ 1408 /* GM_MIB_CNT_BASE + 184: reserved */
1413 GM_TXF_UC_OK = GM_MIB_CNT_BASE + 192, /* Unicast Frames Xmitted OK */ 1409 GM_TXF_UC_OK = GM_MIB_CNT_BASE + 192, /* Unicast Frames Xmitted OK */
1414 GM_TXF_BC_OK = GM_MIB_CNT_BASE + 200, /* Broadcast Frames Xmitted OK */ 1410 GM_TXF_BC_OK = GM_MIB_CNT_BASE + 200, /* Broadcast Frames Xmitted OK */
1415 GM_TXF_MPAUSE = GM_MIB_CNT_BASE + 208, /* Pause MAC Ctrl Frames Xmitted */ 1411 GM_TXF_MPAUSE = GM_MIB_CNT_BASE + 208, /* Pause MAC Ctrl Frames Xmitted */
1416 GM_TXF_MC_OK = GM_MIB_CNT_BASE + 216, /* Multicast Frames Xmitted OK */ 1412 GM_TXF_MC_OK = GM_MIB_CNT_BASE + 216, /* Multicast Frames Xmitted OK */
1417 GM_TXO_OK_LO = GM_MIB_CNT_BASE + 224, /* Octets Transmitted OK Low */ 1413 GM_TXO_OK_LO = GM_MIB_CNT_BASE + 224, /* Octets Transmitted OK Low */
1418 GM_TXO_OK_HI = GM_MIB_CNT_BASE + 232, /* Octets Transmitted OK High */ 1414 GM_TXO_OK_HI = GM_MIB_CNT_BASE + 232, /* Octets Transmitted OK High */
1419 GM_TXF_64B = GM_MIB_CNT_BASE + 240, /* 64 Byte Tx Frame */ 1415 GM_TXF_64B = GM_MIB_CNT_BASE + 240, /* 64 Byte Tx Frame */
1420 GM_TXF_127B = GM_MIB_CNT_BASE + 248, /* 65-127 Byte Tx Frame */ 1416 GM_TXF_127B = GM_MIB_CNT_BASE + 248, /* 65-127 Byte Tx Frame */
1421 GM_TXF_255B = GM_MIB_CNT_BASE + 256, /* 128-255 Byte Tx Frame */ 1417 GM_TXF_255B = GM_MIB_CNT_BASE + 256, /* 128-255 Byte Tx Frame */
1422 GM_TXF_511B = GM_MIB_CNT_BASE + 264, /* 256-511 Byte Tx Frame */ 1418 GM_TXF_511B = GM_MIB_CNT_BASE + 264, /* 256-511 Byte Tx Frame */
1423 GM_TXF_1023B = GM_MIB_CNT_BASE + 272, /* 512-1023 Byte Tx Frame */ 1419 GM_TXF_1023B = GM_MIB_CNT_BASE + 272, /* 512-1023 Byte Tx Frame */
1424 GM_TXF_1518B = GM_MIB_CNT_BASE + 280, /* 1024-1518 Byte Tx Frame */ 1420 GM_TXF_1518B = GM_MIB_CNT_BASE + 280, /* 1024-1518 Byte Tx Frame */
1425 GM_TXF_MAX_SZ = GM_MIB_CNT_BASE + 288, /* 1519-MaxSize Byte Tx Frame */ 1421 GM_TXF_MAX_SZ = GM_MIB_CNT_BASE + 288, /* 1519-MaxSize Byte Tx Frame */
1426 1422
1427 GM_TXF_COL = GM_MIB_CNT_BASE + 304, /* Tx Collision */ 1423 GM_TXF_COL = GM_MIB_CNT_BASE + 304, /* Tx Collision */
1428 GM_TXF_LAT_COL = GM_MIB_CNT_BASE + 312, /* Tx Late Collision */ 1424 GM_TXF_LAT_COL = GM_MIB_CNT_BASE + 312, /* Tx Late Collision */
1429 GM_TXF_ABO_COL = GM_MIB_CNT_BASE + 320, /* Tx aborted due to Exces. Col. */ 1425 GM_TXF_ABO_COL = GM_MIB_CNT_BASE + 320, /* Tx aborted due to Exces. Col. */
1430 GM_TXF_MUL_COL = GM_MIB_CNT_BASE + 328, /* Tx Multiple Collision */ 1426 GM_TXF_MUL_COL = GM_MIB_CNT_BASE + 328, /* Tx Multiple Collision */
1431 GM_TXF_SNG_COL = GM_MIB_CNT_BASE + 336, /* Tx Single Collision */ 1427 GM_TXF_SNG_COL = GM_MIB_CNT_BASE + 336, /* Tx Single Collision */
1432 GM_TXE_FIFO_UR = GM_MIB_CNT_BASE + 344, /* Tx FIFO Underrun Event */ 1428 GM_TXE_FIFO_UR = GM_MIB_CNT_BASE + 344, /* Tx FIFO Underrun Event */
1433 }; 1429 };
1434 1430
1435 /* GMAC Bit Definitions */ 1431 /* GMAC Bit Definitions */
1436 /* GM_GP_STAT 16 bit r/o General Purpose Status Register */ 1432 /* GM_GP_STAT 16 bit r/o General Purpose Status Register */
1437 enum { 1433 enum {
1438 GM_GPSR_SPEED = 1<<15, /* Bit 15: Port Speed (1 = 100 Mbps) */ 1434 GM_GPSR_SPEED = 1<<15, /* Bit 15: Port Speed (1 = 100 Mbps) */
1439 GM_GPSR_DUPLEX = 1<<14, /* Bit 14: Duplex Mode (1 = Full) */ 1435 GM_GPSR_DUPLEX = 1<<14, /* Bit 14: Duplex Mode (1 = Full) */
1440 GM_GPSR_FC_TX_DIS = 1<<13, /* Bit 13: Tx Flow-Control Mode Disabled */ 1436 GM_GPSR_FC_TX_DIS = 1<<13, /* Bit 13: Tx Flow-Control Mode Disabled */
1441 GM_GPSR_LINK_UP = 1<<12, /* Bit 12: Link Up Status */ 1437 GM_GPSR_LINK_UP = 1<<12, /* Bit 12: Link Up Status */
1442 GM_GPSR_PAUSE = 1<<11, /* Bit 11: Pause State */ 1438 GM_GPSR_PAUSE = 1<<11, /* Bit 11: Pause State */
1443 GM_GPSR_TX_ACTIVE = 1<<10, /* Bit 10: Tx in Progress */ 1439 GM_GPSR_TX_ACTIVE = 1<<10, /* Bit 10: Tx in Progress */
1444 GM_GPSR_EXC_COL = 1<<9, /* Bit 9: Excessive Collisions Occured */ 1440 GM_GPSR_EXC_COL = 1<<9, /* Bit 9: Excessive Collisions Occured */
1445 GM_GPSR_LAT_COL = 1<<8, /* Bit 8: Late Collisions Occured */ 1441 GM_GPSR_LAT_COL = 1<<8, /* Bit 8: Late Collisions Occured */
1446 1442
1447 GM_GPSR_PHY_ST_CH = 1<<5, /* Bit 5: PHY Status Change */ 1443 GM_GPSR_PHY_ST_CH = 1<<5, /* Bit 5: PHY Status Change */
1448 GM_GPSR_GIG_SPEED = 1<<4, /* Bit 4: Gigabit Speed (1 = 1000 Mbps) */ 1444 GM_GPSR_GIG_SPEED = 1<<4, /* Bit 4: Gigabit Speed (1 = 1000 Mbps) */
1449 GM_GPSR_PART_MODE = 1<<3, /* Bit 3: Partition mode */ 1445 GM_GPSR_PART_MODE = 1<<3, /* Bit 3: Partition mode */
1450 GM_GPSR_FC_RX_DIS = 1<<2, /* Bit 2: Rx Flow-Control Mode Disabled */ 1446 GM_GPSR_FC_RX_DIS = 1<<2, /* Bit 2: Rx Flow-Control Mode Disabled */
1451 GM_GPSR_PROM_EN = 1<<1, /* Bit 1: Promiscuous Mode Enabled */ 1447 GM_GPSR_PROM_EN = 1<<1, /* Bit 1: Promiscuous Mode Enabled */
1452 }; 1448 };
1453 1449
1454 /* GM_GP_CTRL 16 bit r/w General Purpose Control Register */ 1450 /* GM_GP_CTRL 16 bit r/w General Purpose Control Register */
1455 enum { 1451 enum {
1456 GM_GPCR_PROM_ENA = 1<<14, /* Bit 14: Enable Promiscuous Mode */ 1452 GM_GPCR_PROM_ENA = 1<<14, /* Bit 14: Enable Promiscuous Mode */
1457 GM_GPCR_FC_TX_DIS = 1<<13, /* Bit 13: Disable Tx Flow-Control Mode */ 1453 GM_GPCR_FC_TX_DIS = 1<<13, /* Bit 13: Disable Tx Flow-Control Mode */
1458 GM_GPCR_TX_ENA = 1<<12, /* Bit 12: Enable Transmit */ 1454 GM_GPCR_TX_ENA = 1<<12, /* Bit 12: Enable Transmit */
1459 GM_GPCR_RX_ENA = 1<<11, /* Bit 11: Enable Receive */ 1455 GM_GPCR_RX_ENA = 1<<11, /* Bit 11: Enable Receive */
1460 GM_GPCR_BURST_ENA = 1<<10, /* Bit 10: Enable Burst Mode */ 1456 GM_GPCR_BURST_ENA = 1<<10, /* Bit 10: Enable Burst Mode */
1461 GM_GPCR_LOOP_ENA = 1<<9, /* Bit 9: Enable MAC Loopback Mode */ 1457 GM_GPCR_LOOP_ENA = 1<<9, /* Bit 9: Enable MAC Loopback Mode */
1462 GM_GPCR_PART_ENA = 1<<8, /* Bit 8: Enable Partition Mode */ 1458 GM_GPCR_PART_ENA = 1<<8, /* Bit 8: Enable Partition Mode */
1463 GM_GPCR_GIGS_ENA = 1<<7, /* Bit 7: Gigabit Speed (1000 Mbps) */ 1459 GM_GPCR_GIGS_ENA = 1<<7, /* Bit 7: Gigabit Speed (1000 Mbps) */
1464 GM_GPCR_FL_PASS = 1<<6, /* Bit 6: Force Link Pass */ 1460 GM_GPCR_FL_PASS = 1<<6, /* Bit 6: Force Link Pass */
1465 GM_GPCR_DUP_FULL = 1<<5, /* Bit 5: Full Duplex Mode */ 1461 GM_GPCR_DUP_FULL = 1<<5, /* Bit 5: Full Duplex Mode */
1466 GM_GPCR_FC_RX_DIS = 1<<4, /* Bit 4: Disable Rx Flow-Control Mode */ 1462 GM_GPCR_FC_RX_DIS = 1<<4, /* Bit 4: Disable Rx Flow-Control Mode */
1467 GM_GPCR_SPEED_100 = 1<<3, /* Bit 3: Port Speed 100 Mbps */ 1463 GM_GPCR_SPEED_100 = 1<<3, /* Bit 3: Port Speed 100 Mbps */
1468 GM_GPCR_AU_DUP_DIS = 1<<2, /* Bit 2: Disable Auto-Update Duplex */ 1464 GM_GPCR_AU_DUP_DIS = 1<<2, /* Bit 2: Disable Auto-Update Duplex */
1469 GM_GPCR_AU_FCT_DIS = 1<<1, /* Bit 1: Disable Auto-Update Flow-C. */ 1465 GM_GPCR_AU_FCT_DIS = 1<<1, /* Bit 1: Disable Auto-Update Flow-C. */
1470 GM_GPCR_AU_SPD_DIS = 1<<0, /* Bit 0: Disable Auto-Update Speed */ 1466 GM_GPCR_AU_SPD_DIS = 1<<0, /* Bit 0: Disable Auto-Update Speed */
1471 }; 1467 };
1472 1468
1473 #define GM_GPCR_SPEED_1000 (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100) 1469 #define GM_GPCR_SPEED_1000 (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100)
1474 #define GM_GPCR_AU_ALL_DIS (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS|GM_GPCR_AU_SPD_DIS) 1470 #define GM_GPCR_AU_ALL_DIS (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS|GM_GPCR_AU_SPD_DIS)
1475 1471
1476 /* GM_TX_CTRL 16 bit r/w Transmit Control Register */ 1472 /* GM_TX_CTRL 16 bit r/w Transmit Control Register */
1477 enum { 1473 enum {
1478 GM_TXCR_FORCE_JAM = 1<<15, /* Bit 15: Force Jam / Flow-Control */ 1474 GM_TXCR_FORCE_JAM = 1<<15, /* Bit 15: Force Jam / Flow-Control */
1479 GM_TXCR_CRC_DIS = 1<<14, /* Bit 14: Disable insertion of CRC */ 1475 GM_TXCR_CRC_DIS = 1<<14, /* Bit 14: Disable insertion of CRC */
1480 GM_TXCR_PAD_DIS = 1<<13, /* Bit 13: Disable padding of packets */ 1476 GM_TXCR_PAD_DIS = 1<<13, /* Bit 13: Disable padding of packets */
1481 GM_TXCR_COL_THR_MSK = 1<<10, /* Bit 12..10: Collision Threshold */ 1477 GM_TXCR_COL_THR_MSK = 1<<10, /* Bit 12..10: Collision Threshold */
1482 }; 1478 };
1483 1479
1484 #define TX_COL_THR(x) (((x)<<10) & GM_TXCR_COL_THR_MSK) 1480 #define TX_COL_THR(x) (((x)<<10) & GM_TXCR_COL_THR_MSK)
1485 #define TX_COL_DEF 0x04 1481 #define TX_COL_DEF 0x04
1486 1482
1487 /* GM_RX_CTRL 16 bit r/w Receive Control Register */ 1483 /* GM_RX_CTRL 16 bit r/w Receive Control Register */
1488 enum { 1484 enum {
1489 GM_RXCR_UCF_ENA = 1<<15, /* Bit 15: Enable Unicast filtering */ 1485 GM_RXCR_UCF_ENA = 1<<15, /* Bit 15: Enable Unicast filtering */
1490 GM_RXCR_MCF_ENA = 1<<14, /* Bit 14: Enable Multicast filtering */ 1486 GM_RXCR_MCF_ENA = 1<<14, /* Bit 14: Enable Multicast filtering */
1491 GM_RXCR_CRC_DIS = 1<<13, /* Bit 13: Remove 4-byte CRC */ 1487 GM_RXCR_CRC_DIS = 1<<13, /* Bit 13: Remove 4-byte CRC */
1492 GM_RXCR_PASS_FC = 1<<12, /* Bit 12: Pass FC packets to FIFO */ 1488 GM_RXCR_PASS_FC = 1<<12, /* Bit 12: Pass FC packets to FIFO */
1493 }; 1489 };
1494 1490
1495 /* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */ 1491 /* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */
1496 enum { 1492 enum {
1497 GM_TXPA_JAMLEN_MSK = 0x03<<14, /* Bit 15..14: Jam Length */ 1493 GM_TXPA_JAMLEN_MSK = 0x03<<14, /* Bit 15..14: Jam Length */
1498 GM_TXPA_JAMIPG_MSK = 0x1f<<9, /* Bit 13..9: Jam IPG */ 1494 GM_TXPA_JAMIPG_MSK = 0x1f<<9, /* Bit 13..9: Jam IPG */
1499 GM_TXPA_JAMDAT_MSK = 0x1f<<4, /* Bit 8..4: IPG Jam to Data */ 1495 GM_TXPA_JAMDAT_MSK = 0x1f<<4, /* Bit 8..4: IPG Jam to Data */
1500 GM_TXPA_BO_LIM_MSK = 0x0f, /* Bit 3.. 0: Backoff Limit Mask */ 1496 GM_TXPA_BO_LIM_MSK = 0x0f, /* Bit 3.. 0: Backoff Limit Mask */
1501 1497
1502 TX_JAM_LEN_DEF = 0x03, 1498 TX_JAM_LEN_DEF = 0x03,
1503 TX_JAM_IPG_DEF = 0x0b, 1499 TX_JAM_IPG_DEF = 0x0b,
1504 TX_IPG_JAM_DEF = 0x1c, 1500 TX_IPG_JAM_DEF = 0x1c,
1505 TX_BOF_LIM_DEF = 0x04, 1501 TX_BOF_LIM_DEF = 0x04,
1506 }; 1502 };
1507 1503
1508 #define TX_JAM_LEN_VAL(x) (((x)<<14) & GM_TXPA_JAMLEN_MSK) 1504 #define TX_JAM_LEN_VAL(x) (((x)<<14) & GM_TXPA_JAMLEN_MSK)
1509 #define TX_JAM_IPG_VAL(x) (((x)<<9) & GM_TXPA_JAMIPG_MSK) 1505 #define TX_JAM_IPG_VAL(x) (((x)<<9) & GM_TXPA_JAMIPG_MSK)
1510 #define TX_IPG_JAM_DATA(x) (((x)<<4) & GM_TXPA_JAMDAT_MSK) 1506 #define TX_IPG_JAM_DATA(x) (((x)<<4) & GM_TXPA_JAMDAT_MSK)
1511 #define TX_BACK_OFF_LIM(x) ((x) & GM_TXPA_BO_LIM_MSK) 1507 #define TX_BACK_OFF_LIM(x) ((x) & GM_TXPA_BO_LIM_MSK)
1512 1508
1513 1509
1514 /* GM_SERIAL_MODE 16 bit r/w Serial Mode Register */ 1510 /* GM_SERIAL_MODE 16 bit r/w Serial Mode Register */
1515 enum { 1511 enum {
1516 GM_SMOD_DATABL_MSK = 0x1f<<11, /* Bit 15..11: Data Blinder (r/o) */ 1512 GM_SMOD_DATABL_MSK = 0x1f<<11, /* Bit 15..11: Data Blinder (r/o) */
1517 GM_SMOD_LIMIT_4 = 1<<10, /* Bit 10: 4 consecutive Tx trials */ 1513 GM_SMOD_LIMIT_4 = 1<<10, /* Bit 10: 4 consecutive Tx trials */
1518 GM_SMOD_VLAN_ENA = 1<<9, /* Bit 9: Enable VLAN (Max. Frame Len) */ 1514 GM_SMOD_VLAN_ENA = 1<<9, /* Bit 9: Enable VLAN (Max. Frame Len) */
1519 GM_SMOD_JUMBO_ENA = 1<<8, /* Bit 8: Enable Jumbo (Max. Frame Len) */ 1515 GM_SMOD_JUMBO_ENA = 1<<8, /* Bit 8: Enable Jumbo (Max. Frame Len) */
1520 GM_SMOD_IPG_MSK = 0x1f /* Bit 4..0: Inter-Packet Gap (IPG) */ 1516 GM_SMOD_IPG_MSK = 0x1f /* Bit 4..0: Inter-Packet Gap (IPG) */
1521 }; 1517 };
1522 1518
1523 #define DATA_BLIND_VAL(x) (((x)<<11) & GM_SMOD_DATABL_MSK) 1519 #define DATA_BLIND_VAL(x) (((x)<<11) & GM_SMOD_DATABL_MSK)
1524 #define DATA_BLIND_DEF 0x04 1520 #define DATA_BLIND_DEF 0x04
1525 1521
1526 #define IPG_DATA_VAL(x) (x & GM_SMOD_IPG_MSK) 1522 #define IPG_DATA_VAL(x) (x & GM_SMOD_IPG_MSK)
1527 #define IPG_DATA_DEF 0x1e 1523 #define IPG_DATA_DEF 0x1e
1528 1524
1529 /* GM_SMI_CTRL 16 bit r/w SMI Control Register */ 1525 /* GM_SMI_CTRL 16 bit r/w SMI Control Register */
1530 enum { 1526 enum {
1531 GM_SMI_CT_PHY_A_MSK = 0x1f<<11,/* Bit 15..11: PHY Device Address */ 1527 GM_SMI_CT_PHY_A_MSK = 0x1f<<11,/* Bit 15..11: PHY Device Address */
1532 GM_SMI_CT_REG_A_MSK = 0x1f<<6,/* Bit 10.. 6: PHY Register Address */ 1528 GM_SMI_CT_REG_A_MSK = 0x1f<<6,/* Bit 10.. 6: PHY Register Address */
1533 GM_SMI_CT_OP_RD = 1<<5, /* Bit 5: OpCode Read (0=Write)*/ 1529 GM_SMI_CT_OP_RD = 1<<5, /* Bit 5: OpCode Read (0=Write)*/
1534 GM_SMI_CT_RD_VAL = 1<<4, /* Bit 4: Read Valid (Read completed) */ 1530 GM_SMI_CT_RD_VAL = 1<<4, /* Bit 4: Read Valid (Read completed) */
1535 GM_SMI_CT_BUSY = 1<<3, /* Bit 3: Busy (Operation in progress) */ 1531 GM_SMI_CT_BUSY = 1<<3, /* Bit 3: Busy (Operation in progress) */
1536 }; 1532 };
1537 1533
1538 #define GM_SMI_CT_PHY_AD(x) (((x)<<11) & GM_SMI_CT_PHY_A_MSK) 1534 #define GM_SMI_CT_PHY_AD(x) (((x)<<11) & GM_SMI_CT_PHY_A_MSK)
1539 #define GM_SMI_CT_REG_AD(x) (((x)<<6) & GM_SMI_CT_REG_A_MSK) 1535 #define GM_SMI_CT_REG_AD(x) (((x)<<6) & GM_SMI_CT_REG_A_MSK)
1540 1536
1541 /* GM_PHY_ADDR 16 bit r/w GPHY Address Register */ 1537 /* GM_PHY_ADDR 16 bit r/w GPHY Address Register */
1542 enum { 1538 enum {
1543 GM_PAR_MIB_CLR = 1<<5, /* Bit 5: Set MIB Clear Counter Mode */ 1539 GM_PAR_MIB_CLR = 1<<5, /* Bit 5: Set MIB Clear Counter Mode */
1544 GM_PAR_MIB_TST = 1<<4, /* Bit 4: MIB Load Counter (Test Mode) */ 1540 GM_PAR_MIB_TST = 1<<4, /* Bit 4: MIB Load Counter (Test Mode) */
1545 }; 1541 };
1546 1542
1547 /* Receive Frame Status Encoding */ 1543 /* Receive Frame Status Encoding */
1548 enum { 1544 enum {
1549 GMR_FS_LEN = 0xffff<<16, /* Bit 31..16: Rx Frame Length */ 1545 GMR_FS_LEN = 0xffff<<16, /* Bit 31..16: Rx Frame Length */
1550 GMR_FS_VLAN = 1<<13, /* VLAN Packet */ 1546 GMR_FS_VLAN = 1<<13, /* VLAN Packet */
1551 GMR_FS_JABBER = 1<<12, /* Jabber Packet */ 1547 GMR_FS_JABBER = 1<<12, /* Jabber Packet */
1552 GMR_FS_UN_SIZE = 1<<11, /* Undersize Packet */ 1548 GMR_FS_UN_SIZE = 1<<11, /* Undersize Packet */
1553 GMR_FS_MC = 1<<10, /* Multicast Packet */ 1549 GMR_FS_MC = 1<<10, /* Multicast Packet */
1554 GMR_FS_BC = 1<<9, /* Broadcast Packet */ 1550 GMR_FS_BC = 1<<9, /* Broadcast Packet */
1555 GMR_FS_RX_OK = 1<<8, /* Receive OK (Good Packet) */ 1551 GMR_FS_RX_OK = 1<<8, /* Receive OK (Good Packet) */
1556 GMR_FS_GOOD_FC = 1<<7, /* Good Flow-Control Packet */ 1552 GMR_FS_GOOD_FC = 1<<7, /* Good Flow-Control Packet */
1557 GMR_FS_BAD_FC = 1<<6, /* Bad Flow-Control Packet */ 1553 GMR_FS_BAD_FC = 1<<6, /* Bad Flow-Control Packet */
1558 GMR_FS_MII_ERR = 1<<5, /* MII Error */ 1554 GMR_FS_MII_ERR = 1<<5, /* MII Error */
1559 GMR_FS_LONG_ERR = 1<<4, /* Too Long Packet */ 1555 GMR_FS_LONG_ERR = 1<<4, /* Too Long Packet */
1560 GMR_FS_FRAGMENT = 1<<3, /* Fragment */ 1556 GMR_FS_FRAGMENT = 1<<3, /* Fragment */
1561 1557
1562 GMR_FS_CRC_ERR = 1<<1, /* CRC Error */ 1558 GMR_FS_CRC_ERR = 1<<1, /* CRC Error */
1563 GMR_FS_RX_FF_OV = 1<<0, /* Rx FIFO Overflow */ 1559 GMR_FS_RX_FF_OV = 1<<0, /* Rx FIFO Overflow */
1564 1560
1565 GMR_FS_ANY_ERR = GMR_FS_RX_FF_OV | GMR_FS_CRC_ERR | 1561 GMR_FS_ANY_ERR = GMR_FS_RX_FF_OV | GMR_FS_CRC_ERR |
1566 GMR_FS_FRAGMENT | GMR_FS_LONG_ERR | 1562 GMR_FS_FRAGMENT | GMR_FS_LONG_ERR |
1567 GMR_FS_MII_ERR | GMR_FS_BAD_FC | GMR_FS_GOOD_FC | 1563 GMR_FS_MII_ERR | GMR_FS_BAD_FC | GMR_FS_GOOD_FC |
1568 GMR_FS_UN_SIZE | GMR_FS_JABBER, 1564 GMR_FS_UN_SIZE | GMR_FS_JABBER,
1569 }; 1565 };
1570 1566
1571 /* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */ 1567 /* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */
1572 enum { 1568 enum {
1573 RX_TRUNC_ON = 1<<27, /* enable packet truncation */ 1569 RX_TRUNC_ON = 1<<27, /* enable packet truncation */
1574 RX_TRUNC_OFF = 1<<26, /* disable packet truncation */ 1570 RX_TRUNC_OFF = 1<<26, /* disable packet truncation */
1575 RX_VLAN_STRIP_ON = 1<<25, /* enable VLAN stripping */ 1571 RX_VLAN_STRIP_ON = 1<<25, /* enable VLAN stripping */
1576 RX_VLAN_STRIP_OFF = 1<<24, /* disable VLAN stripping */ 1572 RX_VLAN_STRIP_OFF = 1<<24, /* disable VLAN stripping */
1577 1573
1578 GMF_WP_TST_ON = 1<<14, /* Write Pointer Test On */ 1574 GMF_WP_TST_ON = 1<<14, /* Write Pointer Test On */
1579 GMF_WP_TST_OFF = 1<<13, /* Write Pointer Test Off */ 1575 GMF_WP_TST_OFF = 1<<13, /* Write Pointer Test Off */
1580 GMF_WP_STEP = 1<<12, /* Write Pointer Step/Increment */ 1576 GMF_WP_STEP = 1<<12, /* Write Pointer Step/Increment */
1581 1577
1582 GMF_RP_TST_ON = 1<<10, /* Read Pointer Test On */ 1578 GMF_RP_TST_ON = 1<<10, /* Read Pointer Test On */
1583 GMF_RP_TST_OFF = 1<<9, /* Read Pointer Test Off */ 1579 GMF_RP_TST_OFF = 1<<9, /* Read Pointer Test Off */
1584 GMF_RP_STEP = 1<<8, /* Read Pointer Step/Increment */ 1580 GMF_RP_STEP = 1<<8, /* Read Pointer Step/Increment */
1585 GMF_RX_F_FL_ON = 1<<7, /* Rx FIFO Flush Mode On */ 1581 GMF_RX_F_FL_ON = 1<<7, /* Rx FIFO Flush Mode On */
1586 GMF_RX_F_FL_OFF = 1<<6, /* Rx FIFO Flush Mode Off */ 1582 GMF_RX_F_FL_OFF = 1<<6, /* Rx FIFO Flush Mode Off */
1587 GMF_CLI_RX_FO = 1<<5, /* Clear IRQ Rx FIFO Overrun */ 1583 GMF_CLI_RX_FO = 1<<5, /* Clear IRQ Rx FIFO Overrun */
1588 GMF_CLI_RX_C = 1<<4, /* Clear IRQ Rx Frame Complete */ 1584 GMF_CLI_RX_C = 1<<4, /* Clear IRQ Rx Frame Complete */
1589 1585
1590 GMF_OPER_ON = 1<<3, /* Operational Mode On */ 1586 GMF_OPER_ON = 1<<3, /* Operational Mode On */
1591 GMF_OPER_OFF = 1<<2, /* Operational Mode Off */ 1587 GMF_OPER_OFF = 1<<2, /* Operational Mode Off */
1592 GMF_RST_CLR = 1<<1, /* Clear GMAC FIFO Reset */ 1588 GMF_RST_CLR = 1<<1, /* Clear GMAC FIFO Reset */
1593 GMF_RST_SET = 1<<0, /* Set GMAC FIFO Reset */ 1589 GMF_RST_SET = 1<<0, /* Set GMAC FIFO Reset */
1594 1590
1595 RX_GMF_FL_THR_DEF = 0xa, /* flush threshold (default) */ 1591 RX_GMF_FL_THR_DEF = 0xa, /* flush threshold (default) */
1596 1592
1597 GMF_RX_CTRL_DEF = GMF_OPER_ON | GMF_RX_F_FL_ON, 1593 GMF_RX_CTRL_DEF = GMF_OPER_ON | GMF_RX_F_FL_ON,
1598 }; 1594 };
1599 1595
1600 1596
1601 /* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test */ 1597 /* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test */
1602 enum { 1598 enum {
1603 TX_STFW_DIS = 1<<31,/* Disable Store & Forward (Yukon-EC Ultra) */ 1599 TX_STFW_DIS = 1<<31,/* Disable Store & Forward (Yukon-EC Ultra) */
1604 TX_STFW_ENA = 1<<30,/* Enable Store & Forward (Yukon-EC Ultra) */ 1600 TX_STFW_ENA = 1<<30,/* Enable Store & Forward (Yukon-EC Ultra) */
1605 1601
1606 TX_VLAN_TAG_ON = 1<<25,/* enable VLAN tagging */ 1602 TX_VLAN_TAG_ON = 1<<25,/* enable VLAN tagging */
1607 TX_VLAN_TAG_OFF = 1<<24,/* disable VLAN tagging */ 1603 TX_VLAN_TAG_OFF = 1<<24,/* disable VLAN tagging */
1608 1604
1609 GMF_WSP_TST_ON = 1<<18,/* Write Shadow Pointer Test On */ 1605 GMF_WSP_TST_ON = 1<<18,/* Write Shadow Pointer Test On */
1610 GMF_WSP_TST_OFF = 1<<17,/* Write Shadow Pointer Test Off */ 1606 GMF_WSP_TST_OFF = 1<<17,/* Write Shadow Pointer Test Off */
1611 GMF_WSP_STEP = 1<<16,/* Write Shadow Pointer Step/Increment */ 1607 GMF_WSP_STEP = 1<<16,/* Write Shadow Pointer Step/Increment */
1612 1608
1613 GMF_CLI_TX_FU = 1<<6, /* Clear IRQ Tx FIFO Underrun */ 1609 GMF_CLI_TX_FU = 1<<6, /* Clear IRQ Tx FIFO Underrun */
1614 GMF_CLI_TX_FC = 1<<5, /* Clear IRQ Tx Frame Complete */ 1610 GMF_CLI_TX_FC = 1<<5, /* Clear IRQ Tx Frame Complete */
1615 GMF_CLI_TX_PE = 1<<4, /* Clear IRQ Tx Parity Error */ 1611 GMF_CLI_TX_PE = 1<<4, /* Clear IRQ Tx Parity Error */
1616 }; 1612 };
1617 1613
1618 /* GMAC_TI_ST_CTRL 8 bit Time Stamp Timer Ctrl Reg (YUKON only) */ 1614 /* GMAC_TI_ST_CTRL 8 bit Time Stamp Timer Ctrl Reg (YUKON only) */
1619 enum { 1615 enum {
1620 GMT_ST_START = 1<<2, /* Start Time Stamp Timer */ 1616 GMT_ST_START = 1<<2, /* Start Time Stamp Timer */
1621 GMT_ST_STOP = 1<<1, /* Stop Time Stamp Timer */ 1617 GMT_ST_STOP = 1<<1, /* Stop Time Stamp Timer */
1622 GMT_ST_CLR_IRQ = 1<<0, /* Clear Time Stamp Timer IRQ */ 1618 GMT_ST_CLR_IRQ = 1<<0, /* Clear Time Stamp Timer IRQ */
1623 }; 1619 };
1624 1620
1625 /* B28_Y2_ASF_STAT_CMD 32 bit ASF Status and Command Reg */ 1621 /* B28_Y2_ASF_STAT_CMD 32 bit ASF Status and Command Reg */
1626 enum { 1622 enum {
1627 Y2_ASF_OS_PRES = 1<<4, /* ASF operation system present */ 1623 Y2_ASF_OS_PRES = 1<<4, /* ASF operation system present */
1628 Y2_ASF_RESET = 1<<3, /* ASF system in reset state */ 1624 Y2_ASF_RESET = 1<<3, /* ASF system in reset state */
1629 Y2_ASF_RUNNING = 1<<2, /* ASF system operational */ 1625 Y2_ASF_RUNNING = 1<<2, /* ASF system operational */
1630 Y2_ASF_CLR_HSTI = 1<<1, /* Clear ASF IRQ */ 1626 Y2_ASF_CLR_HSTI = 1<<1, /* Clear ASF IRQ */
1631 Y2_ASF_IRQ = 1<<0, /* Issue an IRQ to ASF system */ 1627 Y2_ASF_IRQ = 1<<0, /* Issue an IRQ to ASF system */
1632 1628
1633 Y2_ASF_UC_STATE = 3<<2, /* ASF uC State */ 1629 Y2_ASF_UC_STATE = 3<<2, /* ASF uC State */
1634 Y2_ASF_CLK_HALT = 0, /* ASF system clock stopped */ 1630 Y2_ASF_CLK_HALT = 0, /* ASF system clock stopped */
1635 }; 1631 };
1636 1632
1637 /* B28_Y2_ASF_HOST_COM 32 bit ASF Host Communication Reg */ 1633 /* B28_Y2_ASF_HOST_COM 32 bit ASF Host Communication Reg */
1638 enum { 1634 enum {
1639 Y2_ASF_CLR_ASFI = 1<<1, /* Clear host IRQ */ 1635 Y2_ASF_CLR_ASFI = 1<<1, /* Clear host IRQ */
1640 Y2_ASF_HOST_IRQ = 1<<0, /* Issue an IRQ to HOST system */ 1636 Y2_ASF_HOST_IRQ = 1<<0, /* Issue an IRQ to HOST system */
1641 }; 1637 };
1642 1638
1643 /* STAT_CTRL 32 bit Status BMU control register (Yukon-2 only) */ 1639 /* STAT_CTRL 32 bit Status BMU control register (Yukon-2 only) */
1644 enum { 1640 enum {
1645 SC_STAT_CLR_IRQ = 1<<4, /* Status Burst IRQ clear */ 1641 SC_STAT_CLR_IRQ = 1<<4, /* Status Burst IRQ clear */
1646 SC_STAT_OP_ON = 1<<3, /* Operational Mode On */ 1642 SC_STAT_OP_ON = 1<<3, /* Operational Mode On */
1647 SC_STAT_OP_OFF = 1<<2, /* Operational Mode Off */ 1643 SC_STAT_OP_OFF = 1<<2, /* Operational Mode Off */
1648 SC_STAT_RST_CLR = 1<<1, /* Clear Status Unit Reset (Enable) */ 1644 SC_STAT_RST_CLR = 1<<1, /* Clear Status Unit Reset (Enable) */
1649 SC_STAT_RST_SET = 1<<0, /* Set Status Unit Reset */ 1645 SC_STAT_RST_SET = 1<<0, /* Set Status Unit Reset */
1650 }; 1646 };
1651 1647
1652 /* GMAC_CTRL 32 bit GMAC Control Reg (YUKON only) */ 1648 /* GMAC_CTRL 32 bit GMAC Control Reg (YUKON only) */
1653 enum { 1649 enum {
1654 GMC_H_BURST_ON = 1<<7, /* Half Duplex Burst Mode On */ 1650 GMC_H_BURST_ON = 1<<7, /* Half Duplex Burst Mode On */
1655 GMC_H_BURST_OFF = 1<<6, /* Half Duplex Burst Mode Off */ 1651 GMC_H_BURST_OFF = 1<<6, /* Half Duplex Burst Mode Off */
1656 GMC_F_LOOPB_ON = 1<<5, /* FIFO Loopback On */ 1652 GMC_F_LOOPB_ON = 1<<5, /* FIFO Loopback On */
1657 GMC_F_LOOPB_OFF = 1<<4, /* FIFO Loopback Off */ 1653 GMC_F_LOOPB_OFF = 1<<4, /* FIFO Loopback Off */
1658 GMC_PAUSE_ON = 1<<3, /* Pause On */ 1654 GMC_PAUSE_ON = 1<<3, /* Pause On */
1659 GMC_PAUSE_OFF = 1<<2, /* Pause Off */ 1655 GMC_PAUSE_OFF = 1<<2, /* Pause Off */
1660 GMC_RST_CLR = 1<<1, /* Clear GMAC Reset */ 1656 GMC_RST_CLR = 1<<1, /* Clear GMAC Reset */
1661 GMC_RST_SET = 1<<0, /* Set GMAC Reset */ 1657 GMC_RST_SET = 1<<0, /* Set GMAC Reset */
1662 }; 1658 };
1663 1659
1664 /* GPHY_CTRL 32 bit GPHY Control Reg (YUKON only) */ 1660 /* GPHY_CTRL 32 bit GPHY Control Reg (YUKON only) */
1665 enum { 1661 enum {
1666 GPC_SEL_BDT = 1<<28, /* Select Bi-Dir. Transfer for MDC/MDIO */ 1662 GPC_SEL_BDT = 1<<28, /* Select Bi-Dir. Transfer for MDC/MDIO */
1667 GPC_INT_POL_HI = 1<<27, /* IRQ Polarity is Active HIGH */ 1663 GPC_INT_POL_HI = 1<<27, /* IRQ Polarity is Active HIGH */
1668 GPC_75_OHM = 1<<26, /* Use 75 Ohm Termination instead of 50 */ 1664 GPC_75_OHM = 1<<26, /* Use 75 Ohm Termination instead of 50 */
1669 GPC_DIS_FC = 1<<25, /* Disable Automatic Fiber/Copper Detection */ 1665 GPC_DIS_FC = 1<<25, /* Disable Automatic Fiber/Copper Detection */
1670 GPC_DIS_SLEEP = 1<<24, /* Disable Energy Detect */ 1666 GPC_DIS_SLEEP = 1<<24, /* Disable Energy Detect */
1671 GPC_HWCFG_M_3 = 1<<23, /* HWCFG_MODE[3] */ 1667 GPC_HWCFG_M_3 = 1<<23, /* HWCFG_MODE[3] */
1672 GPC_HWCFG_M_2 = 1<<22, /* HWCFG_MODE[2] */ 1668 GPC_HWCFG_M_2 = 1<<22, /* HWCFG_MODE[2] */
1673 GPC_HWCFG_M_1 = 1<<21, /* HWCFG_MODE[1] */ 1669 GPC_HWCFG_M_1 = 1<<21, /* HWCFG_MODE[1] */
1674 GPC_HWCFG_M_0 = 1<<20, /* HWCFG_MODE[0] */ 1670 GPC_HWCFG_M_0 = 1<<20, /* HWCFG_MODE[0] */
1675 GPC_ANEG_0 = 1<<19, /* ANEG[0] */ 1671 GPC_ANEG_0 = 1<<19, /* ANEG[0] */
1676 GPC_ENA_XC = 1<<18, /* Enable MDI crossover */ 1672 GPC_ENA_XC = 1<<18, /* Enable MDI crossover */
1677 GPC_DIS_125 = 1<<17, /* Disable 125 MHz clock */ 1673 GPC_DIS_125 = 1<<17, /* Disable 125 MHz clock */
1678 GPC_ANEG_3 = 1<<16, /* ANEG[3] */ 1674 GPC_ANEG_3 = 1<<16, /* ANEG[3] */
1679 GPC_ANEG_2 = 1<<15, /* ANEG[2] */ 1675 GPC_ANEG_2 = 1<<15, /* ANEG[2] */
1680 GPC_ANEG_1 = 1<<14, /* ANEG[1] */ 1676 GPC_ANEG_1 = 1<<14, /* ANEG[1] */
1681 GPC_ENA_PAUSE = 1<<13, /* Enable Pause (SYM_OR_REM) */ 1677 GPC_ENA_PAUSE = 1<<13, /* Enable Pause (SYM_OR_REM) */
1682 GPC_PHYADDR_4 = 1<<12, /* Bit 4 of Phy Addr */ 1678 GPC_PHYADDR_4 = 1<<12, /* Bit 4 of Phy Addr */
1683 GPC_PHYADDR_3 = 1<<11, /* Bit 3 of Phy Addr */ 1679 GPC_PHYADDR_3 = 1<<11, /* Bit 3 of Phy Addr */
1684 GPC_PHYADDR_2 = 1<<10, /* Bit 2 of Phy Addr */ 1680 GPC_PHYADDR_2 = 1<<10, /* Bit 2 of Phy Addr */
1685 GPC_PHYADDR_1 = 1<<9, /* Bit 1 of Phy Addr */ 1681 GPC_PHYADDR_1 = 1<<9, /* Bit 1 of Phy Addr */
1686 GPC_PHYADDR_0 = 1<<8, /* Bit 0 of Phy Addr */ 1682 GPC_PHYADDR_0 = 1<<8, /* Bit 0 of Phy Addr */
1687 /* Bits 7..2: reserved */ 1683 /* Bits 7..2: reserved */
1688 GPC_RST_CLR = 1<<1, /* Clear GPHY Reset */ 1684 GPC_RST_CLR = 1<<1, /* Clear GPHY Reset */
1689 GPC_RST_SET = 1<<0, /* Set GPHY Reset */ 1685 GPC_RST_SET = 1<<0, /* Set GPHY Reset */
1690 }; 1686 };
1691 1687
1692 /* GMAC_IRQ_SRC 8 bit GMAC Interrupt Source Reg (YUKON only) */ 1688 /* GMAC_IRQ_SRC 8 bit GMAC Interrupt Source Reg (YUKON only) */
1693 /* GMAC_IRQ_MSK 8 bit GMAC Interrupt Mask Reg (YUKON only) */ 1689 /* GMAC_IRQ_MSK 8 bit GMAC Interrupt Mask Reg (YUKON only) */
1694 enum { 1690 enum {
1695 GM_IS_TX_CO_OV = 1<<5, /* Transmit Counter Overflow IRQ */ 1691 GM_IS_TX_CO_OV = 1<<5, /* Transmit Counter Overflow IRQ */
1696 GM_IS_RX_CO_OV = 1<<4, /* Receive Counter Overflow IRQ */ 1692 GM_IS_RX_CO_OV = 1<<4, /* Receive Counter Overflow IRQ */
1697 GM_IS_TX_FF_UR = 1<<3, /* Transmit FIFO Underrun */ 1693 GM_IS_TX_FF_UR = 1<<3, /* Transmit FIFO Underrun */
1698 GM_IS_TX_COMPL = 1<<2, /* Frame Transmission Complete */ 1694 GM_IS_TX_COMPL = 1<<2, /* Frame Transmission Complete */
1699 GM_IS_RX_FF_OR = 1<<1, /* Receive FIFO Overrun */ 1695 GM_IS_RX_FF_OR = 1<<1, /* Receive FIFO Overrun */
1700 GM_IS_RX_COMPL = 1<<0, /* Frame Reception Complete */ 1696 GM_IS_RX_COMPL = 1<<0, /* Frame Reception Complete */
1701 1697
1702 #define GMAC_DEF_MSK GM_IS_TX_FF_UR 1698 #define GMAC_DEF_MSK GM_IS_TX_FF_UR
1703 1699
1704 /* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */ 1700 /* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */
1705 /* Bits 15.. 2: reserved */ 1701 /* Bits 15.. 2: reserved */
1706 GMLC_RST_CLR = 1<<1, /* Clear GMAC Link Reset */ 1702 GMLC_RST_CLR = 1<<1, /* Clear GMAC Link Reset */
1707 GMLC_RST_SET = 1<<0, /* Set GMAC Link Reset */ 1703 GMLC_RST_SET = 1<<0, /* Set GMAC Link Reset */
1708 1704
1709 1705
1710 /* WOL_CTRL_STAT 16 bit WOL Control/Status Reg */ 1706 /* WOL_CTRL_STAT 16 bit WOL Control/Status Reg */
1711 WOL_CTL_LINK_CHG_OCC = 1<<15, 1707 WOL_CTL_LINK_CHG_OCC = 1<<15,
1712 WOL_CTL_MAGIC_PKT_OCC = 1<<14, 1708 WOL_CTL_MAGIC_PKT_OCC = 1<<14,
1713 WOL_CTL_PATTERN_OCC = 1<<13, 1709 WOL_CTL_PATTERN_OCC = 1<<13,
1714 WOL_CTL_CLEAR_RESULT = 1<<12, 1710 WOL_CTL_CLEAR_RESULT = 1<<12,
1715 WOL_CTL_ENA_PME_ON_LINK_CHG = 1<<11, 1711 WOL_CTL_ENA_PME_ON_LINK_CHG = 1<<11,
1716 WOL_CTL_DIS_PME_ON_LINK_CHG = 1<<10, 1712 WOL_CTL_DIS_PME_ON_LINK_CHG = 1<<10,
1717 WOL_CTL_ENA_PME_ON_MAGIC_PKT = 1<<9, 1713 WOL_CTL_ENA_PME_ON_MAGIC_PKT = 1<<9,
1718 WOL_CTL_DIS_PME_ON_MAGIC_PKT = 1<<8, 1714 WOL_CTL_DIS_PME_ON_MAGIC_PKT = 1<<8,
1719 WOL_CTL_ENA_PME_ON_PATTERN = 1<<7, 1715 WOL_CTL_ENA_PME_ON_PATTERN = 1<<7,
1720 WOL_CTL_DIS_PME_ON_PATTERN = 1<<6, 1716 WOL_CTL_DIS_PME_ON_PATTERN = 1<<6,
1721 WOL_CTL_ENA_LINK_CHG_UNIT = 1<<5, 1717 WOL_CTL_ENA_LINK_CHG_UNIT = 1<<5,
1722 WOL_CTL_DIS_LINK_CHG_UNIT = 1<<4, 1718 WOL_CTL_DIS_LINK_CHG_UNIT = 1<<4,
1723 WOL_CTL_ENA_MAGIC_PKT_UNIT = 1<<3, 1719 WOL_CTL_ENA_MAGIC_PKT_UNIT = 1<<3,
1724 WOL_CTL_DIS_MAGIC_PKT_UNIT = 1<<2, 1720 WOL_CTL_DIS_MAGIC_PKT_UNIT = 1<<2,
1725 WOL_CTL_ENA_PATTERN_UNIT = 1<<1, 1721 WOL_CTL_ENA_PATTERN_UNIT = 1<<1,
1726 WOL_CTL_DIS_PATTERN_UNIT = 1<<0, 1722 WOL_CTL_DIS_PATTERN_UNIT = 1<<0,
1727 }; 1723 };
1728 1724
1729 #define WOL_CTL_DEFAULT \ 1725 #define WOL_CTL_DEFAULT \
1730 (WOL_CTL_DIS_PME_ON_LINK_CHG | \ 1726 (WOL_CTL_DIS_PME_ON_LINK_CHG | \
1731 WOL_CTL_DIS_PME_ON_PATTERN | \ 1727 WOL_CTL_DIS_PME_ON_PATTERN | \
1732 WOL_CTL_DIS_PME_ON_MAGIC_PKT | \ 1728 WOL_CTL_DIS_PME_ON_MAGIC_PKT | \
1733 WOL_CTL_DIS_LINK_CHG_UNIT | \ 1729 WOL_CTL_DIS_LINK_CHG_UNIT | \
1734 WOL_CTL_DIS_PATTERN_UNIT | \ 1730 WOL_CTL_DIS_PATTERN_UNIT | \
1735 WOL_CTL_DIS_MAGIC_PKT_UNIT) 1731 WOL_CTL_DIS_MAGIC_PKT_UNIT)
1736 1732
1737 /* WOL_MATCH_CTL 8 bit WOL Match Control Reg */ 1733 /* WOL_MATCH_CTL 8 bit WOL Match Control Reg */
1738 #define WOL_CTL_PATT_ENA(x) (1 << (x)) 1734 #define WOL_CTL_PATT_ENA(x) (1 << (x))
1739 1735
1740 1736
1741 /* Control flags */ 1737 /* Control flags */
1742 enum { 1738 enum {
1743 UDPTCP = 1<<0, 1739 UDPTCP = 1<<0,
1744 CALSUM = 1<<1, 1740 CALSUM = 1<<1,
1745 WR_SUM = 1<<2, 1741 WR_SUM = 1<<2,
1746 INIT_SUM= 1<<3, 1742 INIT_SUM= 1<<3,
1747 LOCK_SUM= 1<<4, 1743 LOCK_SUM= 1<<4,
1748 INS_VLAN= 1<<5, 1744 INS_VLAN= 1<<5,
1749 FRC_STAT= 1<<6, 1745 FRC_STAT= 1<<6,
1750 EOP = 1<<7, 1746 EOP = 1<<7,
1751 }; 1747 };
1752 1748
1753 enum { 1749 enum {
1754 HW_OWNER = 1<<7, 1750 HW_OWNER = 1<<7,
1755 OP_TCPWRITE = 0x11, 1751 OP_TCPWRITE = 0x11,
1756 OP_TCPSTART = 0x12, 1752 OP_TCPSTART = 0x12,
1757 OP_TCPINIT = 0x14, 1753 OP_TCPINIT = 0x14,
1758 OP_TCPLCK = 0x18, 1754 OP_TCPLCK = 0x18,
1759 OP_TCPCHKSUM = OP_TCPSTART, 1755 OP_TCPCHKSUM = OP_TCPSTART,
1760 OP_TCPIS = OP_TCPINIT | OP_TCPSTART, 1756 OP_TCPIS = OP_TCPINIT | OP_TCPSTART,
1761 OP_TCPLW = OP_TCPLCK | OP_TCPWRITE, 1757 OP_TCPLW = OP_TCPLCK | OP_TCPWRITE,
1762 OP_TCPLSW = OP_TCPLCK | OP_TCPSTART | OP_TCPWRITE, 1758 OP_TCPLSW = OP_TCPLCK | OP_TCPSTART | OP_TCPWRITE,
1763 OP_TCPLISW = OP_TCPLCK | OP_TCPINIT | OP_TCPSTART | OP_TCPWRITE, 1759 OP_TCPLISW = OP_TCPLCK | OP_TCPINIT | OP_TCPSTART | OP_TCPWRITE,
1764 1760
1765 OP_ADDR64 = 0x21, 1761 OP_ADDR64 = 0x21,
1766 OP_VLAN = 0x22, 1762 OP_VLAN = 0x22,
1767 OP_ADDR64VLAN = OP_ADDR64 | OP_VLAN, 1763 OP_ADDR64VLAN = OP_ADDR64 | OP_VLAN,
1768 OP_LRGLEN = 0x24, 1764 OP_LRGLEN = 0x24,
1769 OP_LRGLENVLAN = OP_LRGLEN | OP_VLAN, 1765 OP_LRGLENVLAN = OP_LRGLEN | OP_VLAN,
1770 OP_BUFFER = 0x40, 1766 OP_BUFFER = 0x40,
1771 OP_PACKET = 0x41, 1767 OP_PACKET = 0x41,
1772 OP_LARGESEND = 0x43, 1768 OP_LARGESEND = 0x43,
1773 1769
1774 /* YUKON-2 STATUS opcodes defines */ 1770 /* YUKON-2 STATUS opcodes defines */
1775 OP_RXSTAT = 0x60, 1771 OP_RXSTAT = 0x60,
1776 OP_RXTIMESTAMP = 0x61, 1772 OP_RXTIMESTAMP = 0x61,
1777 OP_RXVLAN = 0x62, 1773 OP_RXVLAN = 0x62,
1778 OP_RXCHKS = 0x64, 1774 OP_RXCHKS = 0x64,
1779 OP_RXCHKSVLAN = OP_RXCHKS | OP_RXVLAN, 1775 OP_RXCHKSVLAN = OP_RXCHKS | OP_RXVLAN,
1780 OP_RXTIMEVLAN = OP_RXTIMESTAMP | OP_RXVLAN, 1776 OP_RXTIMEVLAN = OP_RXTIMESTAMP | OP_RXVLAN,
1781 OP_RSS_HASH = 0x65, 1777 OP_RSS_HASH = 0x65,
1782 OP_TXINDEXLE = 0x68, 1778 OP_TXINDEXLE = 0x68,
1783 }; 1779 };
1784 1780
1785 /* Yukon 2 hardware interface 1781 /* Yukon 2 hardware interface
1786 * Not tested on big endian 1782 * Not tested on big endian
1787 */ 1783 */
1788 struct sky2_tx_le { 1784 struct sky2_tx_le {
1789 union { 1785 union {
1790 __le32 addr; 1786 __le32 addr;
1791 struct { 1787 struct {
1792 __le16 offset; 1788 __le16 offset;
1793 __le16 start; 1789 __le16 start;
1794 } csum __attribute((packed)); 1790 } csum __attribute((packed));
1795 struct { 1791 struct {
1796 __le16 size; 1792 __le16 size;
1797 __le16 rsvd; 1793 __le16 rsvd;
1798 } tso __attribute((packed)); 1794 } tso __attribute((packed));
1799 } tx; 1795 } tx;
1800 __le16 length; /* also vlan tag or checksum start */ 1796 __le16 length; /* also vlan tag or checksum start */
1801 u8 ctrl; 1797 u8 ctrl;
1802 u8 opcode; 1798 u8 opcode;
1803 } __attribute((packed)); 1799 } __attribute((packed));
1804 1800
1805 struct sky2_rx_le { 1801 struct sky2_rx_le {
1806 __le32 addr; 1802 __le32 addr;
1807 __le16 length; 1803 __le16 length;
1808 u8 ctrl; 1804 u8 ctrl;
1809 u8 opcode; 1805 u8 opcode;
1810 } __attribute((packed));; 1806 } __attribute((packed));;
1811 1807
1812 struct sky2_status_le { 1808 struct sky2_status_le {
1813 __le32 status; /* also checksum */ 1809 __le32 status; /* also checksum */
1814 __le16 length; /* also vlan tag */ 1810 __le16 length; /* also vlan tag */
1815 u8 link; 1811 u8 link;
1816 u8 opcode; 1812 u8 opcode;
1817 } __attribute((packed)); 1813 } __attribute((packed));
1818 1814
1819 struct tx_ring_info { 1815 struct tx_ring_info {
1820 struct sk_buff *skb; 1816 struct sk_buff *skb;
1821 DECLARE_PCI_UNMAP_ADDR(mapaddr); 1817 DECLARE_PCI_UNMAP_ADDR(mapaddr);
1822 u16 idx; 1818 u16 idx;
1823 }; 1819 };
1824 1820
1825 struct ring_info { 1821 struct ring_info {
1826 struct sk_buff *skb; 1822 struct sk_buff *skb;
1827 dma_addr_t mapaddr; 1823 dma_addr_t mapaddr;
1828 }; 1824 };
1829 1825
1830 struct sky2_port { 1826 struct sky2_port {
1831 struct sky2_hw *hw; 1827 struct sky2_hw *hw;
1832 struct net_device *netdev; 1828 struct net_device *netdev;
1833 unsigned port; 1829 unsigned port;
1834 u32 msg_enable; 1830 u32 msg_enable;
1831 spinlock_t phy_lock;
1835 1832
1836 spinlock_t tx_lock ____cacheline_aligned_in_smp; 1833 spinlock_t tx_lock ____cacheline_aligned_in_smp;
1837 struct tx_ring_info *tx_ring; 1834 struct tx_ring_info *tx_ring;
1838 struct sky2_tx_le *tx_le; 1835 struct sky2_tx_le *tx_le;
1839 u16 tx_cons; /* next le to check */ 1836 u16 tx_cons; /* next le to check */
1840 u16 tx_prod; /* next le to use */ 1837 u16 tx_prod; /* next le to use */
1841 u32 tx_addr64; 1838 u32 tx_addr64;
1842 u16 tx_pending; 1839 u16 tx_pending;
1843 u16 tx_last_mss; 1840 u16 tx_last_mss;
1844 1841
1845 struct ring_info *rx_ring ____cacheline_aligned_in_smp; 1842 struct ring_info *rx_ring ____cacheline_aligned_in_smp;
1846 struct sky2_rx_le *rx_le; 1843 struct sky2_rx_le *rx_le;
1847 u32 rx_addr64; 1844 u32 rx_addr64;
1848 u16 rx_next; /* next re to check */ 1845 u16 rx_next; /* next re to check */
1849 u16 rx_put; /* next le index to use */ 1846 u16 rx_put; /* next le index to use */
1850 u16 rx_pending; 1847 u16 rx_pending;
1851 u16 rx_bufsize; 1848 u16 rx_bufsize;
1852 #ifdef SKY2_VLAN_TAG_USED 1849 #ifdef SKY2_VLAN_TAG_USED
1853 u16 rx_tag; 1850 u16 rx_tag;
1854 struct vlan_group *vlgrp; 1851 struct vlan_group *vlgrp;
1855 #endif 1852 #endif
1856 1853
1857 dma_addr_t rx_le_map; 1854 dma_addr_t rx_le_map;
1858 dma_addr_t tx_le_map; 1855 dma_addr_t tx_le_map;
1859 u32 advertising; /* ADVERTISED_ bits */ 1856 u32 advertising; /* ADVERTISED_ bits */
1860 u16 speed; /* SPEED_1000, SPEED_100, ... */ 1857 u16 speed; /* SPEED_1000, SPEED_100, ... */
1861 u8 autoneg; /* AUTONEG_ENABLE, AUTONEG_DISABLE */ 1858 u8 autoneg; /* AUTONEG_ENABLE, AUTONEG_DISABLE */
1862 u8 duplex; /* DUPLEX_HALF, DUPLEX_FULL */ 1859 u8 duplex; /* DUPLEX_HALF, DUPLEX_FULL */
1863 u8 rx_pause; 1860 u8 rx_pause;
1864 u8 tx_pause; 1861 u8 tx_pause;
1865 u8 rx_csum; 1862 u8 rx_csum;
1866 1863
1867 struct net_device_stats net_stats; 1864 struct net_device_stats net_stats;
1868 1865
1869 struct work_struct phy_task;
1870 struct semaphore phy_sema;
1871 }; 1866 };
1872 1867
1873 struct sky2_hw { 1868 struct sky2_hw {
1874 void __iomem *regs; 1869 void __iomem *regs;
1875 struct pci_dev *pdev; 1870 struct pci_dev *pdev;
1876 struct net_device *dev[2]; 1871 struct net_device *dev[2];
1877 spinlock_t hw_lock;
1878 u32 intr_mask;
1879 1872
1880 int pm_cap; 1873 int pm_cap;
1881 u8 chip_id; 1874 u8 chip_id;
1882 u8 chip_rev; 1875 u8 chip_rev;
1883 u8 copper; 1876 u8 copper;
1884 u8 ports; 1877 u8 ports;
1885 1878
1886 struct sky2_status_le *st_le; 1879 struct sky2_status_le *st_le;
1887 u32 st_idx; 1880 u32 st_idx;
1888 dma_addr_t st_dma; 1881 dma_addr_t st_dma;
1889 }; 1882 };
1890 1883
1891 /* Register accessor for memory mapped device */ 1884 /* Register accessor for memory mapped device */
1892 static inline u32 sky2_read32(const struct sky2_hw *hw, unsigned reg) 1885 static inline u32 sky2_read32(const struct sky2_hw *hw, unsigned reg)
1893 { 1886 {
1894 return readl(hw->regs + reg); 1887 return readl(hw->regs + reg);
1895 } 1888 }
1896 1889
1897 static inline u16 sky2_read16(const struct sky2_hw *hw, unsigned reg) 1890 static inline u16 sky2_read16(const struct sky2_hw *hw, unsigned reg)
1898 { 1891 {
1899 return readw(hw->regs + reg); 1892 return readw(hw->regs + reg);
1900 } 1893 }
1901 1894
1902 static inline u8 sky2_read8(const struct sky2_hw *hw, unsigned reg) 1895 static inline u8 sky2_read8(const struct sky2_hw *hw, unsigned reg)
1903 { 1896 {
1904 return readb(hw->regs + reg); 1897 return readb(hw->regs + reg);
1905 } 1898 }
1906 1899
1907 static inline void sky2_write32(const struct sky2_hw *hw, unsigned reg, u32 val) 1900 static inline void sky2_write32(const struct sky2_hw *hw, unsigned reg, u32 val)
1908 { 1901 {
1909 writel(val, hw->regs + reg); 1902 writel(val, hw->regs + reg);
1910 } 1903 }
1911 1904
1912 static inline void sky2_write16(const struct sky2_hw *hw, unsigned reg, u16 val) 1905 static inline void sky2_write16(const struct sky2_hw *hw, unsigned reg, u16 val)
1913 { 1906 {
1914 writew(val, hw->regs + reg); 1907 writew(val, hw->regs + reg);
1915 } 1908 }
1916 1909
1917 static inline void sky2_write8(const struct sky2_hw *hw, unsigned reg, u8 val) 1910 static inline void sky2_write8(const struct sky2_hw *hw, unsigned reg, u8 val)
1918 { 1911 {
1919 writeb(val, hw->regs + reg); 1912 writeb(val, hw->regs + reg);
1920 } 1913 }
1921 1914
1922 /* Yukon PHY related registers */ 1915 /* Yukon PHY related registers */
1923 #define SK_GMAC_REG(port,reg) \ 1916 #define SK_GMAC_REG(port,reg) \
1924 (BASE_GMAC_1 + (port) * (BASE_GMAC_2-BASE_GMAC_1) + (reg)) 1917 (BASE_GMAC_1 + (port) * (BASE_GMAC_2-BASE_GMAC_1) + (reg))
1925 #define GM_PHY_RETRIES 100 1918 #define GM_PHY_RETRIES 100
1926 1919
1927 static inline u16 gma_read16(const struct sky2_hw *hw, unsigned port, unsigned reg) 1920 static inline u16 gma_read16(const struct sky2_hw *hw, unsigned port, unsigned reg)
1928 { 1921 {
1929 return sky2_read16(hw, SK_GMAC_REG(port,reg)); 1922 return sky2_read16(hw, SK_GMAC_REG(port,reg));
1930 } 1923 }
1931 1924
1932 static inline u32 gma_read32(struct sky2_hw *hw, unsigned port, unsigned reg) 1925 static inline u32 gma_read32(struct sky2_hw *hw, unsigned port, unsigned reg)
1933 { 1926 {
1934 unsigned base = SK_GMAC_REG(port, reg); 1927 unsigned base = SK_GMAC_REG(port, reg);
1935 return (u32) sky2_read16(hw, base) 1928 return (u32) sky2_read16(hw, base)
1936 | (u32) sky2_read16(hw, base+4) << 16; 1929 | (u32) sky2_read16(hw, base+4) << 16;
1937 } 1930 }
1938 1931
1939 static inline void gma_write16(const struct sky2_hw *hw, unsigned port, int r, u16 v) 1932 static inline void gma_write16(const struct sky2_hw *hw, unsigned port, int r, u16 v)
1940 { 1933 {
1941 sky2_write16(hw, SK_GMAC_REG(port,r), v); 1934 sky2_write16(hw, SK_GMAC_REG(port,r), v);
1942 } 1935 }
1943 1936
1944 static inline void gma_set_addr(struct sky2_hw *hw, unsigned port, unsigned reg, 1937 static inline void gma_set_addr(struct sky2_hw *hw, unsigned port, unsigned reg,
1945 const u8 *addr) 1938 const u8 *addr)
1946 { 1939 {
1947 gma_write16(hw, port, reg, (u16) addr[0] | ((u16) addr[1] << 8)); 1940 gma_write16(hw, port, reg, (u16) addr[0] | ((u16) addr[1] << 8));
1948 gma_write16(hw, port, reg+4,(u16) addr[2] | ((u16) addr[3] << 8)); 1941 gma_write16(hw, port, reg+4,(u16) addr[2] | ((u16) addr[3] << 8));
1949 gma_write16(hw, port, reg+8,(u16) addr[4] | ((u16) addr[5] << 8)); 1942 gma_write16(hw, port, reg+8,(u16) addr[4] | ((u16) addr[5] << 8));
1950 } 1943 }
1951 1944
1952 /* PCI config space access */ 1945 /* PCI config space access */
1953 static inline u32 sky2_pci_read32(const struct sky2_hw *hw, unsigned reg) 1946 static inline u32 sky2_pci_read32(const struct sky2_hw *hw, unsigned reg)
1954 { 1947 {
1955 return sky2_read32(hw, Y2_CFG_SPC + reg); 1948 return sky2_read32(hw, Y2_CFG_SPC + reg);
1956 } 1949 }
1957 1950
1958 static inline u16 sky2_pci_read16(const struct sky2_hw *hw, unsigned reg) 1951 static inline u16 sky2_pci_read16(const struct sky2_hw *hw, unsigned reg)
1959 { 1952 {
1960 return sky2_read16(hw, Y2_CFG_SPC + reg); 1953 return sky2_read16(hw, Y2_CFG_SPC + reg);
1961 } 1954 }
1962 1955
1963 static inline void sky2_pci_write32(struct sky2_hw *hw, unsigned reg, u32 val) 1956 static inline void sky2_pci_write32(struct sky2_hw *hw, unsigned reg, u32 val)
1964 { 1957 {
1965 sky2_write32(hw, Y2_CFG_SPC + reg, val); 1958 sky2_write32(hw, Y2_CFG_SPC + reg, val);
1966 } 1959 }
1967 1960
1968 static inline void sky2_pci_write16(struct sky2_hw *hw, unsigned reg, u16 val) 1961 static inline void sky2_pci_write16(struct sky2_hw *hw, unsigned reg, u16 val)
1969 { 1962 {
1970 sky2_write16(hw, Y2_CFG_SPC + reg, val); 1963 sky2_write16(hw, Y2_CFG_SPC + reg, val);
1971 } 1964 }
1972 #endif 1965 #endif