Eric Lee / linux-smarc-t335x-v3.2

Commit f2ab4461249df85b20930a7a57b54f39c5ae291a

Authored by Zachary Amsden 2005-09-04 06:56:42 +0800

Committed by Linus Torvalds 2005-09-05 15:06:12 +0800

Exists in master and in 4 other branches

[PATCH] x86: more asm cleanups

Some more assembler cleanups I noticed along the way.

Signed-off-by: Zachary Amsden <zach@vmware.com>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

Showing 8 changed files with 35 additions and 50 deletions Inline Diff

arch/i386/kernel/cpu/intel.c
arch/i386/kernel/crash.c
arch/i386/kernel/machine_kexec.c
arch/i386/kernel/msr.c
arch/i386/kernel/process.c
arch/i386/mach-voyager/voyager_basic.c
arch/i386/mach-voyager/voyager_smp.c
include/asm-i386/msr.h

arch/i386/kernel/cpu/intel.c

Diff comments View file @ f2ab446

 #include <linux/config.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/string.h>
 #include <linux/bitops.h>
 #include <linux/smp.h>
 #include <linux/thread_info.h>
 #include <asm/processor.h>
 #include <asm/msr.h>
 #include <asm/uaccess.h>
 #include "cpu.h"
 #ifdef CONFIG_X86_LOCAL_APIC
 #include <asm/mpspec.h>
 #include <asm/apic.h>
 #include <mach_apic.h>
 #endif
 extern int trap_init_f00f_bug(void);
 #ifdef CONFIG_X86_INTEL_USERCOPY
 /*
  * Alignment at which movsl is preferred for bulk memory copies.
  */
 struct movsl_mask movsl_mask __read_mostly;
 #endif
 void __devinit early_intel_workaround(struct cpuinfo_x86 *c)
 {
 	if (c->x86_vendor != X86_VENDOR_INTEL)
 		return;
 	/* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
 	if (c->x86 == 15 && c->x86_cache_alignment == 64)
 		c->x86_cache_alignment = 128;
 }
 /*
  *	Early probe support logic for ppro memory erratum #50
  *
  *	This is called before we do cpu ident work
  */
 int __devinit ppro_with_ram_bug(void)
 {
 	/* Uses data from early_cpu_detect now */
 	if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
 	    boot_cpu_data.x86 == 6 &&
 	    boot_cpu_data.x86_model == 1 &&
 	    boot_cpu_data.x86_mask < 8) {
 		printk(KERN_INFO "Pentium Pro with Errata#50 detected. Taking evasive action.\n");
 		return 1;
 	}
 	return 0;
 }
 /*
  * P4 Xeon errata 037 workaround.
  * Hardware prefetcher may cause stale data to be loaded into the cache.
  */
 static void __devinit Intel_errata_workarounds(struct cpuinfo_x86 *c)
 {
 	unsigned long lo, hi;
 	if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
 		rdmsr (MSR_IA32_MISC_ENABLE, lo, hi);
 		if ((lo & (1<<9)) == 0) {
 			printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
 			printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");
 			lo |= (1<<9);	/* Disable hw prefetching */
 			wrmsr (MSR_IA32_MISC_ENABLE, lo, hi);
 		}
 	}
 }
 /*
  * find out the number of processor cores on the die
  */
 static int __devinit num_cpu_cores(struct cpuinfo_x86 *c)
 {
-	unsigned int eax;
+	unsigned int eax, ebx, ecx, edx;
 	if (c->cpuid_level < 4)
 		return 1;
-	__asm__("cpuid"
+	/* Intel has a non-standard dependency on %ecx for this CPUID level. */
-		: "=a" (eax)
+	cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
-		: "0" (4), "c" (0)
-		: "bx", "dx");
 	if (eax & 0x1f)
 		return ((eax >> 26) + 1);
 	else
 		return 1;
 }
 static void __devinit init_intel(struct cpuinfo_x86 *c)
 {
 	unsigned int l2 = 0;
 	char *p = NULL;
 #ifdef CONFIG_X86_F00F_BUG
 	/*
 	 * All current models of Pentium and Pentium with MMX technology CPUs
 	 * have the F0 0F bug, which lets nonprivileged users lock up the system.
 	 * Note that the workaround only should be initialized once...
 	 */
 	c->f00f_bug = 0;
 	if ( c->x86 == 5 ) {
 		static int f00f_workaround_enabled = 0;
 		c->f00f_bug = 1;
 		if ( !f00f_workaround_enabled ) {
 			trap_init_f00f_bug();
 			printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n");
 			f00f_workaround_enabled = 1;
 		}
 	}
 #endif
 	select_idle_routine(c);
 	l2 = init_intel_cacheinfo(c);
 	/* SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until model 3 mask 3 */
 	if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
 		clear_bit(X86_FEATURE_SEP, c->x86_capability);
 	/* Names for the Pentium II/Celeron processors
 	   detectable only by also checking the cache size.
 	   Dixon is NOT a Celeron. */
 	if (c->x86 == 6) {
 		switch (c->x86_model) {
 		case 5:
 			if (c->x86_mask == 0) {
 				if (l2 == 0)
 					p = "Celeron (Covington)";
 				else if (l2 == 256)
 					p = "Mobile Pentium II (Dixon)";
 			}
 			break;
 		case 6:
 			if (l2 == 128)
 				p = "Celeron (Mendocino)";
 			else if (c->x86_mask == 0 || c->x86_mask == 5)
 				p = "Celeron-A";
 			break;
 		case 8:
 			if (l2 == 128)
 				p = "Celeron (Coppermine)";
 			break;
 		}
 	}
 	if ( p )
 		strcpy(c->x86_model_id, p);
 	c->x86_num_cores = num_cpu_cores(c);
 	detect_ht(c);
 	/* Work around errata */
 	Intel_errata_workarounds(c);
 #ifdef CONFIG_X86_INTEL_USERCOPY
 	/*
 	 * Set up the preferred alignment for movsl bulk memory moves
 	 */
 	switch (c->x86) {
 	case 4:		/* 486: untested */
 		break;
 	case 5:		/* Old Pentia: untested */
 		break;
 	case 6:		/* PII/PIII only like movsl with 8-byte alignment */
 		movsl_mask.mask = 7;
 		break;
 	case 15:	/* P4 is OK down to 8-byte alignment */
 		movsl_mask.mask = 7;
 		break;
 	}
 #endif
 	if (c->x86 == 15)
 		set_bit(X86_FEATURE_P4, c->x86_capability);
 	if (c->x86 == 6)
 		set_bit(X86_FEATURE_P3, c->x86_capability);
 }
 static unsigned int intel_size_cache(struct cpuinfo_x86 * c, unsigned int size)
 {
 	/* Intel PIII Tualatin. This comes in two flavours.
 	 * One has 256kb of cache, the other 512. We have no way
 	 * to determine which, so we use a boottime override
 	 * for the 512kb model, and assume 256 otherwise.
 	 */
 	if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
 		size = 256;
 	return size;
 }
 static struct cpu_dev intel_cpu_dev __devinitdata = {
 	.c_vendor	= "Intel",
 	.c_ident 	= { "GenuineIntel" },
 	.c_models = {
 		{ .vendor = X86_VENDOR_INTEL, .family = 4, .model_names =
 		  {
 			  [0] = "486 DX-25/33",
 			  [1] = "486 DX-50",
 			  [2] = "486 SX",
 			  [3] = "486 DX/2",
 			  [4] = "486 SL",
 			  [5] = "486 SX/2",
 			  [7] = "486 DX/2-WB",
 			  [8] = "486 DX/4",
 			  [9] = "486 DX/4-WB"
 		  }
 		},
 		{ .vendor = X86_VENDOR_INTEL, .family = 5, .model_names =
 		  {
 			  [0] = "Pentium 60/66 A-step",
 			  [1] = "Pentium 60/66",
 			  [2] = "Pentium 75 - 200",
 			  [3] = "OverDrive PODP5V83",
 			  [4] = "Pentium MMX",
 			  [7] = "Mobile Pentium 75 - 200",
 			  [8] = "Mobile Pentium MMX"
 		  }
 		},
 		{ .vendor = X86_VENDOR_INTEL, .family = 6, .model_names =
 		  {
 			  [0] = "Pentium Pro A-step",
 			  [1] = "Pentium Pro",
 			  [3] = "Pentium II (Klamath)",
 			  [4] = "Pentium II (Deschutes)",
 			  [5] = "Pentium II (Deschutes)",
 			  [6] = "Mobile Pentium II",
 			  [7] = "Pentium III (Katmai)",
 			  [8] = "Pentium III (Coppermine)",
 			  [10] = "Pentium III (Cascades)",
 			  [11] = "Pentium III (Tualatin)",
 		  }
 		},
 		{ .vendor = X86_VENDOR_INTEL, .family = 15, .model_names =
 		  {
 			  [0] = "Pentium 4 (Unknown)",
 			  [1] = "Pentium 4 (Willamette)",
 			  [2] = "Pentium 4 (Northwood)",
 			  [4] = "Pentium 4 (Foster)",
 			  [5] = "Pentium 4 (Foster)",
 		  }
 		},
 	},
 	.c_init		= init_intel,
 	.c_identify	= generic_identify,
 	.c_size_cache	= intel_size_cache,
 };
 __init int intel_cpu_init(void)
 {
 	cpu_devs[X86_VENDOR_INTEL] = &intel_cpu_dev;
 	return 0;
 }
 // arch_initcall(intel_cpu_init);

arch/i386/kernel/crash.c

Diff comments View file @ f2ab446

1	/*	1	/*
2	* Architecture specific (i386) functions for kexec based crash dumps.	2	* Architecture specific (i386) functions for kexec based crash dumps.
3	*	3	*
4	* Created by: Hariprasad Nellitheertha (hari@in.ibm.com)	4	* Created by: Hariprasad Nellitheertha (hari@in.ibm.com)
5	*	5	*
6	* Copyright (C) IBM Corporation, 2004. All rights reserved.	6	* Copyright (C) IBM Corporation, 2004. All rights reserved.
7	*	7	*
8	*/	8	*/
9		9
10	#include <linux/init.h>	10	#include <linux/init.h>
11	#include <linux/types.h>	11	#include <linux/types.h>
12	#include <linux/kernel.h>	12	#include <linux/kernel.h>
13	#include <linux/smp.h>	13	#include <linux/smp.h>
14	#include <linux/irq.h>	14	#include <linux/irq.h>
15	#include <linux/reboot.h>	15	#include <linux/reboot.h>
16	#include <linux/kexec.h>	16	#include <linux/kexec.h>
17	#include <linux/irq.h>	17	#include <linux/irq.h>
18	#include <linux/delay.h>	18	#include <linux/delay.h>
19	#include <linux/elf.h>	19	#include <linux/elf.h>
20	#include <linux/elfcore.h>	20	#include <linux/elfcore.h>
21		21
22	#include <asm/processor.h>	22	#include <asm/processor.h>
23	#include <asm/hardirq.h>	23	#include <asm/hardirq.h>
24	#include <asm/nmi.h>	24	#include <asm/nmi.h>
25	#include <asm/hw_irq.h>	25	#include <asm/hw_irq.h>
26	#include <asm/apic.h>	26	#include <asm/apic.h>
27	#include <mach_ipi.h>	27	#include <mach_ipi.h>
28		28
29		29
30	note_buf_t crash_notes[NR_CPUS];	30	note_buf_t crash_notes[NR_CPUS];
31	/* This keeps a track of which one is crashing cpu. */	31	/* This keeps a track of which one is crashing cpu. */
32	static int crashing_cpu;	32	static int crashing_cpu;
33		33
34	static u32 append_elf_note(u32 buf, char name, unsigned type, void data,	34	static u32 append_elf_note(u32 buf, char name, unsigned type, void data,
35	size_t data_len)	35	size_t data_len)
36	{	36	{
37	struct elf_note note;	37	struct elf_note note;
38		38
39	note.n_namesz = strlen(name) + 1;	39	note.n_namesz = strlen(name) + 1;
40	note.n_descsz = data_len;	40	note.n_descsz = data_len;
41	note.n_type = type;	41	note.n_type = type;
42	memcpy(buf, &note, sizeof(note));	42	memcpy(buf, &note, sizeof(note));
43	buf += (sizeof(note) +3)/4;	43	buf += (sizeof(note) +3)/4;
44	memcpy(buf, name, note.n_namesz);	44	memcpy(buf, name, note.n_namesz);
45	buf += (note.n_namesz + 3)/4;	45	buf += (note.n_namesz + 3)/4;
46	memcpy(buf, data, note.n_descsz);	46	memcpy(buf, data, note.n_descsz);
47	buf += (note.n_descsz + 3)/4;	47	buf += (note.n_descsz + 3)/4;
48		48
49	return buf;	49	return buf;
50	}	50	}
51		51
52	static void final_note(u32 *buf)	52	static void final_note(u32 *buf)
53	{	53	{
54	struct elf_note note;	54	struct elf_note note;
55		55
56	note.n_namesz = 0;	56	note.n_namesz = 0;
57	note.n_descsz = 0;	57	note.n_descsz = 0;
58	note.n_type = 0;	58	note.n_type = 0;
59	memcpy(buf, &note, sizeof(note));	59	memcpy(buf, &note, sizeof(note));
60	}	60	}
61		61
62	static void crash_save_this_cpu(struct pt_regs *regs, int cpu)	62	static void crash_save_this_cpu(struct pt_regs *regs, int cpu)
63	{	63	{
64	struct elf_prstatus prstatus;	64	struct elf_prstatus prstatus;
65	u32 *buf;	65	u32 *buf;
66		66
67	if ((cpu < 0) \|\| (cpu >= NR_CPUS))	67	if ((cpu < 0) \|\| (cpu >= NR_CPUS))
68	return;	68	return;
69		69
70	/* Using ELF notes here is opportunistic.	70	/* Using ELF notes here is opportunistic.
71	* I need a well defined structure format	71	* I need a well defined structure format
72	* for the data I pass, and I need tags	72	* for the data I pass, and I need tags
73	* on the data to indicate what information I have	73	* on the data to indicate what information I have
74	* squirrelled away. ELF notes happen to provide	74	* squirrelled away. ELF notes happen to provide
75	* all of that that no need to invent something new.	75	* all of that that no need to invent something new.
76	*/	76	*/
77	buf = &crash_notes[cpu][0];	77	buf = &crash_notes[cpu][0];
78	memset(&prstatus, 0, sizeof(prstatus));	78	memset(&prstatus, 0, sizeof(prstatus));
79	prstatus.pr_pid = current->pid;	79	prstatus.pr_pid = current->pid;
80	elf_core_copy_regs(&prstatus.pr_reg, regs);	80	elf_core_copy_regs(&prstatus.pr_reg, regs);
81	buf = append_elf_note(buf, "CORE", NT_PRSTATUS, &prstatus,	81	buf = append_elf_note(buf, "CORE", NT_PRSTATUS, &prstatus,
82	sizeof(prstatus));	82	sizeof(prstatus));
83	final_note(buf);	83	final_note(buf);
84	}	84	}
85		85
86	static void crash_get_current_regs(struct pt_regs *regs)	86	static void crash_get_current_regs(struct pt_regs *regs)
87	{	87	{
88	__asm__ __volatile__("movl %%ebx,%0" : "=m"(regs->ebx));	88	__asm__ __volatile__("movl %%ebx,%0" : "=m"(regs->ebx));
89	__asm__ __volatile__("movl %%ecx,%0" : "=m"(regs->ecx));	89	__asm__ __volatile__("movl %%ecx,%0" : "=m"(regs->ecx));
90	__asm__ __volatile__("movl %%edx,%0" : "=m"(regs->edx));	90	__asm__ __volatile__("movl %%edx,%0" : "=m"(regs->edx));
91	__asm__ __volatile__("movl %%esi,%0" : "=m"(regs->esi));	91	__asm__ __volatile__("movl %%esi,%0" : "=m"(regs->esi));
92	__asm__ __volatile__("movl %%edi,%0" : "=m"(regs->edi));	92	__asm__ __volatile__("movl %%edi,%0" : "=m"(regs->edi));
93	__asm__ __volatile__("movl %%ebp,%0" : "=m"(regs->ebp));	93	__asm__ __volatile__("movl %%ebp,%0" : "=m"(regs->ebp));
94	__asm__ __volatile__("movl %%eax,%0" : "=m"(regs->eax));	94	__asm__ __volatile__("movl %%eax,%0" : "=m"(regs->eax));
95	__asm__ __volatile__("movl %%esp,%0" : "=m"(regs->esp));	95	__asm__ __volatile__("movl %%esp,%0" : "=m"(regs->esp));
96	__asm__ __volatile__("movw %%ss, %%ax;" :"=a"(regs->xss));	96	__asm__ __volatile__("movw %%ss, %%ax;" :"=a"(regs->xss));
97	__asm__ __volatile__("movw %%cs, %%ax;" :"=a"(regs->xcs));	97	__asm__ __volatile__("movw %%cs, %%ax;" :"=a"(regs->xcs));
98	__asm__ __volatile__("movw %%ds, %%ax;" :"=a"(regs->xds));	98	__asm__ __volatile__("movw %%ds, %%ax;" :"=a"(regs->xds));
99	__asm__ __volatile__("movw %%es, %%ax;" :"=a"(regs->xes));	99	__asm__ __volatile__("movw %%es, %%ax;" :"=a"(regs->xes));
100	__asm__ __volatile__("pushfl; popl %0" :"=m"(regs->eflags));	100	__asm__ __volatile__("pushfl; popl %0" :"=m"(regs->eflags));
101		101
102	regs->eip = (unsigned long)current_text_addr();	102	regs->eip = (unsigned long)current_text_addr();
103	}	103	}
104		104
105	/* CPU does not save ss and esp on stack if execution is already	105	/* CPU does not save ss and esp on stack if execution is already
106	* running in kernel mode at the time of NMI occurrence. This code	106	* running in kernel mode at the time of NMI occurrence. This code
107	* fixes it.	107	* fixes it.
108	*/	108	*/
109	static void crash_setup_regs(struct pt_regs newregs, struct pt_regs oldregs)	109	static void crash_setup_regs(struct pt_regs newregs, struct pt_regs oldregs)
110	{	110	{
111	memcpy(newregs, oldregs, sizeof(*newregs));	111	memcpy(newregs, oldregs, sizeof(*newregs));
112	newregs->esp = (unsigned long)&(oldregs->esp);	112	newregs->esp = (unsigned long)&(oldregs->esp);
113	__asm__ __volatile__("xorl %eax, %eax;");	113	__asm__ __volatile__("xorl %eax, %eax;");
114	__asm__ __volatile__ ("movw %%ss, %%ax;" :"=a"(newregs->xss));	114	__asm__ __volatile__ ("movw %%ss, %%ax;" :"=a"(newregs->xss));
115	}	115	}
116		116
117	/* We may have saved_regs from where the error came from	117	/* We may have saved_regs from where the error came from
118	* or it is NULL if via a direct panic().	118	* or it is NULL if via a direct panic().
119	*/	119	*/
120	static void crash_save_self(struct pt_regs *saved_regs)	120	static void crash_save_self(struct pt_regs *saved_regs)
121	{	121	{
122	struct pt_regs regs;	122	struct pt_regs regs;
123	int cpu;	123	int cpu;
124		124
125	cpu = smp_processor_id();	125	cpu = smp_processor_id();
126	if (saved_regs)	126	if (saved_regs)
127	crash_setup_regs(&regs, saved_regs);	127	crash_setup_regs(&regs, saved_regs);
128	else	128	else
129	crash_get_current_regs(&regs);	129	crash_get_current_regs(&regs);
130	crash_save_this_cpu(&regs, cpu);	130	crash_save_this_cpu(&regs, cpu);
131	}	131	}
132		132
133	#ifdef CONFIG_SMP	133	#ifdef CONFIG_SMP
134	static atomic_t waiting_for_crash_ipi;	134	static atomic_t waiting_for_crash_ipi;
135		135
136	static int crash_nmi_callback(struct pt_regs *regs, int cpu)	136	static int crash_nmi_callback(struct pt_regs *regs, int cpu)
137	{	137	{
138	struct pt_regs fixed_regs;	138	struct pt_regs fixed_regs;
139		139
140	/* Don't do anything if this handler is invoked on crashing cpu.	140	/* Don't do anything if this handler is invoked on crashing cpu.
141	* Otherwise, system will completely hang. Crashing cpu can get	141	* Otherwise, system will completely hang. Crashing cpu can get
142	* an NMI if system was initially booted with nmi_watchdog parameter.	142	* an NMI if system was initially booted with nmi_watchdog parameter.
143	*/	143	*/
144	if (cpu == crashing_cpu)	144	if (cpu == crashing_cpu)
145	return 1;	145	return 1;
146	local_irq_disable();	146	local_irq_disable();
147		147
148	if (!user_mode(regs)) {	148	if (!user_mode(regs)) {
149	crash_setup_regs(&fixed_regs, regs);	149	crash_setup_regs(&fixed_regs, regs);
150	regs = &fixed_regs;	150	regs = &fixed_regs;
151	}	151	}
152	crash_save_this_cpu(regs, cpu);	152	crash_save_this_cpu(regs, cpu);
153	disable_local_APIC();	153	disable_local_APIC();
154	atomic_dec(&waiting_for_crash_ipi);	154	atomic_dec(&waiting_for_crash_ipi);
155	/* Assume hlt works */	155	/* Assume hlt works */
156	__asm__("hlt");	156	halt();
157	for(;;);	157	for(;;);
158		158
159	return 1;	159	return 1;
160	}	160	}
161		161
162	/*	162	/*
163	* By using the NMI code instead of a vector we just sneak thru the	163	* By using the NMI code instead of a vector we just sneak thru the
164	* word generator coming out with just what we want. AND it does	164	* word generator coming out with just what we want. AND it does
165	* not matter if clustered_apic_mode is set or not.	165	* not matter if clustered_apic_mode is set or not.
166	*/	166	*/
167	static void smp_send_nmi_allbutself(void)	167	static void smp_send_nmi_allbutself(void)
168	{	168	{
169	send_IPI_allbutself(APIC_DM_NMI);	169	send_IPI_allbutself(APIC_DM_NMI);
170	}	170	}
171		171
172	static void nmi_shootdown_cpus(void)	172	static void nmi_shootdown_cpus(void)
173	{	173	{
174	unsigned long msecs;	174	unsigned long msecs;
175		175
176	atomic_set(&waiting_for_crash_ipi, num_online_cpus() - 1);	176	atomic_set(&waiting_for_crash_ipi, num_online_cpus() - 1);
177	/* Would it be better to replace the trap vector here? */	177	/* Would it be better to replace the trap vector here? */
178	set_nmi_callback(crash_nmi_callback);	178	set_nmi_callback(crash_nmi_callback);
179	/* Ensure the new callback function is set before sending	179	/* Ensure the new callback function is set before sending
180	* out the NMI	180	* out the NMI
181	*/	181	*/
182	wmb();	182	wmb();
183		183
184	smp_send_nmi_allbutself();	184	smp_send_nmi_allbutself();
185		185
186	msecs = 1000; /* Wait at most a second for the other cpus to stop */	186	msecs = 1000; /* Wait at most a second for the other cpus to stop */
187	while ((atomic_read(&waiting_for_crash_ipi) > 0) && msecs) {	187	while ((atomic_read(&waiting_for_crash_ipi) > 0) && msecs) {
188	mdelay(1);	188	mdelay(1);
189	msecs--;	189	msecs--;
190	}	190	}
191		191
192	/* Leave the nmi callback set */	192	/* Leave the nmi callback set */
193	disable_local_APIC();	193	disable_local_APIC();
194	}	194	}
195	#else	195	#else
196	static void nmi_shootdown_cpus(void)	196	static void nmi_shootdown_cpus(void)
197	{	197	{
198	/* There are no cpus to shootdown */	198	/* There are no cpus to shootdown */
199	}	199	}
200	#endif	200	#endif
201		201
202	void machine_crash_shutdown(struct pt_regs *regs)	202	void machine_crash_shutdown(struct pt_regs *regs)
203	{	203	{
204	/* This function is only called after the system	204	/* This function is only called after the system
205	* has paniced or is otherwise in a critical state.	205	* has paniced or is otherwise in a critical state.
206	* The minimum amount of code to allow a kexec'd kernel	206	* The minimum amount of code to allow a kexec'd kernel
207	* to run successfully needs to happen here.	207	* to run successfully needs to happen here.
208	*	208	*
209	* In practice this means shooting down the other cpus in	209	* In practice this means shooting down the other cpus in
210	* an SMP system.	210	* an SMP system.
211	*/	211	*/
212	/* The kernel is broken so disable interrupts */	212	/* The kernel is broken so disable interrupts */
213	local_irq_disable();	213	local_irq_disable();
214		214
215	/* Make a note of crashing cpu. Will be used in NMI callback.*/	215	/* Make a note of crashing cpu. Will be used in NMI callback.*/
216	crashing_cpu = smp_processor_id();	216	crashing_cpu = smp_processor_id();
217	nmi_shootdown_cpus();	217	nmi_shootdown_cpus();
218	lapic_shutdown();	218	lapic_shutdown();
219	#if defined(CONFIG_X86_IO_APIC)	219	#if defined(CONFIG_X86_IO_APIC)
220	disable_IO_APIC();	220	disable_IO_APIC();
221	#endif	221	#endif
222	crash_save_self(regs);	222	crash_save_self(regs);
223	}	223	}
224		224

arch/i386/kernel/machine_kexec.c

Diff comments View file @ f2ab446

 /*
  * machine_kexec.c - handle transition of Linux booting another kernel
  * Copyright (C) 2002-2005 Eric Biederman  <ebiederm@xmission.com>
  *
  * This source code is licensed under the GNU General Public License,
  * Version 2.  See the file COPYING for more details.
  */
 #include <linux/mm.h>
 #include <linux/kexec.h>
 #include <linux/delay.h>
 #include <asm/pgtable.h>
 #include <asm/pgalloc.h>
 #include <asm/tlbflush.h>
 #include <asm/mmu_context.h>
 #include <asm/io.h>
 #include <asm/apic.h>
 #include <asm/cpufeature.h>
 #include <asm/desc.h>
 #include <asm/system.h>
 #define PAGE_ALIGNED __attribute__ ((__aligned__(PAGE_SIZE)))
 #define L0_ATTR (_PAGE_PRESENT | _PAGE_RW | _PAGE_ACCESSED | _PAGE_DIRTY)
 #define L1_ATTR (_PAGE_PRESENT | _PAGE_RW | _PAGE_ACCESSED | _PAGE_DIRTY)
 #define L2_ATTR (_PAGE_PRESENT)
 #define LEVEL0_SIZE (1UL << 12UL)
 #ifndef CONFIG_X86_PAE
 #define LEVEL1_SIZE (1UL << 22UL)
 static u32 pgtable_level1[1024] PAGE_ALIGNED;
 static void identity_map_page(unsigned long address)
 {
 	unsigned long level1_index, level2_index;
 	u32 *pgtable_level2;
 	/* Find the current page table */
 	pgtable_level2 = __va(read_cr3());
 	/* Find the indexes of the physical address to identity map */
 	level1_index = (address % LEVEL1_SIZE)/LEVEL0_SIZE;
 	level2_index = address / LEVEL1_SIZE;
 	/* Identity map the page table entry */
 	pgtable_level1[level1_index] = address | L0_ATTR;
 	pgtable_level2[level2_index] = __pa(pgtable_level1) | L1_ATTR;
 	/* Flush the tlb so the new mapping takes effect.
 	 * Global tlb entries are not flushed but that is not an issue.
 	 */
 	load_cr3(pgtable_level2);
 }
 #else
 #define LEVEL1_SIZE (1UL << 21UL)
 #define LEVEL2_SIZE (1UL << 30UL)
 static u64 pgtable_level1[512] PAGE_ALIGNED;
 static u64 pgtable_level2[512] PAGE_ALIGNED;
 static void identity_map_page(unsigned long address)
 {
 	unsigned long level1_index, level2_index, level3_index;
 	u64 *pgtable_level3;
 	/* Find the current page table */
 	pgtable_level3 = __va(read_cr3());
 	/* Find the indexes of the physical address to identity map */
 	level1_index = (address % LEVEL1_SIZE)/LEVEL0_SIZE;
 	level2_index = (address % LEVEL2_SIZE)/LEVEL1_SIZE;
 	level3_index = address / LEVEL2_SIZE;
 	/* Identity map the page table entry */
 	pgtable_level1[level1_index] = address | L0_ATTR;
 	pgtable_level2[level2_index] = __pa(pgtable_level1) | L1_ATTR;
 	set_64bit(&pgtable_level3[level3_index],
 					       __pa(pgtable_level2) | L2_ATTR);
 	/* Flush the tlb so the new mapping takes effect.
 	 * Global tlb entries are not flushed but that is not an issue.
 	 */
 	load_cr3(pgtable_level3);
 }
 #endif
 static void set_idt(void *newidt, __u16 limit)
 {
 	struct Xgt_desc_struct curidt;
 	/* ia32 supports unaliged loads & stores */
 	curidt.size    = limit;
 	curidt.address = (unsigned long)newidt;
-	__asm__ __volatile__ (
+	load_idt(&curidt);
-		"lidtl %0\n"
-		: : "m" (curidt)
-		);
 };
 static void set_gdt(void *newgdt, __u16 limit)
 {
 	struct Xgt_desc_struct curgdt;
 	/* ia32 supports unaligned loads & stores */
 	curgdt.size    = limit;
 	curgdt.address = (unsigned long)newgdt;
-	__asm__ __volatile__ (
+	load_gdt(&curgdt);
-		"lgdtl %0\n"
-		: : "m" (curgdt)
-		);
 };
 static void load_segments(void)
 {
 #define __STR(X) #X
 #define STR(X) __STR(X)
 	__asm__ __volatile__ (
 		"\tljmp $"STR(__KERNEL_CS)",$1f\n"
 		"\t1:\n"
 		"\tmovl $"STR(__KERNEL_DS)",%eax\n"
 		"\tmovl %eax,%ds\n"
 		"\tmovl %eax,%es\n"
 		"\tmovl %eax,%fs\n"
 		"\tmovl %eax,%gs\n"
 		"\tmovl %eax,%ss\n"
 		);
 #undef STR
 #undef __STR
 }
 typedef asmlinkage NORET_TYPE void (*relocate_new_kernel_t)(
 					unsigned long indirection_page,
 					unsigned long reboot_code_buffer,
 					unsigned long start_address,
 					unsigned int has_pae) ATTRIB_NORET;
 const extern unsigned char relocate_new_kernel[];
 extern void relocate_new_kernel_end(void);
 const extern unsigned int relocate_new_kernel_size;
 /*
  * A architecture hook called to validate the
  * proposed image and prepare the control pages
  * as needed.  The pages for KEXEC_CONTROL_CODE_SIZE
  * have been allocated, but the segments have yet
  * been copied into the kernel.
  *
  * Do what every setup is needed on image and the
  * reboot code buffer to allow us to avoid allocations
  * later.
  *
  * Currently nothing.
  */
 int machine_kexec_prepare(struct kimage *image)
 {
 	return 0;
 }
 /*
  * Undo anything leftover by machine_kexec_prepare
  * when an image is freed.
  */
 void machine_kexec_cleanup(struct kimage *image)
 {
 }
 /*
  * Do not allocate memory (or fail in any way) in machine_kexec().
  * We are past the point of no return, committed to rebooting now.
  */
 NORET_TYPE void machine_kexec(struct kimage *image)
 {
 	unsigned long page_list;
 	unsigned long reboot_code_buffer;
 	relocate_new_kernel_t rnk;
 	/* Interrupts aren't acceptable while we reboot */
 	local_irq_disable();
 	/* Compute some offsets */
 	reboot_code_buffer = page_to_pfn(image->control_code_page)
 								<< PAGE_SHIFT;
 	page_list = image->head;
 	/* Set up an identity mapping for the reboot_code_buffer */
 	identity_map_page(reboot_code_buffer);
 	/* copy it out */
 	memcpy((void *)reboot_code_buffer, relocate_new_kernel,
 						relocate_new_kernel_size);
 	/* The segment registers are funny things, they are
 	 * automatically loaded from a table, in memory wherever you
 	 * set them to a specific selector, but this table is never
 	 * accessed again you set the segment to a different selector.
 	 *
 	 * The more common model is are caches where the behide
 	 * the scenes work is done, but is also dropped at arbitrary
 	 * times.
 	 *
 	 * I take advantage of this here by force loading the
 	 * segments, before I zap the gdt with an invalid value.
 	 */
 	load_segments();
 	/* The gdt & idt are now invalid.
 	 * If you want to load them you must set up your own idt & gdt.
 	 */
 	set_gdt(phys_to_virt(0),0);
 	set_idt(phys_to_virt(0),0);
 	/* now call it */
 	rnk = (relocate_new_kernel_t) reboot_code_buffer;
 	(*rnk)(page_list, reboot_code_buffer, image->start, cpu_has_pae);
 }

arch/i386/kernel/msr.c

Diff comments View file @ f2ab446

 /* ----------------------------------------------------------------------- *
  *
  *   Copyright 2000 H. Peter Anvin - All Rights Reserved
  *
  *   This program is free software; you can redistribute it and/or modify
  *   it under the terms of the GNU General Public License as published by
  *   the Free Software Foundation, Inc., 675 Mass Ave, Cambridge MA 02139,
  *   USA; either version 2 of the License, or (at your option) any later
  *   version; incorporated herein by reference.
  *
  * ----------------------------------------------------------------------- */
 /*
  * msr.c
  *
  * x86 MSR access device
  *
  * This device is accessed by lseek() to the appropriate register number
  * and then read/write in chunks of 8 bytes.  A larger size means multiple
  * reads or writes of the same register.
  *
  * This driver uses /dev/cpu/%d/msr where %d is the minor number, and on
  * an SMP box will direct the access to CPU %d.
  */
 #include <linux/module.h>
 #include <linux/config.h>
 #include <linux/types.h>
 #include <linux/errno.h>
 #include <linux/fcntl.h>
 #include <linux/init.h>
 #include <linux/poll.h>
 #include <linux/smp.h>
 #include <linux/smp_lock.h>
 #include <linux/major.h>
 #include <linux/fs.h>
 #include <linux/device.h>
 #include <linux/cpu.h>
 #include <linux/notifier.h>
 #include <asm/processor.h>
 #include <asm/msr.h>
 #include <asm/uaccess.h>
 #include <asm/system.h>
 static struct class *msr_class;
-/* Note: "err" is handled in a funny way below.  Otherwise one version
-   of gcc or another breaks. */
 static inline int wrmsr_eio(u32 reg, u32 eax, u32 edx)
 {
 	int err;
-	asm volatile ("1:	wrmsr\n"
+	err = wrmsr_safe(reg, eax, edx);
-		      "2:\n"
+	if (err)
-		      ".section .fixup,\"ax\"\n"
+		err = -EIO;
-		      "3:	movl %4,%0\n"
-		      "	jmp 2b\n"
-		      ".previous\n"
-		      ".section __ex_table,\"a\"\n"
-		      "	.align 4\n" "	.long 1b,3b\n" ".previous":"=&bDS" (err)
-		      :"a"(eax), "d"(edx), "c"(reg), "i"(-EIO), "0"(0));
 	return err;
 }
 static inline int rdmsr_eio(u32 reg, u32 *eax, u32 *edx)
 {
 	int err;
-	asm volatile ("1:	rdmsr\n"
+	err = rdmsr_safe(reg, eax, edx);
-		      "2:\n"
+	if (err)
-		      ".section .fixup,\"ax\"\n"
+		err = -EIO;
-		      "3:	movl %4,%0\n"
-		      "	jmp 2b\n"
-		      ".previous\n"
-		      ".section __ex_table,\"a\"\n"
-		      "	.align 4\n"
-		      "	.long 1b,3b\n"
-		      ".previous":"=&bDS" (err), "=a"(*eax), "=d"(*edx)
-		      :"c"(reg), "i"(-EIO), "0"(0));
 	return err;
 }
 #ifdef CONFIG_SMP
 struct msr_command {
 	int cpu;
 	int err;
 	u32 reg;
 	u32 data[2];
 };
 static void msr_smp_wrmsr(void *cmd_block)
 {
 	struct msr_command *cmd = (struct msr_command *)cmd_block;
 	if (cmd->cpu == smp_processor_id())
 		cmd->err = wrmsr_eio(cmd->reg, cmd->data[0], cmd->data[1]);
 }
 static void msr_smp_rdmsr(void *cmd_block)
 {
 	struct msr_command *cmd = (struct msr_command *)cmd_block;
 	if (cmd->cpu == smp_processor_id())
 		cmd->err = rdmsr_eio(cmd->reg, &cmd->data[0], &cmd->data[1]);
 }
 static inline int do_wrmsr(int cpu, u32 reg, u32 eax, u32 edx)
 {
 	struct msr_command cmd;
 	int ret;
 	preempt_disable();
 	if (cpu == smp_processor_id()) {
 		ret = wrmsr_eio(reg, eax, edx);
 	} else {
 		cmd.cpu = cpu;
 		cmd.reg = reg;
 		cmd.data[0] = eax;
 		cmd.data[1] = edx;
 		smp_call_function(msr_smp_wrmsr, &cmd, 1, 1);
 		ret = cmd.err;
 	}
 	preempt_enable();
 	return ret;
 }
 static inline int do_rdmsr(int cpu, u32 reg, u32 * eax, u32 * edx)
 {
 	struct msr_command cmd;
 	int ret;
 	preempt_disable();
 	if (cpu == smp_processor_id()) {
 		ret = rdmsr_eio(reg, eax, edx);
 	} else {
 		cmd.cpu = cpu;
 		cmd.reg = reg;
 		smp_call_function(msr_smp_rdmsr, &cmd, 1, 1);
 		*eax = cmd.data[0];
 		*edx = cmd.data[1];
 		ret = cmd.err;
 	}
 	preempt_enable();
 	return ret;
 }
 #else				/* ! CONFIG_SMP */
 static inline int do_wrmsr(int cpu, u32 reg, u32 eax, u32 edx)
 {
 	return wrmsr_eio(reg, eax, edx);
 }
 static inline int do_rdmsr(int cpu, u32 reg, u32 *eax, u32 *edx)
 {
 	return rdmsr_eio(reg, eax, edx);
 }
 #endif				/* ! CONFIG_SMP */
 static loff_t msr_seek(struct file *file, loff_t offset, int orig)
 {
 	loff_t ret = -EINVAL;
 	lock_kernel();
 	switch (orig) {
 	case 0:
 		file->f_pos = offset;
 		ret = file->f_pos;
 		break;
 	case 1:
 		file->f_pos += offset;
 		ret = file->f_pos;
 	}
 	unlock_kernel();
 	return ret;
 }
 static ssize_t msr_read(struct file *file, char __user * buf,
 			size_t count, loff_t * ppos)
 {
 	u32 __user *tmp = (u32 __user *) buf;
 	u32 data[2];
 	size_t rv;
 	u32 reg = *ppos;
 	int cpu = iminor(file->f_dentry->d_inode);
 	int err;
 	if (count % 8)
 		return -EINVAL;	/* Invalid chunk size */
 	for (rv = 0; count; count -= 8) {
 		err = do_rdmsr(cpu, reg, &data[0], &data[1]);
 		if (err)
 			return err;
 		if (copy_to_user(tmp, &data, 8))
 			return -EFAULT;
 		tmp += 2;
 	}
 	return ((char __user *)tmp) - buf;
 }
 static ssize_t msr_write(struct file *file, const char __user *buf,
 			 size_t count, loff_t *ppos)
 {
 	const u32 __user *tmp = (const u32 __user *)buf;
 	u32 data[2];
 	size_t rv;
 	u32 reg = *ppos;
 	int cpu = iminor(file->f_dentry->d_inode);
 	int err;
 	if (count % 8)
 		return -EINVAL;	/* Invalid chunk size */
 	for (rv = 0; count; count -= 8) {
 		if (copy_from_user(&data, tmp, 8))
 			return -EFAULT;
 		err = do_wrmsr(cpu, reg, data[0], data[1]);
 		if (err)
 			return err;
 		tmp += 2;
 	}
 	return ((char __user *)tmp) - buf;
 }
 static int msr_open(struct inode *inode, struct file *file)
 {
 	unsigned int cpu = iminor(file->f_dentry->d_inode);
 	struct cpuinfo_x86 *c = &(cpu_data)[cpu];
 	if (cpu >= NR_CPUS || !cpu_online(cpu))
 		return -ENXIO;	/* No such CPU */
 	if (!cpu_has(c, X86_FEATURE_MSR))
 		return -EIO;	/* MSR not supported */
 	return 0;
 }
 /*
  * File operations we support
  */
 static struct file_operations msr_fops = {
 	.owner = THIS_MODULE,
 	.llseek = msr_seek,
 	.read = msr_read,
 	.write = msr_write,
 	.open = msr_open,
 };
 static int msr_class_device_create(int i)
 {
 	int err = 0;
 	struct class_device *class_err;
 	class_err = class_device_create(msr_class, MKDEV(MSR_MAJOR, i), NULL, "msr%d",i);
 	if (IS_ERR(class_err))
 		err = PTR_ERR(class_err);
 	return err;
 }
 static int __devinit msr_class_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu)
 {
 	unsigned int cpu = (unsigned long)hcpu;
 	switch (action) {
 	case CPU_ONLINE:
 		msr_class_device_create(cpu);
 		break;
 	case CPU_DEAD:
 		class_device_destroy(msr_class, MKDEV(MSR_MAJOR, cpu));
 		break;
 	}
 	return NOTIFY_OK;
 }
 static struct notifier_block msr_class_cpu_notifier =
 {
 	.notifier_call = msr_class_cpu_callback,
 };
 static int __init msr_init(void)
 {
 	int i, err = 0;
 	i = 0;
 	if (register_chrdev(MSR_MAJOR, "cpu/msr", &msr_fops)) {
 		printk(KERN_ERR "msr: unable to get major %d for msr\n",
 		       MSR_MAJOR);
 		err = -EBUSY;
 		goto out;
 	}
 	msr_class = class_create(THIS_MODULE, "msr");
 	if (IS_ERR(msr_class)) {
 		err = PTR_ERR(msr_class);
 		goto out_chrdev;
 	}
 	for_each_online_cpu(i) {
 		err = msr_class_device_create(i);
 		if (err != 0)
 			goto out_class;
 	}
 	register_cpu_notifier(&msr_class_cpu_notifier);
 	err = 0;
 	goto out;
 out_class:
 	i = 0;
 	for_each_online_cpu(i)
 		class_device_destroy(msr_class, MKDEV(MSR_MAJOR, i));
 	class_destroy(msr_class);
 out_chrdev:
 	unregister_chrdev(MSR_MAJOR, "cpu/msr");
 out:
 	return err;
 }
 static void __exit msr_exit(void)
 {
 	int cpu = 0;
 	for_each_online_cpu(cpu)
 		class_device_destroy(msr_class, MKDEV(MSR_MAJOR, cpu));
 	class_destroy(msr_class);
 	unregister_chrdev(MSR_MAJOR, "cpu/msr");
 	unregister_cpu_notifier(&msr_class_cpu_notifier);
 }
 module_init(msr_init);
 module_exit(msr_exit)
 MODULE_AUTHOR("H. Peter Anvin <hpa@zytor.com>");
 MODULE_DESCRIPTION("x86 generic MSR driver");
 MODULE_LICENSE("GPL");

arch/i386/kernel/process.c

Diff comments View file @ f2ab446

1	/*	1	/*
2	* linux/arch/i386/kernel/process.c	2	* linux/arch/i386/kernel/process.c
3	*	3	*
4	* Copyright (C) 1995 Linus Torvalds	4	* Copyright (C) 1995 Linus Torvalds
5	*	5	*
6	* Pentium III FXSR, SSE support	6	* Pentium III FXSR, SSE support
7	* Gareth Hughes <gareth@valinux.com>, May 2000	7	* Gareth Hughes <gareth@valinux.com>, May 2000
8	*/	8	*/
9		9
10	/*	10	/*
11	* This file handles the architecture-dependent parts of process handling..	11	* This file handles the architecture-dependent parts of process handling..
12	*/	12	*/
13		13
14	#include <stdarg.h>	14	#include <stdarg.h>
15		15
16	#include <linux/cpu.h>	16	#include <linux/cpu.h>
17	#include <linux/errno.h>	17	#include <linux/errno.h>
18	#include <linux/sched.h>	18	#include <linux/sched.h>
19	#include <linux/fs.h>	19	#include <linux/fs.h>
20	#include <linux/kernel.h>	20	#include <linux/kernel.h>
21	#include <linux/mm.h>	21	#include <linux/mm.h>
22	#include <linux/elfcore.h>	22	#include <linux/elfcore.h>
23	#include <linux/smp.h>	23	#include <linux/smp.h>
24	#include <linux/smp_lock.h>	24	#include <linux/smp_lock.h>
25	#include <linux/stddef.h>	25	#include <linux/stddef.h>
26	#include <linux/slab.h>	26	#include <linux/slab.h>
27	#include <linux/vmalloc.h>	27	#include <linux/vmalloc.h>
28	#include <linux/user.h>	28	#include <linux/user.h>
29	#include <linux/a.out.h>	29	#include <linux/a.out.h>
30	#include <linux/interrupt.h>	30	#include <linux/interrupt.h>
31	#include <linux/config.h>	31	#include <linux/config.h>
32	#include <linux/utsname.h>	32	#include <linux/utsname.h>
33	#include <linux/delay.h>	33	#include <linux/delay.h>
34	#include <linux/reboot.h>	34	#include <linux/reboot.h>
35	#include <linux/init.h>	35	#include <linux/init.h>
36	#include <linux/mc146818rtc.h>	36	#include <linux/mc146818rtc.h>
37	#include <linux/module.h>	37	#include <linux/module.h>
38	#include <linux/kallsyms.h>	38	#include <linux/kallsyms.h>
39	#include <linux/ptrace.h>	39	#include <linux/ptrace.h>
40	#include <linux/random.h>	40	#include <linux/random.h>
41	#include <linux/kprobes.h>	41	#include <linux/kprobes.h>
42		42
43	#include <asm/uaccess.h>	43	#include <asm/uaccess.h>
44	#include <asm/pgtable.h>	44	#include <asm/pgtable.h>
45	#include <asm/system.h>	45	#include <asm/system.h>
46	#include <asm/io.h>	46	#include <asm/io.h>
47	#include <asm/ldt.h>	47	#include <asm/ldt.h>
48	#include <asm/processor.h>	48	#include <asm/processor.h>
49	#include <asm/i387.h>	49	#include <asm/i387.h>
50	#include <asm/irq.h>	50	#include <asm/irq.h>
51	#include <asm/desc.h>	51	#include <asm/desc.h>
52	#ifdef CONFIG_MATH_EMULATION	52	#ifdef CONFIG_MATH_EMULATION
53	#include <asm/math_emu.h>	53	#include <asm/math_emu.h>
54	#endif	54	#endif
55		55
56	#include <linux/irq.h>	56	#include <linux/irq.h>
57	#include <linux/err.h>	57	#include <linux/err.h>
58		58
59	#include <asm/tlbflush.h>	59	#include <asm/tlbflush.h>
60	#include <asm/cpu.h>	60	#include <asm/cpu.h>
61		61
62	asmlinkage void ret_from_fork(void) __asm__("ret_from_fork");	62	asmlinkage void ret_from_fork(void) __asm__("ret_from_fork");
63		63
64	static int hlt_counter;	64	static int hlt_counter;
65		65
66	unsigned long boot_option_idle_override = 0;	66	unsigned long boot_option_idle_override = 0;
67	EXPORT_SYMBOL(boot_option_idle_override);	67	EXPORT_SYMBOL(boot_option_idle_override);
68		68
69	/*	69	/*
70	* Return saved PC of a blocked thread.	70	* Return saved PC of a blocked thread.
71	*/	71	*/
72	unsigned long thread_saved_pc(struct task_struct *tsk)	72	unsigned long thread_saved_pc(struct task_struct *tsk)
73	{	73	{
74	return ((unsigned long *)tsk->thread.esp)[3];	74	return ((unsigned long *)tsk->thread.esp)[3];
75	}	75	}
76		76
77	/*	77	/*
78	* Powermanagement idle function, if any..	78	* Powermanagement idle function, if any..
79	*/	79	*/
80	void (*pm_idle)(void);	80	void (*pm_idle)(void);
81	EXPORT_SYMBOL(pm_idle);	81	EXPORT_SYMBOL(pm_idle);
82	static DEFINE_PER_CPU(unsigned int, cpu_idle_state);	82	static DEFINE_PER_CPU(unsigned int, cpu_idle_state);
83		83
84	void disable_hlt(void)	84	void disable_hlt(void)
85	{	85	{
86	hlt_counter++;	86	hlt_counter++;
87	}	87	}
88		88
89	EXPORT_SYMBOL(disable_hlt);	89	EXPORT_SYMBOL(disable_hlt);
90		90
91	void enable_hlt(void)	91	void enable_hlt(void)
92	{	92	{
93	hlt_counter--;	93	hlt_counter--;
94	}	94	}
95		95
96	EXPORT_SYMBOL(enable_hlt);	96	EXPORT_SYMBOL(enable_hlt);
97		97
98	/*	98	/*
99	* We use this if we don't have any better	99	* We use this if we don't have any better
100	* idle routine..	100	* idle routine..
101	*/	101	*/
102	void default_idle(void)	102	void default_idle(void)
103	{	103	{
104	if (!hlt_counter && boot_cpu_data.hlt_works_ok) {	104	if (!hlt_counter && boot_cpu_data.hlt_works_ok) {
105	local_irq_disable();	105	local_irq_disable();
106	if (!need_resched())	106	if (!need_resched())
107	safe_halt();	107	safe_halt();
108	else	108	else
109	local_irq_enable();	109	local_irq_enable();
110	} else {	110	} else {
111	cpu_relax();	111	cpu_relax();
112	}	112	}
113	}	113	}
114	#ifdef CONFIG_APM_MODULE	114	#ifdef CONFIG_APM_MODULE
115	EXPORT_SYMBOL(default_idle);	115	EXPORT_SYMBOL(default_idle);
116	#endif	116	#endif
117		117
118	/*	118	/*
119	* On SMP it's slightly faster (but much more power-consuming!)	119	* On SMP it's slightly faster (but much more power-consuming!)
120	* to poll the ->work.need_resched flag instead of waiting for the	120	* to poll the ->work.need_resched flag instead of waiting for the
121	* cross-CPU IPI to arrive. Use this option with caution.	121	* cross-CPU IPI to arrive. Use this option with caution.
122	*/	122	*/
123	static void poll_idle (void)	123	static void poll_idle (void)
124	{	124	{
125	int oldval;	125	int oldval;
126		126
127	local_irq_enable();	127	local_irq_enable();
128		128
129	/*	129	/*
130	* Deal with another CPU just having chosen a thread to	130	* Deal with another CPU just having chosen a thread to
131	* run here:	131	* run here:
132	*/	132	*/
133	oldval = test_and_clear_thread_flag(TIF_NEED_RESCHED);	133	oldval = test_and_clear_thread_flag(TIF_NEED_RESCHED);
134		134
135	if (!oldval) {	135	if (!oldval) {
136	set_thread_flag(TIF_POLLING_NRFLAG);	136	set_thread_flag(TIF_POLLING_NRFLAG);
137	asm volatile(	137	asm volatile(
138	"2:"	138	"2:"
139	"testl %0, %1;"	139	"testl %0, %1;"
140	"rep; nop;"	140	"rep; nop;"
141	"je 2b;"	141	"je 2b;"
142	: : "i"(_TIF_NEED_RESCHED), "m" (current_thread_info()->flags));	142	: : "i"(_TIF_NEED_RESCHED), "m" (current_thread_info()->flags));
143		143
144	clear_thread_flag(TIF_POLLING_NRFLAG);	144	clear_thread_flag(TIF_POLLING_NRFLAG);
145	} else {	145	} else {
146	set_need_resched();	146	set_need_resched();
147	}	147	}
148	}	148	}
149		149
150	#ifdef CONFIG_HOTPLUG_CPU	150	#ifdef CONFIG_HOTPLUG_CPU
151	#include <asm/nmi.h>	151	#include <asm/nmi.h>
152	/* We don't actually take CPU down, just spin without interrupts. */	152	/* We don't actually take CPU down, just spin without interrupts. */
153	static inline void play_dead(void)	153	static inline void play_dead(void)
154	{	154	{
155	/* This must be done before dead CPU ack */	155	/* This must be done before dead CPU ack */
156	cpu_exit_clear();	156	cpu_exit_clear();
157	wbinvd();	157	wbinvd();
158	mb();	158	mb();
159	/* Ack it */	159	/* Ack it */
160	__get_cpu_var(cpu_state) = CPU_DEAD;	160	__get_cpu_var(cpu_state) = CPU_DEAD;
161		161
162	/*	162	/*
163	* With physical CPU hotplug, we should halt the cpu	163	* With physical CPU hotplug, we should halt the cpu
164	*/	164	*/
165	local_irq_disable();	165	local_irq_disable();
166	while (1)	166	while (1)
167	__asm__ __volatile__("hlt":::"memory");	167	halt();
168	}	168	}
169	#else	169	#else
170	static inline void play_dead(void)	170	static inline void play_dead(void)
171	{	171	{
172	BUG();	172	BUG();
173	}	173	}
174	#endif /* CONFIG_HOTPLUG_CPU */	174	#endif /* CONFIG_HOTPLUG_CPU */
175		175
176	/*	176	/*
177	* The idle thread. There's no useful work to be	177	* The idle thread. There's no useful work to be
178	* done, so just try to conserve power and have a	178	* done, so just try to conserve power and have a
179	* low exit latency (ie sit in a loop waiting for	179	* low exit latency (ie sit in a loop waiting for
180	* somebody to say that they'd like to reschedule)	180	* somebody to say that they'd like to reschedule)
181	*/	181	*/
182	void cpu_idle(void)	182	void cpu_idle(void)
183	{	183	{
184	int cpu = raw_smp_processor_id();	184	int cpu = raw_smp_processor_id();
185		185
186	/* endless idle loop with no priority at all */	186	/* endless idle loop with no priority at all */
187	while (1) {	187	while (1) {
188	while (!need_resched()) {	188	while (!need_resched()) {
189	void (*idle)(void);	189	void (*idle)(void);
190		190
191	if (__get_cpu_var(cpu_idle_state))	191	if (__get_cpu_var(cpu_idle_state))
192	__get_cpu_var(cpu_idle_state) = 0;	192	__get_cpu_var(cpu_idle_state) = 0;
193		193
194	rmb();	194	rmb();
195	idle = pm_idle;	195	idle = pm_idle;
196		196
197	if (!idle)	197	if (!idle)
198	idle = default_idle;	198	idle = default_idle;
199		199
200	if (cpu_is_offline(cpu))	200	if (cpu_is_offline(cpu))
201	play_dead();	201	play_dead();
202		202
203	__get_cpu_var(irq_stat).idle_timestamp = jiffies;	203	__get_cpu_var(irq_stat).idle_timestamp = jiffies;
204	idle();	204	idle();
205	}	205	}
206	schedule();	206	schedule();
207	}	207	}
208	}	208	}
209		209
210	void cpu_idle_wait(void)	210	void cpu_idle_wait(void)
211	{	211	{
212	unsigned int cpu, this_cpu = get_cpu();	212	unsigned int cpu, this_cpu = get_cpu();
213	cpumask_t map;	213	cpumask_t map;
214		214
215	set_cpus_allowed(current, cpumask_of_cpu(this_cpu));	215	set_cpus_allowed(current, cpumask_of_cpu(this_cpu));
216	put_cpu();	216	put_cpu();
217		217
218	cpus_clear(map);	218	cpus_clear(map);
219	for_each_online_cpu(cpu) {	219	for_each_online_cpu(cpu) {
220	per_cpu(cpu_idle_state, cpu) = 1;	220	per_cpu(cpu_idle_state, cpu) = 1;
221	cpu_set(cpu, map);	221	cpu_set(cpu, map);
222	}	222	}
223		223
224	__get_cpu_var(cpu_idle_state) = 0;	224	__get_cpu_var(cpu_idle_state) = 0;
225		225
226	wmb();	226	wmb();
227	do {	227	do {
228	ssleep(1);	228	ssleep(1);
229	for_each_online_cpu(cpu) {	229	for_each_online_cpu(cpu) {
230	if (cpu_isset(cpu, map) && !per_cpu(cpu_idle_state, cpu))	230	if (cpu_isset(cpu, map) && !per_cpu(cpu_idle_state, cpu))
231	cpu_clear(cpu, map);	231	cpu_clear(cpu, map);
232	}	232	}
233	cpus_and(map, map, cpu_online_map);	233	cpus_and(map, map, cpu_online_map);
234	} while (!cpus_empty(map));	234	} while (!cpus_empty(map));
235	}	235	}
236	EXPORT_SYMBOL_GPL(cpu_idle_wait);	236	EXPORT_SYMBOL_GPL(cpu_idle_wait);
237		237
238	/*	238	/*
239	* This uses new MONITOR/MWAIT instructions on P4 processors with PNI,	239	* This uses new MONITOR/MWAIT instructions on P4 processors with PNI,
240	* which can obviate IPI to trigger checking of need_resched.	240	* which can obviate IPI to trigger checking of need_resched.
241	* We execute MONITOR against need_resched and enter optimized wait state	241	* We execute MONITOR against need_resched and enter optimized wait state
242	* through MWAIT. Whenever someone changes need_resched, we would be woken	242	* through MWAIT. Whenever someone changes need_resched, we would be woken
243	* up from MWAIT (without an IPI).	243	* up from MWAIT (without an IPI).
244	*/	244	*/
245	static void mwait_idle(void)	245	static void mwait_idle(void)
246	{	246	{
247	local_irq_enable();	247	local_irq_enable();
248		248
249	if (!need_resched()) {	249	if (!need_resched()) {
250	set_thread_flag(TIF_POLLING_NRFLAG);	250	set_thread_flag(TIF_POLLING_NRFLAG);
251	do {	251	do {
252	__monitor((void *)&current_thread_info()->flags, 0, 0);	252	__monitor((void *)&current_thread_info()->flags, 0, 0);
253	if (need_resched())	253	if (need_resched())
254	break;	254	break;
255	__mwait(0, 0);	255	__mwait(0, 0);
256	} while (!need_resched());	256	} while (!need_resched());
257	clear_thread_flag(TIF_POLLING_NRFLAG);	257	clear_thread_flag(TIF_POLLING_NRFLAG);
258	}	258	}
259	}	259	}
260		260
261	void __devinit select_idle_routine(const struct cpuinfo_x86 *c)	261	void __devinit select_idle_routine(const struct cpuinfo_x86 *c)
262	{	262	{
263	if (cpu_has(c, X86_FEATURE_MWAIT)) {	263	if (cpu_has(c, X86_FEATURE_MWAIT)) {
264	printk("monitor/mwait feature present.\n");	264	printk("monitor/mwait feature present.\n");
265	/*	265	/*
266	* Skip, if setup has overridden idle.	266	* Skip, if setup has overridden idle.
267	* One CPU supports mwait => All CPUs supports mwait	267	* One CPU supports mwait => All CPUs supports mwait
268	*/	268	*/
269	if (!pm_idle) {	269	if (!pm_idle) {
270	printk("using mwait in idle threads.\n");	270	printk("using mwait in idle threads.\n");
271	pm_idle = mwait_idle;	271	pm_idle = mwait_idle;
272	}	272	}
273	}	273	}
274	}	274	}
275		275
276	static int __init idle_setup (char *str)	276	static int __init idle_setup (char *str)
277	{	277	{
278	if (!strncmp(str, "poll", 4)) {	278	if (!strncmp(str, "poll", 4)) {
279	printk("using polling idle threads.\n");	279	printk("using polling idle threads.\n");
280	pm_idle = poll_idle;	280	pm_idle = poll_idle;
281	#ifdef CONFIG_X86_SMP	281	#ifdef CONFIG_X86_SMP
282	if (smp_num_siblings > 1)	282	if (smp_num_siblings > 1)
283	printk("WARNING: polling idle and HT enabled, performance may degrade.\n");	283	printk("WARNING: polling idle and HT enabled, performance may degrade.\n");
284	#endif	284	#endif
285	} else if (!strncmp(str, "halt", 4)) {	285	} else if (!strncmp(str, "halt", 4)) {
286	printk("using halt in idle threads.\n");	286	printk("using halt in idle threads.\n");
287	pm_idle = default_idle;	287	pm_idle = default_idle;
288	}	288	}
289		289
290	boot_option_idle_override = 1;	290	boot_option_idle_override = 1;
291	return 1;	291	return 1;
292	}	292	}
293		293
294	__setup("idle=", idle_setup);	294	__setup("idle=", idle_setup);
295		295
296	void show_regs(struct pt_regs * regs)	296	void show_regs(struct pt_regs * regs)
297	{	297	{
298	unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L;	298	unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L;
299		299
300	printk("\n");	300	printk("\n");
301	printk("Pid: %d, comm: %20s\n", current->pid, current->comm);	301	printk("Pid: %d, comm: %20s\n", current->pid, current->comm);
302	printk("EIP: %04x:[<%08lx>] CPU: %d\n",0xffff & regs->xcs,regs->eip, smp_processor_id());	302	printk("EIP: %04x:[<%08lx>] CPU: %d\n",0xffff & regs->xcs,regs->eip, smp_processor_id());
303	print_symbol("EIP is at %s\n", regs->eip);	303	print_symbol("EIP is at %s\n", regs->eip);
304		304
305	if (user_mode(regs))	305	if (user_mode(regs))
306	printk(" ESP: %04x:%08lx",0xffff & regs->xss,regs->esp);	306	printk(" ESP: %04x:%08lx",0xffff & regs->xss,regs->esp);
307	printk(" EFLAGS: %08lx %s (%s)\n",	307	printk(" EFLAGS: %08lx %s (%s)\n",
308	regs->eflags, print_tainted(), system_utsname.release);	308	regs->eflags, print_tainted(), system_utsname.release);
309	printk("EAX: %08lx EBX: %08lx ECX: %08lx EDX: %08lx\n",	309	printk("EAX: %08lx EBX: %08lx ECX: %08lx EDX: %08lx\n",
310	regs->eax,regs->ebx,regs->ecx,regs->edx);	310	regs->eax,regs->ebx,regs->ecx,regs->edx);
311	printk("ESI: %08lx EDI: %08lx EBP: %08lx",	311	printk("ESI: %08lx EDI: %08lx EBP: %08lx",
312	regs->esi, regs->edi, regs->ebp);	312	regs->esi, regs->edi, regs->ebp);
313	printk(" DS: %04x ES: %04x\n",	313	printk(" DS: %04x ES: %04x\n",
314	0xffff & regs->xds,0xffff & regs->xes);	314	0xffff & regs->xds,0xffff & regs->xes);
315		315
316	cr0 = read_cr0();	316	cr0 = read_cr0();
317	cr2 = read_cr2();	317	cr2 = read_cr2();
318	cr3 = read_cr3();	318	cr3 = read_cr3();
319	if (current_cpu_data.x86 > 4) {	319	if (current_cpu_data.x86 > 4) {
320	cr4 = read_cr4();	320	cr4 = read_cr4();
321	}	321	}
322	printk("CR0: %08lx CR2: %08lx CR3: %08lx CR4: %08lx\n", cr0, cr2, cr3, cr4);	322	printk("CR0: %08lx CR2: %08lx CR3: %08lx CR4: %08lx\n", cr0, cr2, cr3, cr4);
323	show_trace(NULL, &regs->esp);	323	show_trace(NULL, &regs->esp);
324	}	324	}
325		325
326	/*	326	/*
327	* This gets run with %ebx containing the	327	* This gets run with %ebx containing the
328	* function to call, and %edx containing	328	* function to call, and %edx containing
329	* the "args".	329	* the "args".
330	*/	330	*/
331	extern void kernel_thread_helper(void);	331	extern void kernel_thread_helper(void);
332	__asm__(".section .text\n"	332	__asm__(".section .text\n"
333	".align 4\n"	333	".align 4\n"
334	"kernel_thread_helper:\n\t"	334	"kernel_thread_helper:\n\t"
335	"movl %edx,%eax\n\t"	335	"movl %edx,%eax\n\t"
336	"pushl %edx\n\t"	336	"pushl %edx\n\t"
337	"call *%ebx\n\t"	337	"call *%ebx\n\t"
338	"pushl %eax\n\t"	338	"pushl %eax\n\t"
339	"call do_exit\n"	339	"call do_exit\n"
340	".previous");	340	".previous");
341		341
342	/*	342	/*
343	* Create a kernel thread	343	* Create a kernel thread
344	*/	344	*/
345	int kernel_thread(int (fn)(void ), void * arg, unsigned long flags)	345	int kernel_thread(int (fn)(void ), void * arg, unsigned long flags)
346	{	346	{
347	struct pt_regs regs;	347	struct pt_regs regs;
348		348
349	memset(&regs, 0, sizeof(regs));	349	memset(&regs, 0, sizeof(regs));
350		350
351	regs.ebx = (unsigned long) fn;	351	regs.ebx = (unsigned long) fn;
352	regs.edx = (unsigned long) arg;	352	regs.edx = (unsigned long) arg;
353		353
354	regs.xds = __USER_DS;	354	regs.xds = __USER_DS;
355	regs.xes = __USER_DS;	355	regs.xes = __USER_DS;
356	regs.orig_eax = -1;	356	regs.orig_eax = -1;
357	regs.eip = (unsigned long) kernel_thread_helper;	357	regs.eip = (unsigned long) kernel_thread_helper;
358	regs.xcs = __KERNEL_CS;	358	regs.xcs = __KERNEL_CS;
359	regs.eflags = X86_EFLAGS_IF \| X86_EFLAGS_SF \| X86_EFLAGS_PF \| 0x2;	359	regs.eflags = X86_EFLAGS_IF \| X86_EFLAGS_SF \| X86_EFLAGS_PF \| 0x2;
360		360
361	/* Ok, create the new process.. */	361	/* Ok, create the new process.. */
362	return do_fork(flags \| CLONE_VM \| CLONE_UNTRACED, 0, &regs, 0, NULL, NULL);	362	return do_fork(flags \| CLONE_VM \| CLONE_UNTRACED, 0, &regs, 0, NULL, NULL);
363	}	363	}
364	EXPORT_SYMBOL(kernel_thread);	364	EXPORT_SYMBOL(kernel_thread);
365		365
366	/*	366	/*
367	* Free current thread data structures etc..	367	* Free current thread data structures etc..
368	*/	368	*/
369	void exit_thread(void)	369	void exit_thread(void)
370	{	370	{
371	struct task_struct *tsk = current;	371	struct task_struct *tsk = current;
372	struct thread_struct *t = &tsk->thread;	372	struct thread_struct *t = &tsk->thread;
373		373
374	/*	374	/*
375	* Remove function-return probe instances associated with this task	375	* Remove function-return probe instances associated with this task
376	* and put them back on the free list. Do not insert an exit probe for	376	* and put them back on the free list. Do not insert an exit probe for
377	* this function, it will be disabled by kprobe_flush_task if you do.	377	* this function, it will be disabled by kprobe_flush_task if you do.
378	*/	378	*/
379	kprobe_flush_task(tsk);	379	kprobe_flush_task(tsk);
380		380
381	/* The process may have allocated an io port bitmap... nuke it. */	381	/* The process may have allocated an io port bitmap... nuke it. */
382	if (unlikely(NULL != t->io_bitmap_ptr)) {	382	if (unlikely(NULL != t->io_bitmap_ptr)) {
383	int cpu = get_cpu();	383	int cpu = get_cpu();
384	struct tss_struct *tss = &per_cpu(init_tss, cpu);	384	struct tss_struct *tss = &per_cpu(init_tss, cpu);
385		385
386	kfree(t->io_bitmap_ptr);	386	kfree(t->io_bitmap_ptr);
387	t->io_bitmap_ptr = NULL;	387	t->io_bitmap_ptr = NULL;
388	/*	388	/*
389	* Careful, clear this in the TSS too:	389	* Careful, clear this in the TSS too:
390	*/	390	*/
391	memset(tss->io_bitmap, 0xff, tss->io_bitmap_max);	391	memset(tss->io_bitmap, 0xff, tss->io_bitmap_max);
392	t->io_bitmap_max = 0;	392	t->io_bitmap_max = 0;
393	tss->io_bitmap_owner = NULL;	393	tss->io_bitmap_owner = NULL;
394	tss->io_bitmap_max = 0;	394	tss->io_bitmap_max = 0;
395	tss->io_bitmap_base = INVALID_IO_BITMAP_OFFSET;	395	tss->io_bitmap_base = INVALID_IO_BITMAP_OFFSET;
396	put_cpu();	396	put_cpu();
397	}	397	}
398	}	398	}
399		399
400	void flush_thread(void)	400	void flush_thread(void)
401	{	401	{
402	struct task_struct *tsk = current;	402	struct task_struct *tsk = current;
403		403
404	/*	404	/*
405	* Remove function-return probe instances associated with this task	405	* Remove function-return probe instances associated with this task
406	* and put them back on the free list. Do not insert an exit probe for	406	* and put them back on the free list. Do not insert an exit probe for
407	* this function, it will be disabled by kprobe_flush_task if you do.	407	* this function, it will be disabled by kprobe_flush_task if you do.
408	*/	408	*/
409	kprobe_flush_task(tsk);	409	kprobe_flush_task(tsk);
410		410
411	memset(tsk->thread.debugreg, 0, sizeof(unsigned long)*8);	411	memset(tsk->thread.debugreg, 0, sizeof(unsigned long)*8);
412	memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));	412	memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
413	/*	413	/*
414	* Forget coprocessor state..	414	* Forget coprocessor state..
415	*/	415	*/
416	clear_fpu(tsk);	416	clear_fpu(tsk);
417	clear_used_math();	417	clear_used_math();
418	}	418	}
419		419
420	void release_thread(struct task_struct *dead_task)	420	void release_thread(struct task_struct *dead_task)
421	{	421	{
422	if (dead_task->mm) {	422	if (dead_task->mm) {
423	// temporary debugging check	423	// temporary debugging check
424	if (dead_task->mm->context.size) {	424	if (dead_task->mm->context.size) {
425	printk("WARNING: dead process %8s still has LDT? <%p/%d>\n",	425	printk("WARNING: dead process %8s still has LDT? <%p/%d>\n",
426	dead_task->comm,	426	dead_task->comm,
427	dead_task->mm->context.ldt,	427	dead_task->mm->context.ldt,
428	dead_task->mm->context.size);	428	dead_task->mm->context.size);
429	BUG();	429	BUG();
430	}	430	}
431	}	431	}
432		432
433	release_vm86_irqs(dead_task);	433	release_vm86_irqs(dead_task);
434	}	434	}
435		435
436	/*	436	/*
437	* This gets called before we allocate a new thread and copy	437	* This gets called before we allocate a new thread and copy
438	* the current task into it.	438	* the current task into it.
439	*/	439	*/
440	void prepare_to_copy(struct task_struct *tsk)	440	void prepare_to_copy(struct task_struct *tsk)
441	{	441	{
442	unlazy_fpu(tsk);	442	unlazy_fpu(tsk);
443	}	443	}
444		444
445	int copy_thread(int nr, unsigned long clone_flags, unsigned long esp,	445	int copy_thread(int nr, unsigned long clone_flags, unsigned long esp,
446	unsigned long unused,	446	unsigned long unused,
447	struct task_struct * p, struct pt_regs * regs)	447	struct task_struct * p, struct pt_regs * regs)
448	{	448	{
449	struct pt_regs * childregs;	449	struct pt_regs * childregs;
450	struct task_struct *tsk;	450	struct task_struct *tsk;
451	int err;	451	int err;
452		452
453	childregs = ((struct pt_regs *) (THREAD_SIZE + (unsigned long) p->thread_info)) - 1;	453	childregs = ((struct pt_regs *) (THREAD_SIZE + (unsigned long) p->thread_info)) - 1;
454	/*	454	/*
455	* The below -8 is to reserve 8 bytes on top of the ring0 stack.	455	* The below -8 is to reserve 8 bytes on top of the ring0 stack.
456	* This is necessary to guarantee that the entire "struct pt_regs"	456	* This is necessary to guarantee that the entire "struct pt_regs"
457	* is accessable even if the CPU haven't stored the SS/ESP registers	457	* is accessable even if the CPU haven't stored the SS/ESP registers
458	* on the stack (interrupt gate does not save these registers	458	* on the stack (interrupt gate does not save these registers
459	* when switching to the same priv ring).	459	* when switching to the same priv ring).
460	* Therefore beware: accessing the xss/esp fields of the	460	* Therefore beware: accessing the xss/esp fields of the
461	* "struct pt_regs" is possible, but they may contain the	461	* "struct pt_regs" is possible, but they may contain the
462	* completely wrong values.	462	* completely wrong values.
463	*/	463	*/
464	childregs = (struct pt_regs *) ((unsigned long) childregs - 8);	464	childregs = (struct pt_regs *) ((unsigned long) childregs - 8);
465	childregs = regs;	465	childregs = regs;
466	childregs->eax = 0;	466	childregs->eax = 0;
467	childregs->esp = esp;	467	childregs->esp = esp;
468		468
469	p->thread.esp = (unsigned long) childregs;	469	p->thread.esp = (unsigned long) childregs;
470	p->thread.esp0 = (unsigned long) (childregs+1);	470	p->thread.esp0 = (unsigned long) (childregs+1);
471		471
472	p->thread.eip = (unsigned long) ret_from_fork;	472	p->thread.eip = (unsigned long) ret_from_fork;
473		473
474	savesegment(fs,p->thread.fs);	474	savesegment(fs,p->thread.fs);
475	savesegment(gs,p->thread.gs);	475	savesegment(gs,p->thread.gs);
476		476
477	tsk = current;	477	tsk = current;
478	if (unlikely(NULL != tsk->thread.io_bitmap_ptr)) {	478	if (unlikely(NULL != tsk->thread.io_bitmap_ptr)) {
479	p->thread.io_bitmap_ptr = kmalloc(IO_BITMAP_BYTES, GFP_KERNEL);	479	p->thread.io_bitmap_ptr = kmalloc(IO_BITMAP_BYTES, GFP_KERNEL);
480	if (!p->thread.io_bitmap_ptr) {	480	if (!p->thread.io_bitmap_ptr) {
481	p->thread.io_bitmap_max = 0;	481	p->thread.io_bitmap_max = 0;
482	return -ENOMEM;	482	return -ENOMEM;
483	}	483	}
484	memcpy(p->thread.io_bitmap_ptr, tsk->thread.io_bitmap_ptr,	484	memcpy(p->thread.io_bitmap_ptr, tsk->thread.io_bitmap_ptr,
485	IO_BITMAP_BYTES);	485	IO_BITMAP_BYTES);
486	}	486	}
487		487
488	/*	488	/*
489	* Set a new TLS for the child thread?	489	* Set a new TLS for the child thread?
490	*/	490	*/
491	if (clone_flags & CLONE_SETTLS) {	491	if (clone_flags & CLONE_SETTLS) {
492	struct desc_struct *desc;	492	struct desc_struct *desc;
493	struct user_desc info;	493	struct user_desc info;
494	int idx;	494	int idx;
495		495
496	err = -EFAULT;	496	err = -EFAULT;
497	if (copy_from_user(&info, (void __user *)childregs->esi, sizeof(info)))	497	if (copy_from_user(&info, (void __user *)childregs->esi, sizeof(info)))
498	goto out;	498	goto out;
499	err = -EINVAL;	499	err = -EINVAL;
500	if (LDT_empty(&info))	500	if (LDT_empty(&info))
501	goto out;	501	goto out;
502		502
503	idx = info.entry_number;	503	idx = info.entry_number;
504	if (idx < GDT_ENTRY_TLS_MIN \|\| idx > GDT_ENTRY_TLS_MAX)	504	if (idx < GDT_ENTRY_TLS_MIN \|\| idx > GDT_ENTRY_TLS_MAX)
505	goto out;	505	goto out;
506		506
507	desc = p->thread.tls_array + idx - GDT_ENTRY_TLS_MIN;	507	desc = p->thread.tls_array + idx - GDT_ENTRY_TLS_MIN;
508	desc->a = LDT_entry_a(&info);	508	desc->a = LDT_entry_a(&info);
509	desc->b = LDT_entry_b(&info);	509	desc->b = LDT_entry_b(&info);
510	}	510	}
511		511
512	err = 0;	512	err = 0;
513	out:	513	out:
514	if (err && p->thread.io_bitmap_ptr) {	514	if (err && p->thread.io_bitmap_ptr) {
515	kfree(p->thread.io_bitmap_ptr);	515	kfree(p->thread.io_bitmap_ptr);
516	p->thread.io_bitmap_max = 0;	516	p->thread.io_bitmap_max = 0;
517	}	517	}
518	return err;	518	return err;
519	}	519	}
520		520
521	/*	521	/*
522	* fill in the user structure for a core dump..	522	* fill in the user structure for a core dump..
523	*/	523	*/
524	void dump_thread(struct pt_regs * regs, struct user * dump)	524	void dump_thread(struct pt_regs * regs, struct user * dump)
525	{	525	{
526	int i;	526	int i;
527		527
528	/* changed the size calculations - should hopefully work better. lbt */	528	/* changed the size calculations - should hopefully work better. lbt */
529	dump->magic = CMAGIC;	529	dump->magic = CMAGIC;
530	dump->start_code = 0;	530	dump->start_code = 0;
531	dump->start_stack = regs->esp & ~(PAGE_SIZE - 1);	531	dump->start_stack = regs->esp & ~(PAGE_SIZE - 1);
532	dump->u_tsize = ((unsigned long) current->mm->end_code) >> PAGE_SHIFT;	532	dump->u_tsize = ((unsigned long) current->mm->end_code) >> PAGE_SHIFT;
533	dump->u_dsize = ((unsigned long) (current->mm->brk + (PAGE_SIZE-1))) >> PAGE_SHIFT;	533	dump->u_dsize = ((unsigned long) (current->mm->brk + (PAGE_SIZE-1))) >> PAGE_SHIFT;
534	dump->u_dsize -= dump->u_tsize;	534	dump->u_dsize -= dump->u_tsize;
535	dump->u_ssize = 0;	535	dump->u_ssize = 0;
536	for (i = 0; i < 8; i++)	536	for (i = 0; i < 8; i++)
537	dump->u_debugreg[i] = current->thread.debugreg[i];	537	dump->u_debugreg[i] = current->thread.debugreg[i];
538		538
539	if (dump->start_stack < TASK_SIZE)	539	if (dump->start_stack < TASK_SIZE)
540	dump->u_ssize = ((unsigned long) (TASK_SIZE - dump->start_stack)) >> PAGE_SHIFT;	540	dump->u_ssize = ((unsigned long) (TASK_SIZE - dump->start_stack)) >> PAGE_SHIFT;
541		541
542	dump->regs.ebx = regs->ebx;	542	dump->regs.ebx = regs->ebx;
543	dump->regs.ecx = regs->ecx;	543	dump->regs.ecx = regs->ecx;
544	dump->regs.edx = regs->edx;	544	dump->regs.edx = regs->edx;
545	dump->regs.esi = regs->esi;	545	dump->regs.esi = regs->esi;
546	dump->regs.edi = regs->edi;	546	dump->regs.edi = regs->edi;
547	dump->regs.ebp = regs->ebp;	547	dump->regs.ebp = regs->ebp;
548	dump->regs.eax = regs->eax;	548	dump->regs.eax = regs->eax;
549	dump->regs.ds = regs->xds;	549	dump->regs.ds = regs->xds;
550	dump->regs.es = regs->xes;	550	dump->regs.es = regs->xes;
551	savesegment(fs,dump->regs.fs);	551	savesegment(fs,dump->regs.fs);
552	savesegment(gs,dump->regs.gs);	552	savesegment(gs,dump->regs.gs);
553	dump->regs.orig_eax = regs->orig_eax;	553	dump->regs.orig_eax = regs->orig_eax;
554	dump->regs.eip = regs->eip;	554	dump->regs.eip = regs->eip;
555	dump->regs.cs = regs->xcs;	555	dump->regs.cs = regs->xcs;
556	dump->regs.eflags = regs->eflags;	556	dump->regs.eflags = regs->eflags;
557	dump->regs.esp = regs->esp;	557	dump->regs.esp = regs->esp;
558	dump->regs.ss = regs->xss;	558	dump->regs.ss = regs->xss;
559		559
560	dump->u_fpvalid = dump_fpu (regs, &dump->i387);	560	dump->u_fpvalid = dump_fpu (regs, &dump->i387);
561	}	561	}
562	EXPORT_SYMBOL(dump_thread);	562	EXPORT_SYMBOL(dump_thread);
563		563
564	/*	564	/*
565	* Capture the user space registers if the task is not running (in user space)	565	* Capture the user space registers if the task is not running (in user space)
566	*/	566	*/
567	int dump_task_regs(struct task_struct tsk, elf_gregset_t regs)	567	int dump_task_regs(struct task_struct tsk, elf_gregset_t regs)
568	{	568	{
569	struct pt_regs ptregs;	569	struct pt_regs ptregs;
570		570
571	ptregs = (struct pt_regs )	571	ptregs = (struct pt_regs )
572	((unsigned long)tsk->thread_info+THREAD_SIZE - sizeof(ptregs));	572	((unsigned long)tsk->thread_info+THREAD_SIZE - sizeof(ptregs));
573	ptregs.xcs &= 0xffff;	573	ptregs.xcs &= 0xffff;
574	ptregs.xds &= 0xffff;	574	ptregs.xds &= 0xffff;
575	ptregs.xes &= 0xffff;	575	ptregs.xes &= 0xffff;
576	ptregs.xss &= 0xffff;	576	ptregs.xss &= 0xffff;
577		577
578	elf_core_copy_regs(regs, &ptregs);	578	elf_core_copy_regs(regs, &ptregs);
579		579
580	return 1;	580	return 1;
581	}	581	}
582		582
583	static inline void	583	static inline void
584	handle_io_bitmap(struct thread_struct next, struct tss_struct tss)	584	handle_io_bitmap(struct thread_struct next, struct tss_struct tss)
585	{	585	{
586	if (!next->io_bitmap_ptr) {	586	if (!next->io_bitmap_ptr) {
587	/*	587	/*
588	* Disable the bitmap via an invalid offset. We still cache	588	* Disable the bitmap via an invalid offset. We still cache
589	* the previous bitmap owner and the IO bitmap contents:	589	* the previous bitmap owner and the IO bitmap contents:
590	*/	590	*/
591	tss->io_bitmap_base = INVALID_IO_BITMAP_OFFSET;	591	tss->io_bitmap_base = INVALID_IO_BITMAP_OFFSET;
592	return;	592	return;
593	}	593	}
594	if (likely(next == tss->io_bitmap_owner)) {	594	if (likely(next == tss->io_bitmap_owner)) {
595	/*	595	/*
596	* Previous owner of the bitmap (hence the bitmap content)	596	* Previous owner of the bitmap (hence the bitmap content)
597	* matches the next task, we dont have to do anything but	597	* matches the next task, we dont have to do anything but
598	* to set a valid offset in the TSS:	598	* to set a valid offset in the TSS:
599	*/	599	*/
600	tss->io_bitmap_base = IO_BITMAP_OFFSET;	600	tss->io_bitmap_base = IO_BITMAP_OFFSET;
601	return;	601	return;
602	}	602	}
603	/*	603	/*
604	* Lazy TSS's I/O bitmap copy. We set an invalid offset here	604	* Lazy TSS's I/O bitmap copy. We set an invalid offset here
605	* and we let the task to get a GPF in case an I/O instruction	605	* and we let the task to get a GPF in case an I/O instruction
606	* is performed. The handler of the GPF will verify that the	606	* is performed. The handler of the GPF will verify that the
607	* faulting task has a valid I/O bitmap and, it true, does the	607	* faulting task has a valid I/O bitmap and, it true, does the
608	* real copy and restart the instruction. This will save us	608	* real copy and restart the instruction. This will save us
609	* redundant copies when the currently switched task does not	609	* redundant copies when the currently switched task does not
610	* perform any I/O during its timeslice.	610	* perform any I/O during its timeslice.
611	*/	611	*/
612	tss->io_bitmap_base = INVALID_IO_BITMAP_OFFSET_LAZY;	612	tss->io_bitmap_base = INVALID_IO_BITMAP_OFFSET_LAZY;
613	}	613	}
614		614
615	/*	615	/*
616	* This function selects if the context switch from prev to next	616	* This function selects if the context switch from prev to next
617	* has to tweak the TSC disable bit in the cr4.	617	* has to tweak the TSC disable bit in the cr4.
618	*/	618	*/
619	static inline void disable_tsc(struct task_struct *prev_p,	619	static inline void disable_tsc(struct task_struct *prev_p,
620	struct task_struct *next_p)	620	struct task_struct *next_p)
621	{	621	{
622	struct thread_info prev, next;	622	struct thread_info prev, next;
623		623
624	/*	624	/*
625	* gcc should eliminate the ->thread_info dereference if	625	* gcc should eliminate the ->thread_info dereference if
626	* has_secure_computing returns 0 at compile time (SECCOMP=n).	626	* has_secure_computing returns 0 at compile time (SECCOMP=n).
627	*/	627	*/
628	prev = prev_p->thread_info;	628	prev = prev_p->thread_info;
629	next = next_p->thread_info;	629	next = next_p->thread_info;
630		630
631	if (has_secure_computing(prev) \|\| has_secure_computing(next)) {	631	if (has_secure_computing(prev) \|\| has_secure_computing(next)) {
632	/* slow path here */	632	/* slow path here */
633	if (has_secure_computing(prev) &&	633	if (has_secure_computing(prev) &&
634	!has_secure_computing(next)) {	634	!has_secure_computing(next)) {
635	write_cr4(read_cr4() & ~X86_CR4_TSD);	635	write_cr4(read_cr4() & ~X86_CR4_TSD);
636	} else if (!has_secure_computing(prev) &&	636	} else if (!has_secure_computing(prev) &&
637	has_secure_computing(next))	637	has_secure_computing(next))
638	write_cr4(read_cr4() \| X86_CR4_TSD);	638	write_cr4(read_cr4() \| X86_CR4_TSD);
639	}	639	}
640	}	640	}
641		641
642	/*	642	/*
643	* switch_to(x,yn) should switch tasks from x to y.	643	* switch_to(x,yn) should switch tasks from x to y.
644	*	644	*
645	* We fsave/fwait so that an exception goes off at the right time	645	* We fsave/fwait so that an exception goes off at the right time
646	* (as a call from the fsave or fwait in effect) rather than to	646	* (as a call from the fsave or fwait in effect) rather than to
647	* the wrong process. Lazy FP saving no longer makes any sense	647	* the wrong process. Lazy FP saving no longer makes any sense
648	* with modern CPU's, and this simplifies a lot of things (SMP	648	* with modern CPU's, and this simplifies a lot of things (SMP
649	* and UP become the same).	649	* and UP become the same).
650	*	650	*
651	* NOTE! We used to use the x86 hardware context switching. The	651	* NOTE! We used to use the x86 hardware context switching. The
652	* reason for not using it any more becomes apparent when you	652	* reason for not using it any more becomes apparent when you
653	* try to recover gracefully from saved state that is no longer	653	* try to recover gracefully from saved state that is no longer
654	* valid (stale segment register values in particular). With the	654	* valid (stale segment register values in particular). With the
655	* hardware task-switch, there is no way to fix up bad state in	655	* hardware task-switch, there is no way to fix up bad state in
656	* a reasonable manner.	656	* a reasonable manner.
657	*	657	*
658	* The fact that Intel documents the hardware task-switching to	658	* The fact that Intel documents the hardware task-switching to
659	* be slow is a fairly red herring - this code is not noticeably	659	* be slow is a fairly red herring - this code is not noticeably
660	* faster. However, there _is_ some room for improvement here,	660	* faster. However, there _is_ some room for improvement here,
661	* so the performance issues may eventually be a valid point.	661	* so the performance issues may eventually be a valid point.
662	* More important, however, is the fact that this allows us much	662	* More important, however, is the fact that this allows us much
663	* more flexibility.	663	* more flexibility.
664	*	664	*
665	* The return value (in %eax) will be the "prev" task after	665	* The return value (in %eax) will be the "prev" task after
666	* the task-switch, and shows up in ret_from_fork in entry.S,	666	* the task-switch, and shows up in ret_from_fork in entry.S,
667	* for example.	667	* for example.
668	*/	668	*/
669	struct task_struct fastcall * __switch_to(struct task_struct prev_p, struct task_struct next_p)	669	struct task_struct fastcall * __switch_to(struct task_struct prev_p, struct task_struct next_p)
670	{	670	{
671	struct thread_struct *prev = &prev_p->thread,	671	struct thread_struct *prev = &prev_p->thread,
672	*next = &next_p->thread;	672	*next = &next_p->thread;
673	int cpu = smp_processor_id();	673	int cpu = smp_processor_id();
674	struct tss_struct *tss = &per_cpu(init_tss, cpu);	674	struct tss_struct *tss = &per_cpu(init_tss, cpu);
675		675
676	/* never put a printk in __switch_to... printk() calls wake_up() indirectly /	676	/* never put a printk in __switch_to... printk() calls wake_up() indirectly /
677		677
678	__unlazy_fpu(prev_p);	678	__unlazy_fpu(prev_p);
679		679
680	/*	680	/*
681	* Reload esp0.	681	* Reload esp0.
682	*/	682	*/
683	load_esp0(tss, next);	683	load_esp0(tss, next);
684		684
685	/*	685	/*
686	* Save away %fs and %gs. No need to save %es and %ds, as	686	* Save away %fs and %gs. No need to save %es and %ds, as
687	* those are always kernel segments while inside the kernel.	687	* those are always kernel segments while inside the kernel.
688	* Doing this before setting the new TLS descriptors avoids	688	* Doing this before setting the new TLS descriptors avoids
689	* the situation where we temporarily have non-reloadable	689	* the situation where we temporarily have non-reloadable
690	* segments in %fs and %gs. This could be an issue if the	690	* segments in %fs and %gs. This could be an issue if the
691	* NMI handler ever used %fs or %gs (it does not today), or	691	* NMI handler ever used %fs or %gs (it does not today), or
692	* if the kernel is running inside of a hypervisor layer.	692	* if the kernel is running inside of a hypervisor layer.
693	*/	693	*/
694	savesegment(fs, prev->fs);	694	savesegment(fs, prev->fs);
695	savesegment(gs, prev->gs);	695	savesegment(gs, prev->gs);
696		696
697	/*	697	/*
698	* Load the per-thread Thread-Local Storage descriptor.	698	* Load the per-thread Thread-Local Storage descriptor.
699	*/	699	*/
700	load_TLS(next, cpu);	700	load_TLS(next, cpu);
701		701
702	/*	702	/*
703	* Restore %fs and %gs if needed.	703	* Restore %fs and %gs if needed.
704	*	704	*
705	* Glibc normally makes %fs be zero, and %gs is one of	705	* Glibc normally makes %fs be zero, and %gs is one of
706	* the TLS segments.	706	* the TLS segments.
707	*/	707	*/
708	if (unlikely(prev->fs \| next->fs))	708	if (unlikely(prev->fs \| next->fs))
709	loadsegment(fs, next->fs);	709	loadsegment(fs, next->fs);
710		710
711	if (prev->gs \| next->gs)	711	if (prev->gs \| next->gs)
712	loadsegment(gs, next->gs);	712	loadsegment(gs, next->gs);
713		713
714	/*	714	/*
715	* Now maybe reload the debug registers	715	* Now maybe reload the debug registers
716	*/	716	*/
717	if (unlikely(next->debugreg[7])) {	717	if (unlikely(next->debugreg[7])) {
718	set_debugreg(next->debugreg[0], 0);	718	set_debugreg(next->debugreg[0], 0);
719	set_debugreg(next->debugreg[1], 1);	719	set_debugreg(next->debugreg[1], 1);
720	set_debugreg(next->debugreg[2], 2);	720	set_debugreg(next->debugreg[2], 2);
721	set_debugreg(next->debugreg[3], 3);	721	set_debugreg(next->debugreg[3], 3);
722	/* no 4 and 5 */	722	/* no 4 and 5 */
723	set_debugreg(next->debugreg[6], 6);	723	set_debugreg(next->debugreg[6], 6);
724	set_debugreg(next->debugreg[7], 7);	724	set_debugreg(next->debugreg[7], 7);
725	}	725	}
726		726
727	if (unlikely(prev->io_bitmap_ptr \|\| next->io_bitmap_ptr))	727	if (unlikely(prev->io_bitmap_ptr \|\| next->io_bitmap_ptr))
728	handle_io_bitmap(next, tss);	728	handle_io_bitmap(next, tss);
729		729
730	disable_tsc(prev_p, next_p);	730	disable_tsc(prev_p, next_p);
731		731
732	return prev_p;	732	return prev_p;
733	}	733	}
734		734
735	asmlinkage int sys_fork(struct pt_regs regs)	735	asmlinkage int sys_fork(struct pt_regs regs)
736	{	736	{
737	return do_fork(SIGCHLD, regs.esp, &regs, 0, NULL, NULL);	737	return do_fork(SIGCHLD, regs.esp, &regs, 0, NULL, NULL);
738	}	738	}
739		739
740	asmlinkage int sys_clone(struct pt_regs regs)	740	asmlinkage int sys_clone(struct pt_regs regs)
741	{	741	{
742	unsigned long clone_flags;	742	unsigned long clone_flags;
743	unsigned long newsp;	743	unsigned long newsp;
744	int __user parent_tidptr, child_tidptr;	744	int __user parent_tidptr, child_tidptr;
745		745
746	clone_flags = regs.ebx;	746	clone_flags = regs.ebx;
747	newsp = regs.ecx;	747	newsp = regs.ecx;
748	parent_tidptr = (int __user *)regs.edx;	748	parent_tidptr = (int __user *)regs.edx;
749	child_tidptr = (int __user *)regs.edi;	749	child_tidptr = (int __user *)regs.edi;
750	if (!newsp)	750	if (!newsp)
751	newsp = regs.esp;	751	newsp = regs.esp;
752	return do_fork(clone_flags, newsp, &regs, 0, parent_tidptr, child_tidptr);	752	return do_fork(clone_flags, newsp, &regs, 0, parent_tidptr, child_tidptr);
753	}	753	}
754		754
755	/*	755	/*
756	* This is trivial, and on the face of it looks like it	756	* This is trivial, and on the face of it looks like it
757	* could equally well be done in user mode.	757	* could equally well be done in user mode.
758	*	758	*
759	* Not so, for quite unobvious reasons - register pressure.	759	* Not so, for quite unobvious reasons - register pressure.
760	* In user mode vfork() cannot have a stack frame, and if	760	* In user mode vfork() cannot have a stack frame, and if
761	* done by calling the "clone()" system call directly, you	761	* done by calling the "clone()" system call directly, you
762	* do not have enough call-clobbered registers to hold all	762	* do not have enough call-clobbered registers to hold all
763	* the information you need.	763	* the information you need.
764	*/	764	*/
765	asmlinkage int sys_vfork(struct pt_regs regs)	765	asmlinkage int sys_vfork(struct pt_regs regs)
766	{	766	{
767	return do_fork(CLONE_VFORK \| CLONE_VM \| SIGCHLD, regs.esp, &regs, 0, NULL, NULL);	767	return do_fork(CLONE_VFORK \| CLONE_VM \| SIGCHLD, regs.esp, &regs, 0, NULL, NULL);
768	}	768	}
769		769
770	/*	770	/*
771	* sys_execve() executes a new program.	771	* sys_execve() executes a new program.
772	*/	772	*/
773	asmlinkage int sys_execve(struct pt_regs regs)	773	asmlinkage int sys_execve(struct pt_regs regs)
774	{	774	{
775	int error;	775	int error;
776	char * filename;	776	char * filename;
777		777
778	filename = getname((char __user *) regs.ebx);	778	filename = getname((char __user *) regs.ebx);
779	error = PTR_ERR(filename);	779	error = PTR_ERR(filename);
780	if (IS_ERR(filename))	780	if (IS_ERR(filename))
781	goto out;	781	goto out;
782	error = do_execve(filename,	782	error = do_execve(filename,
783	(char __user * __user *) regs.ecx,	783	(char __user * __user *) regs.ecx,
784	(char __user * __user *) regs.edx,	784	(char __user * __user *) regs.edx,
785	&regs);	785	&regs);
786	if (error == 0) {	786	if (error == 0) {
787	task_lock(current);	787	task_lock(current);
788	current->ptrace &= ~PT_DTRACE;	788	current->ptrace &= ~PT_DTRACE;
789	task_unlock(current);	789	task_unlock(current);
790	/* Make sure we don't return using sysenter.. */	790	/* Make sure we don't return using sysenter.. */
791	set_thread_flag(TIF_IRET);	791	set_thread_flag(TIF_IRET);
792	}	792	}
793	putname(filename);	793	putname(filename);
794	out:	794	out:
795	return error;	795	return error;
796	}	796	}
797		797
798	#define top_esp (THREAD_SIZE - sizeof(unsigned long))	798	#define top_esp (THREAD_SIZE - sizeof(unsigned long))
799	#define top_ebp (THREAD_SIZE - 2*sizeof(unsigned long))	799	#define top_ebp (THREAD_SIZE - 2*sizeof(unsigned long))
800		800
801	unsigned long get_wchan(struct task_struct *p)	801	unsigned long get_wchan(struct task_struct *p)
802	{	802	{
803	unsigned long ebp, esp, eip;	803	unsigned long ebp, esp, eip;
804	unsigned long stack_page;	804	unsigned long stack_page;
805	int count = 0;	805	int count = 0;
806	if (!p \|\| p == current \|\| p->state == TASK_RUNNING)	806	if (!p \|\| p == current \|\| p->state == TASK_RUNNING)
807	return 0;	807	return 0;
808	stack_page = (unsigned long)p->thread_info;	808	stack_page = (unsigned long)p->thread_info;
809	esp = p->thread.esp;	809	esp = p->thread.esp;
810	if (!stack_page \|\| esp < stack_page \|\| esp > top_esp+stack_page)	810	if (!stack_page \|\| esp < stack_page \|\| esp > top_esp+stack_page)
811	return 0;	811	return 0;
812	/* include/asm-i386/system.h:switch_to() pushes ebp last. */	812	/* include/asm-i386/system.h:switch_to() pushes ebp last. */
813	ebp = (unsigned long ) esp;	813	ebp = (unsigned long ) esp;
814	do {	814	do {
815	if (ebp < stack_page \|\| ebp > top_ebp+stack_page)	815	if (ebp < stack_page \|\| ebp > top_ebp+stack_page)
816	return 0;	816	return 0;
817	eip = (unsigned long ) (ebp+4);	817	eip = (unsigned long ) (ebp+4);
818	if (!in_sched_functions(eip))	818	if (!in_sched_functions(eip))
819	return eip;	819	return eip;
820	ebp = (unsigned long ) ebp;	820	ebp = (unsigned long ) ebp;
821	} while (count++ < 16);	821	} while (count++ < 16);
822	return 0;	822	return 0;
823	}	823	}
824	EXPORT_SYMBOL(get_wchan);	824	EXPORT_SYMBOL(get_wchan);
825		825
826	/*	826	/*
827	* sys_alloc_thread_area: get a yet unused TLS descriptor index.	827	* sys_alloc_thread_area: get a yet unused TLS descriptor index.
828	*/	828	*/
829	static int get_free_idx(void)	829	static int get_free_idx(void)
830	{	830	{
831	struct thread_struct *t = &current->thread;	831	struct thread_struct *t = &current->thread;
832	int idx;	832	int idx;
833		833
834	for (idx = 0; idx < GDT_ENTRY_TLS_ENTRIES; idx++)	834	for (idx = 0; idx < GDT_ENTRY_TLS_ENTRIES; idx++)
835	if (desc_empty(t->tls_array + idx))	835	if (desc_empty(t->tls_array + idx))
836	return idx + GDT_ENTRY_TLS_MIN;	836	return idx + GDT_ENTRY_TLS_MIN;
837	return -ESRCH;	837	return -ESRCH;
838	}	838	}
839		839
840	/*	840	/*
841	* Set a given TLS descriptor:	841	* Set a given TLS descriptor:
842	*/	842	*/
843	asmlinkage int sys_set_thread_area(struct user_desc __user *u_info)	843	asmlinkage int sys_set_thread_area(struct user_desc __user *u_info)
844	{	844	{
845	struct thread_struct *t = &current->thread;	845	struct thread_struct *t = &current->thread;
846	struct user_desc info;	846	struct user_desc info;
847	struct desc_struct *desc;	847	struct desc_struct *desc;
848	int cpu, idx;	848	int cpu, idx;
849		849
850	if (copy_from_user(&info, u_info, sizeof(info)))	850	if (copy_from_user(&info, u_info, sizeof(info)))
851	return -EFAULT;	851	return -EFAULT;
852	idx = info.entry_number;	852	idx = info.entry_number;
853		853
854	/*	854	/*
855	* index -1 means the kernel should try to find and	855	* index -1 means the kernel should try to find and
856	* allocate an empty descriptor:	856	* allocate an empty descriptor:
857	*/	857	*/
858	if (idx == -1) {	858	if (idx == -1) {
859	idx = get_free_idx();	859	idx = get_free_idx();
860	if (idx < 0)	860	if (idx < 0)
861	return idx;	861	return idx;
862	if (put_user(idx, &u_info->entry_number))	862	if (put_user(idx, &u_info->entry_number))
863	return -EFAULT;	863	return -EFAULT;
864	}	864	}
865		865
866	if (idx < GDT_ENTRY_TLS_MIN \|\| idx > GDT_ENTRY_TLS_MAX)	866	if (idx < GDT_ENTRY_TLS_MIN \|\| idx > GDT_ENTRY_TLS_MAX)
867	return -EINVAL;	867	return -EINVAL;
868		868
869	desc = t->tls_array + idx - GDT_ENTRY_TLS_MIN;	869	desc = t->tls_array + idx - GDT_ENTRY_TLS_MIN;
870		870
871	/*	871	/*
872	* We must not get preempted while modifying the TLS.	872	* We must not get preempted while modifying the TLS.
873	*/	873	*/
874	cpu = get_cpu();	874	cpu = get_cpu();
875		875
876	if (LDT_empty(&info)) {	876	if (LDT_empty(&info)) {
877	desc->a = 0;	877	desc->a = 0;
878	desc->b = 0;	878	desc->b = 0;
879	} else {	879	} else {
880	desc->a = LDT_entry_a(&info);	880	desc->a = LDT_entry_a(&info);
881	desc->b = LDT_entry_b(&info);	881	desc->b = LDT_entry_b(&info);
882	}	882	}
883	load_TLS(t, cpu);	883	load_TLS(t, cpu);
884		884
885	put_cpu();	885	put_cpu();
886		886
887	return 0;	887	return 0;
888	}	888	}
889		889
890	/*	890	/*
891	* Get the current Thread-Local Storage area:	891	* Get the current Thread-Local Storage area:
892	*/	892	*/
893		893
894	#define GET_BASE(desc) ( \	894	#define GET_BASE(desc) ( \
895	(((desc)->a >> 16) & 0x0000ffff) \| \	895	(((desc)->a >> 16) & 0x0000ffff) \| \
896	(((desc)->b << 16) & 0x00ff0000) \| \	896	(((desc)->b << 16) & 0x00ff0000) \| \
897	( (desc)->b & 0xff000000) )	897	( (desc)->b & 0xff000000) )
898		898
899	#define GET_LIMIT(desc) ( \	899	#define GET_LIMIT(desc) ( \
900	((desc)->a & 0x0ffff) \| \	900	((desc)->a & 0x0ffff) \| \
901	((desc)->b & 0xf0000) )	901	((desc)->b & 0xf0000) )
902		902
903	#define GET_32BIT(desc) (((desc)->b >> 22) & 1)	903	#define GET_32BIT(desc) (((desc)->b >> 22) & 1)
904	#define GET_CONTENTS(desc) (((desc)->b >> 10) & 3)	904	#define GET_CONTENTS(desc) (((desc)->b >> 10) & 3)
905	#define GET_WRITABLE(desc) (((desc)->b >> 9) & 1)	905	#define GET_WRITABLE(desc) (((desc)->b >> 9) & 1)
906	#define GET_LIMIT_PAGES(desc) (((desc)->b >> 23) & 1)	906	#define GET_LIMIT_PAGES(desc) (((desc)->b >> 23) & 1)
907	#define GET_PRESENT(desc) (((desc)->b >> 15) & 1)	907	#define GET_PRESENT(desc) (((desc)->b >> 15) & 1)
908	#define GET_USEABLE(desc) (((desc)->b >> 20) & 1)	908	#define GET_USEABLE(desc) (((desc)->b >> 20) & 1)
909		909
910	asmlinkage int sys_get_thread_area(struct user_desc __user *u_info)	910	asmlinkage int sys_get_thread_area(struct user_desc __user *u_info)
911	{	911	{
912	struct user_desc info;	912	struct user_desc info;
913	struct desc_struct *desc;	913	struct desc_struct *desc;
914	int idx;	914	int idx;
915		915
916	if (get_user(idx, &u_info->entry_number))	916	if (get_user(idx, &u_info->entry_number))
917	return -EFAULT;	917	return -EFAULT;
918	if (idx < GDT_ENTRY_TLS_MIN \|\| idx > GDT_ENTRY_TLS_MAX)	918	if (idx < GDT_ENTRY_TLS_MIN \|\| idx > GDT_ENTRY_TLS_MAX)
919	return -EINVAL;	919	return -EINVAL;
920		920
921	memset(&info, 0, sizeof(info));	921	memset(&info, 0, sizeof(info));
922		922
923	desc = current->thread.tls_array + idx - GDT_ENTRY_TLS_MIN;	923	desc = current->thread.tls_array + idx - GDT_ENTRY_TLS_MIN;
924		924
925	info.entry_number = idx;	925	info.entry_number = idx;
926	info.base_addr = GET_BASE(desc);	926	info.base_addr = GET_BASE(desc);
927	info.limit = GET_LIMIT(desc);	927	info.limit = GET_LIMIT(desc);
928	info.seg_32bit = GET_32BIT(desc);	928	info.seg_32bit = GET_32BIT(desc);
929	info.contents = GET_CONTENTS(desc);	929	info.contents = GET_CONTENTS(desc);
930	info.read_exec_only = !GET_WRITABLE(desc);	930	info.read_exec_only = !GET_WRITABLE(desc);
931	info.limit_in_pages = GET_LIMIT_PAGES(desc);	931	info.limit_in_pages = GET_LIMIT_PAGES(desc);
932	info.seg_not_present = !GET_PRESENT(desc);	932	info.seg_not_present = !GET_PRESENT(desc);
933	info.useable = GET_USEABLE(desc);	933	info.useable = GET_USEABLE(desc);
934		934
935	if (copy_to_user(u_info, &info, sizeof(info)))	935	if (copy_to_user(u_info, &info, sizeof(info)))
936	return -EFAULT;	936	return -EFAULT;
937	return 0;	937	return 0;
938	}	938	}
939		939
940	unsigned long arch_align_stack(unsigned long sp)	940	unsigned long arch_align_stack(unsigned long sp)
941	{	941	{
942	if (randomize_va_space)	942	if (randomize_va_space)
943	sp -= get_random_int() % 8192;	943	sp -= get_random_int() % 8192;
944	return sp & ~0xf;	944	return sp & ~0xf;
945	}	945	}
946		946

arch/i386/mach-voyager/voyager_basic.c

Diff comments View file @ f2ab446

 /* Copyright (C) 1999,2001
  *
  * Author: J.E.J.Bottomley@HansenPartnership.com
  *
  * linux/arch/i386/kernel/voyager.c
  *
  * This file contains all the voyager specific routines for getting
  * initialisation of the architecture to function.  For additional
  * features see:
  *
  *	voyager_cat.c - Voyager CAT bus interface
  *	voyager_smp.c - Voyager SMP hal (emulates linux smp.c)
  */
 #include <linux/config.h>
 #include <linux/module.h>
 #include <linux/types.h>
 #include <linux/sched.h>
 #include <linux/ptrace.h>
 #include <linux/ioport.h>
 #include <linux/interrupt.h>
 #include <linux/init.h>
 #include <linux/delay.h>
 #include <linux/reboot.h>
 #include <linux/sysrq.h>
 #include <asm/io.h>
 #include <asm/voyager.h>
 #include <asm/vic.h>
 #include <linux/pm.h>
 #include <linux/irq.h>
 #include <asm/tlbflush.h>
 #include <asm/arch_hooks.h>
 #include <asm/i8253.h>
 /*
  * Power off function, if any
  */
 void (*pm_power_off)(void);
 EXPORT_SYMBOL(pm_power_off);
 int voyager_level = 0;
 struct voyager_SUS *voyager_SUS = NULL;
 #ifdef CONFIG_SMP
 static void
 voyager_dump(int dummy1, struct pt_regs *dummy2, struct tty_struct *dummy3)
 {
 	/* get here via a sysrq */
 	voyager_smp_dump();
 }
 static struct sysrq_key_op sysrq_voyager_dump_op = {
 	.handler	= voyager_dump,
 	.help_msg	= "Voyager",
 	.action_msg	= "Dump Voyager Status",
 };
 #endif
 void
 voyager_detect(struct voyager_bios_info *bios)
 {
 	if(bios->len != 0xff) {
 		int class = (bios->class_1 << 8)
 			| (bios->class_2 & 0xff);
 		printk("Voyager System detected.\n"
 		       "        Class %x, Revision %d.%d\n",
 		       class, bios->major, bios->minor);
 		if(class == VOYAGER_LEVEL4)
 			voyager_level = 4;
 		else if(class < VOYAGER_LEVEL5_AND_ABOVE)
 			voyager_level = 3;
 		else
 			voyager_level = 5;
 		printk("        Architecture Level %d\n", voyager_level);
 		if(voyager_level < 4)
 			printk("\n**WARNING**: Voyager HAL only supports Levels 4 and 5 Architectures at the moment\n\n");
 		/* install the power off handler */
 		pm_power_off = voyager_power_off;
 #ifdef CONFIG_SMP
 		register_sysrq_key('v', &sysrq_voyager_dump_op);
 #endif
 	} else {
 		printk("\n\n**WARNING**: No Voyager Subsystem Found\n");
 	}
 }
 void
 voyager_system_interrupt(int cpl, void *dev_id, struct pt_regs *regs)
 {
 	printk("Voyager: detected system interrupt\n");
 }
 /* Routine to read information from the extended CMOS area */
 __u8
 voyager_extended_cmos_read(__u16 addr)
 {
 	outb(addr & 0xff, 0x74);
 	outb((addr >> 8) & 0xff, 0x75);
 	return inb(0x76);
 }
 /* internal definitions for the SUS Click Map of memory */
 #define CLICK_ENTRIES	16
 #define CLICK_SIZE	4096	/* click to byte conversion for Length */
 typedef struct ClickMap {
 	struct Entry {
 		__u32	Address;
 		__u32	Length;
 	} Entry[CLICK_ENTRIES];
 } ClickMap_t;
 /* This routine is pretty much an awful hack to read the bios clickmap by
  * mapping it into page 0.  There are usually three regions in the map:
  * 	Base Memory
  * 	Extended Memory
  *	zero length marker for end of map
  *
  * Returns are 0 for failure and 1 for success on extracting region.
  */
 int __init
 voyager_memory_detect(int region, __u32 *start, __u32 *length)
 {
 	int i;
 	int retval = 0;
 	__u8 cmos[4];
 	ClickMap_t *map;
 	unsigned long map_addr;
 	unsigned long old;
 	if(region >= CLICK_ENTRIES) {
 		printk("Voyager: Illegal ClickMap region %d\n", region);
 		return 0;
 	}
 	for(i = 0; i < sizeof(cmos); i++)
 		cmos[i] = voyager_extended_cmos_read(VOYAGER_MEMORY_CLICKMAP + i);
 	map_addr = *(unsigned long *)cmos;
 	/* steal page 0 for this */
 	old = pg0[0];
 	pg0[0] = ((map_addr & PAGE_MASK) | _PAGE_RW | _PAGE_PRESENT);
 	local_flush_tlb();
 	/* now clear everything out but page 0 */
 	map = (ClickMap_t *)(map_addr & (~PAGE_MASK));
 	/* zero length is the end of the clickmap */
 	if(map->Entry[region].Length != 0) {
 		*length = map->Entry[region].Length * CLICK_SIZE;
 		*start = map->Entry[region].Address;
 		retval = 1;
 	}
 	/* replace the mapping */
 	pg0[0] = old;
 	local_flush_tlb();
 	return retval;
 }
 /* voyager specific handling code for timer interrupts.  Used to hand
  * off the timer tick to the SMP code, since the VIC doesn't have an
  * internal timer (The QIC does, but that's another story). */
 void
 voyager_timer_interrupt(struct pt_regs *regs)
 {
 	if((jiffies & 0x3ff) == 0) {
 		/* There seems to be something flaky in either
 		 * hardware or software that is resetting the timer 0
 		 * count to something much higher than it should be
 		 * This seems to occur in the boot sequence, just
 		 * before root is mounted.  Therefore, every 10
 		 * seconds or so, we sanity check the timer zero count
 		 * and kick it back to where it should be.
 		 *
 		 * FIXME: This is the most awful hack yet seen.  I
 		 * should work out exactly what is interfering with
 		 * the timer count settings early in the boot sequence
 		 * and swiftly introduce it to something sharp and
 		 * pointy.  */
 		__u16 val;
 		spin_lock(&i8253_lock);
 		outb_p(0x00, 0x43);
 		val = inb_p(0x40);
 		val |= inb(0x40) << 8;
 		spin_unlock(&i8253_lock);
 		if(val > LATCH) {
 			printk("\nVOYAGER: countdown timer value too high (%d), resetting\n\n", val);
 			spin_lock(&i8253_lock);
 			outb(0x34,0x43);
 			outb_p(LATCH & 0xff , 0x40);	/* LSB */
 			outb(LATCH >> 8 , 0x40);	/* MSB */
 			spin_unlock(&i8253_lock);
 		}
 	}
 #ifdef CONFIG_SMP
 	smp_vic_timer_interrupt(regs);
 #endif
 }
 void
 voyager_power_off(void)
 {
 	printk("VOYAGER Power Off\n");
 	if(voyager_level == 5) {
 		voyager_cat_power_off();
 	} else if(voyager_level == 4) {
 		/* This doesn't apparently work on most L4 machines,
 		 * but the specs say to do this to get automatic power
 		 * off.  Unfortunately, if it doesn't power off the
 		 * machine, it ends up doing a cold restart, which
 		 * isn't really intended, so comment out the code */
 #if 0
 		int port;
 		/* enable the voyager Configuration Space */
 		outb((inb(VOYAGER_MC_SETUP) & 0xf0) | 0x8,
 		     VOYAGER_MC_SETUP);
 		/* the port for the power off flag is an offset from the
 		   floating base */
 		port = (inb(VOYAGER_SSPB_RELOCATION_PORT) << 8) + 0x21;
 		/* set the power off flag */
 		outb(inb(port) | 0x1, port);
 #endif
 	}
 	/* and wait for it to happen */
-	for(;;) {
+	local_irq_disable();
-		__asm("cli");
+	for(;;)
-		__asm("hlt");
+		halt();
-	}
 }
 /* copied from process.c */
 static inline void
 kb_wait(void)
 {
 	int i;
 	for (i=0; i<0x10000; i++)
 		if ((inb_p(0x64) & 0x02) == 0)
 			break;
 }
 void
 machine_shutdown(void)
 {
 	/* Architecture specific shutdown needed before a kexec */
 }
 void
 machine_restart(char *cmd)
 {
 	printk("Voyager Warm Restart\n");
 	kb_wait();
 	if(voyager_level == 5) {
 		/* write magic values to the RTC to inform system that
 		 * shutdown is beginning */
 		outb(0x8f, 0x70);
 		outb(0x5 , 0x71);
 		udelay(50);
 		outb(0xfe,0x64);         /* pull reset low */
 	} else if(voyager_level == 4) {
 		__u16 catbase = inb(VOYAGER_SSPB_RELOCATION_PORT)<<8;
 		__u8 basebd = inb(VOYAGER_MC_SETUP);
 		outb(basebd | 0x08, VOYAGER_MC_SETUP);
 		outb(0x02, catbase + 0x21);
 	}
-	for(;;) {
+	local_irq_disable();
-		asm("cli");
+	for(;;)
-		asm("hlt");
+		halt();
-	}
 }
 void
 machine_emergency_restart(void)
 {
 	/*for now, just hook this to a warm restart */
 	machine_restart(NULL);
 }
 void
 mca_nmi_hook(void)
 {
 	__u8 dumpval __attribute__((unused)) = inb(0xf823);
 	__u8 swnmi __attribute__((unused)) = inb(0xf813);
 	/* FIXME: assume dump switch pressed */
 	/* check to see if the dump switch was pressed */
 	VDEBUG(("VOYAGER: dumpval = 0x%x, swnmi = 0x%x\n", dumpval, swnmi));
 	/* clear swnmi */
 	outb(0xff, 0xf813);
 	/* tell SUS to ignore dump */
 	if(voyager_level == 5 && voyager_SUS != NULL) {
 		if(voyager_SUS->SUS_mbox == VOYAGER_DUMP_BUTTON_NMI) {
 			voyager_SUS->kernel_mbox = VOYAGER_NO_COMMAND;
 			voyager_SUS->kernel_flags |= VOYAGER_OS_IN_PROGRESS;
 			udelay(1000);
 			voyager_SUS->kernel_mbox = VOYAGER_IGNORE_DUMP;
 			voyager_SUS->kernel_flags &= ~VOYAGER_OS_IN_PROGRESS;
 		}
 	}
 	printk(KERN_ERR "VOYAGER: Dump switch pressed, printing CPU%d tracebacks\n", smp_processor_id());
 	show_stack(NULL, NULL);
 	show_state();
 }
 void
 machine_halt(void)
 {
 	/* treat a halt like a power off */
 	machine_power_off();
 }
 void machine_power_off(void)
 {
 	if (pm_power_off)
 		pm_power_off();
 }

arch/i386/mach-voyager/voyager_smp.c

Diff comments View file @ f2ab446

1	/* -- mode: c; c-basic-offset: 8 -- */	1	/* -- mode: c; c-basic-offset: 8 -- */
2		2
3	/* Copyright (C) 1999,2001	3	/* Copyright (C) 1999,2001
4	*	4	*
5	* Author: J.E.J.Bottomley@HansenPartnership.com	5	* Author: J.E.J.Bottomley@HansenPartnership.com
6	*	6	*
7	* linux/arch/i386/kernel/voyager_smp.c	7	* linux/arch/i386/kernel/voyager_smp.c
8	*	8	*
9	* This file provides all the same external entries as smp.c but uses	9	* This file provides all the same external entries as smp.c but uses
10	* the voyager hal to provide the functionality	10	* the voyager hal to provide the functionality
11	*/	11	*/
12	#include <linux/config.h>	12	#include <linux/config.h>
13	#include <linux/module.h>	13	#include <linux/module.h>
14	#include <linux/mm.h>	14	#include <linux/mm.h>
15	#include <linux/kernel_stat.h>	15	#include <linux/kernel_stat.h>
16	#include <linux/delay.h>	16	#include <linux/delay.h>
17	#include <linux/mc146818rtc.h>	17	#include <linux/mc146818rtc.h>
18	#include <linux/cache.h>	18	#include <linux/cache.h>
19	#include <linux/interrupt.h>	19	#include <linux/interrupt.h>
20	#include <linux/smp_lock.h>	20	#include <linux/smp_lock.h>
21	#include <linux/init.h>	21	#include <linux/init.h>
22	#include <linux/kernel.h>	22	#include <linux/kernel.h>
23	#include <linux/bootmem.h>	23	#include <linux/bootmem.h>
24	#include <linux/completion.h>	24	#include <linux/completion.h>
25	#include <asm/desc.h>	25	#include <asm/desc.h>
26	#include <asm/voyager.h>	26	#include <asm/voyager.h>
27	#include <asm/vic.h>	27	#include <asm/vic.h>
28	#include <asm/mtrr.h>	28	#include <asm/mtrr.h>
29	#include <asm/pgalloc.h>	29	#include <asm/pgalloc.h>
30	#include <asm/tlbflush.h>	30	#include <asm/tlbflush.h>
31	#include <asm/arch_hooks.h>	31	#include <asm/arch_hooks.h>
32		32
33	#include <linux/irq.h>	33	#include <linux/irq.h>
34		34
35	/* TLB state -- visible externally, indexed physically */	35	/* TLB state -- visible externally, indexed physically */
36	DEFINE_PER_CPU(struct tlb_state, cpu_tlbstate) ____cacheline_aligned = { &init_mm, 0 };	36	DEFINE_PER_CPU(struct tlb_state, cpu_tlbstate) ____cacheline_aligned = { &init_mm, 0 };
37		37
38	/* CPU IRQ affinity -- set to all ones initially */	38	/* CPU IRQ affinity -- set to all ones initially */
39	static unsigned long cpu_irq_affinity[NR_CPUS] __cacheline_aligned = { [0 ... NR_CPUS-1] = ~0UL };	39	static unsigned long cpu_irq_affinity[NR_CPUS] __cacheline_aligned = { [0 ... NR_CPUS-1] = ~0UL };
40		40
41	/* per CPU data structure (for /proc/cpuinfo et al), visible externally	41	/* per CPU data structure (for /proc/cpuinfo et al), visible externally
42	* indexed physically */	42	* indexed physically */
43	struct cpuinfo_x86 cpu_data[NR_CPUS] __cacheline_aligned;	43	struct cpuinfo_x86 cpu_data[NR_CPUS] __cacheline_aligned;
44	EXPORT_SYMBOL(cpu_data);	44	EXPORT_SYMBOL(cpu_data);
45		45
46	/* physical ID of the CPU used to boot the system */	46	/* physical ID of the CPU used to boot the system */
47	unsigned char boot_cpu_id;	47	unsigned char boot_cpu_id;
48		48
49	/* The memory line addresses for the Quad CPIs */	49	/* The memory line addresses for the Quad CPIs */
50	struct voyager_qic_cpi *voyager_quad_cpi_addr[NR_CPUS] __cacheline_aligned;	50	struct voyager_qic_cpi *voyager_quad_cpi_addr[NR_CPUS] __cacheline_aligned;
51		51
52	/* The masks for the Extended VIC processors, filled in by cat_init */	52	/* The masks for the Extended VIC processors, filled in by cat_init */
53	__u32 voyager_extended_vic_processors = 0;	53	__u32 voyager_extended_vic_processors = 0;
54		54
55	/* Masks for the extended Quad processors which cannot be VIC booted */	55	/* Masks for the extended Quad processors which cannot be VIC booted */
56	__u32 voyager_allowed_boot_processors = 0;	56	__u32 voyager_allowed_boot_processors = 0;
57		57
58	/* The mask for the Quad Processors (both extended and non-extended) */	58	/* The mask for the Quad Processors (both extended and non-extended) */
59	__u32 voyager_quad_processors = 0;	59	__u32 voyager_quad_processors = 0;
60		60
61	/* Total count of live CPUs, used in process.c to display	61	/* Total count of live CPUs, used in process.c to display
62	* the CPU information and in irq.c for the per CPU irq	62	* the CPU information and in irq.c for the per CPU irq
63	* activity count. Finally exported by i386_ksyms.c */	63	* activity count. Finally exported by i386_ksyms.c */
64	static int voyager_extended_cpus = 1;	64	static int voyager_extended_cpus = 1;
65		65
66	/* Have we found an SMP box - used by time.c to do the profiling	66	/* Have we found an SMP box - used by time.c to do the profiling
67	interrupt for timeslicing; do not set to 1 until the per CPU timer	67	interrupt for timeslicing; do not set to 1 until the per CPU timer
68	interrupt is active */	68	interrupt is active */
69	int smp_found_config = 0;	69	int smp_found_config = 0;
70		70
71	/* Used for the invalidate map that's also checked in the spinlock */	71	/* Used for the invalidate map that's also checked in the spinlock */
72	static volatile unsigned long smp_invalidate_needed;	72	static volatile unsigned long smp_invalidate_needed;
73		73
74	/* Bitmask of currently online CPUs - used by setup.c for	74	/* Bitmask of currently online CPUs - used by setup.c for
75	/proc/cpuinfo, visible externally but still physical */	75	/proc/cpuinfo, visible externally but still physical */
76	cpumask_t cpu_online_map = CPU_MASK_NONE;	76	cpumask_t cpu_online_map = CPU_MASK_NONE;
77	EXPORT_SYMBOL(cpu_online_map);	77	EXPORT_SYMBOL(cpu_online_map);
78		78
79	/* Bitmask of CPUs present in the system - exported by i386_syms.c, used	79	/* Bitmask of CPUs present in the system - exported by i386_syms.c, used
80	* by scheduler but indexed physically */	80	* by scheduler but indexed physically */
81	cpumask_t phys_cpu_present_map = CPU_MASK_NONE;	81	cpumask_t phys_cpu_present_map = CPU_MASK_NONE;
82		82
83		83
84	/* The internal functions */	84	/* The internal functions */
85	static void send_CPI(__u32 cpuset, __u8 cpi);	85	static void send_CPI(__u32 cpuset, __u8 cpi);
86	static void ack_CPI(__u8 cpi);	86	static void ack_CPI(__u8 cpi);
87	static int ack_QIC_CPI(__u8 cpi);	87	static int ack_QIC_CPI(__u8 cpi);
88	static void ack_special_QIC_CPI(__u8 cpi);	88	static void ack_special_QIC_CPI(__u8 cpi);
89	static void ack_VIC_CPI(__u8 cpi);	89	static void ack_VIC_CPI(__u8 cpi);
90	static void send_CPI_allbutself(__u8 cpi);	90	static void send_CPI_allbutself(__u8 cpi);
91	static void enable_vic_irq(unsigned int irq);	91	static void enable_vic_irq(unsigned int irq);
92	static void disable_vic_irq(unsigned int irq);	92	static void disable_vic_irq(unsigned int irq);
93	static unsigned int startup_vic_irq(unsigned int irq);	93	static unsigned int startup_vic_irq(unsigned int irq);
94	static void enable_local_vic_irq(unsigned int irq);	94	static void enable_local_vic_irq(unsigned int irq);
95	static void disable_local_vic_irq(unsigned int irq);	95	static void disable_local_vic_irq(unsigned int irq);
96	static void before_handle_vic_irq(unsigned int irq);	96	static void before_handle_vic_irq(unsigned int irq);
97	static void after_handle_vic_irq(unsigned int irq);	97	static void after_handle_vic_irq(unsigned int irq);
98	static void set_vic_irq_affinity(unsigned int irq, cpumask_t mask);	98	static void set_vic_irq_affinity(unsigned int irq, cpumask_t mask);
99	static void ack_vic_irq(unsigned int irq);	99	static void ack_vic_irq(unsigned int irq);
100	static void vic_enable_cpi(void);	100	static void vic_enable_cpi(void);
101	static void do_boot_cpu(__u8 cpuid);	101	static void do_boot_cpu(__u8 cpuid);
102	static void do_quad_bootstrap(void);	102	static void do_quad_bootstrap(void);
103		103
104	int hard_smp_processor_id(void);	104	int hard_smp_processor_id(void);
105		105
106	/* Inline functions */	106	/* Inline functions */
107	static inline void	107	static inline void
108	send_one_QIC_CPI(__u8 cpu, __u8 cpi)	108	send_one_QIC_CPI(__u8 cpu, __u8 cpi)
109	{	109	{
110	voyager_quad_cpi_addr[cpu]->qic_cpi[cpi].cpi =	110	voyager_quad_cpi_addr[cpu]->qic_cpi[cpi].cpi =
111	(smp_processor_id() << 16) + cpi;	111	(smp_processor_id() << 16) + cpi;
112	}	112	}
113		113
114	static inline void	114	static inline void
115	send_QIC_CPI(__u32 cpuset, __u8 cpi)	115	send_QIC_CPI(__u32 cpuset, __u8 cpi)
116	{	116	{
117	int cpu;	117	int cpu;
118		118
119	for_each_online_cpu(cpu) {	119	for_each_online_cpu(cpu) {
120	if(cpuset & (1<<cpu)) {	120	if(cpuset & (1<<cpu)) {
121	#ifdef VOYAGER_DEBUG	121	#ifdef VOYAGER_DEBUG
122	if(!cpu_isset(cpu, cpu_online_map))	122	if(!cpu_isset(cpu, cpu_online_map))
123	VDEBUG(("CPU%d sending cpi %d to CPU%d not in cpu_online_map\n", hard_smp_processor_id(), cpi, cpu));	123	VDEBUG(("CPU%d sending cpi %d to CPU%d not in cpu_online_map\n", hard_smp_processor_id(), cpi, cpu));
124	#endif	124	#endif
125	send_one_QIC_CPI(cpu, cpi - QIC_CPI_OFFSET);	125	send_one_QIC_CPI(cpu, cpi - QIC_CPI_OFFSET);
126	}	126	}
127	}	127	}
128	}	128	}
129		129
130	static inline void	130	static inline void
131	wrapper_smp_local_timer_interrupt(struct pt_regs *regs)	131	wrapper_smp_local_timer_interrupt(struct pt_regs *regs)
132	{	132	{
133	irq_enter();	133	irq_enter();
134	smp_local_timer_interrupt(regs);	134	smp_local_timer_interrupt(regs);
135	irq_exit();	135	irq_exit();
136	}	136	}
137		137
138	static inline void	138	static inline void
139	send_one_CPI(__u8 cpu, __u8 cpi)	139	send_one_CPI(__u8 cpu, __u8 cpi)
140	{	140	{
141	if(voyager_quad_processors & (1<<cpu))	141	if(voyager_quad_processors & (1<<cpu))
142	send_one_QIC_CPI(cpu, cpi - QIC_CPI_OFFSET);	142	send_one_QIC_CPI(cpu, cpi - QIC_CPI_OFFSET);
143	else	143	else
144	send_CPI(1<<cpu, cpi);	144	send_CPI(1<<cpu, cpi);
145	}	145	}
146		146
147	static inline void	147	static inline void
148	send_CPI_allbutself(__u8 cpi)	148	send_CPI_allbutself(__u8 cpi)
149	{	149	{
150	__u8 cpu = smp_processor_id();	150	__u8 cpu = smp_processor_id();
151	__u32 mask = cpus_addr(cpu_online_map)[0] & ~(1 << cpu);	151	__u32 mask = cpus_addr(cpu_online_map)[0] & ~(1 << cpu);
152	send_CPI(mask, cpi);	152	send_CPI(mask, cpi);
153	}	153	}
154		154
155	static inline int	155	static inline int
156	is_cpu_quad(void)	156	is_cpu_quad(void)
157	{	157	{
158	__u8 cpumask = inb(VIC_PROC_WHO_AM_I);	158	__u8 cpumask = inb(VIC_PROC_WHO_AM_I);
159	return ((cpumask & QUAD_IDENTIFIER) == QUAD_IDENTIFIER);	159	return ((cpumask & QUAD_IDENTIFIER) == QUAD_IDENTIFIER);
160	}	160	}
161		161
162	static inline int	162	static inline int
163	is_cpu_extended(void)	163	is_cpu_extended(void)
164	{	164	{
165	__u8 cpu = hard_smp_processor_id();	165	__u8 cpu = hard_smp_processor_id();
166		166
167	return(voyager_extended_vic_processors & (1<<cpu));	167	return(voyager_extended_vic_processors & (1<<cpu));
168	}	168	}
169		169
170	static inline int	170	static inline int
171	is_cpu_vic_boot(void)	171	is_cpu_vic_boot(void)
172	{	172	{
173	__u8 cpu = hard_smp_processor_id();	173	__u8 cpu = hard_smp_processor_id();
174		174
175	return(voyager_extended_vic_processors	175	return(voyager_extended_vic_processors
176	& voyager_allowed_boot_processors & (1<<cpu));	176	& voyager_allowed_boot_processors & (1<<cpu));
177	}	177	}
178		178
179		179
180	static inline void	180	static inline void
181	ack_CPI(__u8 cpi)	181	ack_CPI(__u8 cpi)
182	{	182	{
183	switch(cpi) {	183	switch(cpi) {
184	case VIC_CPU_BOOT_CPI:	184	case VIC_CPU_BOOT_CPI:
185	if(is_cpu_quad() && !is_cpu_vic_boot())	185	if(is_cpu_quad() && !is_cpu_vic_boot())
186	ack_QIC_CPI(cpi);	186	ack_QIC_CPI(cpi);
187	else	187	else
188	ack_VIC_CPI(cpi);	188	ack_VIC_CPI(cpi);
189	break;	189	break;
190	case VIC_SYS_INT:	190	case VIC_SYS_INT:
191	case VIC_CMN_INT:	191	case VIC_CMN_INT:
192	/* These are slightly strange. Even on the Quad card,	192	/* These are slightly strange. Even on the Quad card,
193	* They are vectored as VIC CPIs */	193	* They are vectored as VIC CPIs */
194	if(is_cpu_quad())	194	if(is_cpu_quad())
195	ack_special_QIC_CPI(cpi);	195	ack_special_QIC_CPI(cpi);
196	else	196	else
197	ack_VIC_CPI(cpi);	197	ack_VIC_CPI(cpi);
198	break;	198	break;
199	default:	199	default:
200	printk("VOYAGER ERROR: CPI%d is in common CPI code\n", cpi);	200	printk("VOYAGER ERROR: CPI%d is in common CPI code\n", cpi);
201	break;	201	break;
202	}	202	}
203	}	203	}
204		204
205	/* local variables */	205	/* local variables */
206		206
207	/* The VIC IRQ descriptors -- these look almost identical to the	207	/* The VIC IRQ descriptors -- these look almost identical to the
208	* 8259 IRQs except that masks and things must be kept per processor	208	* 8259 IRQs except that masks and things must be kept per processor
209	*/	209	*/
210	static struct hw_interrupt_type vic_irq_type = {	210	static struct hw_interrupt_type vic_irq_type = {
211	.typename = "VIC-level",	211	.typename = "VIC-level",
212	.startup = startup_vic_irq,	212	.startup = startup_vic_irq,
213	.shutdown = disable_vic_irq,	213	.shutdown = disable_vic_irq,
214	.enable = enable_vic_irq,	214	.enable = enable_vic_irq,
215	.disable = disable_vic_irq,	215	.disable = disable_vic_irq,
216	.ack = before_handle_vic_irq,	216	.ack = before_handle_vic_irq,
217	.end = after_handle_vic_irq,	217	.end = after_handle_vic_irq,
218	.set_affinity = set_vic_irq_affinity,	218	.set_affinity = set_vic_irq_affinity,
219	};	219	};
220		220
221	/* used to count up as CPUs are brought on line (starts at 0) */	221	/* used to count up as CPUs are brought on line (starts at 0) */
222	static int cpucount = 0;	222	static int cpucount = 0;
223		223
224	/* steal a page from the bottom of memory for the trampoline and	224	/* steal a page from the bottom of memory for the trampoline and
225	* squirrel its address away here. This will be in kernel virtual	225	* squirrel its address away here. This will be in kernel virtual
226	* space */	226	* space */
227	static __u32 trampoline_base;	227	static __u32 trampoline_base;
228		228
229	/* The per cpu profile stuff - used in smp_local_timer_interrupt */	229	/* The per cpu profile stuff - used in smp_local_timer_interrupt */
230	static DEFINE_PER_CPU(int, prof_multiplier) = 1;	230	static DEFINE_PER_CPU(int, prof_multiplier) = 1;
231	static DEFINE_PER_CPU(int, prof_old_multiplier) = 1;	231	static DEFINE_PER_CPU(int, prof_old_multiplier) = 1;
232	static DEFINE_PER_CPU(int, prof_counter) = 1;	232	static DEFINE_PER_CPU(int, prof_counter) = 1;
233		233
234	/* the map used to check if a CPU has booted */	234	/* the map used to check if a CPU has booted */
235	static __u32 cpu_booted_map;	235	static __u32 cpu_booted_map;
236		236
237	/* the synchronize flag used to hold all secondary CPUs spinning in	237	/* the synchronize flag used to hold all secondary CPUs spinning in
238	* a tight loop until the boot sequence is ready for them */	238	* a tight loop until the boot sequence is ready for them */
239	static cpumask_t smp_commenced_mask = CPU_MASK_NONE;	239	static cpumask_t smp_commenced_mask = CPU_MASK_NONE;
240		240
241	/* This is for the new dynamic CPU boot code */	241	/* This is for the new dynamic CPU boot code */
242	cpumask_t cpu_callin_map = CPU_MASK_NONE;	242	cpumask_t cpu_callin_map = CPU_MASK_NONE;
243	cpumask_t cpu_callout_map = CPU_MASK_NONE;	243	cpumask_t cpu_callout_map = CPU_MASK_NONE;
244	EXPORT_SYMBOL(cpu_callout_map);	244	EXPORT_SYMBOL(cpu_callout_map);
245		245
246	/* The per processor IRQ masks (these are usually kept in sync) */	246	/* The per processor IRQ masks (these are usually kept in sync) */
247	static __u16 vic_irq_mask[NR_CPUS] __cacheline_aligned;	247	static __u16 vic_irq_mask[NR_CPUS] __cacheline_aligned;
248		248
249	/* the list of IRQs to be enabled by the VIC_ENABLE_IRQ_CPI */	249	/* the list of IRQs to be enabled by the VIC_ENABLE_IRQ_CPI */
250	static __u16 vic_irq_enable_mask[NR_CPUS] __cacheline_aligned = { 0 };	250	static __u16 vic_irq_enable_mask[NR_CPUS] __cacheline_aligned = { 0 };
251		251
252	/* Lock for enable/disable of VIC interrupts */	252	/* Lock for enable/disable of VIC interrupts */
253	static __cacheline_aligned DEFINE_SPINLOCK(vic_irq_lock);	253	static __cacheline_aligned DEFINE_SPINLOCK(vic_irq_lock);
254		254
255	/* The boot processor is correctly set up in PC mode when it	255	/* The boot processor is correctly set up in PC mode when it
256	* comes up, but the secondaries need their master/slave 8259	256	* comes up, but the secondaries need their master/slave 8259
257	* pairs initializing correctly */	257	* pairs initializing correctly */
258		258
259	/* Interrupt counters (per cpu) and total - used to try to	259	/* Interrupt counters (per cpu) and total - used to try to
260	* even up the interrupt handling routines */	260	* even up the interrupt handling routines */
261	static long vic_intr_total = 0;	261	static long vic_intr_total = 0;
262	static long vic_intr_count[NR_CPUS] __cacheline_aligned = { 0 };	262	static long vic_intr_count[NR_CPUS] __cacheline_aligned = { 0 };
263	static unsigned long vic_tick[NR_CPUS] __cacheline_aligned = { 0 };	263	static unsigned long vic_tick[NR_CPUS] __cacheline_aligned = { 0 };
264		264
265	/* Since we can only use CPI0, we fake all the other CPIs */	265	/* Since we can only use CPI0, we fake all the other CPIs */
266	static unsigned long vic_cpi_mailbox[NR_CPUS] __cacheline_aligned;	266	static unsigned long vic_cpi_mailbox[NR_CPUS] __cacheline_aligned;
267		267
268	/* debugging routine to read the isr of the cpu's pic */	268	/* debugging routine to read the isr of the cpu's pic */
269	static inline __u16	269	static inline __u16
270	vic_read_isr(void)	270	vic_read_isr(void)
271	{	271	{
272	__u16 isr;	272	__u16 isr;
273		273
274	outb(0x0b, 0xa0);	274	outb(0x0b, 0xa0);
275	isr = inb(0xa0) << 8;	275	isr = inb(0xa0) << 8;
276	outb(0x0b, 0x20);	276	outb(0x0b, 0x20);
277	isr \|= inb(0x20);	277	isr \|= inb(0x20);
278		278
279	return isr;	279	return isr;
280	}	280	}
281		281
282	static __init void	282	static __init void
283	qic_setup(void)	283	qic_setup(void)
284	{	284	{
285	if(!is_cpu_quad()) {	285	if(!is_cpu_quad()) {
286	/* not a quad, no setup */	286	/* not a quad, no setup */
287	return;	287	return;
288	}	288	}
289	outb(QIC_DEFAULT_MASK0, QIC_MASK_REGISTER0);	289	outb(QIC_DEFAULT_MASK0, QIC_MASK_REGISTER0);
290	outb(QIC_CPI_ENABLE, QIC_MASK_REGISTER1);	290	outb(QIC_CPI_ENABLE, QIC_MASK_REGISTER1);
291		291
292	if(is_cpu_extended()) {	292	if(is_cpu_extended()) {
293	/* the QIC duplicate of the VIC base register */	293	/* the QIC duplicate of the VIC base register */
294	outb(VIC_DEFAULT_CPI_BASE, QIC_VIC_CPI_BASE_REGISTER);	294	outb(VIC_DEFAULT_CPI_BASE, QIC_VIC_CPI_BASE_REGISTER);
295	outb(QIC_DEFAULT_CPI_BASE, QIC_CPI_BASE_REGISTER);	295	outb(QIC_DEFAULT_CPI_BASE, QIC_CPI_BASE_REGISTER);
296		296
297	/* FIXME: should set up the QIC timer and memory parity	297	/* FIXME: should set up the QIC timer and memory parity
298	* error vectors here */	298	* error vectors here */
299	}	299	}
300	}	300	}
301		301
302	static __init void	302	static __init void
303	vic_setup_pic(void)	303	vic_setup_pic(void)
304	{	304	{
305	outb(1, VIC_REDIRECT_REGISTER_1);	305	outb(1, VIC_REDIRECT_REGISTER_1);
306	/* clear the claim registers for dynamic routing */	306	/* clear the claim registers for dynamic routing */
307	outb(0, VIC_CLAIM_REGISTER_0);	307	outb(0, VIC_CLAIM_REGISTER_0);
308	outb(0, VIC_CLAIM_REGISTER_1);	308	outb(0, VIC_CLAIM_REGISTER_1);
309		309
310	outb(0, VIC_PRIORITY_REGISTER);	310	outb(0, VIC_PRIORITY_REGISTER);
311	/* Set the Primary and Secondary Microchannel vector	311	/* Set the Primary and Secondary Microchannel vector
312	* bases to be the same as the ordinary interrupts	312	* bases to be the same as the ordinary interrupts
313	*	313	*
314	* FIXME: This would be more efficient using separate	314	* FIXME: This would be more efficient using separate
315	* vectors. */	315	* vectors. */
316	outb(FIRST_EXTERNAL_VECTOR, VIC_PRIMARY_MC_BASE);	316	outb(FIRST_EXTERNAL_VECTOR, VIC_PRIMARY_MC_BASE);
317	outb(FIRST_EXTERNAL_VECTOR, VIC_SECONDARY_MC_BASE);	317	outb(FIRST_EXTERNAL_VECTOR, VIC_SECONDARY_MC_BASE);
318	/* Now initiallise the master PIC belonging to this CPU by	318	/* Now initiallise the master PIC belonging to this CPU by
319	* sending the four ICWs */	319	* sending the four ICWs */
320		320
321	/* ICW1: level triggered, ICW4 needed */	321	/* ICW1: level triggered, ICW4 needed */
322	outb(0x19, 0x20);	322	outb(0x19, 0x20);
323		323
324	/* ICW2: vector base */	324	/* ICW2: vector base */
325	outb(FIRST_EXTERNAL_VECTOR, 0x21);	325	outb(FIRST_EXTERNAL_VECTOR, 0x21);
326		326
327	/* ICW3: slave at line 2 */	327	/* ICW3: slave at line 2 */
328	outb(0x04, 0x21);	328	outb(0x04, 0x21);
329		329
330	/* ICW4: 8086 mode */	330	/* ICW4: 8086 mode */
331	outb(0x01, 0x21);	331	outb(0x01, 0x21);
332		332
333	/* now the same for the slave PIC */	333	/* now the same for the slave PIC */
334		334
335	/* ICW1: level trigger, ICW4 needed */	335	/* ICW1: level trigger, ICW4 needed */
336	outb(0x19, 0xA0);	336	outb(0x19, 0xA0);
337		337
338	/* ICW2: slave vector base */	338	/* ICW2: slave vector base */
339	outb(FIRST_EXTERNAL_VECTOR + 8, 0xA1);	339	outb(FIRST_EXTERNAL_VECTOR + 8, 0xA1);
340		340
341	/* ICW3: slave ID */	341	/* ICW3: slave ID */
342	outb(0x02, 0xA1);	342	outb(0x02, 0xA1);
343		343
344	/* ICW4: 8086 mode */	344	/* ICW4: 8086 mode */
345	outb(0x01, 0xA1);	345	outb(0x01, 0xA1);
346	}	346	}
347		347
348	static void	348	static void
349	do_quad_bootstrap(void)	349	do_quad_bootstrap(void)
350	{	350	{
351	if(is_cpu_quad() && is_cpu_vic_boot()) {	351	if(is_cpu_quad() && is_cpu_vic_boot()) {
352	int i;	352	int i;
353	unsigned long flags;	353	unsigned long flags;
354	__u8 cpuid = hard_smp_processor_id();	354	__u8 cpuid = hard_smp_processor_id();
355		355
356	local_irq_save(flags);	356	local_irq_save(flags);
357		357
358	for(i = 0; i<4; i++) {	358	for(i = 0; i<4; i++) {
359	/* FIXME: this would be >>3 &0x7 on the 32 way */	359	/* FIXME: this would be >>3 &0x7 on the 32 way */
360	if(((cpuid >> 2) & 0x03) == i)	360	if(((cpuid >> 2) & 0x03) == i)
361	/* don't lower our own mask! */	361	/* don't lower our own mask! */
362	continue;	362	continue;
363		363
364	/* masquerade as local Quad CPU */	364	/* masquerade as local Quad CPU */
365	outb(QIC_CPUID_ENABLE \| i, QIC_PROCESSOR_ID);	365	outb(QIC_CPUID_ENABLE \| i, QIC_PROCESSOR_ID);
366	/* enable the startup CPI */	366	/* enable the startup CPI */
367	outb(QIC_BOOT_CPI_MASK, QIC_MASK_REGISTER1);	367	outb(QIC_BOOT_CPI_MASK, QIC_MASK_REGISTER1);
368	/* restore cpu id */	368	/* restore cpu id */
369	outb(0, QIC_PROCESSOR_ID);	369	outb(0, QIC_PROCESSOR_ID);
370	}	370	}
371	local_irq_restore(flags);	371	local_irq_restore(flags);
372	}	372	}
373	}	373	}
374		374
375		375
376	/* Set up all the basic stuff: read the SMP config and make all the	376	/* Set up all the basic stuff: read the SMP config and make all the
377	* SMP information reflect only the boot cpu. All others will be	377	* SMP information reflect only the boot cpu. All others will be
378	* brought on-line later. */	378	* brought on-line later. */
379	void __init	379	void __init
380	find_smp_config(void)	380	find_smp_config(void)
381	{	381	{
382	int i;	382	int i;
383		383
384	boot_cpu_id = hard_smp_processor_id();	384	boot_cpu_id = hard_smp_processor_id();
385		385
386	printk("VOYAGER SMP: Boot cpu is %d\n", boot_cpu_id);	386	printk("VOYAGER SMP: Boot cpu is %d\n", boot_cpu_id);
387		387
388	/* initialize the CPU structures (moved from smp_boot_cpus) */	388	/* initialize the CPU structures (moved from smp_boot_cpus) */
389	for(i=0; i<NR_CPUS; i++) {	389	for(i=0; i<NR_CPUS; i++) {
390	cpu_irq_affinity[i] = ~0;	390	cpu_irq_affinity[i] = ~0;
391	}	391	}
392	cpu_online_map = cpumask_of_cpu(boot_cpu_id);	392	cpu_online_map = cpumask_of_cpu(boot_cpu_id);
393		393
394	/* The boot CPU must be extended */	394	/* The boot CPU must be extended */
395	voyager_extended_vic_processors = 1<<boot_cpu_id;	395	voyager_extended_vic_processors = 1<<boot_cpu_id;
396	/* initially, all of the first 8 cpu's can boot */	396	/* initially, all of the first 8 cpu's can boot */
397	voyager_allowed_boot_processors = 0xff;	397	voyager_allowed_boot_processors = 0xff;
398	/* set up everything for just this CPU, we can alter	398	/* set up everything for just this CPU, we can alter
399	* this as we start the other CPUs later */	399	* this as we start the other CPUs later */
400	/* now get the CPU disposition from the extended CMOS */	400	/* now get the CPU disposition from the extended CMOS */
401	cpus_addr(phys_cpu_present_map)[0] = voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK);	401	cpus_addr(phys_cpu_present_map)[0] = voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK);
402	cpus_addr(phys_cpu_present_map)[0] \|= voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK + 1) << 8;	402	cpus_addr(phys_cpu_present_map)[0] \|= voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK + 1) << 8;
403	cpus_addr(phys_cpu_present_map)[0] \|= voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK + 2) << 16;	403	cpus_addr(phys_cpu_present_map)[0] \|= voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK + 2) << 16;
404	cpus_addr(phys_cpu_present_map)[0] \|= voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK + 3) << 24;	404	cpus_addr(phys_cpu_present_map)[0] \|= voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK + 3) << 24;
405	printk("VOYAGER SMP: phys_cpu_present_map = 0x%lx\n", cpus_addr(phys_cpu_present_map)[0]);	405	printk("VOYAGER SMP: phys_cpu_present_map = 0x%lx\n", cpus_addr(phys_cpu_present_map)[0]);
406	/* Here we set up the VIC to enable SMP */	406	/* Here we set up the VIC to enable SMP */
407	/* enable the CPIs by writing the base vector to their register */	407	/* enable the CPIs by writing the base vector to their register */
408	outb(VIC_DEFAULT_CPI_BASE, VIC_CPI_BASE_REGISTER);	408	outb(VIC_DEFAULT_CPI_BASE, VIC_CPI_BASE_REGISTER);
409	outb(1, VIC_REDIRECT_REGISTER_1);	409	outb(1, VIC_REDIRECT_REGISTER_1);
410	/* set the claim registers for static routing --- Boot CPU gets	410	/* set the claim registers for static routing --- Boot CPU gets
411	* all interrupts untill all other CPUs started */	411	* all interrupts untill all other CPUs started */
412	outb(0xff, VIC_CLAIM_REGISTER_0);	412	outb(0xff, VIC_CLAIM_REGISTER_0);
413	outb(0xff, VIC_CLAIM_REGISTER_1);	413	outb(0xff, VIC_CLAIM_REGISTER_1);
414	/* Set the Primary and Secondary Microchannel vector	414	/* Set the Primary and Secondary Microchannel vector
415	* bases to be the same as the ordinary interrupts	415	* bases to be the same as the ordinary interrupts
416	*	416	*
417	* FIXME: This would be more efficient using separate	417	* FIXME: This would be more efficient using separate
418	* vectors. */	418	* vectors. */
419	outb(FIRST_EXTERNAL_VECTOR, VIC_PRIMARY_MC_BASE);	419	outb(FIRST_EXTERNAL_VECTOR, VIC_PRIMARY_MC_BASE);
420	outb(FIRST_EXTERNAL_VECTOR, VIC_SECONDARY_MC_BASE);	420	outb(FIRST_EXTERNAL_VECTOR, VIC_SECONDARY_MC_BASE);
421		421
422	/* Finally tell the firmware that we're driving */	422	/* Finally tell the firmware that we're driving */
423	outb(inb(VOYAGER_SUS_IN_CONTROL_PORT) \| VOYAGER_IN_CONTROL_FLAG,	423	outb(inb(VOYAGER_SUS_IN_CONTROL_PORT) \| VOYAGER_IN_CONTROL_FLAG,
424	VOYAGER_SUS_IN_CONTROL_PORT);	424	VOYAGER_SUS_IN_CONTROL_PORT);
425		425
426	current_thread_info()->cpu = boot_cpu_id;	426	current_thread_info()->cpu = boot_cpu_id;
427	}	427	}
428		428
429	/*	429	/*
430	* The bootstrap kernel entry code has set these up. Save them	430	* The bootstrap kernel entry code has set these up. Save them
431	* for a given CPU, id is physical */	431	* for a given CPU, id is physical */
432	void __init	432	void __init
433	smp_store_cpu_info(int id)	433	smp_store_cpu_info(int id)
434	{	434	{
435	struct cpuinfo_x86 *c=&cpu_data[id];	435	struct cpuinfo_x86 *c=&cpu_data[id];
436		436
437	*c = boot_cpu_data;	437	*c = boot_cpu_data;
438		438
439	identify_cpu(c);	439	identify_cpu(c);
440	}	440	}
441		441
442	/* set up the trampoline and return the physical address of the code */	442	/* set up the trampoline and return the physical address of the code */
443	static __u32 __init	443	static __u32 __init
444	setup_trampoline(void)	444	setup_trampoline(void)
445	{	445	{
446	/* these two are global symbols in trampoline.S */	446	/* these two are global symbols in trampoline.S */
447	extern __u8 trampoline_end[];	447	extern __u8 trampoline_end[];
448	extern __u8 trampoline_data[];	448	extern __u8 trampoline_data[];
449		449
450	memcpy((__u8 *)trampoline_base, trampoline_data,	450	memcpy((__u8 *)trampoline_base, trampoline_data,
451	trampoline_end - trampoline_data);	451	trampoline_end - trampoline_data);
452	return virt_to_phys((__u8 *)trampoline_base);	452	return virt_to_phys((__u8 *)trampoline_base);
453	}	453	}
454		454
455	/* Routine initially called when a non-boot CPU is brought online */	455	/* Routine initially called when a non-boot CPU is brought online */
456	static void __init	456	static void __init
457	start_secondary(void *unused)	457	start_secondary(void *unused)
458	{	458	{
459	__u8 cpuid = hard_smp_processor_id();	459	__u8 cpuid = hard_smp_processor_id();
460	/* external functions not defined in the headers */	460	/* external functions not defined in the headers */
461	extern void calibrate_delay(void);	461	extern void calibrate_delay(void);
462		462
463	cpu_init();	463	cpu_init();
464		464
465	/* OK, we're in the routine */	465	/* OK, we're in the routine */
466	ack_CPI(VIC_CPU_BOOT_CPI);	466	ack_CPI(VIC_CPU_BOOT_CPI);
467		467
468	/* setup the 8259 master slave pair belonging to this CPU ---	468	/* setup the 8259 master slave pair belonging to this CPU ---
469	* we won't actually receive any until the boot CPU	469	* we won't actually receive any until the boot CPU
470	* relinquishes it's static routing mask */	470	* relinquishes it's static routing mask */
471	vic_setup_pic();	471	vic_setup_pic();
472		472
473	qic_setup();	473	qic_setup();
474		474
475	if(is_cpu_quad() && !is_cpu_vic_boot()) {	475	if(is_cpu_quad() && !is_cpu_vic_boot()) {
476	/* clear the boot CPI */	476	/* clear the boot CPI */
477	__u8 dummy;	477	__u8 dummy;
478		478
479	dummy = voyager_quad_cpi_addr[cpuid]->qic_cpi[VIC_CPU_BOOT_CPI].cpi;	479	dummy = voyager_quad_cpi_addr[cpuid]->qic_cpi[VIC_CPU_BOOT_CPI].cpi;
480	printk("read dummy %d\n", dummy);	480	printk("read dummy %d\n", dummy);
481	}	481	}
482		482
483	/* lower the mask to receive CPIs */	483	/* lower the mask to receive CPIs */
484	vic_enable_cpi();	484	vic_enable_cpi();
485		485
486	VDEBUG(("VOYAGER SMP: CPU%d, stack at about %p\n", cpuid, &cpuid));	486	VDEBUG(("VOYAGER SMP: CPU%d, stack at about %p\n", cpuid, &cpuid));
487		487
488	/* enable interrupts */	488	/* enable interrupts */
489	local_irq_enable();	489	local_irq_enable();
490		490
491	/* get our bogomips */	491	/* get our bogomips */
492	calibrate_delay();	492	calibrate_delay();
493		493
494	/* save our processor parameters */	494	/* save our processor parameters */
495	smp_store_cpu_info(cpuid);	495	smp_store_cpu_info(cpuid);
496		496
497	/* if we're a quad, we may need to bootstrap other CPUs */	497	/* if we're a quad, we may need to bootstrap other CPUs */
498	do_quad_bootstrap();	498	do_quad_bootstrap();
499		499
500	/* FIXME: this is rather a poor hack to prevent the CPU	500	/* FIXME: this is rather a poor hack to prevent the CPU
501	* activating softirqs while it's supposed to be waiting for	501	* activating softirqs while it's supposed to be waiting for
502	* permission to proceed. Without this, the new per CPU stuff	502	* permission to proceed. Without this, the new per CPU stuff
503	* in the softirqs will fail */	503	* in the softirqs will fail */
504	local_irq_disable();	504	local_irq_disable();
505	cpu_set(cpuid, cpu_callin_map);	505	cpu_set(cpuid, cpu_callin_map);
506		506
507	/* signal that we're done */	507	/* signal that we're done */
508	cpu_booted_map = 1;	508	cpu_booted_map = 1;
509		509
510	while (!cpu_isset(cpuid, smp_commenced_mask))	510	while (!cpu_isset(cpuid, smp_commenced_mask))
511	rep_nop();	511	rep_nop();
512	local_irq_enable();	512	local_irq_enable();
513		513
514	local_flush_tlb();	514	local_flush_tlb();
515		515
516	cpu_set(cpuid, cpu_online_map);	516	cpu_set(cpuid, cpu_online_map);
517	wmb();	517	wmb();
518	cpu_idle();	518	cpu_idle();
519	}	519	}
520		520
521		521
522	/* Routine to kick start the given CPU and wait for it to report ready	522	/* Routine to kick start the given CPU and wait for it to report ready
523	* (or timeout in startup). When this routine returns, the requested	523	* (or timeout in startup). When this routine returns, the requested
524	* CPU is either fully running and configured or known to be dead.	524	* CPU is either fully running and configured or known to be dead.
525	*	525	*
526	* We call this routine sequentially 1 CPU at a time, so no need for	526	* We call this routine sequentially 1 CPU at a time, so no need for
527	* locking */	527	* locking */
528		528
529	static void __init	529	static void __init
530	do_boot_cpu(__u8 cpu)	530	do_boot_cpu(__u8 cpu)
531	{	531	{
532	struct task_struct *idle;	532	struct task_struct *idle;
533	int timeout;	533	int timeout;
534	unsigned long flags;	534	unsigned long flags;
535	int quad_boot = (1<<cpu) & voyager_quad_processors	535	int quad_boot = (1<<cpu) & voyager_quad_processors
536	& ~( voyager_extended_vic_processors	536	& ~( voyager_extended_vic_processors
537	& voyager_allowed_boot_processors);	537	& voyager_allowed_boot_processors);
538		538
539	/* For the 486, we can't use the 4Mb page table trick, so	539	/* For the 486, we can't use the 4Mb page table trick, so
540	* must map a region of memory */	540	* must map a region of memory */
541	#ifdef CONFIG_M486	541	#ifdef CONFIG_M486
542	int i;	542	int i;
543	unsigned long page_table_copies = (unsigned long )	543	unsigned long page_table_copies = (unsigned long )
544	__get_free_page(GFP_KERNEL);	544	__get_free_page(GFP_KERNEL);
545	#endif	545	#endif
546	pgd_t orig_swapper_pg_dir0;	546	pgd_t orig_swapper_pg_dir0;
547		547
548	/* This is an area in head.S which was used to set up the	548	/* This is an area in head.S which was used to set up the
549	* initial kernel stack. We need to alter this to give the	549	* initial kernel stack. We need to alter this to give the
550	* booting CPU a new stack (taken from its idle process) */	550	* booting CPU a new stack (taken from its idle process) */
551	extern struct {	551	extern struct {
552	__u8 *esp;	552	__u8 *esp;
553	unsigned short ss;	553	unsigned short ss;
554	} stack_start;	554	} stack_start;
555	/* This is the format of the CPI IDT gate (in real mode) which	555	/* This is the format of the CPI IDT gate (in real mode) which
556	* we're hijacking to boot the CPU */	556	* we're hijacking to boot the CPU */
557	union IDTFormat {	557	union IDTFormat {
558	struct seg {	558	struct seg {
559	__u16 Offset;	559	__u16 Offset;
560	__u16 Segment;	560	__u16 Segment;
561	} idt;	561	} idt;
562	__u32 val;	562	__u32 val;
563	} hijack_source;	563	} hijack_source;
564		564
565	__u32 *hijack_vector;	565	__u32 *hijack_vector;
566	__u32 start_phys_address = setup_trampoline();	566	__u32 start_phys_address = setup_trampoline();
567		567
568	/* There's a clever trick to this: The linux trampoline is	568	/* There's a clever trick to this: The linux trampoline is
569	* compiled to begin at absolute location zero, so make the	569	* compiled to begin at absolute location zero, so make the
570	* address zero but have the data segment selector compensate	570	* address zero but have the data segment selector compensate
571	* for the actual address */	571	* for the actual address */
572	hijack_source.idt.Offset = start_phys_address & 0x000F;	572	hijack_source.idt.Offset = start_phys_address & 0x000F;
573	hijack_source.idt.Segment = (start_phys_address >> 4) & 0xFFFF;	573	hijack_source.idt.Segment = (start_phys_address >> 4) & 0xFFFF;
574		574
575	cpucount++;	575	cpucount++;
576	idle = fork_idle(cpu);	576	idle = fork_idle(cpu);
577	if(IS_ERR(idle))	577	if(IS_ERR(idle))
578	panic("failed fork for CPU%d", cpu);	578	panic("failed fork for CPU%d", cpu);
579	idle->thread.eip = (unsigned long) start_secondary;	579	idle->thread.eip = (unsigned long) start_secondary;
580	/* init_tasks (in sched.c) is indexed logically */	580	/* init_tasks (in sched.c) is indexed logically */
581	stack_start.esp = (void *) idle->thread.esp;	581	stack_start.esp = (void *) idle->thread.esp;
582		582
583	irq_ctx_init(cpu);	583	irq_ctx_init(cpu);
584		584
585	/* Note: Don't modify initial ss override */	585	/* Note: Don't modify initial ss override */
586	VDEBUG(("VOYAGER SMP: Booting CPU%d at 0x%lx[%x:%x], stack %p\n", cpu,	586	VDEBUG(("VOYAGER SMP: Booting CPU%d at 0x%lx[%x:%x], stack %p\n", cpu,
587	(unsigned long)hijack_source.val, hijack_source.idt.Segment,	587	(unsigned long)hijack_source.val, hijack_source.idt.Segment,
588	hijack_source.idt.Offset, stack_start.esp));	588	hijack_source.idt.Offset, stack_start.esp));
589	/* set the original swapper_pg_dir[0] to map 0 to 4Mb transparently	589	/* set the original swapper_pg_dir[0] to map 0 to 4Mb transparently
590	* (so that the booting CPU can find start_32 */	590	* (so that the booting CPU can find start_32 */
591	orig_swapper_pg_dir0 = swapper_pg_dir[0];	591	orig_swapper_pg_dir0 = swapper_pg_dir[0];
592	#ifdef CONFIG_M486	592	#ifdef CONFIG_M486
593	if(page_table_copies == NULL)	593	if(page_table_copies == NULL)
594	panic("No free memory for 486 page tables\n");	594	panic("No free memory for 486 page tables\n");
595	for(i = 0; i < PAGE_SIZE/sizeof(unsigned long); i++)	595	for(i = 0; i < PAGE_SIZE/sizeof(unsigned long); i++)
596	page_table_copies[i] = (i * PAGE_SIZE)	596	page_table_copies[i] = (i * PAGE_SIZE)
597	\| _PAGE_RW \| _PAGE_USER \| _PAGE_PRESENT;	597	\| _PAGE_RW \| _PAGE_USER \| _PAGE_PRESENT;
598		598
599	((unsigned long *)swapper_pg_dir)[0] =	599	((unsigned long *)swapper_pg_dir)[0] =
600	((virt_to_phys(page_table_copies)) & PAGE_MASK)	600	((virt_to_phys(page_table_copies)) & PAGE_MASK)
601	\| _PAGE_RW \| _PAGE_USER \| _PAGE_PRESENT;	601	\| _PAGE_RW \| _PAGE_USER \| _PAGE_PRESENT;
602	#else	602	#else
603	((unsigned long *)swapper_pg_dir)[0] =	603	((unsigned long *)swapper_pg_dir)[0] =
604	(virt_to_phys(pg0) & PAGE_MASK)	604	(virt_to_phys(pg0) & PAGE_MASK)
605	\| _PAGE_RW \| _PAGE_USER \| _PAGE_PRESENT;	605	\| _PAGE_RW \| _PAGE_USER \| _PAGE_PRESENT;
606	#endif	606	#endif
607		607
608	if(quad_boot) {	608	if(quad_boot) {
609	printk("CPU %d: non extended Quad boot\n", cpu);	609	printk("CPU %d: non extended Quad boot\n", cpu);
610	hijack_vector = (__u32 )phys_to_virt((VIC_CPU_BOOT_CPI + QIC_DEFAULT_CPI_BASE)4);	610	hijack_vector = (__u32 )phys_to_virt((VIC_CPU_BOOT_CPI + QIC_DEFAULT_CPI_BASE)4);
611	*hijack_vector = hijack_source.val;	611	*hijack_vector = hijack_source.val;
612	} else {	612	} else {
613	printk("CPU%d: extended VIC boot\n", cpu);	613	printk("CPU%d: extended VIC boot\n", cpu);
614	hijack_vector = (__u32 )phys_to_virt((VIC_CPU_BOOT_CPI + VIC_DEFAULT_CPI_BASE)4);	614	hijack_vector = (__u32 )phys_to_virt((VIC_CPU_BOOT_CPI + VIC_DEFAULT_CPI_BASE)4);
615	*hijack_vector = hijack_source.val;	615	*hijack_vector = hijack_source.val;
616	/* VIC errata, may also receive interrupt at this address */	616	/* VIC errata, may also receive interrupt at this address */
617	hijack_vector = (__u32 )phys_to_virt((VIC_CPU_BOOT_ERRATA_CPI + VIC_DEFAULT_CPI_BASE)4);	617	hijack_vector = (__u32 )phys_to_virt((VIC_CPU_BOOT_ERRATA_CPI + VIC_DEFAULT_CPI_BASE)4);
618	*hijack_vector = hijack_source.val;	618	*hijack_vector = hijack_source.val;
619	}	619	}
620	/* All non-boot CPUs start with interrupts fully masked. Need	620	/* All non-boot CPUs start with interrupts fully masked. Need
621	* to lower the mask of the CPI we're about to send. We do	621	* to lower the mask of the CPI we're about to send. We do
622	* this in the VIC by masquerading as the processor we're	622	* this in the VIC by masquerading as the processor we're
623	* about to boot and lowering its interrupt mask */	623	* about to boot and lowering its interrupt mask */
624	local_irq_save(flags);	624	local_irq_save(flags);
625	if(quad_boot) {	625	if(quad_boot) {
626	send_one_QIC_CPI(cpu, VIC_CPU_BOOT_CPI);	626	send_one_QIC_CPI(cpu, VIC_CPU_BOOT_CPI);
627	} else {	627	} else {
628	outb(VIC_CPU_MASQUERADE_ENABLE \| cpu, VIC_PROCESSOR_ID);	628	outb(VIC_CPU_MASQUERADE_ENABLE \| cpu, VIC_PROCESSOR_ID);
629	/* here we're altering registers belonging to `cpu' */	629	/* here we're altering registers belonging to `cpu' */
630		630
631	outb(VIC_BOOT_INTERRUPT_MASK, 0x21);	631	outb(VIC_BOOT_INTERRUPT_MASK, 0x21);
632	/* now go back to our original identity */	632	/* now go back to our original identity */
633	outb(boot_cpu_id, VIC_PROCESSOR_ID);	633	outb(boot_cpu_id, VIC_PROCESSOR_ID);
634		634
635	/* and boot the CPU */	635	/* and boot the CPU */
636		636
637	send_CPI((1<<cpu), VIC_CPU_BOOT_CPI);	637	send_CPI((1<<cpu), VIC_CPU_BOOT_CPI);
638	}	638	}
639	cpu_booted_map = 0;	639	cpu_booted_map = 0;
640	local_irq_restore(flags);	640	local_irq_restore(flags);
641		641
642	/* now wait for it to become ready (or timeout) */	642	/* now wait for it to become ready (or timeout) */
643	for(timeout = 0; timeout < 50000; timeout++) {	643	for(timeout = 0; timeout < 50000; timeout++) {
644	if(cpu_booted_map)	644	if(cpu_booted_map)
645	break;	645	break;
646	udelay(100);	646	udelay(100);
647	}	647	}
648	/* reset the page table */	648	/* reset the page table */
649	swapper_pg_dir[0] = orig_swapper_pg_dir0;	649	swapper_pg_dir[0] = orig_swapper_pg_dir0;
650	local_flush_tlb();	650	local_flush_tlb();
651	#ifdef CONFIG_M486	651	#ifdef CONFIG_M486
652	free_page((unsigned long)page_table_copies);	652	free_page((unsigned long)page_table_copies);
653	#endif	653	#endif
654		654
655	if (cpu_booted_map) {	655	if (cpu_booted_map) {
656	VDEBUG(("CPU%d: Booted successfully, back in CPU %d\n",	656	VDEBUG(("CPU%d: Booted successfully, back in CPU %d\n",
657	cpu, smp_processor_id()));	657	cpu, smp_processor_id()));
658		658
659	printk("CPU%d: ", cpu);	659	printk("CPU%d: ", cpu);
660	print_cpu_info(&cpu_data[cpu]);	660	print_cpu_info(&cpu_data[cpu]);
661	wmb();	661	wmb();
662	cpu_set(cpu, cpu_callout_map);	662	cpu_set(cpu, cpu_callout_map);
663	}	663	}
664	else {	664	else {
665	printk("CPU%d FAILED TO BOOT: ", cpu);	665	printk("CPU%d FAILED TO BOOT: ", cpu);
666	if (((volatile unsigned char )phys_to_virt(start_phys_address))==0xA5)	666	if (((volatile unsigned char )phys_to_virt(start_phys_address))==0xA5)
667	printk("Stuck.\n");	667	printk("Stuck.\n");
668	else	668	else
669	printk("Not responding.\n");	669	printk("Not responding.\n");
670		670
671	cpucount--;	671	cpucount--;
672	}	672	}
673	}	673	}
674		674
675	void __init	675	void __init
676	smp_boot_cpus(void)	676	smp_boot_cpus(void)
677	{	677	{
678	int i;	678	int i;
679		679
680	/* CAT BUS initialisation must be done after the memory */	680	/* CAT BUS initialisation must be done after the memory */
681	/* FIXME: The L4 has a catbus too, it just needs to be	681	/* FIXME: The L4 has a catbus too, it just needs to be
682	* accessed in a totally different way */	682	* accessed in a totally different way */
683	if(voyager_level == 5) {	683	if(voyager_level == 5) {
684	voyager_cat_init();	684	voyager_cat_init();
685		685
686	/* now that the cat has probed the Voyager System Bus, sanity	686	/* now that the cat has probed the Voyager System Bus, sanity
687	* check the cpu map */	687	* check the cpu map */
688	if( ((voyager_quad_processors \| voyager_extended_vic_processors)	688	if( ((voyager_quad_processors \| voyager_extended_vic_processors)
689	& cpus_addr(phys_cpu_present_map)[0]) != cpus_addr(phys_cpu_present_map)[0]) {	689	& cpus_addr(phys_cpu_present_map)[0]) != cpus_addr(phys_cpu_present_map)[0]) {
690	/* should panic */	690	/* should panic */
691	printk("\n\n*WARNING* Sanity check of CPU present map FAILED\n");	691	printk("\n\n*WARNING* Sanity check of CPU present map FAILED\n");
692	}	692	}
693	} else if(voyager_level == 4)	693	} else if(voyager_level == 4)
694	voyager_extended_vic_processors = cpus_addr(phys_cpu_present_map)[0];	694	voyager_extended_vic_processors = cpus_addr(phys_cpu_present_map)[0];
695		695
696	/* this sets up the idle task to run on the current cpu */	696	/* this sets up the idle task to run on the current cpu */
697	voyager_extended_cpus = 1;	697	voyager_extended_cpus = 1;
698	/* Remove the global_irq_holder setting, it triggers a BUG() on	698	/* Remove the global_irq_holder setting, it triggers a BUG() on
699	* schedule at the moment */	699	* schedule at the moment */
700	//global_irq_holder = boot_cpu_id;	700	//global_irq_holder = boot_cpu_id;
701		701
702	/* FIXME: Need to do something about this but currently only works	702	/* FIXME: Need to do something about this but currently only works
703	* on CPUs with a tsc which none of mine have.	703	* on CPUs with a tsc which none of mine have.
704	smp_tune_scheduling();	704	smp_tune_scheduling();
705	*/	705	*/
706	smp_store_cpu_info(boot_cpu_id);	706	smp_store_cpu_info(boot_cpu_id);
707	printk("CPU%d: ", boot_cpu_id);	707	printk("CPU%d: ", boot_cpu_id);
708	print_cpu_info(&cpu_data[boot_cpu_id]);	708	print_cpu_info(&cpu_data[boot_cpu_id]);
709		709
710	if(is_cpu_quad()) {	710	if(is_cpu_quad()) {
711	/* booting on a Quad CPU */	711	/* booting on a Quad CPU */
712	printk("VOYAGER SMP: Boot CPU is Quad\n");	712	printk("VOYAGER SMP: Boot CPU is Quad\n");
713	qic_setup();	713	qic_setup();
714	do_quad_bootstrap();	714	do_quad_bootstrap();
715	}	715	}
716		716
717	/* enable our own CPIs */	717	/* enable our own CPIs */
718	vic_enable_cpi();	718	vic_enable_cpi();
719		719
720	cpu_set(boot_cpu_id, cpu_online_map);	720	cpu_set(boot_cpu_id, cpu_online_map);
721	cpu_set(boot_cpu_id, cpu_callout_map);	721	cpu_set(boot_cpu_id, cpu_callout_map);
722		722
723	/* loop over all the extended VIC CPUs and boot them. The	723	/* loop over all the extended VIC CPUs and boot them. The
724	* Quad CPUs must be bootstrapped by their extended VIC cpu */	724	* Quad CPUs must be bootstrapped by their extended VIC cpu */
725	for(i = 0; i < NR_CPUS; i++) {	725	for(i = 0; i < NR_CPUS; i++) {
726	if(i == boot_cpu_id \|\| !cpu_isset(i, phys_cpu_present_map))	726	if(i == boot_cpu_id \|\| !cpu_isset(i, phys_cpu_present_map))
727	continue;	727	continue;
728	do_boot_cpu(i);	728	do_boot_cpu(i);
729	/* This udelay seems to be needed for the Quad boots	729	/* This udelay seems to be needed for the Quad boots
730	* don't remove unless you know what you're doing */	730	* don't remove unless you know what you're doing */
731	udelay(1000);	731	udelay(1000);
732	}	732	}
733	/* we could compute the total bogomips here, but why bother?,	733	/* we could compute the total bogomips here, but why bother?,
734	* Code added from smpboot.c */	734	* Code added from smpboot.c */
735	{	735	{
736	unsigned long bogosum = 0;	736	unsigned long bogosum = 0;
737	for (i = 0; i < NR_CPUS; i++)	737	for (i = 0; i < NR_CPUS; i++)
738	if (cpu_isset(i, cpu_online_map))	738	if (cpu_isset(i, cpu_online_map))
739	bogosum += cpu_data[i].loops_per_jiffy;	739	bogosum += cpu_data[i].loops_per_jiffy;
740	printk(KERN_INFO "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",	740	printk(KERN_INFO "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
741	cpucount+1,	741	cpucount+1,
742	bogosum/(500000/HZ),	742	bogosum/(500000/HZ),
743	(bogosum/(5000/HZ))%100);	743	(bogosum/(5000/HZ))%100);
744	}	744	}
745	voyager_extended_cpus = hweight32(voyager_extended_vic_processors);	745	voyager_extended_cpus = hweight32(voyager_extended_vic_processors);
746	printk("VOYAGER: Extended (interrupt handling CPUs): %d, non-extended: %d\n", voyager_extended_cpus, num_booting_cpus() - voyager_extended_cpus);	746	printk("VOYAGER: Extended (interrupt handling CPUs): %d, non-extended: %d\n", voyager_extended_cpus, num_booting_cpus() - voyager_extended_cpus);
747	/* that's it, switch to symmetric mode */	747	/* that's it, switch to symmetric mode */
748	outb(0, VIC_PRIORITY_REGISTER);	748	outb(0, VIC_PRIORITY_REGISTER);
749	outb(0, VIC_CLAIM_REGISTER_0);	749	outb(0, VIC_CLAIM_REGISTER_0);
750	outb(0, VIC_CLAIM_REGISTER_1);	750	outb(0, VIC_CLAIM_REGISTER_1);
751		751
752	VDEBUG(("VOYAGER SMP: Booted with %d CPUs\n", num_booting_cpus()));	752	VDEBUG(("VOYAGER SMP: Booted with %d CPUs\n", num_booting_cpus()));
753	}	753	}
754		754
755	/* Reload the secondary CPUs task structure (this function does not	755	/* Reload the secondary CPUs task structure (this function does not
756	* return ) */	756	* return ) */
757	void __init	757	void __init
758	initialize_secondary(void)	758	initialize_secondary(void)
759	{	759	{
760	#if 0	760	#if 0
761	// AC kernels only	761	// AC kernels only
762	set_current(hard_get_current());	762	set_current(hard_get_current());
763	#endif	763	#endif
764		764
765	/*	765	/*
766	* We don't actually need to load the full TSS,	766	* We don't actually need to load the full TSS,
767	* basically just the stack pointer and the eip.	767	* basically just the stack pointer and the eip.
768	*/	768	*/
769		769
770	asm volatile(	770	asm volatile(
771	"movl %0,%%esp\n\t"	771	"movl %0,%%esp\n\t"
772	"jmp *%1"	772	"jmp *%1"
773	:	773	:
774	:"r" (current->thread.esp),"r" (current->thread.eip));	774	:"r" (current->thread.esp),"r" (current->thread.eip));
775	}	775	}
776		776
777	/* handle a Voyager SYS_INT -- If we don't, the base board will	777	/* handle a Voyager SYS_INT -- If we don't, the base board will
778	* panic the system.	778	* panic the system.
779	*	779	*
780	* System interrupts occur because some problem was detected on the	780	* System interrupts occur because some problem was detected on the
781	* various busses. To find out what you have to probe all the	781	* various busses. To find out what you have to probe all the
782	* hardware via the CAT bus. FIXME: At the moment we do nothing. */	782	* hardware via the CAT bus. FIXME: At the moment we do nothing. */
783	fastcall void	783	fastcall void
784	smp_vic_sys_interrupt(struct pt_regs *regs)	784	smp_vic_sys_interrupt(struct pt_regs *regs)
785	{	785	{
786	ack_CPI(VIC_SYS_INT);	786	ack_CPI(VIC_SYS_INT);
787	printk("Voyager SYSTEM INTERRUPT\n");	787	printk("Voyager SYSTEM INTERRUPT\n");
788	}	788	}
789		789
790	/* Handle a voyager CMN_INT; These interrupts occur either because of	790	/* Handle a voyager CMN_INT; These interrupts occur either because of
791	* a system status change or because a single bit memory error	791	* a system status change or because a single bit memory error
792	* occurred. FIXME: At the moment, ignore all this. */	792	* occurred. FIXME: At the moment, ignore all this. */
793	fastcall void	793	fastcall void
794	smp_vic_cmn_interrupt(struct pt_regs *regs)	794	smp_vic_cmn_interrupt(struct pt_regs *regs)
795	{	795	{
796	static __u8 in_cmn_int = 0;	796	static __u8 in_cmn_int = 0;
797	static DEFINE_SPINLOCK(cmn_int_lock);	797	static DEFINE_SPINLOCK(cmn_int_lock);
798		798
799	/* common ints are broadcast, so make sure we only do this once */	799	/* common ints are broadcast, so make sure we only do this once */
800	_raw_spin_lock(&cmn_int_lock);	800	_raw_spin_lock(&cmn_int_lock);
801	if(in_cmn_int)	801	if(in_cmn_int)
802	goto unlock_end;	802	goto unlock_end;
803		803
804	in_cmn_int++;	804	in_cmn_int++;
805	_raw_spin_unlock(&cmn_int_lock);	805	_raw_spin_unlock(&cmn_int_lock);
806		806
807	VDEBUG(("Voyager COMMON INTERRUPT\n"));	807	VDEBUG(("Voyager COMMON INTERRUPT\n"));
808		808
809	if(voyager_level == 5)	809	if(voyager_level == 5)
810	voyager_cat_do_common_interrupt();	810	voyager_cat_do_common_interrupt();
811		811
812	_raw_spin_lock(&cmn_int_lock);	812	_raw_spin_lock(&cmn_int_lock);
813	in_cmn_int = 0;	813	in_cmn_int = 0;
814	unlock_end:	814	unlock_end:
815	_raw_spin_unlock(&cmn_int_lock);	815	_raw_spin_unlock(&cmn_int_lock);
816	ack_CPI(VIC_CMN_INT);	816	ack_CPI(VIC_CMN_INT);
817	}	817	}
818		818
819	/*	819	/*
820	* Reschedule call back. Nothing to do, all the work is done	820	* Reschedule call back. Nothing to do, all the work is done
821	* automatically when we return from the interrupt. */	821	* automatically when we return from the interrupt. */
822	static void	822	static void
823	smp_reschedule_interrupt(void)	823	smp_reschedule_interrupt(void)
824	{	824	{
825	/* do nothing */	825	/* do nothing */
826	}	826	}
827		827
828	static struct mm_struct * flush_mm;	828	static struct mm_struct * flush_mm;
829	static unsigned long flush_va;	829	static unsigned long flush_va;
830	static DEFINE_SPINLOCK(tlbstate_lock);	830	static DEFINE_SPINLOCK(tlbstate_lock);
831	#define FLUSH_ALL 0xffffffff	831	#define FLUSH_ALL 0xffffffff
832		832
833	/*	833	/*
834	* We cannot call mmdrop() because we are in interrupt context,	834	* We cannot call mmdrop() because we are in interrupt context,
835	* instead update mm->cpu_vm_mask.	835	* instead update mm->cpu_vm_mask.
836	*	836	*
837	* We need to reload %cr3 since the page tables may be going	837	* We need to reload %cr3 since the page tables may be going
838	* away from under us..	838	* away from under us..
839	*/	839	*/
840	static inline void	840	static inline void
841	leave_mm (unsigned long cpu)	841	leave_mm (unsigned long cpu)
842	{	842	{
843	if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_OK)	843	if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_OK)
844	BUG();	844	BUG();
845	cpu_clear(cpu, per_cpu(cpu_tlbstate, cpu).active_mm->cpu_vm_mask);	845	cpu_clear(cpu, per_cpu(cpu_tlbstate, cpu).active_mm->cpu_vm_mask);
846	load_cr3(swapper_pg_dir);	846	load_cr3(swapper_pg_dir);
847	}	847	}
848		848
849		849
850	/*	850	/*
851	* Invalidate call-back	851	* Invalidate call-back
852	*/	852	*/
853	static void	853	static void
854	smp_invalidate_interrupt(void)	854	smp_invalidate_interrupt(void)
855	{	855	{
856	__u8 cpu = smp_processor_id();	856	__u8 cpu = smp_processor_id();
857		857
858	if (!test_bit(cpu, &smp_invalidate_needed))	858	if (!test_bit(cpu, &smp_invalidate_needed))
859	return;	859	return;
860	/* This will flood messages. Don't uncomment unless you see	860	/* This will flood messages. Don't uncomment unless you see
861	* Problems with cross cpu invalidation	861	* Problems with cross cpu invalidation
862	VDEBUG(("VOYAGER SMP: CPU%d received INVALIDATE_CPI\n",	862	VDEBUG(("VOYAGER SMP: CPU%d received INVALIDATE_CPI\n",
863	smp_processor_id()));	863	smp_processor_id()));
864	*/	864	*/
865		865
866	if (flush_mm == per_cpu(cpu_tlbstate, cpu).active_mm) {	866	if (flush_mm == per_cpu(cpu_tlbstate, cpu).active_mm) {
867	if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_OK) {	867	if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_OK) {
868	if (flush_va == FLUSH_ALL)	868	if (flush_va == FLUSH_ALL)
869	local_flush_tlb();	869	local_flush_tlb();
870	else	870	else
871	__flush_tlb_one(flush_va);	871	__flush_tlb_one(flush_va);
872	} else	872	} else
873	leave_mm(cpu);	873	leave_mm(cpu);
874	}	874	}
875	smp_mb__before_clear_bit();	875	smp_mb__before_clear_bit();
876	clear_bit(cpu, &smp_invalidate_needed);	876	clear_bit(cpu, &smp_invalidate_needed);
877	smp_mb__after_clear_bit();	877	smp_mb__after_clear_bit();
878	}	878	}
879		879
880	/* All the new flush operations for 2.4 */	880	/* All the new flush operations for 2.4 */
881		881
882		882
883	/* This routine is called with a physical cpu mask */	883	/* This routine is called with a physical cpu mask */
884	static void	884	static void
885	flush_tlb_others (unsigned long cpumask, struct mm_struct *mm,	885	flush_tlb_others (unsigned long cpumask, struct mm_struct *mm,
886	unsigned long va)	886	unsigned long va)
887	{	887	{
888	int stuck = 50000;	888	int stuck = 50000;
889		889
890	if (!cpumask)	890	if (!cpumask)
891	BUG();	891	BUG();
892	if ((cpumask & cpus_addr(cpu_online_map)[0]) != cpumask)	892	if ((cpumask & cpus_addr(cpu_online_map)[0]) != cpumask)
893	BUG();	893	BUG();
894	if (cpumask & (1 << smp_processor_id()))	894	if (cpumask & (1 << smp_processor_id()))
895	BUG();	895	BUG();
896	if (!mm)	896	if (!mm)
897	BUG();	897	BUG();
898		898
899	spin_lock(&tlbstate_lock);	899	spin_lock(&tlbstate_lock);
900		900
901	flush_mm = mm;	901	flush_mm = mm;
902	flush_va = va;	902	flush_va = va;
903	atomic_set_mask(cpumask, &smp_invalidate_needed);	903	atomic_set_mask(cpumask, &smp_invalidate_needed);
904	/*	904	/*
905	* We have to send the CPI only to	905	* We have to send the CPI only to
906	* CPUs affected.	906	* CPUs affected.
907	*/	907	*/
908	send_CPI(cpumask, VIC_INVALIDATE_CPI);	908	send_CPI(cpumask, VIC_INVALIDATE_CPI);
909		909
910	while (smp_invalidate_needed) {	910	while (smp_invalidate_needed) {
911	mb();	911	mb();
912	if(--stuck == 0) {	912	if(--stuck == 0) {
913	printk("*WARNING* Stuck doing invalidate CPI (CPU%d)\n", smp_processor_id());	913	printk("*WARNING* Stuck doing invalidate CPI (CPU%d)\n", smp_processor_id());
914	break;	914	break;
915	}	915	}
916	}	916	}
917		917
918	/* Uncomment only to debug invalidation problems	918	/* Uncomment only to debug invalidation problems
919	VDEBUG(("VOYAGER SMP: Completed invalidate CPI (CPU%d)\n", cpu));	919	VDEBUG(("VOYAGER SMP: Completed invalidate CPI (CPU%d)\n", cpu));
920	*/	920	*/
921		921
922	flush_mm = NULL;	922	flush_mm = NULL;
923	flush_va = 0;	923	flush_va = 0;
924	spin_unlock(&tlbstate_lock);	924	spin_unlock(&tlbstate_lock);
925	}	925	}
926		926
927	void	927	void
928	flush_tlb_current_task(void)	928	flush_tlb_current_task(void)
929	{	929	{
930	struct mm_struct *mm = current->mm;	930	struct mm_struct *mm = current->mm;
931	unsigned long cpu_mask;	931	unsigned long cpu_mask;
932		932
933	preempt_disable();	933	preempt_disable();
934		934
935	cpu_mask = cpus_addr(mm->cpu_vm_mask)[0] & ~(1 << smp_processor_id());	935	cpu_mask = cpus_addr(mm->cpu_vm_mask)[0] & ~(1 << smp_processor_id());
936	local_flush_tlb();	936	local_flush_tlb();
937	if (cpu_mask)	937	if (cpu_mask)
938	flush_tlb_others(cpu_mask, mm, FLUSH_ALL);	938	flush_tlb_others(cpu_mask, mm, FLUSH_ALL);
939		939
940	preempt_enable();	940	preempt_enable();
941	}	941	}
942		942
943		943
944	void	944	void
945	flush_tlb_mm (struct mm_struct * mm)	945	flush_tlb_mm (struct mm_struct * mm)
946	{	946	{
947	unsigned long cpu_mask;	947	unsigned long cpu_mask;
948		948
949	preempt_disable();	949	preempt_disable();
950		950
951	cpu_mask = cpus_addr(mm->cpu_vm_mask)[0] & ~(1 << smp_processor_id());	951	cpu_mask = cpus_addr(mm->cpu_vm_mask)[0] & ~(1 << smp_processor_id());
952		952
953	if (current->active_mm == mm) {	953	if (current->active_mm == mm) {
954	if (current->mm)	954	if (current->mm)
955	local_flush_tlb();	955	local_flush_tlb();
956	else	956	else
957	leave_mm(smp_processor_id());	957	leave_mm(smp_processor_id());
958	}	958	}
959	if (cpu_mask)	959	if (cpu_mask)
960	flush_tlb_others(cpu_mask, mm, FLUSH_ALL);	960	flush_tlb_others(cpu_mask, mm, FLUSH_ALL);
961		961
962	preempt_enable();	962	preempt_enable();
963	}	963	}
964		964
965	void flush_tlb_page(struct vm_area_struct * vma, unsigned long va)	965	void flush_tlb_page(struct vm_area_struct * vma, unsigned long va)
966	{	966	{
967	struct mm_struct *mm = vma->vm_mm;	967	struct mm_struct *mm = vma->vm_mm;
968	unsigned long cpu_mask;	968	unsigned long cpu_mask;
969		969
970	preempt_disable();	970	preempt_disable();
971		971
972	cpu_mask = cpus_addr(mm->cpu_vm_mask)[0] & ~(1 << smp_processor_id());	972	cpu_mask = cpus_addr(mm->cpu_vm_mask)[0] & ~(1 << smp_processor_id());
973	if (current->active_mm == mm) {	973	if (current->active_mm == mm) {
974	if(current->mm)	974	if(current->mm)
975	__flush_tlb_one(va);	975	__flush_tlb_one(va);
976	else	976	else
977	leave_mm(smp_processor_id());	977	leave_mm(smp_processor_id());
978	}	978	}
979		979
980	if (cpu_mask)	980	if (cpu_mask)
981	flush_tlb_others(cpu_mask, mm, va);	981	flush_tlb_others(cpu_mask, mm, va);
982		982
983	preempt_enable();	983	preempt_enable();
984	}	984	}
985	EXPORT_SYMBOL(flush_tlb_page);	985	EXPORT_SYMBOL(flush_tlb_page);
986		986
987	/* enable the requested IRQs */	987	/* enable the requested IRQs */
988	static void	988	static void
989	smp_enable_irq_interrupt(void)	989	smp_enable_irq_interrupt(void)
990	{	990	{
991	__u8 irq;	991	__u8 irq;
992	__u8 cpu = get_cpu();	992	__u8 cpu = get_cpu();
993		993
994	VDEBUG(("VOYAGER SMP: CPU%d enabling irq mask 0x%x\n", cpu,	994	VDEBUG(("VOYAGER SMP: CPU%d enabling irq mask 0x%x\n", cpu,
995	vic_irq_enable_mask[cpu]));	995	vic_irq_enable_mask[cpu]));
996		996
997	spin_lock(&vic_irq_lock);	997	spin_lock(&vic_irq_lock);
998	for(irq = 0; irq < 16; irq++) {	998	for(irq = 0; irq < 16; irq++) {
999	if(vic_irq_enable_mask[cpu] & (1<<irq))	999	if(vic_irq_enable_mask[cpu] & (1<<irq))
1000	enable_local_vic_irq(irq);	1000	enable_local_vic_irq(irq);
1001	}	1001	}
1002	vic_irq_enable_mask[cpu] = 0;	1002	vic_irq_enable_mask[cpu] = 0;
1003	spin_unlock(&vic_irq_lock);	1003	spin_unlock(&vic_irq_lock);
1004		1004
1005	put_cpu_no_resched();	1005	put_cpu_no_resched();
1006	}	1006	}
1007		1007
1008	/*	1008	/*
1009	* CPU halt call-back	1009	* CPU halt call-back
1010	*/	1010	*/
1011	static void	1011	static void
1012	smp_stop_cpu_function(void *dummy)	1012	smp_stop_cpu_function(void *dummy)
1013	{	1013	{
1014	VDEBUG(("VOYAGER SMP: CPU%d is STOPPING\n", smp_processor_id()));	1014	VDEBUG(("VOYAGER SMP: CPU%d is STOPPING\n", smp_processor_id()));
1015	cpu_clear(smp_processor_id(), cpu_online_map);	1015	cpu_clear(smp_processor_id(), cpu_online_map);
1016	local_irq_disable();	1016	local_irq_disable();
1017	for(;;)	1017	for(;;)
1018	__asm__("hlt");	1018	halt();
1019	}	1019	}
1020		1020
1021	static DEFINE_SPINLOCK(call_lock);	1021	static DEFINE_SPINLOCK(call_lock);
1022		1022
1023	struct call_data_struct {	1023	struct call_data_struct {
1024	void (func) (void info);	1024	void (func) (void info);
1025	void *info;	1025	void *info;
1026	volatile unsigned long started;	1026	volatile unsigned long started;
1027	volatile unsigned long finished;	1027	volatile unsigned long finished;
1028	int wait;	1028	int wait;
1029	};	1029	};
1030		1030
1031	static struct call_data_struct * call_data;	1031	static struct call_data_struct * call_data;
1032		1032
1033	/* execute a thread on a new CPU. The function to be called must be	1033	/* execute a thread on a new CPU. The function to be called must be
1034	* previously set up. This is used to schedule a function for	1034	* previously set up. This is used to schedule a function for
1035	* execution on all CPU's - set up the function then broadcast a	1035	* execution on all CPU's - set up the function then broadcast a
1036	* function_interrupt CPI to come here on each CPU */	1036	* function_interrupt CPI to come here on each CPU */
1037	static void	1037	static void
1038	smp_call_function_interrupt(void)	1038	smp_call_function_interrupt(void)
1039	{	1039	{
1040	void (func) (void info) = call_data->func;	1040	void (func) (void info) = call_data->func;
1041	void *info = call_data->info;	1041	void *info = call_data->info;
1042	/* must take copy of wait because call_data may be replaced	1042	/* must take copy of wait because call_data may be replaced
1043	* unless the function is waiting for us to finish */	1043	* unless the function is waiting for us to finish */
1044	int wait = call_data->wait;	1044	int wait = call_data->wait;
1045	__u8 cpu = smp_processor_id();	1045	__u8 cpu = smp_processor_id();
1046		1046
1047	/*	1047	/*
1048	* Notify initiating CPU that I've grabbed the data and am	1048	* Notify initiating CPU that I've grabbed the data and am
1049	* about to execute the function	1049	* about to execute the function
1050	*/	1050	*/
1051	mb();	1051	mb();
1052	if(!test_and_clear_bit(cpu, &call_data->started)) {	1052	if(!test_and_clear_bit(cpu, &call_data->started)) {
1053	/* If the bit wasn't set, this could be a replay */	1053	/* If the bit wasn't set, this could be a replay */
1054	printk(KERN_WARNING "VOYAGER SMP: CPU %d received call funtion with no call pending\n", cpu);	1054	printk(KERN_WARNING "VOYAGER SMP: CPU %d received call funtion with no call pending\n", cpu);
1055	return;	1055	return;
1056	}	1056	}
1057	/*	1057	/*
1058	* At this point the info structure may be out of scope unless wait==1	1058	* At this point the info structure may be out of scope unless wait==1
1059	*/	1059	*/
1060	irq_enter();	1060	irq_enter();
1061	(*func)(info);	1061	(*func)(info);
1062	irq_exit();	1062	irq_exit();
1063	if (wait) {	1063	if (wait) {
1064	mb();	1064	mb();
1065	clear_bit(cpu, &call_data->finished);	1065	clear_bit(cpu, &call_data->finished);
1066	}	1066	}
1067	}	1067	}
1068		1068
1069	/* Call this function on all CPUs using the function_interrupt above	1069	/* Call this function on all CPUs using the function_interrupt above
1070	<func> The function to run. This must be fast and non-blocking.	1070	<func> The function to run. This must be fast and non-blocking.
1071	<info> An arbitrary pointer to pass to the function.	1071	<info> An arbitrary pointer to pass to the function.
1072	<retry> If true, keep retrying until ready.	1072	<retry> If true, keep retrying until ready.
1073	<wait> If true, wait until function has completed on other CPUs.	1073	<wait> If true, wait until function has completed on other CPUs.
1074	[RETURNS] 0 on success, else a negative status code. Does not return until	1074	[RETURNS] 0 on success, else a negative status code. Does not return until
1075	remote CPUs are nearly ready to execute <<func>> or are or have executed.	1075	remote CPUs are nearly ready to execute <<func>> or are or have executed.
1076	*/	1076	*/
1077	int	1077	int
1078	smp_call_function (void (func) (void info), void *info, int retry,	1078	smp_call_function (void (func) (void info), void *info, int retry,
1079	int wait)	1079	int wait)
1080	{	1080	{
1081	struct call_data_struct data;	1081	struct call_data_struct data;
1082	__u32 mask = cpus_addr(cpu_online_map)[0];	1082	__u32 mask = cpus_addr(cpu_online_map)[0];
1083		1083
1084	mask &= ~(1<<smp_processor_id());	1084	mask &= ~(1<<smp_processor_id());
1085		1085
1086	if (!mask)	1086	if (!mask)
1087	return 0;	1087	return 0;
1088		1088
1089	/* Can deadlock when called with interrupts disabled */	1089	/* Can deadlock when called with interrupts disabled */
1090	WARN_ON(irqs_disabled());	1090	WARN_ON(irqs_disabled());
1091		1091
1092	data.func = func;	1092	data.func = func;
1093	data.info = info;	1093	data.info = info;
1094	data.started = mask;	1094	data.started = mask;
1095	data.wait = wait;	1095	data.wait = wait;
1096	if (wait)	1096	if (wait)
1097	data.finished = mask;	1097	data.finished = mask;
1098		1098
1099	spin_lock(&call_lock);	1099	spin_lock(&call_lock);
1100	call_data = &data;	1100	call_data = &data;
1101	wmb();	1101	wmb();
1102	/* Send a message to all other CPUs and wait for them to respond */	1102	/* Send a message to all other CPUs and wait for them to respond */
1103	send_CPI_allbutself(VIC_CALL_FUNCTION_CPI);	1103	send_CPI_allbutself(VIC_CALL_FUNCTION_CPI);
1104		1104
1105	/* Wait for response */	1105	/* Wait for response */
1106	while (data.started)	1106	while (data.started)
1107	barrier();	1107	barrier();
1108		1108
1109	if (wait)	1109	if (wait)
1110	while (data.finished)	1110	while (data.finished)
1111	barrier();	1111	barrier();
1112		1112
1113	spin_unlock(&call_lock);	1113	spin_unlock(&call_lock);
1114		1114
1115	return 0;	1115	return 0;
1116	}	1116	}
1117	EXPORT_SYMBOL(smp_call_function);	1117	EXPORT_SYMBOL(smp_call_function);
1118		1118
1119	/* Sorry about the name. In an APIC based system, the APICs	1119	/* Sorry about the name. In an APIC based system, the APICs
1120	* themselves are programmed to send a timer interrupt. This is used	1120	* themselves are programmed to send a timer interrupt. This is used
1121	* by linux to reschedule the processor. Voyager doesn't have this,	1121	* by linux to reschedule the processor. Voyager doesn't have this,
1122	* so we use the system clock to interrupt one processor, which in	1122	* so we use the system clock to interrupt one processor, which in
1123	* turn, broadcasts a timer CPI to all the others --- we receive that	1123	* turn, broadcasts a timer CPI to all the others --- we receive that
1124	* CPI here. We don't use this actually for counting so losing	1124	* CPI here. We don't use this actually for counting so losing
1125	* ticks doesn't matter	1125	* ticks doesn't matter
1126	*	1126	*
1127	* FIXME: For those CPU's which actually have a local APIC, we could	1127	* FIXME: For those CPU's which actually have a local APIC, we could
1128	* try to use it to trigger this interrupt instead of having to	1128	* try to use it to trigger this interrupt instead of having to
1129	* broadcast the timer tick. Unfortunately, all my pentium DYADs have	1129	* broadcast the timer tick. Unfortunately, all my pentium DYADs have
1130	* no local APIC, so I can't do this	1130	* no local APIC, so I can't do this
1131	*	1131	*
1132	* This function is currently a placeholder and is unused in the code */	1132	* This function is currently a placeholder and is unused in the code */
1133	fastcall void	1133	fastcall void
1134	smp_apic_timer_interrupt(struct pt_regs *regs)	1134	smp_apic_timer_interrupt(struct pt_regs *regs)
1135	{	1135	{
1136	wrapper_smp_local_timer_interrupt(regs);	1136	wrapper_smp_local_timer_interrupt(regs);
1137	}	1137	}
1138		1138
1139	/* All of the QUAD interrupt GATES */	1139	/* All of the QUAD interrupt GATES */
1140	fastcall void	1140	fastcall void
1141	smp_qic_timer_interrupt(struct pt_regs *regs)	1141	smp_qic_timer_interrupt(struct pt_regs *regs)
1142	{	1142	{
1143	ack_QIC_CPI(QIC_TIMER_CPI);	1143	ack_QIC_CPI(QIC_TIMER_CPI);
1144	wrapper_smp_local_timer_interrupt(regs);	1144	wrapper_smp_local_timer_interrupt(regs);
1145	}	1145	}
1146		1146
1147	fastcall void	1147	fastcall void
1148	smp_qic_invalidate_interrupt(struct pt_regs *regs)	1148	smp_qic_invalidate_interrupt(struct pt_regs *regs)
1149	{	1149	{
1150	ack_QIC_CPI(QIC_INVALIDATE_CPI);	1150	ack_QIC_CPI(QIC_INVALIDATE_CPI);
1151	smp_invalidate_interrupt();	1151	smp_invalidate_interrupt();
1152	}	1152	}
1153		1153
1154	fastcall void	1154	fastcall void
1155	smp_qic_reschedule_interrupt(struct pt_regs *regs)	1155	smp_qic_reschedule_interrupt(struct pt_regs *regs)
1156	{	1156	{
1157	ack_QIC_CPI(QIC_RESCHEDULE_CPI);	1157	ack_QIC_CPI(QIC_RESCHEDULE_CPI);
1158	smp_reschedule_interrupt();	1158	smp_reschedule_interrupt();
1159	}	1159	}
1160		1160
1161	fastcall void	1161	fastcall void
1162	smp_qic_enable_irq_interrupt(struct pt_regs *regs)	1162	smp_qic_enable_irq_interrupt(struct pt_regs *regs)
1163	{	1163	{
1164	ack_QIC_CPI(QIC_ENABLE_IRQ_CPI);	1164	ack_QIC_CPI(QIC_ENABLE_IRQ_CPI);
1165	smp_enable_irq_interrupt();	1165	smp_enable_irq_interrupt();
1166	}	1166	}
1167		1167
1168	fastcall void	1168	fastcall void
1169	smp_qic_call_function_interrupt(struct pt_regs *regs)	1169	smp_qic_call_function_interrupt(struct pt_regs *regs)
1170	{	1170	{
1171	ack_QIC_CPI(QIC_CALL_FUNCTION_CPI);	1171	ack_QIC_CPI(QIC_CALL_FUNCTION_CPI);
1172	smp_call_function_interrupt();	1172	smp_call_function_interrupt();
1173	}	1173	}
1174		1174
1175	fastcall void	1175	fastcall void
1176	smp_vic_cpi_interrupt(struct pt_regs *regs)	1176	smp_vic_cpi_interrupt(struct pt_regs *regs)
1177	{	1177	{
1178	__u8 cpu = smp_processor_id();	1178	__u8 cpu = smp_processor_id();
1179		1179
1180	if(is_cpu_quad())	1180	if(is_cpu_quad())
1181	ack_QIC_CPI(VIC_CPI_LEVEL0);	1181	ack_QIC_CPI(VIC_CPI_LEVEL0);
1182	else	1182	else
1183	ack_VIC_CPI(VIC_CPI_LEVEL0);	1183	ack_VIC_CPI(VIC_CPI_LEVEL0);
1184		1184
1185	if(test_and_clear_bit(VIC_TIMER_CPI, &vic_cpi_mailbox[cpu]))	1185	if(test_and_clear_bit(VIC_TIMER_CPI, &vic_cpi_mailbox[cpu]))
1186	wrapper_smp_local_timer_interrupt(regs);	1186	wrapper_smp_local_timer_interrupt(regs);
1187	if(test_and_clear_bit(VIC_INVALIDATE_CPI, &vic_cpi_mailbox[cpu]))	1187	if(test_and_clear_bit(VIC_INVALIDATE_CPI, &vic_cpi_mailbox[cpu]))
1188	smp_invalidate_interrupt();	1188	smp_invalidate_interrupt();
1189	if(test_and_clear_bit(VIC_RESCHEDULE_CPI, &vic_cpi_mailbox[cpu]))	1189	if(test_and_clear_bit(VIC_RESCHEDULE_CPI, &vic_cpi_mailbox[cpu]))
1190	smp_reschedule_interrupt();	1190	smp_reschedule_interrupt();
1191	if(test_and_clear_bit(VIC_ENABLE_IRQ_CPI, &vic_cpi_mailbox[cpu]))	1191	if(test_and_clear_bit(VIC_ENABLE_IRQ_CPI, &vic_cpi_mailbox[cpu]))
1192	smp_enable_irq_interrupt();	1192	smp_enable_irq_interrupt();
1193	if(test_and_clear_bit(VIC_CALL_FUNCTION_CPI, &vic_cpi_mailbox[cpu]))	1193	if(test_and_clear_bit(VIC_CALL_FUNCTION_CPI, &vic_cpi_mailbox[cpu]))
1194	smp_call_function_interrupt();	1194	smp_call_function_interrupt();
1195	}	1195	}
1196		1196
1197	static void	1197	static void
1198	do_flush_tlb_all(void* info)	1198	do_flush_tlb_all(void* info)
1199	{	1199	{
1200	unsigned long cpu = smp_processor_id();	1200	unsigned long cpu = smp_processor_id();
1201		1201
1202	__flush_tlb_all();	1202	__flush_tlb_all();
1203	if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_LAZY)	1203	if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_LAZY)
1204	leave_mm(cpu);	1204	leave_mm(cpu);
1205	}	1205	}
1206		1206
1207		1207
1208	/* flush the TLB of every active CPU in the system */	1208	/* flush the TLB of every active CPU in the system */
1209	void	1209	void
1210	flush_tlb_all(void)	1210	flush_tlb_all(void)
1211	{	1211	{
1212	on_each_cpu(do_flush_tlb_all, 0, 1, 1);	1212	on_each_cpu(do_flush_tlb_all, 0, 1, 1);
1213	}	1213	}
1214		1214
1215	/* used to set up the trampoline for other CPUs when the memory manager	1215	/* used to set up the trampoline for other CPUs when the memory manager
1216	* is sorted out */	1216	* is sorted out */
1217	void __init	1217	void __init
1218	smp_alloc_memory(void)	1218	smp_alloc_memory(void)
1219	{	1219	{
1220	trampoline_base = (__u32)alloc_bootmem_low_pages(PAGE_SIZE);	1220	trampoline_base = (__u32)alloc_bootmem_low_pages(PAGE_SIZE);
1221	if(__pa(trampoline_base) >= 0x93000)	1221	if(__pa(trampoline_base) >= 0x93000)
1222	BUG();	1222	BUG();
1223	}	1223	}
1224		1224
1225	/* send a reschedule CPI to one CPU by physical CPU number*/	1225	/* send a reschedule CPI to one CPU by physical CPU number*/
1226	void	1226	void
1227	smp_send_reschedule(int cpu)	1227	smp_send_reschedule(int cpu)
1228	{	1228	{
1229	send_one_CPI(cpu, VIC_RESCHEDULE_CPI);	1229	send_one_CPI(cpu, VIC_RESCHEDULE_CPI);
1230	}	1230	}
1231		1231
1232		1232
1233	int	1233	int
1234	hard_smp_processor_id(void)	1234	hard_smp_processor_id(void)
1235	{	1235	{
1236	__u8 i;	1236	__u8 i;
1237	__u8 cpumask = inb(VIC_PROC_WHO_AM_I);	1237	__u8 cpumask = inb(VIC_PROC_WHO_AM_I);
1238	if((cpumask & QUAD_IDENTIFIER) == QUAD_IDENTIFIER)	1238	if((cpumask & QUAD_IDENTIFIER) == QUAD_IDENTIFIER)
1239	return cpumask & 0x1F;	1239	return cpumask & 0x1F;
1240		1240
1241	for(i = 0; i < 8; i++) {	1241	for(i = 0; i < 8; i++) {
1242	if(cpumask & (1<<i))	1242	if(cpumask & (1<<i))
1243	return i;	1243	return i;
1244	}	1244	}
1245	printk(" WARNING Illegal cpuid returned by VIC: %d", cpumask);	1245	printk(" WARNING Illegal cpuid returned by VIC: %d", cpumask);
1246	return 0;	1246	return 0;
1247	}	1247	}
1248		1248
1249	/* broadcast a halt to all other CPUs */	1249	/* broadcast a halt to all other CPUs */
1250	void	1250	void
1251	smp_send_stop(void)	1251	smp_send_stop(void)
1252	{	1252	{
1253	smp_call_function(smp_stop_cpu_function, NULL, 1, 1);	1253	smp_call_function(smp_stop_cpu_function, NULL, 1, 1);
1254	}	1254	}
1255		1255
1256	/* this function is triggered in time.c when a clock tick fires	1256	/* this function is triggered in time.c when a clock tick fires
1257	* we need to re-broadcast the tick to all CPUs */	1257	* we need to re-broadcast the tick to all CPUs */
1258	void	1258	void
1259	smp_vic_timer_interrupt(struct pt_regs *regs)	1259	smp_vic_timer_interrupt(struct pt_regs *regs)
1260	{	1260	{
1261	send_CPI_allbutself(VIC_TIMER_CPI);	1261	send_CPI_allbutself(VIC_TIMER_CPI);
1262	smp_local_timer_interrupt(regs);	1262	smp_local_timer_interrupt(regs);
1263	}	1263	}
1264		1264
1265	/* local (per CPU) timer interrupt. It does both profiling and	1265	/* local (per CPU) timer interrupt. It does both profiling and
1266	* process statistics/rescheduling.	1266	* process statistics/rescheduling.
1267	*	1267	*
1268	* We do profiling in every local tick, statistics/rescheduling	1268	* We do profiling in every local tick, statistics/rescheduling
1269	* happen only every 'profiling multiplier' ticks. The default	1269	* happen only every 'profiling multiplier' ticks. The default
1270	* multiplier is 1 and it can be changed by writing the new multiplier	1270	* multiplier is 1 and it can be changed by writing the new multiplier
1271	* value into /proc/profile.	1271	* value into /proc/profile.
1272	*/	1272	*/
1273	void	1273	void
1274	smp_local_timer_interrupt(struct pt_regs * regs)	1274	smp_local_timer_interrupt(struct pt_regs * regs)
1275	{	1275	{
1276	int cpu = smp_processor_id();	1276	int cpu = smp_processor_id();
1277	long weight;	1277	long weight;
1278		1278
1279	profile_tick(CPU_PROFILING, regs);	1279	profile_tick(CPU_PROFILING, regs);
1280	if (--per_cpu(prof_counter, cpu) <= 0) {	1280	if (--per_cpu(prof_counter, cpu) <= 0) {
1281	/*	1281	/*
1282	* The multiplier may have changed since the last time we got	1282	* The multiplier may have changed since the last time we got
1283	* to this point as a result of the user writing to	1283	* to this point as a result of the user writing to
1284	* /proc/profile. In this case we need to adjust the APIC	1284	* /proc/profile. In this case we need to adjust the APIC
1285	* timer accordingly.	1285	* timer accordingly.
1286	*	1286	*
1287	* Interrupts are already masked off at this point.	1287	* Interrupts are already masked off at this point.
1288	*/	1288	*/
1289	per_cpu(prof_counter,cpu) = per_cpu(prof_multiplier, cpu);	1289	per_cpu(prof_counter,cpu) = per_cpu(prof_multiplier, cpu);
1290	if (per_cpu(prof_counter, cpu) !=	1290	if (per_cpu(prof_counter, cpu) !=
1291	per_cpu(prof_old_multiplier, cpu)) {	1291	per_cpu(prof_old_multiplier, cpu)) {
1292	/* FIXME: need to update the vic timer tick here */	1292	/* FIXME: need to update the vic timer tick here */
1293	per_cpu(prof_old_multiplier, cpu) =	1293	per_cpu(prof_old_multiplier, cpu) =
1294	per_cpu(prof_counter, cpu);	1294	per_cpu(prof_counter, cpu);
1295	}	1295	}
1296		1296
1297	update_process_times(user_mode_vm(regs));	1297	update_process_times(user_mode_vm(regs));
1298	}	1298	}
1299		1299
1300	if( ((1<<cpu) & voyager_extended_vic_processors) == 0)	1300	if( ((1<<cpu) & voyager_extended_vic_processors) == 0)
1301	/* only extended VIC processors participate in	1301	/* only extended VIC processors participate in
1302	* interrupt distribution */	1302	* interrupt distribution */
1303	return;	1303	return;
1304		1304
1305	/*	1305	/*
1306	* We take the 'long' return path, and there every subsystem	1306	* We take the 'long' return path, and there every subsystem
1307	* grabs the apropriate locks (kernel lock/ irq lock).	1307	* grabs the apropriate locks (kernel lock/ irq lock).
1308	*	1308	*
1309	* we might want to decouple profiling from the 'long path',	1309	* we might want to decouple profiling from the 'long path',
1310	* and do the profiling totally in assembly.	1310	* and do the profiling totally in assembly.
1311	*	1311	*
1312	* Currently this isn't too much of an issue (performance wise),	1312	* Currently this isn't too much of an issue (performance wise),
1313	* we can take more than 100K local irqs per second on a 100 MHz P5.	1313	* we can take more than 100K local irqs per second on a 100 MHz P5.
1314	*/	1314	*/
1315		1315
1316	if((++vic_tick[cpu] & 0x7) != 0)	1316	if((++vic_tick[cpu] & 0x7) != 0)
1317	return;	1317	return;
1318	/* get here every 16 ticks (about every 1/6 of a second) */	1318	/* get here every 16 ticks (about every 1/6 of a second) */
1319		1319
1320	/* Change our priority to give someone else a chance at getting	1320	/* Change our priority to give someone else a chance at getting
1321	* the IRQ. The algorithm goes like this:	1321	* the IRQ. The algorithm goes like this:
1322	*	1322	*
1323	* In the VIC, the dynamically routed interrupt is always	1323	* In the VIC, the dynamically routed interrupt is always
1324	* handled by the lowest priority eligible (i.e. receiving	1324	* handled by the lowest priority eligible (i.e. receiving
1325	* interrupts) CPU. If >1 eligible CPUs are equal lowest, the	1325	* interrupts) CPU. If >1 eligible CPUs are equal lowest, the
1326	* lowest processor number gets it.	1326	* lowest processor number gets it.
1327	*	1327	*
1328	* The priority of a CPU is controlled by a special per-CPU	1328	* The priority of a CPU is controlled by a special per-CPU
1329	* VIC priority register which is 3 bits wide 0 being lowest	1329	* VIC priority register which is 3 bits wide 0 being lowest
1330	* and 7 highest priority..	1330	* and 7 highest priority..
1331	*	1331	*
1332	* Therefore we subtract the average number of interrupts from	1332	* Therefore we subtract the average number of interrupts from
1333	* the number we've fielded. If this number is negative, we	1333	* the number we've fielded. If this number is negative, we
1334	* lower the activity count and if it is positive, we raise	1334	* lower the activity count and if it is positive, we raise
1335	* it.	1335	* it.
1336	*	1336	*
1337	* I'm afraid this still leads to odd looking interrupt counts:	1337	* I'm afraid this still leads to odd looking interrupt counts:
1338	* the totals are all roughly equal, but the individual ones	1338	* the totals are all roughly equal, but the individual ones
1339	* look rather skewed.	1339	* look rather skewed.
1340	*	1340	*
1341	* FIXME: This algorithm is total crap when mixed with SMP	1341	* FIXME: This algorithm is total crap when mixed with SMP
1342	* affinity code since we now try to even up the interrupt	1342	* affinity code since we now try to even up the interrupt
1343	* counts when an affinity binding is keeping them on a	1343	* counts when an affinity binding is keeping them on a
1344	* particular CPU*/	1344	* particular CPU*/
1345	weight = (vic_intr_count[cpu]*voyager_extended_cpus	1345	weight = (vic_intr_count[cpu]*voyager_extended_cpus
1346	- vic_intr_total) >> 4;	1346	- vic_intr_total) >> 4;
1347	weight += 4;	1347	weight += 4;
1348	if(weight > 7)	1348	if(weight > 7)
1349	weight = 7;	1349	weight = 7;
1350	if(weight < 0)	1350	if(weight < 0)
1351	weight = 0;	1351	weight = 0;
1352		1352
1353	outb((__u8)weight, VIC_PRIORITY_REGISTER);	1353	outb((__u8)weight, VIC_PRIORITY_REGISTER);
1354		1354
1355	#ifdef VOYAGER_DEBUG	1355	#ifdef VOYAGER_DEBUG
1356	if((vic_tick[cpu] & 0xFFF) == 0) {	1356	if((vic_tick[cpu] & 0xFFF) == 0) {
1357	/* print this message roughly every 25 secs */	1357	/* print this message roughly every 25 secs */
1358	printk("VOYAGER SMP: vic_tick[%d] = %lu, weight = %ld\n",	1358	printk("VOYAGER SMP: vic_tick[%d] = %lu, weight = %ld\n",
1359	cpu, vic_tick[cpu], weight);	1359	cpu, vic_tick[cpu], weight);
1360	}	1360	}
1361	#endif	1361	#endif
1362	}	1362	}
1363		1363
1364	/* setup the profiling timer */	1364	/* setup the profiling timer */
1365	int	1365	int
1366	setup_profiling_timer(unsigned int multiplier)	1366	setup_profiling_timer(unsigned int multiplier)
1367	{	1367	{
1368	int i;	1368	int i;
1369		1369
1370	if ( (!multiplier))	1370	if ( (!multiplier))
1371	return -EINVAL;	1371	return -EINVAL;
1372		1372
1373	/*	1373	/*
1374	* Set the new multiplier for each CPU. CPUs don't start using the	1374	* Set the new multiplier for each CPU. CPUs don't start using the
1375	* new values until the next timer interrupt in which they do process	1375	* new values until the next timer interrupt in which they do process
1376	* accounting.	1376	* accounting.
1377	*/	1377	*/
1378	for (i = 0; i < NR_CPUS; ++i)	1378	for (i = 0; i < NR_CPUS; ++i)
1379	per_cpu(prof_multiplier, i) = multiplier;	1379	per_cpu(prof_multiplier, i) = multiplier;
1380		1380
1381	return 0;	1381	return 0;
1382	}	1382	}
1383		1383
1384		1384
1385	/* The CPIs are handled in the per cpu 8259s, so they must be	1385	/* The CPIs are handled in the per cpu 8259s, so they must be
1386	* enabled to be received: FIX: enabling the CPIs in the early	1386	* enabled to be received: FIX: enabling the CPIs in the early
1387	* boot sequence interferes with bug checking; enable them later	1387	* boot sequence interferes with bug checking; enable them later
1388	* on in smp_init */	1388	* on in smp_init */
1389	#define VIC_SET_GATE(cpi, vector) \	1389	#define VIC_SET_GATE(cpi, vector) \
1390	set_intr_gate((cpi) + VIC_DEFAULT_CPI_BASE, (vector))	1390	set_intr_gate((cpi) + VIC_DEFAULT_CPI_BASE, (vector))
1391	#define QIC_SET_GATE(cpi, vector) \	1391	#define QIC_SET_GATE(cpi, vector) \
1392	set_intr_gate((cpi) + QIC_DEFAULT_CPI_BASE, (vector))	1392	set_intr_gate((cpi) + QIC_DEFAULT_CPI_BASE, (vector))
1393		1393
1394	void __init	1394	void __init
1395	smp_intr_init(void)	1395	smp_intr_init(void)
1396	{	1396	{
1397	int i;	1397	int i;
1398		1398
1399	/* initialize the per cpu irq mask to all disabled */	1399	/* initialize the per cpu irq mask to all disabled */
1400	for(i = 0; i < NR_CPUS; i++)	1400	for(i = 0; i < NR_CPUS; i++)
1401	vic_irq_mask[i] = 0xFFFF;	1401	vic_irq_mask[i] = 0xFFFF;
1402		1402
1403	VIC_SET_GATE(VIC_CPI_LEVEL0, vic_cpi_interrupt);	1403	VIC_SET_GATE(VIC_CPI_LEVEL0, vic_cpi_interrupt);
1404		1404
1405	VIC_SET_GATE(VIC_SYS_INT, vic_sys_interrupt);	1405	VIC_SET_GATE(VIC_SYS_INT, vic_sys_interrupt);
1406	VIC_SET_GATE(VIC_CMN_INT, vic_cmn_interrupt);	1406	VIC_SET_GATE(VIC_CMN_INT, vic_cmn_interrupt);
1407		1407
1408	QIC_SET_GATE(QIC_TIMER_CPI, qic_timer_interrupt);	1408	QIC_SET_GATE(QIC_TIMER_CPI, qic_timer_interrupt);
1409	QIC_SET_GATE(QIC_INVALIDATE_CPI, qic_invalidate_interrupt);	1409	QIC_SET_GATE(QIC_INVALIDATE_CPI, qic_invalidate_interrupt);
1410	QIC_SET_GATE(QIC_RESCHEDULE_CPI, qic_reschedule_interrupt);	1410	QIC_SET_GATE(QIC_RESCHEDULE_CPI, qic_reschedule_interrupt);
1411	QIC_SET_GATE(QIC_ENABLE_IRQ_CPI, qic_enable_irq_interrupt);	1411	QIC_SET_GATE(QIC_ENABLE_IRQ_CPI, qic_enable_irq_interrupt);
1412	QIC_SET_GATE(QIC_CALL_FUNCTION_CPI, qic_call_function_interrupt);	1412	QIC_SET_GATE(QIC_CALL_FUNCTION_CPI, qic_call_function_interrupt);
1413		1413
1414		1414
1415	/* now put the VIC descriptor into the first 48 IRQs	1415	/* now put the VIC descriptor into the first 48 IRQs
1416	*	1416	*
1417	* This is for later: first 16 correspond to PC IRQs; next 16	1417	* This is for later: first 16 correspond to PC IRQs; next 16
1418	* are Primary MC IRQs and final 16 are Secondary MC IRQs */	1418	* are Primary MC IRQs and final 16 are Secondary MC IRQs */
1419	for(i = 0; i < 48; i++)	1419	for(i = 0; i < 48; i++)
1420	irq_desc[i].handler = &vic_irq_type;	1420	irq_desc[i].handler = &vic_irq_type;
1421	}	1421	}
1422		1422
1423	/* send a CPI at level cpi to a set of cpus in cpuset (set 1 bit per	1423	/* send a CPI at level cpi to a set of cpus in cpuset (set 1 bit per
1424	* processor to receive CPI */	1424	* processor to receive CPI */
1425	static void	1425	static void
1426	send_CPI(__u32 cpuset, __u8 cpi)	1426	send_CPI(__u32 cpuset, __u8 cpi)
1427	{	1427	{
1428	int cpu;	1428	int cpu;
1429	__u32 quad_cpuset = (cpuset & voyager_quad_processors);	1429	__u32 quad_cpuset = (cpuset & voyager_quad_processors);
1430		1430
1431	if(cpi < VIC_START_FAKE_CPI) {	1431	if(cpi < VIC_START_FAKE_CPI) {
1432	/* fake CPI are only used for booting, so send to the	1432	/* fake CPI are only used for booting, so send to the
1433	* extended quads as well---Quads must be VIC booted */	1433	* extended quads as well---Quads must be VIC booted */
1434	outb((__u8)(cpuset), VIC_CPI_Registers[cpi]);	1434	outb((__u8)(cpuset), VIC_CPI_Registers[cpi]);
1435	return;	1435	return;
1436	}	1436	}
1437	if(quad_cpuset)	1437	if(quad_cpuset)
1438	send_QIC_CPI(quad_cpuset, cpi);	1438	send_QIC_CPI(quad_cpuset, cpi);
1439	cpuset &= ~quad_cpuset;	1439	cpuset &= ~quad_cpuset;
1440	cpuset &= 0xff; /* only first 8 CPUs vaild for VIC CPI */	1440	cpuset &= 0xff; /* only first 8 CPUs vaild for VIC CPI */
1441	if(cpuset == 0)	1441	if(cpuset == 0)
1442	return;	1442	return;
1443	for_each_online_cpu(cpu) {	1443	for_each_online_cpu(cpu) {
1444	if(cpuset & (1<<cpu))	1444	if(cpuset & (1<<cpu))
1445	set_bit(cpi, &vic_cpi_mailbox[cpu]);	1445	set_bit(cpi, &vic_cpi_mailbox[cpu]);
1446	}	1446	}
1447	if(cpuset)	1447	if(cpuset)
1448	outb((__u8)cpuset, VIC_CPI_Registers[VIC_CPI_LEVEL0]);	1448	outb((__u8)cpuset, VIC_CPI_Registers[VIC_CPI_LEVEL0]);
1449	}	1449	}
1450		1450
1451	/* Acknowledge receipt of CPI in the QIC, clear in QIC hardware and	1451	/* Acknowledge receipt of CPI in the QIC, clear in QIC hardware and
1452	* set the cache line to shared by reading it.	1452	* set the cache line to shared by reading it.
1453	*	1453	*
1454	* DON'T make this inline otherwise the cache line read will be	1454	* DON'T make this inline otherwise the cache line read will be
1455	* optimised away	1455	* optimised away
1456	* */	1456	* */
1457	static int	1457	static int
1458	ack_QIC_CPI(__u8 cpi) {	1458	ack_QIC_CPI(__u8 cpi) {
1459	__u8 cpu = hard_smp_processor_id();	1459	__u8 cpu = hard_smp_processor_id();
1460		1460
1461	cpi &= 7;	1461	cpi &= 7;
1462		1462
1463	outb(1<<cpi, QIC_INTERRUPT_CLEAR1);	1463	outb(1<<cpi, QIC_INTERRUPT_CLEAR1);
1464	return voyager_quad_cpi_addr[cpu]->qic_cpi[cpi].cpi;	1464	return voyager_quad_cpi_addr[cpu]->qic_cpi[cpi].cpi;
1465	}	1465	}
1466		1466
1467	static void	1467	static void
1468	ack_special_QIC_CPI(__u8 cpi)	1468	ack_special_QIC_CPI(__u8 cpi)
1469	{	1469	{
1470	switch(cpi) {	1470	switch(cpi) {
1471	case VIC_CMN_INT:	1471	case VIC_CMN_INT:
1472	outb(QIC_CMN_INT, QIC_INTERRUPT_CLEAR0);	1472	outb(QIC_CMN_INT, QIC_INTERRUPT_CLEAR0);
1473	break;	1473	break;
1474	case VIC_SYS_INT:	1474	case VIC_SYS_INT:
1475	outb(QIC_SYS_INT, QIC_INTERRUPT_CLEAR0);	1475	outb(QIC_SYS_INT, QIC_INTERRUPT_CLEAR0);
1476	break;	1476	break;
1477	}	1477	}
1478	/* also clear at the VIC, just in case (nop for non-extended proc) */	1478	/* also clear at the VIC, just in case (nop for non-extended proc) */
1479	ack_VIC_CPI(cpi);	1479	ack_VIC_CPI(cpi);
1480	}	1480	}
1481		1481
1482	/* Acknowledge receipt of CPI in the VIC (essentially an EOI) */	1482	/* Acknowledge receipt of CPI in the VIC (essentially an EOI) */
1483	static void	1483	static void
1484	ack_VIC_CPI(__u8 cpi)	1484	ack_VIC_CPI(__u8 cpi)
1485	{	1485	{
1486	#ifdef VOYAGER_DEBUG	1486	#ifdef VOYAGER_DEBUG
1487	unsigned long flags;	1487	unsigned long flags;
1488	__u16 isr;	1488	__u16 isr;
1489	__u8 cpu = smp_processor_id();	1489	__u8 cpu = smp_processor_id();
1490		1490
1491	local_irq_save(flags);	1491	local_irq_save(flags);
1492	isr = vic_read_isr();	1492	isr = vic_read_isr();
1493	if((isr & (1<<(cpi &7))) == 0) {	1493	if((isr & (1<<(cpi &7))) == 0) {
1494	printk("VOYAGER SMP: CPU%d lost CPI%d\n", cpu, cpi);	1494	printk("VOYAGER SMP: CPU%d lost CPI%d\n", cpu, cpi);
1495	}	1495	}
1496	#endif	1496	#endif
1497	/* send specific EOI; the two system interrupts have	1497	/* send specific EOI; the two system interrupts have
1498	* bit 4 set for a separate vector but behave as the	1498	* bit 4 set for a separate vector but behave as the
1499	* corresponding 3 bit intr */	1499	* corresponding 3 bit intr */
1500	outb_p(0x60\|(cpi & 7),0x20);	1500	outb_p(0x60\|(cpi & 7),0x20);
1501		1501
1502	#ifdef VOYAGER_DEBUG	1502	#ifdef VOYAGER_DEBUG
1503	if((vic_read_isr() & (1<<(cpi &7))) != 0) {	1503	if((vic_read_isr() & (1<<(cpi &7))) != 0) {
1504	printk("VOYAGER SMP: CPU%d still asserting CPI%d\n", cpu, cpi);	1504	printk("VOYAGER SMP: CPU%d still asserting CPI%d\n", cpu, cpi);
1505	}	1505	}
1506	local_irq_restore(flags);	1506	local_irq_restore(flags);
1507	#endif	1507	#endif
1508	}	1508	}
1509		1509
1510	/* cribbed with thanks from irq.c */	1510	/* cribbed with thanks from irq.c */
1511	#define __byte(x,y) (((unsigned char *)&(y))[x])	1511	#define __byte(x,y) (((unsigned char *)&(y))[x])
1512	#define cached_21(cpu) (__byte(0,vic_irq_mask[cpu]))	1512	#define cached_21(cpu) (__byte(0,vic_irq_mask[cpu]))
1513	#define cached_A1(cpu) (__byte(1,vic_irq_mask[cpu]))	1513	#define cached_A1(cpu) (__byte(1,vic_irq_mask[cpu]))
1514		1514
1515	static unsigned int	1515	static unsigned int
1516	startup_vic_irq(unsigned int irq)	1516	startup_vic_irq(unsigned int irq)
1517	{	1517	{
1518	enable_vic_irq(irq);	1518	enable_vic_irq(irq);
1519		1519
1520	return 0;	1520	return 0;
1521	}	1521	}
1522		1522
1523	/* The enable and disable routines. This is where we run into	1523	/* The enable and disable routines. This is where we run into
1524	* conflicting architectural philosophy. Fundamentally, the voyager	1524	* conflicting architectural philosophy. Fundamentally, the voyager
1525	* architecture does not expect to have to disable interrupts globally	1525	* architecture does not expect to have to disable interrupts globally
1526	* (the IRQ controllers belong to each CPU). The processor masquerade	1526	* (the IRQ controllers belong to each CPU). The processor masquerade
1527	* which is used to start the system shouldn't be used in a running OS	1527	* which is used to start the system shouldn't be used in a running OS
1528	* since it will cause great confusion if two separate CPUs drive to	1528	* since it will cause great confusion if two separate CPUs drive to
1529	* the same IRQ controller (I know, I've tried it).	1529	* the same IRQ controller (I know, I've tried it).
1530	*	1530	*
1531	* The solution is a variant on the NCR lazy SPL design:	1531	* The solution is a variant on the NCR lazy SPL design:
1532	*	1532	*
1533	* 1) To disable an interrupt, do nothing (other than set the	1533	* 1) To disable an interrupt, do nothing (other than set the
1534	* IRQ_DISABLED flag). This dares the interrupt actually to arrive.	1534	* IRQ_DISABLED flag). This dares the interrupt actually to arrive.
1535	*	1535	*
1536	* 2) If the interrupt dares to come in, raise the local mask against	1536	* 2) If the interrupt dares to come in, raise the local mask against
1537	* it (this will result in all the CPU masks being raised	1537	* it (this will result in all the CPU masks being raised
1538	* eventually).	1538	* eventually).
1539	*	1539	*
1540	* 3) To enable the interrupt, lower the mask on the local CPU and	1540	* 3) To enable the interrupt, lower the mask on the local CPU and
1541	* broadcast an Interrupt enable CPI which causes all other CPUs to	1541	* broadcast an Interrupt enable CPI which causes all other CPUs to
1542	* adjust their masks accordingly. */	1542	* adjust their masks accordingly. */
1543		1543
1544	static void	1544	static void
1545	enable_vic_irq(unsigned int irq)	1545	enable_vic_irq(unsigned int irq)
1546	{	1546	{
1547	/* linux doesn't to processor-irq affinity, so enable on	1547	/* linux doesn't to processor-irq affinity, so enable on
1548	* all CPUs we know about */	1548	* all CPUs we know about */
1549	int cpu = smp_processor_id(), real_cpu;	1549	int cpu = smp_processor_id(), real_cpu;
1550	__u16 mask = (1<<irq);	1550	__u16 mask = (1<<irq);
1551	__u32 processorList = 0;	1551	__u32 processorList = 0;
1552	unsigned long flags;	1552	unsigned long flags;
1553		1553
1554	VDEBUG(("VOYAGER: enable_vic_irq(%d) CPU%d affinity 0x%lx\n",	1554	VDEBUG(("VOYAGER: enable_vic_irq(%d) CPU%d affinity 0x%lx\n",
1555	irq, cpu, cpu_irq_affinity[cpu]));	1555	irq, cpu, cpu_irq_affinity[cpu]));
1556	spin_lock_irqsave(&vic_irq_lock, flags);	1556	spin_lock_irqsave(&vic_irq_lock, flags);
1557	for_each_online_cpu(real_cpu) {	1557	for_each_online_cpu(real_cpu) {
1558	if(!(voyager_extended_vic_processors & (1<<real_cpu)))	1558	if(!(voyager_extended_vic_processors & (1<<real_cpu)))
1559	continue;	1559	continue;
1560	if(!(cpu_irq_affinity[real_cpu] & mask)) {	1560	if(!(cpu_irq_affinity[real_cpu] & mask)) {
1561	/* irq has no affinity for this CPU, ignore */	1561	/* irq has no affinity for this CPU, ignore */
1562	continue;	1562	continue;
1563	}	1563	}
1564	if(real_cpu == cpu) {	1564	if(real_cpu == cpu) {
1565	enable_local_vic_irq(irq);	1565	enable_local_vic_irq(irq);
1566	}	1566	}
1567	else if(vic_irq_mask[real_cpu] & mask) {	1567	else if(vic_irq_mask[real_cpu] & mask) {
1568	vic_irq_enable_mask[real_cpu] \|= mask;	1568	vic_irq_enable_mask[real_cpu] \|= mask;
1569	processorList \|= (1<<real_cpu);	1569	processorList \|= (1<<real_cpu);
1570	}	1570	}
1571	}	1571	}
1572	spin_unlock_irqrestore(&vic_irq_lock, flags);	1572	spin_unlock_irqrestore(&vic_irq_lock, flags);
1573	if(processorList)	1573	if(processorList)
1574	send_CPI(processorList, VIC_ENABLE_IRQ_CPI);	1574	send_CPI(processorList, VIC_ENABLE_IRQ_CPI);
1575	}	1575	}
1576		1576
1577	static void	1577	static void
1578	disable_vic_irq(unsigned int irq)	1578	disable_vic_irq(unsigned int irq)
1579	{	1579	{
1580	/* lazy disable, do nothing */	1580	/* lazy disable, do nothing */
1581	}	1581	}
1582		1582
1583	static void	1583	static void
1584	enable_local_vic_irq(unsigned int irq)	1584	enable_local_vic_irq(unsigned int irq)
1585	{	1585	{
1586	__u8 cpu = smp_processor_id();	1586	__u8 cpu = smp_processor_id();
1587	__u16 mask = ~(1 << irq);	1587	__u16 mask = ~(1 << irq);
1588	__u16 old_mask = vic_irq_mask[cpu];	1588	__u16 old_mask = vic_irq_mask[cpu];
1589		1589
1590	vic_irq_mask[cpu] &= mask;	1590	vic_irq_mask[cpu] &= mask;
1591	if(vic_irq_mask[cpu] == old_mask)	1591	if(vic_irq_mask[cpu] == old_mask)
1592	return;	1592	return;
1593		1593
1594	VDEBUG(("VOYAGER DEBUG: Enabling irq %d in hardware on CPU %d\n",	1594	VDEBUG(("VOYAGER DEBUG: Enabling irq %d in hardware on CPU %d\n",
1595	irq, cpu));	1595	irq, cpu));
1596		1596
1597	if (irq & 8) {	1597	if (irq & 8) {
1598	outb_p(cached_A1(cpu),0xA1);	1598	outb_p(cached_A1(cpu),0xA1);
1599	(void)inb_p(0xA1);	1599	(void)inb_p(0xA1);
1600	}	1600	}
1601	else {	1601	else {
1602	outb_p(cached_21(cpu),0x21);	1602	outb_p(cached_21(cpu),0x21);
1603	(void)inb_p(0x21);	1603	(void)inb_p(0x21);
1604	}	1604	}
1605	}	1605	}
1606		1606
1607	static void	1607	static void
1608	disable_local_vic_irq(unsigned int irq)	1608	disable_local_vic_irq(unsigned int irq)
1609	{	1609	{
1610	__u8 cpu = smp_processor_id();	1610	__u8 cpu = smp_processor_id();
1611	__u16 mask = (1 << irq);	1611	__u16 mask = (1 << irq);
1612	__u16 old_mask = vic_irq_mask[cpu];	1612	__u16 old_mask = vic_irq_mask[cpu];
1613		1613
1614	if(irq == 7)	1614	if(irq == 7)
1615	return;	1615	return;
1616		1616
1617	vic_irq_mask[cpu] \|= mask;	1617	vic_irq_mask[cpu] \|= mask;
1618	if(old_mask == vic_irq_mask[cpu])	1618	if(old_mask == vic_irq_mask[cpu])
1619	return;	1619	return;
1620		1620
1621	VDEBUG(("VOYAGER DEBUG: Disabling irq %d in hardware on CPU %d\n",	1621	VDEBUG(("VOYAGER DEBUG: Disabling irq %d in hardware on CPU %d\n",
1622	irq, cpu));	1622	irq, cpu));
1623		1623
1624	if (irq & 8) {	1624	if (irq & 8) {
1625	outb_p(cached_A1(cpu),0xA1);	1625	outb_p(cached_A1(cpu),0xA1);
1626	(void)inb_p(0xA1);	1626	(void)inb_p(0xA1);
1627	}	1627	}
1628	else {	1628	else {
1629	outb_p(cached_21(cpu),0x21);	1629	outb_p(cached_21(cpu),0x21);
1630	(void)inb_p(0x21);	1630	(void)inb_p(0x21);
1631	}	1631	}
1632	}	1632	}
1633		1633
1634	/* The VIC is level triggered, so the ack can only be issued after the	1634	/* The VIC is level triggered, so the ack can only be issued after the
1635	* interrupt completes. However, we do Voyager lazy interrupt	1635	* interrupt completes. However, we do Voyager lazy interrupt
1636	* handling here: It is an extremely expensive operation to mask an	1636	* handling here: It is an extremely expensive operation to mask an
1637	* interrupt in the vic, so we merely set a flag (IRQ_DISABLED). If	1637	* interrupt in the vic, so we merely set a flag (IRQ_DISABLED). If
1638	* this interrupt actually comes in, then we mask and ack here to push	1638	* this interrupt actually comes in, then we mask and ack here to push
1639	* the interrupt off to another CPU */	1639	* the interrupt off to another CPU */
1640	static void	1640	static void
1641	before_handle_vic_irq(unsigned int irq)	1641	before_handle_vic_irq(unsigned int irq)
1642	{	1642	{
1643	irq_desc_t *desc = irq_desc + irq;	1643	irq_desc_t *desc = irq_desc + irq;
1644	__u8 cpu = smp_processor_id();	1644	__u8 cpu = smp_processor_id();
1645		1645
1646	_raw_spin_lock(&vic_irq_lock);	1646	_raw_spin_lock(&vic_irq_lock);
1647	vic_intr_total++;	1647	vic_intr_total++;
1648	vic_intr_count[cpu]++;	1648	vic_intr_count[cpu]++;
1649		1649
1650	if(!(cpu_irq_affinity[cpu] & (1<<irq))) {	1650	if(!(cpu_irq_affinity[cpu] & (1<<irq))) {
1651	/* The irq is not in our affinity mask, push it off	1651	/* The irq is not in our affinity mask, push it off
1652	* onto another CPU */	1652	* onto another CPU */
1653	VDEBUG(("VOYAGER DEBUG: affinity triggered disable of irq %d on cpu %d\n",	1653	VDEBUG(("VOYAGER DEBUG: affinity triggered disable of irq %d on cpu %d\n",
1654	irq, cpu));	1654	irq, cpu));
1655	disable_local_vic_irq(irq);	1655	disable_local_vic_irq(irq);
1656	/* set IRQ_INPROGRESS to prevent the handler in irq.c from	1656	/* set IRQ_INPROGRESS to prevent the handler in irq.c from
1657	* actually calling the interrupt routine */	1657	* actually calling the interrupt routine */
1658	desc->status \|= IRQ_REPLAY \| IRQ_INPROGRESS;	1658	desc->status \|= IRQ_REPLAY \| IRQ_INPROGRESS;
1659	} else if(desc->status & IRQ_DISABLED) {	1659	} else if(desc->status & IRQ_DISABLED) {
1660	/* Damn, the interrupt actually arrived, do the lazy	1660	/* Damn, the interrupt actually arrived, do the lazy
1661	* disable thing. The interrupt routine in irq.c will	1661	* disable thing. The interrupt routine in irq.c will
1662	* not handle a IRQ_DISABLED interrupt, so nothing more	1662	* not handle a IRQ_DISABLED interrupt, so nothing more
1663	* need be done here */	1663	* need be done here */
1664	VDEBUG(("VOYAGER DEBUG: lazy disable of irq %d on CPU %d\n",	1664	VDEBUG(("VOYAGER DEBUG: lazy disable of irq %d on CPU %d\n",
1665	irq, cpu));	1665	irq, cpu));
1666	disable_local_vic_irq(irq);	1666	disable_local_vic_irq(irq);
1667	desc->status \|= IRQ_REPLAY;	1667	desc->status \|= IRQ_REPLAY;
1668	} else {	1668	} else {
1669	desc->status &= ~IRQ_REPLAY;	1669	desc->status &= ~IRQ_REPLAY;
1670	}	1670	}
1671		1671
1672	_raw_spin_unlock(&vic_irq_lock);	1672	_raw_spin_unlock(&vic_irq_lock);
1673	}	1673	}
1674		1674
1675	/* Finish the VIC interrupt: basically mask */	1675	/* Finish the VIC interrupt: basically mask */
1676	static void	1676	static void
1677	after_handle_vic_irq(unsigned int irq)	1677	after_handle_vic_irq(unsigned int irq)
1678	{	1678	{
1679	irq_desc_t *desc = irq_desc + irq;	1679	irq_desc_t *desc = irq_desc + irq;
1680		1680
1681	_raw_spin_lock(&vic_irq_lock);	1681	_raw_spin_lock(&vic_irq_lock);
1682	{	1682	{
1683	unsigned int status = desc->status & ~IRQ_INPROGRESS;	1683	unsigned int status = desc->status & ~IRQ_INPROGRESS;
1684	#ifdef VOYAGER_DEBUG	1684	#ifdef VOYAGER_DEBUG
1685	__u16 isr;	1685	__u16 isr;
1686	#endif	1686	#endif
1687		1687
1688	desc->status = status;	1688	desc->status = status;
1689	if ((status & IRQ_DISABLED))	1689	if ((status & IRQ_DISABLED))
1690	disable_local_vic_irq(irq);	1690	disable_local_vic_irq(irq);
1691	#ifdef VOYAGER_DEBUG	1691	#ifdef VOYAGER_DEBUG
1692	/* DEBUG: before we ack, check what's in progress */	1692	/* DEBUG: before we ack, check what's in progress */
1693	isr = vic_read_isr();	1693	isr = vic_read_isr();
1694	if((isr & (1<<irq) && !(status & IRQ_REPLAY)) == 0) {	1694	if((isr & (1<<irq) && !(status & IRQ_REPLAY)) == 0) {
1695	int i;	1695	int i;
1696	__u8 cpu = smp_processor_id();	1696	__u8 cpu = smp_processor_id();
1697	__u8 real_cpu;	1697	__u8 real_cpu;
1698	int mask; /* Um... initialize me??? --RR */	1698	int mask; /* Um... initialize me??? --RR */
1699		1699
1700	printk("VOYAGER SMP: CPU%d lost interrupt %d\n",	1700	printk("VOYAGER SMP: CPU%d lost interrupt %d\n",
1701	cpu, irq);	1701	cpu, irq);
1702	for_each_cpu(real_cpu, mask) {	1702	for_each_cpu(real_cpu, mask) {
1703		1703
1704	outb(VIC_CPU_MASQUERADE_ENABLE \| real_cpu,	1704	outb(VIC_CPU_MASQUERADE_ENABLE \| real_cpu,
1705	VIC_PROCESSOR_ID);	1705	VIC_PROCESSOR_ID);
1706	isr = vic_read_isr();	1706	isr = vic_read_isr();
1707	if(isr & (1<<irq)) {	1707	if(isr & (1<<irq)) {
1708	printk("VOYAGER SMP: CPU%d ack irq %d\n",	1708	printk("VOYAGER SMP: CPU%d ack irq %d\n",
1709	real_cpu, irq);	1709	real_cpu, irq);
1710	ack_vic_irq(irq);	1710	ack_vic_irq(irq);
1711	}	1711	}
1712	outb(cpu, VIC_PROCESSOR_ID);	1712	outb(cpu, VIC_PROCESSOR_ID);
1713	}	1713	}
1714	}	1714	}
1715	#endif /* VOYAGER_DEBUG */	1715	#endif /* VOYAGER_DEBUG */
1716	/* as soon as we ack, the interrupt is eligible for	1716	/* as soon as we ack, the interrupt is eligible for
1717	* receipt by another CPU so everything must be in	1717	* receipt by another CPU so everything must be in
1718	* order here */	1718	* order here */
1719	ack_vic_irq(irq);	1719	ack_vic_irq(irq);
1720	if(status & IRQ_REPLAY) {	1720	if(status & IRQ_REPLAY) {
1721	/* replay is set if we disable the interrupt	1721	/* replay is set if we disable the interrupt
1722	* in the before_handle_vic_irq() routine, so	1722	* in the before_handle_vic_irq() routine, so
1723	* clear the in progress bit here to allow the	1723	* clear the in progress bit here to allow the
1724	* next CPU to handle this correctly */	1724	* next CPU to handle this correctly */
1725	desc->status &= ~(IRQ_REPLAY \| IRQ_INPROGRESS);	1725	desc->status &= ~(IRQ_REPLAY \| IRQ_INPROGRESS);
1726	}	1726	}
1727	#ifdef VOYAGER_DEBUG	1727	#ifdef VOYAGER_DEBUG
1728	isr = vic_read_isr();	1728	isr = vic_read_isr();
1729	if((isr & (1<<irq)) != 0)	1729	if((isr & (1<<irq)) != 0)
1730	printk("VOYAGER SMP: after_handle_vic_irq() after ack irq=%d, isr=0x%x\n",	1730	printk("VOYAGER SMP: after_handle_vic_irq() after ack irq=%d, isr=0x%x\n",
1731	irq, isr);	1731	irq, isr);
1732	#endif /* VOYAGER_DEBUG */	1732	#endif /* VOYAGER_DEBUG */
1733	}	1733	}
1734	_raw_spin_unlock(&vic_irq_lock);	1734	_raw_spin_unlock(&vic_irq_lock);
1735		1735
1736	/* All code after this point is out of the main path - the IRQ	1736	/* All code after this point is out of the main path - the IRQ
1737	* may be intercepted by another CPU if reasserted */	1737	* may be intercepted by another CPU if reasserted */
1738	}	1738	}
1739		1739
1740		1740
1741	/* Linux processor - interrupt affinity manipulations.	1741	/* Linux processor - interrupt affinity manipulations.
1742	*	1742	*
1743	* For each processor, we maintain a 32 bit irq affinity mask.	1743	* For each processor, we maintain a 32 bit irq affinity mask.
1744	* Initially it is set to all 1's so every processor accepts every	1744	* Initially it is set to all 1's so every processor accepts every
1745	* interrupt. In this call, we change the processor's affinity mask:	1745	* interrupt. In this call, we change the processor's affinity mask:
1746	*	1746	*
1747	* Change from enable to disable:	1747	* Change from enable to disable:
1748	*	1748	*
1749	* If the interrupt ever comes in to the processor, we will disable it	1749	* If the interrupt ever comes in to the processor, we will disable it
1750	* and ack it to push it off to another CPU, so just accept the mask here.	1750	* and ack it to push it off to another CPU, so just accept the mask here.
1751	*	1751	*
1752	* Change from disable to enable:	1752	* Change from disable to enable:
1753	*	1753	*
1754	* change the mask and then do an interrupt enable CPI to re-enable on	1754	* change the mask and then do an interrupt enable CPI to re-enable on
1755	* the selected processors */	1755	* the selected processors */
1756		1756
1757	void	1757	void
1758	set_vic_irq_affinity(unsigned int irq, cpumask_t mask)	1758	set_vic_irq_affinity(unsigned int irq, cpumask_t mask)
1759	{	1759	{
1760	/* Only extended processors handle interrupts */	1760	/* Only extended processors handle interrupts */
1761	unsigned long real_mask;	1761	unsigned long real_mask;
1762	unsigned long irq_mask = 1 << irq;	1762	unsigned long irq_mask = 1 << irq;
1763	int cpu;	1763	int cpu;
1764		1764
1765	real_mask = cpus_addr(mask)[0] & voyager_extended_vic_processors;	1765	real_mask = cpus_addr(mask)[0] & voyager_extended_vic_processors;
1766		1766
1767	if(cpus_addr(mask)[0] == 0)	1767	if(cpus_addr(mask)[0] == 0)
1768	/* can't have no cpu's to accept the interrupt -- extremely	1768	/* can't have no cpu's to accept the interrupt -- extremely
1769	* bad things will happen */	1769	* bad things will happen */
1770	return;	1770	return;
1771		1771
1772	if(irq == 0)	1772	if(irq == 0)
1773	/* can't change the affinity of the timer IRQ. This	1773	/* can't change the affinity of the timer IRQ. This
1774	* is due to the constraint in the voyager	1774	* is due to the constraint in the voyager
1775	* architecture that the CPI also comes in on and IRQ	1775	* architecture that the CPI also comes in on and IRQ
1776	* line and we have chosen IRQ0 for this. If you	1776	* line and we have chosen IRQ0 for this. If you
1777	* raise the mask on this interrupt, the processor	1777	* raise the mask on this interrupt, the processor
1778	* will no-longer be able to accept VIC CPIs */	1778	* will no-longer be able to accept VIC CPIs */
1779	return;	1779	return;
1780		1780
1781	if(irq >= 32)	1781	if(irq >= 32)
1782	/* You can only have 32 interrupts in a voyager system	1782	/* You can only have 32 interrupts in a voyager system
1783	* (and 32 only if you have a secondary microchannel	1783	* (and 32 only if you have a secondary microchannel
1784	* bus) */	1784	* bus) */
1785	return;	1785	return;
1786		1786
1787	for_each_online_cpu(cpu) {	1787	for_each_online_cpu(cpu) {
1788	unsigned long cpu_mask = 1 << cpu;	1788	unsigned long cpu_mask = 1 << cpu;
1789		1789
1790	if(cpu_mask & real_mask) {	1790	if(cpu_mask & real_mask) {
1791	/* enable the interrupt for this cpu */	1791	/* enable the interrupt for this cpu */
1792	cpu_irq_affinity[cpu] \|= irq_mask;	1792	cpu_irq_affinity[cpu] \|= irq_mask;
1793	} else {	1793	} else {
1794	/* disable the interrupt for this cpu */	1794	/* disable the interrupt for this cpu */
1795	cpu_irq_affinity[cpu] &= ~irq_mask;	1795	cpu_irq_affinity[cpu] &= ~irq_mask;
1796	}	1796	}
1797	}	1797	}
1798	/* this is magic, we now have the correct affinity maps, so	1798	/* this is magic, we now have the correct affinity maps, so
1799	* enable the interrupt. This will send an enable CPI to	1799	* enable the interrupt. This will send an enable CPI to
1800	* those cpu's who need to enable it in their local masks,	1800	* those cpu's who need to enable it in their local masks,
1801	* causing them to correct for the new affinity . If the	1801	* causing them to correct for the new affinity . If the
1802	* interrupt is currently globally disabled, it will simply be	1802	* interrupt is currently globally disabled, it will simply be
1803	* disabled again as it comes in (voyager lazy disable). If	1803	* disabled again as it comes in (voyager lazy disable). If
1804	* the affinity map is tightened to disable the interrupt on a	1804	* the affinity map is tightened to disable the interrupt on a
1805	* cpu, it will be pushed off when it comes in */	1805	* cpu, it will be pushed off when it comes in */
1806	enable_vic_irq(irq);	1806	enable_vic_irq(irq);
1807	}	1807	}
1808		1808
1809	static void	1809	static void
1810	ack_vic_irq(unsigned int irq)	1810	ack_vic_irq(unsigned int irq)
1811	{	1811	{
1812	if (irq & 8) {	1812	if (irq & 8) {
1813	outb(0x62,0x20); /* Specific EOI to cascade */	1813	outb(0x62,0x20); /* Specific EOI to cascade */
1814	outb(0x60\|(irq & 7),0xA0);	1814	outb(0x60\|(irq & 7),0xA0);
1815	} else {	1815	} else {
1816	outb(0x60 \| (irq & 7),0x20);	1816	outb(0x60 \| (irq & 7),0x20);
1817	}	1817	}
1818	}	1818	}
1819		1819
1820	/* enable the CPIs. In the VIC, the CPIs are delivered by the 8259	1820	/* enable the CPIs. In the VIC, the CPIs are delivered by the 8259
1821	* but are not vectored by it. This means that the 8259 mask must be	1821	* but are not vectored by it. This means that the 8259 mask must be
1822	* lowered to receive them */	1822	* lowered to receive them */
1823	static __init void	1823	static __init void
1824	vic_enable_cpi(void)	1824	vic_enable_cpi(void)
1825	{	1825	{
1826	__u8 cpu = smp_processor_id();	1826	__u8 cpu = smp_processor_id();
1827		1827
1828	/* just take a copy of the current mask (nop for boot cpu) */	1828	/* just take a copy of the current mask (nop for boot cpu) */
1829	vic_irq_mask[cpu] = vic_irq_mask[boot_cpu_id];	1829	vic_irq_mask[cpu] = vic_irq_mask[boot_cpu_id];
1830		1830
1831	enable_local_vic_irq(VIC_CPI_LEVEL0);	1831	enable_local_vic_irq(VIC_CPI_LEVEL0);
1832	enable_local_vic_irq(VIC_CPI_LEVEL1);	1832	enable_local_vic_irq(VIC_CPI_LEVEL1);
1833	/* for sys int and cmn int */	1833	/* for sys int and cmn int */
1834	enable_local_vic_irq(7);	1834	enable_local_vic_irq(7);
1835		1835
1836	if(is_cpu_quad()) {	1836	if(is_cpu_quad()) {
1837	outb(QIC_DEFAULT_MASK0, QIC_MASK_REGISTER0);	1837	outb(QIC_DEFAULT_MASK0, QIC_MASK_REGISTER0);
1838	outb(QIC_CPI_ENABLE, QIC_MASK_REGISTER1);	1838	outb(QIC_CPI_ENABLE, QIC_MASK_REGISTER1);
1839	VDEBUG(("VOYAGER SMP: QIC ENABLE CPI: CPU%d: MASK 0x%x\n",	1839	VDEBUG(("VOYAGER SMP: QIC ENABLE CPI: CPU%d: MASK 0x%x\n",
1840	cpu, QIC_CPI_ENABLE));	1840	cpu, QIC_CPI_ENABLE));
1841	}	1841	}
1842		1842
1843	VDEBUG(("VOYAGER SMP: ENABLE CPI: CPU%d: MASK 0x%x\n",	1843	VDEBUG(("VOYAGER SMP: ENABLE CPI: CPU%d: MASK 0x%x\n",
1844	cpu, vic_irq_mask[cpu]));	1844	cpu, vic_irq_mask[cpu]));
1845	}	1845	}
1846		1846
1847	void	1847	void
1848	voyager_smp_dump()	1848	voyager_smp_dump()
1849	{	1849	{
1850	int old_cpu = smp_processor_id(), cpu;	1850	int old_cpu = smp_processor_id(), cpu;
1851		1851
1852	/* dump the interrupt masks of each processor */	1852	/* dump the interrupt masks of each processor */
1853	for_each_online_cpu(cpu) {	1853	for_each_online_cpu(cpu) {
1854	__u16 imr, isr, irr;	1854	__u16 imr, isr, irr;
1855	unsigned long flags;	1855	unsigned long flags;
1856		1856
1857	local_irq_save(flags);	1857	local_irq_save(flags);
1858	outb(VIC_CPU_MASQUERADE_ENABLE \| cpu, VIC_PROCESSOR_ID);	1858	outb(VIC_CPU_MASQUERADE_ENABLE \| cpu, VIC_PROCESSOR_ID);
1859	imr = (inb(0xa1) << 8) \| inb(0x21);	1859	imr = (inb(0xa1) << 8) \| inb(0x21);
1860	outb(0x0a, 0xa0);	1860	outb(0x0a, 0xa0);
1861	irr = inb(0xa0) << 8;	1861	irr = inb(0xa0) << 8;
1862	outb(0x0a, 0x20);	1862	outb(0x0a, 0x20);
1863	irr \|= inb(0x20);	1863	irr \|= inb(0x20);
1864	outb(0x0b, 0xa0);	1864	outb(0x0b, 0xa0);
1865	isr = inb(0xa0) << 8;	1865	isr = inb(0xa0) << 8;
1866	outb(0x0b, 0x20);	1866	outb(0x0b, 0x20);
1867	isr \|= inb(0x20);	1867	isr \|= inb(0x20);
1868	outb(old_cpu, VIC_PROCESSOR_ID);	1868	outb(old_cpu, VIC_PROCESSOR_ID);
1869	local_irq_restore(flags);	1869	local_irq_restore(flags);
1870	printk("\tCPU%d: mask=0x%x, IMR=0x%x, IRR=0x%x, ISR=0x%x\n",	1870	printk("\tCPU%d: mask=0x%x, IMR=0x%x, IRR=0x%x, ISR=0x%x\n",
1871	cpu, vic_irq_mask[cpu], imr, irr, isr);	1871	cpu, vic_irq_mask[cpu], imr, irr, isr);
1872	#if 0	1872	#if 0
1873	/* These lines are put in to try to unstick an un ack'd irq */	1873	/* These lines are put in to try to unstick an un ack'd irq */
1874	if(isr != 0) {	1874	if(isr != 0) {
1875	int irq;	1875	int irq;
1876	for(irq=0; irq<16; irq++) {	1876	for(irq=0; irq<16; irq++) {
1877	if(isr & (1<<irq)) {	1877	if(isr & (1<<irq)) {
1878	printk("\tCPU%d: ack irq %d\n",	1878	printk("\tCPU%d: ack irq %d\n",
1879	cpu, irq);	1879	cpu, irq);
1880	local_irq_save(flags);	1880	local_irq_save(flags);
1881	outb(VIC_CPU_MASQUERADE_ENABLE \| cpu,	1881	outb(VIC_CPU_MASQUERADE_ENABLE \| cpu,
1882	VIC_PROCESSOR_ID);	1882	VIC_PROCESSOR_ID);
1883	ack_vic_irq(irq);	1883	ack_vic_irq(irq);
1884	outb(old_cpu, VIC_PROCESSOR_ID);	1884	outb(old_cpu, VIC_PROCESSOR_ID);
1885	local_irq_restore(flags);	1885	local_irq_restore(flags);
1886	}	1886	}
1887	}	1887	}
1888	}	1888	}
1889	#endif	1889	#endif
1890	}	1890	}
1891	}	1891	}
1892		1892
1893	void	1893	void
1894	smp_voyager_power_off(void *dummy)	1894	smp_voyager_power_off(void *dummy)
1895	{	1895	{
1896	if(smp_processor_id() == boot_cpu_id)	1896	if(smp_processor_id() == boot_cpu_id)
1897	voyager_power_off();	1897	voyager_power_off();
1898	else	1898	else
1899	smp_stop_cpu_function(NULL);	1899	smp_stop_cpu_function(NULL);
1900	}	1900	}
1901		1901
1902	void __init	1902	void __init
1903	smp_prepare_cpus(unsigned int max_cpus)	1903	smp_prepare_cpus(unsigned int max_cpus)
1904	{	1904	{
1905	/* FIXME: ignore max_cpus for now */	1905	/* FIXME: ignore max_cpus for now */
1906	smp_boot_cpus();	1906	smp_boot_cpus();
1907	}	1907	}
1908		1908
1909	void __devinit smp_prepare_boot_cpu(void)	1909	void __devinit smp_prepare_boot_cpu(void)
1910	{	1910	{
1911	cpu_set(smp_processor_id(), cpu_online_map);	1911	cpu_set(smp_processor_id(), cpu_online_map);
1912	cpu_set(smp_processor_id(), cpu_callout_map);	1912	cpu_set(smp_processor_id(), cpu_callout_map);
1913	}	1913	}
1914		1914
1915	int __devinit	1915	int __devinit
1916	__cpu_up(unsigned int cpu)	1916	__cpu_up(unsigned int cpu)
1917	{	1917	{
1918	/* This only works at boot for x86. See "rewrite" above. */	1918	/* This only works at boot for x86. See "rewrite" above. */
1919	if (cpu_isset(cpu, smp_commenced_mask))	1919	if (cpu_isset(cpu, smp_commenced_mask))
1920	return -ENOSYS;	1920	return -ENOSYS;
1921		1921
1922	/* In case one didn't come up */	1922	/* In case one didn't come up */
1923	if (!cpu_isset(cpu, cpu_callin_map))	1923	if (!cpu_isset(cpu, cpu_callin_map))
1924	return -EIO;	1924	return -EIO;
1925	/* Unleash the CPU! */	1925	/* Unleash the CPU! */
1926	cpu_set(cpu, smp_commenced_mask);	1926	cpu_set(cpu, smp_commenced_mask);
1927	while (!cpu_isset(cpu, cpu_online_map))	1927	while (!cpu_isset(cpu, cpu_online_map))
1928	mb();	1928	mb();
1929	return 0;	1929	return 0;
1930	}	1930	}
1931		1931
1932	void __init	1932	void __init
1933	smp_cpus_done(unsigned int max_cpus)	1933	smp_cpus_done(unsigned int max_cpus)
1934	{	1934	{
1935	zap_low_mappings();	1935	zap_low_mappings();
1936	}	1936	}
1937		1937

include/asm-i386/msr.h

Diff comments View file @ f2ab446

 #ifndef __ASM_MSR_H
 #define __ASM_MSR_H
 /*
  * Access to machine-specific registers (available on 586 and better only)
  * Note: the rd* operations modify the parameters directly (without using
  * pointer indirection), this allows gcc to optimize better
  */
 #define rdmsr(msr,val1,val2) \
 	__asm__ __volatile__("rdmsr" \
 			  : "=a" (val1), "=d" (val2) \
 			  : "c" (msr))
 #define wrmsr(msr,val1,val2) \
 	__asm__ __volatile__("wrmsr" \
 			  : /* no outputs */ \
 			  : "c" (msr), "a" (val1), "d" (val2))
 #define rdmsrl(msr,val) do { \
 	unsigned long l__,h__; \
 	rdmsr (msr, l__, h__);  \
 	val = l__;  \
 	val |= ((u64)h__<<32);  \
 } while(0)
 static inline void wrmsrl (unsigned long msr, unsigned long long val)
 {
 	unsigned long lo, hi;
 	lo = (unsigned long) val;
 	hi = val >> 32;
 	wrmsr (msr, lo, hi);
 }
 /* wrmsr with exception handling */
 #define wrmsr_safe(msr,a,b) ({ int ret__;						\
 	asm volatile("2: wrmsr ; xorl %0,%0\n"						\
 		     "1:\n\t"								\
 		     ".section .fixup,\"ax\"\n\t"					\
 		     "3:  movl %4,%0 ; jmp 1b\n\t"					\
 		     ".previous\n\t"							\
  		     ".section __ex_table,\"a\"\n"					\
 		     "   .align 4\n\t"							\
 		     "   .long 	2b,3b\n\t"						\
 		     ".previous"							\
 		     : "=a" (ret__)							\
 		     : "c" (msr), "0" (a), "d" (b), "i" (-EFAULT));\
 	ret__; })
+/* rdmsr with exception handling */
+#define rdmsr_safe(msr,a,b) ({ int ret__;						\
+	asm volatile("2: rdmsr ; xorl %0,%0\n"						\
+		     "1:\n\t"								\
+		     ".section .fixup,\"ax\"\n\t"					\
+		     "3:  movl %4,%0 ; jmp 1b\n\t"					\
+		     ".previous\n\t"							\
+ 		     ".section __ex_table,\"a\"\n"					\
+		     "   .align 4\n\t"							\
+		     "   .long 	2b,3b\n\t"						\
+		     ".previous"							\
+		     : "=r" (ret__), "=a" (*(a)), "=d" (*(b))				\
+		     : "c" (msr), "i" (-EFAULT));\
+	ret__; })
 #define rdtsc(low,high) \
      __asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high))
 #define rdtscl(low) \
      __asm__ __volatile__("rdtsc" : "=a" (low) : : "edx")
 #define rdtscll(val) \
      __asm__ __volatile__("rdtsc" : "=A" (val))
 #define write_tsc(val1,val2) wrmsr(0x10, val1, val2)
 #define rdpmc(counter,low,high) \
      __asm__ __volatile__("rdpmc" \
 			  : "=a" (low), "=d" (high) \
 			  : "c" (counter))
 /* symbolic names for some interesting MSRs */
 /* Intel defined MSRs. */
 #define MSR_IA32_P5_MC_ADDR		0
 #define MSR_IA32_P5_MC_TYPE		1
 #define MSR_IA32_PLATFORM_ID		0x17
 #define MSR_IA32_EBL_CR_POWERON		0x2a
 #define MSR_IA32_APICBASE		0x1b
 #define MSR_IA32_APICBASE_BSP		(1<<8)
 #define MSR_IA32_APICBASE_ENABLE	(1<<11)
 #define MSR_IA32_APICBASE_BASE		(0xfffff<<12)
 #define MSR_IA32_UCODE_WRITE		0x79
 #define MSR_IA32_UCODE_REV		0x8b
 #define MSR_P6_PERFCTR0		0xc1
 #define MSR_P6_PERFCTR1		0xc2
 #define MSR_IA32_BBL_CR_CTL		0x119
 #define MSR_IA32_SYSENTER_CS		0x174
 #define MSR_IA32_SYSENTER_ESP		0x175
 #define MSR_IA32_SYSENTER_EIP		0x176
 #define MSR_IA32_MCG_CAP		0x179
 #define MSR_IA32_MCG_STATUS		0x17a
 #define MSR_IA32_MCG_CTL		0x17b
 /* P4/Xeon+ specific */
 #define MSR_IA32_MCG_EAX		0x180
 #define MSR_IA32_MCG_EBX		0x181
 #define MSR_IA32_MCG_ECX		0x182
 #define MSR_IA32_MCG_EDX		0x183
 #define MSR_IA32_MCG_ESI		0x184
 #define MSR_IA32_MCG_EDI		0x185
 #define MSR_IA32_MCG_EBP		0x186
 #define MSR_IA32_MCG_ESP		0x187
 #define MSR_IA32_MCG_EFLAGS		0x188
 #define MSR_IA32_MCG_EIP		0x189
 #define MSR_IA32_MCG_RESERVED		0x18A
 #define MSR_P6_EVNTSEL0			0x186
 #define MSR_P6_EVNTSEL1			0x187
 #define MSR_IA32_PERF_STATUS		0x198
 #define MSR_IA32_PERF_CTL		0x199
 #define MSR_IA32_THERM_CONTROL		0x19a
 #define MSR_IA32_THERM_INTERRUPT	0x19b
 #define MSR_IA32_THERM_STATUS		0x19c
 #define MSR_IA32_MISC_ENABLE		0x1a0
 #define MSR_IA32_DEBUGCTLMSR		0x1d9
 #define MSR_IA32_LASTBRANCHFROMIP	0x1db
 #define MSR_IA32_LASTBRANCHTOIP		0x1dc
 #define MSR_IA32_LASTINTFROMIP		0x1dd
 #define MSR_IA32_LASTINTTOIP		0x1de
 #define MSR_IA32_MC0_CTL		0x400
 #define MSR_IA32_MC0_STATUS		0x401
 #define MSR_IA32_MC0_ADDR		0x402
 #define MSR_IA32_MC0_MISC		0x403
 /* Pentium IV performance counter MSRs */
 #define MSR_P4_BPU_PERFCTR0 		0x300
 #define MSR_P4_BPU_PERFCTR1 		0x301
 #define MSR_P4_BPU_PERFCTR2 		0x302
 #define MSR_P4_BPU_PERFCTR3 		0x303
 #define MSR_P4_MS_PERFCTR0 		0x304
 #define MSR_P4_MS_PERFCTR1 		0x305
 #define MSR_P4_MS_PERFCTR2 		0x306
 #define MSR_P4_MS_PERFCTR3 		0x307
 #define MSR_P4_FLAME_PERFCTR0 		0x308
 #define MSR_P4_FLAME_PERFCTR1 		0x309
 #define MSR_P4_FLAME_PERFCTR2 		0x30a
 #define MSR_P4_FLAME_PERFCTR3 		0x30b
 #define MSR_P4_IQ_PERFCTR0 		0x30c
 #define MSR_P4_IQ_PERFCTR1 		0x30d
 #define MSR_P4_IQ_PERFCTR2 		0x30e
 #define MSR_P4_IQ_PERFCTR3 		0x30f
 #define MSR_P4_IQ_PERFCTR4 		0x310
 #define MSR_P4_IQ_PERFCTR5 		0x311
 #define MSR_P4_BPU_CCCR0 		0x360
 #define MSR_P4_BPU_CCCR1 		0x361
 #define MSR_P4_BPU_CCCR2 		0x362
 #define MSR_P4_BPU_CCCR3 		0x363
 #define MSR_P4_MS_CCCR0 		0x364
 #define MSR_P4_MS_CCCR1 		0x365
 #define MSR_P4_MS_CCCR2 		0x366
 #define MSR_P4_MS_CCCR3 		0x367
 #define MSR_P4_FLAME_CCCR0 		0x368
 #define MSR_P4_FLAME_CCCR1 		0x369
 #define MSR_P4_FLAME_CCCR2 		0x36a
 #define MSR_P4_FLAME_CCCR3 		0x36b
 #define MSR_P4_IQ_CCCR0 		0x36c
 #define MSR_P4_IQ_CCCR1 		0x36d
 #define MSR_P4_IQ_CCCR2 		0x36e
 #define MSR_P4_IQ_CCCR3 		0x36f
 #define MSR_P4_IQ_CCCR4 		0x370
 #define MSR_P4_IQ_CCCR5 		0x371
 #define MSR_P4_ALF_ESCR0 		0x3ca
 #define MSR_P4_ALF_ESCR1 		0x3cb
 #define MSR_P4_BPU_ESCR0 		0x3b2
 #define MSR_P4_BPU_ESCR1 		0x3b3
 #define MSR_P4_BSU_ESCR0 		0x3a0
 #define MSR_P4_BSU_ESCR1 		0x3a1
 #define MSR_P4_CRU_ESCR0 		0x3b8
 #define MSR_P4_CRU_ESCR1 		0x3b9
 #define MSR_P4_CRU_ESCR2 		0x3cc
 #define MSR_P4_CRU_ESCR3 		0x3cd
 #define MSR_P4_CRU_ESCR4 		0x3e0
 #define MSR_P4_CRU_ESCR5 		0x3e1
 #define MSR_P4_DAC_ESCR0 		0x3a8
 #define MSR_P4_DAC_ESCR1 		0x3a9
 #define MSR_P4_FIRM_ESCR0 		0x3a4
 #define MSR_P4_FIRM_ESCR1 		0x3a5
 #define MSR_P4_FLAME_ESCR0 		0x3a6
 #define MSR_P4_FLAME_ESCR1 		0x3a7
 #define MSR_P4_FSB_ESCR0 		0x3a2
 #define MSR_P4_FSB_ESCR1 		0x3a3
 #define MSR_P4_IQ_ESCR0 		0x3ba
 #define MSR_P4_IQ_ESCR1 		0x3bb
 #define MSR_P4_IS_ESCR0 		0x3b4
 #define MSR_P4_IS_ESCR1 		0x3b5
 #define MSR_P4_ITLB_ESCR0 		0x3b6
 #define MSR_P4_ITLB_ESCR1 		0x3b7
 #define MSR_P4_IX_ESCR0 		0x3c8
 #define MSR_P4_IX_ESCR1 		0x3c9
 #define MSR_P4_MOB_ESCR0 		0x3aa
 #define MSR_P4_MOB_ESCR1 		0x3ab
 #define MSR_P4_MS_ESCR0 		0x3c0
 #define MSR_P4_MS_ESCR1 		0x3c1
 #define MSR_P4_PMH_ESCR0 		0x3ac
 #define MSR_P4_PMH_ESCR1 		0x3ad
 #define MSR_P4_RAT_ESCR0 		0x3bc
 #define MSR_P4_RAT_ESCR1 		0x3bd
 #define MSR_P4_SAAT_ESCR0 		0x3ae
 #define MSR_P4_SAAT_ESCR1 		0x3af
 #define MSR_P4_SSU_ESCR0 		0x3be
 #define MSR_P4_SSU_ESCR1 		0x3bf    /* guess: not defined in manual */
 #define MSR_P4_TBPU_ESCR0 		0x3c2
 #define MSR_P4_TBPU_ESCR1 		0x3c3
 #define MSR_P4_TC_ESCR0 		0x3c4
 #define MSR_P4_TC_ESCR1 		0x3c5
 #define MSR_P4_U2L_ESCR0 		0x3b0
 #define MSR_P4_U2L_ESCR1 		0x3b1
 /* AMD Defined MSRs */
 #define MSR_K6_EFER			0xC0000080
 #define MSR_K6_STAR			0xC0000081
 #define MSR_K6_WHCR			0xC0000082
 #define MSR_K6_UWCCR			0xC0000085
 #define MSR_K6_EPMR			0xC0000086
 #define MSR_K6_PSOR			0xC0000087
 #define MSR_K6_PFIR			0xC0000088
 #define MSR_K7_EVNTSEL0			0xC0010000
 #define MSR_K7_EVNTSEL1			0xC0010001
 #define MSR_K7_EVNTSEL2			0xC0010002
 #define MSR_K7_EVNTSEL3			0xC0010003
 #define MSR_K7_PERFCTR0			0xC0010004
 #define MSR_K7_PERFCTR1			0xC0010005
 #define MSR_K7_PERFCTR2			0xC0010006
 #define MSR_K7_PERFCTR3			0xC0010007
 #define MSR_K7_HWCR			0xC0010015
 #define MSR_K7_CLK_CTL			0xC001001b
 #define MSR_K7_FID_VID_CTL		0xC0010041
 #define MSR_K7_FID_VID_STATUS		0xC0010042
 /* extended feature register */
 #define MSR_EFER 			0xc0000080
 /* EFER bits: */
 /* Execute Disable enable */
 #define _EFER_NX			11
 #define EFER_NX				(1<<_EFER_NX)
 /* Centaur-Hauls/IDT defined MSRs. */
 #define MSR_IDT_FCR1			0x107
 #define MSR_IDT_FCR2			0x108
 #define MSR_IDT_FCR3			0x109
 #define MSR_IDT_FCR4			0x10a
 #define MSR_IDT_MCR0			0x110
 #define MSR_IDT_MCR1			0x111
 #define MSR_IDT_MCR2			0x112
 #define MSR_IDT_MCR3			0x113
 #define MSR_IDT_MCR4			0x114
 #define MSR_IDT_MCR5			0x115
 #define MSR_IDT_MCR6			0x116
 #define MSR_IDT_MCR7			0x117
 #define MSR_IDT_MCR_CTRL		0x120
 /* VIA Cyrix defined MSRs*/
 #define MSR_VIA_FCR			0x1107
 #define MSR_VIA_LONGHAUL		0x110a
 #define MSR_VIA_RNG			0x110b
 #define MSR_VIA_BCR2			0x1147
 /* Transmeta defined MSRs */
 #define MSR_TMTA_LONGRUN_CTRL		0x80868010
 #define MSR_TMTA_LONGRUN_FLAGS		0x80868011
 #define MSR_TMTA_LRTI_READOUT		0x80868018
 #define MSR_TMTA_LRTI_VOLT_MHZ		0x8086801a
 #endif /* __ASM_MSR_H */