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Commit f776471f620a07be234f40288a1fd9932d039e26

Authored by Benoit Cousson
Committed by Kevin Hilman
1 parent 4fe20e97c8
Exists in master and in 4 other branches v3.2_AM335xPSP_04.06.00.11, v3.2_NEWT335xPSP_04.06.00.11, v3.2_SBC_SMARTMEN, v3.2_SMARCT335xPSP_04.06.00.11

OMAP4: hwmod: add I2C hwmods for OMAP4430 

Add hwmod structures for I2C controllers on OMAP4430.

Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>

Showing 1 changed file with 237 additions and 0 deletions Inline Diff

arch/arm/mach-omap2/omap_hwmod_44xx_data.c
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1 /* 1 /*
2 * Hardware modules present on the OMAP44xx chips 2 * Hardware modules present on the OMAP44xx chips
3 * 3 *
4 * Copyright (C) 2009-2010 Texas Instruments, Inc. 4 * Copyright (C) 2009-2010 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation 5 * Copyright (C) 2009-2010 Nokia Corporation
6 * 6 *
7 * Paul Walmsley 7 * Paul Walmsley
8 * Benoit Cousson 8 * Benoit Cousson
9 * 9 *
10 * This file is automatically generated from the OMAP hardware databases. 10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated 11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the 12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept 13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents. 14 * up-to-date with the file contents.
15 * 15 *
16 * This program is free software; you can redistribute it and/or modify 16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as 17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation. 18 * published by the Free Software Foundation.
19 */ 19 */
20 20
21 #include <linux/io.h> 21 #include <linux/io.h>
22 22
23 #include <plat/omap_hwmod.h> 23 #include <plat/omap_hwmod.h>
24 #include <plat/cpu.h> 24 #include <plat/cpu.h>
25 25
26 #include "omap_hwmod_common_data.h" 26 #include "omap_hwmod_common_data.h"
27 27
28 #include "cm.h" 28 #include "cm.h"
29 #include "prm-regbits-44xx.h" 29 #include "prm-regbits-44xx.h"
30 30
31 /* Base offset for all OMAP4 interrupts external to MPUSS */ 31 /* Base offset for all OMAP4 interrupts external to MPUSS */
32 #define OMAP44XX_IRQ_GIC_START 32 32 #define OMAP44XX_IRQ_GIC_START 32
33 33
34 /* Base offset for all OMAP4 dma requests */ 34 /* Base offset for all OMAP4 dma requests */
35 #define OMAP44XX_DMA_REQ_START 1 35 #define OMAP44XX_DMA_REQ_START 1
36 36
37 /* Backward references (IPs with Bus Master capability) */ 37 /* Backward references (IPs with Bus Master capability) */
38 static struct omap_hwmod omap44xx_dmm_hwmod; 38 static struct omap_hwmod omap44xx_dmm_hwmod;
39 static struct omap_hwmod omap44xx_emif_fw_hwmod; 39 static struct omap_hwmod omap44xx_emif_fw_hwmod;
40 static struct omap_hwmod omap44xx_l3_instr_hwmod; 40 static struct omap_hwmod omap44xx_l3_instr_hwmod;
41 static struct omap_hwmod omap44xx_l3_main_1_hwmod; 41 static struct omap_hwmod omap44xx_l3_main_1_hwmod;
42 static struct omap_hwmod omap44xx_l3_main_2_hwmod; 42 static struct omap_hwmod omap44xx_l3_main_2_hwmod;
43 static struct omap_hwmod omap44xx_l3_main_3_hwmod; 43 static struct omap_hwmod omap44xx_l3_main_3_hwmod;
44 static struct omap_hwmod omap44xx_l4_abe_hwmod; 44 static struct omap_hwmod omap44xx_l4_abe_hwmod;
45 static struct omap_hwmod omap44xx_l4_cfg_hwmod; 45 static struct omap_hwmod omap44xx_l4_cfg_hwmod;
46 static struct omap_hwmod omap44xx_l4_per_hwmod; 46 static struct omap_hwmod omap44xx_l4_per_hwmod;
47 static struct omap_hwmod omap44xx_l4_wkup_hwmod; 47 static struct omap_hwmod omap44xx_l4_wkup_hwmod;
48 static struct omap_hwmod omap44xx_mpu_hwmod; 48 static struct omap_hwmod omap44xx_mpu_hwmod;
49 static struct omap_hwmod omap44xx_mpu_private_hwmod; 49 static struct omap_hwmod omap44xx_mpu_private_hwmod;
50 50
51 /* 51 /*
52 * Interconnects omap_hwmod structures 52 * Interconnects omap_hwmod structures
53 * hwmods that compose the global OMAP interconnect 53 * hwmods that compose the global OMAP interconnect
54 */ 54 */
55 55
56 /* 56 /*
57 * 'dmm' class 57 * 'dmm' class
58 * instance(s): dmm 58 * instance(s): dmm
59 */ 59 */
60 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = { 60 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
61 .name = "dmm", 61 .name = "dmm",
62 }; 62 };
63 63
64 /* dmm interface data */ 64 /* dmm interface data */
65 /* l3_main_1 -> dmm */ 65 /* l3_main_1 -> dmm */
66 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = { 66 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
67 .master = &omap44xx_l3_main_1_hwmod, 67 .master = &omap44xx_l3_main_1_hwmod,
68 .slave = &omap44xx_dmm_hwmod, 68 .slave = &omap44xx_dmm_hwmod,
69 .clk = "l3_div_ck", 69 .clk = "l3_div_ck",
70 .user = OCP_USER_MPU | OCP_USER_SDMA, 70 .user = OCP_USER_MPU | OCP_USER_SDMA,
71 }; 71 };
72 72
73 /* mpu -> dmm */ 73 /* mpu -> dmm */
74 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = { 74 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
75 .master = &omap44xx_mpu_hwmod, 75 .master = &omap44xx_mpu_hwmod,
76 .slave = &omap44xx_dmm_hwmod, 76 .slave = &omap44xx_dmm_hwmod,
77 .clk = "l3_div_ck", 77 .clk = "l3_div_ck",
78 .user = OCP_USER_MPU | OCP_USER_SDMA, 78 .user = OCP_USER_MPU | OCP_USER_SDMA,
79 }; 79 };
80 80
81 /* dmm slave ports */ 81 /* dmm slave ports */
82 static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = { 82 static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
83 &omap44xx_l3_main_1__dmm, 83 &omap44xx_l3_main_1__dmm,
84 &omap44xx_mpu__dmm, 84 &omap44xx_mpu__dmm,
85 }; 85 };
86 86
87 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = { 87 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
88 { .irq = 113 + OMAP44XX_IRQ_GIC_START }, 88 { .irq = 113 + OMAP44XX_IRQ_GIC_START },
89 }; 89 };
90 90
91 static struct omap_hwmod omap44xx_dmm_hwmod = { 91 static struct omap_hwmod omap44xx_dmm_hwmod = {
92 .name = "dmm", 92 .name = "dmm",
93 .class = &omap44xx_dmm_hwmod_class, 93 .class = &omap44xx_dmm_hwmod_class,
94 .slaves = omap44xx_dmm_slaves, 94 .slaves = omap44xx_dmm_slaves,
95 .slaves_cnt = ARRAY_SIZE(omap44xx_dmm_slaves), 95 .slaves_cnt = ARRAY_SIZE(omap44xx_dmm_slaves),
96 .mpu_irqs = omap44xx_dmm_irqs, 96 .mpu_irqs = omap44xx_dmm_irqs,
97 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dmm_irqs), 97 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dmm_irqs),
98 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 98 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
99 }; 99 };
100 100
101 /* 101 /*
102 * 'emif_fw' class 102 * 'emif_fw' class
103 * instance(s): emif_fw 103 * instance(s): emif_fw
104 */ 104 */
105 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = { 105 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
106 .name = "emif_fw", 106 .name = "emif_fw",
107 }; 107 };
108 108
109 /* emif_fw interface data */ 109 /* emif_fw interface data */
110 /* dmm -> emif_fw */ 110 /* dmm -> emif_fw */
111 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = { 111 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
112 .master = &omap44xx_dmm_hwmod, 112 .master = &omap44xx_dmm_hwmod,
113 .slave = &omap44xx_emif_fw_hwmod, 113 .slave = &omap44xx_emif_fw_hwmod,
114 .clk = "l3_div_ck", 114 .clk = "l3_div_ck",
115 .user = OCP_USER_MPU | OCP_USER_SDMA, 115 .user = OCP_USER_MPU | OCP_USER_SDMA,
116 }; 116 };
117 117
118 /* l4_cfg -> emif_fw */ 118 /* l4_cfg -> emif_fw */
119 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = { 119 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
120 .master = &omap44xx_l4_cfg_hwmod, 120 .master = &omap44xx_l4_cfg_hwmod,
121 .slave = &omap44xx_emif_fw_hwmod, 121 .slave = &omap44xx_emif_fw_hwmod,
122 .clk = "l4_div_ck", 122 .clk = "l4_div_ck",
123 .user = OCP_USER_MPU | OCP_USER_SDMA, 123 .user = OCP_USER_MPU | OCP_USER_SDMA,
124 }; 124 };
125 125
126 /* emif_fw slave ports */ 126 /* emif_fw slave ports */
127 static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = { 127 static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = {
128 &omap44xx_dmm__emif_fw, 128 &omap44xx_dmm__emif_fw,
129 &omap44xx_l4_cfg__emif_fw, 129 &omap44xx_l4_cfg__emif_fw,
130 }; 130 };
131 131
132 static struct omap_hwmod omap44xx_emif_fw_hwmod = { 132 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
133 .name = "emif_fw", 133 .name = "emif_fw",
134 .class = &omap44xx_emif_fw_hwmod_class, 134 .class = &omap44xx_emif_fw_hwmod_class,
135 .slaves = omap44xx_emif_fw_slaves, 135 .slaves = omap44xx_emif_fw_slaves,
136 .slaves_cnt = ARRAY_SIZE(omap44xx_emif_fw_slaves), 136 .slaves_cnt = ARRAY_SIZE(omap44xx_emif_fw_slaves),
137 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 137 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
138 }; 138 };
139 139
140 /* 140 /*
141 * 'l3' class 141 * 'l3' class
142 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3 142 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
143 */ 143 */
144 static struct omap_hwmod_class omap44xx_l3_hwmod_class = { 144 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
145 .name = "l3", 145 .name = "l3",
146 }; 146 };
147 147
148 /* l3_instr interface data */ 148 /* l3_instr interface data */
149 /* l3_main_3 -> l3_instr */ 149 /* l3_main_3 -> l3_instr */
150 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = { 150 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
151 .master = &omap44xx_l3_main_3_hwmod, 151 .master = &omap44xx_l3_main_3_hwmod,
152 .slave = &omap44xx_l3_instr_hwmod, 152 .slave = &omap44xx_l3_instr_hwmod,
153 .clk = "l3_div_ck", 153 .clk = "l3_div_ck",
154 .user = OCP_USER_MPU | OCP_USER_SDMA, 154 .user = OCP_USER_MPU | OCP_USER_SDMA,
155 }; 155 };
156 156
157 /* l3_instr slave ports */ 157 /* l3_instr slave ports */
158 static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = { 158 static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = {
159 &omap44xx_l3_main_3__l3_instr, 159 &omap44xx_l3_main_3__l3_instr,
160 }; 160 };
161 161
162 static struct omap_hwmod omap44xx_l3_instr_hwmod = { 162 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
163 .name = "l3_instr", 163 .name = "l3_instr",
164 .class = &omap44xx_l3_hwmod_class, 164 .class = &omap44xx_l3_hwmod_class,
165 .slaves = omap44xx_l3_instr_slaves, 165 .slaves = omap44xx_l3_instr_slaves,
166 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_instr_slaves), 166 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_instr_slaves),
167 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 167 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
168 }; 168 };
169 169
170 /* l3_main_2 -> l3_main_1 */ 170 /* l3_main_2 -> l3_main_1 */
171 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = { 171 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
172 .master = &omap44xx_l3_main_2_hwmod, 172 .master = &omap44xx_l3_main_2_hwmod,
173 .slave = &omap44xx_l3_main_1_hwmod, 173 .slave = &omap44xx_l3_main_1_hwmod,
174 .clk = "l3_div_ck", 174 .clk = "l3_div_ck",
175 .user = OCP_USER_MPU | OCP_USER_SDMA, 175 .user = OCP_USER_MPU | OCP_USER_SDMA,
176 }; 176 };
177 177
178 /* l4_cfg -> l3_main_1 */ 178 /* l4_cfg -> l3_main_1 */
179 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = { 179 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
180 .master = &omap44xx_l4_cfg_hwmod, 180 .master = &omap44xx_l4_cfg_hwmod,
181 .slave = &omap44xx_l3_main_1_hwmod, 181 .slave = &omap44xx_l3_main_1_hwmod,
182 .clk = "l4_div_ck", 182 .clk = "l4_div_ck",
183 .user = OCP_USER_MPU | OCP_USER_SDMA, 183 .user = OCP_USER_MPU | OCP_USER_SDMA,
184 }; 184 };
185 185
186 /* mpu -> l3_main_1 */ 186 /* mpu -> l3_main_1 */
187 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = { 187 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
188 .master = &omap44xx_mpu_hwmod, 188 .master = &omap44xx_mpu_hwmod,
189 .slave = &omap44xx_l3_main_1_hwmod, 189 .slave = &omap44xx_l3_main_1_hwmod,
190 .clk = "l3_div_ck", 190 .clk = "l3_div_ck",
191 .user = OCP_USER_MPU | OCP_USER_SDMA, 191 .user = OCP_USER_MPU | OCP_USER_SDMA,
192 }; 192 };
193 193
194 /* l3_main_1 slave ports */ 194 /* l3_main_1 slave ports */
195 static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = { 195 static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
196 &omap44xx_l3_main_2__l3_main_1, 196 &omap44xx_l3_main_2__l3_main_1,
197 &omap44xx_l4_cfg__l3_main_1, 197 &omap44xx_l4_cfg__l3_main_1,
198 &omap44xx_mpu__l3_main_1, 198 &omap44xx_mpu__l3_main_1,
199 }; 199 };
200 200
201 static struct omap_hwmod omap44xx_l3_main_1_hwmod = { 201 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
202 .name = "l3_main_1", 202 .name = "l3_main_1",
203 .class = &omap44xx_l3_hwmod_class, 203 .class = &omap44xx_l3_hwmod_class,
204 .slaves = omap44xx_l3_main_1_slaves, 204 .slaves = omap44xx_l3_main_1_slaves,
205 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves), 205 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
206 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 206 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
207 }; 207 };
208 208
209 /* l3_main_2 interface data */ 209 /* l3_main_2 interface data */
210 /* l3_main_1 -> l3_main_2 */ 210 /* l3_main_1 -> l3_main_2 */
211 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = { 211 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
212 .master = &omap44xx_l3_main_1_hwmod, 212 .master = &omap44xx_l3_main_1_hwmod,
213 .slave = &omap44xx_l3_main_2_hwmod, 213 .slave = &omap44xx_l3_main_2_hwmod,
214 .clk = "l3_div_ck", 214 .clk = "l3_div_ck",
215 .user = OCP_USER_MPU | OCP_USER_SDMA, 215 .user = OCP_USER_MPU | OCP_USER_SDMA,
216 }; 216 };
217 217
218 /* l4_cfg -> l3_main_2 */ 218 /* l4_cfg -> l3_main_2 */
219 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = { 219 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
220 .master = &omap44xx_l4_cfg_hwmod, 220 .master = &omap44xx_l4_cfg_hwmod,
221 .slave = &omap44xx_l3_main_2_hwmod, 221 .slave = &omap44xx_l3_main_2_hwmod,
222 .clk = "l4_div_ck", 222 .clk = "l4_div_ck",
223 .user = OCP_USER_MPU | OCP_USER_SDMA, 223 .user = OCP_USER_MPU | OCP_USER_SDMA,
224 }; 224 };
225 225
226 /* l3_main_2 slave ports */ 226 /* l3_main_2 slave ports */
227 static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = { 227 static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
228 &omap44xx_l3_main_1__l3_main_2, 228 &omap44xx_l3_main_1__l3_main_2,
229 &omap44xx_l4_cfg__l3_main_2, 229 &omap44xx_l4_cfg__l3_main_2,
230 }; 230 };
231 231
232 static struct omap_hwmod omap44xx_l3_main_2_hwmod = { 232 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
233 .name = "l3_main_2", 233 .name = "l3_main_2",
234 .class = &omap44xx_l3_hwmod_class, 234 .class = &omap44xx_l3_hwmod_class,
235 .slaves = omap44xx_l3_main_2_slaves, 235 .slaves = omap44xx_l3_main_2_slaves,
236 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_2_slaves), 236 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
237 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 237 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
238 }; 238 };
239 239
240 /* l3_main_3 interface data */ 240 /* l3_main_3 interface data */
241 /* l3_main_1 -> l3_main_3 */ 241 /* l3_main_1 -> l3_main_3 */
242 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = { 242 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
243 .master = &omap44xx_l3_main_1_hwmod, 243 .master = &omap44xx_l3_main_1_hwmod,
244 .slave = &omap44xx_l3_main_3_hwmod, 244 .slave = &omap44xx_l3_main_3_hwmod,
245 .clk = "l3_div_ck", 245 .clk = "l3_div_ck",
246 .user = OCP_USER_MPU | OCP_USER_SDMA, 246 .user = OCP_USER_MPU | OCP_USER_SDMA,
247 }; 247 };
248 248
249 /* l3_main_2 -> l3_main_3 */ 249 /* l3_main_2 -> l3_main_3 */
250 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = { 250 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
251 .master = &omap44xx_l3_main_2_hwmod, 251 .master = &omap44xx_l3_main_2_hwmod,
252 .slave = &omap44xx_l3_main_3_hwmod, 252 .slave = &omap44xx_l3_main_3_hwmod,
253 .clk = "l3_div_ck", 253 .clk = "l3_div_ck",
254 .user = OCP_USER_MPU | OCP_USER_SDMA, 254 .user = OCP_USER_MPU | OCP_USER_SDMA,
255 }; 255 };
256 256
257 /* l4_cfg -> l3_main_3 */ 257 /* l4_cfg -> l3_main_3 */
258 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = { 258 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
259 .master = &omap44xx_l4_cfg_hwmod, 259 .master = &omap44xx_l4_cfg_hwmod,
260 .slave = &omap44xx_l3_main_3_hwmod, 260 .slave = &omap44xx_l3_main_3_hwmod,
261 .clk = "l4_div_ck", 261 .clk = "l4_div_ck",
262 .user = OCP_USER_MPU | OCP_USER_SDMA, 262 .user = OCP_USER_MPU | OCP_USER_SDMA,
263 }; 263 };
264 264
265 /* l3_main_3 slave ports */ 265 /* l3_main_3 slave ports */
266 static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = { 266 static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = {
267 &omap44xx_l3_main_1__l3_main_3, 267 &omap44xx_l3_main_1__l3_main_3,
268 &omap44xx_l3_main_2__l3_main_3, 268 &omap44xx_l3_main_2__l3_main_3,
269 &omap44xx_l4_cfg__l3_main_3, 269 &omap44xx_l4_cfg__l3_main_3,
270 }; 270 };
271 271
272 static struct omap_hwmod omap44xx_l3_main_3_hwmod = { 272 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
273 .name = "l3_main_3", 273 .name = "l3_main_3",
274 .class = &omap44xx_l3_hwmod_class, 274 .class = &omap44xx_l3_hwmod_class,
275 .slaves = omap44xx_l3_main_3_slaves, 275 .slaves = omap44xx_l3_main_3_slaves,
276 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_3_slaves), 276 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
277 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 277 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
278 }; 278 };
279 279
280 /* 280 /*
281 * 'l4' class 281 * 'l4' class
282 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup 282 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
283 */ 283 */
284 static struct omap_hwmod_class omap44xx_l4_hwmod_class = { 284 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
285 .name = "l4", 285 .name = "l4",
286 }; 286 };
287 287
288 /* l4_abe interface data */ 288 /* l4_abe interface data */
289 /* l3_main_1 -> l4_abe */ 289 /* l3_main_1 -> l4_abe */
290 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = { 290 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
291 .master = &omap44xx_l3_main_1_hwmod, 291 .master = &omap44xx_l3_main_1_hwmod,
292 .slave = &omap44xx_l4_abe_hwmod, 292 .slave = &omap44xx_l4_abe_hwmod,
293 .clk = "l3_div_ck", 293 .clk = "l3_div_ck",
294 .user = OCP_USER_MPU | OCP_USER_SDMA, 294 .user = OCP_USER_MPU | OCP_USER_SDMA,
295 }; 295 };
296 296
297 /* mpu -> l4_abe */ 297 /* mpu -> l4_abe */
298 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = { 298 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
299 .master = &omap44xx_mpu_hwmod, 299 .master = &omap44xx_mpu_hwmod,
300 .slave = &omap44xx_l4_abe_hwmod, 300 .slave = &omap44xx_l4_abe_hwmod,
301 .clk = "ocp_abe_iclk", 301 .clk = "ocp_abe_iclk",
302 .user = OCP_USER_MPU | OCP_USER_SDMA, 302 .user = OCP_USER_MPU | OCP_USER_SDMA,
303 }; 303 };
304 304
305 /* l4_abe slave ports */ 305 /* l4_abe slave ports */
306 static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = { 306 static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
307 &omap44xx_l3_main_1__l4_abe, 307 &omap44xx_l3_main_1__l4_abe,
308 &omap44xx_mpu__l4_abe, 308 &omap44xx_mpu__l4_abe,
309 }; 309 };
310 310
311 static struct omap_hwmod omap44xx_l4_abe_hwmod = { 311 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
312 .name = "l4_abe", 312 .name = "l4_abe",
313 .class = &omap44xx_l4_hwmod_class, 313 .class = &omap44xx_l4_hwmod_class,
314 .slaves = omap44xx_l4_abe_slaves, 314 .slaves = omap44xx_l4_abe_slaves,
315 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_abe_slaves), 315 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_abe_slaves),
316 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 316 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
317 }; 317 };
318 318
319 /* l4_cfg interface data */ 319 /* l4_cfg interface data */
320 /* l3_main_1 -> l4_cfg */ 320 /* l3_main_1 -> l4_cfg */
321 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = { 321 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
322 .master = &omap44xx_l3_main_1_hwmod, 322 .master = &omap44xx_l3_main_1_hwmod,
323 .slave = &omap44xx_l4_cfg_hwmod, 323 .slave = &omap44xx_l4_cfg_hwmod,
324 .clk = "l3_div_ck", 324 .clk = "l3_div_ck",
325 .user = OCP_USER_MPU | OCP_USER_SDMA, 325 .user = OCP_USER_MPU | OCP_USER_SDMA,
326 }; 326 };
327 327
328 /* l4_cfg slave ports */ 328 /* l4_cfg slave ports */
329 static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = { 329 static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = {
330 &omap44xx_l3_main_1__l4_cfg, 330 &omap44xx_l3_main_1__l4_cfg,
331 }; 331 };
332 332
333 static struct omap_hwmod omap44xx_l4_cfg_hwmod = { 333 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
334 .name = "l4_cfg", 334 .name = "l4_cfg",
335 .class = &omap44xx_l4_hwmod_class, 335 .class = &omap44xx_l4_hwmod_class,
336 .slaves = omap44xx_l4_cfg_slaves, 336 .slaves = omap44xx_l4_cfg_slaves,
337 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_cfg_slaves), 337 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
338 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 338 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
339 }; 339 };
340 340
341 /* l4_per interface data */ 341 /* l4_per interface data */
342 /* l3_main_2 -> l4_per */ 342 /* l3_main_2 -> l4_per */
343 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = { 343 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
344 .master = &omap44xx_l3_main_2_hwmod, 344 .master = &omap44xx_l3_main_2_hwmod,
345 .slave = &omap44xx_l4_per_hwmod, 345 .slave = &omap44xx_l4_per_hwmod,
346 .clk = "l3_div_ck", 346 .clk = "l3_div_ck",
347 .user = OCP_USER_MPU | OCP_USER_SDMA, 347 .user = OCP_USER_MPU | OCP_USER_SDMA,
348 }; 348 };
349 349
350 /* l4_per slave ports */ 350 /* l4_per slave ports */
351 static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = { 351 static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = {
352 &omap44xx_l3_main_2__l4_per, 352 &omap44xx_l3_main_2__l4_per,
353 }; 353 };
354 354
355 static struct omap_hwmod omap44xx_l4_per_hwmod = { 355 static struct omap_hwmod omap44xx_l4_per_hwmod = {
356 .name = "l4_per", 356 .name = "l4_per",
357 .class = &omap44xx_l4_hwmod_class, 357 .class = &omap44xx_l4_hwmod_class,
358 .slaves = omap44xx_l4_per_slaves, 358 .slaves = omap44xx_l4_per_slaves,
359 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_per_slaves), 359 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_per_slaves),
360 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 360 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
361 }; 361 };
362 362
363 /* l4_wkup interface data */ 363 /* l4_wkup interface data */
364 /* l4_cfg -> l4_wkup */ 364 /* l4_cfg -> l4_wkup */
365 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = { 365 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
366 .master = &omap44xx_l4_cfg_hwmod, 366 .master = &omap44xx_l4_cfg_hwmod,
367 .slave = &omap44xx_l4_wkup_hwmod, 367 .slave = &omap44xx_l4_wkup_hwmod,
368 .clk = "l4_div_ck", 368 .clk = "l4_div_ck",
369 .user = OCP_USER_MPU | OCP_USER_SDMA, 369 .user = OCP_USER_MPU | OCP_USER_SDMA,
370 }; 370 };
371 371
372 /* l4_wkup slave ports */ 372 /* l4_wkup slave ports */
373 static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = { 373 static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = {
374 &omap44xx_l4_cfg__l4_wkup, 374 &omap44xx_l4_cfg__l4_wkup,
375 }; 375 };
376 376
377 static struct omap_hwmod omap44xx_l4_wkup_hwmod = { 377 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
378 .name = "l4_wkup", 378 .name = "l4_wkup",
379 .class = &omap44xx_l4_hwmod_class, 379 .class = &omap44xx_l4_hwmod_class,
380 .slaves = omap44xx_l4_wkup_slaves, 380 .slaves = omap44xx_l4_wkup_slaves,
381 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_wkup_slaves), 381 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
382 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 382 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
383 }; 383 };
384 384
385 /* 385 /*
386 * 'i2c' class
387 * multimaster high-speed i2c controller
388 */
389
390 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
391 .sysc_offs = 0x0010,
392 .syss_offs = 0x0090,
393 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
394 SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SOFTRESET |
395 SYSC_HAS_AUTOIDLE),
396 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
397 .sysc_fields = &omap_hwmod_sysc_type1,
398 };
399
400 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
401 .name = "i2c",
402 .sysc = &omap44xx_i2c_sysc,
403 };
404
405 /* i2c1 */
406 static struct omap_hwmod omap44xx_i2c1_hwmod;
407 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
408 { .irq = 56 + OMAP44XX_IRQ_GIC_START },
409 };
410
411 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
412 { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
413 { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
414 };
415
416 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
417 {
418 .pa_start = 0x48070000,
419 .pa_end = 0x480700ff,
420 .flags = ADDR_TYPE_RT
421 },
422 };
423
424 /* l4_per -> i2c1 */
425 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
426 .master = &omap44xx_l4_per_hwmod,
427 .slave = &omap44xx_i2c1_hwmod,
428 .clk = "l4_div_ck",
429 .addr = omap44xx_i2c1_addrs,
430 .addr_cnt = ARRAY_SIZE(omap44xx_i2c1_addrs),
431 .user = OCP_USER_MPU | OCP_USER_SDMA,
432 };
433
434 /* i2c1 slave ports */
435 static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
436 &omap44xx_l4_per__i2c1,
437 };
438
439 static struct omap_hwmod omap44xx_i2c1_hwmod = {
440 .name = "i2c1",
441 .class = &omap44xx_i2c_hwmod_class,
442 .flags = HWMOD_INIT_NO_RESET,
443 .mpu_irqs = omap44xx_i2c1_irqs,
444 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c1_irqs),
445 .sdma_reqs = omap44xx_i2c1_sdma_reqs,
446 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c1_sdma_reqs),
447 .main_clk = "i2c1_fck",
448 .prcm = {
449 .omap4 = {
450 .clkctrl_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
451 },
452 },
453 .slaves = omap44xx_i2c1_slaves,
454 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c1_slaves),
455 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
456 };
457
458 /* i2c2 */
459 static struct omap_hwmod omap44xx_i2c2_hwmod;
460 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
461 { .irq = 57 + OMAP44XX_IRQ_GIC_START },
462 };
463
464 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
465 { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
466 { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
467 };
468
469 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
470 {
471 .pa_start = 0x48072000,
472 .pa_end = 0x480720ff,
473 .flags = ADDR_TYPE_RT
474 },
475 };
476
477 /* l4_per -> i2c2 */
478 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
479 .master = &omap44xx_l4_per_hwmod,
480 .slave = &omap44xx_i2c2_hwmod,
481 .clk = "l4_div_ck",
482 .addr = omap44xx_i2c2_addrs,
483 .addr_cnt = ARRAY_SIZE(omap44xx_i2c2_addrs),
484 .user = OCP_USER_MPU | OCP_USER_SDMA,
485 };
486
487 /* i2c2 slave ports */
488 static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
489 &omap44xx_l4_per__i2c2,
490 };
491
492 static struct omap_hwmod omap44xx_i2c2_hwmod = {
493 .name = "i2c2",
494 .class = &omap44xx_i2c_hwmod_class,
495 .flags = HWMOD_INIT_NO_RESET,
496 .mpu_irqs = omap44xx_i2c2_irqs,
497 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c2_irqs),
498 .sdma_reqs = omap44xx_i2c2_sdma_reqs,
499 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c2_sdma_reqs),
500 .main_clk = "i2c2_fck",
501 .prcm = {
502 .omap4 = {
503 .clkctrl_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
504 },
505 },
506 .slaves = omap44xx_i2c2_slaves,
507 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c2_slaves),
508 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
509 };
510
511 /* i2c3 */
512 static struct omap_hwmod omap44xx_i2c3_hwmod;
513 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
514 { .irq = 61 + OMAP44XX_IRQ_GIC_START },
515 };
516
517 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
518 { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
519 { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
520 };
521
522 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
523 {
524 .pa_start = 0x48060000,
525 .pa_end = 0x480600ff,
526 .flags = ADDR_TYPE_RT
527 },
528 };
529
530 /* l4_per -> i2c3 */
531 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
532 .master = &omap44xx_l4_per_hwmod,
533 .slave = &omap44xx_i2c3_hwmod,
534 .clk = "l4_div_ck",
535 .addr = omap44xx_i2c3_addrs,
536 .addr_cnt = ARRAY_SIZE(omap44xx_i2c3_addrs),
537 .user = OCP_USER_MPU | OCP_USER_SDMA,
538 };
539
540 /* i2c3 slave ports */
541 static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
542 &omap44xx_l4_per__i2c3,
543 };
544
545 static struct omap_hwmod omap44xx_i2c3_hwmod = {
546 .name = "i2c3",
547 .class = &omap44xx_i2c_hwmod_class,
548 .flags = HWMOD_INIT_NO_RESET,
549 .mpu_irqs = omap44xx_i2c3_irqs,
550 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c3_irqs),
551 .sdma_reqs = omap44xx_i2c3_sdma_reqs,
552 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c3_sdma_reqs),
553 .main_clk = "i2c3_fck",
554 .prcm = {
555 .omap4 = {
556 .clkctrl_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
557 },
558 },
559 .slaves = omap44xx_i2c3_slaves,
560 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c3_slaves),
561 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
562 };
563
564 /* i2c4 */
565 static struct omap_hwmod omap44xx_i2c4_hwmod;
566 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
567 { .irq = 62 + OMAP44XX_IRQ_GIC_START },
568 };
569
570 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
571 { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
572 { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
573 };
574
575 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
576 {
577 .pa_start = 0x48350000,
578 .pa_end = 0x483500ff,
579 .flags = ADDR_TYPE_RT
580 },
581 };
582
583 /* l4_per -> i2c4 */
584 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
585 .master = &omap44xx_l4_per_hwmod,
586 .slave = &omap44xx_i2c4_hwmod,
587 .clk = "l4_div_ck",
588 .addr = omap44xx_i2c4_addrs,
589 .addr_cnt = ARRAY_SIZE(omap44xx_i2c4_addrs),
590 .user = OCP_USER_MPU | OCP_USER_SDMA,
591 };
592
593 /* i2c4 slave ports */
594 static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
595 &omap44xx_l4_per__i2c4,
596 };
597
598 static struct omap_hwmod omap44xx_i2c4_hwmod = {
599 .name = "i2c4",
600 .class = &omap44xx_i2c_hwmod_class,
601 .flags = HWMOD_INIT_NO_RESET,
602 .mpu_irqs = omap44xx_i2c4_irqs,
603 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c4_irqs),
604 .sdma_reqs = omap44xx_i2c4_sdma_reqs,
605 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c4_sdma_reqs),
606 .main_clk = "i2c4_fck",
607 .prcm = {
608 .omap4 = {
609 .clkctrl_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
610 },
611 },
612 .slaves = omap44xx_i2c4_slaves,
613 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c4_slaves),
614 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
615 };
616
617 /*
386 * 'mpu_bus' class 618 * 'mpu_bus' class
387 * instance(s): mpu_private 619 * instance(s): mpu_private
388 */ 620 */
389 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = { 621 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
390 .name = "mpu_bus", 622 .name = "mpu_bus",
391 }; 623 };
392 624
393 /* mpu_private interface data */ 625 /* mpu_private interface data */
394 /* mpu -> mpu_private */ 626 /* mpu -> mpu_private */
395 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = { 627 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
396 .master = &omap44xx_mpu_hwmod, 628 .master = &omap44xx_mpu_hwmod,
397 .slave = &omap44xx_mpu_private_hwmod, 629 .slave = &omap44xx_mpu_private_hwmod,
398 .clk = "l3_div_ck", 630 .clk = "l3_div_ck",
399 .user = OCP_USER_MPU | OCP_USER_SDMA, 631 .user = OCP_USER_MPU | OCP_USER_SDMA,
400 }; 632 };
401 633
402 /* mpu_private slave ports */ 634 /* mpu_private slave ports */
403 static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = { 635 static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = {
404 &omap44xx_mpu__mpu_private, 636 &omap44xx_mpu__mpu_private,
405 }; 637 };
406 638
407 static struct omap_hwmod omap44xx_mpu_private_hwmod = { 639 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
408 .name = "mpu_private", 640 .name = "mpu_private",
409 .class = &omap44xx_mpu_bus_hwmod_class, 641 .class = &omap44xx_mpu_bus_hwmod_class,
410 .slaves = omap44xx_mpu_private_slaves, 642 .slaves = omap44xx_mpu_private_slaves,
411 .slaves_cnt = ARRAY_SIZE(omap44xx_mpu_private_slaves), 643 .slaves_cnt = ARRAY_SIZE(omap44xx_mpu_private_slaves),
412 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 644 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
413 }; 645 };
414 646
415 /* 647 /*
416 * 'mpu' class 648 * 'mpu' class
417 * mpu sub-system 649 * mpu sub-system
418 */ 650 */
419 651
420 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = { 652 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
421 .name = "mpu", 653 .name = "mpu",
422 }; 654 };
423 655
424 /* mpu */ 656 /* mpu */
425 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = { 657 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
426 { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START }, 658 { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
427 { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START }, 659 { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
428 { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START }, 660 { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
429 }; 661 };
430 662
431 /* mpu master ports */ 663 /* mpu master ports */
432 static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = { 664 static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = {
433 &omap44xx_mpu__l3_main_1, 665 &omap44xx_mpu__l3_main_1,
434 &omap44xx_mpu__l4_abe, 666 &omap44xx_mpu__l4_abe,
435 &omap44xx_mpu__dmm, 667 &omap44xx_mpu__dmm,
436 }; 668 };
437 669
438 static struct omap_hwmod omap44xx_mpu_hwmod = { 670 static struct omap_hwmod omap44xx_mpu_hwmod = {
439 .name = "mpu", 671 .name = "mpu",
440 .class = &omap44xx_mpu_hwmod_class, 672 .class = &omap44xx_mpu_hwmod_class,
441 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), 673 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
442 .mpu_irqs = omap44xx_mpu_irqs, 674 .mpu_irqs = omap44xx_mpu_irqs,
443 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mpu_irqs), 675 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mpu_irqs),
444 .main_clk = "dpll_mpu_m2_ck", 676 .main_clk = "dpll_mpu_m2_ck",
445 .prcm = { 677 .prcm = {
446 .omap4 = { 678 .omap4 = {
447 .clkctrl_reg = OMAP4430_CM_MPU_MPU_CLKCTRL, 679 .clkctrl_reg = OMAP4430_CM_MPU_MPU_CLKCTRL,
448 }, 680 },
449 }, 681 },
450 .masters = omap44xx_mpu_masters, 682 .masters = omap44xx_mpu_masters,
451 .masters_cnt = ARRAY_SIZE(omap44xx_mpu_masters), 683 .masters_cnt = ARRAY_SIZE(omap44xx_mpu_masters),
452 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 684 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
453 }; 685 };
454 686
455 /* 687 /*
456 * 'wd_timer' class 688 * 'wd_timer' class
457 * 32-bit watchdog upward counter that generates a pulse on the reset pin on 689 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
458 * overflow condition 690 * overflow condition
459 */ 691 */
460 692
461 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = { 693 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
462 .rev_offs = 0x0000, 694 .rev_offs = 0x0000,
463 .sysc_offs = 0x0010, 695 .sysc_offs = 0x0010,
464 .syss_offs = 0x0014, 696 .syss_offs = 0x0014,
465 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE | 697 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
466 SYSC_HAS_SOFTRESET), 698 SYSC_HAS_SOFTRESET),
467 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 699 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
468 .sysc_fields = &omap_hwmod_sysc_type1, 700 .sysc_fields = &omap_hwmod_sysc_type1,
469 }; 701 };
470 702
471 /* 703 /*
472 * 'uart' class 704 * 'uart' class
473 * universal asynchronous receiver/transmitter (uart) 705 * universal asynchronous receiver/transmitter (uart)
474 */ 706 */
475 707
476 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = { 708 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
477 .rev_offs = 0x0050, 709 .rev_offs = 0x0050,
478 .sysc_offs = 0x0054, 710 .sysc_offs = 0x0054,
479 .syss_offs = 0x0058, 711 .syss_offs = 0x0058,
480 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | 712 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
481 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), 713 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
482 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 714 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
483 .sysc_fields = &omap_hwmod_sysc_type1, 715 .sysc_fields = &omap_hwmod_sysc_type1,
484 }; 716 };
485 717
486 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = { 718 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
487 .name = "wd_timer", 719 .name = "wd_timer",
488 .sysc = &omap44xx_wd_timer_sysc, 720 .sysc = &omap44xx_wd_timer_sysc,
489 }; 721 };
490 722
491 /* wd_timer2 */ 723 /* wd_timer2 */
492 static struct omap_hwmod omap44xx_wd_timer2_hwmod; 724 static struct omap_hwmod omap44xx_wd_timer2_hwmod;
493 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = { 725 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
494 { .irq = 80 + OMAP44XX_IRQ_GIC_START }, 726 { .irq = 80 + OMAP44XX_IRQ_GIC_START },
495 }; 727 };
496 728
497 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = { 729 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
498 { 730 {
499 .pa_start = 0x4a314000, 731 .pa_start = 0x4a314000,
500 .pa_end = 0x4a31407f, 732 .pa_end = 0x4a31407f,
501 .flags = ADDR_TYPE_RT 733 .flags = ADDR_TYPE_RT
502 }, 734 },
503 }; 735 };
504 736
505 static struct omap_hwmod_class omap44xx_uart_hwmod_class = { 737 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
506 .name = "uart", 738 .name = "uart",
507 .sysc = &omap44xx_uart_sysc, 739 .sysc = &omap44xx_uart_sysc,
508 }; 740 };
509 741
510 /* uart1 */ 742 /* uart1 */
511 static struct omap_hwmod omap44xx_uart1_hwmod; 743 static struct omap_hwmod omap44xx_uart1_hwmod;
512 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = { 744 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
513 { .irq = 72 + OMAP44XX_IRQ_GIC_START }, 745 { .irq = 72 + OMAP44XX_IRQ_GIC_START },
514 }; 746 };
515 747
516 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = { 748 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
517 { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START }, 749 { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
518 { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START }, 750 { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
519 }; 751 };
520 752
521 static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = { 753 static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
522 { 754 {
523 .pa_start = 0x4806a000, 755 .pa_start = 0x4806a000,
524 .pa_end = 0x4806a0ff, 756 .pa_end = 0x4806a0ff,
525 .flags = ADDR_TYPE_RT 757 .flags = ADDR_TYPE_RT
526 }, 758 },
527 }; 759 };
528 760
529 /* l4_per -> uart1 */ 761 /* l4_per -> uart1 */
530 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = { 762 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
531 .master = &omap44xx_l4_per_hwmod, 763 .master = &omap44xx_l4_per_hwmod,
532 .slave = &omap44xx_uart1_hwmod, 764 .slave = &omap44xx_uart1_hwmod,
533 .clk = "l4_div_ck", 765 .clk = "l4_div_ck",
534 .addr = omap44xx_uart1_addrs, 766 .addr = omap44xx_uart1_addrs,
535 .addr_cnt = ARRAY_SIZE(omap44xx_uart1_addrs), 767 .addr_cnt = ARRAY_SIZE(omap44xx_uart1_addrs),
536 .user = OCP_USER_MPU | OCP_USER_SDMA, 768 .user = OCP_USER_MPU | OCP_USER_SDMA,
537 }; 769 };
538 770
539 /* uart1 slave ports */ 771 /* uart1 slave ports */
540 static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = { 772 static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = {
541 &omap44xx_l4_per__uart1, 773 &omap44xx_l4_per__uart1,
542 }; 774 };
543 775
544 static struct omap_hwmod omap44xx_uart1_hwmod = { 776 static struct omap_hwmod omap44xx_uart1_hwmod = {
545 .name = "uart1", 777 .name = "uart1",
546 .class = &omap44xx_uart_hwmod_class, 778 .class = &omap44xx_uart_hwmod_class,
547 .mpu_irqs = omap44xx_uart1_irqs, 779 .mpu_irqs = omap44xx_uart1_irqs,
548 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart1_irqs), 780 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart1_irqs),
549 .sdma_reqs = omap44xx_uart1_sdma_reqs, 781 .sdma_reqs = omap44xx_uart1_sdma_reqs,
550 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart1_sdma_reqs), 782 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart1_sdma_reqs),
551 .main_clk = "uart1_fck", 783 .main_clk = "uart1_fck",
552 .prcm = { 784 .prcm = {
553 .omap4 = { 785 .omap4 = {
554 .clkctrl_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL, 786 .clkctrl_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL,
555 }, 787 },
556 }, 788 },
557 .slaves = omap44xx_uart1_slaves, 789 .slaves = omap44xx_uart1_slaves,
558 .slaves_cnt = ARRAY_SIZE(omap44xx_uart1_slaves), 790 .slaves_cnt = ARRAY_SIZE(omap44xx_uart1_slaves),
559 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 791 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
560 }; 792 };
561 793
562 /* uart2 */ 794 /* uart2 */
563 static struct omap_hwmod omap44xx_uart2_hwmod; 795 static struct omap_hwmod omap44xx_uart2_hwmod;
564 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = { 796 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
565 { .irq = 73 + OMAP44XX_IRQ_GIC_START }, 797 { .irq = 73 + OMAP44XX_IRQ_GIC_START },
566 }; 798 };
567 799
568 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = { 800 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
569 { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START }, 801 { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
570 { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START }, 802 { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
571 }; 803 };
572 804
573 static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = { 805 static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
574 { 806 {
575 .pa_start = 0x4806c000, 807 .pa_start = 0x4806c000,
576 .pa_end = 0x4806c0ff, 808 .pa_end = 0x4806c0ff,
577 .flags = ADDR_TYPE_RT 809 .flags = ADDR_TYPE_RT
578 }, 810 },
579 }; 811 };
580 812
581 /* l4_wkup -> wd_timer2 */ 813 /* l4_wkup -> wd_timer2 */
582 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = { 814 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
583 .master = &omap44xx_l4_wkup_hwmod, 815 .master = &omap44xx_l4_wkup_hwmod,
584 .slave = &omap44xx_wd_timer2_hwmod, 816 .slave = &omap44xx_wd_timer2_hwmod,
585 .clk = "l4_wkup_clk_mux_ck", 817 .clk = "l4_wkup_clk_mux_ck",
586 .addr = omap44xx_wd_timer2_addrs, 818 .addr = omap44xx_wd_timer2_addrs,
587 .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer2_addrs), 819 .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer2_addrs),
588 .user = OCP_USER_MPU | OCP_USER_SDMA, 820 .user = OCP_USER_MPU | OCP_USER_SDMA,
589 }; 821 };
590 822
591 /* wd_timer2 slave ports */ 823 /* wd_timer2 slave ports */
592 static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = { 824 static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = {
593 &omap44xx_l4_wkup__wd_timer2, 825 &omap44xx_l4_wkup__wd_timer2,
594 }; 826 };
595 827
596 static struct omap_hwmod omap44xx_wd_timer2_hwmod = { 828 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
597 .name = "wd_timer2", 829 .name = "wd_timer2",
598 .class = &omap44xx_wd_timer_hwmod_class, 830 .class = &omap44xx_wd_timer_hwmod_class,
599 .mpu_irqs = omap44xx_wd_timer2_irqs, 831 .mpu_irqs = omap44xx_wd_timer2_irqs,
600 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_wd_timer2_irqs), 832 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_wd_timer2_irqs),
601 .main_clk = "wd_timer2_fck", 833 .main_clk = "wd_timer2_fck",
602 .prcm = { 834 .prcm = {
603 .omap4 = { 835 .omap4 = {
604 .clkctrl_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL, 836 .clkctrl_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
605 }, 837 },
606 }, 838 },
607 .slaves = omap44xx_wd_timer2_slaves, 839 .slaves = omap44xx_wd_timer2_slaves,
608 .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer2_slaves), 840 .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer2_slaves),
609 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 841 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
610 }; 842 };
611 843
612 /* wd_timer3 */ 844 /* wd_timer3 */
613 static struct omap_hwmod omap44xx_wd_timer3_hwmod; 845 static struct omap_hwmod omap44xx_wd_timer3_hwmod;
614 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = { 846 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
615 { .irq = 36 + OMAP44XX_IRQ_GIC_START }, 847 { .irq = 36 + OMAP44XX_IRQ_GIC_START },
616 }; 848 };
617 849
618 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = { 850 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
619 { 851 {
620 .pa_start = 0x40130000, 852 .pa_start = 0x40130000,
621 .pa_end = 0x4013007f, 853 .pa_end = 0x4013007f,
622 .flags = ADDR_TYPE_RT 854 .flags = ADDR_TYPE_RT
623 }, 855 },
624 }; 856 };
625 857
626 /* l4_per -> uart2 */ 858 /* l4_per -> uart2 */
627 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = { 859 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
628 .master = &omap44xx_l4_per_hwmod, 860 .master = &omap44xx_l4_per_hwmod,
629 .slave = &omap44xx_uart2_hwmod, 861 .slave = &omap44xx_uart2_hwmod,
630 .clk = "l4_div_ck", 862 .clk = "l4_div_ck",
631 .addr = omap44xx_uart2_addrs, 863 .addr = omap44xx_uart2_addrs,
632 .addr_cnt = ARRAY_SIZE(omap44xx_uart2_addrs), 864 .addr_cnt = ARRAY_SIZE(omap44xx_uart2_addrs),
633 .user = OCP_USER_MPU | OCP_USER_SDMA, 865 .user = OCP_USER_MPU | OCP_USER_SDMA,
634 }; 866 };
635 867
636 /* uart2 slave ports */ 868 /* uart2 slave ports */
637 static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = { 869 static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = {
638 &omap44xx_l4_per__uart2, 870 &omap44xx_l4_per__uart2,
639 }; 871 };
640 872
641 static struct omap_hwmod omap44xx_uart2_hwmod = { 873 static struct omap_hwmod omap44xx_uart2_hwmod = {
642 .name = "uart2", 874 .name = "uart2",
643 .class = &omap44xx_uart_hwmod_class, 875 .class = &omap44xx_uart_hwmod_class,
644 .mpu_irqs = omap44xx_uart2_irqs, 876 .mpu_irqs = omap44xx_uart2_irqs,
645 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart2_irqs), 877 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart2_irqs),
646 .sdma_reqs = omap44xx_uart2_sdma_reqs, 878 .sdma_reqs = omap44xx_uart2_sdma_reqs,
647 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart2_sdma_reqs), 879 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart2_sdma_reqs),
648 .main_clk = "uart2_fck", 880 .main_clk = "uart2_fck",
649 .prcm = { 881 .prcm = {
650 .omap4 = { 882 .omap4 = {
651 .clkctrl_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL, 883 .clkctrl_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL,
652 }, 884 },
653 }, 885 },
654 .slaves = omap44xx_uart2_slaves, 886 .slaves = omap44xx_uart2_slaves,
655 .slaves_cnt = ARRAY_SIZE(omap44xx_uart2_slaves), 887 .slaves_cnt = ARRAY_SIZE(omap44xx_uart2_slaves),
656 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 888 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
657 }; 889 };
658 890
659 /* uart3 */ 891 /* uart3 */
660 static struct omap_hwmod omap44xx_uart3_hwmod; 892 static struct omap_hwmod omap44xx_uart3_hwmod;
661 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = { 893 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
662 { .irq = 74 + OMAP44XX_IRQ_GIC_START }, 894 { .irq = 74 + OMAP44XX_IRQ_GIC_START },
663 }; 895 };
664 896
665 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = { 897 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
666 { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START }, 898 { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
667 { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START }, 899 { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
668 }; 900 };
669 901
670 static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = { 902 static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
671 { 903 {
672 .pa_start = 0x48020000, 904 .pa_start = 0x48020000,
673 .pa_end = 0x480200ff, 905 .pa_end = 0x480200ff,
674 .flags = ADDR_TYPE_RT 906 .flags = ADDR_TYPE_RT
675 }, 907 },
676 }; 908 };
677 909
678 /* l4_abe -> wd_timer3 */ 910 /* l4_abe -> wd_timer3 */
679 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = { 911 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
680 .master = &omap44xx_l4_abe_hwmod, 912 .master = &omap44xx_l4_abe_hwmod,
681 .slave = &omap44xx_wd_timer3_hwmod, 913 .slave = &omap44xx_wd_timer3_hwmod,
682 .clk = "ocp_abe_iclk", 914 .clk = "ocp_abe_iclk",
683 .addr = omap44xx_wd_timer3_addrs, 915 .addr = omap44xx_wd_timer3_addrs,
684 .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer3_addrs), 916 .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer3_addrs),
685 .user = OCP_USER_MPU, 917 .user = OCP_USER_MPU,
686 }; 918 };
687 919
688 /* l4_abe -> wd_timer3 (dma) */ 920 /* l4_abe -> wd_timer3 (dma) */
689 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = { 921 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
690 { 922 {
691 .pa_start = 0x49030000, 923 .pa_start = 0x49030000,
692 .pa_end = 0x4903007f, 924 .pa_end = 0x4903007f,
693 .flags = ADDR_TYPE_RT 925 .flags = ADDR_TYPE_RT
694 }, 926 },
695 }; 927 };
696 928
697 /* l4_per -> uart3 */ 929 /* l4_per -> uart3 */
698 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = { 930 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
699 .master = &omap44xx_l4_per_hwmod, 931 .master = &omap44xx_l4_per_hwmod,
700 .slave = &omap44xx_uart3_hwmod, 932 .slave = &omap44xx_uart3_hwmod,
701 .clk = "l4_div_ck", 933 .clk = "l4_div_ck",
702 .addr = omap44xx_uart3_addrs, 934 .addr = omap44xx_uart3_addrs,
703 .addr_cnt = ARRAY_SIZE(omap44xx_uart3_addrs), 935 .addr_cnt = ARRAY_SIZE(omap44xx_uart3_addrs),
704 .user = OCP_USER_MPU | OCP_USER_SDMA, 936 .user = OCP_USER_MPU | OCP_USER_SDMA,
705 }; 937 };
706 938
707 /* uart3 slave ports */ 939 /* uart3 slave ports */
708 static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = { 940 static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = {
709 &omap44xx_l4_per__uart3, 941 &omap44xx_l4_per__uart3,
710 }; 942 };
711 943
712 static struct omap_hwmod omap44xx_uart3_hwmod = { 944 static struct omap_hwmod omap44xx_uart3_hwmod = {
713 .name = "uart3", 945 .name = "uart3",
714 .class = &omap44xx_uart_hwmod_class, 946 .class = &omap44xx_uart_hwmod_class,
715 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), 947 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
716 .mpu_irqs = omap44xx_uart3_irqs, 948 .mpu_irqs = omap44xx_uart3_irqs,
717 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart3_irqs), 949 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart3_irqs),
718 .sdma_reqs = omap44xx_uart3_sdma_reqs, 950 .sdma_reqs = omap44xx_uart3_sdma_reqs,
719 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart3_sdma_reqs), 951 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart3_sdma_reqs),
720 .main_clk = "uart3_fck", 952 .main_clk = "uart3_fck",
721 .prcm = { 953 .prcm = {
722 .omap4 = { 954 .omap4 = {
723 .clkctrl_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL, 955 .clkctrl_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL,
724 }, 956 },
725 }, 957 },
726 .slaves = omap44xx_uart3_slaves, 958 .slaves = omap44xx_uart3_slaves,
727 .slaves_cnt = ARRAY_SIZE(omap44xx_uart3_slaves), 959 .slaves_cnt = ARRAY_SIZE(omap44xx_uart3_slaves),
728 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 960 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
729 }; 961 };
730 962
731 /* uart4 */ 963 /* uart4 */
732 static struct omap_hwmod omap44xx_uart4_hwmod; 964 static struct omap_hwmod omap44xx_uart4_hwmod;
733 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = { 965 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
734 { .irq = 70 + OMAP44XX_IRQ_GIC_START }, 966 { .irq = 70 + OMAP44XX_IRQ_GIC_START },
735 }; 967 };
736 968
737 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = { 969 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
738 { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START }, 970 { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
739 { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START }, 971 { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
740 }; 972 };
741 973
742 static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = { 974 static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
743 { 975 {
744 .pa_start = 0x4806e000, 976 .pa_start = 0x4806e000,
745 .pa_end = 0x4806e0ff, 977 .pa_end = 0x4806e0ff,
746 .flags = ADDR_TYPE_RT 978 .flags = ADDR_TYPE_RT
747 }, 979 },
748 }; 980 };
749 981
750 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = { 982 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
751 .master = &omap44xx_l4_abe_hwmod, 983 .master = &omap44xx_l4_abe_hwmod,
752 .slave = &omap44xx_wd_timer3_hwmod, 984 .slave = &omap44xx_wd_timer3_hwmod,
753 .clk = "ocp_abe_iclk", 985 .clk = "ocp_abe_iclk",
754 .addr = omap44xx_wd_timer3_dma_addrs, 986 .addr = omap44xx_wd_timer3_dma_addrs,
755 .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer3_dma_addrs), 987 .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer3_dma_addrs),
756 .user = OCP_USER_SDMA, 988 .user = OCP_USER_SDMA,
757 }; 989 };
758 990
759 /* wd_timer3 slave ports */ 991 /* wd_timer3 slave ports */
760 static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = { 992 static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = {
761 &omap44xx_l4_abe__wd_timer3, 993 &omap44xx_l4_abe__wd_timer3,
762 &omap44xx_l4_abe__wd_timer3_dma, 994 &omap44xx_l4_abe__wd_timer3_dma,
763 }; 995 };
764 996
765 static struct omap_hwmod omap44xx_wd_timer3_hwmod = { 997 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
766 .name = "wd_timer3", 998 .name = "wd_timer3",
767 .class = &omap44xx_wd_timer_hwmod_class, 999 .class = &omap44xx_wd_timer_hwmod_class,
768 .mpu_irqs = omap44xx_wd_timer3_irqs, 1000 .mpu_irqs = omap44xx_wd_timer3_irqs,
769 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_wd_timer3_irqs), 1001 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_wd_timer3_irqs),
770 .main_clk = "wd_timer3_fck", 1002 .main_clk = "wd_timer3_fck",
771 .prcm = { 1003 .prcm = {
772 .omap4 = { 1004 .omap4 = {
773 .clkctrl_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL, 1005 .clkctrl_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
774 }, 1006 },
775 }, 1007 },
776 .slaves = omap44xx_wd_timer3_slaves, 1008 .slaves = omap44xx_wd_timer3_slaves,
777 .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer3_slaves), 1009 .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer3_slaves),
778 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 1010 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
779 }; 1011 };
780 1012
781 /* l4_per -> uart4 */ 1013 /* l4_per -> uart4 */
782 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = { 1014 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
783 .master = &omap44xx_l4_per_hwmod, 1015 .master = &omap44xx_l4_per_hwmod,
784 .slave = &omap44xx_uart4_hwmod, 1016 .slave = &omap44xx_uart4_hwmod,
785 .clk = "l4_div_ck", 1017 .clk = "l4_div_ck",
786 .addr = omap44xx_uart4_addrs, 1018 .addr = omap44xx_uart4_addrs,
787 .addr_cnt = ARRAY_SIZE(omap44xx_uart4_addrs), 1019 .addr_cnt = ARRAY_SIZE(omap44xx_uart4_addrs),
788 .user = OCP_USER_MPU | OCP_USER_SDMA, 1020 .user = OCP_USER_MPU | OCP_USER_SDMA,
789 }; 1021 };
790 1022
791 /* uart4 slave ports */ 1023 /* uart4 slave ports */
792 static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = { 1024 static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = {
793 &omap44xx_l4_per__uart4, 1025 &omap44xx_l4_per__uart4,
794 }; 1026 };
795 1027
796 static struct omap_hwmod omap44xx_uart4_hwmod = { 1028 static struct omap_hwmod omap44xx_uart4_hwmod = {
797 .name = "uart4", 1029 .name = "uart4",
798 .class = &omap44xx_uart_hwmod_class, 1030 .class = &omap44xx_uart_hwmod_class,
799 .mpu_irqs = omap44xx_uart4_irqs, 1031 .mpu_irqs = omap44xx_uart4_irqs,
800 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart4_irqs), 1032 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart4_irqs),
801 .sdma_reqs = omap44xx_uart4_sdma_reqs, 1033 .sdma_reqs = omap44xx_uart4_sdma_reqs,
802 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart4_sdma_reqs), 1034 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart4_sdma_reqs),
803 .main_clk = "uart4_fck", 1035 .main_clk = "uart4_fck",
804 .prcm = { 1036 .prcm = {
805 .omap4 = { 1037 .omap4 = {
806 .clkctrl_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL, 1038 .clkctrl_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL,
807 }, 1039 },
808 }, 1040 },
809 .slaves = omap44xx_uart4_slaves, 1041 .slaves = omap44xx_uart4_slaves,
810 .slaves_cnt = ARRAY_SIZE(omap44xx_uart4_slaves), 1042 .slaves_cnt = ARRAY_SIZE(omap44xx_uart4_slaves),
811 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 1043 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
812 }; 1044 };
813 1045
814 static __initdata struct omap_hwmod *omap44xx_hwmods[] = { 1046 static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
815 /* dmm class */ 1047 /* dmm class */
816 &omap44xx_dmm_hwmod, 1048 &omap44xx_dmm_hwmod,
817 /* emif_fw class */ 1049 /* emif_fw class */
818 &omap44xx_emif_fw_hwmod, 1050 &omap44xx_emif_fw_hwmod,
819 /* l3 class */ 1051 /* l3 class */
820 &omap44xx_l3_instr_hwmod, 1052 &omap44xx_l3_instr_hwmod,
821 &omap44xx_l3_main_1_hwmod, 1053 &omap44xx_l3_main_1_hwmod,
822 &omap44xx_l3_main_2_hwmod, 1054 &omap44xx_l3_main_2_hwmod,
823 &omap44xx_l3_main_3_hwmod, 1055 &omap44xx_l3_main_3_hwmod,
824 /* l4 class */ 1056 /* l4 class */
825 &omap44xx_l4_abe_hwmod, 1057 &omap44xx_l4_abe_hwmod,
826 &omap44xx_l4_cfg_hwmod, 1058 &omap44xx_l4_cfg_hwmod,
827 &omap44xx_l4_per_hwmod, 1059 &omap44xx_l4_per_hwmod,
828 &omap44xx_l4_wkup_hwmod, 1060 &omap44xx_l4_wkup_hwmod,
1061 /* i2c class */
1062 &omap44xx_i2c1_hwmod,
1063 &omap44xx_i2c2_hwmod,
1064 &omap44xx_i2c3_hwmod,
1065 &omap44xx_i2c4_hwmod,
829 /* mpu_bus class */ 1066 /* mpu_bus class */
830 &omap44xx_mpu_private_hwmod, 1067 &omap44xx_mpu_private_hwmod,
831 1068
832 /* mpu class */ 1069 /* mpu class */
833 &omap44xx_mpu_hwmod, 1070 &omap44xx_mpu_hwmod,
834 /* wd_timer class */ 1071 /* wd_timer class */
835 &omap44xx_wd_timer2_hwmod, 1072 &omap44xx_wd_timer2_hwmod,
836 &omap44xx_wd_timer3_hwmod, 1073 &omap44xx_wd_timer3_hwmod,
837 1074
838 /* uart class */ 1075 /* uart class */
839 &omap44xx_uart1_hwmod, 1076 &omap44xx_uart1_hwmod,
840 &omap44xx_uart2_hwmod, 1077 &omap44xx_uart2_hwmod,
841 &omap44xx_uart3_hwmod, 1078 &omap44xx_uart3_hwmod,
842 &omap44xx_uart4_hwmod, 1079 &omap44xx_uart4_hwmod,
843 NULL, 1080 NULL,
844 }; 1081 };
845 1082
846 int __init omap44xx_hwmod_init(void) 1083 int __init omap44xx_hwmod_init(void)
847 { 1084 {
848 return omap_hwmod_init(omap44xx_hwmods); 1085 return omap_hwmod_init(omap44xx_hwmods);
849 } 1086 }
850 1087
851 1088