Eric Lee / linux-smarc-t335x-v3.2

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Commit fe9bf4373aa24e077bfac4e8da94fa3cb43ae184

Authored by Afzal Mohammed
1 parent af4ec5a39f
Exists in master

arm:omap:am33xx: MPU voltage domain 

MPU voltage domain data added. Also added
OPP table for MPU voltage domain.

OPP table for CORE voltage domain has not been
added as there were issues upon reducing CORE
voltage, hence no dependency has been defined
for MPU.

Signed-off-by: Afzal Mohammed <afzal@ti.com>

Showing 2 changed files with 96 additions and 0 deletions Inline Diff

arch/arm/mach-omap2/opp3xxx_data.c
Diff comments   View file @ fe9bf43
1 /* 1 /*
2 * OMAP3 OPP table definitions. 2 * OMAP3 OPP table definitions.
3 * 3 *
4 * Copyright (C) 2009-2010 Texas Instruments Incorporated - http://www.ti.com/ 4 * Copyright (C) 2009-2010 Texas Instruments Incorporated - http://www.ti.com/
5 * Nishanth Menon 5 * Nishanth Menon
6 * Kevin Hilman 6 * Kevin Hilman
7 * Copyright (C) 2010-2011 Nokia Corporation. 7 * Copyright (C) 2010-2011 Nokia Corporation.
8 * Eduardo Valentin 8 * Eduardo Valentin
9 * Paul Walmsley 9 * Paul Walmsley
10 * 10 *
11 * This program is free software; you can redistribute it and/or modify 11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as 12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation. 13 * published by the Free Software Foundation.
14 * 14 *
15 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 15 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
16 * kind, whether express or implied; without even the implied warranty 16 * kind, whether express or implied; without even the implied warranty
17 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details. 18 * GNU General Public License for more details.
19 */ 19 */
20 #include <linux/module.h> 20 #include <linux/module.h>
21 21
22 #include <plat/cpu.h> 22 #include <plat/cpu.h>
23 23
24 #include "control.h" 24 #include "control.h"
25 #include "omap_opp_data.h" 25 #include "omap_opp_data.h"
26 #include "pm.h" 26 #include "pm.h"
27 27
28 /* 34xx */ 28 /* 34xx */
29 29
30 /* VDD1 */ 30 /* VDD1 */
31 31
32 #define OMAP3430_VDD_MPU_OPP1_UV 975000 32 #define OMAP3430_VDD_MPU_OPP1_UV 975000
33 #define OMAP3430_VDD_MPU_OPP2_UV 1075000 33 #define OMAP3430_VDD_MPU_OPP2_UV 1075000
34 #define OMAP3430_VDD_MPU_OPP3_UV 1200000 34 #define OMAP3430_VDD_MPU_OPP3_UV 1200000
35 #define OMAP3430_VDD_MPU_OPP4_UV 1270000 35 #define OMAP3430_VDD_MPU_OPP4_UV 1270000
36 #define OMAP3430_VDD_MPU_OPP5_UV 1350000 36 #define OMAP3430_VDD_MPU_OPP5_UV 1350000
37 37
38 struct omap_volt_data omap34xx_vddmpu_volt_data[] = { 38 struct omap_volt_data omap34xx_vddmpu_volt_data[] = {
39 VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP1_UV, OMAP343X_CONTROL_FUSE_OPP1_VDD1, 0xf4, 0x0c), 39 VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP1_UV, OMAP343X_CONTROL_FUSE_OPP1_VDD1, 0xf4, 0x0c),
40 VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP2_UV, OMAP343X_CONTROL_FUSE_OPP2_VDD1, 0xf4, 0x0c), 40 VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP2_UV, OMAP343X_CONTROL_FUSE_OPP2_VDD1, 0xf4, 0x0c),
41 VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP3_UV, OMAP343X_CONTROL_FUSE_OPP3_VDD1, 0xf9, 0x18), 41 VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP3_UV, OMAP343X_CONTROL_FUSE_OPP3_VDD1, 0xf9, 0x18),
42 VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP4_UV, OMAP343X_CONTROL_FUSE_OPP4_VDD1, 0xf9, 0x18), 42 VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP4_UV, OMAP343X_CONTROL_FUSE_OPP4_VDD1, 0xf9, 0x18),
43 VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP5_UV, OMAP343X_CONTROL_FUSE_OPP5_VDD1, 0xf9, 0x18), 43 VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP5_UV, OMAP343X_CONTROL_FUSE_OPP5_VDD1, 0xf9, 0x18),
44 VOLT_DATA_DEFINE(0, 0, 0, 0), 44 VOLT_DATA_DEFINE(0, 0, 0, 0),
45 }; 45 };
46 46
47 /* VDD2 */ 47 /* VDD2 */
48 48
49 #define OMAP3430_VDD_CORE_OPP1_UV 975000 49 #define OMAP3430_VDD_CORE_OPP1_UV 975000
50 #define OMAP3430_VDD_CORE_OPP2_UV 1050000 50 #define OMAP3430_VDD_CORE_OPP2_UV 1050000
51 #define OMAP3430_VDD_CORE_OPP3_UV 1150000 51 #define OMAP3430_VDD_CORE_OPP3_UV 1150000
52 52
53 struct omap_volt_data omap34xx_vddcore_volt_data[] = { 53 struct omap_volt_data omap34xx_vddcore_volt_data[] = {
54 VOLT_DATA_DEFINE(OMAP3430_VDD_CORE_OPP1_UV, OMAP343X_CONTROL_FUSE_OPP1_VDD2, 0xf4, 0x0c), 54 VOLT_DATA_DEFINE(OMAP3430_VDD_CORE_OPP1_UV, OMAP343X_CONTROL_FUSE_OPP1_VDD2, 0xf4, 0x0c),
55 VOLT_DATA_DEFINE(OMAP3430_VDD_CORE_OPP2_UV, OMAP343X_CONTROL_FUSE_OPP2_VDD2, 0xf4, 0x0c), 55 VOLT_DATA_DEFINE(OMAP3430_VDD_CORE_OPP2_UV, OMAP343X_CONTROL_FUSE_OPP2_VDD2, 0xf4, 0x0c),
56 VOLT_DATA_DEFINE(OMAP3430_VDD_CORE_OPP3_UV, OMAP343X_CONTROL_FUSE_OPP3_VDD2, 0xf9, 0x18), 56 VOLT_DATA_DEFINE(OMAP3430_VDD_CORE_OPP3_UV, OMAP343X_CONTROL_FUSE_OPP3_VDD2, 0xf9, 0x18),
57 VOLT_DATA_DEFINE(0, 0, 0, 0), 57 VOLT_DATA_DEFINE(0, 0, 0, 0),
58 }; 58 };
59 59
60 /* OMAP 3430 MPU Core VDD dependency table */ 60 /* OMAP 3430 MPU Core VDD dependency table */
61 static struct omap_vdd_dep_volt omap34xx_vdd_mpu_core_dep_data[] = { 61 static struct omap_vdd_dep_volt omap34xx_vdd_mpu_core_dep_data[] = {
62 {.main_vdd_volt = OMAP3430_VDD_MPU_OPP1_UV, .dep_vdd_volt = OMAP3430_VDD_CORE_OPP2_UV}, 62 {.main_vdd_volt = OMAP3430_VDD_MPU_OPP1_UV, .dep_vdd_volt = OMAP3430_VDD_CORE_OPP2_UV},
63 {.main_vdd_volt = OMAP3430_VDD_MPU_OPP2_UV, .dep_vdd_volt = OMAP3430_VDD_CORE_OPP2_UV}, 63 {.main_vdd_volt = OMAP3430_VDD_MPU_OPP2_UV, .dep_vdd_volt = OMAP3430_VDD_CORE_OPP2_UV},
64 {.main_vdd_volt = OMAP3430_VDD_MPU_OPP3_UV, .dep_vdd_volt = OMAP3430_VDD_CORE_OPP3_UV}, 64 {.main_vdd_volt = OMAP3430_VDD_MPU_OPP3_UV, .dep_vdd_volt = OMAP3430_VDD_CORE_OPP3_UV},
65 {.main_vdd_volt = OMAP3430_VDD_MPU_OPP4_UV, .dep_vdd_volt = OMAP3430_VDD_CORE_OPP3_UV}, 65 {.main_vdd_volt = OMAP3430_VDD_MPU_OPP4_UV, .dep_vdd_volt = OMAP3430_VDD_CORE_OPP3_UV},
66 {.main_vdd_volt = OMAP3430_VDD_MPU_OPP5_UV, .dep_vdd_volt = OMAP3430_VDD_CORE_OPP3_UV}, 66 {.main_vdd_volt = OMAP3430_VDD_MPU_OPP5_UV, .dep_vdd_volt = OMAP3430_VDD_CORE_OPP3_UV},
67 }; 67 };
68 68
69 struct omap_vdd_dep_info omap34xx_vddmpu_dep_info[] = { 69 struct omap_vdd_dep_info omap34xx_vddmpu_dep_info[] = {
70 { 70 {
71 .name = "core", 71 .name = "core",
72 .dep_table = omap34xx_vdd_mpu_core_dep_data, 72 .dep_table = omap34xx_vdd_mpu_core_dep_data,
73 .nr_dep_entries = ARRAY_SIZE(omap34xx_vdd_mpu_core_dep_data), 73 .nr_dep_entries = ARRAY_SIZE(omap34xx_vdd_mpu_core_dep_data),
74 }, 74 },
75 {.name = NULL, .dep_table = NULL, .nr_dep_entries = 0}, 75 {.name = NULL, .dep_table = NULL, .nr_dep_entries = 0},
76 }; 76 };
77 77
78 /* 36xx */ 78 /* 36xx */
79 79
80 /* VDD1 */ 80 /* VDD1 */
81 81
82 #define OMAP3630_VDD_MPU_OPP50_UV 1012500 82 #define OMAP3630_VDD_MPU_OPP50_UV 1012500
83 #define OMAP3630_VDD_MPU_OPP100_UV 1200000 83 #define OMAP3630_VDD_MPU_OPP100_UV 1200000
84 #define OMAP3630_VDD_MPU_OPP120_UV 1325000 84 #define OMAP3630_VDD_MPU_OPP120_UV 1325000
85 #define OMAP3630_VDD_MPU_OPP1G_UV 1375000 85 #define OMAP3630_VDD_MPU_OPP1G_UV 1375000
86 86
87 struct omap_volt_data omap36xx_vddmpu_volt_data[] = { 87 struct omap_volt_data omap36xx_vddmpu_volt_data[] = {
88 VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP50_UV, OMAP3630_CONTROL_FUSE_OPP50_VDD1, 0xf4, 0x0c), 88 VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP50_UV, OMAP3630_CONTROL_FUSE_OPP50_VDD1, 0xf4, 0x0c),
89 VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP100_UV, OMAP3630_CONTROL_FUSE_OPP100_VDD1, 0xf9, 0x16), 89 VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP100_UV, OMAP3630_CONTROL_FUSE_OPP100_VDD1, 0xf9, 0x16),
90 VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP120_UV, OMAP3630_CONTROL_FUSE_OPP120_VDD1, 0xfa, 0x23), 90 VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP120_UV, OMAP3630_CONTROL_FUSE_OPP120_VDD1, 0xfa, 0x23),
91 VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP1G_UV, OMAP3630_CONTROL_FUSE_OPP1G_VDD1, 0xfa, 0x27), 91 VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP1G_UV, OMAP3630_CONTROL_FUSE_OPP1G_VDD1, 0xfa, 0x27),
92 VOLT_DATA_DEFINE(0, 0, 0, 0), 92 VOLT_DATA_DEFINE(0, 0, 0, 0),
93 }; 93 };
94 94
95 /* VDD2 */ 95 /* VDD2 */
96 96
97 #define OMAP3630_VDD_CORE_OPP50_UV 1000000 97 #define OMAP3630_VDD_CORE_OPP50_UV 1000000
98 #define OMAP3630_VDD_CORE_OPP100_UV 1200000 98 #define OMAP3630_VDD_CORE_OPP100_UV 1200000
99 99
100 struct omap_volt_data omap36xx_vddcore_volt_data[] = { 100 struct omap_volt_data omap36xx_vddcore_volt_data[] = {
101 VOLT_DATA_DEFINE(OMAP3630_VDD_CORE_OPP50_UV, OMAP3630_CONTROL_FUSE_OPP50_VDD2, 0xf4, 0x0c), 101 VOLT_DATA_DEFINE(OMAP3630_VDD_CORE_OPP50_UV, OMAP3630_CONTROL_FUSE_OPP50_VDD2, 0xf4, 0x0c),
102 VOLT_DATA_DEFINE(OMAP3630_VDD_CORE_OPP100_UV, OMAP3630_CONTROL_FUSE_OPP100_VDD2, 0xf9, 0x16), 102 VOLT_DATA_DEFINE(OMAP3630_VDD_CORE_OPP100_UV, OMAP3630_CONTROL_FUSE_OPP100_VDD2, 0xf9, 0x16),
103 VOLT_DATA_DEFINE(0, 0, 0, 0), 103 VOLT_DATA_DEFINE(0, 0, 0, 0),
104 }; 104 };
105 105
106 /* OPP data */ 106 /* OPP data */
107 107
108 static struct omap_opp_def __initdata omap34xx_opp_def_list[] = { 108 static struct omap_opp_def __initdata omap34xx_opp_def_list[] = {
109 /* MPU OPP1 */ 109 /* MPU OPP1 */
110 OPP_INITIALIZER("mpu", "dpll1_ck", "mpu_iva", true, 125000000, OMAP3430_VDD_MPU_OPP1_UV), 110 OPP_INITIALIZER("mpu", "dpll1_ck", "mpu_iva", true, 125000000, OMAP3430_VDD_MPU_OPP1_UV),
111 /* MPU OPP2 */ 111 /* MPU OPP2 */
112 OPP_INITIALIZER("mpu", "dpll1_ck", "mpu_iva", true, 250000000, OMAP3430_VDD_MPU_OPP2_UV), 112 OPP_INITIALIZER("mpu", "dpll1_ck", "mpu_iva", true, 250000000, OMAP3430_VDD_MPU_OPP2_UV),
113 /* MPU OPP3 */ 113 /* MPU OPP3 */
114 OPP_INITIALIZER("mpu", "dpll1_ck", "mpu_iva", true, 500000000, OMAP3430_VDD_MPU_OPP3_UV), 114 OPP_INITIALIZER("mpu", "dpll1_ck", "mpu_iva", true, 500000000, OMAP3430_VDD_MPU_OPP3_UV),
115 /* MPU OPP4 */ 115 /* MPU OPP4 */
116 OPP_INITIALIZER("mpu", "dpll1_ck", "mpu_iva", true, 550000000, OMAP3430_VDD_MPU_OPP4_UV), 116 OPP_INITIALIZER("mpu", "dpll1_ck", "mpu_iva", true, 550000000, OMAP3430_VDD_MPU_OPP4_UV),
117 /* MPU OPP5 */ 117 /* MPU OPP5 */
118 OPP_INITIALIZER("mpu", "dpll1_ck", "mpu_iva", true, 600000000, OMAP3430_VDD_MPU_OPP5_UV), 118 OPP_INITIALIZER("mpu", "dpll1_ck", "mpu_iva", true, 600000000, OMAP3430_VDD_MPU_OPP5_UV),
119 119
120 /* 120 /*
121 * L3 OPP1 - 41.5 MHz is disabled because: The voltage for that OPP is 121 * L3 OPP1 - 41.5 MHz is disabled because: The voltage for that OPP is
122 * almost the same than the one at 83MHz thus providing very little 122 * almost the same than the one at 83MHz thus providing very little
123 * gain for the power point of view. In term of energy it will even 123 * gain for the power point of view. In term of energy it will even
124 * increase the consumption due to the very negative performance 124 * increase the consumption due to the very negative performance
125 * impact that frequency will do to the MPU and the whole system in 125 * impact that frequency will do to the MPU and the whole system in
126 * general. 126 * general.
127 */ 127 */
128 OPP_INITIALIZER("l3_main", "dpll3_ck", "core", false, 41500000, OMAP3430_VDD_CORE_OPP1_UV), 128 OPP_INITIALIZER("l3_main", "dpll3_ck", "core", false, 41500000, OMAP3430_VDD_CORE_OPP1_UV),
129 /* L3 OPP2 */ 129 /* L3 OPP2 */
130 OPP_INITIALIZER("l3_main", "dpll3_ck", "core", true, 83000000, OMAP3430_VDD_CORE_OPP2_UV), 130 OPP_INITIALIZER("l3_main", "dpll3_ck", "core", true, 83000000, OMAP3430_VDD_CORE_OPP2_UV),
131 /* L3 OPP3 */ 131 /* L3 OPP3 */
132 OPP_INITIALIZER("l3_main", "dpll3_ck", "core", true, 166000000, OMAP3430_VDD_CORE_OPP3_UV), 132 OPP_INITIALIZER("l3_main", "dpll3_ck", "core", true, 166000000, OMAP3430_VDD_CORE_OPP3_UV),
133 133
134 /* DSP OPP1 */ 134 /* DSP OPP1 */
135 OPP_INITIALIZER("iva", "dpll2_ck", "mpu_iva", true, 90000000, OMAP3430_VDD_MPU_OPP1_UV), 135 OPP_INITIALIZER("iva", "dpll2_ck", "mpu_iva", true, 90000000, OMAP3430_VDD_MPU_OPP1_UV),
136 /* DSP OPP2 */ 136 /* DSP OPP2 */
137 OPP_INITIALIZER("iva", "dpll2_ck", "mpu_iva", true, 180000000, OMAP3430_VDD_MPU_OPP2_UV), 137 OPP_INITIALIZER("iva", "dpll2_ck", "mpu_iva", true, 180000000, OMAP3430_VDD_MPU_OPP2_UV),
138 /* DSP OPP3 */ 138 /* DSP OPP3 */
139 OPP_INITIALIZER("iva", "dpll2_ck", "mpu_iva", true, 360000000, OMAP3430_VDD_MPU_OPP3_UV), 139 OPP_INITIALIZER("iva", "dpll2_ck", "mpu_iva", true, 360000000, OMAP3430_VDD_MPU_OPP3_UV),
140 /* DSP OPP4 */ 140 /* DSP OPP4 */
141 OPP_INITIALIZER("iva", "dpll2_ck", "mpu_iva", true, 400000000, OMAP3430_VDD_MPU_OPP4_UV), 141 OPP_INITIALIZER("iva", "dpll2_ck", "mpu_iva", true, 400000000, OMAP3430_VDD_MPU_OPP4_UV),
142 /* DSP OPP5 */ 142 /* DSP OPP5 */
143 OPP_INITIALIZER("iva", "dpll2_ck", "mpu_iva", true, 430000000, OMAP3430_VDD_MPU_OPP5_UV), 143 OPP_INITIALIZER("iva", "dpll2_ck", "mpu_iva", true, 430000000, OMAP3430_VDD_MPU_OPP5_UV),
144 }; 144 };
145 145
146 static struct omap_opp_def __initdata omap36xx_opp_def_list[] = { 146 static struct omap_opp_def __initdata omap36xx_opp_def_list[] = {
147 /* MPU OPP1 - OPP50 */ 147 /* MPU OPP1 - OPP50 */
148 OPP_INITIALIZER("mpu", "dpll1_ck", "mpu_iva", true, 300000000, OMAP3630_VDD_MPU_OPP50_UV), 148 OPP_INITIALIZER("mpu", "dpll1_ck", "mpu_iva", true, 300000000, OMAP3630_VDD_MPU_OPP50_UV),
149 /* MPU OPP2 - OPP100 */ 149 /* MPU OPP2 - OPP100 */
150 OPP_INITIALIZER("mpu", "dpll1_ck", "mpu_iva", true, 600000000, OMAP3630_VDD_MPU_OPP100_UV), 150 OPP_INITIALIZER("mpu", "dpll1_ck", "mpu_iva", true, 600000000, OMAP3630_VDD_MPU_OPP100_UV),
151 /* MPU OPP3 - OPP-Turbo */ 151 /* MPU OPP3 - OPP-Turbo */
152 OPP_INITIALIZER("mpu", "dpll1_ck", "mpu_iva", false, 800000000, OMAP3630_VDD_MPU_OPP120_UV), 152 OPP_INITIALIZER("mpu", "dpll1_ck", "mpu_iva", false, 800000000, OMAP3630_VDD_MPU_OPP120_UV),
153 /* MPU OPP4 - OPP-SB */ 153 /* MPU OPP4 - OPP-SB */
154 OPP_INITIALIZER("mpu", "dpll1_ck", "mpu_iva", false, 1000000000, OMAP3630_VDD_MPU_OPP1G_UV), 154 OPP_INITIALIZER("mpu", "dpll1_ck", "mpu_iva", false, 1000000000, OMAP3630_VDD_MPU_OPP1G_UV),
155 155
156 /* L3 OPP1 - OPP50 */ 156 /* L3 OPP1 - OPP50 */
157 OPP_INITIALIZER("l3_main", "dpll3_ck", "core", true, 100000000, OMAP3630_VDD_CORE_OPP50_UV), 157 OPP_INITIALIZER("l3_main", "dpll3_ck", "core", true, 100000000, OMAP3630_VDD_CORE_OPP50_UV),
158 /* L3 OPP2 - OPP100, OPP-Turbo, OPP-SB */ 158 /* L3 OPP2 - OPP100, OPP-Turbo, OPP-SB */
159 OPP_INITIALIZER("l3_main", "dpll3_ck", "core", true, 200000000, OMAP3630_VDD_CORE_OPP100_UV), 159 OPP_INITIALIZER("l3_main", "dpll3_ck", "core", true, 200000000, OMAP3630_VDD_CORE_OPP100_UV),
160 160
161 /* DSP OPP1 - OPP50 */ 161 /* DSP OPP1 - OPP50 */
162 OPP_INITIALIZER("iva", "dpll2_ck", "mpu_iva", true, 260000000, OMAP3630_VDD_MPU_OPP50_UV), 162 OPP_INITIALIZER("iva", "dpll2_ck", "mpu_iva", true, 260000000, OMAP3630_VDD_MPU_OPP50_UV),
163 /* DSP OPP2 - OPP100 */ 163 /* DSP OPP2 - OPP100 */
164 OPP_INITIALIZER("iva", "dpll2_ck", "mpu_iva", true, 520000000, OMAP3630_VDD_MPU_OPP100_UV), 164 OPP_INITIALIZER("iva", "dpll2_ck", "mpu_iva", true, 520000000, OMAP3630_VDD_MPU_OPP100_UV),
165 /* DSP OPP3 - OPP-Turbo */ 165 /* DSP OPP3 - OPP-Turbo */
166 OPP_INITIALIZER("iva", "dpll2_ck", "mpu_iva", false, 660000000, OMAP3630_VDD_MPU_OPP120_UV), 166 OPP_INITIALIZER("iva", "dpll2_ck", "mpu_iva", false, 660000000, OMAP3630_VDD_MPU_OPP120_UV),
167 /* DSP OPP4 - OPP-SB */ 167 /* DSP OPP4 - OPP-SB */
168 OPP_INITIALIZER("iva", "dpll2_ck", "mpu_iva", false, 800000000, OMAP3630_VDD_MPU_OPP1G_UV), 168 OPP_INITIALIZER("iva", "dpll2_ck", "mpu_iva", false, 800000000, OMAP3630_VDD_MPU_OPP1G_UV),
169 }; 169 };
170 170
171 /* OMAP 3630 MPU Core VDD dependency table */ 171 /* OMAP 3630 MPU Core VDD dependency table */
172 static struct omap_vdd_dep_volt omap36xx_vdd_mpu_core_dep_data[] = { 172 static struct omap_vdd_dep_volt omap36xx_vdd_mpu_core_dep_data[] = {
173 {.main_vdd_volt = OMAP3630_VDD_MPU_OPP50_UV, .dep_vdd_volt = OMAP3630_VDD_CORE_OPP50_UV}, 173 {.main_vdd_volt = OMAP3630_VDD_MPU_OPP50_UV, .dep_vdd_volt = OMAP3630_VDD_CORE_OPP50_UV},
174 {.main_vdd_volt = OMAP3630_VDD_MPU_OPP100_UV, .dep_vdd_volt = OMAP3630_VDD_CORE_OPP100_UV}, 174 {.main_vdd_volt = OMAP3630_VDD_MPU_OPP100_UV, .dep_vdd_volt = OMAP3630_VDD_CORE_OPP100_UV},
175 {.main_vdd_volt = OMAP3630_VDD_MPU_OPP120_UV, .dep_vdd_volt = OMAP3630_VDD_CORE_OPP100_UV}, 175 {.main_vdd_volt = OMAP3630_VDD_MPU_OPP120_UV, .dep_vdd_volt = OMAP3630_VDD_CORE_OPP100_UV},
176 {.main_vdd_volt = OMAP3630_VDD_MPU_OPP1G_UV, .dep_vdd_volt = OMAP3630_VDD_CORE_OPP100_UV}, 176 {.main_vdd_volt = OMAP3630_VDD_MPU_OPP1G_UV, .dep_vdd_volt = OMAP3630_VDD_CORE_OPP100_UV},
177 }; 177 };
178 178
179 struct omap_vdd_dep_info omap36xx_vddmpu_dep_info[] = { 179 struct omap_vdd_dep_info omap36xx_vddmpu_dep_info[] = {
180 { 180 {
181 .name = "core", 181 .name = "core",
182 .dep_table = omap36xx_vdd_mpu_core_dep_data, 182 .dep_table = omap36xx_vdd_mpu_core_dep_data,
183 .nr_dep_entries = ARRAY_SIZE(omap36xx_vdd_mpu_core_dep_data), 183 .nr_dep_entries = ARRAY_SIZE(omap36xx_vdd_mpu_core_dep_data),
184 }, 184 },
185 {.name = NULL, .dep_table = NULL, .nr_dep_entries = 0}, 185 {.name = NULL, .dep_table = NULL, .nr_dep_entries = 0},
186 }; 186 };
187 187
188 /* 33xx */
189
190 /* VDD1 */
191
192 #define AM33XX_VDD_MPU_OPP50_UV 950000
193 #define AM33XX_VDD_MPU_OPP100_UV 1100000
194 #define AM33XX_VDD_MPU_OPP120_UV 1200000
195 #define AM33XX_VDD_MPU_OPPTURBO_UV 1260000
196
197 static struct omap_opp_def __initdata am33xx_opp_def_list[] = {
198 /* MPU OPP1 - OPP50 */
199 OPP_INITIALIZER("mpu", "dpll_mpu_ck", "mpu", true, 275000000, AM33XX_VDD_MPU_OPP50_UV),
200 /* MPU OPP2 - OPP100 */
201 OPP_INITIALIZER("mpu", "dpll_mpu_ck", "mpu", true, 500000000, AM33XX_VDD_MPU_OPP100_UV),
202 /* MPU OPP3 - OPP120 */
203 OPP_INITIALIZER("mpu", "dpll_mpu_ck", "mpu", true, 600000000, AM33XX_VDD_MPU_OPP120_UV),
204 /* MPU OPP4 - OPPTurbo */
205 OPP_INITIALIZER("mpu", "dpll_mpu_ck", "mpu", true, 720000000, AM33XX_VDD_MPU_OPPTURBO_UV),
206 };
207
188 /** 208 /**
189 * omap3_opp_init() - initialize omap3 opp table 209 * omap3_opp_init() - initialize omap3 opp table
190 */ 210 */
191 int __init omap3_opp_init(void) 211 int __init omap3_opp_init(void)
192 { 212 {
193 int r = -ENODEV; 213 int r = -ENODEV;
194 214
195 if (!cpu_is_omap34xx()) 215 if (!cpu_is_omap34xx())
196 return r; 216 return r;
197 217
198 if (cpu_is_omap3630()) 218 if (cpu_is_omap3630())
199 r = omap_init_opp_table(omap36xx_opp_def_list, 219 r = omap_init_opp_table(omap36xx_opp_def_list,
200 ARRAY_SIZE(omap36xx_opp_def_list)); 220 ARRAY_SIZE(omap36xx_opp_def_list));
221 else if (cpu_is_am33xx())
222 r = omap_init_opp_table(am33xx_opp_def_list,
223 ARRAY_SIZE(am33xx_opp_def_list));
201 else 224 else
202 r = omap_init_opp_table(omap34xx_opp_def_list, 225 r = omap_init_opp_table(omap34xx_opp_def_list,
203 ARRAY_SIZE(omap34xx_opp_def_list)); 226 ARRAY_SIZE(omap34xx_opp_def_list));
204 227
205 return r; 228 return r;
206 } 229 }
207 device_initcall(omap3_opp_init); 230 device_initcall(omap3_opp_init);
208 231
arch/arm/mach-omap2/voltagedomains33xx_data.c
Diff comments   View file @ fe9bf43
1 /* 1 /*
2 * AM33XX voltage domain data 2 * AM33XX voltage domain data
3 * 3 *
4 * Copyright (C) 2011 Texas Instruments, Inc. 4 * Copyright (C) 2011 Texas Instruments, Inc.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as 7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10 #include <linux/kernel.h> 10 #include <linux/kernel.h>
11 #include <linux/init.h> 11 #include <linux/init.h>
12 #include <linux/regulator/consumer.h>
12 13
13 #include <plat/voltage.h> 14 #include <plat/voltage.h>
15 #include <plat/omap_device.h>
14 16
17 #include "omap_opp_data.h"
18
19 #define TOLERANCE 12500 /* in uV */
20
21 int am33x_mpu_voltdm_scale(struct voltagedomain *voltdm,
22 unsigned long target_volt)
23 {
24 int ret = -EINVAL;
25
26
27 if (!voltdm->regulator)
28 return ret;
29
30
31 ret = regulator_set_voltage(voltdm->regulator, target_volt,
32 target_volt + TOLERANCE);
33
34 if (ret)
35 pr_debug("Voltage change failed, ret = %d\n", ret);
36 else
37 pr_debug("Voltage scaled to %d\n",
38 regulator_get_voltage(voltdm->regulator));
39
40 return ret;
41 }
42
43 struct omap_vdd_dep_info am33xx_vddmpu_dep_info[] = {
44 {.name = NULL, .dep_table = NULL, .nr_dep_entries = 0},
45 };
46
47 static struct omap_vdd_info am33xx_vdd1_info;
48
49 int am33x_mpu_voltdm_init(struct voltagedomain *voltdm)
50 {
51 struct regulator *mpu_regulator;
52 struct device *mpu_dev;
53
54 mpu_dev = omap_device_get_by_hwmod_name("mpu");
55 if (!mpu_dev) {
56 pr_warning("%s: unable to get the mpu device\n", __func__);
57 return -EINVAL;
58 }
59
60 mpu_regulator = regulator_get(mpu_dev, voltdm->name);
61
62 if (IS_ERR(mpu_regulator)) {
63 pr_err("%s: Could not get regulator for %s\n",
64 __func__, voltdm->name);
65 return -ENODEV;
66 } else {
67 voltdm->regulator = mpu_regulator;
68 voltdm->scale = &am33x_mpu_voltdm_scale;
69 }
70
71 return 0;
72 }
73
15 static struct voltagedomain am33xx_voltdm_mpu = { 74 static struct voltagedomain am33xx_voltdm_mpu = {
16 .name = "mpu", 75 .name = "mpu",
76 .scalable = true,
77 .use_regulator = 1,
78 .regulator_init = &am33x_mpu_voltdm_init,
79 .vdd = &am33xx_vdd1_info,
17 }; 80 };
18 81
19 static struct voltagedomain am33xx_voltdm_core = { 82 static struct voltagedomain am33xx_voltdm_core = {
20 .name = "core", 83 .name = "core",
21 }; 84 };
22 85
23 static struct voltagedomain am33xx_voltdm_rtc = { 86 static struct voltagedomain am33xx_voltdm_rtc = {
24 .name = "rtc", 87 .name = "rtc",
25 }; 88 };
26 89
27 static struct voltagedomain *voltagedomains_am33xx[] __initdata = { 90 static struct voltagedomain *voltagedomains_am33xx[] __initdata = {
28 &am33xx_voltdm_mpu, 91 &am33xx_voltdm_mpu,
29 &am33xx_voltdm_core, 92 &am33xx_voltdm_core,
30 &am33xx_voltdm_rtc, 93 &am33xx_voltdm_rtc,
31 NULL, 94 NULL,
32 }; 95 };
33 96
97 static const char *sys_clk_name __initdata = "sys_clkin_ck";
98
34 void __init am33xx_voltagedomains_init(void) 99 void __init am33xx_voltagedomains_init(void)
35 { 100 {
101 struct voltagedomain *voltdm;
102 int i;
103
104 am33xx_vdd1_info.dep_vdd_info = am33xx_vddmpu_dep_info;
105
106 for (i = 0; voltdm = voltagedomains_am33xx[i], voltdm; i++)
107 voltdm->sys_clk.name = sys_clk_name;
108
36 voltdm_init(voltagedomains_am33xx); 109 voltdm_init(voltagedomains_am33xx);
37 } 110 }
38 111