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drivers/pinctrl/pinctrl-amd.c
25.9 KB
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// SPDX-License-Identifier: GPL-2.0-only |
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/* * GPIO driver for AMD * * Copyright (c) 2014,2015 AMD Corporation. * Authors: Ken Xue <Ken.Xue@amd.com> * Wu, Jeff <Jeff.Wu@amd.com> * |
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* Contact Information: Nehal Shah <Nehal-bakulchandra.Shah@amd.com> * Shyam Sundar S K <Shyam-sundar.S-k@amd.com> |
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*/ #include <linux/err.h> #include <linux/bug.h> #include <linux/kernel.h> #include <linux/module.h> #include <linux/spinlock.h> #include <linux/compiler.h> #include <linux/types.h> #include <linux/errno.h> #include <linux/log2.h> #include <linux/io.h> |
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#include <linux/gpio/driver.h> |
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#include <linux/slab.h> #include <linux/platform_device.h> #include <linux/mutex.h> #include <linux/acpi.h> #include <linux/seq_file.h> #include <linux/interrupt.h> #include <linux/list.h> #include <linux/bitops.h> |
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#include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinconf-generic.h> |
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#include "core.h" |
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#include "pinctrl-utils.h" #include "pinctrl-amd.h" |
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static int amd_gpio_get_direction(struct gpio_chip *gc, unsigned offset) { unsigned long flags; u32 pin_reg; struct amd_gpio *gpio_dev = gpiochip_get_data(gc); raw_spin_lock_irqsave(&gpio_dev->lock, flags); pin_reg = readl(gpio_dev->base + offset * 4); raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); return !(pin_reg & BIT(OUTPUT_ENABLE_OFF)); } |
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static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset) { unsigned long flags; u32 pin_reg; |
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struct amd_gpio *gpio_dev = gpiochip_get_data(gc); |
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|
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raw_spin_lock_irqsave(&gpio_dev->lock, flags); |
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pin_reg = readl(gpio_dev->base + offset * 4); |
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pin_reg &= ~BIT(OUTPUT_ENABLE_OFF); writel(pin_reg, gpio_dev->base + offset * 4); |
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raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); |
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return 0; } static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset, int value) { u32 pin_reg; unsigned long flags; |
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struct amd_gpio *gpio_dev = gpiochip_get_data(gc); |
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|
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raw_spin_lock_irqsave(&gpio_dev->lock, flags); |
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pin_reg = readl(gpio_dev->base + offset * 4); pin_reg |= BIT(OUTPUT_ENABLE_OFF); if (value) pin_reg |= BIT(OUTPUT_VALUE_OFF); else pin_reg &= ~BIT(OUTPUT_VALUE_OFF); writel(pin_reg, gpio_dev->base + offset * 4); |
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raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); |
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return 0; } static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset) { u32 pin_reg; unsigned long flags; |
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struct amd_gpio *gpio_dev = gpiochip_get_data(gc); |
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|
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raw_spin_lock_irqsave(&gpio_dev->lock, flags); |
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pin_reg = readl(gpio_dev->base + offset * 4); |
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raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); |
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return !!(pin_reg & BIT(PIN_STS_OFF)); } static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value) { u32 pin_reg; unsigned long flags; |
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struct amd_gpio *gpio_dev = gpiochip_get_data(gc); |
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|
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raw_spin_lock_irqsave(&gpio_dev->lock, flags); |
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pin_reg = readl(gpio_dev->base + offset * 4); if (value) pin_reg |= BIT(OUTPUT_VALUE_OFF); else pin_reg &= ~BIT(OUTPUT_VALUE_OFF); writel(pin_reg, gpio_dev->base + offset * 4); |
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raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); |
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} static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset, unsigned debounce) { |
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u32 time; |
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u32 pin_reg; int ret = 0; |
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unsigned long flags; |
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struct amd_gpio *gpio_dev = gpiochip_get_data(gc); |
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|
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raw_spin_lock_irqsave(&gpio_dev->lock, flags); |
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pin_reg = readl(gpio_dev->base + offset * 4); if (debounce) { pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; pin_reg &= ~DB_TMR_OUT_MASK; /* Debounce Debounce Timer Max TmrLarge TmrOutUnit Unit Debounce Time 0 0 61 usec (2 RtcClk) 976 usec 0 1 244 usec (8 RtcClk) 3.9 msec 1 0 15.6 msec (512 RtcClk) 250 msec 1 1 62.5 msec (2048 RtcClk) 1 sec */ if (debounce < 61) { pin_reg |= 1; pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); pin_reg &= ~BIT(DB_TMR_LARGE_OFF); } else if (debounce < 976) { time = debounce / 61; pin_reg |= time & DB_TMR_OUT_MASK; pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); pin_reg &= ~BIT(DB_TMR_LARGE_OFF); } else if (debounce < 3900) { time = debounce / 244; pin_reg |= time & DB_TMR_OUT_MASK; pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); pin_reg &= ~BIT(DB_TMR_LARGE_OFF); } else if (debounce < 250000) { time = debounce / 15600; pin_reg |= time & DB_TMR_OUT_MASK; pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); pin_reg |= BIT(DB_TMR_LARGE_OFF); } else if (debounce < 1000000) { time = debounce / 62500; pin_reg |= time & DB_TMR_OUT_MASK; pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); pin_reg |= BIT(DB_TMR_LARGE_OFF); } else { pin_reg &= ~DB_CNTRl_MASK; |
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ret = -EINVAL; |
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} } else { pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); pin_reg &= ~BIT(DB_TMR_LARGE_OFF); pin_reg &= ~DB_TMR_OUT_MASK; pin_reg &= ~DB_CNTRl_MASK; } writel(pin_reg, gpio_dev->base + offset * 4); |
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raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); |
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|
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return ret; |
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} |
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static int amd_gpio_set_config(struct gpio_chip *gc, unsigned offset, unsigned long config) { u32 debounce; if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) return -ENOTSUPP; debounce = pinconf_to_config_argument(config); return amd_gpio_set_debounce(gc, offset, debounce); } |
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#ifdef CONFIG_DEBUG_FS static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc) { u32 pin_reg; unsigned long flags; unsigned int bank, i, pin_num; |
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struct amd_gpio *gpio_dev = gpiochip_get_data(gc); |
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char *level_trig; char *active_level; char *interrupt_enable; char *interrupt_mask; char *wake_cntrl0; char *wake_cntrl1; char *wake_cntrl2; char *pin_sts; char *pull_up_sel; char *pull_up_enable; char *pull_down_enable; char *output_value; char *output_enable; |
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for (bank = 0; bank < gpio_dev->hwbank_num; bank++) { |
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seq_printf(s, "GPIO bank%d\t", bank); switch (bank) { case 0: i = 0; pin_num = AMD_GPIO_PINS_BANK0; break; case 1: i = 64; pin_num = AMD_GPIO_PINS_BANK1 + i; break; case 2: i = 128; pin_num = AMD_GPIO_PINS_BANK2 + i; break; |
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case 3: i = 192; pin_num = AMD_GPIO_PINS_BANK3 + i; break; |
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default: /* Illegal bank number, ignore */ continue; |
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} |
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for (; i < pin_num; i++) { seq_printf(s, "pin%d\t", i); |
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raw_spin_lock_irqsave(&gpio_dev->lock, flags); |
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pin_reg = readl(gpio_dev->base + i * 4); |
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raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); |
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if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) { |
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u8 level = (pin_reg >> ACTIVE_LEVEL_OFF) & ACTIVE_LEVEL_MASK; |
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interrupt_enable = "interrupt is enabled|"; |
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if (level == ACTIVE_LEVEL_HIGH) |
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active_level = "Active high|"; |
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else if (level == ACTIVE_LEVEL_LOW) active_level = "Active low|"; else if (!(pin_reg & BIT(LEVEL_TRIG_OFF)) && level == ACTIVE_LEVEL_BOTH) |
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active_level = "Active on both|"; else |
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active_level = "Unknown Active level|"; |
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if (pin_reg & BIT(LEVEL_TRIG_OFF)) level_trig = "Level trigger|"; else level_trig = "Edge trigger|"; } else { interrupt_enable = "interrupt is disabled|"; active_level = " "; level_trig = " "; } if (pin_reg & BIT(INTERRUPT_MASK_OFF)) interrupt_mask = "interrupt is unmasked|"; else interrupt_mask = "interrupt is masked|"; |
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if (pin_reg & BIT(WAKE_CNTRL_OFF_S0I3)) |
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wake_cntrl0 = "enable wakeup in S0i3 state|"; else wake_cntrl0 = "disable wakeup in S0i3 state|"; |
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if (pin_reg & BIT(WAKE_CNTRL_OFF_S3)) |
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wake_cntrl1 = "enable wakeup in S3 state|"; else wake_cntrl1 = "disable wakeup in S3 state|"; |
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if (pin_reg & BIT(WAKE_CNTRL_OFF_S4)) |
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wake_cntrl2 = "enable wakeup in S4/S5 state|"; else wake_cntrl2 = "disable wakeup in S4/S5 state|"; if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) { pull_up_enable = "pull-up is enabled|"; if (pin_reg & BIT(PULL_UP_SEL_OFF)) pull_up_sel = "8k pull-up|"; else pull_up_sel = "4k pull-up|"; } else { pull_up_enable = "pull-up is disabled|"; pull_up_sel = " "; } if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF)) pull_down_enable = "pull-down is enabled|"; else pull_down_enable = "Pull-down is disabled|"; if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) { pin_sts = " "; output_enable = "output is enabled|"; if (pin_reg & BIT(OUTPUT_VALUE_OFF)) output_value = "output is high|"; else output_value = "output is low|"; } else { output_enable = "output is disabled|"; output_value = " "; if (pin_reg & BIT(PIN_STS_OFF)) pin_sts = "input is high|"; else pin_sts = "input is low|"; } seq_printf(s, "%s %s %s %s %s %s " " %s %s %s %s %s %s %s 0x%x ", level_trig, active_level, interrupt_enable, interrupt_mask, wake_cntrl0, wake_cntrl1, wake_cntrl2, pin_sts, pull_up_sel, pull_up_enable, pull_down_enable, output_value, output_enable, pin_reg); } } } #else #define amd_gpio_dbg_show NULL #endif static void amd_gpio_irq_enable(struct irq_data *d) { u32 pin_reg; unsigned long flags; struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
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struct amd_gpio *gpio_dev = gpiochip_get_data(gc); |
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raw_spin_lock_irqsave(&gpio_dev->lock, flags); |
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pin_reg = readl(gpio_dev->base + (d->hwirq)*4); |
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pin_reg |= BIT(INTERRUPT_ENABLE_OFF); pin_reg |= BIT(INTERRUPT_MASK_OFF); writel(pin_reg, gpio_dev->base + (d->hwirq)*4); |
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raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); |
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} static void amd_gpio_irq_disable(struct irq_data *d) { u32 pin_reg; unsigned long flags; struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
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struct amd_gpio *gpio_dev = gpiochip_get_data(gc); |
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|
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raw_spin_lock_irqsave(&gpio_dev->lock, flags); |
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pin_reg = readl(gpio_dev->base + (d->hwirq)*4); pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF); pin_reg &= ~BIT(INTERRUPT_MASK_OFF); writel(pin_reg, gpio_dev->base + (d->hwirq)*4); |
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raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); |
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} static void amd_gpio_irq_mask(struct irq_data *d) { u32 pin_reg; unsigned long flags; struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
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struct amd_gpio *gpio_dev = gpiochip_get_data(gc); |
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|
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raw_spin_lock_irqsave(&gpio_dev->lock, flags); |
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pin_reg = readl(gpio_dev->base + (d->hwirq)*4); pin_reg &= ~BIT(INTERRUPT_MASK_OFF); writel(pin_reg, gpio_dev->base + (d->hwirq)*4); |
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raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); |
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} static void amd_gpio_irq_unmask(struct irq_data *d) { u32 pin_reg; unsigned long flags; struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
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struct amd_gpio *gpio_dev = gpiochip_get_data(gc); |
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raw_spin_lock_irqsave(&gpio_dev->lock, flags); |
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pin_reg = readl(gpio_dev->base + (d->hwirq)*4); pin_reg |= BIT(INTERRUPT_MASK_OFF); writel(pin_reg, gpio_dev->base + (d->hwirq)*4); |
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raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); |
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} static void amd_gpio_irq_eoi(struct irq_data *d) { u32 reg; unsigned long flags; struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
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struct amd_gpio *gpio_dev = gpiochip_get_data(gc); |
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|
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raw_spin_lock_irqsave(&gpio_dev->lock, flags); |
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reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); reg |= EOI_MASK; writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG); |
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raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); |
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} static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type) { int ret = 0; |
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u32 pin_reg, pin_reg_irq_en, mask; |
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unsigned long flags, irq_flags; |
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
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struct amd_gpio *gpio_dev = gpiochip_get_data(gc); |
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|
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raw_spin_lock_irqsave(&gpio_dev->lock, flags); |
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pin_reg = readl(gpio_dev->base + (d->hwirq)*4); |
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/* Ignore the settings coming from the client and * read the values from the ACPI tables * while setting the trigger type |
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*/ |
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|
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irq_flags = irq_get_trigger_type(d->irq); if (irq_flags != IRQ_TYPE_NONE) type = irq_flags; |
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|
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switch (type & IRQ_TYPE_SENSE_MASK) { case IRQ_TYPE_EDGE_RISING: pin_reg &= ~BIT(LEVEL_TRIG_OFF); pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; |
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irq_set_handler_locked(d, handle_edge_irq); |
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break; case IRQ_TYPE_EDGE_FALLING: pin_reg &= ~BIT(LEVEL_TRIG_OFF); pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; |
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irq_set_handler_locked(d, handle_edge_irq); |
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break; case IRQ_TYPE_EDGE_BOTH: pin_reg &= ~BIT(LEVEL_TRIG_OFF); pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF; pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; |
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irq_set_handler_locked(d, handle_edge_irq); |
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break; case IRQ_TYPE_LEVEL_HIGH: pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); pin_reg |= DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF; |
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irq_set_handler_locked(d, handle_level_irq); |
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break; case IRQ_TYPE_LEVEL_LOW: pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); pin_reg |= DB_TYPE_PRESERVE_HIGH_GLITCH << DB_CNTRL_OFF; |
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irq_set_handler_locked(d, handle_level_irq); |
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break; case IRQ_TYPE_NONE: break; default: dev_err(&gpio_dev->pdev->dev, "Invalid type value "); ret = -EINVAL; |
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} pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF; |
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/* * If WAKE_INT_MASTER_REG.MaskStsEn is set, a software write to the * debounce registers of any GPIO will block wake/interrupt status |
48c67f1fc pinctrl/amd: fix ... |
480 |
* generation for *all* GPIOs for a length of time that depends on |
b85bfa246 pinctrl/amd: poll... |
481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 |
* WAKE_INT_MASTER_REG.MaskStsLength[11:0]. During this period the * INTERRUPT_ENABLE bit will read as 0. * * We temporarily enable irq for the GPIO whose configuration is * changing, and then wait for it to read back as 1 to know when * debounce has settled and then disable the irq again. * We do this polling with the spinlock held to ensure other GPIO * access routines do not read an incorrect value for the irq enable * bit of other GPIOs. We keep the GPIO masked while polling to avoid * spurious irqs, and disable the irq again after polling. */ mask = BIT(INTERRUPT_ENABLE_OFF); pin_reg_irq_en = pin_reg; pin_reg_irq_en |= mask; pin_reg_irq_en &= ~BIT(INTERRUPT_MASK_OFF); writel(pin_reg_irq_en, gpio_dev->base + (d->hwirq)*4); while ((readl(gpio_dev->base + (d->hwirq)*4) & mask) != mask) continue; |
dbad75dd1 pinctrl: add AMD ... |
499 |
writel(pin_reg, gpio_dev->base + (d->hwirq)*4); |
229710fec pinctrl: amd: mak... |
500 |
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); |
dbad75dd1 pinctrl: add AMD ... |
501 |
|
dbad75dd1 pinctrl: add AMD ... |
502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 |
return ret; } static void amd_irq_ack(struct irq_data *d) { /* * based on HW design,there is no need to ack HW * before handle current irq. But this routine is * necessary for handle_edge_irq */ } static struct irq_chip amd_gpio_irqchip = { .name = "amd_gpio", .irq_ack = amd_irq_ack, .irq_enable = amd_gpio_irq_enable, .irq_disable = amd_gpio_irq_disable, .irq_mask = amd_gpio_irq_mask, .irq_unmask = amd_gpio_irq_unmask, .irq_eoi = amd_gpio_irq_eoi, .irq_set_type = amd_gpio_irq_set_type, |
3bfd44306 pinctrl: amd: Add... |
523 |
.flags = IRQCHIP_SKIP_SET_WAKE, |
dbad75dd1 pinctrl: add AMD ... |
524 |
}; |
ba714a9c1 pinctrl/amd: Use ... |
525 526 527 |
#define PIN_IRQ_PENDING (BIT(INTERRUPT_STS_OFF) | BIT(WAKE_STS_OFF)) static irqreturn_t amd_gpio_irq_handler(int irq, void *dev_id) |
dbad75dd1 pinctrl: add AMD ... |
528 |
{ |
ba714a9c1 pinctrl/amd: Use ... |
529 530 531 532 |
struct amd_gpio *gpio_dev = dev_id; struct gpio_chip *gc = &gpio_dev->gc; irqreturn_t ret = IRQ_NONE; unsigned int i, irqnr; |
dbad75dd1 pinctrl: add AMD ... |
533 |
unsigned long flags; |
d8073aa69 pinctrl: amd: fix... |
534 535 |
u32 __iomem *regs; u32 regval; |
ba714a9c1 pinctrl/amd: Use ... |
536 |
u64 status, mask; |
dbad75dd1 pinctrl: add AMD ... |
537 |
|
ba714a9c1 pinctrl/amd: Use ... |
538 |
/* Read the wake status */ |
229710fec pinctrl: amd: mak... |
539 |
raw_spin_lock_irqsave(&gpio_dev->lock, flags); |
ba714a9c1 pinctrl/amd: Use ... |
540 541 542 |
status = readl(gpio_dev->base + WAKE_INT_STATUS_REG1); status <<= 32; status |= readl(gpio_dev->base + WAKE_INT_STATUS_REG0); |
229710fec pinctrl: amd: mak... |
543 |
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); |
dbad75dd1 pinctrl: add AMD ... |
544 |
|
ba714a9c1 pinctrl/amd: Use ... |
545 546 547 548 549 550 551 552 553 554 555 |
/* Bit 0-45 contain the relevant status bits */ status &= (1ULL << 46) - 1; regs = gpio_dev->base; for (mask = 1, irqnr = 0; status; mask <<= 1, regs += 4, irqnr += 4) { if (!(status & mask)) continue; status &= ~mask; /* Each status bit covers four pins */ for (i = 0; i < 4; i++) { regval = readl(regs + i); |
8bbed1eef pinctrl/amd: only... |
556 557 |
if (!(regval & PIN_IRQ_PENDING) || !(regval & BIT(INTERRUPT_MASK_OFF))) |
ba714a9c1 pinctrl/amd: Use ... |
558 |
continue; |
f0fbe7bce gpio: Move irqdom... |
559 |
irq = irq_find_mapping(gc->irq.domain, irqnr + i); |
d21b8adbd pinctrl: amd: dis... |
560 561 |
if (irq != 0) generic_handle_irq(irq); |
6afb10267 pinctrl/amd: fix ... |
562 563 564 565 566 |
/* Clear interrupt. * We must read the pin register again, in case the * value was changed while executing * generic_handle_irq() above. |
d21b8adbd pinctrl: amd: dis... |
567 568 569 |
* If we didn't find a mapping for the interrupt, * disable it in order to avoid a system hang caused * by an interrupt storm. |
6afb10267 pinctrl/amd: fix ... |
570 571 572 |
*/ raw_spin_lock_irqsave(&gpio_dev->lock, flags); regval = readl(regs + i); |
d21b8adbd pinctrl: amd: dis... |
573 574 575 576 577 578 579 |
if (irq == 0) { regval &= ~BIT(INTERRUPT_ENABLE_OFF); dev_dbg(&gpio_dev->pdev->dev, "Disabling spurious GPIO IRQ %d ", irqnr + i); } |
ba714a9c1 pinctrl/amd: Use ... |
580 |
writel(regval, regs + i); |
6afb10267 pinctrl/amd: fix ... |
581 |
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); |
ba714a9c1 pinctrl/amd: Use ... |
582 |
ret = IRQ_HANDLED; |
dbad75dd1 pinctrl: add AMD ... |
583 584 |
} } |
ba714a9c1 pinctrl/amd: Use ... |
585 |
/* Signal EOI to the GPIO unit */ |
229710fec pinctrl: amd: mak... |
586 |
raw_spin_lock_irqsave(&gpio_dev->lock, flags); |
ba714a9c1 pinctrl/amd: Use ... |
587 588 589 |
regval = readl(gpio_dev->base + WAKE_INT_MASTER_REG); regval |= EOI_MASK; writel(regval, gpio_dev->base + WAKE_INT_MASTER_REG); |
229710fec pinctrl: amd: mak... |
590 |
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); |
dbad75dd1 pinctrl: add AMD ... |
591 |
|
ba714a9c1 pinctrl/amd: Use ... |
592 |
return ret; |
dbad75dd1 pinctrl: add AMD ... |
593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 |
} static int amd_get_groups_count(struct pinctrl_dev *pctldev) { struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); return gpio_dev->ngroups; } static const char *amd_get_group_name(struct pinctrl_dev *pctldev, unsigned group) { struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); return gpio_dev->groups[group].name; } static int amd_get_group_pins(struct pinctrl_dev *pctldev, unsigned group, const unsigned **pins, unsigned *num_pins) { struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); *pins = gpio_dev->groups[group].pins; *num_pins = gpio_dev->groups[group].npins; return 0; } static const struct pinctrl_ops amd_pinctrl_ops = { .get_groups_count = amd_get_groups_count, .get_group_name = amd_get_group_name, .get_group_pins = amd_get_group_pins, #ifdef CONFIG_OF .dt_node_to_map = pinconf_generic_dt_node_to_map_group, |
d32f7fd3b pinctrl: Rename p... |
628 |
.dt_free_map = pinctrl_utils_free_map, |
dbad75dd1 pinctrl: add AMD ... |
629 630 631 632 633 634 635 636 637 638 639 640 |
#endif }; static int amd_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, unsigned long *config) { u32 pin_reg; unsigned arg; unsigned long flags; struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); enum pin_config_param param = pinconf_to_config_param(*config); |
229710fec pinctrl: amd: mak... |
641 |
raw_spin_lock_irqsave(&gpio_dev->lock, flags); |
dbad75dd1 pinctrl: add AMD ... |
642 |
pin_reg = readl(gpio_dev->base + pin*4); |
229710fec pinctrl: amd: mak... |
643 |
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); |
dbad75dd1 pinctrl: add AMD ... |
644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 |
switch (param) { case PIN_CONFIG_INPUT_DEBOUNCE: arg = pin_reg & DB_TMR_OUT_MASK; break; case PIN_CONFIG_BIAS_PULL_DOWN: arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0); break; case PIN_CONFIG_BIAS_PULL_UP: arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1)); break; case PIN_CONFIG_DRIVE_STRENGTH: arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK; break; default: dev_err(&gpio_dev->pdev->dev, "Invalid config param %04x ", param); return -ENOTSUPP; } *config = pinconf_to_config_packed(param, arg); return 0; } static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, unsigned long *configs, unsigned num_configs) { int i; |
dbad75dd1 pinctrl: add AMD ... |
677 |
u32 arg; |
25a853d03 Fix inconsistent ... |
678 679 |
int ret = 0; u32 pin_reg; |
dbad75dd1 pinctrl: add AMD ... |
680 681 682 |
unsigned long flags; enum pin_config_param param; struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); |
229710fec pinctrl: amd: mak... |
683 |
raw_spin_lock_irqsave(&gpio_dev->lock, flags); |
dbad75dd1 pinctrl: add AMD ... |
684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 |
for (i = 0; i < num_configs; i++) { param = pinconf_to_config_param(configs[i]); arg = pinconf_to_config_argument(configs[i]); pin_reg = readl(gpio_dev->base + pin*4); switch (param) { case PIN_CONFIG_INPUT_DEBOUNCE: pin_reg &= ~DB_TMR_OUT_MASK; pin_reg |= arg & DB_TMR_OUT_MASK; break; case PIN_CONFIG_BIAS_PULL_DOWN: pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF); pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF; break; case PIN_CONFIG_BIAS_PULL_UP: pin_reg &= ~BIT(PULL_UP_SEL_OFF); pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF; pin_reg &= ~BIT(PULL_UP_ENABLE_OFF); pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF; break; case PIN_CONFIG_DRIVE_STRENGTH: pin_reg &= ~(DRV_STRENGTH_SEL_MASK << DRV_STRENGTH_SEL_OFF); pin_reg |= (arg & DRV_STRENGTH_SEL_MASK) << DRV_STRENGTH_SEL_OFF; break; default: dev_err(&gpio_dev->pdev->dev, "Invalid config param %04x ", param); |
25a853d03 Fix inconsistent ... |
718 |
ret = -ENOTSUPP; |
dbad75dd1 pinctrl: add AMD ... |
719 720 721 722 |
} writel(pin_reg, gpio_dev->base + pin*4); } |
229710fec pinctrl: amd: mak... |
723 |
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); |
dbad75dd1 pinctrl: add AMD ... |
724 |
|
25a853d03 Fix inconsistent ... |
725 |
return ret; |
dbad75dd1 pinctrl: add AMD ... |
726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 |
} static int amd_pinconf_group_get(struct pinctrl_dev *pctldev, unsigned int group, unsigned long *config) { const unsigned *pins; unsigned npins; int ret; ret = amd_get_group_pins(pctldev, group, &pins, &npins); if (ret) return ret; if (amd_pinconf_get(pctldev, pins[0], config)) return -ENOTSUPP; return 0; } static int amd_pinconf_group_set(struct pinctrl_dev *pctldev, unsigned group, unsigned long *configs, unsigned num_configs) { const unsigned *pins; unsigned npins; int i, ret; ret = amd_get_group_pins(pctldev, group, &pins, &npins); if (ret) return ret; for (i = 0; i < npins; i++) { if (amd_pinconf_set(pctldev, pins[i], configs, num_configs)) return -ENOTSUPP; } return 0; } static const struct pinconf_ops amd_pinconf_ops = { .pin_config_get = amd_pinconf_get, .pin_config_set = amd_pinconf_set, .pin_config_group_get = amd_pinconf_group_get, .pin_config_group_set = amd_pinconf_group_set, }; |
79d2c8bed pinctrl/amd: save... |
770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 |
#ifdef CONFIG_PM_SLEEP static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin) { const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin); if (!pd) return false; /* * Only restore the pin if it is actually in use by the kernel (or * by userspace). */ if (pd->mux_owner || pd->gpio_owner || gpiochip_line_is_irq(&gpio_dev->gc, pin)) return true; return false; } |
2d71dfa2d pinctrl/amd: make... |
788 |
static int amd_gpio_suspend(struct device *dev) |
79d2c8bed pinctrl/amd: save... |
789 |
{ |
9f540c3e1 pinctrl: pinctrl-... |
790 |
struct amd_gpio *gpio_dev = dev_get_drvdata(dev); |
79d2c8bed pinctrl/amd: save... |
791 792 793 794 795 796 797 798 799 800 801 802 803 804 |
struct pinctrl_desc *desc = gpio_dev->pctrl->desc; int i; for (i = 0; i < desc->npins; i++) { int pin = desc->pins[i].number; if (!amd_gpio_should_save(gpio_dev, pin)) continue; gpio_dev->saved_regs[i] = readl(gpio_dev->base + pin*4); } return 0; } |
2d71dfa2d pinctrl/amd: make... |
805 |
static int amd_gpio_resume(struct device *dev) |
79d2c8bed pinctrl/amd: save... |
806 |
{ |
9f540c3e1 pinctrl: pinctrl-... |
807 |
struct amd_gpio *gpio_dev = dev_get_drvdata(dev); |
79d2c8bed pinctrl/amd: save... |
808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 |
struct pinctrl_desc *desc = gpio_dev->pctrl->desc; int i; for (i = 0; i < desc->npins; i++) { int pin = desc->pins[i].number; if (!amd_gpio_should_save(gpio_dev, pin)) continue; writel(gpio_dev->saved_regs[i], gpio_dev->base + pin*4); } return 0; } static const struct dev_pm_ops amd_gpio_pm_ops = { SET_LATE_SYSTEM_SLEEP_PM_OPS(amd_gpio_suspend, amd_gpio_resume) }; #endif |
dbad75dd1 pinctrl: add AMD ... |
828 829 830 831 832 833 834 835 836 837 838 |
static struct pinctrl_desc amd_pinctrl_desc = { .pins = kerncz_pins, .npins = ARRAY_SIZE(kerncz_pins), .pctlops = &amd_pinctrl_ops, .confops = &amd_pinconf_ops, .owner = THIS_MODULE, }; static int amd_gpio_probe(struct platform_device *pdev) { int ret = 0; |
25a853d03 Fix inconsistent ... |
839 |
int irq_base; |
dbad75dd1 pinctrl: add AMD ... |
840 841 842 843 844 845 846 |
struct resource *res; struct amd_gpio *gpio_dev; gpio_dev = devm_kzalloc(&pdev->dev, sizeof(struct amd_gpio), GFP_KERNEL); if (!gpio_dev) return -ENOMEM; |
229710fec pinctrl: amd: mak... |
847 |
raw_spin_lock_init(&gpio_dev->lock); |
dbad75dd1 pinctrl: add AMD ... |
848 849 850 851 852 853 854 855 856 857 |
res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) { dev_err(&pdev->dev, "Failed to get gpio io resource. "); return -EINVAL; } gpio_dev->base = devm_ioremap_nocache(&pdev->dev, res->start, resource_size(res)); |
424a6c607 pinctrl: Fix retu... |
858 859 |
if (!gpio_dev->base) return -ENOMEM; |
dbad75dd1 pinctrl: add AMD ... |
860 861 |
irq_base = platform_get_irq(pdev, 0); |
64c4dcbfc pinctrl: Remove d... |
862 |
if (irq_base < 0) |
2e6424ab8 pinctrl: amd: fix... |
863 |
return irq_base; |
dbad75dd1 pinctrl: add AMD ... |
864 |
|
79d2c8bed pinctrl/amd: save... |
865 866 867 868 869 870 871 |
#ifdef CONFIG_PM_SLEEP gpio_dev->saved_regs = devm_kcalloc(&pdev->dev, amd_pinctrl_desc.npins, sizeof(*gpio_dev->saved_regs), GFP_KERNEL); if (!gpio_dev->saved_regs) return -ENOMEM; #endif |
dbad75dd1 pinctrl: add AMD ... |
872 |
gpio_dev->pdev = pdev; |
12b10f47e pinctrl/amd: add ... |
873 |
gpio_dev->gc.get_direction = amd_gpio_get_direction; |
dbad75dd1 pinctrl: add AMD ... |
874 875 876 877 |
gpio_dev->gc.direction_input = amd_gpio_direction_input; gpio_dev->gc.direction_output = amd_gpio_direction_output; gpio_dev->gc.get = amd_gpio_get_value; gpio_dev->gc.set = amd_gpio_set_value; |
2956b5d94 pinctrl / gpio: I... |
878 |
gpio_dev->gc.set_config = amd_gpio_set_config; |
dbad75dd1 pinctrl: add AMD ... |
879 |
gpio_dev->gc.dbg_show = amd_gpio_dbg_show; |
3bfd44306 pinctrl: amd: Add... |
880 |
gpio_dev->gc.base = -1; |
dbad75dd1 pinctrl: add AMD ... |
881 882 |
gpio_dev->gc.label = pdev->name; gpio_dev->gc.owner = THIS_MODULE; |
58383c784 gpio: change memb... |
883 |
gpio_dev->gc.parent = &pdev->dev; |
3bfd44306 pinctrl: amd: Add... |
884 |
gpio_dev->gc.ngpio = resource_size(res) / 4; |
dbad75dd1 pinctrl: add AMD ... |
885 886 887 |
#if defined(CONFIG_OF_GPIO) gpio_dev->gc.of_node = pdev->dev.of_node; #endif |
3bfd44306 pinctrl: amd: Add... |
888 |
gpio_dev->hwbank_num = gpio_dev->gc.ngpio / 64; |
dbad75dd1 pinctrl: add AMD ... |
889 890 891 892 |
gpio_dev->groups = kerncz_groups; gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups); amd_pinctrl_desc.name = dev_name(&pdev->dev); |
251e22abd pinctrl: amd: Use... |
893 894 |
gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc, gpio_dev); |
323de9efd pinctrl: make pin... |
895 |
if (IS_ERR(gpio_dev->pctrl)) { |
dbad75dd1 pinctrl: add AMD ... |
896 897 |
dev_err(&pdev->dev, "Couldn't register pinctrl driver "); |
323de9efd pinctrl: make pin... |
898 |
return PTR_ERR(gpio_dev->pctrl); |
dbad75dd1 pinctrl: add AMD ... |
899 |
} |
04d367231 pinctrl: amd: use... |
900 |
ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev); |
dbad75dd1 pinctrl: add AMD ... |
901 |
if (ret) |
251e22abd pinctrl: amd: Use... |
902 |
return ret; |
dbad75dd1 pinctrl: add AMD ... |
903 904 |
ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev), |
3bfd44306 pinctrl: amd: Add... |
905 |
0, 0, gpio_dev->gc.ngpio); |
dbad75dd1 pinctrl: add AMD ... |
906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 |
if (ret) { dev_err(&pdev->dev, "Failed to add pin range "); goto out2; } ret = gpiochip_irqchip_add(&gpio_dev->gc, &amd_gpio_irqchip, 0, handle_simple_irq, IRQ_TYPE_NONE); if (ret) { dev_err(&pdev->dev, "could not add irqchip "); ret = -ENODEV; goto out2; } |
279ffafaf pinctrl: Added IR... |
923 924 |
ret = devm_request_irq(&pdev->dev, irq_base, amd_gpio_irq_handler, IRQF_SHARED, KBUILD_MODNAME, gpio_dev); |
ba714a9c1 pinctrl/amd: Use ... |
925 926 |
if (ret) goto out2; |
dbad75dd1 pinctrl: add AMD ... |
927 928 929 930 931 932 933 934 |
platform_set_drvdata(pdev, gpio_dev); dev_dbg(&pdev->dev, "amd gpio driver loaded "); return ret; out2: gpiochip_remove(&gpio_dev->gc); |
dbad75dd1 pinctrl: add AMD ... |
935 936 937 938 939 940 941 942 943 944 |
return ret; } static int amd_gpio_remove(struct platform_device *pdev) { struct amd_gpio *gpio_dev; gpio_dev = platform_get_drvdata(pdev); gpiochip_remove(&gpio_dev->gc); |
dbad75dd1 pinctrl: add AMD ... |
945 946 947 948 949 950 |
return 0; } static const struct acpi_device_id amd_gpio_acpi_match[] = { { "AMD0030", 0 }, |
42a44402e pinctrl: amd:Add ... |
951 |
{ "AMDI0030", 0}, |
dbad75dd1 pinctrl: add AMD ... |
952 953 954 955 956 957 958 |
{ }, }; MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match); static struct platform_driver amd_gpio_driver = { .driver = { .name = "amd_gpio", |
dbad75dd1 pinctrl: add AMD ... |
959 |
.acpi_match_table = ACPI_PTR(amd_gpio_acpi_match), |
79d2c8bed pinctrl/amd: save... |
960 961 962 |
#ifdef CONFIG_PM_SLEEP .pm = &amd_gpio_pm_ops, #endif |
dbad75dd1 pinctrl: add AMD ... |
963 964 965 966 967 968 969 970 971 972 |
}, .probe = amd_gpio_probe, .remove = amd_gpio_remove, }; module_platform_driver(amd_gpio_driver); MODULE_LICENSE("GPL v2"); MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>"); MODULE_DESCRIPTION("AMD GPIO pinctrl driver"); |