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arch/mips/kernel/smtc.c
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/* * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation; either version 2 * of the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * * Copyright (C) 2004 Mips Technologies, Inc * Copyright (C) 2008 Kevin D. Kissell */ |
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#include <linux/clockchips.h> |
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#include <linux/kernel.h> #include <linux/sched.h> |
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#include <linux/smp.h> |
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#include <linux/cpumask.h> #include <linux/interrupt.h> |
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#include <linux/kernel_stat.h> |
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#include <linux/module.h> |
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#include <linux/ftrace.h> |
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#include <linux/slab.h> |
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#include <asm/cpu.h> #include <asm/processor.h> |
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#include <linux/atomic.h> |
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#include <asm/system.h> #include <asm/hardirq.h> #include <asm/hazards.h> |
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#include <asm/irq.h> |
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#include <asm/mmu_context.h> |
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#include <asm/mipsregs.h> #include <asm/cacheflush.h> #include <asm/time.h> #include <asm/addrspace.h> #include <asm/smtc.h> |
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#include <asm/smtc_proc.h> /* |
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* SMTC Kernel needs to manipulate low-level CPU interrupt mask * in do_IRQ. These are passed in setup_irq_smtc() and stored * in this table. |
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*/ |
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unsigned long irq_hwmask[NR_IRQS]; |
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#define LOCK_MT_PRA() \ local_irq_save(flags); \ mtflags = dmt() #define UNLOCK_MT_PRA() \ emt(mtflags); \ local_irq_restore(flags) #define LOCK_CORE_PRA() \ local_irq_save(flags); \ mtflags = dvpe() #define UNLOCK_CORE_PRA() \ evpe(mtflags); \ local_irq_restore(flags) /* * Data structures purely associated with SMTC parallelism */ /* * Table for tracking ASIDs whose lifetime is prolonged. */ asiduse smtc_live_asid[MAX_SMTC_TLBS][MAX_SMTC_ASIDS]; |
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/* |
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* Number of InterProcessor Interrupt (IPI) message buffers to allocate |
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*/ #define IPIBUF_PER_CPU 4 |
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struct smtc_ipi_q IPIQ[NR_CPUS]; |
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static struct smtc_ipi_q freeIPIq; |
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/* Forward declarations */ |
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void ipi_decode(struct smtc_ipi *); |
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static void post_direct_ipi(int cpu, struct smtc_ipi *pipi); |
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static void setup_cross_vpe_interrupts(unsigned int nvpe); |
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void init_smtc_stats(void); /* Global SMTC Status */ |
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unsigned int smtc_status; |
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/* Boot command line configuration overrides */ |
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static int vpe0limit; |
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static int ipibuffers; static int nostlb; static int asidmask; |
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unsigned long smtc_asid_mask = 0xff; |
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static int __init vpe0tcs(char *str) { get_option(&str, &vpe0limit); return 1; } |
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static int __init ipibufs(char *str) { get_option(&str, &ipibuffers); return 1; } static int __init stlb_disable(char *s) { nostlb = 1; return 1; } static int __init asidmask_set(char *str) { get_option(&str, &asidmask); |
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switch (asidmask) { |
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case 0x1: case 0x3: case 0x7: case 0xf: case 0x1f: case 0x3f: case 0x7f: case 0xff: smtc_asid_mask = (unsigned long)asidmask; break; default: printk("ILLEGAL ASID mask 0x%x from command line ", asidmask); } return 1; } |
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__setup("vpe0tcs=", vpe0tcs); |
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__setup("ipibufs=", ipibufs); __setup("nostlb", stlb_disable); __setup("asidmask=", asidmask_set); |
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#ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG |
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static int hang_trig; |
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static int __init hangtrig_enable(char *s) { hang_trig = 1; return 1; } __setup("hangtrig", hangtrig_enable); #define DEFAULT_BLOCKED_IPI_LIMIT 32 static int timerq_limit = DEFAULT_BLOCKED_IPI_LIMIT; static int __init tintq(char *str) { get_option(&str, &timerq_limit); return 1; } __setup("tintq=", tintq); |
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static int imstuckcount[2][8]; |
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/* vpemask represents IM/IE bits of per-VPE Status registers, low-to-high */ |
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static int vpemask[2][8] = { |
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{0, 0, 1, 0, 0, 0, 0, 1}, {0, 0, 0, 0, 0, 0, 0, 1} }; |
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int tcnoprog[NR_CPUS]; |
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static atomic_t idle_hook_initialized = ATOMIC_INIT(0); |
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static int clock_hang_reported[NR_CPUS]; |
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#endif /* CONFIG_SMTC_IDLE_HOOK_DEBUG */ |
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/* * Configure shared TLB - VPC configuration bit must be set by caller */ |
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static void smtc_configure_tlb(void) |
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{ |
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int i, tlbsiz, vpes; |
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unsigned long mvpconf0; unsigned long config1val; /* Set up ASID preservation table */ for (vpes=0; vpes<MAX_SMTC_TLBS; vpes++) { for(i = 0; i < MAX_SMTC_ASIDS; i++) { smtc_live_asid[vpes][i] = 0; } } mvpconf0 = read_c0_mvpconf0(); if ((vpes = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1) > 1) { /* If we have multiple VPEs, try to share the TLB */ if ((mvpconf0 & MVPCONF0_TLBS) && !nostlb) { /* * If TLB sizing is programmable, shared TLB * size is the total available complement. * Otherwise, we have to take the sum of all * static VPE TLB entries. */ if ((tlbsiz = ((mvpconf0 & MVPCONF0_PTLBE) >> MVPCONF0_PTLBE_SHIFT)) == 0) { /* * If there's more than one VPE, there had better * be more than one TC, because we need one to bind * to each VPE in turn to be able to read * its configuration state! */ settc(1); /* Stop the TC from doing anything foolish */ write_tc_c0_tchalt(TCHALT_H); mips_ihb(); /* No need to un-Halt - that happens later anyway */ for (i=0; i < vpes; i++) { write_tc_c0_tcbind(i); /* * To be 100% sure we're really getting the right * information, we exit the configuration state * and do an IHB after each rebinding. */ write_c0_mvpcontrol( read_c0_mvpcontrol() & ~ MVPCONTROL_VPC ); mips_ihb(); /* * Only count if the MMU Type indicated is TLB */ |
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if (((read_vpe_c0_config() & MIPS_CONF_MT) >> 7) == 1) { |
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config1val = read_vpe_c0_config1(); tlbsiz += ((config1val >> 25) & 0x3f) + 1; } /* Put core back in configuration state */ write_c0_mvpcontrol( read_c0_mvpcontrol() | MVPCONTROL_VPC ); mips_ihb(); } } write_c0_mvpcontrol(read_c0_mvpcontrol() | MVPCONTROL_STLB); |
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ehb(); |
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/* * Setup kernel data structures to use software total, * rather than read the per-VPE Config1 value. The values * for "CPU 0" gets copied to all the other CPUs as part * of their initialization in smtc_cpu_setup(). */ |
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/* MIPS32 limits TLB indices to 64 */ if (tlbsiz > 64) tlbsiz = 64; cpu_data[0].tlbsize = current_cpu_data.tlbsize = tlbsiz; |
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smtc_status |= SMTC_TLB_SHARED; |
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local_flush_tlb_all(); |
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printk("TLB of %d entry pairs shared by %d VPEs ", tlbsiz, vpes); } else { printk("WARNING: TLB Not Sharable on SMTC Boot! "); } } } /* * Incrementally build the CPU map out of constituent MIPS MT cores, * using the specified available VPEs and TCs. Plaform code needs * to ensure that each MIPS MT core invokes this routine on reset, * one at a time(!). * * This version of the build_cpu_map and prepare_cpus routines assumes * that *all* TCs of a MIPS MT core will be used for Linux, and that * they will be spread across *all* available VPEs (to minimise the * loss of efficiency due to exception service serialization). * An improved version would pick up configuration information and * possibly leave some TCs/VPEs as "slave" processors. * * Use c0_MVPConf0 to find out how many TCs are available, setting up |
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* cpu_possible_map and the logical/physical mappings. |
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*/ |
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int __init smtc_build_cpu_map(int start_cpu_slot) |
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{ int i, ntcs; /* * The CPU map isn't actually used for anything at this point, * so it's not clear what else we should do apart from set * everything up so that "logical" = "physical". */ ntcs = ((read_c0_mvpconf0() & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1; for (i=start_cpu_slot; i<NR_CPUS && i<ntcs; i++) { |
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set_cpu_possible(i, true); |
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__cpu_number_map[i] = i; __cpu_logical_map[i] = i; } |
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#ifdef CONFIG_MIPS_MT_FPAFF |
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/* Initialize map of CPUs with FPUs */ cpus_clear(mt_fpu_cpumask); |
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#endif |
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/* One of those TC's is the one booting, and not a secondary... */ printk("%i available secondary CPU TC(s) ", i - 1); return i; } /* * Common setup before any secondaries are started * Make sure all CPU's are in a sensible state before we boot any of the * secondaries. * * For MIPS MT "SMTC" operation, we set up all TCs, spread as evenly * as possible across the available VPEs. */ static void smtc_tc_setup(int vpe, int tc, int cpu) { settc(tc); write_tc_c0_tchalt(TCHALT_H); mips_ihb(); write_tc_c0_tcstatus((read_tc_c0_tcstatus() & ~(TCSTATUS_TKSU | TCSTATUS_DA | TCSTATUS_IXMT)) | TCSTATUS_A); |
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/* * TCContext gets an offset from the base of the IPIQ array * to be used in low-level code to detect the presence of * an active IPI queue */ write_tc_c0_tccontext((sizeof(struct smtc_ipi_q) * cpu) << 16); |
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/* Bind tc to vpe */ write_tc_c0_tcbind(vpe); /* In general, all TCs should have the same cpu_data indications */ memcpy(&cpu_data[cpu], &cpu_data[0], sizeof(struct cpuinfo_mips)); /* For 34Kf, start with TC/CPU 0 as sole owner of single FPU context */ |
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if (cpu_data[0].cputype == CPU_34K || cpu_data[0].cputype == CPU_1004K) |
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cpu_data[cpu].options &= ~MIPS_CPU_FPU; cpu_data[cpu].vpe_id = vpe; cpu_data[cpu].tc_id = tc; |
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/* Multi-core SMTC hasn't been tested, but be prepared */ cpu_data[cpu].core = (read_vpe_c0_ebase() >> 1) & 0xff; |
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} |
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/* * Tweak to get Count registes in as close a sync as possible. * Value seems good for 34K-class cores. */ #define CP0_SKEW 8 |
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void smtc_prepare_cpus(int cpus) |
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{ |
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int i, vpe, tc, ntc, nvpe, tcpervpe[NR_CPUS], slop, cpu; |
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unsigned long flags; unsigned long val; int nipi; struct smtc_ipi *pipi; /* disable interrupts so we can disable MT */ local_irq_save(flags); /* disable MT so we can configure */ dvpe(); dmt(); |
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spin_lock_init(&freeIPIq.lock); |
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/* * We probably don't have as many VPEs as we do SMP "CPUs", * but it's possible - and in any case we'll never use more! */ for (i=0; i<NR_CPUS; i++) { IPIQ[i].head = IPIQ[i].tail = NULL; |
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spin_lock_init(&IPIQ[i].lock); |
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IPIQ[i].depth = 0; |
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IPIQ[i].resched_flag = 0; /* No reschedules queued initially */ |
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} /* cpu_data index starts at zero */ cpu = 0; cpu_data[cpu].vpe_id = 0; cpu_data[cpu].tc_id = 0; |
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cpu_data[cpu].core = (read_c0_ebase() >> 1) & 0xff; |
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cpu++; /* Report on boot-time options */ |
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mips_mt_set_cpuoptions(); |
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if (vpelimit > 0) printk("Limit of %d VPEs set ", vpelimit); if (tclimit > 0) printk("Limit of %d TCs set ", tclimit); if (nostlb) { printk("Shared TLB Use Inhibited - UNSAFE for Multi-VPE Operation "); } if (asidmask) printk("ASID mask value override to 0x%x ", asidmask); /* Temporary */ |
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#ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG |
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if (hang_trig) printk("Logic Analyser Trigger on suspected TC hang "); |
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#endif /* CONFIG_SMTC_IDLE_HOOK_DEBUG */ |
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/* Put MVPE's into 'configuration state' */ write_c0_mvpcontrol( read_c0_mvpcontrol() | MVPCONTROL_VPC ); val = read_c0_mvpconf0(); nvpe = ((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1; if (vpelimit > 0 && nvpe > vpelimit) nvpe = vpelimit; ntc = ((val & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1; if (ntc > NR_CPUS) ntc = NR_CPUS; if (tclimit > 0 && ntc > tclimit) ntc = tclimit; |
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slop = ntc % nvpe; for (i = 0; i < nvpe; i++) { tcpervpe[i] = ntc / nvpe; if (slop) { if((slop - i) > 0) tcpervpe[i]++; } } /* Handle command line override for VPE0 */ if (vpe0limit > ntc) vpe0limit = ntc; if (vpe0limit > 0) { int slopslop; if (vpe0limit < tcpervpe[0]) { /* Reducing TC count - distribute to others */ slop = tcpervpe[0] - vpe0limit; slopslop = slop % (nvpe - 1); tcpervpe[0] = vpe0limit; for (i = 1; i < nvpe; i++) { tcpervpe[i] += slop / (nvpe - 1); if(slopslop && ((slopslop - (i - 1) > 0))) tcpervpe[i]++; } } else if (vpe0limit > tcpervpe[0]) { /* Increasing TC count - steal from others */ slop = vpe0limit - tcpervpe[0]; slopslop = slop % (nvpe - 1); tcpervpe[0] = vpe0limit; for (i = 1; i < nvpe; i++) { tcpervpe[i] -= slop / (nvpe - 1); if(slopslop && ((slopslop - (i - 1) > 0))) tcpervpe[i]--; } } } |
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/* Set up shared TLB */ smtc_configure_tlb(); for (tc = 0, vpe = 0 ; (vpe < nvpe) && (tc < ntc) ; vpe++) { |
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if (tcpervpe[vpe] == 0) continue; |
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if (vpe != 0) printk(", "); printk("VPE %d: TC", vpe); |
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for (i = 0; i < tcpervpe[vpe]; i++) { |
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/* * TC 0 is bound to VPE 0 at reset, * and is presumably executing this * code. Leave it alone! */ if (tc != 0) { |
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smtc_tc_setup(vpe, tc, cpu); |
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cpu++; } printk(" %d", tc); tc++; } |
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if (vpe != 0) { /* |
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* Allow this VPE to control others. */ write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_MVP); /* |
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* Clear any stale software interrupts from VPE's Cause */ write_vpe_c0_cause(0); /* * Clear ERL/EXL of VPEs other than 0 * and set restricted interrupt enable/mask. */ write_vpe_c0_status((read_vpe_c0_status() & ~(ST0_BEV | ST0_ERL | ST0_EXL | ST0_IM)) | (STATUSF_IP0 | STATUSF_IP1 | STATUSF_IP7 | ST0_IE)); /* * set config to be the same as vpe0, * particularly kseg0 coherency alg */ write_vpe_c0_config(read_c0_config()); /* Clear any pending timer interrupt */ write_vpe_c0_compare(0); /* Propagate Config7 */ write_vpe_c0_config7(read_c0_config7()); |
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write_vpe_c0_count(read_c0_count() + CP0_SKEW); ehb(); |
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} /* enable multi-threading within VPE */ write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() | VPECONTROL_TE); /* enable the VPE */ write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_VPA); } /* * Pull any physically present but unused TCs out of circulation. */ while (tc < (((val & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1)) { |
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set_cpu_possible(tc, false); set_cpu_present(tc, false); |
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tc++; } /* release config state */ write_c0_mvpcontrol( read_c0_mvpcontrol() & ~ MVPCONTROL_VPC ); printk(" "); /* Set up coprocessor affinity CPU mask(s) */ |
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#ifdef CONFIG_MIPS_MT_FPAFF |
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536 |
for (tc = 0; tc < ntc; tc++) { |
4bf42d427 [MIPS] SMTC: Refo... |
537 |
if (cpu_data[tc].options & MIPS_CPU_FPU) |
41c594ab6 [MIPS] MT: Improv... |
538 539 |
cpu_set(tc, mt_fpu_cpumask); } |
ea5804015 [MIPS] Dyntick su... |
540 |
#endif |
41c594ab6 [MIPS] MT: Improv... |
541 542 543 544 |
/* set up ipi interrupts... */ /* If we have multiple VPEs running, set up the cross-VPE interrupt */ |
20bb25d10 [MIPS] SMTC: Fix ... |
545 |
setup_cross_vpe_interrupts(nvpe); |
41c594ab6 [MIPS] MT: Improv... |
546 547 548 549 550 551 552 553 |
/* Set up queue of free IPI "messages". */ nipi = NR_CPUS * IPIBUF_PER_CPU; if (ipibuffers > 0) nipi = ipibuffers; pipi = kmalloc(nipi *sizeof(struct smtc_ipi), GFP_KERNEL); if (pipi == NULL) |
ab75dc02c MIPS: Fix up inco... |
554 |
panic("kmalloc of IPI message buffers failed"); |
41c594ab6 [MIPS] MT: Improv... |
555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 |
else printk("IPI buffer pool of %d buffers ", nipi); for (i = 0; i < nipi; i++) { smtc_ipi_nq(&freeIPIq, pipi); pipi++; } /* Arm multithreading and enable other VPEs - but all TCs are Halted */ emt(EMT_ENABLE); evpe(EVPE_ENABLE); local_irq_restore(flags); /* Initialize SMTC /proc statistics/diagnostics */ init_smtc_stats(); } /* * Setup the PC, SP, and GP of a secondary processor and start it * running! * smp_bootstrap is the place to resume from * __KSTK_TOS(idle) is apparently the stack pointer * (unsigned long)idle->thread_info the gp * */ |
e119d49ab [MIPS] SMTC: Fix ... |
580 |
void __cpuinit smtc_boot_secondary(int cpu, struct task_struct *idle) |
41c594ab6 [MIPS] MT: Improv... |
581 582 |
{ extern u32 kernelsp[NR_CPUS]; |
b7e4226e4 [MIPS] Build fix:... |
583 |
unsigned long flags; |
41c594ab6 [MIPS] MT: Improv... |
584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 |
int mtflags; LOCK_MT_PRA(); if (cpu_data[cpu].vpe_id != cpu_data[smp_processor_id()].vpe_id) { dvpe(); } settc(cpu_data[cpu].tc_id); /* pc */ write_tc_c0_tcrestart((unsigned long)&smp_bootstrap); /* stack pointer */ kernelsp[cpu] = __KSTK_TOS(idle); write_tc_gpr_sp(__KSTK_TOS(idle)); /* global pointer */ |
c9f4f06d3 wrap access to th... |
600 |
write_tc_gpr_gp((unsigned long)task_thread_info(idle)); |
41c594ab6 [MIPS] MT: Improv... |
601 602 603 604 605 606 607 608 609 610 611 |
smtc_status |= SMTC_MTC_ACTIVE; write_tc_c0_tchalt(0); if (cpu_data[cpu].vpe_id != cpu_data[smp_processor_id()].vpe_id) { evpe(EVPE_ENABLE); } UNLOCK_MT_PRA(); } void smtc_init_secondary(void) { |
41c594ab6 [MIPS] MT: Improv... |
612 613 614 615 616 |
local_irq_enable(); } void smtc_smp_finish(void) { |
8531a35e5 [MIPS] SMTC: Fix ... |
617 618 619 620 621 622 623 624 625 626 |
int cpu = smp_processor_id(); /* * Lowest-numbered CPU per VPE starts a clock tick. * Like per_cpu_trap_init() hack, this assumes that * SMTC init code assigns TCs consdecutively and * in ascending order across available VPEs. */ if (cpu > 0 && (cpu_data[cpu].vpe_id != cpu_data[cpu - 1].vpe_id)) write_c0_compare(read_c0_count() + mips_hpt_frequency/HZ); |
41c594ab6 [MIPS] MT: Improv... |
627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 |
printk("TC %d going on-line as CPU %d ", cpu_data[smp_processor_id()].tc_id, smp_processor_id()); } void smtc_cpus_done(void) { } /* * Support for SMTC-optimized driver IRQ registration */ /* * SMTC Kernel needs to manipulate low-level CPU interrupt mask * in do_IRQ. These are passed in setup_irq_smtc() and stored * in this table. */ int setup_irq_smtc(unsigned int irq, struct irqaction * new, unsigned long hwmask) { |
ef36fc3c5 [MIPS] SMTC: Fix ... |
649 |
#ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG |
20bb25d10 [MIPS] SMTC: Fix ... |
650 |
unsigned int vpe = current_cpu_data.vpe_id; |
3b1d4ed53 [MIPS] Don't drag... |
651 |
vpemask[vpe][irq - MIPS_CPU_IRQ_BASE] = 1; |
20bb25d10 [MIPS] SMTC: Fix ... |
652 |
#endif |
ef36fc3c5 [MIPS] SMTC: Fix ... |
653 |
irq_hwmask[irq] = hwmask; |
41c594ab6 [MIPS] MT: Improv... |
654 655 656 |
return setup_irq(irq, new); } |
f571eff0a [MIPS] IRQ Affini... |
657 658 659 660 661 662 663 664 665 666 667 668 669 |
#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF /* * Support for IRQ affinity to TCs */ void smtc_set_irq_affinity(unsigned int irq, cpumask_t affinity) { /* * If a "fast path" cache of quickly decodable affinity state * is maintained, this is where it gets done, on a call up * from the platform affinity code. */ } |
930cd54b3 MIPS: SMTC: Clean... |
670 |
void smtc_forward_irq(struct irq_data *d) |
f571eff0a [MIPS] IRQ Affini... |
671 |
{ |
930cd54b3 MIPS: SMTC: Clean... |
672 |
unsigned int irq = d->irq; |
f571eff0a [MIPS] IRQ Affini... |
673 674 675 676 677 678 679 680 681 682 683 684 |
int target; /* * OK wise guy, now figure out how to get the IRQ * to be serviced on an authorized "CPU". * * Ideally, to handle the situation where an IRQ has multiple * eligible CPUS, we would maintain state per IRQ that would * allow a fair distribution of service requests. Since the * expected use model is any-or-only-one, for simplicity * and efficiency, we just pick the easiest one to find. */ |
2a2b22129 MIPS: SMTC: Use i... |
685 |
target = cpumask_first(d->affinity); |
f571eff0a [MIPS] IRQ Affini... |
686 687 688 689 690 691 692 693 694 695 696 697 698 699 |
/* * We depend on the platform code to have correctly processed * IRQ affinity change requests to ensure that the IRQ affinity * mask has been purged of bits corresponding to nonexistent and * offline "CPUs", and to TCs bound to VPEs other than the VPE * connected to the physical interrupt input for the interrupt * in question. Otherwise we have a nasty problem with interrupt * mask management. This is best handled in non-performance-critical * platform IRQ affinity setting code, to minimize interrupt-time * checks. */ /* If no one is eligible, service locally */ |
930cd54b3 MIPS: SMTC: Clean... |
700 |
if (target >= NR_CPUS) |
f571eff0a [MIPS] IRQ Affini... |
701 |
do_IRQ_no_affinity(irq); |
930cd54b3 MIPS: SMTC: Clean... |
702 703 |
else smtc_send_ipi(target, IRQ_AFFINITY_IPI, irq); |
f571eff0a [MIPS] IRQ Affini... |
704 705 706 |
} #endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */ |
41c594ab6 [MIPS] MT: Improv... |
707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 |
/* * IPI model for SMTC is tricky, because interrupts aren't TC-specific. * Within a VPE one TC can interrupt another by different approaches. * The easiest to get right would probably be to make all TCs except * the target IXMT and set a software interrupt, but an IXMT-based * scheme requires that a handler must run before a new IPI could * be sent, which would break the "broadcast" loops in MIPS MT. * A more gonzo approach within a VPE is to halt the TC, extract * its Restart, Status, and a couple of GPRs, and program the Restart * address to emulate an interrupt. * * Within a VPE, one can be confident that the target TC isn't in * a critical EXL state when halted, since the write to the Halt * register could not have issued on the writing thread if the * halting thread had EXL set. So k0 and k1 of the target TC * can be used by the injection code. Across VPEs, one can't * be certain that the target TC isn't in a critical exception * state. So we try a two-step process of sending a software * interrupt to the target VPE, which either handles the event * itself (if it was the target) or injects the event within * the VPE. */ |
5868756dc [MIPS] SMTC: Make... |
729 |
static void smtc_ipi_qdump(void) |
41c594ab6 [MIPS] MT: Improv... |
730 731 |
{ int i; |
2e41f91d9 MIPS: SMTC: Avoid... |
732 |
struct smtc_ipi *temp; |
41c594ab6 [MIPS] MT: Improv... |
733 734 |
for (i = 0; i < NR_CPUS ;i++) { |
2e41f91d9 MIPS: SMTC: Avoid... |
735 736 |
pr_info("IPIQ[%d]: head = 0x%x, tail = 0x%x, depth = %d ", |
41c594ab6 [MIPS] MT: Improv... |
737 738 |
i, (unsigned)IPIQ[i].head, (unsigned)IPIQ[i].tail, IPIQ[i].depth); |
2e41f91d9 MIPS: SMTC: Avoid... |
739 740 741 742 743 744 745 746 747 748 749 750 751 752 |
temp = IPIQ[i].head; while (temp != IPIQ[i].tail) { pr_debug("%d %d %d: ", temp->type, temp->dest, (int)temp->arg); #ifdef SMTC_IPI_DEBUG pr_debug("%u %lu ", temp->sender, temp->stamp); #else pr_debug(" "); #endif temp = temp->flink; } |
41c594ab6 [MIPS] MT: Improv... |
753 754 755 756 757 758 759 760 761 762 763 |
} } /* * The standard atomic.h primitives don't quite do what we want * here: We need an atomic add-and-return-previous-value (which * could be done with atomic_add_return and a decrement) and an * atomic set/zero-and-return-previous-value (which can't really * be done with the atomic.h primitives). And since this is * MIPS MT, we can assume that we have LL/SC. */ |
ea5804015 [MIPS] Dyntick su... |
764 |
static inline int atomic_postincrement(atomic_t *v) |
41c594ab6 [MIPS] MT: Improv... |
765 766 767 768 769 770 771 772 773 774 775 776 777 778 |
{ unsigned long result; unsigned long temp; __asm__ __volatile__( "1: ll %0, %2 " " addu %1, %0, 1 " " sc %1, %2 " " beqz %1, 1b " |
d87d0c930 [MIPS] SMTC: Micr... |
779 |
__WEAK_LLSC_MB |
ea5804015 [MIPS] Dyntick su... |
780 781 |
: "=&r" (result), "=&r" (temp), "=m" (v->counter) : "m" (v->counter) |
41c594ab6 [MIPS] MT: Improv... |
782 783 784 785 |
: "memory"); return result; } |
41c594ab6 [MIPS] MT: Improv... |
786 787 788 789 |
void smtc_send_ipi(int cpu, int type, unsigned int action) { int tcstatus; struct smtc_ipi *pipi; |
b7e4226e4 [MIPS] Build fix:... |
790 |
unsigned long flags; |
41c594ab6 [MIPS] MT: Improv... |
791 |
int mtflags; |
8531a35e5 [MIPS] SMTC: Fix ... |
792 793 |
unsigned long tcrestart; extern void r4k_wait_irqoff(void), __pastwait(void); |
2e41f91d9 MIPS: SMTC: Avoid... |
794 795 |
int set_resched_flag = (type == LINUX_SMP_IPI && action == SMP_RESCHEDULE_YOURSELF); |
41c594ab6 [MIPS] MT: Improv... |
796 797 798 799 800 801 |
if (cpu == smp_processor_id()) { printk("Cannot Send IPI to self! "); return; } |
2e41f91d9 MIPS: SMTC: Avoid... |
802 803 |
if (set_resched_flag && IPIQ[cpu].resched_flag != 0) return; /* There is a reschedule queued already */ |
41c594ab6 [MIPS] MT: Improv... |
804 805 806 807 808 |
/* Set up a descriptor, to be delivered either promptly or queued */ pipi = smtc_ipi_dq(&freeIPIq); if (pipi == NULL) { bust_spinlocks(1); mips_mt_regdump(dvpe()); |
ab75dc02c MIPS: Fix up inco... |
809 |
panic("IPI Msg. Buffers Depleted"); |
41c594ab6 [MIPS] MT: Improv... |
810 811 812 813 814 |
} pipi->type = type; pipi->arg = (void *)action; pipi->dest = cpu; if (cpu_data[cpu].vpe_id != cpu_data[smp_processor_id()].vpe_id) { |
603e82edf arch/mips/: Spell... |
815 |
/* If not on same VPE, enqueue and send cross-VPE interrupt */ |
2e41f91d9 MIPS: SMTC: Avoid... |
816 |
IPIQ[cpu].resched_flag |= set_resched_flag; |
41c594ab6 [MIPS] MT: Improv... |
817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 |
smtc_ipi_nq(&IPIQ[cpu], pipi); LOCK_CORE_PRA(); settc(cpu_data[cpu].tc_id); write_vpe_c0_cause(read_vpe_c0_cause() | C_SW1); UNLOCK_CORE_PRA(); } else { /* * Not sufficient to do a LOCK_MT_PRA (dmt) here, * since ASID shootdown on the other VPE may * collide with this operation. */ LOCK_CORE_PRA(); settc(cpu_data[cpu].tc_id); /* Halt the targeted TC */ write_tc_c0_tchalt(TCHALT_H); mips_ihb(); /* * Inspect TCStatus - if IXMT is set, we have to queue * a message. Otherwise, we set up the "interrupt" * of the other TC */ tcstatus = read_tc_c0_tcstatus(); if ((tcstatus & TCSTATUS_IXMT) != 0) { /* |
8531a35e5 [MIPS] SMTC: Fix ... |
843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 |
* If we're in the the irq-off version of the wait * loop, we need to force exit from the wait and * do a direct post of the IPI. */ if (cpu_wait == r4k_wait_irqoff) { tcrestart = read_tc_c0_tcrestart(); if (tcrestart >= (unsigned long)r4k_wait_irqoff && tcrestart < (unsigned long)__pastwait) { write_tc_c0_tcrestart(__pastwait); tcstatus &= ~TCSTATUS_IXMT; write_tc_c0_tcstatus(tcstatus); goto postdirect; } } /* * Otherwise we queue the message for the target TC * to pick up when he does a local_irq_restore() |
41c594ab6 [MIPS] MT: Improv... |
860 861 862 |
*/ write_tc_c0_tchalt(0); UNLOCK_CORE_PRA(); |
2e41f91d9 MIPS: SMTC: Avoid... |
863 |
IPIQ[cpu].resched_flag |= set_resched_flag; |
41c594ab6 [MIPS] MT: Improv... |
864 865 |
smtc_ipi_nq(&IPIQ[cpu], pipi); } else { |
8531a35e5 [MIPS] SMTC: Fix ... |
866 |
postdirect: |
41c594ab6 [MIPS] MT: Improv... |
867 868 869 870 871 872 873 874 875 876 |
post_direct_ipi(cpu, pipi); write_tc_c0_tchalt(0); UNLOCK_CORE_PRA(); } } } /* * Send IPI message to Halted TC, TargTC/TargVPE already having been set */ |
5868756dc [MIPS] SMTC: Make... |
877 |
static void post_direct_ipi(int cpu, struct smtc_ipi *pipi) |
41c594ab6 [MIPS] MT: Improv... |
878 879 880 881 882 883 |
{ struct pt_regs *kstack; unsigned long tcstatus; unsigned long tcrestart; extern u32 kernelsp[NR_CPUS]; extern void __smtc_ipi_vector(void); |
ea5804015 [MIPS] Dyntick su... |
884 885 |
//printk("%s: on %d for %d ", __func__, smp_processor_id(), cpu); |
41c594ab6 [MIPS] MT: Improv... |
886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 |
/* Extract Status, EPC from halted TC */ tcstatus = read_tc_c0_tcstatus(); tcrestart = read_tc_c0_tcrestart(); /* If TCRestart indicates a WAIT instruction, advance the PC */ if ((tcrestart & 0x80000000) && ((*(unsigned int *)tcrestart & 0xfe00003f) == 0x42000020)) { tcrestart += 4; } /* * Save on TC's future kernel stack * * CU bit of Status is indicator that TC was * already running on a kernel stack... */ |
4bf42d427 [MIPS] SMTC: Refo... |
901 |
if (tcstatus & ST0_CU0) { |
41c594ab6 [MIPS] MT: Improv... |
902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 |
/* Note that this "- 1" is pointer arithmetic */ kstack = ((struct pt_regs *)read_tc_gpr_sp()) - 1; } else { kstack = ((struct pt_regs *)kernelsp[cpu]) - 1; } kstack->cp0_epc = (long)tcrestart; /* Save TCStatus */ kstack->cp0_tcstatus = tcstatus; /* Pass token of operation to be performed kernel stack pad area */ kstack->pad0[4] = (unsigned long)pipi; /* Pass address of function to be called likewise */ kstack->pad0[5] = (unsigned long)&ipi_decode; /* Set interrupt exempt and kernel mode */ tcstatus |= TCSTATUS_IXMT; tcstatus &= ~TCSTATUS_TKSU; write_tc_c0_tcstatus(tcstatus); ehb(); /* Set TC Restart address to be SMTC IPI vector */ write_tc_c0_tcrestart(__smtc_ipi_vector); } |
937a80157 [MIPS] Complete f... |
923 |
static void ipi_resched_interrupt(void) |
41c594ab6 [MIPS] MT: Improv... |
924 |
{ |
184748cc5 sched: Provide sc... |
925 |
scheduler_ipi(); |
41c594ab6 [MIPS] MT: Improv... |
926 |
} |
937a80157 [MIPS] Complete f... |
927 |
static void ipi_call_interrupt(void) |
41c594ab6 [MIPS] MT: Improv... |
928 929 930 931 |
{ /* Invoke generic function invocation code in smp.c */ smp_call_function_interrupt(); } |
8531a35e5 [MIPS] SMTC: Fix ... |
932 |
DECLARE_PER_CPU(struct clock_event_device, mips_clockevent_device); |
ea5804015 [MIPS] Dyntick su... |
933 |
|
8f99a1626 MIPS: Tracing: Ad... |
934 |
static void __irq_entry smtc_clock_tick_interrupt(void) |
41c594ab6 [MIPS] MT: Improv... |
935 |
{ |
ea5804015 [MIPS] Dyntick su... |
936 937 |
unsigned int cpu = smp_processor_id(); struct clock_event_device *cd; |
8f99a1626 MIPS: Tracing: Ad... |
938 939 940 941 942 943 944 945 946 947 948 |
int irq = MIPS_CPU_IRQ_BASE + 1; irq_enter(); kstat_incr_irqs_this_cpu(irq, irq_to_desc(irq)); cd = &per_cpu(mips_clockevent_device, cpu); cd->event_handler(cd); irq_exit(); } void ipi_decode(struct smtc_ipi *pipi) { |
41c594ab6 [MIPS] MT: Improv... |
949 950 |
void *arg_copy = pipi->arg; int type_copy = pipi->type; |
d2287f5eb irq: update all a... |
951 |
|
41c594ab6 [MIPS] MT: Improv... |
952 |
smtc_ipi_nq(&freeIPIq, pipi); |
dbc1d911b MIPS: SMTC: Fix f... |
953 |
|
41c594ab6 [MIPS] MT: Improv... |
954 |
switch (type_copy) { |
4bf42d427 [MIPS] SMTC: Refo... |
955 |
case SMTC_CLOCK_TICK: |
8f99a1626 MIPS: Tracing: Ad... |
956 |
smtc_clock_tick_interrupt(); |
4bf42d427 [MIPS] SMTC: Refo... |
957 |
break; |
ea5804015 [MIPS] Dyntick su... |
958 |
|
4bf42d427 [MIPS] SMTC: Refo... |
959 960 961 |
case LINUX_SMP_IPI: switch ((int)arg_copy) { case SMP_RESCHEDULE_YOURSELF: |
937a80157 [MIPS] Complete f... |
962 |
ipi_resched_interrupt(); |
41c594ab6 [MIPS] MT: Improv... |
963 |
break; |
4bf42d427 [MIPS] SMTC: Refo... |
964 |
case SMP_CALL_FUNCTION: |
937a80157 [MIPS] Complete f... |
965 |
ipi_call_interrupt(); |
41c594ab6 [MIPS] MT: Improv... |
966 967 |
break; default: |
fa90c8729 MIPS: SMTC: Use %... |
968 969 |
printk("Impossible SMTC IPI Argument %p ", arg_copy); |
41c594ab6 [MIPS] MT: Improv... |
970 |
break; |
4bf42d427 [MIPS] SMTC: Refo... |
971 972 |
} break; |
f571eff0a [MIPS] IRQ Affini... |
973 974 975 976 977 978 979 980 981 |
#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF case IRQ_AFFINITY_IPI: /* * Accept a "forwarded" interrupt that was initially * taken by a TC who doesn't have affinity for the IRQ. */ do_IRQ_no_affinity((int)arg_copy); break; #endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */ |
4bf42d427 [MIPS] SMTC: Refo... |
982 983 984 985 |
default: printk("Impossible SMTC IPI Type 0x%x ", type_copy); break; |
41c594ab6 [MIPS] MT: Improv... |
986 987 |
} } |
8531a35e5 [MIPS] SMTC: Fix ... |
988 989 990 991 992 |
/* * Similar to smtc_ipi_replay(), but invoked from context restore, * so it reuses the current exception frame rather than set up a * new one with self_ipi. */ |
937a80157 [MIPS] Complete f... |
993 |
void deferred_smtc_ipi(void) |
41c594ab6 [MIPS] MT: Improv... |
994 |
{ |
8531a35e5 [MIPS] SMTC: Fix ... |
995 |
int cpu = smp_processor_id(); |
41c594ab6 [MIPS] MT: Improv... |
996 997 998 999 |
/* * Test is not atomic, but much faster than a dequeue, * and the vast majority of invocations will have a null queue. |
8531a35e5 [MIPS] SMTC: Fix ... |
1000 1001 1002 1003 |
* If irq_disabled when this was called, then any IPIs queued * after we test last will be taken on the next irq_enable/restore. * If interrupts were enabled, then any IPIs added after the * last test will be taken directly. |
41c594ab6 [MIPS] MT: Improv... |
1004 |
*/ |
8531a35e5 [MIPS] SMTC: Fix ... |
1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 |
while (IPIQ[cpu].head != NULL) { struct smtc_ipi_q *q = &IPIQ[cpu]; struct smtc_ipi *pipi; unsigned long flags; /* * It may be possible we'll come in with interrupts * already enabled. */ local_irq_save(flags); |
8531a35e5 [MIPS] SMTC: Fix ... |
1016 1017 1018 |
spin_lock(&q->lock); pipi = __smtc_ipi_dq(q); spin_unlock(&q->lock); |
2e41f91d9 MIPS: SMTC: Avoid... |
1019 1020 1021 1022 |
if (pipi != NULL) { if (pipi->type == LINUX_SMP_IPI && (int)pipi->arg == SMP_RESCHEDULE_YOURSELF) IPIQ[cpu].resched_flag = 0; |
937a80157 [MIPS] Complete f... |
1023 |
ipi_decode(pipi); |
2e41f91d9 MIPS: SMTC: Avoid... |
1024 |
} |
8531a35e5 [MIPS] SMTC: Fix ... |
1025 1026 1027 1028 1029 1030 |
/* * The use of the __raw_local restore isn't * as obviously necessary here as in smtc_ipi_replay(), * but it's more efficient, given that we're already * running down the IPI queue. */ |
df9ee2927 Fix IRQ flag hand... |
1031 |
__arch_local_irq_restore(flags); |
41c594ab6 [MIPS] MT: Improv... |
1032 1033 1034 1035 |
} } /* |
41c594ab6 [MIPS] MT: Improv... |
1036 1037 1038 1039 1040 |
* Cross-VPE interrupts in the SMTC prototype use "software interrupts" * set via cross-VPE MTTR manipulation of the Cause register. It would be * in some regards preferable to have external logic for "doorbell" hardware * interrupts. */ |
97dcb82de [MIPS] Define MIP... |
1041 |
static int cpu_ipi_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_IRQ; |
41c594ab6 [MIPS] MT: Improv... |
1042 |
|
937a80157 [MIPS] Complete f... |
1043 |
static irqreturn_t ipi_interrupt(int irq, void *dev_idm) |
41c594ab6 [MIPS] MT: Improv... |
1044 1045 1046 1047 1048 1049 1050 |
{ int my_vpe = cpu_data[smp_processor_id()].vpe_id; int my_tc = cpu_data[smp_processor_id()].tc_id; int cpu; struct smtc_ipi *pipi; unsigned long tcstatus; int sent; |
b7e4226e4 [MIPS] Build fix:... |
1051 |
unsigned long flags; |
41c594ab6 [MIPS] MT: Improv... |
1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 |
unsigned int mtflags; unsigned int vpflags; /* * So long as cross-VPE interrupts are done via * MFTR/MTTR read-modify-writes of Cause, we need * to stop other VPEs whenever the local VPE does * anything similar. */ local_irq_save(flags); vpflags = dvpe(); clear_c0_cause(0x100 << MIPS_CPU_IPI_IRQ); set_c0_status(0x100 << MIPS_CPU_IPI_IRQ); irq_enable_hazard(); evpe(vpflags); local_irq_restore(flags); /* * Cross-VPE Interrupt handler: Try to directly deliver IPIs * queued for TCs on this VPE other than the current one. * Return-from-interrupt should cause us to drain the queue * for the current TC, so we ought not to have to do it explicitly here. */ for_each_online_cpu(cpu) { if (cpu_data[cpu].vpe_id != my_vpe) continue; pipi = smtc_ipi_dq(&IPIQ[cpu]); if (pipi != NULL) { if (cpu_data[cpu].tc_id != my_tc) { sent = 0; LOCK_MT_PRA(); settc(cpu_data[cpu].tc_id); write_tc_c0_tchalt(TCHALT_H); mips_ihb(); tcstatus = read_tc_c0_tcstatus(); if ((tcstatus & TCSTATUS_IXMT) == 0) { post_direct_ipi(cpu, pipi); sent = 1; } write_tc_c0_tchalt(0); UNLOCK_MT_PRA(); if (!sent) { smtc_ipi_req(&IPIQ[cpu], pipi); } } else { /* * ipi_decode() should be called * with interrupts off */ local_irq_save(flags); |
2e41f91d9 MIPS: SMTC: Avoid... |
1104 1105 1106 |
if (pipi->type == LINUX_SMP_IPI && (int)pipi->arg == SMP_RESCHEDULE_YOURSELF) IPIQ[cpu].resched_flag = 0; |
937a80157 [MIPS] Complete f... |
1107 |
ipi_decode(pipi); |
41c594ab6 [MIPS] MT: Improv... |
1108 1109 1110 1111 1112 1113 1114 |
local_irq_restore(flags); } } } return IRQ_HANDLED; } |
937a80157 [MIPS] Complete f... |
1115 |
static void ipi_irq_dispatch(void) |
41c594ab6 [MIPS] MT: Improv... |
1116 |
{ |
937a80157 [MIPS] Complete f... |
1117 |
do_IRQ(cpu_ipi_irq); |
41c594ab6 [MIPS] MT: Improv... |
1118 |
} |
033890b08 [MIPS] SMTC: Stat... |
1119 1120 |
static struct irqaction irq_ipi = { .handler = ipi_interrupt, |
8b5690f88 MIPS: irq: Remove... |
1121 |
.flags = IRQF_PERCPU, |
b26515839 MIPS: SMTC: Remov... |
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.name = "SMTC_IPI" |
033890b08 [MIPS] SMTC: Stat... |
1123 |
}; |
41c594ab6 [MIPS] MT: Improv... |
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|
20bb25d10 [MIPS] SMTC: Fix ... |
1125 |
static void setup_cross_vpe_interrupts(unsigned int nvpe) |
41c594ab6 [MIPS] MT: Improv... |
1126 |
{ |
20bb25d10 [MIPS] SMTC: Fix ... |
1127 1128 |
if (nvpe < 1) return; |
41c594ab6 [MIPS] MT: Improv... |
1129 |
if (!cpu_has_vint) |
603e82edf arch/mips/: Spell... |
1130 |
panic("SMTC Kernel requires Vectored Interrupt support"); |
41c594ab6 [MIPS] MT: Improv... |
1131 1132 |
set_vi_handler(MIPS_CPU_IPI_IRQ, ipi_irq_dispatch); |
41c594ab6 [MIPS] MT: Improv... |
1133 |
setup_irq_smtc(cpu_ipi_irq, &irq_ipi, (0x100 << MIPS_CPU_IPI_IRQ)); |
e4ec7989b MIPS: Convert the... |
1134 |
irq_set_handler(cpu_ipi_irq, handle_percpu_irq); |
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} /* * SMTC-specific hacks invoked from elsewhere in the kernel. */ |
8531a35e5 [MIPS] SMTC: Fix ... |
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/* * smtc_ipi_replay is called from raw_local_irq_restore */ void smtc_ipi_replay(void) |
ac8be9550 [MIPS] SMTC: Inst... |
1145 |
{ |
8a1e97ee2 [MIPS] SMTC: Fix ... |
1146 |
unsigned int cpu = smp_processor_id(); |
ac8be9550 [MIPS] SMTC: Inst... |
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/* * To the extent that we've ever turned interrupts off, * we may have accumulated deferred IPIs. This is subtle. |
ac8be9550 [MIPS] SMTC: Inst... |
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* we should be OK: If we pick up something and dispatch * it here, that's great. If we see nothing, but concurrent * with this operation, another TC sends us an IPI, IXMT * is clear, and we'll handle it as a real pseudo-interrupt |
8531a35e5 [MIPS] SMTC: Fix ... |
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* and not a pseudo-pseudo interrupt. The important thing * is to do the last check for queued message *after* the * re-enabling of interrupts. |
ac8be9550 [MIPS] SMTC: Inst... |
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*/ |
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while (IPIQ[cpu].head != NULL) { struct smtc_ipi_q *q = &IPIQ[cpu]; struct smtc_ipi *pipi; unsigned long flags; |
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|
8531a35e5 [MIPS] SMTC: Fix ... |
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/* * It's just possible we'll come in with interrupts * already enabled. */ local_irq_save(flags); spin_lock(&q->lock); pipi = __smtc_ipi_dq(q); spin_unlock(&q->lock); /* ** But use a raw restore here to avoid recursion. */ |
df9ee2927 Fix IRQ flag hand... |
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__arch_local_irq_restore(flags); |
8531a35e5 [MIPS] SMTC: Fix ... |
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if (pipi) { |
ac8be9550 [MIPS] SMTC: Inst... |
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self_ipi(pipi); |
8a1e97ee2 [MIPS] SMTC: Fix ... |
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smtc_cpu_stats[cpu].selfipis++; |
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} } } |
ec43c0142 [MIPS] SMTC: Fix ... |
1183 |
EXPORT_SYMBOL(smtc_ipi_replay); |
41c594ab6 [MIPS] MT: Improv... |
1184 1185 |
void smtc_idle_loop_hook(void) { |
c68644d33 [MIPS] Make SMTC_... |
1186 |
#ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG |
41c594ab6 [MIPS] MT: Improv... |
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int im; int flags; int mtflags; int bit; int vpe; int tc; int hook_ntcs; /* * printk within DMT-protected regions can deadlock, * so buffer diagnostic messages for later output. */ char *pdb_msg; char id_ho_db_msg[768]; /* worst-case use should be less than 700 */ if (atomic_read(&idle_hook_initialized) == 0) { /* fast test */ if (atomic_add_return(1, &idle_hook_initialized) == 1) { int mvpconf0; /* Tedious stuff to just do once */ mvpconf0 = read_c0_mvpconf0(); hook_ntcs = ((mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1; if (hook_ntcs > NR_CPUS) hook_ntcs = NR_CPUS; for (tc = 0; tc < hook_ntcs; tc++) { tcnoprog[tc] = 0; clock_hang_reported[tc] = 0; } for (vpe = 0; vpe < 2; vpe++) for (im = 0; im < 8; im++) imstuckcount[vpe][im] = 0; printk("Idle loop test hook initialized for %d TCs ", hook_ntcs); atomic_set(&idle_hook_initialized, 1000); } else { /* Someone else is initializing in parallel - let 'em finish */ while (atomic_read(&idle_hook_initialized) < 1000) ; } } /* Have we stupidly left IXMT set somewhere? */ if (read_c0_tcstatus() & 0x400) { write_c0_tcstatus(read_c0_tcstatus() & ~0x400); ehb(); printk("Dangling IXMT in cpu_idle() "); } /* Have we stupidly left an IM bit turned off? */ #define IM_LIMIT 2000 local_irq_save(flags); mtflags = dmt(); pdb_msg = &id_ho_db_msg[0]; im = read_c0_status(); |
8f8771a05 [MIPS] SMTC: Use ... |
1240 |
vpe = current_cpu_data.vpe_id; |
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for (bit = 0; bit < 8; bit++) { /* * In current prototype, I/O interrupts * are masked for VPE > 0 */ if (vpemask[vpe][bit]) { if (!(im & (0x100 << bit))) imstuckcount[vpe][bit]++; else imstuckcount[vpe][bit] = 0; if (imstuckcount[vpe][bit] > IM_LIMIT) { set_c0_status(0x100 << bit); ehb(); imstuckcount[vpe][bit] = 0; pdb_msg += sprintf(pdb_msg, "Dangling IM %d fixed for VPE %d ", bit, vpe); } } } |
41c594ab6 [MIPS] MT: Improv... |
1262 1263 1264 1265 |
emt(mtflags); local_irq_restore(flags); if (pdb_msg != &id_ho_db_msg[0]) printk("CPU%d: %s", smp_processor_id(), id_ho_db_msg); |
c68644d33 [MIPS] Make SMTC_... |
1266 |
#endif /* CONFIG_SMTC_IDLE_HOOK_DEBUG */ |
ac8be9550 [MIPS] SMTC: Inst... |
1267 |
|
8531a35e5 [MIPS] SMTC: Fix ... |
1268 |
smtc_ipi_replay(); |
41c594ab6 [MIPS] MT: Improv... |
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} void smtc_soft_dump(void) { int i; printk("Counter Interrupts taken per CPU (TC) "); for (i=0; i < NR_CPUS; i++) { printk("%d: %ld ", i, smtc_cpu_stats[i].timerints); } printk("Self-IPI invocations: "); for (i=0; i < NR_CPUS; i++) { printk("%d: %ld ", i, smtc_cpu_stats[i].selfipis); } smtc_ipi_qdump(); |
41c594ab6 [MIPS] MT: Improv... |
1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 |
printk("%d Recoveries of \"stolen\" FPU ", atomic_read(&smtc_fpu_recoveries)); } /* * TLB management routines special to SMTC */ void smtc_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu) { unsigned long flags, mtflags, tcstat, prevhalt, asid; int tlb, i; /* * It would be nice to be able to use a spinlock here, * but this is invoked from within TLB flush routines * that protect themselves with DVPE, so if a lock is |
e0daad449 [MIPS] Whitespace... |
1307 |
* held by another TC, it'll never be freed. |
41c594ab6 [MIPS] MT: Improv... |
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* * DVPE/DMT must not be done with interrupts enabled, * so even so most callers will already have disabled * them, let's be really careful... */ local_irq_save(flags); if (smtc_status & SMTC_TLB_SHARED) { mtflags = dvpe(); tlb = 0; } else { mtflags = dmt(); tlb = cpu_data[cpu].vpe_id; } asid = asid_cache(cpu); do { if (!((asid += ASID_INC) & ASID_MASK) ) { if (cpu_has_vtag_icache) flush_icache_all(); |
af901ca18 tree-wide: fix as... |
1328 |
/* Traverse all online CPUs (hack requires contiguous range) */ |
b5eb55114 [MIPS] Kill num_o... |
1329 |
for_each_online_cpu(i) { |
41c594ab6 [MIPS] MT: Improv... |
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/* * We don't need to worry about our own CPU, nor those of * CPUs who don't share our TLB. */ if ((i != smp_processor_id()) && ((smtc_status & SMTC_TLB_SHARED) || (cpu_data[i].vpe_id == cpu_data[cpu].vpe_id))) { settc(cpu_data[i].tc_id); prevhalt = read_tc_c0_tchalt() & TCHALT_H; if (!prevhalt) { write_tc_c0_tchalt(TCHALT_H); mips_ihb(); } tcstat = read_tc_c0_tcstatus(); smtc_live_asid[tlb][(tcstat & ASID_MASK)] |= (asiduse)(0x1 << i); if (!prevhalt) write_tc_c0_tchalt(0); } } if (!asid) /* fix version if needed */ asid = ASID_FIRST_VERSION; local_flush_tlb_all(); /* start new asid cycle */ } } while (smtc_live_asid[tlb][(asid & ASID_MASK)]); /* * SMTC shares the TLB within VPEs and possibly across all VPEs. */ |
b5eb55114 [MIPS] Kill num_o... |
1358 |
for_each_online_cpu(i) { |
41c594ab6 [MIPS] MT: Improv... |
1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 |
if ((smtc_status & SMTC_TLB_SHARED) || (cpu_data[i].vpe_id == cpu_data[cpu].vpe_id)) cpu_context(i, mm) = asid_cache(i) = asid; } if (smtc_status & SMTC_TLB_SHARED) evpe(mtflags); else emt(mtflags); local_irq_restore(flags); } /* * Invoked from macros defined in mmu_context.h * which must already have disabled interrupts * and done a DVPE or DMT as appropriate. */ void smtc_flush_tlb_asid(unsigned long asid) { int entry; unsigned long ehi; entry = read_c0_wired(); /* Traverse all non-wired entries */ while (entry < current_cpu_data.tlbsize) { write_c0_index(entry); ehb(); tlb_read(); ehb(); ehi = read_c0_entryhi(); |
4bf42d427 [MIPS] SMTC: Refo... |
1391 |
if ((ehi & ASID_MASK) == asid) { |
41c594ab6 [MIPS] MT: Improv... |
1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 |
/* * Invalidate only entries with specified ASID, * makiing sure all entries differ. */ write_c0_entryhi(CKSEG0 + (entry << (PAGE_SHIFT + 1))); write_c0_entrylo0(0); write_c0_entrylo1(0); mtc0_tlbw_hazard(); tlb_write_indexed(); } entry++; } write_c0_index(PARKED_INDEX); tlbw_use_hazard(); } /* * Support for single-threading cache flush operations. */ |
5868756dc [MIPS] SMTC: Make... |
1411 |
static int halt_state_save[NR_CPUS]; |
41c594ab6 [MIPS] MT: Improv... |
1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 |
/* * To really, really be sure that nothing is being done * by other TCs, halt them all. This code assumes that * a DVPE has already been done, so while their Halted * state is theoretically architecturally unstable, in * practice, it's not going to change while we're looking * at it. */ void smtc_cflush_lockdown(void) { int cpu; for_each_online_cpu(cpu) { if (cpu != smp_processor_id()) { settc(cpu_data[cpu].tc_id); halt_state_save[cpu] = read_tc_c0_tchalt(); write_tc_c0_tchalt(TCHALT_H); } } mips_ihb(); } /* It would be cheating to change the cpu_online states during a flush! */ void smtc_cflush_release(void) { int cpu; /* * Start with a hazard barrier to ensure * that all CACHE ops have played through. */ mips_ihb(); for_each_online_cpu(cpu) { if (cpu != smp_processor_id()) { settc(cpu_data[cpu].tc_id); write_tc_c0_tchalt(halt_state_save[cpu]); } } mips_ihb(); } |