// SPDX-License-Identifier: GPL-2.0+

  /*
   * drivers/net/phy/realtek.c
   *
   * Driver for Realtek PHYs
   *
   * Author: Johnson Leung <r58129@freescale.com>
   *
   * Copyright (c) 2004 Freescale Semiconductor, Inc.

   */

  #include <linux/bitops.h>

  #include <linux/phy.h>

  #include <linux/module.h>

  #define RTL821x_PHYSR				0x11
  #define RTL821x_PHYSR_DUPLEX			BIT(13)
  #define RTL821x_PHYSR_SPEED			GENMASK(15, 14)

  #define RTL821x_INER				0x12
  #define RTL8211B_INER_INIT			0x6400
  #define RTL8211E_INER_LINK_STATUS		BIT(10)
  #define RTL8211F_INER_LINK_STATUS		BIT(4)

  #define RTL821x_INSR				0x13

  #define RTL821x_EXT_PAGE_SELECT			0x1e

  #define RTL821x_PAGE_SELECT			0x1f

  #define RTL8211F_INSR				0x1d

  #define RTL8211F_RX_DELAY			BIT(3)

  #define RTL8211F_TX_DELAY			BIT(8)

  #define RTL8211E_TX_DELAY			BIT(1)
  #define RTL8211E_RX_DELAY			BIT(2)
  #define RTL8211E_MODE_MII_GMII			BIT(3)

  
  #define RTL8201F_ISR				0x1e
  #define RTL8201F_IER				0x13

  #define RTL8366RB_POWER_SAVE			0x15
  #define RTL8366RB_POWER_SAVE_ON			BIT(12)

  #define RTL_SUPPORTS_5000FULL			BIT(14)
  #define RTL_SUPPORTS_2500FULL			BIT(13)
  #define RTL_SUPPORTS_10000FULL			BIT(0)

  #define RTL_ADV_2500FULL			BIT(7)
  #define RTL_LPADV_10000FULL			BIT(11)
  #define RTL_LPADV_5000FULL			BIT(6)
  #define RTL_LPADV_2500FULL			BIT(5)

  #define RTL_GENERIC_PHYID			0x001cc800

  MODULE_DESCRIPTION("Realtek PHY driver");
  MODULE_AUTHOR("Johnson Leung");
  MODULE_LICENSE("GPL");

  static int rtl821x_read_page(struct phy_device *phydev)

  {

  	return __phy_read(phydev, RTL821x_PAGE_SELECT);

  }

  static int rtl821x_write_page(struct phy_device *phydev, int page)

  {

  	return __phy_write(phydev, RTL821x_PAGE_SELECT, page);

  }

  static int rtl8201_ack_interrupt(struct phy_device *phydev)
  {
  	int err;
  
  	err = phy_read(phydev, RTL8201F_ISR);
  
  	return (err < 0) ? err : 0;
  }

  static int rtl821x_ack_interrupt(struct phy_device *phydev)
  {
  	int err;
  
  	err = phy_read(phydev, RTL821x_INSR);
  
  	return (err < 0) ? err : 0;
  }

  static int rtl8211f_ack_interrupt(struct phy_device *phydev)
  {
  	int err;

  	err = phy_read_paged(phydev, 0xa43, RTL8211F_INSR);

  
  	return (err < 0) ? err : 0;
  }

  static int rtl8201_config_intr(struct phy_device *phydev)
  {

  	u16 val;

  
  	if (phydev->interrupts == PHY_INTERRUPT_ENABLED)

  		val = BIT(13) | BIT(12) | BIT(11);

  	else

  		val = 0;

  	return phy_write_paged(phydev, 0x7, RTL8201F_IER, val);

  }

  static int rtl8211b_config_intr(struct phy_device *phydev)

  {
  	int err;
  
  	if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
  		err = phy_write(phydev, RTL821x_INER,

  				RTL8211B_INER_INIT);

  	else
  		err = phy_write(phydev, RTL821x_INER, 0);
  
  	return err;
  }

  static int rtl8211e_config_intr(struct phy_device *phydev)
  {
  	int err;
  
  	if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
  		err = phy_write(phydev, RTL821x_INER,

  				RTL8211E_INER_LINK_STATUS);

  	else
  		err = phy_write(phydev, RTL821x_INER, 0);
  
  	return err;
  }

  static int rtl8211f_config_intr(struct phy_device *phydev)
  {

  	u16 val;

  
  	if (phydev->interrupts == PHY_INTERRUPT_ENABLED)

  		val = RTL8211F_INER_LINK_STATUS;

  	else

  		val = 0;

  	return phy_write_paged(phydev, 0xa42, RTL821x_INER, val);

  }

  static int rtl8211_config_aneg(struct phy_device *phydev)
  {
  	int ret;
  
  	ret = genphy_config_aneg(phydev);
  	if (ret < 0)
  		return ret;
  
  	/* Quirk was copied from vendor driver. Unfortunately it includes no
  	 * description of the magic numbers.
  	 */
  	if (phydev->speed == SPEED_100 && phydev->autoneg == AUTONEG_DISABLE) {
  		phy_write(phydev, 0x17, 0x2138);
  		phy_write(phydev, 0x0e, 0x0260);
  	} else {
  		phy_write(phydev, 0x17, 0x2108);
  		phy_write(phydev, 0x0e, 0x0000);
  	}
  
  	return 0;
  }

  static int rtl8211c_config_init(struct phy_device *phydev)
  {
  	/* RTL8211C has an issue when operating in Gigabit slave mode */

  	return phy_set_bits(phydev, MII_CTRL1000,
  			    CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);

  }

  static int rtl8211f_config_init(struct phy_device *phydev)
  {

  	u16 txdly = 0;
  	u16 rxdly = 0;
  	int ret;

  	/* enable TX-delay for rgmii-{id,txid}, and disable it for rgmii and
  	 * rgmii-rxid. The RX-delay can be enabled by the external RXDLY pin.
  	 */
  	switch (phydev->interface) {

  	case PHY_INTERFACE_MODE_RGMII_ID:
  		rxdly = RTL8211F_RX_DELAY;
  		txdly = RTL8211F_TX_DELAY;
  		break;

  	case PHY_INTERFACE_MODE_RGMII_RXID:

  		rxdly = RTL8211F_RX_DELAY;

  		break;

  	case PHY_INTERFACE_MODE_RGMII_TXID:

  		txdly = RTL8211F_TX_DELAY;

  		break;
  	default: /* the rest of the modes imply leaving delay as is. */
  		return 0;
  	}

  	/* Set green LED for Link, yellow LED for Active */
  	phy_write(phydev, RTL821x_PAGE_SELECT, 0xd04);
  	phy_write(phydev, 0x10, 0x617f);
  	phy_write(phydev, RTL821x_PAGE_SELECT, 0x0);

  	ret = phy_modify_paged(phydev, 0xd08, 0x11, RTL8211F_TX_DELAY, txdly);
  	if (ret < 0) {
  		dev_err(&phydev->mdio.dev, "tx delay set failed
  ");
  		return ret;
  	}
  
  	ret = phy_modify_paged(phydev, 0xd08, 0x15, RTL8211F_RX_DELAY, rxdly);
  	if (ret < 0) {
  		dev_err(&phydev->mdio.dev, "rx delay set failed
  ");
  		return ret;
  	}
  
  	return ret;

  }

  static int rtl8211e_config_init(struct phy_device *phydev)
  {
  	int ret = 0, oldpage;
  	u16 val;
  
  	/* enable TX/RX delay for rgmii-* modes, and disable them for rgmii. */
  	switch (phydev->interface) {
  	case PHY_INTERFACE_MODE_RGMII:
  		val = 0;
  		break;
  	case PHY_INTERFACE_MODE_RGMII_ID:
  		val = RTL8211E_TX_DELAY | RTL8211E_RX_DELAY;
  		break;
  	case PHY_INTERFACE_MODE_RGMII_RXID:
  		val = RTL8211E_RX_DELAY;
  		break;
  	case PHY_INTERFACE_MODE_RGMII_TXID:
  		val = RTL8211E_TX_DELAY;
  		break;
  	default: /* the rest of the modes imply leaving delays as is. */
  		return 0;
  	}
  
  	/* According to a sample driver there is a 0x1c config register on the
  	 * 0xa4 extension page (0x7) layout. It can be used to disable/enable
  	 * the RX/TX delays otherwise controlled by RXDLY/TXDLY pins. It can
  	 * also be used to customize the whole configuration register:
  	 * 8:6 = PHY Address, 5:4 = Auto-Negotiation, 3 = Interface Mode Select,
  	 * 2 = RX Delay, 1 = TX Delay, 0 = SELRGV (see original PHY datasheet
  	 * for details).
  	 */
  	oldpage = phy_select_page(phydev, 0x7);
  	if (oldpage < 0)
  		goto err_restore_page;

  	ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, 0xa4);

  	if (ret)
  		goto err_restore_page;

  	ret = __phy_modify(phydev, 0x1c, RTL8211E_TX_DELAY | RTL8211E_RX_DELAY,
  			   val);

  
  err_restore_page:
  	return phy_restore_page(phydev, oldpage, ret);
  }

  static int rtl8211b_suspend(struct phy_device *phydev)
  {
  	phy_write(phydev, MII_MMD_DATA, BIT(9));
  
  	return genphy_suspend(phydev);
  }
  
  static int rtl8211b_resume(struct phy_device *phydev)
  {
  	phy_write(phydev, MII_MMD_DATA, 0);
  
  	return genphy_resume(phydev);
  }

  static int rtl8366rb_config_init(struct phy_device *phydev)
  {
  	int ret;

  	ret = phy_set_bits(phydev, RTL8366RB_POWER_SAVE,
  			   RTL8366RB_POWER_SAVE_ON);
  	if (ret) {
  		dev_err(&phydev->mdio.dev,
  			"error enabling power management
  ");
  	}
  
  	return ret;
  }

  static int rtlgen_read_mmd(struct phy_device *phydev, int devnum, u16 regnum)
  {
  	int ret;
  
  	if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE) {
  		rtl821x_write_page(phydev, 0xa5c);
  		ret = __phy_read(phydev, 0x12);
  		rtl821x_write_page(phydev, 0);
  	} else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) {
  		rtl821x_write_page(phydev, 0xa5d);
  		ret = __phy_read(phydev, 0x10);
  		rtl821x_write_page(phydev, 0);
  	} else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE) {
  		rtl821x_write_page(phydev, 0xa5d);
  		ret = __phy_read(phydev, 0x11);
  		rtl821x_write_page(phydev, 0);
  	} else {
  		ret = -EOPNOTSUPP;
  	}
  
  	return ret;
  }
  
  static int rtlgen_write_mmd(struct phy_device *phydev, int devnum, u16 regnum,
  			    u16 val)
  {
  	int ret;
  
  	if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) {
  		rtl821x_write_page(phydev, 0xa5d);
  		ret = __phy_write(phydev, 0x10, val);
  		rtl821x_write_page(phydev, 0);
  	} else {
  		ret = -EOPNOTSUPP;
  	}
  
  	return ret;
  }

  static int rtl8125_read_mmd(struct phy_device *phydev, int devnum, u16 regnum)
  {
  	int ret = rtlgen_read_mmd(phydev, devnum, regnum);
  
  	if (ret != -EOPNOTSUPP)
  		return ret;
  
  	if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE2) {
  		rtl821x_write_page(phydev, 0xa6e);
  		ret = __phy_read(phydev, 0x16);
  		rtl821x_write_page(phydev, 0);
  	} else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) {
  		rtl821x_write_page(phydev, 0xa6d);
  		ret = __phy_read(phydev, 0x12);
  		rtl821x_write_page(phydev, 0);
  	} else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE2) {
  		rtl821x_write_page(phydev, 0xa6d);
  		ret = __phy_read(phydev, 0x10);
  		rtl821x_write_page(phydev, 0);
  	}
  
  	return ret;
  }
  
  static int rtl8125_write_mmd(struct phy_device *phydev, int devnum, u16 regnum,
  			     u16 val)
  {
  	int ret = rtlgen_write_mmd(phydev, devnum, regnum, val);
  
  	if (ret != -EOPNOTSUPP)
  		return ret;
  
  	if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) {
  		rtl821x_write_page(phydev, 0xa6d);
  		ret = __phy_write(phydev, 0x12, val);
  		rtl821x_write_page(phydev, 0);
  	}
  
  	return ret;
  }

  static int rtl8125_get_features(struct phy_device *phydev)
  {

  	int val;
  
  	val = phy_read_paged(phydev, 0xa61, 0x13);
  	if (val < 0)
  		return val;
  
  	linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
  			 phydev->supported, val & RTL_SUPPORTS_2500FULL);
  	linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
  			 phydev->supported, val & RTL_SUPPORTS_5000FULL);
  	linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
  			 phydev->supported, val & RTL_SUPPORTS_10000FULL);

  
  	return genphy_read_abilities(phydev);
  }
  
  static int rtl8125_config_aneg(struct phy_device *phydev)
  {
  	int ret = 0;
  
  	if (phydev->autoneg == AUTONEG_ENABLE) {
  		u16 adv2500 = 0;
  
  		if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
  				      phydev->advertising))
  			adv2500 = RTL_ADV_2500FULL;
  
  		ret = phy_modify_paged_changed(phydev, 0xa5d, 0x12,
  					       RTL_ADV_2500FULL, adv2500);
  		if (ret < 0)
  			return ret;
  	}
  
  	return __genphy_config_aneg(phydev, ret);
  }
  
  static int rtl8125_read_status(struct phy_device *phydev)
  {
  	if (phydev->autoneg == AUTONEG_ENABLE) {
  		int lpadv = phy_read_paged(phydev, 0xa5d, 0x13);
  
  		if (lpadv < 0)
  			return lpadv;
  
  		linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
  			phydev->lp_advertising, lpadv & RTL_LPADV_10000FULL);
  		linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
  			phydev->lp_advertising, lpadv & RTL_LPADV_5000FULL);
  		linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
  			phydev->lp_advertising, lpadv & RTL_LPADV_2500FULL);
  	}
  
  	return genphy_read_status(phydev);
  }

  static bool rtlgen_supports_2_5gbps(struct phy_device *phydev)
  {
  	int val;
  
  	phy_write(phydev, RTL821x_PAGE_SELECT, 0xa61);
  	val = phy_read(phydev, 0x13);
  	phy_write(phydev, RTL821x_PAGE_SELECT, 0);
  
  	return val >= 0 && val & RTL_SUPPORTS_2500FULL;
  }
  
  static int rtlgen_match_phy_device(struct phy_device *phydev)
  {
  	return phydev->phy_id == RTL_GENERIC_PHYID &&
  	       !rtlgen_supports_2_5gbps(phydev);
  }
  
  static int rtl8125_match_phy_device(struct phy_device *phydev)
  {
  	return phydev->phy_id == RTL_GENERIC_PHYID &&
  	       rtlgen_supports_2_5gbps(phydev);
  }

  static struct phy_driver realtek_drvs[] = {
  	{

  		PHY_ID_MATCH_EXACT(0x00008201),

  		.name           = "RTL8201CP Ethernet",

  	}, {

  		PHY_ID_MATCH_EXACT(0x001cc816),

  		.name		= "RTL8201F Fast Ethernet",

  		.ack_interrupt	= &rtl8201_ack_interrupt,
  		.config_intr	= &rtl8201_config_intr,
  		.suspend	= genphy_suspend,
  		.resume		= genphy_resume,

  		.read_page	= rtl821x_read_page,
  		.write_page	= rtl821x_write_page,

  	}, {

  		PHY_ID_MATCH_EXACT(0x001cc910),

  		.name		= "RTL8211 Gigabit Ethernet",

  		.config_aneg	= rtl8211_config_aneg,
  		.read_mmd	= &genphy_read_mmd_unsupported,
  		.write_mmd	= &genphy_write_mmd_unsupported,

  		.read_page	= rtl821x_read_page,
  		.write_page	= rtl821x_write_page,

  	}, {

  		PHY_ID_MATCH_EXACT(0x001cc912),

  		.name		= "RTL8211B Gigabit Ethernet",

  		.ack_interrupt	= &rtl821x_ack_interrupt,
  		.config_intr	= &rtl8211b_config_intr,

  		.read_mmd	= &genphy_read_mmd_unsupported,
  		.write_mmd	= &genphy_write_mmd_unsupported,

  		.suspend	= rtl8211b_suspend,
  		.resume		= rtl8211b_resume,

  		.read_page	= rtl821x_read_page,
  		.write_page	= rtl821x_write_page,

  	}, {

  		PHY_ID_MATCH_EXACT(0x001cc913),

  		.name		= "RTL8211C Gigabit Ethernet",

  		.config_init	= rtl8211c_config_init,
  		.read_mmd	= &genphy_read_mmd_unsupported,
  		.write_mmd	= &genphy_write_mmd_unsupported,

  		.read_page	= rtl821x_read_page,
  		.write_page	= rtl821x_write_page,

  	}, {

  		PHY_ID_MATCH_EXACT(0x001cc914),

  		.name		= "RTL8211DN Gigabit Ethernet",

  		.ack_interrupt	= rtl821x_ack_interrupt,
  		.config_intr	= rtl8211e_config_intr,
  		.suspend	= genphy_suspend,
  		.resume		= genphy_resume,

  		.read_page	= rtl821x_read_page,
  		.write_page	= rtl821x_write_page,

  	}, {

  		PHY_ID_MATCH_EXACT(0x001cc915),

  		.name		= "RTL8211E Gigabit Ethernet",

  		.config_init	= &rtl8211e_config_init,

  		.ack_interrupt	= &rtl821x_ack_interrupt,
  		.config_intr	= &rtl8211e_config_intr,
  		.suspend	= genphy_suspend,
  		.resume		= genphy_resume,

  		.read_page	= rtl821x_read_page,
  		.write_page	= rtl821x_write_page,

  	}, {

  		PHY_ID_MATCH_EXACT(0x001cc916),

  		.name		= "RTL8211F Gigabit Ethernet",

  		.config_init	= &rtl8211f_config_init,

  		.ack_interrupt	= &rtl8211f_ack_interrupt,
  		.config_intr	= &rtl8211f_config_intr,
  		.suspend	= genphy_suspend,
  		.resume		= genphy_resume,

  		.read_page	= rtl821x_read_page,
  		.write_page	= rtl821x_write_page,

  	}, {

  		.name		= "Generic FE-GE Realtek PHY",
  		.match_phy_device = rtlgen_match_phy_device,

  		.suspend	= genphy_suspend,
  		.resume		= genphy_resume,
  		.read_page	= rtl821x_read_page,
  		.write_page	= rtl821x_write_page,

  		.read_mmd	= rtlgen_read_mmd,
  		.write_mmd	= rtlgen_write_mmd,

  	}, {

  		.name		= "RTL8125 2.5Gbps internal",

  		.match_phy_device = rtl8125_match_phy_device,

  		.get_features	= rtl8125_get_features,
  		.config_aneg	= rtl8125_config_aneg,
  		.read_status	= rtl8125_read_status,
  		.suspend	= genphy_suspend,
  		.resume		= genphy_resume,
  		.read_page	= rtl821x_read_page,
  		.write_page	= rtl821x_write_page,

  		.read_mmd	= rtl8125_read_mmd,
  		.write_mmd	= rtl8125_write_mmd,

  	}, {

  		PHY_ID_MATCH_EXACT(0x001cc961),

  		.name		= "RTL8366RB Gigabit Ethernet",

  		.config_init	= &rtl8366rb_config_init,

  		/* These interrupts are handled by the irq controller
  		 * embedded inside the RTL8366RB, they get unmasked when the
  		 * irq is requested and ACKed by reading the status register,
  		 * which is done by the irqchip code.
  		 */
  		.ack_interrupt	= genphy_no_ack_interrupt,
  		.config_intr	= genphy_no_config_intr,

  		.suspend	= genphy_suspend,
  		.resume		= genphy_resume,

  	},

  };

  module_phy_driver(realtek_drvs);

  static const struct mdio_device_id __maybe_unused realtek_tbl[] = {

  	{ PHY_ID_MATCH_VENDOR(0x001cc800) },

  	{ }
  };
  
  MODULE_DEVICE_TABLE(mdio, realtek_tbl);