01 Jul, 2022
1 commit
02 Jan, 2020
1 commit
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Add RX delay enable support for RTL8211F PHY.
Reviewed-by: Richard Zhu
Signed-off-by: Fugang Duan
20 Aug, 2019
1 commit
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Emulate the 802.3bz MMD EEE registers for 2.5Gbps EEE on RTL8125.
Signed-off-by: Heiner Kallweit
Signed-off-by: David S. Miller
16 Aug, 2019
1 commit
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EEE-related registers on newer integrated PHY's have the standard
layout, but are accessible not via MMD but via vendor-specific
registers. Emulating the standard MMD registers allows to use the
generic functions for EEE control.Signed-off-by: Heiner Kallweit
Reviewed-by: Florian Fainelli
Signed-off-by: David S. Miller
15 Aug, 2019
1 commit
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Realtek provided information on how the new NIC-integrated PHY's
expose whether they support 2.5G/5G/10G. This allows to automatically
differentiate 1Gbps and 2.5Gbps PHY's, and therefore allows to
remove the fake PHY ID mechanism for RTL8125.
So far RTL8125 supports 2.5Gbps only, but register layout for faster
modes has been defined already, so let's use this information to be
future-proof.Signed-off-by: Heiner Kallweit
Signed-off-by: David S. Miller
12 Aug, 2019
1 commit
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This adds support for the integrated 2.5Gbps PHY in Realtek RTL8125.
Advertisement of 2.5Gbps mode is done via a vendor-specific register.
Same applies to reading NBase-T link partner advertisement.
Unfortunately this 2.5Gbps PHY shares the PHY ID with the integrated
1Gbps PHY's in other Realtek network chips and so far no method is
known to differentiate them. As a workaround use a dedicated fake PHY ID
that is set by the network driver by intercepting the MDIO PHY ID read.v2:
- Create dedicated PHY driver and use a fake PHY ID that is injected by
the network driver. Suggested by Andrew Lunn.Signed-off-by: Heiner Kallweit
Reviewed-by: Andrew Lunn
Signed-off-by: David S. Miller
14 May, 2019
1 commit
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After calling phy_select_page() and until calling phy_restore_page(),
the mutex 'mdio_lock' is already locked, so the driver should use
non-locked version of phy functions. Or there will be a deadlock with
'mdio_lock'.This replaces phy functions called from rtl8211e_config_init() to avoid
the deadlock issue.Fixes: f81dadbcf7fd ("net: phy: realtek: Add rtl8211e rx/tx delays config")
Signed-off-by: Kunihiko Hayashi
Reviewed-by: Andrew Lunn
Signed-off-by: David S. Miller
12 May, 2019
1 commit
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When adding missing callbacks I missed that one had them set already.
Interesting that the compiler didn't complain.Fixes: daf3ddbe11a2 ("net: phy: realtek: add missing page operations")
Signed-off-by: Heiner Kallweit
Signed-off-by: David S. Miller
11 May, 2019
1 commit
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Add missing page operation callbacks to few Realtek drivers.
This also fixes a NPE after the referenced commit added code to the
RTL8211E driver that uses phy_select_page().Fixes: f81dadbcf7fd ("net: phy: realtek: Add rtl8211e rx/tx delays config")
Signed-off-by: Heiner Kallweit
Reviewed-by: Florian Fainelli
Reported-by: Vicente Bergas
Signed-off-by: David S. Miller
09 May, 2019
2 commits
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It's prone to problems if delay is cleared out for other than RGMII
modes. So lets set/clear the TX-delay in the config register only
if actually RGMII-like interface mode is requested. This only
concerns rtl8211f chips.Signed-off-by: Serge Semin
Signed-off-by: David S. Miller -
There are two chip pins named TXDLY and RXDLY which actually adds the 2ns
delays to TXC and RXC for TXD/RXD latching. Alas this is the only
documented info regarding the RGMII timing control configurations the PHY
provides. It turns out the same settings can be setup via MDIO registers
hidden in the extension pages layout. Particularly the extension page 0xa4
provides a register 0x1c, which bits 1 and 2 control the described delays.
They are used to implement the "rgmii-{id,rxid,txid}" phy-mode.The hidden RGMII configs register utilization was found in the rtl8211e
U-boot driver:
https://elixir.bootlin.com/u-boot/v2019.01/source/drivers/net/phy/realtek.c#L99There is also a freebsd-folks discussion regarding this register:
https://reviews.freebsd.org/D13591It confirms that the register bits field must control the so called
configuration pins described in the table 12-13 of the official PHY
datasheet:
8:6 = PHY Address
5:4 = Auto-Negotiation
3 = Interface Mode Select
2 = RX Delay
1 = TX Delay
0 = SELRGVReviewed-by: Andrew Lunn
Signed-off-by: Serge Semin
Signed-off-by: David S. Miller
05 Apr, 2019
1 commit
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Now that phylib uses genphy_read_abilities() as fallback, we don't have
to set callback get_features any longer.Signed-off-by: Heiner Kallweit
Reviewed-by: Andrew Lunn
Signed-off-by: David S. Miller
03 Apr, 2019
1 commit
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Use new function genphy_read_abilities(). This allows to remove all
calls to genphy_config_init().Signed-off-by: Heiner Kallweit
Signed-off-by: David S. Miller
25 Feb, 2019
1 commit
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Three conflicts, one of which, for marvell10g.c is non-trivial and
requires some follow-up from Heiner or someone else.The issue is that Heiner converted the marvell10g driver over to
use the generic c45 code as much as possible.However, in 'net' a bug fix appeared which makes sure that a new
local mask (MDIO_AN_10GBT_CTRL_ADV_NBT_MASK) with value 0x01e0
is cleared.Signed-off-by: David S. Miller
24 Feb, 2019
1 commit
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This fixes a regression introduced by
commit 0d2e778e38e0ddffab4bb2b0e9ed2ad5165c4bf7
"net: phy: replace PHY_HAS_INTERRUPT with a check for
config_intr and ack_interrupt".This assumes that a PHY cannot trigger interrupt unless
it has .config_intr() or .ack_interrupt() implemented.
A later patch makes the code assume both need to be
implemented for interrupts to be present.But this PHY (which is inside a DSA) will happily
fire interrupts without either callback.Implement dummy callbacks for .config_intr() and
.ack_interrupt() in the phy header to fix this.Tested on the RTL8366RB on D-Link DIR-685.
Fixes: 0d2e778e38e0 ("net: phy: replace PHY_HAS_INTERRUPT with a check for config_intr and ack_interrupt")
Cc: Heiner Kallweit
Signed-off-by: Linus Walleij
Reviewed-by: Andrew Lunn
Signed-off-by: David S. Miller
04 Feb, 2019
1 commit
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The integrated PHY's of later RTL8168 network chips report the generic
PHYID 0x001cc800 (Realtek OUI, model and revision number both set to
zero) and therefore currently the genphy driver is used.To be able to use the paged version of e.g. phy_write() we need a
PHY driver with the read_page and write_page callbacks implemented.
So basically make a copy of the genphy driver, just with the
read_page and write_page callbacks being set.Signed-off-by: Heiner Kallweit
Signed-off-by: David S. Miller
23 Jan, 2019
1 commit
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Where the license text and the MODULE_LICENSE() value agree, convert
to using an SPDX header, removing the license text.Signed-off-by: Andrew Lunn
Signed-off-by: David S. Miller
12 Nov, 2018
2 commits
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Use new macros for PHYID matching to avoid boilerplate code.
Signed-off-by: Heiner Kallweit
Signed-off-by: David S. Miller -
Now that flag PHY_HAS_INTERRUPT has been replaced with a check for
callbacks config_intr and ack_interrupt, we can remove setting this
flag from all driver configs.
Last but not least remove flag PHY_HAS_INTERRUPT completely.Signed-off-by: Heiner Kallweit
Reviewed-by: Andrew Lunn
Signed-off-by: David S. Miller
08 Nov, 2018
1 commit
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Instead of listing every single PHYID, load the driver for every PHYID
with a Realtek OUI, independent of model number and revision.This patch also improves two further aspects:
- constify realtek_tbl[]
- the mask should have been 0xffffffff instead of 0x001fffff so far,
by masking out some bits a PHY from another vendor could have been
matchedSigned-off-by: Heiner Kallweit
Signed-off-by: David S. Miller
05 Nov, 2018
1 commit
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Since 4.19 the following error in sysfs has appeared when using the
r8169 NIC driver:$cd /sys/module/realtek/drivers
$ls -l
ls: cannot access 'mdio_bus:RTL8201F 10/100Mbps Ethernet': No such file or directory
[..garbled dir entries follow..]Apparently the forward slash in "10/100Mbps Ethernet" is interpreted
as directory separator that leads nowhere, and was introduced in commit
513588dd44b ("net: phy: realtek: add RTL8201F phy-id and functions").Fix this by removing the offending slash in the driver name.
Other drivers in net/phy seem to have the same problem, but I cannot
test/verify them.Fixes: 513588dd44b ("net: phy: realtek: add RTL8201F phy-id and functions")
Signed-off-by: Holger Hoffstätte
Reviewed-by: Andrew Lunn
Signed-off-by: David S. Miller
18 Jul, 2018
1 commit
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The RTL8366RB is an ASIC with five internal PHYs for
LAN0..LAN3 and WAN. The PHYs are spawn off the main
device so they can be handled in a distributed manner
by the Realtek PHY driver. All that is really needed
is the power save feature enablement and letting the
PHY driver core pick up the IRQ from the switch chip.Cc: Antti Seppälä
Cc: Roman Yeryomin
Cc: Colin Leitner
Cc: Gabor Juhos
Cc: Florian Fainelli
Signed-off-by: Linus Walleij
Signed-off-by: David S. Miller
17 Jul, 2018
1 commit
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Add missing entry for RTL8211C to mdio_device_id table.
Signed-off-by: Heiner Kallweit
Fixes: cf87915cb9f8 ("net: phy: realtek: add support for RTL8211C")
Signed-off-by: David S. Miller
02 Jul, 2018
2 commits
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RTL8211C has an issue when operating in Gigabit slave mode, therefore
genphy driver can't be used. See also this U-boot change.
https://lists.denx.de/pipermail/u-boot/2016-March/249712.htmlAdd a PHY driver for this chip with the quirk to force Gigabit master
mode. As a note: This will make it impossible to connect two network
ports directly which both are driven by a RTl8211C.Signed-off-by: Heiner Kallweit
Signed-off-by: David S. Miller -
When adding support for RTL8211 I forgot to update the mdio_device_id
table.Signed-off-by: Heiner Kallweit
Fixes: d241d4aac93f ("net: phy: realtek: add support for RTL8211")
Signed-off-by: David S. Miller
30 Jun, 2018
1 commit
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In preparation of adding phylib support to the r8169 driver we need
PHY drivers for all chip-internal PHY types. Fortunately almost all
of them are either supported by the Realtek PHY driver already or work
with the genphy driver.
Still missing is support for the PHY of RTL8169s, it requires a quirk
to properly support 100Mbit-fixed mode. The quirk was copied from
r8169 driver which copied it from the vendor driver.
Based on the PHYID the internal PHY seems to be a RTL8211.Signed-off-by: Heiner Kallweit
Signed-off-by: David S. Miller
29 May, 2018
1 commit
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Add RTL8211B suspend / resume callbacks.
Signed-off-by: Heiner Kallweit
Signed-off-by: David S. Miller
22 Mar, 2018
1 commit
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The Ethernet on mpc8315erdb is broken since commit b6b5e8a69118
("gianfar: Disable EEE autoneg by default"). The reason is that
even though the rtl8211b doesn't support the MMD extended registers
access, it does return some random values if we trying to access
the MMD register via indirect method. This makes it seem that the
EEE is supported by this phy device. And the subsequent writing to
the MMD registers does cause the phy malfunction. So use the dummy
stubs for the MMD register access to fix this issue.Fixes: b6b5e8a69118 ("gianfar: Disable EEE autoneg by default")
Signed-off-by: Kevin Hao
Signed-off-by: David S. Miller
17 Jan, 2018
1 commit
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Make use of the new helpers for paged register access.
Signed-off-by: Heiner Kallweit
Signed-off-by: David S. Miller
03 Dec, 2017
5 commits
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Realtek PHYs implement the concept of so-called "extension pages". The
reason for this is probably because these PHYs expose more registers
than available in the standard address range.
After all read/write operations on such a page are done the driver
should switch back to page 0 where the standard MII registers (such as
MII_BMCR) are available.When referring to such a register the datasheets of RTL8211E and
RTL8211F always specify:
- the page / "ext. page" which has to be written to RTL821x_PAGE_SELECT
- an address (sometimes also called reg)These new utility functions make the existing code easier to read since
it removes some duplication (switching back to page 0 is done within the
new helpers for example).No functional changes are intended.
Signed-off-by: Martin Blumenstingl
Reviewed-by: Andrew Lunn
Signed-off-by: David S. Miller -
This simply makes the code easier to read. No functional changes.
Signed-off-by: Martin Blumenstingl
Reviewed-by: Andrew Lunn
Signed-off-by: David S. Miller -
This simply moves all register bit #defines which describe the (PHY
specific) bits in the RTL821x_INER right below the RTL821x_INER register
definition. This makes it easier to spot which registers and bits belong
together.
No functional changes.Signed-off-by: Martin Blumenstingl
Reviewed-by: Andrew Lunn
Signed-off-by: David S. Miller -
This macro is only used by the RTL8211B code. RTL8211E and RTL8211F both
use other bits to initialize the RTL821x_INER register.
No functional changes.Signed-off-by: Martin Blumenstingl
Reviewed-by: Andrew Lunn
Signed-off-by: David S. Miller -
This makes it easier to compare the #defines with the datasheets.
No functional changes.Signed-off-by: Martin Blumenstingl
Reviewed-by: Andrew Lunn
Signed-off-by: David S. Miller
02 Dec, 2017
1 commit
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Remove generic settings for callbacks config_aneg and read_status
from drivers.Signed-off-by: Heiner Kallweit
Reviewed-by: Florian Fainelli
Signed-off-by: David S. Miller
14 Nov, 2017
1 commit
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After commit b94d22d94ad22 "ARM64: dts: meson-gx: add external PHY
interrupt on some platforms" ethernet stopped working on my Odroid-C2
which has a RTL8211F phy.It turned out that no interrupts were triggered. Further analysis
showed the register INER can't be altered on page 0.
Because register INSR needs to be accessed via page 0xa43 I assumed
that register INER needs to be accessed via some page too.
Some brute force check resulted in page 0xa42 being the right one.With this patch the phy is working properly in interrupt mode.
Fixes: 3447cf2e9a11 ("net/phy: Add support for Realtek RTL8211F")
Signed-off-by: Heiner Kallweit
Tested-by: Jerome Brunet
Signed-off-by: David S. Miller
19 Sep, 2017
2 commits
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Add RTL8201F phy-id and the related functions to the driver.
The original patch is as follows:
https://patchwork.kernel.org/patch/2538341/Signed-off-by: Jongsung Kim
Signed-off-by: Jassi Brar
Signed-off-by: Kunihiko Hayashi
Reviewed-by: Andrew Lunn
Reviewed-by: Florian Fainelli
Signed-off-by: David S. Miller -
This renames the definition of page select register from
RTL8211F_PAGE_SELECT to RTL821x_PAGE_SELECT to use it across models.Signed-off-by: Kunihiko Hayashi
Reviewed-by: Andrew Lunn
Signed-off-by: David S. Miller
29 Nov, 2016
1 commit
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The old logic always enabled the TX-delay when the phy-mode was set to
PHY_INTERFACE_MODE_RGMII. There are dedicated phy-modes which tell the
PHY driver to enable the RX and/or TX delays:
- PHY_INTERFACE_MODE_RGMII should disable the RX and TX delay in the
PHY (if required, the MAC should add the delays in this case)
- PHY_INTERFACE_MODE_RGMII_ID should enable RX and TX delay in the PHY
- PHY_INTERFACE_MODE_RGMII_TXID should enable the TX delay in the PHY
- PHY_INTERFACE_MODE_RGMII_RXID should enable the RX delay in the PHY
(currently not supported by RTL8211F)With this patch we enable the TX delay for PHY_INTERFACE_MODE_RGMII_ID
and PHY_INTERFACE_MODE_RGMII_TXID.
Additionally we now explicity disable the TX-delay, which seems to be
enabled automatically after a hard-reset of the PHY (by triggering it's
reset pin) to get a consistent state (as defined by the phy-mode).This fixes a compatibility problem with some SoCs where the TX-delay was
also added by the MAC. With the TX-delay being applied twice the TX
clock was off and TX traffic was broken or very slow (
Reviewed-by: Florian Fainelli
Signed-off-by: David S. Miller
08 Jan, 2016
1 commit
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Rather than have each driver set the driver owner field, do it once in
the core code. This will also help with later changes, when the device
structure will move.Signed-off-by: Andrew Lunn
Reviewed-by: Florian Fainelli
Signed-off-by: David S. Miller