Blame view
drivers/edac/ie31200_edac.c
16.1 KB
7ee40b897 ie31200_edac: Int... |
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 |
/* * Intel E3-1200 * Copyright (C) 2014 Jason Baron <jbaron@akamai.com> * * Support for the E3-1200 processor family. Heavily based on previous * Intel EDAC drivers. * * Since the DRAM controller is on the cpu chip, we can use its PCI device * id to identify these processors. * * PCI DRAM controller device ids (Taken from The PCI ID Repository - http://pci-ids.ucw.cz/) * * 0108: Xeon E3-1200 Processor Family DRAM Controller * 010c: Xeon E3-1200/2nd Generation Core Processor Family DRAM Controller * 0150: Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller * 0158: Xeon E3-1200 v2/Ivy Bridge DRAM Controller * 015c: Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller * 0c04: Xeon E3-1200 v3/4th Gen Core Processor DRAM Controller * 0c08: Xeon E3-1200 v3 Processor DRAM Controller |
953dee9bb EDAC, ie31200_eda... |
20 |
* 1918: Xeon E3-1200 v5 Skylake Host Bridge/DRAM Registers |
7ee40b897 ie31200_edac: Int... |
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 |
* * Based on Intel specification: * http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-e3-1200v3-vol-2-datasheet.pdf * http://www.intel.com/content/www/us/en/processors/xeon/xeon-e3-1200-family-vol-2-datasheet.html * * According to the above datasheet (p.16): * " * 6. Software must not access B0/D0/F0 32-bit memory-mapped registers with * requests that cross a DW boundary. * " * * Thus, we make use of the explicit: lo_hi_readq(), which breaks the readq into * 2 readl() calls. This restriction may be lifted in subsequent chip releases, * but lo_hi_readq() ensures that we are safe across all e3-1200 processors. */ #include <linux/module.h> #include <linux/init.h> #include <linux/pci.h> #include <linux/pci_ids.h> #include <linux/edac.h> |
2f8e2c877 move io-64-nonato... |
42 |
#include <linux/io-64-nonatomic-lo-hi.h> |
78d88e8a3 edac: rename edac... |
43 |
#include "edac_module.h" |
7ee40b897 ie31200_edac: Int... |
44 45 46 47 48 49 50 51 52 53 54 55 56 57 |
#define IE31200_REVISION "1.0" #define EDAC_MOD_STR "ie31200_edac" #define ie31200_printk(level, fmt, arg...) \ edac_printk(level, "ie31200", fmt, ##arg) #define PCI_DEVICE_ID_INTEL_IE31200_HB_1 0x0108 #define PCI_DEVICE_ID_INTEL_IE31200_HB_2 0x010c #define PCI_DEVICE_ID_INTEL_IE31200_HB_3 0x0150 #define PCI_DEVICE_ID_INTEL_IE31200_HB_4 0x0158 #define PCI_DEVICE_ID_INTEL_IE31200_HB_5 0x015c #define PCI_DEVICE_ID_INTEL_IE31200_HB_6 0x0c04 #define PCI_DEVICE_ID_INTEL_IE31200_HB_7 0x0c08 |
953dee9bb EDAC, ie31200_eda... |
58 |
#define PCI_DEVICE_ID_INTEL_IE31200_HB_8 0x1918 |
7ee40b897 ie31200_edac: Int... |
59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 |
#define IE31200_DIMMS 4 #define IE31200_RANKS 8 #define IE31200_RANKS_PER_CHANNEL 4 #define IE31200_DIMMS_PER_CHANNEL 2 #define IE31200_CHANNELS 2 /* Intel IE31200 register addresses - device 0 function 0 - DRAM Controller */ #define IE31200_MCHBAR_LOW 0x48 #define IE31200_MCHBAR_HIGH 0x4c #define IE31200_MCHBAR_MASK GENMASK_ULL(38, 15) #define IE31200_MMR_WINDOW_SIZE BIT(15) /* * Error Status Register (16b) * * 15 reserved * 14 Isochronous TBWRR Run Behind FIFO Full * (ITCV) * 13 Isochronous TBWRR Run Behind FIFO Put * (ITSTV) * 12 reserved * 11 MCH Thermal Sensor Event * for SMI/SCI/SERR (GTSE) * 10 reserved * 9 LOCK to non-DRAM Memory Flag (LCKF) * 8 reserved * 7 DRAM Throttle Flag (DTF) * 6:2 reserved * 1 Multi-bit DRAM ECC Error Flag (DMERR) * 0 Single-bit DRAM ECC Error Flag (DSERR) */ #define IE31200_ERRSTS 0xc8 #define IE31200_ERRSTS_UE BIT(1) #define IE31200_ERRSTS_CE BIT(0) #define IE31200_ERRSTS_BITS (IE31200_ERRSTS_UE | IE31200_ERRSTS_CE) /* * Channel 0 ECC Error Log (64b) * * 63:48 Error Column Address (ERRCOL) * 47:32 Error Row Address (ERRROW) * 31:29 Error Bank Address (ERRBANK) * 28:27 Error Rank Address (ERRRANK) * 26:24 reserved * 23:16 Error Syndrome (ERRSYND) * 15: 2 reserved * 1 Multiple Bit Error Status (MERRSTS) * 0 Correctable Error Status (CERRSTS) */ |
953dee9bb EDAC, ie31200_eda... |
109 |
|
7ee40b897 ie31200_edac: Int... |
110 111 |
#define IE31200_C0ECCERRLOG 0x40c8 #define IE31200_C1ECCERRLOG 0x44c8 |
953dee9bb EDAC, ie31200_eda... |
112 113 |
#define IE31200_C0ECCERRLOG_SKL 0x4048 #define IE31200_C1ECCERRLOG_SKL 0x4448 |
7ee40b897 ie31200_edac: Int... |
114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 |
#define IE31200_ECCERRLOG_CE BIT(0) #define IE31200_ECCERRLOG_UE BIT(1) #define IE31200_ECCERRLOG_RANK_BITS GENMASK_ULL(28, 27) #define IE31200_ECCERRLOG_RANK_SHIFT 27 #define IE31200_ECCERRLOG_SYNDROME_BITS GENMASK_ULL(23, 16) #define IE31200_ECCERRLOG_SYNDROME_SHIFT 16 #define IE31200_ECCERRLOG_SYNDROME(log) \ ((log & IE31200_ECCERRLOG_SYNDROME_BITS) >> \ IE31200_ECCERRLOG_SYNDROME_SHIFT) #define IE31200_CAPID0 0xe4 #define IE31200_CAPID0_PDCD BIT(4) #define IE31200_CAPID0_DDPCD BIT(6) #define IE31200_CAPID0_ECC BIT(1) |
953dee9bb EDAC, ie31200_eda... |
129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 |
#define IE31200_MAD_DIMM_0_OFFSET 0x5004 #define IE31200_MAD_DIMM_0_OFFSET_SKL 0x500C #define IE31200_MAD_DIMM_SIZE GENMASK_ULL(7, 0) #define IE31200_MAD_DIMM_A_RANK BIT(17) #define IE31200_MAD_DIMM_A_RANK_SHIFT 17 #define IE31200_MAD_DIMM_A_RANK_SKL BIT(10) #define IE31200_MAD_DIMM_A_RANK_SKL_SHIFT 10 #define IE31200_MAD_DIMM_A_WIDTH BIT(19) #define IE31200_MAD_DIMM_A_WIDTH_SHIFT 19 #define IE31200_MAD_DIMM_A_WIDTH_SKL GENMASK_ULL(9, 8) #define IE31200_MAD_DIMM_A_WIDTH_SKL_SHIFT 8 /* Skylake reports 1GB increments, everything else is 256MB */ #define IE31200_PAGES(n, skl) \ (n << (28 + (2 * skl) - PAGE_SHIFT)) |
7ee40b897 ie31200_edac: Int... |
144 145 146 147 148 |
static int nr_channels; struct ie31200_priv { void __iomem *window; |
953dee9bb EDAC, ie31200_eda... |
149 150 |
void __iomem *c0errlog; void __iomem *c1errlog; |
7ee40b897 ie31200_edac: Int... |
151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 |
}; enum ie31200_chips { IE31200 = 0, }; struct ie31200_dev_info { const char *ctl_name; }; struct ie31200_error_info { u16 errsts; u16 errsts2; u64 eccerrlog[IE31200_CHANNELS]; }; static const struct ie31200_dev_info ie31200_devs[] = { [IE31200] = { .ctl_name = "IE31200" }, }; struct dimm_data { |
953dee9bb EDAC, ie31200_eda... |
174 |
u8 size; /* in multiples of 256MB, except Skylake is 1GB */ |
7ee40b897 ie31200_edac: Int... |
175 |
u8 dual_rank : 1, |
953dee9bb EDAC, ie31200_eda... |
176 |
x16_width : 2; /* 0 means x8 width */ |
7ee40b897 ie31200_edac: Int... |
177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 |
}; static int how_many_channels(struct pci_dev *pdev) { int n_channels; unsigned char capid0_2b; /* 2nd byte of CAPID0 */ pci_read_config_byte(pdev, IE31200_CAPID0 + 1, &capid0_2b); /* check PDCD: Dual Channel Disable */ if (capid0_2b & IE31200_CAPID0_PDCD) { edac_dbg(0, "In single channel mode "); n_channels = 1; } else { edac_dbg(0, "In dual channel mode "); n_channels = 2; } /* check DDPCD - check if both channels are filled */ if (capid0_2b & IE31200_CAPID0_DDPCD) edac_dbg(0, "2 DIMMS per channel disabled "); else edac_dbg(0, "2 DIMMS per channel enabled "); return n_channels; } static bool ecc_capable(struct pci_dev *pdev) { unsigned char capid0_4b; /* 4th byte of CAPID0 */ pci_read_config_byte(pdev, IE31200_CAPID0 + 3, &capid0_4b); if (capid0_4b & IE31200_CAPID0_ECC) return false; return true; } |
953dee9bb EDAC, ie31200_eda... |
217 |
static int eccerrlog_row(u64 log) |
7ee40b897 ie31200_edac: Int... |
218 |
{ |
953dee9bb EDAC, ie31200_eda... |
219 220 |
return ((log & IE31200_ECCERRLOG_RANK_BITS) >> IE31200_ECCERRLOG_RANK_SHIFT); |
7ee40b897 ie31200_edac: Int... |
221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 |
} static void ie31200_clear_error_info(struct mem_ctl_info *mci) { /* * Clear any error bits. * (Yes, we really clear bits by writing 1 to them.) */ pci_write_bits16(to_pci_dev(mci->pdev), IE31200_ERRSTS, IE31200_ERRSTS_BITS, IE31200_ERRSTS_BITS); } static void ie31200_get_and_clear_error_info(struct mem_ctl_info *mci, struct ie31200_error_info *info) { struct pci_dev *pdev; struct ie31200_priv *priv = mci->pvt_info; |
7ee40b897 ie31200_edac: Int... |
238 239 240 241 242 243 244 245 246 247 248 |
pdev = to_pci_dev(mci->pdev); /* * This is a mess because there is no atomic way to read all the * registers at once and the registers can transition from CE being * overwritten by UE. */ pci_read_config_word(pdev, IE31200_ERRSTS, &info->errsts); if (!(info->errsts & IE31200_ERRSTS_BITS)) return; |
953dee9bb EDAC, ie31200_eda... |
249 |
info->eccerrlog[0] = lo_hi_readq(priv->c0errlog); |
7ee40b897 ie31200_edac: Int... |
250 |
if (nr_channels == 2) |
953dee9bb EDAC, ie31200_eda... |
251 |
info->eccerrlog[1] = lo_hi_readq(priv->c1errlog); |
7ee40b897 ie31200_edac: Int... |
252 253 254 255 256 257 258 259 260 261 |
pci_read_config_word(pdev, IE31200_ERRSTS, &info->errsts2); /* * If the error is the same for both reads then the first set * of reads is valid. If there is a change then there is a CE * with no info and the second set of reads is valid and * should be UE info. */ if ((info->errsts ^ info->errsts2) & IE31200_ERRSTS_BITS) { |
953dee9bb EDAC, ie31200_eda... |
262 |
info->eccerrlog[0] = lo_hi_readq(priv->c0errlog); |
7ee40b897 ie31200_edac: Int... |
263 264 |
if (nr_channels == 2) info->eccerrlog[1] = |
953dee9bb EDAC, ie31200_eda... |
265 |
lo_hi_readq(priv->c1errlog); |
7ee40b897 ie31200_edac: Int... |
266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 |
} ie31200_clear_error_info(mci); } static void ie31200_process_error_info(struct mem_ctl_info *mci, struct ie31200_error_info *info) { int channel; u64 log; if (!(info->errsts & IE31200_ERRSTS_BITS)) return; if ((info->errsts ^ info->errsts2) & IE31200_ERRSTS_BITS) { edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0, -1, -1, -1, "UE overwrote CE", ""); info->errsts = info->errsts2; } for (channel = 0; channel < nr_channels; channel++) { log = info->eccerrlog[channel]; if (log & IE31200_ECCERRLOG_UE) { edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0, |
953dee9bb EDAC, ie31200_eda... |
291 |
eccerrlog_row(log), |
7ee40b897 ie31200_edac: Int... |
292 293 294 295 296 297 |
channel, -1, "ie31200 UE", ""); } else if (log & IE31200_ECCERRLOG_CE) { edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, 0, 0, IE31200_ECCERRLOG_SYNDROME(log), |
953dee9bb EDAC, ie31200_eda... |
298 |
eccerrlog_row(log), |
7ee40b897 ie31200_edac: Int... |
299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 |
channel, -1, "ie31200 CE", ""); } } } static void ie31200_check(struct mem_ctl_info *mci) { struct ie31200_error_info info; edac_dbg(1, "MC%d ", mci->mc_idx); ie31200_get_and_clear_error_info(mci, &info); ie31200_process_error_info(mci, &info); } static void __iomem *ie31200_map_mchbar(struct pci_dev *pdev) { union { u64 mchbar; struct { u32 mchbar_low; u32 mchbar_high; }; } u; void __iomem *window; pci_read_config_dword(pdev, IE31200_MCHBAR_LOW, &u.mchbar_low); pci_read_config_dword(pdev, IE31200_MCHBAR_HIGH, &u.mchbar_high); u.mchbar &= IE31200_MCHBAR_MASK; if (u.mchbar != (resource_size_t)u.mchbar) { ie31200_printk(KERN_ERR, "mmio space beyond accessible range (0x%llx) ", (unsigned long long)u.mchbar); return NULL; } window = ioremap_nocache(u.mchbar, IE31200_MMR_WINDOW_SIZE); if (!window) ie31200_printk(KERN_ERR, "Cannot map mmio space at 0x%llx ", (unsigned long long)u.mchbar); return window; } |
953dee9bb EDAC, ie31200_eda... |
345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 |
static void __skl_populate_dimm_info(struct dimm_data *dd, u32 addr_decode, int chan) { dd->size = (addr_decode >> (chan << 4)) & IE31200_MAD_DIMM_SIZE; dd->dual_rank = (addr_decode & (IE31200_MAD_DIMM_A_RANK_SKL << (chan << 4))) ? 1 : 0; dd->x16_width = ((addr_decode & (IE31200_MAD_DIMM_A_WIDTH_SKL << (chan << 4))) >> (IE31200_MAD_DIMM_A_WIDTH_SKL_SHIFT + (chan << 4))); } static void __populate_dimm_info(struct dimm_data *dd, u32 addr_decode, int chan) { dd->size = (addr_decode >> (chan << 3)) & IE31200_MAD_DIMM_SIZE; dd->dual_rank = (addr_decode & (IE31200_MAD_DIMM_A_RANK << chan)) ? 1 : 0; dd->x16_width = (addr_decode & (IE31200_MAD_DIMM_A_WIDTH << chan)) ? 1 : 0; } static void populate_dimm_info(struct dimm_data *dd, u32 addr_decode, int chan, bool skl) { if (skl) __skl_populate_dimm_info(dd, addr_decode, chan); else __populate_dimm_info(dd, addr_decode, chan); } |
7ee40b897 ie31200_edac: Int... |
370 371 |
static int ie31200_probe1(struct pci_dev *pdev, int dev_idx) { |
78fd4d124 ie31200_edac: All... |
372 |
int i, j, ret; |
7ee40b897 ie31200_edac: Int... |
373 374 375 376 377 |
struct mem_ctl_info *mci = NULL; struct edac_mc_layer layers[2]; struct dimm_data dimm_info[IE31200_CHANNELS][IE31200_DIMMS_PER_CHANNEL]; void __iomem *window; struct ie31200_priv *priv; |
953dee9bb EDAC, ie31200_eda... |
378 379 |
u32 addr_decode, mad_offset; bool skl = (pdev->device == PCI_DEVICE_ID_INTEL_IE31200_HB_8); |
7ee40b897 ie31200_edac: Int... |
380 381 382 383 384 385 386 387 388 |
edac_dbg(0, "MC: "); if (!ecc_capable(pdev)) { ie31200_printk(KERN_INFO, "No ECC support "); return -ENODEV; } |
7ee40b897 ie31200_edac: Int... |
389 |
nr_channels = how_many_channels(pdev); |
7ee40b897 ie31200_edac: Int... |
390 391 392 393 394 395 396 397 |
layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; layers[0].size = IE31200_DIMMS; layers[0].is_virt_csrow = true; layers[1].type = EDAC_MC_LAYER_CHANNEL; layers[1].size = nr_channels; layers[1].is_virt_csrow = false; mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(struct ie31200_priv)); |
7ee40b897 ie31200_edac: Int... |
398 |
if (!mci) |
78fd4d124 ie31200_edac: All... |
399 |
return -ENOMEM; |
7ee40b897 ie31200_edac: Int... |
400 |
|
78fd4d124 ie31200_edac: All... |
401 402 403 404 405 |
window = ie31200_map_mchbar(pdev); if (!window) { ret = -ENODEV; goto fail_free; } |
7ee40b897 ie31200_edac: Int... |
406 |
|
78fd4d124 ie31200_edac: All... |
407 408 |
edac_dbg(3, "MC: init mci "); |
7ee40b897 ie31200_edac: Int... |
409 |
mci->pdev = &pdev->dev; |
953dee9bb EDAC, ie31200_eda... |
410 411 412 413 |
if (skl) mci->mtype_cap = MEM_FLAG_DDR4; else mci->mtype_cap = MEM_FLAG_DDR3; |
7ee40b897 ie31200_edac: Int... |
414 415 |
mci->edac_ctl_cap = EDAC_FLAG_SECDED; mci->edac_cap = EDAC_FLAG_SECDED; |
7ee40b897 ie31200_edac: Int... |
416 417 418 419 420 421 422 423 |
mci->mod_name = EDAC_MOD_STR; mci->mod_ver = IE31200_REVISION; mci->ctl_name = ie31200_devs[dev_idx].ctl_name; mci->dev_name = pci_name(pdev); mci->edac_check = ie31200_check; mci->ctl_page_to_phys = NULL; priv = mci->pvt_info; priv->window = window; |
953dee9bb EDAC, ie31200_eda... |
424 425 426 427 428 429 430 431 432 |
if (skl) { priv->c0errlog = window + IE31200_C0ECCERRLOG_SKL; priv->c1errlog = window + IE31200_C1ECCERRLOG_SKL; mad_offset = IE31200_MAD_DIMM_0_OFFSET_SKL; } else { priv->c0errlog = window + IE31200_C0ECCERRLOG; priv->c1errlog = window + IE31200_C1ECCERRLOG; mad_offset = IE31200_MAD_DIMM_0_OFFSET; } |
7ee40b897 ie31200_edac: Int... |
433 |
|
78fd4d124 ie31200_edac: All... |
434 435 |
/* populate DIMM info */ for (i = 0; i < IE31200_CHANNELS; i++) { |
953dee9bb EDAC, ie31200_eda... |
436 |
addr_decode = readl(window + mad_offset + |
78fd4d124 ie31200_edac: All... |
437 438 439 440 |
(i * 4)); edac_dbg(0, "addr_decode: 0x%x ", addr_decode); for (j = 0; j < IE31200_DIMMS_PER_CHANNEL; j++) { |
953dee9bb EDAC, ie31200_eda... |
441 442 |
populate_dimm_info(&dimm_info[i][j], addr_decode, j, skl); |
78fd4d124 ie31200_edac: All... |
443 444 445 446 447 448 449 |
edac_dbg(0, "size: 0x%x, rank: %d, width: %d ", dimm_info[i][j].size, dimm_info[i][j].dual_rank, dimm_info[i][j].x16_width); } } |
7ee40b897 ie31200_edac: Int... |
450 451 452 453 454 455 456 457 458 459 |
/* * The dram rank boundary (DRB) reg values are boundary addresses * for each DRAM rank with a granularity of 64MB. DRB regs are * cumulative; the last one will contain the total memory * contained in all ranks. */ for (i = 0; i < IE31200_DIMMS_PER_CHANNEL; i++) { for (j = 0; j < IE31200_CHANNELS; j++) { struct dimm_info *dimm; unsigned long nr_pages; |
953dee9bb EDAC, ie31200_eda... |
460 |
nr_pages = IE31200_PAGES(dimm_info[j][i].size, skl); |
7ee40b897 ie31200_edac: Int... |
461 462 463 464 465 466 467 468 469 470 471 472 |
if (nr_pages == 0) continue; if (dimm_info[j][i].dual_rank) { nr_pages = nr_pages / 2; dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, (i * 2) + 1, j, 0); dimm->nr_pages = nr_pages; edac_dbg(0, "set nr pages: 0x%lx ", nr_pages); dimm->grain = 8; /* just a guess */ |
953dee9bb EDAC, ie31200_eda... |
473 474 475 476 |
if (skl) dimm->mtype = MEM_DDR4; else dimm->mtype = MEM_DDR3; |
7ee40b897 ie31200_edac: Int... |
477 478 479 480 481 482 483 484 485 |
dimm->dtype = DEV_UNKNOWN; dimm->edac_mode = EDAC_UNKNOWN; } dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, i * 2, j, 0); dimm->nr_pages = nr_pages; edac_dbg(0, "set nr pages: 0x%lx ", nr_pages); dimm->grain = 8; /* same guess */ |
953dee9bb EDAC, ie31200_eda... |
486 487 488 489 |
if (skl) dimm->mtype = MEM_DDR4; else dimm->mtype = MEM_DDR3; |
7ee40b897 ie31200_edac: Int... |
490 491 492 493 494 495 |
dimm->dtype = DEV_UNKNOWN; dimm->edac_mode = EDAC_UNKNOWN; } } ie31200_clear_error_info(mci); |
7ee40b897 ie31200_edac: Int... |
496 497 498 |
if (edac_mc_add_mc(mci)) { edac_dbg(3, "MC: failed edac_mc_add_mc() "); |
78fd4d124 ie31200_edac: All... |
499 500 |
ret = -ENODEV; goto fail_unmap; |
7ee40b897 ie31200_edac: Int... |
501 502 503 504 505 506 |
} /* get this far and it's successful */ edac_dbg(3, "MC: success "); return 0; |
7ee40b897 ie31200_edac: Int... |
507 508 |
fail_unmap: iounmap(window); |
78fd4d124 ie31200_edac: All... |
509 510 511 512 |
fail_free: edac_mc_free(mci); return ret; |
7ee40b897 ie31200_edac: Int... |
513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 |
} static int ie31200_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) { edac_dbg(0, "MC: "); if (pci_enable_device(pdev) < 0) return -EIO; return ie31200_probe1(pdev, ent->driver_data); } static void ie31200_remove_one(struct pci_dev *pdev) { struct mem_ctl_info *mci; struct ie31200_priv *priv; edac_dbg(0, " "); mci = edac_mc_del_mc(&pdev->dev); if (!mci) return; priv = mci->pvt_info; iounmap(priv->window); edac_mc_free(mci); } static const struct pci_device_id ie31200_pci_tbl[] = { { PCI_VEND_DEV(INTEL, IE31200_HB_1), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200}, { PCI_VEND_DEV(INTEL, IE31200_HB_2), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200}, { PCI_VEND_DEV(INTEL, IE31200_HB_3), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200}, { PCI_VEND_DEV(INTEL, IE31200_HB_4), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200}, { PCI_VEND_DEV(INTEL, IE31200_HB_5), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200}, { PCI_VEND_DEV(INTEL, IE31200_HB_6), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200}, { PCI_VEND_DEV(INTEL, IE31200_HB_7), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200}, { |
953dee9bb EDAC, ie31200_eda... |
565 566 567 |
PCI_VEND_DEV(INTEL, IE31200_HB_8), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200}, { |
7ee40b897 ie31200_edac: Int... |
568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 |
0, } /* 0 terminated list. */ }; MODULE_DEVICE_TABLE(pci, ie31200_pci_tbl); static struct pci_driver ie31200_driver = { .name = EDAC_MOD_STR, .probe = ie31200_init_one, .remove = ie31200_remove_one, .id_table = ie31200_pci_tbl, }; static int __init ie31200_init(void) { edac_dbg(3, "MC: "); /* Ensure that the OPSTATE is set correctly for POLL or NMI */ opstate_init(); return pci_register_driver(&ie31200_driver); } static void __exit ie31200_exit(void) { edac_dbg(3, "MC: "); pci_unregister_driver(&ie31200_driver); } module_init(ie31200_init); module_exit(ie31200_exit); MODULE_LICENSE("GPL"); MODULE_AUTHOR("Jason Baron <jbaron@akamai.com>"); MODULE_DESCRIPTION("MC support for Intel Processor E31200 memory hub controllers"); |