15 Dec, 2016
1 commit
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Now, all left at edac_core.h are at drivers/edac/edac_mc.c,
so rename it to edac_mc.h.Signed-off-by: Mauro Carvalho Chehab
07 May, 2016
1 commit
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Skylake adjusts some register locations, but otherwise follows the
existing model quite closely. I was able to verify that the 'ce_count'
increments when 'bad dimms' are used. The accounting of 'ce_count' and
'ue_count' is the primary functionality of interest for us. Tested on
Intel(R) Xeon(R) CPU E3-1260L v5 @ 2.90GHz.Signed-off-by: Jason Baron
Acked-by: Tony Luck
Cc: linux-edac
Link: http://lkml.kernel.org/r/1462547927-22679-1-git-send-email-jbaron@akamai.com
Signed-off-by: Borislav Petkov
15 Oct, 2015
1 commit
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These are not implementations of default architecture code but helpers
for drivers. Move them to the place they belong to.Signed-off-by: Christoph Hellwig
Acked-by: Darren Hart
Acked-by: Hitoshi Mitake
Signed-off-by: Arnd Bergmann
10 Jul, 2014
1 commit
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Check for memory allocation and mchbar mapping failures before
initializing the dimm info tables needlessly.Signed-off-by: Jason Baron
Suggested-by: Borislav Petkov
Link: http://lkml.kernel.org/r/ead8f53e699f1ce21c2e17f3cffb4685d4faf72a.1404939455.git.jbaron@akamai.com
Signed-off-by: Borislav Petkov
04 Jul, 2014
1 commit
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Add a driver for the E3-1200 series of Intel DRAM controllers, based on
the following E3-1200 specs:http://www.intel.com/content/www/us/en/processors/xeon/xeon-e3-1200-family-vol-2-datasheet.html
http://www.intel.com/content/www/us/en/processors/xeon/xeon-e3-1200v3-vol-2-datasheet.htmlI've tested this on bad memory hardware, and observed correlating bad
reads and uncorrected memory errors as reported by the driver.Tested against:
CPU E3-1270 v3 @ 3.50GHz : 8086:0c08 (haswell)
CPU E3-1270 V2 @ 3.50GHz : 8086:0158 (ivy bridge)
CPU E31270 @ 3.40GHz : 8086:0108 (sandy bridge)Signed-off-by: Jason Baron
Link: http://lkml.kernel.org/r/95c83e80dd40b5377e8bb206285c5d95ac623872.1403818526.git.jbaron@akamai.com
[ Boris: realign defines ]
Signed-off-by: Borislav Petkov