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drivers/pci/quirks.c
107 KB
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/* * This file contains work-arounds for many known PCI hardware * bugs. Devices present only on certain architectures (host * bridges et cetera) should be handled in arch-specific code. * * Note: any quirks for hotpluggable devices must _NOT_ be declared __init. * * Copyright (c) 1999 Martin Mares <mj@ucw.cz> * |
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* Init/reset quirks for USB host controllers should be in the * USB quirks file, where their drivers can access reuse it. * |
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* The bridge optimization stuff has been removed. If you really * have a silly BIOS which is unable to set your host bridge right, * use the PowerTweak utility (see http://powertweak.sourceforge.net). */ |
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#include <linux/types.h> #include <linux/kernel.h> |
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#include <linux/export.h> |
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#include <linux/pci.h> #include <linux/init.h> #include <linux/delay.h> |
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#include <linux/acpi.h> |
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#include <linux/kallsyms.h> |
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#include <linux/dmi.h> |
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#include <linux/pci-aspm.h> |
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#include <linux/ioport.h> |
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#include <asm/dma.h> /* isa_dma_bridge_buggy */ |
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#include "pci.h" |
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/* |
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* This quirk function disables memory decoding and releases memory resources * of the device specified by kernel's boot parameter 'pci=resource_alignment='. |
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* It also rounds up size to specified alignment. * Later on, the kernel will assign page-aligned memory resource back |
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* to the device. |
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*/ static void __devinit quirk_resource_alignment(struct pci_dev *dev) { int i; struct resource *r; resource_size_t align, size; |
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u16 command; |
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if (!pci_is_reassigndev(dev)) return; if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL && (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) { dev_warn(&dev->dev, "Can't reassign resources to host bridge. "); return; } |
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dev_info(&dev->dev, "Disabling memory decoding and releasing memory resources. "); pci_read_config_word(dev, PCI_COMMAND, &command); command &= ~PCI_COMMAND_MEMORY; pci_write_config_word(dev, PCI_COMMAND, command); |
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align = pci_specified_resource_alignment(dev); for (i=0; i < PCI_BRIDGE_RESOURCES; i++) { r = &dev->resource[i]; if (!(r->flags & IORESOURCE_MEM)) continue; size = resource_size(r); if (size < align) { size = align; dev_info(&dev->dev, "Rounding up size of resource #%d to %#llx. ", i, (unsigned long long)size); } r->end = size - 1; r->start = 0; } /* Need to disable bridge's resource window, * to enable the kernel to reassign new resource * window later on. */ if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE && (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) { r = &dev->resource[i]; if (!(r->flags & IORESOURCE_MEM)) continue; r->end = resource_size(r) - 1; r->start = 0; } pci_disable_bridge_window(dev); } } DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_resource_alignment); |
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/* * Decoding should be disabled for a PCI device during BAR sizing to avoid * conflict. But doing so may cause problems on host bridge and perhaps other * key system devices. For devices that need to have mmio decoding always-on, * we need to set the dev->mmio_always_on bit. */ static void __devinit quirk_mmio_always_on(struct pci_dev *dev) { if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) dev->mmio_always_on = 1; } DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, quirk_mmio_always_on); |
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/* The Mellanox Tavor device gives false positive parity errors * Mark this device with a broken_parity_status, to allow * PCI scanning code to "skip" this now blacklisted device. */ static void __devinit quirk_mellanox_tavor(struct pci_dev *dev) { dev->broken_parity_status = 1; /* This device gives false positives */ } DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor); |
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/* Deal with broken BIOS'es that neglect to enable passive release, which can cause problems in combination with the 82441FX/PPro MTRRs */ |
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static void quirk_passive_release(struct pci_dev *dev) |
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{ struct pci_dev *d = NULL; unsigned char dlc; /* We have to make sure a particular bit is set in the PIIX3 ISA bridge, so we have to go out and find it. */ while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) { pci_read_config_byte(d, 0x82, &dlc); if (!(dlc & 1<<1)) { |
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dev_info(&d->dev, "PIIX3: Enabling Passive Release "); |
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dlc |= 1<<1; pci_write_config_byte(d, 0x82, dlc); } } } |
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); |
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/* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround but VIA don't answer queries. If you happen to have good contacts at VIA ask them for me please -- Alan This appears to be BIOS not version dependent. So presumably there is a chipset level fix */ |
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static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev) { if (!isa_dma_bridge_buggy) { isa_dma_bridge_buggy=1; |
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dev_info(&dev->dev, "Activating ISA DMA hang workarounds "); |
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} } /* * Its not totally clear which chipsets are the problematic ones * We know 82C586 and 82C596 variants are affected. */ |
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs); |
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/* |
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* Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear * for some HT machines to use C4 w/o hanging. */ static void __devinit quirk_tigerpoint_bm_sts(struct pci_dev *dev) { u32 pmbase; u16 pm1a; pci_read_config_dword(dev, 0x40, &pmbase); pmbase = pmbase & 0xff80; pm1a = inw(pmbase); if (pm1a & 0x10) { dev_info(&dev->dev, FW_BUG "TigerPoint LPC.BM_STS cleared "); outw(0x10, pmbase); } } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts); /* |
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* Chipsets where PCI->PCI transfers vanish or hang */ static void __devinit quirk_nopcipci(struct pci_dev *dev) { if ((pci_pci_problems & PCIPCI_FAIL)==0) { |
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dev_info(&dev->dev, "Disabling direct PCI/PCI transfers "); |
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pci_pci_problems |= PCIPCI_FAIL; } } |
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci); |
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static void __devinit quirk_nopciamd(struct pci_dev *dev) { u8 rev; pci_read_config_byte(dev, 0x08, &rev); if (rev == 0x13) { /* Erratum 24 */ |
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dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers "); |
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pci_pci_problems |= PCIAGP_FAIL; } } |
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd); |
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/* * Triton requires workarounds to be used by the drivers */ static void __devinit quirk_triton(struct pci_dev *dev) { if ((pci_pci_problems&PCIPCI_TRITON)==0) { |
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dev_info(&dev->dev, "Limiting direct PCI/PCI transfers "); |
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pci_pci_problems |= PCIPCI_TRITON; } } |
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton); |
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/* * VIA Apollo KT133 needs PCI latency patch * Made according to a windows driver based patch by George E. Breese * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm |
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* and http://www.georgebreese.com/net/software/#PCI |
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* Also see http://www.au-ja.org/review-kt133a-1-en.phtml for * the info on which Mr Breese based his work. * * Updated based on further information from the site and also on * information provided by VIA */ |
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static void quirk_vialatency(struct pci_dev *dev) |
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{ struct pci_dev *p; |
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u8 busarb; /* Ok we have a potential problem chipset here. Now see if we have a buggy southbridge */ p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL); if (p!=NULL) { |
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/* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */ /* Check for buggy part revisions */ |
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if (p->revision < 0x40 || p->revision > 0x42) |
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goto exit; } else { p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL); if (p==NULL) /* No problem parts */ goto exit; |
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/* Check for buggy part revisions */ |
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if (p->revision < 0x10 || p->revision > 0x12) |
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goto exit; } /* * Ok we have the problem. Now set the PCI master grant to * occur every master grant. The apparent bug is that under high * PCI load (quite common in Linux of course) you can get data * loss when the CPU is held off the bus for 3 bus master requests * This happens to include the IDE controllers.... * * VIA only apply this fix when an SB Live! is present but under |
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* both Linux and Windows this isn't enough, and we have seen |
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* corruption without SB Live! but with things like 3 UDMA IDE * controllers. So we ignore that bit of the VIA recommendation.. */ pci_read_config_byte(dev, 0x76, &busarb); /* Set bit 4 and bi 5 of byte 76 to 0x01 "Master priority rotation on every PCI master grant */ busarb &= ~(1<<5); busarb |= (1<<4); pci_write_config_byte(dev, 0x76, busarb); |
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dev_info(&dev->dev, "Applying VIA southbridge workaround "); |
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exit: pci_dev_put(p); } |
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); |
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/* Must restore this on a resume from RAM */ |
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DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); |
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/* * VIA Apollo VP3 needs ETBF on BT848/878 */ static void __devinit quirk_viaetbf(struct pci_dev *dev) { if ((pci_pci_problems&PCIPCI_VIAETBF)==0) { |
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dev_info(&dev->dev, "Limiting direct PCI/PCI transfers "); |
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pci_pci_problems |= PCIPCI_VIAETBF; } } |
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf); |
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static void __devinit quirk_vsfx(struct pci_dev *dev) { if ((pci_pci_problems&PCIPCI_VSFX)==0) { |
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dev_info(&dev->dev, "Limiting direct PCI/PCI transfers "); |
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pci_pci_problems |= PCIPCI_VSFX; } } |
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx); |
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/* * Ali Magik requires workarounds to be used by the drivers * that DMA to AGP space. Latency must be set to 0xA and triton * workaround applied too * [Info kindly provided by ALi] */ static void __init quirk_alimagik(struct pci_dev *dev) { if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) { |
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dev_info(&dev->dev, "Limiting direct PCI/PCI transfers "); |
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pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON; } } |
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik); |
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/* * Natoma has some interesting boundary conditions with Zoran stuff * at least */ static void __devinit quirk_natoma(struct pci_dev *dev) { if ((pci_pci_problems&PCIPCI_NATOMA)==0) { |
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dev_info(&dev->dev, "Limiting direct PCI/PCI transfers "); |
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pci_pci_problems |= PCIPCI_NATOMA; } } |
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma); |
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/* * This chip can cause PCI parity errors if config register 0xA0 is read * while DMAs are occurring. */ static void __devinit quirk_citrine(struct pci_dev *dev) { dev->cfg_size = 0xA0; } |
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine); |
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/* * S3 868 and 968 chips report region size equal to 32M, but they decode 64M. * If it's needed, re-allocate the region. */ static void __devinit quirk_s3_64M(struct pci_dev *dev) { struct resource *r = &dev->resource[0]; if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) { r->start = 0; r->end = 0x3ffffff; } } |
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M); |
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/* * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS * ver. 1.33 20070103) don't set the correct ISA PCI region header info. * BAR0 should be 8 bytes; instead, it may be set to something like 8k * (which conflicts w/ BAR1's memory range). */ static void __devinit quirk_cs5536_vsa(struct pci_dev *dev) { if (pci_resource_len(dev, 0) != 8) { struct resource *res = &dev->resource[0]; res->end = res->start + 8 - 1; dev_info(&dev->dev, "CS5536 ISA bridge bug detected " "(incorrect header); workaround applied. "); } } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa); |
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static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region, unsigned size, int nr, const char *name) |
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{ region &= ~(size-1); if (region) { |
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struct pci_bus_region bus_region; |
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struct resource *res = dev->resource + nr; res->name = pci_name(dev); res->start = region; res->end = region + size - 1; res->flags = IORESOURCE_IO; |
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/* Convert from PCI bus to resource space. */ bus_region.start = res->start; bus_region.end = res->end; pcibios_bus_to_resource(dev, res, &bus_region); |
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if (pci_claim_resource(dev, nr) == 0) dev_info(&dev->dev, "quirk: %pR claimed by %s ", res, name); |
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} } /* * ATI Northbridge setups MCE the processor if you even * read somewhere between 0x3b0->0x3bb or read 0x3d3 */ static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev) { |
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dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb "); |
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/* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */ request_region(0x3b0, 0x0C, "RadeonIGP"); request_region(0x3d3, 0x01, "RadeonIGP"); } |
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce); |
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/* * Let's make the southbridge information explicit instead * of having to worry about people probing the ACPI areas, * for example.. (Yes, it happens, and if you read the wrong * ACPI register it will put the machine to sleep with no * way of waking it up again. Bummer). * * ALI M7101: Two IO regions pointed to by words at * 0xE0 (64 bytes of ACPI registers) * 0xE2 (32 bytes of SMB registers) */ static void __devinit quirk_ali7101_acpi(struct pci_dev *dev) { u16 region; pci_read_config_word(dev, 0xE0, ®ion); |
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quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI"); |
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pci_read_config_word(dev, 0xE2, ®ion); |
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quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB"); |
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} |
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi); |
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static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) { u32 devres; u32 mask, size, base; pci_read_config_dword(dev, port, &devres); if ((devres & enable) != enable) return; mask = (devres >> 16) & 15; base = devres & 0xffff; size = 16; for (;;) { unsigned bit = size >> 1; if ((bit & mask) == bit) break; size = bit; } /* * For now we only print it out. Eventually we'll want to * reserve it (at least if it's in the 0x1000+ range), but * let's get enough confirmation reports first. */ base &= -size; |
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480 481 |
dev_info(&dev->dev, "%s PIO at %04x-%04x ", name, base, base + size - 1); |
6693e74a1
|
482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 |
} static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) { u32 devres; u32 mask, size, base; pci_read_config_dword(dev, port, &devres); if ((devres & enable) != enable) return; base = devres & 0xffff0000; mask = (devres & 0x3f) << 16; size = 128 << 16; for (;;) { unsigned bit = size >> 1; if ((bit & mask) == bit) break; size = bit; } /* * For now we only print it out. Eventually we'll want to * reserve it, but let's get enough confirmation reports first. */ base &= -size; |
f0fda801d
|
506 507 |
dev_info(&dev->dev, "%s MMIO at %04x-%04x ", name, base, base + size - 1); |
6693e74a1
|
508 |
} |
1da177e4c
|
509 510 511 |
/* * PIIX4 ACPI: Two IO regions pointed to by longwords at * 0x40 (64 bytes of ACPI registers) |
08db2a701
|
512 |
* 0x90 (16 bytes of SMB registers) |
6693e74a1
|
513 |
* and a few strange programmable PIIX4 device resources. |
1da177e4c
|
514 515 516 |
*/ static void __devinit quirk_piix4_acpi(struct pci_dev *dev) { |
6693e74a1
|
517 |
u32 region, res_a; |
1da177e4c
|
518 519 |
pci_read_config_dword(dev, 0x40, ®ion); |
6693e74a1
|
520 |
quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI"); |
1da177e4c
|
521 |
pci_read_config_dword(dev, 0x90, ®ion); |
08db2a701
|
522 |
quirk_io_region(dev, region, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB"); |
6693e74a1
|
523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 |
/* Device resource A has enables for some of the other ones */ pci_read_config_dword(dev, 0x5c, &res_a); piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21); piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21); /* Device resource D is just bitfields for static resources */ /* Device 12 enabled? */ if (res_a & (1 << 29)) { piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20); piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7); } /* Device 13 enabled? */ if (res_a & (1 << 30)) { piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20); piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7); } piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20); piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20); |
1da177e4c
|
544 |
} |
652c538eb
|
545 546 |
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi); |
1da177e4c
|
547 |
|
cdb975584
|
548 549 550 551 552 553 554 555 556 557 |
#define ICH_PMBASE 0x40 #define ICH_ACPI_CNTL 0x44 #define ICH4_ACPI_EN 0x10 #define ICH6_ACPI_EN 0x80 #define ICH4_GPIOBASE 0x58 #define ICH4_GPIO_CNTL 0x5c #define ICH4_GPIO_EN 0x10 #define ICH6_GPIOBASE 0x48 #define ICH6_GPIO_CNTL 0x4c #define ICH6_GPIO_EN 0x10 |
1da177e4c
|
558 559 560 561 562 563 564 565 |
/* * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at * 0x40 (128 bytes of ACPI, GPIO & TCO registers) * 0x58 (64 bytes of GPIO I/O space) */ static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev) { u32 region; |
cdb975584
|
566 |
u8 enable; |
1da177e4c
|
567 |
|
87e3dc385
|
568 569 570 571 572 573 574 |
/* * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict * with low legacy (and fixed) ports. We don't know the decoding * priority and can't tell whether the legacy device or the one created * here is really at that address. This happens on boards with broken * BIOSes. */ |
cdb975584
|
575 576 577 |
pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); if (enable & ICH4_ACPI_EN) { pci_read_config_dword(dev, ICH_PMBASE, ®ion); |
87e3dc385
|
578 579 580 581 |
region &= PCI_BASE_ADDRESS_IO_MASK; if (region >= PCIBIOS_MIN_IO) quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH4 ACPI/GPIO/TCO"); |
cdb975584
|
582 |
} |
1da177e4c
|
583 |
|
cdb975584
|
584 585 586 |
pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable); if (enable & ICH4_GPIO_EN) { pci_read_config_dword(dev, ICH4_GPIOBASE, ®ion); |
87e3dc385
|
587 588 589 590 |
region &= PCI_BASE_ADDRESS_IO_MASK; if (region >= PCIBIOS_MIN_IO) quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES + 1, "ICH4 GPIO"); |
cdb975584
|
591 |
} |
1da177e4c
|
592 |
} |
652c538eb
|
593 594 595 596 597 598 599 600 601 602 |
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi); |
1da177e4c
|
603 |
|
894886e5d
|
604 |
static void __devinit ich6_lpc_acpi_gpio(struct pci_dev *dev) |
2cea752f6
|
605 606 |
{ u32 region; |
cdb975584
|
607 |
u8 enable; |
2cea752f6
|
608 |
|
cdb975584
|
609 610 611 |
pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); if (enable & ICH6_ACPI_EN) { pci_read_config_dword(dev, ICH_PMBASE, ®ion); |
87e3dc385
|
612 613 614 615 |
region &= PCI_BASE_ADDRESS_IO_MASK; if (region >= PCIBIOS_MIN_IO) quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH6 ACPI/GPIO/TCO"); |
cdb975584
|
616 |
} |
2cea752f6
|
617 |
|
cdb975584
|
618 |
pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable); |
b6d95bb63
|
619 |
if (enable & ICH6_GPIO_EN) { |
cdb975584
|
620 |
pci_read_config_dword(dev, ICH6_GPIOBASE, ®ion); |
87e3dc385
|
621 622 623 624 |
region &= PCI_BASE_ADDRESS_IO_MASK; if (region >= PCIBIOS_MIN_IO) quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES + 1, "ICH6 GPIO"); |
cdb975584
|
625 |
} |
2cea752f6
|
626 |
} |
894886e5d
|
627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 |
static void __devinit ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize) { u32 val; u32 size, base; pci_read_config_dword(dev, reg, &val); /* Enabled? */ if (!(val & 1)) return; base = val & 0xfffc; if (dynsize) { /* * This is not correct. It is 16, 32 or 64 bytes depending on * register D31:F0:ADh bits 5:4. * * But this gets us at least _part_ of it. */ size = 16; } else { size = 128; } base &= ~(size-1); /* Just print it out for now. We should reserve it after more debugging */ dev_info(&dev->dev, "%s PIO at %04x-%04x ", name, base, base+size-1); } static void __devinit quirk_ich6_lpc(struct pci_dev *dev) { /* Shared ACPI/GPIO decode with all ICH6+ */ ich6_lpc_acpi_gpio(dev); /* ICH6-specific generic IO decode */ ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0); ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1); } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc); static void __devinit ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name) { u32 val; u32 mask, base; pci_read_config_dword(dev, reg, &val); /* Enabled? */ if (!(val & 1)) return; /* * IO base in bits 15:2, mask in bits 23:18, both * are dword-based */ base = val & 0xfffc; mask = (val >> 16) & 0xfc; mask |= 3; /* Just print it out for now. We should reserve it after more debugging */ dev_info(&dev->dev, "%s PIO at %04x (mask %04x) ", name, base, mask); } /* ICH7-10 has the same common LPC generic IO decode registers */ static void __devinit quirk_ich7_lpc(struct pci_dev *dev) { |
5d9c0a795
|
696 |
/* We share the common ACPI/GPIO decode with ICH6 */ |
894886e5d
|
697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 |
ich6_lpc_acpi_gpio(dev); /* And have 4 ICH7+ generic decodes */ ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1"); ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2"); ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3"); ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4"); } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc); |
2cea752f6
|
718 |
|
1da177e4c
|
719 720 721 722 723 724 |
/* * VIA ACPI: One IO region pointed to by longword at * 0x48 or 0x20 (256 bytes of ACPI registers) */ static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev) { |
1da177e4c
|
725 |
u32 region; |
651472fbf
|
726 |
if (dev->revision & 0x10) { |
1da177e4c
|
727 728 |
pci_read_config_dword(dev, 0x48, ®ion); region &= PCI_BASE_ADDRESS_IO_MASK; |
6693e74a1
|
729 |
quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI"); |
1da177e4c
|
730 731 |
} } |
652c538eb
|
732 |
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi); |
1da177e4c
|
733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 |
/* * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at * 0x48 (256 bytes of ACPI registers) * 0x70 (128 bytes of hardware monitoring register) * 0x90 (16 bytes of SMB registers) */ static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev) { u16 hm; u32 smb; quirk_vt82c586_acpi(dev); pci_read_config_word(dev, 0x70, &hm); hm &= PCI_BASE_ADDRESS_IO_MASK; |
02f313b2c
|
749 |
quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1, "vt82c686 HW-mon"); |
1da177e4c
|
750 751 752 |
pci_read_config_dword(dev, 0x90, &smb); smb &= PCI_BASE_ADDRESS_IO_MASK; |
02f313b2c
|
753 |
quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB"); |
1da177e4c
|
754 |
} |
652c538eb
|
755 |
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi); |
1da177e4c
|
756 |
|
6d85f29bb
|
757 758 759 760 761 762 763 764 765 766 767 |
/* * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at * 0x88 (128 bytes of power management registers) * 0xd0 (16 bytes of SMB registers) */ static void __devinit quirk_vt8235_acpi(struct pci_dev *dev) { u16 pm, smb; pci_read_config_word(dev, 0x88, &pm); pm &= PCI_BASE_ADDRESS_IO_MASK; |
6693e74a1
|
768 |
quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM"); |
6d85f29bb
|
769 770 771 |
pci_read_config_word(dev, 0xd0, &smb); smb &= PCI_BASE_ADDRESS_IO_MASK; |
6693e74a1
|
772 |
quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1, "vt8235 SMB"); |
6d85f29bb
|
773 774 |
} DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi); |
1f56f4a2b
|
775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 |
/* * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast back-to-back: * Disable fast back-to-back on the secondary bus segment */ static void __devinit quirk_xio2000a(struct pci_dev *dev) { struct pci_dev *pdev; u16 command; dev_warn(&dev->dev, "TI XIO2000a quirk detected; " "secondary bus fast back-to-back transfers disabled "); list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) { pci_read_config_word(pdev, PCI_COMMAND, &command); if (command & PCI_COMMAND_FAST_BACK) pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK); } } DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A, quirk_xio2000a); |
1da177e4c
|
795 796 797 798 799 800 801 802 803 804 805 806 |
#ifdef CONFIG_X86_IO_APIC #include <asm/io_apic.h> /* * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip * devices to the external APIC. * * TODO: When we have device-specific interrupt routers, * this code will go away from quirks. */ |
1597cacbe
|
807 |
static void quirk_via_ioapic(struct pci_dev *dev) |
1da177e4c
|
808 809 810 811 812 813 814 815 |
{ u8 tmp; if (nr_ioapics < 1) tmp = 0; /* nothing routed to external APIC */ else tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ |
f0fda801d
|
816 817 |
dev_info(&dev->dev, "%sbling VIA external APIC routing ", |
1da177e4c
|
818 819 820 821 822 |
tmp == 0 ? "Disa" : "Ena"); /* Offset 0x58: External APIC IRQ output control */ pci_write_config_byte (dev, 0x58, tmp); } |
652c538eb
|
823 |
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); |
e1a2a51e6
|
824 |
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); |
1da177e4c
|
825 826 |
/* |
a1740913c
|
827 828 829 830 831 |
* VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit. * This leads to doubled level interrupt rates. * Set this bit to get rid of cycle wastage. * Otherwise uncritical. */ |
1597cacbe
|
832 |
static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev) |
a1740913c
|
833 834 835 836 837 838 |
{ u8 misc_control2; #define BYPASS_APIC_DEASSERT 8 pci_read_config_byte(dev, 0x5B, &misc_control2); if (!(misc_control2 & BYPASS_APIC_DEASSERT)) { |
f0fda801d
|
839 840 |
dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message "); |
a1740913c
|
841 842 843 844 |
pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT); } } DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); |
e1a2a51e6
|
845 |
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); |
a1740913c
|
846 847 |
/* |
1da177e4c
|
848 849 850 851 852 |
* The AMD io apic can hang the box when an apic irq is masked. * We check all revs >= B0 (yet not in the pre production!) as the bug * is currently marked NoFix * * We have multiple reports of hangs with this chipset that went away with |
236561e5d
|
853 |
* noapic specified. For the moment we assume it's the erratum. We may be wrong |
1da177e4c
|
854 855 856 857 |
* of course. However the advice is demonstrably good even if so.. */ static void __devinit quirk_amd_ioapic(struct pci_dev *dev) { |
44c10138f
|
858 |
if (dev->revision >= 0x02) { |
f0fda801d
|
859 860 861 862 |
dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try "); dev_warn(&dev->dev, " : booting with the \"noapic\" option "); |
1da177e4c
|
863 864 |
} } |
652c538eb
|
865 |
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic); |
1da177e4c
|
866 867 868 869 870 871 |
static void __init quirk_ioapic_rmw(struct pci_dev *dev) { if (dev->devfn == 0 && dev->bus->number == 0) sis_apic_bug = 1; } |
652c538eb
|
872 |
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw); |
1da177e4c
|
873 |
#endif /* CONFIG_X86_IO_APIC */ |
d556ad4bb
|
874 875 876 877 878 879 |
/* * Some settings of MMRBC can lead to data corruption so block changes. * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide */ static void __init quirk_amd_8131_mmrbc(struct pci_dev *dev) { |
aa288d4d6
|
880 |
if (dev->subordinate && dev->revision <= 0x12) { |
f0fda801d
|
881 882 883 |
dev_info(&dev->dev, "AMD8131 rev %x detected; " "disabling PCI-X MMRBC ", dev->revision); |
d556ad4bb
|
884 885 886 887 |
dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC; } } DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc); |
1da177e4c
|
888 889 |
/* |
1da177e4c
|
890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 |
* FIXME: it is questionable that quirk_via_acpi * is needed. It shows up as an ISA bridge, and does not * support the PCI_INTERRUPT_LINE register at all. Therefore * it seems like setting the pci_dev's 'irq' to the * value of the ACPI SCI interrupt is only done for convenience. * -jgarzik */ static void __devinit quirk_via_acpi(struct pci_dev *d) { /* * VIA ACPI device: SCI IRQ line in PCI config byte 0x42 */ u8 irq; pci_read_config_byte(d, 0x42, &irq); irq &= 0xf; if (irq && (irq != 2)) d->irq = irq; } |
652c538eb
|
908 909 |
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi); |
1da177e4c
|
910 |
|
09d6029f4
|
911 912 |
/* |
1597cacbe
|
913 |
* VIA bridges which have VLink |
09d6029f4
|
914 |
*/ |
1597cacbe
|
915 |
|
c06bb5d49
|
916 917 918 919 920 921 922 |
static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18; static void quirk_via_bridge(struct pci_dev *dev) { /* See what bridge we have and find the device ranges */ switch (dev->device) { case PCI_DEVICE_ID_VIA_82C686: |
cb7468ef4
|
923 924 925 926 927 |
/* The VT82C686 is special, it attaches to PCI and can have any device number. All its subdevices are functions of that single device. */ via_vlink_dev_lo = PCI_SLOT(dev->devfn); via_vlink_dev_hi = PCI_SLOT(dev->devfn); |
c06bb5d49
|
928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 |
break; case PCI_DEVICE_ID_VIA_8237: case PCI_DEVICE_ID_VIA_8237A: via_vlink_dev_lo = 15; break; case PCI_DEVICE_ID_VIA_8235: via_vlink_dev_lo = 16; break; case PCI_DEVICE_ID_VIA_8231: case PCI_DEVICE_ID_VIA_8233_0: case PCI_DEVICE_ID_VIA_8233A: case PCI_DEVICE_ID_VIA_8233C_0: via_vlink_dev_lo = 17; break; } } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge); |
09d6029f4
|
952 |
|
1597cacbe
|
953 954 955 956 957 958 959 |
/** * quirk_via_vlink - VIA VLink IRQ number update * @dev: PCI device * * If the device we are dealing with is on a PIC IRQ we need to * ensure that the IRQ line register which usually is not relevant * for PCI cards, is actually written so that interrupts get sent |
c06bb5d49
|
960 961 962 963 |
* to the right place. * We only do this on systems where a VIA south bridge was detected, * and only for VIA devices on the motherboard (see quirk_via_bridge * above). |
1597cacbe
|
964 965 966 |
*/ static void quirk_via_vlink(struct pci_dev *dev) |
25be5e6cc
|
967 968 |
{ u8 irq, new_irq; |
c06bb5d49
|
969 970 |
/* Check if we have VLink at all */ if (via_vlink_dev_lo == -1) |
09d6029f4
|
971 972 973 974 975 976 977 |
return; new_irq = dev->irq; /* Don't quirk interrupts outside the legacy IRQ range */ if (!new_irq || new_irq > 15) return; |
1597cacbe
|
978 |
/* Internal device ? */ |
c06bb5d49
|
979 980 |
if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi || PCI_SLOT(dev->devfn) < via_vlink_dev_lo) |
1597cacbe
|
981 982 983 984 |
return; /* This is an internal VLink device on a PIC interrupt. The BIOS ought to have set this but may not have, so we redo it */ |
25be5e6cc
|
985 986 |
pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); if (new_irq != irq) { |
f0fda801d
|
987 988 989 |
dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d ", irq, new_irq); |
25be5e6cc
|
990 991 992 993 |
udelay(15); /* unknown if delay really needed */ pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq); } } |
1597cacbe
|
994 |
DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink); |
25be5e6cc
|
995 |
|
1da177e4c
|
996 |
/* |
1da177e4c
|
997 998 999 1000 1001 1002 1003 1004 1005 1006 |
* VIA VT82C598 has its device ID settable and many BIOSes * set it to the ID of VT82C597 for backward compatibility. * We need to switch it off to be able to recognize the real * type of the chip. */ static void __devinit quirk_vt82c598_id(struct pci_dev *dev) { pci_write_config_byte(dev, 0xfc, 0); pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device); } |
652c538eb
|
1007 |
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id); |
1da177e4c
|
1008 1009 1010 1011 1012 1013 1014 |
/* * CardBus controllers have a legacy base address that enables them * to respond as i82365 pcmcia controllers. We don't want them to * do this even if the Linux CardBus driver is not loaded, because * the Linux i82365 driver does not (and should not) handle CardBus. */ |
1597cacbe
|
1015 |
static void quirk_cardbus_legacy(struct pci_dev *dev) |
1da177e4c
|
1016 1017 1018 1019 1020 1021 |
{ if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class) return; pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0); } DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy); |
e1a2a51e6
|
1022 |
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy); |
1da177e4c
|
1023 1024 1025 1026 1027 1028 1029 1030 |
/* * Following the PCI ordering rules is optional on the AMD762. I'm not * sure what the designers were smoking but let's not inhale... * * To be fair to AMD, it follows the spec by default, its BIOS people * who turn it off! */ |
1597cacbe
|
1031 |
static void quirk_amd_ordering(struct pci_dev *dev) |
1da177e4c
|
1032 1033 1034 1035 1036 |
{ u32 pcic; pci_read_config_dword(dev, 0x4C, &pcic); if ((pcic&6)!=6) { pcic |= 6; |
f0fda801d
|
1037 1038 |
dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error "); |
1da177e4c
|
1039 1040 1041 1042 1043 1044 |
pci_write_config_dword(dev, 0x4C, pcic); pci_read_config_dword(dev, 0x84, &pcic); pcic |= (1<<23); /* Required in this mode */ pci_write_config_dword(dev, 0x84, pcic); } } |
652c538eb
|
1045 |
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); |
e1a2a51e6
|
1046 |
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); |
1da177e4c
|
1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 |
/* * DreamWorks provided workaround for Dunord I-3000 problem * * This card decodes and responds to addresses not apparently * assigned to it. We force a larger allocation to ensure that * nothing gets put too close to it. */ static void __devinit quirk_dunord ( struct pci_dev * dev ) { struct resource *r = &dev->resource [1]; r->start = 0; r->end = 0xffffff; } |
652c538eb
|
1061 |
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord); |
1da177e4c
|
1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 |
/* * i82380FB mobile docking controller: its PCI-to-PCI bridge * is subtractive decoding (transparent), and does indicate this * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80 * instead of 0x01. */ static void __devinit quirk_transparent_bridge(struct pci_dev *dev) { dev->transparent = 1; } |
652c538eb
|
1073 1074 |
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge); |
1da177e4c
|
1075 1076 1077 1078 |
/* * Common misconfiguration of the MediaGX/Geode PCI master that will * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 |
631dd1a88
|
1079 |
* datasheets found at http://www.national.com/analog for info on what |
1da177e4c
|
1080 1081 |
* these bits do. <christer@weinigel.se> */ |
1597cacbe
|
1082 |
static void quirk_mediagx_master(struct pci_dev *dev) |
1da177e4c
|
1083 1084 1085 1086 1087 |
{ u8 reg; pci_read_config_byte(dev, 0x41, ®); if (reg & 2) { reg &= ~2; |
f0fda801d
|
1088 1089 |
dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x) ", reg); |
1da177e4c
|
1090 1091 1092 |
pci_write_config_byte(dev, 0x41, reg); } } |
652c538eb
|
1093 1094 |
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); |
1da177e4c
|
1095 1096 |
/* |
1da177e4c
|
1097 1098 1099 1100 |
* Ensure C0 rev restreaming is off. This is normally done by * the BIOS but in the odd case it is not the results are corruption * hence the presence of a Linux check */ |
1597cacbe
|
1101 |
static void quirk_disable_pxb(struct pci_dev *pdev) |
1da177e4c
|
1102 1103 |
{ u16 config; |
1da177e4c
|
1104 |
|
44c10138f
|
1105 |
if (pdev->revision != 0x04) /* Only C0 requires this */ |
1da177e4c
|
1106 1107 1108 1109 1110 |
return; pci_read_config_word(pdev, 0x40, &config); if (config & (1<<6)) { config &= ~(1<<6); pci_write_config_word(pdev, 0x40, config); |
f0fda801d
|
1111 1112 |
dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming "); |
1da177e4c
|
1113 1114 |
} } |
652c538eb
|
1115 |
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); |
e1a2a51e6
|
1116 |
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); |
1da177e4c
|
1117 |
|
05a7d22b9
|
1118 |
static void __devinit quirk_amd_ide_mode(struct pci_dev *pdev) |
ab17443a3
|
1119 |
{ |
5deab5366
|
1120 |
/* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */ |
05a7d22b9
|
1121 |
u8 tmp; |
ab17443a3
|
1122 |
|
05a7d22b9
|
1123 1124 |
pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp); if (tmp == 0x01) { |
ab17443a3
|
1125 1126 1127 1128 1129 |
pci_read_config_byte(pdev, 0x40, &tmp); pci_write_config_byte(pdev, 0x40, tmp|1); pci_write_config_byte(pdev, 0x9, 1); pci_write_config_byte(pdev, 0xa, 6); pci_write_config_byte(pdev, 0x40, tmp); |
c9f89475a
|
1130 |
pdev->class = PCI_CLASS_STORAGE_SATA_AHCI; |
05a7d22b9
|
1131 1132 |
dev_info(&pdev->dev, "set SATA to AHCI mode "); |
ab17443a3
|
1133 1134 |
} } |
05a7d22b9
|
1135 |
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); |
e1a2a51e6
|
1136 |
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); |
05a7d22b9
|
1137 |
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); |
e1a2a51e6
|
1138 |
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); |
5deab5366
|
1139 1140 |
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); |
ab17443a3
|
1141 |
|
1da177e4c
|
1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 |
/* * Serverworks CSB5 IDE does not fully support native mode */ static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev) { u8 prog; pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); if (prog & 5) { prog &= ~5; pdev->class &= ~5; pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); |
368c73d4f
|
1153 |
/* PCI layer will sort out resources */ |
1da177e4c
|
1154 1155 |
} } |
652c538eb
|
1156 |
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide); |
1da177e4c
|
1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 |
/* * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same */ static void __init quirk_ide_samemode(struct pci_dev *pdev) { u8 prog; pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) { |
f0fda801d
|
1168 1169 |
dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode "); |
1da177e4c
|
1170 1171 1172 |
prog &= ~5; pdev->class &= ~5; pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); |
1da177e4c
|
1173 1174 |
} } |
368c73d4f
|
1175 |
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode); |
1da177e4c
|
1176 |
|
979b1791e
|
1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 |
/* * Some ATA devices break if put into D3 */ static void __devinit quirk_no_ata_d3(struct pci_dev *pdev) { /* Quirk the legacy ATA devices only. The AHCI ones are ok */ if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3; } DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID, quirk_no_ata_d3); DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID, quirk_no_ata_d3); |
7a661c6f1
|
1189 1190 1191 1192 1193 |
/* ALi loses some register settings that we cannot then restore */ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, quirk_no_ata_d3); /* VIA comes back fine but we need to keep it alive or ACPI GTM failures occur when mode detecting */ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_no_ata_d3); |
979b1791e
|
1194 |
|
1da177e4c
|
1195 1196 1197 1198 1199 1200 1201 |
/* This was originally an Alpha specific thing, but it really fits here. * The i82375 PCI/EISA bridge appears as non-classified. Fix that. */ static void __init quirk_eisa_bridge(struct pci_dev *dev) { dev->class = PCI_CLASS_BRIDGE_EISA << 8; } |
652c538eb
|
1202 |
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge); |
1da177e4c
|
1203 |
|
7daa0c4f5
|
1204 1205 |
/* |
1da177e4c
|
1206 1207 1208 1209 1210 1211 1212 1213 |
* On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge * is not activated. The myth is that Asus said that they do not want the * users to be irritated by just another PCI Device in the Win98 device * manager. (see the file prog/hotplug/README.p4b in the lm_sensors * package 2.7.0 for details) * * The SMBus PCI Device can be activated by setting a bit in the ICH LPC * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it |
d7698edca
|
1214 1215 |
* becomes necessary to do this tweak in two steps -- the chosen trigger * is either the Host bridge (preferred) or on-board VGA controller. |
9208ee828
|
1216 1217 1218 1219 1220 1221 1222 |
* * Note that we used to unhide the SMBus that way on Toshiba laptops * (Satellite A40 and Tecra M2) but then found that the thermal management * was done by SMM code, which could cause unsynchronized concurrent * accesses to the SMBus registers, with potentially bad effects. Thus you * should be very careful when adding new entries: if SMM is accessing the * Intel SMBus, this is a very good reason to leave it hidden. |
a99acc832
|
1223 1224 1225 1226 1227 1228 |
* * Likewise, many recent laptops use ACPI for thermal management. If the * ACPI DSDT code accesses the SMBus, then Linux should not access it * natively, and keeping the SMBus hidden is the right thing to do. If you * are about to add an entry in the table below, please first disassemble * the DSDT and double-check that there is no code accessing the SMBus. |
1da177e4c
|
1229 |
*/ |
9d24a81e8
|
1230 |
static int asus_hides_smbus; |
1da177e4c
|
1231 1232 1233 1234 1235 1236 |
static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev) { if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB) switch(dev->subsystem_device) { |
a00db3716
|
1237 |
case 0x8025: /* P4B-LX */ |
1da177e4c
|
1238 1239 1240 1241 1242 |
case 0x8070: /* P4B */ case 0x8088: /* P4B533 */ case 0x1626: /* L3C notebook */ asus_hides_smbus = 1; } |
2f2d39d28
|
1243 |
else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) |
1da177e4c
|
1244 1245 1246 1247 1248 1249 |
switch(dev->subsystem_device) { case 0x80b1: /* P4GE-V */ case 0x80b2: /* P4PE */ case 0x8093: /* P4B533-V */ asus_hides_smbus = 1; } |
2f2d39d28
|
1250 |
else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB) |
1da177e4c
|
1251 1252 1253 1254 |
switch(dev->subsystem_device) { case 0x8030: /* P4T533 */ asus_hides_smbus = 1; } |
2f2d39d28
|
1255 |
else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0) |
1da177e4c
|
1256 1257 1258 1259 |
switch (dev->subsystem_device) { case 0x8070: /* P4G8X Deluxe */ asus_hides_smbus = 1; } |
2f2d39d28
|
1260 |
else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH) |
321311af2
|
1261 1262 1263 1264 |
switch (dev->subsystem_device) { case 0x80c9: /* PU-DLS */ asus_hides_smbus = 1; } |
2f2d39d28
|
1265 |
else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) |
1da177e4c
|
1266 1267 1268 |
switch (dev->subsystem_device) { case 0x1751: /* M2N notebook */ case 0x1821: /* M5N notebook */ |
4096ed0fc
|
1269 |
case 0x1897: /* A6L notebook */ |
1da177e4c
|
1270 1271 |
asus_hides_smbus = 1; } |
2f2d39d28
|
1272 |
else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) |
1da177e4c
|
1273 1274 1275 1276 1277 |
switch (dev->subsystem_device) { case 0x184b: /* W1N notebook */ case 0x186a: /* M6Ne notebook */ asus_hides_smbus = 1; } |
2f2d39d28
|
1278 |
else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) |
2e45785c5
|
1279 1280 1281 1282 |
switch (dev->subsystem_device) { case 0x80f2: /* P4P800-X */ asus_hides_smbus = 1; } |
2f2d39d28
|
1283 |
else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) |
acc06632e
|
1284 1285 |
switch (dev->subsystem_device) { case 0x1882: /* M6V notebook */ |
2d1e1c754
|
1286 |
case 0x1977: /* A6VA notebook */ |
acc06632e
|
1287 1288 |
asus_hides_smbus = 1; } |
1da177e4c
|
1289 1290 1291 1292 1293 1294 1295 |
} else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) { if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) switch(dev->subsystem_device) { case 0x088C: /* HP Compaq nc8000 */ case 0x0890: /* HP Compaq nc6000 */ asus_hides_smbus = 1; } |
2f2d39d28
|
1296 |
else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) |
1da177e4c
|
1297 1298 |
switch (dev->subsystem_device) { case 0x12bc: /* HP D330L */ |
e3b1bd572
|
1299 |
case 0x12bd: /* HP D530 */ |
74c574289
|
1300 |
case 0x006a: /* HP Compaq nx9500 */ |
1da177e4c
|
1301 1302 |
asus_hides_smbus = 1; } |
677cc6443
|
1303 1304 1305 1306 1307 |
else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB) switch (dev->subsystem_device) { case 0x12bf: /* HP xw4100 */ asus_hides_smbus = 1; } |
1da177e4c
|
1308 1309 1310 1311 1312 1313 |
} else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) { if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) switch(dev->subsystem_device) { case 0xC00C: /* Samsung P35 notebook */ asus_hides_smbus = 1; } |
c87f883ed
|
1314 1315 1316 1317 1318 1319 |
} else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) { if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) switch(dev->subsystem_device) { case 0x0058: /* Compaq Evo N620c */ asus_hides_smbus = 1; } |
d7698edca
|
1320 1321 1322 1323 1324 1325 1326 1327 |
else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3) switch(dev->subsystem_device) { case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */ /* Motherboard doesn't have Host bridge * subvendor/subdevice IDs, therefore checking * its on-board VGA controller */ asus_hides_smbus = 1; } |
8293b0f62
|
1328 |
else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2) |
10260d9ab
|
1329 1330 1331 |
switch(dev->subsystem_device) { case 0x00b8: /* Compaq Evo D510 CMT */ case 0x00b9: /* Compaq Evo D510 SFF */ |
6b5096e4d
|
1332 |
case 0x00ba: /* Compaq Evo D510 USDT */ |
8293b0f62
|
1333 1334 1335 1336 1337 |
/* Motherboard doesn't have Host bridge * subvendor/subdevice IDs and on-board VGA * controller is disabled if an AGP card is * inserted, therefore checking USB UHCI * Controller #1 */ |
10260d9ab
|
1338 1339 |
asus_hides_smbus = 1; } |
27e468597
|
1340 1341 1342 1343 1344 1345 1346 1347 |
else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC) switch (dev->subsystem_device) { case 0x001A: /* Compaq Deskpro EN SSF P667 815E */ /* Motherboard doesn't have host bridge * subvendor/subdevice IDs, therefore checking * its on-board VGA controller */ asus_hides_smbus = 1; } |
1da177e4c
|
1348 1349 |
} } |
652c538eb
|
1350 1351 1352 1353 |
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge); |
677cc6443
|
1354 |
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge); |
652c538eb
|
1355 1356 1357 1358 1359 1360 1361 |
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge); |
8293b0f62
|
1362 |
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge); |
27e468597
|
1363 |
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge); |
d7698edca
|
1364 |
|
1597cacbe
|
1365 |
static void asus_hides_smbus_lpc(struct pci_dev *dev) |
1da177e4c
|
1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 |
{ u16 val; if (likely(!asus_hides_smbus)) return; pci_read_config_word(dev, 0xF2, &val); if (val & 0x8) { pci_write_config_word(dev, 0xF2, val & (~0x8)); pci_read_config_word(dev, 0xF2, &val); if (val & 0x8) |
f0fda801d
|
1377 1378 |
dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x ", val); |
1da177e4c
|
1379 |
else |
f0fda801d
|
1380 1381 |
dev_info(&dev->dev, "Enabled i801 SMBus device "); |
1da177e4c
|
1382 1383 |
} } |
652c538eb
|
1384 1385 1386 1387 1388 1389 1390 |
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); |
e1a2a51e6
|
1391 1392 1393 1394 1395 1396 1397 |
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); |
1597cacbe
|
1398 |
|
e1a2a51e6
|
1399 1400 1401 |
/* It appears we just have one such device. If not, we have a warning */ static void __iomem *asus_rcba_base; static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev) |
acc06632e
|
1402 |
{ |
e1a2a51e6
|
1403 |
u32 rcba; |
acc06632e
|
1404 1405 1406 |
if (likely(!asus_hides_smbus)) return; |
e1a2a51e6
|
1407 |
WARN_ON(asus_rcba_base); |
acc06632e
|
1408 |
pci_read_config_dword(dev, 0xF0, &rcba); |
e1a2a51e6
|
1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 |
/* use bits 31:14, 16 kB aligned */ asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000); if (asus_rcba_base == NULL) return; } static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev) { u32 val; if (likely(!asus_hides_smbus || !asus_rcba_base)) return; /* read the Function Disable register, dword mode only */ val = readl(asus_rcba_base + 0x3418); writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */ } static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev) { if (likely(!asus_hides_smbus || !asus_rcba_base)) return; iounmap(asus_rcba_base); asus_rcba_base = NULL; |
f0fda801d
|
1432 1433 |
dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device "); |
acc06632e
|
1434 |
} |
e1a2a51e6
|
1435 1436 1437 1438 1439 1440 1441 |
static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev) { asus_hides_smbus_lpc_ich6_suspend(dev); asus_hides_smbus_lpc_ich6_resume_early(dev); asus_hides_smbus_lpc_ich6_resume(dev); } |
652c538eb
|
1442 |
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6); |
e1a2a51e6
|
1443 1444 1445 |
DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend); DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume); DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early); |
ce007ea59
|
1446 |
|
1da177e4c
|
1447 1448 1449 |
/* * SiS 96x south bridge: BIOS typically hides SMBus device... */ |
1597cacbe
|
1450 |
static void quirk_sis_96x_smbus(struct pci_dev *dev) |
1da177e4c
|
1451 1452 |
{ u8 val = 0; |
1da177e4c
|
1453 |
pci_read_config_byte(dev, 0x77, &val); |
2f5c33b31
|
1454 |
if (val & 0x10) { |
f0fda801d
|
1455 1456 |
dev_info(&dev->dev, "Enabling SiS 96x SMBus "); |
2f5c33b31
|
1457 1458 |
pci_write_config_byte(dev, 0x77, val & ~0x10); } |
1da177e4c
|
1459 |
} |
652c538eb
|
1460 1461 1462 1463 |
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); |
e1a2a51e6
|
1464 1465 1466 1467 |
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); |
1da177e4c
|
1468 |
|
1da177e4c
|
1469 1470 1471 1472 1473 1474 1475 1476 |
/* * ... This is further complicated by the fact that some SiS96x south * bridges pretend to be 85C503/5513 instead. In that case see if we * spotted a compatible north bridge to make sure. * (pci_find_device doesn't work yet) * * We can also enable the sis96x bit in the discovery register.. */ |
1da177e4c
|
1477 |
#define SIS_DETECT_REGISTER 0x40 |
1597cacbe
|
1478 |
static void quirk_sis_503(struct pci_dev *dev) |
1da177e4c
|
1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 |
{ u8 reg; u16 devid; pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®); pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6)); pci_read_config_word(dev, PCI_DEVICE_ID, &devid); if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) { pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg); return; } |
1da177e4c
|
1490 |
/* |
2f5c33b31
|
1491 1492 1493 |
* Ok, it now shows up as a 96x.. run the 96x quirk by * hand in case it has already been processed. * (depends on link order, which is apparently not guaranteed) |
1da177e4c
|
1494 1495 |
*/ dev->device = devid; |
2f5c33b31
|
1496 |
quirk_sis_96x_smbus(dev); |
1da177e4c
|
1497 |
} |
652c538eb
|
1498 |
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); |
e1a2a51e6
|
1499 |
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); |
1da177e4c
|
1500 |
|
1da177e4c
|
1501 |
|
e5548e960
|
1502 1503 1504 1505 1506 1507 |
/* * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller * and MC97 modem controller are disabled when a second PCI soundcard is * present. This patch, tweaking the VT8237 ISA bridge, enables them. * -- bjd */ |
1597cacbe
|
1508 |
static void asus_hides_ac97_lpc(struct pci_dev *dev) |
e5548e960
|
1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 |
{ u8 val; int asus_hides_ac97 = 0; if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { if (dev->device == PCI_DEVICE_ID_VIA_8237) asus_hides_ac97 = 1; } if (!asus_hides_ac97) return; pci_read_config_byte(dev, 0x50, &val); if (val & 0xc0) { pci_write_config_byte(dev, 0x50, val & (~0xc0)); pci_read_config_byte(dev, 0x50, &val); if (val & 0xc0) |
f0fda801d
|
1526 1527 |
dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x ", val); |
e5548e960
|
1528 |
else |
f0fda801d
|
1529 1530 |
dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices "); |
e5548e960
|
1531 1532 |
} } |
652c538eb
|
1533 |
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); |
e1a2a51e6
|
1534 |
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); |
1597cacbe
|
1535 |
|
779670524
|
1536 |
#if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE) |
15e0c6943
|
1537 1538 1539 1540 1541 1542 |
/* * If we are using libata we can drive this chip properly but must * do this early on to make the additional device appear during * the PCI scanning. */ |
5ee2ae7fb
|
1543 |
static void quirk_jmicron_ata(struct pci_dev *pdev) |
15e0c6943
|
1544 |
{ |
e34bb370d
|
1545 |
u32 conf1, conf5, class; |
15e0c6943
|
1546 1547 1548 1549 1550 |
u8 hdr; /* Only poke fn 0 */ if (PCI_FUNC(pdev->devfn)) return; |
5ee2ae7fb
|
1551 1552 |
pci_read_config_dword(pdev, 0x40, &conf1); pci_read_config_dword(pdev, 0x80, &conf5); |
15e0c6943
|
1553 |
|
5ee2ae7fb
|
1554 1555 1556 1557 |
conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */ conf5 &= ~(1 << 24); /* Clear bit 24 */ switch (pdev->device) { |
4daedcfe8
|
1558 1559 |
case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */ case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */ |
5b6ae5ba0
|
1560 |
case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */ |
5ee2ae7fb
|
1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 |
/* The controller should be in single function ahci mode */ conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */ break; case PCI_DEVICE_ID_JMICRON_JMB365: case PCI_DEVICE_ID_JMICRON_JMB366: /* Redirect IDE second PATA port to the right spot */ conf5 |= (1 << 24); /* Fall through */ case PCI_DEVICE_ID_JMICRON_JMB361: case PCI_DEVICE_ID_JMICRON_JMB363: |
5b6ae5ba0
|
1572 |
case PCI_DEVICE_ID_JMICRON_JMB369: |
5ee2ae7fb
|
1573 1574 |
/* Enable dual function mode, AHCI on fn 0, IDE fn1 */ /* Set the class codes correctly and then direct IDE 0 */ |
3a9e3a51d
|
1575 |
conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */ |
5ee2ae7fb
|
1576 1577 1578 1579 1580 1581 |
break; case PCI_DEVICE_ID_JMICRON_JMB368: /* The controller should be in single function IDE mode */ conf1 |= 0x00C00000; /* Set 22, 23 */ break; |
15e0c6943
|
1582 |
} |
5ee2ae7fb
|
1583 1584 1585 1586 1587 1588 1589 1590 |
pci_write_config_dword(pdev, 0x40, conf1); pci_write_config_dword(pdev, 0x80, conf5); /* Update pdev accordingly */ pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr); pdev->hdr_type = hdr & 0x7f; pdev->multifunction = !!(hdr & 0x80); |
e34bb370d
|
1591 1592 1593 |
pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class); pdev->class = class >> 8; |
15e0c6943
|
1594 |
} |
5ee2ae7fb
|
1595 1596 |
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); |
4daedcfe8
|
1597 |
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); |
5ee2ae7fb
|
1598 |
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); |
5b6ae5ba0
|
1599 |
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); |
5ee2ae7fb
|
1600 1601 1602 |
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); |
5b6ae5ba0
|
1603 |
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); |
e1a2a51e6
|
1604 1605 |
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); |
4daedcfe8
|
1606 |
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); |
e1a2a51e6
|
1607 |
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); |
5b6ae5ba0
|
1608 |
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); |
e1a2a51e6
|
1609 1610 1611 |
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); |
5b6ae5ba0
|
1612 |
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); |
15e0c6943
|
1613 1614 |
#endif |
1da177e4c
|
1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 |
#ifdef CONFIG_X86_IO_APIC static void __init quirk_alder_ioapic(struct pci_dev *pdev) { int i; if ((pdev->class >> 8) != 0xff00) return; /* the first BAR is the location of the IO APIC...we must * not touch this (and it's already covered by the fixmap), so * forcibly insert it into the resource tree */ if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0)) insert_resource(&iomem_resource, &pdev->resource[0]); /* The next five BARs all seem to be rubbish, so just clean * them out */ for (i=1; i < 6; i++) { memset(&pdev->resource[i], 0, sizeof(pdev->resource[i])); } } |
652c538eb
|
1636 |
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic); |
1da177e4c
|
1637 |
#endif |
1da177e4c
|
1638 1639 |
static void __devinit quirk_pcie_mch(struct pci_dev *pdev) { |
0ba379ec0
|
1640 1641 |
pci_msi_off(pdev); pdev->no_msi = 1; |
1da177e4c
|
1642 |
} |
652c538eb
|
1643 1644 1645 |
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch); |
1da177e4c
|
1646 |
|
4602b88d9
|
1647 1648 1649 1650 1651 1652 1653 |
/* * It's possible for the MSI to get corrupted if shpc and acpi * are used together on certain PXH-based systems. */ static void __devinit quirk_pcie_pxh(struct pci_dev *dev) { |
f5f2b1312
|
1654 |
pci_msi_off(dev); |
4602b88d9
|
1655 |
dev->no_msi = 1; |
f0fda801d
|
1656 1657 |
dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled "); |
4602b88d9
|
1658 1659 1660 1661 1662 1663 |
} DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh); DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh); DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh); DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh); DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh); |
ffadcc2ff
|
1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 |
/* * Some Intel PCI Express chipsets have trouble with downstream * device power management. */ static void quirk_intel_pcie_pm(struct pci_dev * dev) { pci_pm_d3_delay = 120; dev->no_d1d2 = 1; } DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm); |
4602b88d9
|
1695 |
|
426b3b8d5
|
1696 1697 |
#ifdef CONFIG_X86_IO_APIC /* |
e1d3a9084
|
1698 1699 1700 1701 1702 1703 1704 |
* Boot interrupts on some chipsets cannot be turned off. For these chipsets, * remap the original interrupt in the linux kernel to the boot interrupt, so * that a PCI device's interrupt handler is installed on the boot interrupt * line instead. */ static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev) { |
41b9eb264
|
1705 |
if (noioapicquirk || noioapicreroute) |
e1d3a9084
|
1706 1707 1708 |
return; dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT; |
fdcdaf6c4
|
1709 1710 1711 |
dev_info(&dev->dev, "rerouting interrupts for [%04x:%04x] ", dev->vendor, dev->device); |
e1d3a9084
|
1712 |
} |
88d1dce3a
|
1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728 |
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); |
e1d3a9084
|
1729 1730 |
/* |
426b3b8d5
|
1731 1732 1733 1734 1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749 1750 1751 |
* On some chipsets we can disable the generation of legacy INTx boot * interrupts. */ /* * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no * 300641-004US, section 5.7.3. */ #define INTEL_6300_IOAPIC_ABAR 0x40 #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14) static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev) { u16 pci_config_word; if (noioapicquirk) return; pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word); pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ; pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word); |
fdcdaf6c4
|
1752 1753 1754 |
dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x] ", dev->vendor, dev->device); |
426b3b8d5
|
1755 |
} |
88d1dce3a
|
1756 1757 |
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt); DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt); |
772511881
|
1758 1759 1760 1761 1762 1763 1764 1765 1766 1767 1768 1769 1770 1771 1772 1773 1774 1775 1776 1777 1778 1779 1780 1781 1782 1783 1784 |
/* * disable boot interrupts on HT-1000 */ #define BC_HT1000_FEATURE_REG 0x64 #define BC_HT1000_PIC_REGS_ENABLE (1<<0) #define BC_HT1000_MAP_IDX 0xC00 #define BC_HT1000_MAP_DATA 0xC01 static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev) { u32 pci_config_dword; u8 irq; if (noioapicquirk) return; pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword); pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword | BC_HT1000_PIC_REGS_ENABLE); for (irq = 0x10; irq < 0x10 + 32; irq++) { outb(irq, BC_HT1000_MAP_IDX); outb(0x00, BC_HT1000_MAP_DATA); } pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword); |
fdcdaf6c4
|
1785 1786 1787 |
dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x] ", dev->vendor, dev->device); |
772511881
|
1788 |
} |
88d1dce3a
|
1789 1790 |
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); |
542622da8
|
1791 1792 1793 1794 1795 1796 1797 1798 1799 1800 1801 |
/* * disable boot interrupts on AMD and ATI chipsets */ /* * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode * (due to an erratum). */ #define AMD_813X_MISC 0x40 #define AMD_813X_NOIOAMODE (1<<0) |
4fd8bdc56
|
1802 |
#define AMD_813X_REV_B1 0x12 |
bbe194433
|
1803 |
#define AMD_813X_REV_B2 0x13 |
542622da8
|
1804 1805 1806 1807 1808 1809 1810 |
static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev) { u32 pci_config_dword; if (noioapicquirk) return; |
4fd8bdc56
|
1811 1812 |
if ((dev->revision == AMD_813X_REV_B1) || (dev->revision == AMD_813X_REV_B2)) |
bbe194433
|
1813 |
return; |
542622da8
|
1814 1815 1816 1817 |
pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword); pci_config_dword &= ~AMD_813X_NOIOAMODE; pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword); |
fdcdaf6c4
|
1818 1819 1820 |
dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x] ", dev->vendor, dev->device); |
542622da8
|
1821 |
} |
4fd8bdc56
|
1822 1823 1824 1825 |
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); |
542622da8
|
1826 1827 1828 1829 1830 1831 1832 1833 1834 1835 1836 1837 |
#define AMD_8111_PCI_IRQ_ROUTING 0x56 static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev) { u16 pci_config_word; if (noioapicquirk) return; pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word); if (!pci_config_word) { |
fdcdaf6c4
|
1838 1839 1840 |
dev_info(&dev->dev, "boot interrupts on device [%04x:%04x] " "already disabled ", dev->vendor, dev->device); |
542622da8
|
1841 1842 1843 |
return; } pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0); |
fdcdaf6c4
|
1844 1845 1846 |
dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x] ", dev->vendor, dev->device); |
542622da8
|
1847 |
} |
88d1dce3a
|
1848 1849 |
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); |
426b3b8d5
|
1850 |
#endif /* CONFIG_X86_IO_APIC */ |
33dced2ea
|
1851 1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 |
/* * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes. * Re-allocate the region if needed... */ static void __init quirk_tc86c001_ide(struct pci_dev *dev) { struct resource *r = &dev->resource[0]; if (r->start & 0x8) { r->start = 0; r->end = 0xf; } } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE, quirk_tc86c001_ide); |
1da177e4c
|
1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 |
static void __devinit quirk_netmos(struct pci_dev *dev) { unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; unsigned int num_serial = dev->subsystem_device & 0xf; /* * These Netmos parts are multiport serial devices with optional * parallel ports. Even when parallel ports are present, they * are identified as class SERIAL, which means the serial driver * will claim them. To prevent this, mark them as class OTHER. * These combo devices should be claimed by parport_serial. * * The subdevice ID is of the form 0x00PS, where <P> is the number * of parallel ports and <S> is the number of serial ports. */ switch (dev->device) { |
4c9c16867
|
1884 1885 1886 1887 1888 |
case PCI_DEVICE_ID_NETMOS_9835: /* Well, this rule doesn't hold for the following 9835 device */ if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && dev->subsystem_device == 0x0299) return; |
1da177e4c
|
1889 1890 |
case PCI_DEVICE_ID_NETMOS_9735: case PCI_DEVICE_ID_NETMOS_9745: |
1da177e4c
|
1891 1892 1893 1894 |
case PCI_DEVICE_ID_NETMOS_9845: case PCI_DEVICE_ID_NETMOS_9855: if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL && num_parallel) { |
f0fda801d
|
1895 |
dev_info(&dev->dev, "Netmos %04x (%u parallel, " |
1da177e4c
|
1896 1897 1898 1899 1900 1901 1902 1903 1904 1905 |
"%u serial); changing class SERIAL to OTHER " "(use parport_serial) ", dev->device, num_parallel, num_serial); dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) | (dev->class & 0xff); } } } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos); |
16a747442
|
1906 1907 |
static void __devinit quirk_e100_interrupt(struct pci_dev *dev) { |
e64aeccbe
|
1908 |
u16 command, pmcsr; |
16a747442
|
1909 1910 |
u8 __iomem *csr; u8 cmd_hi; |
e64aeccbe
|
1911 |
int pm; |
16a747442
|
1912 1913 1914 1915 1916 1917 1918 1919 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936 1937 1938 1939 1940 |
switch (dev->device) { /* PCI IDs taken from drivers/net/e100.c */ case 0x1029: case 0x1030 ... 0x1034: case 0x1038 ... 0x103E: case 0x1050 ... 0x1057: case 0x1059: case 0x1064 ... 0x106B: case 0x1091 ... 0x1095: case 0x1209: case 0x1229: case 0x2449: case 0x2459: case 0x245D: case 0x27DC: break; default: return; } /* * Some firmware hands off the e100 with interrupts enabled, * which can cause a flood of interrupts if packets are * received before the driver attaches to the device. So * disable all e100 interrupts here. The driver will * re-enable them when it's ready. */ pci_read_config_word(dev, PCI_COMMAND, &command); |
16a747442
|
1941 |
|
1bef7dc00
|
1942 |
if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0)) |
16a747442
|
1943 |
return; |
e64aeccbe
|
1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 |
/* * Check that the device is in the D0 power state. If it's not, * there is no point to look any further. */ pm = pci_find_capability(dev, PCI_CAP_ID_PM); if (pm) { pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr); if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) return; } |
1bef7dc00
|
1954 1955 |
/* Convert from PCI bus to resource space. */ csr = ioremap(pci_resource_start(dev, 0), 8); |
16a747442
|
1956 |
if (!csr) { |
f0fda801d
|
1957 1958 |
dev_warn(&dev->dev, "Can't map e100 registers "); |
16a747442
|
1959 1960 1961 1962 1963 |
return; } cmd_hi = readb(csr + 3); if (cmd_hi == 0) { |
f0fda801d
|
1964 1965 1966 |
dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; " "disabling "); |
16a747442
|
1967 1968 1969 1970 1971 |
writeb(1, csr + 3); } iounmap(csr); } |
4e68fc97b
|
1972 |
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_e100_interrupt); |
a5312e28c
|
1973 |
|
649426efc
|
1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 |
/* * The 82575 and 82598 may experience data corruption issues when transitioning * out of L0S. To prevent this we need to disable L0S on the pci-e link */ static void __devinit quirk_disable_aspm_l0s(struct pci_dev *dev) { dev_info(&dev->dev, "Disabling L0s "); pci_disable_link_state(dev, PCIE_LINK_STATE_L0S); } DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s); |
a5312e28c
|
1998 1999 2000 2001 2002 2003 2004 |
static void __devinit fixup_rev1_53c810(struct pci_dev* dev) { /* rev 1 ncr53c810 chips don't set the class at all which means * they don't get their resources remapped. Fix that here. */ if (dev->class == PCI_CLASS_NOT_DEFINED) { |
f0fda801d
|
2005 2006 |
dev_info(&dev->dev, "NCR 53c810 rev 1 detected; setting PCI class "); |
a5312e28c
|
2007 2008 2009 2010 |
dev->class = PCI_CLASS_STORAGE_SCSI; } } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810); |
9d265124d
|
2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 |
/* Enable 1k I/O space granularity on the Intel P64H2 */ static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev) { u16 en1k; u8 io_base_lo, io_limit_lo; unsigned long base, limit; struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES; pci_read_config_word(dev, 0x40, &en1k); if (en1k & 0x200) { |
f0fda801d
|
2022 2023 |
dev_info(&dev->dev, "Enable I/O Space to 1KB granularity "); |
9d265124d
|
2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 |
pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); base = (io_base_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8; limit = (io_limit_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8; if (base <= limit) { res->start = base; res->end = limit + 0x3ff; } } } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io); |
15a260d53
|
2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 |
/* Fix the IOBL_ADR for 1k I/O space granularity on the Intel P64H2 * The IOBL_ADR gets re-written to 4k boundaries in pci_setup_bridge() * in drivers/pci/setup-bus.c */ static void __devinit quirk_p64h2_1k_io_fix_iobl(struct pci_dev *dev) { u16 en1k, iobl_adr, iobl_adr_1k; struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES; pci_read_config_word(dev, 0x40, &en1k); if (en1k & 0x200) { pci_read_config_word(dev, PCI_IO_BASE, &iobl_adr); iobl_adr_1k = iobl_adr | (res->start >> 8) | (res->end & 0xfc00); if (iobl_adr != iobl_adr_1k) { |
f0fda801d
|
2054 2055 |
dev_info(&dev->dev, "Fixing P64H2 IOBL_ADR from 0x%x to 0x%x for 1KB granularity ", |
15a260d53
|
2056 2057 2058 2059 2060 2061 |
iobl_adr,iobl_adr_1k); pci_write_config_word(dev, PCI_IO_BASE, iobl_adr_1k); } } } DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io_fix_iobl); |
cf34a8e07
|
2062 2063 2064 2065 |
/* Under some circumstances, AER is not linked with extended capabilities. * Force it to be linked by setting the corresponding control bit in the * config space. */ |
1597cacbe
|
2066 |
static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev) |
cf34a8e07
|
2067 2068 2069 2070 2071 |
{ uint8_t b; if (pci_read_config_byte(dev, 0xf41, &b) == 0) { if (!(b & 0x20)) { pci_write_config_byte(dev, 0xf41, b | 0x20); |
f0fda801d
|
2072 2073 2074 |
dev_info(&dev->dev, "Linking AER extended capability "); |
cf34a8e07
|
2075 2076 2077 2078 2079 |
} } } DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, quirk_nvidia_ck804_pcie_aer_ext_cap); |
e1a2a51e6
|
2080 |
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, |
1597cacbe
|
2081 |
quirk_nvidia_ck804_pcie_aer_ext_cap); |
cf34a8e07
|
2082 |
|
53a9bf426
|
2083 2084 2085 2086 2087 |
static void __devinit quirk_via_cx700_pci_parking_caching(struct pci_dev *dev) { /* * Disable PCI Bus Parking and PCI Master read caching on CX700 * which causes unspecified timing errors with a VT6212L on the PCI |
ca8463926
|
2088 2089 2090 2091 2092 |
* bus leading to USB2.0 packet loss. * * This quirk is only enabled if a second (on the external PCI bus) * VT6212L is found -- the CX700 core itself also contains a USB * host controller with the same PCI ID as the VT6212L. |
53a9bf426
|
2093 |
*/ |
ca8463926
|
2094 2095 2096 |
/* Count VT6212L instances */ struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, NULL); |
53a9bf426
|
2097 |
uint8_t b; |
ca8463926
|
2098 2099 2100 2101 2102 2103 2104 |
/* p should contain the first (internal) VT6212L -- see if we have an external one by searching again */ p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p); if (!p) return; pci_dev_put(p); |
53a9bf426
|
2105 2106 2107 2108 |
if (pci_read_config_byte(dev, 0x76, &b) == 0) { if (b & 0x40) { /* Turn off PCI Bus Parking */ pci_write_config_byte(dev, 0x76, b ^ 0x40); |
bc0432745
|
2109 2110 2111 2112 2113 2114 2115 2116 |
dev_info(&dev->dev, "Disabling VIA CX700 PCI parking "); } } if (pci_read_config_byte(dev, 0x72, &b) == 0) { if (b != 0) { |
53a9bf426
|
2117 2118 |
/* Turn off PCI Master read caching */ pci_write_config_byte(dev, 0x72, 0x0); |
bc0432745
|
2119 2120 |
/* Set PCI Master Bus time-out to "1x16 PCLK" */ |
53a9bf426
|
2121 |
pci_write_config_byte(dev, 0x75, 0x1); |
bc0432745
|
2122 2123 |
/* Disable "Read FIFO Timer" */ |
53a9bf426
|
2124 |
pci_write_config_byte(dev, 0x77, 0x0); |
d6505a523
|
2125 |
dev_info(&dev->dev, |
bc0432745
|
2126 2127 |
"Disabling VIA CX700 PCI caching "); |
53a9bf426
|
2128 2129 2130 |
} } } |
ca8463926
|
2131 |
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching); |
53a9bf426
|
2132 |
|
99cb233d6
|
2133 2134 2135 2136 2137 2138 2139 2140 2141 2142 2143 2144 2145 |
/* * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the * VPD end tag will hang the device. This problem was initially * observed when a vpd entry was created in sysfs * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry * will dump 32k of data. Reading a full 32k will cause an access * beyond the VPD end tag causing the device to hang. Once the device * is hung, the bnx2 driver will not be able to reset the device. * We believe that it is legal to read beyond the end tag and * therefore the solution is to limit the read/write length. */ static void __devinit quirk_brcm_570x_limit_vpd(struct pci_dev *dev) { |
9d82d8eae
|
2146 |
/* |
35405f256
|
2147 2148 |
* Only disable the VPD capability for 5706, 5706S, 5708, * 5708S and 5709 rev. A |
9d82d8eae
|
2149 |
*/ |
99cb233d6
|
2150 |
if ((dev->device == PCI_DEVICE_ID_NX2_5706) || |
35405f256
|
2151 |
(dev->device == PCI_DEVICE_ID_NX2_5706S) || |
99cb233d6
|
2152 |
(dev->device == PCI_DEVICE_ID_NX2_5708) || |
9d82d8eae
|
2153 |
(dev->device == PCI_DEVICE_ID_NX2_5708S) || |
99cb233d6
|
2154 2155 2156 2157 2158 2159 |
((dev->device == PCI_DEVICE_ID_NX2_5709) && (dev->revision & 0xf0) == 0x0)) { if (dev->vpd) dev->vpd->len = 0x80; } } |
bffadffd4
|
2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175 2176 2177 |
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706, quirk_brcm_570x_limit_vpd); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S, quirk_brcm_570x_limit_vpd); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708, quirk_brcm_570x_limit_vpd); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S, quirk_brcm_570x_limit_vpd); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709, quirk_brcm_570x_limit_vpd); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S, quirk_brcm_570x_limit_vpd); |
99cb233d6
|
2178 |
|
26c56dc0c
|
2179 2180 2181 2182 2183 2184 2185 2186 2187 2188 2189 2190 2191 2192 2193 2194 2195 2196 2197 2198 2199 |
/* Originally in EDAC sources for i82875P: * Intel tells BIOS developers to hide device 6 which * configures the overflow device access containing * the DRBs - this is where we expose device 6. * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm */ static void __devinit quirk_unhide_mch_dev6(struct pci_dev *dev) { u8 reg; if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) { dev_info(&dev->dev, "Enabling MCH 'Overflow' Device "); pci_write_config_byte(dev, 0xF4, reg | 0x02); } } DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, quirk_unhide_mch_dev6); DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, quirk_unhide_mch_dev6); |
f02cbbe65
|
2200 2201 2202 2203 2204 2205 2206 2207 2208 2209 2210 2211 2212 2213 2214 2215 2216 2217 |
#ifdef CONFIG_TILE /* * The Tilera TILEmpower platform needs to set the link speed * to 2.5GT(Giga-Transfers)/s (Gen 1). The default link speed * setting is 5GT/s (Gen 2). 0x98 is the Link Control2 PCIe * capability register of the PEX8624 PCIe switch. The switch * supports link speed auto negotiation, but falsely sets * the link speed to 5GT/s. */ static void __devinit quirk_tile_plx_gen1(struct pci_dev *dev) { if (tile_plx_gen1) { pci_write_config_dword(dev, 0x98, 0x1); mdelay(50); } } DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1); #endif /* CONFIG_TILE */ |
26c56dc0c
|
2218 |
|
3f79e107f
|
2219 |
#ifdef CONFIG_PCI_MSI |
ebdf7d399
|
2220 2221 2222 2223 2224 |
/* Some chipsets do not support MSI. We cannot easily rely on setting * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually * some other busses controlled by the chipset even if Linux is not * aware of it. Instead of setting the flag on all busses in the * machine, simply disable MSI globally. |
3f79e107f
|
2225 |
*/ |
ebdf7d399
|
2226 |
static void __init quirk_disable_all_msi(struct pci_dev *dev) |
3f79e107f
|
2227 |
{ |
88187dfa4
|
2228 |
pci_no_msi(); |
f0fda801d
|
2229 2230 |
dev_warn(&dev->dev, "MSI quirk detected; MSI disabled "); |
3f79e107f
|
2231 |
} |
ebdf7d399
|
2232 2233 2234 |
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi); |
66d715c95
|
2235 |
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi); |
184b812f7
|
2236 |
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi); |
162dedd39
|
2237 |
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi); |
549e15611
|
2238 |
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi); |
3f79e107f
|
2239 2240 2241 2242 2243 |
/* Disable MSI on chipsets that are known to not support it */ static void __devinit quirk_disable_msi(struct pci_dev *dev) { if (dev->subordinate) { |
f0fda801d
|
2244 2245 2246 |
dev_warn(&dev->dev, "MSI quirk detected; " "subordinate MSI disabled "); |
3f79e107f
|
2247 2248 2249 2250 |
dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; } } DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi); |
134b34508
|
2251 |
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi); |
9313ff450
|
2252 |
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi); |
6397c75cb
|
2253 |
|
aff613697
|
2254 2255 2256 2257 2258 2259 2260 2261 2262 2263 2264 2265 2266 2267 2268 2269 2270 2271 2272 |
/* * The APC bridge device in AMD 780 family northbridges has some random * OEM subsystem ID in its vendor ID register (erratum 18), so instead * we use the possible vendor/device IDs of the host bridge for the * declared quirk, and search for the APC bridge by slot number. */ static void __devinit quirk_amd_780_apc_msi(struct pci_dev *host_bridge) { struct pci_dev *apc_bridge; apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0)); if (apc_bridge) { if (apc_bridge->device == 0x9602) quirk_disable_msi(apc_bridge); pci_dev_put(apc_bridge); } } DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi); |
6397c75cb
|
2273 2274 2275 2276 |
/* Go through the list of Hypertransport capabilities and * return 1 if a HT MSI capability is found and enabled */ static int __devinit msi_ht_cap_enabled(struct pci_dev *dev) { |
7a380507c
|
2277 2278 2279 2280 2281 2282 2283 2284 2285 |
int pos, ttl = 48; pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); while (pos && ttl--) { u8 flags; if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, &flags) == 0) { |
f0fda801d
|
2286 2287 |
dev_info(&dev->dev, "Found %s HT MSI Mapping ", |
7a380507c
|
2288 |
flags & HT_MSI_FLAGS_ENABLE ? |
f0fda801d
|
2289 |
"enabled" : "disabled"); |
7a380507c
|
2290 |
return (flags & HT_MSI_FLAGS_ENABLE) != 0; |
6397c75cb
|
2291 |
} |
7a380507c
|
2292 2293 2294 |
pos = pci_find_next_ht_capability(dev, pos, HT_CAPTYPE_MSI_MAPPING); |
6397c75cb
|
2295 2296 2297 2298 2299 2300 2301 2302 |
} return 0; } /* Check the hypertransport MSI mapping to know whether MSI is enabled or not */ static void __devinit quirk_msi_ht_cap(struct pci_dev *dev) { if (dev->subordinate && !msi_ht_cap_enabled(dev)) { |
f0fda801d
|
2303 2304 2305 |
dev_warn(&dev->dev, "MSI quirk detected; " "subordinate MSI disabled "); |
6397c75cb
|
2306 2307 2308 2309 2310 |
dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; } } DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE, quirk_msi_ht_cap); |
6bae1d96c
|
2311 |
|
6397c75cb
|
2312 2313 2314 2315 2316 2317 2318 2319 2320 2321 2322 2323 2324 |
/* The nVidia CK804 chipset may have 2 HT MSI mappings. * MSI are supported if the MSI capability set in any of these mappings. */ static void __devinit quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev) { struct pci_dev *pdev; if (!dev->subordinate) return; /* check HT MSI cap on this chipset and the root one. * a single one having MSI is enough to be sure that MSI are supported. */ |
11f242f04
|
2325 |
pdev = pci_get_slot(dev->bus, 0); |
9ac0ce859
|
2326 2327 |
if (!pdev) return; |
0c875c286
|
2328 |
if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) { |
f0fda801d
|
2329 2330 2331 |
dev_warn(&dev->dev, "MSI quirk detected; " "subordinate MSI disabled "); |
6397c75cb
|
2332 2333 |
dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; } |
11f242f04
|
2334 |
pci_dev_put(pdev); |
6397c75cb
|
2335 2336 2337 |
} DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, quirk_nvidia_ck804_msi_ht_cap); |
ba698ad4b
|
2338 |
|
415b6d0e8
|
2339 2340 |
/* Force enable MSI mapping capability on HT bridges */ static void __devinit ht_enable_msi_mapping(struct pci_dev *dev) |
9dc625e72
|
2341 2342 2343 2344 2345 2346 2347 2348 2349 2350 2351 2352 2353 2354 2355 2356 2357 2358 2359 |
{ int pos, ttl = 48; pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); while (pos && ttl--) { u8 flags; if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, &flags) == 0) { dev_info(&dev->dev, "Enabling HT MSI Mapping "); pci_write_config_byte(dev, pos + HT_MSI_FLAGS, flags | HT_MSI_FLAGS_ENABLE); } pos = pci_find_next_ht_capability(dev, pos, HT_CAPTYPE_MSI_MAPPING); } } |
415b6d0e8
|
2360 2361 2362 |
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB, ht_enable_msi_mapping); |
9dc625e72
|
2363 |
|
e0ae4f550
|
2364 2365 |
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, ht_enable_msi_mapping); |
e4146bb90
|
2366 |
/* The P5N32-SLI motherboards from Asus have a problem with msi |
75e07fc3d
|
2367 2368 2369 2370 2371 |
* for the MCP55 NIC. It is not yet determined whether the msi problem * also affects other devices. As for now, turn off msi for this device. */ static void __devinit nvenet_msi_disable(struct pci_dev *dev) { |
9251bac97
|
2372 2373 2374 2375 2376 |
const char *board_name = dmi_get_system_info(DMI_BOARD_NAME); if (board_name && (strstr(board_name, "P5N32-SLI PREMIUM") || strstr(board_name, "P5N32-E SLI"))) { |
75e07fc3d
|
2377 |
dev_info(&dev->dev, |
e4146bb90
|
2378 2379 |
"Disabling msi for MCP55 NIC on P5N32-SLI "); |
75e07fc3d
|
2380 2381 2382 2383 2384 2385 |
dev->no_msi = 1; } } DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15, nvenet_msi_disable); |
66db60eaf
|
2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396 2397 2398 |
/* * Some versions of the MCP55 bridge from nvidia have a legacy irq routing * config register. This register controls the routing of legacy interrupts * from devices that route through the MCP55. If this register is misprogramed * interrupts are only sent to the bsp, unlike conventional systems where the * irq is broadxast to all online cpus. Not having this register set * properly prevents kdump from booting up properly, so lets make sure that * we have it set correctly. * Note this is an undocumented register. */ static void __devinit nvbridge_check_legacy_irq_routing(struct pci_dev *dev) { u32 cfg; |
49c2fa08a
|
2399 2400 |
if (!pci_find_capability(dev, PCI_CAP_ID_HT)) return; |
66db60eaf
|
2401 2402 2403 2404 2405 2406 2407 2408 2409 2410 2411 2412 2413 2414 2415 2416 2417 |
pci_read_config_dword(dev, 0x74, &cfg); if (cfg & ((1 << 2) | (1 << 15))) { printk(KERN_INFO "Rewriting irq routing register on MCP55 "); cfg &= ~((1 << 2) | (1 << 15)); pci_write_config_dword(dev, 0x74, cfg); } } DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0, nvbridge_check_legacy_irq_routing); DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4, nvbridge_check_legacy_irq_routing); |
de7453065
|
2418 2419 2420 2421 2422 2423 2424 2425 2426 2427 2428 2429 2430 2431 2432 2433 2434 2435 2436 2437 2438 2439 2440 2441 2442 2443 2444 2445 2446 2447 2448 2449 2450 2451 2452 2453 2454 2455 2456 2457 2458 2459 2460 2461 2462 2463 2464 2465 2466 2467 2468 2469 2470 2471 2472 2473 2474 2475 |
static int __devinit ht_check_msi_mapping(struct pci_dev *dev) { int pos, ttl = 48; int found = 0; /* check if there is HT MSI cap or enabled on this device */ pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); while (pos && ttl--) { u8 flags; if (found < 1) found = 1; if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, &flags) == 0) { if (flags & HT_MSI_FLAGS_ENABLE) { if (found < 2) { found = 2; break; } } } pos = pci_find_next_ht_capability(dev, pos, HT_CAPTYPE_MSI_MAPPING); } return found; } static int __devinit host_bridge_with_leaf(struct pci_dev *host_bridge) { struct pci_dev *dev; int pos; int i, dev_no; int found = 0; dev_no = host_bridge->devfn >> 3; for (i = dev_no + 1; i < 0x20; i++) { dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0)); if (!dev) continue; /* found next host bridge ?*/ pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); if (pos != 0) { pci_dev_put(dev); break; } if (ht_check_msi_mapping(dev)) { found = 1; pci_dev_put(dev); break; } pci_dev_put(dev); } return found; } |
eeafda70b
|
2476 2477 2478 2479 2480 2481 2482 2483 2484 2485 2486 2487 2488 2489 2490 2491 2492 2493 2494 2495 2496 2497 2498 2499 2500 2501 |
#define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */ #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */ static int __devinit is_end_of_ht_chain(struct pci_dev *dev) { int pos, ctrl_off; int end = 0; u16 flags, ctrl; pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); if (!pos) goto out; pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags); ctrl_off = ((flags >> 10) & 1) ? PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1; pci_read_config_word(dev, pos + ctrl_off, &ctrl); if (ctrl & (1 << 6)) end = 1; out: return end; } |
1dec6b054
|
2502 |
static void __devinit nv_ht_enable_msi_mapping(struct pci_dev *dev) |
9dc625e72
|
2503 2504 |
{ struct pci_dev *host_bridge; |
1dec6b054
|
2505 2506 2507 2508 2509 2510 2511 2512 2513 2514 2515 2516 2517 2518 2519 2520 2521 2522 2523 2524 |
int pos; int i, dev_no; int found = 0; dev_no = dev->devfn >> 3; for (i = dev_no; i >= 0; i--) { host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0)); if (!host_bridge) continue; pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); if (pos != 0) { found = 1; break; } pci_dev_put(host_bridge); } if (!found) return; |
eeafda70b
|
2525 2526 2527 |
/* don't enable end_device/host_bridge with leaf directly here */ if (host_bridge == dev && is_end_of_ht_chain(host_bridge) && host_bridge_with_leaf(host_bridge)) |
de7453065
|
2528 |
goto out; |
1dec6b054
|
2529 2530 2531 2532 2533 2534 2535 2536 2537 2538 2539 2540 2541 2542 2543 2544 2545 2546 2547 2548 |
/* root did that ! */ if (msi_ht_cap_enabled(host_bridge)) goto out; ht_enable_msi_mapping(dev); out: pci_dev_put(host_bridge); } static void __devinit ht_disable_msi_mapping(struct pci_dev *dev) { int pos, ttl = 48; pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); while (pos && ttl--) { u8 flags; if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, &flags) == 0) { |
6a958d5b2
|
2549 2550 |
dev_info(&dev->dev, "Disabling HT MSI Mapping "); |
1dec6b054
|
2551 2552 2553 2554 2555 2556 2557 2558 |
pci_write_config_byte(dev, pos + HT_MSI_FLAGS, flags & ~HT_MSI_FLAGS_ENABLE); } pos = pci_find_next_ht_capability(dev, pos, HT_CAPTYPE_MSI_MAPPING); } } |
de7453065
|
2559 |
static void __devinit __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all) |
1dec6b054
|
2560 2561 2562 2563 |
{ struct pci_dev *host_bridge; int pos; int found; |
3d2a53180
|
2564 2565 |
if (!pci_msi_enabled()) return; |
1dec6b054
|
2566 2567 2568 2569 2570 2571 |
/* check if there is HT MSI cap or enabled on this device */ found = ht_check_msi_mapping(dev); /* no HT MSI CAP */ if (found == 0) return; |
9dc625e72
|
2572 2573 2574 2575 2576 2577 2578 2579 2580 2581 2582 2583 2584 2585 2586 2587 |
/* * HT MSI mapping should be disabled on devices that are below * a non-Hypertransport host bridge. Locate the host bridge... */ host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0)); if (host_bridge == NULL) { dev_warn(&dev->dev, "nv_msi_ht_cap_quirk didn't locate host bridge "); return; } pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); if (pos != 0) { /* Host bridge is to HT */ |
1dec6b054
|
2588 2589 |
if (found == 1) { /* it is not enabled, try to enable it */ |
de7453065
|
2590 2591 2592 2593 |
if (all) ht_enable_msi_mapping(dev); else nv_ht_enable_msi_mapping(dev); |
1dec6b054
|
2594 |
} |
9dc625e72
|
2595 2596 |
return; } |
1dec6b054
|
2597 2598 2599 |
/* HT MSI is not enabled */ if (found == 1) return; |
9dc625e72
|
2600 |
|
1dec6b054
|
2601 2602 |
/* Host bridge is not to HT, disable HT MSI mapping on this device */ ht_disable_msi_mapping(dev); |
9dc625e72
|
2603 |
} |
de7453065
|
2604 2605 2606 2607 2608 2609 2610 2611 2612 2613 2614 2615 |
static void __devinit nv_msi_ht_cap_quirk_all(struct pci_dev *dev) { return __nv_msi_ht_cap_quirk(dev, 1); } static void __devinit nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev) { return __nv_msi_ht_cap_quirk(dev, 0); } DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); |
6dab62ee5
|
2616 |
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); |
de7453065
|
2617 2618 |
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); |
6dab62ee5
|
2619 |
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); |
9dc625e72
|
2620 |
|
ba698ad4b
|
2621 2622 2623 2624 |
static void __devinit quirk_msi_intx_disable_bug(struct pci_dev *dev) { dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; } |
4600c9d74
|
2625 2626 2627 2628 2629 2630 2631 2632 2633 2634 2635 2636 2637 2638 2639 2640 2641 |
static void __devinit quirk_msi_intx_disable_ati_bug(struct pci_dev *dev) { struct pci_dev *p; /* SB700 MSI issue will be fixed at HW level from revision A21, * we need check PCI REVISION ID of SMBus controller to get SB700 * revision. */ p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, NULL); if (!p) return; if ((p->revision < 0x3B) && (p->revision >= 0x30)) dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; pci_dev_put(p); } |
ba698ad4b
|
2642 2643 2644 2645 2646 2647 2648 2649 2650 2651 2652 2653 2654 2655 2656 2657 2658 2659 |
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780, quirk_msi_intx_disable_bug); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S, quirk_msi_intx_disable_bug); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714, quirk_msi_intx_disable_bug); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S, quirk_msi_intx_disable_bug); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715, quirk_msi_intx_disable_bug); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S, quirk_msi_intx_disable_bug); |
bc38b411f
|
2660 |
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390, |
4600c9d74
|
2661 |
quirk_msi_intx_disable_ati_bug); |
bc38b411f
|
2662 |
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391, |
4600c9d74
|
2663 |
quirk_msi_intx_disable_ati_bug); |
bc38b411f
|
2664 |
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392, |
4600c9d74
|
2665 |
quirk_msi_intx_disable_ati_bug); |
bc38b411f
|
2666 |
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393, |
4600c9d74
|
2667 |
quirk_msi_intx_disable_ati_bug); |
bc38b411f
|
2668 |
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394, |
4600c9d74
|
2669 |
quirk_msi_intx_disable_ati_bug); |
bc38b411f
|
2670 2671 2672 2673 2674 2675 2676 |
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373, quirk_msi_intx_disable_bug); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374, quirk_msi_intx_disable_bug); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375, quirk_msi_intx_disable_bug); |
3f79e107f
|
2677 |
#endif /* CONFIG_PCI_MSI */ |
3d1373102
|
2678 |
|
3322340a9
|
2679 2680 2681 2682 2683 2684 2685 2686 2687 2688 2689 2690 |
/* Allow manual resource allocation for PCI hotplug bridges * via pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For * some PCI-PCI hotplug bridges, like PLX 6254 (former HINT HB6), * kernel fails to allocate resources when hotplug device is * inserted and PCI bus is rescanned. */ static void __devinit quirk_hotplug_bridge(struct pci_dev *dev) { dev->is_hotplug_bridge = 1; } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge); |
03cd8f7eb
|
2691 2692 2693 |
/* * This is a quirk for the Ricoh MMC controller found as a part of * some mulifunction chips. |
25985edce
|
2694 |
* This is very similar and based on the ricoh_mmc driver written by |
03cd8f7eb
|
2695 2696 2697 2698 2699 2700 2701 2702 2703 2704 2705 2706 2707 2708 2709 2710 2711 2712 2713 2714 2715 2716 2717 2718 2719 2720 2721 2722 2723 2724 2725 2726 2727 2728 2729 2730 2731 2732 2733 2734 2735 2736 2737 2738 2739 2740 2741 2742 2743 2744 2745 2746 2747 2748 2749 2750 2751 2752 2753 2754 2755 2756 2757 |
* Philip Langdale. Thank you for these magic sequences. * * These chips implement the four main memory card controllers (SD, MMC, MS, xD) * and one or both of cardbus or firewire. * * It happens that they implement SD and MMC * support as separate controllers (and PCI functions). The linux SDHCI * driver supports MMC cards but the chip detects MMC cards in hardware * and directs them to the MMC controller - so the SDHCI driver never sees * them. * * To get around this, we must disable the useless MMC controller. * At that point, the SDHCI controller will start seeing them * It seems to be the case that the relevant PCI registers to deactivate the * MMC controller live on PCI function 0, which might be the cardbus controller * or the firewire controller, depending on the particular chip in question * * This has to be done early, because as soon as we disable the MMC controller * other pci functions shift up one level, e.g. function #2 becomes function * #1, and this will confuse the pci core. */ #ifdef CONFIG_MMC_RICOH_MMC static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev) { /* disable via cardbus interface */ u8 write_enable; u8 write_target; u8 disable; /* disable must be done via function #0 */ if (PCI_FUNC(dev->devfn)) return; pci_read_config_byte(dev, 0xB7, &disable); if (disable & 0x02) return; pci_read_config_byte(dev, 0x8E, &write_enable); pci_write_config_byte(dev, 0x8E, 0xAA); pci_read_config_byte(dev, 0x8D, &write_target); pci_write_config_byte(dev, 0x8D, 0xB7); pci_write_config_byte(dev, 0xB7, disable | 0x02); pci_write_config_byte(dev, 0x8E, write_enable); pci_write_config_byte(dev, 0x8D, write_target); dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via cardbus function) "); dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller "); } DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev) { /* disable via firewire interface */ u8 write_enable; u8 disable; /* disable must be done via function #0 */ if (PCI_FUNC(dev->devfn)) return; |
15bed0f2f
|
2758 2759 2760 2761 2762 2763 2764 2765 2766 2767 2768 2769 2770 2771 2772 2773 2774 2775 2776 2777 2778 2779 2780 |
/* * RICOH 0xe823 SD/MMC card reader fails to recognize * certain types of SD/MMC cards. Lowering the SD base * clock frequency from 200Mhz to 50Mhz fixes this issue. * * 0x150 - SD2.0 mode enable for changing base clock * frequency to 50Mhz * 0xe1 - Base clock frequency * 0x32 - 50Mhz new clock frequency * 0xf9 - Key register for 0x150 * 0xfc - key register for 0xe1 */ if (dev->device == PCI_DEVICE_ID_RICOH_R5CE823) { pci_write_config_byte(dev, 0xf9, 0xfc); pci_write_config_byte(dev, 0x150, 0x10); pci_write_config_byte(dev, 0xf9, 0x00); pci_write_config_byte(dev, 0xfc, 0x01); pci_write_config_byte(dev, 0xe1, 0x32); pci_write_config_byte(dev, 0xfc, 0x00); dev_notice(&dev->dev, "MMC controller base frequency changed to 50Mhz. "); } |
3e309cdf0
|
2781 2782 2783 2784 2785 2786 2787 2788 2789 2790 2791 2792 2793 2794 2795 |
pci_read_config_byte(dev, 0xCB, &disable); if (disable & 0x02) return; pci_read_config_byte(dev, 0xCA, &write_enable); pci_write_config_byte(dev, 0xCA, 0x57); pci_write_config_byte(dev, 0xCB, disable | 0x02); pci_write_config_byte(dev, 0xCA, write_enable); dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via firewire function) "); dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller "); |
03cd8f7eb
|
2796 2797 2798 |
} DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); |
be98ca652
|
2799 2800 |
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832); DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832); |
03cd8f7eb
|
2801 |
#endif /*CONFIG_MMC_RICOH_MMC*/ |
d3f138106
|
2802 |
#ifdef CONFIG_DMAR_TABLE |
254e42006
|
2803 2804 2805 2806 2807 2808 2809 2810 2811 2812 2813 2814 2815 2816 2817 2818 2819 2820 2821 2822 2823 2824 |
#define VTUNCERRMSK_REG 0x1ac #define VTD_MSK_SPEC_ERRORS (1 << 31) /* * This is a quirk for masking vt-d spec defined errors to platform error * handling logic. With out this, platforms using Intel 7500, 5500 chipsets * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based * on the RAS config settings of the platform) when a vt-d fault happens. * The resulting SMI caused the system to hang. * * VT-d spec related errors are already handled by the VT-d OS code, so no * need to report the same error through other channels. */ static void vtd_mask_spec_errors(struct pci_dev *dev) { u32 word; pci_read_config_dword(dev, VTUNCERRMSK_REG, &word); pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS); } DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors); DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors); #endif |
03cd8f7eb
|
2825 |
|
63c440807
|
2826 2827 2828 2829 2830 2831 2832 2833 2834 2835 |
static void __devinit fixup_ti816x_class(struct pci_dev* dev) { /* TI 816x devices do not have class code set when in PCIe boot mode */ if (dev->class == PCI_CLASS_NOT_DEFINED) { dev_info(&dev->dev, "Setting PCI class for 816x PCIe device "); dev->class = PCI_CLASS_MULTIMEDIA_VIDEO; } } DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_TI, 0xb800, fixup_ti816x_class); |
a94d072b2
|
2836 2837 2838 2839 2840 2841 2842 2843 2844 2845 2846 2847 2848 |
/* Some PCIe devices do not work reliably with the claimed maximum * payload size supported. */ static void __devinit fixup_mpss_256(struct pci_dev *dev) { dev->pcie_mpss = 1; /* 256 bytes */ } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE, PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE, PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE, PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256); |
d387a8d66
|
2849 2850 2851 2852 2853 2854 2855 2856 2857 2858 2859 2860 2861 2862 2863 2864 2865 2866 2867 2868 2869 2870 2871 2872 2873 2874 2875 2876 2877 2878 2879 2880 2881 2882 2883 2884 2885 2886 2887 2888 2889 2890 2891 2892 2893 2894 2895 2896 2897 2898 2899 2900 2901 2902 2903 2904 2905 2906 2907 2908 2909 2910 2911 2912 2913 2914 2915 2916 2917 2918 2919 |
/* Intel 5000 and 5100 Memory controllers have an errata with read completion * coalescing (which is enabled by default on some BIOSes) and MPS of 256B. * Since there is no way of knowing what the PCIE MPS on each fabric will be * until all of the devices are discovered and buses walked, read completion * coalescing must be disabled. Unfortunately, it cannot be re-enabled because * it is possible to hotplug a device with MPS of 256B. */ static void __devinit quirk_intel_mc_errata(struct pci_dev *dev) { int err; u16 rcc; if (pcie_bus_config == PCIE_BUS_TUNE_OFF) return; /* Intel errata specifies bits to change but does not say what they are. * Keeping them magical until such time as the registers and values can * be explained. */ err = pci_read_config_word(dev, 0x48, &rcc); if (err) { dev_err(&dev->dev, "Error attempting to read the read " "completion coalescing register. "); return; } if (!(rcc & (1 << 10))) return; rcc &= ~(1 << 10); err = pci_write_config_word(dev, 0x48, rcc); if (err) { dev_err(&dev->dev, "Error attempting to write the read " "completion coalescing register. "); return; } pr_info_once("Read completion coalescing disabled due to hardware " "errata relating to 256B MPS. "); } /* Intel 5000 series memory controllers and ports 2-7 */ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata); /* Intel 5100 series memory controllers and ports 2-7 */ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata); |
bfb0f330a
|
2920 2921 |
static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, struct pci_fixup *end) |
3d1373102
|
2922 2923 2924 |
{ while (f < end) { if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) && |
bfb0f330a
|
2925 |
(f->device == dev->device || f->device == (u16) PCI_ANY_ID)) { |
c9bbb4abb
|
2926 2927 |
dev_dbg(&dev->dev, "calling %pF ", f->hook); |
3d1373102
|
2928 2929 2930 2931 2932 2933 2934 2935 2936 2937 2938 2939 2940 2941 2942 2943 2944 2945 2946 2947 2948 2949 2950 2951 2952 2953 2954 2955 2956 2957 2958 2959 2960 2961 2962 2963 2964 2965 2966 2967 2968 2969 2970 2971 2972 2973 2974 2975 2976 2977 2978 2979 2980 2981 2982 2983 2984 2985 2986 2987 2988 2989 2990 2991 2992 2993 2994 2995 |
f->hook(dev); } f++; } } extern struct pci_fixup __start_pci_fixups_early[]; extern struct pci_fixup __end_pci_fixups_early[]; extern struct pci_fixup __start_pci_fixups_header[]; extern struct pci_fixup __end_pci_fixups_header[]; extern struct pci_fixup __start_pci_fixups_final[]; extern struct pci_fixup __end_pci_fixups_final[]; extern struct pci_fixup __start_pci_fixups_enable[]; extern struct pci_fixup __end_pci_fixups_enable[]; extern struct pci_fixup __start_pci_fixups_resume[]; extern struct pci_fixup __end_pci_fixups_resume[]; extern struct pci_fixup __start_pci_fixups_resume_early[]; extern struct pci_fixup __end_pci_fixups_resume_early[]; extern struct pci_fixup __start_pci_fixups_suspend[]; extern struct pci_fixup __end_pci_fixups_suspend[]; void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) { struct pci_fixup *start, *end; switch(pass) { case pci_fixup_early: start = __start_pci_fixups_early; end = __end_pci_fixups_early; break; case pci_fixup_header: start = __start_pci_fixups_header; end = __end_pci_fixups_header; break; case pci_fixup_final: start = __start_pci_fixups_final; end = __end_pci_fixups_final; break; case pci_fixup_enable: start = __start_pci_fixups_enable; end = __end_pci_fixups_enable; break; case pci_fixup_resume: start = __start_pci_fixups_resume; end = __end_pci_fixups_resume; break; case pci_fixup_resume_early: start = __start_pci_fixups_resume_early; end = __end_pci_fixups_resume_early; break; case pci_fixup_suspend: start = __start_pci_fixups_suspend; end = __end_pci_fixups_suspend; break; default: /* stupid compiler warning, you would think with an enum... */ return; } pci_do_fixups(dev, start, end); } |
93177a748
|
2996 |
EXPORT_SYMBOL(pci_fixup_device); |
8d86fb2c8
|
2997 |
|
000102688
|
2998 |
static int __init pci_apply_final_quirks(void) |
8d86fb2c8
|
2999 3000 |
{ struct pci_dev *dev = NULL; |
ac1aa47b1
|
3001 3002 3003 3004 3005 3006 3007 |
u8 cls = 0; u8 tmp; if (pci_cache_line_size) printk(KERN_DEBUG "PCI: CLS %u bytes ", pci_cache_line_size << 2); |
8d86fb2c8
|
3008 |
|
4e344b1cc
|
3009 |
for_each_pci_dev(dev) { |
8d86fb2c8
|
3010 |
pci_fixup_device(pci_fixup_final, dev); |
ac1aa47b1
|
3011 3012 3013 3014 3015 3016 3017 3018 3019 3020 3021 3022 3023 3024 3025 3026 3027 3028 3029 3030 3031 3032 3033 |
/* * If arch hasn't set it explicitly yet, use the CLS * value shared by all PCI devices. If there's a * mismatch, fall back to the default value. */ if (!pci_cache_line_size) { pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp); if (!cls) cls = tmp; if (!tmp || cls == tmp) continue; printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), " "using %u bytes ", cls << 2, tmp << 2, pci_dfl_cache_line_size << 2); pci_cache_line_size = pci_dfl_cache_line_size; } } if (!pci_cache_line_size) { printk(KERN_DEBUG "PCI: CLS %u bytes, default %u ", cls << 2, pci_dfl_cache_line_size << 2); |
2820f333e
|
3034 |
pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size; |
8d86fb2c8
|
3035 3036 3037 3038 |
} return 0; } |
cf6f3bf7e
|
3039 |
fs_initcall_sync(pci_apply_final_quirks); |
b9c3b2664
|
3040 3041 3042 3043 3044 3045 |
/* * Followings are device-specific reset methods which can be used to * reset a single function if other methods (e.g. FLR, PM D0->D3) are * not available. */ |
aeb30016f
|
3046 3047 3048 3049 3050 3051 3052 3053 3054 3055 3056 3057 3058 3059 3060 3061 3062 3063 3064 3065 3066 |
static int reset_intel_generic_dev(struct pci_dev *dev, int probe) { int pos; /* only implement PCI_CLASS_SERIAL_USB at present */ if (dev->class == PCI_CLASS_SERIAL_USB) { pos = pci_find_capability(dev, PCI_CAP_ID_VNDR); if (!pos) return -ENOTTY; if (probe) return 0; pci_write_config_byte(dev, pos + 0x4, 1); msleep(100); return 0; } else { return -ENOTTY; } } |
c763e7b58
|
3067 3068 3069 3070 3071 3072 3073 3074 3075 3076 3077 3078 3079 3080 3081 3082 3083 3084 3085 |
static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe) { int pos; pos = pci_find_capability(dev, PCI_CAP_ID_EXP); if (!pos) return -ENOTTY; if (probe) return 0; pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR); msleep(100); return 0; } #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed |
5b889bf23
|
3086 |
static const struct pci_dev_reset_methods pci_dev_reset_methods[] = { |
c763e7b58
|
3087 3088 |
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF, reset_intel_82599_sfp_virtfn }, |
aeb30016f
|
3089 3090 |
{ PCI_VENDOR_ID_INTEL, PCI_ANY_ID, reset_intel_generic_dev }, |
b9c3b2664
|
3091 3092 |
{ 0 } }; |
5b889bf23
|
3093 3094 3095 |
int pci_dev_specific_reset(struct pci_dev *dev, int probe) { |
df9d1e8a4
|
3096 |
const struct pci_dev_reset_methods *i; |
5b889bf23
|
3097 3098 3099 3100 3101 3102 3103 3104 3105 3106 3107 |
for (i = pci_dev_reset_methods; i->reset; i++) { if ((i->vendor == dev->vendor || i->vendor == (u16)PCI_ANY_ID) && (i->device == dev->device || i->device == (u16)PCI_ANY_ID)) return i->reset(dev, probe); } return -ENOTTY; } |