// SPDX-License-Identifier: GPL-2.0

  /*

   * This file contains work-arounds for many known PCI hardware bugs.
   * Devices present only on certain architectures (host bridges et cetera)
   * should be handled in arch-specific code.

   *

   * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.

   *

   * Copyright (c) 1999 Martin Mares <mj@ucw.cz>

   *

   * Init/reset quirks for USB host controllers should be in the USB quirks
   * file, where their drivers can use them.

   */

  #include <linux/types.h>
  #include <linux/kernel.h>

  #include <linux/export.h>

  #include <linux/pci.h>
  #include <linux/init.h>
  #include <linux/delay.h>

  #include <linux/acpi.h>

  #include <linux/dmi.h>

  #include <linux/ioport.h>

  #include <linux/sched.h>
  #include <linux/ktime.h>

  #include <linux/mm.h>

  #include <linux/nvme.h>

  #include <linux/platform_data/x86/apple.h>

  #include <linux/pm_runtime.h>

  #include <linux/switchtec.h>

  #include <asm/dma.h>	/* isa_dma_bridge_buggy */

  #include "pci.h"

  static ktime_t fixup_debug_start(struct pci_dev *dev,
  				 void (*fn)(struct pci_dev *dev))
  {
  	if (initcall_debug)

  		pci_info(dev, "calling  %pS @ %i
  ", fn, task_pid_nr(current));

  
  	return ktime_get();
  }
  
  static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime,
  			       void (*fn)(struct pci_dev *dev))
  {
  	ktime_t delta, rettime;
  	unsigned long long duration;
  
  	rettime = ktime_get();
  	delta = ktime_sub(rettime, calltime);
  	duration = (unsigned long long) ktime_to_ns(delta) >> 10;
  	if (initcall_debug || duration > 10000)

  		pci_info(dev, "%pS took %lld usecs
  ", fn, duration);

  }
  
  static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
  			  struct pci_fixup *end)
  {
  	ktime_t calltime;
  
  	for (; f < end; f++)
  		if ((f->class == (u32) (dev->class >> f->class_shift) ||
  		     f->class == (u32) PCI_ANY_ID) &&
  		    (f->vendor == dev->vendor ||
  		     f->vendor == (u16) PCI_ANY_ID) &&
  		    (f->device == dev->device ||
  		     f->device == (u16) PCI_ANY_ID)) {

  			void (*hook)(struct pci_dev *dev);
  #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
  			hook = offset_to_ptr(&f->hook_offset);
  #else
  			hook = f->hook;
  #endif
  			calltime = fixup_debug_start(dev, hook);
  			hook(dev);
  			fixup_debug_report(dev, calltime, hook);

  		}
  }
  
  extern struct pci_fixup __start_pci_fixups_early[];
  extern struct pci_fixup __end_pci_fixups_early[];
  extern struct pci_fixup __start_pci_fixups_header[];
  extern struct pci_fixup __end_pci_fixups_header[];
  extern struct pci_fixup __start_pci_fixups_final[];
  extern struct pci_fixup __end_pci_fixups_final[];
  extern struct pci_fixup __start_pci_fixups_enable[];
  extern struct pci_fixup __end_pci_fixups_enable[];
  extern struct pci_fixup __start_pci_fixups_resume[];
  extern struct pci_fixup __end_pci_fixups_resume[];
  extern struct pci_fixup __start_pci_fixups_resume_early[];
  extern struct pci_fixup __end_pci_fixups_resume_early[];
  extern struct pci_fixup __start_pci_fixups_suspend[];
  extern struct pci_fixup __end_pci_fixups_suspend[];
  extern struct pci_fixup __start_pci_fixups_suspend_late[];
  extern struct pci_fixup __end_pci_fixups_suspend_late[];
  
  static bool pci_apply_fixup_final_quirks;
  
  void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
  {
  	struct pci_fixup *start, *end;
  
  	switch (pass) {
  	case pci_fixup_early:
  		start = __start_pci_fixups_early;
  		end = __end_pci_fixups_early;
  		break;
  
  	case pci_fixup_header:
  		start = __start_pci_fixups_header;
  		end = __end_pci_fixups_header;
  		break;
  
  	case pci_fixup_final:
  		if (!pci_apply_fixup_final_quirks)
  			return;
  		start = __start_pci_fixups_final;
  		end = __end_pci_fixups_final;
  		break;
  
  	case pci_fixup_enable:
  		start = __start_pci_fixups_enable;
  		end = __end_pci_fixups_enable;
  		break;
  
  	case pci_fixup_resume:
  		start = __start_pci_fixups_resume;
  		end = __end_pci_fixups_resume;
  		break;
  
  	case pci_fixup_resume_early:
  		start = __start_pci_fixups_resume_early;
  		end = __end_pci_fixups_resume_early;
  		break;
  
  	case pci_fixup_suspend:
  		start = __start_pci_fixups_suspend;
  		end = __end_pci_fixups_suspend;
  		break;
  
  	case pci_fixup_suspend_late:
  		start = __start_pci_fixups_suspend_late;
  		end = __end_pci_fixups_suspend_late;
  		break;
  
  	default:
  		/* stupid compiler warning, you would think with an enum... */
  		return;
  	}
  	pci_do_fixups(dev, start, end);
  }
  EXPORT_SYMBOL(pci_fixup_device);
  
  static int __init pci_apply_final_quirks(void)
  {
  	struct pci_dev *dev = NULL;
  	u8 cls = 0;
  	u8 tmp;
  
  	if (pci_cache_line_size)

  		pr_info("PCI: CLS %u bytes
  ", pci_cache_line_size << 2);

  
  	pci_apply_fixup_final_quirks = true;
  	for_each_pci_dev(dev) {
  		pci_fixup_device(pci_fixup_final, dev);
  		/*
  		 * If arch hasn't set it explicitly yet, use the CLS
  		 * value shared by all PCI devices.  If there's a
  		 * mismatch, fall back to the default value.
  		 */
  		if (!pci_cache_line_size) {
  			pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp);
  			if (!cls)
  				cls = tmp;
  			if (!tmp || cls == tmp)
  				continue;

  			pci_info(dev, "CLS mismatch (%u != %u), using %u bytes
  ",
  			         cls << 2, tmp << 2,
  				 pci_dfl_cache_line_size << 2);

  			pci_cache_line_size = pci_dfl_cache_line_size;
  		}
  	}
  
  	if (!pci_cache_line_size) {

  		pr_info("PCI: CLS %u bytes, default %u
  ", cls << 2,
  			pci_dfl_cache_line_size << 2);

  		pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
  	}
  
  	return 0;
  }
  fs_initcall_sync(pci_apply_final_quirks);

  /*

   * Decoding should be disabled for a PCI device during BAR sizing to avoid
   * conflict. But doing so may cause problems on host bridge and perhaps other
   * key system devices. For devices that need to have mmio decoding always-on,
   * we need to set the dev->mmio_always_on bit.
   */

  static void quirk_mmio_always_on(struct pci_dev *dev)

  {

  	dev->mmio_always_on = 1;

  }

  DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID,
  				PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on);

  /*
   * The Mellanox Tavor device gives false positive parity errors.  Mark this
   * device with a broken_parity_status to allow PCI scanning code to "skip"
   * this now blacklisted device.

   */

  static void quirk_mellanox_tavor(struct pci_dev *dev)

  {
  	dev->broken_parity_status = 1;	/* This device gives false positives */
  }

  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, quirk_mellanox_tavor);
  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, quirk_mellanox_tavor);

  /*
   * Deal with broken BIOSes that neglect to enable passive release,
   * which can cause problems in combination with the 82441FX/PPro MTRRs
   */

  static void quirk_passive_release(struct pci_dev *dev)

  {
  	struct pci_dev *d = NULL;
  	unsigned char dlc;

  	/*
  	 * We have to make sure a particular bit is set in the PIIX3
  	 * ISA bridge, so we have to go out and find it.
  	 */

  	while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
  		pci_read_config_byte(d, 0x82, &dlc);
  		if (!(dlc & 1<<1)) {

  			pci_info(d, "PIIX3: Enabling Passive Release
  ");

  			dlc |= 1<<1;
  			pci_write_config_byte(d, 0x82, dlc);
  		}
  	}
  }

  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82441,	quirk_passive_release);
  DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82441,	quirk_passive_release);

  /*
   * The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a
   * workaround but VIA don't answer queries. If you happen to have good
   * contacts at VIA ask them for me please -- Alan
   *
   * This appears to be BIOS not version dependent. So presumably there is a
   * chipset level fix.
   */

  static void quirk_isa_dma_hangs(struct pci_dev *dev)

  {
  	if (!isa_dma_bridge_buggy) {

  		isa_dma_bridge_buggy = 1;

  		pci_info(dev, "Activating ISA DMA hang workarounds
  ");

  	}
  }

  /*
   * It's not totally clear which chipsets are the problematic ones.  We know
   * 82C586 and 82C596 variants are affected.
   */

  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C586_0,	quirk_isa_dma_hangs);
  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C596,	quirk_isa_dma_hangs);
  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82371SB_0,  quirk_isa_dma_hangs);

  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL,	PCI_DEVICE_ID_AL_M1533,		quirk_isa_dma_hangs);

  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC,	PCI_DEVICE_ID_NEC_CBUS_1,	quirk_isa_dma_hangs);
  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC,	PCI_DEVICE_ID_NEC_CBUS_2,	quirk_isa_dma_hangs);
  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC,	PCI_DEVICE_ID_NEC_CBUS_3,	quirk_isa_dma_hangs);

  /*

   * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear
   * for some HT machines to use C4 w/o hanging.
   */

  static void quirk_tigerpoint_bm_sts(struct pci_dev *dev)

  {
  	u32 pmbase;
  	u16 pm1a;
  
  	pci_read_config_dword(dev, 0x40, &pmbase);
  	pmbase = pmbase & 0xff80;
  	pm1a = inw(pmbase);
  
  	if (pm1a & 0x10) {

  		pci_info(dev, FW_BUG "TigerPoint LPC.BM_STS cleared
  ");

  		outw(0x10, pmbase);
  	}
  }
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts);

  /* Chipsets where PCI->PCI transfers vanish or hang */

  static void quirk_nopcipci(struct pci_dev *dev)

  {

  	if ((pci_pci_problems & PCIPCI_FAIL) == 0) {

  		pci_info(dev, "Disabling direct PCI/PCI transfers
  ");

  		pci_pci_problems |= PCIPCI_FAIL;
  	}
  }

  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_5597,		quirk_nopcipci);
  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_496,		quirk_nopcipci);

  static void quirk_nopciamd(struct pci_dev *dev)

  {
  	u8 rev;
  	pci_read_config_byte(dev, 0x08, &rev);
  	if (rev == 0x13) {
  		/* Erratum 24 */

  		pci_info(dev, "Chipset erratum: Disabling direct PCI/AGP transfers
  ");

  		pci_pci_problems |= PCIAGP_FAIL;
  	}
  }

  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,	PCI_DEVICE_ID_AMD_8151_0,	quirk_nopciamd);

  /* Triton requires workarounds to be used by the drivers */

  static void quirk_triton(struct pci_dev *dev)

  {

  	if ((pci_pci_problems&PCIPCI_TRITON) == 0) {

  		pci_info(dev, "Limiting direct PCI/PCI transfers
  ");

  		pci_pci_problems |= PCIPCI_TRITON;
  	}
  }

  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82437,	quirk_triton);
  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82437VX,	quirk_triton);
  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82439,	quirk_triton);
  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82439TX,	quirk_triton);

  
  /*

   * VIA Apollo KT133 needs PCI latency patch
   * Made according to a Windows driver-based patch by George E. Breese;
   * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
   * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for the info on
   * which Mr Breese based his work.

   *

   * Updated based on further information from the site and also on
   * information provided by VIA

   */

  static void quirk_vialatency(struct pci_dev *dev)

  {
  	struct pci_dev *p;

  	u8 busarb;

  	/*
  	 * Ok, we have a potential problem chipset here. Now see if we have
  	 * a buggy southbridge.
  	 */

  	p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);

  	if (p != NULL) {

  
  		/*
  		 * 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A;
  		 * thanks Dan Hollis.
  		 * Check for buggy part revisions
  		 */

  		if (p->revision < 0x40 || p->revision > 0x42)

  			goto exit;
  	} else {
  		p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);

  		if (p == NULL)	/* No problem parts */

  			goto exit;

  		/* Check for buggy part revisions */

  		if (p->revision < 0x10 || p->revision > 0x12)

  			goto exit;
  	}

  	/*

  	 * Ok we have the problem. Now set the PCI master grant to occur
  	 * every master grant. The apparent bug is that under high PCI load
  	 * (quite common in Linux of course) you can get data loss when the
  	 * CPU is held off the bus for 3 bus master requests.  This happens
  	 * to include the IDE controllers....

  	 *

  	 * VIA only apply this fix when an SB Live! is present but under
  	 * both Linux and Windows this isn't enough, and we have seen
  	 * corruption without SB Live! but with things like 3 UDMA IDE
  	 * controllers. So we ignore that bit of the VIA recommendation..

  	 */

  	pci_read_config_byte(dev, 0x76, &busarb);

  
  	/*
  	 * Set bit 4 and bit 5 of byte 76 to 0x01
  	 * "Master priority rotation on every PCI master grant"
  	 */

  	busarb &= ~(1<<5);
  	busarb |= (1<<4);
  	pci_write_config_byte(dev, 0x76, busarb);

  	pci_info(dev, "Applying VIA southbridge workaround
  ");

  exit:
  	pci_dev_put(p);
  }

  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8363_0,	quirk_vialatency);
  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8371_1,	quirk_vialatency);
  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8361,		quirk_vialatency);

  /* Must restore this on a resume from RAM */

  DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8363_0,	quirk_vialatency);
  DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8371_1,	quirk_vialatency);
  DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8361,		quirk_vialatency);

  /* VIA Apollo VP3 needs ETBF on BT848/878 */

  static void quirk_viaetbf(struct pci_dev *dev)

  {

  	if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) {

  		pci_info(dev, "Limiting direct PCI/PCI transfers
  ");

  		pci_pci_problems |= PCIPCI_VIAETBF;
  	}
  }

  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C597_0,	quirk_viaetbf);

  static void quirk_vsfx(struct pci_dev *dev)

  {

  	if ((pci_pci_problems&PCIPCI_VSFX) == 0) {

  		pci_info(dev, "Limiting direct PCI/PCI transfers
  ");

  		pci_pci_problems |= PCIPCI_VSFX;
  	}
  }

  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C576,	quirk_vsfx);

  
  /*

   * ALi Magik requires workarounds to be used by the drivers that DMA to AGP
   * space. Latency must be set to 0xA and Triton workaround applied too.
   * [Info kindly provided by ALi]

   */

  static void quirk_alimagik(struct pci_dev *dev)

  {

  	if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) {

  		pci_info(dev, "Limiting direct PCI/PCI transfers
  ");

  		pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
  	}
  }

  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL,	PCI_DEVICE_ID_AL_M1647,		quirk_alimagik);
  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL,	PCI_DEVICE_ID_AL_M1651,		quirk_alimagik);

  /* Natoma has some interesting boundary conditions with Zoran stuff at least */

  static void quirk_natoma(struct pci_dev *dev)

  {

  	if ((pci_pci_problems&PCIPCI_NATOMA) == 0) {

  		pci_info(dev, "Limiting direct PCI/PCI transfers
  ");

  		pci_pci_problems |= PCIPCI_NATOMA;
  	}
  }

  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82441,	quirk_natoma);
  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82443LX_0,	quirk_natoma);
  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82443LX_1,	quirk_natoma);
  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82443BX_0,	quirk_natoma);
  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82443BX_1,	quirk_natoma);
  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82443BX_2,	quirk_natoma);

  
  /*

   * This chip can cause PCI parity errors if config register 0xA0 is read
   * while DMAs are occurring.

   */

  static void quirk_citrine(struct pci_dev *dev)

  {
  	dev->cfg_size = 0xA0;
  }

  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM,	PCI_DEVICE_ID_IBM_CITRINE,	quirk_citrine);

  /*
   * This chip can cause bus lockups if config addresses above 0x600
   * are read or written.
   */
  static void quirk_nfp6000(struct pci_dev *dev)
  {
  	dev->cfg_size = 0x600;
  }

  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME,	PCI_DEVICE_ID_NETRONOME_NFP4000,	quirk_nfp6000);

  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME,	PCI_DEVICE_ID_NETRONOME_NFP6000,	quirk_nfp6000);

  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME,	PCI_DEVICE_ID_NETRONOME_NFP5000,	quirk_nfp6000);

  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME,	PCI_DEVICE_ID_NETRONOME_NFP6000_VF,	quirk_nfp6000);

  /*  On IBM Crocodile ipr SAS adapters, expand BAR to system page size */
  static void quirk_extend_bar_to_page(struct pci_dev *dev)
  {
  	int i;

  	for (i = 0; i < PCI_STD_NUM_BARS; i++) {

  		struct resource *r = &dev->resource[i];
  
  		if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) {
  			r->end = PAGE_SIZE - 1;
  			r->start = 0;
  			r->flags |= IORESOURCE_UNSET;

  			pci_info(dev, "expanded BAR %d to page size: %pR
  ",

  				 i, r);
  		}
  	}
  }
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page);

  /*

   * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
   * If it's needed, re-allocate the region.

   */

  static void quirk_s3_64M(struct pci_dev *dev)

  {
  	struct resource *r = &dev->resource[0];
  
  	if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {

  		r->flags |= IORESOURCE_UNSET;

  		r->start = 0;
  		r->end = 0x3ffffff;
  	}
  }

  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3,	PCI_DEVICE_ID_S3_868,		quirk_s3_64M);
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3,	PCI_DEVICE_ID_S3_968,		quirk_s3_64M);

  static void quirk_io(struct pci_dev *dev, int pos, unsigned size,
  		     const char *name)
  {
  	u32 region;
  	struct pci_bus_region bus_region;
  	struct resource *res = dev->resource + pos;
  
  	pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), &region);
  
  	if (!region)
  		return;
  
  	res->name = pci_name(dev);
  	res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK;
  	res->flags |=
  		(IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN);
  	region &= ~(size - 1);
  
  	/* Convert from PCI bus to resource space */
  	bus_region.start = region;
  	bus_region.end = region + size - 1;
  	pcibios_bus_to_resource(dev->bus, res, &bus_region);

  	pci_info(dev, FW_BUG "%s quirk: reg 0x%x: %pR
  ",

  		 name, PCI_BASE_ADDRESS_0 + (pos << 2), res);
  }

  /*
   * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
   * ver. 1.33  20070103) don't set the correct ISA PCI region header info.
   * BAR0 should be 8 bytes; instead, it may be set to something like 8k
   * (which conflicts w/ BAR1's memory range).

   *
   * CS553x's ISA PCI BARs may also be read-only (ref:
   * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward).

   */

  static void quirk_cs5536_vsa(struct pci_dev *dev)

  {

  	static char *name = "CS5536 ISA bridge";

  	if (pci_resource_len(dev, 0) != 8) {

  		quirk_io(dev, 0,   8, name);	/* SMB */
  		quirk_io(dev, 1, 256, name);	/* GPIO */
  		quirk_io(dev, 2,  64, name);	/* MFGPT */

  		pci_info(dev, "%s bug detected (incorrect header); workaround applied
  ",

  			 name);

  	}
  }
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa);

  static void quirk_io_region(struct pci_dev *dev, int port,
  				unsigned size, int nr, const char *name)
  {
  	u16 region;
  	struct pci_bus_region bus_region;
  	struct resource *res = dev->resource + nr;
  
  	pci_read_config_word(dev, port, &region);
  	region &= ~(size - 1);
  
  	if (!region)
  		return;
  
  	res->name = pci_name(dev);
  	res->flags = IORESOURCE_IO;
  
  	/* Convert from PCI bus to resource space */
  	bus_region.start = region;
  	bus_region.end = region + size - 1;

  	pcibios_bus_to_resource(dev->bus, res, &bus_region);

  
  	if (!pci_claim_resource(dev, nr))

  		pci_info(dev, "quirk: %pR claimed by %s
  ", res, name);

  }

  
  /*

   * ATI Northbridge setups MCE the processor if you even read somewhere
   * between 0x3b0->0x3bb or read 0x3d3

   */

  static void quirk_ati_exploding_mce(struct pci_dev *dev)

  {

  	pci_info(dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb
  ");

  	/* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
  	request_region(0x3b0, 0x0C, "RadeonIGP");
  	request_region(0x3d3, 0x01, "RadeonIGP");
  }

  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI,	PCI_DEVICE_ID_ATI_RS100,   quirk_ati_exploding_mce);

  
  /*

   * In the AMD NL platform, this device ([1022:7912]) has a class code of
   * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will
   * claim it.

   *

   * But the dwc3 driver is a more specific driver for this device, and we'd
   * prefer to use it instead of xhci. To prevent xhci from claiming the
   * device, change the class code to 0x0c03fe, which the PCI r3.0 spec
   * defines as "USB device (not host controller)". The dwc3 driver can then
   * claim it based on its Vendor and Device ID.
   */
  static void quirk_amd_nl_class(struct pci_dev *pdev)
  {

  	u32 class = pdev->class;
  
  	/* Use "USB Device (not host controller)" class */

  	pdev->class = PCI_CLASS_SERIAL_USB_DEVICE;

  	pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci
  ",

  		 class, pdev->class);

  }
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB,
  		quirk_amd_nl_class);
  
  /*

   * Synopsys USB 3.x host HAPS platform has a class code of
   * PCI_CLASS_SERIAL_USB_XHCI, and xhci driver can claim it.  However, these
   * devices should use dwc3-haps driver.  Change these devices' class code to
   * PCI_CLASS_SERIAL_USB_DEVICE to prevent the xhci-pci driver from claiming
   * them.
   */
  static void quirk_synopsys_haps(struct pci_dev *pdev)
  {
  	u32 class = pdev->class;
  
  	switch (pdev->device) {
  	case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3:
  	case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI:
  	case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31:
  		pdev->class = PCI_CLASS_SERIAL_USB_DEVICE;
  		pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci
  ",
  			 class, pdev->class);
  		break;
  	}
  }

  DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_SYNOPSYS, PCI_ANY_ID,
  			       PCI_CLASS_SERIAL_USB_XHCI, 0,
  			       quirk_synopsys_haps);

  
  /*

   * Let's make the southbridge information explicit instead of having to
   * worry about people probing the ACPI areas, for example.. (Yes, it
   * happens, and if you read the wrong ACPI register it will put the machine
   * to sleep with no way of waking it up again. Bummer).

   *
   * ALI M7101: Two IO regions pointed to by words at
   *	0xE0 (64 bytes of ACPI registers)
   *	0xE2 (32 bytes of SMB registers)
   */

  static void quirk_ali7101_acpi(struct pci_dev *dev)

  {

  	quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
  	quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");

  }

  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL,	PCI_DEVICE_ID_AL_M7101,		quirk_ali7101_acpi);

  static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
  {
  	u32 devres;
  	u32 mask, size, base;
  
  	pci_read_config_dword(dev, port, &devres);
  	if ((devres & enable) != enable)
  		return;
  	mask = (devres >> 16) & 15;
  	base = devres & 0xffff;
  	size = 16;
  	for (;;) {
  		unsigned bit = size >> 1;
  		if ((bit & mask) == bit)
  			break;
  		size = bit;
  	}
  	/*
  	 * For now we only print it out. Eventually we'll want to
  	 * reserve it (at least if it's in the 0x1000+ range), but

  	 * let's get enough confirmation reports first.

  	 */
  	base &= -size;

  	pci_info(dev, "%s PIO at %04x-%04x
  ", name, base, base + size - 1);

  }
  
  static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
  {
  	u32 devres;
  	u32 mask, size, base;
  
  	pci_read_config_dword(dev, port, &devres);
  	if ((devres & enable) != enable)
  		return;
  	base = devres & 0xffff0000;
  	mask = (devres & 0x3f) << 16;
  	size = 128 << 16;
  	for (;;) {
  		unsigned bit = size >> 1;
  		if ((bit & mask) == bit)
  			break;
  		size = bit;
  	}

  	/*
  	 * For now we only print it out. Eventually we'll want to

  	 * reserve it, but let's get enough confirmation reports first.

  	 */
  	base &= -size;

  	pci_info(dev, "%s MMIO at %04x-%04x
  ", name, base, base + size - 1);

  }

  /*
   * PIIX4 ACPI: Two IO regions pointed to by longwords at
   *	0x40 (64 bytes of ACPI registers)

   *	0x90 (16 bytes of SMB registers)

   * and a few strange programmable PIIX4 device resources.

   */

  static void quirk_piix4_acpi(struct pci_dev *dev)

  {

  	u32 res_a;

  	quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
  	quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");

  
  	/* Device resource A has enables for some of the other ones */
  	pci_read_config_dword(dev, 0x5c, &res_a);
  
  	piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
  	piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
  
  	/* Device resource D is just bitfields for static resources */
  
  	/* Device 12 enabled? */
  	if (res_a & (1 << 29)) {
  		piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
  		piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
  	}
  	/* Device 13 enabled? */
  	if (res_a & (1 << 30)) {
  		piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
  		piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
  	}
  	piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
  	piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);

  }

  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82371AB_3,	quirk_piix4_acpi);
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82443MX_3,	quirk_piix4_acpi);

  #define ICH_PMBASE	0x40
  #define ICH_ACPI_CNTL	0x44
  #define  ICH4_ACPI_EN	0x10
  #define  ICH6_ACPI_EN	0x80
  #define ICH4_GPIOBASE	0x58
  #define ICH4_GPIO_CNTL	0x5c
  #define  ICH4_GPIO_EN	0x10
  #define ICH6_GPIOBASE	0x48
  #define ICH6_GPIO_CNTL	0x4c
  #define  ICH6_GPIO_EN	0x10

  /*
   * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
   *	0x40 (128 bytes of ACPI, GPIO & TCO registers)
   *	0x58 (64 bytes of GPIO I/O space)
   */

  static void quirk_ich4_lpc_acpi(struct pci_dev *dev)

  {

  	u8 enable;

  	/*
  	 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict
  	 * with low legacy (and fixed) ports. We don't know the decoding
  	 * priority and can't tell whether the legacy device or the one created
  	 * here is really at that address.  This happens on boards with broken
  	 * BIOSes.

  	 */

  	pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);

  	if (enable & ICH4_ACPI_EN)
  		quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
  				 "ICH4 ACPI/GPIO/TCO");

  	pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable);

  	if (enable & ICH4_GPIO_EN)
  		quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
  				"ICH4 GPIO");

  }

  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801AA_0,		quirk_ich4_lpc_acpi);
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801AB_0,		quirk_ich4_lpc_acpi);
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801BA_0,		quirk_ich4_lpc_acpi);
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801BA_10,	quirk_ich4_lpc_acpi);
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801CA_0,		quirk_ich4_lpc_acpi);
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801CA_12,	quirk_ich4_lpc_acpi);
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801DB_0,		quirk_ich4_lpc_acpi);
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801DB_12,	quirk_ich4_lpc_acpi);
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801EB_0,		quirk_ich4_lpc_acpi);
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_ESB_1,		quirk_ich4_lpc_acpi);

  static void ich6_lpc_acpi_gpio(struct pci_dev *dev)

  {

  	u8 enable;

  	pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);

  	if (enable & ICH6_ACPI_EN)
  		quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
  				 "ICH6 ACPI/GPIO/TCO");

  	pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable);

  	if (enable & ICH6_GPIO_EN)
  		quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
  				"ICH6 GPIO");

  }

  static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg,
  				    const char *name, int dynsize)

  {
  	u32 val;
  	u32 size, base;
  
  	pci_read_config_dword(dev, reg, &val);
  
  	/* Enabled? */
  	if (!(val & 1))
  		return;
  	base = val & 0xfffc;
  	if (dynsize) {
  		/*
  		 * This is not correct. It is 16, 32 or 64 bytes depending on
  		 * register D31:F0:ADh bits 5:4.
  		 *
  		 * But this gets us at least _part_ of it.
  		 */
  		size = 16;
  	} else {
  		size = 128;
  	}
  	base &= ~(size-1);

  	/*
  	 * Just print it out for now. We should reserve it after more
  	 * debugging.
  	 */

  	pci_info(dev, "%s PIO at %04x-%04x
  ", name, base, base+size-1);

  }

  static void quirk_ich6_lpc(struct pci_dev *dev)

  {
  	/* Shared ACPI/GPIO decode with all ICH6+ */
  	ich6_lpc_acpi_gpio(dev);
  
  	/* ICH6-specific generic IO decode */
  	ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
  	ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
  }
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);

  static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg,
  				    const char *name)

  {
  	u32 val;
  	u32 mask, base;
  
  	pci_read_config_dword(dev, reg, &val);
  
  	/* Enabled? */
  	if (!(val & 1))
  		return;

  	/* IO base in bits 15:2, mask in bits 23:18, both are dword-based */

  	base = val & 0xfffc;
  	mask = (val >> 16) & 0xfc;
  	mask |= 3;

  	/*
  	 * Just print it out for now. We should reserve it after more
  	 * debugging.
  	 */

  	pci_info(dev, "%s PIO at %04x (mask %04x)
  ", name, base, mask);

  }
  
  /* ICH7-10 has the same common LPC generic IO decode registers */

  static void quirk_ich7_lpc(struct pci_dev *dev)

  {

  	/* We share the common ACPI/GPIO decode with ICH6 */

  	ich6_lpc_acpi_gpio(dev);
  
  	/* And have 4 ICH7+ generic decodes */
  	ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
  	ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
  	ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
  	ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
  }
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);

  /*
   * VIA ACPI: One IO region pointed to by longword at
   *	0x48 or 0x20 (256 bytes of ACPI registers)
   */

  static void quirk_vt82c586_acpi(struct pci_dev *dev)

  {

  	if (dev->revision & 0x10)
  		quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES,
  				"vt82c586 ACPI");

  }

  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C586_3,	quirk_vt82c586_acpi);

  
  /*
   * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
   *	0x48 (256 bytes of ACPI registers)
   *	0x70 (128 bytes of hardware monitoring register)
   *	0x90 (16 bytes of SMB registers)
   */

  static void quirk_vt82c686_acpi(struct pci_dev *dev)

  {

  	quirk_vt82c586_acpi(dev);

  	quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1,
  				 "vt82c686 HW-mon");

  	quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB");

  }

  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C686_4,	quirk_vt82c686_acpi);

  /*
   * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
   *	0x88 (128 bytes of power management registers)
   *	0xd0 (16 bytes of SMB registers)
   */

  static void quirk_vt8235_acpi(struct pci_dev *dev)

  {

  	quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
  	quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB");

  }
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8235,	quirk_vt8235_acpi);

  /*

   * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast
   * back-to-back: Disable fast back-to-back on the secondary bus segment

   */

  static void quirk_xio2000a(struct pci_dev *dev)

  {
  	struct pci_dev *pdev;
  	u16 command;

  	pci_warn(dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled
  ");

  	list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
  		pci_read_config_word(pdev, PCI_COMMAND, &command);
  		if (command & PCI_COMMAND_FAST_BACK)
  			pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK);
  	}
  }
  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
  			quirk_xio2000a);

  #ifdef CONFIG_X86_IO_APIC

  
  #include <asm/io_apic.h>
  
  /*
   * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
   * devices to the external APIC.
   *

   * TODO: When we have device-specific interrupt routers, this code will go
   * away from quirks.

   */

  static void quirk_via_ioapic(struct pci_dev *dev)

  {
  	u8 tmp;

  	if (nr_ioapics < 1)
  		tmp = 0;    /* nothing routed to external APIC */
  	else
  		tmp = 0x1f; /* all known bits (4-0) routed to external APIC */

  	pci_info(dev, "%sbling VIA external APIC routing
  ",

  	       tmp == 0 ? "Disa" : "Ena");
  
  	/* Offset 0x58: External APIC IRQ output control */

  	pci_write_config_byte(dev, 0x58, tmp);

  }

  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C686,	quirk_via_ioapic);

  DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C686,	quirk_via_ioapic);

  
  /*

   * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit.

   * This leads to doubled level interrupt rates.
   * Set this bit to get rid of cycle wastage.
   * Otherwise uncritical.
   */

  static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)

  {
  	u8 misc_control2;
  #define BYPASS_APIC_DEASSERT 8
  
  	pci_read_config_byte(dev, 0x5B, &misc_control2);
  	if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {

  		pci_info(dev, "Bypassing VIA 8237 APIC De-Assert Message
  ");

  		pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
  	}
  }
  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8237,		quirk_via_vt8237_bypass_apic_deassert);

  DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8237,		quirk_via_vt8237_bypass_apic_deassert);

  
  /*

   * The AMD IO-APIC can hang the box when an APIC IRQ is masked.

   * We check all revs >= B0 (yet not in the pre production!) as the bug
   * is currently marked NoFix
   *
   * We have multiple reports of hangs with this chipset that went away with

   * noapic specified. For the moment we assume it's the erratum. We may be wrong

   * of course. However the advice is demonstrably good even if so.

   */

  static void quirk_amd_ioapic(struct pci_dev *dev)

  {

  	if (dev->revision >= 0x02) {

  		pci_warn(dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try
  ");
  		pci_warn(dev, "        : booting with the \"noapic\" option
  ");

  	}
  }

  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,	PCI_DEVICE_ID_AMD_VIPER_7410,	quirk_amd_ioapic);

  #endif /* CONFIG_X86_IO_APIC */

  #if defined(CONFIG_ARM64) && defined(CONFIG_PCI_ATS)

  
  static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev)
  {

  	/* Fix for improper SR-IOV configuration on Cavium cn88xx RNM device */

  	if (dev->subsystem_device == 0xa118)
  		dev->sriov->link = dev->devfn;
  }
  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link);
  #endif

  /*
   * Some settings of MMRBC can lead to data corruption so block changes.
   * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
   */

  static void quirk_amd_8131_mmrbc(struct pci_dev *dev)

  {

  	if (dev->subordinate && dev->revision <= 0x12) {

  		pci_info(dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC
  ",

  			 dev->revision);

  		dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
  	}
  }
  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);

  
  /*

   * FIXME: it is questionable that quirk_via_acpi() is needed.  It shows up
   * as an ISA bridge, and does not support the PCI_INTERRUPT_LINE register
   * at all.  Therefore it seems like setting the pci_dev's IRQ to the value
   * of the ACPI SCI interrupt is only done for convenience.

   *	-jgarzik
   */

  static void quirk_via_acpi(struct pci_dev *d)

  {

  	u8 irq;

  
  	/* VIA ACPI device: SCI IRQ line in PCI config byte 0x42 */

  	pci_read_config_byte(d, 0x42, &irq);
  	irq &= 0xf;
  	if (irq && (irq != 2))
  		d->irq = irq;
  }

  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C586_3,	quirk_via_acpi);
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C686_4,	quirk_via_acpi);

  /* VIA bridges which have VLink */

  static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
  
  static void quirk_via_bridge(struct pci_dev *dev)
  {
  	/* See what bridge we have and find the device ranges */
  	switch (dev->device) {
  	case PCI_DEVICE_ID_VIA_82C686:

  		/*
  		 * The VT82C686 is special; it attaches to PCI and can have
  		 * any device number. All its subdevices are functions of
  		 * that single device.
  		 */

  		via_vlink_dev_lo = PCI_SLOT(dev->devfn);
  		via_vlink_dev_hi = PCI_SLOT(dev->devfn);

  		break;
  	case PCI_DEVICE_ID_VIA_8237:
  	case PCI_DEVICE_ID_VIA_8237A:
  		via_vlink_dev_lo = 15;
  		break;
  	case PCI_DEVICE_ID_VIA_8235:
  		via_vlink_dev_lo = 16;
  		break;
  	case PCI_DEVICE_ID_VIA_8231:
  	case PCI_DEVICE_ID_VIA_8233_0:
  	case PCI_DEVICE_ID_VIA_8233A:
  	case PCI_DEVICE_ID_VIA_8233C_0:
  		via_vlink_dev_lo = 17;
  		break;
  	}
  }
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C686,	quirk_via_bridge);
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8231,		quirk_via_bridge);
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8233_0,	quirk_via_bridge);
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8233A,	quirk_via_bridge);
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8233C_0,	quirk_via_bridge);
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8235,		quirk_via_bridge);
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8237,		quirk_via_bridge);
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8237A,	quirk_via_bridge);

  /*
   * quirk_via_vlink		-	VIA VLink IRQ number update
   * @dev: PCI device

   *

   * If the device we are dealing with is on a PIC IRQ we need to ensure that
   * the IRQ line register which usually is not relevant for PCI cards, is
   * actually written so that interrupts get sent to the right place.
   *
   * We only do this on systems where a VIA south bridge was detected, and
   * only for VIA devices on the motherboard (see quirk_via_bridge above).

   */

  static void quirk_via_vlink(struct pci_dev *dev)

  {
  	u8 irq, new_irq;

  	/* Check if we have VLink at all */
  	if (via_vlink_dev_lo == -1)

  		return;
  
  	new_irq = dev->irq;
  
  	/* Don't quirk interrupts outside the legacy IRQ range */
  	if (!new_irq || new_irq > 15)
  		return;

  	/* Internal device ? */

  	if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
  	    PCI_SLOT(dev->devfn) < via_vlink_dev_lo)

  		return;

  	/*
  	 * This is an internal VLink device on a PIC interrupt. The BIOS
  	 * ought to have set this but may not have, so we redo it.
  	 */

  	pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
  	if (new_irq != irq) {

  		pci_info(dev, "VIA VLink IRQ fixup, from %d to %d
  ",

  			irq, new_irq);

  		udelay(15);	/* unknown if delay really needed */
  		pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
  	}
  }

  DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);

  /*

   * VIA VT82C598 has its device ID settable and many BIOSes set it to the ID
   * of VT82C597 for backward compatibility.  We need to switch it off to be
   * able to recognize the real type of the chip.

   */

  static void quirk_vt82c598_id(struct pci_dev *dev)

  {
  	pci_write_config_byte(dev, 0xfc, 0);
  	pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
  }

  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C597_0,	quirk_vt82c598_id);

  
  /*

   * CardBus controllers have a legacy base address that enables them to
   * respond as i82365 pcmcia controllers.  We don't want them to do this
   * even if the Linux CardBus driver is not loaded, because the Linux i82365
   * driver does not (and should not) handle CardBus.

   */

  static void quirk_cardbus_legacy(struct pci_dev *dev)

  {

  	pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
  }

  DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
  			PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
  DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID,
  			PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);

  
  /*

   * Following the PCI ordering rules is optional on the AMD762. I'm not sure
   * what the designers were smoking but let's not inhale...

   *

   * To be fair to AMD, it follows the spec by default, it's BIOS people who
   * turn it off!

   */

  static void quirk_amd_ordering(struct pci_dev *dev)

  {
  	u32 pcic;
  	pci_read_config_dword(dev, 0x4C, &pcic);

  	if ((pcic & 6) != 6) {

  		pcic |= 6;

  		pci_warn(dev, "BIOS failed to enable PCI standards compliance; fixing this error
  ");

  		pci_write_config_dword(dev, 0x4C, pcic);
  		pci_read_config_dword(dev, 0x84, &pcic);

  		pcic |= (1 << 23);	/* Required in this mode */

  		pci_write_config_dword(dev, 0x84, pcic);
  	}
  }

  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,	PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);

  DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD,	PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);

  
  /*

   * DreamWorks-provided workaround for Dunord I-3000 problem

   *

   * This card decodes and responds to addresses not apparently assigned to
   * it.  We force a larger allocation to ensure that nothing gets put too
   * close to it.

   */

  static void quirk_dunord(struct pci_dev *dev)

  {

  	struct resource *r = &dev->resource[1];

  
  	r->flags |= IORESOURCE_UNSET;

  	r->start = 0;
  	r->end = 0xffffff;
  }

  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD,	PCI_DEVICE_ID_DUNORD_I3000,	quirk_dunord);

  
  /*

   * i82380FB mobile docking controller: its PCI-to-PCI bridge is subtractive
   * decoding (transparent), and does indicate this in the ProgIf.
   * Unfortunately, the ProgIf value is wrong - 0x80 instead of 0x01.

   */

  static void quirk_transparent_bridge(struct pci_dev *dev)

  {
  	dev->transparent = 1;
  }

  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82380FB,	quirk_transparent_bridge);
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA,	0x605,	quirk_transparent_bridge);

  
  /*

   * Common misconfiguration of the MediaGX/Geode PCI master that will reduce
   * PCI bandwidth from 70MB/s to 25MB/s.  See the GXM/GXLV/GX1 datasheets
   * found at http://www.national.com/analog for info on what these bits do.
   * <christer@weinigel.se>

   */

  static void quirk_mediagx_master(struct pci_dev *dev)

  {
  	u8 reg;

  	pci_read_config_byte(dev, 0x41, &reg);
  	if (reg & 2) {
  		reg &= ~2;

  		pci_info(dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)
  ",

  			 reg);

  		pci_write_config_byte(dev, 0x41, reg);

  	}
  }

  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX,	PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
  DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX,	PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);

  
  /*

   * Ensure C0 rev restreaming is off. This is normally done by the BIOS but
   * in the odd case it is not the results are corruption hence the presence
   * of a Linux check.

   */

  static void quirk_disable_pxb(struct pci_dev *pdev)

  {
  	u16 config;

  	if (pdev->revision != 0x04)		/* Only C0 requires this */

  		return;
  	pci_read_config_word(pdev, 0x40, &config);
  	if (config & (1<<6)) {
  		config &= ~(1<<6);
  		pci_write_config_word(pdev, 0x40, config);

  		pci_info(pdev, "C0 revision 450NX. Disabling PCI restreaming
  ");

  	}
  }

  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82454NX,	quirk_disable_pxb);

  DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82454NX,	quirk_disable_pxb);

  static void quirk_amd_ide_mode(struct pci_dev *pdev)

  {

  	/* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */

  	u8 tmp;

  	pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
  	if (tmp == 0x01) {

  		pci_read_config_byte(pdev, 0x40, &tmp);
  		pci_write_config_byte(pdev, 0x40, tmp|1);
  		pci_write_config_byte(pdev, 0x9, 1);
  		pci_write_config_byte(pdev, 0xa, 6);
  		pci_write_config_byte(pdev, 0x40, tmp);

  		pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;

  		pci_info(pdev, "set SATA to AHCI mode
  ");

  	}
  }

  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);

  DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);

  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);

  DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);

  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
  DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);

  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
  DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);

  /* Serverworks CSB5 IDE does not fully support native mode */

  static void quirk_svwks_csb5ide(struct pci_dev *pdev)

  {
  	u8 prog;
  	pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
  	if (prog & 5) {
  		prog &= ~5;
  		pdev->class &= ~5;
  		pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);

  		/* PCI layer will sort out resources */

  	}
  }

  DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);

  /* Intel 82801CAM ICH3-M datasheet says IDE modes must be the same */

  static void quirk_ide_samemode(struct pci_dev *pdev)

  {
  	u8 prog;
  
  	pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
  
  	if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {

  		pci_info(pdev, "IDE mode mismatch; forcing legacy mode
  ");

  		prog &= ~5;
  		pdev->class &= ~5;
  		pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);

  	}
  }

  DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);

  /* Some ATA devices break if put into D3 */

  static void quirk_no_ata_d3(struct pci_dev *pdev)

  {

  	pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;

  }

  /* Quirk the legacy ATA devices only. The AHCI ones are ok */
  DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID,
  				PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
  DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
  				PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);

  /* ALi loses some register settings that we cannot then restore */

  DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID,
  				PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);

  /* VIA comes back fine but we need to keep it alive or ACPI GTM failures
     occur when mode detecting */

  DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID,
  				PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);

  /* Quirk the CYW4356 WIFI chip because the firmware still doesn't support
     D3 mode */
  DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_BROADCOM, 0x43ec,
  				PCI_CLASS_NETWORK_OTHER, 8, quirk_no_ata_d3);

  /*
   * This was originally an Alpha-specific thing, but it really fits here.

   * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
   */

  static void quirk_eisa_bridge(struct pci_dev *dev)

  {
  	dev->class = PCI_CLASS_BRIDGE_EISA << 8;
  }

  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82375,	quirk_eisa_bridge);

  /*

   * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
   * is not activated. The myth is that Asus said that they do not want the
   * users to be irritated by just another PCI Device in the Win98 device

   * manager. (see the file prog/hotplug/README.p4b in the lm_sensors

   * package 2.7.0 for details)
   *

   * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
   * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it

   * becomes necessary to do this tweak in two steps -- the chosen trigger
   * is either the Host bridge (preferred) or on-board VGA controller.

   *
   * Note that we used to unhide the SMBus that way on Toshiba laptops
   * (Satellite A40 and Tecra M2) but then found that the thermal management
   * was done by SMM code, which could cause unsynchronized concurrent
   * accesses to the SMBus registers, with potentially bad effects. Thus you
   * should be very careful when adding new entries: if SMM is accessing the
   * Intel SMBus, this is a very good reason to leave it hidden.

   *
   * Likewise, many recent laptops use ACPI for thermal management. If the
   * ACPI DSDT code accesses the SMBus, then Linux should not access it
   * natively, and keeping the SMBus hidden is the right thing to do. If you
   * are about to add an entry in the table below, please first disassemble
   * the DSDT and double-check that there is no code accessing the SMBus.

   */

  static int asus_hides_smbus;

  static void asus_hides_smbus_hostbridge(struct pci_dev *dev)

  {
  	if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
  		if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)

  			switch (dev->subsystem_device) {

  			case 0x8025: /* P4B-LX */

  			case 0x8070: /* P4B */
  			case 0x8088: /* P4B533 */
  			case 0x1626: /* L3C notebook */
  				asus_hides_smbus = 1;
  			}

  		else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)

  			switch (dev->subsystem_device) {

  			case 0x80b1: /* P4GE-V */
  			case 0x80b2: /* P4PE */
  			case 0x8093: /* P4B533-V */
  				asus_hides_smbus = 1;
  			}

  		else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)

  			switch (dev->subsystem_device) {

  			case 0x8030: /* P4T533 */
  				asus_hides_smbus = 1;
  			}

  		else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)

  			switch (dev->subsystem_device) {
  			case 0x8070: /* P4G8X Deluxe */
  				asus_hides_smbus = 1;
  			}

  		else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)

  			switch (dev->subsystem_device) {
  			case 0x80c9: /* PU-DLS */
  				asus_hides_smbus = 1;
  			}

  		else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)

  			switch (dev->subsystem_device) {
  			case 0x1751: /* M2N notebook */
  			case 0x1821: /* M5N notebook */

  			case 0x1897: /* A6L notebook */

  				asus_hides_smbus = 1;
  			}

  		else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)

  			switch (dev->subsystem_device) {
  			case 0x184b: /* W1N notebook */
  			case 0x186a: /* M6Ne notebook */
  				asus_hides_smbus = 1;
  			}

  		else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)

  			switch (dev->subsystem_device) {
  			case 0x80f2: /* P4P800-X */
  				asus_hides_smbus = 1;
  			}

  		else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)

  			switch (dev->subsystem_device) {
  			case 0x1882: /* M6V notebook */

  			case 0x1977: /* A6VA notebook */

  				asus_hides_smbus = 1;
  			}

  	} else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
  		if (dev->device ==  PCI_DEVICE_ID_INTEL_82855PM_HB)

  			switch (dev->subsystem_device) {

  			case 0x088C: /* HP Compaq nc8000 */
  			case 0x0890: /* HP Compaq nc6000 */
  				asus_hides_smbus = 1;
  			}

  		else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)

  			switch (dev->subsystem_device) {
  			case 0x12bc: /* HP D330L */

  			case 0x12bd: /* HP D530 */

  			case 0x006a: /* HP Compaq nx9500 */

  				asus_hides_smbus = 1;
  			}

  		else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
  			switch (dev->subsystem_device) {
  			case 0x12bf: /* HP xw4100 */
  				asus_hides_smbus = 1;
  			}

  	} else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
  		if (dev->device ==  PCI_DEVICE_ID_INTEL_82855PM_HB)
  			switch (dev->subsystem_device) {
  			case 0xC00C: /* Samsung P35 notebook */
  				asus_hides_smbus = 1;
  		}

  	} else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
  		if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)

  			switch (dev->subsystem_device) {

  			case 0x0058: /* Compaq Evo N620c */
  				asus_hides_smbus = 1;
  			}

  		else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)

  			switch (dev->subsystem_device) {

  			case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
  				/* Motherboard doesn't have Host bridge
  				 * subvendor/subdevice IDs, therefore checking
  				 * its on-board VGA controller */
  				asus_hides_smbus = 1;
  			}

  		else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)

  			switch (dev->subsystem_device) {

  			case 0x00b8: /* Compaq Evo D510 CMT */
  			case 0x00b9: /* Compaq Evo D510 SFF */

  			case 0x00ba: /* Compaq Evo D510 USDT */

  				/* Motherboard doesn't have Host bridge
  				 * subvendor/subdevice IDs and on-board VGA
  				 * controller is disabled if an AGP card is
  				 * inserted, therefore checking USB UHCI
  				 * Controller #1 */

  				asus_hides_smbus = 1;
  			}

  		else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
  			switch (dev->subsystem_device) {
  			case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
  				/* Motherboard doesn't have host bridge
  				 * subvendor/subdevice IDs, therefore checking
  				 * its on-board VGA controller */
  				asus_hides_smbus = 1;
  			}

  	}
  }

  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82845_HB,	asus_hides_smbus_hostbridge);
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82845G_HB,	asus_hides_smbus_hostbridge);
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82850_HB,	asus_hides_smbus_hostbridge);
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82865_HB,	asus_hides_smbus_hostbridge);

  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82875_HB,	asus_hides_smbus_hostbridge);

  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_7205_0,	asus_hides_smbus_hostbridge);
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_E7501_MCH,	asus_hides_smbus_hostbridge);
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82855PM_HB,	asus_hides_smbus_hostbridge);
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82855GM_HB,	asus_hides_smbus_hostbridge);
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
  
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82810_IG3,	asus_hides_smbus_hostbridge);

  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801DB_2,	asus_hides_smbus_hostbridge);

  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82815_CGC,	asus_hides_smbus_hostbridge);

  static void asus_hides_smbus_lpc(struct pci_dev *dev)

  {
  	u16 val;

  	if (likely(!asus_hides_smbus))
  		return;
  
  	pci_read_config_word(dev, 0xF2, &val);
  	if (val & 0x8) {
  		pci_write_config_word(dev, 0xF2, val & (~0x8));
  		pci_read_config_word(dev, 0xF2, &val);
  		if (val & 0x8)

  			pci_info(dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x
  ",

  				 val);

  		else

  			pci_info(dev, "Enabled i801 SMBus device
  ");

  	}
  }

  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801AA_0,	asus_hides_smbus_lpc);
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801DB_0,	asus_hides_smbus_lpc);
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801BA_0,	asus_hides_smbus_lpc);
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801CA_0,	asus_hides_smbus_lpc);
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801CA_12,	asus_hides_smbus_lpc);
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801DB_12,	asus_hides_smbus_lpc);
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801EB_0,	asus_hides_smbus_lpc);

  DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801AA_0,	asus_hides_smbus_lpc);
  DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801DB_0,	asus_hides_smbus_lpc);
  DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801BA_0,	asus_hides_smbus_lpc);
  DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801CA_0,	asus_hides_smbus_lpc);
  DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801CA_12,	asus_hides_smbus_lpc);
  DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801DB_12,	asus_hides_smbus_lpc);
  DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801EB_0,	asus_hides_smbus_lpc);

  /* It appears we just have one such device. If not, we have a warning */
  static void __iomem *asus_rcba_base;
  static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)

  {

  	u32 rcba;

  
  	if (likely(!asus_hides_smbus))
  		return;

  	WARN_ON(asus_rcba_base);

  	pci_read_config_dword(dev, 0xF0, &rcba);

  	/* use bits 31:14, 16 kB aligned */

  	asus_rcba_base = ioremap(rcba & 0xFFFFC000, 0x4000);

  	if (asus_rcba_base == NULL)
  		return;
  }
  
  static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
  {
  	u32 val;
  
  	if (likely(!asus_hides_smbus || !asus_rcba_base))
  		return;

  	/* read the Function Disable register, dword mode only */
  	val = readl(asus_rcba_base + 0x3418);

  
  	/* enable the SMBus device */
  	writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418);

  }
  
  static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
  {
  	if (likely(!asus_hides_smbus || !asus_rcba_base))
  		return;

  	iounmap(asus_rcba_base);
  	asus_rcba_base = NULL;

  	pci_info(dev, "Enabled ICH6/i801 SMBus device
  ");

  }

  
  static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
  {
  	asus_hides_smbus_lpc_ich6_suspend(dev);
  	asus_hides_smbus_lpc_ich6_resume_early(dev);
  	asus_hides_smbus_lpc_ich6_resume(dev);
  }

  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH6_1,	asus_hides_smbus_lpc_ich6);

  DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH6_1,	asus_hides_smbus_lpc_ich6_suspend);
  DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH6_1,	asus_hides_smbus_lpc_ich6_resume);
  DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH6_1,	asus_hides_smbus_lpc_ich6_resume_early);

  /* SiS 96x south bridge: BIOS typically hides SMBus device...  */

  static void quirk_sis_96x_smbus(struct pci_dev *dev)

  {
  	u8 val = 0;

  	pci_read_config_byte(dev, 0x77, &val);

  	if (val & 0x10) {

  		pci_info(dev, "Enabling SiS 96x SMBus
  ");

  		pci_write_config_byte(dev, 0x77, val & ~0x10);
  	}

  }

  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_961,		quirk_sis_96x_smbus);
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_962,		quirk_sis_96x_smbus);
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_963,		quirk_sis_96x_smbus);
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_LPC,		quirk_sis_96x_smbus);

  DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_961,		quirk_sis_96x_smbus);
  DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_962,		quirk_sis_96x_smbus);
  DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_963,		quirk_sis_96x_smbus);
  DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_LPC,		quirk_sis_96x_smbus);

  /*
   * ... This is further complicated by the fact that some SiS96x south
   * bridges pretend to be 85C503/5513 instead.  In that case see if we
   * spotted a compatible north bridge to make sure.

   * (pci_find_device() doesn't work yet)

   *
   * We can also enable the sis96x bit in the discovery register..
   */

  #define SIS_DETECT_REGISTER 0x40

  static void quirk_sis_503(struct pci_dev *dev)

  {
  	u8 reg;
  	u16 devid;
  
  	pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg);
  	pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
  	pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
  	if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
  		pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
  		return;
  	}

  	/*

  	 * Ok, it now shows up as a 96x.  Run the 96x quirk by hand in case
  	 * it has already been processed.  (Depends on link order, which is
  	 * apparently not guaranteed)

  	 */
  	dev->device = devid;

  	quirk_sis_96x_smbus(dev);

  }

  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_503,		quirk_sis_503);