/*
   * Copyright 2013 Freescale Semiconductor, Inc.
   *

   * This file is dual-licensed: you can use it either under the terms
   * of the GPL or the X11 license, at your option. Note that this dual
   * licensing only applies to this file, and not this project as a
   * whole.
   *
   *  a) This file is free software; you can redistribute it and/or
   *     modify it under the terms of the GNU General Public License
   *     version 2 as published by the Free Software Foundation.
   *
   *     This file is distributed in the hope that it will be useful
   *     but WITHOUT ANY WARRANTY; without even the implied warranty of
   *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   *     GNU General Public License for more details.
   *
   * Or, alternatively
   *
   *  b) Permission is hereby granted, free of charge, to any person
   *     obtaining a copy of this software and associated documentation
   *     files (the "Software"), to deal in the Software without
   *     restriction, including without limitation the rights to use
   *     copy, modify, merge, publish, distribute, sublicense, and/or
   *     sell copies of the Software, and to permit persons to whom the
   *     Software is furnished to do so, subject to the following
   *     conditions:
   *
   *     The above copyright notice and this permission notice shall be
   *     included in all copies or substantial portions of the Software.
   *
   *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
   *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
   *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
   *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
   *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
   *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
   *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
   *     OTHER DEALINGS IN THE SOFTWARE.

   */

  #include "vf500.dtsi"

  &a5_cpu {
  	next-level-cache = <&L2>;
  };

  &aips0 {
  	L2: l2-cache@40006000 {
  		compatible = "arm,pl310-cache";
  		reg = <0x40006000 0x1000>;
  		cache-unified;
  		cache-level = <2>;

  		arm,data-latency = <3 3 3>;

  		arm,tag-latency = <2 2 2>;

  	};
  };