Eric Lee / smarc-fsl-linux-kernel

29 Feb, 2016

1 commit

  • 4a4d45c78   ARM: dts: vf610: relicense vf???.dtsi under GPLv2/X11 ... Browse Code »

    GPLv2-only devicetrees make reuse difficult for software components
    licensed under a different license.

    The consensus is that a GPL/X11 dual-license should allow all necessary
    uses, so relicense the vfxxx.dtsi, vf500.dtsi and vf610.dtsi files to
    this combination.

    CCs were acquired using (updated some email addresses, commented out
    bouncing email addresses with --):
    git shortlog -sne --no-merges arch/arm/boot/dts/vf???.dtsi

    --CC: Chao Fu
    CC: Cosmin Stoica
    CC: Frank Li
    CC: Fugang Duan
    --CC: Huang Shijie
    --CC: Jingchang Lu
    --CC: Xiubo Li
    Acked-by: Shawn Guo
    Acked-by: Lucas Stach
    Acked-by: Stephen Warren
    Acked-by: Cory Tusar
    Acked-by: Sanchayan Maity
    Acked-by: Bhuvanchandra DV
    Acked-by: Yuan Yao
    Signed-off-by: Stefan Agner
    Signed-off-by: Shawn Guo

    Stefan Agner
     

11 Dec, 2015

1 commit

  • 9c1719059   ARM: dts: vf610: use reset values for L2 cache latencies ... Browse Code »

    Linux on Vybrid used several different L2 latencies so far, none
    of them seem to be the right ones. According to the application note
    AN4947 ("Understanding Vybrid Architecture"), the tag portion runs
    on CPU clock and is inside the L2 cache controller, whereas the data
    portion is stored in the external SRAM running on platform clock.
    Hence it is likely that the correct value requires a higher data
    latency then tag latency.

    These are the values which have been used so far:
    - The mainline values:
    arm,data-latency = ;
    arm,tag-latency = ;
    Those values have lead to problems on higher clocks. They look
    like a poor translation from the reset values (missing +1 offset
    and a mix up between tag/latency values).
    - The Linux 3.0 (SoC vendor BSP) values (converted to DT notation):
    arm,data-latency =
    arm,tag-latency =
    The cache initialization function along with the value matches the
    i.MX6 code from the same kernel, so it seems that those values have
    just been copied.
    - The Colibri values:
    arm,data-latency = ;
    arm,tag-latency = ;
    Those were a mix between the values of the Linux 3.0 based BSP and
    the mainline values above.
    - The SoC Reset values (converted to DT notation):
    arm,data-latency = ;
    arm,tag-latency = ;

    So far there is no official statement on what the correct values are.
    See also the related Freescale community thread:
    https://community.freescale.com/message/579785#579785

    For now, the reset values seem to be the best bet. Remove all other
    "bogus" values and use the reset value on vf610.dtsi level.

    Signed-off-by: Stefan Agner
    Cc:
    Signed-off-by: Shawn Guo

    Stefan Agner
     

23 Nov, 2014

4 commits

  • efb45b305   ARM: dts: vf610: create generic base device trees ... Browse Code »

    This adds more generic base device trees for Vybrid SoCs. There
    are three series of Vybrid SoC commonly available:
    - VF3xx series: single core, Cortex-A5 without external memory
    - VF5xx series: single core, Cortex-A5
    - VF6xx series: dual core, Cortex-A5/Cortex-M4

    The second digit represents the presents of a L2 cache (VFx1x).

    The VF3xx series are not suitable for Linux especially since the
    internal memory is quite small (1.5MiB).

    The VF500 is essentially the base SoC, with only one core and
    without L1 cache. The VF610 is a superset of the VF500, hence
    vf500.dtsi is then included and enhanced by vf610.dtsi. There is
    no board using VF510 or VF600 currently, but, if needed, they can
    be added easily.

    The Linux kernel can also run on the Cortex-M4 CPU of Vybrid
    using !MMU support. This patchset creates a device tree structure
    which allows to share peripherals nodes for a VF6xx Cortex-M4
    device tree too. The two CPU types have different views of the
    system: Foremost they are using different interrupt controllers,
    but also the memory map is slightly different. The base device
    tree vfxxx.dtsi allows to create SoC and board level device trees
    supporting the Cortex-M4 while reusing the shared peripherals
    nodes.

    Signed-off-by: Stefan Agner
    Signed-off-by: Shawn Guo

    Stefan Agner
     
  • 3f3ebfb84   ARM: dts: vf610: assign oscillator to clock module ... Browse Code »

    The clock controller module (CCM) has several clock inputs, which
    are connected to external crystal oscillators. To reflect this,
    assign these fixed clocks to the CCM node directly.

    This especially resolves initialization order dependencies we had
    with the earlier initialization code: When resolving of the fixed
    clocks failed in clk-vf610, the code created fixed clocks with a
    rate of 0.

    Signed-off-by: Stefan Agner
    Signed-off-by: Shawn Guo

    Stefan Agner
     
  • a1d00bc59   ARM: dts: vf610: Add PWM second instance ... Browse Code »

    Signed-off-by: Bhuvanchandra DV
    Signed-off-by: Shawn Guo

    Bhuvanchandra DV
     
  • 81c483190   ARM: dts: vf610: Add ARM Global Timer ... Browse Code »

    Add Global Timer support which is part of the private peripherals
    of the Cortex-A5 processor. This Global Timer is compatible with the
    Cortex-A9 implementation. It's a 64-bit timer and is clocked by the
    peripheral clock, which is typically 133 or 166MHz on Vybrid.

    Signed-off-by: Stefan Agner
    Acked-by: Bill Pringlemeir
    Signed-off-by: Shawn Guo

    Stefan Agner
     

16 Sep, 2014

2 commits

  • 763dab227   ARM: dts: vf610: Add usbmisc for non-core registers ... Browse Code »

    Add device tree node for usbmisc which controls the non-core USB
    registers. This is required to use the property to disable the over-
    current detection.

    Signed-off-by: Stefan Agner
    Signed-off-by: Shawn Guo

    Stefan Agner
     
  • e34a68a31   ARM: dts: vf610: Add USB PHY and controller ... Browse Code »

    This adds USB PHY and USB controller nodes. Vybrid SoCs have two
    independent USB cores which each supports DR (dual role). However,
    real OTG is not supported since the OTG ID pin is not available.

    The PHYs are located within the anadig register range, hence we need
    to change the length of the anadig registers.

    Signed-off-by: Stefan Agner
    Signed-off-by: Shawn Guo

    Stefan Agner
     

18 Jul, 2014

2 commits

05 Jun, 2014

1 commit

  • 82e627eb5   Merge branch 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kerne… ... Browse Code »

    …l/git/tip/tip into next

    Pull timer core updates from Thomas Gleixner:
    "This time you get nothing really exciting:
    - A huge update to the sh* clocksource drivers
    - Support for two more ARM SoCs
    - Removal of the deprecated setup_sched_clock() API
    - The usual pile of fixlets all over the place"

    * 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (23 commits)
    clocksource: Add Freescale FlexTimer Module (FTM) timer support
    ARM: dts: vf610: Add Freescale FlexTimer Module timer node.
    clocksource: ftm: Add FlexTimer Module (FTM) Timer devicetree Documentation
    clocksource: sh_tmu: Remove unnecessary OOM messages
    clocksource: sh_mtu2: Remove unnecessary OOM messages
    clocksource: sh_cmt: Remove unnecessary OOM messages
    clocksource: em_sti: Remove unnecessary OOM messages
    clocksource: dw_apb_timer_of: Do not trace read_sched_clock
    clocksource: Fix clocksource_mmio_readX_down
    clocksource: Fix type confusion for clocksource_mmio_readX_Y
    clocksource: sh_tmu: Fix channel IRQ retrieval in legacy case
    clocksource: qcom: Implement read_current_timer for udelay
    ntp: Make is_error_status() use its argument
    ntp: Convert simple_strtol to kstrtol
    timer_stats/doc: Fix /proc/timer_stats documentation
    sched_clock: Remove deprecated setup_sched_clock() API
    ARM: sun6i: a31: Add support for the High Speed Timers
    clocksource: sun5i: Add support for reset controller
    clocksource: efm32: use $vendor,$device scheme for compatible string
    KConfig: Vexpress: build the ARM_GLOBAL_TIMER with vexpress platform
    ...

    Linus Torvalds
     

23 May, 2014

1 commit

16 May, 2014

1 commit

30 Apr, 2014

1 commit

  • 0517fe6aa   ARM: dts: vf610-twr: Add support for sdhc1 ... Browse Code »

    The kernel was not able to boot from SD card because sdhc support
    was not present into the dts.

    A new entry for sdhc1 was added for vf610-twr board based on the
    compatible entry present on imx53.

    After applying these changes, the kernel is able to boot successfully
    from SD card.

    Signed-off-by: Cosmin Stoica
    Signed-off-by: Chircu Bogdan
    Signed-off-by: Eddy Petrisor
    Signed-off-by: Shawn Guo

    Cosmin Stoica
     

14 Apr, 2014

2 commits

27 Feb, 2014

1 commit

24 Feb, 2014

1 commit

  • 64436ff66   ARM: dts: vf610-twr: Add ADC support ... Browse Code »

    vf610 has two ADC controllers, and vf610-twr board ADC0_SE5 pin connect
    to sliding rheostat for ADC test, other ADC pins connect to connectors for
    future use.

    Add support for ADC0_SE5.

    CC: Jonathan Cameron
    CC: Mark Rutland
    CC: Otavio Salvador
    CC: Peter Meerwald
    CC: Lars-Peter Clausen
    Signed-off-by: Fugang Duan
    Signed-off-by: Shawn Guo

    Fugang Duan
     

20 Feb, 2014

1 commit

18 Feb, 2014

2 commits

09 Feb, 2014

2 commits

  • 2bc88b1b3   ARM: dts: vf610: use the interrupt macros ... Browse Code »

    This patch uses the IRQ_TYPE_LEVEL_HIGH/IRQ_TYPE_NONE to replace
    the hardcode.

    [shawn.guo: While at it, we also fix the typo in uart0 interrupts
    property, where the 0x00 should 0x04. Hense, it should also be
    IRQ_TYPE_LEVEL_HIGH just like other UART instances.]

    Signed-off-by: Huang Shijie
    Signed-off-by: Shawn Guo

    Huang Shijie
     
  • 07ed1eed5   ARM: dts: vf610: make pinctrl nodes board specific ... Browse Code »

    Currently, all pinctrl setting nodes are defined in .dtsi, so that
    boards that share the same pinctrl setting do not have to define it time
    and time again in .dts. However, along with the devices and use
    cases being added continuously, the pinctrl setting nodes under iomuxc
    becomes more than expected. This bloats device tree blob for particular
    board unnecessarily since only a small subset of those pinctrl setting
    nodes will be used by the board. It impacts not only the DTB file size
    but also the run-time device tree lookup efficiency.

    The patch moves all the pinctrl data into individual boards as needed.
    With the changes, the pinctrl setting nodes becomes local to particular
    board, and it makes no sense to continue numbering the setting for
    given peripheral. Thus, all the pinctrl phandler name gets updated to
    have only peripheral name in there.

    Signed-off-by: Shawn Guo
    Acked-by: Fugang Duan

    Shawn Guo
     

26 Sep, 2013

1 commit

15 Jul, 2013

1 commit

  • 4f71612ee   ARM: imx: fix vf610 enet module clock selection ... Browse Code »

    The fec/enet driver calculates MDC rate with the formula below.

    ref_freq / ((MII_SPEED + 1) x 2)

    The ref_freq here is the fec internal module clock, which is missing
    from clk-vf610 clock driver right now. And clk-vf610 driver mistakenly
    supplies RMII clock (50 MHz) as the source to fec. This results in the
    situation that fec driver gets ref_freq as 50 MHz, while physically it
    runs at 66 MHz (fec module clock physically sources from ipg which runs
    at 66 MHz). That's why software expects MDC runs at 2.5 MHz, while the
    measurement tells it runs at 3.3 MHz. And this causes the PHY KSZ8041
    keeps swithing between Full and Half mode as below.

    libphy: 400d0000.etherne:00 - Link is Up - 100/Full
    libphy: 400d0000.etherne:00 - Link is Up - 100/Half
    libphy: 400d0000.etherne:00 - Link is Up - 100/Full
    libphy: 400d0000.etherne:00 - Link is Up - 100/Half
    libphy: 400d0000.etherne:00 - Link is Up - 100/Full
    libphy: 400d0000.etherne:00 - Link is Up - 100/Half

    Add the missing module clock for ENET0 and ENET1, and correct the clock
    supplying in device tree to fix above issue.

    Thanks to Alison Wang for debugging the issue.

    Signed-off-by: Shawn Guo

    Shawn Guo
     

17 Jun, 2013

2 commits