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drivers/clocksource/cadence_ttc_timer.c
14.7 KB
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/* |
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* This file contains driver for the Cadence Triple Timer Counter Rev 06 |
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* |
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* Copyright (C) 2011-2013 Xilinx |
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* * based on arch/mips/kernel/time.c timer driver * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ |
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#include <linux/clk.h> |
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#include <linux/interrupt.h> |
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#include <linux/clockchips.h> |
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#include <linux/of_address.h> #include <linux/of_irq.h> #include <linux/slab.h> |
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#include <linux/sched_clock.h> |
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|
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/* |
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* This driver configures the 2 16/32-bit count-up timers as follows: |
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* * T1: Timer 1, clocksource for generic timekeeping * T2: Timer 2, clockevent source for hrtimers * T3: Timer 3, <unused> * * The input frequency to the timer module for emulation is 2.5MHz which is * common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32, * the timers are clocked at 78.125KHz (12.8 us resolution). * The input frequency to the timer module in silicon is configurable and * obtained from device tree. The pre-scaler of 32 is used. */ /* |
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* Timer Register Offset Definitions of Timer 1, Increment base address by 4 * and use same offsets for Timer 2 */ |
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#define TTC_CLK_CNTRL_OFFSET 0x00 /* Clock Control Reg, RW */ #define TTC_CNT_CNTRL_OFFSET 0x0C /* Counter Control Reg, RW */ #define TTC_COUNT_VAL_OFFSET 0x18 /* Counter Value Reg, RO */ #define TTC_INTR_VAL_OFFSET 0x24 /* Interval Count Reg, RW */ #define TTC_ISR_OFFSET 0x54 /* Interrupt Status Reg, RO */ #define TTC_IER_OFFSET 0x60 /* Interrupt Enable Reg, RW */ |
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#define TTC_CNT_CNTRL_DISABLE_MASK 0x1 |
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|
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#define TTC_CLK_CNTRL_CSRC_MASK (1 << 5) /* clock source */ |
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#define TTC_CLK_CNTRL_PSV_MASK 0x1e #define TTC_CLK_CNTRL_PSV_SHIFT 1 |
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|
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/* * Setup the timers to use pre-scaling, using a fixed value for now that will |
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* work across most input frequency, but it may need to be more dynamic */ #define PRESCALE_EXPONENT 11 /* 2 ^ PRESCALE_EXPONENT = PRESCALE */ #define PRESCALE 2048 /* The exponent must match this */ #define CLK_CNTRL_PRESCALE ((PRESCALE_EXPONENT - 1) << 1) #define CLK_CNTRL_PRESCALE_EN 1 |
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#define CNT_CNTRL_RESET (1 << 4) |
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|
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#define MAX_F_ERR 50 |
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/** |
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* struct ttc_timer - This definition defines local timer structure |
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* * @base_addr: Base address of timer |
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* @freq: Timer input clock frequency |
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* @clk: Associated clock source * @clk_rate_change_nb Notifier block for clock rate changes */ |
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struct ttc_timer { |
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void __iomem *base_addr; |
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unsigned long freq; |
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struct clk *clk; struct notifier_block clk_rate_change_nb; |
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}; |
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#define to_ttc_timer(x) \ container_of(x, struct ttc_timer, clk_rate_change_nb) |
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|
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struct ttc_timer_clocksource { |
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u32 scale_clk_ctrl_reg_old; u32 scale_clk_ctrl_reg_new; |
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struct ttc_timer ttc; |
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struct clocksource cs; |
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}; |
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#define to_ttc_timer_clksrc(x) \ container_of(x, struct ttc_timer_clocksource, cs) |
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|
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struct ttc_timer_clockevent { struct ttc_timer ttc; |
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struct clock_event_device ce; |
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}; |
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#define to_ttc_timer_clkevent(x) \ container_of(x, struct ttc_timer_clockevent, ce) |
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|
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static void __iomem *ttc_sched_clock_val_reg; |
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/** |
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* ttc_set_interval - Set the timer interval value |
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* * @timer: Pointer to the timer instance * @cycles: Timer interval ticks **/ |
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static void ttc_set_interval(struct ttc_timer *timer, |
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unsigned long cycles) { u32 ctrl_reg; /* Disable the counter, set the counter value and re-enable counter */ |
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ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET); |
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ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK; |
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writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET); |
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|
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writel_relaxed(cycles, timer->base_addr + TTC_INTR_VAL_OFFSET); |
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|
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/* * Reset the counter (0x10) so that it starts from 0, one-shot * mode makes this needed for timing to be right. */ |
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ctrl_reg |= CNT_CNTRL_RESET; |
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ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK; |
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writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET); |
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} /** |
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* ttc_clock_event_interrupt - Clock event timer interrupt handler |
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* * @irq: IRQ number of the Timer |
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* @dev_id: void pointer to the ttc_timer instance |
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* * returns: Always IRQ_HANDLED - success **/ |
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static irqreturn_t ttc_clock_event_interrupt(int irq, void *dev_id) |
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{ |
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struct ttc_timer_clockevent *ttce = dev_id; struct ttc_timer *timer = &ttce->ttc; |
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/* Acknowledge the interrupt and call event handler */ |
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readl_relaxed(timer->base_addr + TTC_ISR_OFFSET); |
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|
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ttce->ce.event_handler(&ttce->ce); |
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return IRQ_HANDLED; } |
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/** |
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* __ttc_clocksource_read - Reads the timer counter register |
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* * returns: Current timer counter register value **/ |
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static cycle_t __ttc_clocksource_read(struct clocksource *cs) |
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{ |
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struct ttc_timer *timer = &to_ttc_timer_clksrc(cs)->ttc; |
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|
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return (cycle_t)readl_relaxed(timer->base_addr + |
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TTC_COUNT_VAL_OFFSET); |
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} |
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static u64 notrace ttc_sched_clock_read(void) |
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{ |
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return readl_relaxed(ttc_sched_clock_val_reg); |
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} |
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/** |
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* ttc_set_next_event - Sets the time interval for next event |
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* * @cycles: Timer interval ticks * @evt: Address of clock event instance * * returns: Always 0 - success **/ |
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static int ttc_set_next_event(unsigned long cycles, |
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struct clock_event_device *evt) { |
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struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt); struct ttc_timer *timer = &ttce->ttc; |
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|
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ttc_set_interval(timer, cycles); |
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return 0; } /** |
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* ttc_set_{shutdown|oneshot|periodic} - Sets the state of timer |
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* |
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* @evt: Address of clock event instance **/ |
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static int ttc_shutdown(struct clock_event_device *evt) |
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{ |
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struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt); struct ttc_timer *timer = &ttce->ttc; |
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u32 ctrl_reg; |
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ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET); ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK; writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET); return 0; } static int ttc_set_periodic(struct clock_event_device *evt) { struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt); struct ttc_timer *timer = &ttce->ttc; ttc_set_interval(timer, DIV_ROUND_CLOSEST(ttce->ttc.freq, PRESCALE * HZ)); return 0; } static int ttc_resume(struct clock_event_device *evt) { struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt); struct ttc_timer *timer = &ttce->ttc; u32 ctrl_reg; ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET); ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK; writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET); return 0; |
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} |
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static int ttc_rate_change_clocksource_cb(struct notifier_block *nb, |
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unsigned long event, void *data) { struct clk_notifier_data *ndata = data; |
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struct ttc_timer *ttc = to_ttc_timer(nb); struct ttc_timer_clocksource *ttccs = container_of(ttc, struct ttc_timer_clocksource, ttc); |
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switch (event) { |
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case PRE_RATE_CHANGE: { u32 psv; unsigned long factor, rate_low, rate_high; if (ndata->new_rate > ndata->old_rate) { factor = DIV_ROUND_CLOSEST(ndata->new_rate, ndata->old_rate); rate_low = ndata->old_rate; rate_high = ndata->new_rate; } else { factor = DIV_ROUND_CLOSEST(ndata->old_rate, ndata->new_rate); rate_low = ndata->new_rate; rate_high = ndata->old_rate; } if (!is_power_of_2(factor)) return NOTIFY_BAD; if (abs(rate_high - (factor * rate_low)) > MAX_F_ERR) return NOTIFY_BAD; factor = __ilog2_u32(factor); |
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/* |
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* store timer clock ctrl register so we can restore it in case * of an abort. |
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*/ |
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ttccs->scale_clk_ctrl_reg_old = |
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readl_relaxed(ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET); |
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psv = (ttccs->scale_clk_ctrl_reg_old & TTC_CLK_CNTRL_PSV_MASK) >> TTC_CLK_CNTRL_PSV_SHIFT; if (ndata->new_rate < ndata->old_rate) psv -= factor; else psv += factor; /* prescaler within legal range? */ if (psv & ~(TTC_CLK_CNTRL_PSV_MASK >> TTC_CLK_CNTRL_PSV_SHIFT)) return NOTIFY_BAD; ttccs->scale_clk_ctrl_reg_new = ttccs->scale_clk_ctrl_reg_old & ~TTC_CLK_CNTRL_PSV_MASK; ttccs->scale_clk_ctrl_reg_new |= psv << TTC_CLK_CNTRL_PSV_SHIFT; /* scale down: adjust divider in post-change notification */ if (ndata->new_rate < ndata->old_rate) return NOTIFY_DONE; /* scale up: adjust divider now - before frequency change */ |
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writel_relaxed(ttccs->scale_clk_ctrl_reg_new, ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET); |
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break; } case POST_RATE_CHANGE: /* scale up: pre-change notification did the adjustment */ if (ndata->new_rate > ndata->old_rate) return NOTIFY_OK; /* scale down: adjust divider now - after frequency change */ |
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writel_relaxed(ttccs->scale_clk_ctrl_reg_new, ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET); |
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break; |
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case ABORT_RATE_CHANGE: |
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/* we have to undo the adjustment in case we scale up */ if (ndata->new_rate < ndata->old_rate) return NOTIFY_OK; /* restore original register value */ |
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writel_relaxed(ttccs->scale_clk_ctrl_reg_old, ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET); |
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/* fall through */ |
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default: return NOTIFY_DONE; } |
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return NOTIFY_DONE; |
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} |
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static int __init ttc_setup_clocksource(struct clk *clk, void __iomem *base, |
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u32 timer_width) |
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{ |
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struct ttc_timer_clocksource *ttccs; |
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int err; |
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ttccs = kzalloc(sizeof(*ttccs), GFP_KERNEL); |
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if (!ttccs) return -ENOMEM; |
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|
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ttccs->ttc.clk = clk; |
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err = clk_prepare_enable(ttccs->ttc.clk); |
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if (err) { |
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kfree(ttccs); |
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return err; |
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} |
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|
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ttccs->ttc.freq = clk_get_rate(ttccs->ttc.clk); |
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ttccs->ttc.clk_rate_change_nb.notifier_call = ttc_rate_change_clocksource_cb; ttccs->ttc.clk_rate_change_nb.next = NULL; |
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err = clk_notifier_register(ttccs->ttc.clk, &ttccs->ttc.clk_rate_change_nb); if (err) |
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pr_warn("Unable to register clock notifier. "); |
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|
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ttccs->ttc.base_addr = base; ttccs->cs.name = "ttc_clocksource"; |
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ttccs->cs.rating = 200; |
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ttccs->cs.read = __ttc_clocksource_read; |
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ttccs->cs.mask = CLOCKSOURCE_MASK(timer_width); |
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ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS; |
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/* * Setup the clock source counter to be an incrementing counter * with no interrupt and it rolls over at 0xFFFF. Pre-scale * it by 32 also. Let it start running now. */ |
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writel_relaxed(0x0, ttccs->ttc.base_addr + TTC_IER_OFFSET); writel_relaxed(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN, |
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ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET); |
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writel_relaxed(CNT_CNTRL_RESET, |
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ttccs->ttc.base_addr + TTC_CNT_CNTRL_OFFSET); |
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|
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err = clocksource_register_hz(&ttccs->cs, ttccs->ttc.freq / PRESCALE); |
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if (err) { |
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kfree(ttccs); |
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return err; |
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} |
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ttc_sched_clock_val_reg = base + TTC_COUNT_VAL_OFFSET; |
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sched_clock_register(ttc_sched_clock_read, timer_width, ttccs->ttc.freq / PRESCALE); |
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return 0; |
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} |
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static int ttc_rate_change_clockevent_cb(struct notifier_block *nb, |
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370 371 372 |
unsigned long event, void *data) { struct clk_notifier_data *ndata = data; |
9e09dc5f7 arm: zynq: Do not... |
373 374 375 |
struct ttc_timer *ttc = to_ttc_timer(nb); struct ttc_timer_clockevent *ttcce = container_of(ttc, struct ttc_timer_clockevent, ttc); |
e932900a3 arm: zynq: Use st... |
376 377 378 |
switch (event) { case POST_RATE_CHANGE: |
c1dcc927d clocksource: cade... |
379 380 |
/* update cached frequency */ ttc->freq = ndata->new_rate; |
5f0ba3b46 clocksource/caden... |
381 |
clockevents_update_freq(&ttcce->ce, ndata->new_rate / PRESCALE); |
e932900a3 arm: zynq: Use st... |
382 |
/* fall through */ |
e932900a3 arm: zynq: Use st... |
383 384 385 386 387 388 |
case PRE_RATE_CHANGE: case ABORT_RATE_CHANGE: default: return NOTIFY_DONE; } } |
70504f311 clocksource/drive... |
389 390 |
static int __init ttc_setup_clockevent(struct clk *clk, void __iomem *base, u32 irq) |
91dc985c5 ARM: zynq: add cl... |
391 |
{ |
9e09dc5f7 arm: zynq: Do not... |
392 |
struct ttc_timer_clockevent *ttcce; |
e932900a3 arm: zynq: Use st... |
393 |
int err; |
91dc985c5 ARM: zynq: add cl... |
394 395 |
ttcce = kzalloc(sizeof(*ttcce), GFP_KERNEL); |
70504f311 clocksource/drive... |
396 397 |
if (!ttcce) return -ENOMEM; |
91dc985c5 ARM: zynq: add cl... |
398 |
|
9e09dc5f7 arm: zynq: Do not... |
399 |
ttcce->ttc.clk = clk; |
91dc985c5 ARM: zynq: add cl... |
400 |
|
9e09dc5f7 arm: zynq: Do not... |
401 |
err = clk_prepare_enable(ttcce->ttc.clk); |
70504f311 clocksource/drive... |
402 |
if (err) { |
c5263bb8b arm: zynq: Move t... |
403 |
kfree(ttcce); |
70504f311 clocksource/drive... |
404 |
return err; |
c5263bb8b arm: zynq: Move t... |
405 |
} |
91dc985c5 ARM: zynq: add cl... |
406 |
|
9e09dc5f7 arm: zynq: Do not... |
407 408 409 |
ttcce->ttc.clk_rate_change_nb.notifier_call = ttc_rate_change_clockevent_cb; ttcce->ttc.clk_rate_change_nb.next = NULL; |
70504f311 clocksource/drive... |
410 411 412 413 |
err = clk_notifier_register(ttcce->ttc.clk, &ttcce->ttc.clk_rate_change_nb); if (err) { |
e932900a3 arm: zynq: Use st... |
414 415 |
pr_warn("Unable to register clock notifier. "); |
70504f311 clocksource/drive... |
416 417 |
return err; } |
c1dcc927d clocksource: cade... |
418 |
ttcce->ttc.freq = clk_get_rate(ttcce->ttc.clk); |
91dc985c5 ARM: zynq: add cl... |
419 |
|
9e09dc5f7 arm: zynq: Do not... |
420 421 |
ttcce->ttc.base_addr = base; ttcce->ce.name = "ttc_clockevent"; |
91dc985c5 ARM: zynq: add cl... |
422 |
ttcce->ce.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; |
9e09dc5f7 arm: zynq: Do not... |
423 |
ttcce->ce.set_next_event = ttc_set_next_event; |
5c0a4bbef clockevents/drive... |
424 425 426 427 |
ttcce->ce.set_state_shutdown = ttc_shutdown; ttcce->ce.set_state_periodic = ttc_set_periodic; ttcce->ce.set_state_oneshot = ttc_shutdown; ttcce->ce.tick_resume = ttc_resume; |
91dc985c5 ARM: zynq: add cl... |
428 429 |
ttcce->ce.rating = 200; ttcce->ce.irq = irq; |
87e4ee759 arm: zynq: timer:... |
430 |
ttcce->ce.cpumask = cpu_possible_mask; |
91dc985c5 ARM: zynq: add cl... |
431 |
|
e932900a3 arm: zynq: Use st... |
432 433 434 435 436 |
/* * Setup the clock event timer to be an interval timer which * is prescaled by 32 using the interval interrupt. Leave it * disabled for now. */ |
87ab4361b clocksource: cade... |
437 438 |
writel_relaxed(0x23, ttcce->ttc.base_addr + TTC_CNT_CNTRL_OFFSET); writel_relaxed(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN, |
9e09dc5f7 arm: zynq: Do not... |
439 |
ttcce->ttc.base_addr + TTC_CLK_CNTRL_OFFSET); |
87ab4361b clocksource: cade... |
440 |
writel_relaxed(0x1, ttcce->ttc.base_addr + TTC_IER_OFFSET); |
91dc985c5 ARM: zynq: add cl... |
441 |
|
9e09dc5f7 arm: zynq: Do not... |
442 |
err = request_irq(irq, ttc_clock_event_interrupt, |
38c30a842 clocksource: misc... |
443 |
IRQF_TIMER, ttcce->ce.name, ttcce); |
70504f311 clocksource/drive... |
444 |
if (err) { |
c5263bb8b arm: zynq: Move t... |
445 |
kfree(ttcce); |
70504f311 clocksource/drive... |
446 |
return err; |
c5263bb8b arm: zynq: Move t... |
447 |
} |
91dc985c5 ARM: zynq: add cl... |
448 449 |
clockevents_config_and_register(&ttcce->ce, |
c1dcc927d clocksource: cade... |
450 |
ttcce->ttc.freq / PRESCALE, 1, 0xfffe); |
70504f311 clocksource/drive... |
451 452 |
return 0; |
91dc985c5 ARM: zynq: add cl... |
453 |
} |
b85a3ef4a ARM: Xilinx: Addi... |
454 |
/** |
9e09dc5f7 arm: zynq: Do not... |
455 |
* ttc_timer_init - Initialize the timer |
b85a3ef4a ARM: Xilinx: Addi... |
456 457 458 |
* * Initializes the timer hardware and register the clock source and clock event * timers with Linux kernal timer framework |
e932900a3 arm: zynq: Use st... |
459 |
*/ |
70504f311 clocksource/drive... |
460 |
static int __init ttc_timer_init(struct device_node *timer) |
e932900a3 arm: zynq: Use st... |
461 462 463 |
{ unsigned int irq; void __iomem *timer_baseaddr; |
30e1e2859 arm: zynq: Migrat... |
464 |
struct clk *clk_cs, *clk_ce; |
c5263bb8b arm: zynq: Move t... |
465 |
static int initialized; |
70504f311 clocksource/drive... |
466 |
int clksel, ret; |
4e2bec0c3 clocksource: cade... |
467 |
u32 timer_width = 16; |
c5263bb8b arm: zynq: Move t... |
468 469 |
if (initialized) |
70504f311 clocksource/drive... |
470 |
return 0; |
c5263bb8b arm: zynq: Move t... |
471 472 |
initialized = 1; |
e932900a3 arm: zynq: Use st... |
473 474 475 476 477 478 479 480 481 482 |
/* * Get the 1st Triple Timer Counter (TTC) block from the device tree * and use it. Note that the event timer uses the interrupt and it's the * 2nd TTC hence the irq_of_parse_and_map(,1) */ timer_baseaddr = of_iomap(timer, 0); if (!timer_baseaddr) { pr_err("ERROR: invalid timer base address "); |
70504f311 clocksource/drive... |
483 |
return -ENXIO; |
e932900a3 arm: zynq: Use st... |
484 485 486 487 488 489 |
} irq = irq_of_parse_and_map(timer, 1); if (irq <= 0) { pr_err("ERROR: invalid interrupt number "); |
70504f311 clocksource/drive... |
490 |
return -EINVAL; |
e932900a3 arm: zynq: Use st... |
491 |
} |
4e2bec0c3 clocksource: cade... |
492 |
of_property_read_u32(timer, "timer-width", &timer_width); |
87ab4361b clocksource: cade... |
493 |
clksel = readl_relaxed(timer_baseaddr + TTC_CLK_CNTRL_OFFSET); |
30e1e2859 arm: zynq: Migrat... |
494 495 496 497 498 |
clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK); clk_cs = of_clk_get(timer, clksel); if (IS_ERR(clk_cs)) { pr_err("ERROR: timer input clock not found "); |
70504f311 clocksource/drive... |
499 |
return PTR_ERR(clk_cs); |
30e1e2859 arm: zynq: Migrat... |
500 |
} |
87ab4361b clocksource: cade... |
501 |
clksel = readl_relaxed(timer_baseaddr + 4 + TTC_CLK_CNTRL_OFFSET); |
30e1e2859 arm: zynq: Migrat... |
502 503 504 |
clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK); clk_ce = of_clk_get(timer, clksel); if (IS_ERR(clk_ce)) { |
e932900a3 arm: zynq: Use st... |
505 506 |
pr_err("ERROR: timer input clock not found "); |
34c720a91 clocksource/drive... |
507 |
return PTR_ERR(clk_ce); |
e932900a3 arm: zynq: Use st... |
508 |
} |
70504f311 clocksource/drive... |
509 510 511 512 513 514 515 |
ret = ttc_setup_clocksource(clk_cs, timer_baseaddr, timer_width); if (ret) return ret; ret = ttc_setup_clockevent(clk_ce, timer_baseaddr + 4, irq); if (ret) return ret; |
e932900a3 arm: zynq: Use st... |
516 517 518 |
pr_info("%s #0 at %p, irq=%d ", timer->name, timer_baseaddr, irq); |
70504f311 clocksource/drive... |
519 520 |
return 0; |
e932900a3 arm: zynq: Use st... |
521 |
} |
177cf6e52 clocksources: Swi... |
522 |
CLOCKSOURCE_OF_DECLARE(ttc, "cdns,ttc", ttc_timer_init); |