Blame view
drivers/edac/i7300_edac.c
35.3 KB
fcaf780b2 i7300_edac: start... |
1 2 3 4 5 6 7 |
/* * Intel 7300 class Memory Controllers kernel module (Clarksboro) * * This file may be distributed under the terms of the * GNU General Public License version 2 only. * * Copyright (c) 2010 by: |
37e59f876 [media, edac] Cha... |
8 |
* Mauro Carvalho Chehab |
fcaf780b2 i7300_edac: start... |
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 |
* * Red Hat Inc. http://www.redhat.com * * Intel 7300 Chipset Memory Controller Hub (MCH) - Datasheet * http://www.intel.com/Assets/PDF/datasheet/318082.pdf * * TODO: The chipset allow checking for PCI Express errors also. Currently, * the driver covers only memory error errors * * This driver uses "csrows" EDAC attribute to represent DIMM slot# */ #include <linux/module.h> #include <linux/init.h> #include <linux/pci.h> #include <linux/pci_ids.h> #include <linux/slab.h> #include <linux/edac.h> #include <linux/mmzone.h> #include "edac_core.h" /* * Alter this version for the I7300 module when modifications are made */ |
152ba3942 edac: Drop __DATE... |
34 |
#define I7300_REVISION " Ver: 1.0.0" |
fcaf780b2 i7300_edac: start... |
35 36 37 38 39 40 41 42 |
#define EDAC_MOD_STR "i7300_edac" #define i7300_printk(level, fmt, arg...) \ edac_printk(level, "i7300", fmt, ##arg) #define i7300_mc_printk(mci, level, fmt, arg...) \ edac_mc_chipset_printk(mci, level, "i7300", fmt, ##arg) |
b4552aceb i7300_edac: Clean... |
43 44 45 |
/*********************************************** * i7300 Limit constants Structs and static vars ***********************************************/ |
fcaf780b2 i7300_edac: start... |
46 47 48 49 50 51 52 53 54 |
/* * Memory topology is organized as: * Branch 0 - 2 channels: channels 0 and 1 (FDB0 PCI dev 21.0) * Branch 1 - 2 channels: channels 2 and 3 (FDB1 PCI dev 22.0) * Each channel can have to 8 DIMM sets (called as SLOTS) * Slots should generally be filled in pairs * Except on Single Channel mode of operation * just slot 0/channel0 filled on this mode * On normal operation mode, the two channels on a branch should be |
c3af2eaf7 i7300_edac: add g... |
55 |
* filled together for the same SLOT# |
fcaf780b2 i7300_edac: start... |
56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 |
* When in mirrored mode, Branch 1 replicate memory at Branch 0, so, the four * channels on both branches should be filled */ /* Limits for i7300 */ #define MAX_SLOTS 8 #define MAX_BRANCHES 2 #define MAX_CH_PER_BRANCH 2 #define MAX_CHANNELS (MAX_CH_PER_BRANCH * MAX_BRANCHES) #define MAX_MIR 3 #define to_channel(ch, branch) ((((branch)) << 1) | (ch)) #define to_csrow(slot, ch, branch) \ (to_channel(ch, branch) | ((slot) << 2)) |
b4552aceb i7300_edac: Clean... |
71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 |
/* Device name and register DID (Device ID) */ struct i7300_dev_info { const char *ctl_name; /* name for this device */ u16 fsb_mapping_errors; /* DID for the branchmap,control */ }; /* Table of devices attributes supported by this driver */ static const struct i7300_dev_info i7300_devs[] = { { .ctl_name = "I7300", .fsb_mapping_errors = PCI_DEVICE_ID_INTEL_I7300_MCH_ERR, }, }; struct i7300_dimm_info { int megabytes; /* size, 0 means not present */ }; /* driver private data structure */ struct i7300_pvt { struct pci_dev *pci_dev_16_0_fsb_ctlr; /* 16.0 */ struct pci_dev *pci_dev_16_1_fsb_addr_map; /* 16.1 */ struct pci_dev *pci_dev_16_2_fsb_err_regs; /* 16.2 */ struct pci_dev *pci_dev_2x_0_fbd_branch[MAX_BRANCHES]; /* 21.0 and 22.0 */ u16 tolm; /* top of low memory */ u64 ambase; /* AMB BAR */ u32 mc_settings; /* Report several settings */ u32 mc_settings_a; u16 mir[MAX_MIR]; /* Memory Interleave Reg*/ |
9c6f6b65d i7300-edac: Codin... |
103 |
u16 mtr[MAX_SLOTS][MAX_BRANCHES]; /* Memory Technlogy Reg */ |
b4552aceb i7300_edac: Clean... |
104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 |
u16 ambpresent[MAX_CHANNELS]; /* AMB present regs */ /* DIMM information matrix, allocating architecture maximums */ struct i7300_dimm_info dimm_info[MAX_SLOTS][MAX_CHANNELS]; /* Temporary buffer for use when preparing error messages */ char *tmp_prt_buffer; }; /* FIXME: Why do we need to have this static? */ static struct edac_pci_ctl_info *i7300_pci; /*************************************************** * i7300 Register definitions for memory enumeration ***************************************************/ |
c3af2eaf7 i7300_edac: add g... |
119 |
/* |
c3af2eaf7 i7300_edac: add g... |
120 121 122 123 |
* Device 16, * Function 0: System Address (not documented) * Function 1: Memory Branch Map, Control, Errors Register */ |
fcaf780b2 i7300_edac: start... |
124 |
/* OFFSETS for Function 0 */ |
af3d8831e i7300_edac: displ... |
125 126 127 |
#define AMBASE 0x48 /* AMB Mem Mapped Reg Region Base */ #define MAXCH 0x56 /* Max Channel Number */ #define MAXDIMMPERCH 0x57 /* Max DIMM PER Channel Number */ |
fcaf780b2 i7300_edac: start... |
128 129 |
/* OFFSETS for Function 1 */ |
af3d8831e i7300_edac: displ... |
130 |
#define MC_SETTINGS 0x40 |
bb81a2163 i7300_edac: Detec... |
131 132 133 134 |
#define IS_MIRRORED(mc) ((mc) & (1 << 16)) #define IS_ECC_ENABLED(mc) ((mc) & (1 << 5)) #define IS_RETRY_ENABLED(mc) ((mc) & (1 << 31)) #define IS_SCRBALGO_ENHANCED(mc) ((mc) & (1 << 8)) |
fcaf780b2 i7300_edac: start... |
135 |
|
bb81a2163 i7300_edac: Detec... |
136 137 |
#define MC_SETTINGS_A 0x58 #define IS_SINGLE_MODE(mca) ((mca) & (1 << 14)) |
d7de2bdb0 i7300_edac: Adds ... |
138 |
|
af3d8831e i7300_edac: displ... |
139 |
#define TOLM 0x6C |
af3d8831e i7300_edac: displ... |
140 141 142 143 |
#define MIR0 0x80 #define MIR1 0x84 #define MIR2 0x88 |
fcaf780b2 i7300_edac: start... |
144 |
|
fcaf780b2 i7300_edac: start... |
145 146 147 148 149 150 151 152 153 154 155 156 157 |
/* * Note: Other Intel EDAC drivers use AMBPRESENT to identify if the available * memory. From datasheet item 7.3.1 (FB-DIMM technology & organization), it * seems that we cannot use this information directly for the same usage. * Each memory slot may have up to 2 AMB interfaces, one for income and another * for outcome interface to the next slot. * For now, the driver just stores the AMB present registers, but rely only at * the MTR info to detect memory. * Datasheet is also not clear about how to map each AMBPRESENT registers to * one of the 4 available channels. */ #define AMBPRESENT_0 0x64 #define AMBPRESENT_1 0x66 |
42b16b3fb Kill off warning:... |
158 |
static const u16 mtr_regs[MAX_SLOTS] = { |
fcaf780b2 i7300_edac: start... |
159 160 161 |
0x80, 0x84, 0x88, 0x8c, 0x82, 0x86, 0x8a, 0x8e }; |
b4552aceb i7300_edac: Clean... |
162 163 |
/* * Defines to extract the vaious fields from the |
fcaf780b2 i7300_edac: start... |
164 165 166 167 168 169 170 171 172 173 174 175 |
* MTRx - Memory Technology Registers */ #define MTR_DIMMS_PRESENT(mtr) ((mtr) & (1 << 8)) #define MTR_DIMMS_ETHROTTLE(mtr) ((mtr) & (1 << 7)) #define MTR_DRAM_WIDTH(mtr) (((mtr) & (1 << 6)) ? 8 : 4) #define MTR_DRAM_BANKS(mtr) (((mtr) & (1 << 5)) ? 8 : 4) #define MTR_DIMM_RANKS(mtr) (((mtr) & (1 << 4)) ? 1 : 0) #define MTR_DIMM_ROWS(mtr) (((mtr) >> 2) & 0x3) #define MTR_DRAM_BANKS_ADDR_BITS 2 #define MTR_DIMM_ROWS_ADDR_BITS(mtr) (MTR_DIMM_ROWS(mtr) + 13) #define MTR_DIMM_COLS(mtr) ((mtr) & 0x3) #define MTR_DIMM_COLS_ADDR_BITS(mtr) (MTR_DIMM_COLS(mtr) + 10) |
c3af2eaf7 i7300_edac: add g... |
176 177 178 |
/************************************************ * i7300 Register definitions for error detection ************************************************/ |
57021918a i7300_edac: Add s... |
179 180 181 182 183 184 185 186 187 188 189 190 |
/* * Device 16.1: FBD Error Registers */ #define FERR_FAT_FBD 0x98 static const char *ferr_fat_fbd_name[] = { [22] = "Non-Redundant Fast Reset Timeout", [2] = ">Tmid Thermal event with intelligent throttling disabled", [1] = "Memory or FBD configuration CRC read error", [0] = "Memory Write error on non-redundant retry or " "FBD configuration Write error on retry", }; |
7e06b7a33 i7300_edac: Fix e... |
191 192 |
#define GET_FBD_FAT_IDX(fbderr) (((fbderr) >> 28) & 3) #define FERR_FAT_FBD_ERR_MASK ((1 << 0) | (1 << 1) | (1 << 2) | (1 << 22)) |
57021918a i7300_edac: Add s... |
193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 |
#define FERR_NF_FBD 0xa0 static const char *ferr_nf_fbd_name[] = { [24] = "DIMM-Spare Copy Completed", [23] = "DIMM-Spare Copy Initiated", [22] = "Redundant Fast Reset Timeout", [21] = "Memory Write error on redundant retry", [18] = "SPD protocol Error", [17] = "FBD Northbound parity error on FBD Sync Status", [16] = "Correctable Patrol Data ECC", [15] = "Correctable Resilver- or Spare-Copy Data ECC", [14] = "Correctable Mirrored Demand Data ECC", [13] = "Correctable Non-Mirrored Demand Data ECC", [11] = "Memory or FBD configuration CRC read error", [10] = "FBD Configuration Write error on first attempt", [9] = "Memory Write error on first attempt", [8] = "Non-Aliased Uncorrectable Patrol Data ECC", [7] = "Non-Aliased Uncorrectable Resilver- or Spare-Copy Data ECC", [6] = "Non-Aliased Uncorrectable Mirrored Demand Data ECC", [5] = "Non-Aliased Uncorrectable Non-Mirrored Demand Data ECC", [4] = "Aliased Uncorrectable Patrol Data ECC", [3] = "Aliased Uncorrectable Resilver- or Spare-Copy Data ECC", [2] = "Aliased Uncorrectable Mirrored Demand Data ECC", [1] = "Aliased Uncorrectable Non-Mirrored Demand Data ECC", [0] = "Uncorrectable Data ECC on Replay", }; |
7e06b7a33 i7300_edac: Fix e... |
219 |
#define GET_FBD_NF_IDX(fbderr) (((fbderr) >> 28) & 3) |
57021918a i7300_edac: Add s... |
220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 |
#define FERR_NF_FBD_ERR_MASK ((1 << 24) | (1 << 23) | (1 << 22) | (1 << 21) |\ (1 << 18) | (1 << 17) | (1 << 16) | (1 << 15) |\ (1 << 14) | (1 << 13) | (1 << 11) | (1 << 10) |\ (1 << 9) | (1 << 8) | (1 << 7) | (1 << 6) |\ (1 << 5) | (1 << 4) | (1 << 3) | (1 << 2) |\ (1 << 1) | (1 << 0)) #define EMASK_FBD 0xa8 #define EMASK_FBD_ERR_MASK ((1 << 27) | (1 << 26) | (1 << 25) | (1 << 24) |\ (1 << 22) | (1 << 21) | (1 << 20) | (1 << 19) |\ (1 << 18) | (1 << 17) | (1 << 16) | (1 << 14) |\ (1 << 13) | (1 << 12) | (1 << 11) | (1 << 10) |\ (1 << 9) | (1 << 8) | (1 << 7) | (1 << 6) |\ (1 << 5) | (1 << 4) | (1 << 3) | (1 << 2) |\ (1 << 1) | (1 << 0)) |
c3af2eaf7 i7300_edac: add g... |
235 236 237 |
/* * Device 16.2: Global Error Registers */ |
5de6e07ed i7300_edac: Add e... |
238 239 240 241 242 243 244 245 |
#define FERR_GLOBAL_HI 0x48 static const char *ferr_global_hi_name[] = { [3] = "FSB 3 Fatal Error", [2] = "FSB 2 Fatal Error", [1] = "FSB 1 Fatal Error", [0] = "FSB 0 Fatal Error", }; #define ferr_global_hi_is_fatal(errno) 1 |
c3af2eaf7 i7300_edac: add g... |
246 |
#define FERR_GLOBAL_LO 0x40 |
5de6e07ed i7300_edac: Add e... |
247 |
static const char *ferr_global_lo_name[] = { |
c3af2eaf7 i7300_edac: add g... |
248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 |
[31] = "Internal MCH Fatal Error", [30] = "Intel QuickData Technology Device Fatal Error", [29] = "FSB1 Fatal Error", [28] = "FSB0 Fatal Error", [27] = "FBD Channel 3 Fatal Error", [26] = "FBD Channel 2 Fatal Error", [25] = "FBD Channel 1 Fatal Error", [24] = "FBD Channel 0 Fatal Error", [23] = "PCI Express Device 7Fatal Error", [22] = "PCI Express Device 6 Fatal Error", [21] = "PCI Express Device 5 Fatal Error", [20] = "PCI Express Device 4 Fatal Error", [19] = "PCI Express Device 3 Fatal Error", [18] = "PCI Express Device 2 Fatal Error", [17] = "PCI Express Device 1 Fatal Error", [16] = "ESI Fatal Error", [15] = "Internal MCH Non-Fatal Error", [14] = "Intel QuickData Technology Device Non Fatal Error", [13] = "FSB1 Non-Fatal Error", [12] = "FSB 0 Non-Fatal Error", [11] = "FBD Channel 3 Non-Fatal Error", [10] = "FBD Channel 2 Non-Fatal Error", [9] = "FBD Channel 1 Non-Fatal Error", [8] = "FBD Channel 0 Non-Fatal Error", [7] = "PCI Express Device 7 Non-Fatal Error", [6] = "PCI Express Device 6 Non-Fatal Error", [5] = "PCI Express Device 5 Non-Fatal Error", [4] = "PCI Express Device 4 Non-Fatal Error", [3] = "PCI Express Device 3 Non-Fatal Error", [2] = "PCI Express Device 2 Non-Fatal Error", [1] = "PCI Express Device 1 Non-Fatal Error", [0] = "ESI Non-Fatal Error", }; |
5de6e07ed i7300_edac: Add e... |
281 |
#define ferr_global_lo_is_fatal(errno) ((errno < 16) ? 0 : 1) |
fcaf780b2 i7300_edac: start... |
282 |
|
8199d8cc6 i7300_edac: enric... |
283 284 285 286 287 288 289 290 |
#define NRECMEMA 0xbe #define NRECMEMA_BANK(v) (((v) >> 12) & 7) #define NRECMEMA_RANK(v) (((v) >> 8) & 15) #define NRECMEMB 0xc0 #define NRECMEMB_IS_WR(v) ((v) & (1 << 31)) #define NRECMEMB_CAS(v) (((v) >> 16) & 0x1fff) #define NRECMEMB_RAS(v) ((v) & 0xffff) |
32f947261 i7300_edac: enric... |
291 |
#define REDMEMA 0xdc |
37b69cf91 i7300_edac: Prope... |
292 293 |
#define REDMEMB 0x7c #define IS_SECOND_CH(v) ((v) * (1 << 17)) |
32f947261 i7300_edac: enric... |
294 295 296 297 298 299 300 301 |
#define RECMEMA 0xe0 #define RECMEMA_BANK(v) (((v) >> 12) & 7) #define RECMEMA_RANK(v) (((v) >> 8) & 15) #define RECMEMB 0xe4 #define RECMEMB_IS_WR(v) ((v) & (1 << 31)) #define RECMEMB_CAS(v) (((v) >> 16) & 0x1fff) #define RECMEMB_RAS(v) ((v) & 0xffff) |
5de6e07ed i7300_edac: Add e... |
302 303 304 |
/******************************************** * i7300 Functions related to error detection ********************************************/ |
fcaf780b2 i7300_edac: start... |
305 |
|
d091a6eb1 i7300_edac: Impro... |
306 307 308 309 310 311 312 313 314 315 316 317 318 |
/** * get_err_from_table() - Gets the error message from a table * @table: table name (array of char *) * @size: number of elements at the table * @pos: position of the element to be returned * * This is a small routine that gets the pos-th element of a table. If the * element doesn't exist (or it is empty), it returns "reserved". * Instead of calling it directly, the better is to call via the macro * GET_ERR_FROM_TABLE(), that automatically checks the table size via * ARRAY_SIZE() macro */ static const char *get_err_from_table(const char *table[], int size, int pos) |
fcaf780b2 i7300_edac: start... |
319 |
{ |
d091a6eb1 i7300_edac: Impro... |
320 321 322 323 |
if (unlikely(pos >= size)) return "Reserved"; if (unlikely(!table[pos])) |
5de6e07ed i7300_edac: Add e... |
324 325 326 |
return "Reserved"; return table[pos]; |
fcaf780b2 i7300_edac: start... |
327 |
} |
5de6e07ed i7300_edac: Add e... |
328 329 |
#define GET_ERR_FROM_TABLE(table, pos) \ get_err_from_table(table, ARRAY_SIZE(table), pos) |
d091a6eb1 i7300_edac: Impro... |
330 331 332 333 334 |
/** * i7300_process_error_global() - Retrieve the hardware error information from * the hardware global error registers and * sends it to dmesg * @mci: struct mem_ctl_info pointer |
fcaf780b2 i7300_edac: start... |
335 |
*/ |
f42774224 i7300_edac: Clean... |
336 |
static void i7300_process_error_global(struct mem_ctl_info *mci) |
fcaf780b2 i7300_edac: start... |
337 |
{ |
5de6e07ed i7300_edac: Add e... |
338 |
struct i7300_pvt *pvt; |
5f032119d i7300_edac: Fix e... |
339 |
u32 errnum, error_reg; |
5de6e07ed i7300_edac: Add e... |
340 341 342 |
unsigned long errors; const char *specific; bool is_fatal; |
fcaf780b2 i7300_edac: start... |
343 |
|
5de6e07ed i7300_edac: Add e... |
344 |
pvt = mci->pvt_info; |
fcaf780b2 i7300_edac: start... |
345 |
|
5de6e07ed i7300_edac: Add e... |
346 347 |
/* read in the 1st FATAL error register */ pci_read_config_dword(pvt->pci_dev_16_2_fsb_err_regs, |
5f032119d i7300_edac: Fix e... |
348 349 350 |
FERR_GLOBAL_HI, &error_reg); if (unlikely(error_reg)) { errors = error_reg; |
5de6e07ed i7300_edac: Add e... |
351 352 353 354 |
errnum = find_first_bit(&errors, ARRAY_SIZE(ferr_global_hi_name)); specific = GET_ERR_FROM_TABLE(ferr_global_hi_name, errnum); is_fatal = ferr_global_hi_is_fatal(errnum); |
86002324c i7300_edac: Clear... |
355 356 357 |
/* Clear the error bit */ pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs, |
5f032119d i7300_edac: Fix e... |
358 |
FERR_GLOBAL_HI, error_reg); |
86002324c i7300_edac: Clear... |
359 |
|
5de6e07ed i7300_edac: Add e... |
360 |
goto error_global; |
fcaf780b2 i7300_edac: start... |
361 |
} |
5de6e07ed i7300_edac: Add e... |
362 |
pci_read_config_dword(pvt->pci_dev_16_2_fsb_err_regs, |
5f032119d i7300_edac: Fix e... |
363 364 365 |
FERR_GLOBAL_LO, &error_reg); if (unlikely(error_reg)) { errors = error_reg; |
5de6e07ed i7300_edac: Add e... |
366 367 368 369 |
errnum = find_first_bit(&errors, ARRAY_SIZE(ferr_global_lo_name)); specific = GET_ERR_FROM_TABLE(ferr_global_lo_name, errnum); is_fatal = ferr_global_lo_is_fatal(errnum); |
86002324c i7300_edac: Clear... |
370 371 372 |
/* Clear the error bit */ pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs, |
5f032119d i7300_edac: Fix e... |
373 |
FERR_GLOBAL_LO, error_reg); |
86002324c i7300_edac: Clear... |
374 |
|
5de6e07ed i7300_edac: Add e... |
375 376 377 |
goto error_global; } return; |
fcaf780b2 i7300_edac: start... |
378 |
|
5de6e07ed i7300_edac: Add e... |
379 380 381 382 |
error_global: i7300_mc_printk(mci, KERN_EMERG, "%s misc error: %s ", is_fatal ? "Fatal" : "NOT fatal", specific); |
fcaf780b2 i7300_edac: start... |
383 |
} |
d091a6eb1 i7300_edac: Impro... |
384 385 386 387 388 |
/** * i7300_process_fbd_error() - Retrieve the hardware error information from * the FBD error registers and sends it via * EDAC error API calls * @mci: struct mem_ctl_info pointer |
57021918a i7300_edac: Add s... |
389 |
*/ |
f42774224 i7300_edac: Clean... |
390 |
static void i7300_process_fbd_error(struct mem_ctl_info *mci) |
57021918a i7300_edac: Add s... |
391 392 |
{ struct i7300_pvt *pvt; |
5f032119d i7300_edac: Fix e... |
393 |
u32 errnum, value, error_reg; |
8199d8cc6 i7300_edac: enric... |
394 |
u16 val16; |
37b69cf91 i7300_edac: Prope... |
395 |
unsigned branch, channel, bank, rank, cas, ras; |
32f947261 i7300_edac: enric... |
396 |
u32 syndrome; |
57021918a i7300_edac: Add s... |
397 398 |
unsigned long errors; const char *specific; |
32f947261 i7300_edac: enric... |
399 |
bool is_wr; |
57021918a i7300_edac: Add s... |
400 401 402 403 404 |
pvt = mci->pvt_info; /* read in the 1st FATAL error register */ pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, |
5f032119d i7300_edac: Fix e... |
405 406 407 |
FERR_FAT_FBD, &error_reg); if (unlikely(error_reg & FERR_FAT_FBD_ERR_MASK)) { errors = error_reg & FERR_FAT_FBD_ERR_MASK ; |
57021918a i7300_edac: Add s... |
408 409 410 |
errnum = find_first_bit(&errors, ARRAY_SIZE(ferr_fat_fbd_name)); specific = GET_ERR_FROM_TABLE(ferr_fat_fbd_name, errnum); |
5f032119d i7300_edac: Fix e... |
411 |
branch = (GET_FBD_FAT_IDX(error_reg) == 2) ? 1 : 0; |
57021918a i7300_edac: Add s... |
412 |
|
8199d8cc6 i7300_edac: enric... |
413 414 415 416 417 418 419 |
pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, NRECMEMA, &val16); bank = NRECMEMA_BANK(val16); rank = NRECMEMA_RANK(val16); pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, NRECMEMB, &value); |
8199d8cc6 i7300_edac: enric... |
420 421 422 |
is_wr = NRECMEMB_IS_WR(value); cas = NRECMEMB_CAS(value); ras = NRECMEMB_RAS(value); |
5f032119d i7300_edac: Fix e... |
423 424 425 |
/* Clean the error register */ pci_write_config_dword(pvt->pci_dev_16_1_fsb_addr_map, FERR_FAT_FBD, error_reg); |
8199d8cc6 i7300_edac: enric... |
426 |
snprintf(pvt->tmp_prt_buffer, PAGE_SIZE, |
70e2a8379 i7300_edac: conve... |
427 428 |
"Bank=%d RAS=%d CAS=%d Err=0x%lx (%s))", bank, ras, cas, errors, specific); |
9eb07a7fb edac: edac_mc_han... |
429 |
edac_mc_handle_error(HW_EVENT_ERR_FATAL, mci, 1, 0, 0, 0, |
70e2a8379 i7300_edac: conve... |
430 431 |
branch, -1, rank, is_wr ? "Write error" : "Read error", |
03f7eae80 edac: remove arch... |
432 |
pvt->tmp_prt_buffer); |
70e2a8379 i7300_edac: conve... |
433 |
|
57021918a i7300_edac: Add s... |
434 435 436 437 |
} /* read in the 1st NON-FATAL error register */ pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, |
5f032119d i7300_edac: Fix e... |
438 439 440 |
FERR_NF_FBD, &error_reg); if (unlikely(error_reg & FERR_NF_FBD_ERR_MASK)) { errors = error_reg & FERR_NF_FBD_ERR_MASK; |
57021918a i7300_edac: Add s... |
441 442 443 |
errnum = find_first_bit(&errors, ARRAY_SIZE(ferr_nf_fbd_name)); specific = GET_ERR_FROM_TABLE(ferr_nf_fbd_name, errnum); |
7e06b7a33 i7300_edac: Fix e... |
444 |
branch = (GET_FBD_NF_IDX(error_reg) == 2) ? 1 : 0; |
57021918a i7300_edac: Add s... |
445 |
|
32f947261 i7300_edac: enric... |
446 447 |
pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, REDMEMA, &syndrome); |
32f947261 i7300_edac: enric... |
448 449 450 451 452 453 454 |
pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, RECMEMA, &val16); bank = RECMEMA_BANK(val16); rank = RECMEMA_RANK(val16); pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, RECMEMB, &value); |
32f947261 i7300_edac: enric... |
455 456 457 |
is_wr = RECMEMB_IS_WR(value); cas = RECMEMB_CAS(value); ras = RECMEMB_RAS(value); |
8199d8cc6 i7300_edac: enric... |
458 |
|
37b69cf91 i7300_edac: Prope... |
459 460 |
pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, REDMEMB, &value); |
37b69cf91 i7300_edac: Prope... |
461 462 463 |
channel = (branch << 1); if (IS_SECOND_CH(value)) channel++; |
5f032119d i7300_edac: Fix e... |
464 465 466 |
/* Clear the error bit */ pci_write_config_dword(pvt->pci_dev_16_1_fsb_addr_map, FERR_NF_FBD, error_reg); |
32f947261 i7300_edac: enric... |
467 468 |
/* Form out message */ snprintf(pvt->tmp_prt_buffer, PAGE_SIZE, |
70e2a8379 i7300_edac: conve... |
469 470 |
"DRAM-Bank=%d RAS=%d CAS=%d, Err=0x%lx (%s))", bank, ras, cas, errors, specific); |
9eb07a7fb edac: edac_mc_han... |
471 |
edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, 0, 0, |
70e2a8379 i7300_edac: conve... |
472 473 474 |
syndrome, branch >> 1, channel % 2, rank, is_wr ? "Write error" : "Read error", |
03f7eae80 edac: remove arch... |
475 |
pvt->tmp_prt_buffer); |
32f947261 i7300_edac: enric... |
476 477 |
} return; |
57021918a i7300_edac: Add s... |
478 |
} |
d091a6eb1 i7300_edac: Impro... |
479 480 481 |
/** * i7300_check_error() - Calls the error checking subroutines * @mci: struct mem_ctl_info pointer |
fcaf780b2 i7300_edac: start... |
482 |
*/ |
f42774224 i7300_edac: Clean... |
483 |
static void i7300_check_error(struct mem_ctl_info *mci) |
5de6e07ed i7300_edac: Add e... |
484 |
{ |
f42774224 i7300_edac: Clean... |
485 486 |
i7300_process_error_global(mci); i7300_process_fbd_error(mci); |
5de6e07ed i7300_edac: Add e... |
487 |
}; |
fcaf780b2 i7300_edac: start... |
488 |
|
d091a6eb1 i7300_edac: Impro... |
489 490 491 |
/** * i7300_clear_error() - Clears the error registers * @mci: struct mem_ctl_info pointer |
fcaf780b2 i7300_edac: start... |
492 493 494 |
*/ static void i7300_clear_error(struct mem_ctl_info *mci) { |
e43276050 i7300_edac: Add a... |
495 496 497 498 499 500 |
struct i7300_pvt *pvt = mci->pvt_info; u32 value; /* * All error values are RWC - we need to read and write 1 to the * bit that we want to cleanup */ |
fcaf780b2 i7300_edac: start... |
501 |
|
e43276050 i7300_edac: Add a... |
502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 |
/* Clear global error registers */ pci_read_config_dword(pvt->pci_dev_16_2_fsb_err_regs, FERR_GLOBAL_HI, &value); pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs, FERR_GLOBAL_HI, value); pci_read_config_dword(pvt->pci_dev_16_2_fsb_err_regs, FERR_GLOBAL_LO, &value); pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs, FERR_GLOBAL_LO, value); /* Clear FBD error registers */ pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, FERR_FAT_FBD, &value); pci_write_config_dword(pvt->pci_dev_16_1_fsb_addr_map, FERR_FAT_FBD, value); pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, FERR_NF_FBD, &value); pci_write_config_dword(pvt->pci_dev_16_1_fsb_addr_map, FERR_NF_FBD, value); |
fcaf780b2 i7300_edac: start... |
523 |
} |
d091a6eb1 i7300_edac: Impro... |
524 525 526 527 |
/** * i7300_enable_error_reporting() - Enable the memory reporting logic at the * hardware * @mci: struct mem_ctl_info pointer |
fcaf780b2 i7300_edac: start... |
528 529 530 |
*/ static void i7300_enable_error_reporting(struct mem_ctl_info *mci) { |
57021918a i7300_edac: Add s... |
531 532 533 534 535 536 537 538 539 540 541 542 |
struct i7300_pvt *pvt = mci->pvt_info; u32 fbd_error_mask; /* Read the FBD Error Mask Register */ pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, EMASK_FBD, &fbd_error_mask); /* Enable with a '0' */ fbd_error_mask &= ~(EMASK_FBD_ERR_MASK); pci_write_config_dword(pvt->pci_dev_16_1_fsb_addr_map, EMASK_FBD, fbd_error_mask); |
fcaf780b2 i7300_edac: start... |
543 |
} |
5de6e07ed i7300_edac: Add e... |
544 545 546 547 |
/************************************************ * i7300 Functions related to memory enumberation ************************************************/ |
fcaf780b2 i7300_edac: start... |
548 |
|
d091a6eb1 i7300_edac: Impro... |
549 550 551 552 553 554 555 556 |
/** * decode_mtr() - Decodes the MTR descriptor, filling the edac structs * @pvt: pointer to the private data struct used by i7300 driver * @slot: DIMM slot (0 to 7) * @ch: Channel number within the branch (0 or 1) * @branch: Branch number (0 or 1) * @dinfo: Pointer to DIMM info where dimm size is stored * @p_csrow: Pointer to the struct csrow_info that corresponds to that element |
fcaf780b2 i7300_edac: start... |
557 558 559 560 |
*/ static int decode_mtr(struct i7300_pvt *pvt, int slot, int ch, int branch, struct i7300_dimm_info *dinfo, |
a895bf8b1 edac: move nr_pag... |
561 |
struct dimm_info *dimm) |
fcaf780b2 i7300_edac: start... |
562 563 564 565 566 567 568 |
{ int mtr, ans, addrBits, channel; channel = to_channel(ch, branch); mtr = pvt->mtr[slot][branch]; ans = MTR_DIMMS_PRESENT(mtr) ? 1 : 0; |
956b9ba15 edac: Convert deb... |
569 570 571 |
edac_dbg(2, "\tMTR%d CH%d: DIMMs are %sPresent (mtr) ", slot, channel, ans ? "" : "NOT "); |
fcaf780b2 i7300_edac: start... |
572 573 |
/* Determine if there is a DIMM present in this DIMM slot */ |
fcaf780b2 i7300_edac: start... |
574 575 |
if (!ans) return 0; |
fcaf780b2 i7300_edac: start... |
576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 |
/* Start with the number of bits for a Bank * on the DRAM */ addrBits = MTR_DRAM_BANKS_ADDR_BITS; /* Add thenumber of ROW bits */ addrBits += MTR_DIMM_ROWS_ADDR_BITS(mtr); /* add the number of COLUMN bits */ addrBits += MTR_DIMM_COLS_ADDR_BITS(mtr); /* add the number of RANK bits */ addrBits += MTR_DIMM_RANKS(mtr); addrBits += 6; /* add 64 bits per DIMM */ addrBits -= 20; /* divide by 2^^20 */ addrBits -= 3; /* 8 bits per bytes */ dinfo->megabytes = 1 << addrBits; |
956b9ba15 edac: Convert deb... |
592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 |
edac_dbg(2, "\t\tWIDTH: x%d ", MTR_DRAM_WIDTH(mtr)); edac_dbg(2, "\t\tELECTRICAL THROTTLING is %s ", MTR_DIMMS_ETHROTTLE(mtr) ? "enabled" : "disabled"); edac_dbg(2, "\t\tNUMBANK: %d bank(s) ", MTR_DRAM_BANKS(mtr)); edac_dbg(2, "\t\tNUMRANK: %s ", MTR_DIMM_RANKS(mtr) ? "double" : "single"); edac_dbg(2, "\t\tNUMROW: %s ", MTR_DIMM_ROWS(mtr) == 0 ? "8,192 - 13 rows" : MTR_DIMM_ROWS(mtr) == 1 ? "16,384 - 14 rows" : MTR_DIMM_ROWS(mtr) == 2 ? "32,768 - 15 rows" : "65,536 - 16 rows"); edac_dbg(2, "\t\tNUMCOL: %s ", MTR_DIMM_COLS(mtr) == 0 ? "1,024 - 10 columns" : MTR_DIMM_COLS(mtr) == 1 ? "2,048 - 11 columns" : MTR_DIMM_COLS(mtr) == 2 ? "4,096 - 12 columns" : "reserved"); edac_dbg(2, "\t\tSIZE: %d MB ", dinfo->megabytes); |
fcaf780b2 i7300_edac: start... |
618 |
|
116389ed2 i7300_edac: Add a... |
619 |
/* |
15154c57c i7300_edac: Prope... |
620 |
* The type of error detection actually depends of the |
116389ed2 i7300_edac: Add a... |
621 |
* mode of operation. When it is just one single memory chip, at |
15154c57c i7300_edac: Prope... |
622 623 |
* socket 0, channel 0, it uses 8-byte-over-32-byte SECDED+ code. * In normal or mirrored mode, it uses Lockstep mode, |
116389ed2 i7300_edac: Add a... |
624 625 626 |
* with the possibility of using an extended algorithm for x8 memories * See datasheet Sections 7.3.6 to 7.3.8 */ |
15154c57c i7300_edac: Prope... |
627 |
|
a895bf8b1 edac: move nr_pag... |
628 |
dimm->nr_pages = MiB_TO_PAGES(dinfo->megabytes); |
084a4fcce edac: move dimm p... |
629 630 |
dimm->grain = 8; dimm->mtype = MEM_FB_DDR2; |
15154c57c i7300_edac: Prope... |
631 |
if (IS_SINGLE_MODE(pvt->mc_settings_a)) { |
084a4fcce edac: move dimm p... |
632 |
dimm->edac_mode = EDAC_SECDED; |
956b9ba15 edac: Convert deb... |
633 634 |
edac_dbg(2, "\t\tECC code is 8-byte-over-32-byte SECDED+ code "); |
15154c57c i7300_edac: Prope... |
635 |
} else { |
956b9ba15 edac: Convert deb... |
636 637 |
edac_dbg(2, "\t\tECC code is on Lockstep mode "); |
28c2ce7c8 i7300_edac: Fix M... |
638 |
if (MTR_DRAM_WIDTH(mtr) == 8) |
084a4fcce edac: move dimm p... |
639 |
dimm->edac_mode = EDAC_S8ECD8ED; |
15154c57c i7300_edac: Prope... |
640 |
else |
084a4fcce edac: move dimm p... |
641 |
dimm->edac_mode = EDAC_S4ECD4ED; |
15154c57c i7300_edac: Prope... |
642 |
} |
fcaf780b2 i7300_edac: start... |
643 644 |
/* ask what device type on this row */ |
28c2ce7c8 i7300_edac: Fix M... |
645 |
if (MTR_DRAM_WIDTH(mtr) == 8) { |
956b9ba15 edac: Convert deb... |
646 647 648 649 |
edac_dbg(2, "\t\tScrub algorithm for x8 is on %s mode ", IS_SCRBALGO_ENHANCED(pvt->mc_settings) ? "enhanced" : "normal"); |
d7de2bdb0 i7300_edac: Adds ... |
650 |
|
084a4fcce edac: move dimm p... |
651 |
dimm->dtype = DEV_X8; |
d7de2bdb0 i7300_edac: Adds ... |
652 |
} else |
084a4fcce edac: move dimm p... |
653 |
dimm->dtype = DEV_X4; |
fcaf780b2 i7300_edac: start... |
654 655 656 |
return mtr; } |
d091a6eb1 i7300_edac: Impro... |
657 658 659 |
/** * print_dimm_size() - Prints dump of the memory organization * @pvt: pointer to the private data struct used by i7300 driver |
fcaf780b2 i7300_edac: start... |
660 |
* |
d091a6eb1 i7300_edac: Impro... |
661 |
* Useful for debug. If debug is disabled, this routine do nothing |
fcaf780b2 i7300_edac: start... |
662 663 664 |
*/ static void print_dimm_size(struct i7300_pvt *pvt) { |
d091a6eb1 i7300_edac: Impro... |
665 |
#ifdef CONFIG_EDAC_DEBUG |
fcaf780b2 i7300_edac: start... |
666 |
struct i7300_dimm_info *dinfo; |
85580ea4f i7300_edac: pre-a... |
667 |
char *p; |
fcaf780b2 i7300_edac: start... |
668 669 670 671 |
int space, n; int channel, slot; space = PAGE_SIZE; |
85580ea4f i7300_edac: pre-a... |
672 |
p = pvt->tmp_prt_buffer; |
fcaf780b2 i7300_edac: start... |
673 674 675 676 677 678 679 680 681 |
n = snprintf(p, space, " "); p += n; space -= n; for (channel = 0; channel < MAX_CHANNELS; channel++) { n = snprintf(p, space, "channel %d | ", channel); p += n; space -= n; } |
956b9ba15 edac: Convert deb... |
682 683 |
edac_dbg(2, "%s ", pvt->tmp_prt_buffer); |
85580ea4f i7300_edac: pre-a... |
684 |
p = pvt->tmp_prt_buffer; |
fcaf780b2 i7300_edac: start... |
685 686 |
space = PAGE_SIZE; n = snprintf(p, space, "-------------------------------" |
9c6f6b65d i7300-edac: Codin... |
687 |
"------------------------------"); |
fcaf780b2 i7300_edac: start... |
688 689 |
p += n; space -= n; |
956b9ba15 edac: Convert deb... |
690 691 |
edac_dbg(2, "%s ", pvt->tmp_prt_buffer); |
85580ea4f i7300_edac: pre-a... |
692 |
p = pvt->tmp_prt_buffer; |
fcaf780b2 i7300_edac: start... |
693 694 695 696 697 698 699 700 701 702 703 704 705 |
space = PAGE_SIZE; for (slot = 0; slot < MAX_SLOTS; slot++) { n = snprintf(p, space, "csrow/SLOT %d ", slot); p += n; space -= n; for (channel = 0; channel < MAX_CHANNELS; channel++) { dinfo = &pvt->dimm_info[slot][channel]; n = snprintf(p, space, "%4d MB | ", dinfo->megabytes); p += n; space -= n; } |
956b9ba15 edac: Convert deb... |
706 707 |
edac_dbg(2, "%s ", pvt->tmp_prt_buffer); |
85580ea4f i7300_edac: pre-a... |
708 |
p = pvt->tmp_prt_buffer; |
fcaf780b2 i7300_edac: start... |
709 710 711 712 |
space = PAGE_SIZE; } n = snprintf(p, space, "-------------------------------" |
9c6f6b65d i7300-edac: Codin... |
713 |
"------------------------------"); |
fcaf780b2 i7300_edac: start... |
714 715 |
p += n; space -= n; |
956b9ba15 edac: Convert deb... |
716 717 |
edac_dbg(2, "%s ", pvt->tmp_prt_buffer); |
85580ea4f i7300_edac: pre-a... |
718 |
p = pvt->tmp_prt_buffer; |
fcaf780b2 i7300_edac: start... |
719 |
space = PAGE_SIZE; |
d091a6eb1 i7300_edac: Impro... |
720 |
#endif |
fcaf780b2 i7300_edac: start... |
721 |
} |
d091a6eb1 i7300_edac: Impro... |
722 723 724 725 726 |
/** * i7300_init_csrows() - Initialize the 'csrows' table within * the mci control structure with the * addressing of memory. * @mci: struct mem_ctl_info pointer |
fcaf780b2 i7300_edac: start... |
727 728 729 730 731 |
*/ static int i7300_init_csrows(struct mem_ctl_info *mci) { struct i7300_pvt *pvt; struct i7300_dimm_info *dinfo; |
d091a6eb1 i7300_edac: Impro... |
732 |
int rc = -ENODEV; |
fcaf780b2 i7300_edac: start... |
733 |
int mtr; |
33ad41263 i7300_edac: Fix m... |
734 |
int ch, branch, slot, channel, max_channel, max_branch; |
084a4fcce edac: move dimm p... |
735 |
struct dimm_info *dimm; |
fcaf780b2 i7300_edac: start... |
736 737 |
pvt = mci->pvt_info; |
956b9ba15 edac: Convert deb... |
738 739 |
edac_dbg(2, "Memory Technology Registers: "); |
fcaf780b2 i7300_edac: start... |
740 |
|
33ad41263 i7300_edac: Fix m... |
741 742 743 744 745 746 747 |
if (IS_SINGLE_MODE(pvt->mc_settings_a)) { max_branch = 1; max_channel = 1; } else { max_branch = MAX_BRANCHES; max_channel = MAX_CH_PER_BRANCH; } |
fcaf780b2 i7300_edac: start... |
748 |
/* Get the AMB present registers for the four channels */ |
33ad41263 i7300_edac: Fix m... |
749 |
for (branch = 0; branch < max_branch; branch++) { |
fcaf780b2 i7300_edac: start... |
750 751 |
/* Read and dump branch 0's MTRs */ channel = to_channel(0, branch); |
9c6f6b65d i7300-edac: Codin... |
752 753 |
pci_read_config_word(pvt->pci_dev_2x_0_fbd_branch[branch], AMBPRESENT_0, |
fcaf780b2 i7300_edac: start... |
754 |
&pvt->ambpresent[channel]); |
956b9ba15 edac: Convert deb... |
755 756 757 |
edac_dbg(2, "\t\tAMB-present CH%d = 0x%x: ", channel, pvt->ambpresent[channel]); |
fcaf780b2 i7300_edac: start... |
758 |
|
33ad41263 i7300_edac: Fix m... |
759 760 |
if (max_channel == 1) continue; |
fcaf780b2 i7300_edac: start... |
761 |
channel = to_channel(1, branch); |
9c6f6b65d i7300-edac: Codin... |
762 763 |
pci_read_config_word(pvt->pci_dev_2x_0_fbd_branch[branch], AMBPRESENT_1, |
fcaf780b2 i7300_edac: start... |
764 |
&pvt->ambpresent[channel]); |
956b9ba15 edac: Convert deb... |
765 766 767 |
edac_dbg(2, "\t\tAMB-present CH%d = 0x%x: ", channel, pvt->ambpresent[channel]); |
fcaf780b2 i7300_edac: start... |
768 769 770 771 772 |
} /* Get the set of MTR[0-7] regs by each branch */ for (slot = 0; slot < MAX_SLOTS; slot++) { int where = mtr_regs[slot]; |
33ad41263 i7300_edac: Fix m... |
773 |
for (branch = 0; branch < max_branch; branch++) { |
3e57eef64 i7300_edac: Bette... |
774 |
pci_read_config_word(pvt->pci_dev_2x_0_fbd_branch[branch], |
fcaf780b2 i7300_edac: start... |
775 776 |
where, &pvt->mtr[slot][branch]); |
33ad41263 i7300_edac: Fix m... |
777 |
for (ch = 0; ch < max_channel; ch++) { |
fcaf780b2 i7300_edac: start... |
778 |
int channel = to_channel(ch, branch); |
70e2a8379 i7300_edac: conve... |
779 780 |
dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, branch, ch, slot); |
fcaf780b2 i7300_edac: start... |
781 |
|
70e2a8379 i7300_edac: conve... |
782 |
dinfo = &pvt->dimm_info[slot][channel]; |
084a4fcce edac: move dimm p... |
783 |
|
fcaf780b2 i7300_edac: start... |
784 |
mtr = decode_mtr(pvt, slot, ch, branch, |
a895bf8b1 edac: move nr_pag... |
785 |
dinfo, dimm); |
fcaf780b2 i7300_edac: start... |
786 787 788 |
/* if no DIMMS on this row, continue */ if (!MTR_DIMMS_PRESENT(mtr)) continue; |
d091a6eb1 i7300_edac: Impro... |
789 |
rc = 0; |
a895bf8b1 edac: move nr_pag... |
790 |
|
fcaf780b2 i7300_edac: start... |
791 792 793 |
} } } |
d091a6eb1 i7300_edac: Impro... |
794 |
return rc; |
fcaf780b2 i7300_edac: start... |
795 |
} |
d091a6eb1 i7300_edac: Impro... |
796 797 798 799 800 |
/** * decode_mir() - Decodes Memory Interleave Register (MIR) info * @int mir_no: number of the MIR register to decode * @mir: array with the MIR data cached on the driver */ |
fcaf780b2 i7300_edac: start... |
801 802 803 |
static void decode_mir(int mir_no, u16 mir[MAX_MIR]) { if (mir[mir_no] & 3) |
956b9ba15 edac: Convert deb... |
804 805 806 807 808 809 |
edac_dbg(2, "MIR%d: limit= 0x%x Branch(es) that participate: %s %s ", mir_no, (mir[mir_no] >> 4) & 0xfff, (mir[mir_no] & 1) ? "B0" : "", (mir[mir_no] & 2) ? "B1" : ""); |
fcaf780b2 i7300_edac: start... |
810 |
} |
d091a6eb1 i7300_edac: Impro... |
811 812 813 |
/** * i7300_get_mc_regs() - Get the contents of the MC enumeration registers * @mci: struct mem_ctl_info pointer |
fcaf780b2 i7300_edac: start... |
814 |
* |
d091a6eb1 i7300_edac: Impro... |
815 |
* Data read is cached internally for its usage when needed |
fcaf780b2 i7300_edac: start... |
816 817 818 819 820 821 822 823 |
*/ static int i7300_get_mc_regs(struct mem_ctl_info *mci) { struct i7300_pvt *pvt; u32 actual_tolm; int i, rc; pvt = mci->pvt_info; |
3e57eef64 i7300_edac: Bette... |
824 |
pci_read_config_dword(pvt->pci_dev_16_0_fsb_ctlr, AMBASE, |
fcaf780b2 i7300_edac: start... |
825 |
(u32 *) &pvt->ambase); |
956b9ba15 edac: Convert deb... |
826 827 |
edac_dbg(2, "AMBASE= 0x%lx ", (long unsigned int)pvt->ambase); |
fcaf780b2 i7300_edac: start... |
828 829 |
/* Get the Branch Map regs */ |
3e57eef64 i7300_edac: Bette... |
830 |
pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, TOLM, &pvt->tolm); |
fcaf780b2 i7300_edac: start... |
831 |
pvt->tolm >>= 12; |
956b9ba15 edac: Convert deb... |
832 833 834 |
edac_dbg(2, "TOLM (number of 256M regions) =%u (0x%x) ", pvt->tolm, pvt->tolm); |
fcaf780b2 i7300_edac: start... |
835 836 |
actual_tolm = (u32) ((1000l * pvt->tolm) >> (30 - 28)); |
956b9ba15 edac: Convert deb... |
837 838 839 |
edac_dbg(2, "Actual TOLM byte addr=%u.%03u GB (0x%x) ", actual_tolm/1000, actual_tolm % 1000, pvt->tolm << 28); |
fcaf780b2 i7300_edac: start... |
840 |
|
af3d8831e i7300_edac: displ... |
841 |
/* Get memory controller settings */ |
3e57eef64 i7300_edac: Bette... |
842 |
pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, MC_SETTINGS, |
af3d8831e i7300_edac: displ... |
843 |
&pvt->mc_settings); |
bb81a2163 i7300_edac: Detec... |
844 845 |
pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, MC_SETTINGS_A, &pvt->mc_settings_a); |
d7de2bdb0 i7300_edac: Adds ... |
846 |
|
bb81a2163 i7300_edac: Detec... |
847 |
if (IS_SINGLE_MODE(pvt->mc_settings_a)) |
956b9ba15 edac: Convert deb... |
848 849 |
edac_dbg(0, "Memory controller operating on single mode "); |
bb81a2163 i7300_edac: Detec... |
850 |
else |
956b9ba15 edac: Convert deb... |
851 852 853 |
edac_dbg(0, "Memory controller operating on %smirrored mode ", IS_MIRRORED(pvt->mc_settings) ? "" : "non-"); |
bb81a2163 i7300_edac: Detec... |
854 |
|
956b9ba15 edac: Convert deb... |
855 856 857 858 859 860 |
edac_dbg(0, "Error detection is %s ", IS_ECC_ENABLED(pvt->mc_settings) ? "enabled" : "disabled"); edac_dbg(0, "Retry is %s ", IS_RETRY_ENABLED(pvt->mc_settings) ? "enabled" : "disabled"); |
af3d8831e i7300_edac: displ... |
861 862 |
/* Get Memory Interleave Range registers */ |
9c6f6b65d i7300-edac: Codin... |
863 864 865 866 867 868 |
pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, MIR0, &pvt->mir[0]); pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, MIR1, &pvt->mir[1]); pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, MIR2, &pvt->mir[2]); |
fcaf780b2 i7300_edac: start... |
869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 |
/* Decode the MIR regs */ for (i = 0; i < MAX_MIR; i++) decode_mir(i, pvt->mir); rc = i7300_init_csrows(mci); if (rc < 0) return rc; /* Go and determine the size of each DIMM and place in an * orderly matrix */ print_dimm_size(pvt); return 0; } |
5de6e07ed i7300_edac: Add e... |
884 885 886 |
/************************************************* * i7300 Functions related to device probe/release *************************************************/ |
d091a6eb1 i7300_edac: Impro... |
887 888 889 |
/** * i7300_put_devices() - Release the PCI devices * @mci: struct mem_ctl_info pointer |
fcaf780b2 i7300_edac: start... |
890 891 892 893 894 895 896 897 898 899 |
*/ static void i7300_put_devices(struct mem_ctl_info *mci) { struct i7300_pvt *pvt; int branch; pvt = mci->pvt_info; /* Decrement usage count for devices */ for (branch = 0; branch < MAX_CH_PER_BRANCH; branch++) |
3e57eef64 i7300_edac: Bette... |
900 901 902 |
pci_dev_put(pvt->pci_dev_2x_0_fbd_branch[branch]); pci_dev_put(pvt->pci_dev_16_2_fsb_err_regs); pci_dev_put(pvt->pci_dev_16_1_fsb_addr_map); |
fcaf780b2 i7300_edac: start... |
903 |
} |
d091a6eb1 i7300_edac: Impro... |
904 905 906 907 |
/** * i7300_get_devices() - Find and perform 'get' operation on the MCH's * device/functions we want to reference for this driver * @mci: struct mem_ctl_info pointer |
fcaf780b2 i7300_edac: start... |
908 |
* |
d091a6eb1 i7300_edac: Impro... |
909 910 911 912 913 |
* Access and prepare the several devices for usage: * I7300 devices used by this driver: * Device 16, functions 0,1 and 2: PCI_DEVICE_ID_INTEL_I7300_MCH_ERR * Device 21 function 0: PCI_DEVICE_ID_INTEL_I7300_MCH_FB0 * Device 22 function 0: PCI_DEVICE_ID_INTEL_I7300_MCH_FB1 |
fcaf780b2 i7300_edac: start... |
914 |
*/ |
9b3c6e85c Drivers: edac: re... |
915 |
static int i7300_get_devices(struct mem_ctl_info *mci) |
fcaf780b2 i7300_edac: start... |
916 917 918 919 920 921 922 923 |
{ struct i7300_pvt *pvt; struct pci_dev *pdev; pvt = mci->pvt_info; /* Attempt to 'get' the MCH register we want */ pdev = NULL; |
75135da0d i7300_edac: Fix d... |
924 925 926 |
while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I7300_MCH_ERR, pdev))) { |
fcaf780b2 i7300_edac: start... |
927 928 929 |
/* Store device 16 funcs 1 and 2 */ switch (PCI_FUNC(pdev->devfn)) { case 1: |
75135da0d i7300_edac: Fix d... |
930 931 932 |
if (!pvt->pci_dev_16_1_fsb_addr_map) pvt->pci_dev_16_1_fsb_addr_map = pci_dev_get(pdev); |
fcaf780b2 i7300_edac: start... |
933 934 |
break; case 2: |
75135da0d i7300_edac: Fix d... |
935 936 937 |
if (!pvt->pci_dev_16_2_fsb_err_regs) pvt->pci_dev_16_2_fsb_err_regs = pci_dev_get(pdev); |
fcaf780b2 i7300_edac: start... |
938 939 940 |
break; } } |
75135da0d i7300_edac: Fix d... |
941 942 943 944 945 946 947 948 949 950 951 |
if (!pvt->pci_dev_16_1_fsb_addr_map || !pvt->pci_dev_16_2_fsb_err_regs) { /* At least one device was not found */ i7300_printk(KERN_ERR, "'system address,Process Bus' device not found:" "vendor 0x%x device 0x%x ERR funcs (broken BIOS?) ", PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I7300_MCH_ERR); goto error; } |
956b9ba15 edac: Convert deb... |
952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 |
edac_dbg(1, "System Address, processor bus- PCI Bus ID: %s %x:%x ", pci_name(pvt->pci_dev_16_0_fsb_ctlr), pvt->pci_dev_16_0_fsb_ctlr->vendor, pvt->pci_dev_16_0_fsb_ctlr->device); edac_dbg(1, "Branchmap, control and errors - PCI Bus ID: %s %x:%x ", pci_name(pvt->pci_dev_16_1_fsb_addr_map), pvt->pci_dev_16_1_fsb_addr_map->vendor, pvt->pci_dev_16_1_fsb_addr_map->device); edac_dbg(1, "FSB Error Regs - PCI Bus ID: %s %x:%x ", pci_name(pvt->pci_dev_16_2_fsb_err_regs), pvt->pci_dev_16_2_fsb_err_regs->vendor, pvt->pci_dev_16_2_fsb_err_regs->device); |
fcaf780b2 i7300_edac: start... |
967 |
|
3e57eef64 i7300_edac: Bette... |
968 |
pvt->pci_dev_2x_0_fbd_branch[0] = pci_get_device(PCI_VENDOR_ID_INTEL, |
9c6f6b65d i7300-edac: Codin... |
969 |
PCI_DEVICE_ID_INTEL_I7300_MCH_FB0, |
fcaf780b2 i7300_edac: start... |
970 |
NULL); |
3e57eef64 i7300_edac: Bette... |
971 |
if (!pvt->pci_dev_2x_0_fbd_branch[0]) { |
fcaf780b2 i7300_edac: start... |
972 973 974 975 976 977 978 |
i7300_printk(KERN_ERR, "MC: 'BRANCH 0' device not found:" "vendor 0x%x device 0x%x Func 0 (broken BIOS?) ", PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I7300_MCH_FB0); goto error; } |
3e57eef64 i7300_edac: Bette... |
979 |
pvt->pci_dev_2x_0_fbd_branch[1] = pci_get_device(PCI_VENDOR_ID_INTEL, |
fcaf780b2 i7300_edac: start... |
980 981 |
PCI_DEVICE_ID_INTEL_I7300_MCH_FB1, NULL); |
3e57eef64 i7300_edac: Bette... |
982 |
if (!pvt->pci_dev_2x_0_fbd_branch[1]) { |
fcaf780b2 i7300_edac: start... |
983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 |
i7300_printk(KERN_ERR, "MC: 'BRANCH 1' device not found:" "vendor 0x%x device 0x%x Func 0 " "(broken BIOS?) ", PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I7300_MCH_FB1); goto error; } return 0; error: i7300_put_devices(mci); return -ENODEV; } |
d091a6eb1 i7300_edac: Impro... |
999 1000 1001 1002 |
/** * i7300_init_one() - Probe for one instance of the device * @pdev: struct pci_dev pointer * @id: struct pci_device_id pointer - currently unused |
fcaf780b2 i7300_edac: start... |
1003 |
*/ |
9b3c6e85c Drivers: edac: re... |
1004 |
static int i7300_init_one(struct pci_dev *pdev, const struct pci_device_id *id) |
fcaf780b2 i7300_edac: start... |
1005 1006 |
{ struct mem_ctl_info *mci; |
70e2a8379 i7300_edac: conve... |
1007 |
struct edac_mc_layer layers[3]; |
fcaf780b2 i7300_edac: start... |
1008 |
struct i7300_pvt *pvt; |
d091a6eb1 i7300_edac: Impro... |
1009 |
int rc; |
fcaf780b2 i7300_edac: start... |
1010 |
|
d091a6eb1 i7300_edac: Impro... |
1011 1012 1013 1014 |
/* wake up device */ rc = pci_enable_device(pdev); if (rc == -EIO) return rc; |
fcaf780b2 i7300_edac: start... |
1015 |
|
956b9ba15 edac: Convert deb... |
1016 1017 1018 1019 |
edac_dbg(0, "MC: pdev bus %u dev=0x%x fn=0x%x ", pdev->bus->number, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); |
fcaf780b2 i7300_edac: start... |
1020 1021 1022 1023 |
/* We only are looking for func 0 of the set */ if (PCI_FUNC(pdev->devfn) != 0) return -ENODEV; |
fcaf780b2 i7300_edac: start... |
1024 |
/* allocate a new MC control structure */ |
70e2a8379 i7300_edac: conve... |
1025 1026 1027 1028 1029 1030 1031 1032 1033 |
layers[0].type = EDAC_MC_LAYER_BRANCH; layers[0].size = MAX_BRANCHES; layers[0].is_virt_csrow = false; layers[1].type = EDAC_MC_LAYER_CHANNEL; layers[1].size = MAX_CH_PER_BRANCH; layers[1].is_virt_csrow = true; layers[2].type = EDAC_MC_LAYER_SLOT; layers[2].size = MAX_SLOTS; layers[2].is_virt_csrow = true; |
ca0907b9e edac: Remove the ... |
1034 |
mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt)); |
fcaf780b2 i7300_edac: start... |
1035 1036 |
if (mci == NULL) return -ENOMEM; |
956b9ba15 edac: Convert deb... |
1037 1038 |
edac_dbg(0, "MC: mci = %p ", mci); |
fcaf780b2 i7300_edac: start... |
1039 |
|
fd687502d edac: Rename the ... |
1040 |
mci->pdev = &pdev->dev; /* record ptr to the generic device */ |
fcaf780b2 i7300_edac: start... |
1041 1042 |
pvt = mci->pvt_info; |
3e57eef64 i7300_edac: Bette... |
1043 |
pvt->pci_dev_16_0_fsb_ctlr = pdev; /* Record this device in our private */ |
fcaf780b2 i7300_edac: start... |
1044 |
|
85580ea4f i7300_edac: pre-a... |
1045 1046 1047 1048 1049 |
pvt->tmp_prt_buffer = kmalloc(PAGE_SIZE, GFP_KERNEL); if (!pvt->tmp_prt_buffer) { edac_mc_free(mci); return -ENOMEM; } |
fcaf780b2 i7300_edac: start... |
1050 |
/* 'get' the pci devices we want to reserve for our use */ |
d091a6eb1 i7300_edac: Impro... |
1051 |
if (i7300_get_devices(mci)) |
fcaf780b2 i7300_edac: start... |
1052 1053 1054 1055 1056 1057 1058 1059 |
goto fail0; mci->mc_idx = 0; mci->mtype_cap = MEM_FLAG_FB_DDR2; mci->edac_ctl_cap = EDAC_FLAG_NONE; mci->edac_cap = EDAC_FLAG_NONE; mci->mod_name = "i7300_edac.c"; mci->mod_ver = I7300_REVISION; |
d091a6eb1 i7300_edac: Impro... |
1060 |
mci->ctl_name = i7300_devs[0].ctl_name; |
fcaf780b2 i7300_edac: start... |
1061 1062 |
mci->dev_name = pci_name(pdev); mci->ctl_page_to_phys = NULL; |
fcaf780b2 i7300_edac: start... |
1063 1064 |
/* Set the function pointer to an actual operation function */ mci->edac_check = i7300_check_error; |
fcaf780b2 i7300_edac: start... |
1065 1066 1067 1068 |
/* initialize the MC control structure 'csrows' table * with the mapping and control information */ if (i7300_get_mc_regs(mci)) { |
956b9ba15 edac: Convert deb... |
1069 1070 |
edac_dbg(0, "MC: Setting mci->edac_cap to EDAC_FLAG_NONE because i7300_init_csrows() returned nonzero value "); |
fcaf780b2 i7300_edac: start... |
1071 1072 |
mci->edac_cap = EDAC_FLAG_NONE; /* no csrows found */ } else { |
956b9ba15 edac: Convert deb... |
1073 1074 |
edac_dbg(1, "MC: Enable error reporting now "); |
fcaf780b2 i7300_edac: start... |
1075 |
i7300_enable_error_reporting(mci); |
fcaf780b2 i7300_edac: start... |
1076 1077 1078 1079 |
} /* add this new MC control structure to EDAC's list of MCs */ if (edac_mc_add_mc(mci)) { |
956b9ba15 edac: Convert deb... |
1080 1081 |
edac_dbg(0, "MC: failed edac_mc_add_mc() "); |
fcaf780b2 i7300_edac: start... |
1082 1083 1084 1085 1086 |
/* FIXME: perhaps some code should go here that disables error * reporting if we just enabled it */ goto fail1; } |
fcaf780b2 i7300_edac: start... |
1087 |
i7300_clear_error(mci); |
fcaf780b2 i7300_edac: start... |
1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 |
/* allocating generic PCI control info */ i7300_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR); if (!i7300_pci) { printk(KERN_WARNING "%s(): Unable to create PCI control ", __func__); printk(KERN_WARNING "%s(): PCI error report via EDAC not setup ", __func__); } return 0; /* Error exit unwinding stack */ fail1: i7300_put_devices(mci); fail0: |
85580ea4f i7300_edac: pre-a... |
1110 |
kfree(pvt->tmp_prt_buffer); |
fcaf780b2 i7300_edac: start... |
1111 1112 1113 |
edac_mc_free(mci); return -ENODEV; } |
d091a6eb1 i7300_edac: Impro... |
1114 1115 1116 |
/** * i7300_remove_one() - Remove the driver * @pdev: struct pci_dev pointer |
fcaf780b2 i7300_edac: start... |
1117 |
*/ |
9b3c6e85c Drivers: edac: re... |
1118 |
static void i7300_remove_one(struct pci_dev *pdev) |
fcaf780b2 i7300_edac: start... |
1119 1120 |
{ struct mem_ctl_info *mci; |
85580ea4f i7300_edac: pre-a... |
1121 |
char *tmp; |
fcaf780b2 i7300_edac: start... |
1122 |
|
956b9ba15 edac: Convert deb... |
1123 1124 |
edac_dbg(0, " "); |
fcaf780b2 i7300_edac: start... |
1125 1126 1127 1128 1129 1130 1131 |
if (i7300_pci) edac_pci_release_generic_ctl(i7300_pci); mci = edac_mc_del_mc(&pdev->dev); if (!mci) return; |
85580ea4f i7300_edac: pre-a... |
1132 |
tmp = ((struct i7300_pvt *)mci->pvt_info)->tmp_prt_buffer; |
fcaf780b2 i7300_edac: start... |
1133 1134 |
/* retrieve references to resources, and free those resources */ i7300_put_devices(mci); |
85580ea4f i7300_edac: pre-a... |
1135 |
kfree(tmp); |
fcaf780b2 i7300_edac: start... |
1136 1137 1138 1139 |
edac_mc_free(mci); } /* |
d091a6eb1 i7300_edac: Impro... |
1140 |
* pci_device_id: table for which devices we are looking for |
fcaf780b2 i7300_edac: start... |
1141 |
* |
d091a6eb1 i7300_edac: Impro... |
1142 |
* Has only 8086:360c PCI ID |
fcaf780b2 i7300_edac: start... |
1143 |
*/ |
ba935f409 EDAC: Remove DEFI... |
1144 |
static const struct pci_device_id i7300_pci_tbl[] = { |
fcaf780b2 i7300_edac: start... |
1145 1146 1147 1148 1149 1150 1151 |
{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I7300_MCH_ERR)}, {0,} /* 0 terminated list. */ }; MODULE_DEVICE_TABLE(pci, i7300_pci_tbl); /* |
d091a6eb1 i7300_edac: Impro... |
1152 |
* i7300_driver: pci_driver structure for this module |
fcaf780b2 i7300_edac: start... |
1153 1154 1155 1156 |
*/ static struct pci_driver i7300_driver = { .name = "i7300_edac", .probe = i7300_init_one, |
9b3c6e85c Drivers: edac: re... |
1157 |
.remove = i7300_remove_one, |
fcaf780b2 i7300_edac: start... |
1158 1159 |
.id_table = i7300_pci_tbl, }; |
d091a6eb1 i7300_edac: Impro... |
1160 1161 |
/** * i7300_init() - Registers the driver |
fcaf780b2 i7300_edac: start... |
1162 1163 1164 1165 |
*/ static int __init i7300_init(void) { int pci_rc; |
956b9ba15 edac: Convert deb... |
1166 1167 |
edac_dbg(2, " "); |
fcaf780b2 i7300_edac: start... |
1168 1169 1170 1171 1172 1173 1174 1175 |
/* Ensure that the OPSTATE is set correctly for POLL or NMI */ opstate_init(); pci_rc = pci_register_driver(&i7300_driver); return (pci_rc < 0) ? pci_rc : 0; } |
d091a6eb1 i7300_edac: Impro... |
1176 1177 |
/** * i7300_init() - Unregisters the driver |
fcaf780b2 i7300_edac: start... |
1178 1179 1180 |
*/ static void __exit i7300_exit(void) { |
956b9ba15 edac: Convert deb... |
1181 1182 |
edac_dbg(2, " "); |
fcaf780b2 i7300_edac: start... |
1183 1184 1185 1186 1187 1188 1189 |
pci_unregister_driver(&i7300_driver); } module_init(i7300_init); module_exit(i7300_exit); MODULE_LICENSE("GPL"); |
37e59f876 [media, edac] Cha... |
1190 |
MODULE_AUTHOR("Mauro Carvalho Chehab"); |
fcaf780b2 i7300_edac: start... |
1191 1192 1193 1194 1195 1196 |
MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)"); MODULE_DESCRIPTION("MC Driver for Intel I7300 memory controllers - " I7300_REVISION); module_param(edac_op_state, int, 0444); MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); |