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3110628d8 spi: sh-msiof: Configure MSIOF sync signal timing in device tree ... Browse Code »

The MSIOF controller has DTDL and SYNCDL in SITMDR1 register. So,
this patch adds new properties like the following commit:
d0fb47a5237d8b9576113568bacfd27892308b62
(spi: fsl-espi: Configure FSL eSPI CSBEF and CSAFT)

Signed-off-by: Yoshihiro Shimoda
Signed-off-by: Mark Brown

Yoshihiro Shimoda
2014-12-24 20:31:17 +0800

sh_msiof.h 259 Bytes

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#ifndef __SPI_SH_MSIOF_H__
#define __SPI_SH_MSIOF_H__

struct sh_msiof_spi_info {
	int tx_fifo_override;
	int rx_fifo_override;
	u16 num_chipselect;
	unsigned int dma_tx_id;
	unsigned int dma_rx_id;
	u32 dtdl;
	u32 syncdl;
};

#endif /* __SPI_SH_MSIOF_H__ */