fsl-smarcimx8mm.dts
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/*
* Copyright 2018 NXP
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/dts-v1/;
#include "../freescale/fsl-imx8mm.dtsi"
/ {
firmware {
android {
compatible = "android,firmware";
fstab {
compatible = "android,fstab";
vendor {
compatible = "android,vendor";
/* sd card node which used if androidboot.storage_type=sd */
dev_sd = "/dev/block/platform/30b50000.mmc/by-name/vendor";
/* emmc node which used if androidboot.storage_type=emmc */
dev_emmc = "/dev/block/platform/30b60000.mmc/by-name/vendor";
type = "ext4";
mnt_flags = "ro,barrier=1,inode_readahead_blks=8";
fsmgr_flags = "wait,slotselect,avb";
};
};
vbmeta {
/*we need use FirstStageMountVBootV2 if we enable avb*/
compatible = "android,vbmeta";
/*parts means the partition witch can be mount in first stage*/
parts = "vbmeta,boot,system,vendor";
};
};
};
};
/ {
model = "Embedian SMARC-iMX8MM CPU board";
compatible = "embedian,imx8mm-smarcimx8mm", "fsl,imx8mm";
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_usb_otg1_vbus: usbotg1_regulator {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "usb_otg1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio3 10 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usb_otg2_vbus: usbotg2_regulator {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "usb_otg2_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio3 11 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_sd1_vmmc: sd1_regulator {
compatible = "regulator-fixed";
regulator-name = "VEMMC_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpio = <&gpio2 10 GPIO_ACTIVE_HIGH>;
off-on-delay = <20000>;
startup-delay-us = <100>;
enable-active-high;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
off-on-delay = <20000>;
enable-active-high;
};
reg_audio: audio_vdd {
compatible = "regulator-fixed";
regulator-name = "sgtl5000_supply";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_3p3v: 3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_5p0v: 5p0v {
compatible = "regulator-fixed";
regulator-name = "5P0V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
reg_1p8v: 1p8v {
compatible = "regulator-fixed";
regulator-name = "1P8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
};
reserved-memory {
/* cma region is provided by kernel command line as cma=<size>M */
/delete-node/ linux,cma;
/delete-node/ rpmsg@0xb8000000;
rpmsg_reserved: rpmsg@0x40000000 {
no-map;
reg = <0 0x40000000 0 0x400000>;
};
};
sound-sgtl5000 {
compatible = "fsl,imx-audio-sgtl5000",
"smarc,imx8mq-audio-sgtl5000";
model = "imx8mq-audio-sgtl5000";
ssi-controller = <&sai2>;
audio-codec = <&codec>;
audio-routing =
"MIC_IN", "Mic Jack",
"Mic Jack", "Mic Bias",
"Headphone Jack", "HP_OUT";
fsl,no-audmux;
};
backlight: backlight {
compatible = "pwm-backlight";
enable-gpios = <&gpio4 0 0>; /* Backlight Enable */
pwms = <&pwm1 0 1000000 0>;
brightness-levels = < 0 1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19
20 21 22 23 24 25 26 27 28 29
30 31 32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47 48 49
50 51 52 53 54 55 56 57 58 59
60 61 62 63 64 65 66 67 68 69
70 71 72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87 88 89
90 91 92 93 94 95 96 97 98 99
100>;
default-brightness-level = <80>;
status = "okay";
};
/* external oscillator of mcp2515 on SPI1.2 and SPI1.3 */
can_osc: can_osc {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
};
&clk {
assigned-clocks = <&clk IMX8MM_AUDIO_PLL1>, <&clk IMX8MM_AUDIO_PLL2>;
assigned-clock-rates = <786432000>, <722534400>;
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
smarcimx8mm {
pinctrl_hog: hoggrp {
fsl,pins = <
MX8MM_IOMUXC_NAND_DATA06_GPIO3_IO12 0x19 /*RESET_OUT#*/
MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x41 /*FEC_IRQ#*/
MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x41 /*PCIE_WAKE#*/
MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x41 /*LID#*/
MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x41 /*SLEEP#*/
MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x41 /*CHARGING#*/
MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x41 /*CHARGER_PRSNT#*/
MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19 /*CARRIER_STBY#*/
MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x41 /*BATLOW#*/
MX8MM_IOMUXC_NAND_DATA04_GPIO3_IO10 0x41 /*USB0_EN_OC#*/
MX8MM_IOMUXC_NAND_DATA05_GPIO3_IO11 0x41 /*USB1_EN_OC#*/
>;
};
pinctrl_csi1: csi1grp {
fsl,pins = <
MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x19 /*GPIO1*/
MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19 /*GPIO3*/
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
>;
};
pinctrl_flexspi0: flexspi0grp {
fsl,pins = <
MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2
MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
>;
};
pinctrl_usbotg1: usbotg1 {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x41
>;
};
pinctrl_usbotg2: usbotg2 {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x41
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
>;
};
pinctrl_pcie0: pcie0grp {
fsl,pins = <
MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x41
>;
};
pinctrl_pmic: pmicirq {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
>;
};
pinctrl_typec1: typec1grp {
fsl,pins = <
MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159
>;
};
pinctrl_typec2: typec2grp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x159
>;
};
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x06
>;
};
pinctrl_sai1: sai1grp {
fsl,pins = <
MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6
MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6
MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0xd6
MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6
MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6
MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6
MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6
MX8MM_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6
MX8MM_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6
MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6
MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6
MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6
>;
};
pinctrl_sai1_dsd: sai1grp_dsd {
fsl,pins = <
MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6
MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6
MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0xd6
MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6
MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6
MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6
MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6
MX8MM_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6
MX8MM_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6
MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6
MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6
MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6
>;
};
pinctrl_sai2: sai2grp {
fsl,pins = <
MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6
MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6
>;
};
pinctrl_sai3: sai3grp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0xd6
>;
};
pinctrl_sai5: sai5grp {
fsl,pins = <
MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6
MX8MM_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0xd6
MX8MM_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6
MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6
MX8MM_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0xd6
MX8MM_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0xd6
MX8MM_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0xd6
>;
};
pinctrl_pdm: pdmgrp {
fsl,pins = <
MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6
MX8MM_IOMUXC_SAI5_RXC_PDM_CLK 0xd6
MX8MM_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6
MX8MM_IOMUXC_SAI5_RXD0_PDM_DATA0 0xd6
MX8MM_IOMUXC_SAI5_RXD1_PDM_DATA1 0xd6
MX8MM_IOMUXC_SAI5_RXD2_PDM_DATA2 0xd6
MX8MM_IOMUXC_SAI5_RXD3_PDM_DATA3 0xd6
>;
};
pinctrl_spdif1: spdif1grp {
fsl,pins = <
MX8MM_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6
MX8MM_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x140
MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x140
MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140
MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x140
MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x140
MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x140
MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x140
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140
MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0
MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0
MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0
MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190
MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41
>;
};
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
fsl,pins = <
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4
MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4
MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4
MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194
MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41
>;
};
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
fsl,pins = <
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6
MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6
MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6
MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196
MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41
>;
};
pinctrl_usdhc2_gpio: usdhc2grpgpio {
fsl,pins = <
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
>;
};
pinctrl_ecspi2: ecspi2grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x13
MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x13
MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x13
MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x13
MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x13
>;
};
pinctrl_ecspi3: ecspi3grp {
fsl,pins = <
MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x13
MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x13
MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x13
MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x13
MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x13
MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x13
MX8MM_IOMUXC_NAND_WE_B_GPIO3_IO17 0x13
>;
};
pinctrl_lvds: lvdsgrp {
fsl,pins = <
MX8MM_IOMUXC_NAND_DATA07_GPIO3_IO13 0x16
>;
};
};
};
&csi1_bridge {
fsl,mipi-mode;
status = "okay";
port {
csi1_ep: endpoint {
remote-endpoint = <&csi1_mipi_ep>;
};
};
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
pmic: bd71837@4b {
reg = <0x4b>;
compatible = "rohm,bd71840", "rohm,bd71837";
/* PMIC BD71837 PMIC_nINT GPIO1_IO3 */
pinctrl-0 = <&pinctrl_pmic>;
gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>;
gpo {
rohm,drv = <0x0C>; /* 0b0000_1100 all gpos with cmos output mode */
};
regulators {
#address-cells = <1>;
#size-cells = <0>;
bd71837,pmic-buck2-uses-i2c-dvs;
bd71837,pmic-buck2-dvs-voltage = <1000000>, <900000>, <0>; /* VDD_ARM: Run-Idle */
buck1_reg: regulator@0 {
reg = <0>;
regulator-compatible = "buck1";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <1250>;
};
buck2_reg: regulator@1 {
reg = <1>;
regulator-compatible = "buck2";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <1250>;
};
buck3_reg: regulator@2 {
reg = <2>;
regulator-compatible = "buck3";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
};
buck4_reg: regulator@3 {
reg = <3>;
regulator-compatible = "buck4";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
};
buck5_reg: regulator@4 {
reg = <4>;
regulator-compatible = "buck5";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1350000>;
regulator-boot-on;
regulator-always-on;
};
buck6_reg: regulator@5 {
reg = <5>;
regulator-compatible = "buck6";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
buck7_reg: regulator@6 {
reg = <6>;
regulator-compatible = "buck7";
regulator-min-microvolt = <1605000>;
regulator-max-microvolt = <1995000>;
regulator-boot-on;
regulator-always-on;
};
buck8_reg: regulator@7 {
reg = <7>;
regulator-compatible = "buck8";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1400000>;
regulator-boot-on;
regulator-always-on;
};
ldo1_reg: regulator@8 {
reg = <8>;
regulator-compatible = "ldo1";
regulator-min-microvolt = <1600000>;
regulator-max-microvolt = <1900000>;
regulator-boot-on;
regulator-always-on;
};
ldo2_reg: regulator@9 {
reg = <9>;
regulator-compatible = "ldo2";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <900000>;
regulator-boot-on;
regulator-always-on;
};
ldo3_reg: regulator@10 {
reg = <10>;
regulator-compatible = "ldo3";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo4_reg: regulator@11 {
reg = <11>;
regulator-compatible = "ldo4";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
ldo6_reg: regulator@13 {
reg = <13>;
regulator-compatible = "ldo6";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
};
};
s35390a: s35390a@30 {
compatible = "sii,s35390a";
reg = <0x30>;
};
cape_eeprom0: cape_eeprom@57 {
compatible = "at,24c256";
reg = <0x57>;
};
codec: sgtl5000@0a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
clocks = <&clk IMX8MM_CLK_SAI2_ROOT>;
clock-names = "mclk";
VDDA-supply = <®_audio>;
VDDIO-supply = <®_1p8v>;
status = "okay";
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
dsi_lvds_bridge: sn65dsi84@2c {
status = "okay";
reg = <0x2c>;
compatible = "ti,sn65dsi84";
enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
interrupt-parent = <&gpio4>;
interrupts = <29 IRQ_TYPE_EDGE_FALLING>;
/* AUO G070VW01 7-inch 800x480 LVDS Display */
sn65dsi84,addresses = < 0x09 0x0A 0x0B 0x0D 0x10 0x11 0x12 0x13
0x18 0x19 0x1A 0x1B 0x20 0x21 0x22 0x23
0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B
0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33
0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B
0x3C 0x3D 0x3E 0xE0 0x0D>;
sn65dsi84,values = < 0x00 0x01 0x10 0x00 0x26 0x00 0x13 0x00
0x78 0x00 0x03 0x00 0x20 0x03 0x00 0x00
0x00 0x00 0x00 0x00 0x21 0x00 0x00 0x00
0x80 0x00 0x00 0x00 0x0e 0x00 0x00 0x00
0x40 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x01 0x01>;
/* AUO G185XW01 18.5-inch 1366x768 LVDS Display */
/*sn65dsi84,addresses = < 0x09 0x0A 0x0B 0x0D 0x10 0x11 0x12 0x13
0x18 0x19 0x1A 0x1B 0x20 0x21 0x22 0x23
0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B
0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33
0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B
0x3C 0x3D 0x3E 0xE0 0x0D>;
sn65dsi84,values = < 0x00 0x05 0x10 0x00 0x26 0x00 0x2E 0x00
0x78 0x00 0x03 0x00 0x56 0x05 0x00 0x00
0x00 0x00 0x00 0x00 0x21 0x00 0x00 0x00
0x78 0x00 0x00 0x00 0x12 0x00 0x00 0x00
0x3C 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x01 0x01>;*/
/* AUO G240HW01 V0 24-inch 1920x1080 LVDS Display */
/*sn65dsi84,addresses = < 0x09 0x0A 0x0B 0x0D 0x10 0x11 0x12 0x13
0x18 0x19 0x1A 0x1B 0x20 0x21 0x22 0x23
0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B
0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33
0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B
0x3C 0x3D 0x3E 0xE0 0x0D>;
sn65dsi84,values = < 0x00 0x05 0x20 0x00 0x26 0x00 0x4E 0x00
0x6C 0x00 0x03 0x00 0x80 0x07 0x00 0x00
0x00 0x00 0x00 0x00 0xC3 0x00 0x00 0x00
0x32 0x00 0x00 0x00 0x14 0x00 0x00 0x00
0x19 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x01 0x01>;*/
};
ov5640_mipi: ov5640_mipi@3c {
compatible = "ovti,ov5640_mipi";
reg = <0x3c>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_csi1>;
clocks = <&clk IMX8MM_CLK_CLKO1_DIV>;
clock-names = "csi_mclk";
assigned-clocks = <&clk IMX8MM_CLK_CLKO1_SRC>,
<&clk IMX8MM_CLK_CLKO1_DIV>;
assigned-clock-parents = <&clk IMX8MM_CLK_24M>;
assigned-clock-rates = <0>, <24000000>;
csi_id = <0>;
pwn-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; /* GPIO1 */
rst-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; /* GPIO3 */
mclk = <24000000>;
mclk_source = <0>;
port {
ov5640_mipi1_ep: endpoint {
remote-endpoint = <&mipi1_sensor_ep>;
};
};
};
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
baseboard_eeprom: baseboard_eeprom@50 {
compatible = "at,24c256";
reg = <0x50>;
};
};
&i2c4 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
status = "okay";
};
&mipi_csi_1 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
port {
mipi1_sensor_ep: endpoint1 {
remote-endpoint = <&ov5640_mipi1_ep>;
data-lanes = <4>;
csis-hs-settle = <13>;
csis-clk-settle = <2>;
csis-wclk;
};
csi1_mipi_ep: endpoint2 {
remote-endpoint = <&csi1_ep>;
};
};
};
&lcdif {
status = "okay";
};
&mipi_dsi {
status = "okay";
panel@0 {
reg = <0>;
status = "okay";
/* AUO G070VW01 800x480 LVDS Display */
compatible = "auo,g070vw01";
/* AUO G185XW01 1366x768 LVDS Display */
/*compatible = "auo,g185xw01";*/
/* AUO G240HW01 1920x1080 LVDS Display */
/*compatible = "auo,g240hw01";*/
backlight = <&backlight>;
enable-gpios = <&gpio4 1 0>; /* Enable LCD_VDD_EN pin */
dsi-lanes = <4>;
/* AUO G070VW01 800x480 LVDS Display */
panel-width-mm = <152>;
panel-height-mm = <91>;
/* AUO G185XW01 1366x768 LVDS Display */
/*panel-width-mm = <410>;
panel-height-mm = <230>;*/
/* AUO G240HW01 1920x1080 LVDS Display */
/*panel-width-mm = <531>;
panel-height-mm = <299>;*/
delay,prepare = <120>;
port {
dsi_lvds_bridge_in: endpoint {
remote-endpoint = <&mipi_dsi_out>;
};
};
};
port@1 {
mipi_dsi_out: endpoint {
remote-endpoint = <&dsi_lvds_bridge_in>;
};
};
};
&pwm1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
};
&ecspi2 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
cs-gpios = <&gpio5 13 0>, <&gpio1 0 0>;
fsl,spi-num-chipselects = <2>;
status = "okay";
spidev@0 {
compatible = "rohm,dh2228fv";
reg = <0>;
spi-max-frequency = <24000000>;
};
spidev@1 {
compatible = "rohm,dh2228fv";
reg = <1>;
spi-max-frequency = <24000000>;
};
};
&ecspi3 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi3>;
cs-gpios = <&gpio5 25 0>, <&gpio3 2 0>, <&gpio3 15 0>, <&gpio3 17 0>;
fsl,spi-num-chipselects = <4>;
status = "okay";
spidev@0 {
compatible = "rohm,dh2228fv";
reg = <0>;
spi-max-frequency = <24000000>;
};
spidev@1 {
compatible = "rohm,dh2228fv";
reg = <1>;
spi-max-frequency = <24000000>;
};
can1: can@2 {
compatible = "microchip,mcp2515";
reg = <2>;
interrupt-parent = <&gpio3>;
interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
spi-max-frequency = <12000000>;
clocks = <&can_osc>;
vdd-supply = <®_3p3v>;
xceiver-supply = <®_5p0v>;
};
can2: can@3 {
compatible = "microchip,mcp2515";
reg = <3>;
interrupt-parent = <&gpio3>;
interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
spi-max-frequency = <12000000>;
clocks = <&can_osc>;
vdd-supply = <®_3p3v>;
xceiver-supply = <®_5p0v>;
};
};
&mu {
status = "okay";
};
&sai2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai2>;
assigned-clocks = <&clk IMX8MM_CLK_SAI2_DIV>;
assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
assigned-clock-rates = <24576000>;
status = "okay";
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-id";
phy-handle = <ðphy0>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <6>;
at803x,led-act-blind-workaround;
at803x,eee-okay;
at803x,vddio-1p8v;
};
};
};
&pcie0{
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0>;
reset-gpio = <&gpio3 3 GPIO_ACTIVE_LOW>;
ext_osc = <1>;
status = "okay";
};
/* SER0 */
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
assigned-clocks = <&clk IMX8MM_CLK_UART1_SRC>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
fsl,uart-has-rtscts;
status = "okay";
};
/* SER1 */
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
status = "okay";
};
/* SER2 */
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
assigned-clocks = <&clk IMX8MM_CLK_UART3_SRC>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
fsl,uart-has-rtscts;
status = "okay";
};
/* SER3 */
&uart2 { /* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&usbotg1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg1>;
vbus-supply = <®_usb_otg1_vbus>;
dr_mode = "otg";
picophy,pre-emp-curr-control = <3>;
picophy,dc-vol-level-adjust = <7>;
status = "okay";
};
&usbotg2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg2>;
vbus-supply = <®_usb_otg2_vbus>;
dr_mode = "host";
picophy,pre-emp-curr-control = <3>;
picophy,dc-vol-level-adjust = <7>;
status = "okay";
};
/* eMMC */
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
bus-width = <8>;
vmmc-supply = <®_sd1_vmmc>;
non-removable;
status = "okay";
};
&usdhc2 {
/*pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;*/
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
bus-width = <4>;
vmmc-supply = <®_usdhc2_vmmc>;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&A53_0 {
arm-supply = <&buck2_reg>;
};
&gpu {
status = "okay";
};
&vpu_g1 {
status = "okay";
};
&vpu_g2 {
status = "okay";
};
&vpu_h1 {
status = "okay";
};
&snvs_rtc {
status = "okay";
};
&crypto {
status = "disabled";
};